14c14
< (==) Log file: "/var/log/Xorg.0.log", Time: Wed Feb 28 12:28:46 2007
---
> (==) Log file: "/var/log/Xorg.0.log", Time: Wed Feb 28 17:28:09 2007
391,393c391,393
< (II) intel(0):    VCLK_DIVISOR_VGA0: 0x00021207
< (II) intel(0):    VCLK_DIVISOR_VGA1: 0x00031406
< (II) intel(0):        VCLK_POST_DIV: 0x0000888b
---
> (II) intel(0):    VCLK_DIVISOR_VGA0: 0x00021207 (n = 2, m1 = 18, m2 = 7)
> (II) intel(0):    VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6)
> (II) intel(0):        VCLK_POST_DIV: 0x0000888b (vga0 p1 = 13, p2 = 4, vga1 p1 = 10, p2 = 4)
431c431
< (II) intel(0):               DPLL_A: 0x808b0000 (enabled, non-dvo, VGA, unknown mode, default clock, p1 = 1, p2 = 0)
---
> (II) intel(0):               DPLL_A: 0x808b0000 (enabled, non-dvo, VGA, default clock, DAC/serial mode, p1 = 13, p2 = 4)
452c452
< (II) intel(0):               DPLL_B: 0x90016000 (enabled, non-dvo, unknown mode, unknown clock, p1 = 1, p2 = 0)
---
> (II) intel(0):               DPLL_B: 0x90016000 (enabled, non-dvo, unknown clock, LVDS mode, p1 = 1, p2 = 2)
543c543
< (II) intel(0):                 CR22: 0x01
---
> (II) intel(0):                 CR22: 0x00
566c566
< (WW) intel(0): Unknown DPLL mode 00000000 in programmed mode
---
> probed: dotclock 327000 vco 654000 ((m 109, m1 18, m2 7), n 6, (p 2, p1 -1, p2 0))
592c592
< (II) intel(0): Modeline "1024x768"x0.0    0.00  1024 1048 1184 1344  768 771 777 806 (0.0 kHz)
---
> (II) intel(0): Modeline "1024x768"x0.0  327.00  1024 1048 1184 1344  768 771 777 806 (243.3 kHz)
711c711
< (II) intel(0): Modeline "1024x768"x0.0    0.00  1024 1048 1184 1344  768 771 777 806 (0.0 kHz)
---
> (II) intel(0): Modeline "1024x768"x301.9  327.00  1024 1048 1184 1344  768 771 777 806 (243.3 kHz)
755,757d754
< (WW) intel(0): Register 0x61200 (PP_STATUS) changed from 0xc0000008 to 0xd0000009
< (WW) intel(0): PP_STATUS before: on, ready, sequencing idle
< (WW) intel(0): PP_STATUS after: on, ready, sequencing on