Running Steam on arch 32-bit STEAM_RUNTIME is enabled automatically Installing breakpad exception handler for appid(steam)/version(1383158641_client) [2013-11-23 15:29:01] Startup - updater built Oct 7 2013 12:10:55 FRAG 0: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) ret void } declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32) attributes #0 = { "ShaderType"="0" } # Machine code for function main: Post SSA, not tracking liveness BB#0: derived from LLVM BB %main_body %VGPR0 = V_MOV_B32_e32 0, %EXEC EXP 0, 0, 0, 1, 1, %VGPR0, %VGPR0, %VGPR0, %VGPR0, %EXEC S_ENDPGM # End machine code for function main. Shader Disassembly: V_MOV_B32_e32 v0, 0 ; 7E000280 EXP 0, 0, 0, 1, 1, v0, v0, v0, v0 ; F8001800 00000000 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %21 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %4) %22 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %4) %23 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %4) %24 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %4) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %21, float %22, float %23, float %24) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } # Machine code for function main: Post SSA, not tracking liveness Function Live Ins: %SGPR7 in %vreg4 BB#0: derived from LLVM BB %main_body Live Ins: %SGPR7 %EXEC = S_WQM_B64 %EXEC %M0 = S_MOV_B32 %SGPR7 %VGPR0 = V_INTERP_MOV_F32 2, 3, 0, %M0, %EXEC %VGPR1 = V_INTERP_MOV_F32 2, 2, 0, %M0, %EXEC %VGPR2 = V_INTERP_MOV_F32 2, 1, 0, %M0, %EXEC %VGPR3 = V_INTERP_MOV_F32 2, 0, 0, %M0, %EXEC EXP 15, 0, 0, 1, 1, %VGPR3, %VGPR2, %VGPR1, %VGPR0, %EXEC S_ENDPGM # End machine code for function main. Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s7 ; BEFC0307 V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302 V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202 V_INTERP_MOV_F32 v2, P0, 1, 0, [m0] ; C80A0102 V_INTERP_MOV_F32 v3, P0, 0, 0, [m0] ; C80E0002 EXP 15, 0, 0, 1, 1, v3, v2, v1, v0 ; F800180F 00010203 S_ENDPGM ; BF810000 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %21 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %4) %22 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %4) %23 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %4) %24 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %4) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %21, float %22, float %23, float %24) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } # Machine code for function main: Post SSA, not tracking liveness Function Live Ins: %SGPR7 in %vreg4 BB#0: derived from LLVM BB %main_body Live Ins: %SGPR7 %EXEC = S_WQM_B64 %EXEC %M0 = S_MOV_B32 %SGPR7 %VGPR0 = V_INTERP_MOV_F32 2, 3, 0, %M0, %EXEC %VGPR1 = V_INTERP_MOV_F32 2, 2, 0, %M0, %EXEC %VGPR2 = V_INTERP_MOV_F32 2, 1, 0, %M0, %EXEC %VGPR3 = V_INTERP_MOV_F32 2, 0, 0, %M0, %EXEC EXP 15, 0, 0, 1, 1, %VGPR3, %VGPR2, %VGPR1, %VGPR0, %EXEC S_ENDPGM # End machine code for function main. Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s7 ; BEFC0307 V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302 V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202 V_INTERP_MOV_F32 v2, P0, 1, 0, [m0] ; C80A0102 V_INTERP_MOV_F32 v3, P0, 0, 0, [m0] ; C80E0002 EXP 15, 0, 0, 1, 1, v3, v2, v1, v0 ; F800180F 00010203 S_ENDPGM ; BF810000 VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] 0: MOV OUT[0], IN[0] 1: MOV OUT[1], IN[1] 2: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0 %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0 %12 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %11, i32 0, i32 %6) %13 = extractelement <4 x float> %12, i32 0 %14 = extractelement <4 x float> %12, i32 1 %15 = extractelement <4 x float> %12, i32 2 %16 = extractelement <4 x float> %12, i32 3 %17 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 1 %18 = load <16 x i8> addrspace(2)* %17, !tbaa !0 %19 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %18, i32 0, i32 %6) %20 = extractelement <4 x float> %19, i32 0 %21 = extractelement <4 x float> %19, i32 1 %22 = extractelement <4 x float> %19, i32 2 %23 = extractelement <4 x float> %19, i32 3 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %20, float %21, float %22, float %23) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %13, float %14, float %15, float %16) ret void } ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} # Machine code for function main: Post SSA, not tracking liveness Function Live Ins: %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg6 BB#0: derived from LLVM BB %main_body Live Ins: %SGPR6_SGPR7 %VGPR0 %SGPR0_SGPR1_SGPR2_SGPR3 = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%20](align=8)(tbaa=!"const") S_WAITCNT 127 %VGPR1_VGPR2_VGPR3_VGPR4 = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR0, 0, %EXEC S_WAITCNT 1904 EXP 15, 32, 0, 0, 0, %VGPR1, %VGPR2, %VGPR3, %VGPR4, %EXEC, %VGPR1_VGPR2_VGPR3_VGPR4 %SGPR0_SGPR1_SGPR2_SGPR3 = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 0; mem:LD16[%11](align=8)(tbaa=!"const") S_WAITCNT 15 %VGPR0_VGPR1_VGPR2_VGPR3 = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR0, 0, %EXEC S_WAITCNT 1904 EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR1, %VGPR2, %VGPR3, %EXEC, %VGPR0_VGPR1_VGPR2_VGPR3 S_ENDPGM # End machine code for function main. Shader Disassembly: S_LOAD_DWORDX4 s[0:3], s[6:7], 4 ; C0800704 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[1:4], s[0:3][v0] + 0 ; E00C2000 80000100 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 32, 0, 0, 0, v1, v2, v3, v4 ; F800020F 04030201 S_LOAD_DWORDX4 s[0:3], s[6:7], 0 ; C0800700 S_WAITCNT expcnt(0) lgkmcnt(0) ; BF8C000F BUFFER_LOAD_FORMAT_XYZW v[0:3], s[0:3][v0] + 0 ; E00C2000 80000000 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 12, 0, 1, 0, v0, v1, v2, v3 ; F80008CF 03020100 S_ENDPGM ; BF810000 VERT DCL IN[0] DCL OUT[0], POSITION 0: MOV OUT[0], IN[0] 1: END STREAMOUT 0: BUF0[0..0] <- OUT[0].x ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %13 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 0 %14 = load <16 x i8> addrspace(2)* %13, !tbaa !0 %15 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0 %16 = load <16 x i8> addrspace(2)* %15, !tbaa !0 %17 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %16, i32 0, i32 %9) %18 = extractelement <4 x float> %17, i32 0 %19 = extractelement <4 x float> %17, i32 1 %20 = extractelement <4 x float> %17, i32 2 %21 = extractelement <4 x float> %17, i32 3 %22 = lshr i32 %6, 16 %23 = and i32 %22, 127 %24 = call i32 @llvm.SI.tid() %25 = icmp ult i32 %24, %23 br i1 %25, label %if-true-block, label %endif-block if-true-block: ; preds = %main_body %26 = add i32 %7, %24 %27 = mul i32 %8, 4 %28 = mul i32 %26, 4 %29 = add i32 %28, %27 %30 = bitcast float %18 to i32 call void @llvm.SI.tbuffer.store.i32(<16 x i8> %14, i32 %30, i32 1, i32 %29, i32 0, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0) br label %endif-block endif-block: ; preds = %main_body, %if-true-block call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %18, float %19, float %20, float %21) ret void } ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 ; Function Attrs: readnone declare i32 @llvm.SI.tid() #2 declare void @llvm.SI.tbuffer.store.i32(<16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32) declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } !0 = metadata !{metadata !"const", null, i32 1} # Machine code for function main: Post SSA, not tracking liveness Function Live Ins: %SGPR6_SGPR7 in %vreg7, %SGPR8_SGPR9 in %vreg8, %SGPR11 in %vreg10, %SGPR12 in %vreg11, %SGPR13 in %vreg12, %VGPR0 in %vreg13 BB#0: derived from LLVM BB %main_body Live Ins: %SGPR6_SGPR7 %SGPR8_SGPR9 %SGPR11 %SGPR12 %SGPR13 %VGPR0 %SGPR0_SGPR1_SGPR2_SGPR3 = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 0; mem:LD16[%14](align=8)(tbaa=!"const") S_WAITCNT 127 %VGPR0_VGPR1_VGPR2_VGPR3 = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR0, 0, %EXEC %SGPR0 = S_LSHR_B32 %SGPR11, 16 %VGPR4 = V_MOV_B32_e32 127, %EXEC %VGPR5 = V_AND_B32_e32 %SGPR0, %VGPR4, %EXEC %VGPR4 = V_MBCNT_LO_U32_B32_e64 -1, 0, 0, 0, 0, 0, %EXEC %VGPR4 = V_MBCNT_HI_U32_B32_e32 -1, %VGPR4, %EXEC %SGPR0_SGPR1 = V_CMP_LT_U32_e64 %VGPR4, %VGPR5, 0, 0, 0, 0, %EXEC S_WAITCNT 1904 %SGPR0_SGPR1 = S_AND_SAVEEXEC_B64 %SGPR0_SGPR1, %EXEC, %EXEC %SGPR0_SGPR1 = S_XOR_B64 %EXEC, %SGPR0_SGPR1 Successors according to CFG: BB#1(16) BB#2(16) BB#1: derived from LLVM BB %if-true-block Live Ins: %VGPR0_VGPR1_VGPR2_VGPR3 %SGPR8_SGPR9 %SGPR12 %SGPR13 %SGPR0_SGPR1 %VGPR4 Predecessors according to CFG: BB#0 %VGPR4 = V_ADD_I32_e32 %SGPR12, %VGPR4, %EXEC, %VCC %VGPR4 = V_LSHLREV_B32_e32 2, %VGPR4, %EXEC %SGPR2 = S_LSHL_B32 %SGPR13, 2 %VGPR4 = V_ADD_I32_e32 %SGPR2, %VGPR4, %EXEC, %VCC %SGPR4_SGPR5_SGPR6_SGPR7 = S_LOAD_DWORDX4_IMM %SGPR8_SGPR9, 0; mem:LD16[%27](align=8)(tbaa=!"const") S_WAITCNT 127 TBUFFER_STORE_FORMAT_X %VGPR0, 0, -1, 0, -1, 0, 4, 4, %VGPR4, %SGPR4_SGPR5_SGPR6_SGPR7, -1, 0, 0, %EXEC S_WAITCNT 1792 Successors according to CFG: BB#2 BB#2: derived from LLVM BB %endif-block Live Ins: %VGPR0_VGPR1_VGPR2_VGPR3 %SGPR0_SGPR1 Predecessors according to CFG: BB#0 BB#1 %EXEC = S_OR_B64 %EXEC, %SGPR0_SGPR1 EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR1, %VGPR2, %VGPR3, %EXEC, %VGPR0_VGPR1_VGPR2_VGPR3 S_ENDPGM # End machine code for function main. Shader Disassembly: S_LOAD_DWORDX4 s[0:3], s[6:7], 0 ; C0800700 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[0:3], s[0:3][v0] + 0 ; E00C2000 80000000 S_LSHR_B32 s0, s11, 16 ; 9000900B V_MOV_B32_e32 v4, 127 ; 7E0802FF 0000007F V_AND_B32_e32 v5, s0, v4 ; 360A0800 V_MBCNT_LO_U32_B32_e64 v4, -1, 0, 0, 0, 0, 0 ; D2460004 020100C1 V_MBCNT_HI_U32_B32_e32 v4, -1, v4 ; 480808C1 V_CMP_LT_U32_e64 s[0:1], v4, v5, 0, 0, 0, 0 ; D1820000 02020B04 S_WAITCNT vmcnt(0) ; BF8C0770 S_AND_SAVEEXEC_B64 s[0:1], s[0:1] ; BE802400 S_XOR_B64 s[0:1], exec, s[0:1] ; 8980007E V_ADD_I32_e32 v4, s12, v4 ; 4A08080C V_LSHLREV_B32_e32 v4, 2, v4 ; 34080882 S_LSHL_B32 s2, s13, 2 ; 8F02820D V_ADD_I32_e32 v4, s2, v4 ; 4A080802 S_LOAD_DWORDX4 s[4:7], s[8:9], 0 ; C0820900 S_WAITCNT lgkmcnt(0) ; BF8C007F TBUFFER_STORE_FORMAT_X v0, 0, -1, 0, -1, 0, 4, 4, v4, s[4:7], -1, 0, 0 ; EA245000 80410004 S_WAITCNT vmcnt(0) expcnt(0) ; BF8C0700 S_OR_B64 exec, exec, s[0:1] ; 88FE007E EXP 15, 12, 0, 1, 0, v0, v1, v2, v3 ; F80008CF 03020100 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[0], CONSTANT 0: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } # Machine code for function main: Post SSA, not tracking liveness BB#0: derived from LLVM BB %main_body %VGPR0 = V_MOV_B32_e32 0, %EXEC EXP 0, 0, 0, 1, 1, %VGPR0, %VGPR0, %VGPR0, %VGPR0, %EXEC S_ENDPGM # End machine code for function main. Shader Disassembly: V_MOV_B32_e32 v0, 0 ; 7E000280 EXP 0, 0, 0, 1, 1, v0, v0, v0, v0 ; F8001800 00000000 S_ENDPGM ; BF810000 FRAG 0: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) ret void } declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32) attributes #0 = { "ShaderType"="0" } # Machine code for function main: Post SSA, not tracking liveness BB#0: derived from LLVM BB %main_body %VGPR0 = V_MOV_B32_e32 0, %EXEC EXP 0, 0, 0, 1, 1, %VGPR0, %VGPR0, %VGPR0, %VGPR0, %EXEC S_ENDPGM # End machine code for function main. Shader Disassembly: V_MOV_B32_e32 v0, 0 ; 7E000280 EXP 0, 0, 0, 1, 1, v0, v0, v0, v0 ; F8001800 00000000 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %21 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %4) %22 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %4) %23 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %4) %24 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %4) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %21, float %22, float %23, float %24) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } # Machine code for function main: Post SSA, not tracking liveness Function Live Ins: %SGPR7 in %vreg4 BB#0: derived from LLVM BB %main_body Live Ins: %SGPR7 %EXEC = S_WQM_B64 %EXEC %M0 = S_MOV_B32 %SGPR7 %VGPR0 = V_INTERP_MOV_F32 2, 3, 0, %M0, %EXEC %VGPR1 = V_INTERP_MOV_F32 2, 2, 0, %M0, %EXEC %VGPR2 = V_INTERP_MOV_F32 2, 1, 0, %M0, %EXEC %VGPR3 = V_INTERP_MOV_F32 2, 0, 0, %M0, %EXEC EXP 15, 0, 0, 1, 1, %VGPR3, %VGPR2, %VGPR1, %VGPR0, %EXEC S_ENDPGM # End machine code for function main. Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s7 ; BEFC0307 V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302 V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202 V_INTERP_MOV_F32 v2, P0, 1, 0, [m0] ; C80A0102 V_INTERP_MOV_F32 v3, P0, 0, 0, [m0] ; C80E0002 EXP 15, 0, 0, 1, 1, v3, v2, v1, v0 ; F800180F 00010203 S_ENDPGM ; BF810000 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %21 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %4) %22 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %4) %23 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %4) %24 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %4) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %21, float %22, float %23, float %24) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } # Machine code for function main: Post SSA, not tracking liveness Function Live Ins: %SGPR7 in %vreg4 BB#0: derived from LLVM BB %main_body Live Ins: %SGPR7 %EXEC = S_WQM_B64 %EXEC %M0 = S_MOV_B32 %SGPR7 %VGPR0 = V_INTERP_MOV_F32 2, 3, 0, %M0, %EXEC %VGPR1 = V_INTERP_MOV_F32 2, 2, 0, %M0, %EXEC %VGPR2 = V_INTERP_MOV_F32 2, 1, 0, %M0, %EXEC %VGPR3 = V_INTERP_MOV_F32 2, 0, 0, %M0, %EXEC EXP 15, 0, 0, 1, 1, %VGPR3, %VGPR2, %VGPR1, %VGPR0, %EXEC S_ENDPGM # End machine code for function main. Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s7 ; BEFC0307 V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302 V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202 V_INTERP_MOV_F32 v2, P0, 1, 0, [m0] ; C80A0102 V_INTERP_MOV_F32 v3, P0, 0, 0, [m0] ; C80E0002 EXP 15, 0, 0, 1, 1, v3, v2, v1, v0 ; F800180F 00010203 S_ENDPGM ; BF810000 VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] 0: MOV OUT[0], IN[0] 1: MOV OUT[1], IN[1] 2: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0 %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0 %12 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %11, i32 0, i32 %6) %13 = extractelement <4 x float> %12, i32 0 %14 = extractelement <4 x float> %12, i32 1 %15 = extractelement <4 x float> %12, i32 2 %16 = extractelement <4 x float> %12, i32 3 %17 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 1 %18 = load <16 x i8> addrspace(2)* %17, !tbaa !0 %19 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %18, i32 0, i32 %6) %20 = extractelement <4 x float> %19, i32 0 %21 = extractelement <4 x float> %19, i32 1 %22 = extractelement <4 x float> %19, i32 2 %23 = extractelement <4 x float> %19, i32 3 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %20, float %21, float %22, float %23) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %13, float %14, float %15, float %16) ret void } ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} # Machine code for function main: Post SSA, not tracking liveness Function Live Ins: %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg6 BB#0: derived from LLVM BB %main_body Live Ins: %SGPR6_SGPR7 %VGPR0 %SGPR0_SGPR1_SGPR2_SGPR3 = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%20](align=8)(tbaa=!"const") S_WAITCNT 127 %VGPR1_VGPR2_VGPR3_VGPR4 = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR0, 0, %EXEC S_WAITCNT 1904 EXP 15, 32, 0, 0, 0, %VGPR1, %VGPR2, %VGPR3, %VGPR4, %EXEC, %VGPR1_VGPR2_VGPR3_VGPR4 %SGPR0_SGPR1_SGPR2_SGPR3 = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 0; mem:LD16[%11](align=8)(tbaa=!"const") S_WAITCNT 15 %VGPR0_VGPR1_VGPR2_VGPR3 = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR0, 0, %EXEC S_WAITCNT 1904 EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR1, %VGPR2, %VGPR3, %EXEC, %VGPR0_VGPR1_VGPR2_VGPR3 S_ENDPGM # End machine code for function main. Shader Disassembly: S_LOAD_DWORDX4 s[0:3], s[6:7], 4 ; C0800704 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[1:4], s[0:3][v0] + 0 ; E00C2000 80000100 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 32, 0, 0, 0, v1, v2, v3, v4 ; F800020F 04030201 S_LOAD_DWORDX4 s[0:3], s[6:7], 0 ; C0800700 S_WAITCNT expcnt(0) lgkmcnt(0) ; BF8C000F BUFFER_LOAD_FORMAT_XYZW v[0:3], s[0:3][v0] + 0 ; E00C2000 80000000 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 12, 0, 1, 0, v0, v1, v2, v3 ; F80008CF 03020100 S_ENDPGM ; BF810000 VERT DCL IN[0] DCL OUT[0], POSITION 0: MOV OUT[0], IN[0] 1: END STREAMOUT 0: BUF0[0..0] <- OUT[0].x ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %13 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 0 %14 = load <16 x i8> addrspace(2)* %13, !tbaa !0 %15 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0 %16 = load <16 x i8> addrspace(2)* %15, !tbaa !0 %17 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %16, i32 0, i32 %9) %18 = extractelement <4 x float> %17, i32 0 %19 = extractelement <4 x float> %17, i32 1 %20 = extractelement <4 x float> %17, i32 2 %21 = extractelement <4 x float> %17, i32 3 %22 = lshr i32 %6, 16 %23 = and i32 %22, 127 %24 = call i32 @llvm.SI.tid() %25 = icmp ult i32 %24, %23 br i1 %25, label %if-true-block, label %endif-block if-true-block: ; preds = %main_body %26 = add i32 %7, %24 %27 = mul i32 %8, 4 %28 = mul i32 %26, 4 %29 = add i32 %28, %27 %30 = bitcast float %18 to i32 call void @llvm.SI.tbuffer.store.i32(<16 x i8> %14, i32 %30, i32 1, i32 %29, i32 0, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0) br label %endif-block endif-block: ; preds = %main_body, %if-true-block call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %18, float %19, float %20, float %21) ret void } ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 ; Function Attrs: readnone declare i32 @llvm.SI.tid() #2 declare void @llvm.SI.tbuffer.store.i32(<16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32) declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } !0 = metadata !{metadata !"const", null, i32 1} # Machine code for function main: Post SSA, not tracking liveness Function Live Ins: %SGPR6_SGPR7 in %vreg7, %SGPR8_SGPR9 in %vreg8, %SGPR11 in %vreg10, %SGPR12 in %vreg11, %SGPR13 in %vreg12, %VGPR0 in %vreg13 BB#0: derived from LLVM BB %main_body Live Ins: %SGPR6_SGPR7 %SGPR8_SGPR9 %SGPR11 %SGPR12 %SGPR13 %VGPR0 %SGPR0_SGPR1_SGPR2_SGPR3 = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 0; mem:LD16[%14](align=8)(tbaa=!"const") S_WAITCNT 127 %VGPR0_VGPR1_VGPR2_VGPR3 = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR0, 0, %EXEC %SGPR0 = S_LSHR_B32 %SGPR11, 16 %VGPR4 = V_MOV_B32_e32 127, %EXEC %VGPR5 = V_AND_B32_e32 %SGPR0, %VGPR4, %EXEC %VGPR4 = V_MBCNT_LO_U32_B32_e64 -1, 0, 0, 0, 0, 0, %EXEC %VGPR4 = V_MBCNT_HI_U32_B32_e32 -1, %VGPR4, %EXEC %SGPR0_SGPR1 = V_CMP_LT_U32_e64 %VGPR4, %VGPR5, 0, 0, 0, 0, %EXEC S_WAITCNT 1904 %SGPR0_SGPR1 = S_AND_SAVEEXEC_B64 %SGPR0_SGPR1, %EXEC, %EXEC %SGPR0_SGPR1 = S_XOR_B64 %EXEC, %SGPR0_SGPR1 Successors according to CFG: BB#1(16) BB#2(16) BB#1: derived from LLVM BB %if-true-block Live Ins: %VGPR0_VGPR1_VGPR2_VGPR3 %SGPR8_SGPR9 %SGPR12 %SGPR13 %SGPR0_SGPR1 %VGPR4 Predecessors according to CFG: BB#0 %VGPR4 = V_ADD_I32_e32 %SGPR12, %VGPR4, %EXEC, %VCC %VGPR4 = V_LSHLREV_B32_e32 2, %VGPR4, %EXEC %SGPR2 = S_LSHL_B32 %SGPR13, 2 %VGPR4 = V_ADD_I32_e32 %SGPR2, %VGPR4, %EXEC, %VCC %SGPR4_SGPR5_SGPR6_SGPR7 = S_LOAD_DWORDX4_IMM %SGPR8_SGPR9, 0; mem:LD16[%27](align=8)(tbaa=!"const") S_WAITCNT 127 TBUFFER_STORE_FORMAT_X %VGPR0, 0, -1, 0, -1, 0, 4, 4, %VGPR4, %SGPR4_SGPR5_SGPR6_SGPR7, -1, 0, 0, %EXEC S_WAITCNT 1792 Successors according to CFG: BB#2 BB#2: derived from LLVM BB %endif-block Live Ins: %VGPR0_VGPR1_VGPR2_VGPR3 %SGPR0_SGPR1 Predecessors according to CFG: BB#0 BB#1 %EXEC = S_OR_B64 %EXEC, %SGPR0_SGPR1 EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR1, %VGPR2, %VGPR3, %EXEC, %VGPR0_VGPR1_VGPR2_VGPR3 S_ENDPGM # End machine code for function main. Shader Disassembly: S_LOAD_DWORDX4 s[0:3], s[6:7], 0 ; C0800700 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[0:3], s[0:3][v0] + 0 ; E00C2000 80000000 S_LSHR_B32 s0, s11, 16 ; 9000900B V_MOV_B32_e32 v4, 127 ; 7E0802FF 0000007F V_AND_B32_e32 v5, s0, v4 ; 360A0800 V_MBCNT_LO_U32_B32_e64 v4, -1, 0, 0, 0, 0, 0 ; D2460004 020100C1 V_MBCNT_HI_U32_B32_e32 v4, -1, v4 ; 480808C1 V_CMP_LT_U32_e64 s[0:1], v4, v5, 0, 0, 0, 0 ; D1820000 02020B04 S_WAITCNT vmcnt(0) ; BF8C0770 S_AND_SAVEEXEC_B64 s[0:1], s[0:1] ; BE802400 S_XOR_B64 s[0:1], exec, s[0:1] ; 8980007E V_ADD_I32_e32 v4, s12, v4 ; 4A08080C V_LSHLREV_B32_e32 v4, 2, v4 ; 34080882 S_LSHL_B32 s2, s13, 2 ; 8F02820D V_ADD_I32_e32 v4, s2, v4 ; 4A080802 S_LOAD_DWORDX4 s[4:7], s[8:9], 0 ; C0820900 S_WAITCNT lgkmcnt(0) ; BF8C007F TBUFFER_STORE_FORMAT_X v0, 0, -1, 0, -1, 0, 4, 4, v4, s[4:7], -1, 0, 0 ; EA245000 80410004 S_WAITCNT vmcnt(0) expcnt(0) ; BF8C0700 S_OR_B64 exec, exec, s[0:1] ; 88FE007E EXP 15, 12, 0, 1, 0, v0, v1, v2, v3 ; F80008CF 03020100 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[0], CONSTANT 0: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } # Machine code for function main: Post SSA, not tracking liveness BB#0: derived from LLVM BB %main_body %VGPR0 = V_MOV_B32_e32 0, %EXEC EXP 0, 0, 0, 1, 1, %VGPR0, %VGPR0, %VGPR0, %VGPR0, %EXEC S_ENDPGM # End machine code for function main. Shader Disassembly: V_MOV_B32_e32 v0, 0 ; 7E000280 EXP 0, 0, 0, 1, 1, v0, v0, v0, v0 ; F8001800 00000000 S_ENDPGM ; BF810000 Installing breakpad exception handler for appid(steam)/version(1383158641_client) Installing breakpad exception handler for appid(steam)/version(1383158641_client) unlinked 0 orphaned pipes removing stale semaphore last operated on by process 20218 with name 0eBlobRegistryMutex_39626960151840A68533EB6D56096F9D removing stale semaphore last operated on by process 20218 with name 0eBlobRegistrySignal_39626960151840A68533EB6D56096F9D removing stale semaphore last operated on by process 20218 with name 0emSteamEngineInstance removing stale semaphore last operated on by process 20218 with name 0eSteamEngineLock Fontconfig error: "/etc/fonts/conf.d/10-scale-bitmap-fonts.conf", line 70: non-double matrix element Fontconfig error: "/etc/fonts/conf.d/10-scale-bitmap-fonts.conf", line 70: non-double matrix element Fontconfig warning: "/etc/fonts/conf.d/10-scale-bitmap-fonts.conf", line 78: saw unknown, expected number Installing breakpad exception handler for appid(steam)/version(1383158641_client) Looks like steam didn't shutdown cleanly, scheduling immediate update check [2013-11-23 15:29:01] Checking for update on startup [2013-11-23 15:29:01] Checking for available updates... [2013-11-23 15:29:02] Download skipped: /client/steam_client_ubuntu12 version 1383158641, installed version 1383158641 [2013-11-23 15:29:02] Nothing to do [2013-11-23 15:29:02] Verifying installation... [2013-11-23 15:29:02] Performing checksum verification of executable files [2013-11-23 15:29:03] BVerifyInstalledFiles: bad CRC on linux32/steamerrorreporter (b44f4bc expected, d9741f19 actual) [2013-11-23 15:29:04] BVerifyInstalledFiles: steam.sh is 21689 bytes, expected 22072 [2013-11-23 15:29:04] BVerifyInstalledFiles: bad CRC on ubuntu12_32/crashhandler.so (595a711c expected, 6aafc2c9 actual) [2013-11-23 15:29:06] BVerifyInstalledFiles: ubuntu12_32/steam is 3448966 bytes, expected 3456286 [2013-11-23 15:29:08] Verification complete [2013-11-23 15:29:08] BRepairInstalledFiles: ignoring bootstrap file ubuntu12_32/steam [2013-11-23 15:29:08] BRepairInstalledFiles: ignoring bootstrap file steam.sh FRAG 0: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) ret void } declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32) attributes #0 = { "ShaderType"="0" } # Machine code for function main: Post SSA, not tracking liveness BB#0: derived from LLVM BB %main_body %VGPR0 = V_MOV_B32_e32 0, %EXEC EXP 0, 0, 0, 1, 1, %VGPR0, %VGPR0, %VGPR0, %VGPR0, %EXEC S_ENDPGM # End machine code for function main. Shader Disassembly: V_MOV_B32_e32 v0, 0 ; 7E000280 EXP 0, 0, 0, 1, 1, v0, v0, v0, v0 ; F8001800 00000000 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %21 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %4) %22 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %4) %23 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %4) %24 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %4) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %21, float %22, float %23, float %24) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } [1123/152908:WARNING:proxy_service.cc(958)] PAC support disabled because there is no system implementation # Machine code for function main: Post SSA, not tracking liveness Function Live Ins: %SGPR7 in %vreg4 BB#0: derived from LLVM BB %main_body Live Ins: %SGPR7 %EXEC = S_WQM_B64 %EXEC %M0 = S_MOV_B32 %SGPR7 %VGPR0 = V_INTERP_MOV_F32 2, 3, 0, %M0, %EXEC %VGPR1 = V_INTERP_MOV_F32 2, 2, 0, %M0, %EXEC %VGPR2 = V_INTERP_MOV_F32 2, 1, 0, %M0, %EXEC %VGPR3 = V_INTERP_MOV_F32 2, 0, 0, %M0, %EXEC EXP 15, 0, 0, 1, 1, %VGPR3, %VGPR2, %VGPR1, %VGPR0, %EXEC S_ENDPGM # End machine code for function main. Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s7 ; BEFC0307 V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302 V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202 V_INTERP_MOV_F32 v2, P0, 1, 0, [m0] ; C80A0102 V_INTERP_MOV_F32 v3, P0, 0, 0, [m0] ; C80E0002 EXP 15, 0, 0, 1, 1, v3, v2, v1, v0 ; F800180F 00010203 S_ENDPGM ; BF810000 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %21 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %4) %22 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %4) %23 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %4) %24 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %4) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %21, float %22, float %23, float %24) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } # Machine code for function main: Post SSA, not tracking liveness Function Live Ins: %SGPR7 in %vreg4 BB#0: derived from LLVM BB %main_body Live Ins: %SGPR7 %EXEC = S_WQM_B64 %EXEC %M0 = S_MOV_B32 %SGPR7 %VGPR0 = V_INTERP_MOV_F32 2, 3, 0, %M0, %EXEC %VGPR1 = V_INTERP_MOV_F32 2, 2, 0, %M0, %EXEC %VGPR2 = V_INTERP_MOV_F32 2, 1, 0, %M0, %EXEC %VGPR3 = V_INTERP_MOV_F32 2, 0, 0, %M0, %EXEC EXP 15, 0, 0, 1, 1, %VGPR3, %VGPR2, %VGPR1, %VGPR0, %EXEC S_ENDPGM # End machine code for function main. Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s7 ; BEFC0307 V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302 V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202 V_INTERP_MOV_F32 v2, P0, 1, 0, [m0] ; C80A0102 V_INTERP_MOV_F32 v3, P0, 0, 0, [m0] ; C80E0002 EXP 15, 0, 0, 1, 1, v3, v2, v1, v0 ; F800180F 00010203 S_ENDPGM ; BF810000 VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] 0: MOV OUT[0], IN[0] 1: MOV OUT[1], IN[1] 2: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0 %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0 %12 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %11, i32 0, i32 %6) %13 = extractelement <4 x float> %12, i32 0 %14 = extractelement <4 x float> %12, i32 1 %15 = extractelement <4 x float> %12, i32 2 %16 = extractelement <4 x float> %12, i32 3 %17 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 1 %18 = load <16 x i8> addrspace(2)* %17, !tbaa !0 %19 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %18, i32 0, i32 %6) %20 = extractelement <4 x float> %19, i32 0 %21 = extractelement <4 x float> %19, i32 1 %22 = extractelement <4 x float> %19, i32 2 %23 = extractelement <4 x float> %19, i32 3 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %20, float %21, float %22, float %23) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %13, float %14, float %15, float %16) ret void } ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} # Machine code for function main: Post SSA, not tracking liveness Function Live Ins: %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg6 BB#0: derived from LLVM BB %main_body Live Ins: %SGPR6_SGPR7 %VGPR0 %SGPR0_SGPR1_SGPR2_SGPR3 = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%20](align=8)(tbaa=!"const") S_WAITCNT 127 %VGPR1_VGPR2_VGPR3_VGPR4 = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR0, 0, %EXEC S_WAITCNT 1904 EXP 15, 32, 0, 0, 0, %VGPR1, %VGPR2, %VGPR3, %VGPR4, %EXEC, %VGPR1_VGPR2_VGPR3_VGPR4 %SGPR0_SGPR1_SGPR2_SGPR3 = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 0; mem:LD16[%11](align=8)(tbaa=!"const") S_WAITCNT 15 %VGPR0_VGPR1_VGPR2_VGPR3 = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR0, 0, %EXEC S_WAITCNT 1904 EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR1, %VGPR2, %VGPR3, %EXEC, %VGPR0_VGPR1_VGPR2_VGPR3 S_ENDPGM # End machine code for function main. Shader Disassembly: S_LOAD_DWORDX4 s[0:3], s[6:7], 4 ; C0800704 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[1:4], s[0:3][v0] + 0 ; E00C2000 80000100 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 32, 0, 0, 0, v1, v2, v3, v4 ; F800020F 04030201 S_LOAD_DWORDX4 s[0:3], s[6:7], 0 ; C0800700 S_WAITCNT expcnt(0) lgkmcnt(0) ; BF8C000F BUFFER_LOAD_FORMAT_XYZW v[0:3], s[0:3][v0] + 0 ; E00C2000 80000000 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 12, 0, 1, 0, v0, v1, v2, v3 ; F80008CF 03020100 S_ENDPGM ; BF810000 VERT DCL IN[0] DCL OUT[0], POSITION 0: MOV OUT[0], IN[0] 1: END STREAMOUT 0: BUF0[0..0] <- OUT[0].x ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %13 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 0 %14 = load <16 x i8> addrspace(2)* %13, !tbaa !0 %15 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0 %16 = load <16 x i8> addrspace(2)* %15, !tbaa !0 %17 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %16, i32 0, i32 %9) %18 = extractelement <4 x float> %17, i32 0 %19 = extractelement <4 x float> %17, i32 1 %20 = extractelement <4 x float> %17, i32 2 %21 = extractelement <4 x float> %17, i32 3 %22 = lshr i32 %6, 16 %23 = and i32 %22, 127 %24 = call i32 @llvm.SI.tid() %25 = icmp ult i32 %24, %23 br i1 %25, label %if-true-block, label %endif-block if-true-block: ; preds = %main_body %26 = add i32 %7, %24 %27 = mul i32 %8, 4 %28 = mul i32 %26, 4 %29 = add i32 %28, %27 %30 = bitcast float %18 to i32 call void @llvm.SI.tbuffer.store.i32(<16 x i8> %14, i32 %30, i32 1, i32 %29, i32 0, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0) br label %endif-block endif-block: ; preds = %main_body, %if-true-block call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %18, float %19, float %20, float %21) ret void } ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 ; Function Attrs: readnone declare i32 @llvm.SI.tid() #2 declare void @llvm.SI.tbuffer.store.i32(<16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32) declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } !0 = metadata !{metadata !"const", null, i32 1} # Machine code for function main: Post SSA, not tracking liveness Function Live Ins: %SGPR6_SGPR7 in %vreg7, %SGPR8_SGPR9 in %vreg8, %SGPR11 in %vreg10, %SGPR12 in %vreg11, %SGPR13 in %vreg12, %VGPR0 in %vreg13 BB#0: derived from LLVM BB %main_body Live Ins: %SGPR6_SGPR7 %SGPR8_SGPR9 %SGPR11 %SGPR12 %SGPR13 %VGPR0 %SGPR0_SGPR1_SGPR2_SGPR3 = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 0; mem:LD16[%14](align=8)(tbaa=!"const") S_WAITCNT 127 %VGPR0_VGPR1_VGPR2_VGPR3 = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR0, 0, %EXEC %SGPR0 = S_LSHR_B32 %SGPR11, 16 %VGPR4 = V_MOV_B32_e32 127, %EXEC %VGPR5 = V_AND_B32_e32 %SGPR0, %VGPR4, %EXEC %VGPR4 = V_MBCNT_LO_U32_B32_e64 -1, 0, 0, 0, 0, 0, %EXEC %VGPR4 = V_MBCNT_HI_U32_B32_e32 -1, %VGPR4, %EXEC %SGPR0_SGPR1 = V_CMP_LT_U32_e64 %VGPR4, %VGPR5, 0, 0, 0, 0, %EXEC S_WAITCNT 1904 %SGPR0_SGPR1 = S_AND_SAVEEXEC_B64 %SGPR0_SGPR1, %EXEC, %EXEC %SGPR0_SGPR1 = S_XOR_B64 %EXEC, %SGPR0_SGPR1 Successors according to CFG: BB#1(16) BB#2(16) BB#1: derived from LLVM BB %if-true-block Live Ins: %VGPR0_VGPR1_VGPR2_VGPR3 %SGPR8_SGPR9 %SGPR12 %SGPR13 %SGPR0_SGPR1 %VGPR4 Predecessors according to CFG: BB#0 %VGPR4 = V_ADD_I32_e32 %SGPR12, %VGPR4, %EXEC, %VCC %VGPR4 = V_LSHLREV_B32_e32 2, %VGPR4, %EXEC %SGPR2 = S_LSHL_B32 %SGPR13, 2 %VGPR4 = V_ADD_I32_e32 %SGPR2, %VGPR4, %EXEC, %VCC %SGPR4_SGPR5_SGPR6_SGPR7 = S_LOAD_DWORDX4_IMM %SGPR8_SGPR9, 0; mem:LD16[%27](align=8)(tbaa=!"const") S_WAITCNT 127 TBUFFER_STORE_FORMAT_X %VGPR0, 0, -1, 0, -1, 0, 4, 4, %VGPR4, %SGPR4_SGPR5_SGPR6_SGPR7, -1, 0, 0, %EXEC S_WAITCNT 1792 Successors according to CFG: BB#2 BB#2: derived from LLVM BB %endif-block Live Ins: %VGPR0_VGPR1_VGPR2_VGPR3 %SGPR0_SGPR1 Predecessors according to CFG: BB#0 BB#1 %EXEC = S_OR_B64 %EXEC, %SGPR0_SGPR1 EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR1, %VGPR2, %VGPR3, %EXEC, %VGPR0_VGPR1_VGPR2_VGPR3 S_ENDPGM # End machine code for function main. Shader Disassembly: S_LOAD_DWORDX4 s[0:3], s[6:7], 0 ; C0800700 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[0:3], s[0:3][v0] + 0 ; E00C2000 80000000 S_LSHR_B32 s0, s11, 16 ; 9000900B V_MOV_B32_e32 v4, 127 ; 7E0802FF 0000007F V_AND_B32_e32 v5, s0, v4 ; 360A0800 V_MBCNT_LO_U32_B32_e64 v4, -1, 0, 0, 0, 0, 0 ; D2460004 020100C1 V_MBCNT_HI_U32_B32_e32 v4, -1, v4 ; 480808C1 V_CMP_LT_U32_e64 s[0:1], v4, v5, 0, 0, 0, 0 ; D1820000 02020B04 S_WAITCNT vmcnt(0) ; BF8C0770 S_AND_SAVEEXEC_B64 s[0:1], s[0:1] ; BE802400 S_XOR_B64 s[0:1], exec, s[0:1] ; 8980007E V_ADD_I32_e32 v4, s12, v4 ; 4A08080C V_LSHLREV_B32_e32 v4, 2, v4 ; 34080882 S_LSHL_B32 s2, s13, 2 ; 8F02820D V_ADD_I32_e32 v4, s2, v4 ; 4A080802 S_LOAD_DWORDX4 s[4:7], s[8:9], 0 ; C0820900 S_WAITCNT lgkmcnt(0) ; BF8C007F TBUFFER_STORE_FORMAT_X v0, 0, -1, 0, -1, 0, 4, 4, v4, s[4:7], -1, 0, 0 ; EA245000 80410004 S_WAITCNT vmcnt(0) expcnt(0) ; BF8C0700 S_OR_B64 exec, exec, s[0:1] ; 88FE007E EXP 15, 12, 0, 1, 0, v0, v1, v2, v3 ; F80008CF 03020100 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[0], CONSTANT 0: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } # Machine code for function main: Post SSA, not tracking liveness BB#0: derived from LLVM BB %main_body %VGPR0 = V_MOV_B32_e32 0, %EXEC EXP 0, 0, 0, 1, 1, %VGPR0, %VGPR0, %VGPR0, %VGPR0, %EXEC S_ENDPGM # End machine code for function main. Shader Disassembly: V_MOV_B32_e32 v0, 0 ; 7E000280 EXP 0, 0, 0, 1, 1, v0, v0, v0, v0 ; F8001800 00000000 S_ENDPGM ; BF810000 FRAG 0: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) ret void } declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32) attributes #0 = { "ShaderType"="0" } # Machine code for function main: Post SSA, not tracking liveness BB#0: derived from LLVM BB %main_body %VGPR0 = V_MOV_B32_e32 0, %EXEC EXP 0, 0, 0, 1, 1, %VGPR0, %VGPR0, %VGPR0, %VGPR0, %EXEC S_ENDPGM # End machine code for function main. Shader Disassembly: V_MOV_B32_e32 v0, 0 ; 7E000280 EXP 0, 0, 0, 1, 1, v0, v0, v0, v0 ; F8001800 00000000 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %21 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %4) %22 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %4) %23 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %4) %24 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %4) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %21, float %22, float %23, float %24) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } # Machine code for function main: Post SSA, not tracking liveness Function Live Ins: %SGPR7 in %vreg4 BB#0: derived from LLVM BB %main_body Live Ins: %SGPR7 %EXEC = S_WQM_B64 %EXEC %M0 = S_MOV_B32 %SGPR7 %VGPR0 = V_INTERP_MOV_F32 2, 3, 0, %M0, %EXEC %VGPR1 = V_INTERP_MOV_F32 2, 2, 0, %M0, %EXEC %VGPR2 = V_INTERP_MOV_F32 2, 1, 0, %M0, %EXEC %VGPR3 = V_INTERP_MOV_F32 2, 0, 0, %M0, %EXEC EXP 15, 0, 0, 1, 1, %VGPR3, %VGPR2, %VGPR1, %VGPR0, %EXEC S_ENDPGM # End machine code for function main. Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s7 ; BEFC0307 V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302 V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202 V_INTERP_MOV_F32 v2, P0, 1, 0, [m0] ; C80A0102 V_INTERP_MOV_F32 v3, P0, 0, 0, [m0] ; C80E0002 EXP 15, 0, 0, 1, 1, v3, v2, v1, v0 ; F800180F 00010203 S_ENDPGM ; BF810000 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %21 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %4) %22 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %4) %23 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %4) %24 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %4) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %21, float %22, float %23, float %24) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } # Machine code for function main: Post SSA, not tracking liveness Function Live Ins: %SGPR7 in %vreg4 BB#0: derived from LLVM BB %main_body Live Ins: %SGPR7 %EXEC = S_WQM_B64 %EXEC %M0 = S_MOV_B32 %SGPR7 %VGPR0 = V_INTERP_MOV_F32 2, 3, 0, %M0, %EXEC %VGPR1 = V_INTERP_MOV_F32 2, 2, 0, %M0, %EXEC %VGPR2 = V_INTERP_MOV_F32 2, 1, 0, %M0, %EXEC %VGPR3 = V_INTERP_MOV_F32 2, 0, 0, %M0, %EXEC EXP 15, 0, 0, 1, 1, %VGPR3, %VGPR2, %VGPR1, %VGPR0, %EXEC S_ENDPGM # End machine code for function main. Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s7 ; BEFC0307 V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302 V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202 V_INTERP_MOV_F32 v2, P0, 1, 0, [m0] ; C80A0102 V_INTERP_MOV_F32 v3, P0, 0, 0, [m0] ; C80E0002 EXP 15, 0, 0, 1, 1, v3, v2, v1, v0 ; F800180F 00010203 S_ENDPGM ; BF810000 VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] 0: MOV OUT[0], IN[0] 1: MOV OUT[1], IN[1] 2: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0 %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0 %12 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %11, i32 0, i32 %6) %13 = extractelement <4 x float> %12, i32 0 %14 = extractelement <4 x float> %12, i32 1 %15 = extractelement <4 x float> %12, i32 2 %16 = extractelement <4 x float> %12, i32 3 %17 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 1 %18 = load <16 x i8> addrspace(2)* %17, !tbaa !0 %19 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %18, i32 0, i32 %6) %20 = extractelement <4 x float> %19, i32 0 %21 = extractelement <4 x float> %19, i32 1 %22 = extractelement <4 x float> %19, i32 2 %23 = extractelement <4 x float> %19, i32 3 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %20, float %21, float %22, float %23) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %13, float %14, float %15, float %16) ret void } ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} # Machine code for function main: Post SSA, not tracking liveness Function Live Ins: %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg6 BB#0: derived from LLVM BB %main_body Live Ins: %SGPR6_SGPR7 %VGPR0 %SGPR0_SGPR1_SGPR2_SGPR3 = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%20](align=8)(tbaa=!"const") S_WAITCNT 127 %VGPR1_VGPR2_VGPR3_VGPR4 = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR0, 0, %EXEC S_WAITCNT 1904 EXP 15, 32, 0, 0, 0, %VGPR1, %VGPR2, %VGPR3, %VGPR4, %EXEC, %VGPR1_VGPR2_VGPR3_VGPR4 %SGPR0_SGPR1_SGPR2_SGPR3 = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 0; mem:LD16[%11](align=8)(tbaa=!"const") S_WAITCNT 15 %VGPR0_VGPR1_VGPR2_VGPR3 = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR0, 0, %EXEC S_WAITCNT 1904 EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR1, %VGPR2, %VGPR3, %EXEC, %VGPR0_VGPR1_VGPR2_VGPR3 S_ENDPGM # End machine code for function main. Shader Disassembly: S_LOAD_DWORDX4 s[0:3], s[6:7], 4 ; C0800704 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[1:4], s[0:3][v0] + 0 ; E00C2000 80000100 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 32, 0, 0, 0, v1, v2, v3, v4 ; F800020F 04030201 S_LOAD_DWORDX4 s[0:3], s[6:7], 0 ; C0800700 S_WAITCNT expcnt(0) lgkmcnt(0) ; BF8C000F BUFFER_LOAD_FORMAT_XYZW v[0:3], s[0:3][v0] + 0 ; E00C2000 80000000 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 12, 0, 1, 0, v0, v1, v2, v3 ; F80008CF 03020100 S_ENDPGM ; BF810000 VERT DCL IN[0] DCL OUT[0], POSITION 0: MOV OUT[0], IN[0] 1: END STREAMOUT 0: BUF0[0..0] <- OUT[0].x ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %13 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 0 %14 = load <16 x i8> addrspace(2)* %13, !tbaa !0 %15 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0 %16 = load <16 x i8> addrspace(2)* %15, !tbaa !0 %17 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %16, i32 0, i32 %9) %18 = extractelement <4 x float> %17, i32 0 %19 = extractelement <4 x float> %17, i32 1 %20 = extractelement <4 x float> %17, i32 2 %21 = extractelement <4 x float> %17, i32 3 %22 = lshr i32 %6, 16 %23 = and i32 %22, 127 %24 = call i32 @llvm.SI.tid() %25 = icmp ult i32 %24, %23 br i1 %25, label %if-true-block, label %endif-block if-true-block: ; preds = %main_body %26 = add i32 %7, %24 %27 = mul i32 %8, 4 %28 = mul i32 %26, 4 %29 = add i32 %28, %27 %30 = bitcast float %18 to i32 call void @llvm.SI.tbuffer.store.i32(<16 x i8> %14, i32 %30, i32 1, i32 %29, i32 0, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0) br label %endif-block endif-block: ; preds = %main_body, %if-true-block call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %18, float %19, float %20, float %21) ret void } ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 ; Function Attrs: readnone declare i32 @llvm.SI.tid() #2 declare void @llvm.SI.tbuffer.store.i32(<16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32) declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } !0 = metadata !{metadata !"const", null, i32 1} # Machine code for function main: Post SSA, not tracking liveness Function Live Ins: %SGPR6_SGPR7 in %vreg7, %SGPR8_SGPR9 in %vreg8, %SGPR11 in %vreg10, %SGPR12 in %vreg11, %SGPR13 in %vreg12, %VGPR0 in %vreg13 BB#0: derived from LLVM BB %main_body Live Ins: %SGPR6_SGPR7 %SGPR8_SGPR9 %SGPR11 %SGPR12 %SGPR13 %VGPR0 %SGPR0_SGPR1_SGPR2_SGPR3 = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 0; mem:LD16[%14](align=8)(tbaa=!"const") S_WAITCNT 127 %VGPR0_VGPR1_VGPR2_VGPR3 = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR0, 0, %EXEC %SGPR0 = S_LSHR_B32 %SGPR11, 16 %VGPR4 = V_MOV_B32_e32 127, %EXEC %VGPR5 = V_AND_B32_e32 %SGPR0, %VGPR4, %EXEC %VGPR4 = V_MBCNT_LO_U32_B32_e64 -1, 0, 0, 0, 0, 0, %EXEC %VGPR4 = V_MBCNT_HI_U32_B32_e32 -1, %VGPR4, %EXEC %SGPR0_SGPR1 = V_CMP_LT_U32_e64 %VGPR4, %VGPR5, 0, 0, 0, 0, %EXEC S_WAITCNT 1904 %SGPR0_SGPR1 = S_AND_SAVEEXEC_B64 %SGPR0_SGPR1, %EXEC, %EXEC %SGPR0_SGPR1 = S_XOR_B64 %EXEC, %SGPR0_SGPR1 Successors according to CFG: BB#1(16) BB#2(16) BB#1: derived from LLVM BB %if-true-block Live Ins: %VGPR0_VGPR1_VGPR2_VGPR3 %SGPR8_SGPR9 %SGPR12 %SGPR13 %SGPR0_SGPR1 %VGPR4 Predecessors according to CFG: BB#0 %VGPR4 = V_ADD_I32_e32 %SGPR12, %VGPR4, %EXEC, %VCC %VGPR4 = V_LSHLREV_B32_e32 2, %VGPR4, %EXEC %SGPR2 = S_LSHL_B32 %SGPR13, 2 %VGPR4 = V_ADD_I32_e32 %SGPR2, %VGPR4, %EXEC, %VCC %SGPR4_SGPR5_SGPR6_SGPR7 = S_LOAD_DWORDX4_IMM %SGPR8_SGPR9, 0; mem:LD16[%27](align=8)(tbaa=!"const") S_WAITCNT 127 TBUFFER_STORE_FORMAT_X %VGPR0, 0, -1, 0, -1, 0, 4, 4, %VGPR4, %SGPR4_SGPR5_SGPR6_SGPR7, -1, 0, 0, %EXEC S_WAITCNT 1792 Successors according to CFG: BB#2 BB#2: derived from LLVM BB %endif-block Live Ins: %VGPR0_VGPR1_VGPR2_VGPR3 %SGPR0_SGPR1 Predecessors according to CFG: BB#0 BB#1 %EXEC = S_OR_B64 %EXEC, %SGPR0_SGPR1 EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR1, %VGPR2, %VGPR3, %EXEC, %VGPR0_VGPR1_VGPR2_VGPR3 S_ENDPGM # End machine code for function main. Shader Disassembly: S_LOAD_DWORDX4 s[0:3], s[6:7], 0 ; C0800700 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[0:3], s[0:3][v0] + 0 ; E00C2000 80000000 S_LSHR_B32 s0, s11, 16 ; 9000900B V_MOV_B32_e32 v4, 127 ; 7E0802FF 0000007F V_AND_B32_e32 v5, s0, v4 ; 360A0800 V_MBCNT_LO_U32_B32_e64 v4, -1, 0, 0, 0, 0, 0 ; D2460004 020100C1 V_MBCNT_HI_U32_B32_e32 v4, -1, v4 ; 480808C1 V_CMP_LT_U32_e64 s[0:1], v4, v5, 0, 0, 0, 0 ; D1820000 02020B04 S_WAITCNT vmcnt(0) ; BF8C0770 S_AND_SAVEEXEC_B64 s[0:1], s[0:1] ; BE802400 S_XOR_B64 s[0:1], exec, s[0:1] ; 8980007E V_ADD_I32_e32 v4, s12, v4 ; 4A08080C V_LSHLREV_B32_e32 v4, 2, v4 ; 34080882 S_LSHL_B32 s2, s13, 2 ; 8F02820D V_ADD_I32_e32 v4, s2, v4 ; 4A080802 S_LOAD_DWORDX4 s[4:7], s[8:9], 0 ; C0820900 S_WAITCNT lgkmcnt(0) ; BF8C007F TBUFFER_STORE_FORMAT_X v0, 0, -1, 0, -1, 0, 4, 4, v4, s[4:7], -1, 0, 0 ; EA245000 80410004 S_WAITCNT vmcnt(0) expcnt(0) ; BF8C0700 S_OR_B64 exec, exec, s[0:1] ; 88FE007E EXP 15, 12, 0, 1, 0, v0, v1, v2, v3 ; F80008CF 03020100 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[0], CONSTANT 0: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } # Machine code for function main: Post SSA, not tracking liveness BB#0: derived from LLVM BB %main_body %VGPR0 = V_MOV_B32_e32 0, %EXEC EXP 0, 0, 0, 1, 1, %VGPR0, %VGPR0, %VGPR0, %VGPR0, %EXEC S_ENDPGM # End machine code for function main. Shader Disassembly: V_MOV_B32_e32 v0, 0 ; 7E000280 EXP 0, 0, 0, 1, 1, v0, v0, v0, v0 ; F8001800 00000000 S_ENDPGM ; BF810000 Installing breakpad exception handler for appid(steam)/version(1383158641_client) Installing breakpad exception handler for appid(steam)/version(1383158641_client) Installing breakpad exception handler for appid(steam)/version(1383158641_client) Installing breakpad exception handler for appid(steam)/version(1383158641_client) FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], COLOR, COLOR DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %21 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %4, <2 x i32> %6) %22 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %4, <2 x i32> %6) %23 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %4, <2 x i32> %6) %24 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %4, <2 x i32> %6) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %21, float %22, float %23, float %24) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } # Machine code for function main: Post SSA, not tracking liveness Function Live Ins: %SGPR7 in %vreg4, %VGPR0 in %vreg5, %VGPR1 in %vreg6 BB#0: derived from LLVM BB %main_body Live Ins: %SGPR7 %VGPR0 %VGPR1 %EXEC = S_WQM_B64 %EXEC %VGPR1 = KILL %VGPR1, %VGPR0_VGPR1 %VGPR0 = KILL %VGPR0, %VGPR0_VGPR1, %VGPR0_VGPR1 %M0 = S_MOV_B32 %SGPR7 %VGPR2 = V_INTERP_P1_F32 %VGPR0, 3, 0, %M0, %EXEC %VGPR2 = V_INTERP_P2_F32 %VGPR2, %VGPR1, 3, 0, %M0, %EXEC %VGPR3 = V_INTERP_P1_F32 %VGPR0, 2, 0, %M0, %EXEC %VGPR3 = V_INTERP_P2_F32 %VGPR3, %VGPR1, 2, 0, %M0, %EXEC %VGPR4 = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0, %EXEC %VGPR4 = V_INTERP_P2_F32 %VGPR4, %VGPR1, 1, 0, %M0, %EXEC %VGPR5 = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0, %EXEC %VGPR5 = V_INTERP_P2_F32 %VGPR5, %VGPR1, 0, 0, %M0, %EXEC, %VGPR0_VGPR1 EXP 15, 0, 0, 1, 1, %VGPR5, %VGPR4, %VGPR3, %VGPR2, %EXEC S_ENDPGM # End machine code for function main. Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s7 ; BEFC0307 V_INTERP_P1_F32 v2, v0, 3, 0, [m0] ; C8080300 V_INTERP_P2_F32 v2, [v2], v1, 3, 0, [m0] ; C8090301 V_INTERP_P1_F32 v3, v0, 2, 0, [m0] ; C80C0200 V_INTERP_P2_F32 v3, [v3], v1, 2, 0, [m0] ; C80D0201 V_INTERP_P1_F32 v4, v0, 1, 0, [m0] ; C8100100 V_INTERP_P2_F32 v4, [v4], v1, 1, 0, [m0] ; C8110101 V_INTERP_P1_F32 v5, v0, 0, 0, [m0] ; C8140000 V_INTERP_P2_F32 v5, [v5], v1, 0, 0, [m0] ; C8150001 EXP 15, 0, 0, 1, 1, v5, v4, v3, v2 ; F800180F 02030405 S_ENDPGM ; BF810000 VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], COLOR DCL CONST[0..3] DCL TEMP[0] 0: MUL TEMP[0], IN[0].xxxx, CONST[0] 1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0] 2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0] 3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0] 4: MOV_SAT OUT[1], IN[1] 5: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0 %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0 %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0) %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4) %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8) %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12) %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16) %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20) %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24) %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28) %20 = call float @llvm.SI.load.const(<16 x i8> %11, i32 32) %21 = call float @llvm.SI.load.const(<16 x i8> %11, i32 36) %22 = call float @llvm.SI.load.const(<16 x i8> %11, i32 40) %23 = call float @llvm.SI.load.const(<16 x i8> %11, i32 44) %24 = call float @llvm.SI.load.const(<16 x i8> %11, i32 48) %25 = call float @llvm.SI.load.const(<16 x i8> %11, i32 52) %26 = call float @llvm.SI.load.const(<16 x i8> %11, i32 56) %27 = call float @llvm.SI.load.const(<16 x i8> %11, i32 60) %28 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0 %29 = load <16 x i8> addrspace(2)* %28, !tbaa !0 %30 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %29, i32 0, i32 %6) %31 = extractelement <4 x float> %30, i32 0 %32 = extractelement <4 x float> %30, i32 1 %33 = extractelement <4 x float> %30, i32 2 %34 = extractelement <4 x float> %30, i32 3 %35 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 1 %36 = load <16 x i8> addrspace(2)* %35, !tbaa !0 %37 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %36, i32 0, i32 %6) %38 = extractelement <4 x float> %37, i32 0 %39 = extractelement <4 x float> %37, i32 1 %40 = extractelement <4 x float> %37, i32 2 %41 = extractelement <4 x float> %37, i32 3 %42 = fmul float %31, %12 %43 = fmul float %31, %13 %44 = fmul float %31, %14 %45 = fmul float %31, %15 %46 = fmul float %32, %16 %47 = fadd float %46, %42 %48 = fmul float %32, %17 %49 = fadd float %48, %43 %50 = fmul float %32, %18 %51 = fadd float %50, %44 %52 = fmul float %32, %19 %53 = fadd float %52, %45 %54 = fmul float %33, %20 %55 = fadd float %54, %47 %56 = fmul float %33, %21 %57 = fadd float %56, %49 %58 = fmul float %33, %22 %59 = fadd float %58, %51 %60 = fmul float %33, %23 %61 = fadd float %60, %53 %62 = fmul float %34, %24 %63 = fadd float %62, %55 %64 = fmul float %34, %25 %65 = fadd float %64, %57 %66 = fmul float %34, %26 %67 = fadd float %66, %59 %68 = fmul float %34, %27 %69 = fadd float %68, %61 %70 = call float @llvm.AMDIL.clamp.(float %38, float 0.000000e+00, float 1.000000e+00) %71 = call float @llvm.AMDIL.clamp.(float %39, float 0.000000e+00, float 1.000000e+00) %72 = call float @llvm.AMDIL.clamp.(float %40, float 0.000000e+00, float 1.000000e+00) %73 = call float @llvm.AMDIL.clamp.(float %41, float 0.000000e+00, float 1.000000e+00) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %70, float %71, float %72, float %73) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %63, float %65, float %67, float %69) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 ; Function Attrs: readnone declare float @llvm.AMDIL.clamp.(float, float, float) #2 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } !0 = metadata !{metadata !"const", null, i32 1} # Machine code for function main: Post SSA, not tracking liveness Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg6 BB#0: derived from LLVM BB %main_body Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0 %SGPR8_SGPR9_SGPR10_SGPR11 = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%40](align=8)(tbaa=!"const") S_WAITCNT 127 %VGPR1_VGPR2_VGPR3_VGPR4 = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR0, 0, %EXEC S_WAITCNT 1904 %VGPR5 = V_ADD_F32_e64 0, %VGPR4, 0, 1, 0, 0, %EXEC %VGPR6 = V_ADD_F32_e64 0, %VGPR3, 0, 1, 0, 0, %EXEC %VGPR7 = V_ADD_F32_e64 0, %VGPR2, 0, 1, 0, 0, %EXEC %VGPR1 = V_ADD_F32_e64 0, %VGPR1, 0, 1, 0, 0, %EXEC, %VGPR1_VGPR2_VGPR3_VGPR4 EXP 15, 32, 0, 0, 0, %VGPR1, %VGPR7, %VGPR6, %VGPR5, %EXEC %SGPR4_SGPR5_SGPR6_SGPR7 = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 0; mem:LD16[%31](align=8)(tbaa=!"const") S_WAITCNT 15 %VGPR0_VGPR1_VGPR2_VGPR3 = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7, %VGPR0, 0, %EXEC %SGPR0_SGPR1_SGPR2_SGPR3 = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1, 0; mem:LD16[%11](align=8)(tbaa=!"const") S_WAITCNT 112 %SGPR4 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 3; mem:LD4[] S_WAITCNT 127 %VGPR4 = V_MOV_B32_e32 %SGPR4, %EXEC %VGPR4 = V_MUL_F32_e64 %VGPR0, %VGPR4, 0, 0, 0, 0, %EXEC %SGPR4 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 7; mem:LD4[] S_WAITCNT 127 %VGPR5 = V_MOV_B32_e32 %SGPR4, %EXEC %VGPR4 = V_MAD_F32 %VGPR1, %VGPR5, %VGPR4, 0, 0, 0, 0, %EXEC %SGPR4 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 11; mem:LD4[] S_WAITCNT 127 %VGPR5 = V_MOV_B32_e32 %SGPR4, %EXEC %VGPR4 = V_MAD_F32 %VGPR2, %VGPR5, %VGPR4, 0, 0, 0, 0, %EXEC %SGPR4 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 15; mem:LD4[] S_WAITCNT 127 %VGPR5 = V_MOV_B32_e32 %SGPR4, %EXEC %VGPR4 = V_MAD_F32 %VGPR3, %VGPR5, %VGPR4, 0, 0, 0, 0, %EXEC %SGPR4 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2; mem:LD4[] S_WAITCNT 127 %VGPR5 = V_MOV_B32_e32 %SGPR4, %EXEC %VGPR5 = V_MUL_F32_e64 %VGPR0, %VGPR5, 0, 0, 0, 0, %EXEC %SGPR4 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 6; mem:LD4[] S_WAITCNT 127 %VGPR6 = V_MOV_B32_e32 %SGPR4, %EXEC %VGPR5 = V_MAD_F32 %VGPR1, %VGPR6, %VGPR5, 0, 0, 0, 0, %EXEC %SGPR4 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 10; mem:LD4[] S_WAITCNT 127 %VGPR6 = V_MOV_B32_e32 %SGPR4, %EXEC %VGPR5 = V_MAD_F32 %VGPR2, %VGPR6, %VGPR5, 0, 0, 0, 0, %EXEC %SGPR4 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 14; mem:LD4[] S_WAITCNT 127 %VGPR6 = V_MOV_B32_e32 %SGPR4, %EXEC %VGPR5 = V_MAD_F32 %VGPR3, %VGPR6, %VGPR5, 0, 0, 0, 0, %EXEC %SGPR4 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1; mem:LD4[] S_WAITCNT 127 %VGPR6 = V_MOV_B32_e32 %SGPR4, %EXEC %VGPR6 = V_MUL_F32_e64 %VGPR0, %VGPR6, 0, 0, 0, 0, %EXEC %SGPR4 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 5; mem:LD4[] S_WAITCNT 127 %VGPR7 = V_MOV_B32_e32 %SGPR4, %EXEC %VGPR6 = V_MAD_F32 %VGPR1, %VGPR7, %VGPR6, 0, 0, 0, 0, %EXEC %SGPR4 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 9; mem:LD4[] S_WAITCNT 127 %VGPR7 = V_MOV_B32_e32 %SGPR4, %EXEC %VGPR6 = V_MAD_F32 %VGPR2, %VGPR7, %VGPR6, 0, 0, 0, 0, %EXEC %SGPR4 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 13; mem:LD4[] S_WAITCNT 127 %VGPR7 = V_MOV_B32_e32 %SGPR4, %EXEC %VGPR6 = V_MAD_F32 %VGPR3, %VGPR7, %VGPR6, 0, 0, 0, 0, %EXEC %SGPR4 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 0; mem:LD4[] S_WAITCNT 127 %VGPR7 = V_MOV_B32_e32 %SGPR4, %EXEC %VGPR7 = V_MUL_F32_e64 %VGPR0, %VGPR7, 0, 0, 0, 0, %EXEC %SGPR4 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 4; mem:LD4[] S_WAITCNT 127 %VGPR8 = V_MOV_B32_e32 %SGPR4, %EXEC %VGPR7 = V_MAD_F32 %VGPR1, %VGPR8, %VGPR7, 0, 0, 0, 0, %EXEC %SGPR4 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 8; mem:LD4[] S_WAITCNT 127 %VGPR8 = V_MOV_B32_e32 %SGPR4, %EXEC %VGPR7 = V_MAD_F32 %VGPR2, %VGPR8, %VGPR7, 0, 0, 0, 0, %EXEC %SGPR0 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 12; mem:LD4[] S_WAITCNT 127 %VGPR8 = V_MOV_B32_e32 %SGPR0, %EXEC %VGPR0 = V_MAD_F32 %VGPR3, %VGPR8, %VGPR7, 0, 0, 0, 0, %EXEC, %VGPR0_VGPR1_VGPR2_VGPR3 EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR6, %VGPR5, %VGPR4, %EXEC S_ENDPGM # End machine code for function main. Shader Disassembly: S_LOAD_DWORDX4 s[8:11], s[6:7], 4 ; C0840704 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[1:4], s[8:11][v0] + 0 ; E00C2000 80020100 S_WAITCNT vmcnt(0) ; BF8C0770 V_ADD_F32_e64 v5, 0, v4, 0, 1, 0, 0 ; D2060805 02020880 V_ADD_F32_e64 v6, 0, v3, 0, 1, 0, 0 ; D2060806 02020680 V_ADD_F32_e64 v7, 0, v2, 0, 1, 0, 0 ; D2060807 02020480 V_ADD_F32_e64 v1, 0, v1, 0, 1, 0, 0 ; D2060801 02020280 EXP 15, 32, 0, 0, 0, v1, v7, v6, v5 ; F800020F 05060701 S_LOAD_DWORDX4 s[4:7], s[6:7], 0 ; C0820700 S_WAITCNT expcnt(0) lgkmcnt(0) ; BF8C000F BUFFER_LOAD_FORMAT_XYZW v[0:3], s[4:7][v0] + 0 ; E00C2000 80010000 S_LOAD_DWORDX4 s[0:3], s[0:1], 0 ; C0800100 S_WAITCNT vmcnt(0) lgkmcnt(0) ; BF8C0070 S_BUFFER_LOAD_DWORD s4, s[0:3], 3 ; C2020103 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v4, s4 ; 7E080204 V_MUL_F32_e64 v4, v0, v4, 0, 0, 0, 0 ; D2100004 02020900 S_BUFFER_LOAD_DWORD s4, s[0:3], 7 ; C2020107 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v5, s4 ; 7E0A0204 V_MAD_F32 v4, v1, v5, v4, 0, 0, 0, 0 ; D2820004 04120B01 S_BUFFER_LOAD_DWORD s4, s[0:3], 11 ; C202010B S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v5, s4 ; 7E0A0204 V_MAD_F32 v4, v2, v5, v4, 0, 0, 0, 0 ; D2820004 04120B02 S_BUFFER_LOAD_DWORD s4, s[0:3], 15 ; C202010F S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v5, s4 ; 7E0A0204 V_MAD_F32 v4, v3, v5, v4, 0, 0, 0, 0 ; D2820004 04120B03 S_BUFFER_LOAD_DWORD s4, s[0:3], 2 ; C2020102 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v5, s4 ; 7E0A0204 V_MUL_F32_e64 v5, v0, v5, 0, 0, 0, 0 ; D2100005 02020B00 S_BUFFER_LOAD_DWORD s4, s[0:3], 6 ; C2020106 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v6, s4 ; 7E0C0204 V_MAD_F32 v5, v1, v6, v5, 0, 0, 0, 0 ; D2820005 04160D01 S_BUFFER_LOAD_DWORD s4, s[0:3], 10 ; C202010A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v6, s4 ; 7E0C0204 V_MAD_F32 v5, v2, v6, v5, 0, 0, 0, 0 ; D2820005 04160D02 S_BUFFER_LOAD_DWORD s4, s[0:3], 14 ; C202010E S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v6, s4 ; 7E0C0204 V_MAD_F32 v5, v3, v6, v5, 0, 0, 0, 0 ; D2820005 04160D03 S_BUFFER_LOAD_DWORD s4, s[0:3], 1 ; C2020101 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v6, s4 ; 7E0C0204 V_MUL_F32_e64 v6, v0, v6, 0, 0, 0, 0 ; D2100006 02020D00 S_BUFFER_LOAD_DWORD s4, s[0:3], 5 ; C2020105 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v7, s4 ; 7E0E0204 V_MAD_F32 v6, v1, v7, v6, 0, 0, 0, 0 ; D2820006 041A0F01 S_BUFFER_LOAD_DWORD s4, s[0:3], 9 ; C2020109 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v7, s4 ; 7E0E0204 V_MAD_F32 v6, v2, v7, v6, 0, 0, 0, 0 ; D2820006 041A0F02 S_BUFFER_LOAD_DWORD s4, s[0:3], 13 ; C202010D S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v7, s4 ; 7E0E0204 V_MAD_F32 v6, v3, v7, v6, 0, 0, 0, 0 ; D2820006 041A0F03 S_BUFFER_LOAD_DWORD s4, s[0:3], 0 ; C2020100 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v7, s4 ; 7E0E0204 V_MUL_F32_e64 v7, v0, v7, 0, 0, 0, 0 ; D2100007 02020F00 S_BUFFER_LOAD_DWORD s4, s[0:3], 4 ; C2020104 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v8, s4 ; 7E100204 V_MAD_F32 v7, v1, v8, v7, 0, 0, 0, 0 ; D2820007 041E1101 S_BUFFER_LOAD_DWORD s4, s[0:3], 8 ; C2020108 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v8, s4 ; 7E100204 V_MAD_F32 v7, v2, v8, v7, 0, 0, 0, 0 ; D2820007 041E1102 S_BUFFER_LOAD_DWORD s0, s[0:3], 12 ; C200010C S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v8, s0 ; 7E100200 V_MAD_F32 v0, v3, v8, v7, 0, 0, 0, 0 ; D2820000 041E1103 EXP 15, 12, 0, 1, 0, v0, v6, v5, v4 ; F80008CF 04050600 S_ENDPGM ; BF810000 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %21 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %4) %22 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %4) %23 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %4) %24 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %4) %25 = call i32 @llvm.SI.packf16(float %21, float %22) %26 = bitcast i32 %25 to float %27 = call i32 @llvm.SI.packf16(float %23, float %24) %28 = bitcast i32 %27 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %26, float %28, float %26, float %28) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } # Machine code for function main: Post SSA, not tracking liveness Function Live Ins: %SGPR7 in %vreg4 BB#0: derived from LLVM BB %main_body Live Ins: %SGPR7 %EXEC = S_WQM_B64 %EXEC %M0 = S_MOV_B32 %SGPR7 %VGPR0 = V_INTERP_MOV_F32 2, 3, 0, %M0, %EXEC %VGPR1 = V_INTERP_MOV_F32 2, 2, 0, %M0, %EXEC %VGPR0 = V_CVT_PKRTZ_F16_F32_e32 %VGPR1, %VGPR0, %EXEC %VGPR1 = V_INTERP_MOV_F32 2, 1, 0, %M0, %EXEC %VGPR2 = V_INTERP_MOV_F32 2, 0, 0, %M0, %EXEC %VGPR1 = V_CVT_PKRTZ_F16_F32_e32 %VGPR2, %VGPR1, %EXEC EXP 15, 0, 1, 1, 1, %VGPR1, %VGPR0, %VGPR1, %VGPR0, %EXEC S_ENDPGM # End machine code for function main. Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s7 ; BEFC0307 V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302 V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202 V_CVT_PKRTZ_F16_F32_e32 v0, v1, v0 ; 5E000101 V_INTERP_MOV_F32 v1, P0, 1, 0, [m0] ; C8060102 V_INTERP_MOV_F32 v2, P0, 0, 0, [m0] ; C80A0002 V_CVT_PKRTZ_F16_F32_e32 v1, v2, v1 ; 5E020302 EXP 15, 0, 1, 1, 1, v1, v0, v1, v0 ; F8001C0F 00010001 S_ENDPGM ; BF810000 Installing breakpad exception handler for appid(steam)/version(1383158641_client) FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL CONST[1..4] DCL TEMP[0], LOCAL 0: MOV TEMP[0].xy, IN[0].xyyy 1: MOV TEMP[0].w, IN[0].wwww 2: TXP TEMP[0], TEMP[0], SAMP[0], 2D 3: MUL TEMP[0], TEMP[0], CONST[4] 4: MOV OUT[0], TEMP[0] 5: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %21 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0 %22 = load <16 x i8> addrspace(2)* %21, !tbaa !0 %23 = call float @llvm.SI.load.const(<16 x i8> %22, i32 64) %24 = call float @llvm.SI.load.const(<16 x i8> %22, i32 68) %25 = call float @llvm.SI.load.const(<16 x i8> %22, i32 72) %26 = call float @llvm.SI.load.const(<16 x i8> %22, i32 76) %27 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0 %28 = load <32 x i8> addrspace(2)* %27, !tbaa !0 %29 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0 %30 = load <16 x i8> addrspace(2)* %29, !tbaa !0 %31 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %4, <2 x i32> %6) %32 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %4, <2 x i32> %6) %33 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %4, <2 x i32> %6) %34 = fdiv float %31, %33 %35 = fdiv float %32, %33 %36 = bitcast float %34 to i32 %37 = bitcast float %35 to i32 %38 = insertelement <2 x i32> undef, i32 %36, i32 0 %39 = insertelement <2 x i32> %38, i32 %37, i32 1 %40 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %39, <32 x i8> %28, <16 x i8> %30, i32 2) %41 = extractelement <4 x float> %40, i32 0 %42 = extractelement <4 x float> %40, i32 1 %43 = extractelement <4 x float> %40, i32 2 %44 = extractelement <4 x float> %40, i32 3 %45 = fmul float %41, %23 %46 = fmul float %42, %24 %47 = fmul float %43, %25 %48 = fmul float %44, %26 %49 = call i32 @llvm.SI.packf16(float %45, float %46) %50 = bitcast i32 %49 to float %51 = call i32 @llvm.SI.packf16(float %47, float %48) %52 = bitcast i32 %51 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %50, float %52, float %50, float %52) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} # Machine code for function main: Post SSA, not tracking liveness Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR7 in %vreg4, %VGPR0 in %vreg5, %VGPR1 in %vreg6 BB#0: derived from LLVM BB %main_body Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR7 %VGPR0 %VGPR1 %EXEC = S_WQM_B64 %EXEC %VGPR1 = KILL %VGPR1, %VGPR0_VGPR1 %VGPR0 = KILL %VGPR0, %VGPR0_VGPR1, %VGPR0_VGPR1 %M0 = S_MOV_B32 %SGPR7 %VGPR2 = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0, %EXEC %VGPR2 = V_INTERP_P2_F32 %VGPR2, %VGPR1, 1, 0, %M0, %EXEC %VGPR3 = V_INTERP_P1_F32 %VGPR0, 3, 0, %M0, %EXEC %VGPR3 = V_INTERP_P2_F32 %VGPR3, %VGPR1, 3, 0, %M0, %EXEC %VGPR3 = V_RCP_F32_e32 %VGPR3, %EXEC %VGPR5 = V_MUL_F32_e32 %VGPR2, %VGPR3, %EXEC, %VGPR4_VGPR5 %VGPR2 = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0, %EXEC %VGPR2 = V_INTERP_P2_F32 %VGPR2, %VGPR1, 0, 0, %M0, %EXEC, %VGPR0_VGPR1 %VGPR4 = V_MUL_F32_e32 %VGPR2, %VGPR3, %EXEC, %VGPR4_VGPR5, %VGPR4_VGPR5 %SGPR8_SGPR9_SGPR10_SGPR11 = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 0; mem:LD16[%32](align=8)(tbaa=!"const") %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 0; mem:LD32[%29](tbaa=!"const") S_WAITCNT 127 %VGPR0_VGPR1_VGPR2_VGPR3 = IMAGE_SAMPLE_V4_V2 15, 0, 0, 0, 0, 0, 0, 0, %VGPR4_VGPR5, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC %SGPR0_SGPR1_SGPR2_SGPR3 = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1, 0; mem:LD16[%22](align=8)(tbaa=!"const") S_WAITCNT 112 %SGPR4 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 19; mem:LD4[] S_WAITCNT 127 %VGPR4 = V_MOV_B32_e32 %SGPR4, %EXEC %VGPR4 = V_MUL_F32_e64 %VGPR3, %VGPR4, 0, 0, 0, 0, %EXEC %SGPR4 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 18; mem:LD4[] S_WAITCNT 127 %VGPR5 = V_MOV_B32_e32 %SGPR4, %EXEC %VGPR5 = V_MUL_F32_e64 %VGPR2, %VGPR5, 0, 0, 0, 0, %EXEC %VGPR4 = V_CVT_PKRTZ_F16_F32_e32 %VGPR5, %VGPR4, %EXEC %SGPR4 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 17; mem:LD4[] S_WAITCNT 127 %VGPR5 = V_MOV_B32_e32 %SGPR4, %EXEC %VGPR5 = V_MUL_F32_e64 %VGPR1, %VGPR5, 0, 0, 0, 0, %EXEC %SGPR0 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 16; mem:LD4[] S_WAITCNT 127 %VGPR6 = V_MOV_B32_e32 %SGPR0, %EXEC %VGPR0 = V_MUL_F32_e64 %VGPR0, %VGPR6, 0, 0, 0, 0, %EXEC, %VGPR0_VGPR1_VGPR2_VGPR3 %VGPR0 = V_CVT_PKRTZ_F16_F32_e32 %VGPR0, %VGPR5, %EXEC EXP 15, 0, 1, 1, 1, %VGPR0, %VGPR4, %VGPR0, %VGPR4, %EXEC S_ENDPGM # End machine code for function main. Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s7 ; BEFC0307 V_INTERP_P1_F32 v2, v0, 1, 0, [m0] ; C8080100 V_INTERP_P2_F32 v2, [v2], v1, 1, 0, [m0] ; C8090101 V_INTERP_P1_F32 v3, v0, 3, 0, [m0] ; C80C0300 V_INTERP_P2_F32 v3, [v3], v1, 3, 0, [m0] ; C80D0301 V_RCP_F32_e32 v3, v3 ; 7E065503 V_MUL_F32_e32 v5, v2, v3 ; 100A0702 V_INTERP_P1_F32 v2, v0, 0, 0, [m0] ; C8080000 V_INTERP_P2_F32 v2, [v2], v1, 0, 0, [m0] ; C8090001 V_MUL_F32_e32 v4, v2, v3 ; 10080702 S_LOAD_DWORDX4 s[8:11], s[2:3], 0 ; C0840300 S_LOAD_DWORDX8 s[12:19], s[4:5], 0 ; C0C60500 S_WAITCNT lgkmcnt(0) ; BF8C007F IMAGE_SAMPLE v[0:3], 15, 0, 0, 0, 0, 0, 0, 0, v[4:5], s[12:19], s[8:11] ; F0800F00 00430004 S_LOAD_DWORDX4 s[0:3], s[0:1], 0 ; C0800100 S_WAITCNT vmcnt(0) lgkmcnt(0) ; BF8C0070 S_BUFFER_LOAD_DWORD s4, s[0:3], 19 ; C2020113 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v4, s4 ; 7E080204 V_MUL_F32_e64 v4, v3, v4, 0, 0, 0, 0 ; D2100004 02020903 S_BUFFER_LOAD_DWORD s4, s[0:3], 18 ; C2020112 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v5, s4 ; 7E0A0204 V_MUL_F32_e64 v5, v2, v5, 0, 0, 0, 0 ; D2100005 02020B02 V_CVT_PKRTZ_F16_F32_e32 v4, v5, v4 ; 5E080905 S_BUFFER_LOAD_DWORD s4, s[0:3], 17 ; C2020111 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v5, s4 ; 7E0A0204 V_MUL_F32_e64 v5, v1, v5, 0, 0, 0, 0 ; D2100005 02020B01 S_BUFFER_LOAD_DWORD s0, s[0:3], 16 ; C2000110 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v6, s0 ; 7E0C0200 V_MUL_F32_e64 v0, v0, v6, 0, 0, 0, 0 ; D2100000 02020D00 V_CVT_PKRTZ_F16_F32_e32 v0, v0, v5 ; 5E000B00 EXP 15, 0, 1, 1, 1, v0, v4, v0, v4 ; F8001C0F 04000400 S_ENDPGM ; BF810000 VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] DCL CONST[0..3] DCL TEMP[0] 0: MUL TEMP[0], IN[0].xxxx, CONST[0] 1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0] 2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0] 3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0] 4: MOV OUT[1], IN[1] 5: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0 %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0 %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0) %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4) %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8) %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12) %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16) %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20) %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24) %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28) %20 = call float @llvm.SI.load.const(<16 x i8> %11, i32 32) %21 = call float @llvm.SI.load.const(<16 x i8> %11, i32 36) %22 = call float @llvm.SI.load.const(<16 x i8> %11, i32 40) %23 = call float @llvm.SI.load.const(<16 x i8> %11, i32 44) %24 = call float @llvm.SI.load.const(<16 x i8> %11, i32 48) %25 = call float @llvm.SI.load.const(<16 x i8> %11, i32 52) %26 = call float @llvm.SI.load.const(<16 x i8> %11, i32 56) %27 = call float @llvm.SI.load.const(<16 x i8> %11, i32 60) %28 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0 %29 = load <16 x i8> addrspace(2)* %28, !tbaa !0 %30 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %29, i32 0, i32 %6) %31 = extractelement <4 x float> %30, i32 0 %32 = extractelement <4 x float> %30, i32 1 %33 = extractelement <4 x float> %30, i32 2 %34 = extractelement <4 x float> %30, i32 3 %35 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 1 %36 = load <16 x i8> addrspace(2)* %35, !tbaa !0 %37 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %36, i32 0, i32 %6) %38 = extractelement <4 x float> %37, i32 0 %39 = extractelement <4 x float> %37, i32 1 %40 = extractelement <4 x float> %37, i32 2 %41 = extractelement <4 x float> %37, i32 3 %42 = fmul float %31, %12 %43 = fmul float %31, %13 %44 = fmul float %31, %14 %45 = fmul float %31, %15 %46 = fmul float %32, %16 %47 = fadd float %46, %42 %48 = fmul float %32, %17 %49 = fadd float %48, %43 %50 = fmul float %32, %18 %51 = fadd float %50, %44 %52 = fmul float %32, %19 %53 = fadd float %52, %45 %54 = fmul float %33, %20 %55 = fadd float %54, %47 %56 = fmul float %33, %21 %57 = fadd float %56, %49 %58 = fmul float %33, %22 %59 = fadd float %58, %51 %60 = fmul float %33, %23 %61 = fadd float %60, %53 %62 = fmul float %34, %24 %63 = fadd float %62, %55 %64 = fmul float %34, %25 %65 = fadd float %64, %57 %66 = fmul float %34, %26 %67 = fadd float %66, %59 %68 = fmul float %34, %27 %69 = fadd float %68, %61 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %38, float %39, float %40, float %41) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %63, float %65, float %67, float %69) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} # Machine code for function main: Post SSA, not tracking liveness Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg6 BB#0: derived from LLVM BB %main_body Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0 %SGPR8_SGPR9_SGPR10_SGPR11 = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%40](align=8)(tbaa=!"const") S_WAITCNT 127 %VGPR1_VGPR2_VGPR3_VGPR4 = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR0, 0, %EXEC S_WAITCNT 1904 EXP 15, 32, 0, 0, 0, %VGPR1, %VGPR2, %VGPR3, %VGPR4, %EXEC, %VGPR1_VGPR2_VGPR3_VGPR4 %SGPR4_SGPR5_SGPR6_SGPR7 = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 0; mem:LD16[%31](align=8)(tbaa=!"const") S_WAITCNT 15 %VGPR0_VGPR1_VGPR2_VGPR3 = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7, %VGPR0, 0, %EXEC %SGPR0_SGPR1_SGPR2_SGPR3 = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1, 0; mem:LD16[%11](align=8)(tbaa=!"const") S_WAITCNT 112 %SGPR4 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 3; mem:LD4[] S_WAITCNT 127 %VGPR4 = V_MOV_B32_e32 %SGPR4, %EXEC %VGPR4 = V_MUL_F32_e64 %VGPR0, %VGPR4, 0, 0, 0, 0, %EXEC %SGPR4 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 7; mem:LD4[] S_WAITCNT 127 %VGPR5 = V_MOV_B32_e32 %SGPR4, %EXEC %VGPR4 = V_MAD_F32 %VGPR1, %VGPR5, %VGPR4, 0, 0, 0, 0, %EXEC %SGPR4 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 11; mem:LD4[] S_WAITCNT 127 %VGPR5 = V_MOV_B32_e32 %SGPR4, %EXEC %VGPR4 = V_MAD_F32 %VGPR2, %VGPR5, %VGPR4, 0, 0, 0, 0, %EXEC %SGPR4 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 15; mem:LD4[] S_WAITCNT 127 %VGPR5 = V_MOV_B32_e32 %SGPR4, %EXEC %VGPR4 = V_MAD_F32 %VGPR3, %VGPR5, %VGPR4, 0, 0, 0, 0, %EXEC %SGPR4 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2; mem:LD4[] S_WAITCNT 127 %VGPR5 = V_MOV_B32_e32 %SGPR4, %EXEC %VGPR5 = V_MUL_F32_e64 %VGPR0, %VGPR5, 0, 0, 0, 0, %EXEC %SGPR4 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 6; mem:LD4[] S_WAITCNT 127 %VGPR6 = V_MOV_B32_e32 %SGPR4, %EXEC %VGPR5 = V_MAD_F32 %VGPR1, %VGPR6, %VGPR5, 0, 0, 0, 0, %EXEC %SGPR4 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 10; mem:LD4[] S_WAITCNT 127 %VGPR6 = V_MOV_B32_e32 %SGPR4, %EXEC %VGPR5 = V_MAD_F32 %VGPR2, %VGPR6, %VGPR5, 0, 0, 0, 0, %EXEC %SGPR4 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 14; mem:LD4[] S_WAITCNT 127 %VGPR6 = V_MOV_B32_e32 %SGPR4, %EXEC %VGPR5 = V_MAD_F32 %VGPR3, %VGPR6, %VGPR5, 0, 0, 0, 0, %EXEC %SGPR4 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1; mem:LD4[] S_WAITCNT 127 %VGPR6 = V_MOV_B32_e32 %SGPR4, %EXEC %VGPR6 = V_MUL_F32_e64 %VGPR0, %VGPR6, 0, 0, 0, 0, %EXEC %SGPR4 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 5; mem:LD4[] S_WAITCNT 127 %VGPR7 = V_MOV_B32_e32 %SGPR4, %EXEC %VGPR6 = V_MAD_F32 %VGPR1, %VGPR7, %VGPR6, 0, 0, 0, 0, %EXEC %SGPR4 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 9; mem:LD4[] S_WAITCNT 127 %VGPR7 = V_MOV_B32_e32 %SGPR4, %EXEC %VGPR6 = V_MAD_F32 %VGPR2, %VGPR7, %VGPR6, 0, 0, 0, 0, %EXEC %SGPR4 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 13; mem:LD4[] S_WAITCNT 127 %VGPR7 = V_MOV_B32_e32 %SGPR4, %EXEC %VGPR6 = V_MAD_F32 %VGPR3, %VGPR7, %VGPR6, 0, 0, 0, 0, %EXEC %SGPR4 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 0; mem:LD4[] S_WAITCNT 127 %VGPR7 = V_MOV_B32_e32 %SGPR4, %EXEC %VGPR7 = V_MUL_F32_e64 %VGPR0, %VGPR7, 0, 0, 0, 0, %EXEC %SGPR4 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 4; mem:LD4[] S_WAITCNT 127 %VGPR8 = V_MOV_B32_e32 %SGPR4, %EXEC %VGPR7 = V_MAD_F32 %VGPR1, %VGPR8, %VGPR7, 0, 0, 0, 0, %EXEC %SGPR4 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 8; mem:LD4[] S_WAITCNT 127 %VGPR8 = V_MOV_B32_e32 %SGPR4, %EXEC %VGPR7 = V_MAD_F32 %VGPR2, %VGPR8, %VGPR7, 0, 0, 0, 0, %EXEC %SGPR0 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 12; mem:LD4[] S_WAITCNT 127 %VGPR8 = V_MOV_B32_e32 %SGPR0, %EXEC %VGPR0 = V_MAD_F32 %VGPR3, %VGPR8, %VGPR7, 0, 0, 0, 0, %EXEC, %VGPR0_VGPR1_VGPR2_VGPR3 EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR6, %VGPR5, %VGPR4, %EXEC S_ENDPGM # End machine code for function main. Shader Disassembly: S_LOAD_DWORDX4 s[8:11], s[6:7], 4 ; C0840704 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[1:4], s[8:11][v0] + 0 ; E00C2000 80020100 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 32, 0, 0, 0, v1, v2, v3, v4 ; F800020F 04030201 S_LOAD_DWORDX4 s[4:7], s[6:7], 0 ; C0820700 S_WAITCNT expcnt(0) lgkmcnt(0) ; BF8C000F BUFFER_LOAD_FORMAT_XYZW v[0:3], s[4:7][v0] + 0 ; E00C2000 80010000 S_LOAD_DWORDX4 s[0:3], s[0:1], 0 ; C0800100 S_WAITCNT vmcnt(0) lgkmcnt(0) ; BF8C0070 S_BUFFER_LOAD_DWORD s4, s[0:3], 3 ; C2020103 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v4, s4 ; 7E080204 V_MUL_F32_e64 v4, v0, v4, 0, 0, 0, 0 ; D2100004 02020900 S_BUFFER_LOAD_DWORD s4, s[0:3], 7 ; C2020107 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v5, s4 ; 7E0A0204 V_MAD_F32 v4, v1, v5, v4, 0, 0, 0, 0 ; D2820004 04120B01 S_BUFFER_LOAD_DWORD s4, s[0:3], 11 ; C202010B S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v5, s4 ; 7E0A0204 V_MAD_F32 v4, v2, v5, v4, 0, 0, 0, 0 ; D2820004 04120B02 S_BUFFER_LOAD_DWORD s4, s[0:3], 15 ; C202010F S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v5, s4 ; 7E0A0204 V_MAD_F32 v4, v3, v5, v4, 0, 0, 0, 0 ; D2820004 04120B03 S_BUFFER_LOAD_DWORD s4, s[0:3], 2 ; C2020102 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v5, s4 ; 7E0A0204 V_MUL_F32_e64 v5, v0, v5, 0, 0, 0, 0 ; D2100005 02020B00 S_BUFFER_LOAD_DWORD s4, s[0:3], 6 ; C2020106 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v6, s4 ; 7E0C0204 V_MAD_F32 v5, v1, v6, v5, 0, 0, 0, 0 ; D2820005 04160D01 S_BUFFER_LOAD_DWORD s4, s[0:3], 10 ; C202010A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v6, s4 ; 7E0C0204 V_MAD_F32 v5, v2, v6, v5, 0, 0, 0, 0 ; D2820005 04160D02 S_BUFFER_LOAD_DWORD s4, s[0:3], 14 ; C202010E S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v6, s4 ; 7E0C0204 V_MAD_F32 v5, v3, v6, v5, 0, 0, 0, 0 ; D2820005 04160D03 S_BUFFER_LOAD_DWORD s4, s[0:3], 1 ; C2020101 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v6, s4 ; 7E0C0204 V_MUL_F32_e64 v6, v0, v6, 0, 0, 0, 0 ; D2100006 02020D00 S_BUFFER_LOAD_DWORD s4, s[0:3], 5 ; C2020105 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v7, s4 ; 7E0E0204 V_MAD_F32 v6, v1, v7, v6, 0, 0, 0, 0 ; D2820006 041A0F01 S_BUFFER_LOAD_DWORD s4, s[0:3], 9 ; C2020109 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v7, s4 ; 7E0E0204 V_MAD_F32 v6, v2, v7, v6, 0, 0, 0, 0 ; D2820006 041A0F02 S_BUFFER_LOAD_DWORD s4, s[0:3], 13 ; C202010D S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v7, s4 ; 7E0E0204 V_MAD_F32 v6, v3, v7, v6, 0, 0, 0, 0 ; D2820006 041A0F03 S_BUFFER_LOAD_DWORD s4, s[0:3], 0 ; C2020100 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v7, s4 ; 7E0E0204 V_MUL_F32_e64 v7, v0, v7, 0, 0, 0, 0 ; D2100007 02020F00 S_BUFFER_LOAD_DWORD s4, s[0:3], 4 ; C2020104 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v8, s4 ; 7E100204 V_MAD_F32 v7, v1, v8, v7, 0, 0, 0, 0 ; D2820007 041E1101 S_BUFFER_LOAD_DWORD s4, s[0:3], 8 ; C2020108 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v8, s4 ; 7E100204 V_MAD_F32 v7, v2, v8, v7, 0, 0, 0, 0 ; D2820007 041E1102 S_BUFFER_LOAD_DWORD s0, s[0:3], 12 ; C200010C S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v8, s0 ; 7E100200 V_MAD_F32 v0, v3, v8, v7, 0, 0, 0, 0 ; D2820000 041E1103 EXP 15, 12, 0, 1, 0, v0, v6, v5, v4 ; F80008CF 04050600 S_ENDPGM ; BF810000 Generating new string page texture 2: 48x256, total string texture memory is 49.15 KB FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], COLOR, COLOR DCL IN[1], GENERIC[0], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL TEMP[0], LOCAL 0: MOV TEMP[0].xy, IN[1].xyyy 1: MOV TEMP[0].w, IN[1].wwww 2: TXP TEMP[0], TEMP[0], SAMP[0], 2D 3: MUL TEMP[0], TEMP[0], IN[0] 4: MOV OUT[0], TEMP[0] 5: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %21 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0 %22 = load <32 x i8> addrspace(2)* %21, !tbaa !0 %23 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0 %24 = load <16 x i8> addrspace(2)* %23, !tbaa !0 %25 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %4, <2 x i32> %6) %26 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %4, <2 x i32> %6) %27 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %4, <2 x i32> %6) %28 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %4, <2 x i32> %6) %29 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %4, <2 x i32> %6) %30 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %4, <2 x i32> %6) %31 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %4, <2 x i32> %6) %32 = fdiv float %29, %31 %33 = fdiv float %30, %31 %34 = bitcast float %32 to i32 %35 = bitcast float %33 to i32 %36 = insertelement <2 x i32> undef, i32 %34, i32 0 %37 = insertelement <2 x i32> %36, i32 %35, i32 1 %38 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %37, <32 x i8> %22, <16 x i8> %24, i32 2) %39 = extractelement <4 x float> %38, i32 0 %40 = extractelement <4 x float> %38, i32 1 %41 = extractelement <4 x float> %38, i32 2 %42 = extractelement <4 x float> %38, i32 3 %43 = fmul float %39, %25 %44 = fmul float %40, %26 %45 = fmul float %41, %27 %46 = fmul float %42, %28 %47 = call i32 @llvm.SI.packf16(float %43, float %44) %48 = bitcast i32 %47 to float %49 = call i32 @llvm.SI.packf16(float %45, float %46) %50 = bitcast i32 %49 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %48, float %50, float %48, float %50) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} # Machine code for function main: Post SSA, not tracking liveness Function Live Ins: %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR7 in %vreg4, %VGPR0 in %vreg5, %VGPR1 in %vreg6 BB#0: derived from LLVM BB %main_body Live Ins: %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR7 %VGPR0 %VGPR1 %EXEC = S_WQM_B64 %EXEC %VGPR1 = KILL %VGPR1, %VGPR0_VGPR1 %VGPR0 = KILL %VGPR0, %VGPR0_VGPR1, %VGPR0_VGPR1 %M0 = S_MOV_B32 %SGPR7 %VGPR2 = V_INTERP_P1_F32 %VGPR0, 1, 1, %M0, %EXEC %VGPR2 = V_INTERP_P2_F32 %VGPR2, %VGPR1, 1, 1, %M0, %EXEC %VGPR3 = V_INTERP_P1_F32 %VGPR0, 3, 1, %M0, %EXEC %VGPR3 = V_INTERP_P2_F32 %VGPR3, %VGPR1, 3, 1, %M0, %EXEC %VGPR3 = V_RCP_F32_e32 %VGPR3, %EXEC %VGPR5 = V_MUL_F32_e32 %VGPR2, %VGPR3, %EXEC, %VGPR4_VGPR5 %VGPR2 = V_INTERP_P1_F32 %VGPR0, 0, 1, %M0, %EXEC %VGPR2 = V_INTERP_P2_F32 %VGPR2, %VGPR1, 0, 1, %M0, %EXEC %VGPR4 = V_MUL_F32_e32 %VGPR2, %VGPR3, %EXEC, %VGPR4_VGPR5, %VGPR4_VGPR5 %SGPR0_SGPR1_SGPR2_SGPR3 = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 0; mem:LD16[%24](align=8)(tbaa=!"const") %SGPR8_SGPR9_SGPR10_SGPR11_SGPR12_SGPR13_SGPR14_SGPR15 = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 0; mem:LD32[%21](tbaa=!"const") S_WAITCNT 127 %VGPR2_VGPR3_VGPR4_VGPR5 = IMAGE_SAMPLE_V4_V2 15, 0, 0, 0, 0, 0, 0, 0, %VGPR4_VGPR5, %SGPR8_SGPR9_SGPR10_SGPR11_SGPR12_SGPR13_SGPR14_SGPR15, %SGPR0_SGPR1_SGPR2_SGPR3, %EXEC %VGPR6 = V_INTERP_P1_F32 %VGPR0, 3, 0, %M0, %EXEC %VGPR6 = V_INTERP_P2_F32 %VGPR6, %VGPR1, 3, 0, %M0, %EXEC S_WAITCNT 1904 %VGPR6 = V_MUL_F32_e32 %VGPR5, %VGPR6, %EXEC %VGPR7 = V_INTERP_P1_F32 %VGPR0, 2, 0, %M0, %EXEC %VGPR7 = V_INTERP_P2_F32 %VGPR7, %VGPR1, 2, 0, %M0, %EXEC %VGPR7 = V_MUL_F32_e32 %VGPR4, %VGPR7, %EXEC %VGPR6 = V_CVT_PKRTZ_F16_F32_e32 %VGPR7, %VGPR6, %EXEC %VGPR7 = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0, %EXEC %VGPR7 = V_INTERP_P2_F32 %VGPR7, %VGPR1, 1, 0, %M0, %EXEC %VGPR7 = V_MUL_F32_e32 %VGPR3, %VGPR7, %EXEC %VGPR8 = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0, %EXEC %VGPR8 = V_INTERP_P2_F32 %VGPR8, %VGPR1, 0, 0, %M0, %EXEC, %VGPR0_VGPR1 %VGPR0 = V_MUL_F32_e32 %VGPR2, %VGPR8, %EXEC, %VGPR2_VGPR3_VGPR4_VGPR5 %VGPR0 = V_CVT_PKRTZ_F16_F32_e32 %VGPR0, %VGPR7, %EXEC EXP 15, 0, 1, 1, 1, %VGPR0, %VGPR6, %VGPR0, %VGPR6, %EXEC S_ENDPGM # End machine code for function main. Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s7 ; BEFC0307 V_INTERP_P1_F32 v2, v0, 1, 1, [m0] ; C8080500 V_INTERP_P2_F32 v2, [v2], v1, 1, 1, [m0] ; C8090501 V_INTERP_P1_F32 v3, v0, 3, 1, [m0] ; C80C0700 V_INTERP_P2_F32 v3, [v3], v1, 3, 1, [m0] ; C80D0701 V_RCP_F32_e32 v3, v3 ; 7E065503 V_MUL_F32_e32 v5, v2, v3 ; 100A0702 V_INTERP_P1_F32 v2, v0, 0, 1, [m0] ; C8080400 V_INTERP_P2_F32 v2, [v2], v1, 0, 1, [m0] ; C8090401 V_MUL_F32_e32 v4, v2, v3 ; 10080702 S_LOAD_DWORDX4 s[0:3], s[2:3], 0 ; C0800300 S_LOAD_DWORDX8 s[8:15], s[4:5], 0 ; C0C40500 S_WAITCNT lgkmcnt(0) ; BF8C007F IMAGE_SAMPLE v[2:5], 15, 0, 0, 0, 0, 0, 0, 0, v[4:5], s[8:15], s[0:3] ; F0800F00 00020204 V_INTERP_P1_F32 v6, v0, 3, 0, [m0] ; C8180300 V_INTERP_P2_F32 v6, [v6], v1, 3, 0, [m0] ; C8190301 S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v6, v5, v6 ; 100C0D05 V_INTERP_P1_F32 v7, v0, 2, 0, [m0] ; C81C0200 V_INTERP_P2_F32 v7, [v7], v1, 2, 0, [m0] ; C81D0201 V_MUL_F32_e32 v7, v4, v7 ; 100E0F04 V_CVT_PKRTZ_F16_F32_e32 v6, v7, v6 ; 5E0C0D07 V_INTERP_P1_F32 v7, v0, 1, 0, [m0] ; C81C0100 V_INTERP_P2_F32 v7, [v7], v1, 1, 0, [m0] ; C81D0101 V_MUL_F32_e32 v7, v3, v7 ; 100E0F03 V_INTERP_P1_F32 v8, v0, 0, 0, [m0] ; C8200000 V_INTERP_P2_F32 v8, [v8], v1, 0, 0, [m0] ; C8210001 V_MUL_F32_e32 v0, v2, v8 ; 10001102 V_CVT_PKRTZ_F16_F32_e32 v0, v0, v7 ; 5E000F00 EXP 15, 0, 1, 1, 1, v0, v6, v0, v6 ; F8001C0F 06000600 S_ENDPGM ; BF810000 VERT DCL IN[0] DCL IN[1] DCL IN[2] DCL OUT[0], POSITION DCL OUT[1], COLOR DCL OUT[2], GENERIC[0] DCL CONST[0..3] DCL TEMP[0] 0: MUL TEMP[0], IN[0].xxxx, CONST[0] 1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0] 2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0] 3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0] 4: MOV_SAT OUT[1], IN[1] 5: MOV OUT[2], IN[2] 6: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0 %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0 %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0) %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4) %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8) %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12) %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16) %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20) %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24) %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28) %20 = call float @llvm.SI.load.const(<16 x i8> %11, i32 32) %21 = call float @llvm.SI.load.const(<16 x i8> %11, i32 36) %22 = call float @llvm.SI.load.const(<16 x i8> %11, i32 40) %23 = call float @llvm.SI.load.const(<16 x i8> %11, i32 44) %24 = call float @llvm.SI.load.const(<16 x i8> %11, i32 48) %25 = call float @llvm.SI.load.const(<16 x i8> %11, i32 52) %26 = call float @llvm.SI.load.const(<16 x i8> %11, i32 56) %27 = call float @llvm.SI.load.const(<16 x i8> %11, i32 60) %28 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0 %29 = load <16 x i8> addrspace(2)* %28, !tbaa !0 %30 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %29, i32 0, i32 %6) %31 = extractelement <4 x float> %30, i32 0 %32 = extractelement <4 x float> %30, i32 1 %33 = extractelement <4 x float> %30, i32 2 %34 = extractelement <4 x float> %30, i32 3 %35 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 1 %36 = load <16 x i8> addrspace(2)* %35, !tbaa !0 %37 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %36, i32 0, i32 %6) %38 = extractelement <4 x float> %37, i32 0 %39 = extractelement <4 x float> %37, i32 1 %40 = extractelement <4 x float> %37, i32 2 %41 = extractelement <4 x float> %37, i32 3 %42 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 2 %43 = load <16 x i8> addrspace(2)* %42, !tbaa !0 %44 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %43, i32 0, i32 %6) %45 = extractelement <4 x float> %44, i32 0 %46 = extractelement <4 x float> %44, i32 1 %47 = extractelement <4 x float> %44, i32 2 %48 = extractelement <4 x float> %44, i32 3 %49 = fmul float %31, %12 %50 = fmul float %31, %13 %51 = fmul float %31, %14 %52 = fmul float %31, %15 %53 = fmul float %32, %16 %54 = fadd float %53, %49 %55 = fmul float %32, %17 %56 = fadd float %55, %50 %57 = fmul float %32, %18 %58 = fadd float %57, %51 %59 = fmul float %32, %19 %60 = fadd float %59, %52 %61 = fmul float %33, %20 %62 = fadd float %61, %54 %63 = fmul float %33, %21 %64 = fadd float %63, %56 %65 = fmul float %33, %22 %66 = fadd float %65, %58 %67 = fmul float %33, %23 %68 = fadd float %67, %60 %69 = fmul float %34, %24 %70 = fadd float %69, %62 %71 = fmul float %34, %25 %72 = fadd float %71, %64 %73 = fmul float %34, %26 %74 = fadd float %73, %66 %75 = fmul float %34, %27 %76 = fadd float %75, %68 %77 = call float @llvm.AMDIL.clamp.(float %38, float 0.000000e+00, float 1.000000e+00) %78 = call float @llvm.AMDIL.clamp.(float %39, float 0.000000e+00, float 1.000000e+00) %79 = call float @llvm.AMDIL.clamp.(float %40, float 0.000000e+00, float 1.000000e+00) %80 = call float @llvm.AMDIL.clamp.(float %41, float 0.000000e+00, float 1.000000e+00) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %77, float %78, float %79, float %80) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %45, float %46, float %47, float %48) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %70, float %72, float %74, float %76) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 ; Function Attrs: readnone declare float @llvm.AMDIL.clamp.(float, float, float) #2 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } !0 = metadata !{metadata !"const", null, i32 1} # Machine code for function main: Post SSA, not tracking liveness Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg6 BB#0: derived from LLVM BB %main_body Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0 %SGPR8_SGPR9_SGPR10_SGPR11 = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%40](align=8)(tbaa=!"const") S_WAITCNT 127 %VGPR1_VGPR2_VGPR3_VGPR4 = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR0, 0, %EXEC S_WAITCNT 1904 %VGPR5 = V_ADD_F32_e64 0, %VGPR4, 0, 1, 0, 0, %EXEC %VGPR6 = V_ADD_F32_e64 0, %VGPR3, 0, 1, 0, 0, %EXEC %VGPR7 = V_ADD_F32_e64 0, %VGPR2, 0, 1, 0, 0, %EXEC %VGPR1 = V_ADD_F32_e64 0, %VGPR1, 0, 1, 0, 0, %EXEC, %VGPR1_VGPR2_VGPR3_VGPR4 EXP 15, 32, 0, 0, 0, %VGPR1, %VGPR7, %VGPR6, %VGPR5, %EXEC %SGPR8_SGPR9_SGPR10_SGPR11 = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 8; mem:LD16[%49](align=8)(tbaa=!"const") S_WAITCNT 15 %VGPR1_VGPR2_VGPR3_VGPR4 = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR0, 0, %EXEC S_WAITCNT 1904 EXP 15, 33, 0, 0, 0, %VGPR1, %VGPR2, %VGPR3, %VGPR4, %EXEC, %VGPR1_VGPR2_VGPR3_VGPR4 %SGPR4_SGPR5_SGPR6_SGPR7 = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 0; mem:LD16[%31](align=8)(tbaa=!"const") S_WAITCNT 15 %VGPR0_VGPR1_VGPR2_VGPR3 = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7, %VGPR0, 0, %EXEC %SGPR0_SGPR1_SGPR2_SGPR3 = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1, 0; mem:LD16[%11](align=8)(tbaa=!"const") S_WAITCNT 112 %SGPR4 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 3; mem:LD4[] S_WAITCNT 127 %VGPR4 = V_MOV_B32_e32 %SGPR4, %EXEC %VGPR4 = V_MUL_F32_e64 %VGPR0, %VGPR4, 0, 0, 0, 0, %EXEC %SGPR4 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 7; mem:LD4[] S_WAITCNT 127 %VGPR5 = V_MOV_B32_e32 %SGPR4, %EXEC %VGPR4 = V_MAD_F32 %VGPR1, %VGPR5, %VGPR4, 0, 0, 0, 0, %EXEC %SGPR4 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 11; mem:LD4[] S_WAITCNT 127 %VGPR5 = V_MOV_B32_e32 %SGPR4, %EXEC %VGPR4 = V_MAD_F32 %VGPR2, %VGPR5, %VGPR4, 0, 0, 0, 0, %EXEC %SGPR4 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 15; mem:LD4[] S_WAITCNT 127 %VGPR5 = V_MOV_B32_e32 %SGPR4, %EXEC %VGPR4 = V_MAD_F32 %VGPR3, %VGPR5, %VGPR4, 0, 0, 0, 0, %EXEC %SGPR4 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2; mem:LD4[] S_WAITCNT 127 %VGPR5 = V_MOV_B32_e32 %SGPR4, %EXEC %VGPR5 = V_MUL_F32_e64 %VGPR0, %VGPR5, 0, 0, 0, 0, %EXEC %SGPR4 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 6; mem:LD4[] S_WAITCNT 127 %VGPR6 = V_MOV_B32_e32 %SGPR4, %EXEC %VGPR5 = V_MAD_F32 %VGPR1, %VGPR6, %VGPR5, 0, 0, 0, 0, %EXEC %SGPR4 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 10; mem:LD4[] S_WAITCNT 127 %VGPR6 = V_MOV_B32_e32 %SGPR4, %EXEC %VGPR5 = V_MAD_F32 %VGPR2, %VGPR6, %VGPR5, 0, 0, 0, 0, %EXEC %SGPR4 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 14; mem:LD4[] S_WAITCNT 127 %VGPR6 = V_MOV_B32_e32 %SGPR4, %EXEC %VGPR5 = V_MAD_F32 %VGPR3, %VGPR6, %VGPR5, 0, 0, 0, 0, %EXEC %SGPR4 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1; mem:LD4[] S_WAITCNT 127 %VGPR6 = V_MOV_B32_e32 %SGPR4, %EXEC %VGPR6 = V_MUL_F32_e64 %VGPR0, %VGPR6, 0, 0, 0, 0, %EXEC %SGPR4 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 5; mem:LD4[] S_WAITCNT 127 %VGPR7 = V_MOV_B32_e32 %SGPR4, %EXEC %VGPR6 = V_MAD_F32 %VGPR1, %VGPR7, %VGPR6, 0, 0, 0, 0, %EXEC %SGPR4 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 9; mem:LD4[] S_WAITCNT 127 %VGPR7 = V_MOV_B32_e32 %SGPR4, %EXEC %VGPR6 = V_MAD_F32 %VGPR2, %VGPR7, %VGPR6, 0, 0, 0, 0, %EXEC %SGPR4 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 13; mem:LD4[] S_WAITCNT 127 %VGPR7 = V_MOV_B32_e32 %SGPR4, %EXEC %VGPR6 = V_MAD_F32 %VGPR3, %VGPR7, %VGPR6, 0, 0, 0, 0, %EXEC %SGPR4 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 0; mem:LD4[] S_WAITCNT 127 %VGPR7 = V_MOV_B32_e32 %SGPR4, %EXEC %VGPR7 = V_MUL_F32_e64 %VGPR0, %VGPR7, 0, 0, 0, 0, %EXEC %SGPR4 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 4; mem:LD4[] S_WAITCNT 127 %VGPR8 = V_MOV_B32_e32 %SGPR4, %EXEC %VGPR7 = V_MAD_F32 %VGPR1, %VGPR8, %VGPR7, 0, 0, 0, 0, %EXEC %SGPR4 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 8; mem:LD4[] S_WAITCNT 127 %VGPR8 = V_MOV_B32_e32 %SGPR4, %EXEC %VGPR7 = V_MAD_F32 %VGPR2, %VGPR8, %VGPR7, 0, 0, 0, 0, %EXEC %SGPR0 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 12; mem:LD4[] S_WAITCNT 127 %VGPR8 = V_MOV_B32_e32 %SGPR0, %EXEC %VGPR0 = V_MAD_F32 %VGPR3, %VGPR8, %VGPR7, 0, 0, 0, 0, %EXEC, %VGPR0_VGPR1_VGPR2_VGPR3 EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR6, %VGPR5, %VGPR4, %EXEC S_ENDPGM # End machine code for function main. Shader Disassembly: S_LOAD_DWORDX4 s[8:11], s[6:7], 4 ; C0840704 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[1:4], s[8:11][v0] + 0 ; E00C2000 80020100 S_WAITCNT vmcnt(0) ; BF8C0770 V_ADD_F32_e64 v5, 0, v4, 0, 1, 0, 0 ; D2060805 02020880 V_ADD_F32_e64 v6, 0, v3, 0, 1, 0, 0 ; D2060806 02020680 V_ADD_F32_e64 v7, 0, v2, 0, 1, 0, 0 ; D2060807 02020480 V_ADD_F32_e64 v1, 0, v1, 0, 1, 0, 0 ; D2060801 02020280 EXP 15, 32, 0, 0, 0, v1, v7, v6, v5 ; F800020F 05060701 S_LOAD_DWORDX4 s[8:11], s[6:7], 8 ; C0840708 S_WAITCNT expcnt(0) lgkmcnt(0) ; BF8C000F BUFFER_LOAD_FORMAT_XYZW v[1:4], s[8:11][v0] + 0 ; E00C2000 80020100 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 33, 0, 0, 0, v1, v2, v3, v4 ; F800021F 04030201 S_LOAD_DWORDX4 s[4:7], s[6:7], 0 ; C0820700 S_WAITCNT expcnt(0) lgkmcnt(0) ; BF8C000F BUFFER_LOAD_FORMAT_XYZW v[0:3], s[4:7][v0] + 0 ; E00C2000 80010000 S_LOAD_DWORDX4 s[0:3], s[0:1], 0 ; C0800100 S_WAITCNT vmcnt(0) lgkmcnt(0) ; BF8C0070 S_BUFFER_LOAD_DWORD s4, s[0:3], 3 ; C2020103 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v4, s4 ; 7E080204 V_MUL_F32_e64 v4, v0, v4, 0, 0, 0, 0 ; D2100004 02020900 S_BUFFER_LOAD_DWORD s4, s[0:3], 7 ; C2020107 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v5, s4 ; 7E0A0204 V_MAD_F32 v4, v1, v5, v4, 0, 0, 0, 0 ; D2820004 04120B01 S_BUFFER_LOAD_DWORD s4, s[0:3], 11 ; C202010B S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v5, s4 ; 7E0A0204 V_MAD_F32 v4, v2, v5, v4, 0, 0, 0, 0 ; D2820004 04120B02 S_BUFFER_LOAD_DWORD s4, s[0:3], 15 ; C202010F S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v5, s4 ; 7E0A0204 V_MAD_F32 v4, v3, v5, v4, 0, 0, 0, 0 ; D2820004 04120B03 S_BUFFER_LOAD_DWORD s4, s[0:3], 2 ; C2020102 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v5, s4 ; 7E0A0204 V_MUL_F32_e64 v5, v0, v5, 0, 0, 0, 0 ; D2100005 02020B00 S_BUFFER_LOAD_DWORD s4, s[0:3], 6 ; C2020106 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v6, s4 ; 7E0C0204 V_MAD_F32 v5, v1, v6, v5, 0, 0, 0, 0 ; D2820005 04160D01 S_BUFFER_LOAD_DWORD s4, s[0:3], 10 ; C202010A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v6, s4 ; 7E0C0204 V_MAD_F32 v5, v2, v6, v5, 0, 0, 0, 0 ; D2820005 04160D02 S_BUFFER_LOAD_DWORD s4, s[0:3], 14 ; C202010E S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v6, s4 ; 7E0C0204 V_MAD_F32 v5, v3, v6, v5, 0, 0, 0, 0 ; D2820005 04160D03 S_BUFFER_LOAD_DWORD s4, s[0:3], 1 ; C2020101 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v6, s4 ; 7E0C0204 V_MUL_F32_e64 v6, v0, v6, 0, 0, 0, 0 ; D2100006 02020D00 S_BUFFER_LOAD_DWORD s4, s[0:3], 5 ; C2020105 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v7, s4 ; 7E0E0204 V_MAD_F32 v6, v1, v7, v6, 0, 0, 0, 0 ; D2820006 041A0F01 S_BUFFER_LOAD_DWORD s4, s[0:3], 9 ; C2020109 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v7, s4 ; 7E0E0204 V_MAD_F32 v6, v2, v7, v6, 0, 0, 0, 0 ; D2820006 041A0F02 S_BUFFER_LOAD_DWORD s4, s[0:3], 13 ; C202010D S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v7, s4 ; 7E0E0204 V_MAD_F32 v6, v3, v7, v6, 0, 0, 0, 0 ; D2820006 041A0F03 S_BUFFER_LOAD_DWORD s4, s[0:3], 0 ; C2020100 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v7, s4 ; 7E0E0204 V_MUL_F32_e64 v7, v0, v7, 0, 0, 0, 0 ; D2100007 02020F00 S_BUFFER_LOAD_DWORD s4, s[0:3], 4 ; C2020104 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v8, s4 ; 7E100204 V_MAD_F32 v7, v1, v8, v7, 0, 0, 0, 0 ; D2820007 041E1101 S_BUFFER_LOAD_DWORD s4, s[0:3], 8 ; C2020108 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v8, s4 ; 7E100204 V_MAD_F32 v7, v2, v8, v7, 0, 0, 0, 0 ; D2820007 041E1102 S_BUFFER_LOAD_DWORD s0, s[0:3], 12 ; C200010C S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v8, s0 ; 7E100200 V_MAD_F32 v0, v3, v8, v7, 0, 0, 0, 0 ; D2820000 041E1103 EXP 15, 12, 0, 1, 0, v0, v6, v5, v4 ; F80008CF 04050600 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[0], LINEAR DCL OUT[0], COLOR DCL SAMP[0] 0: TEX OUT[0], IN[0], SAMP[0], 2D 1: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %21 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0 %22 = load <32 x i8> addrspace(2)* %21, !tbaa !0 %23 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0 %24 = load <16 x i8> addrspace(2)* %23, !tbaa !0 %25 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %4, <2 x i32> %10) %26 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %4, <2 x i32> %10) %27 = bitcast float %25 to i32 %28 = bitcast float %26 to i32 %29 = insertelement <2 x i32> undef, i32 %27, i32 0 %30 = insertelement <2 x i32> %29, i32 %28, i32 1 %31 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %30, <32 x i8> %22, <16 x i8> %24, i32 2) %32 = extractelement <4 x float> %31, i32 0 %33 = extractelement <4 x float> %31, i32 1 %34 = extractelement <4 x float> %31, i32 2 %35 = extractelement <4 x float> %31, i32 3 %36 = call i32 @llvm.SI.packf16(float %32, float %33) %37 = bitcast i32 %36 to float %38 = call i32 @llvm.SI.packf16(float %34, float %35) %39 = bitcast i32 %38 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %37, float %39, float %37, float %39) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} # Machine code for function main: Post SSA, not tracking liveness Function Live Ins: %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR7 in %vreg4, %VGPR0 in %vreg5, %VGPR1 in %vreg6 BB#0: derived from LLVM BB %main_body Live Ins: %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR7 %VGPR0 %VGPR1 %EXEC = S_WQM_B64 %EXEC %VGPR1 = KILL %VGPR1, %VGPR0_VGPR1 %VGPR0 = KILL %VGPR0, %VGPR0_VGPR1, %VGPR0_VGPR1 %M0 = S_MOV_B32 %SGPR7 %VGPR3 = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0, %EXEC, %VGPR2_VGPR3 %VGPR3 = V_INTERP_P2_F32 %VGPR3, %VGPR1, 1, 0, %M0, %EXEC, %VGPR2_VGPR3, %VGPR2_VGPR3 %VGPR2 = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0, %EXEC, %VGPR2_VGPR3, %VGPR2_VGPR3 %VGPR2 = V_INTERP_P2_F32 %VGPR2, %VGPR1, 0, 0, %M0, %EXEC, %VGPR0_VGPR1, %VGPR2_VGPR3, %VGPR2_VGPR3 %SGPR0_SGPR1_SGPR2_SGPR3 = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 0; mem:LD16[%24](align=8)(tbaa=!"const") %SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11 = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 0; mem:LD32[%21](tbaa=!"const") S_WAITCNT 127 %VGPR0_VGPR1_VGPR2_VGPR3 = IMAGE_SAMPLE_V4_V2 15, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3, %SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11, %SGPR0_SGPR1_SGPR2_SGPR3, %EXEC S_WAITCNT 1904 %VGPR4 = V_CVT_PKRTZ_F16_F32_e32 %VGPR2, %VGPR3, %EXEC %VGPR0 = V_CVT_PKRTZ_F16_F32_e32 %VGPR0, %VGPR1, %EXEC, %VGPR0_VGPR1_VGPR2_VGPR3 EXP 15, 0, 1, 1, 1, %VGPR0, %VGPR4, %VGPR0, %VGPR4, %EXEC S_ENDPGM # End machine code for function main. Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s7 ; BEFC0307 V_INTERP_P1_F32 v3, v0, 1, 0, [m0] ; C80C0100 V_INTERP_P2_F32 v3, [v3], v1, 1, 0, [m0] ; C80D0101 V_INTERP_P1_F32 v2, v0, 0, 0, [m0] ; C8080000 V_INTERP_P2_F32 v2, [v2], v1, 0, 0, [m0] ; C8090001 S_LOAD_DWORDX4 s[0:3], s[2:3], 0 ; C0800300 S_LOAD_DWORDX8 s[4:11], s[4:5], 0 ; C0C20500 S_WAITCNT lgkmcnt(0) ; BF8C007F IMAGE_SAMPLE v[0:3], 15, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[4:11], s[0:3] ; F0800F00 00010002 S_WAITCNT vmcnt(0) ; BF8C0770 V_CVT_PKRTZ_F16_F32_e32 v4, v2, v3 ; 5E080702 V_CVT_PKRTZ_F16_F32_e32 v0, v0, v1 ; 5E000300 EXP 15, 0, 1, 1, 1, v0, v4, v0, v4 ; F8001C0F 04000400 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[0], LINEAR DCL OUT[0], COLOR DCL SAMP[0] 0: TEX OUT[0], IN[0], SAMP[0], 2D 1: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %21 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0 %22 = load <32 x i8> addrspace(2)* %21, !tbaa !0 %23 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0 %24 = load <16 x i8> addrspace(2)* %23, !tbaa !0 %25 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %4, <2 x i32> %10) %26 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %4, <2 x i32> %10) %27 = bitcast float %25 to i32 %28 = bitcast float %26 to i32 %29 = insertelement <2 x i32> undef, i32 %27, i32 0 %30 = insertelement <2 x i32> %29, i32 %28, i32 1 %31 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %30, <32 x i8> %22, <16 x i8> %24, i32 2) %32 = extractelement <4 x float> %31, i32 0 %33 = extractelement <4 x float> %31, i32 1 %34 = extractelement <4 x float> %31, i32 2 %35 = extractelement <4 x float> %31, i32 3 %36 = call i32 @llvm.SI.packf16(float %32, float %33) %37 = bitcast i32 %36 to float %38 = call i32 @llvm.SI.packf16(float %34, float %35) %39 = bitcast i32 %38 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %37, float %39, float %37, float %39) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} # Machine code for function main: Post SSA, not tracking liveness Function Live Ins: %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR7 in %vreg4, %VGPR0 in %vreg5, %VGPR1 in %vreg6 BB#0: derived from LLVM BB %main_body Live Ins: %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR7 %VGPR0 %VGPR1 %EXEC = S_WQM_B64 %EXEC %VGPR1 = KILL %VGPR1, %VGPR0_VGPR1 %VGPR0 = KILL %VGPR0, %VGPR0_VGPR1, %VGPR0_VGPR1 %M0 = S_MOV_B32 %SGPR7 %VGPR3 = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0, %EXEC, %VGPR2_VGPR3 %VGPR3 = V_INTERP_P2_F32 %VGPR3, %VGPR1, 1, 0, %M0, %EXEC, %VGPR2_VGPR3, %VGPR2_VGPR3 %VGPR2 = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0, %EXEC, %VGPR2_VGPR3, %VGPR2_VGPR3 %VGPR2 = V_INTERP_P2_F32 %VGPR2, %VGPR1, 0, 0, %M0, %EXEC, %VGPR0_VGPR1, %VGPR2_VGPR3, %VGPR2_VGPR3 %SGPR0_SGPR1_SGPR2_SGPR3 = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 0; mem:LD16[%24](align=8)(tbaa=!"const") %SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11 = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 0; mem:LD32[%21](tbaa=!"const") S_WAITCNT 127 %VGPR0_VGPR1_VGPR2_VGPR3 = IMAGE_SAMPLE_V4_V2 15, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3, %SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11, %SGPR0_SGPR1_SGPR2_SGPR3, %EXEC S_WAITCNT 1904 %VGPR4 = V_CVT_PKRTZ_F16_F32_e32 %VGPR2, %VGPR3, %EXEC %VGPR0 = V_CVT_PKRTZ_F16_F32_e32 %VGPR0, %VGPR1, %EXEC, %VGPR0_VGPR1_VGPR2_VGPR3 EXP 15, 0, 1, 1, 1, %VGPR0, %VGPR4, %VGPR0, %VGPR4, %EXEC S_ENDPGM # End machine code for function main. Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s7 ; BEFC0307 V_INTERP_P1_F32 v3, v0, 1, 0, [m0] ; C80C0100 V_INTERP_P2_F32 v3, [v3], v1, 1, 0, [m0] ; C80D0101 V_INTERP_P1_F32 v2, v0, 0, 0, [m0] ; C8080000 V_INTERP_P2_F32 v2, [v2], v1, 0, 0, [m0] ; C8090001 S_LOAD_DWORDX4 s[0:3], s[2:3], 0 ; C0800300 S_LOAD_DWORDX8 s[4:11], s[4:5], 0 ; C0C20500 S_WAITCNT lgkmcnt(0) ; BF8C007F IMAGE_SAMPLE v[0:3], 15, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[4:11], s[0:3] ; F0800F00 00010002 S_WAITCNT vmcnt(0) ; BF8C0770 V_CVT_PKRTZ_F16_F32_e32 v4, v2, v3 ; 5E080702 V_CVT_PKRTZ_F16_F32_e32 v0, v0, v1 ; 5E000300 EXP 15, 0, 1, 1, 1, v0, v4, v0, v4 ; F8001C0F 04000400 S_ENDPGM ; BF810000 Generating new string page texture 3: 256x256, total string texture memory is 311.30 KB Installing breakpad exception handler for appid(steam)/version(1383158641_client) local (potentially out of sync) copy of roaming config loaded - 1270 bytes. Installing breakpad exception handler for appid(steam)/version(1383158641_client) Adding license for package 0 Adding license for package 2481 Adding license for package 4077 Adding license for package 6443 Adding license for package 8892 Adding license for package 12361 Adding license for package 27644 Adding license for package 34953 Adding license for package 35058 roaming config store loaded successfully - 1270 bytes. migrating temporary roaming config store Installing breakpad exception handler for appid(steam)/version(1383158641_client) ExecCommandLine: "/home/arek/.local/share/Steam/ubuntu12_32/steam steam://rungameid/41070" ExecSteamURL: "steam://rungameid/41070" FRAG 0: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) ret void } declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32) attributes #0 = { "ShaderType"="0" } # Machine code for function main: Post SSA, not tracking liveness BB#0: derived from LLVM BB %main_body %VGPR0 = V_MOV_B32_e32 0, %EXEC EXP 0, 0, 0, 1, 1, %VGPR0, %VGPR0, %VGPR0, %VGPR0, %EXEC S_ENDPGM # End machine code for function main. Shader Disassembly: V_MOV_B32_e32 v0, 0 ; 7E000280 EXP 0, 0, 0, 1, 1, v0, v0, v0, v0 ; F8001800 00000000 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %21 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %4) %22 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %4) %23 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %4) %24 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %4) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %21, float %22, float %23, float %24) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } # Machine code for function main: Post SSA, not tracking liveness Function Live Ins: %SGPR7 in %vreg4 BB#0: derived from LLVM BB %main_body Live Ins: %SGPR7 %EXEC = S_WQM_B64 %EXEC %M0 = S_MOV_B32 %SGPR7 %VGPR0 = V_INTERP_MOV_F32 2, 3, 0, %M0, %EXEC %VGPR1 = V_INTERP_MOV_F32 2, 2, 0, %M0, %EXEC %VGPR2 = V_INTERP_MOV_F32 2, 1, 0, %M0, %EXEC %VGPR3 = V_INTERP_MOV_F32 2, 0, 0, %M0, %EXEC EXP 15, 0, 0, 1, 1, %VGPR3, %VGPR2, %VGPR1, %VGPR0, %EXEC S_ENDPGM # End machine code for function main. Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s7 ; BEFC0307 V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302 V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202 V_INTERP_MOV_F32 v2, P0, 1, 0, [m0] ; C80A0102 V_INTERP_MOV_F32 v3, P0, 0, 0, [m0] ; C80E0002 EXP 15, 0, 0, 1, 1, v3, v2, v1, v0 ; F800180F 00010203 S_ENDPGM ; BF810000 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %21 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %4) %22 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %4) %23 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %4) %24 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %4) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %21, float %22, float %23, float %24) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } # Machine code for function main: Post SSA, not tracking liveness Function Live Ins: %SGPR7 in %vreg4 BB#0: derived from LLVM BB %main_body Live Ins: %SGPR7 %EXEC = S_WQM_B64 %EXEC %M0 = S_MOV_B32 %SGPR7 %VGPR0 = V_INTERP_MOV_F32 2, 3, 0, %M0, %EXEC %VGPR1 = V_INTERP_MOV_F32 2, 2, 0, %M0, %EXEC %VGPR2 = V_INTERP_MOV_F32 2, 1, 0, %M0, %EXEC %VGPR3 = V_INTERP_MOV_F32 2, 0, 0, %M0, %EXEC EXP 15, 0, 0, 1, 1, %VGPR3, %VGPR2, %VGPR1, %VGPR0, %EXEC S_ENDPGM # End machine code for function main. Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s7 ; BEFC0307 V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302 V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202 V_INTERP_MOV_F32 v2, P0, 1, 0, [m0] ; C80A0102 V_INTERP_MOV_F32 v3, P0, 0, 0, [m0] ; C80E0002 EXP 15, 0, 0, 1, 1, v3, v2, v1, v0 ; F800180F 00010203 S_ENDPGM ; BF810000 VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] 0: MOV OUT[0], IN[0] 1: MOV OUT[1], IN[1] 2: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0 %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0 %12 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %11, i32 0, i32 %6) %13 = extractelement <4 x float> %12, i32 0 %14 = extractelement <4 x float> %12, i32 1 %15 = extractelement <4 x float> %12, i32 2 %16 = extractelement <4 x float> %12, i32 3 %17 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 1 %18 = load <16 x i8> addrspace(2)* %17, !tbaa !0 %19 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %18, i32 0, i32 %6) %20 = extractelement <4 x float> %19, i32 0 %21 = extractelement <4 x float> %19, i32 1 %22 = extractelement <4 x float> %19, i32 2 %23 = extractelement <4 x float> %19, i32 3 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %20, float %21, float %22, float %23) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %13, float %14, float %15, float %16) ret void } ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} # Machine code for function main: Post SSA, not tracking liveness Function Live Ins: %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg6 BB#0: derived from LLVM BB %main_body Live Ins: %SGPR6_SGPR7 %VGPR0 %SGPR0_SGPR1_SGPR2_SGPR3 = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%20](align=8)(tbaa=!"const") S_WAITCNT 127 %VGPR1_VGPR2_VGPR3_VGPR4 = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR0, 0, %EXEC S_WAITCNT 1904 EXP 15, 32, 0, 0, 0, %VGPR1, %VGPR2, %VGPR3, %VGPR4, %EXEC, %VGPR1_VGPR2_VGPR3_VGPR4 %SGPR0_SGPR1_SGPR2_SGPR3 = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 0; mem:LD16[%11](align=8)(tbaa=!"const") S_WAITCNT 15 %VGPR0_VGPR1_VGPR2_VGPR3 = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR0, 0, %EXEC S_WAITCNT 1904 EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR1, %VGPR2, %VGPR3, %EXEC, %VGPR0_VGPR1_VGPR2_VGPR3 S_ENDPGM # End machine code for function main. Shader Disassembly: S_LOAD_DWORDX4 s[0:3], s[6:7], 4 ; C0800704 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[1:4], s[0:3][v0] + 0 ; E00C2000 80000100 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 32, 0, 0, 0, v1, v2, v3, v4 ; F800020F 04030201 S_LOAD_DWORDX4 s[0:3], s[6:7], 0 ; C0800700 S_WAITCNT expcnt(0) lgkmcnt(0) ; BF8C000F BUFFER_LOAD_FORMAT_XYZW v[0:3], s[0:3][v0] + 0 ; E00C2000 80000000 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 12, 0, 1, 0, v0, v1, v2, v3 ; F80008CF 03020100 S_ENDPGM ; BF810000 VERT DCL IN[0] DCL OUT[0], POSITION 0: MOV OUT[0], IN[0] 1: END STREAMOUT 0: BUF0[0..0] <- OUT[0].x ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %13 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 0 %14 = load <16 x i8> addrspace(2)* %13, !tbaa !0 %15 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0 %16 = load <16 x i8> addrspace(2)* %15, !tbaa !0 %17 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %16, i32 0, i32 %9) %18 = extractelement <4 x float> %17, i32 0 %19 = extractelement <4 x float> %17, i32 1 %20 = extractelement <4 x float> %17, i32 2 %21 = extractelement <4 x float> %17, i32 3 %22 = lshr i32 %6, 16 %23 = and i32 %22, 127 %24 = call i32 @llvm.SI.tid() %25 = icmp ult i32 %24, %23 br i1 %25, label %if-true-block, label %endif-block if-true-block: ; preds = %main_body %26 = add i32 %7, %24 %27 = mul i32 %8, 4 %28 = mul i32 %26, 4 %29 = add i32 %28, %27 %30 = bitcast float %18 to i32 call void @llvm.SI.tbuffer.store.i32(<16 x i8> %14, i32 %30, i32 1, i32 %29, i32 0, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0) br label %endif-block endif-block: ; preds = %main_body, %if-true-block call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %18, float %19, float %20, float %21) ret void } ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 ; Function Attrs: readnone declare i32 @llvm.SI.tid() #2 declare void @llvm.SI.tbuffer.store.i32(<16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32) declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } !0 = metadata !{metadata !"const", null, i32 1} # Machine code for function main: Post SSA, not tracking liveness Function Live Ins: %SGPR6_SGPR7 in %vreg7, %SGPR8_SGPR9 in %vreg8, %SGPR11 in %vreg10, %SGPR12 in %vreg11, %SGPR13 in %vreg12, %VGPR0 in %vreg13 BB#0: derived from LLVM BB %main_body Live Ins: %SGPR6_SGPR7 %SGPR8_SGPR9 %SGPR11 %SGPR12 %SGPR13 %VGPR0 %SGPR0_SGPR1_SGPR2_SGPR3 = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 0; mem:LD16[%14](align=8)(tbaa=!"const") S_WAITCNT 127 %VGPR0_VGPR1_VGPR2_VGPR3 = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR0, 0, %EXEC %SGPR0 = S_LSHR_B32 %SGPR11, 16 %VGPR4 = V_MOV_B32_e32 127, %EXEC %VGPR5 = V_AND_B32_e32 %SGPR0, %VGPR4, %EXEC %VGPR4 = V_MBCNT_LO_U32_B32_e64 -1, 0, 0, 0, 0, 0, %EXEC %VGPR4 = V_MBCNT_HI_U32_B32_e32 -1, %VGPR4, %EXEC %SGPR0_SGPR1 = V_CMP_LT_U32_e64 %VGPR4, %VGPR5, 0, 0, 0, 0, %EXEC S_WAITCNT 1904 %SGPR0_SGPR1 = S_AND_SAVEEXEC_B64 %SGPR0_SGPR1, %EXEC, %EXEC %SGPR0_SGPR1 = S_XOR_B64 %EXEC, %SGPR0_SGPR1 Successors according to CFG: BB#1(16) BB#2(16) BB#1: derived from LLVM BB %if-true-block Live Ins: %VGPR0_VGPR1_VGPR2_VGPR3 %SGPR8_SGPR9 %SGPR12 %SGPR13 %SGPR0_SGPR1 %VGPR4 Predecessors according to CFG: BB#0 %VGPR4 = V_ADD_I32_e32 %SGPR12, %VGPR4, %EXEC, %VCC %VGPR4 = V_LSHLREV_B32_e32 2, %VGPR4, %EXEC %SGPR2 = S_LSHL_B32 %SGPR13, 2 %VGPR4 = V_ADD_I32_e32 %SGPR2, %VGPR4, %EXEC, %VCC %SGPR4_SGPR5_SGPR6_SGPR7 = S_LOAD_DWORDX4_IMM %SGPR8_SGPR9, 0; mem:LD16[%27](align=8)(tbaa=!"const") S_WAITCNT 127 TBUFFER_STORE_FORMAT_X %VGPR0, 0, -1, 0, -1, 0, 4, 4, %VGPR4, %SGPR4_SGPR5_SGPR6_SGPR7, -1, 0, 0, %EXEC S_WAITCNT 1792 Successors according to CFG: BB#2 BB#2: derived from LLVM BB %endif-block Live Ins: %VGPR0_VGPR1_VGPR2_VGPR3 %SGPR0_SGPR1 Predecessors according to CFG: BB#0 BB#1 %EXEC = S_OR_B64 %EXEC, %SGPR0_SGPR1 EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR1, %VGPR2, %VGPR3, %EXEC, %VGPR0_VGPR1_VGPR2_VGPR3 S_ENDPGM # End machine code for function main. Shader Disassembly: S_LOAD_DWORDX4 s[0:3], s[6:7], 0 ; C0800700 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[0:3], s[0:3][v0] + 0 ; E00C2000 80000000 S_LSHR_B32 s0, s11, 16 ; 9000900B V_MOV_B32_e32 v4, 127 ; 7E0802FF 0000007F V_AND_B32_e32 v5, s0, v4 ; 360A0800 V_MBCNT_LO_U32_B32_e64 v4, -1, 0, 0, 0, 0, 0 ; D2460004 020100C1 V_MBCNT_HI_U32_B32_e32 v4, -1, v4 ; 480808C1 V_CMP_LT_U32_e64 s[0:1], v4, v5, 0, 0, 0, 0 ; D1820000 02020B04 S_WAITCNT vmcnt(0) ; BF8C0770 S_AND_SAVEEXEC_B64 s[0:1], s[0:1] ; BE802400 S_XOR_B64 s[0:1], exec, s[0:1] ; 8980007E V_ADD_I32_e32 v4, s12, v4 ; 4A08080C V_LSHLREV_B32_e32 v4, 2, v4 ; 34080882 S_LSHL_B32 s2, s13, 2 ; 8F02820D V_ADD_I32_e32 v4, s2, v4 ; 4A080802 S_LOAD_DWORDX4 s[4:7], s[8:9], 0 ; C0820900 S_WAITCNT lgkmcnt(0) ; BF8C007F TBUFFER_STORE_FORMAT_X v0, 0, -1, 0, -1, 0, 4, 4, v4, s[4:7], -1, 0, 0 ; EA245000 80410004 S_WAITCNT vmcnt(0) expcnt(0) ; BF8C0700 S_OR_B64 exec, exec, s[0:1] ; 88FE007E EXP 15, 12, 0, 1, 0, v0, v1, v2, v3 ; F80008CF 03020100 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[0], CONSTANT 0: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } # Machine code for function main: Post SSA, not tracking liveness BB#0: derived from LLVM BB %main_body %VGPR0 = V_MOV_B32_e32 0, %EXEC EXP 0, 0, 0, 1, 1, %VGPR0, %VGPR0, %VGPR0, %VGPR0, %EXEC S_ENDPGM # End machine code for function main. Shader Disassembly: V_MOV_B32_e32 v0, 0 ; 7E000280 EXP 0, 0, 0, 1, 1, v0, v0, v0, v0 ; F8001800 00000000 S_ENDPGM ; BF810000 System startup time: 6.52 seconds Running Steam on arch 32-bit STEAM_RUNTIME has been set by the user to: /home/arek/.local/share/Steam/ubuntu12_32/steam-runtime ExecCommandLine: "/home/arek/.steam/root/ubuntu12_32/steam steam://open/driverhelperready" ExecSteamURL: "steam://open/driverhelperready" Generating new string page texture 64: 32x256, total string texture memory is 344.06 KB Generating new string page texture 65: 64x256, total string texture memory is 409.60 KB Installing breakpad exception handler for appid(steam)/version(1383158641_client) Game update: AppID 41070 "Serious Sam 3: BFE", ProcID 20476, IP 0.0.0.0:0 (steam:20358): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent. (steam:20358): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent. (steam:20358): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent. (steam:20358): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent. (steam:20358): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent. (steam:20358): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent. (steam:20358): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent. (steam:20358): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent. (steam:20358): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent. (steam:20358): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent. (steam:20358): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent. (steam:20358): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent. (steam:20358): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent. (steam:20358): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent. cat: /etc/debian_version: No such file or directory Setting breakpad minidump AppID = 41070 Steam_SetMinidumpSteamID: Caching Steam ID: 76561198090478818 [API loaded no] INF: GameEnv API: Steam INF: Encoded user ID = fbc68a8b:44652b57 INF: INF: * Desktop settings... INF: Color depth: 32-bit INF: Desktop resolution: 1680 x 1050 INF: Fullscreen on primary display FRAG 0: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) ret void } declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32) attributes #0 = { "ShaderType"="0" } # Machine code for function main: Post SSA, not tracking liveness BB#0: derived from LLVM BB %main_body %VGPR0 = V_MOV_B32_e32 0, %EXEC EXP 0, 0, 0, 1, 1, %VGPR0, %VGPR0, %VGPR0, %VGPR0, %EXEC S_ENDPGM # End machine code for function main. Shader Disassembly: V_MOV_B32_e32 v0, 0 ; 7E000280 EXP 0, 0, 0, 1, 1, v0, v0, v0, v0 ; F8001800 00000000 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %21 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %4) %22 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %4) %23 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %4) %24 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %4) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %21, float %22, float %23, float %24) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } # Machine code for function main: Post SSA, not tracking liveness Function Live Ins: %SGPR7 in %vreg4 BB#0: derived from LLVM BB %main_body Live Ins: %SGPR7 %EXEC = S_WQM_B64 %EXEC %M0 = S_MOV_B32 %SGPR7 %VGPR0 = V_INTERP_MOV_F32 2, 3, 0, %M0, %EXEC %VGPR1 = V_INTERP_MOV_F32 2, 2, 0, %M0, %EXEC %VGPR2 = V_INTERP_MOV_F32 2, 1, 0, %M0, %EXEC %VGPR3 = V_INTERP_MOV_F32 2, 0, 0, %M0, %EXEC EXP 15, 0, 0, 1, 1, %VGPR3, %VGPR2, %VGPR1, %VGPR0, %EXEC S_ENDPGM # End machine code for function main. Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s7 ; BEFC0307 V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302 V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202 V_INTERP_MOV_F32 v2, P0, 1, 0, [m0] ; C80A0102 V_INTERP_MOV_F32 v3, P0, 0, 0, [m0] ; C80E0002 EXP 15, 0, 0, 1, 1, v3, v2, v1, v0 ; F800180F 00010203 S_ENDPGM ; BF810000 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %21 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %4) %22 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %4) %23 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %4) %24 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %4) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %21, float %22, float %23, float %24) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } # Machine code for function main: Post SSA, not tracking liveness Function Live Ins: %SGPR7 in %vreg4 BB#0: derived from LLVM BB %main_body Live Ins: %SGPR7 %EXEC = S_WQM_B64 %EXEC %M0 = S_MOV_B32 %SGPR7 %VGPR0 = V_INTERP_MOV_F32 2, 3, 0, %M0, %EXEC %VGPR1 = V_INTERP_MOV_F32 2, 2, 0, %M0, %EXEC %VGPR2 = V_INTERP_MOV_F32 2, 1, 0, %M0, %EXEC %VGPR3 = V_INTERP_MOV_F32 2, 0, 0, %M0, %EXEC EXP 15, 0, 0, 1, 1, %VGPR3, %VGPR2, %VGPR1, %VGPR0, %EXEC S_ENDPGM # End machine code for function main. Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s7 ; BEFC0307 V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302 V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202 V_INTERP_MOV_F32 v2, P0, 1, 0, [m0] ; C80A0102 V_INTERP_MOV_F32 v3, P0, 0, 0, [m0] ; C80E0002 EXP 15, 0, 0, 1, 1, v3, v2, v1, v0 ; F800180F 00010203 S_ENDPGM ; BF810000 VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] 0: MOV OUT[0], IN[0] 1: MOV OUT[1], IN[1] 2: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0 %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0 %12 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %11, i32 0, i32 %6) %13 = extractelement <4 x float> %12, i32 0 %14 = extractelement <4 x float> %12, i32 1 %15 = extractelement <4 x float> %12, i32 2 %16 = extractelement <4 x float> %12, i32 3 %17 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 1 %18 = load <16 x i8> addrspace(2)* %17, !tbaa !0 %19 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %18, i32 0, i32 %6) %20 = extractelement <4 x float> %19, i32 0 %21 = extractelement <4 x float> %19, i32 1 %22 = extractelement <4 x float> %19, i32 2 %23 = extractelement <4 x float> %19, i32 3 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %20, float %21, float %22, float %23) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %13, float %14, float %15, float %16) ret void } ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} # Machine code for function main: Post SSA, not tracking liveness Function Live Ins: %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg6 BB#0: derived from LLVM BB %main_body Live Ins: %SGPR6_SGPR7 %VGPR0 %SGPR0_SGPR1_SGPR2_SGPR3 = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%20](align=8)(tbaa=!"const") S_WAITCNT 127 %VGPR1_VGPR2_VGPR3_VGPR4 = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR0, 0, %EXEC S_WAITCNT 1904 EXP 15, 32, 0, 0, 0, %VGPR1, %VGPR2, %VGPR3, %VGPR4, %EXEC, %VGPR1_VGPR2_VGPR3_VGPR4 %SGPR0_SGPR1_SGPR2_SGPR3 = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 0; mem:LD16[%11](align=8)(tbaa=!"const") S_WAITCNT 15 %VGPR0_VGPR1_VGPR2_VGPR3 = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR0, 0, %EXEC S_WAITCNT 1904 EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR1, %VGPR2, %VGPR3, %EXEC, %VGPR0_VGPR1_VGPR2_VGPR3 S_ENDPGM # End machine code for function main. Shader Disassembly: S_LOAD_DWORDX4 s[0:3], s[6:7], 4 ; C0800704 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[1:4], s[0:3][v0] + 0 ; E00C2000 80000100 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 32, 0, 0, 0, v1, v2, v3, v4 ; F800020F 04030201 S_LOAD_DWORDX4 s[0:3], s[6:7], 0 ; C0800700 S_WAITCNT expcnt(0) lgkmcnt(0) ; BF8C000F BUFFER_LOAD_FORMAT_XYZW v[0:3], s[0:3][v0] + 0 ; E00C2000 80000000 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 12, 0, 1, 0, v0, v1, v2, v3 ; F80008CF 03020100 S_ENDPGM ; BF810000 VERT DCL IN[0] DCL OUT[0], POSITION 0: MOV OUT[0], IN[0] 1: END STREAMOUT 0: BUF0[0..0] <- OUT[0].x ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %13 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 0 %14 = load <16 x i8> addrspace(2)* %13, !tbaa !0 %15 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0 %16 = load <16 x i8> addrspace(2)* %15, !tbaa !0 %17 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %16, i32 0, i32 %9) %18 = extractelement <4 x float> %17, i32 0 %19 = extractelement <4 x float> %17, i32 1 %20 = extractelement <4 x float> %17, i32 2 %21 = extractelement <4 x float> %17, i32 3 %22 = lshr i32 %6, 16 %23 = and i32 %22, 127 %24 = call i32 @llvm.SI.tid() %25 = icmp ult i32 %24, %23 br i1 %25, label %if-true-block, label %endif-block if-true-block: ; preds = %main_body %26 = add i32 %7, %24 %27 = mul i32 %8, 4 %28 = mul i32 %26, 4 %29 = add i32 %28, %27 %30 = bitcast float %18 to i32 call void @llvm.SI.tbuffer.store.i32(<16 x i8> %14, i32 %30, i32 1, i32 %29, i32 0, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0) br label %endif-block endif-block: ; preds = %main_body, %if-true-block call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %18, float %19, float %20, float %21) ret void } ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 ; Function Attrs: readnone declare i32 @llvm.SI.tid() #2 declare void @llvm.SI.tbuffer.store.i32(<16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32) declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } !0 = metadata !{metadata !"const", null, i32 1} # Machine code for function main: Post SSA, not tracking liveness Function Live Ins: %SGPR6_SGPR7 in %vreg7, %SGPR8_SGPR9 in %vreg8, %SGPR11 in %vreg10, %SGPR12 in %vreg11, %SGPR13 in %vreg12, %VGPR0 in %vreg13 BB#0: derived from LLVM BB %main_body Live Ins: %SGPR6_SGPR7 %SGPR8_SGPR9 %SGPR11 %SGPR12 %SGPR13 %VGPR0 %SGPR0_SGPR1_SGPR2_SGPR3 = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 0; mem:LD16[%14](align=8)(tbaa=!"const") S_WAITCNT 127 %VGPR0_VGPR1_VGPR2_VGPR3 = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR0, 0, %EXEC %SGPR0 = S_LSHR_B32 %SGPR11, 16 %VGPR4 = V_MOV_B32_e32 127, %EXEC %VGPR5 = V_AND_B32_e32 %SGPR0, %VGPR4, %EXEC %VGPR4 = V_MBCNT_LO_U32_B32_e64 -1, 0, 0, 0, 0, 0, %EXEC %VGPR4 = V_MBCNT_HI_U32_B32_e32 -1, %VGPR4, %EXEC %SGPR0_SGPR1 = V_CMP_LT_U32_e64 %VGPR4, %VGPR5, 0, 0, 0, 0, %EXEC S_WAITCNT 1904 %SGPR0_SGPR1 = S_AND_SAVEEXEC_B64 %SGPR0_SGPR1, %EXEC, %EXEC %SGPR0_SGPR1 = S_XOR_B64 %EXEC, %SGPR0_SGPR1 Successors according to CFG: BB#1(16) BB#2(16) BB#1: derived from LLVM BB %if-true-block Live Ins: %VGPR0_VGPR1_VGPR2_VGPR3 %SGPR8_SGPR9 %SGPR12 %SGPR13 %SGPR0_SGPR1 %VGPR4 Predecessors according to CFG: BB#0 %VGPR4 = V_ADD_I32_e32 %SGPR12, %VGPR4, %EXEC, %VCC %VGPR4 = V_LSHLREV_B32_e32 2, %VGPR4, %EXEC %SGPR2 = S_LSHL_B32 %SGPR13, 2 %VGPR4 = V_ADD_I32_e32 %SGPR2, %VGPR4, %EXEC, %VCC %SGPR4_SGPR5_SGPR6_SGPR7 = S_LOAD_DWORDX4_IMM %SGPR8_SGPR9, 0; mem:LD16[%27](align=8)(tbaa=!"const") S_WAITCNT 127 TBUFFER_STORE_FORMAT_X %VGPR0, 0, -1, 0, -1, 0, 4, 4, %VGPR4, %SGPR4_SGPR5_SGPR6_SGPR7, -1, 0, 0, %EXEC S_WAITCNT 1792 Successors according to CFG: BB#2 BB#2: derived from LLVM BB %endif-block Live Ins: %VGPR0_VGPR1_VGPR2_VGPR3 %SGPR0_SGPR1 Predecessors according to CFG: BB#0 BB#1 %EXEC = S_OR_B64 %EXEC, %SGPR0_SGPR1 EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR1, %VGPR2, %VGPR3, %EXEC, %VGPR0_VGPR1_VGPR2_VGPR3 S_ENDPGM # End machine code for function main. Shader Disassembly: S_LOAD_DWORDX4 s[0:3], s[6:7], 0 ; C0800700 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[0:3], s[0:3][v0] + 0 ; E00C2000 80000000 S_LSHR_B32 s0, s11, 16 ; 9000900B V_MOV_B32_e32 v4, 127 ; 7E0802FF 0000007F V_AND_B32_e32 v5, s0, v4 ; 360A0800 V_MBCNT_LO_U32_B32_e64 v4, -1, 0, 0, 0, 0, 0 ; D2460004 020100C1 V_MBCNT_HI_U32_B32_e32 v4, -1, v4 ; 480808C1 V_CMP_LT_U32_e64 s[0:1], v4, v5, 0, 0, 0, 0 ; D1820000 02020B04 S_WAITCNT vmcnt(0) ; BF8C0770 S_AND_SAVEEXEC_B64 s[0:1], s[0:1] ; BE802400 S_XOR_B64 s[0:1], exec, s[0:1] ; 8980007E V_ADD_I32_e32 v4, s12, v4 ; 4A08080C V_LSHLREV_B32_e32 v4, 2, v4 ; 34080882 S_LSHL_B32 s2, s13, 2 ; 8F02820D V_ADD_I32_e32 v4, s2, v4 ; 4A080802 S_LOAD_DWORDX4 s[4:7], s[8:9], 0 ; C0820900 S_WAITCNT lgkmcnt(0) ; BF8C007F TBUFFER_STORE_FORMAT_X v0, 0, -1, 0, -1, 0, 4, 4, v4, s[4:7], -1, 0, 0 ; EA245000 80410004 S_WAITCNT vmcnt(0) expcnt(0) ; BF8C0700 S_OR_B64 exec, exec, s[0:1] ; 88FE007E EXP 15, 12, 0, 1, 0, v0, v1, v2, v3 ; F80008CF 03020100 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[0], CONSTANT 0: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } # Machine code for function main: Post SSA, not tracking liveness BB#0: derived from LLVM BB %main_body %VGPR0 = V_MOV_B32_e32 0, %EXEC EXP 0, 0, 0, 1, 1, %VGPR0, %VGPR0, %VGPR0, %VGPR0, %EXEC S_ENDPGM # End machine code for function main. Shader Disassembly: V_MOV_B32_e32 v0, 0 ; 7E000280 EXP 0, 0, 0, 1, 1, v0, v0, v0, v0 ; F8001800 00000000 S_ENDPGM ; BF810000 FRAG 0: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) ret void } declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32) attributes #0 = { "ShaderType"="0" } # Machine code for function main: Post SSA, not tracking liveness BB#0: derived from LLVM BB %main_body %VGPR0 = V_MOV_B32_e32 0, %EXEC EXP 0, 0, 0, 1, 1, %VGPR0, %VGPR0, %VGPR0, %VGPR0, %EXEC S_ENDPGM # End machine code for function main. Shader Disassembly: V_MOV_B32_e32 v0, 0 ; 7E000280 EXP 0, 0, 0, 1, 1, v0, v0, v0, v0 ; F8001800 00000000 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %21 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %4) %22 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %4) %23 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %4) %24 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %4) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %21, float %22, float %23, float %24) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } # Machine code for function main: Post SSA, not tracking liveness Function Live Ins: %SGPR7 in %vreg4 BB#0: derived from LLVM BB %main_body Live Ins: %SGPR7 %EXEC = S_WQM_B64 %EXEC %M0 = S_MOV_B32 %SGPR7 %VGPR0 = V_INTERP_MOV_F32 2, 3, 0, %M0, %EXEC %VGPR1 = V_INTERP_MOV_F32 2, 2, 0, %M0, %EXEC %VGPR2 = V_INTERP_MOV_F32 2, 1, 0, %M0, %EXEC %VGPR3 = V_INTERP_MOV_F32 2, 0, 0, %M0, %EXEC EXP 15, 0, 0, 1, 1, %VGPR3, %VGPR2, %VGPR1, %VGPR0, %EXEC S_ENDPGM # End machine code for function main. Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s7 ; BEFC0307 V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302 V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202 V_INTERP_MOV_F32 v2, P0, 1, 0, [m0] ; C80A0102 V_INTERP_MOV_F32 v3, P0, 0, 0, [m0] ; C80E0002 EXP 15, 0, 0, 1, 1, v3, v2, v1, v0 ; F800180F 00010203 S_ENDPGM ; BF810000 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %21 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %4) %22 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %4) %23 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %4) %24 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %4) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %21, float %22, float %23, float %24) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } # Machine code for function main: Post SSA, not tracking liveness Function Live Ins: %SGPR7 in %vreg4 BB#0: derived from LLVM BB %main_body Live Ins: %SGPR7 %EXEC = S_WQM_B64 %EXEC %M0 = S_MOV_B32 %SGPR7 %VGPR0 = V_INTERP_MOV_F32 2, 3, 0, %M0, %EXEC %VGPR1 = V_INTERP_MOV_F32 2, 2, 0, %M0, %EXEC %VGPR2 = V_INTERP_MOV_F32 2, 1, 0, %M0, %EXEC %VGPR3 = V_INTERP_MOV_F32 2, 0, 0, %M0, %EXEC EXP 15, 0, 0, 1, 1, %VGPR3, %VGPR2, %VGPR1, %VGPR0, %EXEC S_ENDPGM # End machine code for function main. Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s7 ; BEFC0307 V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302 V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202 V_INTERP_MOV_F32 v2, P0, 1, 0, [m0] ; C80A0102 V_INTERP_MOV_F32 v3, P0, 0, 0, [m0] ; C80E0002 EXP 15, 0, 0, 1, 1, v3, v2, v1, v0 ; F800180F 00010203 S_ENDPGM ; BF810000 VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] 0: MOV OUT[0], IN[0] 1: MOV OUT[1], IN[1] 2: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0 %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0 %12 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %11, i32 0, i32 %6) %13 = extractelement <4 x float> %12, i32 0 %14 = extractelement <4 x float> %12, i32 1 %15 = extractelement <4 x float> %12, i32 2 %16 = extractelement <4 x float> %12, i32 3 %17 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 1 %18 = load <16 x i8> addrspace(2)* %17, !tbaa !0 %19 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %18, i32 0, i32 %6) %20 = extractelement <4 x float> %19, i32 0 %21 = extractelement <4 x float> %19, i32 1 %22 = extractelement <4 x float> %19, i32 2 %23 = extractelement <4 x float> %19, i32 3 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %20, float %21, float %22, float %23) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %13, float %14, float %15, float %16) ret void } ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} # Machine code for function main: Post SSA, not tracking liveness Function Live Ins: %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg6 BB#0: derived from LLVM BB %main_body Live Ins: %SGPR6_SGPR7 %VGPR0 %SGPR0_SGPR1_SGPR2_SGPR3 = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%20](align=8)(tbaa=!"const") S_WAITCNT 127 %VGPR1_VGPR2_VGPR3_VGPR4 = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR0, 0, %EXEC S_WAITCNT 1904 EXP 15, 32, 0, 0, 0, %VGPR1, %VGPR2, %VGPR3, %VGPR4, %EXEC, %VGPR1_VGPR2_VGPR3_VGPR4 %SGPR0_SGPR1_SGPR2_SGPR3 = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 0; mem:LD16[%11](align=8)(tbaa=!"const") S_WAITCNT 15 %VGPR0_VGPR1_VGPR2_VGPR3 = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR0, 0, %EXEC S_WAITCNT 1904 EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR1, %VGPR2, %VGPR3, %EXEC, %VGPR0_VGPR1_VGPR2_VGPR3 S_ENDPGM # End machine code for function main. Shader Disassembly: S_LOAD_DWORDX4 s[0:3], s[6:7], 4 ; C0800704 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[1:4], s[0:3][v0] + 0 ; E00C2000 80000100 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 32, 0, 0, 0, v1, v2, v3, v4 ; F800020F 04030201 S_LOAD_DWORDX4 s[0:3], s[6:7], 0 ; C0800700 S_WAITCNT expcnt(0) lgkmcnt(0) ; BF8C000F BUFFER_LOAD_FORMAT_XYZW v[0:3], s[0:3][v0] + 0 ; E00C2000 80000000 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 12, 0, 1, 0, v0, v1, v2, v3 ; F80008CF 03020100 S_ENDPGM ; BF810000 VERT DCL IN[0] DCL OUT[0], POSITION 0: MOV OUT[0], IN[0] 1: END STREAMOUT 0: BUF0[0..0] <- OUT[0].x ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %13 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 0 %14 = load <16 x i8> addrspace(2)* %13, !tbaa !0 %15 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0 %16 = load <16 x i8> addrspace(2)* %15, !tbaa !0 %17 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %16, i32 0, i32 %9) %18 = extractelement <4 x float> %17, i32 0 %19 = extractelement <4 x float> %17, i32 1 %20 = extractelement <4 x float> %17, i32 2 %21 = extractelement <4 x float> %17, i32 3 %22 = lshr i32 %6, 16 %23 = and i32 %22, 127 %24 = call i32 @llvm.SI.tid() %25 = icmp ult i32 %24, %23 br i1 %25, label %if-true-block, label %endif-block if-true-block: ; preds = %main_body %26 = add i32 %7, %24 %27 = mul i32 %8, 4 %28 = mul i32 %26, 4 %29 = add i32 %28, %27 %30 = bitcast float %18 to i32 call void @llvm.SI.tbuffer.store.i32(<16 x i8> %14, i32 %30, i32 1, i32 %29, i32 0, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0) br label %endif-block endif-block: ; preds = %main_body, %if-true-block call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %18, float %19, float %20, float %21) ret void } ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 ; Function Attrs: readnone declare i32 @llvm.SI.tid() #2 declare void @llvm.SI.tbuffer.store.i32(<16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32) declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } !0 = metadata !{metadata !"const", null, i32 1} # Machine code for function main: Post SSA, not tracking liveness Function Live Ins: %SGPR6_SGPR7 in %vreg7, %SGPR8_SGPR9 in %vreg8, %SGPR11 in %vreg10, %SGPR12 in %vreg11, %SGPR13 in %vreg12, %VGPR0 in %vreg13 BB#0: derived from LLVM BB %main_body Live Ins: %SGPR6_SGPR7 %SGPR8_SGPR9 %SGPR11 %SGPR12 %SGPR13 %VGPR0 %SGPR0_SGPR1_SGPR2_SGPR3 = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 0; mem:LD16[%14](align=8)(tbaa=!"const") S_WAITCNT 127 %VGPR0_VGPR1_VGPR2_VGPR3 = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR0, 0, %EXEC %SGPR0 = S_LSHR_B32 %SGPR11, 16 %VGPR4 = V_MOV_B32_e32 127, %EXEC %VGPR5 = V_AND_B32_e32 %SGPR0, %VGPR4, %EXEC %VGPR4 = V_MBCNT_LO_U32_B32_e64 -1, 0, 0, 0, 0, 0, %EXEC %VGPR4 = V_MBCNT_HI_U32_B32_e32 -1, %VGPR4, %EXEC %SGPR0_SGPR1 = V_CMP_LT_U32_e64 %VGPR4, %VGPR5, 0, 0, 0, 0, %EXEC S_WAITCNT 1904 %SGPR0_SGPR1 = S_AND_SAVEEXEC_B64 %SGPR0_SGPR1, %EXEC, %EXEC %SGPR0_SGPR1 = S_XOR_B64 %EXEC, %SGPR0_SGPR1 Successors according to CFG: BB#1(16) BB#2(16) BB#1: derived from LLVM BB %if-true-block Live Ins: %VGPR0_VGPR1_VGPR2_VGPR3 %SGPR8_SGPR9 %SGPR12 %SGPR13 %SGPR0_SGPR1 %VGPR4 Predecessors according to CFG: BB#0 %VGPR4 = V_ADD_I32_e32 %SGPR12, %VGPR4, %EXEC, %VCC %VGPR4 = V_LSHLREV_B32_e32 2, %VGPR4, %EXEC %SGPR2 = S_LSHL_B32 %SGPR13, 2 %VGPR4 = V_ADD_I32_e32 %SGPR2, %VGPR4, %EXEC, %VCC %SGPR4_SGPR5_SGPR6_SGPR7 = S_LOAD_DWORDX4_IMM %SGPR8_SGPR9, 0; mem:LD16[%27](align=8)(tbaa=!"const") S_WAITCNT 127 TBUFFER_STORE_FORMAT_X %VGPR0, 0, -1, 0, -1, 0, 4, 4, %VGPR4, %SGPR4_SGPR5_SGPR6_SGPR7, -1, 0, 0, %EXEC S_WAITCNT 1792 Successors according to CFG: BB#2 BB#2: derived from LLVM BB %endif-block Live Ins: %VGPR0_VGPR1_VGPR2_VGPR3 %SGPR0_SGPR1 Predecessors according to CFG: BB#0 BB#1 %EXEC = S_OR_B64 %EXEC, %SGPR0_SGPR1 EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR1, %VGPR2, %VGPR3, %EXEC, %VGPR0_VGPR1_VGPR2_VGPR3 S_ENDPGM # End machine code for function main. Shader Disassembly: S_LOAD_DWORDX4 s[0:3], s[6:7], 0 ; C0800700 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[0:3], s[0:3][v0] + 0 ; E00C2000 80000000 S_LSHR_B32 s0, s11, 16 ; 9000900B V_MOV_B32_e32 v4, 127 ; 7E0802FF 0000007F V_AND_B32_e32 v5, s0, v4 ; 360A0800 V_MBCNT_LO_U32_B32_e64 v4, -1, 0, 0, 0, 0, 0 ; D2460004 020100C1 V_MBCNT_HI_U32_B32_e32 v4, -1, v4 ; 480808C1 V_CMP_LT_U32_e64 s[0:1], v4, v5, 0, 0, 0, 0 ; D1820000 02020B04 S_WAITCNT vmcnt(0) ; BF8C0770 S_AND_SAVEEXEC_B64 s[0:1], s[0:1] ; BE802400 S_XOR_B64 s[0:1], exec, s[0:1] ; 8980007E V_ADD_I32_e32 v4, s12, v4 ; 4A08080C V_LSHLREV_B32_e32 v4, 2, v4 ; 34080882 S_LSHL_B32 s2, s13, 2 ; 8F02820D V_ADD_I32_e32 v4, s2, v4 ; 4A080802 S_LOAD_DWORDX4 s[4:7], s[8:9], 0 ; C0820900 S_WAITCNT lgkmcnt(0) ; BF8C007F TBUFFER_STORE_FORMAT_X v0, 0, -1, 0, -1, 0, 4, 4, v4, s[4:7], -1, 0, 0 ; EA245000 80410004 S_WAITCNT vmcnt(0) expcnt(0) ; BF8C0700 S_OR_B64 exec, exec, s[0:1] ; 88FE007E EXP 15, 12, 0, 1, 0, v0, v1, v2, v3 ; F80008CF 03020100 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[0], CONSTANT 0: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } # Machine code for function main: Post SSA, not tracking liveness BB#0: derived from LLVM BB %main_body %VGPR0 = V_MOV_B32_e32 0, %EXEC EXP 0, 0, 0, 1, 1, %VGPR0, %VGPR0, %VGPR0, %VGPR0, %EXEC S_ENDPGM # End machine code for function main. Shader Disassembly: V_MOV_B32_e32 v0, 0 ; 7E000280 EXP 0, 0, 0, 1, 1, v0, v0, v0, v0 ; F8001800 00000000 S_ENDPGM ; BF810000 WRN: [OpenGL] "GL_ARB_get_program_binary" extension is present but not used because no binary formats are exposed. WRN: [OpenGL] Unable to determine VRAM size... assuming 512 MB. FRAG DCL IN[0], GENERIC[0], LINEAR DCL OUT[0], COLOR DCL SAMP[0] 0: TEX OUT[0], IN[0], SAMP[0], 2D 1: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %21 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0 %22 = load <32 x i8> addrspace(2)* %21, !tbaa !0 %23 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0 %24 = load <16 x i8> addrspace(2)* %23, !tbaa !0 %25 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %4, <2 x i32> %10) %26 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %4, <2 x i32> %10) %27 = bitcast float %25 to i32 %28 = bitcast float %26 to i32 %29 = insertelement <2 x i32> undef, i32 %27, i32 0 %30 = insertelement <2 x i32> %29, i32 %28, i32 1 %31 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %30, <32 x i8> %22, <16 x i8> %24, i32 2) %32 = extractelement <4 x float> %31, i32 0 %33 = extractelement <4 x float> %31, i32 1 %34 = extractelement <4 x float> %31, i32 2 %35 = extractelement <4 x float> %31, i32 3 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %32, float %33, float %34, float %35) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} # Machine code for function main: Post SSA, not tracking liveness Function Live Ins: %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR7 in %vreg4, %VGPR0 in %vreg5, %VGPR1 in %vreg6 BB#0: derived from LLVM BB %main_body Live Ins: %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR7 %VGPR0 %VGPR1 %EXEC = S_WQM_B64 %EXEC %VGPR1 = KILL %VGPR1, %VGPR0_VGPR1 %VGPR0 = KILL %VGPR0, %VGPR0_VGPR1, %VGPR0_VGPR1 %M0 = S_MOV_B32 %SGPR7 %VGPR3 = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0, %EXEC, %VGPR2_VGPR3 %VGPR3 = V_INTERP_P2_F32 %VGPR3, %VGPR1, 1, 0, %M0, %EXEC, %VGPR2_VGPR3, %VGPR2_VGPR3 %VGPR2 = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0, %EXEC, %VGPR2_VGPR3, %VGPR2_VGPR3 %VGPR2 = V_INTERP_P2_F32 %VGPR2, %VGPR1, 0, 0, %M0, %EXEC, %VGPR0_VGPR1, %VGPR2_VGPR3, %VGPR2_VGPR3 %SGPR0_SGPR1_SGPR2_SGPR3 = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 0; mem:LD16[%24](align=8)(tbaa=!"const") %SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11 = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 0; mem:LD32[%21](tbaa=!"const") S_WAITCNT 127 %VGPR0_VGPR1_VGPR2_VGPR3 = IMAGE_SAMPLE_V4_V2 15, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3, %SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11, %SGPR0_SGPR1_SGPR2_SGPR3, %EXEC S_WAITCNT 1904 EXP 15, 0, 0, 1, 1, %VGPR0, %VGPR1, %VGPR2, %VGPR3, %EXEC, %VGPR0_VGPR1_VGPR2_VGPR3 S_ENDPGM # End machine code for function main. Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s7 ; BEFC0307 V_INTERP_P1_F32 v3, v0, 1, 0, [m0] ; C80C0100 V_INTERP_P2_F32 v3, [v3], v1, 1, 0, [m0] ; C80D0101 V_INTERP_P1_F32 v2, v0, 0, 0, [m0] ; C8080000 V_INTERP_P2_F32 v2, [v2], v1, 0, 0, [m0] ; C8090001 S_LOAD_DWORDX4 s[0:3], s[2:3], 0 ; C0800300 S_LOAD_DWORDX8 s[4:11], s[4:5], 0 ; C0C20500 S_WAITCNT lgkmcnt(0) ; BF8C007F IMAGE_SAMPLE v[0:3], 15, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[4:11], s[0:3] ; F0800F00 00010002 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 0, 0, 1, 1, v0, v1, v2, v3 ; F800180F 03020100 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[0], LINEAR DCL OUT[0], COLOR DCL SAMP[0] 0: TEX OUT[0], IN[0], SAMP[0], 2D 1: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %21 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0 %22 = load <32 x i8> addrspace(2)* %21, !tbaa !0 %23 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0 %24 = load <16 x i8> addrspace(2)* %23, !tbaa !0 %25 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %4, <2 x i32> %10) %26 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %4, <2 x i32> %10) %27 = bitcast float %25 to i32 %28 = bitcast float %26 to i32 %29 = insertelement <2 x i32> undef, i32 %27, i32 0 %30 = insertelement <2 x i32> %29, i32 %28, i32 1 %31 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %30, <32 x i8> %22, <16 x i8> %24, i32 2) %32 = extractelement <4 x float> %31, i32 0 %33 = extractelement <4 x float> %31, i32 1 %34 = extractelement <4 x float> %31, i32 2 %35 = extractelement <4 x float> %31, i32 3 %36 = call i32 @llvm.SI.packf16(float %32, float %33) %37 = bitcast i32 %36 to float %38 = call i32 @llvm.SI.packf16(float %34, float %35) %39 = bitcast i32 %38 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %37, float %39, float %37, float %39) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} # Machine code for function main: Post SSA, not tracking liveness Function Live Ins: %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR7 in %vreg4, %VGPR0 in %vreg5, %VGPR1 in %vreg6 BB#0: derived from LLVM BB %main_body Live Ins: %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR7 %VGPR0 %VGPR1 %EXEC = S_WQM_B64 %EXEC %VGPR1 = KILL %VGPR1, %VGPR0_VGPR1 %VGPR0 = KILL %VGPR0, %VGPR0_VGPR1, %VGPR0_VGPR1 %M0 = S_MOV_B32 %SGPR7 %VGPR3 = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0, %EXEC, %VGPR2_VGPR3 %VGPR3 = V_INTERP_P2_F32 %VGPR3, %VGPR1, 1, 0, %M0, %EXEC, %VGPR2_VGPR3, %VGPR2_VGPR3 %VGPR2 = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0, %EXEC, %VGPR2_VGPR3, %VGPR2_VGPR3 %VGPR2 = V_INTERP_P2_F32 %VGPR2, %VGPR1, 0, 0, %M0, %EXEC, %VGPR0_VGPR1, %VGPR2_VGPR3, %VGPR2_VGPR3 %SGPR0_SGPR1_SGPR2_SGPR3 = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 0; mem:LD16[%24](align=8)(tbaa=!"const") %SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11 = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 0; mem:LD32[%21](tbaa=!"const") S_WAITCNT 127 %VGPR0_VGPR1_VGPR2_VGPR3 = IMAGE_SAMPLE_V4_V2 15, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3, %SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11, %SGPR0_SGPR1_SGPR2_SGPR3, %EXEC S_WAITCNT 1904 %VGPR4 = V_CVT_PKRTZ_F16_F32_e32 %VGPR2, %VGPR3, %EXEC %VGPR0 = V_CVT_PKRTZ_F16_F32_e32 %VGPR0, %VGPR1, %EXEC, %VGPR0_VGPR1_VGPR2_VGPR3 EXP 15, 0, 1, 1, 1, %VGPR0, %VGPR4, %VGPR0, %VGPR4, %EXEC S_ENDPGM # End machine code for function main. Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s7 ; BEFC0307 V_INTERP_P1_F32 v3, v0, 1, 0, [m0] ; C80C0100 V_INTERP_P2_F32 v3, [v3], v1, 1, 0, [m0] ; C80D0101 V_INTERP_P1_F32 v2, v0, 0, 0, [m0] ; C8080000 V_INTERP_P2_F32 v2, [v2], v1, 0, 0, [m0] ; C8090001 S_LOAD_DWORDX4 s[0:3], s[2:3], 0 ; C0800300 S_LOAD_DWORDX8 s[4:11], s[4:5], 0 ; C0C20500 S_WAITCNT lgkmcnt(0) ; BF8C007F IMAGE_SAMPLE v[0:3], 15, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[4:11], s[0:3] ; F0800F00 00010002 S_WAITCNT vmcnt(0) ; BF8C0770 V_CVT_PKRTZ_F16_F32_e32 v4, v2, v3 ; 5E080702 V_CVT_PKRTZ_F16_F32_e32 v0, v0, v1 ; 5E000300 EXP 15, 0, 1, 1, 1, v0, v4, v0, v4 ; F8001C0F 04000400 S_ENDPGM ; BF810000 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[19], PERSPECTIVE DCL IN[1], GENERIC[20], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL CONST[0] DCL TEMP[0..2], LOCAL IMM[0] FLT32 { 32.0000, -16.0000, 1.0000, 0.0000} 0: MOV TEMP[0].xy, IN[1].xyyy 1: TEX TEMP[0], TEMP[0], SAMP[0], 2D 2: MAD TEMP[1].x, TEMP[0].wwww, IMM[0].xxxx, IMM[0].yyyy 3: EX2 TEMP[1].x, TEMP[1].xxxx 4: MUL TEMP[1].xyz, TEMP[0].xyzz, TEMP[1].xxxx 5: MOV TEMP[1].w, IMM[0].zzzz 6: FSGE TEMP[2].x, CONST[0].xxxx, IMM[0].wwww 7: UIF TEMP[2].xxxx :0 8: MOV TEMP[1], TEMP[1] 9: ELSE :0 10: MOV TEMP[1], TEMP[0] 11: ENDIF 12: MUL TEMP[0], TEMP[1], IN[0] 13: MOV OUT[0], TEMP[0] 14: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %21 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0 %22 = load <16 x i8> addrspace(2)* %21, !tbaa !0 %23 = call float @llvm.SI.load.const(<16 x i8> %22, i32 0) %24 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0 %25 = load <32 x i8> addrspace(2)* %24, !tbaa !0 %26 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0 %27 = load <16 x i8> addrspace(2)* %26, !tbaa !0 %28 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %4, <2 x i32> %6) %29 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %4, <2 x i32> %6) %30 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %4, <2 x i32> %6) %31 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %4, <2 x i32> %6) %32 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %4, <2 x i32> %6) %33 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %4, <2 x i32> %6) %34 = bitcast float %32 to i32 %35 = bitcast float %33 to i32 %36 = insertelement <2 x i32> undef, i32 %34, i32 0 %37 = insertelement <2 x i32> %36, i32 %35, i32 1 %38 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %37, <32 x i8> %25, <16 x i8> %27, i32 2) %39 = extractelement <4 x float> %38, i32 0 %40 = extractelement <4 x float> %38, i32 1 %41 = extractelement <4 x float> %38, i32 2 %42 = extractelement <4 x float> %38, i32 3 %43 = fmul float %42, 3.200000e+01 %44 = fadd float %43, -1.600000e+01 %45 = call float @llvm.AMDIL.exp.(float %44) %46 = fmul float %39, %45 %47 = fmul float %40, %45 %48 = fmul float %41, %45 %49 = fcmp oge float %23, 0.000000e+00 %50 = sext i1 %49 to i32 %51 = bitcast i32 %50 to float %52 = bitcast float %51 to i32 %53 = icmp ne i32 %52, 0 %. = select i1 %53, float %46, float %39 %.12 = select i1 %53, float %47, float %40 %.13 = select i1 %53, float %48, float %41 %.14 = select i1 %53, float 1.000000e+00, float %42 %54 = fmul float %., %28 %55 = fmul float %.12, %29 %56 = fmul float %.13, %30 %57 = fmul float %.14, %31 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %54, float %55, float %56, float %57) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1 ; Function Attrs: readnone declare float @llvm.AMDIL.exp.(float) #2 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } !0 = metadata !{metadata !"const", null, i32 1} # Machine code for function main: Post SSA, not tracking liveness Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR7 in %vreg4, %VGPR0 in %vreg5, %VGPR1 in %vreg6 BB#0: derived from LLVM BB %main_body Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR7 %VGPR0 %VGPR1 %EXEC = S_WQM_B64 %EXEC %VGPR1 = KILL %VGPR1, %VGPR0_VGPR1 %VGPR0 = KILL %VGPR0, %VGPR0_VGPR1, %VGPR0_VGPR1 %M0 = S_MOV_B32 %SGPR7 %VGPR3 = V_INTERP_P1_F32 %VGPR0, 1, 1, %M0, %EXEC, %VGPR2_VGPR3 %VGPR3 = V_INTERP_P2_F32 %VGPR3, %VGPR1, 1, 1, %M0, %EXEC, %VGPR2_VGPR3, %VGPR2_VGPR3 %VGPR2 = V_INTERP_P1_F32 %VGPR0, 0, 1, %M0, %EXEC, %VGPR2_VGPR3, %VGPR2_VGPR3 %VGPR2 = V_INTERP_P2_F32 %VGPR2, %VGPR1, 0, 1, %M0, %EXEC, %VGPR2_VGPR3, %VGPR2_VGPR3 %SGPR8_SGPR9_SGPR10_SGPR11 = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 0; mem:LD16[%29](align=8)(tbaa=!"const") %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 0; mem:LD32[%26](tbaa=!"const") S_WAITCNT 127 %VGPR2_VGPR3_VGPR4_VGPR5 = IMAGE_SAMPLE_V4_V2 15, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC %VGPR6 = V_MOV_B32_e32 -1.600000e+01, %EXEC %VGPR7 = V_MOV_B32_e32 3.200000e+01, %EXEC S_WAITCNT 1904 %VGPR6 = V_MAD_F32 %VGPR5, %VGPR7, %VGPR6, 0, 0, 0, 0, %EXEC %VGPR6 = V_EXP_F32_e32 %VGPR6, %EXEC %VGPR7 = V_MUL_F32_e32 %VGPR4, %VGPR6, %EXEC %SGPR0_SGPR1_SGPR2_SGPR3 = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1, 0; mem:LD16[%22](align=8)(tbaa=!"const") S_WAITCNT 127 %SGPR0 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 0; mem:LD4[] S_WAITCNT 127 %SGPR0_SGPR1 = V_CMP_GE_F32_e64 %SGPR0, 0.000000e+00, 0, 0, 0, 0, %EXEC %VGPR7 = V_CNDMASK_B32_e64 %VGPR4, %VGPR7, %SGPR0_SGPR1, 0, 0, 0, 0, %EXEC %VGPR8 = V_INTERP_P1_F32 %VGPR0, 2, 0, %M0, %EXEC %VGPR8 = V_INTERP_P2_F32 %VGPR8, %VGPR1, 2, 0, %M0, %EXEC %VGPR7 = V_MUL_F32_e32 %VGPR7, %VGPR8, %EXEC %VGPR8 = V_MUL_F32_e32 %VGPR3, %VGPR6, %EXEC %VGPR8 = V_CNDMASK_B32_e64 %VGPR3, %VGPR8, %SGPR0_SGPR1, 0, 0, 0, 0, %EXEC %VGPR9 = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0, %EXEC %VGPR9 = V_INTERP_P2_F32 %VGPR9, %VGPR1, 1, 0, %M0, %EXEC %VGPR8 = V_MUL_F32_e32 %VGPR8, %VGPR9, %EXEC %VGPR6 = V_MUL_F32_e32 %VGPR2, %VGPR6, %EXEC %VGPR6 = V_CNDMASK_B32_e64 %VGPR2, %VGPR6, %SGPR0_SGPR1, 0, 0, 0, 0, %EXEC %VGPR9 = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0, %EXEC %VGPR9 = V_INTERP_P2_F32 %VGPR9, %VGPR1, 0, 0, %M0, %EXEC %VGPR6 = V_MUL_F32_e32 %VGPR6, %VGPR9, %EXEC %VGPR2 = V_CNDMASK_B32_e64 %VGPR5, 1.000000e+00, %SGPR0_SGPR1, 0, 0, 0, 0, %EXEC, %VGPR2_VGPR3_VGPR4_VGPR5 %VGPR3 = V_INTERP_P1_F32 %VGPR0, 3, 0, %M0, %EXEC %VGPR3 = V_INTERP_P2_F32 %VGPR3, %VGPR1, 3, 0, %M0, %EXEC, %VGPR0_VGPR1 %VGPR0 = V_MUL_F32_e32 %VGPR2, %VGPR3, %EXEC EXP 15, 0, 0, 1, 1, %VGPR6, %VGPR8, %VGPR7, %VGPR0, %EXEC S_ENDPGM # End machine code for function main. Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s7 ; BEFC0307 V_INTERP_P1_F32 v3, v0, 1, 1, [m0] ; C80C0500 V_INTERP_P2_F32 v3, [v3], v1, 1, 1, [m0] ; C80D0501 V_INTERP_P1_F32 v2, v0, 0, 1, [m0] ; C8080400 V_INTERP_P2_F32 v2, [v2], v1, 0, 1, [m0] ; C8090401 S_LOAD_DWORDX4 s[8:11], s[2:3], 0 ; C0840300 S_LOAD_DWORDX8 s[12:19], s[4:5], 0 ; C0C60500 S_WAITCNT lgkmcnt(0) ; BF8C007F IMAGE_SAMPLE v[2:5], 15, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[12:19], s[8:11] ; F0800F00 00430202 V_MOV_B32_e32 v6, -1.600000e+01 ; 7E0C02FF C1800000 V_MOV_B32_e32 v7, 3.200000e+01 ; 7E0E02FF 42000000 S_WAITCNT vmcnt(0) ; BF8C0770 V_MAD_F32 v6, v5, v7, v6, 0, 0, 0, 0 ; D2820006 041A0F05 V_EXP_F32_e32 v6, v6 ; 7E0C4B06 V_MUL_F32_e32 v7, v4, v6 ; 100E0D04 S_LOAD_DWORDX4 s[0:3], s[0:1], 0 ; C0800100 S_WAITCNT lgkmcnt(0) ; BF8C007F S_BUFFER_LOAD_DWORD s0, s[0:3], 0 ; C2000100 S_WAITCNT lgkmcnt(0) ; BF8C007F V_CMP_GE_F32_e64 s[0:1], s0, 0.000000e+00, 0, 0, 0, 0 ; D00C0000 02010000 V_CNDMASK_B32_e64 v7, v4, v7, s[0:1], 0, 0, 0, 0 ; D2000007 00020F04 V_INTERP_P1_F32 v8, v0, 2, 0, [m0] ; C8200200 V_INTERP_P2_F32 v8, [v8], v1, 2, 0, [m0] ; C8210201 V_MUL_F32_e32 v7, v7, v8 ; 100E1107 V_MUL_F32_e32 v8, v3, v6 ; 10100D03 V_CNDMASK_B32_e64 v8, v3, v8, s[0:1], 0, 0, 0, 0 ; D2000008 00021103 V_INTERP_P1_F32 v9, v0, 1, 0, [m0] ; C8240100 V_INTERP_P2_F32 v9, [v9], v1, 1, 0, [m0] ; C8250101 V_MUL_F32_e32 v8, v8, v9 ; 10101308 V_MUL_F32_e32 v6, v2, v6 ; 100C0D02 V_CNDMASK_B32_e64 v6, v2, v6, s[0:1], 0, 0, 0, 0 ; D2000006 00020D02 V_INTERP_P1_F32 v9, v0, 0, 0, [m0] ; C8240000 V_INTERP_P2_F32 v9, [v9], v1, 0, 0, [m0] ; C8250001 V_MUL_F32_e32 v6, v6, v9 ; 100C1306 V_CNDMASK_B32_e64 v2, v5, 1.000000e+00, s[0:1], 0, 0, 0, 0 ; D2000002 0001E505 V_INTERP_P1_F32 v3, v0, 3, 0, [m0] ; C80C0300 V_INTERP_P2_F32 v3, [v3], v1, 3, 0, [m0] ; C80D0301 V_MUL_F32_e32 v0, v2, v3 ; 10000702 EXP 15, 0, 0, 1, 1, v6, v8, v7, v0 ; F800180F 00070806 S_ENDPGM ; BF810000 VERT DCL IN[0] DCL IN[1] DCL IN[2] DCL OUT[0], POSITION DCL OUT[1], CLIPVERTEX DCL OUT[2], GENERIC[19] DCL OUT[3], GENERIC[20] DCL CONST[0..5] DCL TEMP[0..3], LOCAL IMM[0] FLT32 { 0.0000, 0.0000, 0.0000, 0.0000} 0: DP4 TEMP[0].x, IN[0], CONST[0] 1: DP4 TEMP[1].x, IN[0], CONST[1] 2: MOV TEMP[0].y, TEMP[1].xxxx 3: DP4 TEMP[1].x, IN[0], CONST[2] 4: MOV TEMP[0].z, TEMP[1].xxxx 5: DP4 TEMP[1].x, IN[0], CONST[3] 6: MOV TEMP[0].w, TEMP[1].xxxx 7: FSGE TEMP[1].x, CONST[4].zzzz, IMM[0].xxxx 8: UIF TEMP[1].xxxx :0 9: MOV TEMP[1], IN[2].zyxw 10: ELSE :0 11: MOV TEMP[1], CONST[5] 12: ENDIF 13: MOV TEMP[2].w, TEMP[1].wwww 14: POW TEMP[3].x, TEMP[1].xxxx, CONST[4].xxxx 15: POW TEMP[3].y, TEMP[1].yyyy, CONST[4].xxxx 16: POW TEMP[3].z, TEMP[1].zzzz, CONST[4].xxxx 17: MUL TEMP[2].xyz, TEMP[3].xyzz, CONST[4].yyyy 18: MUL TEMP[0], TEMP[0], CONST[4].wwww 19: MOV TEMP[1].xy, IN[1].xyxx 20: MOV OUT[3], TEMP[1] 21: MOV OUT[2], TEMP[2] 22: MOV OUT[0], TEMP[0] 23: MOV OUT[1], TEMP[0] 24: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0 %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0 %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0) %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4) %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8) %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12) %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16) %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20) %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24) %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28) %20 = call float @llvm.SI.load.const(<16 x i8> %11, i32 32) %21 = call float @llvm.SI.load.const(<16 x i8> %11, i32 36) %22 = call float @llvm.SI.load.const(<16 x i8> %11, i32 40) %23 = call float @llvm.SI.load.const(<16 x i8> %11, i32 44) %24 = call float @llvm.SI.load.const(<16 x i8> %11, i32 48) %25 = call float @llvm.SI.load.const(<16 x i8> %11, i32 52) %26 = call float @llvm.SI.load.const(<16 x i8> %11, i32 56) %27 = call float @llvm.SI.load.const(<16 x i8> %11, i32 60) %28 = call float @llvm.SI.load.const(<16 x i8> %11, i32 64) %29 = call float @llvm.SI.load.const(<16 x i8> %11, i32 68) %30 = call float @llvm.SI.load.const(<16 x i8> %11, i32 72) %31 = call float @llvm.SI.load.const(<16 x i8> %11, i32 76) %32 = call float @llvm.SI.load.const(<16 x i8> %11, i32 80) %33 = call float @llvm.SI.load.const(<16 x i8> %11, i32 84) %34 = call float @llvm.SI.load.const(<16 x i8> %11, i32 88) %35 = call float @llvm.SI.load.const(<16 x i8> %11, i32 92) %36 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0 %37 = load <16 x i8> addrspace(2)* %36, !tbaa !0 %38 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %37, i32 0, i32 %6) %39 = extractelement <4 x float> %38, i32 0 %40 = extractelement <4 x float> %38, i32 1 %41 = extractelement <4 x float> %38, i32 2 %42 = extractelement <4 x float> %38, i32 3 %43 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 1 %44 = load <16 x i8> addrspace(2)* %43, !tbaa !0 %45 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %44, i32 0, i32 %6) %46 = extractelement <4 x float> %45, i32 0 %47 = extractelement <4 x float> %45, i32 1 %48 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 2 %49 = load <16 x i8> addrspace(2)* %48, !tbaa !0 %50 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %49, i32 0, i32 %6) %51 = extractelement <4 x float> %50, i32 0 %52 = extractelement <4 x float> %50, i32 1 %53 = extractelement <4 x float> %50, i32 2 %54 = extractelement <4 x float> %50, i32 3 %55 = fmul float %39, %12 %56 = fmul float %40, %13 %57 = fadd float %55, %56 %58 = fmul float %41, %14 %59 = fadd float %57, %58 %60 = fmul float %42, %15 %61 = fadd float %59, %60 %62 = fmul float %39, %16 %63 = fmul float %40, %17 %64 = fadd float %62, %63 %65 = fmul float %41, %18 %66 = fadd float %64, %65 %67 = fmul float %42, %19 %68 = fadd float %66, %67 %69 = fmul float %39, %20 %70 = fmul float %40, %21 %71 = fadd float %69, %70 %72 = fmul float %41, %22 %73 = fadd float %71, %72 %74 = fmul float %42, %23 %75 = fadd float %73, %74 %76 = fmul float %39, %24 %77 = fmul float %40, %25 %78 = fadd float %76, %77 %79 = fmul float %41, %26 %80 = fadd float %78, %79 %81 = fmul float %42, %27 %82 = fadd float %80, %81 %83 = fcmp oge float %30, 0.000000e+00 %84 = sext i1 %83 to i32 %85 = bitcast i32 %84 to float %86 = bitcast float %85 to i32 %87 = icmp ne i32 %86, 0 %. = select i1 %87, float %53, float %32 %.16 = select i1 %87, float %52, float %33 %.17 = select i1 %87, float %51, float %34 %.18 = select i1 %87, float %54, float %35 %88 = call float @llvm.pow.f32(float %., float %28) %89 = call float @llvm.pow.f32(float %.16, float %28) %90 = call float @llvm.pow.f32(float %.17, float %28) %91 = fmul float %88, %29 %92 = fmul float %89, %29 %93 = fmul float %90, %29 %94 = fmul float %61, %31 %95 = fmul float %68, %31 %96 = fmul float %75, %31 %97 = fmul float %82, %31 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %91, float %92, float %93, float %.18) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %46, float %47, float %.17, float %.18) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %94, float %95, float %96, float %97) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 ; Function Attrs: nounwind readonly declare float @llvm.pow.f32(float, float) #2 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" } attributes #1 = { nounwind readnone } attributes #2 = { nounwind readonly } !0 = metadata !{metadata !"const", null, i32 1} # Machine code for function main: Post SSA, not tracking liveness Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg6 BB#0: derived from LLVM BB %main_body Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0 %SGPR8_SGPR9_SGPR10_SGPR11 = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 8; mem:LD16[%55](align=8)(tbaa=!"const") S_WAITCNT 127 %VGPR1_VGPR2_VGPR3_VGPR4 = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR0, 0, %EXEC %SGPR0_SGPR1_SGPR2_SGPR3 = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1, 0; mem:LD16[%11](align=8)(tbaa=!"const") S_WAITCNT 112 %SGPR4 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 18; mem:LD4[] S_WAITCNT 127 %SGPR4_SGPR5 = V_CMP_GE_F32_e64 %SGPR4, 0.000000e+00, 0, 0, 0, 0, %EXEC %SGPR8 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 23; mem:LD4[] S_WAITCNT 127 %VGPR5 = V_MOV_B32_e32 %SGPR8, %EXEC %VGPR5 = V_CNDMASK_B32_e64 %VGPR5, %VGPR4, %SGPR4_SGPR5, 0, 0, 0, 0, %EXEC %SGPR8 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 22; mem:LD4[] S_WAITCNT 127 %VGPR6 = V_MOV_B32_e32 %SGPR8, %EXEC %VGPR6 = V_CNDMASK_B32_e64 %VGPR6, %VGPR1, %SGPR4_SGPR5, 0, 0, 0, 0, %EXEC %VGPR7 = V_LOG_F32_e32 %VGPR6, %EXEC %SGPR8 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 16; mem:LD4[] S_WAITCNT 127 %VGPR7 = V_MUL_LEGACY_F32_e32 %SGPR8, %VGPR7, %EXEC %VGPR7 = V_EXP_F32_e32 %VGPR7, %EXEC %SGPR9 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 17; mem:LD4[] S_WAITCNT 127 %VGPR7 = V_MUL_F32_e32 %SGPR9, %VGPR7, %EXEC %SGPR10 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 21; mem:LD4[] S_WAITCNT 127 %VGPR8 = V_MOV_B32_e32 %SGPR10, %EXEC %VGPR8 = V_CNDMASK_B32_e64 %VGPR8, %VGPR2, %SGPR4_SGPR5, 0, 0, 0, 0, %EXEC %VGPR8 = V_LOG_F32_e32 %VGPR8, %EXEC %VGPR8 = V_MUL_LEGACY_F32_e32 %SGPR8, %VGPR8, %EXEC %VGPR8 = V_EXP_F32_e32 %VGPR8, %EXEC %VGPR8 = V_MUL_F32_e32 %SGPR9, %VGPR8, %EXEC %SGPR10 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 20; mem:LD4[] S_WAITCNT 127 %VGPR9 = V_MOV_B32_e32 %SGPR10, %EXEC %VGPR1 = V_CNDMASK_B32_e64 %VGPR9, %VGPR3, %SGPR4_SGPR5, 0, 0, 0, 0, %EXEC, %VGPR1_VGPR2_VGPR3_VGPR4 %VGPR1 = V_LOG_F32_e32 %VGPR1, %EXEC %VGPR1 = V_MUL_LEGACY_F32_e32 %SGPR8, %VGPR1, %EXEC %VGPR1 = V_EXP_F32_e32 %VGPR1, %EXEC %VGPR1 = V_MUL_F32_e32 %SGPR9, %VGPR1, %EXEC EXP 15, 32, 0, 0, 0, %VGPR1, %VGPR8, %VGPR7, %VGPR5, %EXEC %SGPR8_SGPR9_SGPR10_SGPR11 = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%48](align=8)(tbaa=!"const") S_WAITCNT 15 %VGPR1_VGPR2_VGPR3_VGPR4 = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR0, 0, %EXEC S_WAITCNT 1904 EXP 15, 33, 0, 0, 0, %VGPR1, %VGPR2, %VGPR6, %VGPR5, %EXEC, %VGPR1_VGPR2_VGPR3_VGPR4 %SGPR4_SGPR5_SGPR6_SGPR7 = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 0; mem:LD16[%39](align=8)(tbaa=!"const") S_WAITCNT 15 %VGPR0_VGPR1_VGPR2_VGPR3 = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7, %VGPR0, 0, %EXEC %SGPR4 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 13; mem:LD4[] S_WAITCNT 112 %VGPR4 = V_MOV_B32_e32 %SGPR4, %EXEC %VGPR4 = V_MUL_F32_e64 %VGPR1, %VGPR4, 0, 0, 0, 0, %EXEC %SGPR4 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 12; mem:LD4[] S_WAITCNT 127 %VGPR5 = V_MOV_B32_e32 %SGPR4, %EXEC %VGPR4 = V_MAD_F32 %VGPR0, %VGPR5, %VGPR4, 0, 0, 0, 0, %EXEC %SGPR4 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 14; mem:LD4[] S_WAITCNT 127 %VGPR5 = V_MOV_B32_e32 %SGPR4, %EXEC %VGPR4 = V_MAD_F32 %VGPR2, %VGPR5, %VGPR4, 0, 0, 0, 0, %EXEC %SGPR4 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 15; mem:LD4[] S_WAITCNT 127 %VGPR5 = V_MOV_B32_e32 %SGPR4, %EXEC %VGPR4 = V_MAD_F32 %VGPR3, %VGPR5, %VGPR4, 0, 0, 0, 0, %EXEC %SGPR4 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 19; mem:LD4[] S_WAITCNT 127 %VGPR4 = V_MUL_F32_e32 %SGPR4, %VGPR4, %EXEC %SGPR5 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 9; mem:LD4[] S_WAITCNT 127 %VGPR5 = V_MOV_B32_e32 %SGPR5, %EXEC %VGPR5 = V_MUL_F32_e64 %VGPR1, %VGPR5, 0, 0, 0, 0, %EXEC %SGPR5 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 8; mem:LD4[] S_WAITCNT 127 %VGPR6 = V_MOV_B32_e32 %SGPR5, %EXEC %VGPR5 = V_MAD_F32 %VGPR0, %VGPR6, %VGPR5, 0, 0, 0, 0, %EXEC %SGPR5 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 10; mem:LD4[] S_WAITCNT 127 %VGPR6 = V_MOV_B32_e32 %SGPR5, %EXEC %VGPR5 = V_MAD_F32 %VGPR2, %VGPR6, %VGPR5, 0, 0, 0, 0, %EXEC %SGPR5 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 11; mem:LD4[] S_WAITCNT 127 %VGPR6 = V_MOV_B32_e32 %SGPR5, %EXEC %VGPR5 = V_MAD_F32 %VGPR3, %VGPR6, %VGPR5, 0, 0, 0, 0, %EXEC %VGPR5 = V_MUL_F32_e32 %SGPR4, %VGPR5, %EXEC %SGPR5 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 5; mem:LD4[] S_WAITCNT 127 %VGPR6 = V_MOV_B32_e32 %SGPR5, %EXEC %VGPR6 = V_MUL_F32_e64 %VGPR1, %VGPR6, 0, 0, 0, 0, %EXEC %SGPR5 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 4; mem:LD4[] S_WAITCNT 127 %VGPR7 = V_MOV_B32_e32 %SGPR5, %EXEC %VGPR6 = V_MAD_F32 %VGPR0, %VGPR7, %VGPR6, 0, 0, 0, 0, %EXEC %SGPR5 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 6; mem:LD4[] S_WAITCNT 127 %VGPR7 = V_MOV_B32_e32 %SGPR5, %EXEC %VGPR6 = V_MAD_F32 %VGPR2, %VGPR7, %VGPR6, 0, 0, 0, 0, %EXEC %SGPR5 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 7; mem:LD4[] S_WAITCNT 127 %VGPR7 = V_MOV_B32_e32 %SGPR5, %EXEC %VGPR6 = V_MAD_F32 %VGPR3, %VGPR7, %VGPR6, 0, 0, 0, 0, %EXEC %VGPR6 = V_MUL_F32_e32 %SGPR4, %VGPR6, %EXEC %SGPR5 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1; mem:LD4[] S_WAITCNT 127 %VGPR7 = V_MOV_B32_e32 %SGPR5, %EXEC %VGPR7 = V_MUL_F32_e64 %VGPR1, %VGPR7, 0, 0, 0, 0, %EXEC %SGPR5 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 0; mem:LD4[] S_WAITCNT 127 %VGPR8 = V_MOV_B32_e32 %SGPR5, %EXEC %VGPR7 = V_MAD_F32 %VGPR0, %VGPR8, %VGPR7, 0, 0, 0, 0, %EXEC %SGPR5 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2; mem:LD4[] S_WAITCNT 127 %VGPR8 = V_MOV_B32_e32 %SGPR5, %EXEC %VGPR7 = V_MAD_F32 %VGPR2, %VGPR8, %VGPR7, 0, 0, 0, 0, %EXEC %SGPR0 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 3; mem:LD4[] S_WAITCNT 127 %VGPR8 = V_MOV_B32_e32 %SGPR0, %EXEC %VGPR0 = V_MAD_F32 %VGPR3, %VGPR8, %VGPR7, 0, 0, 0, 0, %EXEC, %VGPR0_VGPR1_VGPR2_VGPR3 %VGPR0 = V_MUL_F32_e32 %SGPR4, %VGPR0, %EXEC EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR6, %VGPR5, %VGPR4, %EXEC S_ENDPGM # End machine code for function main. Shader Disassembly: S_LOAD_DWORDX4 s[8:11], s[6:7], 8 ; C0840708 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[1:4], s[8:11][v0] + 0 ; E00C2000 80020100 S_LOAD_DWORDX4 s[0:3], s[0:1], 0 ; C0800100 S_WAITCNT vmcnt(0) lgkmcnt(0) ; BF8C0070 S_BUFFER_LOAD_DWORD s4, s[0:3], 18 ; C2020112 S_WAITCNT lgkmcnt(0) ; BF8C007F V_CMP_GE_F32_e64 s[4:5], s4, 0.000000e+00, 0, 0, 0, 0 ; D00C0004 02010004 S_BUFFER_LOAD_DWORD s8, s[0:3], 23 ; C2040117 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v5, s8 ; 7E0A0208 V_CNDMASK_B32_e64 v5, v5, v4, s[4:5], 0, 0, 0, 0 ; D2000005 00120905 S_BUFFER_LOAD_DWORD s8, s[0:3], 22 ; C2040116 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v6, s8 ; 7E0C0208 V_CNDMASK_B32_e64 v6, v6, v1, s[4:5], 0, 0, 0, 0 ; D2000006 00120306 V_LOG_F32_e32 v7, v6 ; 7E0E4F06 S_BUFFER_LOAD_DWORD s8, s[0:3], 16 ; C2040110 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_LEGACY_F32_e32 v7, s8, v7 ; 0E0E0E08 V_EXP_F32_e32 v7, v7 ; 7E0E4B07 S_BUFFER_LOAD_DWORD s9, s[0:3], 17 ; C2048111 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v7, s9, v7 ; 100E0E09 S_BUFFER_LOAD_DWORD s10, s[0:3], 21 ; C2050115 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v8, s10 ; 7E10020A V_CNDMASK_B32_e64 v8, v8, v2, s[4:5], 0, 0, 0, 0 ; D2000008 00120508 V_LOG_F32_e32 v8, v8 ; 7E104F08 V_MUL_LEGACY_F32_e32 v8, s8, v8 ; 0E101008 V_EXP_F32_e32 v8, v8 ; 7E104B08 V_MUL_F32_e32 v8, s9, v8 ; 10101009 S_BUFFER_LOAD_DWORD s10, s[0:3], 20 ; C2050114 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v9, s10 ; 7E12020A V_CNDMASK_B32_e64 v1, v9, v3, s[4:5], 0, 0, 0, 0 ; D2000001 00120709 V_LOG_F32_e32 v1, v1 ; 7E024F01 V_MUL_LEGACY_F32_e32 v1, s8, v1 ; 0E020208 V_EXP_F32_e32 v1, v1 ; 7E024B01 V_MUL_F32_e32 v1, s9, v1 ; 10020209 EXP 15, 32, 0, 0, 0, v1, v8, v7, v5 ; F800020F 05070801 S_LOAD_DWORDX4 s[8:11], s[6:7], 4 ; C0840704 S_WAITCNT expcnt(0) lgkmcnt(0) ; BF8C000F BUFFER_LOAD_FORMAT_XYZW v[1:4], s[8:11][v0] + 0 ; E00C2000 80020100 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 33, 0, 0, 0, v1, v2, v6, v5 ; F800021F 05060201 S_LOAD_DWORDX4 s[4:7], s[6:7], 0 ; C0820700 S_WAITCNT expcnt(0) lgkmcnt(0) ; BF8C000F BUFFER_LOAD_FORMAT_XYZW v[0:3], s[4:7][v0] + 0 ; E00C2000 80010000 S_BUFFER_LOAD_DWORD s4, s[0:3], 13 ; C202010D S_WAITCNT vmcnt(0) lgkmcnt(0) ; BF8C0070 V_MOV_B32_e32 v4, s4 ; 7E080204 V_MUL_F32_e64 v4, v1, v4, 0, 0, 0, 0 ; D2100004 02020901 S_BUFFER_LOAD_DWORD s4, s[0:3], 12 ; C202010C S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v5, s4 ; 7E0A0204 V_MAD_F32 v4, v0, v5, v4, 0, 0, 0, 0 ; D2820004 04120B00 S_BUFFER_LOAD_DWORD s4, s[0:3], 14 ; C202010E S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v5, s4 ; 7E0A0204 V_MAD_F32 v4, v2, v5, v4, 0, 0, 0, 0 ; D2820004 04120B02 S_BUFFER_LOAD_DWORD s4, s[0:3], 15 ; C202010F S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v5, s4 ; 7E0A0204 V_MAD_F32 v4, v3, v5, v4, 0, 0, 0, 0 ; D2820004 04120B03 S_BUFFER_LOAD_DWORD s4, s[0:3], 19 ; C2020113 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v4, s4, v4 ; 10080804 S_BUFFER_LOAD_DWORD s5, s[0:3], 9 ; C2028109 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v5, s5 ; 7E0A0205 V_MUL_F32_e64 v5, v1, v5, 0, 0, 0, 0 ; D2100005 02020B01 S_BUFFER_LOAD_DWORD s5, s[0:3], 8 ; C2028108 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v6, s5 ; 7E0C0205 V_MAD_F32 v5, v0, v6, v5, 0, 0, 0, 0 ; D2820005 04160D00 S_BUFFER_LOAD_DWORD s5, s[0:3], 10 ; C202810A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v6, s5 ; 7E0C0205 V_MAD_F32 v5, v2, v6, v5, 0, 0, 0, 0 ; D2820005 04160D02 S_BUFFER_LOAD_DWORD s5, s[0:3], 11 ; C202810B S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v6, s5 ; 7E0C0205 V_MAD_F32 v5, v3, v6, v5, 0, 0, 0, 0 ; D2820005 04160D03 V_MUL_F32_e32 v5, s4, v5 ; 100A0A04 S_BUFFER_LOAD_DWORD s5, s[0:3], 5 ; C2028105 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v6, s5 ; 7E0C0205 V_MUL_F32_e64 v6, v1, v6, 0, 0, 0, 0 ; D2100006 02020D01 S_BUFFER_LOAD_DWORD s5, s[0:3], 4 ; C2028104 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v7, s5 ; 7E0E0205 V_MAD_F32 v6, v0, v7, v6, 0, 0, 0, 0 ; D2820006 041A0F00 S_BUFFER_LOAD_DWORD s5, s[0:3], 6 ; C2028106 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v7, s5 ; 7E0E0205 V_MAD_F32 v6, v2, v7, v6, 0, 0, 0, 0 ; D2820006 041A0F02 S_BUFFER_LOAD_DWORD s5, s[0:3], 7 ; C2028107 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v7, s5 ; 7E0E0205 V_MAD_F32 v6, v3, v7, v6, 0, 0, 0, 0 ; D2820006 041A0F03 V_MUL_F32_e32 v6, s4, v6 ; 100C0C04 S_BUFFER_LOAD_DWORD s5, s[0:3], 1 ; C2028101 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v7, s5 ; 7E0E0205 V_MUL_F32_e64 v7, v1, v7, 0, 0, 0, 0 ; D2100007 02020F01 S_BUFFER_LOAD_DWORD s5, s[0:3], 0 ; C2028100 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v8, s5 ; 7E100205 V_MAD_F32 v7, v0, v8, v7, 0, 0, 0, 0 ; D2820007 041E1100 S_BUFFER_LOAD_DWORD s5, s[0:3], 2 ; C2028102 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v8, s5 ; 7E100205 V_MAD_F32 v7, v2, v8, v7, 0, 0, 0, 0 ; D2820007 041E1102 S_BUFFER_LOAD_DWORD s0, s[0:3], 3 ; C2000103 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v8, s0 ; 7E100200 V_MAD_F32 v0, v3, v8, v7, 0, 0, 0, 0 ; D2820000 041E1103 V_MUL_F32_e32 v0, s4, v0 ; 10000004 EXP 15, 12, 0, 1, 0, v0, v6, v5, v4 ; F80008CF 04050600 S_ENDPGM ; BF810000 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[19], PERSPECTIVE DCL IN[1], GENERIC[20], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL CONST[0] DCL TEMP[0..2], LOCAL IMM[0] FLT32 { 32.0000, -16.0000, 1.0000, 0.0000} 0: MOV TEMP[0].xy, IN[1].xyyy 1: TEX TEMP[0], TEMP[0], SAMP[0], 2D 2: MAD TEMP[1].x, TEMP[0].wwww, IMM[0].xxxx, IMM[0].yyyy 3: EX2 TEMP[1].x, TEMP[1].xxxx 4: MUL TEMP[1].xyz, TEMP[0].xyzz, TEMP[1].xxxx 5: MOV TEMP[1].w, IMM[0].zzzz 6: FSGE TEMP[2].x, CONST[0].xxxx, IMM[0].wwww 7: UIF TEMP[2].xxxx :0 8: MOV TEMP[1], TEMP[1] 9: ELSE :0 10: MOV TEMP[1], TEMP[0] 11: ENDIF 12: MUL TEMP[0], TEMP[1], IN[0] 13: MOV OUT[0], TEMP[0] 14: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %21 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0 %22 = load <16 x i8> addrspace(2)* %21, !tbaa !0 %23 = call float @llvm.SI.load.const(<16 x i8> %22, i32 0) %24 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0 %25 = load <32 x i8> addrspace(2)* %24, !tbaa !0 %26 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0 %27 = load <16 x i8> addrspace(2)* %26, !tbaa !0 %28 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %4, <2 x i32> %6) %29 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %4, <2 x i32> %6) %30 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %4, <2 x i32> %6) %31 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %4, <2 x i32> %6) %32 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %4, <2 x i32> %6) %33 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %4, <2 x i32> %6) %34 = bitcast float %32 to i32 %35 = bitcast float %33 to i32 %36 = insertelement <2 x i32> undef, i32 %34, i32 0 %37 = insertelement <2 x i32> %36, i32 %35, i32 1 %38 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %37, <32 x i8> %25, <16 x i8> %27, i32 2) %39 = extractelement <4 x float> %38, i32 0 %40 = extractelement <4 x float> %38, i32 1 %41 = extractelement <4 x float> %38, i32 2 %42 = extractelement <4 x float> %38, i32 3 %43 = fmul float %42, 3.200000e+01 %44 = fadd float %43, -1.600000e+01 %45 = call float @llvm.AMDIL.exp.(float %44) %46 = fmul float %39, %45 %47 = fmul float %40, %45 %48 = fmul float %41, %45 %49 = fcmp oge float %23, 0.000000e+00 %50 = sext i1 %49 to i32 %51 = bitcast i32 %50 to float %52 = bitcast float %51 to i32 %53 = icmp ne i32 %52, 0 %. = select i1 %53, float %46, float %39 %.12 = select i1 %53, float %47, float %40 %.13 = select i1 %53, float %48, float %41 %.14 = select i1 %53, float 1.000000e+00, float %42 %54 = fmul float %., %28 %55 = fmul float %.12, %29 %56 = fmul float %.13, %30 %57 = fmul float %.14, %31 %58 = call i32 @llvm.SI.packf16(float %54, float %55) %59 = bitcast i32 %58 to float %60 = call i32 @llvm.SI.packf16(float %56, float %57) %61 = bitcast i32 %60 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %59, float %61, float %59, float %61) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1 ; Function Attrs: readnone declare float @llvm.AMDIL.exp.(float) #2 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } !0 = metadata !{metadata !"const", null, i32 1} # Machine code for function main: Post SSA, not tracking liveness Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR7 in %vreg4, %VGPR0 in %vreg5, %VGPR1 in %vreg6 BB#0: derived from LLVM BB %main_body Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR7 %VGPR0 %VGPR1 %EXEC = S_WQM_B64 %EXEC %VGPR1 = KILL %VGPR1, %VGPR0_VGPR1 %VGPR0 = KILL %VGPR0, %VGPR0_VGPR1, %VGPR0_VGPR1 %M0 = S_MOV_B32 %SGPR7 %VGPR3 = V_INTERP_P1_F32 %VGPR0, 1, 1, %M0, %EXEC, %VGPR2_VGPR3 %VGPR3 = V_INTERP_P2_F32 %VGPR3, %VGPR1, 1, 1, %M0, %EXEC, %VGPR2_VGPR3, %VGPR2_VGPR3 %VGPR2 = V_INTERP_P1_F32 %VGPR0, 0, 1, %M0, %EXEC, %VGPR2_VGPR3, %VGPR2_VGPR3 %VGPR2 = V_INTERP_P2_F32 %VGPR2, %VGPR1, 0, 1, %M0, %EXEC, %VGPR2_VGPR3, %VGPR2_VGPR3 %SGPR8_SGPR9_SGPR10_SGPR11 = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 0; mem:LD16[%29](align=8)(tbaa=!"const") %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 0; mem:LD32[%26](tbaa=!"const") S_WAITCNT 127 %VGPR2_VGPR3_VGPR4_VGPR5 = IMAGE_SAMPLE_V4_V2 15, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC %VGPR6 = V_MOV_B32_e32 -1.600000e+01, %EXEC %VGPR7 = V_MOV_B32_e32 3.200000e+01, %EXEC S_WAITCNT 1904 %VGPR6 = V_MAD_F32 %VGPR5, %VGPR7, %VGPR6, 0, 0, 0, 0, %EXEC %VGPR6 = V_EXP_F32_e32 %VGPR6, %EXEC %VGPR7 = V_MUL_F32_e32 %VGPR3, %VGPR6, %EXEC %SGPR0_SGPR1_SGPR2_SGPR3 = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1, 0; mem:LD16[%22](align=8)(tbaa=!"const") S_WAITCNT 127 %SGPR0 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 0; mem:LD4[] S_WAITCNT 127 %SGPR0_SGPR1 = V_CMP_GE_F32_e64 %SGPR0, 0.000000e+00, 0, 0, 0, 0, %EXEC %VGPR7 = V_CNDMASK_B32_e64 %VGPR3, %VGPR7, %SGPR0_SGPR1, 0, 0, 0, 0, %EXEC %VGPR8 = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0, %EXEC %VGPR8 = V_INTERP_P2_F32 %VGPR8, %VGPR1, 1, 0, %M0, %EXEC %VGPR7 = V_MUL_F32_e32 %VGPR7, %VGPR8, %EXEC %VGPR8 = V_MUL_F32_e32 %VGPR2, %VGPR6, %EXEC %VGPR8 = V_CNDMASK_B32_e64 %VGPR2, %VGPR8, %SGPR0_SGPR1, 0, 0, 0, 0, %EXEC %VGPR9 = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0, %EXEC %VGPR9 = V_INTERP_P2_F32 %VGPR9, %VGPR1, 0, 0, %M0, %EXEC %VGPR8 = V_MUL_F32_e32 %VGPR8, %VGPR9, %EXEC %VGPR7 = V_CVT_PKRTZ_F16_F32_e32 %VGPR8, %VGPR7, %EXEC %VGPR6 = V_MUL_F32_e32 %VGPR4, %VGPR6, %EXEC %VGPR6 = V_CNDMASK_B32_e64 %VGPR4, %VGPR6, %SGPR0_SGPR1, 0, 0, 0, 0, %EXEC %VGPR8 = V_INTERP_P1_F32 %VGPR0, 2, 0, %M0, %EXEC %VGPR8 = V_INTERP_P2_F32 %VGPR8, %VGPR1, 2, 0, %M0, %EXEC %VGPR6 = V_MUL_F32_e32 %VGPR6, %VGPR8, %EXEC %VGPR2 = V_CNDMASK_B32_e64 %VGPR5, 1.000000e+00, %SGPR0_SGPR1, 0, 0, 0, 0, %EXEC, %VGPR2_VGPR3_VGPR4_VGPR5 %VGPR3 = V_INTERP_P1_F32 %VGPR0, 3, 0, %M0, %EXEC %VGPR3 = V_INTERP_P2_F32 %VGPR3, %VGPR1, 3, 0, %M0, %EXEC, %VGPR0_VGPR1 %VGPR0 = V_MUL_F32_e32 %VGPR2, %VGPR3, %EXEC %VGPR0 = V_CVT_PKRTZ_F16_F32_e32 %VGPR6, %VGPR0, %EXEC EXP 15, 0, 1, 1, 1, %VGPR7, %VGPR0, %VGPR7, %VGPR0, %EXEC S_ENDPGM # End machine code for function main. Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s7 ; BEFC0307 V_INTERP_P1_F32 v3, v0, 1, 1, [m0] ; C80C0500 V_INTERP_P2_F32 v3, [v3], v1, 1, 1, [m0] ; C80D0501 V_INTERP_P1_F32 v2, v0, 0, 1, [m0] ; C8080400 V_INTERP_P2_F32 v2, [v2], v1, 0, 1, [m0] ; C8090401 S_LOAD_DWORDX4 s[8:11], s[2:3], 0 ; C0840300 S_LOAD_DWORDX8 s[12:19], s[4:5], 0 ; C0C60500 S_WAITCNT lgkmcnt(0) ; BF8C007F IMAGE_SAMPLE v[2:5], 15, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[12:19], s[8:11] ; F0800F00 00430202 V_MOV_B32_e32 v6, -1.600000e+01 ; 7E0C02FF C1800000 V_MOV_B32_e32 v7, 3.200000e+01 ; 7E0E02FF 42000000 S_WAITCNT vmcnt(0) ; BF8C0770 V_MAD_F32 v6, v5, v7, v6, 0, 0, 0, 0 ; D2820006 041A0F05 V_EXP_F32_e32 v6, v6 ; 7E0C4B06 V_MUL_F32_e32 v7, v3, v6 ; 100E0D03 S_LOAD_DWORDX4 s[0:3], s[0:1], 0 ; C0800100 S_WAITCNT lgkmcnt(0) ; BF8C007F S_BUFFER_LOAD_DWORD s0, s[0:3], 0 ; C2000100 S_WAITCNT lgkmcnt(0) ; BF8C007F V_CMP_GE_F32_e64 s[0:1], s0, 0.000000e+00, 0, 0, 0, 0 ; D00C0000 02010000 V_CNDMASK_B32_e64 v7, v3, v7, s[0:1], 0, 0, 0, 0 ; D2000007 00020F03 V_INTERP_P1_F32 v8, v0, 1, 0, [m0] ; C8200100 V_INTERP_P2_F32 v8, [v8], v1, 1, 0, [m0] ; C8210101 V_MUL_F32_e32 v7, v7, v8 ; 100E1107 V_MUL_F32_e32 v8, v2, v6 ; 10100D02 V_CNDMASK_B32_e64 v8, v2, v8, s[0:1], 0, 0, 0, 0 ; D2000008 00021102 V_INTERP_P1_F32 v9, v0, 0, 0, [m0] ; C8240000 V_INTERP_P2_F32 v9, [v9], v1, 0, 0, [m0] ; C8250001 V_MUL_F32_e32 v8, v8, v9 ; 10101308 V_CVT_PKRTZ_F16_F32_e32 v7, v8, v7 ; 5E0E0F08 V_MUL_F32_e32 v6, v4, v6 ; 100C0D04 V_CNDMASK_B32_e64 v6, v4, v6, s[0:1], 0, 0, 0, 0 ; D2000006 00020D04 V_INTERP_P1_F32 v8, v0, 2, 0, [m0] ; C8200200 V_INTERP_P2_F32 v8, [v8], v1, 2, 0, [m0] ; C8210201 V_MUL_F32_e32 v6, v6, v8 ; 100C1106 V_CNDMASK_B32_e64 v2, v5, 1.000000e+00, s[0:1], 0, 0, 0, 0 ; D2000002 0001E505 V_INTERP_P1_F32 v3, v0, 3, 0, [m0] ; C80C0300 V_INTERP_P2_F32 v3, [v3], v1, 3, 0, [m0] ; C80D0301 V_MUL_F32_e32 v0, v2, v3 ; 10000702 V_CVT_PKRTZ_F16_F32_e32 v0, v6, v0 ; 5E000106 EXP 15, 0, 1, 1, 1, v7, v0, v7, v0 ; F8001C0F 00070007 S_ENDPGM ; BF810000 INF: INF: Gfx API: OpenGL INF: Resolution: 1680 x 1050 INF: Vendor: ATI (0x1002) INF: Driver: X.Org (0x683D) INF: Renderer: Gallium 0.4 on AMD CAPE VERDE INF: Version: 3.0 Mesa 10.1.0-devel (git-751e869) INF: Video memory size: 512 MB INF: Available for textures: 512 MB INF: Active GPU(s): 1 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %21 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %4) %22 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %4) %23 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %4) %24 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %4) %25 = call i32 @llvm.SI.packf16(float %21, float %22) %26 = bitcast i32 %25 to float %27 = call i32 @llvm.SI.packf16(float %23, float %24) %28 = bitcast i32 %27 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %26, float %28, float %26, float %28) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } # Machine code for function main: Post SSA, not tracking liveness Function Live Ins: %SGPR7 in %vreg4 BB#0: derived from LLVM BB %main_body Live Ins: %SGPR7 %EXEC = S_WQM_B64 %EXEC %M0 = S_MOV_B32 %SGPR7 %VGPR0 = V_INTERP_MOV_F32 2, 3, 0, %M0, %EXEC %VGPR1 = V_INTERP_MOV_F32 2, 2, 0, %M0, %EXEC %VGPR0 = V_CVT_PKRTZ_F16_F32_e32 %VGPR1, %VGPR0, %EXEC %VGPR1 = V_INTERP_MOV_F32 2, 1, 0, %M0, %EXEC %VGPR2 = V_INTERP_MOV_F32 2, 0, 0, %M0, %EXEC %VGPR1 = V_CVT_PKRTZ_F16_F32_e32 %VGPR2, %VGPR1, %EXEC EXP 15, 0, 1, 1, 1, %VGPR1, %VGPR0, %VGPR1, %VGPR0, %EXEC S_ENDPGM # End machine code for function main. Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s7 ; BEFC0307 V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302 V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202 V_CVT_PKRTZ_F16_F32_e32 v0, v1, v0 ; 5E000101 V_INTERP_MOV_F32 v1, P0, 1, 0, [m0] ; C8060102 V_INTERP_MOV_F32 v2, P0, 0, 0, [m0] ; C80A0002 V_CVT_PKRTZ_F16_F32_e32 v1, v2, v1 ; 5E020302 EXP 15, 0, 1, 1, 1, v1, v0, v1, v0 ; F8001C0F 00010001 S_ENDPGM ; BF810000 WRN: Display driver is too old, please update it ASAP! INF: SysMessage: Display driver is too old or version cannot be determined. INF: Press OK to update driver, or Cancel to continue. INF: Fullscreen on primary display FRAG 0: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) ret void } declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32) attributes #0 = { "ShaderType"="0" } # Machine code for function main: Post SSA, not tracking liveness BB#0: derived from LLVM BB %main_body %VGPR0 = V_MOV_B32_e32 0, %EXEC EXP 0, 0, 0, 1, 1, %VGPR0, %VGPR0, %VGPR0, %VGPR0, %EXEC S_ENDPGM # End machine code for function main. Shader Disassembly: V_MOV_B32_e32 v0, 0 ; 7E000280 EXP 0, 0, 0, 1, 1, v0, v0, v0, v0 ; F8001800 00000000 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %21 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %4) %22 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %4) %23 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %4) %24 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %4) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %21, float %22, float %23, float %24) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } # Machine code for function main: Post SSA, not tracking liveness Function Live Ins: %SGPR7 in %vreg4 BB#0: derived from LLVM BB %main_body Live Ins: %SGPR7 %EXEC = S_WQM_B64 %EXEC %M0 = S_MOV_B32 %SGPR7 %VGPR0 = V_INTERP_MOV_F32 2, 3, 0, %M0, %EXEC %VGPR1 = V_INTERP_MOV_F32 2, 2, 0, %M0, %EXEC %VGPR2 = V_INTERP_MOV_F32 2, 1, 0, %M0, %EXEC %VGPR3 = V_INTERP_MOV_F32 2, 0, 0, %M0, %EXEC EXP 15, 0, 0, 1, 1, %VGPR3, %VGPR2, %VGPR1, %VGPR0, %EXEC S_ENDPGM # End machine code for function main. Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s7 ; BEFC0307 V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302 V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202 V_INTERP_MOV_F32 v2, P0, 1, 0, [m0] ; C80A0102 V_INTERP_MOV_F32 v3, P0, 0, 0, [m0] ; C80E0002 EXP 15, 0, 0, 1, 1, v3, v2, v1, v0 ; F800180F 00010203 S_ENDPGM ; BF810000 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %21 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %4) %22 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %4) %23 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %4) %24 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %4) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %21, float %22, float %23, float %24) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } # Machine code for function main: Post SSA, not tracking liveness Function Live Ins: %SGPR7 in %vreg4 BB#0: derived from LLVM BB %main_body Live Ins: %SGPR7 %EXEC = S_WQM_B64 %EXEC %M0 = S_MOV_B32 %SGPR7 %VGPR0 = V_INTERP_MOV_F32 2, 3, 0, %M0, %EXEC %VGPR1 = V_INTERP_MOV_F32 2, 2, 0, %M0, %EXEC %VGPR2 = V_INTERP_MOV_F32 2, 1, 0, %M0, %EXEC %VGPR3 = V_INTERP_MOV_F32 2, 0, 0, %M0, %EXEC EXP 15, 0, 0, 1, 1, %VGPR3, %VGPR2, %VGPR1, %VGPR0, %EXEC S_ENDPGM # End machine code for function main. Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s7 ; BEFC0307 V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302 V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202 V_INTERP_MOV_F32 v2, P0, 1, 0, [m0] ; C80A0102 V_INTERP_MOV_F32 v3, P0, 0, 0, [m0] ; C80E0002 EXP 15, 0, 0, 1, 1, v3, v2, v1, v0 ; F800180F 00010203 S_ENDPGM ; BF810000 VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] 0: MOV OUT[0], IN[0] 1: MOV OUT[1], IN[1] 2: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0 %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0 %12 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %11, i32 0, i32 %6) %13 = extractelement <4 x float> %12, i32 0 %14 = extractelement <4 x float> %12, i32 1 %15 = extractelement <4 x float> %12, i32 2 %16 = extractelement <4 x float> %12, i32 3 %17 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 1 %18 = load <16 x i8> addrspace(2)* %17, !tbaa !0 %19 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %18, i32 0, i32 %6) %20 = extractelement <4 x float> %19, i32 0 %21 = extractelement <4 x float> %19, i32 1 %22 = extractelement <4 x float> %19, i32 2 %23 = extractelement <4 x float> %19, i32 3 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %20, float %21, float %22, float %23) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %13, float %14, float %15, float %16) ret void } ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} # Machine code for function main: Post SSA, not tracking liveness Function Live Ins: %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg6 BB#0: derived from LLVM BB %main_body Live Ins: %SGPR6_SGPR7 %VGPR0 %SGPR0_SGPR1_SGPR2_SGPR3 = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%20](align=8)(tbaa=!"const") S_WAITCNT 127 %VGPR1_VGPR2_VGPR3_VGPR4 = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR0, 0, %EXEC S_WAITCNT 1904 EXP 15, 32, 0, 0, 0, %VGPR1, %VGPR2, %VGPR3, %VGPR4, %EXEC, %VGPR1_VGPR2_VGPR3_VGPR4 %SGPR0_SGPR1_SGPR2_SGPR3 = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 0; mem:LD16[%11](align=8)(tbaa=!"const") S_WAITCNT 15 %VGPR0_VGPR1_VGPR2_VGPR3 = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR0, 0, %EXEC S_WAITCNT 1904 EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR1, %VGPR2, %VGPR3, %EXEC, %VGPR0_VGPR1_VGPR2_VGPR3 S_ENDPGM # End machine code for function main. Shader Disassembly: S_LOAD_DWORDX4 s[0:3], s[6:7], 4 ; C0800704 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[1:4], s[0:3][v0] + 0 ; E00C2000 80000100 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 32, 0, 0, 0, v1, v2, v3, v4 ; F800020F 04030201 S_LOAD_DWORDX4 s[0:3], s[6:7], 0 ; C0800700 S_WAITCNT expcnt(0) lgkmcnt(0) ; BF8C000F BUFFER_LOAD_FORMAT_XYZW v[0:3], s[0:3][v0] + 0 ; E00C2000 80000000 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 12, 0, 1, 0, v0, v1, v2, v3 ; F80008CF 03020100 S_ENDPGM ; BF810000 VERT DCL IN[0] DCL OUT[0], POSITION 0: MOV OUT[0], IN[0] 1: END STREAMOUT 0: BUF0[0..0] <- OUT[0].x ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %13 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 0 %14 = load <16 x i8> addrspace(2)* %13, !tbaa !0 %15 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0 %16 = load <16 x i8> addrspace(2)* %15, !tbaa !0 %17 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %16, i32 0, i32 %9) %18 = extractelement <4 x float> %17, i32 0 %19 = extractelement <4 x float> %17, i32 1 %20 = extractelement <4 x float> %17, i32 2 %21 = extractelement <4 x float> %17, i32 3 %22 = lshr i32 %6, 16 %23 = and i32 %22, 127 %24 = call i32 @llvm.SI.tid() %25 = icmp ult i32 %24, %23 br i1 %25, label %if-true-block, label %endif-block if-true-block: ; preds = %main_body %26 = add i32 %7, %24 %27 = mul i32 %8, 4 %28 = mul i32 %26, 4 %29 = add i32 %28, %27 %30 = bitcast float %18 to i32 call void @llvm.SI.tbuffer.store.i32(<16 x i8> %14, i32 %30, i32 1, i32 %29, i32 0, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0) br label %endif-block endif-block: ; preds = %main_body, %if-true-block call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %18, float %19, float %20, float %21) ret void } ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 ; Function Attrs: readnone declare i32 @llvm.SI.tid() #2 declare void @llvm.SI.tbuffer.store.i32(<16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32) declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } !0 = metadata !{metadata !"const", null, i32 1} # Machine code for function main: Post SSA, not tracking liveness Function Live Ins: %SGPR6_SGPR7 in %vreg7, %SGPR8_SGPR9 in %vreg8, %SGPR11 in %vreg10, %SGPR12 in %vreg11, %SGPR13 in %vreg12, %VGPR0 in %vreg13 BB#0: derived from LLVM BB %main_body Live Ins: %SGPR6_SGPR7 %SGPR8_SGPR9 %SGPR11 %SGPR12 %SGPR13 %VGPR0 %SGPR0_SGPR1_SGPR2_SGPR3 = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 0; mem:LD16[%14](align=8)(tbaa=!"const") S_WAITCNT 127 %VGPR0_VGPR1_VGPR2_VGPR3 = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR0, 0, %EXEC %SGPR0 = S_LSHR_B32 %SGPR11, 16 %VGPR4 = V_MOV_B32_e32 127, %EXEC %VGPR5 = V_AND_B32_e32 %SGPR0, %VGPR4, %EXEC %VGPR4 = V_MBCNT_LO_U32_B32_e64 -1, 0, 0, 0, 0, 0, %EXEC %VGPR4 = V_MBCNT_HI_U32_B32_e32 -1, %VGPR4, %EXEC %SGPR0_SGPR1 = V_CMP_LT_U32_e64 %VGPR4, %VGPR5, 0, 0, 0, 0, %EXEC S_WAITCNT 1904 %SGPR0_SGPR1 = S_AND_SAVEEXEC_B64 %SGPR0_SGPR1, %EXEC, %EXEC %SGPR0_SGPR1 = S_XOR_B64 %EXEC, %SGPR0_SGPR1 Successors according to CFG: BB#1(16) BB#2(16) BB#1: derived from LLVM BB %if-true-block Live Ins: %VGPR0_VGPR1_VGPR2_VGPR3 %SGPR8_SGPR9 %SGPR12 %SGPR13 %SGPR0_SGPR1 %VGPR4 Predecessors according to CFG: BB#0 %VGPR4 = V_ADD_I32_e32 %SGPR12, %VGPR4, %EXEC, %VCC %VGPR4 = V_LSHLREV_B32_e32 2, %VGPR4, %EXEC %SGPR2 = S_LSHL_B32 %SGPR13, 2 %VGPR4 = V_ADD_I32_e32 %SGPR2, %VGPR4, %EXEC, %VCC %SGPR4_SGPR5_SGPR6_SGPR7 = S_LOAD_DWORDX4_IMM %SGPR8_SGPR9, 0; mem:LD16[%27](align=8)(tbaa=!"const") S_WAITCNT 127 TBUFFER_STORE_FORMAT_X %VGPR0, 0, -1, 0, -1, 0, 4, 4, %VGPR4, %SGPR4_SGPR5_SGPR6_SGPR7, -1, 0, 0, %EXEC S_WAITCNT 1792 Successors according to CFG: BB#2 BB#2: derived from LLVM BB %endif-block Live Ins: %VGPR0_VGPR1_VGPR2_VGPR3 %SGPR0_SGPR1 Predecessors according to CFG: BB#0 BB#1 %EXEC = S_OR_B64 %EXEC, %SGPR0_SGPR1 EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR1, %VGPR2, %VGPR3, %EXEC, %VGPR0_VGPR1_VGPR2_VGPR3 S_ENDPGM # End machine code for function main. Shader Disassembly: S_LOAD_DWORDX4 s[0:3], s[6:7], 0 ; C0800700 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[0:3], s[0:3][v0] + 0 ; E00C2000 80000000 S_LSHR_B32 s0, s11, 16 ; 9000900B V_MOV_B32_e32 v4, 127 ; 7E0802FF 0000007F V_AND_B32_e32 v5, s0, v4 ; 360A0800 V_MBCNT_LO_U32_B32_e64 v4, -1, 0, 0, 0, 0, 0 ; D2460004 020100C1 V_MBCNT_HI_U32_B32_e32 v4, -1, v4 ; 480808C1 V_CMP_LT_U32_e64 s[0:1], v4, v5, 0, 0, 0, 0 ; D1820000 02020B04 S_WAITCNT vmcnt(0) ; BF8C0770 S_AND_SAVEEXEC_B64 s[0:1], s[0:1] ; BE802400 S_XOR_B64 s[0:1], exec, s[0:1] ; 8980007E V_ADD_I32_e32 v4, s12, v4 ; 4A08080C V_LSHLREV_B32_e32 v4, 2, v4 ; 34080882 S_LSHL_B32 s2, s13, 2 ; 8F02820D V_ADD_I32_e32 v4, s2, v4 ; 4A080802 S_LOAD_DWORDX4 s[4:7], s[8:9], 0 ; C0820900 S_WAITCNT lgkmcnt(0) ; BF8C007F TBUFFER_STORE_FORMAT_X v0, 0, -1, 0, -1, 0, 4, 4, v4, s[4:7], -1, 0, 0 ; EA245000 80410004 S_WAITCNT vmcnt(0) expcnt(0) ; BF8C0700 S_OR_B64 exec, exec, s[0:1] ; 88FE007E EXP 15, 12, 0, 1, 0, v0, v1, v2, v3 ; F80008CF 03020100 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[0], CONSTANT 0: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } # Machine code for function main: Post SSA, not tracking liveness BB#0: derived from LLVM BB %main_body %VGPR0 = V_MOV_B32_e32 0, %EXEC EXP 0, 0, 0, 1, 1, %VGPR0, %VGPR0, %VGPR0, %VGPR0, %EXEC S_ENDPGM # End machine code for function main. Shader Disassembly: V_MOV_B32_e32 v0, 0 ; 7E000280 EXP 0, 0, 0, 1, 1, v0, v0, v0, v0 ; F8001800 00000000 S_ENDPGM ; BF810000 WRN: [OpenGL] "GL_ARB_get_program_binary" extension is present but not used because no binary formats are exposed. WRN: [OpenGL] Unable to determine VRAM size... assuming 512 MB. FRAG DCL IN[0], GENERIC[0], LINEAR DCL OUT[0], COLOR DCL SAMP[0] 0: TEX OUT[0], IN[0], SAMP[0], 2D 1: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %21 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0 %22 = load <32 x i8> addrspace(2)* %21, !tbaa !0 %23 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0 %24 = load <16 x i8> addrspace(2)* %23, !tbaa !0 %25 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %4, <2 x i32> %10) %26 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %4, <2 x i32> %10) %27 = bitcast float %25 to i32 %28 = bitcast float %26 to i32 %29 = insertelement <2 x i32> undef, i32 %27, i32 0 %30 = insertelement <2 x i32> %29, i32 %28, i32 1 %31 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %30, <32 x i8> %22, <16 x i8> %24, i32 2) %32 = extractelement <4 x float> %31, i32 0 %33 = extractelement <4 x float> %31, i32 1 %34 = extractelement <4 x float> %31, i32 2 %35 = extractelement <4 x float> %31, i32 3 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %32, float %33, float %34, float %35) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} # Machine code for function main: Post SSA, not tracking liveness Function Live Ins: %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR7 in %vreg4, %VGPR0 in %vreg5, %VGPR1 in %vreg6 BB#0: derived from LLVM BB %main_body Live Ins: %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR7 %VGPR0 %VGPR1 %EXEC = S_WQM_B64 %EXEC %VGPR1 = KILL %VGPR1, %VGPR0_VGPR1 %VGPR0 = KILL %VGPR0, %VGPR0_VGPR1, %VGPR0_VGPR1 %M0 = S_MOV_B32 %SGPR7 %VGPR3 = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0, %EXEC, %VGPR2_VGPR3 %VGPR3 = V_INTERP_P2_F32 %VGPR3, %VGPR1, 1, 0, %M0, %EXEC, %VGPR2_VGPR3, %VGPR2_VGPR3 %VGPR2 = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0, %EXEC, %VGPR2_VGPR3, %VGPR2_VGPR3 %VGPR2 = V_INTERP_P2_F32 %VGPR2, %VGPR1, 0, 0, %M0, %EXEC, %VGPR0_VGPR1, %VGPR2_VGPR3, %VGPR2_VGPR3 %SGPR0_SGPR1_SGPR2_SGPR3 = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 0; mem:LD16[%24](align=8)(tbaa=!"const") %SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11 = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 0; mem:LD32[%21](tbaa=!"const") S_WAITCNT 127 %VGPR0_VGPR1_VGPR2_VGPR3 = IMAGE_SAMPLE_V4_V2 15, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3, %SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11, %SGPR0_SGPR1_SGPR2_SGPR3, %EXEC S_WAITCNT 1904 EXP 15, 0, 0, 1, 1, %VGPR0, %VGPR1, %VGPR2, %VGPR3, %EXEC, %VGPR0_VGPR1_VGPR2_VGPR3 S_ENDPGM # End machine code for function main. Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s7 ; BEFC0307 V_INTERP_P1_F32 v3, v0, 1, 0, [m0] ; C80C0100 V_INTERP_P2_F32 v3, [v3], v1, 1, 0, [m0] ; C80D0101 V_INTERP_P1_F32 v2, v0, 0, 0, [m0] ; C8080000 V_INTERP_P2_F32 v2, [v2], v1, 0, 0, [m0] ; C8090001 S_LOAD_DWORDX4 s[0:3], s[2:3], 0 ; C0800300 S_LOAD_DWORDX8 s[4:11], s[4:5], 0 ; C0C20500 S_WAITCNT lgkmcnt(0) ; BF8C007F IMAGE_SAMPLE v[0:3], 15, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[4:11], s[0:3] ; F0800F00 00010002 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 0, 0, 1, 1, v0, v1, v2, v3 ; F800180F 03020100 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[0], LINEAR DCL OUT[0], COLOR DCL SAMP[0] 0: TEX OUT[0], IN[0], SAMP[0], 2D 1: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %21 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0 %22 = load <32 x i8> addrspace(2)* %21, !tbaa !0 %23 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0 %24 = load <16 x i8> addrspace(2)* %23, !tbaa !0 %25 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %4, <2 x i32> %10) %26 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %4, <2 x i32> %10) %27 = bitcast float %25 to i32 %28 = bitcast float %26 to i32 %29 = insertelement <2 x i32> undef, i32 %27, i32 0 %30 = insertelement <2 x i32> %29, i32 %28, i32 1 %31 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %30, <32 x i8> %22, <16 x i8> %24, i32 2) %32 = extractelement <4 x float> %31, i32 0 %33 = extractelement <4 x float> %31, i32 1 %34 = extractelement <4 x float> %31, i32 2 %35 = extractelement <4 x float> %31, i32 3 %36 = call i32 @llvm.SI.packf16(float %32, float %33) %37 = bitcast i32 %36 to float %38 = call i32 @llvm.SI.packf16(float %34, float %35) %39 = bitcast i32 %38 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %37, float %39, float %37, float %39) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} # Machine code for function main: Post SSA, not tracking liveness Function Live Ins: %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR7 in %vreg4, %VGPR0 in %vreg5, %VGPR1 in %vreg6 BB#0: derived from LLVM BB %main_body Live Ins: %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR7 %VGPR0 %VGPR1 %EXEC = S_WQM_B64 %EXEC %VGPR1 = KILL %VGPR1, %VGPR0_VGPR1 %VGPR0 = KILL %VGPR0, %VGPR0_VGPR1, %VGPR0_VGPR1 %M0 = S_MOV_B32 %SGPR7 %VGPR3 = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0, %EXEC, %VGPR2_VGPR3 %VGPR3 = V_INTERP_P2_F32 %VGPR3, %VGPR1, 1, 0, %M0, %EXEC, %VGPR2_VGPR3, %VGPR2_VGPR3 %VGPR2 = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0, %EXEC, %VGPR2_VGPR3, %VGPR2_VGPR3 %VGPR2 = V_INTERP_P2_F32 %VGPR2, %VGPR1, 0, 0, %M0, %EXEC, %VGPR0_VGPR1, %VGPR2_VGPR3, %VGPR2_VGPR3 %SGPR0_SGPR1_SGPR2_SGPR3 = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 0; mem:LD16[%24](align=8)(tbaa=!"const") %SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11 = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 0; mem:LD32[%21](tbaa=!"const") S_WAITCNT 127 %VGPR0_VGPR1_VGPR2_VGPR3 = IMAGE_SAMPLE_V4_V2 15, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3, %SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11, %SGPR0_SGPR1_SGPR2_SGPR3, %EXEC S_WAITCNT 1904 %VGPR4 = V_CVT_PKRTZ_F16_F32_e32 %VGPR2, %VGPR3, %EXEC %VGPR0 = V_CVT_PKRTZ_F16_F32_e32 %VGPR0, %VGPR1, %EXEC, %VGPR0_VGPR1_VGPR2_VGPR3 EXP 15, 0, 1, 1, 1, %VGPR0, %VGPR4, %VGPR0, %VGPR4, %EXEC S_ENDPGM # End machine code for function main. Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s7 ; BEFC0307 V_INTERP_P1_F32 v3, v0, 1, 0, [m0] ; C80C0100 V_INTERP_P2_F32 v3, [v3], v1, 1, 0, [m0] ; C80D0101 V_INTERP_P1_F32 v2, v0, 0, 0, [m0] ; C8080000 V_INTERP_P2_F32 v2, [v2], v1, 0, 0, [m0] ; C8090001 S_LOAD_DWORDX4 s[0:3], s[2:3], 0 ; C0800300 S_LOAD_DWORDX8 s[4:11], s[4:5], 0 ; C0C20500 S_WAITCNT lgkmcnt(0) ; BF8C007F IMAGE_SAMPLE v[0:3], 15, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[4:11], s[0:3] ; F0800F00 00010002 S_WAITCNT vmcnt(0) ; BF8C0770 V_CVT_PKRTZ_F16_F32_e32 v4, v2, v3 ; 5E080702 V_CVT_PKRTZ_F16_F32_e32 v0, v0, v1 ; 5E000300 EXP 15, 0, 1, 1, 1, v0, v4, v0, v4 ; F8001C0F 04000400 S_ENDPGM ; BF810000 INF: INF: Gfx API: OpenGL INF: Resolution: 1680 x 1050 INF: Vendor: ATI (0x1002) INF: Driver: X.Org (0x683D) INF: Renderer: Gallium 0.4 on AMD CAPE VERDE INF: Version: 3.0 Mesa 10.1.0-devel (git-751e869) INF: Video memory size: 512 MB INF: Available for textures: 512 MB INF: Active GPU(s): 1 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], COLOR, COLOR DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %21 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %4) %22 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %4) %23 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %4) %24 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %4) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %21, float %22, float %23, float %24) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } # Machine code for function main: Post SSA, not tracking liveness Function Live Ins: %SGPR7 in %vreg4 BB#0: derived from LLVM BB %main_body Live Ins: %SGPR7 %EXEC = S_WQM_B64 %EXEC %M0 = S_MOV_B32 %SGPR7 %VGPR0 = V_INTERP_MOV_F32 2, 3, 0, %M0, %EXEC %VGPR1 = V_INTERP_MOV_F32 2, 2, 0, %M0, %EXEC %VGPR2 = V_INTERP_MOV_F32 2, 1, 0, %M0, %EXEC %VGPR3 = V_INTERP_MOV_F32 2, 0, 0, %M0, %EXEC EXP 15, 0, 0, 1, 1, %VGPR3, %VGPR2, %VGPR1, %VGPR0, %EXEC S_ENDPGM # End machine code for function main. Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s7 ; BEFC0307 V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302 V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202 V_INTERP_MOV_F32 v2, P0, 1, 0, [m0] ; C80A0102 V_INTERP_MOV_F32 v3, P0, 0, 0, [m0] ; C80E0002 EXP 15, 0, 0, 1, 1, v3, v2, v1, v0 ; F800180F 00010203 S_ENDPGM ; BF810000 VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], COLOR DCL CONST[0..3] DCL TEMP[0] 0: MUL TEMP[0], IN[0].xxxx, CONST[0] 1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0] 2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0] 3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0] 4: MOV OUT[1], IN[1] 5: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0 %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0 %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0) %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4) %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8) %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12) %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16) %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20) %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24) %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28) %20 = call float @llvm.SI.load.const(<16 x i8> %11, i32 32) %21 = call float @llvm.SI.load.const(<16 x i8> %11, i32 36) %22 = call float @llvm.SI.load.const(<16 x i8> %11, i32 40) %23 = call float @llvm.SI.load.const(<16 x i8> %11, i32 44) %24 = call float @llvm.SI.load.const(<16 x i8> %11, i32 48) %25 = call float @llvm.SI.load.const(<16 x i8> %11, i32 52) %26 = call float @llvm.SI.load.const(<16 x i8> %11, i32 56) %27 = call float @llvm.SI.load.const(<16 x i8> %11, i32 60) %28 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0 %29 = load <16 x i8> addrspace(2)* %28, !tbaa !0 %30 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %29, i32 0, i32 %6) %31 = extractelement <4 x float> %30, i32 0 %32 = extractelement <4 x float> %30, i32 1 %33 = extractelement <4 x float> %30, i32 2 %34 = extractelement <4 x float> %30, i32 3 %35 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 1 %36 = load <16 x i8> addrspace(2)* %35, !tbaa !0 %37 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %36, i32 0, i32 %6) %38 = extractelement <4 x float> %37, i32 0 %39 = extractelement <4 x float> %37, i32 1 %40 = extractelement <4 x float> %37, i32 2 %41 = extractelement <4 x float> %37, i32 3 %42 = fmul float %31, %12 %43 = fmul float %31, %13 %44 = fmul float %31, %14 %45 = fmul float %31, %15 %46 = fmul float %32, %16 %47 = fadd float %46, %42 %48 = fmul float %32, %17 %49 = fadd float %48, %43 %50 = fmul float %32, %18 %51 = fadd float %50, %44 %52 = fmul float %32, %19 %53 = fadd float %52, %45 %54 = fmul float %33, %20 %55 = fadd float %54, %47 %56 = fmul float %33, %21 %57 = fadd float %56, %49 %58 = fmul float %33, %22 %59 = fadd float %58, %51 %60 = fmul float %33, %23 %61 = fadd float %60, %53 %62 = fmul float %34, %24 %63 = fadd float %62, %55 %64 = fmul float %34, %25 %65 = fadd float %64, %57 %66 = fmul float %34, %26 %67 = fadd float %66, %59 %68 = fmul float %34, %27 %69 = fadd float %68, %61 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %38, float %39, float %40, float %41) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %63, float %65, float %67, float %69) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} # Machine code for function main: Post SSA, not tracking liveness Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg6 BB#0: derived from LLVM BB %main_body Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0 %SGPR8_SGPR9_SGPR10_SGPR11 = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%40](align=8)(tbaa=!"const") S_WAITCNT 127 %VGPR1_VGPR2_VGPR3_VGPR4 = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR0, 0, %EXEC S_WAITCNT 1904 EXP 15, 32, 0, 0, 0, %VGPR1, %VGPR2, %VGPR3, %VGPR4, %EXEC, %VGPR1_VGPR2_VGPR3_VGPR4 %SGPR4_SGPR5_SGPR6_SGPR7 = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 0; mem:LD16[%31](align=8)(tbaa=!"const") S_WAITCNT 15 %VGPR0_VGPR1_VGPR2_VGPR3 = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7, %VGPR0, 0, %EXEC %SGPR0_SGPR1_SGPR2_SGPR3 = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1, 0; mem:LD16[%11](align=8)(tbaa=!"const") S_WAITCNT 112 %SGPR4 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 3; mem:LD4[] S_WAITCNT 127 %VGPR4 = V_MOV_B32_e32 %SGPR4, %EXEC %VGPR4 = V_MUL_F32_e64 %VGPR0, %VGPR4, 0, 0, 0, 0, %EXEC %SGPR4 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 7; mem:LD4[] S_WAITCNT 127 %VGPR5 = V_MOV_B32_e32 %SGPR4, %EXEC %VGPR4 = V_MAD_F32 %VGPR1, %VGPR5, %VGPR4, 0, 0, 0, 0, %EXEC %SGPR4 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 11; mem:LD4[] S_WAITCNT 127 %VGPR5 = V_MOV_B32_e32 %SGPR4, %EXEC %VGPR4 = V_MAD_F32 %VGPR2, %VGPR5, %VGPR4, 0, 0, 0, 0, %EXEC %SGPR4 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 15; mem:LD4[] S_WAITCNT 127 %VGPR5 = V_MOV_B32_e32 %SGPR4, %EXEC %VGPR4 = V_MAD_F32 %VGPR3, %VGPR5, %VGPR4, 0, 0, 0, 0, %EXEC %SGPR4 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2; mem:LD4[] S_WAITCNT 127 %VGPR5 = V_MOV_B32_e32 %SGPR4, %EXEC %VGPR5 = V_MUL_F32_e64 %VGPR0, %VGPR5, 0, 0, 0, 0, %EXEC %SGPR4 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 6; mem:LD4[] S_WAITCNT 127 %VGPR6 = V_MOV_B32_e32 %SGPR4, %EXEC %VGPR5 = V_MAD_F32 %VGPR1, %VGPR6, %VGPR5, 0, 0, 0, 0, %EXEC %SGPR4 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 10; mem:LD4[] S_WAITCNT 127 %VGPR6 = V_MOV_B32_e32 %SGPR4, %EXEC %VGPR5 = V_MAD_F32 %VGPR2, %VGPR6, %VGPR5, 0, 0, 0, 0, %EXEC %SGPR4 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 14; mem:LD4[] S_WAITCNT 127 %VGPR6 = V_MOV_B32_e32 %SGPR4, %EXEC %VGPR5 = V_MAD_F32 %VGPR3, %VGPR6, %VGPR5, 0, 0, 0, 0, %EXEC %SGPR4 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1; mem:LD4[] S_WAITCNT 127 %VGPR6 = V_MOV_B32_e32 %SGPR4, %EXEC %VGPR6 = V_MUL_F32_e64 %VGPR0, %VGPR6, 0, 0, 0, 0, %EXEC %SGPR4 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 5; mem:LD4[] S_WAITCNT 127 %VGPR7 = V_MOV_B32_e32 %SGPR4, %EXEC %VGPR6 = V_MAD_F32 %VGPR1, %VGPR7, %VGPR6, 0, 0, 0, 0, %EXEC %SGPR4 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 9; mem:LD4[] S_WAITCNT 127 %VGPR7 = V_MOV_B32_e32 %SGPR4, %EXEC %VGPR6 = V_MAD_F32 %VGPR2, %VGPR7, %VGPR6, 0, 0, 0, 0, %EXEC %SGPR4 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 13; mem:LD4[] S_WAITCNT 127 %VGPR7 = V_MOV_B32_e32 %SGPR4, %EXEC %VGPR6 = V_MAD_F32 %VGPR3, %VGPR7, %VGPR6, 0, 0, 0, 0, %EXEC %SGPR4 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 0; mem:LD4[] S_WAITCNT 127 %VGPR7 = V_MOV_B32_e32 %SGPR4, %EXEC %VGPR7 = V_MUL_F32_e64 %VGPR0, %VGPR7, 0, 0, 0, 0, %EXEC %SGPR4 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 4; mem:LD4[] S_WAITCNT 127 %VGPR8 = V_MOV_B32_e32 %SGPR4, %EXEC %VGPR7 = V_MAD_F32 %VGPR1, %VGPR8, %VGPR7, 0, 0, 0, 0, %EXEC %SGPR4 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 8; mem:LD4[] S_WAITCNT 127 %VGPR8 = V_MOV_B32_e32 %SGPR4, %EXEC %VGPR7 = V_MAD_F32 %VGPR2, %VGPR8, %VGPR7, 0, 0, 0, 0, %EXEC %SGPR0 = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 12; mem:LD4[] S_WAITCNT 127 %VGPR8 = V_MOV_B32_e32 %SGPR0, %EXEC %VGPR0 = V_MAD_F32 %VGPR3, %VGPR8, %VGPR7, 0, 0, 0, 0, %EXEC, %VGPR0_VGPR1_VGPR2_VGPR3 EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR6, %VGPR5, %VGPR4, %EXEC S_ENDPGM # End machine code for function main. Shader Disassembly: S_LOAD_DWORDX4 s[8:11], s[6:7], 4 ; C0840704 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[1:4], s[8:11][v0] + 0 ; E00C2000 80020100 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 32, 0, 0, 0, v1, v2, v3, v4 ; F800020F 04030201 S_LOAD_DWORDX4 s[4:7], s[6:7], 0 ; C0820700 S_WAITCNT expcnt(0) lgkmcnt(0) ; BF8C000F BUFFER_LOAD_FORMAT_XYZW v[0:3], s[4:7][v0] + 0 ; E00C2000 80010000 S_LOAD_DWORDX4 s[0:3], s[0:1], 0 ; C0800100 S_WAITCNT vmcnt(0) lgkmcnt(0) ; BF8C0070 S_BUFFER_LOAD_DWORD s4, s[0:3], 3 ; C2020103 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v4, s4 ; 7E080204 V_MUL_F32_e64 v4, v0, v4, 0, 0, 0, 0 ; D2100004 02020900 S_BUFFER_LOAD_DWORD s4, s[0:3], 7 ; C2020107 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v5, s4 ; 7E0A0204 V_MAD_F32 v4, v1, v5, v4, 0, 0, 0, 0 ; D2820004 04120B01 S_BUFFER_LOAD_DWORD s4, s[0:3], 11 ; C202010B S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v5, s4 ; 7E0A0204 V_MAD_F32 v4, v2, v5, v4, 0, 0, 0, 0 ; D2820004 04120B02 S_BUFFER_LOAD_DWORD s4, s[0:3], 15 ; C202010F S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v5, s4 ; 7E0A0204 V_MAD_F32 v4, v3, v5, v4, 0, 0, 0, 0 ; D2820004 04120B03 S_BUFFER_LOAD_DWORD s4, s[0:3], 2 ; C2020102 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v5, s4 ; 7E0A0204 V_MUL_F32_e64 v5, v0, v5, 0, 0, 0, 0 ; D2100005 02020B00 S_BUFFER_LOAD_DWORD s4, s[0:3], 6 ; C2020106 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v6, s4 ; 7E0C0204 V_MAD_F32 v5, v1, v6, v5, 0, 0, 0, 0 ; D2820005 04160D01 S_BUFFER_LOAD_DWORD s4, s[0:3], 10 ; C202010A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v6, s4 ; 7E0C0204 V_MAD_F32 v5, v2, v6, v5, 0, 0, 0, 0 ; D2820005 04160D02 S_BUFFER_LOAD_DWORD s4, s[0:3], 14 ; C202010E S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v6, s4 ; 7E0C0204 V_MAD_F32 v5, v3, v6, v5, 0, 0, 0, 0 ; D2820005 04160D03 S_BUFFER_LOAD_DWORD s4, s[0:3], 1 ; C2020101 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v6, s4 ; 7E0C0204 V_MUL_F32_e64 v6, v0, v6, 0, 0, 0, 0 ; D2100006 02020D00 S_BUFFER_LOAD_DWORD s4, s[0:3], 5 ; C2020105 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v7, s4 ; 7E0E0204 V_MAD_F32 v6, v1, v7, v6, 0, 0, 0, 0 ; D2820006 041A0F01 S_BUFFER_LOAD_DWORD s4, s[0:3], 9 ; C2020109 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v7, s4 ; 7E0E0204 V_MAD_F32 v6, v2, v7, v6, 0, 0, 0, 0 ; D2820006 041A0F02 S_BUFFER_LOAD_DWORD s4, s[0:3], 13 ; C202010D S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v7, s4 ; 7E0E0204 V_MAD_F32 v6, v3, v7, v6, 0, 0, 0, 0 ; D2820006 041A0F03 S_BUFFER_LOAD_DWORD s4, s[0:3], 0 ; C2020100 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v7, s4 ; 7E0E0204 V_MUL_F32_e64 v7, v0, v7, 0, 0, 0, 0 ; D2100007 02020F00 S_BUFFER_LOAD_DWORD s4, s[0:3], 4 ; C2020104 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v8, s4 ; 7E100204 V_MAD_F32 v7, v1, v8, v7, 0, 0, 0, 0 ; D2820007 041E1101 S_BUFFER_LOAD_DWORD s4, s[0:3], 8 ; C2020108 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v8, s4 ; 7E100204 V_MAD_F32 v7, v2, v8, v7, 0, 0, 0, 0 ; D2820007 041E1102 S_BUFFER_LOAD_DWORD s0, s[0:3], 12 ; C200010C S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v8, s0 ; 7E100200 V_MAD_F32 v0, v3, v8, v7, 0, 0, 0, 0 ; D2820000 041E1103 EXP 15, 12, 0, 1, 0, v0, v6, v5, v4 ; F80008CF 04050600 S_ENDPGM ; BF810000 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %21 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %4) %22 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %4) %23 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %4) %24 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %4) %25 = call i32 @llvm.SI.packf16(float %21, float %22) %26 = bitcast i32 %25 to float %27 = call i32 @llvm.SI.packf16(float %23, float %24) %28 = bitcast i32 %27 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %26, float %28, float %26, float %28) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } # Machine code for function main: Post SSA, not tracking liveness Function Live Ins: %SGPR7 in %vreg4 BB#0: derived from LLVM BB %main_body Live Ins: %SGPR7 %EXEC = S_WQM_B64 %EXEC %M0 = S_MOV_B32 %SGPR7 %VGPR0 = V_INTERP_MOV_F32 2, 3, 0, %M0, %EXEC %VGPR1 = V_INTERP_MOV_F32 2, 2, 0, %M0, %EXEC %VGPR0 = V_CVT_PKRTZ_F16_F32_e32 %VGPR1, %VGPR0, %EXEC %VGPR1 = V_INTERP_MOV_F32 2, 1, 0, %M0, %EXEC %VGPR2 = V_INTERP_MOV_F32 2, 0, 0, %M0, %EXEC %VGPR1 = V_CVT_PKRTZ_F16_F32_e32 %VGPR2, %VGPR1, %EXEC EXP 15, 0, 1, 1, 1, %VGPR1, %VGPR0, %VGPR1, %VGPR0, %EXEC S_ENDPGM # End machine code for function main. Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s7 ; BEFC0307 V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302 V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202 V_CVT_PKRTZ_F16_F32_e32 v0, v1, v0 ; 5E000101 V_INTERP_MOV_F32 v1, P0, 1, 0, [m0] ; C8060102 V_INTERP_MOV_F32 v2, P0, 0, 0, [m0] ; C80A0002 V_CVT_PKRTZ_F16_F32_e32 v1, v2, v1 ; 5E020302 EXP 15, 0, 1, 1, 1, v1, v0, v1, v0 ; F8001C0F 00010001 S_ENDPGM ; BF810000 INF: INF: Sfx API: OpenAL INF: Device: PulseAudio Default INF: Mixer frequency: 44100 Hz INF: Mixer voices: 64 INF: Max sound sources: 25 INF: Max total volume: 3 INF: Speaker config: (unknown) INF: Environment FX: not supported INF: INF: Connected gamepad 0 - A4TECH USB Device (/dev/input/js0) with 57 buttons and 37 axes. INF: Cannot send rumble effect to gamepad 0 FRAG DCL IN[0], GENERIC[0], LINEAR DCL OUT[0], COLOR DCL SAMP[0] 0: TEX OUT[0], IN[0], SAMP[0], 2D 1: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %21 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0 %22 = load <32 x i8> addrspace(2)* %21, !tbaa !0 %23 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0 %24 = load <16 x i8> addrspace(2)* %23, !tbaa !0 %25 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %4, <2 x i32> %10) %26 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %4, <2 x i32> %10) %27 = bitcast float %25 to i32 %28 = bitcast float %26 to i32 %29 = insertelement <2 x i32> undef, i32 %27, i32 0 %30 = insertelement <2 x i32> %29, i32 %28, i32 1 %31 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %30, <32 x i8> %22, <16 x i8> %24, i32 2) %32 = extractelement <4 x float> %31, i32 0 %33 = extractelement <4 x float> %31, i32 1 %34 = extractelement <4 x float> %31, i32 2 %35 = extractelement <4 x float> %31, i32 3 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %32, float %33, float %34, float %35) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} # Machine code for function main: Post SSA, not tracking liveness Function Live Ins: %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR7 in %vreg4, %VGPR0 in %vreg5, %VGPR1 in %vreg6 BB#0: derived from LLVM BB %main_body Live Ins: %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR7 %VGPR0 %VGPR1 %EXEC = S_WQM_B64 %EXEC %VGPR1 = KILL %VGPR1, %VGPR0_VGPR1 %VGPR0 = KILL %VGPR0, %VGPR0_VGPR1, %VGPR0_VGPR1 %M0 = S_MOV_B32 %SGPR7 %VGPR3 = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0, %EXEC, %VGPR2_VGPR3 %VGPR3 = V_INTERP_P2_F32 %VGPR3, %VGPR1, 1, 0, %M0, %EXEC, %VGPR2_VGPR3, %VGPR2_VGPR3 %VGPR2 = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0, %EXEC, %VGPR2_VGPR3, %VGPR2_VGPR3 %VGPR2 = V_INTERP_P2_F32 %VGPR2, %VGPR1, 0, 0, %M0, %EXEC, %VGPR0_VGPR1, %VGPR2_VGPR3, %VGPR2_VGPR3 %SGPR0_SGPR1_SGPR2_SGPR3 = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 0; mem:LD16[%24](align=8)(tbaa=!"const") %SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11 = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 0; mem:LD32[%21](tbaa=!"const") S_WAITCNT 127 %VGPR0_VGPR1_VGPR2_VGPR3 = IMAGE_SAMPLE_V4_V2 15, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3, %SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11, %SGPR0_SGPR1_SGPR2_SGPR3, %EXEC S_WAITCNT 1904 EXP 15, 0, 0, 1, 1, %VGPR0, %VGPR1, %VGPR2, %VGPR3, %EXEC, %VGPR0_VGPR1_VGPR2_VGPR3 S_ENDPGM # End machine code for function main. Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s7 ; BEFC0307 V_INTERP_P1_F32 v3, v0, 1, 0, [m0] ; C80C0100 V_INTERP_P2_F32 v3, [v3], v1, 1, 0, [m0] ; C80D0101 V_INTERP_P1_F32 v2, v0, 0, 0, [m0] ; C8080000 V_INTERP_P2_F32 v2, [v2], v1, 0, 0, [m0] ; C8090001 S_LOAD_DWORDX4 s[0:3], s[2:3], 0 ; C0800300 S_LOAD_DWORDX8 s[4:11], s[4:5], 0 ; C0C20500 S_WAITCNT lgkmcnt(0) ; BF8C007F IMAGE_SAMPLE v[0:3], 15, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[4:11], s[0:3] ; F0800F00 00010002 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 0, 0, 1, 1, v0, v1, v2, v3 ; F800180F 03020100 S_ENDPGM ; BF810000 INF: AutoDetect: No previous hardware values stored, adjusting settings automatically. INF: CPU efficiency: 3300 MHz * 2 cores = 5940 Mhz INF: ID: 0x683d; card: Radeon HD 8760/7700 series; quality: 4 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %21 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %4) %22 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %4) %23 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %4) %24 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %4) %25 = call i32 @llvm.SI.packf16(float %21, float %22) %26 = bitcast i32 %25 to float %27 = call i32 @llvm.SI.packf16(float %23, float %24) %28 = bitcast i32 %27 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %26, float %28, float %26, float %28) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } # Machine code for function main: Post SSA, not tracking liveness Function Live Ins: %SGPR7 in %vreg4 BB#0: derived from LLVM BB %main_body Live Ins: %SGPR7 %EXEC = S_WQM_B64 %EXEC %M0 = S_MOV_B32 %SGPR7 %VGPR0 = V_INTERP_MOV_F32 2, 3, 0, %M0, %EXEC %VGPR1 = V_INTERP_MOV_F32 2, 2, 0, %M0, %EXEC %VGPR0 = V_CVT_PKRTZ_F16_F32_e32 %VGPR1, %VGPR0, %EXEC %VGPR1 = V_INTERP_MOV_F32 2, 1, 0, %M0, %EXEC %VGPR2 = V_INTERP_MOV_F32 2, 0, 0, %M0, %EXEC %VGPR1 = V_CVT_PKRTZ_F16_F32_e32 %VGPR2, %VGPR1, %EXEC EXP 15, 0, 1, 1, 1, %VGPR1, %VGPR0, %VGPR1, %VGPR0, %EXEC S_ENDPGM # End machine code for function main. Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s7 ; BEFC0307 V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302 V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202 V_CVT_PKRTZ_F16_F32_e32 v0, v1, v0 ; 5E000101 V_INTERP_MOV_F32 v1, P0, 1, 0, [m0] ; C8060102 V_INTERP_MOV_F32 v2, P0, 0, 0, [m0] ; C80A0002 V_CVT_PKRTZ_F16_F32_e32 v1, v2, v1 ; 5E020302 EXP 15, 0, 1, 1, 1, v1, v0, v1, v0 ; F8001C0F 00010001 S_ENDPGM ; BF810000 VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] 0: MOV OUT[0], IN[0] 1: MOV OUT[1], IN[1] 2: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0 %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0 %12 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %11, i32 0, i32 %6) %13 = extractelement <4 x float> %12, i32 0 %14 = extractelement <4 x float> %12, i32 1 %15 = extractelement <4 x float> %12, i32 2 %16 = extractelement <4 x float> %12, i32 3 %17 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 1 %18 = load <16 x i8> addrspace(2)* %17, !tbaa !0 %19 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %18, i32 0, i32 %6) %20 = extractelement <4 x float> %19, i32 0 %21 = extractelement <4 x float> %19, i32 1 %22 = extractelement <4 x float> %19, i32 2 %23 = extractelement <4 x float> %19, i32 3 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %20, float %21, float %22, float %23) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %13, float %14, float %15, float %16) ret void } ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} # Machine code for function main: Post SSA, not tracking liveness Function Live Ins: %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg6 BB#0: derived from LLVM BB %main_body Live Ins: %SGPR6_SGPR7 %VGPR0 %SGPR0_SGPR1_SGPR2_SGPR3 = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%20](align=8)(tbaa=!"const") S_WAITCNT 127 %VGPR1_VGPR2_VGPR3_VGPR4 = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR0, 0, %EXEC S_WAITCNT 1904 EXP 15, 32, 0, 0, 0, %VGPR1, %VGPR2, %VGPR3, %VGPR4, %EXEC, %VGPR1_VGPR2_VGPR3_VGPR4 %SGPR0_SGPR1_SGPR2_SGPR3 = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 0; mem:LD16[%11](align=8)(tbaa=!"const") S_WAITCNT 15 %VGPR0_VGPR1_VGPR2_VGPR3 = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR0, 0, %EXEC S_WAITCNT 1904 EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR1, %VGPR2, %VGPR3, %EXEC, %VGPR0_VGPR1_VGPR2_VGPR3 S_ENDPGM # End machine code for function main. Shader Disassembly: S_LOAD_DWORDX4 s[0:3], s[6:7], 4 ; C0800704 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[1:4], s[0:3][v0] + 0 ; E00C2000 80000100 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 32, 0, 0, 0, v1, v2, v3, v4 ; F800020F 04030201 S_LOAD_DWORDX4 s[0:3], s[6:7], 0 ; C0800700 S_WAITCNT expcnt(0) lgkmcnt(0) ; BF8C000F BUFFER_LOAD_FORMAT_XYZW v[0:3], s[0:3][v0] + 0 ; E00C2000 80000000 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 12, 0, 1, 0, v0, v1, v2, v3 ; F80008CF 03020100 S_ENDPGM ; BF810000 Installing breakpad exception handler for appid(gameoverlayui)/version(20131030110811_client) Installing breakpad exception handler for appid(gameoverlayui)/version(1.0_client) Uploading dump (out-of-process) [proxy ''] /tmp/dumps/crash_20131123152925_2.dmp