Running Steam on arch  32-bit
STEAM_RUNTIME is enabled automatically
Installing breakpad exception handler for appid(steam)/version(1383158641_client)
[2013-11-24 19:00:02] Startup - updater built Oct  7 2013 12:10:55
FRAG
  0: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
# Machine code for function main: Post SSA, not tracking liveness

BB#0: derived from LLVM BB %main_body
	%VGPR0<def> = V_MOV_B32_e32 0, %EXEC<imp-use>
	EXP 0, 0, 0, 1, 1, %VGPR0<kill>, %VGPR0, %VGPR0, %VGPR0, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	V_MOV_B32_e32 v0, 0               ; 7E000280
	EXP 0, 0, 0, 1, 1, v0, v0, v0, v0 ; F8001800 00000000
	S_ENDPGM                          ; BF810000

FRAG
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %21 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %4)
  %22 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %4)
  %23 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %4)
  %24 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %4)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %21, float %22, float %23, float %24)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR7 in %vreg4

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR7
	%EXEC<def> = S_WQM_B64 %EXEC
	%M0<def> = S_MOV_B32 %SGPR7
	%VGPR0<def> = V_INTERP_MOV_F32 2, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_INTERP_MOV_F32 2, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_INTERP_MOV_F32 2, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_INTERP_MOV_F32 2, 0, 0, %M0<kill>, %EXEC<imp-use>
	EXP 15, 0, 0, 1, 1, %VGPR3<kill>, %VGPR2<kill>, %VGPR1<kill>, %VGPR0<kill>, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_WQM_B64 exec, exec                ; BEFE0A7E
	S_MOV_B32 m0, s7                    ; BEFC0307
	V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302
	V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202
	V_INTERP_MOV_F32 v2, P0, 1, 0, [m0] ; C80A0102
	V_INTERP_MOV_F32 v3, P0, 0, 0, [m0] ; C80E0002
	EXP 15, 0, 0, 1, 1, v3, v2, v1, v0  ; F800180F 00010203
	S_ENDPGM                            ; BF810000

FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %21 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %4)
  %22 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %4)
  %23 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %4)
  %24 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %4)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %21, float %22, float %23, float %24)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR7 in %vreg4

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR7
	%EXEC<def> = S_WQM_B64 %EXEC
	%M0<def> = S_MOV_B32 %SGPR7
	%VGPR0<def> = V_INTERP_MOV_F32 2, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_INTERP_MOV_F32 2, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_INTERP_MOV_F32 2, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_INTERP_MOV_F32 2, 0, 0, %M0<kill>, %EXEC<imp-use>
	EXP 15, 0, 0, 1, 1, %VGPR3<kill>, %VGPR2<kill>, %VGPR1<kill>, %VGPR0<kill>, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_WQM_B64 exec, exec                ; BEFE0A7E
	S_MOV_B32 m0, s7                    ; BEFC0307
	V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302
	V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202
	V_INTERP_MOV_F32 v2, P0, 1, 0, [m0] ; C80A0102
	V_INTERP_MOV_F32 v3, P0, 0, 0, [m0] ; C80E0002
	EXP 15, 0, 0, 1, 1, v3, v2, v1, v0  ; F800180F 00010203
	S_ENDPGM                            ; BF810000

VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[0]
  0: MOV OUT[0], IN[0]
  1: MOV OUT[1], IN[1]
  2: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %11, i32 0, i32 %6)
  %13 = extractelement <4 x float> %12, i32 0
  %14 = extractelement <4 x float> %12, i32 1
  %15 = extractelement <4 x float> %12, i32 2
  %16 = extractelement <4 x float> %12, i32 3
  %17 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 1
  %18 = load <16 x i8> addrspace(2)* %17, !tbaa !0
  %19 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %18, i32 0, i32 %6)
  %20 = extractelement <4 x float> %19, i32 0
  %21 = extractelement <4 x float> %19, i32 1
  %22 = extractelement <4 x float> %19, i32 2
  %23 = extractelement <4 x float> %19, i32 3
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %20, float %21, float %22, float %23)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %13, float %14, float %15, float %16)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg6

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR6_SGPR7 %VGPR0
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%20](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%VGPR1_VGPR2_VGPR3_VGPR4<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	EXP 15, 32, 0, 0, 0, %VGPR1, %VGPR2, %VGPR3, %VGPR4, %EXEC<imp-use>, %VGPR1_VGPR2_VGPR3_VGPR4<imp-use,kill>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%11](align=8)(tbaa=!"const")
	S_WAITCNT 15
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR1, %VGPR2, %VGPR3, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_LOAD_DWORDX4 s[0:3], s[6:7], 4               ; C0800704
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	BUFFER_LOAD_FORMAT_XYZW v[1:4], s[0:3][v0] + 0 ; E00C2000 80000100
	S_WAITCNT vmcnt(0)                             ; BF8C0770
	EXP 15, 32, 0, 0, 0, v1, v2, v3, v4            ; F800020F 04030201
	S_LOAD_DWORDX4 s[0:3], s[6:7], 0               ; C0800700
	S_WAITCNT expcnt(0) lgkmcnt(0)                 ; BF8C000F
	BUFFER_LOAD_FORMAT_XYZW v[0:3], s[0:3][v0] + 0 ; E00C2000 80000000
	S_WAITCNT vmcnt(0)                             ; BF8C0770
	EXP 15, 12, 0, 1, 0, v0, v1, v2, v3            ; F80008CF 03020100
	S_ENDPGM                                       ; BF810000

VERT
DCL IN[0]
DCL OUT[0], POSITION
  0: MOV OUT[0], IN[0]
  1: END
STREAMOUT
  0: BUF0[0..0] <- OUT[0].x
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %13 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 0
  %14 = load <16 x i8> addrspace(2)* %13, !tbaa !0
  %15 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0
  %16 = load <16 x i8> addrspace(2)* %15, !tbaa !0
  %17 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %16, i32 0, i32 %9)
  %18 = extractelement <4 x float> %17, i32 0
  %19 = extractelement <4 x float> %17, i32 1
  %20 = extractelement <4 x float> %17, i32 2
  %21 = extractelement <4 x float> %17, i32 3
  %22 = lshr i32 %6, 16
  %23 = and i32 %22, 127
  %24 = call i32 @llvm.SI.tid()
  %25 = icmp ult i32 %24, %23
  br i1 %25, label %if-true-block, label %endif-block

if-true-block:                                    ; preds = %main_body
  %26 = add i32 %7, %24
  %27 = mul i32 %8, 4
  %28 = mul i32 %26, 4
  %29 = add i32 %28, %27
  %30 = bitcast float %18 to i32
  call void @llvm.SI.tbuffer.store.i32(<16 x i8> %14, i32 %30, i32 1, i32 %29, i32 0, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0)
  br label %endif-block

endif-block:                                      ; preds = %main_body, %if-true-block
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %18, float %19, float %20, float %21)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare i32 @llvm.SI.tid() #2

declare void @llvm.SI.tbuffer.store.i32(<16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32)

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR6_SGPR7 in %vreg7, %SGPR8_SGPR9 in %vreg8, %SGPR11 in %vreg10, %SGPR12 in %vreg11, %SGPR13 in %vreg12, %VGPR0 in %vreg13

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR6_SGPR7 %SGPR8_SGPR9 %SGPR11 %SGPR12 %SGPR13 %VGPR0
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%14](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LSHR_B32 %SGPR11<kill>, 16
	%VGPR4<def> = V_MOV_B32_e32 127, %EXEC<imp-use>
	%VGPR5<def> = V_AND_B32_e32 %SGPR0<kill>, %VGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MBCNT_LO_U32_B32_e64 -1, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MBCNT_HI_U32_B32_e32 -1, %VGPR4<kill>, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = V_CMP_LT_U32_e64 %VGPR4, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%SGPR0_SGPR1<def> = S_AND_SAVEEXEC_B64 %SGPR0_SGPR1, %EXEC<imp-def>, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_XOR_B64 %EXEC, %SGPR0_SGPR1
    Successors according to CFG: BB#1(16) BB#2(16)

BB#1: derived from LLVM BB %if-true-block
    Live Ins: %VGPR0_VGPR1_VGPR2_VGPR3 %SGPR8_SGPR9 %SGPR12 %SGPR13 %SGPR0_SGPR1 %VGPR4
    Predecessors according to CFG: BB#0
	%VGPR4<def> = V_ADD_I32_e32 %SGPR12<kill>, %VGPR4<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR4<def> = V_LSHLREV_B32_e32 2, %VGPR4<kill>, %EXEC<imp-use>
	%SGPR2<def> = S_LSHL_B32 %SGPR13<kill>, 2
	%VGPR4<def> = V_ADD_I32_e32 %SGPR2<kill>, %VGPR4<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR8_SGPR9<kill>, 0; mem:LD16[%27](align=8)(tbaa=!"const")
	S_WAITCNT 127
	TBUFFER_STORE_FORMAT_X %VGPR0, 0, -1, 0, -1, 0, 4, 4, %VGPR4<kill>, %SGPR4_SGPR5_SGPR6_SGPR7<kill>, -1, 0, 0, %EXEC<imp-use>
	S_WAITCNT 1792
    Successors according to CFG: BB#2

BB#2: derived from LLVM BB %endif-block
    Live Ins: %VGPR0_VGPR1_VGPR2_VGPR3 %SGPR0_SGPR1
    Predecessors according to CFG: BB#0 BB#1
	%EXEC<def> = S_OR_B64 %EXEC, %SGPR0_SGPR1
	EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR1, %VGPR2, %VGPR3, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_LOAD_DWORDX4 s[0:3], s[6:7], 0                                       ; C0800700
	S_WAITCNT lgkmcnt(0)                                                   ; BF8C007F
	BUFFER_LOAD_FORMAT_XYZW v[0:3], s[0:3][v0] + 0                         ; E00C2000 80000000
	S_LSHR_B32 s0, s11, 16                                                 ; 9000900B
	V_MOV_B32_e32 v4, 127                                                  ; 7E0802FF 0000007F
	V_AND_B32_e32 v5, s0, v4                                               ; 360A0800
	V_MBCNT_LO_U32_B32_e64 v4, -1, 0, 0, 0, 0, 0                           ; D2460004 020100C1
	V_MBCNT_HI_U32_B32_e32 v4, -1, v4                                      ; 480808C1
	V_CMP_LT_U32_e64 s[0:1], v4, v5, 0, 0, 0, 0                            ; D1820000 02020B04
	S_WAITCNT vmcnt(0)                                                     ; BF8C0770
	S_AND_SAVEEXEC_B64 s[0:1], s[0:1]                                      ; BE802400
	S_XOR_B64 s[0:1], exec, s[0:1]                                         ; 8980007E
	V_ADD_I32_e32 v4, s12, v4                                              ; 4A08080C
	V_LSHLREV_B32_e32 v4, 2, v4                                            ; 34080882
	S_LSHL_B32 s2, s13, 2                                                  ; 8F02820D
	V_ADD_I32_e32 v4, s2, v4                                               ; 4A080802
	S_LOAD_DWORDX4 s[4:7], s[8:9], 0                                       ; C0820900
	S_WAITCNT lgkmcnt(0)                                                   ; BF8C007F
	TBUFFER_STORE_FORMAT_X v0, 0, -1, 0, -1, 0, 4, 4, v4, s[4:7], -1, 0, 0 ; EA245000 80410004
	S_WAITCNT vmcnt(0) expcnt(0)                                           ; BF8C0700
	S_OR_B64 exec, exec, s[0:1]                                            ; 88FE007E
	EXP 15, 12, 0, 1, 0, v0, v1, v2, v3                                    ; F80008CF 03020100
	S_ENDPGM                                                               ; BF810000

FRAG
DCL IN[0], GENERIC[0], CONSTANT
  0: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
# Machine code for function main: Post SSA, not tracking liveness

BB#0: derived from LLVM BB %main_body
	%VGPR0<def> = V_MOV_B32_e32 0, %EXEC<imp-use>
	EXP 0, 0, 0, 1, 1, %VGPR0<kill>, %VGPR0, %VGPR0, %VGPR0, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	V_MOV_B32_e32 v0, 0               ; 7E000280
	EXP 0, 0, 0, 1, 1, v0, v0, v0, v0 ; F8001800 00000000
	S_ENDPGM                          ; BF810000

FRAG
  0: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
# Machine code for function main: Post SSA, not tracking liveness

BB#0: derived from LLVM BB %main_body
	%VGPR0<def> = V_MOV_B32_e32 0, %EXEC<imp-use>
	EXP 0, 0, 0, 1, 1, %VGPR0<kill>, %VGPR0, %VGPR0, %VGPR0, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	V_MOV_B32_e32 v0, 0               ; 7E000280
	EXP 0, 0, 0, 1, 1, v0, v0, v0, v0 ; F8001800 00000000
	S_ENDPGM                          ; BF810000

FRAG
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %21 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %4)
  %22 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %4)
  %23 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %4)
  %24 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %4)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %21, float %22, float %23, float %24)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR7 in %vreg4

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR7
	%EXEC<def> = S_WQM_B64 %EXEC
	%M0<def> = S_MOV_B32 %SGPR7
	%VGPR0<def> = V_INTERP_MOV_F32 2, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_INTERP_MOV_F32 2, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_INTERP_MOV_F32 2, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_INTERP_MOV_F32 2, 0, 0, %M0<kill>, %EXEC<imp-use>
	EXP 15, 0, 0, 1, 1, %VGPR3<kill>, %VGPR2<kill>, %VGPR1<kill>, %VGPR0<kill>, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_WQM_B64 exec, exec                ; BEFE0A7E
	S_MOV_B32 m0, s7                    ; BEFC0307
	V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302
	V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202
	V_INTERP_MOV_F32 v2, P0, 1, 0, [m0] ; C80A0102
	V_INTERP_MOV_F32 v3, P0, 0, 0, [m0] ; C80E0002
	EXP 15, 0, 0, 1, 1, v3, v2, v1, v0  ; F800180F 00010203
	S_ENDPGM                            ; BF810000

FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %21 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %4)
  %22 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %4)
  %23 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %4)
  %24 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %4)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %21, float %22, float %23, float %24)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR7 in %vreg4

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR7
	%EXEC<def> = S_WQM_B64 %EXEC
	%M0<def> = S_MOV_B32 %SGPR7
	%VGPR0<def> = V_INTERP_MOV_F32 2, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_INTERP_MOV_F32 2, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_INTERP_MOV_F32 2, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_INTERP_MOV_F32 2, 0, 0, %M0<kill>, %EXEC<imp-use>
	EXP 15, 0, 0, 1, 1, %VGPR3<kill>, %VGPR2<kill>, %VGPR1<kill>, %VGPR0<kill>, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_WQM_B64 exec, exec                ; BEFE0A7E
	S_MOV_B32 m0, s7                    ; BEFC0307
	V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302
	V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202
	V_INTERP_MOV_F32 v2, P0, 1, 0, [m0] ; C80A0102
	V_INTERP_MOV_F32 v3, P0, 0, 0, [m0] ; C80E0002
	EXP 15, 0, 0, 1, 1, v3, v2, v1, v0  ; F800180F 00010203
	S_ENDPGM                            ; BF810000

VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[0]
  0: MOV OUT[0], IN[0]
  1: MOV OUT[1], IN[1]
  2: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %11, i32 0, i32 %6)
  %13 = extractelement <4 x float> %12, i32 0
  %14 = extractelement <4 x float> %12, i32 1
  %15 = extractelement <4 x float> %12, i32 2
  %16 = extractelement <4 x float> %12, i32 3
  %17 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 1
  %18 = load <16 x i8> addrspace(2)* %17, !tbaa !0
  %19 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %18, i32 0, i32 %6)
  %20 = extractelement <4 x float> %19, i32 0
  %21 = extractelement <4 x float> %19, i32 1
  %22 = extractelement <4 x float> %19, i32 2
  %23 = extractelement <4 x float> %19, i32 3
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %20, float %21, float %22, float %23)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %13, float %14, float %15, float %16)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg6

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR6_SGPR7 %VGPR0
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%20](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%VGPR1_VGPR2_VGPR3_VGPR4<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	EXP 15, 32, 0, 0, 0, %VGPR1, %VGPR2, %VGPR3, %VGPR4, %EXEC<imp-use>, %VGPR1_VGPR2_VGPR3_VGPR4<imp-use,kill>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%11](align=8)(tbaa=!"const")
	S_WAITCNT 15
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR1, %VGPR2, %VGPR3, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_LOAD_DWORDX4 s[0:3], s[6:7], 4               ; C0800704
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	BUFFER_LOAD_FORMAT_XYZW v[1:4], s[0:3][v0] + 0 ; E00C2000 80000100
	S_WAITCNT vmcnt(0)                             ; BF8C0770
	EXP 15, 32, 0, 0, 0, v1, v2, v3, v4            ; F800020F 04030201
	S_LOAD_DWORDX4 s[0:3], s[6:7], 0               ; C0800700
	S_WAITCNT expcnt(0) lgkmcnt(0)                 ; BF8C000F
	BUFFER_LOAD_FORMAT_XYZW v[0:3], s[0:3][v0] + 0 ; E00C2000 80000000
	S_WAITCNT vmcnt(0)                             ; BF8C0770
	EXP 15, 12, 0, 1, 0, v0, v1, v2, v3            ; F80008CF 03020100
	S_ENDPGM                                       ; BF810000

VERT
DCL IN[0]
DCL OUT[0], POSITION
  0: MOV OUT[0], IN[0]
  1: END
STREAMOUT
  0: BUF0[0..0] <- OUT[0].x
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %13 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 0
  %14 = load <16 x i8> addrspace(2)* %13, !tbaa !0
  %15 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0
  %16 = load <16 x i8> addrspace(2)* %15, !tbaa !0
  %17 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %16, i32 0, i32 %9)
  %18 = extractelement <4 x float> %17, i32 0
  %19 = extractelement <4 x float> %17, i32 1
  %20 = extractelement <4 x float> %17, i32 2
  %21 = extractelement <4 x float> %17, i32 3
  %22 = lshr i32 %6, 16
  %23 = and i32 %22, 127
  %24 = call i32 @llvm.SI.tid()
  %25 = icmp ult i32 %24, %23
  br i1 %25, label %if-true-block, label %endif-block

if-true-block:                                    ; preds = %main_body
  %26 = add i32 %7, %24
  %27 = mul i32 %8, 4
  %28 = mul i32 %26, 4
  %29 = add i32 %28, %27
  %30 = bitcast float %18 to i32
  call void @llvm.SI.tbuffer.store.i32(<16 x i8> %14, i32 %30, i32 1, i32 %29, i32 0, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0)
  br label %endif-block

endif-block:                                      ; preds = %main_body, %if-true-block
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %18, float %19, float %20, float %21)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare i32 @llvm.SI.tid() #2

declare void @llvm.SI.tbuffer.store.i32(<16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32)

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR6_SGPR7 in %vreg7, %SGPR8_SGPR9 in %vreg8, %SGPR11 in %vreg10, %SGPR12 in %vreg11, %SGPR13 in %vreg12, %VGPR0 in %vreg13

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR6_SGPR7 %SGPR8_SGPR9 %SGPR11 %SGPR12 %SGPR13 %VGPR0
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%14](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LSHR_B32 %SGPR11<kill>, 16
	%VGPR4<def> = V_MOV_B32_e32 127, %EXEC<imp-use>
	%VGPR5<def> = V_AND_B32_e32 %SGPR0<kill>, %VGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MBCNT_LO_U32_B32_e64 -1, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MBCNT_HI_U32_B32_e32 -1, %VGPR4<kill>, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = V_CMP_LT_U32_e64 %VGPR4, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%SGPR0_SGPR1<def> = S_AND_SAVEEXEC_B64 %SGPR0_SGPR1, %EXEC<imp-def>, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_XOR_B64 %EXEC, %SGPR0_SGPR1
    Successors according to CFG: BB#1(16) BB#2(16)

BB#1: derived from LLVM BB %if-true-block
    Live Ins: %VGPR0_VGPR1_VGPR2_VGPR3 %SGPR8_SGPR9 %SGPR12 %SGPR13 %SGPR0_SGPR1 %VGPR4
    Predecessors according to CFG: BB#0
	%VGPR4<def> = V_ADD_I32_e32 %SGPR12<kill>, %VGPR4<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR4<def> = V_LSHLREV_B32_e32 2, %VGPR4<kill>, %EXEC<imp-use>
	%SGPR2<def> = S_LSHL_B32 %SGPR13<kill>, 2
	%VGPR4<def> = V_ADD_I32_e32 %SGPR2<kill>, %VGPR4<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR8_SGPR9<kill>, 0; mem:LD16[%27](align=8)(tbaa=!"const")
	S_WAITCNT 127
	TBUFFER_STORE_FORMAT_X %VGPR0, 0, -1, 0, -1, 0, 4, 4, %VGPR4<kill>, %SGPR4_SGPR5_SGPR6_SGPR7<kill>, -1, 0, 0, %EXEC<imp-use>
	S_WAITCNT 1792
    Successors according to CFG: BB#2

BB#2: derived from LLVM BB %endif-block
    Live Ins: %VGPR0_VGPR1_VGPR2_VGPR3 %SGPR0_SGPR1
    Predecessors according to CFG: BB#0 BB#1
	%EXEC<def> = S_OR_B64 %EXEC, %SGPR0_SGPR1
	EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR1, %VGPR2, %VGPR3, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_LOAD_DWORDX4 s[0:3], s[6:7], 0                                       ; C0800700
	S_WAITCNT lgkmcnt(0)                                                   ; BF8C007F
	BUFFER_LOAD_FORMAT_XYZW v[0:3], s[0:3][v0] + 0                         ; E00C2000 80000000
	S_LSHR_B32 s0, s11, 16                                                 ; 9000900B
	V_MOV_B32_e32 v4, 127                                                  ; 7E0802FF 0000007F
	V_AND_B32_e32 v5, s0, v4                                               ; 360A0800
	V_MBCNT_LO_U32_B32_e64 v4, -1, 0, 0, 0, 0, 0                           ; D2460004 020100C1
	V_MBCNT_HI_U32_B32_e32 v4, -1, v4                                      ; 480808C1
	V_CMP_LT_U32_e64 s[0:1], v4, v5, 0, 0, 0, 0                            ; D1820000 02020B04
	S_WAITCNT vmcnt(0)                                                     ; BF8C0770
	S_AND_SAVEEXEC_B64 s[0:1], s[0:1]                                      ; BE802400
	S_XOR_B64 s[0:1], exec, s[0:1]                                         ; 8980007E
	V_ADD_I32_e32 v4, s12, v4                                              ; 4A08080C
	V_LSHLREV_B32_e32 v4, 2, v4                                            ; 34080882
	S_LSHL_B32 s2, s13, 2                                                  ; 8F02820D
	V_ADD_I32_e32 v4, s2, v4                                               ; 4A080802
	S_LOAD_DWORDX4 s[4:7], s[8:9], 0                                       ; C0820900
	S_WAITCNT lgkmcnt(0)                                                   ; BF8C007F
	TBUFFER_STORE_FORMAT_X v0, 0, -1, 0, -1, 0, 4, 4, v4, s[4:7], -1, 0, 0 ; EA245000 80410004
	S_WAITCNT vmcnt(0) expcnt(0)                                           ; BF8C0700
	S_OR_B64 exec, exec, s[0:1]                                            ; 88FE007E
	EXP 15, 12, 0, 1, 0, v0, v1, v2, v3                                    ; F80008CF 03020100
	S_ENDPGM                                                               ; BF810000

FRAG
DCL IN[0], GENERIC[0], CONSTANT
  0: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
# Machine code for function main: Post SSA, not tracking liveness

BB#0: derived from LLVM BB %main_body
	%VGPR0<def> = V_MOV_B32_e32 0, %EXEC<imp-use>
	EXP 0, 0, 0, 1, 1, %VGPR0<kill>, %VGPR0, %VGPR0, %VGPR0, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	V_MOV_B32_e32 v0, 0               ; 7E000280
	EXP 0, 0, 0, 1, 1, v0, v0, v0, v0 ; F8001800 00000000
	S_ENDPGM                          ; BF810000

Installing breakpad exception handler for appid(steam)/version(1383158641_client)
Installing breakpad exception handler for appid(steam)/version(1383158641_client)
unlinked 0 orphaned pipes
Installing breakpad exception handler for appid(steam)/version(1383158641_client)
Fontconfig error: "/etc/fonts/conf.d/10-scale-bitmap-fonts.conf", line 70: non-double matrix element
Fontconfig error: "/etc/fonts/conf.d/10-scale-bitmap-fonts.conf", line 70: non-double matrix element
Fontconfig warning: "/etc/fonts/conf.d/10-scale-bitmap-fonts.conf", line 78: saw unknown, expected number
[1124/190013:WARNING:proxy_service.cc(958)] PAC support disabled because there is no system implementation
Looks like steam didn't shutdown cleanly, scheduling immediate update check
[2013-11-24 19:00:02] Checking for update on startup
[2013-11-24 19:00:02] Checking for available updates...
[2013-11-24 19:00:03] Download skipped: /client/steam_client_ubuntu12 version 1383158641, installed version 1383158641
[2013-11-24 19:00:03] Nothing to do
[2013-11-24 19:00:03] Verifying installation...
[2013-11-24 19:00:03] Performing checksum verification of executable files
[2013-11-24 19:00:05] BVerifyInstalledFiles: steam.sh is 21689 bytes, expected 22072
[2013-11-24 19:00:08] BVerifyInstalledFiles: ubuntu12_32/steam is 3448966 bytes, expected 3456286
[2013-11-24 19:00:10] Verification complete
[2013-11-24 19:00:10] BRepairInstalledFiles: ignoring bootstrap file ubuntu12_32/steam
[2013-11-24 19:00:10] BRepairInstalledFiles: ignoring bootstrap file steam.sh
FRAG
  0: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
# Machine code for function main: Post SSA, not tracking liveness

BB#0: derived from LLVM BB %main_body
	%VGPR0<def> = V_MOV_B32_e32 0, %EXEC<imp-use>
	EXP 0, 0, 0, 1, 1, %VGPR0<kill>, %VGPR0, %VGPR0, %VGPR0, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	V_MOV_B32_e32 v0, 0               ; 7E000280
	EXP 0, 0, 0, 1, 1, v0, v0, v0, v0 ; F8001800 00000000
	S_ENDPGM                          ; BF810000

FRAG
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %21 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %4)
  %22 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %4)
  %23 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %4)
  %24 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %4)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %21, float %22, float %23, float %24)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR7 in %vreg4

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR7
	%EXEC<def> = S_WQM_B64 %EXEC
	%M0<def> = S_MOV_B32 %SGPR7
	%VGPR0<def> = V_INTERP_MOV_F32 2, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_INTERP_MOV_F32 2, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_INTERP_MOV_F32 2, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_INTERP_MOV_F32 2, 0, 0, %M0<kill>, %EXEC<imp-use>
	EXP 15, 0, 0, 1, 1, %VGPR3<kill>, %VGPR2<kill>, %VGPR1<kill>, %VGPR0<kill>, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_WQM_B64 exec, exec                ; BEFE0A7E
	S_MOV_B32 m0, s7                    ; BEFC0307
	V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302
	V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202
	V_INTERP_MOV_F32 v2, P0, 1, 0, [m0] ; C80A0102
	V_INTERP_MOV_F32 v3, P0, 0, 0, [m0] ; C80E0002
	EXP 15, 0, 0, 1, 1, v3, v2, v1, v0  ; F800180F 00010203
	S_ENDPGM                            ; BF810000

FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %21 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %4)
  %22 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %4)
  %23 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %4)
  %24 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %4)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %21, float %22, float %23, float %24)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR7 in %vreg4

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR7
	%EXEC<def> = S_WQM_B64 %EXEC
	%M0<def> = S_MOV_B32 %SGPR7
	%VGPR0<def> = V_INTERP_MOV_F32 2, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_INTERP_MOV_F32 2, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_INTERP_MOV_F32 2, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_INTERP_MOV_F32 2, 0, 0, %M0<kill>, %EXEC<imp-use>
	EXP 15, 0, 0, 1, 1, %VGPR3<kill>, %VGPR2<kill>, %VGPR1<kill>, %VGPR0<kill>, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_WQM_B64 exec, exec                ; BEFE0A7E
	S_MOV_B32 m0, s7                    ; BEFC0307
	V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302
	V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202
	V_INTERP_MOV_F32 v2, P0, 1, 0, [m0] ; C80A0102
	V_INTERP_MOV_F32 v3, P0, 0, 0, [m0] ; C80E0002
	EXP 15, 0, 0, 1, 1, v3, v2, v1, v0  ; F800180F 00010203
	S_ENDPGM                            ; BF810000

VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[0]
  0: MOV OUT[0], IN[0]
  1: MOV OUT[1], IN[1]
  2: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %11, i32 0, i32 %6)
  %13 = extractelement <4 x float> %12, i32 0
  %14 = extractelement <4 x float> %12, i32 1
  %15 = extractelement <4 x float> %12, i32 2
  %16 = extractelement <4 x float> %12, i32 3
  %17 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 1
  %18 = load <16 x i8> addrspace(2)* %17, !tbaa !0
  %19 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %18, i32 0, i32 %6)
  %20 = extractelement <4 x float> %19, i32 0
  %21 = extractelement <4 x float> %19, i32 1
  %22 = extractelement <4 x float> %19, i32 2
  %23 = extractelement <4 x float> %19, i32 3
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %20, float %21, float %22, float %23)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %13, float %14, float %15, float %16)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg6

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR6_SGPR7 %VGPR0
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%20](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%VGPR1_VGPR2_VGPR3_VGPR4<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	EXP 15, 32, 0, 0, 0, %VGPR1, %VGPR2, %VGPR3, %VGPR4, %EXEC<imp-use>, %VGPR1_VGPR2_VGPR3_VGPR4<imp-use,kill>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%11](align=8)(tbaa=!"const")
	S_WAITCNT 15
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR1, %VGPR2, %VGPR3, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_LOAD_DWORDX4 s[0:3], s[6:7], 4               ; C0800704
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	BUFFER_LOAD_FORMAT_XYZW v[1:4], s[0:3][v0] + 0 ; E00C2000 80000100
	S_WAITCNT vmcnt(0)                             ; BF8C0770
	EXP 15, 32, 0, 0, 0, v1, v2, v3, v4            ; F800020F 04030201
	S_LOAD_DWORDX4 s[0:3], s[6:7], 0               ; C0800700
	S_WAITCNT expcnt(0) lgkmcnt(0)                 ; BF8C000F
	BUFFER_LOAD_FORMAT_XYZW v[0:3], s[0:3][v0] + 0 ; E00C2000 80000000
	S_WAITCNT vmcnt(0)                             ; BF8C0770
	EXP 15, 12, 0, 1, 0, v0, v1, v2, v3            ; F80008CF 03020100
	S_ENDPGM                                       ; BF810000

VERT
DCL IN[0]
DCL OUT[0], POSITION
  0: MOV OUT[0], IN[0]
  1: END
STREAMOUT
  0: BUF0[0..0] <- OUT[0].x
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %13 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 0
  %14 = load <16 x i8> addrspace(2)* %13, !tbaa !0
  %15 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0
  %16 = load <16 x i8> addrspace(2)* %15, !tbaa !0
  %17 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %16, i32 0, i32 %9)
  %18 = extractelement <4 x float> %17, i32 0
  %19 = extractelement <4 x float> %17, i32 1
  %20 = extractelement <4 x float> %17, i32 2
  %21 = extractelement <4 x float> %17, i32 3
  %22 = lshr i32 %6, 16
  %23 = and i32 %22, 127
  %24 = call i32 @llvm.SI.tid()
  %25 = icmp ult i32 %24, %23
  br i1 %25, label %if-true-block, label %endif-block

if-true-block:                                    ; preds = %main_body
  %26 = add i32 %7, %24
  %27 = mul i32 %8, 4
  %28 = mul i32 %26, 4
  %29 = add i32 %28, %27
  %30 = bitcast float %18 to i32
  call void @llvm.SI.tbuffer.store.i32(<16 x i8> %14, i32 %30, i32 1, i32 %29, i32 0, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0)
  br label %endif-block

endif-block:                                      ; preds = %main_body, %if-true-block
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %18, float %19, float %20, float %21)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare i32 @llvm.SI.tid() #2

declare void @llvm.SI.tbuffer.store.i32(<16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32)

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR6_SGPR7 in %vreg7, %SGPR8_SGPR9 in %vreg8, %SGPR11 in %vreg10, %SGPR12 in %vreg11, %SGPR13 in %vreg12, %VGPR0 in %vreg13

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR6_SGPR7 %SGPR8_SGPR9 %SGPR11 %SGPR12 %SGPR13 %VGPR0
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%14](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LSHR_B32 %SGPR11<kill>, 16
	%VGPR4<def> = V_MOV_B32_e32 127, %EXEC<imp-use>
	%VGPR5<def> = V_AND_B32_e32 %SGPR0<kill>, %VGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MBCNT_LO_U32_B32_e64 -1, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MBCNT_HI_U32_B32_e32 -1, %VGPR4<kill>, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = V_CMP_LT_U32_e64 %VGPR4, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%SGPR0_SGPR1<def> = S_AND_SAVEEXEC_B64 %SGPR0_SGPR1, %EXEC<imp-def>, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_XOR_B64 %EXEC, %SGPR0_SGPR1
    Successors according to CFG: BB#1(16) BB#2(16)

BB#1: derived from LLVM BB %if-true-block
    Live Ins: %VGPR0_VGPR1_VGPR2_VGPR3 %SGPR8_SGPR9 %SGPR12 %SGPR13 %SGPR0_SGPR1 %VGPR4
    Predecessors according to CFG: BB#0
	%VGPR4<def> = V_ADD_I32_e32 %SGPR12<kill>, %VGPR4<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR4<def> = V_LSHLREV_B32_e32 2, %VGPR4<kill>, %EXEC<imp-use>
	%SGPR2<def> = S_LSHL_B32 %SGPR13<kill>, 2
	%VGPR4<def> = V_ADD_I32_e32 %SGPR2<kill>, %VGPR4<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR8_SGPR9<kill>, 0; mem:LD16[%27](align=8)(tbaa=!"const")
	S_WAITCNT 127
	TBUFFER_STORE_FORMAT_X %VGPR0, 0, -1, 0, -1, 0, 4, 4, %VGPR4<kill>, %SGPR4_SGPR5_SGPR6_SGPR7<kill>, -1, 0, 0, %EXEC<imp-use>
	S_WAITCNT 1792
    Successors according to CFG: BB#2

BB#2: derived from LLVM BB %endif-block
    Live Ins: %VGPR0_VGPR1_VGPR2_VGPR3 %SGPR0_SGPR1
    Predecessors according to CFG: BB#0 BB#1
	%EXEC<def> = S_OR_B64 %EXEC, %SGPR0_SGPR1
	EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR1, %VGPR2, %VGPR3, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_LOAD_DWORDX4 s[0:3], s[6:7], 0                                       ; C0800700
	S_WAITCNT lgkmcnt(0)                                                   ; BF8C007F
	BUFFER_LOAD_FORMAT_XYZW v[0:3], s[0:3][v0] + 0                         ; E00C2000 80000000
	S_LSHR_B32 s0, s11, 16                                                 ; 9000900B
	V_MOV_B32_e32 v4, 127                                                  ; 7E0802FF 0000007F
	V_AND_B32_e32 v5, s0, v4                                               ; 360A0800
	V_MBCNT_LO_U32_B32_e64 v4, -1, 0, 0, 0, 0, 0                           ; D2460004 020100C1
	V_MBCNT_HI_U32_B32_e32 v4, -1, v4                                      ; 480808C1
	V_CMP_LT_U32_e64 s[0:1], v4, v5, 0, 0, 0, 0                            ; D1820000 02020B04
	S_WAITCNT vmcnt(0)                                                     ; BF8C0770
	S_AND_SAVEEXEC_B64 s[0:1], s[0:1]                                      ; BE802400
	S_XOR_B64 s[0:1], exec, s[0:1]                                         ; 8980007E
	V_ADD_I32_e32 v4, s12, v4                                              ; 4A08080C
	V_LSHLREV_B32_e32 v4, 2, v4                                            ; 34080882
	S_LSHL_B32 s2, s13, 2                                                  ; 8F02820D
	V_ADD_I32_e32 v4, s2, v4                                               ; 4A080802
	S_LOAD_DWORDX4 s[4:7], s[8:9], 0                                       ; C0820900
	S_WAITCNT lgkmcnt(0)                                                   ; BF8C007F
	TBUFFER_STORE_FORMAT_X v0, 0, -1, 0, -1, 0, 4, 4, v4, s[4:7], -1, 0, 0 ; EA245000 80410004
	S_WAITCNT vmcnt(0) expcnt(0)                                           ; BF8C0700
	S_OR_B64 exec, exec, s[0:1]                                            ; 88FE007E
	EXP 15, 12, 0, 1, 0, v0, v1, v2, v3                                    ; F80008CF 03020100
	S_ENDPGM                                                               ; BF810000

FRAG
DCL IN[0], GENERIC[0], CONSTANT
  0: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
# Machine code for function main: Post SSA, not tracking liveness

BB#0: derived from LLVM BB %main_body
	%VGPR0<def> = V_MOV_B32_e32 0, %EXEC<imp-use>
	EXP 0, 0, 0, 1, 1, %VGPR0<kill>, %VGPR0, %VGPR0, %VGPR0, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	V_MOV_B32_e32 v0, 0               ; 7E000280
	EXP 0, 0, 0, 1, 1, v0, v0, v0, v0 ; F8001800 00000000
	S_ENDPGM                          ; BF810000

FRAG
  0: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
# Machine code for function main: Post SSA, not tracking liveness

BB#0: derived from LLVM BB %main_body
	%VGPR0<def> = V_MOV_B32_e32 0, %EXEC<imp-use>
	EXP 0, 0, 0, 1, 1, %VGPR0<kill>, %VGPR0, %VGPR0, %VGPR0, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	V_MOV_B32_e32 v0, 0               ; 7E000280
	EXP 0, 0, 0, 1, 1, v0, v0, v0, v0 ; F8001800 00000000
	S_ENDPGM                          ; BF810000

FRAG
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %21 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %4)
  %22 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %4)
  %23 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %4)
  %24 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %4)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %21, float %22, float %23, float %24)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR7 in %vreg4

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR7
	%EXEC<def> = S_WQM_B64 %EXEC
	%M0<def> = S_MOV_B32 %SGPR7
	%VGPR0<def> = V_INTERP_MOV_F32 2, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_INTERP_MOV_F32 2, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_INTERP_MOV_F32 2, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_INTERP_MOV_F32 2, 0, 0, %M0<kill>, %EXEC<imp-use>
	EXP 15, 0, 0, 1, 1, %VGPR3<kill>, %VGPR2<kill>, %VGPR1<kill>, %VGPR0<kill>, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_WQM_B64 exec, exec                ; BEFE0A7E
	S_MOV_B32 m0, s7                    ; BEFC0307
	V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302
	V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202
	V_INTERP_MOV_F32 v2, P0, 1, 0, [m0] ; C80A0102
	V_INTERP_MOV_F32 v3, P0, 0, 0, [m0] ; C80E0002
	EXP 15, 0, 0, 1, 1, v3, v2, v1, v0  ; F800180F 00010203
	S_ENDPGM                            ; BF810000

FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %21 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %4)
  %22 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %4)
  %23 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %4)
  %24 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %4)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %21, float %22, float %23, float %24)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR7 in %vreg4

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR7
	%EXEC<def> = S_WQM_B64 %EXEC
	%M0<def> = S_MOV_B32 %SGPR7
	%VGPR0<def> = V_INTERP_MOV_F32 2, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_INTERP_MOV_F32 2, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_INTERP_MOV_F32 2, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_INTERP_MOV_F32 2, 0, 0, %M0<kill>, %EXEC<imp-use>
	EXP 15, 0, 0, 1, 1, %VGPR3<kill>, %VGPR2<kill>, %VGPR1<kill>, %VGPR0<kill>, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_WQM_B64 exec, exec                ; BEFE0A7E
	S_MOV_B32 m0, s7                    ; BEFC0307
	V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302
	V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202
	V_INTERP_MOV_F32 v2, P0, 1, 0, [m0] ; C80A0102
	V_INTERP_MOV_F32 v3, P0, 0, 0, [m0] ; C80E0002
	EXP 15, 0, 0, 1, 1, v3, v2, v1, v0  ; F800180F 00010203
	S_ENDPGM                            ; BF810000

VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[0]
  0: MOV OUT[0], IN[0]
  1: MOV OUT[1], IN[1]
  2: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %11, i32 0, i32 %6)
  %13 = extractelement <4 x float> %12, i32 0
  %14 = extractelement <4 x float> %12, i32 1
  %15 = extractelement <4 x float> %12, i32 2
  %16 = extractelement <4 x float> %12, i32 3
  %17 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 1
  %18 = load <16 x i8> addrspace(2)* %17, !tbaa !0
  %19 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %18, i32 0, i32 %6)
  %20 = extractelement <4 x float> %19, i32 0
  %21 = extractelement <4 x float> %19, i32 1
  %22 = extractelement <4 x float> %19, i32 2
  %23 = extractelement <4 x float> %19, i32 3
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %20, float %21, float %22, float %23)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %13, float %14, float %15, float %16)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg6

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR6_SGPR7 %VGPR0
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%20](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%VGPR1_VGPR2_VGPR3_VGPR4<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	EXP 15, 32, 0, 0, 0, %VGPR1, %VGPR2, %VGPR3, %VGPR4, %EXEC<imp-use>, %VGPR1_VGPR2_VGPR3_VGPR4<imp-use,kill>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%11](align=8)(tbaa=!"const")
	S_WAITCNT 15
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR1, %VGPR2, %VGPR3, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_LOAD_DWORDX4 s[0:3], s[6:7], 4               ; C0800704
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	BUFFER_LOAD_FORMAT_XYZW v[1:4], s[0:3][v0] + 0 ; E00C2000 80000100
	S_WAITCNT vmcnt(0)                             ; BF8C0770
	EXP 15, 32, 0, 0, 0, v1, v2, v3, v4            ; F800020F 04030201
	S_LOAD_DWORDX4 s[0:3], s[6:7], 0               ; C0800700
	S_WAITCNT expcnt(0) lgkmcnt(0)                 ; BF8C000F
	BUFFER_LOAD_FORMAT_XYZW v[0:3], s[0:3][v0] + 0 ; E00C2000 80000000
	S_WAITCNT vmcnt(0)                             ; BF8C0770
	EXP 15, 12, 0, 1, 0, v0, v1, v2, v3            ; F80008CF 03020100
	S_ENDPGM                                       ; BF810000

VERT
DCL IN[0]
DCL OUT[0], POSITION
  0: MOV OUT[0], IN[0]
  1: END
STREAMOUT
  0: BUF0[0..0] <- OUT[0].x
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %13 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 0
  %14 = load <16 x i8> addrspace(2)* %13, !tbaa !0
  %15 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0
  %16 = load <16 x i8> addrspace(2)* %15, !tbaa !0
  %17 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %16, i32 0, i32 %9)
  %18 = extractelement <4 x float> %17, i32 0
  %19 = extractelement <4 x float> %17, i32 1
  %20 = extractelement <4 x float> %17, i32 2
  %21 = extractelement <4 x float> %17, i32 3
  %22 = lshr i32 %6, 16
  %23 = and i32 %22, 127
  %24 = call i32 @llvm.SI.tid()
  %25 = icmp ult i32 %24, %23
  br i1 %25, label %if-true-block, label %endif-block

if-true-block:                                    ; preds = %main_body
  %26 = add i32 %7, %24
  %27 = mul i32 %8, 4
  %28 = mul i32 %26, 4
  %29 = add i32 %28, %27
  %30 = bitcast float %18 to i32
  call void @llvm.SI.tbuffer.store.i32(<16 x i8> %14, i32 %30, i32 1, i32 %29, i32 0, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0)
  br label %endif-block

endif-block:                                      ; preds = %main_body, %if-true-block
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %18, float %19, float %20, float %21)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare i32 @llvm.SI.tid() #2

declare void @llvm.SI.tbuffer.store.i32(<16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32)

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR6_SGPR7 in %vreg7, %SGPR8_SGPR9 in %vreg8, %SGPR11 in %vreg10, %SGPR12 in %vreg11, %SGPR13 in %vreg12, %VGPR0 in %vreg13

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR6_SGPR7 %SGPR8_SGPR9 %SGPR11 %SGPR12 %SGPR13 %VGPR0
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%14](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LSHR_B32 %SGPR11<kill>, 16
	%VGPR4<def> = V_MOV_B32_e32 127, %EXEC<imp-use>
	%VGPR5<def> = V_AND_B32_e32 %SGPR0<kill>, %VGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MBCNT_LO_U32_B32_e64 -1, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MBCNT_HI_U32_B32_e32 -1, %VGPR4<kill>, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = V_CMP_LT_U32_e64 %VGPR4, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%SGPR0_SGPR1<def> = S_AND_SAVEEXEC_B64 %SGPR0_SGPR1, %EXEC<imp-def>, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_XOR_B64 %EXEC, %SGPR0_SGPR1
    Successors according to CFG: BB#1(16) BB#2(16)

BB#1: derived from LLVM BB %if-true-block
    Live Ins: %VGPR0_VGPR1_VGPR2_VGPR3 %SGPR8_SGPR9 %SGPR12 %SGPR13 %SGPR0_SGPR1 %VGPR4
    Predecessors according to CFG: BB#0
	%VGPR4<def> = V_ADD_I32_e32 %SGPR12<kill>, %VGPR4<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR4<def> = V_LSHLREV_B32_e32 2, %VGPR4<kill>, %EXEC<imp-use>
	%SGPR2<def> = S_LSHL_B32 %SGPR13<kill>, 2
	%VGPR4<def> = V_ADD_I32_e32 %SGPR2<kill>, %VGPR4<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR8_SGPR9<kill>, 0; mem:LD16[%27](align=8)(tbaa=!"const")
	S_WAITCNT 127
	TBUFFER_STORE_FORMAT_X %VGPR0, 0, -1, 0, -1, 0, 4, 4, %VGPR4<kill>, %SGPR4_SGPR5_SGPR6_SGPR7<kill>, -1, 0, 0, %EXEC<imp-use>
	S_WAITCNT 1792
    Successors according to CFG: BB#2

BB#2: derived from LLVM BB %endif-block
    Live Ins: %VGPR0_VGPR1_VGPR2_VGPR3 %SGPR0_SGPR1
    Predecessors according to CFG: BB#0 BB#1
	%EXEC<def> = S_OR_B64 %EXEC, %SGPR0_SGPR1
	EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR1, %VGPR2, %VGPR3, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_LOAD_DWORDX4 s[0:3], s[6:7], 0                                       ; C0800700
	S_WAITCNT lgkmcnt(0)                                                   ; BF8C007F
	BUFFER_LOAD_FORMAT_XYZW v[0:3], s[0:3][v0] + 0                         ; E00C2000 80000000
	S_LSHR_B32 s0, s11, 16                                                 ; 9000900B
	V_MOV_B32_e32 v4, 127                                                  ; 7E0802FF 0000007F
	V_AND_B32_e32 v5, s0, v4                                               ; 360A0800
	V_MBCNT_LO_U32_B32_e64 v4, -1, 0, 0, 0, 0, 0                           ; D2460004 020100C1
	V_MBCNT_HI_U32_B32_e32 v4, -1, v4                                      ; 480808C1
	V_CMP_LT_U32_e64 s[0:1], v4, v5, 0, 0, 0, 0                            ; D1820000 02020B04
	S_WAITCNT vmcnt(0)                                                     ; BF8C0770
	S_AND_SAVEEXEC_B64 s[0:1], s[0:1]                                      ; BE802400
	S_XOR_B64 s[0:1], exec, s[0:1]                                         ; 8980007E
	V_ADD_I32_e32 v4, s12, v4                                              ; 4A08080C
	V_LSHLREV_B32_e32 v4, 2, v4                                            ; 34080882
	S_LSHL_B32 s2, s13, 2                                                  ; 8F02820D
	V_ADD_I32_e32 v4, s2, v4                                               ; 4A080802
	S_LOAD_DWORDX4 s[4:7], s[8:9], 0                                       ; C0820900
	S_WAITCNT lgkmcnt(0)                                                   ; BF8C007F
	TBUFFER_STORE_FORMAT_X v0, 0, -1, 0, -1, 0, 4, 4, v4, s[4:7], -1, 0, 0 ; EA245000 80410004
	S_WAITCNT vmcnt(0) expcnt(0)                                           ; BF8C0700
	S_OR_B64 exec, exec, s[0:1]                                            ; 88FE007E
	EXP 15, 12, 0, 1, 0, v0, v1, v2, v3                                    ; F80008CF 03020100
	S_ENDPGM                                                               ; BF810000

FRAG
DCL IN[0], GENERIC[0], CONSTANT
  0: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
# Machine code for function main: Post SSA, not tracking liveness

BB#0: derived from LLVM BB %main_body
	%VGPR0<def> = V_MOV_B32_e32 0, %EXEC<imp-use>
	EXP 0, 0, 0, 1, 1, %VGPR0<kill>, %VGPR0, %VGPR0, %VGPR0, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	V_MOV_B32_e32 v0, 0               ; 7E000280
	EXP 0, 0, 0, 1, 1, v0, v0, v0, v0 ; F8001800 00000000
	S_ENDPGM                          ; BF810000

Installing breakpad exception handler for appid(steam)/version(1383158641_client)
Installing breakpad exception handler for appid(steam)/version(1383158641_client)
Installing breakpad exception handler for appid(steam)/version(1383158641_client)
Installing breakpad exception handler for appid(steam)/version(1383158641_client)
Process 790 created /arek-ValveIPCSharedObjects5
Installing breakpad exception handler for appid(steam)/version(1383158641_client)
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], COLOR, COLOR
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %21 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %4, <2 x i32> %6)
  %22 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %4, <2 x i32> %6)
  %23 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %4, <2 x i32> %6)
  %24 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %4, <2 x i32> %6)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %21, float %22, float %23, float %24)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR7 in %vreg4, %VGPR0 in %vreg5, %VGPR1 in %vreg6

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR7 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR7
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<kill,tied0>, %VGPR1, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<kill,tied0>, %VGPR1, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR4<def,tied1> = V_INTERP_P2_F32 %VGPR4<kill,tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR5<def,tied1> = V_INTERP_P2_F32 %VGPR5<kill,tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>
	EXP 15, 0, 0, 1, 1, %VGPR5<kill>, %VGPR4<kill>, %VGPR3<kill>, %VGPR2<kill>, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_WQM_B64 exec, exec                     ; BEFE0A7E
	S_MOV_B32 m0, s7                         ; BEFC0307
	V_INTERP_P1_F32 v2, v0, 3, 0, [m0]       ; C8080300
	V_INTERP_P2_F32 v2, [v2], v1, 3, 0, [m0] ; C8090301
	V_INTERP_P1_F32 v3, v0, 2, 0, [m0]       ; C80C0200
	V_INTERP_P2_F32 v3, [v3], v1, 2, 0, [m0] ; C80D0201
	V_INTERP_P1_F32 v4, v0, 1, 0, [m0]       ; C8100100
	V_INTERP_P2_F32 v4, [v4], v1, 1, 0, [m0] ; C8110101
	V_INTERP_P1_F32 v5, v0, 0, 0, [m0]       ; C8140000
	V_INTERP_P2_F32 v5, [v5], v1, 0, 0, [m0] ; C8150001
	EXP 15, 0, 0, 1, 1, v5, v4, v3, v2       ; F800180F 02030405
	S_ENDPGM                                 ; BF810000

VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], COLOR
DCL CONST[0..3]
DCL TEMP[0]
  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
  4: MOV_SAT OUT[1], IN[1]
  5: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0)
  %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4)
  %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8)
  %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12)
  %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16)
  %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20)
  %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24)
  %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28)
  %20 = call float @llvm.SI.load.const(<16 x i8> %11, i32 32)
  %21 = call float @llvm.SI.load.const(<16 x i8> %11, i32 36)
  %22 = call float @llvm.SI.load.const(<16 x i8> %11, i32 40)
  %23 = call float @llvm.SI.load.const(<16 x i8> %11, i32 44)
  %24 = call float @llvm.SI.load.const(<16 x i8> %11, i32 48)
  %25 = call float @llvm.SI.load.const(<16 x i8> %11, i32 52)
  %26 = call float @llvm.SI.load.const(<16 x i8> %11, i32 56)
  %27 = call float @llvm.SI.load.const(<16 x i8> %11, i32 60)
  %28 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0
  %29 = load <16 x i8> addrspace(2)* %28, !tbaa !0
  %30 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %29, i32 0, i32 %6)
  %31 = extractelement <4 x float> %30, i32 0
  %32 = extractelement <4 x float> %30, i32 1
  %33 = extractelement <4 x float> %30, i32 2
  %34 = extractelement <4 x float> %30, i32 3
  %35 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 1
  %36 = load <16 x i8> addrspace(2)* %35, !tbaa !0
  %37 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %36, i32 0, i32 %6)
  %38 = extractelement <4 x float> %37, i32 0
  %39 = extractelement <4 x float> %37, i32 1
  %40 = extractelement <4 x float> %37, i32 2
  %41 = extractelement <4 x float> %37, i32 3
  %42 = fmul float %31, %12
  %43 = fmul float %31, %13
  %44 = fmul float %31, %14
  %45 = fmul float %31, %15
  %46 = fmul float %32, %16
  %47 = fadd float %46, %42
  %48 = fmul float %32, %17
  %49 = fadd float %48, %43
  %50 = fmul float %32, %18
  %51 = fadd float %50, %44
  %52 = fmul float %32, %19
  %53 = fadd float %52, %45
  %54 = fmul float %33, %20
  %55 = fadd float %54, %47
  %56 = fmul float %33, %21
  %57 = fadd float %56, %49
  %58 = fmul float %33, %22
  %59 = fadd float %58, %51
  %60 = fmul float %33, %23
  %61 = fadd float %60, %53
  %62 = fmul float %34, %24
  %63 = fadd float %62, %55
  %64 = fmul float %34, %25
  %65 = fadd float %64, %57
  %66 = fmul float %34, %26
  %67 = fadd float %66, %59
  %68 = fmul float %34, %27
  %69 = fadd float %68, %61
  %70 = call float @llvm.AMDIL.clamp.(float %38, float 0.000000e+00, float 1.000000e+00)
  %71 = call float @llvm.AMDIL.clamp.(float %39, float 0.000000e+00, float 1.000000e+00)
  %72 = call float @llvm.AMDIL.clamp.(float %40, float 0.000000e+00, float 1.000000e+00)
  %73 = call float @llvm.AMDIL.clamp.(float %41, float 0.000000e+00, float 1.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %70, float %71, float %72, float %73)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %63, float %65, float %67, float %69)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg6

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%40](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%VGPR1_VGPR2_VGPR3_VGPR4<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR5<def> = V_ADD_F32_e64 0, %VGPR4, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_ADD_F32_e64 0, %VGPR3, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_ADD_F32_e64 0, %VGPR2, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_ADD_F32_e64 0, %VGPR1, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR1_VGPR2_VGPR3_VGPR4<imp-use,kill>
	EXP 15, 32, 0, 0, 0, %VGPR1<kill>, %VGPR7<kill>, %VGPR6<kill>, %VGPR5<kill>, %EXEC<imp-use>
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%31](align=8)(tbaa=!"const")
	S_WAITCNT 15
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%11](align=8)(tbaa=!"const")
	S_WAITCNT 112
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 3; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR4<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e64 %VGPR0, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 7; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR1, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 11; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR2, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 15; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR3, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MUL_F32_e64 %VGPR0, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 6; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR1, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 10; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR2, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 14; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR3, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e64 %VGPR0, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 5; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR1, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 9; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR2, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 13; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR3, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 0; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MUL_F32_e64 %VGPR0, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 4; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR8<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR1, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 8; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR8<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR2, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 12; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR8<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR3, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	EXP 15, 12, 0, 1, 0, %VGPR0<kill>, %VGPR6<kill>, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_LOAD_DWORDX4 s[8:11], s[6:7], 4               ; C0840704
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	BUFFER_LOAD_FORMAT_XYZW v[1:4], s[8:11][v0] + 0 ; E00C2000 80020100
	S_WAITCNT vmcnt(0)                              ; BF8C0770
	V_ADD_F32_e64 v5, 0, v4, 0, 1, 0, 0             ; D2060805 02020880
	V_ADD_F32_e64 v6, 0, v3, 0, 1, 0, 0             ; D2060806 02020680
	V_ADD_F32_e64 v7, 0, v2, 0, 1, 0, 0             ; D2060807 02020480
	V_ADD_F32_e64 v1, 0, v1, 0, 1, 0, 0             ; D2060801 02020280
	EXP 15, 32, 0, 0, 0, v1, v7, v6, v5             ; F800020F 05060701
	S_LOAD_DWORDX4 s[4:7], s[6:7], 0                ; C0820700
	S_WAITCNT expcnt(0) lgkmcnt(0)                  ; BF8C000F
	BUFFER_LOAD_FORMAT_XYZW v[0:3], s[4:7][v0] + 0  ; E00C2000 80010000
	S_LOAD_DWORDX4 s[0:3], s[0:1], 0                ; C0800100
	S_WAITCNT vmcnt(0) lgkmcnt(0)                   ; BF8C0070
	S_BUFFER_LOAD_DWORD s4, s[0:3], 3               ; C2020103
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v4, s4                            ; 7E080204
	V_MUL_F32_e64 v4, v0, v4, 0, 0, 0, 0            ; D2100004 02020900
	S_BUFFER_LOAD_DWORD s4, s[0:3], 7               ; C2020107
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v5, s4                            ; 7E0A0204
	V_MAD_F32 v4, v1, v5, v4, 0, 0, 0, 0            ; D2820004 04120B01
	S_BUFFER_LOAD_DWORD s4, s[0:3], 11              ; C202010B
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v5, s4                            ; 7E0A0204
	V_MAD_F32 v4, v2, v5, v4, 0, 0, 0, 0            ; D2820004 04120B02
	S_BUFFER_LOAD_DWORD s4, s[0:3], 15              ; C202010F
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v5, s4                            ; 7E0A0204
	V_MAD_F32 v4, v3, v5, v4, 0, 0, 0, 0            ; D2820004 04120B03
	S_BUFFER_LOAD_DWORD s4, s[0:3], 2               ; C2020102
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v5, s4                            ; 7E0A0204
	V_MUL_F32_e64 v5, v0, v5, 0, 0, 0, 0            ; D2100005 02020B00
	S_BUFFER_LOAD_DWORD s4, s[0:3], 6               ; C2020106
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v6, s4                            ; 7E0C0204
	V_MAD_F32 v5, v1, v6, v5, 0, 0, 0, 0            ; D2820005 04160D01
	S_BUFFER_LOAD_DWORD s4, s[0:3], 10              ; C202010A
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v6, s4                            ; 7E0C0204
	V_MAD_F32 v5, v2, v6, v5, 0, 0, 0, 0            ; D2820005 04160D02
	S_BUFFER_LOAD_DWORD s4, s[0:3], 14              ; C202010E
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v6, s4                            ; 7E0C0204
	V_MAD_F32 v5, v3, v6, v5, 0, 0, 0, 0            ; D2820005 04160D03
	S_BUFFER_LOAD_DWORD s4, s[0:3], 1               ; C2020101
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v6, s4                            ; 7E0C0204
	V_MUL_F32_e64 v6, v0, v6, 0, 0, 0, 0            ; D2100006 02020D00
	S_BUFFER_LOAD_DWORD s4, s[0:3], 5               ; C2020105
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v7, s4                            ; 7E0E0204
	V_MAD_F32 v6, v1, v7, v6, 0, 0, 0, 0            ; D2820006 041A0F01
	S_BUFFER_LOAD_DWORD s4, s[0:3], 9               ; C2020109
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v7, s4                            ; 7E0E0204
	V_MAD_F32 v6, v2, v7, v6, 0, 0, 0, 0            ; D2820006 041A0F02
	S_BUFFER_LOAD_DWORD s4, s[0:3], 13              ; C202010D
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v7, s4                            ; 7E0E0204
	V_MAD_F32 v6, v3, v7, v6, 0, 0, 0, 0            ; D2820006 041A0F03
	S_BUFFER_LOAD_DWORD s4, s[0:3], 0               ; C2020100
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v7, s4                            ; 7E0E0204
	V_MUL_F32_e64 v7, v0, v7, 0, 0, 0, 0            ; D2100007 02020F00
	S_BUFFER_LOAD_DWORD s4, s[0:3], 4               ; C2020104
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v8, s4                            ; 7E100204
	V_MAD_F32 v7, v1, v8, v7, 0, 0, 0, 0            ; D2820007 041E1101
	S_BUFFER_LOAD_DWORD s4, s[0:3], 8               ; C2020108
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v8, s4                            ; 7E100204
	V_MAD_F32 v7, v2, v8, v7, 0, 0, 0, 0            ; D2820007 041E1102
	S_BUFFER_LOAD_DWORD s0, s[0:3], 12              ; C200010C
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v8, s0                            ; 7E100200
	V_MAD_F32 v0, v3, v8, v7, 0, 0, 0, 0            ; D2820000 041E1103
	EXP 15, 12, 0, 1, 0, v0, v6, v5, v4             ; F80008CF 04050600
	S_ENDPGM                                        ; BF810000

FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %21 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %4)
  %22 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %4)
  %23 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %4)
  %24 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %4)
  %25 = call i32 @llvm.SI.packf16(float %21, float %22)
  %26 = bitcast i32 %25 to float
  %27 = call i32 @llvm.SI.packf16(float %23, float %24)
  %28 = bitcast i32 %27 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %26, float %28, float %26, float %28)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR7 in %vreg4

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR7
	%EXEC<def> = S_WQM_B64 %EXEC
	%M0<def> = S_MOV_B32 %SGPR7
	%VGPR0<def> = V_INTERP_MOV_F32 2, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_INTERP_MOV_F32 2, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR1<kill>, %VGPR0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_INTERP_MOV_F32 2, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_INTERP_MOV_F32 2, 0, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR2<kill>, %VGPR1<kill>, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR1<kill>, %VGPR0<kill>, %VGPR1, %VGPR0, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_WQM_B64 exec, exec                ; BEFE0A7E
	S_MOV_B32 m0, s7                    ; BEFC0307
	V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302
	V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202
	V_CVT_PKRTZ_F16_F32_e32 v0, v1, v0  ; 5E000101
	V_INTERP_MOV_F32 v1, P0, 1, 0, [m0] ; C8060102
	V_INTERP_MOV_F32 v2, P0, 0, 0, [m0] ; C80A0002
	V_CVT_PKRTZ_F16_F32_e32 v1, v2, v1  ; 5E020302
	EXP 15, 0, 1, 1, 1, v1, v0, v1, v0  ; F8001C0F 00010001
	S_ENDPGM                            ; BF810000

FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[0], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL CONST[1..4]
DCL TEMP[0], LOCAL
  0: MOV TEMP[0].xy, IN[0].xyyy
  1: MOV TEMP[0].w, IN[0].wwww
  2: TXP TEMP[0], TEMP[0], SAMP[0], 2D
  3: MUL TEMP[0], TEMP[0], CONST[4]
  4: MOV OUT[0], TEMP[0]
  5: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %21 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
  %22 = load <16 x i8> addrspace(2)* %21, !tbaa !0
  %23 = call float @llvm.SI.load.const(<16 x i8> %22, i32 64)
  %24 = call float @llvm.SI.load.const(<16 x i8> %22, i32 68)
  %25 = call float @llvm.SI.load.const(<16 x i8> %22, i32 72)
  %26 = call float @llvm.SI.load.const(<16 x i8> %22, i32 76)
  %27 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0
  %28 = load <32 x i8> addrspace(2)* %27, !tbaa !0
  %29 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0
  %30 = load <16 x i8> addrspace(2)* %29, !tbaa !0
  %31 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %4, <2 x i32> %6)
  %32 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %4, <2 x i32> %6)
  %33 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %4, <2 x i32> %6)
  %34 = fdiv float %31, %33
  %35 = fdiv float %32, %33
  %36 = bitcast float %34 to i32
  %37 = bitcast float %35 to i32
  %38 = insertelement <2 x i32> undef, i32 %36, i32 0
  %39 = insertelement <2 x i32> %38, i32 %37, i32 1
  %40 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %39, <32 x i8> %28, <16 x i8> %30, i32 2)
  %41 = extractelement <4 x float> %40, i32 0
  %42 = extractelement <4 x float> %40, i32 1
  %43 = extractelement <4 x float> %40, i32 2
  %44 = extractelement <4 x float> %40, i32 3
  %45 = fmul float %41, %23
  %46 = fmul float %42, %24
  %47 = fmul float %43, %25
  %48 = fmul float %44, %26
  %49 = call i32 @llvm.SI.packf16(float %45, float %46)
  %50 = bitcast i32 %49 to float
  %51 = call i32 @llvm.SI.packf16(float %47, float %48)
  %52 = bitcast i32 %51 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %50, float %52, float %50, float %52)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR7 in %vreg4, %VGPR0 in %vreg5, %VGPR1 in %vreg6

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR7 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR7
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<kill,tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<kill,tied0>, %VGPR1, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_RCP_F32_e32 %VGPR3<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MUL_F32_e32 %VGPR2<kill>, %VGPR3, %EXEC<imp-use>, %VGPR4_VGPR5<imp-def>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<kill,tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>
	%VGPR4<def> = V_MUL_F32_e32 %VGPR2<kill>, %VGPR3<kill>, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%32](align=8)(tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%29](tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = IMAGE_SAMPLE_V4_V2 15, 0, 0, 0, 0, 0, 0, 0, %VGPR4_VGPR5<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%22](align=8)(tbaa=!"const")
	S_WAITCNT 112
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 19; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR4<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e64 %VGPR3, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 18; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MUL_F32_e64 %VGPR2, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 17; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MUL_F32_e64 %VGPR1, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 16; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_F32_e64 %VGPR0, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0<kill>, %VGPR5<kill>, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR0<kill>, %VGPR4<kill>, %VGPR0, %VGPR4, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_WQM_B64 exec, exec                                                    ; BEFE0A7E
	S_MOV_B32 m0, s7                                                        ; BEFC0307
	V_INTERP_P1_F32 v2, v0, 1, 0, [m0]                                      ; C8080100
	V_INTERP_P2_F32 v2, [v2], v1, 1, 0, [m0]                                ; C8090101
	V_INTERP_P1_F32 v3, v0, 3, 0, [m0]                                      ; C80C0300
	V_INTERP_P2_F32 v3, [v3], v1, 3, 0, [m0]                                ; C80D0301
	V_RCP_F32_e32 v3, v3                                                    ; 7E065503
	V_MUL_F32_e32 v5, v2, v3                                                ; 100A0702
	V_INTERP_P1_F32 v2, v0, 0, 0, [m0]                                      ; C8080000
	V_INTERP_P2_F32 v2, [v2], v1, 0, 0, [m0]                                ; C8090001
	V_MUL_F32_e32 v4, v2, v3                                                ; 10080702
	S_LOAD_DWORDX4 s[8:11], s[2:3], 0                                       ; C0840300
	S_LOAD_DWORDX8 s[12:19], s[4:5], 0                                      ; C0C60500
	S_WAITCNT lgkmcnt(0)                                                    ; BF8C007F
	IMAGE_SAMPLE v[0:3], 15, 0, 0, 0, 0, 0, 0, 0, v[4:5], s[12:19], s[8:11] ; F0800F00 00430004
	S_LOAD_DWORDX4 s[0:3], s[0:1], 0                                        ; C0800100
	S_WAITCNT vmcnt(0) lgkmcnt(0)                                           ; BF8C0070
	S_BUFFER_LOAD_DWORD s4, s[0:3], 19                                      ; C2020113
	S_WAITCNT lgkmcnt(0)                                                    ; BF8C007F
	V_MOV_B32_e32 v4, s4                                                    ; 7E080204
	V_MUL_F32_e64 v4, v3, v4, 0, 0, 0, 0                                    ; D2100004 02020903
	S_BUFFER_LOAD_DWORD s4, s[0:3], 18                                      ; C2020112
	S_WAITCNT lgkmcnt(0)                                                    ; BF8C007F
	V_MOV_B32_e32 v5, s4                                                    ; 7E0A0204
	V_MUL_F32_e64 v5, v2, v5, 0, 0, 0, 0                                    ; D2100005 02020B02
	V_CVT_PKRTZ_F16_F32_e32 v4, v5, v4                                      ; 5E080905
	S_BUFFER_LOAD_DWORD s4, s[0:3], 17                                      ; C2020111
	S_WAITCNT lgkmcnt(0)                                                    ; BF8C007F
	V_MOV_B32_e32 v5, s4                                                    ; 7E0A0204
	V_MUL_F32_e64 v5, v1, v5, 0, 0, 0, 0                                    ; D2100005 02020B01
	S_BUFFER_LOAD_DWORD s0, s[0:3], 16                                      ; C2000110
	S_WAITCNT lgkmcnt(0)                                                    ; BF8C007F
	V_MOV_B32_e32 v6, s0                                                    ; 7E0C0200
	V_MUL_F32_e64 v0, v0, v6, 0, 0, 0, 0                                    ; D2100000 02020D00
	V_CVT_PKRTZ_F16_F32_e32 v0, v0, v5                                      ; 5E000B00
	EXP 15, 0, 1, 1, 1, v0, v4, v0, v4                                      ; F8001C0F 04000400
	S_ENDPGM                                                                ; BF810000

VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[0]
DCL CONST[0..3]
DCL TEMP[0]
  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
  4: MOV OUT[1], IN[1]
  5: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0)
  %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4)
  %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8)
  %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12)
  %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16)
  %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20)
  %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24)
  %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28)
  %20 = call float @llvm.SI.load.const(<16 x i8> %11, i32 32)
  %21 = call float @llvm.SI.load.const(<16 x i8> %11, i32 36)
  %22 = call float @llvm.SI.load.const(<16 x i8> %11, i32 40)
  %23 = call float @llvm.SI.load.const(<16 x i8> %11, i32 44)
  %24 = call float @llvm.SI.load.const(<16 x i8> %11, i32 48)
  %25 = call float @llvm.SI.load.const(<16 x i8> %11, i32 52)
  %26 = call float @llvm.SI.load.const(<16 x i8> %11, i32 56)
  %27 = call float @llvm.SI.load.const(<16 x i8> %11, i32 60)
  %28 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0
  %29 = load <16 x i8> addrspace(2)* %28, !tbaa !0
  %30 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %29, i32 0, i32 %6)
  %31 = extractelement <4 x float> %30, i32 0
  %32 = extractelement <4 x float> %30, i32 1
  %33 = extractelement <4 x float> %30, i32 2
  %34 = extractelement <4 x float> %30, i32 3
  %35 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 1
  %36 = load <16 x i8> addrspace(2)* %35, !tbaa !0
  %37 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %36, i32 0, i32 %6)
  %38 = extractelement <4 x float> %37, i32 0
  %39 = extractelement <4 x float> %37, i32 1
  %40 = extractelement <4 x float> %37, i32 2
  %41 = extractelement <4 x float> %37, i32 3
  %42 = fmul float %31, %12
  %43 = fmul float %31, %13
  %44 = fmul float %31, %14
  %45 = fmul float %31, %15
  %46 = fmul float %32, %16
  %47 = fadd float %46, %42
  %48 = fmul float %32, %17
  %49 = fadd float %48, %43
  %50 = fmul float %32, %18
  %51 = fadd float %50, %44
  %52 = fmul float %32, %19
  %53 = fadd float %52, %45
  %54 = fmul float %33, %20
  %55 = fadd float %54, %47
  %56 = fmul float %33, %21
  %57 = fadd float %56, %49
  %58 = fmul float %33, %22
  %59 = fadd float %58, %51
  %60 = fmul float %33, %23
  %61 = fadd float %60, %53
  %62 = fmul float %34, %24
  %63 = fadd float %62, %55
  %64 = fmul float %34, %25
  %65 = fadd float %64, %57
  %66 = fmul float %34, %26
  %67 = fadd float %66, %59
  %68 = fmul float %34, %27
  %69 = fadd float %68, %61
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %38, float %39, float %40, float %41)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %63, float %65, float %67, float %69)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg6

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%40](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%VGPR1_VGPR2_VGPR3_VGPR4<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	EXP 15, 32, 0, 0, 0, %VGPR1, %VGPR2, %VGPR3, %VGPR4, %EXEC<imp-use>, %VGPR1_VGPR2_VGPR3_VGPR4<imp-use,kill>
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%31](align=8)(tbaa=!"const")
	S_WAITCNT 15
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%11](align=8)(tbaa=!"const")
	S_WAITCNT 112
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 3; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR4<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e64 %VGPR0, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 7; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR1, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 11; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR2, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 15; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR3, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MUL_F32_e64 %VGPR0, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 6; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR1, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 10; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR2, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 14; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR3, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e64 %VGPR0, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 5; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR1, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 9; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR2, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 13; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR3, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 0; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MUL_F32_e64 %VGPR0, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 4; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR8<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR1, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 8; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR8<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR2, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 12; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR8<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR3, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	EXP 15, 12, 0, 1, 0, %VGPR0<kill>, %VGPR6<kill>, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_LOAD_DWORDX4 s[8:11], s[6:7], 4               ; C0840704
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	BUFFER_LOAD_FORMAT_XYZW v[1:4], s[8:11][v0] + 0 ; E00C2000 80020100
	S_WAITCNT vmcnt(0)                              ; BF8C0770
	EXP 15, 32, 0, 0, 0, v1, v2, v3, v4             ; F800020F 04030201
	S_LOAD_DWORDX4 s[4:7], s[6:7], 0                ; C0820700
	S_WAITCNT expcnt(0) lgkmcnt(0)                  ; BF8C000F
	BUFFER_LOAD_FORMAT_XYZW v[0:3], s[4:7][v0] + 0  ; E00C2000 80010000
	S_LOAD_DWORDX4 s[0:3], s[0:1], 0                ; C0800100
	S_WAITCNT vmcnt(0) lgkmcnt(0)                   ; BF8C0070
	S_BUFFER_LOAD_DWORD s4, s[0:3], 3               ; C2020103
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v4, s4                            ; 7E080204
	V_MUL_F32_e64 v4, v0, v4, 0, 0, 0, 0            ; D2100004 02020900
	S_BUFFER_LOAD_DWORD s4, s[0:3], 7               ; C2020107
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v5, s4                            ; 7E0A0204
	V_MAD_F32 v4, v1, v5, v4, 0, 0, 0, 0            ; D2820004 04120B01
	S_BUFFER_LOAD_DWORD s4, s[0:3], 11              ; C202010B
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v5, s4                            ; 7E0A0204
	V_MAD_F32 v4, v2, v5, v4, 0, 0, 0, 0            ; D2820004 04120B02
	S_BUFFER_LOAD_DWORD s4, s[0:3], 15              ; C202010F
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v5, s4                            ; 7E0A0204
	V_MAD_F32 v4, v3, v5, v4, 0, 0, 0, 0            ; D2820004 04120B03
	S_BUFFER_LOAD_DWORD s4, s[0:3], 2               ; C2020102
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v5, s4                            ; 7E0A0204
	V_MUL_F32_e64 v5, v0, v5, 0, 0, 0, 0            ; D2100005 02020B00
	S_BUFFER_LOAD_DWORD s4, s[0:3], 6               ; C2020106
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v6, s4                            ; 7E0C0204
	V_MAD_F32 v5, v1, v6, v5, 0, 0, 0, 0            ; D2820005 04160D01
	S_BUFFER_LOAD_DWORD s4, s[0:3], 10              ; C202010A
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v6, s4                            ; 7E0C0204
	V_MAD_F32 v5, v2, v6, v5, 0, 0, 0, 0            ; D2820005 04160D02
	S_BUFFER_LOAD_DWORD s4, s[0:3], 14              ; C202010E
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v6, s4                            ; 7E0C0204
	V_MAD_F32 v5, v3, v6, v5, 0, 0, 0, 0            ; D2820005 04160D03
	S_BUFFER_LOAD_DWORD s4, s[0:3], 1               ; C2020101
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v6, s4                            ; 7E0C0204
	V_MUL_F32_e64 v6, v0, v6, 0, 0, 0, 0            ; D2100006 02020D00
	S_BUFFER_LOAD_DWORD s4, s[0:3], 5               ; C2020105
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v7, s4                            ; 7E0E0204
	V_MAD_F32 v6, v1, v7, v6, 0, 0, 0, 0            ; D2820006 041A0F01
	S_BUFFER_LOAD_DWORD s4, s[0:3], 9               ; C2020109
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v7, s4                            ; 7E0E0204
	V_MAD_F32 v6, v2, v7, v6, 0, 0, 0, 0            ; D2820006 041A0F02
	S_BUFFER_LOAD_DWORD s4, s[0:3], 13              ; C202010D
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v7, s4                            ; 7E0E0204
	V_MAD_F32 v6, v3, v7, v6, 0, 0, 0, 0            ; D2820006 041A0F03
	S_BUFFER_LOAD_DWORD s4, s[0:3], 0               ; C2020100
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v7, s4                            ; 7E0E0204
	V_MUL_F32_e64 v7, v0, v7, 0, 0, 0, 0            ; D2100007 02020F00
	S_BUFFER_LOAD_DWORD s4, s[0:3], 4               ; C2020104
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v8, s4                            ; 7E100204
	V_MAD_F32 v7, v1, v8, v7, 0, 0, 0, 0            ; D2820007 041E1101
	S_BUFFER_LOAD_DWORD s4, s[0:3], 8               ; C2020108
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v8, s4                            ; 7E100204
	V_MAD_F32 v7, v2, v8, v7, 0, 0, 0, 0            ; D2820007 041E1102
	S_BUFFER_LOAD_DWORD s0, s[0:3], 12              ; C200010C
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v8, s0                            ; 7E100200
	V_MAD_F32 v0, v3, v8, v7, 0, 0, 0, 0            ; D2820000 041E1103
	EXP 15, 12, 0, 1, 0, v0, v6, v5, v4             ; F80008CF 04050600
	S_ENDPGM                                        ; BF810000

Generating new string page texture 2: 48x256, total string texture memory is 49.15 KB
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], COLOR, COLOR
DCL IN[1], GENERIC[0], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL TEMP[0], LOCAL
  0: MOV TEMP[0].xy, IN[1].xyyy
  1: MOV TEMP[0].w, IN[1].wwww
  2: TXP TEMP[0], TEMP[0], SAMP[0], 2D
  3: MUL TEMP[0], TEMP[0], IN[0]
  4: MOV OUT[0], TEMP[0]
  5: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %21 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0
  %22 = load <32 x i8> addrspace(2)* %21, !tbaa !0
  %23 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0
  %24 = load <16 x i8> addrspace(2)* %23, !tbaa !0
  %25 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %4, <2 x i32> %6)
  %26 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %4, <2 x i32> %6)
  %27 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %4, <2 x i32> %6)
  %28 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %4, <2 x i32> %6)
  %29 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %4, <2 x i32> %6)
  %30 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %4, <2 x i32> %6)
  %31 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %4, <2 x i32> %6)
  %32 = fdiv float %29, %31
  %33 = fdiv float %30, %31
  %34 = bitcast float %32 to i32
  %35 = bitcast float %33 to i32
  %36 = insertelement <2 x i32> undef, i32 %34, i32 0
  %37 = insertelement <2 x i32> %36, i32 %35, i32 1
  %38 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %37, <32 x i8> %22, <16 x i8> %24, i32 2)
  %39 = extractelement <4 x float> %38, i32 0
  %40 = extractelement <4 x float> %38, i32 1
  %41 = extractelement <4 x float> %38, i32 2
  %42 = extractelement <4 x float> %38, i32 3
  %43 = fmul float %39, %25
  %44 = fmul float %40, %26
  %45 = fmul float %41, %27
  %46 = fmul float %42, %28
  %47 = call i32 @llvm.SI.packf16(float %43, float %44)
  %48 = bitcast i32 %47 to float
  %49 = call i32 @llvm.SI.packf16(float %45, float %46)
  %50 = bitcast i32 %49 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %48, float %50, float %48, float %50)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR7 in %vreg4, %VGPR0 in %vreg5, %VGPR1 in %vreg6

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR7 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR7
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 1, 1, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<kill,tied0>, %VGPR1, 1, 1, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 3, 1, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<kill,tied0>, %VGPR1, 3, 1, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_RCP_F32_e32 %VGPR3<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MUL_F32_e32 %VGPR2<kill>, %VGPR3, %EXEC<imp-use>, %VGPR4_VGPR5<imp-def>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 1, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<kill,tied0>, %VGPR1, 0, 1, %M0<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e32 %VGPR2<kill>, %VGPR3<kill>, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%24](align=8)(tbaa=!"const")
	%SGPR8_SGPR9_SGPR10_SGPR11_SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%21](tbaa=!"const")
	S_WAITCNT 127
	%VGPR2_VGPR3_VGPR4_VGPR5<def> = IMAGE_SAMPLE_V4_V2 15, 0, 0, 0, 0, 0, 0, 0, %VGPR4_VGPR5<kill>, %SGPR8_SGPR9_SGPR10_SGPR11_SGPR12_SGPR13_SGPR14_SGPR15<kill>, %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_INTERP_P1_F32 %VGPR0, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR6<def,tied1> = V_INTERP_P2_F32 %VGPR6<kill,tied0>, %VGPR1, 3, 0, %M0<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR6<def> = V_MUL_F32_e32 %VGPR5, %VGPR6<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_INTERP_P1_F32 %VGPR0, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR7<def,tied1> = V_INTERP_P2_F32 %VGPR7<kill,tied0>, %VGPR1, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MUL_F32_e32 %VGPR4, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR7<kill>, %VGPR6<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR7<def,tied1> = V_INTERP_P2_F32 %VGPR7<kill,tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MUL_F32_e32 %VGPR3, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR8<def,tied1> = V_INTERP_P2_F32 %VGPR8<kill,tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR2, %VGPR8<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0<kill>, %VGPR7<kill>, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR0<kill>, %VGPR6<kill>, %VGPR0, %VGPR6, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_WQM_B64 exec, exec                                                  ; BEFE0A7E
	S_MOV_B32 m0, s7                                                      ; BEFC0307
	V_INTERP_P1_F32 v2, v0, 1, 1, [m0]                                    ; C8080500
	V_INTERP_P2_F32 v2, [v2], v1, 1, 1, [m0]                              ; C8090501
	V_INTERP_P1_F32 v3, v0, 3, 1, [m0]                                    ; C80C0700
	V_INTERP_P2_F32 v3, [v3], v1, 3, 1, [m0]                              ; C80D0701
	V_RCP_F32_e32 v3, v3                                                  ; 7E065503
	V_MUL_F32_e32 v5, v2, v3                                              ; 100A0702
	V_INTERP_P1_F32 v2, v0, 0, 1, [m0]                                    ; C8080400
	V_INTERP_P2_F32 v2, [v2], v1, 0, 1, [m0]                              ; C8090401
	V_MUL_F32_e32 v4, v2, v3                                              ; 10080702
	S_LOAD_DWORDX4 s[0:3], s[2:3], 0                                      ; C0800300
	S_LOAD_DWORDX8 s[8:15], s[4:5], 0                                     ; C0C40500
	S_WAITCNT lgkmcnt(0)                                                  ; BF8C007F
	IMAGE_SAMPLE v[2:5], 15, 0, 0, 0, 0, 0, 0, 0, v[4:5], s[8:15], s[0:3] ; F0800F00 00020204
	V_INTERP_P1_F32 v6, v0, 3, 0, [m0]                                    ; C8180300
	V_INTERP_P2_F32 v6, [v6], v1, 3, 0, [m0]                              ; C8190301
	S_WAITCNT vmcnt(0)                                                    ; BF8C0770
	V_MUL_F32_e32 v6, v5, v6                                              ; 100C0D05
	V_INTERP_P1_F32 v7, v0, 2, 0, [m0]                                    ; C81C0200
	V_INTERP_P2_F32 v7, [v7], v1, 2, 0, [m0]                              ; C81D0201
	V_MUL_F32_e32 v7, v4, v7                                              ; 100E0F04
	V_CVT_PKRTZ_F16_F32_e32 v6, v7, v6                                    ; 5E0C0D07
	V_INTERP_P1_F32 v7, v0, 1, 0, [m0]                                    ; C81C0100
	V_INTERP_P2_F32 v7, [v7], v1, 1, 0, [m0]                              ; C81D0101
	V_MUL_F32_e32 v7, v3, v7                                              ; 100E0F03
	V_INTERP_P1_F32 v8, v0, 0, 0, [m0]                                    ; C8200000
	V_INTERP_P2_F32 v8, [v8], v1, 0, 0, [m0]                              ; C8210001
	V_MUL_F32_e32 v0, v2, v8                                              ; 10001102
	V_CVT_PKRTZ_F16_F32_e32 v0, v0, v7                                    ; 5E000F00
	EXP 15, 0, 1, 1, 1, v0, v6, v0, v6                                    ; F8001C0F 06000600
	S_ENDPGM                                                              ; BF810000

VERT
DCL IN[0]
DCL IN[1]
DCL IN[2]
DCL OUT[0], POSITION
DCL OUT[1], COLOR
DCL OUT[2], GENERIC[0]
DCL CONST[0..3]
DCL TEMP[0]
  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
  4: MOV_SAT OUT[1], IN[1]
  5: MOV OUT[2], IN[2]
  6: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0)
  %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4)
  %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8)
  %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12)
  %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16)
  %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20)
  %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24)
  %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28)
  %20 = call float @llvm.SI.load.const(<16 x i8> %11, i32 32)
  %21 = call float @llvm.SI.load.const(<16 x i8> %11, i32 36)
  %22 = call float @llvm.SI.load.const(<16 x i8> %11, i32 40)
  %23 = call float @llvm.SI.load.const(<16 x i8> %11, i32 44)
  %24 = call float @llvm.SI.load.const(<16 x i8> %11, i32 48)
  %25 = call float @llvm.SI.load.const(<16 x i8> %11, i32 52)
  %26 = call float @llvm.SI.load.const(<16 x i8> %11, i32 56)
  %27 = call float @llvm.SI.load.const(<16 x i8> %11, i32 60)
  %28 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0
  %29 = load <16 x i8> addrspace(2)* %28, !tbaa !0
  %30 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %29, i32 0, i32 %6)
  %31 = extractelement <4 x float> %30, i32 0
  %32 = extractelement <4 x float> %30, i32 1
  %33 = extractelement <4 x float> %30, i32 2
  %34 = extractelement <4 x float> %30, i32 3
  %35 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 1
  %36 = load <16 x i8> addrspace(2)* %35, !tbaa !0
  %37 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %36, i32 0, i32 %6)
  %38 = extractelement <4 x float> %37, i32 0
  %39 = extractelement <4 x float> %37, i32 1
  %40 = extractelement <4 x float> %37, i32 2
  %41 = extractelement <4 x float> %37, i32 3
  %42 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 2
  %43 = load <16 x i8> addrspace(2)* %42, !tbaa !0
  %44 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %43, i32 0, i32 %6)
  %45 = extractelement <4 x float> %44, i32 0
  %46 = extractelement <4 x float> %44, i32 1
  %47 = extractelement <4 x float> %44, i32 2
  %48 = extractelement <4 x float> %44, i32 3
  %49 = fmul float %31, %12
  %50 = fmul float %31, %13
  %51 = fmul float %31, %14
  %52 = fmul float %31, %15
  %53 = fmul float %32, %16
  %54 = fadd float %53, %49
  %55 = fmul float %32, %17
  %56 = fadd float %55, %50
  %57 = fmul float %32, %18
  %58 = fadd float %57, %51
  %59 = fmul float %32, %19
  %60 = fadd float %59, %52
  %61 = fmul float %33, %20
  %62 = fadd float %61, %54
  %63 = fmul float %33, %21
  %64 = fadd float %63, %56
  %65 = fmul float %33, %22
  %66 = fadd float %65, %58
  %67 = fmul float %33, %23
  %68 = fadd float %67, %60
  %69 = fmul float %34, %24
  %70 = fadd float %69, %62
  %71 = fmul float %34, %25
  %72 = fadd float %71, %64
  %73 = fmul float %34, %26
  %74 = fadd float %73, %66
  %75 = fmul float %34, %27
  %76 = fadd float %75, %68
  %77 = call float @llvm.AMDIL.clamp.(float %38, float 0.000000e+00, float 1.000000e+00)
  %78 = call float @llvm.AMDIL.clamp.(float %39, float 0.000000e+00, float 1.000000e+00)
  %79 = call float @llvm.AMDIL.clamp.(float %40, float 0.000000e+00, float 1.000000e+00)
  %80 = call float @llvm.AMDIL.clamp.(float %41, float 0.000000e+00, float 1.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %77, float %78, float %79, float %80)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %45, float %46, float %47, float %48)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %70, float %72, float %74, float %76)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg6

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%40](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%VGPR1_VGPR2_VGPR3_VGPR4<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR5<def> = V_ADD_F32_e64 0, %VGPR4, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_ADD_F32_e64 0, %VGPR3, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_ADD_F32_e64 0, %VGPR2, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_ADD_F32_e64 0, %VGPR1, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR1_VGPR2_VGPR3_VGPR4<imp-use,kill>
	EXP 15, 32, 0, 0, 0, %VGPR1<kill>, %VGPR7<kill>, %VGPR6<kill>, %VGPR5<kill>, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 8; mem:LD16[%49](align=8)(tbaa=!"const")
	S_WAITCNT 15
	%VGPR1_VGPR2_VGPR3_VGPR4<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	EXP 15, 33, 0, 0, 0, %VGPR1, %VGPR2, %VGPR3, %VGPR4, %EXEC<imp-use>, %VGPR1_VGPR2_VGPR3_VGPR4<imp-use,kill>
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%31](align=8)(tbaa=!"const")
	S_WAITCNT 15
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%11](align=8)(tbaa=!"const")
	S_WAITCNT 112
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 3; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR4<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e64 %VGPR0, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 7; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR1, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 11; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR2, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 15; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR3, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MUL_F32_e64 %VGPR0, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 6; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR1, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 10; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR2, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 14; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR3, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e64 %VGPR0, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 5; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR1, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 9; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR2, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 13; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR3, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 0; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MUL_F32_e64 %VGPR0, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 4; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR8<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR1, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 8; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR8<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR2, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 12; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR8<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR3, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	EXP 15, 12, 0, 1, 0, %VGPR0<kill>, %VGPR6<kill>, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_LOAD_DWORDX4 s[8:11], s[6:7], 4               ; C0840704
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	BUFFER_LOAD_FORMAT_XYZW v[1:4], s[8:11][v0] + 0 ; E00C2000 80020100
	S_WAITCNT vmcnt(0)                              ; BF8C0770
	V_ADD_F32_e64 v5, 0, v4, 0, 1, 0, 0             ; D2060805 02020880
	V_ADD_F32_e64 v6, 0, v3, 0, 1, 0, 0             ; D2060806 02020680
	V_ADD_F32_e64 v7, 0, v2, 0, 1, 0, 0             ; D2060807 02020480
	V_ADD_F32_e64 v1, 0, v1, 0, 1, 0, 0             ; D2060801 02020280
	EXP 15, 32, 0, 0, 0, v1, v7, v6, v5             ; F800020F 05060701
	S_LOAD_DWORDX4 s[8:11], s[6:7], 8               ; C0840708
	S_WAITCNT expcnt(0) lgkmcnt(0)                  ; BF8C000F
	BUFFER_LOAD_FORMAT_XYZW v[1:4], s[8:11][v0] + 0 ; E00C2000 80020100
	S_WAITCNT vmcnt(0)                              ; BF8C0770
	EXP 15, 33, 0, 0, 0, v1, v2, v3, v4             ; F800021F 04030201
	S_LOAD_DWORDX4 s[4:7], s[6:7], 0                ; C0820700
	S_WAITCNT expcnt(0) lgkmcnt(0)                  ; BF8C000F
	BUFFER_LOAD_FORMAT_XYZW v[0:3], s[4:7][v0] + 0  ; E00C2000 80010000
	S_LOAD_DWORDX4 s[0:3], s[0:1], 0                ; C0800100
	S_WAITCNT vmcnt(0) lgkmcnt(0)                   ; BF8C0070
	S_BUFFER_LOAD_DWORD s4, s[0:3], 3               ; C2020103
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v4, s4                            ; 7E080204
	V_MUL_F32_e64 v4, v0, v4, 0, 0, 0, 0            ; D2100004 02020900
	S_BUFFER_LOAD_DWORD s4, s[0:3], 7               ; C2020107
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v5, s4                            ; 7E0A0204
	V_MAD_F32 v4, v1, v5, v4, 0, 0, 0, 0            ; D2820004 04120B01
	S_BUFFER_LOAD_DWORD s4, s[0:3], 11              ; C202010B
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v5, s4                            ; 7E0A0204
	V_MAD_F32 v4, v2, v5, v4, 0, 0, 0, 0            ; D2820004 04120B02
	S_BUFFER_LOAD_DWORD s4, s[0:3], 15              ; C202010F
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v5, s4                            ; 7E0A0204
	V_MAD_F32 v4, v3, v5, v4, 0, 0, 0, 0            ; D2820004 04120B03
	S_BUFFER_LOAD_DWORD s4, s[0:3], 2               ; C2020102
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v5, s4                            ; 7E0A0204
	V_MUL_F32_e64 v5, v0, v5, 0, 0, 0, 0            ; D2100005 02020B00
	S_BUFFER_LOAD_DWORD s4, s[0:3], 6               ; C2020106
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v6, s4                            ; 7E0C0204
	V_MAD_F32 v5, v1, v6, v5, 0, 0, 0, 0            ; D2820005 04160D01
	S_BUFFER_LOAD_DWORD s4, s[0:3], 10              ; C202010A
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v6, s4                            ; 7E0C0204
	V_MAD_F32 v5, v2, v6, v5, 0, 0, 0, 0            ; D2820005 04160D02
	S_BUFFER_LOAD_DWORD s4, s[0:3], 14              ; C202010E
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v6, s4                            ; 7E0C0204
	V_MAD_F32 v5, v3, v6, v5, 0, 0, 0, 0            ; D2820005 04160D03
	S_BUFFER_LOAD_DWORD s4, s[0:3], 1               ; C2020101
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v6, s4                            ; 7E0C0204
	V_MUL_F32_e64 v6, v0, v6, 0, 0, 0, 0            ; D2100006 02020D00
	S_BUFFER_LOAD_DWORD s4, s[0:3], 5               ; C2020105
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v7, s4                            ; 7E0E0204
	V_MAD_F32 v6, v1, v7, v6, 0, 0, 0, 0            ; D2820006 041A0F01
	S_BUFFER_LOAD_DWORD s4, s[0:3], 9               ; C2020109
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v7, s4                            ; 7E0E0204
	V_MAD_F32 v6, v2, v7, v6, 0, 0, 0, 0            ; D2820006 041A0F02
	S_BUFFER_LOAD_DWORD s4, s[0:3], 13              ; C202010D
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v7, s4                            ; 7E0E0204
	V_MAD_F32 v6, v3, v7, v6, 0, 0, 0, 0            ; D2820006 041A0F03
	S_BUFFER_LOAD_DWORD s4, s[0:3], 0               ; C2020100
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v7, s4                            ; 7E0E0204
	V_MUL_F32_e64 v7, v0, v7, 0, 0, 0, 0            ; D2100007 02020F00
	S_BUFFER_LOAD_DWORD s4, s[0:3], 4               ; C2020104
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v8, s4                            ; 7E100204
	V_MAD_F32 v7, v1, v8, v7, 0, 0, 0, 0            ; D2820007 041E1101
	S_BUFFER_LOAD_DWORD s4, s[0:3], 8               ; C2020108
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v8, s4                            ; 7E100204
	V_MAD_F32 v7, v2, v8, v7, 0, 0, 0, 0            ; D2820007 041E1102
	S_BUFFER_LOAD_DWORD s0, s[0:3], 12              ; C200010C
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v8, s0                            ; 7E100200
	V_MAD_F32 v0, v3, v8, v7, 0, 0, 0, 0            ; D2820000 041E1103
	EXP 15, 12, 0, 1, 0, v0, v6, v5, v4             ; F80008CF 04050600
	S_ENDPGM                                        ; BF810000

FRAG
DCL IN[0], GENERIC[0], LINEAR
DCL OUT[0], COLOR
DCL SAMP[0]
  0: TEX OUT[0], IN[0], SAMP[0], 2D
  1: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %21 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0
  %22 = load <32 x i8> addrspace(2)* %21, !tbaa !0
  %23 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0
  %24 = load <16 x i8> addrspace(2)* %23, !tbaa !0
  %25 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %4, <2 x i32> %10)
  %26 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %4, <2 x i32> %10)
  %27 = bitcast float %25 to i32
  %28 = bitcast float %26 to i32
  %29 = insertelement <2 x i32> undef, i32 %27, i32 0
  %30 = insertelement <2 x i32> %29, i32 %28, i32 1
  %31 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %30, <32 x i8> %22, <16 x i8> %24, i32 2)
  %32 = extractelement <4 x float> %31, i32 0
  %33 = extractelement <4 x float> %31, i32 1
  %34 = extractelement <4 x float> %31, i32 2
  %35 = extractelement <4 x float> %31, i32 3
  %36 = call i32 @llvm.SI.packf16(float %32, float %33)
  %37 = bitcast i32 %36 to float
  %38 = call i32 @llvm.SI.packf16(float %34, float %35)
  %39 = bitcast i32 %38 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %37, float %39, float %37, float %39)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR7 in %vreg4, %VGPR0 in %vreg5, %VGPR1 in %vreg6

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR7 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR7
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-def>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%24](align=8)(tbaa=!"const")
	%SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%21](tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = IMAGE_SAMPLE_V4_V2 15, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3<kill>, %SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<kill>, %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR4<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR2, %VGPR3, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0, %VGPR1, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	EXP 15, 0, 1, 1, 1, %VGPR0<kill>, %VGPR4<kill>, %VGPR0, %VGPR4, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_WQM_B64 exec, exec                                                  ; BEFE0A7E
	S_MOV_B32 m0, s7                                                      ; BEFC0307
	V_INTERP_P1_F32 v3, v0, 1, 0, [m0]                                    ; C80C0100
	V_INTERP_P2_F32 v3, [v3], v1, 1, 0, [m0]                              ; C80D0101
	V_INTERP_P1_F32 v2, v0, 0, 0, [m0]                                    ; C8080000
	V_INTERP_P2_F32 v2, [v2], v1, 0, 0, [m0]                              ; C8090001
	S_LOAD_DWORDX4 s[0:3], s[2:3], 0                                      ; C0800300
	S_LOAD_DWORDX8 s[4:11], s[4:5], 0                                     ; C0C20500
	S_WAITCNT lgkmcnt(0)                                                  ; BF8C007F
	IMAGE_SAMPLE v[0:3], 15, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[4:11], s[0:3] ; F0800F00 00010002
	S_WAITCNT vmcnt(0)                                                    ; BF8C0770
	V_CVT_PKRTZ_F16_F32_e32 v4, v2, v3                                    ; 5E080702
	V_CVT_PKRTZ_F16_F32_e32 v0, v0, v1                                    ; 5E000300
	EXP 15, 0, 1, 1, 1, v0, v4, v0, v4                                    ; F8001C0F 04000400
	S_ENDPGM                                                              ; BF810000

FRAG
DCL IN[0], GENERIC[0], LINEAR
DCL OUT[0], COLOR
DCL SAMP[0]
  0: TEX OUT[0], IN[0], SAMP[0], 2D
  1: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %21 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0
  %22 = load <32 x i8> addrspace(2)* %21, !tbaa !0
  %23 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0
  %24 = load <16 x i8> addrspace(2)* %23, !tbaa !0
  %25 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %4, <2 x i32> %10)
  %26 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %4, <2 x i32> %10)
  %27 = bitcast float %25 to i32
  %28 = bitcast float %26 to i32
  %29 = insertelement <2 x i32> undef, i32 %27, i32 0
  %30 = insertelement <2 x i32> %29, i32 %28, i32 1
  %31 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %30, <32 x i8> %22, <16 x i8> %24, i32 2)
  %32 = extractelement <4 x float> %31, i32 0
  %33 = extractelement <4 x float> %31, i32 1
  %34 = extractelement <4 x float> %31, i32 2
  %35 = extractelement <4 x float> %31, i32 3
  %36 = call i32 @llvm.SI.packf16(float %32, float %33)
  %37 = bitcast i32 %36 to float
  %38 = call i32 @llvm.SI.packf16(float %34, float %35)
  %39 = bitcast i32 %38 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %37, float %39, float %37, float %39)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR7 in %vreg4, %VGPR0 in %vreg5, %VGPR1 in %vreg6

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR7 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR7
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-def>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%24](align=8)(tbaa=!"const")
	%SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%21](tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = IMAGE_SAMPLE_V4_V2 15, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3<kill>, %SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<kill>, %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR4<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR2, %VGPR3, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0, %VGPR1, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	EXP 15, 0, 1, 1, 1, %VGPR0<kill>, %VGPR4<kill>, %VGPR0, %VGPR4, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_WQM_B64 exec, exec                                                  ; BEFE0A7E
	S_MOV_B32 m0, s7                                                      ; BEFC0307
	V_INTERP_P1_F32 v3, v0, 1, 0, [m0]                                    ; C80C0100
	V_INTERP_P2_F32 v3, [v3], v1, 1, 0, [m0]                              ; C80D0101
	V_INTERP_P1_F32 v2, v0, 0, 0, [m0]                                    ; C8080000
	V_INTERP_P2_F32 v2, [v2], v1, 0, 0, [m0]                              ; C8090001
	S_LOAD_DWORDX4 s[0:3], s[2:3], 0                                      ; C0800300
	S_LOAD_DWORDX8 s[4:11], s[4:5], 0                                     ; C0C20500
	S_WAITCNT lgkmcnt(0)                                                  ; BF8C007F
	IMAGE_SAMPLE v[0:3], 15, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[4:11], s[0:3] ; F0800F00 00010002
	S_WAITCNT vmcnt(0)                                                    ; BF8C0770
	V_CVT_PKRTZ_F16_F32_e32 v4, v2, v3                                    ; 5E080702
	V_CVT_PKRTZ_F16_F32_e32 v0, v0, v1                                    ; 5E000300
	EXP 15, 0, 1, 1, 1, v0, v4, v0, v4                                    ; F8001C0F 04000400
	S_ENDPGM                                                              ; BF810000

Generating new string page texture 3: 256x256, total string texture memory is 311.30 KB
Installing breakpad exception handler for appid(steam)/version(1383158641_client)
local (potentially out of sync) copy of roaming config loaded - 1270 bytes.
Adding license for package 0
Adding license for package 2481
Adding license for package 4077
Adding license for package 6443
Adding license for package 8892
Adding license for package 12361
Adding license for package 27644
Adding license for package 34953
Adding license for package 35058
roaming config store loaded successfully - 1270 bytes.
migrating temporary roaming config store
Installing breakpad exception handler for appid(steam)/version(1383158641_client)
ExecCommandLine: "/home/arek/.local/share/Steam/ubuntu12_32/steam steam://rungameid/41070"
ExecSteamURL: "steam://rungameid/41070"
FRAG
  0: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
# Machine code for function main: Post SSA, not tracking liveness

BB#0: derived from LLVM BB %main_body
	%VGPR0<def> = V_MOV_B32_e32 0, %EXEC<imp-use>
	EXP 0, 0, 0, 1, 1, %VGPR0<kill>, %VGPR0, %VGPR0, %VGPR0, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	V_MOV_B32_e32 v0, 0               ; 7E000280
	EXP 0, 0, 0, 1, 1, v0, v0, v0, v0 ; F8001800 00000000
	S_ENDPGM                          ; BF810000

FRAG
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %21 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %4)
  %22 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %4)
  %23 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %4)
  %24 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %4)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %21, float %22, float %23, float %24)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR7 in %vreg4

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR7
	%EXEC<def> = S_WQM_B64 %EXEC
	%M0<def> = S_MOV_B32 %SGPR7
	%VGPR0<def> = V_INTERP_MOV_F32 2, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_INTERP_MOV_F32 2, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_INTERP_MOV_F32 2, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_INTERP_MOV_F32 2, 0, 0, %M0<kill>, %EXEC<imp-use>
	EXP 15, 0, 0, 1, 1, %VGPR3<kill>, %VGPR2<kill>, %VGPR1<kill>, %VGPR0<kill>, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_WQM_B64 exec, exec                ; BEFE0A7E
	S_MOV_B32 m0, s7                    ; BEFC0307
	V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302
	V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202
	V_INTERP_MOV_F32 v2, P0, 1, 0, [m0] ; C80A0102
	V_INTERP_MOV_F32 v3, P0, 0, 0, [m0] ; C80E0002
	EXP 15, 0, 0, 1, 1, v3, v2, v1, v0  ; F800180F 00010203
	S_ENDPGM                            ; BF810000

FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %21 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %4)
  %22 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %4)
  %23 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %4)
  %24 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %4)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %21, float %22, float %23, float %24)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR7 in %vreg4

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR7
	%EXEC<def> = S_WQM_B64 %EXEC
	%M0<def> = S_MOV_B32 %SGPR7
	%VGPR0<def> = V_INTERP_MOV_F32 2, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_INTERP_MOV_F32 2, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_INTERP_MOV_F32 2, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_INTERP_MOV_F32 2, 0, 0, %M0<kill>, %EXEC<imp-use>
	EXP 15, 0, 0, 1, 1, %VGPR3<kill>, %VGPR2<kill>, %VGPR1<kill>, %VGPR0<kill>, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_WQM_B64 exec, exec                ; BEFE0A7E
	S_MOV_B32 m0, s7                    ; BEFC0307
	V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302
	V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202
	V_INTERP_MOV_F32 v2, P0, 1, 0, [m0] ; C80A0102
	V_INTERP_MOV_F32 v3, P0, 0, 0, [m0] ; C80E0002
	EXP 15, 0, 0, 1, 1, v3, v2, v1, v0  ; F800180F 00010203
	S_ENDPGM                            ; BF810000

VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[0]
  0: MOV OUT[0], IN[0]
  1: MOV OUT[1], IN[1]
  2: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %11, i32 0, i32 %6)
  %13 = extractelement <4 x float> %12, i32 0
  %14 = extractelement <4 x float> %12, i32 1
  %15 = extractelement <4 x float> %12, i32 2
  %16 = extractelement <4 x float> %12, i32 3
  %17 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 1
  %18 = load <16 x i8> addrspace(2)* %17, !tbaa !0
  %19 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %18, i32 0, i32 %6)
  %20 = extractelement <4 x float> %19, i32 0
  %21 = extractelement <4 x float> %19, i32 1
  %22 = extractelement <4 x float> %19, i32 2
  %23 = extractelement <4 x float> %19, i32 3
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %20, float %21, float %22, float %23)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %13, float %14, float %15, float %16)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg6

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR6_SGPR7 %VGPR0
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%20](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%VGPR1_VGPR2_VGPR3_VGPR4<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	EXP 15, 32, 0, 0, 0, %VGPR1, %VGPR2, %VGPR3, %VGPR4, %EXEC<imp-use>, %VGPR1_VGPR2_VGPR3_VGPR4<imp-use,kill>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%11](align=8)(tbaa=!"const")
	S_WAITCNT 15
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR1, %VGPR2, %VGPR3, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_LOAD_DWORDX4 s[0:3], s[6:7], 4               ; C0800704
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	BUFFER_LOAD_FORMAT_XYZW v[1:4], s[0:3][v0] + 0 ; E00C2000 80000100
	S_WAITCNT vmcnt(0)                             ; BF8C0770
	EXP 15, 32, 0, 0, 0, v1, v2, v3, v4            ; F800020F 04030201
	S_LOAD_DWORDX4 s[0:3], s[6:7], 0               ; C0800700
	S_WAITCNT expcnt(0) lgkmcnt(0)                 ; BF8C000F
	BUFFER_LOAD_FORMAT_XYZW v[0:3], s[0:3][v0] + 0 ; E00C2000 80000000
	S_WAITCNT vmcnt(0)                             ; BF8C0770
	EXP 15, 12, 0, 1, 0, v0, v1, v2, v3            ; F80008CF 03020100
	S_ENDPGM                                       ; BF810000

VERT
DCL IN[0]
DCL OUT[0], POSITION
  0: MOV OUT[0], IN[0]
  1: END
STREAMOUT
  0: BUF0[0..0] <- OUT[0].x
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %13 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 0
  %14 = load <16 x i8> addrspace(2)* %13, !tbaa !0
  %15 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0
  %16 = load <16 x i8> addrspace(2)* %15, !tbaa !0
  %17 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %16, i32 0, i32 %9)
  %18 = extractelement <4 x float> %17, i32 0
  %19 = extractelement <4 x float> %17, i32 1
  %20 = extractelement <4 x float> %17, i32 2
  %21 = extractelement <4 x float> %17, i32 3
  %22 = lshr i32 %6, 16
  %23 = and i32 %22, 127
  %24 = call i32 @llvm.SI.tid()
  %25 = icmp ult i32 %24, %23
  br i1 %25, label %if-true-block, label %endif-block

if-true-block:                                    ; preds = %main_body
  %26 = add i32 %7, %24
  %27 = mul i32 %8, 4
  %28 = mul i32 %26, 4
  %29 = add i32 %28, %27
  %30 = bitcast float %18 to i32
  call void @llvm.SI.tbuffer.store.i32(<16 x i8> %14, i32 %30, i32 1, i32 %29, i32 0, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0)
  br label %endif-block

endif-block:                                      ; preds = %main_body, %if-true-block
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %18, float %19, float %20, float %21)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare i32 @llvm.SI.tid() #2

declare void @llvm.SI.tbuffer.store.i32(<16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32)

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR6_SGPR7 in %vreg7, %SGPR8_SGPR9 in %vreg8, %SGPR11 in %vreg10, %SGPR12 in %vreg11, %SGPR13 in %vreg12, %VGPR0 in %vreg13

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR6_SGPR7 %SGPR8_SGPR9 %SGPR11 %SGPR12 %SGPR13 %VGPR0
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%14](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LSHR_B32 %SGPR11<kill>, 16
	%VGPR4<def> = V_MOV_B32_e32 127, %EXEC<imp-use>
	%VGPR5<def> = V_AND_B32_e32 %SGPR0<kill>, %VGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MBCNT_LO_U32_B32_e64 -1, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MBCNT_HI_U32_B32_e32 -1, %VGPR4<kill>, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = V_CMP_LT_U32_e64 %VGPR4, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%SGPR0_SGPR1<def> = S_AND_SAVEEXEC_B64 %SGPR0_SGPR1, %EXEC<imp-def>, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_XOR_B64 %EXEC, %SGPR0_SGPR1
    Successors according to CFG: BB#1(16) BB#2(16)

BB#1: derived from LLVM BB %if-true-block
    Live Ins: %VGPR0_VGPR1_VGPR2_VGPR3 %SGPR8_SGPR9 %SGPR12 %SGPR13 %SGPR0_SGPR1 %VGPR4
    Predecessors according to CFG: BB#0
	%VGPR4<def> = V_ADD_I32_e32 %SGPR12<kill>, %VGPR4<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR4<def> = V_LSHLREV_B32_e32 2, %VGPR4<kill>, %EXEC<imp-use>
	%SGPR2<def> = S_LSHL_B32 %SGPR13<kill>, 2
	%VGPR4<def> = V_ADD_I32_e32 %SGPR2<kill>, %VGPR4<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR8_SGPR9<kill>, 0; mem:LD16[%27](align=8)(tbaa=!"const")
	S_WAITCNT 127
	TBUFFER_STORE_FORMAT_X %VGPR0, 0, -1, 0, -1, 0, 4, 4, %VGPR4<kill>, %SGPR4_SGPR5_SGPR6_SGPR7<kill>, -1, 0, 0, %EXEC<imp-use>
	S_WAITCNT 1792
    Successors according to CFG: BB#2

BB#2: derived from LLVM BB %endif-block
    Live Ins: %VGPR0_VGPR1_VGPR2_VGPR3 %SGPR0_SGPR1
    Predecessors according to CFG: BB#0 BB#1
	%EXEC<def> = S_OR_B64 %EXEC, %SGPR0_SGPR1
	EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR1, %VGPR2, %VGPR3, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_LOAD_DWORDX4 s[0:3], s[6:7], 0                                       ; C0800700
	S_WAITCNT lgkmcnt(0)                                                   ; BF8C007F
	BUFFER_LOAD_FORMAT_XYZW v[0:3], s[0:3][v0] + 0                         ; E00C2000 80000000
	S_LSHR_B32 s0, s11, 16                                                 ; 9000900B
	V_MOV_B32_e32 v4, 127                                                  ; 7E0802FF 0000007F
	V_AND_B32_e32 v5, s0, v4                                               ; 360A0800
	V_MBCNT_LO_U32_B32_e64 v4, -1, 0, 0, 0, 0, 0                           ; D2460004 020100C1
	V_MBCNT_HI_U32_B32_e32 v4, -1, v4                                      ; 480808C1
	V_CMP_LT_U32_e64 s[0:1], v4, v5, 0, 0, 0, 0                            ; D1820000 02020B04
	S_WAITCNT vmcnt(0)                                                     ; BF8C0770
	S_AND_SAVEEXEC_B64 s[0:1], s[0:1]                                      ; BE802400
	S_XOR_B64 s[0:1], exec, s[0:1]                                         ; 8980007E
	V_ADD_I32_e32 v4, s12, v4                                              ; 4A08080C
	V_LSHLREV_B32_e32 v4, 2, v4                                            ; 34080882
	S_LSHL_B32 s2, s13, 2                                                  ; 8F02820D
	V_ADD_I32_e32 v4, s2, v4                                               ; 4A080802
	S_LOAD_DWORDX4 s[4:7], s[8:9], 0                                       ; C0820900
	S_WAITCNT lgkmcnt(0)                                                   ; BF8C007F
	TBUFFER_STORE_FORMAT_X v0, 0, -1, 0, -1, 0, 4, 4, v4, s[4:7], -1, 0, 0 ; EA245000 80410004
	S_WAITCNT vmcnt(0) expcnt(0)                                           ; BF8C0700
	S_OR_B64 exec, exec, s[0:1]                                            ; 88FE007E
	EXP 15, 12, 0, 1, 0, v0, v1, v2, v3                                    ; F80008CF 03020100
	S_ENDPGM                                                               ; BF810000

FRAG
DCL IN[0], GENERIC[0], CONSTANT
  0: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
# Machine code for function main: Post SSA, not tracking liveness

BB#0: derived from LLVM BB %main_body
	%VGPR0<def> = V_MOV_B32_e32 0, %EXEC<imp-use>
	EXP 0, 0, 0, 1, 1, %VGPR0<kill>, %VGPR0, %VGPR0, %VGPR0, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	V_MOV_B32_e32 v0, 0               ; 7E000280
	EXP 0, 0, 0, 1, 1, v0, v0, v0, v0 ; F8001800 00000000
	S_ENDPGM                          ; BF810000

System startup time: 10.22 seconds
Generating new string page texture 64: 32x256, total string texture memory is 344.06 KB
Generating new string page texture 65: 64x256, total string texture memory is 409.60 KB
Installing breakpad exception handler for appid(steam)/version(1383158641_client)
Running Steam on arch  32-bit
STEAM_RUNTIME has been set by the user to: /home/arek/.local/share/Steam/ubuntu12_32/steam-runtime
ExecCommandLine: "/home/arek/.steam/root/ubuntu12_32/steam steam://open/driverhelperready"
ExecSteamURL: "steam://open/driverhelperready"
Game update: AppID 41070 "Serious Sam 3: BFE", ProcID 906, IP 0.0.0.0:0

(steam:790): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.

(steam:790): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.

(steam:790): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.

(steam:790): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.

(steam:790): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.

(steam:790): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.

(steam:790): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.

(steam:790): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.

(steam:790): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.

(steam:790): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.

(steam:790): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.

(steam:790): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.

(steam:790): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.

(steam:790): LIBDBUSMENU-GLIB-WARNING **: Trying to remove a child that doesn't believe we're it's parent.
cat: /etc/debian_version: No such file or directory
Setting breakpad minidump AppID = 41070
Steam_SetMinidumpSteamID:  Caching Steam ID:  76561198090478818 [API loaded no]
INF:  GameEnv API: Steam
INF:  Encoded user ID = fbc68a8b:44652b57
INF:  
INF:  * Desktop settings...
INF:  Color depth: 32-bit
INF:  Desktop resolution: 1680 x 1050
INF:  Fullscreen on primary display
FRAG
  0: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
# Machine code for function main: Post SSA, not tracking liveness

BB#0: derived from LLVM BB %main_body
	%VGPR0<def> = V_MOV_B32_e32 0, %EXEC<imp-use>
	EXP 0, 0, 0, 1, 1, %VGPR0<kill>, %VGPR0, %VGPR0, %VGPR0, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	V_MOV_B32_e32 v0, 0               ; 7E000280
	EXP 0, 0, 0, 1, 1, v0, v0, v0, v0 ; F8001800 00000000
	S_ENDPGM                          ; BF810000

FRAG
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %21 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %4)
  %22 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %4)
  %23 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %4)
  %24 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %4)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %21, float %22, float %23, float %24)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR7 in %vreg4

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR7
	%EXEC<def> = S_WQM_B64 %EXEC
	%M0<def> = S_MOV_B32 %SGPR7
	%VGPR0<def> = V_INTERP_MOV_F32 2, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_INTERP_MOV_F32 2, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_INTERP_MOV_F32 2, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_INTERP_MOV_F32 2, 0, 0, %M0<kill>, %EXEC<imp-use>
	EXP 15, 0, 0, 1, 1, %VGPR3<kill>, %VGPR2<kill>, %VGPR1<kill>, %VGPR0<kill>, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_WQM_B64 exec, exec                ; BEFE0A7E
	S_MOV_B32 m0, s7                    ; BEFC0307
	V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302
	V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202
	V_INTERP_MOV_F32 v2, P0, 1, 0, [m0] ; C80A0102
	V_INTERP_MOV_F32 v3, P0, 0, 0, [m0] ; C80E0002
	EXP 15, 0, 0, 1, 1, v3, v2, v1, v0  ; F800180F 00010203
	S_ENDPGM                            ; BF810000

FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %21 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %4)
  %22 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %4)
  %23 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %4)
  %24 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %4)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %21, float %22, float %23, float %24)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR7 in %vreg4

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR7
	%EXEC<def> = S_WQM_B64 %EXEC
	%M0<def> = S_MOV_B32 %SGPR7
	%VGPR0<def> = V_INTERP_MOV_F32 2, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_INTERP_MOV_F32 2, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_INTERP_MOV_F32 2, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_INTERP_MOV_F32 2, 0, 0, %M0<kill>, %EXEC<imp-use>
	EXP 15, 0, 0, 1, 1, %VGPR3<kill>, %VGPR2<kill>, %VGPR1<kill>, %VGPR0<kill>, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_WQM_B64 exec, exec                ; BEFE0A7E
	S_MOV_B32 m0, s7                    ; BEFC0307
	V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302
	V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202
	V_INTERP_MOV_F32 v2, P0, 1, 0, [m0] ; C80A0102
	V_INTERP_MOV_F32 v3, P0, 0, 0, [m0] ; C80E0002
	EXP 15, 0, 0, 1, 1, v3, v2, v1, v0  ; F800180F 00010203
	S_ENDPGM                            ; BF810000

VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[0]
  0: MOV OUT[0], IN[0]
  1: MOV OUT[1], IN[1]
  2: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %11, i32 0, i32 %6)
  %13 = extractelement <4 x float> %12, i32 0
  %14 = extractelement <4 x float> %12, i32 1
  %15 = extractelement <4 x float> %12, i32 2
  %16 = extractelement <4 x float> %12, i32 3
  %17 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 1
  %18 = load <16 x i8> addrspace(2)* %17, !tbaa !0
  %19 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %18, i32 0, i32 %6)
  %20 = extractelement <4 x float> %19, i32 0
  %21 = extractelement <4 x float> %19, i32 1
  %22 = extractelement <4 x float> %19, i32 2
  %23 = extractelement <4 x float> %19, i32 3
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %20, float %21, float %22, float %23)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %13, float %14, float %15, float %16)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg6

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR6_SGPR7 %VGPR0
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%20](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%VGPR1_VGPR2_VGPR3_VGPR4<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	EXP 15, 32, 0, 0, 0, %VGPR1, %VGPR2, %VGPR3, %VGPR4, %EXEC<imp-use>, %VGPR1_VGPR2_VGPR3_VGPR4<imp-use,kill>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%11](align=8)(tbaa=!"const")
	S_WAITCNT 15
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR1, %VGPR2, %VGPR3, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_LOAD_DWORDX4 s[0:3], s[6:7], 4               ; C0800704
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	BUFFER_LOAD_FORMAT_XYZW v[1:4], s[0:3][v0] + 0 ; E00C2000 80000100
	S_WAITCNT vmcnt(0)                             ; BF8C0770
	EXP 15, 32, 0, 0, 0, v1, v2, v3, v4            ; F800020F 04030201
	S_LOAD_DWORDX4 s[0:3], s[6:7], 0               ; C0800700
	S_WAITCNT expcnt(0) lgkmcnt(0)                 ; BF8C000F
	BUFFER_LOAD_FORMAT_XYZW v[0:3], s[0:3][v0] + 0 ; E00C2000 80000000
	S_WAITCNT vmcnt(0)                             ; BF8C0770
	EXP 15, 12, 0, 1, 0, v0, v1, v2, v3            ; F80008CF 03020100
	S_ENDPGM                                       ; BF810000

VERT
DCL IN[0]
DCL OUT[0], POSITION
  0: MOV OUT[0], IN[0]
  1: END
STREAMOUT
  0: BUF0[0..0] <- OUT[0].x
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %13 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 0
  %14 = load <16 x i8> addrspace(2)* %13, !tbaa !0
  %15 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0
  %16 = load <16 x i8> addrspace(2)* %15, !tbaa !0
  %17 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %16, i32 0, i32 %9)
  %18 = extractelement <4 x float> %17, i32 0
  %19 = extractelement <4 x float> %17, i32 1
  %20 = extractelement <4 x float> %17, i32 2
  %21 = extractelement <4 x float> %17, i32 3
  %22 = lshr i32 %6, 16
  %23 = and i32 %22, 127
  %24 = call i32 @llvm.SI.tid()
  %25 = icmp ult i32 %24, %23
  br i1 %25, label %if-true-block, label %endif-block

if-true-block:                                    ; preds = %main_body
  %26 = add i32 %7, %24
  %27 = mul i32 %8, 4
  %28 = mul i32 %26, 4
  %29 = add i32 %28, %27
  %30 = bitcast float %18 to i32
  call void @llvm.SI.tbuffer.store.i32(<16 x i8> %14, i32 %30, i32 1, i32 %29, i32 0, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0)
  br label %endif-block

endif-block:                                      ; preds = %main_body, %if-true-block
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %18, float %19, float %20, float %21)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare i32 @llvm.SI.tid() #2

declare void @llvm.SI.tbuffer.store.i32(<16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32)

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR6_SGPR7 in %vreg7, %SGPR8_SGPR9 in %vreg8, %SGPR11 in %vreg10, %SGPR12 in %vreg11, %SGPR13 in %vreg12, %VGPR0 in %vreg13

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR6_SGPR7 %SGPR8_SGPR9 %SGPR11 %SGPR12 %SGPR13 %VGPR0
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%14](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LSHR_B32 %SGPR11<kill>, 16
	%VGPR4<def> = V_MOV_B32_e32 127, %EXEC<imp-use>
	%VGPR5<def> = V_AND_B32_e32 %SGPR0<kill>, %VGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MBCNT_LO_U32_B32_e64 -1, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MBCNT_HI_U32_B32_e32 -1, %VGPR4<kill>, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = V_CMP_LT_U32_e64 %VGPR4, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%SGPR0_SGPR1<def> = S_AND_SAVEEXEC_B64 %SGPR0_SGPR1, %EXEC<imp-def>, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_XOR_B64 %EXEC, %SGPR0_SGPR1
    Successors according to CFG: BB#1(16) BB#2(16)

BB#1: derived from LLVM BB %if-true-block
    Live Ins: %VGPR0_VGPR1_VGPR2_VGPR3 %SGPR8_SGPR9 %SGPR12 %SGPR13 %SGPR0_SGPR1 %VGPR4
    Predecessors according to CFG: BB#0
	%VGPR4<def> = V_ADD_I32_e32 %SGPR12<kill>, %VGPR4<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR4<def> = V_LSHLREV_B32_e32 2, %VGPR4<kill>, %EXEC<imp-use>
	%SGPR2<def> = S_LSHL_B32 %SGPR13<kill>, 2
	%VGPR4<def> = V_ADD_I32_e32 %SGPR2<kill>, %VGPR4<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR8_SGPR9<kill>, 0; mem:LD16[%27](align=8)(tbaa=!"const")
	S_WAITCNT 127
	TBUFFER_STORE_FORMAT_X %VGPR0, 0, -1, 0, -1, 0, 4, 4, %VGPR4<kill>, %SGPR4_SGPR5_SGPR6_SGPR7<kill>, -1, 0, 0, %EXEC<imp-use>
	S_WAITCNT 1792
    Successors according to CFG: BB#2

BB#2: derived from LLVM BB %endif-block
    Live Ins: %VGPR0_VGPR1_VGPR2_VGPR3 %SGPR0_SGPR1
    Predecessors according to CFG: BB#0 BB#1
	%EXEC<def> = S_OR_B64 %EXEC, %SGPR0_SGPR1
	EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR1, %VGPR2, %VGPR3, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_LOAD_DWORDX4 s[0:3], s[6:7], 0                                       ; C0800700
	S_WAITCNT lgkmcnt(0)                                                   ; BF8C007F
	BUFFER_LOAD_FORMAT_XYZW v[0:3], s[0:3][v0] + 0                         ; E00C2000 80000000
	S_LSHR_B32 s0, s11, 16                                                 ; 9000900B
	V_MOV_B32_e32 v4, 127                                                  ; 7E0802FF 0000007F
	V_AND_B32_e32 v5, s0, v4                                               ; 360A0800
	V_MBCNT_LO_U32_B32_e64 v4, -1, 0, 0, 0, 0, 0                           ; D2460004 020100C1
	V_MBCNT_HI_U32_B32_e32 v4, -1, v4                                      ; 480808C1
	V_CMP_LT_U32_e64 s[0:1], v4, v5, 0, 0, 0, 0                            ; D1820000 02020B04
	S_WAITCNT vmcnt(0)                                                     ; BF8C0770
	S_AND_SAVEEXEC_B64 s[0:1], s[0:1]                                      ; BE802400
	S_XOR_B64 s[0:1], exec, s[0:1]                                         ; 8980007E
	V_ADD_I32_e32 v4, s12, v4                                              ; 4A08080C
	V_LSHLREV_B32_e32 v4, 2, v4                                            ; 34080882
	S_LSHL_B32 s2, s13, 2                                                  ; 8F02820D
	V_ADD_I32_e32 v4, s2, v4                                               ; 4A080802
	S_LOAD_DWORDX4 s[4:7], s[8:9], 0                                       ; C0820900
	S_WAITCNT lgkmcnt(0)                                                   ; BF8C007F
	TBUFFER_STORE_FORMAT_X v0, 0, -1, 0, -1, 0, 4, 4, v4, s[4:7], -1, 0, 0 ; EA245000 80410004
	S_WAITCNT vmcnt(0) expcnt(0)                                           ; BF8C0700
	S_OR_B64 exec, exec, s[0:1]                                            ; 88FE007E
	EXP 15, 12, 0, 1, 0, v0, v1, v2, v3                                    ; F80008CF 03020100
	S_ENDPGM                                                               ; BF810000

FRAG
DCL IN[0], GENERIC[0], CONSTANT
  0: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
# Machine code for function main: Post SSA, not tracking liveness

BB#0: derived from LLVM BB %main_body
	%VGPR0<def> = V_MOV_B32_e32 0, %EXEC<imp-use>
	EXP 0, 0, 0, 1, 1, %VGPR0<kill>, %VGPR0, %VGPR0, %VGPR0, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	V_MOV_B32_e32 v0, 0               ; 7E000280
	EXP 0, 0, 0, 1, 1, v0, v0, v0, v0 ; F8001800 00000000
	S_ENDPGM                          ; BF810000

FRAG
  0: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
# Machine code for function main: Post SSA, not tracking liveness

BB#0: derived from LLVM BB %main_body
	%VGPR0<def> = V_MOV_B32_e32 0, %EXEC<imp-use>
	EXP 0, 0, 0, 1, 1, %VGPR0<kill>, %VGPR0, %VGPR0, %VGPR0, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	V_MOV_B32_e32 v0, 0               ; 7E000280
	EXP 0, 0, 0, 1, 1, v0, v0, v0, v0 ; F8001800 00000000
	S_ENDPGM                          ; BF810000

FRAG
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %21 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %4)
  %22 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %4)
  %23 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %4)
  %24 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %4)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %21, float %22, float %23, float %24)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR7 in %vreg4

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR7
	%EXEC<def> = S_WQM_B64 %EXEC
	%M0<def> = S_MOV_B32 %SGPR7
	%VGPR0<def> = V_INTERP_MOV_F32 2, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_INTERP_MOV_F32 2, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_INTERP_MOV_F32 2, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_INTERP_MOV_F32 2, 0, 0, %M0<kill>, %EXEC<imp-use>
	EXP 15, 0, 0, 1, 1, %VGPR3<kill>, %VGPR2<kill>, %VGPR1<kill>, %VGPR0<kill>, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_WQM_B64 exec, exec                ; BEFE0A7E
	S_MOV_B32 m0, s7                    ; BEFC0307
	V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302
	V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202
	V_INTERP_MOV_F32 v2, P0, 1, 0, [m0] ; C80A0102
	V_INTERP_MOV_F32 v3, P0, 0, 0, [m0] ; C80E0002
	EXP 15, 0, 0, 1, 1, v3, v2, v1, v0  ; F800180F 00010203
	S_ENDPGM                            ; BF810000

FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %21 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %4)
  %22 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %4)
  %23 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %4)
  %24 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %4)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %21, float %22, float %23, float %24)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR7 in %vreg4

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR7
	%EXEC<def> = S_WQM_B64 %EXEC
	%M0<def> = S_MOV_B32 %SGPR7
	%VGPR0<def> = V_INTERP_MOV_F32 2, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_INTERP_MOV_F32 2, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_INTERP_MOV_F32 2, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_INTERP_MOV_F32 2, 0, 0, %M0<kill>, %EXEC<imp-use>
	EXP 15, 0, 0, 1, 1, %VGPR3<kill>, %VGPR2<kill>, %VGPR1<kill>, %VGPR0<kill>, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_WQM_B64 exec, exec                ; BEFE0A7E
	S_MOV_B32 m0, s7                    ; BEFC0307
	V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302
	V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202
	V_INTERP_MOV_F32 v2, P0, 1, 0, [m0] ; C80A0102
	V_INTERP_MOV_F32 v3, P0, 0, 0, [m0] ; C80E0002
	EXP 15, 0, 0, 1, 1, v3, v2, v1, v0  ; F800180F 00010203
	S_ENDPGM                            ; BF810000

VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[0]
  0: MOV OUT[0], IN[0]
  1: MOV OUT[1], IN[1]
  2: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %11, i32 0, i32 %6)
  %13 = extractelement <4 x float> %12, i32 0
  %14 = extractelement <4 x float> %12, i32 1
  %15 = extractelement <4 x float> %12, i32 2
  %16 = extractelement <4 x float> %12, i32 3
  %17 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 1
  %18 = load <16 x i8> addrspace(2)* %17, !tbaa !0
  %19 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %18, i32 0, i32 %6)
  %20 = extractelement <4 x float> %19, i32 0
  %21 = extractelement <4 x float> %19, i32 1
  %22 = extractelement <4 x float> %19, i32 2
  %23 = extractelement <4 x float> %19, i32 3
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %20, float %21, float %22, float %23)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %13, float %14, float %15, float %16)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg6

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR6_SGPR7 %VGPR0
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%20](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%VGPR1_VGPR2_VGPR3_VGPR4<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	EXP 15, 32, 0, 0, 0, %VGPR1, %VGPR2, %VGPR3, %VGPR4, %EXEC<imp-use>, %VGPR1_VGPR2_VGPR3_VGPR4<imp-use,kill>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%11](align=8)(tbaa=!"const")
	S_WAITCNT 15
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR1, %VGPR2, %VGPR3, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_LOAD_DWORDX4 s[0:3], s[6:7], 4               ; C0800704
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	BUFFER_LOAD_FORMAT_XYZW v[1:4], s[0:3][v0] + 0 ; E00C2000 80000100
	S_WAITCNT vmcnt(0)                             ; BF8C0770
	EXP 15, 32, 0, 0, 0, v1, v2, v3, v4            ; F800020F 04030201
	S_LOAD_DWORDX4 s[0:3], s[6:7], 0               ; C0800700
	S_WAITCNT expcnt(0) lgkmcnt(0)                 ; BF8C000F
	BUFFER_LOAD_FORMAT_XYZW v[0:3], s[0:3][v0] + 0 ; E00C2000 80000000
	S_WAITCNT vmcnt(0)                             ; BF8C0770
	EXP 15, 12, 0, 1, 0, v0, v1, v2, v3            ; F80008CF 03020100
	S_ENDPGM                                       ; BF810000

VERT
DCL IN[0]
DCL OUT[0], POSITION
  0: MOV OUT[0], IN[0]
  1: END
STREAMOUT
  0: BUF0[0..0] <- OUT[0].x
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %13 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 0
  %14 = load <16 x i8> addrspace(2)* %13, !tbaa !0
  %15 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0
  %16 = load <16 x i8> addrspace(2)* %15, !tbaa !0
  %17 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %16, i32 0, i32 %9)
  %18 = extractelement <4 x float> %17, i32 0
  %19 = extractelement <4 x float> %17, i32 1
  %20 = extractelement <4 x float> %17, i32 2
  %21 = extractelement <4 x float> %17, i32 3
  %22 = lshr i32 %6, 16
  %23 = and i32 %22, 127
  %24 = call i32 @llvm.SI.tid()
  %25 = icmp ult i32 %24, %23
  br i1 %25, label %if-true-block, label %endif-block

if-true-block:                                    ; preds = %main_body
  %26 = add i32 %7, %24
  %27 = mul i32 %8, 4
  %28 = mul i32 %26, 4
  %29 = add i32 %28, %27
  %30 = bitcast float %18 to i32
  call void @llvm.SI.tbuffer.store.i32(<16 x i8> %14, i32 %30, i32 1, i32 %29, i32 0, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0)
  br label %endif-block

endif-block:                                      ; preds = %main_body, %if-true-block
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %18, float %19, float %20, float %21)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare i32 @llvm.SI.tid() #2

declare void @llvm.SI.tbuffer.store.i32(<16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32)

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR6_SGPR7 in %vreg7, %SGPR8_SGPR9 in %vreg8, %SGPR11 in %vreg10, %SGPR12 in %vreg11, %SGPR13 in %vreg12, %VGPR0 in %vreg13

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR6_SGPR7 %SGPR8_SGPR9 %SGPR11 %SGPR12 %SGPR13 %VGPR0
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%14](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LSHR_B32 %SGPR11<kill>, 16
	%VGPR4<def> = V_MOV_B32_e32 127, %EXEC<imp-use>
	%VGPR5<def> = V_AND_B32_e32 %SGPR0<kill>, %VGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MBCNT_LO_U32_B32_e64 -1, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MBCNT_HI_U32_B32_e32 -1, %VGPR4<kill>, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = V_CMP_LT_U32_e64 %VGPR4, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%SGPR0_SGPR1<def> = S_AND_SAVEEXEC_B64 %SGPR0_SGPR1, %EXEC<imp-def>, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_XOR_B64 %EXEC, %SGPR0_SGPR1
    Successors according to CFG: BB#1(16) BB#2(16)

BB#1: derived from LLVM BB %if-true-block
    Live Ins: %VGPR0_VGPR1_VGPR2_VGPR3 %SGPR8_SGPR9 %SGPR12 %SGPR13 %SGPR0_SGPR1 %VGPR4
    Predecessors according to CFG: BB#0
	%VGPR4<def> = V_ADD_I32_e32 %SGPR12<kill>, %VGPR4<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR4<def> = V_LSHLREV_B32_e32 2, %VGPR4<kill>, %EXEC<imp-use>
	%SGPR2<def> = S_LSHL_B32 %SGPR13<kill>, 2
	%VGPR4<def> = V_ADD_I32_e32 %SGPR2<kill>, %VGPR4<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR8_SGPR9<kill>, 0; mem:LD16[%27](align=8)(tbaa=!"const")
	S_WAITCNT 127
	TBUFFER_STORE_FORMAT_X %VGPR0, 0, -1, 0, -1, 0, 4, 4, %VGPR4<kill>, %SGPR4_SGPR5_SGPR6_SGPR7<kill>, -1, 0, 0, %EXEC<imp-use>
	S_WAITCNT 1792
    Successors according to CFG: BB#2

BB#2: derived from LLVM BB %endif-block
    Live Ins: %VGPR0_VGPR1_VGPR2_VGPR3 %SGPR0_SGPR1
    Predecessors according to CFG: BB#0 BB#1
	%EXEC<def> = S_OR_B64 %EXEC, %SGPR0_SGPR1
	EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR1, %VGPR2, %VGPR3, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_LOAD_DWORDX4 s[0:3], s[6:7], 0                                       ; C0800700
	S_WAITCNT lgkmcnt(0)                                                   ; BF8C007F
	BUFFER_LOAD_FORMAT_XYZW v[0:3], s[0:3][v0] + 0                         ; E00C2000 80000000
	S_LSHR_B32 s0, s11, 16                                                 ; 9000900B
	V_MOV_B32_e32 v4, 127                                                  ; 7E0802FF 0000007F
	V_AND_B32_e32 v5, s0, v4                                               ; 360A0800
	V_MBCNT_LO_U32_B32_e64 v4, -1, 0, 0, 0, 0, 0                           ; D2460004 020100C1
	V_MBCNT_HI_U32_B32_e32 v4, -1, v4                                      ; 480808C1
	V_CMP_LT_U32_e64 s[0:1], v4, v5, 0, 0, 0, 0                            ; D1820000 02020B04
	S_WAITCNT vmcnt(0)                                                     ; BF8C0770
	S_AND_SAVEEXEC_B64 s[0:1], s[0:1]                                      ; BE802400
	S_XOR_B64 s[0:1], exec, s[0:1]                                         ; 8980007E
	V_ADD_I32_e32 v4, s12, v4                                              ; 4A08080C
	V_LSHLREV_B32_e32 v4, 2, v4                                            ; 34080882
	S_LSHL_B32 s2, s13, 2                                                  ; 8F02820D
	V_ADD_I32_e32 v4, s2, v4                                               ; 4A080802
	S_LOAD_DWORDX4 s[4:7], s[8:9], 0                                       ; C0820900
	S_WAITCNT lgkmcnt(0)                                                   ; BF8C007F
	TBUFFER_STORE_FORMAT_X v0, 0, -1, 0, -1, 0, 4, 4, v4, s[4:7], -1, 0, 0 ; EA245000 80410004
	S_WAITCNT vmcnt(0) expcnt(0)                                           ; BF8C0700
	S_OR_B64 exec, exec, s[0:1]                                            ; 88FE007E
	EXP 15, 12, 0, 1, 0, v0, v1, v2, v3                                    ; F80008CF 03020100
	S_ENDPGM                                                               ; BF810000

FRAG
DCL IN[0], GENERIC[0], CONSTANT
  0: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
# Machine code for function main: Post SSA, not tracking liveness

BB#0: derived from LLVM BB %main_body
	%VGPR0<def> = V_MOV_B32_e32 0, %EXEC<imp-use>
	EXP 0, 0, 0, 1, 1, %VGPR0<kill>, %VGPR0, %VGPR0, %VGPR0, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	V_MOV_B32_e32 v0, 0               ; 7E000280
	EXP 0, 0, 0, 1, 1, v0, v0, v0, v0 ; F8001800 00000000
	S_ENDPGM                          ; BF810000

WRN:  [OpenGL] "GL_ARB_get_program_binary" extension is present but not used because no binary formats are exposed.
WRN:  [OpenGL] Unable to determine VRAM size... assuming 512 MB.
FRAG
DCL IN[0], GENERIC[0], LINEAR
DCL OUT[0], COLOR
DCL SAMP[0]
  0: TEX OUT[0], IN[0], SAMP[0], 2D
  1: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %21 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0
  %22 = load <32 x i8> addrspace(2)* %21, !tbaa !0
  %23 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0
  %24 = load <16 x i8> addrspace(2)* %23, !tbaa !0
  %25 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %4, <2 x i32> %10)
  %26 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %4, <2 x i32> %10)
  %27 = bitcast float %25 to i32
  %28 = bitcast float %26 to i32
  %29 = insertelement <2 x i32> undef, i32 %27, i32 0
  %30 = insertelement <2 x i32> %29, i32 %28, i32 1
  %31 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %30, <32 x i8> %22, <16 x i8> %24, i32 2)
  %32 = extractelement <4 x float> %31, i32 0
  %33 = extractelement <4 x float> %31, i32 1
  %34 = extractelement <4 x float> %31, i32 2
  %35 = extractelement <4 x float> %31, i32 3
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %32, float %33, float %34, float %35)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR7 in %vreg4, %VGPR0 in %vreg5, %VGPR1 in %vreg6

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR7 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR7
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-def>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%24](align=8)(tbaa=!"const")
	%SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%21](tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = IMAGE_SAMPLE_V4_V2 15, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3<kill>, %SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<kill>, %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	EXP 15, 0, 0, 1, 1, %VGPR0, %VGPR1, %VGPR2, %VGPR3, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_WQM_B64 exec, exec                                                  ; BEFE0A7E
	S_MOV_B32 m0, s7                                                      ; BEFC0307
	V_INTERP_P1_F32 v3, v0, 1, 0, [m0]                                    ; C80C0100
	V_INTERP_P2_F32 v3, [v3], v1, 1, 0, [m0]                              ; C80D0101
	V_INTERP_P1_F32 v2, v0, 0, 0, [m0]                                    ; C8080000
	V_INTERP_P2_F32 v2, [v2], v1, 0, 0, [m0]                              ; C8090001
	S_LOAD_DWORDX4 s[0:3], s[2:3], 0                                      ; C0800300
	S_LOAD_DWORDX8 s[4:11], s[4:5], 0                                     ; C0C20500
	S_WAITCNT lgkmcnt(0)                                                  ; BF8C007F
	IMAGE_SAMPLE v[0:3], 15, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[4:11], s[0:3] ; F0800F00 00010002
	S_WAITCNT vmcnt(0)                                                    ; BF8C0770
	EXP 15, 0, 0, 1, 1, v0, v1, v2, v3                                    ; F800180F 03020100
	S_ENDPGM                                                              ; BF810000

FRAG
DCL IN[0], GENERIC[0], LINEAR
DCL OUT[0], COLOR
DCL SAMP[0]
  0: TEX OUT[0], IN[0], SAMP[0], 2D
  1: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %21 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0
  %22 = load <32 x i8> addrspace(2)* %21, !tbaa !0
  %23 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0
  %24 = load <16 x i8> addrspace(2)* %23, !tbaa !0
  %25 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %4, <2 x i32> %10)
  %26 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %4, <2 x i32> %10)
  %27 = bitcast float %25 to i32
  %28 = bitcast float %26 to i32
  %29 = insertelement <2 x i32> undef, i32 %27, i32 0
  %30 = insertelement <2 x i32> %29, i32 %28, i32 1
  %31 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %30, <32 x i8> %22, <16 x i8> %24, i32 2)
  %32 = extractelement <4 x float> %31, i32 0
  %33 = extractelement <4 x float> %31, i32 1
  %34 = extractelement <4 x float> %31, i32 2
  %35 = extractelement <4 x float> %31, i32 3
  %36 = call i32 @llvm.SI.packf16(float %32, float %33)
  %37 = bitcast i32 %36 to float
  %38 = call i32 @llvm.SI.packf16(float %34, float %35)
  %39 = bitcast i32 %38 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %37, float %39, float %37, float %39)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR7 in %vreg4, %VGPR0 in %vreg5, %VGPR1 in %vreg6

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR7 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR7
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-def>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%24](align=8)(tbaa=!"const")
	%SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%21](tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = IMAGE_SAMPLE_V4_V2 15, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3<kill>, %SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<kill>, %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR4<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR2, %VGPR3, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0, %VGPR1, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	EXP 15, 0, 1, 1, 1, %VGPR0<kill>, %VGPR4<kill>, %VGPR0, %VGPR4, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_WQM_B64 exec, exec                                                  ; BEFE0A7E
	S_MOV_B32 m0, s7                                                      ; BEFC0307
	V_INTERP_P1_F32 v3, v0, 1, 0, [m0]                                    ; C80C0100
	V_INTERP_P2_F32 v3, [v3], v1, 1, 0, [m0]                              ; C80D0101
	V_INTERP_P1_F32 v2, v0, 0, 0, [m0]                                    ; C8080000
	V_INTERP_P2_F32 v2, [v2], v1, 0, 0, [m0]                              ; C8090001
	S_LOAD_DWORDX4 s[0:3], s[2:3], 0                                      ; C0800300
	S_LOAD_DWORDX8 s[4:11], s[4:5], 0                                     ; C0C20500
	S_WAITCNT lgkmcnt(0)                                                  ; BF8C007F
	IMAGE_SAMPLE v[0:3], 15, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[4:11], s[0:3] ; F0800F00 00010002
	S_WAITCNT vmcnt(0)                                                    ; BF8C0770
	V_CVT_PKRTZ_F16_F32_e32 v4, v2, v3                                    ; 5E080702
	V_CVT_PKRTZ_F16_F32_e32 v0, v0, v1                                    ; 5E000300
	EXP 15, 0, 1, 1, 1, v0, v4, v0, v4                                    ; F8001C0F 04000400
	S_ENDPGM                                                              ; BF810000

FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL IN[1], GENERIC[20], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL CONST[0]
DCL TEMP[0..2], LOCAL
IMM[0] FLT32 {   32.0000,   -16.0000,     1.0000,     0.0000}
  0: MOV TEMP[0].xy, IN[1].xyyy
  1: TEX TEMP[0], TEMP[0], SAMP[0], 2D
  2: MAD TEMP[1].x, TEMP[0].wwww, IMM[0].xxxx, IMM[0].yyyy
  3: EX2 TEMP[1].x, TEMP[1].xxxx
  4: MUL TEMP[1].xyz, TEMP[0].xyzz, TEMP[1].xxxx
  5: MOV TEMP[1].w, IMM[0].zzzz
  6: FSGE TEMP[2].x, CONST[0].xxxx, IMM[0].wwww
  7: UIF TEMP[2].xxxx :0
  8:   MOV TEMP[1], TEMP[1]
  9: ELSE :0
 10:   MOV TEMP[1], TEMP[0]
 11: ENDIF
 12: MUL TEMP[0], TEMP[1], IN[0]
 13: MOV OUT[0], TEMP[0]
 14: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %21 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
  %22 = load <16 x i8> addrspace(2)* %21, !tbaa !0
  %23 = call float @llvm.SI.load.const(<16 x i8> %22, i32 0)
  %24 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0
  %25 = load <32 x i8> addrspace(2)* %24, !tbaa !0
  %26 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0
  %27 = load <16 x i8> addrspace(2)* %26, !tbaa !0
  %28 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %4, <2 x i32> %6)
  %29 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %4, <2 x i32> %6)
  %30 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %4, <2 x i32> %6)
  %31 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %4, <2 x i32> %6)
  %32 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %4, <2 x i32> %6)
  %33 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %4, <2 x i32> %6)
  %34 = bitcast float %32 to i32
  %35 = bitcast float %33 to i32
  %36 = insertelement <2 x i32> undef, i32 %34, i32 0
  %37 = insertelement <2 x i32> %36, i32 %35, i32 1
  %38 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %37, <32 x i8> %25, <16 x i8> %27, i32 2)
  %39 = extractelement <4 x float> %38, i32 0
  %40 = extractelement <4 x float> %38, i32 1
  %41 = extractelement <4 x float> %38, i32 2
  %42 = extractelement <4 x float> %38, i32 3
  %43 = fmul float %42, 3.200000e+01
  %44 = fadd float %43, -1.600000e+01
  %45 = call float @llvm.AMDIL.exp.(float %44)
  %46 = fmul float %39, %45
  %47 = fmul float %40, %45
  %48 = fmul float %41, %45
  %49 = fcmp oge float %23, 0.000000e+00
  %50 = sext i1 %49 to i32
  %51 = bitcast i32 %50 to float
  %52 = bitcast float %51 to i32
  %53 = icmp ne i32 %52, 0
  %. = select i1 %53, float %46, float %39
  %.12 = select i1 %53, float %47, float %40
  %.13 = select i1 %53, float %48, float %41
  %.14 = select i1 %53, float 1.000000e+00, float %42
  %54 = fmul float %., %28
  %55 = fmul float %.12, %29
  %56 = fmul float %.13, %30
  %57 = fmul float %.14, %31
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %54, float %55, float %56, float %57)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.exp.(float) #2

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR7 in %vreg4, %VGPR0 in %vreg5, %VGPR1 in %vreg6

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR7 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR7
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 1, 1, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-def>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 1, 1, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 1, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<tied0>, %VGPR1, 0, 1, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%29](align=8)(tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%26](tbaa=!"const")
	S_WAITCNT 127
	%VGPR2_VGPR3_VGPR4_VGPR5<def> = IMAGE_SAMPLE_V4_V2 15, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MOV_B32_e32 -1.600000e+01, %EXEC<imp-use>
	%VGPR7<def> = V_MOV_B32_e32 3.200000e+01, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR6<def> = V_MAD_F32 %VGPR5, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_EXP_F32_e32 %VGPR6<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MUL_F32_e32 %VGPR4, %VGPR6, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%22](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 0; mem:LD4[<unknown>]
	S_WAITCNT 127
	%SGPR0_SGPR1<def> = V_CMP_GE_F32_e64 %SGPR0<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_CNDMASK_B32_e64 %VGPR4, %VGPR7<kill>, %SGPR0_SGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_INTERP_P1_F32 %VGPR0, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR8<def,tied1> = V_INTERP_P2_F32 %VGPR8<kill,tied0>, %VGPR1, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MUL_F32_e32 %VGPR7<kill>, %VGPR8<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_F32_e32 %VGPR3, %VGPR6, %EXEC<imp-use>
	%VGPR8<def> = V_CNDMASK_B32_e64 %VGPR3, %VGPR8<kill>, %SGPR0_SGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR9<def,tied1> = V_INTERP_P2_F32 %VGPR9<kill,tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_F32_e32 %VGPR8<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %VGPR2, %VGPR6<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_CNDMASK_B32_e64 %VGPR2, %VGPR6<kill>, %SGPR0_SGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR9<def,tied1> = V_INTERP_P2_F32 %VGPR9<kill,tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %VGPR6<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_CNDMASK_B32_e64 %VGPR5, 1.000000e+00, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<kill,tied0>, %VGPR1, 3, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR2<kill>, %VGPR3<kill>, %EXEC<imp-use>
	EXP 15, 0, 0, 1, 1, %VGPR6<kill>, %VGPR8<kill>, %VGPR7<kill>, %VGPR0<kill>, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_WQM_B64 exec, exec                                                    ; BEFE0A7E
	S_MOV_B32 m0, s7                                                        ; BEFC0307
	V_INTERP_P1_F32 v3, v0, 1, 1, [m0]                                      ; C80C0500
	V_INTERP_P2_F32 v3, [v3], v1, 1, 1, [m0]                                ; C80D0501
	V_INTERP_P1_F32 v2, v0, 0, 1, [m0]                                      ; C8080400
	V_INTERP_P2_F32 v2, [v2], v1, 0, 1, [m0]                                ; C8090401
	S_LOAD_DWORDX4 s[8:11], s[2:3], 0                                       ; C0840300
	S_LOAD_DWORDX8 s[12:19], s[4:5], 0                                      ; C0C60500
	S_WAITCNT lgkmcnt(0)                                                    ; BF8C007F
	IMAGE_SAMPLE v[2:5], 15, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[12:19], s[8:11] ; F0800F00 00430202
	V_MOV_B32_e32 v6, -1.600000e+01                                         ; 7E0C02FF C1800000
	V_MOV_B32_e32 v7, 3.200000e+01                                          ; 7E0E02FF 42000000
	S_WAITCNT vmcnt(0)                                                      ; BF8C0770
	V_MAD_F32 v6, v5, v7, v6, 0, 0, 0, 0                                    ; D2820006 041A0F05
	V_EXP_F32_e32 v6, v6                                                    ; 7E0C4B06
	V_MUL_F32_e32 v7, v4, v6                                                ; 100E0D04
	S_LOAD_DWORDX4 s[0:3], s[0:1], 0                                        ; C0800100
	S_WAITCNT lgkmcnt(0)                                                    ; BF8C007F
	S_BUFFER_LOAD_DWORD s0, s[0:3], 0                                       ; C2000100
	S_WAITCNT lgkmcnt(0)                                                    ; BF8C007F
	V_CMP_GE_F32_e64 s[0:1], s0, 0.000000e+00, 0, 0, 0, 0                   ; D00C0000 02010000
	V_CNDMASK_B32_e64 v7, v4, v7, s[0:1], 0, 0, 0, 0                        ; D2000007 00020F04
	V_INTERP_P1_F32 v8, v0, 2, 0, [m0]                                      ; C8200200
	V_INTERP_P2_F32 v8, [v8], v1, 2, 0, [m0]                                ; C8210201
	V_MUL_F32_e32 v7, v7, v8                                                ; 100E1107
	V_MUL_F32_e32 v8, v3, v6                                                ; 10100D03
	V_CNDMASK_B32_e64 v8, v3, v8, s[0:1], 0, 0, 0, 0                        ; D2000008 00021103
	V_INTERP_P1_F32 v9, v0, 1, 0, [m0]                                      ; C8240100
	V_INTERP_P2_F32 v9, [v9], v1, 1, 0, [m0]                                ; C8250101
	V_MUL_F32_e32 v8, v8, v9                                                ; 10101308
	V_MUL_F32_e32 v6, v2, v6                                                ; 100C0D02
	V_CNDMASK_B32_e64 v6, v2, v6, s[0:1], 0, 0, 0, 0                        ; D2000006 00020D02
	V_INTERP_P1_F32 v9, v0, 0, 0, [m0]                                      ; C8240000
	V_INTERP_P2_F32 v9, [v9], v1, 0, 0, [m0]                                ; C8250001
	V_MUL_F32_e32 v6, v6, v9                                                ; 100C1306
	V_CNDMASK_B32_e64 v2, v5, 1.000000e+00, s[0:1], 0, 0, 0, 0              ; D2000002 0001E505
	V_INTERP_P1_F32 v3, v0, 3, 0, [m0]                                      ; C80C0300
	V_INTERP_P2_F32 v3, [v3], v1, 3, 0, [m0]                                ; C80D0301
	V_MUL_F32_e32 v0, v2, v3                                                ; 10000702
	EXP 15, 0, 0, 1, 1, v6, v8, v7, v0                                      ; F800180F 00070806
	S_ENDPGM                                                                ; BF810000

VERT
DCL IN[0]
DCL IN[1]
DCL IN[2]
DCL OUT[0], POSITION
DCL OUT[1], CLIPVERTEX
DCL OUT[2], GENERIC[19]
DCL OUT[3], GENERIC[20]
DCL CONST[0..5]
DCL TEMP[0..3], LOCAL
IMM[0] FLT32 {    0.0000,     0.0000,     0.0000,     0.0000}
  0: DP4 TEMP[0].x, IN[0], CONST[0]
  1: DP4 TEMP[1].x, IN[0], CONST[1]
  2: MOV TEMP[0].y, TEMP[1].xxxx
  3: DP4 TEMP[1].x, IN[0], CONST[2]
  4: MOV TEMP[0].z, TEMP[1].xxxx
  5: DP4 TEMP[1].x, IN[0], CONST[3]
  6: MOV TEMP[0].w, TEMP[1].xxxx
  7: FSGE TEMP[1].x, CONST[4].zzzz, IMM[0].xxxx
  8: UIF TEMP[1].xxxx :0
  9:   MOV TEMP[1], IN[2].zyxw
 10: ELSE :0
 11:   MOV TEMP[1], CONST[5]
 12: ENDIF
 13: MOV TEMP[2].w, TEMP[1].wwww
 14: POW TEMP[3].x, TEMP[1].xxxx, CONST[4].xxxx
 15: POW TEMP[3].y, TEMP[1].yyyy, CONST[4].xxxx
 16: POW TEMP[3].z, TEMP[1].zzzz, CONST[4].xxxx
 17: MUL TEMP[2].xyz, TEMP[3].xyzz, CONST[4].yyyy
 18: MUL TEMP[0], TEMP[0], CONST[4].wwww
 19: MOV TEMP[1].xy, IN[1].xyxx
 20: MOV OUT[3], TEMP[1]
 21: MOV OUT[2], TEMP[2]
 22: MOV OUT[0], TEMP[0]
 23: MOV OUT[1], TEMP[0]
 24: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0)
  %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4)
  %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8)
  %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12)
  %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16)
  %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20)
  %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24)
  %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28)
  %20 = call float @llvm.SI.load.const(<16 x i8> %11, i32 32)
  %21 = call float @llvm.SI.load.const(<16 x i8> %11, i32 36)
  %22 = call float @llvm.SI.load.const(<16 x i8> %11, i32 40)
  %23 = call float @llvm.SI.load.const(<16 x i8> %11, i32 44)
  %24 = call float @llvm.SI.load.const(<16 x i8> %11, i32 48)
  %25 = call float @llvm.SI.load.const(<16 x i8> %11, i32 52)
  %26 = call float @llvm.SI.load.const(<16 x i8> %11, i32 56)
  %27 = call float @llvm.SI.load.const(<16 x i8> %11, i32 60)
  %28 = call float @llvm.SI.load.const(<16 x i8> %11, i32 64)
  %29 = call float @llvm.SI.load.const(<16 x i8> %11, i32 68)
  %30 = call float @llvm.SI.load.const(<16 x i8> %11, i32 72)
  %31 = call float @llvm.SI.load.const(<16 x i8> %11, i32 76)
  %32 = call float @llvm.SI.load.const(<16 x i8> %11, i32 80)
  %33 = call float @llvm.SI.load.const(<16 x i8> %11, i32 84)
  %34 = call float @llvm.SI.load.const(<16 x i8> %11, i32 88)
  %35 = call float @llvm.SI.load.const(<16 x i8> %11, i32 92)
  %36 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0
  %37 = load <16 x i8> addrspace(2)* %36, !tbaa !0
  %38 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %37, i32 0, i32 %6)
  %39 = extractelement <4 x float> %38, i32 0
  %40 = extractelement <4 x float> %38, i32 1
  %41 = extractelement <4 x float> %38, i32 2
  %42 = extractelement <4 x float> %38, i32 3
  %43 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 1
  %44 = load <16 x i8> addrspace(2)* %43, !tbaa !0
  %45 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %44, i32 0, i32 %6)
  %46 = extractelement <4 x float> %45, i32 0
  %47 = extractelement <4 x float> %45, i32 1
  %48 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 2
  %49 = load <16 x i8> addrspace(2)* %48, !tbaa !0
  %50 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %49, i32 0, i32 %6)
  %51 = extractelement <4 x float> %50, i32 0
  %52 = extractelement <4 x float> %50, i32 1
  %53 = extractelement <4 x float> %50, i32 2
  %54 = extractelement <4 x float> %50, i32 3
  %55 = fmul float %39, %12
  %56 = fmul float %40, %13
  %57 = fadd float %55, %56
  %58 = fmul float %41, %14
  %59 = fadd float %57, %58
  %60 = fmul float %42, %15
  %61 = fadd float %59, %60
  %62 = fmul float %39, %16
  %63 = fmul float %40, %17
  %64 = fadd float %62, %63
  %65 = fmul float %41, %18
  %66 = fadd float %64, %65
  %67 = fmul float %42, %19
  %68 = fadd float %66, %67
  %69 = fmul float %39, %20
  %70 = fmul float %40, %21
  %71 = fadd float %69, %70
  %72 = fmul float %41, %22
  %73 = fadd float %71, %72
  %74 = fmul float %42, %23
  %75 = fadd float %73, %74
  %76 = fmul float %39, %24
  %77 = fmul float %40, %25
  %78 = fadd float %76, %77
  %79 = fmul float %41, %26
  %80 = fadd float %78, %79
  %81 = fmul float %42, %27
  %82 = fadd float %80, %81
  %83 = fcmp oge float %30, 0.000000e+00
  %84 = sext i1 %83 to i32
  %85 = bitcast i32 %84 to float
  %86 = bitcast float %85 to i32
  %87 = icmp ne i32 %86, 0
  %. = select i1 %87, float %53, float %32
  %.16 = select i1 %87, float %52, float %33
  %.17 = select i1 %87, float %51, float %34
  %.18 = select i1 %87, float %54, float %35
  %88 = call float @llvm.pow.f32(float %., float %28)
  %89 = call float @llvm.pow.f32(float %.16, float %28)
  %90 = call float @llvm.pow.f32(float %.17, float %28)
  %91 = fmul float %88, %29
  %92 = fmul float %89, %29
  %93 = fmul float %90, %29
  %94 = fmul float %61, %31
  %95 = fmul float %68, %31
  %96 = fmul float %75, %31
  %97 = fmul float %82, %31
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %91, float %92, float %93, float %.18)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %46, float %47, float %.17, float %.18)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %94, float %95, float %96, float %97)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: nounwind readonly
declare float @llvm.pow.f32(float, float) #2

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { nounwind readonly }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg6

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 8; mem:LD16[%55](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%VGPR1_VGPR2_VGPR3_VGPR4<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%11](align=8)(tbaa=!"const")
	S_WAITCNT 112
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 18; mem:LD4[<unknown>]
	S_WAITCNT 127
	%SGPR4_SGPR5<def> = V_CMP_GE_F32_e64 %SGPR4<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 23; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR8<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_CNDMASK_B32_e64 %VGPR5<kill>, %VGPR4, %SGPR4_SGPR5, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 22; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR8<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_CNDMASK_B32_e64 %VGPR6<kill>, %VGPR1, %SGPR4_SGPR5, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_LOG_F32_e32 %VGPR6, %EXEC<imp-use>
	%SGPR8<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 16; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_LEGACY_F32_e32 %SGPR8, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_EXP_F32_e32 %VGPR7<kill>, %EXEC<imp-use>
	%SGPR9<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 17; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR9, %VGPR7<kill>, %EXEC<imp-use>
	%SGPR10<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 21; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR8<def> = V_MOV_B32_e32 %SGPR10<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_CNDMASK_B32_e64 %VGPR8<kill>, %VGPR2, %SGPR4_SGPR5, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_LOG_F32_e32 %VGPR8<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_LEGACY_F32_e32 %SGPR8, %VGPR8<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_EXP_F32_e32 %VGPR8<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_F32_e32 %SGPR9, %VGPR8<kill>, %EXEC<imp-use>
	%SGPR10<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 20; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR9<def> = V_MOV_B32_e32 %SGPR10<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_CNDMASK_B32_e64 %VGPR9<kill>, %VGPR3, %SGPR4_SGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR1_VGPR2_VGPR3_VGPR4<imp-use,kill>
	%VGPR1<def> = V_LOG_F32_e32 %VGPR1<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_MUL_LEGACY_F32_e32 %SGPR8<kill>, %VGPR1<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_EXP_F32_e32 %VGPR1<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_MUL_F32_e32 %SGPR9<kill>, %VGPR1<kill>, %EXEC<imp-use>
	EXP 15, 32, 0, 0, 0, %VGPR1<kill>, %VGPR8<kill>, %VGPR7<kill>, %VGPR5, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%48](align=8)(tbaa=!"const")
	S_WAITCNT 15
	%VGPR1_VGPR2_VGPR3_VGPR4<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	EXP 15, 33, 0, 0, 0, %VGPR1, %VGPR2, %VGPR6<kill>, %VGPR5<kill>, %EXEC<imp-use>, %VGPR1_VGPR2_VGPR3_VGPR4<imp-use,kill>
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%39](align=8)(tbaa=!"const")
	S_WAITCNT 15
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 13; mem:LD4[<unknown>]
	S_WAITCNT 112
	%VGPR4<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e64 %VGPR1, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 12; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR0, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 14; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR2, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 15; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR3, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 19; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR4<def> = V_MUL_F32_e32 %SGPR4, %VGPR4<kill>, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 9; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MUL_F32_e64 %VGPR1, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 8; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR0, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 10; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR2, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 11; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR3, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_MUL_F32_e32 %SGPR4, %VGPR5<kill>, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 5; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e64 %VGPR1, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 4; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR0, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 6; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR2, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 7; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR3, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %SGPR4, %VGPR6<kill>, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MUL_F32_e64 %VGPR1, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 0; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR8<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR0, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR8<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR2, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 3; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR8<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR3, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	%VGPR0<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR0<kill>, %EXEC<imp-use>
	EXP 15, 12, 0, 1, 0, %VGPR0<kill>, %VGPR6<kill>, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_LOAD_DWORDX4 s[8:11], s[6:7], 8                     ; C0840708
	S_WAITCNT lgkmcnt(0)                                  ; BF8C007F
	BUFFER_LOAD_FORMAT_XYZW v[1:4], s[8:11][v0] + 0       ; E00C2000 80020100
	S_LOAD_DWORDX4 s[0:3], s[0:1], 0                      ; C0800100
	S_WAITCNT vmcnt(0) lgkmcnt(0)                         ; BF8C0070
	S_BUFFER_LOAD_DWORD s4, s[0:3], 18                    ; C2020112
	S_WAITCNT lgkmcnt(0)                                  ; BF8C007F
	V_CMP_GE_F32_e64 s[4:5], s4, 0.000000e+00, 0, 0, 0, 0 ; D00C0004 02010004
	S_BUFFER_LOAD_DWORD s8, s[0:3], 23                    ; C2040117
	S_WAITCNT lgkmcnt(0)                                  ; BF8C007F
	V_MOV_B32_e32 v5, s8                                  ; 7E0A0208
	V_CNDMASK_B32_e64 v5, v5, v4, s[4:5], 0, 0, 0, 0      ; D2000005 00120905
	S_BUFFER_LOAD_DWORD s8, s[0:3], 22                    ; C2040116
	S_WAITCNT lgkmcnt(0)                                  ; BF8C007F
	V_MOV_B32_e32 v6, s8                                  ; 7E0C0208
	V_CNDMASK_B32_e64 v6, v6, v1, s[4:5], 0, 0, 0, 0      ; D2000006 00120306
	V_LOG_F32_e32 v7, v6                                  ; 7E0E4F06
	S_BUFFER_LOAD_DWORD s8, s[0:3], 16                    ; C2040110
	S_WAITCNT lgkmcnt(0)                                  ; BF8C007F
	V_MUL_LEGACY_F32_e32 v7, s8, v7                       ; 0E0E0E08
	V_EXP_F32_e32 v7, v7                                  ; 7E0E4B07
	S_BUFFER_LOAD_DWORD s9, s[0:3], 17                    ; C2048111
	S_WAITCNT lgkmcnt(0)                                  ; BF8C007F
	V_MUL_F32_e32 v7, s9, v7                              ; 100E0E09
	S_BUFFER_LOAD_DWORD s10, s[0:3], 21                   ; C2050115
	S_WAITCNT lgkmcnt(0)                                  ; BF8C007F
	V_MOV_B32_e32 v8, s10                                 ; 7E10020A
	V_CNDMASK_B32_e64 v8, v8, v2, s[4:5], 0, 0, 0, 0      ; D2000008 00120508
	V_LOG_F32_e32 v8, v8                                  ; 7E104F08
	V_MUL_LEGACY_F32_e32 v8, s8, v8                       ; 0E101008
	V_EXP_F32_e32 v8, v8                                  ; 7E104B08
	V_MUL_F32_e32 v8, s9, v8                              ; 10101009
	S_BUFFER_LOAD_DWORD s10, s[0:3], 20                   ; C2050114
	S_WAITCNT lgkmcnt(0)                                  ; BF8C007F
	V_MOV_B32_e32 v9, s10                                 ; 7E12020A
	V_CNDMASK_B32_e64 v1, v9, v3, s[4:5], 0, 0, 0, 0      ; D2000001 00120709
	V_LOG_F32_e32 v1, v1                                  ; 7E024F01
	V_MUL_LEGACY_F32_e32 v1, s8, v1                       ; 0E020208
	V_EXP_F32_e32 v1, v1                                  ; 7E024B01
	V_MUL_F32_e32 v1, s9, v1                              ; 10020209
	EXP 15, 32, 0, 0, 0, v1, v8, v7, v5                   ; F800020F 05070801
	S_LOAD_DWORDX4 s[8:11], s[6:7], 4                     ; C0840704
	S_WAITCNT expcnt(0) lgkmcnt(0)                        ; BF8C000F
	BUFFER_LOAD_FORMAT_XYZW v[1:4], s[8:11][v0] + 0       ; E00C2000 80020100
	S_WAITCNT vmcnt(0)                                    ; BF8C0770
	EXP 15, 33, 0, 0, 0, v1, v2, v6, v5                   ; F800021F 05060201
	S_LOAD_DWORDX4 s[4:7], s[6:7], 0                      ; C0820700
	S_WAITCNT expcnt(0) lgkmcnt(0)                        ; BF8C000F
	BUFFER_LOAD_FORMAT_XYZW v[0:3], s[4:7][v0] + 0        ; E00C2000 80010000
	S_BUFFER_LOAD_DWORD s4, s[0:3], 13                    ; C202010D
	S_WAITCNT vmcnt(0) lgkmcnt(0)                         ; BF8C0070
	V_MOV_B32_e32 v4, s4                                  ; 7E080204
	V_MUL_F32_e64 v4, v1, v4, 0, 0, 0, 0                  ; D2100004 02020901
	S_BUFFER_LOAD_DWORD s4, s[0:3], 12                    ; C202010C
	S_WAITCNT lgkmcnt(0)                                  ; BF8C007F
	V_MOV_B32_e32 v5, s4                                  ; 7E0A0204
	V_MAD_F32 v4, v0, v5, v4, 0, 0, 0, 0                  ; D2820004 04120B00
	S_BUFFER_LOAD_DWORD s4, s[0:3], 14                    ; C202010E
	S_WAITCNT lgkmcnt(0)                                  ; BF8C007F
	V_MOV_B32_e32 v5, s4                                  ; 7E0A0204
	V_MAD_F32 v4, v2, v5, v4, 0, 0, 0, 0                  ; D2820004 04120B02
	S_BUFFER_LOAD_DWORD s4, s[0:3], 15                    ; C202010F
	S_WAITCNT lgkmcnt(0)                                  ; BF8C007F
	V_MOV_B32_e32 v5, s4                                  ; 7E0A0204
	V_MAD_F32 v4, v3, v5, v4, 0, 0, 0, 0                  ; D2820004 04120B03
	S_BUFFER_LOAD_DWORD s4, s[0:3], 19                    ; C2020113
	S_WAITCNT lgkmcnt(0)                                  ; BF8C007F
	V_MUL_F32_e32 v4, s4, v4                              ; 10080804
	S_BUFFER_LOAD_DWORD s5, s[0:3], 9                     ; C2028109
	S_WAITCNT lgkmcnt(0)                                  ; BF8C007F
	V_MOV_B32_e32 v5, s5                                  ; 7E0A0205
	V_MUL_F32_e64 v5, v1, v5, 0, 0, 0, 0                  ; D2100005 02020B01
	S_BUFFER_LOAD_DWORD s5, s[0:3], 8                     ; C2028108
	S_WAITCNT lgkmcnt(0)                                  ; BF8C007F
	V_MOV_B32_e32 v6, s5                                  ; 7E0C0205
	V_MAD_F32 v5, v0, v6, v5, 0, 0, 0, 0                  ; D2820005 04160D00
	S_BUFFER_LOAD_DWORD s5, s[0:3], 10                    ; C202810A
	S_WAITCNT lgkmcnt(0)                                  ; BF8C007F
	V_MOV_B32_e32 v6, s5                                  ; 7E0C0205
	V_MAD_F32 v5, v2, v6, v5, 0, 0, 0, 0                  ; D2820005 04160D02
	S_BUFFER_LOAD_DWORD s5, s[0:3], 11                    ; C202810B
	S_WAITCNT lgkmcnt(0)                                  ; BF8C007F
	V_MOV_B32_e32 v6, s5                                  ; 7E0C0205
	V_MAD_F32 v5, v3, v6, v5, 0, 0, 0, 0                  ; D2820005 04160D03
	V_MUL_F32_e32 v5, s4, v5                              ; 100A0A04
	S_BUFFER_LOAD_DWORD s5, s[0:3], 5                     ; C2028105
	S_WAITCNT lgkmcnt(0)                                  ; BF8C007F
	V_MOV_B32_e32 v6, s5                                  ; 7E0C0205
	V_MUL_F32_e64 v6, v1, v6, 0, 0, 0, 0                  ; D2100006 02020D01
	S_BUFFER_LOAD_DWORD s5, s[0:3], 4                     ; C2028104
	S_WAITCNT lgkmcnt(0)                                  ; BF8C007F
	V_MOV_B32_e32 v7, s5                                  ; 7E0E0205
	V_MAD_F32 v6, v0, v7, v6, 0, 0, 0, 0                  ; D2820006 041A0F00
	S_BUFFER_LOAD_DWORD s5, s[0:3], 6                     ; C2028106
	S_WAITCNT lgkmcnt(0)                                  ; BF8C007F
	V_MOV_B32_e32 v7, s5                                  ; 7E0E0205
	V_MAD_F32 v6, v2, v7, v6, 0, 0, 0, 0                  ; D2820006 041A0F02
	S_BUFFER_LOAD_DWORD s5, s[0:3], 7                     ; C2028107
	S_WAITCNT lgkmcnt(0)                                  ; BF8C007F
	V_MOV_B32_e32 v7, s5                                  ; 7E0E0205
	V_MAD_F32 v6, v3, v7, v6, 0, 0, 0, 0                  ; D2820006 041A0F03
	V_MUL_F32_e32 v6, s4, v6                              ; 100C0C04
	S_BUFFER_LOAD_DWORD s5, s[0:3], 1                     ; C2028101
	S_WAITCNT lgkmcnt(0)                                  ; BF8C007F
	V_MOV_B32_e32 v7, s5                                  ; 7E0E0205
	V_MUL_F32_e64 v7, v1, v7, 0, 0, 0, 0                  ; D2100007 02020F01
	S_BUFFER_LOAD_DWORD s5, s[0:3], 0                     ; C2028100
	S_WAITCNT lgkmcnt(0)                                  ; BF8C007F
	V_MOV_B32_e32 v8, s5                                  ; 7E100205
	V_MAD_F32 v7, v0, v8, v7, 0, 0, 0, 0                  ; D2820007 041E1100
	S_BUFFER_LOAD_DWORD s5, s[0:3], 2                     ; C2028102
	S_WAITCNT lgkmcnt(0)                                  ; BF8C007F
	V_MOV_B32_e32 v8, s5                                  ; 7E100205
	V_MAD_F32 v7, v2, v8, v7, 0, 0, 0, 0                  ; D2820007 041E1102
	S_BUFFER_LOAD_DWORD s0, s[0:3], 3                     ; C2000103
	S_WAITCNT lgkmcnt(0)                                  ; BF8C007F
	V_MOV_B32_e32 v8, s0                                  ; 7E100200
	V_MAD_F32 v0, v3, v8, v7, 0, 0, 0, 0                  ; D2820000 041E1103
	V_MUL_F32_e32 v0, s4, v0                              ; 10000004
	EXP 15, 12, 0, 1, 0, v0, v6, v5, v4                   ; F80008CF 04050600
	S_ENDPGM                                              ; BF810000

FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL IN[1], GENERIC[20], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL CONST[0]
DCL TEMP[0..2], LOCAL
IMM[0] FLT32 {   32.0000,   -16.0000,     1.0000,     0.0000}
  0: MOV TEMP[0].xy, IN[1].xyyy
  1: TEX TEMP[0], TEMP[0], SAMP[0], 2D
  2: MAD TEMP[1].x, TEMP[0].wwww, IMM[0].xxxx, IMM[0].yyyy
  3: EX2 TEMP[1].x, TEMP[1].xxxx
  4: MUL TEMP[1].xyz, TEMP[0].xyzz, TEMP[1].xxxx
  5: MOV TEMP[1].w, IMM[0].zzzz
  6: FSGE TEMP[2].x, CONST[0].xxxx, IMM[0].wwww
  7: UIF TEMP[2].xxxx :0
  8:   MOV TEMP[1], TEMP[1]
  9: ELSE :0
 10:   MOV TEMP[1], TEMP[0]
 11: ENDIF
 12: MUL TEMP[0], TEMP[1], IN[0]
 13: MOV OUT[0], TEMP[0]
 14: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %21 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
  %22 = load <16 x i8> addrspace(2)* %21, !tbaa !0
  %23 = call float @llvm.SI.load.const(<16 x i8> %22, i32 0)
  %24 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0
  %25 = load <32 x i8> addrspace(2)* %24, !tbaa !0
  %26 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0
  %27 = load <16 x i8> addrspace(2)* %26, !tbaa !0
  %28 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %4, <2 x i32> %6)
  %29 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %4, <2 x i32> %6)
  %30 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %4, <2 x i32> %6)
  %31 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %4, <2 x i32> %6)
  %32 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %4, <2 x i32> %6)
  %33 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %4, <2 x i32> %6)
  %34 = bitcast float %32 to i32
  %35 = bitcast float %33 to i32
  %36 = insertelement <2 x i32> undef, i32 %34, i32 0
  %37 = insertelement <2 x i32> %36, i32 %35, i32 1
  %38 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %37, <32 x i8> %25, <16 x i8> %27, i32 2)
  %39 = extractelement <4 x float> %38, i32 0
  %40 = extractelement <4 x float> %38, i32 1
  %41 = extractelement <4 x float> %38, i32 2
  %42 = extractelement <4 x float> %38, i32 3
  %43 = fmul float %42, 3.200000e+01
  %44 = fadd float %43, -1.600000e+01
  %45 = call float @llvm.AMDIL.exp.(float %44)
  %46 = fmul float %39, %45
  %47 = fmul float %40, %45
  %48 = fmul float %41, %45
  %49 = fcmp oge float %23, 0.000000e+00
  %50 = sext i1 %49 to i32
  %51 = bitcast i32 %50 to float
  %52 = bitcast float %51 to i32
  %53 = icmp ne i32 %52, 0
  %. = select i1 %53, float %46, float %39
  %.12 = select i1 %53, float %47, float %40
  %.13 = select i1 %53, float %48, float %41
  %.14 = select i1 %53, float 1.000000e+00, float %42
  %54 = fmul float %., %28
  %55 = fmul float %.12, %29
  %56 = fmul float %.13, %30
  %57 = fmul float %.14, %31
  %58 = call i32 @llvm.SI.packf16(float %54, float %55)
  %59 = bitcast i32 %58 to float
  %60 = call i32 @llvm.SI.packf16(float %56, float %57)
  %61 = bitcast i32 %60 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %59, float %61, float %59, float %61)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.exp.(float) #2

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR7 in %vreg4, %VGPR0 in %vreg5, %VGPR1 in %vreg6

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR7 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR7
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 1, 1, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-def>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 1, 1, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 1, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<tied0>, %VGPR1, 0, 1, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%29](align=8)(tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%26](tbaa=!"const")
	S_WAITCNT 127
	%VGPR2_VGPR3_VGPR4_VGPR5<def> = IMAGE_SAMPLE_V4_V2 15, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MOV_B32_e32 -1.600000e+01, %EXEC<imp-use>
	%VGPR7<def> = V_MOV_B32_e32 3.200000e+01, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR6<def> = V_MAD_F32 %VGPR5, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_EXP_F32_e32 %VGPR6<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MUL_F32_e32 %VGPR3, %VGPR6, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%22](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 0; mem:LD4[<unknown>]
	S_WAITCNT 127
	%SGPR0_SGPR1<def> = V_CMP_GE_F32_e64 %SGPR0<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_CNDMASK_B32_e64 %VGPR3, %VGPR7<kill>, %SGPR0_SGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR8<def,tied1> = V_INTERP_P2_F32 %VGPR8<kill,tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MUL_F32_e32 %VGPR7<kill>, %VGPR8<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_F32_e32 %VGPR2, %VGPR6, %EXEC<imp-use>
	%VGPR8<def> = V_CNDMASK_B32_e64 %VGPR2, %VGPR8<kill>, %SGPR0_SGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR9<def,tied1> = V_INTERP_P2_F32 %VGPR9<kill,tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_F32_e32 %VGPR8<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR8<kill>, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %VGPR4, %VGPR6<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_CNDMASK_B32_e64 %VGPR4, %VGPR6<kill>, %SGPR0_SGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_INTERP_P1_F32 %VGPR0, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR8<def,tied1> = V_INTERP_P2_F32 %VGPR8<kill,tied0>, %VGPR1, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %VGPR6<kill>, %VGPR8<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_CNDMASK_B32_e64 %VGPR5, 1.000000e+00, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<kill,tied0>, %VGPR1, 3, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR2<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR6<kill>, %VGPR0<kill>, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR7<kill>, %VGPR0<kill>, %VGPR7, %VGPR0, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_WQM_B64 exec, exec                                                    ; BEFE0A7E
	S_MOV_B32 m0, s7                                                        ; BEFC0307
	V_INTERP_P1_F32 v3, v0, 1, 1, [m0]                                      ; C80C0500
	V_INTERP_P2_F32 v3, [v3], v1, 1, 1, [m0]                                ; C80D0501
	V_INTERP_P1_F32 v2, v0, 0, 1, [m0]                                      ; C8080400
	V_INTERP_P2_F32 v2, [v2], v1, 0, 1, [m0]                                ; C8090401
	S_LOAD_DWORDX4 s[8:11], s[2:3], 0                                       ; C0840300
	S_LOAD_DWORDX8 s[12:19], s[4:5], 0                                      ; C0C60500
	S_WAITCNT lgkmcnt(0)                                                    ; BF8C007F
	IMAGE_SAMPLE v[2:5], 15, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[12:19], s[8:11] ; F0800F00 00430202
	V_MOV_B32_e32 v6, -1.600000e+01                                         ; 7E0C02FF C1800000
	V_MOV_B32_e32 v7, 3.200000e+01                                          ; 7E0E02FF 42000000
	S_WAITCNT vmcnt(0)                                                      ; BF8C0770
	V_MAD_F32 v6, v5, v7, v6, 0, 0, 0, 0                                    ; D2820006 041A0F05
	V_EXP_F32_e32 v6, v6                                                    ; 7E0C4B06
	V_MUL_F32_e32 v7, v3, v6                                                ; 100E0D03
	S_LOAD_DWORDX4 s[0:3], s[0:1], 0                                        ; C0800100
	S_WAITCNT lgkmcnt(0)                                                    ; BF8C007F
	S_BUFFER_LOAD_DWORD s0, s[0:3], 0                                       ; C2000100
	S_WAITCNT lgkmcnt(0)                                                    ; BF8C007F
	V_CMP_GE_F32_e64 s[0:1], s0, 0.000000e+00, 0, 0, 0, 0                   ; D00C0000 02010000
	V_CNDMASK_B32_e64 v7, v3, v7, s[0:1], 0, 0, 0, 0                        ; D2000007 00020F03
	V_INTERP_P1_F32 v8, v0, 1, 0, [m0]                                      ; C8200100
	V_INTERP_P2_F32 v8, [v8], v1, 1, 0, [m0]                                ; C8210101
	V_MUL_F32_e32 v7, v7, v8                                                ; 100E1107
	V_MUL_F32_e32 v8, v2, v6                                                ; 10100D02
	V_CNDMASK_B32_e64 v8, v2, v8, s[0:1], 0, 0, 0, 0                        ; D2000008 00021102
	V_INTERP_P1_F32 v9, v0, 0, 0, [m0]                                      ; C8240000
	V_INTERP_P2_F32 v9, [v9], v1, 0, 0, [m0]                                ; C8250001
	V_MUL_F32_e32 v8, v8, v9                                                ; 10101308
	V_CVT_PKRTZ_F16_F32_e32 v7, v8, v7                                      ; 5E0E0F08
	V_MUL_F32_e32 v6, v4, v6                                                ; 100C0D04
	V_CNDMASK_B32_e64 v6, v4, v6, s[0:1], 0, 0, 0, 0                        ; D2000006 00020D04
	V_INTERP_P1_F32 v8, v0, 2, 0, [m0]                                      ; C8200200
	V_INTERP_P2_F32 v8, [v8], v1, 2, 0, [m0]                                ; C8210201
	V_MUL_F32_e32 v6, v6, v8                                                ; 100C1106
	V_CNDMASK_B32_e64 v2, v5, 1.000000e+00, s[0:1], 0, 0, 0, 0              ; D2000002 0001E505
	V_INTERP_P1_F32 v3, v0, 3, 0, [m0]                                      ; C80C0300
	V_INTERP_P2_F32 v3, [v3], v1, 3, 0, [m0]                                ; C80D0301
	V_MUL_F32_e32 v0, v2, v3                                                ; 10000702
	V_CVT_PKRTZ_F16_F32_e32 v0, v6, v0                                      ; 5E000106
	EXP 15, 0, 1, 1, 1, v7, v0, v7, v0                                      ; F8001C0F 00070007
	S_ENDPGM                                                                ; BF810000

INF:  
INF:  Gfx API: OpenGL
INF:  Resolution: 1680 x 1050
INF:  Vendor: ATI (0x1002)
INF:  Driver: X.Org (0x683D)
INF:  Renderer: Gallium 0.4 on AMD CAPE VERDE
INF:  Version: 3.0 Mesa 10.1.0-devel (git-3c9f009)
INF:  Video memory size: 512 MB
INF:  Available for textures: 512 MB
INF:  Active GPU(s): 1
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %21 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %4)
  %22 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %4)
  %23 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %4)
  %24 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %4)
  %25 = call i32 @llvm.SI.packf16(float %21, float %22)
  %26 = bitcast i32 %25 to float
  %27 = call i32 @llvm.SI.packf16(float %23, float %24)
  %28 = bitcast i32 %27 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %26, float %28, float %26, float %28)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR7 in %vreg4

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR7
	%EXEC<def> = S_WQM_B64 %EXEC
	%M0<def> = S_MOV_B32 %SGPR7
	%VGPR0<def> = V_INTERP_MOV_F32 2, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_INTERP_MOV_F32 2, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR1<kill>, %VGPR0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_INTERP_MOV_F32 2, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_INTERP_MOV_F32 2, 0, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR2<kill>, %VGPR1<kill>, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR1<kill>, %VGPR0<kill>, %VGPR1, %VGPR0, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_WQM_B64 exec, exec                ; BEFE0A7E
	S_MOV_B32 m0, s7                    ; BEFC0307
	V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302
	V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202
	V_CVT_PKRTZ_F16_F32_e32 v0, v1, v0  ; 5E000101
	V_INTERP_MOV_F32 v1, P0, 1, 0, [m0] ; C8060102
	V_INTERP_MOV_F32 v2, P0, 0, 0, [m0] ; C80A0002
	V_CVT_PKRTZ_F16_F32_e32 v1, v2, v1  ; 5E020302
	EXP 15, 0, 1, 1, 1, v1, v0, v1, v0  ; F8001C0F 00010001
	S_ENDPGM                            ; BF810000

WRN:  Display driver is too old, please update it ASAP!
INF:  SysMessage: Display driver is too old or version cannot be determined.
INF:  Press OK to update driver, or Cancel to continue.
INF:  Fullscreen on primary display
FRAG
  0: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
# Machine code for function main: Post SSA, not tracking liveness

BB#0: derived from LLVM BB %main_body
	%VGPR0<def> = V_MOV_B32_e32 0, %EXEC<imp-use>
	EXP 0, 0, 0, 1, 1, %VGPR0<kill>, %VGPR0, %VGPR0, %VGPR0, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	V_MOV_B32_e32 v0, 0               ; 7E000280
	EXP 0, 0, 0, 1, 1, v0, v0, v0, v0 ; F8001800 00000000
	S_ENDPGM                          ; BF810000

FRAG
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %21 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %4)
  %22 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %4)
  %23 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %4)
  %24 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %4)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %21, float %22, float %23, float %24)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR7 in %vreg4

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR7
	%EXEC<def> = S_WQM_B64 %EXEC
	%M0<def> = S_MOV_B32 %SGPR7
	%VGPR0<def> = V_INTERP_MOV_F32 2, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_INTERP_MOV_F32 2, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_INTERP_MOV_F32 2, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_INTERP_MOV_F32 2, 0, 0, %M0<kill>, %EXEC<imp-use>
	EXP 15, 0, 0, 1, 1, %VGPR3<kill>, %VGPR2<kill>, %VGPR1<kill>, %VGPR0<kill>, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_WQM_B64 exec, exec                ; BEFE0A7E
	S_MOV_B32 m0, s7                    ; BEFC0307
	V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302
	V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202
	V_INTERP_MOV_F32 v2, P0, 1, 0, [m0] ; C80A0102
	V_INTERP_MOV_F32 v3, P0, 0, 0, [m0] ; C80E0002
	EXP 15, 0, 0, 1, 1, v3, v2, v1, v0  ; F800180F 00010203
	S_ENDPGM                            ; BF810000

FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %21 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %4)
  %22 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %4)
  %23 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %4)
  %24 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %4)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %21, float %22, float %23, float %24)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR7 in %vreg4

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR7
	%EXEC<def> = S_WQM_B64 %EXEC
	%M0<def> = S_MOV_B32 %SGPR7
	%VGPR0<def> = V_INTERP_MOV_F32 2, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_INTERP_MOV_F32 2, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_INTERP_MOV_F32 2, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_INTERP_MOV_F32 2, 0, 0, %M0<kill>, %EXEC<imp-use>
	EXP 15, 0, 0, 1, 1, %VGPR3<kill>, %VGPR2<kill>, %VGPR1<kill>, %VGPR0<kill>, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_WQM_B64 exec, exec                ; BEFE0A7E
	S_MOV_B32 m0, s7                    ; BEFC0307
	V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302
	V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202
	V_INTERP_MOV_F32 v2, P0, 1, 0, [m0] ; C80A0102
	V_INTERP_MOV_F32 v3, P0, 0, 0, [m0] ; C80E0002
	EXP 15, 0, 0, 1, 1, v3, v2, v1, v0  ; F800180F 00010203
	S_ENDPGM                            ; BF810000

VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[0]
  0: MOV OUT[0], IN[0]
  1: MOV OUT[1], IN[1]
  2: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %11, i32 0, i32 %6)
  %13 = extractelement <4 x float> %12, i32 0
  %14 = extractelement <4 x float> %12, i32 1
  %15 = extractelement <4 x float> %12, i32 2
  %16 = extractelement <4 x float> %12, i32 3
  %17 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 1
  %18 = load <16 x i8> addrspace(2)* %17, !tbaa !0
  %19 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %18, i32 0, i32 %6)
  %20 = extractelement <4 x float> %19, i32 0
  %21 = extractelement <4 x float> %19, i32 1
  %22 = extractelement <4 x float> %19, i32 2
  %23 = extractelement <4 x float> %19, i32 3
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %20, float %21, float %22, float %23)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %13, float %14, float %15, float %16)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg6

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR6_SGPR7 %VGPR0
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%20](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%VGPR1_VGPR2_VGPR3_VGPR4<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	EXP 15, 32, 0, 0, 0, %VGPR1, %VGPR2, %VGPR3, %VGPR4, %EXEC<imp-use>, %VGPR1_VGPR2_VGPR3_VGPR4<imp-use,kill>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%11](align=8)(tbaa=!"const")
	S_WAITCNT 15
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR1, %VGPR2, %VGPR3, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_LOAD_DWORDX4 s[0:3], s[6:7], 4               ; C0800704
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	BUFFER_LOAD_FORMAT_XYZW v[1:4], s[0:3][v0] + 0 ; E00C2000 80000100
	S_WAITCNT vmcnt(0)                             ; BF8C0770
	EXP 15, 32, 0, 0, 0, v1, v2, v3, v4            ; F800020F 04030201
	S_LOAD_DWORDX4 s[0:3], s[6:7], 0               ; C0800700
	S_WAITCNT expcnt(0) lgkmcnt(0)                 ; BF8C000F
	BUFFER_LOAD_FORMAT_XYZW v[0:3], s[0:3][v0] + 0 ; E00C2000 80000000
	S_WAITCNT vmcnt(0)                             ; BF8C0770
	EXP 15, 12, 0, 1, 0, v0, v1, v2, v3            ; F80008CF 03020100
	S_ENDPGM                                       ; BF810000

VERT
DCL IN[0]
DCL OUT[0], POSITION
  0: MOV OUT[0], IN[0]
  1: END
STREAMOUT
  0: BUF0[0..0] <- OUT[0].x
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %13 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 0
  %14 = load <16 x i8> addrspace(2)* %13, !tbaa !0
  %15 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0
  %16 = load <16 x i8> addrspace(2)* %15, !tbaa !0
  %17 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %16, i32 0, i32 %9)
  %18 = extractelement <4 x float> %17, i32 0
  %19 = extractelement <4 x float> %17, i32 1
  %20 = extractelement <4 x float> %17, i32 2
  %21 = extractelement <4 x float> %17, i32 3
  %22 = lshr i32 %6, 16
  %23 = and i32 %22, 127
  %24 = call i32 @llvm.SI.tid()
  %25 = icmp ult i32 %24, %23
  br i1 %25, label %if-true-block, label %endif-block

if-true-block:                                    ; preds = %main_body
  %26 = add i32 %7, %24
  %27 = mul i32 %8, 4
  %28 = mul i32 %26, 4
  %29 = add i32 %28, %27
  %30 = bitcast float %18 to i32
  call void @llvm.SI.tbuffer.store.i32(<16 x i8> %14, i32 %30, i32 1, i32 %29, i32 0, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0)
  br label %endif-block

endif-block:                                      ; preds = %main_body, %if-true-block
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %18, float %19, float %20, float %21)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare i32 @llvm.SI.tid() #2

declare void @llvm.SI.tbuffer.store.i32(<16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32)

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR6_SGPR7 in %vreg7, %SGPR8_SGPR9 in %vreg8, %SGPR11 in %vreg10, %SGPR12 in %vreg11, %SGPR13 in %vreg12, %VGPR0 in %vreg13

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR6_SGPR7 %SGPR8_SGPR9 %SGPR11 %SGPR12 %SGPR13 %VGPR0
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%14](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	%SGPR0<def> = S_LSHR_B32 %SGPR11<kill>, 16
	%VGPR4<def> = V_MOV_B32_e32 127, %EXEC<imp-use>
	%VGPR5<def> = V_AND_B32_e32 %SGPR0<kill>, %VGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MBCNT_LO_U32_B32_e64 -1, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MBCNT_HI_U32_B32_e32 -1, %VGPR4<kill>, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = V_CMP_LT_U32_e64 %VGPR4, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%SGPR0_SGPR1<def> = S_AND_SAVEEXEC_B64 %SGPR0_SGPR1, %EXEC<imp-def>, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_XOR_B64 %EXEC, %SGPR0_SGPR1
    Successors according to CFG: BB#1(16) BB#2(16)

BB#1: derived from LLVM BB %if-true-block
    Live Ins: %VGPR0_VGPR1_VGPR2_VGPR3 %SGPR8_SGPR9 %SGPR12 %SGPR13 %SGPR0_SGPR1 %VGPR4
    Predecessors according to CFG: BB#0
	%VGPR4<def> = V_ADD_I32_e32 %SGPR12<kill>, %VGPR4<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR4<def> = V_LSHLREV_B32_e32 2, %VGPR4<kill>, %EXEC<imp-use>
	%SGPR2<def> = S_LSHL_B32 %SGPR13<kill>, 2
	%VGPR4<def> = V_ADD_I32_e32 %SGPR2<kill>, %VGPR4<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR8_SGPR9<kill>, 0; mem:LD16[%27](align=8)(tbaa=!"const")
	S_WAITCNT 127
	TBUFFER_STORE_FORMAT_X %VGPR0, 0, -1, 0, -1, 0, 4, 4, %VGPR4<kill>, %SGPR4_SGPR5_SGPR6_SGPR7<kill>, -1, 0, 0, %EXEC<imp-use>
	S_WAITCNT 1792
    Successors according to CFG: BB#2

BB#2: derived from LLVM BB %endif-block
    Live Ins: %VGPR0_VGPR1_VGPR2_VGPR3 %SGPR0_SGPR1
    Predecessors according to CFG: BB#0 BB#1
	%EXEC<def> = S_OR_B64 %EXEC, %SGPR0_SGPR1
	EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR1, %VGPR2, %VGPR3, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_LOAD_DWORDX4 s[0:3], s[6:7], 0                                       ; C0800700
	S_WAITCNT lgkmcnt(0)                                                   ; BF8C007F
	BUFFER_LOAD_FORMAT_XYZW v[0:3], s[0:3][v0] + 0                         ; E00C2000 80000000
	S_LSHR_B32 s0, s11, 16                                                 ; 9000900B
	V_MOV_B32_e32 v4, 127                                                  ; 7E0802FF 0000007F
	V_AND_B32_e32 v5, s0, v4                                               ; 360A0800
	V_MBCNT_LO_U32_B32_e64 v4, -1, 0, 0, 0, 0, 0                           ; D2460004 020100C1
	V_MBCNT_HI_U32_B32_e32 v4, -1, v4                                      ; 480808C1
	V_CMP_LT_U32_e64 s[0:1], v4, v5, 0, 0, 0, 0                            ; D1820000 02020B04
	S_WAITCNT vmcnt(0)                                                     ; BF8C0770
	S_AND_SAVEEXEC_B64 s[0:1], s[0:1]                                      ; BE802400
	S_XOR_B64 s[0:1], exec, s[0:1]                                         ; 8980007E
	V_ADD_I32_e32 v4, s12, v4                                              ; 4A08080C
	V_LSHLREV_B32_e32 v4, 2, v4                                            ; 34080882
	S_LSHL_B32 s2, s13, 2                                                  ; 8F02820D
	V_ADD_I32_e32 v4, s2, v4                                               ; 4A080802
	S_LOAD_DWORDX4 s[4:7], s[8:9], 0                                       ; C0820900
	S_WAITCNT lgkmcnt(0)                                                   ; BF8C007F
	TBUFFER_STORE_FORMAT_X v0, 0, -1, 0, -1, 0, 4, 4, v4, s[4:7], -1, 0, 0 ; EA245000 80410004
	S_WAITCNT vmcnt(0) expcnt(0)                                           ; BF8C0700
	S_OR_B64 exec, exec, s[0:1]                                            ; 88FE007E
	EXP 15, 12, 0, 1, 0, v0, v1, v2, v3                                    ; F80008CF 03020100
	S_ENDPGM                                                               ; BF810000

FRAG
DCL IN[0], GENERIC[0], CONSTANT
  0: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
# Machine code for function main: Post SSA, not tracking liveness

BB#0: derived from LLVM BB %main_body
	%VGPR0<def> = V_MOV_B32_e32 0, %EXEC<imp-use>
	EXP 0, 0, 0, 1, 1, %VGPR0<kill>, %VGPR0, %VGPR0, %VGPR0, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	V_MOV_B32_e32 v0, 0               ; 7E000280
	EXP 0, 0, 0, 1, 1, v0, v0, v0, v0 ; F8001800 00000000
	S_ENDPGM                          ; BF810000

WRN:  [OpenGL] "GL_ARB_get_program_binary" extension is present but not used because no binary formats are exposed.
WRN:  [OpenGL] Unable to determine VRAM size... assuming 512 MB.
FRAG
DCL IN[0], GENERIC[0], LINEAR
DCL OUT[0], COLOR
DCL SAMP[0]
  0: TEX OUT[0], IN[0], SAMP[0], 2D
  1: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %21 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0
  %22 = load <32 x i8> addrspace(2)* %21, !tbaa !0
  %23 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0
  %24 = load <16 x i8> addrspace(2)* %23, !tbaa !0
  %25 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %4, <2 x i32> %10)
  %26 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %4, <2 x i32> %10)
  %27 = bitcast float %25 to i32
  %28 = bitcast float %26 to i32
  %29 = insertelement <2 x i32> undef, i32 %27, i32 0
  %30 = insertelement <2 x i32> %29, i32 %28, i32 1
  %31 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %30, <32 x i8> %22, <16 x i8> %24, i32 2)
  %32 = extractelement <4 x float> %31, i32 0
  %33 = extractelement <4 x float> %31, i32 1
  %34 = extractelement <4 x float> %31, i32 2
  %35 = extractelement <4 x float> %31, i32 3
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %32, float %33, float %34, float %35)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR7 in %vreg4, %VGPR0 in %vreg5, %VGPR1 in %vreg6

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR7 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR7
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-def>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%24](align=8)(tbaa=!"const")
	%SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%21](tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = IMAGE_SAMPLE_V4_V2 15, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3<kill>, %SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<kill>, %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	EXP 15, 0, 0, 1, 1, %VGPR0, %VGPR1, %VGPR2, %VGPR3, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_WQM_B64 exec, exec                                                  ; BEFE0A7E
	S_MOV_B32 m0, s7                                                      ; BEFC0307
	V_INTERP_P1_F32 v3, v0, 1, 0, [m0]                                    ; C80C0100
	V_INTERP_P2_F32 v3, [v3], v1, 1, 0, [m0]                              ; C80D0101
	V_INTERP_P1_F32 v2, v0, 0, 0, [m0]                                    ; C8080000
	V_INTERP_P2_F32 v2, [v2], v1, 0, 0, [m0]                              ; C8090001
	S_LOAD_DWORDX4 s[0:3], s[2:3], 0                                      ; C0800300
	S_LOAD_DWORDX8 s[4:11], s[4:5], 0                                     ; C0C20500
	S_WAITCNT lgkmcnt(0)                                                  ; BF8C007F
	IMAGE_SAMPLE v[0:3], 15, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[4:11], s[0:3] ; F0800F00 00010002
	S_WAITCNT vmcnt(0)                                                    ; BF8C0770
	EXP 15, 0, 0, 1, 1, v0, v1, v2, v3                                    ; F800180F 03020100
	S_ENDPGM                                                              ; BF810000

FRAG
DCL IN[0], GENERIC[0], LINEAR
DCL OUT[0], COLOR
DCL SAMP[0]
  0: TEX OUT[0], IN[0], SAMP[0], 2D
  1: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %21 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0
  %22 = load <32 x i8> addrspace(2)* %21, !tbaa !0
  %23 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0
  %24 = load <16 x i8> addrspace(2)* %23, !tbaa !0
  %25 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %4, <2 x i32> %10)
  %26 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %4, <2 x i32> %10)
  %27 = bitcast float %25 to i32
  %28 = bitcast float %26 to i32
  %29 = insertelement <2 x i32> undef, i32 %27, i32 0
  %30 = insertelement <2 x i32> %29, i32 %28, i32 1
  %31 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %30, <32 x i8> %22, <16 x i8> %24, i32 2)
  %32 = extractelement <4 x float> %31, i32 0
  %33 = extractelement <4 x float> %31, i32 1
  %34 = extractelement <4 x float> %31, i32 2
  %35 = extractelement <4 x float> %31, i32 3
  %36 = call i32 @llvm.SI.packf16(float %32, float %33)
  %37 = bitcast i32 %36 to float
  %38 = call i32 @llvm.SI.packf16(float %34, float %35)
  %39 = bitcast i32 %38 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %37, float %39, float %37, float %39)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR7 in %vreg4, %VGPR0 in %vreg5, %VGPR1 in %vreg6

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR7 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR7
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-def>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%24](align=8)(tbaa=!"const")
	%SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%21](tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = IMAGE_SAMPLE_V4_V2 15, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3<kill>, %SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<kill>, %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR4<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR2, %VGPR3, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0, %VGPR1, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	EXP 15, 0, 1, 1, 1, %VGPR0<kill>, %VGPR4<kill>, %VGPR0, %VGPR4, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_WQM_B64 exec, exec                                                  ; BEFE0A7E
	S_MOV_B32 m0, s7                                                      ; BEFC0307
	V_INTERP_P1_F32 v3, v0, 1, 0, [m0]                                    ; C80C0100
	V_INTERP_P2_F32 v3, [v3], v1, 1, 0, [m0]                              ; C80D0101
	V_INTERP_P1_F32 v2, v0, 0, 0, [m0]                                    ; C8080000
	V_INTERP_P2_F32 v2, [v2], v1, 0, 0, [m0]                              ; C8090001
	S_LOAD_DWORDX4 s[0:3], s[2:3], 0                                      ; C0800300
	S_LOAD_DWORDX8 s[4:11], s[4:5], 0                                     ; C0C20500
	S_WAITCNT lgkmcnt(0)                                                  ; BF8C007F
	IMAGE_SAMPLE v[0:3], 15, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[4:11], s[0:3] ; F0800F00 00010002
	S_WAITCNT vmcnt(0)                                                    ; BF8C0770
	V_CVT_PKRTZ_F16_F32_e32 v4, v2, v3                                    ; 5E080702
	V_CVT_PKRTZ_F16_F32_e32 v0, v0, v1                                    ; 5E000300
	EXP 15, 0, 1, 1, 1, v0, v4, v0, v4                                    ; F8001C0F 04000400
	S_ENDPGM                                                              ; BF810000

INF:  
INF:  Gfx API: OpenGL
INF:  Resolution: 1680 x 1050
INF:  Vendor: ATI (0x1002)
INF:  Driver: X.Org (0x683D)
INF:  Renderer: Gallium 0.4 on AMD CAPE VERDE
INF:  Version: 3.0 Mesa 10.1.0-devel (git-3c9f009)
INF:  Video memory size: 512 MB
INF:  Available for textures: 512 MB
INF:  Active GPU(s): 1
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], COLOR, COLOR
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %21 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %4)
  %22 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %4)
  %23 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %4)
  %24 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %4)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %21, float %22, float %23, float %24)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR7 in %vreg4

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR7
	%EXEC<def> = S_WQM_B64 %EXEC
	%M0<def> = S_MOV_B32 %SGPR7
	%VGPR0<def> = V_INTERP_MOV_F32 2, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_INTERP_MOV_F32 2, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_INTERP_MOV_F32 2, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_INTERP_MOV_F32 2, 0, 0, %M0<kill>, %EXEC<imp-use>
	EXP 15, 0, 0, 1, 1, %VGPR3<kill>, %VGPR2<kill>, %VGPR1<kill>, %VGPR0<kill>, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_WQM_B64 exec, exec                ; BEFE0A7E
	S_MOV_B32 m0, s7                    ; BEFC0307
	V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302
	V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202
	V_INTERP_MOV_F32 v2, P0, 1, 0, [m0] ; C80A0102
	V_INTERP_MOV_F32 v3, P0, 0, 0, [m0] ; C80E0002
	EXP 15, 0, 0, 1, 1, v3, v2, v1, v0  ; F800180F 00010203
	S_ENDPGM                            ; BF810000

VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], COLOR
DCL CONST[0..3]
DCL TEMP[0]
  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
  4: MOV OUT[1], IN[1]
  5: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0)
  %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4)
  %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8)
  %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12)
  %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16)
  %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20)
  %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24)
  %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28)
  %20 = call float @llvm.SI.load.const(<16 x i8> %11, i32 32)
  %21 = call float @llvm.SI.load.const(<16 x i8> %11, i32 36)
  %22 = call float @llvm.SI.load.const(<16 x i8> %11, i32 40)
  %23 = call float @llvm.SI.load.const(<16 x i8> %11, i32 44)
  %24 = call float @llvm.SI.load.const(<16 x i8> %11, i32 48)
  %25 = call float @llvm.SI.load.const(<16 x i8> %11, i32 52)
  %26 = call float @llvm.SI.load.const(<16 x i8> %11, i32 56)
  %27 = call float @llvm.SI.load.const(<16 x i8> %11, i32 60)
  %28 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0
  %29 = load <16 x i8> addrspace(2)* %28, !tbaa !0
  %30 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %29, i32 0, i32 %6)
  %31 = extractelement <4 x float> %30, i32 0
  %32 = extractelement <4 x float> %30, i32 1
  %33 = extractelement <4 x float> %30, i32 2
  %34 = extractelement <4 x float> %30, i32 3
  %35 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 1
  %36 = load <16 x i8> addrspace(2)* %35, !tbaa !0
  %37 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %36, i32 0, i32 %6)
  %38 = extractelement <4 x float> %37, i32 0
  %39 = extractelement <4 x float> %37, i32 1
  %40 = extractelement <4 x float> %37, i32 2
  %41 = extractelement <4 x float> %37, i32 3
  %42 = fmul float %31, %12
  %43 = fmul float %31, %13
  %44 = fmul float %31, %14
  %45 = fmul float %31, %15
  %46 = fmul float %32, %16
  %47 = fadd float %46, %42
  %48 = fmul float %32, %17
  %49 = fadd float %48, %43
  %50 = fmul float %32, %18
  %51 = fadd float %50, %44
  %52 = fmul float %32, %19
  %53 = fadd float %52, %45
  %54 = fmul float %33, %20
  %55 = fadd float %54, %47
  %56 = fmul float %33, %21
  %57 = fadd float %56, %49
  %58 = fmul float %33, %22
  %59 = fadd float %58, %51
  %60 = fmul float %33, %23
  %61 = fadd float %60, %53
  %62 = fmul float %34, %24
  %63 = fadd float %62, %55
  %64 = fmul float %34, %25
  %65 = fadd float %64, %57
  %66 = fmul float %34, %26
  %67 = fadd float %66, %59
  %68 = fmul float %34, %27
  %69 = fadd float %68, %61
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %38, float %39, float %40, float %41)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %63, float %65, float %67, float %69)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg6

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%40](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%VGPR1_VGPR2_VGPR3_VGPR4<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	EXP 15, 32, 0, 0, 0, %VGPR1, %VGPR2, %VGPR3, %VGPR4, %EXEC<imp-use>, %VGPR1_VGPR2_VGPR3_VGPR4<imp-use,kill>
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%31](align=8)(tbaa=!"const")
	S_WAITCNT 15
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%11](align=8)(tbaa=!"const")
	S_WAITCNT 112
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 3; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR4<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e64 %VGPR0, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 7; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR1, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 11; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR2, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 15; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR3, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MUL_F32_e64 %VGPR0, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 6; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR1, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 10; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR2, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 14; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR3, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e64 %VGPR0, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 5; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR1, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 9; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR2, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 13; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR3, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 0; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MUL_F32_e64 %VGPR0, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 4; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR8<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR1, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 8; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR8<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR2, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 12; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR8<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR3, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	EXP 15, 12, 0, 1, 0, %VGPR0<kill>, %VGPR6<kill>, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_LOAD_DWORDX4 s[8:11], s[6:7], 4               ; C0840704
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	BUFFER_LOAD_FORMAT_XYZW v[1:4], s[8:11][v0] + 0 ; E00C2000 80020100
	S_WAITCNT vmcnt(0)                              ; BF8C0770
	EXP 15, 32, 0, 0, 0, v1, v2, v3, v4             ; F800020F 04030201
	S_LOAD_DWORDX4 s[4:7], s[6:7], 0                ; C0820700
	S_WAITCNT expcnt(0) lgkmcnt(0)                  ; BF8C000F
	BUFFER_LOAD_FORMAT_XYZW v[0:3], s[4:7][v0] + 0  ; E00C2000 80010000
	S_LOAD_DWORDX4 s[0:3], s[0:1], 0                ; C0800100
	S_WAITCNT vmcnt(0) lgkmcnt(0)                   ; BF8C0070
	S_BUFFER_LOAD_DWORD s4, s[0:3], 3               ; C2020103
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v4, s4                            ; 7E080204
	V_MUL_F32_e64 v4, v0, v4, 0, 0, 0, 0            ; D2100004 02020900
	S_BUFFER_LOAD_DWORD s4, s[0:3], 7               ; C2020107
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v5, s4                            ; 7E0A0204
	V_MAD_F32 v4, v1, v5, v4, 0, 0, 0, 0            ; D2820004 04120B01
	S_BUFFER_LOAD_DWORD s4, s[0:3], 11              ; C202010B
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v5, s4                            ; 7E0A0204
	V_MAD_F32 v4, v2, v5, v4, 0, 0, 0, 0            ; D2820004 04120B02
	S_BUFFER_LOAD_DWORD s4, s[0:3], 15              ; C202010F
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v5, s4                            ; 7E0A0204
	V_MAD_F32 v4, v3, v5, v4, 0, 0, 0, 0            ; D2820004 04120B03
	S_BUFFER_LOAD_DWORD s4, s[0:3], 2               ; C2020102
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v5, s4                            ; 7E0A0204
	V_MUL_F32_e64 v5, v0, v5, 0, 0, 0, 0            ; D2100005 02020B00
	S_BUFFER_LOAD_DWORD s4, s[0:3], 6               ; C2020106
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v6, s4                            ; 7E0C0204
	V_MAD_F32 v5, v1, v6, v5, 0, 0, 0, 0            ; D2820005 04160D01
	S_BUFFER_LOAD_DWORD s4, s[0:3], 10              ; C202010A
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v6, s4                            ; 7E0C0204
	V_MAD_F32 v5, v2, v6, v5, 0, 0, 0, 0            ; D2820005 04160D02
	S_BUFFER_LOAD_DWORD s4, s[0:3], 14              ; C202010E
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v6, s4                            ; 7E0C0204
	V_MAD_F32 v5, v3, v6, v5, 0, 0, 0, 0            ; D2820005 04160D03
	S_BUFFER_LOAD_DWORD s4, s[0:3], 1               ; C2020101
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v6, s4                            ; 7E0C0204
	V_MUL_F32_e64 v6, v0, v6, 0, 0, 0, 0            ; D2100006 02020D00
	S_BUFFER_LOAD_DWORD s4, s[0:3], 5               ; C2020105
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v7, s4                            ; 7E0E0204
	V_MAD_F32 v6, v1, v7, v6, 0, 0, 0, 0            ; D2820006 041A0F01
	S_BUFFER_LOAD_DWORD s4, s[0:3], 9               ; C2020109
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v7, s4                            ; 7E0E0204
	V_MAD_F32 v6, v2, v7, v6, 0, 0, 0, 0            ; D2820006 041A0F02
	S_BUFFER_LOAD_DWORD s4, s[0:3], 13              ; C202010D
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v7, s4                            ; 7E0E0204
	V_MAD_F32 v6, v3, v7, v6, 0, 0, 0, 0            ; D2820006 041A0F03
	S_BUFFER_LOAD_DWORD s4, s[0:3], 0               ; C2020100
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v7, s4                            ; 7E0E0204
	V_MUL_F32_e64 v7, v0, v7, 0, 0, 0, 0            ; D2100007 02020F00
	S_BUFFER_LOAD_DWORD s4, s[0:3], 4               ; C2020104
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v8, s4                            ; 7E100204
	V_MAD_F32 v7, v1, v8, v7, 0, 0, 0, 0            ; D2820007 041E1101
	S_BUFFER_LOAD_DWORD s4, s[0:3], 8               ; C2020108
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v8, s4                            ; 7E100204
	V_MAD_F32 v7, v2, v8, v7, 0, 0, 0, 0            ; D2820007 041E1102
	S_BUFFER_LOAD_DWORD s0, s[0:3], 12              ; C200010C
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v8, s0                            ; 7E100200
	V_MAD_F32 v0, v3, v8, v7, 0, 0, 0, 0            ; D2820000 041E1103
	EXP 15, 12, 0, 1, 0, v0, v6, v5, v4             ; F80008CF 04050600
	S_ENDPGM                                        ; BF810000

FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %21 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %4)
  %22 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %4)
  %23 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %4)
  %24 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %4)
  %25 = call i32 @llvm.SI.packf16(float %21, float %22)
  %26 = bitcast i32 %25 to float
  %27 = call i32 @llvm.SI.packf16(float %23, float %24)
  %28 = bitcast i32 %27 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %26, float %28, float %26, float %28)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR7 in %vreg4

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR7
	%EXEC<def> = S_WQM_B64 %EXEC
	%M0<def> = S_MOV_B32 %SGPR7
	%VGPR0<def> = V_INTERP_MOV_F32 2, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_INTERP_MOV_F32 2, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR1<kill>, %VGPR0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_INTERP_MOV_F32 2, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_INTERP_MOV_F32 2, 0, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR2<kill>, %VGPR1<kill>, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR1<kill>, %VGPR0<kill>, %VGPR1, %VGPR0, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_WQM_B64 exec, exec                ; BEFE0A7E
	S_MOV_B32 m0, s7                    ; BEFC0307
	V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302
	V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202
	V_CVT_PKRTZ_F16_F32_e32 v0, v1, v0  ; 5E000101
	V_INTERP_MOV_F32 v1, P0, 1, 0, [m0] ; C8060102
	V_INTERP_MOV_F32 v2, P0, 0, 0, [m0] ; C80A0002
	V_CVT_PKRTZ_F16_F32_e32 v1, v2, v1  ; 5E020302
	EXP 15, 0, 1, 1, 1, v1, v0, v1, v0  ; F8001C0F 00010001
	S_ENDPGM                            ; BF810000

INF:  
INF:  Sfx API: OpenAL
INF:  Device: PulseAudio Default
INF:  Mixer frequency: 44100 Hz
INF:  Mixer voices: 64
INF:  Max sound sources: 25
INF:  Max total volume: 3
INF:  Speaker config: (unknown)
INF:  Environment FX: not supported
INF:  
INF:  Connected gamepad 0 - A4TECH USB Device (/dev/input/js0) with 57 buttons and 37 axes.
INF:  Cannot send rumble effect to gamepad 0
FRAG
DCL IN[0], GENERIC[0], LINEAR
DCL OUT[0], COLOR
DCL SAMP[0]
  0: TEX OUT[0], IN[0], SAMP[0], 2D
  1: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %21 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0
  %22 = load <32 x i8> addrspace(2)* %21, !tbaa !0
  %23 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0
  %24 = load <16 x i8> addrspace(2)* %23, !tbaa !0
  %25 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %4, <2 x i32> %10)
  %26 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %4, <2 x i32> %10)
  %27 = bitcast float %25 to i32
  %28 = bitcast float %26 to i32
  %29 = insertelement <2 x i32> undef, i32 %27, i32 0
  %30 = insertelement <2 x i32> %29, i32 %28, i32 1
  %31 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %30, <32 x i8> %22, <16 x i8> %24, i32 2)
  %32 = extractelement <4 x float> %31, i32 0
  %33 = extractelement <4 x float> %31, i32 1
  %34 = extractelement <4 x float> %31, i32 2
  %35 = extractelement <4 x float> %31, i32 3
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %32, float %33, float %34, float %35)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR7 in %vreg4, %VGPR0 in %vreg5, %VGPR1 in %vreg6

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR7 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR7
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-def>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%24](align=8)(tbaa=!"const")
	%SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%21](tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = IMAGE_SAMPLE_V4_V2 15, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3<kill>, %SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<kill>, %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	EXP 15, 0, 0, 1, 1, %VGPR0, %VGPR1, %VGPR2, %VGPR3, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_WQM_B64 exec, exec                                                  ; BEFE0A7E
	S_MOV_B32 m0, s7                                                      ; BEFC0307
	V_INTERP_P1_F32 v3, v0, 1, 0, [m0]                                    ; C80C0100
	V_INTERP_P2_F32 v3, [v3], v1, 1, 0, [m0]                              ; C80D0101
	V_INTERP_P1_F32 v2, v0, 0, 0, [m0]                                    ; C8080000
	V_INTERP_P2_F32 v2, [v2], v1, 0, 0, [m0]                              ; C8090001
	S_LOAD_DWORDX4 s[0:3], s[2:3], 0                                      ; C0800300
	S_LOAD_DWORDX8 s[4:11], s[4:5], 0                                     ; C0C20500
	S_WAITCNT lgkmcnt(0)                                                  ; BF8C007F
	IMAGE_SAMPLE v[0:3], 15, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[4:11], s[0:3] ; F0800F00 00010002
	S_WAITCNT vmcnt(0)                                                    ; BF8C0770
	EXP 15, 0, 0, 1, 1, v0, v1, v2, v3                                    ; F800180F 03020100
	S_ENDPGM                                                              ; BF810000

INF:  AutoDetect: No previous hardware values stored, adjusting settings automatically.
INF:  CPU efficiency: 3300 MHz * 2 cores = 5940 Mhz
INF:  ID: 0x683d; card: Radeon HD 8760/7700 series; quality: 4
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %21 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %4)
  %22 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %4)
  %23 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %4)
  %24 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %4)
  %25 = call i32 @llvm.SI.packf16(float %21, float %22)
  %26 = bitcast i32 %25 to float
  %27 = call i32 @llvm.SI.packf16(float %23, float %24)
  %28 = bitcast i32 %27 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %26, float %28, float %26, float %28)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR7 in %vreg4

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR7
	%EXEC<def> = S_WQM_B64 %EXEC
	%M0<def> = S_MOV_B32 %SGPR7
	%VGPR0<def> = V_INTERP_MOV_F32 2, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_INTERP_MOV_F32 2, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR1<kill>, %VGPR0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_INTERP_MOV_F32 2, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_INTERP_MOV_F32 2, 0, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR2<kill>, %VGPR1<kill>, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR1<kill>, %VGPR0<kill>, %VGPR1, %VGPR0, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_WQM_B64 exec, exec                ; BEFE0A7E
	S_MOV_B32 m0, s7                    ; BEFC0307
	V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302
	V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202
	V_CVT_PKRTZ_F16_F32_e32 v0, v1, v0  ; 5E000101
	V_INTERP_MOV_F32 v1, P0, 1, 0, [m0] ; C8060102
	V_INTERP_MOV_F32 v2, P0, 0, 0, [m0] ; C80A0002
	V_CVT_PKRTZ_F16_F32_e32 v1, v2, v1  ; 5E020302
	EXP 15, 0, 1, 1, 1, v1, v0, v1, v0  ; F8001C0F 00010001
	S_ENDPGM                            ; BF810000

VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[0]
  0: MOV OUT[0], IN[0]
  1: MOV OUT[1], IN[1]
  2: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %11, i32 0, i32 %6)
  %13 = extractelement <4 x float> %12, i32 0
  %14 = extractelement <4 x float> %12, i32 1
  %15 = extractelement <4 x float> %12, i32 2
  %16 = extractelement <4 x float> %12, i32 3
  %17 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 1
  %18 = load <16 x i8> addrspace(2)* %17, !tbaa !0
  %19 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %18, i32 0, i32 %6)
  %20 = extractelement <4 x float> %19, i32 0
  %21 = extractelement <4 x float> %19, i32 1
  %22 = extractelement <4 x float> %19, i32 2
  %23 = extractelement <4 x float> %19, i32 3
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %20, float %21, float %22, float %23)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %13, float %14, float %15, float %16)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg6

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR6_SGPR7 %VGPR0
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%20](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%VGPR1_VGPR2_VGPR3_VGPR4<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	EXP 15, 32, 0, 0, 0, %VGPR1, %VGPR2, %VGPR3, %VGPR4, %EXEC<imp-use>, %VGPR1_VGPR2_VGPR3_VGPR4<imp-use,kill>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%11](align=8)(tbaa=!"const")
	S_WAITCNT 15
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR1, %VGPR2, %VGPR3, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_LOAD_DWORDX4 s[0:3], s[6:7], 4               ; C0800704
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	BUFFER_LOAD_FORMAT_XYZW v[1:4], s[0:3][v0] + 0 ; E00C2000 80000100
	S_WAITCNT vmcnt(0)                             ; BF8C0770
	EXP 15, 32, 0, 0, 0, v1, v2, v3, v4            ; F800020F 04030201
	S_LOAD_DWORDX4 s[0:3], s[6:7], 0               ; C0800700
	S_WAITCNT expcnt(0) lgkmcnt(0)                 ; BF8C000F
	BUFFER_LOAD_FORMAT_XYZW v[0:3], s[0:3][v0] + 0 ; E00C2000 80000000
	S_WAITCNT vmcnt(0)                             ; BF8C0770
	EXP 15, 12, 0, 1, 0, v0, v1, v2, v3            ; F80008CF 03020100
	S_ENDPGM                                       ; BF810000

Installing breakpad exception handler for appid(gameoverlayui)/version(20131030110811_client)
Installing breakpad exception handler for appid(gameoverlayui)/version(1.0_client)
Fontconfig error: "/etc/fonts/conf.d/10-scale-bitmap-fonts.conf", line 70: non-double matrix element
Fontconfig error: "/etc/fonts/conf.d/10-scale-bitmap-fonts.conf", line 70: non-double matrix element
Fontconfig warning: "/etc/fonts/conf.d/10-scale-bitmap-fonts.conf", line 78: saw unknown, expected number
Installing breakpad exception handler for appid(gameoverlayui)/version(1.0_client)
[1124/190030:WARNING:proxy_service.cc(958)] PAC support disabled because there is no system implementation
Installing breakpad exception handler for appid(gameoverlayui)/version(1.0_client)
Installing breakpad exception handler for appid(gameoverlayui)/version(1.0_client)
Installing breakpad exception handler for appid(steam)/version(1383158641_client)
Installing breakpad exception handler for appid(steam)/version(1383158641_client)
INF:  AutoDetect: storing new settings: gfx_iPixelProgramVersion=30,gfx_ctConcurrentGPUs=1,sys_iGPUVendorID=4098,sys_iCPUFamily=6,sys_iCPUMHz=3300,sys_iGPUDeviceID=26685,sys_strCPUVendor=GenuineIntel,gfx_ulVideoMemoryMB=512,
FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], COLOR, COLOR
DCL IN[1], GENERIC[0], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL TEMP[0], LOCAL
  0: MOV TEMP[0].xy, IN[1].xyyy
  1: MOV TEMP[0].w, IN[1].wwww
  2: TXP TEMP[0], TEMP[0], SAMP[0], 2D
  3: MUL TEMP[0], TEMP[0], IN[0]
  4: MOV OUT[0], TEMP[0]
  5: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %21 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0
  %22 = load <32 x i8> addrspace(2)* %21, !tbaa !0
  %23 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0
  %24 = load <16 x i8> addrspace(2)* %23, !tbaa !0
  %25 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %4, <2 x i32> %6)
  %26 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %4, <2 x i32> %6)
  %27 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %4, <2 x i32> %6)
  %28 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %4, <2 x i32> %6)
  %29 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %4, <2 x i32> %6)
  %30 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %4, <2 x i32> %6)
  %31 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %4, <2 x i32> %6)
  %32 = fdiv float %29, %31
  %33 = fdiv float %30, %31
  %34 = bitcast float %32 to i32
  %35 = bitcast float %33 to i32
  %36 = insertelement <2 x i32> undef, i32 %34, i32 0
  %37 = insertelement <2 x i32> %36, i32 %35, i32 1
  %38 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %37, <32 x i8> %22, <16 x i8> %24, i32 2)
  %39 = extractelement <4 x float> %38, i32 0
  %40 = extractelement <4 x float> %38, i32 1
  %41 = extractelement <4 x float> %38, i32 2
  %42 = extractelement <4 x float> %38, i32 3
  %43 = fmul float %39, %25
  %44 = fmul float %40, %26
  %45 = fmul float %41, %27
  %46 = fmul float %42, %28
  %47 = call i32 @llvm.SI.packf16(float %43, float %44)
  %48 = bitcast i32 %47 to float
  %49 = call i32 @llvm.SI.packf16(float %45, float %46)
  %50 = bitcast i32 %49 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %48, float %50, float %48, float %50)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR7 in %vreg4, %VGPR0 in %vreg5, %VGPR1 in %vreg6

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR7 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR7
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 1, 1, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<kill,tied0>, %VGPR1, 1, 1, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 3, 1, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<kill,tied0>, %VGPR1, 3, 1, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_RCP_F32_e32 %VGPR3<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MUL_F32_e32 %VGPR2<kill>, %VGPR3, %EXEC<imp-use>, %VGPR4_VGPR5<imp-def>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 1, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<kill,tied0>, %VGPR1, 0, 1, %M0<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e32 %VGPR2<kill>, %VGPR3<kill>, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%24](align=8)(tbaa=!"const")
	%SGPR8_SGPR9_SGPR10_SGPR11_SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%21](tbaa=!"const")
	S_WAITCNT 127
	%VGPR2_VGPR3_VGPR4_VGPR5<def> = IMAGE_SAMPLE_V4_V2 15, 0, 0, 0, 0, 0, 0, 0, %VGPR4_VGPR5<kill>, %SGPR8_SGPR9_SGPR10_SGPR11_SGPR12_SGPR13_SGPR14_SGPR15<kill>, %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_INTERP_P1_F32 %VGPR0, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR6<def,tied1> = V_INTERP_P2_F32 %VGPR6<kill,tied0>, %VGPR1, 3, 0, %M0<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR6<def> = V_MUL_F32_e32 %VGPR5, %VGPR6<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_INTERP_P1_F32 %VGPR0, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR7<def,tied1> = V_INTERP_P2_F32 %VGPR7<kill,tied0>, %VGPR1, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MUL_F32_e32 %VGPR4, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR7<kill>, %VGPR6<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR7<def,tied1> = V_INTERP_P2_F32 %VGPR7<kill,tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MUL_F32_e32 %VGPR3, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR8<def,tied1> = V_INTERP_P2_F32 %VGPR8<kill,tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR2, %VGPR8<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0<kill>, %VGPR7<kill>, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR0<kill>, %VGPR6<kill>, %VGPR0, %VGPR6, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_WQM_B64 exec, exec                                                  ; BEFE0A7E
	S_MOV_B32 m0, s7                                                      ; BEFC0307
	V_INTERP_P1_F32 v2, v0, 1, 1, [m0]                                    ; C8080500
	V_INTERP_P2_F32 v2, [v2], v1, 1, 1, [m0]                              ; C8090501
	V_INTERP_P1_F32 v3, v0, 3, 1, [m0]                                    ; C80C0700
	V_INTERP_P2_F32 v3, [v3], v1, 3, 1, [m0]                              ; C80D0701
	V_RCP_F32_e32 v3, v3                                                  ; 7E065503
	V_MUL_F32_e32 v5, v2, v3                                              ; 100A0702
	V_INTERP_P1_F32 v2, v0, 0, 1, [m0]                                    ; C8080400
	V_INTERP_P2_F32 v2, [v2], v1, 0, 1, [m0]                              ; C8090401
	V_MUL_F32_e32 v4, v2, v3                                              ; 10080702
	S_LOAD_DWORDX4 s[0:3], s[2:3], 0                                      ; C0800300
	S_LOAD_DWORDX8 s[8:15], s[4:5], 0                                     ; C0C40500
	S_WAITCNT lgkmcnt(0)                                                  ; BF8C007F
	IMAGE_SAMPLE v[2:5], 15, 0, 0, 0, 0, 0, 0, 0, v[4:5], s[8:15], s[0:3] ; F0800F00 00020204
	V_INTERP_P1_F32 v6, v0, 3, 0, [m0]                                    ; C8180300
	V_INTERP_P2_F32 v6, [v6], v1, 3, 0, [m0]                              ; C8190301
	S_WAITCNT vmcnt(0)                                                    ; BF8C0770
	V_MUL_F32_e32 v6, v5, v6                                              ; 100C0D05
	V_INTERP_P1_F32 v7, v0, 2, 0, [m0]                                    ; C81C0200
	V_INTERP_P2_F32 v7, [v7], v1, 2, 0, [m0]                              ; C81D0201
	V_MUL_F32_e32 v7, v4, v7                                              ; 100E0F04
	V_CVT_PKRTZ_F16_F32_e32 v6, v7, v6                                    ; 5E0C0D07
	V_INTERP_P1_F32 v7, v0, 1, 0, [m0]                                    ; C81C0100
	V_INTERP_P2_F32 v7, [v7], v1, 1, 0, [m0]                              ; C81D0101
	V_MUL_F32_e32 v7, v3, v7                                              ; 100E0F03
	V_INTERP_P1_F32 v8, v0, 0, 0, [m0]                                    ; C8200000
	V_INTERP_P2_F32 v8, [v8], v1, 0, 0, [m0]                              ; C8210001
	V_MUL_F32_e32 v0, v2, v8                                              ; 10001102
	V_CVT_PKRTZ_F16_F32_e32 v0, v0, v7                                    ; 5E000F00
	EXP 15, 0, 1, 1, 1, v0, v6, v0, v6                                    ; F8001C0F 06000600
	S_ENDPGM                                                              ; BF810000

VERT
DCL IN[0]
DCL IN[1]
DCL IN[2]
DCL OUT[0], POSITION
DCL OUT[1], COLOR
DCL OUT[2], GENERIC[0]
DCL CONST[0..7]
DCL TEMP[0]
  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
  4: MOV OUT[1], IN[1]
  5: MUL TEMP[0], IN[2].xxxx, CONST[4]
  6: MAD TEMP[0], IN[2].yyyy, CONST[5], TEMP[0]
  7: MAD TEMP[0], IN[2].zzzz, CONST[6], TEMP[0]
  8: MAD OUT[2], IN[2].wwww, CONST[7], TEMP[0]
  9: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0)
  %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4)
  %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8)
  %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12)
  %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16)
  %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20)
  %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24)
  %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28)
  %20 = call float @llvm.SI.load.const(<16 x i8> %11, i32 32)
  %21 = call float @llvm.SI.load.const(<16 x i8> %11, i32 36)
  %22 = call float @llvm.SI.load.const(<16 x i8> %11, i32 40)
  %23 = call float @llvm.SI.load.const(<16 x i8> %11, i32 44)
  %24 = call float @llvm.SI.load.const(<16 x i8> %11, i32 48)
  %25 = call float @llvm.SI.load.const(<16 x i8> %11, i32 52)
  %26 = call float @llvm.SI.load.const(<16 x i8> %11, i32 56)
  %27 = call float @llvm.SI.load.const(<16 x i8> %11, i32 60)
  %28 = call float @llvm.SI.load.const(<16 x i8> %11, i32 64)
  %29 = call float @llvm.SI.load.const(<16 x i8> %11, i32 68)
  %30 = call float @llvm.SI.load.const(<16 x i8> %11, i32 72)
  %31 = call float @llvm.SI.load.const(<16 x i8> %11, i32 76)
  %32 = call float @llvm.SI.load.const(<16 x i8> %11, i32 80)
  %33 = call float @llvm.SI.load.const(<16 x i8> %11, i32 84)
  %34 = call float @llvm.SI.load.const(<16 x i8> %11, i32 88)
  %35 = call float @llvm.SI.load.const(<16 x i8> %11, i32 92)
  %36 = call float @llvm.SI.load.const(<16 x i8> %11, i32 96)
  %37 = call float @llvm.SI.load.const(<16 x i8> %11, i32 100)
  %38 = call float @llvm.SI.load.const(<16 x i8> %11, i32 104)
  %39 = call float @llvm.SI.load.const(<16 x i8> %11, i32 108)
  %40 = call float @llvm.SI.load.const(<16 x i8> %11, i32 112)
  %41 = call float @llvm.SI.load.const(<16 x i8> %11, i32 116)
  %42 = call float @llvm.SI.load.const(<16 x i8> %11, i32 120)
  %43 = call float @llvm.SI.load.const(<16 x i8> %11, i32 124)
  %44 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0
  %45 = load <16 x i8> addrspace(2)* %44, !tbaa !0
  %46 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %45, i32 0, i32 %6)
  %47 = extractelement <4 x float> %46, i32 0
  %48 = extractelement <4 x float> %46, i32 1
  %49 = extractelement <4 x float> %46, i32 2
  %50 = extractelement <4 x float> %46, i32 3
  %51 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 1
  %52 = load <16 x i8> addrspace(2)* %51, !tbaa !0
  %53 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %52, i32 0, i32 %6)
  %54 = extractelement <4 x float> %53, i32 0
  %55 = extractelement <4 x float> %53, i32 1
  %56 = extractelement <4 x float> %53, i32 2
  %57 = extractelement <4 x float> %53, i32 3
  %58 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 2
  %59 = load <16 x i8> addrspace(2)* %58, !tbaa !0
  %60 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %59, i32 0, i32 %6)
  %61 = extractelement <4 x float> %60, i32 0
  %62 = extractelement <4 x float> %60, i32 1
  %63 = extractelement <4 x float> %60, i32 2
  %64 = extractelement <4 x float> %60, i32 3
  %65 = fmul float %47, %12
  %66 = fmul float %47, %13
  %67 = fmul float %47, %14
  %68 = fmul float %47, %15
  %69 = fmul float %48, %16
  %70 = fadd float %69, %65
  %71 = fmul float %48, %17
  %72 = fadd float %71, %66
  %73 = fmul float %48, %18
  %74 = fadd float %73, %67
  %75 = fmul float %48, %19
  %76 = fadd float %75, %68
  %77 = fmul float %49, %20
  %78 = fadd float %77, %70
  %79 = fmul float %49, %21
  %80 = fadd float %79, %72
  %81 = fmul float %49, %22
  %82 = fadd float %81, %74
  %83 = fmul float %49, %23
  %84 = fadd float %83, %76
  %85 = fmul float %50, %24
  %86 = fadd float %85, %78
  %87 = fmul float %50, %25
  %88 = fadd float %87, %80
  %89 = fmul float %50, %26
  %90 = fadd float %89, %82
  %91 = fmul float %50, %27
  %92 = fadd float %91, %84
  %93 = fmul float %61, %28
  %94 = fmul float %61, %29
  %95 = fmul float %61, %30
  %96 = fmul float %61, %31
  %97 = fmul float %62, %32
  %98 = fadd float %97, %93
  %99 = fmul float %62, %33
  %100 = fadd float %99, %94
  %101 = fmul float %62, %34
  %102 = fadd float %101, %95
  %103 = fmul float %62, %35
  %104 = fadd float %103, %96
  %105 = fmul float %63, %36
  %106 = fadd float %105, %98
  %107 = fmul float %63, %37
  %108 = fadd float %107, %100
  %109 = fmul float %63, %38
  %110 = fadd float %109, %102
  %111 = fmul float %63, %39
  %112 = fadd float %111, %104
  %113 = fmul float %64, %40
  %114 = fadd float %113, %106
  %115 = fmul float %64, %41
  %116 = fadd float %115, %108
  %117 = fmul float %64, %42
  %118 = fadd float %117, %110
  %119 = fmul float %64, %43
  %120 = fadd float %119, %112
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %54, float %55, float %56, float %57)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %114, float %116, float %118, float %120)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %86, float %88, float %90, float %92)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg6

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%56](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%VGPR1_VGPR2_VGPR3_VGPR4<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	EXP 15, 32, 0, 0, 0, %VGPR1, %VGPR2, %VGPR3, %VGPR4, %EXEC<imp-use>, %VGPR1_VGPR2_VGPR3_VGPR4<imp-use,kill>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 8; mem:LD16[%65](align=8)(tbaa=!"const")
	S_WAITCNT 15
	%VGPR1_VGPR2_VGPR3_VGPR4<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%11](align=8)(tbaa=!"const")
	S_WAITCNT 112
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 19; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MUL_F32_e64 %VGPR1, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 23; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR2, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 27; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR3, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 31; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR4, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 18; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e64 %VGPR1, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 22; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR2, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 26; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR3, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 30; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR4, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 17; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MUL_F32_e64 %VGPR1, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 21; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR8<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR2, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 25; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR8<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR3, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 29; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR8<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR4, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 16; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR8<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_F32_e64 %VGPR1, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 20; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR9<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_MAD_F32 %VGPR2, %VGPR9<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 24; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR9<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_MAD_F32 %VGPR3, %VGPR9<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 28; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR9<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_MAD_F32 %VGPR4, %VGPR9<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR1_VGPR2_VGPR3_VGPR4<imp-use,kill>
	EXP 15, 33, 0, 0, 0, %VGPR1<kill>, %VGPR7<kill>, %VGPR6<kill>, %VGPR5<kill>, %EXEC<imp-use>
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%47](align=8)(tbaa=!"const")
	S_WAITCNT 15
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 3; mem:LD4[<unknown>]
	S_WAITCNT 112
	%VGPR4<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e64 %VGPR0, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 7; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR1, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 11; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR2, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 15; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR3, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MUL_F32_e64 %VGPR0, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 6; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR1, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 10; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR2, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 14; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR3, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e64 %VGPR0, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 5; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR1, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 9; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR2, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 13; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR3, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 0; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MUL_F32_e64 %VGPR0, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 4; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR8<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR1, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 8; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR8<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR2, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 12; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR8<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR3, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	EXP 15, 12, 0, 1, 0, %VGPR0<kill>, %VGPR6<kill>, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_LOAD_DWORDX4 s[8:11], s[6:7], 4               ; C0840704
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	BUFFER_LOAD_FORMAT_XYZW v[1:4], s[8:11][v0] + 0 ; E00C2000 80020100
	S_WAITCNT vmcnt(0)                              ; BF8C0770
	EXP 15, 32, 0, 0, 0, v1, v2, v3, v4             ; F800020F 04030201
	S_LOAD_DWORDX4 s[8:11], s[6:7], 8               ; C0840708
	S_WAITCNT expcnt(0) lgkmcnt(0)                  ; BF8C000F
	BUFFER_LOAD_FORMAT_XYZW v[1:4], s[8:11][v0] + 0 ; E00C2000 80020100
	S_LOAD_DWORDX4 s[0:3], s[0:1], 0                ; C0800100
	S_WAITCNT vmcnt(0) lgkmcnt(0)                   ; BF8C0070
	S_BUFFER_LOAD_DWORD s4, s[0:3], 19              ; C2020113
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v5, s4                            ; 7E0A0204
	V_MUL_F32_e64 v5, v1, v5, 0, 0, 0, 0            ; D2100005 02020B01
	S_BUFFER_LOAD_DWORD s4, s[0:3], 23              ; C2020117
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v6, s4                            ; 7E0C0204
	V_MAD_F32 v5, v2, v6, v5, 0, 0, 0, 0            ; D2820005 04160D02
	S_BUFFER_LOAD_DWORD s4, s[0:3], 27              ; C202011B
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v6, s4                            ; 7E0C0204
	V_MAD_F32 v5, v3, v6, v5, 0, 0, 0, 0            ; D2820005 04160D03
	S_BUFFER_LOAD_DWORD s4, s[0:3], 31              ; C202011F
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v6, s4                            ; 7E0C0204
	V_MAD_F32 v5, v4, v6, v5, 0, 0, 0, 0            ; D2820005 04160D04
	S_BUFFER_LOAD_DWORD s4, s[0:3], 18              ; C2020112
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v6, s4                            ; 7E0C0204
	V_MUL_F32_e64 v6, v1, v6, 0, 0, 0, 0            ; D2100006 02020D01
	S_BUFFER_LOAD_DWORD s4, s[0:3], 22              ; C2020116
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v7, s4                            ; 7E0E0204
	V_MAD_F32 v6, v2, v7, v6, 0, 0, 0, 0            ; D2820006 041A0F02
	S_BUFFER_LOAD_DWORD s4, s[0:3], 26              ; C202011A
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v7, s4                            ; 7E0E0204
	V_MAD_F32 v6, v3, v7, v6, 0, 0, 0, 0            ; D2820006 041A0F03
	S_BUFFER_LOAD_DWORD s4, s[0:3], 30              ; C202011E
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v7, s4                            ; 7E0E0204
	V_MAD_F32 v6, v4, v7, v6, 0, 0, 0, 0            ; D2820006 041A0F04
	S_BUFFER_LOAD_DWORD s4, s[0:3], 17              ; C2020111
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v7, s4                            ; 7E0E0204
	V_MUL_F32_e64 v7, v1, v7, 0, 0, 0, 0            ; D2100007 02020F01
	S_BUFFER_LOAD_DWORD s4, s[0:3], 21              ; C2020115
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v8, s4                            ; 7E100204
	V_MAD_F32 v7, v2, v8, v7, 0, 0, 0, 0            ; D2820007 041E1102
	S_BUFFER_LOAD_DWORD s4, s[0:3], 25              ; C2020119
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v8, s4                            ; 7E100204
	V_MAD_F32 v7, v3, v8, v7, 0, 0, 0, 0            ; D2820007 041E1103
	S_BUFFER_LOAD_DWORD s4, s[0:3], 29              ; C202011D
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v8, s4                            ; 7E100204
	V_MAD_F32 v7, v4, v8, v7, 0, 0, 0, 0            ; D2820007 041E1104
	S_BUFFER_LOAD_DWORD s4, s[0:3], 16              ; C2020110
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v8, s4                            ; 7E100204
	V_MUL_F32_e64 v8, v1, v8, 0, 0, 0, 0            ; D2100008 02021101
	S_BUFFER_LOAD_DWORD s4, s[0:3], 20              ; C2020114
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v9, s4                            ; 7E120204
	V_MAD_F32 v8, v2, v9, v8, 0, 0, 0, 0            ; D2820008 04221302
	S_BUFFER_LOAD_DWORD s4, s[0:3], 24              ; C2020118
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v9, s4                            ; 7E120204
	V_MAD_F32 v8, v3, v9, v8, 0, 0, 0, 0            ; D2820008 04221303
	S_BUFFER_LOAD_DWORD s4, s[0:3], 28              ; C202011C
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v9, s4                            ; 7E120204
	V_MAD_F32 v1, v4, v9, v8, 0, 0, 0, 0            ; D2820001 04221304
	EXP 15, 33, 0, 0, 0, v1, v7, v6, v5             ; F800021F 05060701
	S_LOAD_DWORDX4 s[4:7], s[6:7], 0                ; C0820700
	S_WAITCNT expcnt(0) lgkmcnt(0)                  ; BF8C000F
	BUFFER_LOAD_FORMAT_XYZW v[0:3], s[4:7][v0] + 0  ; E00C2000 80010000
	S_BUFFER_LOAD_DWORD s4, s[0:3], 3               ; C2020103
	S_WAITCNT vmcnt(0) lgkmcnt(0)                   ; BF8C0070
	V_MOV_B32_e32 v4, s4                            ; 7E080204
	V_MUL_F32_e64 v4, v0, v4, 0, 0, 0, 0            ; D2100004 02020900
	S_BUFFER_LOAD_DWORD s4, s[0:3], 7               ; C2020107
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v5, s4                            ; 7E0A0204
	V_MAD_F32 v4, v1, v5, v4, 0, 0, 0, 0            ; D2820004 04120B01
	S_BUFFER_LOAD_DWORD s4, s[0:3], 11              ; C202010B
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v5, s4                            ; 7E0A0204
	V_MAD_F32 v4, v2, v5, v4, 0, 0, 0, 0            ; D2820004 04120B02
	S_BUFFER_LOAD_DWORD s4, s[0:3], 15              ; C202010F
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v5, s4                            ; 7E0A0204
	V_MAD_F32 v4, v3, v5, v4, 0, 0, 0, 0            ; D2820004 04120B03
	S_BUFFER_LOAD_DWORD s4, s[0:3], 2               ; C2020102
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v5, s4                            ; 7E0A0204
	V_MUL_F32_e64 v5, v0, v5, 0, 0, 0, 0            ; D2100005 02020B00
	S_BUFFER_LOAD_DWORD s4, s[0:3], 6               ; C2020106
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v6, s4                            ; 7E0C0204
	V_MAD_F32 v5, v1, v6, v5, 0, 0, 0, 0            ; D2820005 04160D01
	S_BUFFER_LOAD_DWORD s4, s[0:3], 10              ; C202010A
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v6, s4                            ; 7E0C0204
	V_MAD_F32 v5, v2, v6, v5, 0, 0, 0, 0            ; D2820005 04160D02
	S_BUFFER_LOAD_DWORD s4, s[0:3], 14              ; C202010E
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v6, s4                            ; 7E0C0204
	V_MAD_F32 v5, v3, v6, v5, 0, 0, 0, 0            ; D2820005 04160D03
	S_BUFFER_LOAD_DWORD s4, s[0:3], 1               ; C2020101
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v6, s4                            ; 7E0C0204
	V_MUL_F32_e64 v6, v0, v6, 0, 0, 0, 0            ; D2100006 02020D00
	S_BUFFER_LOAD_DWORD s4, s[0:3], 5               ; C2020105
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v7, s4                            ; 7E0E0204
	V_MAD_F32 v6, v1, v7, v6, 0, 0, 0, 0            ; D2820006 041A0F01
	S_BUFFER_LOAD_DWORD s4, s[0:3], 9               ; C2020109
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v7, s4                            ; 7E0E0204
	V_MAD_F32 v6, v2, v7, v6, 0, 0, 0, 0            ; D2820006 041A0F02
	S_BUFFER_LOAD_DWORD s4, s[0:3], 13              ; C202010D
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v7, s4                            ; 7E0E0204
	V_MAD_F32 v6, v3, v7, v6, 0, 0, 0, 0            ; D2820006 041A0F03
	S_BUFFER_LOAD_DWORD s4, s[0:3], 0               ; C2020100
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v7, s4                            ; 7E0E0204
	V_MUL_F32_e64 v7, v0, v7, 0, 0, 0, 0            ; D2100007 02020F00
	S_BUFFER_LOAD_DWORD s4, s[0:3], 4               ; C2020104
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v8, s4                            ; 7E100204
	V_MAD_F32 v7, v1, v8, v7, 0, 0, 0, 0            ; D2820007 041E1101
	S_BUFFER_LOAD_DWORD s4, s[0:3], 8               ; C2020108
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v8, s4                            ; 7E100204
	V_MAD_F32 v7, v2, v8, v7, 0, 0, 0, 0            ; D2820007 041E1102
	S_BUFFER_LOAD_DWORD s0, s[0:3], 12              ; C200010C
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v8, s0                            ; 7E100200
	V_MAD_F32 v0, v3, v8, v7, 0, 0, 0, 0            ; D2820000 041E1103
	EXP 15, 12, 0, 1, 0, v0, v6, v5, v4             ; F80008CF 04050600
	S_ENDPGM                                        ; BF810000

FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[0], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL CONST[1..4]
DCL TEMP[0], LOCAL
  0: MOV TEMP[0].xy, IN[0].xyyy
  1: MOV TEMP[0].w, IN[0].wwww
  2: TXP TEMP[0], TEMP[0], SAMP[0], 2D
  3: MUL TEMP[0], TEMP[0], CONST[4]
  4: MOV OUT[0], TEMP[0]
  5: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %21 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
  %22 = load <16 x i8> addrspace(2)* %21, !tbaa !0
  %23 = call float @llvm.SI.load.const(<16 x i8> %22, i32 64)
  %24 = call float @llvm.SI.load.const(<16 x i8> %22, i32 68)
  %25 = call float @llvm.SI.load.const(<16 x i8> %22, i32 72)
  %26 = call float @llvm.SI.load.const(<16 x i8> %22, i32 76)
  %27 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0
  %28 = load <32 x i8> addrspace(2)* %27, !tbaa !0
  %29 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0
  %30 = load <16 x i8> addrspace(2)* %29, !tbaa !0
  %31 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %4, <2 x i32> %6)
  %32 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %4, <2 x i32> %6)
  %33 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %4, <2 x i32> %6)
  %34 = fdiv float %31, %33
  %35 = fdiv float %32, %33
  %36 = bitcast float %34 to i32
  %37 = bitcast float %35 to i32
  %38 = insertelement <2 x i32> undef, i32 %36, i32 0
  %39 = insertelement <2 x i32> %38, i32 %37, i32 1
  %40 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %39, <32 x i8> %28, <16 x i8> %30, i32 2)
  %41 = extractelement <4 x float> %40, i32 0
  %42 = extractelement <4 x float> %40, i32 1
  %43 = extractelement <4 x float> %40, i32 2
  %44 = extractelement <4 x float> %40, i32 3
  %45 = fmul float %41, %23
  %46 = fmul float %42, %24
  %47 = fmul float %43, %25
  %48 = fmul float %44, %26
  %49 = call i32 @llvm.SI.packf16(float %45, float %46)
  %50 = bitcast i32 %49 to float
  %51 = call i32 @llvm.SI.packf16(float %47, float %48)
  %52 = bitcast i32 %51 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %50, float %52, float %50, float %52)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR7 in %vreg4, %VGPR0 in %vreg5, %VGPR1 in %vreg6

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR7 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR7
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<kill,tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<kill,tied0>, %VGPR1, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_RCP_F32_e32 %VGPR3<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MUL_F32_e32 %VGPR2<kill>, %VGPR3, %EXEC<imp-use>, %VGPR4_VGPR5<imp-def>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<kill,tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>
	%VGPR4<def> = V_MUL_F32_e32 %VGPR2<kill>, %VGPR3<kill>, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%32](align=8)(tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%29](tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = IMAGE_SAMPLE_V4_V2 15, 0, 0, 0, 0, 0, 0, 0, %VGPR4_VGPR5<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%22](align=8)(tbaa=!"const")
	S_WAITCNT 112
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 19; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR4<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e64 %VGPR3, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 18; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MUL_F32_e64 %VGPR2, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 17; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MUL_F32_e64 %VGPR1, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 16; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_F32_e64 %VGPR0, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0<kill>, %VGPR5<kill>, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR0<kill>, %VGPR4<kill>, %VGPR0, %VGPR4, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_WQM_B64 exec, exec                                                    ; BEFE0A7E
	S_MOV_B32 m0, s7                                                        ; BEFC0307
	V_INTERP_P1_F32 v2, v0, 1, 0, [m0]                                      ; C8080100
	V_INTERP_P2_F32 v2, [v2], v1, 1, 0, [m0]                                ; C8090101
	V_INTERP_P1_F32 v3, v0, 3, 0, [m0]                                      ; C80C0300
	V_INTERP_P2_F32 v3, [v3], v1, 3, 0, [m0]                                ; C80D0301
	V_RCP_F32_e32 v3, v3                                                    ; 7E065503
	V_MUL_F32_e32 v5, v2, v3                                                ; 100A0702
	V_INTERP_P1_F32 v2, v0, 0, 0, [m0]                                      ; C8080000
	V_INTERP_P2_F32 v2, [v2], v1, 0, 0, [m0]                                ; C8090001
	V_MUL_F32_e32 v4, v2, v3                                                ; 10080702
	S_LOAD_DWORDX4 s[8:11], s[2:3], 0                                       ; C0840300
	S_LOAD_DWORDX8 s[12:19], s[4:5], 0                                      ; C0C60500
	S_WAITCNT lgkmcnt(0)                                                    ; BF8C007F
	IMAGE_SAMPLE v[0:3], 15, 0, 0, 0, 0, 0, 0, 0, v[4:5], s[12:19], s[8:11] ; F0800F00 00430004
	S_LOAD_DWORDX4 s[0:3], s[0:1], 0                                        ; C0800100
	S_WAITCNT vmcnt(0) lgkmcnt(0)                                           ; BF8C0070
	S_BUFFER_LOAD_DWORD s4, s[0:3], 19                                      ; C2020113
	S_WAITCNT lgkmcnt(0)                                                    ; BF8C007F
	V_MOV_B32_e32 v4, s4                                                    ; 7E080204
	V_MUL_F32_e64 v4, v3, v4, 0, 0, 0, 0                                    ; D2100004 02020903
	S_BUFFER_LOAD_DWORD s4, s[0:3], 18                                      ; C2020112
	S_WAITCNT lgkmcnt(0)                                                    ; BF8C007F
	V_MOV_B32_e32 v5, s4                                                    ; 7E0A0204
	V_MUL_F32_e64 v5, v2, v5, 0, 0, 0, 0                                    ; D2100005 02020B02
	V_CVT_PKRTZ_F16_F32_e32 v4, v5, v4                                      ; 5E080905
	S_BUFFER_LOAD_DWORD s4, s[0:3], 17                                      ; C2020111
	S_WAITCNT lgkmcnt(0)                                                    ; BF8C007F
	V_MOV_B32_e32 v5, s4                                                    ; 7E0A0204
	V_MUL_F32_e64 v5, v1, v5, 0, 0, 0, 0                                    ; D2100005 02020B01
	S_BUFFER_LOAD_DWORD s0, s[0:3], 16                                      ; C2000110
	S_WAITCNT lgkmcnt(0)                                                    ; BF8C007F
	V_MOV_B32_e32 v6, s0                                                    ; 7E0C0200
	V_MUL_F32_e64 v0, v0, v6, 0, 0, 0, 0                                    ; D2100000 02020D00
	V_CVT_PKRTZ_F16_F32_e32 v0, v0, v5                                      ; 5E000B00
	EXP 15, 0, 1, 1, 1, v0, v4, v0, v4                                      ; F8001C0F 04000400
	S_ENDPGM                                                                ; BF810000

VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[0]
DCL CONST[0..7]
DCL TEMP[0]
  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
  4: MUL TEMP[0], IN[1].xxxx, CONST[4]
  5: MAD TEMP[0], IN[1].yyyy, CONST[5], TEMP[0]
  6: MAD TEMP[0], IN[1].zzzz, CONST[6], TEMP[0]
  7: MAD OUT[1], IN[1].wwww, CONST[7], TEMP[0]
  8: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0)
  %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4)
  %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8)
  %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12)
  %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16)
  %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20)
  %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24)
  %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28)
  %20 = call float @llvm.SI.load.const(<16 x i8> %11, i32 32)
  %21 = call float @llvm.SI.load.const(<16 x i8> %11, i32 36)
  %22 = call float @llvm.SI.load.const(<16 x i8> %11, i32 40)
  %23 = call float @llvm.SI.load.const(<16 x i8> %11, i32 44)
  %24 = call float @llvm.SI.load.const(<16 x i8> %11, i32 48)
  %25 = call float @llvm.SI.load.const(<16 x i8> %11, i32 52)
  %26 = call float @llvm.SI.load.const(<16 x i8> %11, i32 56)
  %27 = call float @llvm.SI.load.const(<16 x i8> %11, i32 60)
  %28 = call float @llvm.SI.load.const(<16 x i8> %11, i32 64)
  %29 = call float @llvm.SI.load.const(<16 x i8> %11, i32 68)
  %30 = call float @llvm.SI.load.const(<16 x i8> %11, i32 72)
  %31 = call float @llvm.SI.load.const(<16 x i8> %11, i32 76)
  %32 = call float @llvm.SI.load.const(<16 x i8> %11, i32 80)
  %33 = call float @llvm.SI.load.const(<16 x i8> %11, i32 84)
  %34 = call float @llvm.SI.load.const(<16 x i8> %11, i32 88)
  %35 = call float @llvm.SI.load.const(<16 x i8> %11, i32 92)
  %36 = call float @llvm.SI.load.const(<16 x i8> %11, i32 96)
  %37 = call float @llvm.SI.load.const(<16 x i8> %11, i32 100)
  %38 = call float @llvm.SI.load.const(<16 x i8> %11, i32 104)
  %39 = call float @llvm.SI.load.const(<16 x i8> %11, i32 108)
  %40 = call float @llvm.SI.load.const(<16 x i8> %11, i32 112)
  %41 = call float @llvm.SI.load.const(<16 x i8> %11, i32 116)
  %42 = call float @llvm.SI.load.const(<16 x i8> %11, i32 120)
  %43 = call float @llvm.SI.load.const(<16 x i8> %11, i32 124)
  %44 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0
  %45 = load <16 x i8> addrspace(2)* %44, !tbaa !0
  %46 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %45, i32 0, i32 %6)
  %47 = extractelement <4 x float> %46, i32 0
  %48 = extractelement <4 x float> %46, i32 1
  %49 = extractelement <4 x float> %46, i32 2
  %50 = extractelement <4 x float> %46, i32 3
  %51 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 1
  %52 = load <16 x i8> addrspace(2)* %51, !tbaa !0
  %53 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %52, i32 0, i32 %6)
  %54 = extractelement <4 x float> %53, i32 0
  %55 = extractelement <4 x float> %53, i32 1
  %56 = extractelement <4 x float> %53, i32 2
  %57 = extractelement <4 x float> %53, i32 3
  %58 = fmul float %47, %12
  %59 = fmul float %47, %13
  %60 = fmul float %47, %14
  %61 = fmul float %47, %15
  %62 = fmul float %48, %16
  %63 = fadd float %62, %58
  %64 = fmul float %48, %17
  %65 = fadd float %64, %59
  %66 = fmul float %48, %18
  %67 = fadd float %66, %60
  %68 = fmul float %48, %19
  %69 = fadd float %68, %61
  %70 = fmul float %49, %20
  %71 = fadd float %70, %63
  %72 = fmul float %49, %21
  %73 = fadd float %72, %65
  %74 = fmul float %49, %22
  %75 = fadd float %74, %67
  %76 = fmul float %49, %23
  %77 = fadd float %76, %69
  %78 = fmul float %50, %24
  %79 = fadd float %78, %71
  %80 = fmul float %50, %25
  %81 = fadd float %80, %73
  %82 = fmul float %50, %26
  %83 = fadd float %82, %75
  %84 = fmul float %50, %27
  %85 = fadd float %84, %77
  %86 = fmul float %54, %28
  %87 = fmul float %54, %29
  %88 = fmul float %54, %30
  %89 = fmul float %54, %31
  %90 = fmul float %55, %32
  %91 = fadd float %90, %86
  %92 = fmul float %55, %33
  %93 = fadd float %92, %87
  %94 = fmul float %55, %34
  %95 = fadd float %94, %88
  %96 = fmul float %55, %35
  %97 = fadd float %96, %89
  %98 = fmul float %56, %36
  %99 = fadd float %98, %91
  %100 = fmul float %56, %37
  %101 = fadd float %100, %93
  %102 = fmul float %56, %38
  %103 = fadd float %102, %95
  %104 = fmul float %56, %39
  %105 = fadd float %104, %97
  %106 = fmul float %57, %40
  %107 = fadd float %106, %99
  %108 = fmul float %57, %41
  %109 = fadd float %108, %101
  %110 = fmul float %57, %42
  %111 = fadd float %110, %103
  %112 = fmul float %57, %43
  %113 = fadd float %112, %105
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %107, float %109, float %111, float %113)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %79, float %81, float %83, float %85)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg6

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%56](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%VGPR1_VGPR2_VGPR3_VGPR4<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%11](align=8)(tbaa=!"const")
	S_WAITCNT 112
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 19; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MUL_F32_e64 %VGPR1, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 23; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR2, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 27; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR3, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 31; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR4, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 18; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e64 %VGPR1, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 22; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR2, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 26; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR3, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 30; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR4, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 17; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MUL_F32_e64 %VGPR1, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 21; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR8<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR2, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 25; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR8<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR3, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 29; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR8<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR4, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 16; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR8<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_F32_e64 %VGPR1, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 20; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR9<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_MAD_F32 %VGPR2, %VGPR9<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 24; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR9<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_MAD_F32 %VGPR3, %VGPR9<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 28; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR9<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_MAD_F32 %VGPR4, %VGPR9<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR1_VGPR2_VGPR3_VGPR4<imp-use,kill>
	EXP 15, 32, 0, 0, 0, %VGPR1<kill>, %VGPR7<kill>, %VGPR6<kill>, %VGPR5<kill>, %EXEC<imp-use>
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%47](align=8)(tbaa=!"const")
	S_WAITCNT 15
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 3; mem:LD4[<unknown>]
	S_WAITCNT 112
	%VGPR4<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e64 %VGPR0, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 7; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR1, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 11; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR2, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 15; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR3, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MUL_F32_e64 %VGPR0, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 6; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR1, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 10; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR2, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 14; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR3, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e64 %VGPR0, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 5; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR1, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 9; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR2, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 13; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR3, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 0; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MUL_F32_e64 %VGPR0, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 4; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR8<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR1, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 8; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR8<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR2, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 12; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR8<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR3, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	EXP 15, 12, 0, 1, 0, %VGPR0<kill>, %VGPR6<kill>, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_LOAD_DWORDX4 s[8:11], s[6:7], 4               ; C0840704
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	BUFFER_LOAD_FORMAT_XYZW v[1:4], s[8:11][v0] + 0 ; E00C2000 80020100
	S_LOAD_DWORDX4 s[0:3], s[0:1], 0                ; C0800100
	S_WAITCNT vmcnt(0) lgkmcnt(0)                   ; BF8C0070
	S_BUFFER_LOAD_DWORD s4, s[0:3], 19              ; C2020113
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v5, s4                            ; 7E0A0204
	V_MUL_F32_e64 v5, v1, v5, 0, 0, 0, 0            ; D2100005 02020B01
	S_BUFFER_LOAD_DWORD s4, s[0:3], 23              ; C2020117
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v6, s4                            ; 7E0C0204
	V_MAD_F32 v5, v2, v6, v5, 0, 0, 0, 0            ; D2820005 04160D02
	S_BUFFER_LOAD_DWORD s4, s[0:3], 27              ; C202011B
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v6, s4                            ; 7E0C0204
	V_MAD_F32 v5, v3, v6, v5, 0, 0, 0, 0            ; D2820005 04160D03
	S_BUFFER_LOAD_DWORD s4, s[0:3], 31              ; C202011F
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v6, s4                            ; 7E0C0204
	V_MAD_F32 v5, v4, v6, v5, 0, 0, 0, 0            ; D2820005 04160D04
	S_BUFFER_LOAD_DWORD s4, s[0:3], 18              ; C2020112
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v6, s4                            ; 7E0C0204
	V_MUL_F32_e64 v6, v1, v6, 0, 0, 0, 0            ; D2100006 02020D01
	S_BUFFER_LOAD_DWORD s4, s[0:3], 22              ; C2020116
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v7, s4                            ; 7E0E0204
	V_MAD_F32 v6, v2, v7, v6, 0, 0, 0, 0            ; D2820006 041A0F02
	S_BUFFER_LOAD_DWORD s4, s[0:3], 26              ; C202011A
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v7, s4                            ; 7E0E0204
	V_MAD_F32 v6, v3, v7, v6, 0, 0, 0, 0            ; D2820006 041A0F03
	S_BUFFER_LOAD_DWORD s4, s[0:3], 30              ; C202011E
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v7, s4                            ; 7E0E0204
	V_MAD_F32 v6, v4, v7, v6, 0, 0, 0, 0            ; D2820006 041A0F04
	S_BUFFER_LOAD_DWORD s4, s[0:3], 17              ; C2020111
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v7, s4                            ; 7E0E0204
	V_MUL_F32_e64 v7, v1, v7, 0, 0, 0, 0            ; D2100007 02020F01
	S_BUFFER_LOAD_DWORD s4, s[0:3], 21              ; C2020115
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v8, s4                            ; 7E100204
	V_MAD_F32 v7, v2, v8, v7, 0, 0, 0, 0            ; D2820007 041E1102
	S_BUFFER_LOAD_DWORD s4, s[0:3], 25              ; C2020119
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v8, s4                            ; 7E100204
	V_MAD_F32 v7, v3, v8, v7, 0, 0, 0, 0            ; D2820007 041E1103
	S_BUFFER_LOAD_DWORD s4, s[0:3], 29              ; C202011D
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v8, s4                            ; 7E100204
	V_MAD_F32 v7, v4, v8, v7, 0, 0, 0, 0            ; D2820007 041E1104
	S_BUFFER_LOAD_DWORD s4, s[0:3], 16              ; C2020110
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v8, s4                            ; 7E100204
	V_MUL_F32_e64 v8, v1, v8, 0, 0, 0, 0            ; D2100008 02021101
	S_BUFFER_LOAD_DWORD s4, s[0:3], 20              ; C2020114
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v9, s4                            ; 7E120204
	V_MAD_F32 v8, v2, v9, v8, 0, 0, 0, 0            ; D2820008 04221302
	S_BUFFER_LOAD_DWORD s4, s[0:3], 24              ; C2020118
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v9, s4                            ; 7E120204
	V_MAD_F32 v8, v3, v9, v8, 0, 0, 0, 0            ; D2820008 04221303
	S_BUFFER_LOAD_DWORD s4, s[0:3], 28              ; C202011C
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v9, s4                            ; 7E120204
	V_MAD_F32 v1, v4, v9, v8, 0, 0, 0, 0            ; D2820001 04221304
	EXP 15, 32, 0, 0, 0, v1, v7, v6, v5             ; F800020F 05060701
	S_LOAD_DWORDX4 s[4:7], s[6:7], 0                ; C0820700
	S_WAITCNT expcnt(0) lgkmcnt(0)                  ; BF8C000F
	BUFFER_LOAD_FORMAT_XYZW v[0:3], s[4:7][v0] + 0  ; E00C2000 80010000
	S_BUFFER_LOAD_DWORD s4, s[0:3], 3               ; C2020103
	S_WAITCNT vmcnt(0) lgkmcnt(0)                   ; BF8C0070
	V_MOV_B32_e32 v4, s4                            ; 7E080204
	V_MUL_F32_e64 v4, v0, v4, 0, 0, 0, 0            ; D2100004 02020900
	S_BUFFER_LOAD_DWORD s4, s[0:3], 7               ; C2020107
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v5, s4                            ; 7E0A0204
	V_MAD_F32 v4, v1, v5, v4, 0, 0, 0, 0            ; D2820004 04120B01
	S_BUFFER_LOAD_DWORD s4, s[0:3], 11              ; C202010B
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v5, s4                            ; 7E0A0204
	V_MAD_F32 v4, v2, v5, v4, 0, 0, 0, 0            ; D2820004 04120B02
	S_BUFFER_LOAD_DWORD s4, s[0:3], 15              ; C202010F
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v5, s4                            ; 7E0A0204
	V_MAD_F32 v4, v3, v5, v4, 0, 0, 0, 0            ; D2820004 04120B03
	S_BUFFER_LOAD_DWORD s4, s[0:3], 2               ; C2020102
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v5, s4                            ; 7E0A0204
	V_MUL_F32_e64 v5, v0, v5, 0, 0, 0, 0            ; D2100005 02020B00
	S_BUFFER_LOAD_DWORD s4, s[0:3], 6               ; C2020106
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v6, s4                            ; 7E0C0204
	V_MAD_F32 v5, v1, v6, v5, 0, 0, 0, 0            ; D2820005 04160D01
	S_BUFFER_LOAD_DWORD s4, s[0:3], 10              ; C202010A
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v6, s4                            ; 7E0C0204
	V_MAD_F32 v5, v2, v6, v5, 0, 0, 0, 0            ; D2820005 04160D02
	S_BUFFER_LOAD_DWORD s4, s[0:3], 14              ; C202010E
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v6, s4                            ; 7E0C0204
	V_MAD_F32 v5, v3, v6, v5, 0, 0, 0, 0            ; D2820005 04160D03
	S_BUFFER_LOAD_DWORD s4, s[0:3], 1               ; C2020101
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v6, s4                            ; 7E0C0204
	V_MUL_F32_e64 v6, v0, v6, 0, 0, 0, 0            ; D2100006 02020D00
	S_BUFFER_LOAD_DWORD s4, s[0:3], 5               ; C2020105
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v7, s4                            ; 7E0E0204
	V_MAD_F32 v6, v1, v7, v6, 0, 0, 0, 0            ; D2820006 041A0F01
	S_BUFFER_LOAD_DWORD s4, s[0:3], 9               ; C2020109
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v7, s4                            ; 7E0E0204
	V_MAD_F32 v6, v2, v7, v6, 0, 0, 0, 0            ; D2820006 041A0F02
	S_BUFFER_LOAD_DWORD s4, s[0:3], 13              ; C202010D
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v7, s4                            ; 7E0E0204
	V_MAD_F32 v6, v3, v7, v6, 0, 0, 0, 0            ; D2820006 041A0F03
	S_BUFFER_LOAD_DWORD s4, s[0:3], 0               ; C2020100
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v7, s4                            ; 7E0E0204
	V_MUL_F32_e64 v7, v0, v7, 0, 0, 0, 0            ; D2100007 02020F00
	S_BUFFER_LOAD_DWORD s4, s[0:3], 4               ; C2020104
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v8, s4                            ; 7E100204
	V_MAD_F32 v7, v1, v8, v7, 0, 0, 0, 0            ; D2820007 041E1101
	S_BUFFER_LOAD_DWORD s4, s[0:3], 8               ; C2020108
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v8, s4                            ; 7E100204
	V_MAD_F32 v7, v2, v8, v7, 0, 0, 0, 0            ; D2820007 041E1102
	S_BUFFER_LOAD_DWORD s0, s[0:3], 12              ; C200010C
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v8, s0                            ; 7E100200
	V_MAD_F32 v0, v3, v8, v7, 0, 0, 0, 0            ; D2820000 041E1103
	EXP 15, 12, 0, 1, 0, v0, v6, v5, v4             ; F80008CF 04050600
	S_ENDPGM                                        ; BF810000

VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], COLOR
DCL CONST[0..3]
DCL TEMP[0]
  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
  4: MOV OUT[1], IN[1]
  5: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0)
  %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4)
  %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8)
  %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12)
  %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16)
  %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20)
  %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24)
  %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28)
  %20 = call float @llvm.SI.load.const(<16 x i8> %11, i32 32)
  %21 = call float @llvm.SI.load.const(<16 x i8> %11, i32 36)
  %22 = call float @llvm.SI.load.const(<16 x i8> %11, i32 40)
  %23 = call float @llvm.SI.load.const(<16 x i8> %11, i32 44)
  %24 = call float @llvm.SI.load.const(<16 x i8> %11, i32 48)
  %25 = call float @llvm.SI.load.const(<16 x i8> %11, i32 52)
  %26 = call float @llvm.SI.load.const(<16 x i8> %11, i32 56)
  %27 = call float @llvm.SI.load.const(<16 x i8> %11, i32 60)
  %28 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0
  %29 = load <16 x i8> addrspace(2)* %28, !tbaa !0
  %30 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %29, i32 0, i32 %6)
  %31 = extractelement <4 x float> %30, i32 0
  %32 = extractelement <4 x float> %30, i32 1
  %33 = extractelement <4 x float> %30, i32 2
  %34 = extractelement <4 x float> %30, i32 3
  %35 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 1
  %36 = load <16 x i8> addrspace(2)* %35, !tbaa !0
  %37 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %36, i32 0, i32 %6)
  %38 = extractelement <4 x float> %37, i32 0
  %39 = extractelement <4 x float> %37, i32 1
  %40 = extractelement <4 x float> %37, i32 2
  %41 = extractelement <4 x float> %37, i32 3
  %42 = fmul float %31, %12
  %43 = fmul float %31, %13
  %44 = fmul float %31, %14
  %45 = fmul float %31, %15
  %46 = fmul float %32, %16
  %47 = fadd float %46, %42
  %48 = fmul float %32, %17
  %49 = fadd float %48, %43
  %50 = fmul float %32, %18
  %51 = fadd float %50, %44
  %52 = fmul float %32, %19
  %53 = fadd float %52, %45
  %54 = fmul float %33, %20
  %55 = fadd float %54, %47
  %56 = fmul float %33, %21
  %57 = fadd float %56, %49
  %58 = fmul float %33, %22
  %59 = fadd float %58, %51
  %60 = fmul float %33, %23
  %61 = fadd float %60, %53
  %62 = fmul float %34, %24
  %63 = fadd float %62, %55
  %64 = fmul float %34, %25
  %65 = fadd float %64, %57
  %66 = fmul float %34, %26
  %67 = fadd float %66, %59
  %68 = fmul float %34, %27
  %69 = fadd float %68, %61
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %38, float %39, float %40, float %41)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %63, float %65, float %67, float %69)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg6

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%40](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%VGPR1_VGPR2_VGPR3_VGPR4<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	EXP 15, 32, 0, 0, 0, %VGPR1, %VGPR2, %VGPR3, %VGPR4, %EXEC<imp-use>, %VGPR1_VGPR2_VGPR3_VGPR4<imp-use,kill>
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%31](align=8)(tbaa=!"const")
	S_WAITCNT 15
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%11](align=8)(tbaa=!"const")
	S_WAITCNT 112
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 3; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR4<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e64 %VGPR0, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 7; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR1, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 11; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR2, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 15; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR3, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MUL_F32_e64 %VGPR0, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 6; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR1, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 10; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR2, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 14; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR3, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e64 %VGPR0, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 5; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR1, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 9; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR2, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 13; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR3, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 0; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MUL_F32_e64 %VGPR0, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 4; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR8<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR1, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 8; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR8<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR2, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 12; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR8<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR3, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	EXP 15, 12, 0, 1, 0, %VGPR0<kill>, %VGPR6<kill>, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_LOAD_DWORDX4 s[8:11], s[6:7], 4               ; C0840704
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	BUFFER_LOAD_FORMAT_XYZW v[1:4], s[8:11][v0] + 0 ; E00C2000 80020100
	S_WAITCNT vmcnt(0)                              ; BF8C0770
	EXP 15, 32, 0, 0, 0, v1, v2, v3, v4             ; F800020F 04030201
	S_LOAD_DWORDX4 s[4:7], s[6:7], 0                ; C0820700
	S_WAITCNT expcnt(0) lgkmcnt(0)                  ; BF8C000F
	BUFFER_LOAD_FORMAT_XYZW v[0:3], s[4:7][v0] + 0  ; E00C2000 80010000
	S_LOAD_DWORDX4 s[0:3], s[0:1], 0                ; C0800100
	S_WAITCNT vmcnt(0) lgkmcnt(0)                   ; BF8C0070
	S_BUFFER_LOAD_DWORD s4, s[0:3], 3               ; C2020103
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v4, s4                            ; 7E080204
	V_MUL_F32_e64 v4, v0, v4, 0, 0, 0, 0            ; D2100004 02020900
	S_BUFFER_LOAD_DWORD s4, s[0:3], 7               ; C2020107
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v5, s4                            ; 7E0A0204
	V_MAD_F32 v4, v1, v5, v4, 0, 0, 0, 0            ; D2820004 04120B01
	S_BUFFER_LOAD_DWORD s4, s[0:3], 11              ; C202010B
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v5, s4                            ; 7E0A0204
	V_MAD_F32 v4, v2, v5, v4, 0, 0, 0, 0            ; D2820004 04120B02
	S_BUFFER_LOAD_DWORD s4, s[0:3], 15              ; C202010F
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v5, s4                            ; 7E0A0204
	V_MAD_F32 v4, v3, v5, v4, 0, 0, 0, 0            ; D2820004 04120B03
	S_BUFFER_LOAD_DWORD s4, s[0:3], 2               ; C2020102
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v5, s4                            ; 7E0A0204
	V_MUL_F32_e64 v5, v0, v5, 0, 0, 0, 0            ; D2100005 02020B00
	S_BUFFER_LOAD_DWORD s4, s[0:3], 6               ; C2020106
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v6, s4                            ; 7E0C0204
	V_MAD_F32 v5, v1, v6, v5, 0, 0, 0, 0            ; D2820005 04160D01
	S_BUFFER_LOAD_DWORD s4, s[0:3], 10              ; C202010A
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v6, s4                            ; 7E0C0204
	V_MAD_F32 v5, v2, v6, v5, 0, 0, 0, 0            ; D2820005 04160D02
	S_BUFFER_LOAD_DWORD s4, s[0:3], 14              ; C202010E
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v6, s4                            ; 7E0C0204
	V_MAD_F32 v5, v3, v6, v5, 0, 0, 0, 0            ; D2820005 04160D03
	S_BUFFER_LOAD_DWORD s4, s[0:3], 1               ; C2020101
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v6, s4                            ; 7E0C0204
	V_MUL_F32_e64 v6, v0, v6, 0, 0, 0, 0            ; D2100006 02020D00
	S_BUFFER_LOAD_DWORD s4, s[0:3], 5               ; C2020105
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v7, s4                            ; 7E0E0204
	V_MAD_F32 v6, v1, v7, v6, 0, 0, 0, 0            ; D2820006 041A0F01
	S_BUFFER_LOAD_DWORD s4, s[0:3], 9               ; C2020109
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v7, s4                            ; 7E0E0204
	V_MAD_F32 v6, v2, v7, v6, 0, 0, 0, 0            ; D2820006 041A0F02
	S_BUFFER_LOAD_DWORD s4, s[0:3], 13              ; C202010D
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v7, s4                            ; 7E0E0204
	V_MAD_F32 v6, v3, v7, v6, 0, 0, 0, 0            ; D2820006 041A0F03
	S_BUFFER_LOAD_DWORD s4, s[0:3], 0               ; C2020100
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v7, s4                            ; 7E0E0204
	V_MUL_F32_e64 v7, v0, v7, 0, 0, 0, 0            ; D2100007 02020F00
	S_BUFFER_LOAD_DWORD s4, s[0:3], 4               ; C2020104
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v8, s4                            ; 7E100204
	V_MAD_F32 v7, v1, v8, v7, 0, 0, 0, 0            ; D2820007 041E1101
	S_BUFFER_LOAD_DWORD s4, s[0:3], 8               ; C2020108
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v8, s4                            ; 7E100204
	V_MAD_F32 v7, v2, v8, v7, 0, 0, 0, 0            ; D2820007 041E1102
	S_BUFFER_LOAD_DWORD s0, s[0:3], 12              ; C200010C
	S_WAITCNT lgkmcnt(0)                            ; BF8C007F
	V_MOV_B32_e32 v8, s0                            ; 7E100200
	V_MAD_F32 v0, v3, v8, v7, 0, 0, 0, 0            ; D2820000 041E1103
	EXP 15, 12, 0, 1, 0, v0, v6, v5, v4             ; F80008CF 04050600
	S_ENDPGM                                        ; BF810000

FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL IN[1], GENERIC[20], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL CONST[0]
DCL TEMP[0..2], LOCAL
IMM[0] FLT32 {   32.0000,   -16.0000,     1.0000,     0.0000}
  0: MOV TEMP[0].xy, IN[1].xyyy
  1: TEX TEMP[0], TEMP[0], SAMP[0], 2D
  2: MAD TEMP[1].x, TEMP[0].wwww, IMM[0].xxxx, IMM[0].yyyy
  3: EX2 TEMP[1].x, TEMP[1].xxxx
  4: MUL TEMP[1].xyz, TEMP[0].xyzz, TEMP[1].xxxx
  5: MOV TEMP[1].w, IMM[0].zzzz
  6: FSGE TEMP[2].x, CONST[0].xxxx, IMM[0].wwww
  7: UIF TEMP[2].xxxx :0
  8:   MOV TEMP[1], TEMP[1]
  9: ELSE :0
 10:   MOV TEMP[1], TEMP[0]
 11: ENDIF
 12: MUL TEMP[0], TEMP[1], IN[0]
 13: MOV OUT[0], TEMP[0]
 14: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %21 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
  %22 = load <16 x i8> addrspace(2)* %21, !tbaa !0
  %23 = call float @llvm.SI.load.const(<16 x i8> %22, i32 0)
  %24 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0
  %25 = load <32 x i8> addrspace(2)* %24, !tbaa !0
  %26 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0
  %27 = load <16 x i8> addrspace(2)* %26, !tbaa !0
  %28 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %4, <2 x i32> %6)
  %29 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %4, <2 x i32> %6)
  %30 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %4, <2 x i32> %6)
  %31 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %4, <2 x i32> %6)
  %32 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %4, <2 x i32> %6)
  %33 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %4, <2 x i32> %6)
  %34 = bitcast float %32 to i32
  %35 = bitcast float %33 to i32
  %36 = insertelement <2 x i32> undef, i32 %34, i32 0
  %37 = insertelement <2 x i32> %36, i32 %35, i32 1
  %38 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %37, <32 x i8> %25, <16 x i8> %27, i32 2)
  %39 = extractelement <4 x float> %38, i32 0
  %40 = extractelement <4 x float> %38, i32 1
  %41 = extractelement <4 x float> %38, i32 2
  %42 = extractelement <4 x float> %38, i32 3
  %43 = fmul float %42, 3.200000e+01
  %44 = fadd float %43, -1.600000e+01
  %45 = call float @llvm.AMDIL.exp.(float %44)
  %46 = fmul float %39, %45
  %47 = fmul float %40, %45
  %48 = fmul float %41, %45
  %49 = fcmp oge float %23, 0.000000e+00
  %50 = sext i1 %49 to i32
  %51 = bitcast i32 %50 to float
  %52 = bitcast float %51 to i32
  %53 = icmp ne i32 %52, 0
  %. = select i1 %53, float %46, float %39
  %.12 = select i1 %53, float %47, float %40
  %.13 = select i1 %53, float %48, float %41
  %.14 = select i1 %53, float 1.000000e+00, float %42
  %54 = fmul float %., %28
  %55 = fmul float %.12, %29
  %56 = fmul float %.13, %30
  %57 = fmul float %.14, %31
  %58 = call i32 @llvm.SI.packf16(float %54, float %55)
  %59 = bitcast i32 %58 to float
  %60 = call i32 @llvm.SI.packf16(float %56, float %57)
  %61 = bitcast i32 %60 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %59, float %61, float %59, float %61)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.exp.(float) #2

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR7 in %vreg4, %VGPR0 in %vreg5, %VGPR1 in %vreg6

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR7 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR7
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 1, 1, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-def>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 1, 1, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 1, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<tied0>, %VGPR1, 0, 1, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%29](align=8)(tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%26](tbaa=!"const")
	S_WAITCNT 127
	%VGPR2_VGPR3_VGPR4_VGPR5<def> = IMAGE_SAMPLE_V4_V2 15, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MOV_B32_e32 -1.600000e+01, %EXEC<imp-use>
	%VGPR7<def> = V_MOV_B32_e32 3.200000e+01, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR6<def> = V_MAD_F32 %VGPR5, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_EXP_F32_e32 %VGPR6<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MUL_F32_e32 %VGPR3, %VGPR6, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%22](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 0; mem:LD4[<unknown>]
	S_WAITCNT 127
	%SGPR0_SGPR1<def> = V_CMP_GE_F32_e64 %SGPR0<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_CNDMASK_B32_e64 %VGPR3, %VGPR7<kill>, %SGPR0_SGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR8<def,tied1> = V_INTERP_P2_F32 %VGPR8<kill,tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MUL_F32_e32 %VGPR7<kill>, %VGPR8<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_F32_e32 %VGPR2, %VGPR6, %EXEC<imp-use>
	%VGPR8<def> = V_CNDMASK_B32_e64 %VGPR2, %VGPR8<kill>, %SGPR0_SGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR9<def,tied1> = V_INTERP_P2_F32 %VGPR9<kill,tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_F32_e32 %VGPR8<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR8<kill>, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %VGPR4, %VGPR6<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_CNDMASK_B32_e64 %VGPR4, %VGPR6<kill>, %SGPR0_SGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_INTERP_P1_F32 %VGPR0, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR8<def,tied1> = V_INTERP_P2_F32 %VGPR8<kill,tied0>, %VGPR1, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %VGPR6<kill>, %VGPR8<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_CNDMASK_B32_e64 %VGPR5, 1.000000e+00, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<kill,tied0>, %VGPR1, 3, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR2<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR6<kill>, %VGPR0<kill>, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR7<kill>, %VGPR0<kill>, %VGPR7, %VGPR0, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_WQM_B64 exec, exec                                                    ; BEFE0A7E
	S_MOV_B32 m0, s7                                                        ; BEFC0307
	V_INTERP_P1_F32 v3, v0, 1, 1, [m0]                                      ; C80C0500
	V_INTERP_P2_F32 v3, [v3], v1, 1, 1, [m0]                                ; C80D0501
	V_INTERP_P1_F32 v2, v0, 0, 1, [m0]                                      ; C8080400
	V_INTERP_P2_F32 v2, [v2], v1, 0, 1, [m0]                                ; C8090401
	S_LOAD_DWORDX4 s[8:11], s[2:3], 0                                       ; C0840300
	S_LOAD_DWORDX8 s[12:19], s[4:5], 0                                      ; C0C60500
	S_WAITCNT lgkmcnt(0)                                                    ; BF8C007F
	IMAGE_SAMPLE v[2:5], 15, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[12:19], s[8:11] ; F0800F00 00430202
	V_MOV_B32_e32 v6, -1.600000e+01                                         ; 7E0C02FF C1800000
	V_MOV_B32_e32 v7, 3.200000e+01                                          ; 7E0E02FF 42000000
	S_WAITCNT vmcnt(0)                                                      ; BF8C0770
	V_MAD_F32 v6, v5, v7, v6, 0, 0, 0, 0                                    ; D2820006 041A0F05
	V_EXP_F32_e32 v6, v6                                                    ; 7E0C4B06
	V_MUL_F32_e32 v7, v3, v6                                                ; 100E0D03
	S_LOAD_DWORDX4 s[0:3], s[0:1], 0                                        ; C0800100
	S_WAITCNT lgkmcnt(0)                                                    ; BF8C007F
	S_BUFFER_LOAD_DWORD s0, s[0:3], 0                                       ; C2000100
	S_WAITCNT lgkmcnt(0)                                                    ; BF8C007F
	V_CMP_GE_F32_e64 s[0:1], s0, 0.000000e+00, 0, 0, 0, 0                   ; D00C0000 02010000
	V_CNDMASK_B32_e64 v7, v3, v7, s[0:1], 0, 0, 0, 0                        ; D2000007 00020F03
	V_INTERP_P1_F32 v8, v0, 1, 0, [m0]                                      ; C8200100
	V_INTERP_P2_F32 v8, [v8], v1, 1, 0, [m0]                                ; C8210101
	V_MUL_F32_e32 v7, v7, v8                                                ; 100E1107
	V_MUL_F32_e32 v8, v2, v6                                                ; 10100D02
	V_CNDMASK_B32_e64 v8, v2, v8, s[0:1], 0, 0, 0, 0                        ; D2000008 00021102
	V_INTERP_P1_F32 v9, v0, 0, 0, [m0]                                      ; C8240000
	V_INTERP_P2_F32 v9, [v9], v1, 0, 0, [m0]                                ; C8250001
	V_MUL_F32_e32 v8, v8, v9                                                ; 10101308
	V_CVT_PKRTZ_F16_F32_e32 v7, v8, v7                                      ; 5E0E0F08
	V_MUL_F32_e32 v6, v4, v6                                                ; 100C0D04
	V_CNDMASK_B32_e64 v6, v4, v6, s[0:1], 0, 0, 0, 0                        ; D2000006 00020D04
	V_INTERP_P1_F32 v8, v0, 2, 0, [m0]                                      ; C8200200
	V_INTERP_P2_F32 v8, [v8], v1, 2, 0, [m0]                                ; C8210201
	V_MUL_F32_e32 v6, v6, v8                                                ; 100C1106
	V_CNDMASK_B32_e64 v2, v5, 1.000000e+00, s[0:1], 0, 0, 0, 0              ; D2000002 0001E505
	V_INTERP_P1_F32 v3, v0, 3, 0, [m0]                                      ; C80C0300
	V_INTERP_P2_F32 v3, [v3], v1, 3, 0, [m0]                                ; C80D0301
	V_MUL_F32_e32 v0, v2, v3                                                ; 10000702
	V_CVT_PKRTZ_F16_F32_e32 v0, v6, v0                                      ; 5E000106
	EXP 15, 0, 1, 1, 1, v7, v0, v7, v0                                      ; F8001C0F 00070007
	S_ENDPGM                                                                ; BF810000

VERT
DCL IN[0]
DCL IN[1]
DCL IN[2]
DCL OUT[0], POSITION
DCL OUT[1], CLIPVERTEX
DCL OUT[2], GENERIC[19]
DCL OUT[3], GENERIC[20]
DCL CONST[0..5]
DCL TEMP[0..3], LOCAL
IMM[0] FLT32 {    0.0000,     0.0000,     0.0000,     0.0000}
  0: DP4 TEMP[0].x, IN[0], CONST[0]
  1: DP4 TEMP[1].x, IN[0], CONST[1]
  2: MOV TEMP[0].y, TEMP[1].xxxx
  3: DP4 TEMP[1].x, IN[0], CONST[2]
  4: MOV TEMP[0].z, TEMP[1].xxxx
  5: DP4 TEMP[1].x, IN[0], CONST[3]
  6: MOV TEMP[0].w, TEMP[1].xxxx
  7: FSGE TEMP[1].x, CONST[4].zzzz, IMM[0].xxxx
  8: UIF TEMP[1].xxxx :0
  9:   MOV TEMP[1], IN[2].zyxw
 10: ELSE :0
 11:   MOV TEMP[1], CONST[5]
 12: ENDIF
 13: MOV TEMP[2].w, TEMP[1].wwww
 14: POW TEMP[3].x, TEMP[1].xxxx, CONST[4].xxxx
 15: POW TEMP[3].y, TEMP[1].yyyy, CONST[4].xxxx
 16: POW TEMP[3].z, TEMP[1].zzzz, CONST[4].xxxx
 17: MUL TEMP[2].xyz, TEMP[3].xyzz, CONST[4].yyyy
 18: MUL TEMP[0], TEMP[0], CONST[4].wwww
 19: MOV TEMP[1].xy, IN[1].xyxx
 20: MOV OUT[3], TEMP[1]
 21: MOV OUT[2], TEMP[2]
 22: MOV OUT[0], TEMP[0]
 23: MOV OUT[1], TEMP[0]
 24: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0)
  %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4)
  %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8)
  %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12)
  %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16)
  %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20)
  %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24)
  %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28)
  %20 = call float @llvm.SI.load.const(<16 x i8> %11, i32 32)
  %21 = call float @llvm.SI.load.const(<16 x i8> %11, i32 36)
  %22 = call float @llvm.SI.load.const(<16 x i8> %11, i32 40)
  %23 = call float @llvm.SI.load.const(<16 x i8> %11, i32 44)
  %24 = call float @llvm.SI.load.const(<16 x i8> %11, i32 48)
  %25 = call float @llvm.SI.load.const(<16 x i8> %11, i32 52)
  %26 = call float @llvm.SI.load.const(<16 x i8> %11, i32 56)
  %27 = call float @llvm.SI.load.const(<16 x i8> %11, i32 60)
  %28 = call float @llvm.SI.load.const(<16 x i8> %11, i32 64)
  %29 = call float @llvm.SI.load.const(<16 x i8> %11, i32 68)
  %30 = call float @llvm.SI.load.const(<16 x i8> %11, i32 72)
  %31 = call float @llvm.SI.load.const(<16 x i8> %11, i32 76)
  %32 = call float @llvm.SI.load.const(<16 x i8> %11, i32 80)
  %33 = call float @llvm.SI.load.const(<16 x i8> %11, i32 84)
  %34 = call float @llvm.SI.load.const(<16 x i8> %11, i32 88)
  %35 = call float @llvm.SI.load.const(<16 x i8> %11, i32 92)
  %36 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0
  %37 = load <16 x i8> addrspace(2)* %36, !tbaa !0
  %38 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %37, i32 0, i32 %6)
  %39 = extractelement <4 x float> %38, i32 0
  %40 = extractelement <4 x float> %38, i32 1
  %41 = extractelement <4 x float> %38, i32 2
  %42 = extractelement <4 x float> %38, i32 3
  %43 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 1
  %44 = load <16 x i8> addrspace(2)* %43, !tbaa !0
  %45 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %44, i32 0, i32 %6)
  %46 = extractelement <4 x float> %45, i32 0
  %47 = extractelement <4 x float> %45, i32 1
  %48 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 2
  %49 = load <16 x i8> addrspace(2)* %48, !tbaa !0
  %50 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %49, i32 0, i32 %6)
  %51 = extractelement <4 x float> %50, i32 0
  %52 = extractelement <4 x float> %50, i32 1
  %53 = extractelement <4 x float> %50, i32 2
  %54 = extractelement <4 x float> %50, i32 3
  %55 = fmul float %39, %12
  %56 = fmul float %40, %13
  %57 = fadd float %55, %56
  %58 = fmul float %41, %14
  %59 = fadd float %57, %58
  %60 = fmul float %42, %15
  %61 = fadd float %59, %60
  %62 = fmul float %39, %16
  %63 = fmul float %40, %17
  %64 = fadd float %62, %63
  %65 = fmul float %41, %18
  %66 = fadd float %64, %65
  %67 = fmul float %42, %19
  %68 = fadd float %66, %67
  %69 = fmul float %39, %20
  %70 = fmul float %40, %21
  %71 = fadd float %69, %70
  %72 = fmul float %41, %22
  %73 = fadd float %71, %72
  %74 = fmul float %42, %23
  %75 = fadd float %73, %74
  %76 = fmul float %39, %24
  %77 = fmul float %40, %25
  %78 = fadd float %76, %77
  %79 = fmul float %41, %26
  %80 = fadd float %78, %79
  %81 = fmul float %42, %27
  %82 = fadd float %80, %81
  %83 = fcmp oge float %30, 0.000000e+00
  %84 = sext i1 %83 to i32
  %85 = bitcast i32 %84 to float
  %86 = bitcast float %85 to i32
  %87 = icmp ne i32 %86, 0
  %. = select i1 %87, float %53, float %32
  %.16 = select i1 %87, float %52, float %33
  %.17 = select i1 %87, float %51, float %34
  %.18 = select i1 %87, float %54, float %35
  %88 = call float @llvm.pow.f32(float %., float %28)
  %89 = call float @llvm.pow.f32(float %.16, float %28)
  %90 = call float @llvm.pow.f32(float %.17, float %28)
  %91 = fmul float %88, %29
  %92 = fmul float %89, %29
  %93 = fmul float %90, %29
  %94 = fmul float %61, %31
  %95 = fmul float %68, %31
  %96 = fmul float %75, %31
  %97 = fmul float %82, %31
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %91, float %92, float %93, float %.18)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %46, float %47, float %.17, float %.18)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %94, float %95, float %96, float %97)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: nounwind readonly
declare float @llvm.pow.f32(float, float) #2

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { nounwind readonly }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg6

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 8; mem:LD16[%55](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%VGPR1_VGPR2_VGPR3_VGPR4<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%11](align=8)(tbaa=!"const")
	S_WAITCNT 112
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 18; mem:LD4[<unknown>]
	S_WAITCNT 127
	%SGPR4_SGPR5<def> = V_CMP_GE_F32_e64 %SGPR4<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 23; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR8<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_CNDMASK_B32_e64 %VGPR5<kill>, %VGPR4, %SGPR4_SGPR5, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 22; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR8<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_CNDMASK_B32_e64 %VGPR6<kill>, %VGPR1, %SGPR4_SGPR5, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_LOG_F32_e32 %VGPR6, %EXEC<imp-use>
	%SGPR8<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 16; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_LEGACY_F32_e32 %SGPR8, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_EXP_F32_e32 %VGPR7<kill>, %EXEC<imp-use>
	%SGPR9<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 17; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR9, %VGPR7<kill>, %EXEC<imp-use>
	%SGPR10<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 21; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR8<def> = V_MOV_B32_e32 %SGPR10<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_CNDMASK_B32_e64 %VGPR8<kill>, %VGPR2, %SGPR4_SGPR5, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_LOG_F32_e32 %VGPR8<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_LEGACY_F32_e32 %SGPR8, %VGPR8<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_EXP_F32_e32 %VGPR8<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_F32_e32 %SGPR9, %VGPR8<kill>, %EXEC<imp-use>
	%SGPR10<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 20; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR9<def> = V_MOV_B32_e32 %SGPR10<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_CNDMASK_B32_e64 %VGPR9<kill>, %VGPR3, %SGPR4_SGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR1_VGPR2_VGPR3_VGPR4<imp-use,kill>
	%VGPR1<def> = V_LOG_F32_e32 %VGPR1<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_MUL_LEGACY_F32_e32 %SGPR8<kill>, %VGPR1<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_EXP_F32_e32 %VGPR1<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_MUL_F32_e32 %SGPR9<kill>, %VGPR1<kill>, %EXEC<imp-use>
	EXP 15, 32, 0, 0, 0, %VGPR1<kill>, %VGPR8<kill>, %VGPR7<kill>, %VGPR5, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%48](align=8)(tbaa=!"const")
	S_WAITCNT 15
	%VGPR1_VGPR2_VGPR3_VGPR4<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	EXP 15, 33, 0, 0, 0, %VGPR1, %VGPR2, %VGPR6<kill>, %VGPR5<kill>, %EXEC<imp-use>, %VGPR1_VGPR2_VGPR3_VGPR4<imp-use,kill>
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%39](align=8)(tbaa=!"const")
	S_WAITCNT 15
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 13; mem:LD4[<unknown>]
	S_WAITCNT 112
	%VGPR4<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e64 %VGPR1, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 12; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR0, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 14; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR2, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 15; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR3, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 19; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR4<def> = V_MUL_F32_e32 %SGPR4, %VGPR4<kill>, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 9; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MUL_F32_e64 %VGPR1, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 8; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR0, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 10; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR2, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 11; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR3, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_MUL_F32_e32 %SGPR4, %VGPR5<kill>, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 5; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e64 %VGPR1, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 4; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR0, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 6; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR2, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 7; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR3, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %SGPR4, %VGPR6<kill>, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MUL_F32_e64 %VGPR1, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 0; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR8<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR0, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR8<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR2, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 3; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR8<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR3, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	%VGPR0<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR0<kill>, %EXEC<imp-use>
	EXP 15, 12, 0, 1, 0, %VGPR0<kill>, %VGPR6<kill>, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_LOAD_DWORDX4 s[8:11], s[6:7], 8                     ; C0840708
	S_WAITCNT lgkmcnt(0)                                  ; BF8C007F
	BUFFER_LOAD_FORMAT_XYZW v[1:4], s[8:11][v0] + 0       ; E00C2000 80020100
	S_LOAD_DWORDX4 s[0:3], s[0:1], 0                      ; C0800100
	S_WAITCNT vmcnt(0) lgkmcnt(0)                         ; BF8C0070
	S_BUFFER_LOAD_DWORD s4, s[0:3], 18                    ; C2020112
	S_WAITCNT lgkmcnt(0)                                  ; BF8C007F
	V_CMP_GE_F32_e64 s[4:5], s4, 0.000000e+00, 0, 0, 0, 0 ; D00C0004 02010004
	S_BUFFER_LOAD_DWORD s8, s[0:3], 23                    ; C2040117
	S_WAITCNT lgkmcnt(0)                                  ; BF8C007F
	V_MOV_B32_e32 v5, s8                                  ; 7E0A0208
	V_CNDMASK_B32_e64 v5, v5, v4, s[4:5], 0, 0, 0, 0      ; D2000005 00120905
	S_BUFFER_LOAD_DWORD s8, s[0:3], 22                    ; C2040116
	S_WAITCNT lgkmcnt(0)                                  ; BF8C007F
	V_MOV_B32_e32 v6, s8                                  ; 7E0C0208
	V_CNDMASK_B32_e64 v6, v6, v1, s[4:5], 0, 0, 0, 0      ; D2000006 00120306
	V_LOG_F32_e32 v7, v6                                  ; 7E0E4F06
	S_BUFFER_LOAD_DWORD s8, s[0:3], 16                    ; C2040110
	S_WAITCNT lgkmcnt(0)                                  ; BF8C007F
	V_MUL_LEGACY_F32_e32 v7, s8, v7                       ; 0E0E0E08
	V_EXP_F32_e32 v7, v7                                  ; 7E0E4B07
	S_BUFFER_LOAD_DWORD s9, s[0:3], 17                    ; C2048111
	S_WAITCNT lgkmcnt(0)                                  ; BF8C007F
	V_MUL_F32_e32 v7, s9, v7                              ; 100E0E09
	S_BUFFER_LOAD_DWORD s10, s[0:3], 21                   ; C2050115
	S_WAITCNT lgkmcnt(0)                                  ; BF8C007F
	V_MOV_B32_e32 v8, s10                                 ; 7E10020A
	V_CNDMASK_B32_e64 v8, v8, v2, s[4:5], 0, 0, 0, 0      ; D2000008 00120508
	V_LOG_F32_e32 v8, v8                                  ; 7E104F08
	V_MUL_LEGACY_F32_e32 v8, s8, v8                       ; 0E101008
	V_EXP_F32_e32 v8, v8                                  ; 7E104B08
	V_MUL_F32_e32 v8, s9, v8                              ; 10101009
	S_BUFFER_LOAD_DWORD s10, s[0:3], 20                   ; C2050114
	S_WAITCNT lgkmcnt(0)                                  ; BF8C007F
	V_MOV_B32_e32 v9, s10                                 ; 7E12020A
	V_CNDMASK_B32_e64 v1, v9, v3, s[4:5], 0, 0, 0, 0      ; D2000001 00120709
	V_LOG_F32_e32 v1, v1                                  ; 7E024F01
	V_MUL_LEGACY_F32_e32 v1, s8, v1                       ; 0E020208
	V_EXP_F32_e32 v1, v1                                  ; 7E024B01
	V_MUL_F32_e32 v1, s9, v1                              ; 10020209
	EXP 15, 32, 0, 0, 0, v1, v8, v7, v5                   ; F800020F 05070801
	S_LOAD_DWORDX4 s[8:11], s[6:7], 4                     ; C0840704
	S_WAITCNT expcnt(0) lgkmcnt(0)                        ; BF8C000F
	BUFFER_LOAD_FORMAT_XYZW v[1:4], s[8:11][v0] + 0       ; E00C2000 80020100
	S_WAITCNT vmcnt(0)                                    ; BF8C0770
	EXP 15, 33, 0, 0, 0, v1, v2, v6, v5                   ; F800021F 05060201
	S_LOAD_DWORDX4 s[4:7], s[6:7], 0                      ; C0820700
	S_WAITCNT expcnt(0) lgkmcnt(0)                        ; BF8C000F
	BUFFER_LOAD_FORMAT_XYZW v[0:3], s[4:7][v0] + 0        ; E00C2000 80010000
	S_BUFFER_LOAD_DWORD s4, s[0:3], 13                    ; C202010D
	S_WAITCNT vmcnt(0) lgkmcnt(0)                         ; BF8C0070
	V_MOV_B32_e32 v4, s4                                  ; 7E080204
	V_MUL_F32_e64 v4, v1, v4, 0, 0, 0, 0                  ; D2100004 02020901
	S_BUFFER_LOAD_DWORD s4, s[0:3], 12                    ; C202010C
	S_WAITCNT lgkmcnt(0)                                  ; BF8C007F
	V_MOV_B32_e32 v5, s4                                  ; 7E0A0204
	V_MAD_F32 v4, v0, v5, v4, 0, 0, 0, 0                  ; D2820004 04120B00
	S_BUFFER_LOAD_DWORD s4, s[0:3], 14                    ; C202010E
	S_WAITCNT lgkmcnt(0)                                  ; BF8C007F
	V_MOV_B32_e32 v5, s4                                  ; 7E0A0204
	V_MAD_F32 v4, v2, v5, v4, 0, 0, 0, 0                  ; D2820004 04120B02
	S_BUFFER_LOAD_DWORD s4, s[0:3], 15                    ; C202010F
	S_WAITCNT lgkmcnt(0)                                  ; BF8C007F
	V_MOV_B32_e32 v5, s4                                  ; 7E0A0204
	V_MAD_F32 v4, v3, v5, v4, 0, 0, 0, 0                  ; D2820004 04120B03
	S_BUFFER_LOAD_DWORD s4, s[0:3], 19                    ; C2020113
	S_WAITCNT lgkmcnt(0)                                  ; BF8C007F
	V_MUL_F32_e32 v4, s4, v4                              ; 10080804
	S_BUFFER_LOAD_DWORD s5, s[0:3], 9                     ; C2028109
	S_WAITCNT lgkmcnt(0)                                  ; BF8C007F
	V_MOV_B32_e32 v5, s5                                  ; 7E0A0205
	V_MUL_F32_e64 v5, v1, v5, 0, 0, 0, 0                  ; D2100005 02020B01
	S_BUFFER_LOAD_DWORD s5, s[0:3], 8                     ; C2028108
	S_WAITCNT lgkmcnt(0)                                  ; BF8C007F
	V_MOV_B32_e32 v6, s5                                  ; 7E0C0205
	V_MAD_F32 v5, v0, v6, v5, 0, 0, 0, 0                  ; D2820005 04160D00
	S_BUFFER_LOAD_DWORD s5, s[0:3], 10                    ; C202810A
	S_WAITCNT lgkmcnt(0)                                  ; BF8C007F
	V_MOV_B32_e32 v6, s5                                  ; 7E0C0205
	V_MAD_F32 v5, v2, v6, v5, 0, 0, 0, 0                  ; D2820005 04160D02
	S_BUFFER_LOAD_DWORD s5, s[0:3], 11                    ; C202810B
	S_WAITCNT lgkmcnt(0)                                  ; BF8C007F
	V_MOV_B32_e32 v6, s5                                  ; 7E0C0205
	V_MAD_F32 v5, v3, v6, v5, 0, 0, 0, 0                  ; D2820005 04160D03
	V_MUL_F32_e32 v5, s4, v5                              ; 100A0A04
	S_BUFFER_LOAD_DWORD s5, s[0:3], 5                     ; C2028105
	S_WAITCNT lgkmcnt(0)                                  ; BF8C007F
	V_MOV_B32_e32 v6, s5                                  ; 7E0C0205
	V_MUL_F32_e64 v6, v1, v6, 0, 0, 0, 0                  ; D2100006 02020D01
	S_BUFFER_LOAD_DWORD s5, s[0:3], 4                     ; C2028104
	S_WAITCNT lgkmcnt(0)                                  ; BF8C007F
	V_MOV_B32_e32 v7, s5                                  ; 7E0E0205
	V_MAD_F32 v6, v0, v7, v6, 0, 0, 0, 0                  ; D2820006 041A0F00
	S_BUFFER_LOAD_DWORD s5, s[0:3], 6                     ; C2028106
	S_WAITCNT lgkmcnt(0)                                  ; BF8C007F
	V_MOV_B32_e32 v7, s5                                  ; 7E0E0205
	V_MAD_F32 v6, v2, v7, v6, 0, 0, 0, 0                  ; D2820006 041A0F02
	S_BUFFER_LOAD_DWORD s5, s[0:3], 7                     ; C2028107
	S_WAITCNT lgkmcnt(0)                                  ; BF8C007F
	V_MOV_B32_e32 v7, s5                                  ; 7E0E0205
	V_MAD_F32 v6, v3, v7, v6, 0, 0, 0, 0                  ; D2820006 041A0F03
	V_MUL_F32_e32 v6, s4, v6                              ; 100C0C04
	S_BUFFER_LOAD_DWORD s5, s[0:3], 1                     ; C2028101
	S_WAITCNT lgkmcnt(0)                                  ; BF8C007F
	V_MOV_B32_e32 v7, s5                                  ; 7E0E0205
	V_MUL_F32_e64 v7, v1, v7, 0, 0, 0, 0                  ; D2100007 02020F01
	S_BUFFER_LOAD_DWORD s5, s[0:3], 0                     ; C2028100
	S_WAITCNT lgkmcnt(0)                                  ; BF8C007F
	V_MOV_B32_e32 v8, s5                                  ; 7E100205
	V_MAD_F32 v7, v0, v8, v7, 0, 0, 0, 0                  ; D2820007 041E1100
	S_BUFFER_LOAD_DWORD s5, s[0:3], 2                     ; C2028102
	S_WAITCNT lgkmcnt(0)                                  ; BF8C007F
	V_MOV_B32_e32 v8, s5                                  ; 7E100205
	V_MAD_F32 v7, v2, v8, v7, 0, 0, 0, 0                  ; D2820007 041E1102
	S_BUFFER_LOAD_DWORD s0, s[0:3], 3                     ; C2000103
	S_WAITCNT lgkmcnt(0)                                  ; BF8C007F
	V_MOV_B32_e32 v8, s0                                  ; 7E100200
	V_MAD_F32 v0, v3, v8, v7, 0, 0, 0, 0                  ; D2820000 041E1103
	V_MUL_F32_e32 v0, s4, v0                              ; 10000004
	EXP 15, 12, 0, 1, 0, v0, v6, v5, v4                   ; F80008CF 04050600
	S_ENDPGM                                              ; BF810000

INF:  Started simulation on 'Content/SeriousSam3/Levels/Menu/Intro.wld' in 0.54 seconds.
FRAG
DCL IN[0], GENERIC[0], LINEAR
DCL OUT[0], COLOR
DCL SAMP[0]
  0: TEX OUT[0], IN[0], SAMP[0], 2D
  1: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %21 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0
  %22 = load <32 x i8> addrspace(2)* %21, !tbaa !0
  %23 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0
  %24 = load <16 x i8> addrspace(2)* %23, !tbaa !0
  %25 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %4, <2 x i32> %10)
  %26 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %4, <2 x i32> %10)
  %27 = bitcast float %25 to i32
  %28 = bitcast float %26 to i32
  %29 = insertelement <2 x i32> undef, i32 %27, i32 0
  %30 = insertelement <2 x i32> %29, i32 %28, i32 1
  %31 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %30, <32 x i8> %22, <16 x i8> %24, i32 2)
  %32 = extractelement <4 x float> %31, i32 0
  %33 = extractelement <4 x float> %31, i32 1
  %34 = extractelement <4 x float> %31, i32 2
  %35 = extractelement <4 x float> %31, i32 3
  %36 = call i32 @llvm.SI.packf16(float %32, float %33)
  %37 = bitcast i32 %36 to float
  %38 = call i32 @llvm.SI.packf16(float %34, float %35)
  %39 = bitcast i32 %38 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %37, float %39, float %37, float %39)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR7 in %vreg4, %VGPR0 in %vreg5, %VGPR1 in %vreg6

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR7 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR7
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-def>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%24](align=8)(tbaa=!"const")
	%SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%21](tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = IMAGE_SAMPLE_V4_V2 15, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3<kill>, %SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<kill>, %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR4<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR2, %VGPR3, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0, %VGPR1, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	EXP 15, 0, 1, 1, 1, %VGPR0<kill>, %VGPR4<kill>, %VGPR0, %VGPR4, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_WQM_B64 exec, exec                                                  ; BEFE0A7E
	S_MOV_B32 m0, s7                                                      ; BEFC0307
	V_INTERP_P1_F32 v3, v0, 1, 0, [m0]                                    ; C80C0100
	V_INTERP_P2_F32 v3, [v3], v1, 1, 0, [m0]                              ; C80D0101
	V_INTERP_P1_F32 v2, v0, 0, 0, [m0]                                    ; C8080000
	V_INTERP_P2_F32 v2, [v2], v1, 0, 0, [m0]                              ; C8090001
	S_LOAD_DWORDX4 s[0:3], s[2:3], 0                                      ; C0800300
	S_LOAD_DWORDX8 s[4:11], s[4:5], 0                                     ; C0C20500
	S_WAITCNT lgkmcnt(0)                                                  ; BF8C007F
	IMAGE_SAMPLE v[0:3], 15, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[4:11], s[0:3] ; F0800F00 00010002
	S_WAITCNT vmcnt(0)                                                    ; BF8C0770
	V_CVT_PKRTZ_F16_F32_e32 v4, v2, v3                                    ; 5E080702
	V_CVT_PKRTZ_F16_F32_e32 v0, v0, v1                                    ; 5E000300
	EXP 15, 0, 1, 1, 1, v0, v4, v0, v4                                    ; F8001C0F 04000400
	S_ENDPGM                                                              ; BF810000

VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[0]
  0: MOV OUT[0], IN[0]
  1: MOV OUT[1], IN[1]
  2: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %11, i32 0, i32 %6)
  %13 = extractelement <4 x float> %12, i32 0
  %14 = extractelement <4 x float> %12, i32 1
  %15 = extractelement <4 x float> %12, i32 2
  %16 = extractelement <4 x float> %12, i32 3
  %17 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 1
  %18 = load <16 x i8> addrspace(2)* %17, !tbaa !0
  %19 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %18, i32 0, i32 %6)
  %20 = extractelement <4 x float> %19, i32 0
  %21 = extractelement <4 x float> %19, i32 1
  %22 = extractelement <4 x float> %19, i32 2
  %23 = extractelement <4 x float> %19, i32 3
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %20, float %21, float %22, float %23)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %13, float %14, float %15, float %16)
  ret void
}

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg6

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR6_SGPR7 %VGPR0
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%20](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%VGPR1_VGPR2_VGPR3_VGPR4<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	EXP 15, 32, 0, 0, 0, %VGPR1, %VGPR2, %VGPR3, %VGPR4, %EXEC<imp-use>, %VGPR1_VGPR2_VGPR3_VGPR4<imp-use,kill>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%11](align=8)(tbaa=!"const")
	S_WAITCNT 15
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR1, %VGPR2, %VGPR3, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_LOAD_DWORDX4 s[0:3], s[6:7], 4               ; C0800704
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	BUFFER_LOAD_FORMAT_XYZW v[1:4], s[0:3][v0] + 0 ; E00C2000 80000100
	S_WAITCNT vmcnt(0)                             ; BF8C0770
	EXP 15, 32, 0, 0, 0, v1, v2, v3, v4            ; F800020F 04030201
	S_LOAD_DWORDX4 s[0:3], s[6:7], 0               ; C0800700
	S_WAITCNT expcnt(0) lgkmcnt(0)                 ; BF8C000F
	BUFFER_LOAD_FORMAT_XYZW v[0:3], s[0:3][v0] + 0 ; E00C2000 80000000
	S_WAITCNT vmcnt(0)                             ; BF8C0770
	EXP 15, 12, 0, 1, 0, v0, v1, v2, v3            ; F80008CF 03020100
	S_ENDPGM                                       ; BF810000

FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %21 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %4)
  %22 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %4)
  %23 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %4)
  %24 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %4)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %21, float %22, float %23, float %24)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR7 in %vreg4

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR7
	%EXEC<def> = S_WQM_B64 %EXEC
	%M0<def> = S_MOV_B32 %SGPR7
	%VGPR0<def> = V_INTERP_MOV_F32 2, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_INTERP_MOV_F32 2, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_INTERP_MOV_F32 2, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_INTERP_MOV_F32 2, 0, 0, %M0<kill>, %EXEC<imp-use>
	EXP 15, 0, 0, 1, 1, %VGPR3<kill>, %VGPR2<kill>, %VGPR1<kill>, %VGPR0<kill>, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_WQM_B64 exec, exec                ; BEFE0A7E
	S_MOV_B32 m0, s7                    ; BEFC0307
	V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302
	V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202
	V_INTERP_MOV_F32 v2, P0, 1, 0, [m0] ; C80A0102
	V_INTERP_MOV_F32 v3, P0, 0, 0, [m0] ; C80E0002
	EXP 15, 0, 0, 1, 1, v3, v2, v1, v0  ; F800180F 00010203
	S_ENDPGM                            ; BF810000

FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL IN[1], GENERIC[20], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL CONST[0]
DCL TEMP[0..2], LOCAL
IMM[0] FLT32 {    0.2500,     0.0000,     0.0000,     0.0000}
  0: MAX TEMP[0], IN[0], CONST[0].xyxy
  1: MIN TEMP[0], TEMP[0], CONST[0].zwzw
  2: MOV TEMP[1].xy, TEMP[0].xyyy
  3: TEX TEMP[1], TEMP[1], SAMP[0], 2D
  4: MUL TEMP[1], TEMP[1], IMM[0].xxxx
  5: MOV TEMP[0].xy, TEMP[0].zwww
  6: TEX TEMP[0], TEMP[0], SAMP[0], 2D
  7: MAD TEMP[1], TEMP[0], IMM[0].xxxx, TEMP[1]
  8: MAX TEMP[0], IN[1], CONST[0].xyxy
  9: MIN TEMP[0], TEMP[0], CONST[0].zwzw
 10: MOV TEMP[2].xy, TEMP[0].xyyy
 11: TEX TEMP[2], TEMP[2], SAMP[0], 2D
 12: MAD TEMP[1], TEMP[2], IMM[0].xxxx, TEMP[1]
 13: MOV TEMP[0].xy, TEMP[0].zwww
 14: TEX TEMP[0], TEMP[0], SAMP[0], 2D
 15: MAD TEMP[0], TEMP[0], IMM[0].xxxx, TEMP[1]
 16: MOV OUT[0], TEMP[0]
 17: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %21 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
  %22 = load <16 x i8> addrspace(2)* %21, !tbaa !0
  %23 = call float @llvm.SI.load.const(<16 x i8> %22, i32 0)
  %24 = call float @llvm.SI.load.const(<16 x i8> %22, i32 4)
  %25 = call float @llvm.SI.load.const(<16 x i8> %22, i32 8)
  %26 = call float @llvm.SI.load.const(<16 x i8> %22, i32 12)
  %27 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0
  %28 = load <32 x i8> addrspace(2)* %27, !tbaa !0
  %29 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0
  %30 = load <16 x i8> addrspace(2)* %29, !tbaa !0
  %31 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %4, <2 x i32> %6)
  %32 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %4, <2 x i32> %6)
  %33 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %4, <2 x i32> %6)
  %34 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %4, <2 x i32> %6)
  %35 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %4, <2 x i32> %6)
  %36 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %4, <2 x i32> %6)
  %37 = call float @llvm.SI.fs.interp(i32 2, i32 1, i32 %4, <2 x i32> %6)
  %38 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %4, <2 x i32> %6)
  %39 = fcmp uge float %31, %23
  %40 = select i1 %39, float %31, float %23
  %41 = fcmp uge float %32, %24
  %42 = select i1 %41, float %32, float %24
  %43 = fcmp uge float %33, %23
  %44 = select i1 %43, float %33, float %23
  %45 = fcmp uge float %34, %24
  %46 = select i1 %45, float %34, float %24
  %47 = fcmp uge float %40, %25
  %48 = select i1 %47, float %25, float %40
  %49 = fcmp uge float %42, %26
  %50 = select i1 %49, float %26, float %42
  %51 = fcmp uge float %44, %25
  %52 = select i1 %51, float %25, float %44
  %53 = fcmp uge float %46, %26
  %54 = select i1 %53, float %26, float %46
  %55 = bitcast float %48 to i32
  %56 = bitcast float %50 to i32
  %57 = insertelement <2 x i32> undef, i32 %55, i32 0
  %58 = insertelement <2 x i32> %57, i32 %56, i32 1
  %59 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %58, <32 x i8> %28, <16 x i8> %30, i32 2)
  %60 = extractelement <4 x float> %59, i32 0
  %61 = extractelement <4 x float> %59, i32 1
  %62 = extractelement <4 x float> %59, i32 2
  %63 = extractelement <4 x float> %59, i32 3
  %64 = fmul float %60, 2.500000e-01
  %65 = fmul float %61, 2.500000e-01
  %66 = fmul float %62, 2.500000e-01
  %67 = fmul float %63, 2.500000e-01
  %68 = bitcast float %52 to i32
  %69 = bitcast float %54 to i32
  %70 = insertelement <2 x i32> undef, i32 %68, i32 0
  %71 = insertelement <2 x i32> %70, i32 %69, i32 1
  %72 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %71, <32 x i8> %28, <16 x i8> %30, i32 2)
  %73 = extractelement <4 x float> %72, i32 0
  %74 = extractelement <4 x float> %72, i32 1
  %75 = extractelement <4 x float> %72, i32 2
  %76 = extractelement <4 x float> %72, i32 3
  %77 = fmul float %73, 2.500000e-01
  %78 = fadd float %77, %64
  %79 = fmul float %74, 2.500000e-01
  %80 = fadd float %79, %65
  %81 = fmul float %75, 2.500000e-01
  %82 = fadd float %81, %66
  %83 = fmul float %76, 2.500000e-01
  %84 = fadd float %83, %67
  %85 = fcmp uge float %35, %23
  %86 = select i1 %85, float %35, float %23
  %87 = fcmp uge float %36, %24
  %88 = select i1 %87, float %36, float %24
  %89 = fcmp uge float %37, %23
  %90 = select i1 %89, float %37, float %23
  %91 = fcmp uge float %38, %24
  %92 = select i1 %91, float %38, float %24
  %93 = fcmp uge float %86, %25
  %94 = select i1 %93, float %25, float %86
  %95 = fcmp uge float %88, %26
  %96 = select i1 %95, float %26, float %88
  %97 = fcmp uge float %90, %25
  %98 = select i1 %97, float %25, float %90
  %99 = fcmp uge float %92, %26
  %100 = select i1 %99, float %26, float %92
  %101 = bitcast float %94 to i32
  %102 = bitcast float %96 to i32
  %103 = insertelement <2 x i32> undef, i32 %101, i32 0
  %104 = insertelement <2 x i32> %103, i32 %102, i32 1
  %105 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %104, <32 x i8> %28, <16 x i8> %30, i32 2)
  %106 = extractelement <4 x float> %105, i32 0
  %107 = extractelement <4 x float> %105, i32 1
  %108 = extractelement <4 x float> %105, i32 2
  %109 = extractelement <4 x float> %105, i32 3
  %110 = fmul float %106, 2.500000e-01
  %111 = fadd float %110, %78
  %112 = fmul float %107, 2.500000e-01
  %113 = fadd float %112, %80
  %114 = fmul float %108, 2.500000e-01
  %115 = fadd float %114, %82
  %116 = fmul float %109, 2.500000e-01
  %117 = fadd float %116, %84
  %118 = bitcast float %98 to i32
  %119 = bitcast float %100 to i32
  %120 = insertelement <2 x i32> undef, i32 %118, i32 0
  %121 = insertelement <2 x i32> %120, i32 %119, i32 1
  %122 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %121, <32 x i8> %28, <16 x i8> %30, i32 2)
  %123 = extractelement <4 x float> %122, i32 0
  %124 = extractelement <4 x float> %122, i32 1
  %125 = extractelement <4 x float> %122, i32 2
  %126 = extractelement <4 x float> %122, i32 3
  %127 = fmul float %123, 2.500000e-01
  %128 = fadd float %127, %111
  %129 = fmul float %124, 2.500000e-01
  %130 = fadd float %129, %113
  %131 = fmul float %125, 2.500000e-01
  %132 = fadd float %131, %115
  %133 = fmul float %126, 2.500000e-01
  %134 = fadd float %133, %117
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %128, float %130, float %132, float %134)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR7 in %vreg4, %VGPR0 in %vreg5, %VGPR1 in %vreg6

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR7 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR7
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<kill,tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%22](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 1; mem:LD4[<unknown>]
	S_WAITCNT 127
	%SGPR12_SGPR13<def> = V_CMP_U_F32_e64 %VGPR2, %SGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR14_SGPR15<def> = V_CMP_GE_F32_e64 %VGPR2, %SGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR12_SGPR13<def> = S_OR_B64 %SGPR14_SGPR15<kill>, %SGPR12_SGPR13<kill>
	%VGPR3<def> = V_MOV_B32_e32 %SGPR0, %EXEC<imp-use>
	%VGPR2<def> = V_CNDMASK_B32_e64 %VGPR3, %VGPR2<kill>, %SGPR12_SGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 3; mem:LD4[<unknown>]
	S_WAITCNT 127
	%SGPR12_SGPR13<def> = V_CMP_U_F32_e64 %VGPR2, %SGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR14_SGPR15<def> = V_CMP_GE_F32_e64 %VGPR2, %SGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR12_SGPR13<def> = S_OR_B64 %SGPR14_SGPR15<kill>, %SGPR12_SGPR13<kill>
	%VGPR4<def> = V_MOV_B32_e32 %SGPR1, %EXEC<imp-use>
	%VGPR6<def> = V_CNDMASK_B32_e64 %VGPR2<kill>, %VGPR4, %SGPR12_SGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR5_VGPR6<imp-def>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<kill,tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>
	%SGPR6<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 0; mem:LD4[<unknown>]
	S_WAITCNT 127
	%SGPR12_SGPR13<def> = V_CMP_U_F32_e64 %VGPR2, %SGPR6, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR14_SGPR15<def> = V_CMP_GE_F32_e64 %VGPR2, %SGPR6, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR12_SGPR13<def> = S_OR_B64 %SGPR14_SGPR15<kill>, %SGPR12_SGPR13<kill>
	%VGPR7<def> = V_MOV_B32_e32 %SGPR6, %EXEC<imp-use>
	%VGPR2<def> = V_CNDMASK_B32_e64 %VGPR7, %VGPR2<kill>, %SGPR12_SGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11<kill>, 2; mem:LD4[<unknown>]
	S_WAITCNT 127
	%SGPR10_SGPR11<def> = V_CMP_U_F32_e64 %VGPR2, %SGPR8, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR12_SGPR13<def> = V_CMP_GE_F32_e64 %VGPR2, %SGPR8, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR10_SGPR11<def> = S_OR_B64 %SGPR12_SGPR13<kill>, %SGPR10_SGPR11<kill>
	%VGPR8<def> = V_MOV_B32_e32 %SGPR8, %EXEC<imp-use>
	%VGPR5<def> = V_CNDMASK_B32_e64 %VGPR2<kill>, %VGPR8, %SGPR10_SGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR5_VGPR6<imp-use,kill>, %VGPR5_VGPR6<imp-def>
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%32](align=8)(tbaa=!"const")
	%SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%29](tbaa=!"const")
	S_WAITCNT 127
	%VGPR9_VGPR10_VGPR11_VGPR12<def> = IMAGE_SAMPLE_V4_V2 15, 0, 0, 0, 0, 0, 0, 0, %VGPR5_VGPR6<kill>, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23, %SGPR12_SGPR13_SGPR14_SGPR15, %EXEC<imp-use>
	%VGPR2<def> = V_MOV_B32_e32 2.500000e-01, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR5<def> = V_MUL_F32_e32 %VGPR12, %VGPR2, %EXEC<imp-use>
	%VGPR6<def> = V_INTERP_P1_F32 %VGPR0, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR6<def,tied1> = V_INTERP_P2_F32 %VGPR6<kill,tied0>, %VGPR1, 3, 0, %M0<kill>, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_U_F32_e64 %VGPR6, %SGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_GE_F32_e64 %VGPR6, %SGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_OR_B64 %SGPR4_SGPR5<kill>, %SGPR2_SGPR3<kill>
	%VGPR6<def> = V_CNDMASK_B32_e64 %VGPR3, %VGPR6<kill>, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_U_F32_e64 %VGPR6, %SGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_GE_F32_e64 %VGPR6, %SGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_OR_B64 %SGPR4_SGPR5<kill>, %SGPR2_SGPR3<kill>
	%VGPR14<def> = V_CNDMASK_B32_e64 %VGPR6<kill>, %VGPR4, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR13_VGPR14<imp-def>
	%VGPR6<def> = V_INTERP_P1_F32 %VGPR0, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR6<def,tied1> = V_INTERP_P2_F32 %VGPR6<kill,tied0>, %VGPR1, 2, 0, %M0<kill>, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_U_F32_e64 %VGPR6, %SGPR6, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_GE_F32_e64 %VGPR6, %SGPR6, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_OR_B64 %SGPR4_SGPR5<kill>, %SGPR2_SGPR3<kill>
	%VGPR6<def> = V_CNDMASK_B32_e64 %VGPR7, %VGPR6<kill>, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_U_F32_e64 %VGPR6, %SGPR8, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_GE_F32_e64 %VGPR6, %SGPR8, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_OR_B64 %SGPR4_SGPR5<kill>, %SGPR2_SGPR3<kill>
	%VGPR13<def> = V_CNDMASK_B32_e64 %VGPR6<kill>, %VGPR8, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR13_VGPR14<imp-use,kill>, %VGPR13_VGPR14<imp-def>
	%VGPR13_VGPR14_VGPR15_VGPR16<def> = IMAGE_SAMPLE_V4_V2 15, 0, 0, 0, 0, 0, 0, 0, %VGPR13_VGPR14<kill>, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23, %SGPR12_SGPR13_SGPR14_SGPR15, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR5<def> = V_MAD_F32 %VGPR16, %VGPR2, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_INTERP_P1_F32 %VGPR0, 1, 1, %M0<kill>, %EXEC<imp-use>
	%VGPR6<def,tied1> = V_INTERP_P2_F32 %VGPR6<kill,tied0>, %VGPR1, 1, 1, %M0<kill>, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_U_F32_e64 %VGPR6, %SGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_GE_F32_e64 %VGPR6, %SGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_OR_B64 %SGPR4_SGPR5<kill>, %SGPR2_SGPR3<kill>
	%VGPR6<def> = V_CNDMASK_B32_e64 %VGPR3, %VGPR6<kill>, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_U_F32_e64 %VGPR6, %SGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_GE_F32_e64 %VGPR6, %SGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_OR_B64 %SGPR4_SGPR5<kill>, %SGPR2_SGPR3<kill>
	%VGPR18<def> = V_CNDMASK_B32_e64 %VGPR6<kill>, %VGPR4, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR17_VGPR18<imp-def>
	%VGPR6<def> = V_INTERP_P1_F32 %VGPR0, 0, 1, %M0<kill>, %EXEC<imp-use>
	%VGPR6<def,tied1> = V_INTERP_P2_F32 %VGPR6<kill,tied0>, %VGPR1, 0, 1, %M0<kill>, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_U_F32_e64 %VGPR6, %SGPR6, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_GE_F32_e64 %VGPR6, %SGPR6, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_OR_B64 %SGPR4_SGPR5<kill>, %SGPR2_SGPR3<kill>
	%VGPR6<def> = V_CNDMASK_B32_e64 %VGPR7, %VGPR6<kill>, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_U_F32_e64 %VGPR6, %SGPR8, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_GE_F32_e64 %VGPR6, %SGPR8, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_OR_B64 %SGPR4_SGPR5<kill>, %SGPR2_SGPR3<kill>
	%VGPR17<def> = V_CNDMASK_B32_e64 %VGPR6<kill>, %VGPR8, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR17_VGPR18<imp-use,kill>, %VGPR17_VGPR18<imp-def>
	%VGPR17_VGPR18_VGPR19_VGPR20<def> = IMAGE_SAMPLE_V4_V2 15, 0, 0, 0, 0, 0, 0, 0, %VGPR17_VGPR18<kill>, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23, %SGPR12_SGPR13_SGPR14_SGPR15, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR5<def> = V_MAD_F32 %VGPR20, %VGPR2, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_INTERP_P1_F32 %VGPR0, 3, 1, %M0<kill>, %EXEC<imp-use>
	%VGPR6<def,tied1> = V_INTERP_P2_F32 %VGPR6<kill,tied0>, %VGPR1, 3, 1, %M0<kill>, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_U_F32_e64 %VGPR6, %SGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_GE_F32_e64 %VGPR6, %SGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_OR_B64 %SGPR4_SGPR5<kill>, %SGPR2_SGPR3<kill>
	%VGPR3<def> = V_CNDMASK_B32_e64 %VGPR3<kill>, %VGPR6<kill>, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_U_F32_e64 %VGPR3, %SGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = V_CMP_GE_F32_e64 %VGPR3, %SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_OR_B64 %SGPR0_SGPR1<kill>, %SGPR2_SGPR3<kill>
	%VGPR4<def> = V_CNDMASK_B32_e64 %VGPR3<kill>, %VGPR4<kill>, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR3_VGPR4<imp-def>
	%VGPR6<def> = V_INTERP_P1_F32 %VGPR0, 2, 1, %M0<kill>, %EXEC<imp-use>
	%VGPR6<def,tied1> = V_INTERP_P2_F32 %VGPR6<kill,tied0>, %VGPR1, 2, 1, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>
	%SGPR0_SGPR1<def> = V_CMP_U_F32_e64 %VGPR6, %SGPR6, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR6, %SGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_OR_B64 %SGPR2_SGPR3<kill>, %SGPR0_SGPR1<kill>
	%VGPR0<def> = V_CNDMASK_B32_e64 %VGPR7<kill>, %VGPR6<kill>, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = V_CMP_U_F32_e64 %VGPR0, %SGPR8, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR0, %SGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_OR_B64 %SGPR2_SGPR3<kill>, %SGPR0_SGPR1<kill>
	%VGPR3<def> = V_CNDMASK_B32_e64 %VGPR0<kill>, %VGPR8<kill>, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR3_VGPR4<imp-use,kill>, %VGPR3_VGPR4<imp-def>
	%VGPR21_VGPR22_VGPR23_VGPR24<def> = IMAGE_SAMPLE_V4_V2 15, 0, 0, 0, 0, 0, 0, 0, %VGPR3_VGPR4<kill>, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23<kill>, %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR0<def> = V_MAD_F32 %VGPR24, %VGPR2, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_MUL_F32_e32 %VGPR11, %VGPR2, %EXEC<imp-use>
	%VGPR1<def> = V_MAD_F32 %VGPR15, %VGPR2, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_MAD_F32 %VGPR19, %VGPR2, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_MAD_F32 %VGPR23, %VGPR2, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_MUL_F32_e32 %VGPR10, %VGPR2, %EXEC<imp-use>
	%VGPR3<def> = V_MAD_F32 %VGPR14, %VGPR2, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_MAD_F32 %VGPR18, %VGPR2, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_MAD_F32 %VGPR22, %VGPR2, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e32 %VGPR9, %VGPR2, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>
	%VGPR4<def> = V_MAD_F32 %VGPR13, %VGPR2, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR13_VGPR14_VGPR15_VGPR16<imp-use,kill>
	%VGPR4<def> = V_MAD_F32 %VGPR17, %VGPR2, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR17_VGPR18_VGPR19_VGPR20<imp-use,kill>
	%VGPR2<def> = V_MAD_F32 %VGPR21, %VGPR2<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR21_VGPR22_VGPR23_VGPR24<imp-use,kill>
	EXP 15, 0, 0, 1, 1, %VGPR2<kill>, %VGPR3<kill>, %VGPR1<kill>, %VGPR0<kill>, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_WQM_B64 exec, exec                                                         ; BEFE0A7E
	S_MOV_B32 m0, s7                                                             ; BEFC0307
	V_INTERP_P1_F32 v2, v0, 1, 0, [m0]                                           ; C8080100
	V_INTERP_P2_F32 v2, [v2], v1, 1, 0, [m0]                                     ; C8090101
	S_LOAD_DWORDX4 s[8:11], s[0:1], 0                                            ; C0840100
	S_WAITCNT lgkmcnt(0)                                                         ; BF8C007F
	S_BUFFER_LOAD_DWORD s0, s[8:11], 1                                           ; C2000901
	S_WAITCNT lgkmcnt(0)                                                         ; BF8C007F
	V_CMP_U_F32_e64 s[12:13], v2, s0, 0, 0, 0, 0                                 ; D010000C 02000102
	V_CMP_GE_F32_e64 s[14:15], v2, s0, 0, 0, 0, 0                                ; D00C000E 02000102
	S_OR_B64 s[12:13], s[14:15], s[12:13]                                        ; 888C0C0E
	V_MOV_B32_e32 v3, s0                                                         ; 7E060200
	V_CNDMASK_B32_e64 v2, v3, v2, s[12:13], 0, 0, 0, 0                           ; D2000002 00320503
	S_BUFFER_LOAD_DWORD s1, s[8:11], 3                                           ; C2008903
	S_WAITCNT lgkmcnt(0)                                                         ; BF8C007F
	V_CMP_U_F32_e64 s[12:13], v2, s1, 0, 0, 0, 0                                 ; D010000C 02000302
	V_CMP_GE_F32_e64 s[14:15], v2, s1, 0, 0, 0, 0                                ; D00C000E 02000302
	S_OR_B64 s[12:13], s[14:15], s[12:13]                                        ; 888C0C0E
	V_MOV_B32_e32 v4, s1                                                         ; 7E080201
	V_CNDMASK_B32_e64 v6, v2, v4, s[12:13], 0, 0, 0, 0                           ; D2000006 00320902
	V_INTERP_P1_F32 v2, v0, 0, 0, [m0]                                           ; C8080000
	V_INTERP_P2_F32 v2, [v2], v1, 0, 0, [m0]                                     ; C8090001
	S_BUFFER_LOAD_DWORD s6, s[8:11], 0                                           ; C2030900
	S_WAITCNT lgkmcnt(0)                                                         ; BF8C007F
	V_CMP_U_F32_e64 s[12:13], v2, s6, 0, 0, 0, 0                                 ; D010000C 02000D02
	V_CMP_GE_F32_e64 s[14:15], v2, s6, 0, 0, 0, 0                                ; D00C000E 02000D02
	S_OR_B64 s[12:13], s[14:15], s[12:13]                                        ; 888C0C0E
	V_MOV_B32_e32 v7, s6                                                         ; 7E0E0206
	V_CNDMASK_B32_e64 v2, v7, v2, s[12:13], 0, 0, 0, 0                           ; D2000002 00320507
	S_BUFFER_LOAD_DWORD s8, s[8:11], 2                                           ; C2040902
	S_WAITCNT lgkmcnt(0)                                                         ; BF8C007F
	V_CMP_U_F32_e64 s[10:11], v2, s8, 0, 0, 0, 0                                 ; D010000A 02001102
	V_CMP_GE_F32_e64 s[12:13], v2, s8, 0, 0, 0, 0                                ; D00C000C 02001102
	S_OR_B64 s[10:11], s[12:13], s[10:11]                                        ; 888A0A0C
	V_MOV_B32_e32 v8, s8                                                         ; 7E100208
	V_CNDMASK_B32_e64 v5, v2, v8, s[10:11], 0, 0, 0, 0                           ; D2000005 002A1102
	S_LOAD_DWORDX4 s[12:15], s[2:3], 0                                           ; C0860300
	S_LOAD_DWORDX8 s[16:23], s[4:5], 0                                           ; C0C80500
	S_WAITCNT lgkmcnt(0)                                                         ; BF8C007F
	IMAGE_SAMPLE v[9:12], 15, 0, 0, 0, 0, 0, 0, 0, v[5:6], s[16:23], s[12:15]    ; F0800F00 00640905
	V_MOV_B32_e32 v2, 2.500000e-01                                               ; 7E0402FF 3E800000
	S_WAITCNT vmcnt(0)                                                           ; BF8C0770
	V_MUL_F32_e32 v5, v12, v2                                                    ; 100A050C
	V_INTERP_P1_F32 v6, v0, 3, 0, [m0]                                           ; C8180300
	V_INTERP_P2_F32 v6, [v6], v1, 3, 0, [m0]                                     ; C8190301
	V_CMP_U_F32_e64 s[2:3], v6, s0, 0, 0, 0, 0                                   ; D0100002 02000106
	V_CMP_GE_F32_e64 s[4:5], v6, s0, 0, 0, 0, 0                                  ; D00C0004 02000106
	S_OR_B64 s[2:3], s[4:5], s[2:3]                                              ; 88820204
	V_CNDMASK_B32_e64 v6, v3, v6, s[2:3], 0, 0, 0, 0                             ; D2000006 000A0D03
	V_CMP_U_F32_e64 s[2:3], v6, s1, 0, 0, 0, 0                                   ; D0100002 02000306
	V_CMP_GE_F32_e64 s[4:5], v6, s1, 0, 0, 0, 0                                  ; D00C0004 02000306
	S_OR_B64 s[2:3], s[4:5], s[2:3]                                              ; 88820204
	V_CNDMASK_B32_e64 v14, v6, v4, s[2:3], 0, 0, 0, 0                            ; D200000E 000A0906
	V_INTERP_P1_F32 v6, v0, 2, 0, [m0]                                           ; C8180200
	V_INTERP_P2_F32 v6, [v6], v1, 2, 0, [m0]                                     ; C8190201
	V_CMP_U_F32_e64 s[2:3], v6, s6, 0, 0, 0, 0                                   ; D0100002 02000D06
	V_CMP_GE_F32_e64 s[4:5], v6, s6, 0, 0, 0, 0                                  ; D00C0004 02000D06
	S_OR_B64 s[2:3], s[4:5], s[2:3]                                              ; 88820204
	V_CNDMASK_B32_e64 v6, v7, v6, s[2:3], 0, 0, 0, 0                             ; D2000006 000A0D07
	V_CMP_U_F32_e64 s[2:3], v6, s8, 0, 0, 0, 0                                   ; D0100002 02001106
	V_CMP_GE_F32_e64 s[4:5], v6, s8, 0, 0, 0, 0                                  ; D00C0004 02001106
	S_OR_B64 s[2:3], s[4:5], s[2:3]                                              ; 88820204
	V_CNDMASK_B32_e64 v13, v6, v8, s[2:3], 0, 0, 0, 0                            ; D200000D 000A1106
	IMAGE_SAMPLE v[13:16], 15, 0, 0, 0, 0, 0, 0, 0, v[13:14], s[16:23], s[12:15] ; F0800F00 00640D0D
	S_WAITCNT vmcnt(0)                                                           ; BF8C0770
	V_MAD_F32 v5, v16, v2, v5, 0, 0, 0, 0                                        ; D2820005 04160510
	V_INTERP_P1_F32 v6, v0, 1, 1, [m0]                                           ; C8180500
	V_INTERP_P2_F32 v6, [v6], v1, 1, 1, [m0]                                     ; C8190501
	V_CMP_U_F32_e64 s[2:3], v6, s0, 0, 0, 0, 0                                   ; D0100002 02000106
	V_CMP_GE_F32_e64 s[4:5], v6, s0, 0, 0, 0, 0                                  ; D00C0004 02000106
	S_OR_B64 s[2:3], s[4:5], s[2:3]                                              ; 88820204
	V_CNDMASK_B32_e64 v6, v3, v6, s[2:3], 0, 0, 0, 0                             ; D2000006 000A0D03
	V_CMP_U_F32_e64 s[2:3], v6, s1, 0, 0, 0, 0                                   ; D0100002 02000306
	V_CMP_GE_F32_e64 s[4:5], v6, s1, 0, 0, 0, 0                                  ; D00C0004 02000306
	S_OR_B64 s[2:3], s[4:5], s[2:3]                                              ; 88820204
	V_CNDMASK_B32_e64 v18, v6, v4, s[2:3], 0, 0, 0, 0                            ; D2000012 000A0906
	V_INTERP_P1_F32 v6, v0, 0, 1, [m0]                                           ; C8180400
	V_INTERP_P2_F32 v6, [v6], v1, 0, 1, [m0]                                     ; C8190401
	V_CMP_U_F32_e64 s[2:3], v6, s6, 0, 0, 0, 0                                   ; D0100002 02000D06
	V_CMP_GE_F32_e64 s[4:5], v6, s6, 0, 0, 0, 0                                  ; D00C0004 02000D06
	S_OR_B64 s[2:3], s[4:5], s[2:3]                                              ; 88820204
	V_CNDMASK_B32_e64 v6, v7, v6, s[2:3], 0, 0, 0, 0                             ; D2000006 000A0D07
	V_CMP_U_F32_e64 s[2:3], v6, s8, 0, 0, 0, 0                                   ; D0100002 02001106
	V_CMP_GE_F32_e64 s[4:5], v6, s8, 0, 0, 0, 0                                  ; D00C0004 02001106
	S_OR_B64 s[2:3], s[4:5], s[2:3]                                              ; 88820204
	V_CNDMASK_B32_e64 v17, v6, v8, s[2:3], 0, 0, 0, 0                            ; D2000011 000A1106
	IMAGE_SAMPLE v[17:20], 15, 0, 0, 0, 0, 0, 0, 0, v[17:18], s[16:23], s[12:15] ; F0800F00 00641111
	S_WAITCNT vmcnt(0)                                                           ; BF8C0770
	V_MAD_F32 v5, v20, v2, v5, 0, 0, 0, 0                                        ; D2820005 04160514
	V_INTERP_P1_F32 v6, v0, 3, 1, [m0]                                           ; C8180700
	V_INTERP_P2_F32 v6, [v6], v1, 3, 1, [m0]                                     ; C8190701
	V_CMP_U_F32_e64 s[2:3], v6, s0, 0, 0, 0, 0                                   ; D0100002 02000106
	V_CMP_GE_F32_e64 s[4:5], v6, s0, 0, 0, 0, 0                                  ; D00C0004 02000106
	S_OR_B64 s[2:3], s[4:5], s[2:3]                                              ; 88820204
	V_CNDMASK_B32_e64 v3, v3, v6, s[2:3], 0, 0, 0, 0                             ; D2000003 000A0D03
	V_CMP_U_F32_e64 s[2:3], v3, s1, 0, 0, 0, 0                                   ; D0100002 02000303
	V_CMP_GE_F32_e64 s[0:1], v3, s1, 0, 0, 0, 0                                  ; D00C0000 02000303
	S_OR_B64 s[0:1], s[0:1], s[2:3]                                              ; 88800200
	V_CNDMASK_B32_e64 v4, v3, v4, s[0:1], 0, 0, 0, 0                             ; D2000004 00020903
	V_INTERP_P1_F32 v6, v0, 2, 1, [m0]                                           ; C8180600
	V_INTERP_P2_F32 v6, [v6], v1, 2, 1, [m0]                                     ; C8190601
	V_CMP_U_F32_e64 s[0:1], v6, s6, 0, 0, 0, 0                                   ; D0100000 02000D06
	V_CMP_GE_F32_e64 s[2:3], v6, s6, 0, 0, 0, 0                                  ; D00C0002 02000D06
	S_OR_B64 s[0:1], s[2:3], s[0:1]                                              ; 88800002
	V_CNDMASK_B32_e64 v0, v7, v6, s[0:1], 0, 0, 0, 0                             ; D2000000 00020D07
	V_CMP_U_F32_e64 s[0:1], v0, s8, 0, 0, 0, 0                                   ; D0100000 02001100
	V_CMP_GE_F32_e64 s[2:3], v0, s8, 0, 0, 0, 0                                  ; D00C0002 02001100
	S_OR_B64 s[0:1], s[2:3], s[0:1]                                              ; 88800002
	V_CNDMASK_B32_e64 v3, v0, v8, s[0:1], 0, 0, 0, 0                             ; D2000003 00021100
	IMAGE_SAMPLE v[21:24], 15, 0, 0, 0, 0, 0, 0, 0, v[3:4], s[16:23], s[12:15]   ; F0800F00 00641503
	S_WAITCNT vmcnt(0)                                                           ; BF8C0770
	V_MAD_F32 v0, v24, v2, v5, 0, 0, 0, 0                                        ; D2820000 04160518
	V_MUL_F32_e32 v1, v11, v2                                                    ; 1002050B
	V_MAD_F32 v1, v15, v2, v1, 0, 0, 0, 0                                        ; D2820001 0406050F
	V_MAD_F32 v1, v19, v2, v1, 0, 0, 0, 0                                        ; D2820001 04060513
	V_MAD_F32 v1, v23, v2, v1, 0, 0, 0, 0                                        ; D2820001 04060517
	V_MUL_F32_e32 v3, v10, v2                                                    ; 1006050A
	V_MAD_F32 v3, v14, v2, v3, 0, 0, 0, 0                                        ; D2820003 040E050E
	V_MAD_F32 v3, v18, v2, v3, 0, 0, 0, 0                                        ; D2820003 040E0512
	V_MAD_F32 v3, v22, v2, v3, 0, 0, 0, 0                                        ; D2820003 040E0516
	V_MUL_F32_e32 v4, v9, v2                                                     ; 10080509
	V_MAD_F32 v4, v13, v2, v4, 0, 0, 0, 0                                        ; D2820004 0412050D
	V_MAD_F32 v4, v17, v2, v4, 0, 0, 0, 0                                        ; D2820004 04120511
	V_MAD_F32 v2, v21, v2, v4, 0, 0, 0, 0                                        ; D2820002 04120515
	EXP 15, 0, 0, 1, 1, v2, v3, v1, v0                                           ; F800180F 00010302
	S_ENDPGM                                                                     ; BF810000

VERT
DCL IN[0]
DCL OUT[0], POSITION
DCL OUT[1], CLIPVERTEX
DCL OUT[2], GENERIC[19]
DCL OUT[3], GENERIC[20]
DCL CONST[0..1]
DCL TEMP[0..3], LOCAL
IMM[0] FLT32 {    0.0000,     1.0000,     0.5000,     0.0000}
  0: MOV TEMP[0].zw, IMM[0].yyxy
  1: MOV TEMP[0].xy, IN[0].xyxx
  2: MAD TEMP[1].xy, IN[0].zwww, CONST[0].xyyy, CONST[0].zwww
  3: MUL TEMP[2].xy, CONST[1].xyyy, IMM[0].zzzz
  4: ADD TEMP[1].xy, TEMP[1].xyyy, -TEMP[2].xyyy
  5: MOV TEMP[2].xy, TEMP[1].xyxx
  6: ADD TEMP[1].x, TEMP[1].xxxx, CONST[1].xxxx
  7: MOV TEMP[2].zw, TEMP[1].yyxy
  8: ADD TEMP[3].x, TEMP[1].yyyy, CONST[1].yyyy
  9: MOV TEMP[1].y, TEMP[3].xxxx
 10: MOV TEMP[3].zw, TEMP[1].yyxy
 11: ADD TEMP[1].x, TEMP[1].xxxx, -CONST[1].xxxx
 12: MOV TEMP[3].xy, TEMP[1].xyxx
 13: MOV OUT[2], TEMP[2]
 14: MOV OUT[3], TEMP[3]
 15: MOV OUT[0], TEMP[0]
 16: MOV OUT[1], TEMP[0]
 17: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0)
  %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4)
  %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8)
  %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12)
  %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16)
  %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20)
  %18 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0
  %19 = load <16 x i8> addrspace(2)* %18, !tbaa !0
  %20 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %19, i32 0, i32 %6)
  %21 = extractelement <4 x float> %20, i32 0
  %22 = extractelement <4 x float> %20, i32 1
  %23 = extractelement <4 x float> %20, i32 2
  %24 = extractelement <4 x float> %20, i32 3
  %25 = fmul float %23, %12
  %26 = fadd float %25, %14
  %27 = fmul float %24, %13
  %28 = fadd float %27, %15
  %29 = fmul float %16, 5.000000e-01
  %30 = fmul float %17, 5.000000e-01
  %31 = fsub float -0.000000e+00, %29
  %32 = fadd float %26, %31
  %33 = fsub float -0.000000e+00, %30
  %34 = fadd float %28, %33
  %35 = fadd float %32, %16
  %36 = fadd float %34, %17
  %37 = fsub float -0.000000e+00, %16
  %38 = fadd float %35, %37
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %32, float %34, float %35, float %34)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %38, float %36, float %35, float %36)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %21, float %22, float 0.000000e+00, float 1.000000e+00)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg6

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%21](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%11](align=8)(tbaa=!"const")
	S_WAITCNT 112
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 3; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR4<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR3, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 5; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MUL_F32_e64 %SGPR4, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_SUB_F32_e32 %VGPR4<kill>, %VGPR5<kill>, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 0; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR2, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 4; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e64 %SGPR0, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_SUB_F32_e32 %VGPR5<kill>, %VGPR6<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_ADD_F32_e32 %SGPR0, %VGPR5, %EXEC<imp-use>
	EXP 15, 32, 0, 0, 0, %VGPR5<kill>, %VGPR4, %VGPR6, %VGPR4, %EXEC<imp-use>
	S_WAITCNT 1807
	%VGPR4<def> = V_ADD_F32_e32 %SGPR4<kill>, %VGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_SUBREV_F32_e32 %SGPR0<kill>, %VGPR6, %EXEC<imp-use>
	EXP 15, 33, 0, 0, 0, %VGPR5<kill>, %VGPR4<kill>, %VGPR6<kill>, %VGPR4, %EXEC<imp-use>
	S_WAITCNT 1807
	%VGPR4<def> = V_MOV_B32_e32 1.000000e+00, %EXEC<imp-use>
	%VGPR5<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR1, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_LOAD_DWORDX4 s[4:7], s[6:7], 0               ; C0820700
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	BUFFER_LOAD_FORMAT_XYZW v[0:3], s[4:7][v0] + 0 ; E00C2000 80010000
	S_LOAD_DWORDX4 s[0:3], s[0:1], 0               ; C0800100
	S_WAITCNT vmcnt(0) lgkmcnt(0)                  ; BF8C0070
	S_BUFFER_LOAD_DWORD s4, s[0:3], 3              ; C2020103
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v4, s4                           ; 7E080204
	S_BUFFER_LOAD_DWORD s4, s[0:3], 1              ; C2020101
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v5, s4                           ; 7E0A0204
	V_MAD_F32 v4, v3, v5, v4, 0, 0, 0, 0           ; D2820004 04120B03
	S_BUFFER_LOAD_DWORD s4, s[0:3], 5              ; C2020105
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MUL_F32_e64 v5, s4, 5.000000e-01, 0, 0, 0, 0 ; D2100005 0201E004
	V_SUB_F32_e32 v4, v4, v5                       ; 08080B04
	S_BUFFER_LOAD_DWORD s5, s[0:3], 2              ; C2028102
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v5, s5                           ; 7E0A0205
	S_BUFFER_LOAD_DWORD s5, s[0:3], 0              ; C2028100
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v6, s5                           ; 7E0C0205
	V_MAD_F32 v5, v2, v6, v5, 0, 0, 0, 0           ; D2820005 04160D02
	S_BUFFER_LOAD_DWORD s0, s[0:3], 4              ; C2000104
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MUL_F32_e64 v6, s0, 5.000000e-01, 0, 0, 0, 0 ; D2100006 0201E000
	V_SUB_F32_e32 v5, v5, v6                       ; 080A0D05
	V_ADD_F32_e32 v6, s0, v5                       ; 060C0A00
	EXP 15, 32, 0, 0, 0, v5, v4, v6, v4            ; F800020F 04060405
	S_WAITCNT expcnt(0)                            ; BF8C070F
	V_ADD_F32_e32 v4, s4, v4                       ; 06080804
	V_SUBREV_F32_e32 v5, s0, v6                    ; 0A0A0C00
	EXP 15, 33, 0, 0, 0, v5, v4, v6, v4            ; F800021F 04060405
	S_WAITCNT expcnt(0)                            ; BF8C070F
	V_MOV_B32_e32 v4, 1.000000e+00                 ; 7E0802F2
	V_MOV_B32_e32 v5, 0.000000e+00                 ; 7E0A0280
	EXP 15, 12, 0, 1, 0, v0, v1, v5, v4            ; F80008CF 04050100
	S_ENDPGM                                       ; BF810000

FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %21 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %4)
  %22 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %4)
  %23 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %4)
  %24 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %4)
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %21, float %22, float %23, float %24)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR7 in %vreg4

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR7
	%EXEC<def> = S_WQM_B64 %EXEC
	%M0<def> = S_MOV_B32 %SGPR7
	%VGPR0<def> = V_INTERP_MOV_F32 2, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_INTERP_MOV_F32 2, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_INTERP_MOV_F32 2, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_INTERP_MOV_F32 2, 0, 0, %M0<kill>, %EXEC<imp-use>
	EXP 15, 0, 0, 1, 1, %VGPR3<kill>, %VGPR2<kill>, %VGPR1<kill>, %VGPR0<kill>, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_WQM_B64 exec, exec                ; BEFE0A7E
	S_MOV_B32 m0, s7                    ; BEFC0307
	V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302
	V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202
	V_INTERP_MOV_F32 v2, P0, 1, 0, [m0] ; C80A0102
	V_INTERP_MOV_F32 v3, P0, 0, 0, [m0] ; C80E0002
	EXP 15, 0, 0, 1, 1, v3, v2, v1, v0  ; F800180F 00010203
	S_ENDPGM                            ; BF810000

FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], POSITION, LINEAR
DCL IN[1], GENERIC[19], PERSPECTIVE
DCL IN[2], GENERIC[20], PERSPECTIVE
DCL IN[3], GENERIC[21], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL SAMP[1]
DCL SAMP[2]
DCL SAMP[3]
DCL CONST[8]
DCL CONST[0..3]
DCL TEMP[0]
DCL TEMP[1..5], LOCAL
IMM[0] FLT32 {    0.0000,     0.0000,     2.0000,    -1.0000}
  0: MOV TEMP[0], IN[0]
  1: MAD TEMP[0].y, IN[0], CONST[8].xxxx, CONST[8].yyyy
  2: MOV TEMP[1].xy, IN[1].zwww
  3: TEX TEMP[1].w, TEMP[1], SAMP[2], 2D
  4: MUL TEMP[1].x, TEMP[1].wwww, IN[3].wwww
  5: MUL TEMP[2].x, CONST[0].xxxx, TEMP[1].xxxx
  6: MUL TEMP[1].x, CONST[0].yyyy, TEMP[1].xxxx
  7: DP3 TEMP[3].x, IN[2].xyzz, IN[2].xyzz
  8: RSQ TEMP[3].x, TEMP[3].xxxx
  9: MUL TEMP[3].xyz, IN[2].xyzz, TEMP[3].xxxx
 10: ABS TEMP[4].x, TEMP[3].zzzz
 11: ADD_SAT TEMP[4].x, TEMP[4].xxxx, -CONST[2].zzzz
 12: MAD TEMP[4].x, TEMP[4].xxxx, CONST[2].yyyy, IMM[0].xxxx
 13: POW TEMP[4].x, TEMP[4].xxxx, CONST[2].xxxx
 14: MUL TEMP[1].x, TEMP[1].xxxx, TEMP[4].xxxx
 15: MUL TEMP[2].x, TEMP[2].xxxx, TEMP[4].xxxx
 16: MOV TEMP[4].xy, IN[1].xyyy
 17: TEX TEMP[4], TEMP[4], SAMP[1], 2D
 18: FSLT TEMP[5].x, IMM[0].yyyy, TEMP[4].zzzz
 19: UIF TEMP[5].xxxx :2
 20:   MOV TEMP[5].xy, TEMP[4].ywyy
 21: ELSE :2
 22:   MOV TEMP[5].xy, TEMP[4].xyxx
 23: ENDIF
 24: MAD TEMP[4].xy, TEMP[5].xyyy, IMM[0].zzzz, IMM[0].wwww
 25: MUL TEMP[2].xy, TEMP[2].xxxx, TEMP[3].xyyy
 26: MAD TEMP[1].xy, TEMP[1].xxxx, -TEMP[4].xyyy, TEMP[2].xyyy
 27: MUL TEMP[2].xy, TEMP[0].xyyy, CONST[3].xyyy
 28: MOV TEMP[3].x, -IN[2].wwww
 29: MOV TEMP[4].xy, TEMP[2].xyyy
 30: TEX TEMP[4].x, TEMP[4], SAMP[3], 2D
 31: ABS TEMP[4].x, TEMP[4].xxxx
 32: MAD TEMP[4].x, TEMP[4].xxxx, CONST[3].wwww, -CONST[3].zzzz
 33: ADD TEMP[4].x, TEMP[4].xxxx, TEMP[3].xxxx
 34: MUL_SAT TEMP[4].x, TEMP[4].xxxx, CONST[2].wwww
 35: MUL TEMP[1].xy, TEMP[1].xyyy, TEMP[4].xxxx
 36: ADD_SAT TEMP[2].xy, TEMP[2].xyyy, TEMP[1].xyyy
 37: MOV TEMP[2].xy, TEMP[2].xyyy
 38: TEX TEMP[2].x, TEMP[2], SAMP[3], 2D
 39: ABS TEMP[2].x, TEMP[2].xxxx
 40: MAD TEMP[2].x, TEMP[2].xxxx, CONST[3].wwww, -CONST[3].zzzz
 41: ADD TEMP[2].x, TEMP[2].xxxx, TEMP[3].xxxx
 42: MUL_SAT TEMP[2].x, TEMP[2].xxxx, CONST[2].wwww
 43: MUL TEMP[1].xy, TEMP[1].xyyy, TEMP[2].xxxx
 44: MAD TEMP[1].xy, TEMP[0].xyyy, CONST[0].zwww, TEMP[1].xyyy
 45: MAX TEMP[1].xy, TEMP[1].xyyy, CONST[1].xyyy
 46: MIN TEMP[1].xy, TEMP[1].xyyy, CONST[1].zwww
 47: MOV TEMP[1].xy, TEMP[1].xyyy
 48: TEX TEMP[1], TEMP[1], SAMP[0], 2D
 49: MOV TEMP[2].w, TEMP[1].wwww
 50: MUL TEMP[2].xyz, TEMP[1].xyzz, IN[3].xyzz
 51: MOV OUT[0], TEMP[2]
 52: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %21 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
  %22 = load <16 x i8> addrspace(2)* %21, !tbaa !0
  %23 = call float @llvm.SI.load.const(<16 x i8> %22, i32 0)
  %24 = call float @llvm.SI.load.const(<16 x i8> %22, i32 4)
  %25 = call float @llvm.SI.load.const(<16 x i8> %22, i32 8)
  %26 = call float @llvm.SI.load.const(<16 x i8> %22, i32 12)
  %27 = call float @llvm.SI.load.const(<16 x i8> %22, i32 16)
  %28 = call float @llvm.SI.load.const(<16 x i8> %22, i32 20)
  %29 = call float @llvm.SI.load.const(<16 x i8> %22, i32 24)
  %30 = call float @llvm.SI.load.const(<16 x i8> %22, i32 28)
  %31 = call float @llvm.SI.load.const(<16 x i8> %22, i32 32)
  %32 = call float @llvm.SI.load.const(<16 x i8> %22, i32 36)
  %33 = call float @llvm.SI.load.const(<16 x i8> %22, i32 40)
  %34 = call float @llvm.SI.load.const(<16 x i8> %22, i32 44)
  %35 = call float @llvm.SI.load.const(<16 x i8> %22, i32 48)
  %36 = call float @llvm.SI.load.const(<16 x i8> %22, i32 52)
  %37 = call float @llvm.SI.load.const(<16 x i8> %22, i32 56)
  %38 = call float @llvm.SI.load.const(<16 x i8> %22, i32 60)
  %39 = call float @llvm.SI.load.const(<16 x i8> %22, i32 128)
  %40 = call float @llvm.SI.load.const(<16 x i8> %22, i32 132)
  %41 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0
  %42 = load <32 x i8> addrspace(2)* %41, !tbaa !0
  %43 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0
  %44 = load <16 x i8> addrspace(2)* %43, !tbaa !0
  %45 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 1
  %46 = load <32 x i8> addrspace(2)* %45, !tbaa !0
  %47 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 1
  %48 = load <16 x i8> addrspace(2)* %47, !tbaa !0
  %49 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 2
  %50 = load <32 x i8> addrspace(2)* %49, !tbaa !0
  %51 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 2
  %52 = load <16 x i8> addrspace(2)* %51, !tbaa !0
  %53 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 3
  %54 = load <32 x i8> addrspace(2)* %53, !tbaa !0
  %55 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 3
  %56 = load <16 x i8> addrspace(2)* %55, !tbaa !0
  %57 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %4, <2 x i32> %6)
  %58 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %4, <2 x i32> %6)
  %59 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %4, <2 x i32> %6)
  %60 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %4, <2 x i32> %6)
  %61 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %4, <2 x i32> %6)
  %62 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %4, <2 x i32> %6)
  %63 = call float @llvm.SI.fs.interp(i32 2, i32 1, i32 %4, <2 x i32> %6)
  %64 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %4, <2 x i32> %6)
  %65 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %4, <2 x i32> %6)
  %66 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %4, <2 x i32> %6)
  %67 = call float @llvm.SI.fs.interp(i32 2, i32 2, i32 %4, <2 x i32> %6)
  %68 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %4, <2 x i32> %6)
  %69 = fmul float %14, %39
  %70 = fadd float %69, %40
  %71 = bitcast float %59 to i32
  %72 = bitcast float %60 to i32
  %73 = insertelement <2 x i32> undef, i32 %71, i32 0
  %74 = insertelement <2 x i32> %73, i32 %72, i32 1
  %75 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %74, <32 x i8> %50, <16 x i8> %52, i32 2)
  %76 = extractelement <4 x float> %75, i32 3
  %77 = fmul float %76, %68
  %78 = fmul float %23, %77
  %79 = fmul float %24, %77
  %80 = fmul float %61, %61
  %81 = fmul float %62, %62
  %82 = fadd float %81, %80
  %83 = fmul float %63, %63
  %84 = fadd float %82, %83
  %85 = call float @llvm.AMDGPU.rsq(float %84)
  %86 = fmul float %61, %85
  %87 = fmul float %62, %85
  %88 = fmul float %63, %85
  %89 = call float @fabs(float %88)
  %90 = fsub float -0.000000e+00, %33
  %91 = fadd float %89, %90
  %92 = call float @llvm.AMDIL.clamp.(float %91, float 0.000000e+00, float 1.000000e+00)
  %93 = fmul float %92, %32
  %94 = fadd float %93, 0x3EE4F8B580000000
  %95 = call float @llvm.pow.f32(float %94, float %31)
  %96 = fmul float %79, %95
  %97 = fmul float %78, %95
  %98 = bitcast float %57 to i32
  %99 = bitcast float %58 to i32
  %100 = insertelement <2 x i32> undef, i32 %98, i32 0
  %101 = insertelement <2 x i32> %100, i32 %99, i32 1
  %102 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %101, <32 x i8> %46, <16 x i8> %48, i32 2)
  %103 = extractelement <4 x float> %102, i32 0
  %104 = extractelement <4 x float> %102, i32 1
  %105 = extractelement <4 x float> %102, i32 2
  %106 = extractelement <4 x float> %102, i32 3
  %107 = fcmp olt float 0.000000e+00, %105
  %108 = sext i1 %107 to i32
  %109 = bitcast i32 %108 to float
  %110 = bitcast float %109 to i32
  %111 = icmp ne i32 %110, 0
  %. = select i1 %111, float %104, float %103
  %.24 = select i1 %111, float %106, float %104
  %112 = fmul float %., 2.000000e+00
  %113 = fadd float %112, -1.000000e+00
  %114 = fmul float %.24, 2.000000e+00
  %115 = fadd float %114, -1.000000e+00
  %116 = fmul float %97, %86
  %117 = fmul float %97, %87
  %118 = fsub float -0.000000e+00, %113
  %119 = fmul float %96, %118
  %120 = fadd float %119, %116
  %121 = fsub float -0.000000e+00, %115
  %122 = fmul float %96, %121
  %123 = fadd float %122, %117
  %124 = fmul float %13, %35
  %125 = fmul float %70, %36
  %126 = fsub float -0.000000e+00, %64
  %127 = bitcast float %124 to i32
  %128 = bitcast float %125 to i32
  %129 = insertelement <2 x i32> undef, i32 %127, i32 0
  %130 = insertelement <2 x i32> %129, i32 %128, i32 1
  %131 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %130, <32 x i8> %54, <16 x i8> %56, i32 2)
  %132 = extractelement <4 x float> %131, i32 0
  %133 = call float @fabs(float %132)
  %134 = fsub float -0.000000e+00, %37
  %135 = fmul float %133, %38
  %136 = fadd float %135, %134
  %137 = fadd float %136, %126
  %138 = fmul float %137, %34
  %139 = call float @llvm.AMDIL.clamp.(float %138, float 0.000000e+00, float 1.000000e+00)
  %140 = fmul float %120, %139
  %141 = fmul float %123, %139
  %142 = fadd float %124, %140
  %143 = fadd float %125, %141
  %144 = call float @llvm.AMDIL.clamp.(float %142, float 0.000000e+00, float 1.000000e+00)
  %145 = call float @llvm.AMDIL.clamp.(float %143, float 0.000000e+00, float 1.000000e+00)
  %146 = bitcast float %144 to i32
  %147 = bitcast float %145 to i32
  %148 = insertelement <2 x i32> undef, i32 %146, i32 0
  %149 = insertelement <2 x i32> %148, i32 %147, i32 1
  %150 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %149, <32 x i8> %54, <16 x i8> %56, i32 2)
  %151 = extractelement <4 x float> %150, i32 0
  %152 = call float @fabs(float %151)
  %153 = fsub float -0.000000e+00, %37
  %154 = fmul float %152, %38
  %155 = fadd float %154, %153
  %156 = fadd float %155, %126
  %157 = fmul float %156, %34
  %158 = call float @llvm.AMDIL.clamp.(float %157, float 0.000000e+00, float 1.000000e+00)
  %159 = fmul float %140, %158
  %160 = fmul float %141, %158
  %161 = fmul float %13, %25
  %162 = fadd float %161, %159
  %163 = fmul float %70, %26
  %164 = fadd float %163, %160
  %165 = fcmp uge float %162, %27
  %166 = select i1 %165, float %162, float %27
  %167 = fcmp uge float %164, %28
  %168 = select i1 %167, float %164, float %28
  %169 = fcmp uge float %166, %29
  %170 = select i1 %169, float %29, float %166
  %171 = fcmp uge float %168, %30
  %172 = select i1 %171, float %30, float %168
  %173 = bitcast float %170 to i32
  %174 = bitcast float %172 to i32
  %175 = insertelement <2 x i32> undef, i32 %173, i32 0
  %176 = insertelement <2 x i32> %175, i32 %174, i32 1
  %177 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %176, <32 x i8> %42, <16 x i8> %44, i32 2)
  %178 = extractelement <4 x float> %177, i32 0
  %179 = extractelement <4 x float> %177, i32 1
  %180 = extractelement <4 x float> %177, i32 2
  %181 = extractelement <4 x float> %177, i32 3
  %182 = fmul float %178, %65
  %183 = fmul float %179, %66
  %184 = fmul float %180, %67
  %185 = call i32 @llvm.SI.packf16(float %182, float %183)
  %186 = bitcast i32 %185 to float
  %187 = call i32 @llvm.SI.packf16(float %184, float %181)
  %188 = bitcast i32 %187 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %186, float %188, float %186, float %188)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDGPU.rsq(float) #2

; Function Attrs: readonly
declare float @fabs(float) #3

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

; Function Attrs: nounwind readonly
declare float @llvm.pow.f32(float, float) #4

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }
attributes #3 = { readonly }
attributes #4 = { nounwind readonly }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR7 in %vreg4, %VGPR0 in %vreg5, %VGPR1 in %vreg6, %VGPR2 in %vreg7, %VGPR3 in %vreg8

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR7 %VGPR0 %VGPR1 %VGPR2 %VGPR3
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR7
	%VGPR5<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR4_VGPR5<imp-def>
	%VGPR5<def,tied1> = V_INTERP_P2_F32 %VGPR5<tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
	%VGPR4<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
	%VGPR4<def,tied1> = V_INTERP_P2_F32 %VGPR4<tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 4; mem:LD16[%52](align=8)(tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 8; mem:LD32[%49](tbaa=!"const")
	S_WAITCNT 127
	%VGPR4_VGPR5_VGPR6_VGPR7<def> = IMAGE_SAMPLE_V4_V2 15, 0, 0, 0, 0, 0, 0, 0, %VGPR4_VGPR5<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%SGPR8_SGPR9<def> = V_CMP_GT_F32_e64 %VGPR6, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_CNDMASK_B32_e64 %VGPR5, %VGPR7, %SGPR8_SGPR9, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_ADD_F32_e32 %VGPR8<kill>, %VGPR8, %EXEC<imp-use>
	%VGPR8<def> = V_ADD_F32_e32 -1.000000e+00, %VGPR8<kill>, %EXEC<imp-use>
	%VGPR10<def> = V_INTERP_P1_F32 %VGPR0, 3, 0, %M0<kill>, %EXEC<imp-use>, %VGPR9_VGPR10<imp-def>
	%VGPR10<def,tied1> = V_INTERP_P2_F32 %VGPR10<tied0>, %VGPR1, 3, 0, %M0<kill>, %EXEC<imp-use>, %VGPR9_VGPR10<imp-use,kill>, %VGPR9_VGPR10<imp-def>
	%VGPR9<def> = V_INTERP_P1_F32 %VGPR0, 2, 0, %M0<kill>, %EXEC<imp-use>, %VGPR9_VGPR10<imp-use,kill>, %VGPR9_VGPR10<imp-def>
	%VGPR9<def,tied1> = V_INTERP_P2_F32 %VGPR9<tied0>, %VGPR1, 2, 0, %M0<kill>, %EXEC<imp-use>, %VGPR9_VGPR10<imp-use,kill>, %VGPR9_VGPR10<imp-def>
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 8; mem:LD16[%58](align=8)(tbaa=!"const")
	%SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 16; mem:LD32[%55](tbaa=!"const")
	S_WAITCNT 127
	%VGPR9<def> = IMAGE_SAMPLE_V1_V2 8, 0, 0, 0, 0, 0, 0, 0, %VGPR9_VGPR10<kill>, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23<kill>, %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %EXEC<imp-use>
	%VGPR10<def> = V_INTERP_P1_F32 %VGPR0, 3, 2, %M0<kill>, %EXEC<imp-use>
	%VGPR10<def,tied1> = V_INTERP_P2_F32 %VGPR10<kill,tied0>, %VGPR1, 3, 2, %M0<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR9<def> = V_MUL_F32_e32 %VGPR9<kill>, %VGPR10<kill>, %EXEC<imp-use>
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%22](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 1; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR9, %EXEC<imp-use>
	%VGPR11<def> = V_INTERP_P1_F32 %VGPR0, 1, 1, %M0<kill>, %EXEC<imp-use>
	%VGPR11<def,tied1> = V_INTERP_P2_F32 %VGPR11<kill,tied0>, %VGPR1, 1, 1, %M0<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_INTERP_P1_F32 %VGPR0, 0, 1, %M0<kill>, %EXEC<imp-use>
	%VGPR12<def,tied1> = V_INTERP_P2_F32 %VGPR12<kill,tied0>, %VGPR1, 0, 1, %M0<kill>, %EXEC<imp-use>
	%VGPR13<def> = V_MUL_F32_e32 %VGPR12, %VGPR12, %EXEC<imp-use>
	%VGPR13<def> = V_MAD_F32 %VGPR11, %VGPR11, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR14<def> = V_INTERP_P1_F32 %VGPR0, 2, 1, %M0<kill>, %EXEC<imp-use>
	%VGPR14<def,tied1> = V_INTERP_P2_F32 %VGPR14<kill,tied0>, %VGPR1, 2, 1, %M0<kill>, %EXEC<imp-use>
	%VGPR13<def> = V_MAD_F32 %VGPR14, %VGPR14, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_RSQ_LEGACY_F32_e32 %VGPR13<kill>, %EXEC<imp-use>
	%VGPR14<def> = V_MUL_F32_e32 %VGPR14<kill>, %VGPR13, %EXEC<imp-use>
	%VGPR14<def> = V_ADD_F32_e64 %VGPR14<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 10; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR14<def> = V_SUBREV_F32_e32 %SGPR0<kill>, %VGPR14<kill>, %EXEC<imp-use>
	%VGPR14<def> = V_ADD_F32_e64 0, %VGPR14<kill>, 0, 1, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 9; mem:LD4[<unknown>]
	%VGPR15<def> = V_MOV_B32_e32 1.000000e-05, %EXEC<imp-use>
	S_WAITCNT 127
	%VGPR14<def> = V_MAD_F32 %VGPR14<kill>, %SGPR0<kill>, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR14<def> = V_LOG_F32_e32 %VGPR14<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 8; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR14<def> = V_MUL_LEGACY_F32_e32 %SGPR0<kill>, %VGPR14<kill>, %EXEC<imp-use>
	%VGPR14<def> = V_EXP_F32_e32 %VGPR14<kill>, %EXEC<imp-use>
	%VGPR10<def> = V_MUL_F32_e32 %VGPR10<kill>, %VGPR14, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_F32_e32 %VGPR10, %VGPR8<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 0; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR9<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_MUL_F32_e32 %VGPR9<kill>, %VGPR14<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_MUL_F32_e32 %VGPR11<kill>, %VGPR13, %EXEC<imp-use>
	%VGPR11<def> = V_MUL_F32_e32 %VGPR9, %VGPR11<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_SUB_F32_e32 %VGPR11<kill>, %VGPR8<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_INTERP_P1_F32 %VGPR0, 3, 1, %M0<kill>, %EXEC<imp-use>
	%VGPR11<def,tied1> = V_INTERP_P2_F32 %VGPR11<kill,tied0>, %VGPR1, 3, 1, %M0<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 32; mem:LD4[<unknown>]
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 33; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR14<def> = V_MOV_B32_e32 %SGPR1<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_MAD_F32 %VGPR3<kill>, %SGPR0<kill>, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 13; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR15<def> = V_MUL_F32_e32 %SGPR0, %VGPR3, %EXEC<imp-use>, %VGPR14_VGPR15<imp-def>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 12; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR14<def> = V_MUL_F32_e32 %SGPR1, %VGPR2, %EXEC<imp-use>, %VGPR14_VGPR15<imp-use,kill>, %VGPR14_VGPR15<imp-def>
	%SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 12; mem:LD16[%64](align=8)(tbaa=!"const")
	%SGPR20_SGPR21_SGPR22_SGPR23_SGPR24_SGPR25_SGPR26_SGPR27<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 24; mem:LD32[%61](tbaa=!"const")
	S_WAITCNT 127
	%VGPR14<def> = IMAGE_SAMPLE_V1_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR14_VGPR15<kill>, %SGPR20_SGPR21_SGPR22_SGPR23_SGPR24_SGPR25_SGPR26_SGPR27, %SGPR16_SGPR17_SGPR18_SGPR19, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR14<def> = V_ADD_F32_e64 %VGPR14<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR6<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 15; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR14<def> = V_MUL_F32_e32 %SGPR6, %VGPR14<kill>, %EXEC<imp-use>
	%SGPR10<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 14; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR14<def> = V_SUBREV_F32_e32 %SGPR10, %VGPR14<kill>, %EXEC<imp-use>
	%VGPR14<def> = V_SUB_F32_e32 %VGPR14<kill>, %VGPR11, %EXEC<imp-use>
	%SGPR11<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 11; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR14<def> = V_MUL_F32_e32 %SGPR11, %VGPR14<kill>, %EXEC<imp-use>
	%VGPR14<def> = V_ADD_F32_e64 0, %VGPR14<kill>, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_F32_e32 %VGPR8<kill>, %VGPR14, %EXEC<imp-use>
	%VGPR15<def> = V_MAD_F32 %VGPR3, %SGPR0<kill>, %VGPR8, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR16<def> = V_ADD_F32_e64 0, %VGPR15<kill>, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR15_VGPR16<imp-def>
	%VGPR4<def> = V_CNDMASK_B32_e64 %VGPR4, %VGPR5, %SGPR8_SGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR4_VGPR5_VGPR6_VGPR7<imp-use,kill>
	%VGPR4<def> = V_ADD_F32_e32 %VGPR4<kill>, %VGPR4, %EXEC<imp-use>
	%VGPR4<def> = V_ADD_F32_e32 -1.000000e+00, %VGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e32 %VGPR10<kill>, %VGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MUL_F32_e32 %VGPR12<kill>, %VGPR13<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MUL_F32_e32 %VGPR9<kill>, %VGPR5<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_SUB_F32_e32 %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e32 %VGPR4<kill>, %VGPR14<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR2, %SGPR1<kill>, %VGPR4, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR15<def> = V_ADD_F32_e64 0, %VGPR5<kill>, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR15_VGPR16<imp-use,kill>, %VGPR15_VGPR16<imp-def>
	%VGPR5<def> = IMAGE_SAMPLE_V1_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR15_VGPR16<kill>, %SGPR20_SGPR21_SGPR22_SGPR23_SGPR24_SGPR25_SGPR26_SGPR27<kill>, %SGPR16_SGPR17_SGPR18_SGPR19<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR5<def> = V_ADD_F32_e64 %VGPR5<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_MUL_F32_e32 %SGPR6<kill>, %VGPR5<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_SUBREV_F32_e32 %SGPR10<kill>, %VGPR5<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_SUB_F32_e32 %VGPR5<kill>, %VGPR11<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MUL_F32_e32 %SGPR11<kill>, %VGPR5<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_ADD_F32_e64 0, %VGPR5<kill>, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %VGPR8<kill>, %VGPR5, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 3; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR3<kill>, %SGPR0<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 5; mem:LD4[<unknown>]
	S_WAITCNT 127
	%SGPR8_SGPR9<def> = V_CMP_U_F32_e64 %VGPR3, %SGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR10_SGPR11<def> = V_CMP_GE_F32_e64 %VGPR3, %SGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8_SGPR9<def> = S_OR_B64 %SGPR10_SGPR11<kill>, %SGPR8_SGPR9<kill>
	%VGPR6<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_CNDMASK_B32_e64 %VGPR6<kill>, %VGPR3<kill>, %SGPR8_SGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 7; mem:LD4[<unknown>]
	S_WAITCNT 127
	%SGPR8_SGPR9<def> = V_CMP_U_F32_e64 %VGPR3, %SGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR10_SGPR11<def> = V_CMP_GE_F32_e64 %VGPR3, %SGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8_SGPR9<def> = S_OR_B64 %SGPR10_SGPR11<kill>, %SGPR8_SGPR9<kill>
	%VGPR6<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_CNDMASK_B32_e64 %VGPR3<kill>, %VGPR6<kill>, %SGPR8_SGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR6_VGPR7<imp-def>
	%VGPR3<def> = V_MUL_F32_e32 %VGPR4<kill>, %VGPR5<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 2; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR2<kill>, %SGPR0<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 4; mem:LD4[<unknown>]
	S_WAITCNT 127
	%SGPR8_SGPR9<def> = V_CMP_U_F32_e64 %VGPR2, %SGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR10_SGPR11<def> = V_CMP_GE_F32_e64 %VGPR2, %SGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8_SGPR9<def> = S_OR_B64 %SGPR10_SGPR11<kill>, %SGPR8_SGPR9<kill>
	%VGPR3<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_CNDMASK_B32_e64 %VGPR3<kill>, %VGPR2<kill>, %SGPR8_SGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15<kill>, 6; mem:LD4[<unknown>]
	S_WAITCNT 127
	%SGPR8_SGPR9<def> = V_CMP_U_F32_e64 %VGPR2, %SGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR10_SGPR11<def> = V_CMP_GE_F32_e64 %VGPR2, %SGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8_SGPR9<def> = S_OR_B64 %SGPR10_SGPR11<kill>, %SGPR8_SGPR9<kill>
	%VGPR3<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_CNDMASK_B32_e64 %VGPR2<kill>, %VGPR3<kill>, %SGPR8_SGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR6_VGPR7<imp-use,kill>, %VGPR6_VGPR7<imp-def>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%46](align=8)(tbaa=!"const")
	%SGPR8_SGPR9_SGPR10_SGPR11_SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%43](tbaa=!"const")
	S_WAITCNT 127
	%VGPR2_VGPR3_VGPR4_VGPR5<def> = IMAGE_SAMPLE_V4_V2 15, 0, 0, 0, 0, 0, 0, 0, %VGPR6_VGPR7<kill>, %SGPR8_SGPR9_SGPR10_SGPR11_SGPR12_SGPR13_SGPR14_SGPR15<kill>, %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_INTERP_P1_F32 %VGPR0, 2, 2, %M0<kill>, %EXEC<imp-use>
	%VGPR6<def,tied1> = V_INTERP_P2_F32 %VGPR6<kill,tied0>, %VGPR1, 2, 2, %M0<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR6<def> = V_MUL_F32_e32 %VGPR4, %VGPR6<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR6<kill>, %VGPR5, %EXEC<imp-use>
	%VGPR7<def> = V_INTERP_P1_F32 %VGPR0, 1, 2, %M0<kill>, %EXEC<imp-use>
	%VGPR7<def,tied1> = V_INTERP_P2_F32 %VGPR7<kill,tied0>, %VGPR1, 1, 2, %M0<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MUL_F32_e32 %VGPR3, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_INTERP_P1_F32 %VGPR0, 0, 2, %M0<kill>, %EXEC<imp-use>
	%VGPR8<def,tied1> = V_INTERP_P2_F32 %VGPR8<kill,tied0>, %VGPR1, 0, 2, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR2, %VGPR8<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0<kill>, %VGPR7<kill>, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR0<kill>, %VGPR6<kill>, %VGPR0, %VGPR6, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_WQM_B64 exec, exec                                                    ; BEFE0A7E
	S_MOV_B32 m0, s7                                                        ; BEFC0307
	V_INTERP_P1_F32 v5, v0, 1, 0, [m0]                                      ; C8140100
	V_INTERP_P2_F32 v5, [v5], v1, 1, 0, [m0]                                ; C8150101
	V_INTERP_P1_F32 v4, v0, 0, 0, [m0]                                      ; C8100000
	V_INTERP_P2_F32 v4, [v4], v1, 0, 0, [m0]                                ; C8110001
	S_LOAD_DWORDX4 s[8:11], s[2:3], 4                                       ; C0840304
	S_LOAD_DWORDX8 s[12:19], s[4:5], 8                                      ; C0C60508
	S_WAITCNT lgkmcnt(0)                                                    ; BF8C007F
	IMAGE_SAMPLE v[4:7], 15, 0, 0, 0, 0, 0, 0, 0, v[4:5], s[12:19], s[8:11] ; F0800F00 00430404
	S_WAITCNT vmcnt(0)                                                      ; BF8C0770
	V_CMP_GT_F32_e64 s[8:9], v6, 0.000000e+00, 0, 0, 0, 0                   ; D0080008 02010106
	V_CNDMASK_B32_e64 v8, v5, v7, s[8:9], 0, 0, 0, 0                        ; D2000008 00220F05
	V_ADD_F32_e32 v8, v8, v8                                                ; 06101108
	V_ADD_F32_e32 v8, -1.000000e+00, v8                                     ; 061010F3
	V_INTERP_P1_F32 v10, v0, 3, 0, [m0]                                     ; C8280300
	V_INTERP_P2_F32 v10, [v10], v1, 3, 0, [m0]                              ; C8290301
	V_INTERP_P1_F32 v9, v0, 2, 0, [m0]                                      ; C8240200
	V_INTERP_P2_F32 v9, [v9], v1, 2, 0, [m0]                                ; C8250201
	S_LOAD_DWORDX4 s[12:15], s[2:3], 8                                      ; C0860308
	S_LOAD_DWORDX8 s[16:23], s[4:5], 16                                     ; C0C80510
	S_WAITCNT lgkmcnt(0)                                                    ; BF8C007F
	IMAGE_SAMPLE v9, 8, 0, 0, 0, 0, 0, 0, 0, v[9:10], s[16:23], s[12:15]    ; F0800800 00640909
	V_INTERP_P1_F32 v10, v0, 3, 2, [m0]                                     ; C8280B00
	V_INTERP_P2_F32 v10, [v10], v1, 3, 2, [m0]                              ; C8290B01
	S_WAITCNT vmcnt(0)                                                      ; BF8C0770
	V_MUL_F32_e32 v9, v9, v10                                               ; 10121509
	S_LOAD_DWORDX4 s[12:15], s[0:1], 0                                      ; C0860100
	S_WAITCNT lgkmcnt(0)                                                    ; BF8C007F
	S_BUFFER_LOAD_DWORD s0, s[12:15], 1                                     ; C2000D01
	S_WAITCNT lgkmcnt(0)                                                    ; BF8C007F
	V_MUL_F32_e32 v10, s0, v9                                               ; 10141200
	V_INTERP_P1_F32 v11, v0, 1, 1, [m0]                                     ; C82C0500
	V_INTERP_P2_F32 v11, [v11], v1, 1, 1, [m0]                              ; C82D0501
	V_INTERP_P1_F32 v12, v0, 0, 1, [m0]                                     ; C8300400
	V_INTERP_P2_F32 v12, [v12], v1, 0, 1, [m0]                              ; C8310401
	V_MUL_F32_e32 v13, v12, v12                                             ; 101A190C
	V_MAD_F32 v13, v11, v11, v13, 0, 0, 0, 0                                ; D282000D 0436170B
	V_INTERP_P1_F32 v14, v0, 2, 1, [m0]                                     ; C8380600
	V_INTERP_P2_F32 v14, [v14], v1, 2, 1, [m0]                              ; C8390601
	V_MAD_F32 v13, v14, v14, v13, 0, 0, 0, 0                                ; D282000D 04361D0E
	V_RSQ_LEGACY_F32_e32 v13, v13                                           ; 7E1A5B0D
	V_MUL_F32_e32 v14, v14, v13                                             ; 101C1B0E
	V_ADD_F32_e64 v14, v14, 0, 1, 0, 0, 0                                   ; D206010E 0201010E
	S_BUFFER_LOAD_DWORD s0, s[12:15], 10                                    ; C2000D0A
	S_WAITCNT lgkmcnt(0)                                                    ; BF8C007F
	V_SUBREV_F32_e32 v14, s0, v14                                           ; 0A1C1C00
	V_ADD_F32_e64 v14, 0, v14, 0, 1, 0, 0                                   ; D206080E 02021C80
	S_BUFFER_LOAD_DWORD s0, s[12:15], 9                                     ; C2000D09
	V_MOV_B32_e32 v15, 1.000000e-05                                         ; 7E1E02FF 3727C5AC
	S_WAITCNT lgkmcnt(0)                                                    ; BF8C007F
	V_MAD_F32 v14, v14, s0, v15, 0, 0, 0, 0                                 ; D282000E 043C010E
	V_LOG_F32_e32 v14, v14                                                  ; 7E1C4F0E
	S_BUFFER_LOAD_DWORD s0, s[12:15], 8                                     ; C2000D08
	S_WAITCNT lgkmcnt(0)                                                    ; BF8C007F
	V_MUL_LEGACY_F32_e32 v14, s0, v14                                       ; 0E1C1C00
	V_EXP_F32_e32 v14, v14                                                  ; 7E1C4B0E
	V_MUL_F32_e32 v10, v10, v14                                             ; 10141D0A
	V_MUL_F32_e32 v8, v10, v8                                               ; 1010110A
	S_BUFFER_LOAD_DWORD s0, s[12:15], 0                                     ; C2000D00
	S_WAITCNT lgkmcnt(0)                                                    ; BF8C007F
	V_MUL_F32_e32 v9, s0, v9                                                ; 10121200
	V_MUL_F32_e32 v9, v9, v14                                               ; 10121D09
	V_MUL_F32_e32 v11, v11, v13                                             ; 10161B0B
	V_MUL_F32_e32 v11, v9, v11                                              ; 10161709
	V_SUB_F32_e32 v8, v11, v8                                               ; 0810110B
	V_INTERP_P1_F32 v11, v0, 3, 1, [m0]                                     ; C82C0700
	V_INTERP_P2_F32 v11, [v11], v1, 3, 1, [m0]                              ; C82D0701
	S_BUFFER_LOAD_DWORD s0, s[12:15], 32                                    ; C2000D20
	S_BUFFER_LOAD_DWORD s1, s[12:15], 33                                    ; C2008D21
	S_WAITCNT lgkmcnt(0)                                                    ; BF8C007F
	V_MOV_B32_e32 v14, s1                                                   ; 7E1C0201
	V_MAD_F32 v3, v3, s0, v14, 0, 0, 0, 0                                   ; D2820003 04380103
	S_BUFFER_LOAD_DWORD s0, s[12:15], 13                                    ; C2000D0D
	S_WAITCNT lgkmcnt(0)                                                    ; BF8C007F
	V_MUL_F32_e32 v15, s0, v3                                               ; 101E0600
	S_BUFFER_LOAD_DWORD s1, s[12:15], 12                                    ; C2008D0C
	S_WAITCNT lgkmcnt(0)                                                    ; BF8C007F
	V_MUL_F32_e32 v14, s1, v2                                               ; 101C0401
	S_LOAD_DWORDX4 s[16:19], s[2:3], 12                                     ; C088030C
	S_LOAD_DWORDX8 s[20:27], s[4:5], 24                                     ; C0CA0518
	S_WAITCNT lgkmcnt(0)                                                    ; BF8C007F
	IMAGE_SAMPLE v14, 1, 0, 0, 0, 0, 0, 0, 0, v[14:15], s[20:27], s[16:19]  ; F0800100 00850E0E
	S_WAITCNT vmcnt(0)                                                      ; BF8C0770
	V_ADD_F32_e64 v14, v14, 0, 1, 0, 0, 0                                   ; D206010E 0201010E
	S_BUFFER_LOAD_DWORD s6, s[12:15], 15                                    ; C2030D0F
	S_WAITCNT lgkmcnt(0)                                                    ; BF8C007F
	V_MUL_F32_e32 v14, s6, v14                                              ; 101C1C06
	S_BUFFER_LOAD_DWORD s10, s[12:15], 14                                   ; C2050D0E
	S_WAITCNT lgkmcnt(0)                                                    ; BF8C007F
	V_SUBREV_F32_e32 v14, s10, v14                                          ; 0A1C1C0A
	V_SUB_F32_e32 v14, v14, v11                                             ; 081C170E
	S_BUFFER_LOAD_DWORD s11, s[12:15], 11                                   ; C2058D0B
	S_WAITCNT lgkmcnt(0)                                                    ; BF8C007F
	V_MUL_F32_e32 v14, s11, v14                                             ; 101C1C0B
	V_ADD_F32_e64 v14, 0, v14, 0, 1, 0, 0                                   ; D206080E 02021C80
	V_MUL_F32_e32 v8, v8, v14                                               ; 10101D08
	V_MAD_F32 v15, v3, s0, v8, 0, 0, 0, 0                                   ; D282000F 04200103
	V_ADD_F32_e64 v16, 0, v15, 0, 1, 0, 0                                   ; D2060810 02021E80
	V_CNDMASK_B32_e64 v4, v4, v5, s[8:9], 0, 0, 0, 0                        ; D2000004 00220B04
	V_ADD_F32_e32 v4, v4, v4                                                ; 06080904
	V_ADD_F32_e32 v4, -1.000000e+00, v4                                     ; 060808F3
	V_MUL_F32_e32 v4, v10, v4                                               ; 1008090A
	V_MUL_F32_e32 v5, v12, v13                                              ; 100A1B0C
	V_MUL_F32_e32 v5, v9, v5                                                ; 100A0B09
	V_SUB_F32_e32 v4, v5, v4                                                ; 08080905
	V_MUL_F32_e32 v4, v4, v14                                               ; 10081D04
	V_MAD_F32 v5, v2, s1, v4, 0, 0, 0, 0                                    ; D2820005 04100302
	V_ADD_F32_e64 v15, 0, v5, 0, 1, 0, 0                                    ; D206080F 02020A80
	IMAGE_SAMPLE v5, 1, 0, 0, 0, 0, 0, 0, 0, v[15:16], s[20:27], s[16:19]   ; F0800100 0085050F
	S_WAITCNT vmcnt(0)                                                      ; BF8C0770
	V_ADD_F32_e64 v5, v5, 0, 1, 0, 0, 0                                     ; D2060105 02010105
	V_MUL_F32_e32 v5, s6, v5                                                ; 100A0A06
	V_SUBREV_F32_e32 v5, s10, v5                                            ; 0A0A0A0A
	V_SUB_F32_e32 v5, v5, v11                                               ; 080A1705
	V_MUL_F32_e32 v5, s11, v5                                               ; 100A0A0B
	V_ADD_F32_e64 v5, 0, v5, 0, 1, 0, 0                                     ; D2060805 02020A80
	V_MUL_F32_e32 v6, v8, v5                                                ; 100C0B08
	S_BUFFER_LOAD_DWORD s0, s[12:15], 3                                     ; C2000D03
	S_WAITCNT lgkmcnt(0)                                                    ; BF8C007F
	V_MAD_F32 v3, v3, s0, v6, 0, 0, 0, 0                                    ; D2820003 04180103
	S_BUFFER_LOAD_DWORD s0, s[12:15], 5                                     ; C2000D05
	S_WAITCNT lgkmcnt(0)                                                    ; BF8C007F
	V_CMP_U_F32_e64 s[8:9], v3, s0, 0, 0, 0, 0                              ; D0100008 02000103
	V_CMP_GE_F32_e64 s[10:11], v3, s0, 0, 0, 0, 0                           ; D00C000A 02000103
	S_OR_B64 s[8:9], s[10:11], s[8:9]                                       ; 8888080A
	V_MOV_B32_e32 v6, s0                                                    ; 7E0C0200
	V_CNDMASK_B32_e64 v3, v6, v3, s[8:9], 0, 0, 0, 0                        ; D2000003 00220706
	S_BUFFER_LOAD_DWORD s0, s[12:15], 7                                     ; C2000D07
	S_WAITCNT lgkmcnt(0)                                                    ; BF8C007F
	V_CMP_U_F32_e64 s[8:9], v3, s0, 0, 0, 0, 0                              ; D0100008 02000103
	V_CMP_GE_F32_e64 s[10:11], v3, s0, 0, 0, 0, 0                           ; D00C000A 02000103
	S_OR_B64 s[8:9], s[10:11], s[8:9]                                       ; 8888080A
	V_MOV_B32_e32 v6, s0                                                    ; 7E0C0200
	V_CNDMASK_B32_e64 v7, v3, v6, s[8:9], 0, 0, 0, 0                        ; D2000007 00220D03
	V_MUL_F32_e32 v3, v4, v5                                                ; 10060B04
	S_BUFFER_LOAD_DWORD s0, s[12:15], 2                                     ; C2000D02
	S_WAITCNT lgkmcnt(0)                                                    ; BF8C007F
	V_MAD_F32 v2, v2, s0, v3, 0, 0, 0, 0                                    ; D2820002 040C0102
	S_BUFFER_LOAD_DWORD s0, s[12:15], 4                                     ; C2000D04
	S_WAITCNT lgkmcnt(0)                                                    ; BF8C007F
	V_CMP_U_F32_e64 s[8:9], v2, s0, 0, 0, 0, 0                              ; D0100008 02000102
	V_CMP_GE_F32_e64 s[10:11], v2, s0, 0, 0, 0, 0                           ; D00C000A 02000102
	S_OR_B64 s[8:9], s[10:11], s[8:9]                                       ; 8888080A
	V_MOV_B32_e32 v3, s0                                                    ; 7E060200
	V_CNDMASK_B32_e64 v2, v3, v2, s[8:9], 0, 0, 0, 0                        ; D2000002 00220503
	S_BUFFER_LOAD_DWORD s0, s[12:15], 6                                     ; C2000D06
	S_WAITCNT lgkmcnt(0)                                                    ; BF8C007F
	V_CMP_U_F32_e64 s[8:9], v2, s0, 0, 0, 0, 0                              ; D0100008 02000102
	V_CMP_GE_F32_e64 s[10:11], v2, s0, 0, 0, 0, 0                           ; D00C000A 02000102
	S_OR_B64 s[8:9], s[10:11], s[8:9]                                       ; 8888080A
	V_MOV_B32_e32 v3, s0                                                    ; 7E060200
	V_CNDMASK_B32_e64 v6, v2, v3, s[8:9], 0, 0, 0, 0                        ; D2000006 00220702
	S_LOAD_DWORDX4 s[0:3], s[2:3], 0                                        ; C0800300
	S_LOAD_DWORDX8 s[8:15], s[4:5], 0                                       ; C0C40500
	S_WAITCNT lgkmcnt(0)                                                    ; BF8C007F
	IMAGE_SAMPLE v[2:5], 15, 0, 0, 0, 0, 0, 0, 0, v[6:7], s[8:15], s[0:3]   ; F0800F00 00020206
	V_INTERP_P1_F32 v6, v0, 2, 2, [m0]                                      ; C8180A00
	V_INTERP_P2_F32 v6, [v6], v1, 2, 2, [m0]                                ; C8190A01
	S_WAITCNT vmcnt(0)                                                      ; BF8C0770
	V_MUL_F32_e32 v6, v4, v6                                                ; 100C0D04
	V_CVT_PKRTZ_F16_F32_e32 v6, v6, v5                                      ; 5E0C0B06
	V_INTERP_P1_F32 v7, v0, 1, 2, [m0]                                      ; C81C0900
	V_INTERP_P2_F32 v7, [v7], v1, 1, 2, [m0]                                ; C81D0901
	V_MUL_F32_e32 v7, v3, v7                                                ; 100E0F03
	V_INTERP_P1_F32 v8, v0, 0, 2, [m0]                                      ; C8200800
	V_INTERP_P2_F32 v8, [v8], v1, 0, 2, [m0]                                ; C8210801
	V_MUL_F32_e32 v0, v2, v8                                                ; 10001102
	V_CVT_PKRTZ_F16_F32_e32 v0, v0, v7                                      ; 5E000F00
	EXP 15, 0, 1, 1, 1, v0, v6, v0, v6                                      ; F8001C0F 06000600
	S_ENDPGM                                                                ; BF810000

VERT
DCL IN[0]
DCL IN[1]
DCL IN[2]
DCL IN[3]
DCL IN[4]
DCL IN[5]
DCL IN[6]
DCL OUT[0], POSITION
DCL OUT[1], CLIPVERTEX
DCL OUT[2], GENERIC[19]
DCL OUT[3], GENERIC[20]
DCL OUT[4], GENERIC[21]
DCL CONST[0..240]
DCL TEMP[0..9], LOCAL
DCL ADDR[0]
IMM[0] FLT32 {    0.0010,     1.0000,   255.0100,    -0.1000}
IMM[1] INT32 {3, 41, 42, 43}
  0: MAD TEMP[0].xyz, IN[1].xyzz, CONST[10].zzzz, CONST[10].wwww
  1: MOV TEMP[1].xz, TEMP[0].xxzx
  2: ADD TEMP[0].x, TEMP[0].yyyy, IMM[0].xxxx
  3: MOV TEMP[1].y, TEMP[0].xxxx
  4: MOV TEMP[0], IN[0]
  5: MOV TEMP[2].xyz, TEMP[1].xyzx
  6: UIF CONST[240].xxxx :0
  7:   DP3 TEMP[3].x, IN[4].xyzz, IMM[0].yyyy
  8:   ADD TEMP[3].x, IMM[0].yyyy, -TEMP[3].xxxx
  9:   MUL TEMP[4], IN[3], IMM[0].zzzz
 10:   F2I TEMP[4], TEMP[4]
 11:   UMAD TEMP[5].x, TEMP[4].wwww, IMM[1].xxxx, IMM[1].yyyy
 12:   UMAD TEMP[6].x, TEMP[4].zzzz, IMM[1].xxxx, IMM[1].yyyy
 13:   UMAD TEMP[7].x, TEMP[4].yyyy, IMM[1].xxxx, IMM[1].yyyy
 14:   UMAD TEMP[8].x, TEMP[4].xxxx, IMM[1].xxxx, IMM[1].yyyy
 15:   UARL ADDR[0].x, TEMP[8].xxxx
 16:   MUL TEMP[8], CONST[ADDR[0].x], IN[4].xxxx
 17:   UARL ADDR[0].x, TEMP[7].xxxx
 18:   MAD TEMP[7], CONST[ADDR[0].x], IN[4].yyyy, TEMP[8]
 19:   UARL ADDR[0].x, TEMP[6].xxxx
 20:   MAD TEMP[6], CONST[ADDR[0].x], IN[4].zzzz, TEMP[7]
 21:   UARL ADDR[0].x, TEMP[5].xxxx
 22:   UARL ADDR[0].x, TEMP[5].xxxx
 23:   MAD TEMP[5], CONST[ADDR[0].x], TEMP[3].xxxx, TEMP[6]
 24:   UMAD TEMP[6].x, TEMP[4].wwww, IMM[1].xxxx, IMM[1].zzzz
 25:   UMAD TEMP[7].x, TEMP[4].zzzz, IMM[1].xxxx, IMM[1].zzzz
 26:   UMAD TEMP[8].x, TEMP[4].yyyy, IMM[1].xxxx, IMM[1].zzzz
 27:   UMAD TEMP[9].x, TEMP[4].xxxx, IMM[1].xxxx, IMM[1].zzzz
 28:   UARL ADDR[0].x, TEMP[9].xxxx
 29:   MUL TEMP[9], CONST[ADDR[0].x], IN[4].xxxx
 30:   UARL ADDR[0].x, TEMP[8].xxxx
 31:   MAD TEMP[8], CONST[ADDR[0].x], IN[4].yyyy, TEMP[9]
 32:   UARL ADDR[0].x, TEMP[7].xxxx
 33:   MAD TEMP[7], CONST[ADDR[0].x], IN[4].zzzz, TEMP[8]
 34:   UARL ADDR[0].x, TEMP[6].xxxx
 35:   UARL ADDR[0].x, TEMP[6].xxxx
 36:   MAD TEMP[6], CONST[ADDR[0].x], TEMP[3].xxxx, TEMP[7]
 37:   UMAD TEMP[7].x, TEMP[4].wwww, IMM[1].xxxx, IMM[1].wwww
 38:   UMAD TEMP[8].x, TEMP[4].zzzz, IMM[1].xxxx, IMM[1].wwww
 39:   UMAD TEMP[9].x, TEMP[4].yyyy, IMM[1].xxxx, IMM[1].wwww
 40:   UMAD TEMP[4].x, TEMP[4].xxxx, IMM[1].xxxx, IMM[1].wwww
 41:   UARL ADDR[0].x, TEMP[4].xxxx
 42:   MUL TEMP[4], CONST[ADDR[0].x], IN[4].xxxx
 43:   UARL ADDR[0].x, TEMP[9].xxxx
 44:   MAD TEMP[4], CONST[ADDR[0].x], IN[4].yyyy, TEMP[4]
 45:   UARL ADDR[0].x, TEMP[8].xxxx
 46:   MAD TEMP[4], CONST[ADDR[0].x], IN[4].zzzz, TEMP[4]
 47:   UARL ADDR[0].x, TEMP[7].xxxx
 48:   UARL ADDR[0].x, TEMP[7].xxxx
 49:   MAD TEMP[3], CONST[ADDR[0].x], TEMP[3].xxxx, TEMP[4]
 50:   DP4 TEMP[4].x, IN[0], TEMP[5]
 51:   DP4 TEMP[7].x, IN[0], TEMP[6]
 52:   MOV TEMP[4].y, TEMP[7].xxxx
 53:   DP4 TEMP[7].x, IN[0], TEMP[3]
 54:   MOV TEMP[4].z, TEMP[7].xxxx
 55:   MOV TEMP[0].xyz, TEMP[4].xyzx
 56:   DP3 TEMP[4].x, TEMP[1].xyzz, TEMP[5].xyzz
 57:   DP3 TEMP[5].x, TEMP[1].xyzz, TEMP[6].xyzz
 58:   MOV TEMP[4].y, TEMP[5].xxxx
 59:   DP3 TEMP[1].x, TEMP[1].xyzz, TEMP[3].xyzz
 60:   MOV TEMP[4].z, TEMP[1].xxxx
 61:   MOV TEMP[2].xyz, TEMP[4].xyzx
 62: ENDIF
 63: DP4 TEMP[1].x, TEMP[0], CONST[0]
 64: DP4 TEMP[3].x, TEMP[0], CONST[1]
 65: MOV TEMP[1].y, TEMP[3].xxxx
 66: DP4 TEMP[3].x, TEMP[0], CONST[2]
 67: MOV TEMP[1].z, TEMP[3].xxxx
 68: DP4 TEMP[3].x, TEMP[0], CONST[3]
 69: MOV TEMP[1].w, TEMP[3].xxxx
 70: DP3 TEMP[3].x, TEMP[2].xyzz, CONST[4].xyzz
 71: DP3 TEMP[4].x, TEMP[2].xyzz, CONST[5].xyzz
 72: DP3 TEMP[2].x, TEMP[2].xyzz, CONST[6].xyzz
 73: MOV TEMP[3].z, TEMP[2].xxxx
 74: MOV TEMP[2].xz, TEMP[3].xxzx
 75: MOV TEMP[2].y, -TEMP[4].xxxx
 76: DP4 TEMP[0].x, TEMP[0], CONST[9]
 77: ADD TEMP[0].x, TEMP[0].xxxx, IMM[0].wwww
 78: MOV TEMP[2].w, TEMP[0].xxxx
 79: DP4 TEMP[0].x, IN[2], CONST[7]
 80: DP4 TEMP[3].x, IN[2], CONST[8]
 81: MOV TEMP[0].y, TEMP[3].xxxx
 82: MOV TEMP[0].xy, TEMP[0].xyxx
 83: MOV TEMP[0].zw, IN[5].yyxy
 84: MAD TEMP[3], IN[6].zyxw, CONST[10].xxxx, CONST[10].yyyy
 85: MOV TEMP[4].w, TEMP[3].wwww
 86: MUL TEMP[4].xyz, TEMP[3].xyzz, TEMP[3].xyzz
 87: LRP TEMP[4].xyz, TEMP[3].wwww, TEMP[4].xyzz, IMM[0].yyyy
 88: MOV OUT[2], TEMP[0]
 89: MOV OUT[3], TEMP[2]
 90: MOV OUT[0], TEMP[1]
 91: MOV OUT[4], TEMP[4]
 92: MOV OUT[1], TEMP[1]
 93: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0)
  %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4)
  %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8)
  %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12)
  %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16)
  %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20)
  %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24)
  %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28)
  %20 = call float @llvm.SI.load.const(<16 x i8> %11, i32 32)
  %21 = call float @llvm.SI.load.const(<16 x i8> %11, i32 36)
  %22 = call float @llvm.SI.load.const(<16 x i8> %11, i32 40)
  %23 = call float @llvm.SI.load.const(<16 x i8> %11, i32 44)
  %24 = call float @llvm.SI.load.const(<16 x i8> %11, i32 48)
  %25 = call float @llvm.SI.load.const(<16 x i8> %11, i32 52)
  %26 = call float @llvm.SI.load.const(<16 x i8> %11, i32 56)
  %27 = call float @llvm.SI.load.const(<16 x i8> %11, i32 60)
  %28 = call float @llvm.SI.load.const(<16 x i8> %11, i32 64)
  %29 = call float @llvm.SI.load.const(<16 x i8> %11, i32 68)
  %30 = call float @llvm.SI.load.const(<16 x i8> %11, i32 72)
  %31 = call float @llvm.SI.load.const(<16 x i8> %11, i32 80)
  %32 = call float @llvm.SI.load.const(<16 x i8> %11, i32 84)
  %33 = call float @llvm.SI.load.const(<16 x i8> %11, i32 88)
  %34 = call float @llvm.SI.load.const(<16 x i8> %11, i32 96)
  %35 = call float @llvm.SI.load.const(<16 x i8> %11, i32 100)
  %36 = call float @llvm.SI.load.const(<16 x i8> %11, i32 104)
  %37 = call float @llvm.SI.load.const(<16 x i8> %11, i32 112)
  %38 = call float @llvm.SI.load.const(<16 x i8> %11, i32 116)
  %39 = call float @llvm.SI.load.const(<16 x i8> %11, i32 120)
  %40 = call float @llvm.SI.load.const(<16 x i8> %11, i32 124)
  %41 = call float @llvm.SI.load.const(<16 x i8> %11, i32 128)
  %42 = call float @llvm.SI.load.const(<16 x i8> %11, i32 132)
  %43 = call float @llvm.SI.load.const(<16 x i8> %11, i32 136)
  %44 = call float @llvm.SI.load.const(<16 x i8> %11, i32 140)
  %45 = call float @llvm.SI.load.const(<16 x i8> %11, i32 144)
  %46 = call float @llvm.SI.load.const(<16 x i8> %11, i32 148)
  %47 = call float @llvm.SI.load.const(<16 x i8> %11, i32 152)
  %48 = call float @llvm.SI.load.const(<16 x i8> %11, i32 156)
  %49 = call float @llvm.SI.load.const(<16 x i8> %11, i32 160)
  %50 = call float @llvm.SI.load.const(<16 x i8> %11, i32 164)
  %51 = call float @llvm.SI.load.const(<16 x i8> %11, i32 168)
  %52 = call float @llvm.SI.load.const(<16 x i8> %11, i32 172)
  %53 = call float @llvm.SI.load.const(<16 x i8> %11, i32 3840)
  %54 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0
  %55 = load <16 x i8> addrspace(2)* %54, !tbaa !0
  %56 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %55, i32 0, i32 %6)
  %57 = extractelement <4 x float> %56, i32 0
  %58 = extractelement <4 x float> %56, i32 1
  %59 = extractelement <4 x float> %56, i32 2
  %60 = extractelement <4 x float> %56, i32 3
  %61 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 1
  %62 = load <16 x i8> addrspace(2)* %61, !tbaa !0
  %63 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %62, i32 0, i32 %6)
  %64 = extractelement <4 x float> %63, i32 0
  %65 = extractelement <4 x float> %63, i32 1
  %66 = extractelement <4 x float> %63, i32 2
  %67 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 2
  %68 = load <16 x i8> addrspace(2)* %67, !tbaa !0
  %69 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %68, i32 0, i32 %6)
  %70 = extractelement <4 x float> %69, i32 0
  %71 = extractelement <4 x float> %69, i32 1
  %72 = extractelement <4 x float> %69, i32 2
  %73 = extractelement <4 x float> %69, i32 3
  %74 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 3
  %75 = load <16 x i8> addrspace(2)* %74, !tbaa !0
  %76 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %75, i32 0, i32 %6)
  %77 = extractelement <4 x float> %76, i32 0
  %78 = extractelement <4 x float> %76, i32 1
  %79 = extractelement <4 x float> %76, i32 2
  %80 = extractelement <4 x float> %76, i32 3
  %81 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 4
  %82 = load <16 x i8> addrspace(2)* %81, !tbaa !0
  %83 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %82, i32 0, i32 %6)
  %84 = extractelement <4 x float> %83, i32 0
  %85 = extractelement <4 x float> %83, i32 1
  %86 = extractelement <4 x float> %83, i32 2
  %87 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 5
  %88 = load <16 x i8> addrspace(2)* %87, !tbaa !0
  %89 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %88, i32 0, i32 %6)
  %90 = extractelement <4 x float> %89, i32 0
  %91 = extractelement <4 x float> %89, i32 1
  %92 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 6
  %93 = load <16 x i8> addrspace(2)* %92, !tbaa !0
  %94 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %93, i32 0, i32 %6)
  %95 = extractelement <4 x float> %94, i32 0
  %96 = extractelement <4 x float> %94, i32 1
  %97 = extractelement <4 x float> %94, i32 2
  %98 = extractelement <4 x float> %94, i32 3
  %99 = fmul float %64, %51
  %100 = fadd float %99, %52
  %101 = fmul float %65, %51
  %102 = fadd float %101, %52
  %103 = fmul float %66, %51
  %104 = fadd float %103, %52
  %105 = fadd float %102, 0x3F50624DE0000000
  %106 = bitcast float %53 to i32
  %107 = icmp ne i32 %106, 0
  br i1 %107, label %IF, label %ENDIF

IF:                                               ; preds = %main_body
  %108 = fmul float %84, 1.000000e+00
  %109 = fmul float %85, 1.000000e+00
  %110 = fadd float %109, %108
  %111 = fmul float %86, 1.000000e+00
  %112 = fadd float %110, %111
  %113 = fsub float -0.000000e+00, %112
  %114 = fadd float 1.000000e+00, %113
  %115 = fmul float %77, 0x406FE051E0000000
  %116 = fmul float %78, 0x406FE051E0000000
  %117 = fmul float %79, 0x406FE051E0000000
  %118 = fmul float %80, 0x406FE051E0000000
  %119 = fptosi float %115 to i32
  %120 = fptosi float %116 to i32
  %121 = fptosi float %117 to i32
  %122 = fptosi float %118 to i32
  %123 = bitcast i32 %119 to float
  %124 = bitcast i32 %120 to float
  %125 = bitcast i32 %121 to float
  %126 = bitcast i32 %122 to float
  %127 = bitcast float %126 to i32
  %128 = mul i32 %127, 3
  %129 = add i32 %128, 41
  %130 = bitcast i32 %129 to float
  %131 = bitcast float %125 to i32
  %132 = mul i32 %131, 3
  %133 = add i32 %132, 41
  %134 = bitcast i32 %133 to float
  %135 = bitcast float %124 to i32
  %136 = mul i32 %135, 3
  %137 = add i32 %136, 41
  %138 = bitcast i32 %137 to float
  %139 = bitcast float %123 to i32
  %140 = mul i32 %139, 3
  %141 = add i32 %140, 41
  %142 = bitcast i32 %141 to float
  %143 = bitcast float %142 to i32
  %144 = shl i32 %143, 4
  %145 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %144)
  %146 = fmul float %145, %84
  %147 = shl i32 %143, 4
  %148 = add i32 %147, 4
  %149 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %148)
  %150 = fmul float %149, %84
  %151 = shl i32 %143, 4
  %152 = add i32 %151, 8
  %153 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %152)
  %154 = fmul float %153, %84
  %155 = shl i32 %143, 4
  %156 = add i32 %155, 12
  %157 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %156)
  %158 = fmul float %157, %84
  %159 = bitcast float %138 to i32
  %160 = shl i32 %159, 4
  %161 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %160)
  %162 = fmul float %161, %85
  %163 = fadd float %162, %146
  %164 = shl i32 %159, 4
  %165 = add i32 %164, 4
  %166 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %165)
  %167 = fmul float %166, %85
  %168 = fadd float %167, %150
  %169 = shl i32 %159, 4
  %170 = add i32 %169, 8
  %171 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %170)
  %172 = fmul float %171, %85
  %173 = fadd float %172, %154
  %174 = shl i32 %159, 4
  %175 = add i32 %174, 12
  %176 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %175)
  %177 = fmul float %176, %85
  %178 = fadd float %177, %158
  %179 = bitcast float %134 to i32
  %180 = shl i32 %179, 4
  %181 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %180)
  %182 = fmul float %181, %86
  %183 = fadd float %182, %163
  %184 = shl i32 %179, 4
  %185 = add i32 %184, 4
  %186 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %185)
  %187 = fmul float %186, %86
  %188 = fadd float %187, %168
  %189 = shl i32 %179, 4
  %190 = add i32 %189, 8
  %191 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %190)
  %192 = fmul float %191, %86
  %193 = fadd float %192, %173
  %194 = shl i32 %179, 4
  %195 = add i32 %194, 12
  %196 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %195)
  %197 = fmul float %196, %86
  %198 = fadd float %197, %178
  %199 = bitcast float %130 to i32
  %200 = shl i32 %199, 4
  %201 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %200)
  %202 = fmul float %201, %114
  %203 = fadd float %202, %183
  %204 = shl i32 %199, 4
  %205 = add i32 %204, 4
  %206 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %205)
  %207 = fmul float %206, %114
  %208 = fadd float %207, %188
  %209 = shl i32 %199, 4
  %210 = add i32 %209, 8
  %211 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %210)
  %212 = fmul float %211, %114
  %213 = fadd float %212, %193
  %214 = shl i32 %199, 4
  %215 = add i32 %214, 12
  %216 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %215)
  %217 = fmul float %216, %114
  %218 = fadd float %217, %198
  %219 = bitcast float %126 to i32
  %220 = mul i32 %219, 3
  %221 = add i32 %220, 42
  %222 = bitcast i32 %221 to float
  %223 = bitcast float %125 to i32
  %224 = mul i32 %223, 3
  %225 = add i32 %224, 42
  %226 = bitcast i32 %225 to float
  %227 = bitcast float %124 to i32
  %228 = mul i32 %227, 3
  %229 = add i32 %228, 42
  %230 = bitcast i32 %229 to float
  %231 = bitcast float %123 to i32
  %232 = mul i32 %231, 3
  %233 = add i32 %232, 42
  %234 = bitcast i32 %233 to float
  %235 = bitcast float %234 to i32
  %236 = shl i32 %235, 4
  %237 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %236)
  %238 = fmul float %237, %84
  %239 = shl i32 %235, 4
  %240 = add i32 %239, 4
  %241 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %240)
  %242 = fmul float %241, %84
  %243 = shl i32 %235, 4
  %244 = add i32 %243, 8
  %245 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %244)
  %246 = fmul float %245, %84
  %247 = shl i32 %235, 4
  %248 = add i32 %247, 12
  %249 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %248)
  %250 = fmul float %249, %84
  %251 = bitcast float %230 to i32
  %252 = shl i32 %251, 4
  %253 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %252)
  %254 = fmul float %253, %85
  %255 = fadd float %254, %238
  %256 = shl i32 %251, 4
  %257 = add i32 %256, 4
  %258 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %257)
  %259 = fmul float %258, %85
  %260 = fadd float %259, %242
  %261 = shl i32 %251, 4
  %262 = add i32 %261, 8
  %263 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %262)
  %264 = fmul float %263, %85
  %265 = fadd float %264, %246
  %266 = shl i32 %251, 4
  %267 = add i32 %266, 12
  %268 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %267)
  %269 = fmul float %268, %85
  %270 = fadd float %269, %250
  %271 = bitcast float %226 to i32
  %272 = shl i32 %271, 4
  %273 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %272)
  %274 = fmul float %273, %86
  %275 = fadd float %274, %255
  %276 = shl i32 %271, 4
  %277 = add i32 %276, 4
  %278 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %277)
  %279 = fmul float %278, %86
  %280 = fadd float %279, %260
  %281 = shl i32 %271, 4
  %282 = add i32 %281, 8
  %283 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %282)
  %284 = fmul float %283, %86
  %285 = fadd float %284, %265
  %286 = shl i32 %271, 4
  %287 = add i32 %286, 12
  %288 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %287)
  %289 = fmul float %288, %86
  %290 = fadd float %289, %270
  %291 = bitcast float %222 to i32
  %292 = shl i32 %291, 4
  %293 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %292)
  %294 = fmul float %293, %114
  %295 = fadd float %294, %275
  %296 = shl i32 %291, 4
  %297 = add i32 %296, 4
  %298 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %297)
  %299 = fmul float %298, %114
  %300 = fadd float %299, %280
  %301 = shl i32 %291, 4
  %302 = add i32 %301, 8
  %303 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %302)
  %304 = fmul float %303, %114
  %305 = fadd float %304, %285
  %306 = shl i32 %291, 4
  %307 = add i32 %306, 12
  %308 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %307)
  %309 = fmul float %308, %114
  %310 = fadd float %309, %290
  %311 = bitcast float %126 to i32
  %312 = mul i32 %311, 3
  %313 = add i32 %312, 43
  %314 = bitcast i32 %313 to float
  %315 = bitcast float %125 to i32
  %316 = mul i32 %315, 3
  %317 = add i32 %316, 43
  %318 = bitcast i32 %317 to float
  %319 = bitcast float %124 to i32
  %320 = mul i32 %319, 3
  %321 = add i32 %320, 43
  %322 = bitcast i32 %321 to float
  %323 = bitcast float %123 to i32
  %324 = mul i32 %323, 3
  %325 = add i32 %324, 43
  %326 = bitcast i32 %325 to float
  %327 = bitcast float %326 to i32
  %328 = shl i32 %327, 4
  %329 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %328)
  %330 = fmul float %329, %84
  %331 = shl i32 %327, 4
  %332 = add i32 %331, 4
  %333 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %332)
  %334 = fmul float %333, %84
  %335 = shl i32 %327, 4
  %336 = add i32 %335, 8
  %337 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %336)
  %338 = fmul float %337, %84
  %339 = shl i32 %327, 4
  %340 = add i32 %339, 12
  %341 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %340)
  %342 = fmul float %341, %84
  %343 = bitcast float %322 to i32
  %344 = shl i32 %343, 4
  %345 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %344)
  %346 = fmul float %345, %85
  %347 = fadd float %346, %330
  %348 = shl i32 %343, 4
  %349 = add i32 %348, 4
  %350 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %349)
  %351 = fmul float %350, %85
  %352 = fadd float %351, %334
  %353 = shl i32 %343, 4
  %354 = add i32 %353, 8
  %355 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %354)
  %356 = fmul float %355, %85
  %357 = fadd float %356, %338
  %358 = shl i32 %343, 4
  %359 = add i32 %358, 12
  %360 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %359)
  %361 = fmul float %360, %85
  %362 = fadd float %361, %342
  %363 = bitcast float %318 to i32
  %364 = shl i32 %363, 4
  %365 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %364)
  %366 = fmul float %365, %86
  %367 = fadd float %366, %347
  %368 = shl i32 %363, 4
  %369 = add i32 %368, 4
  %370 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %369)
  %371 = fmul float %370, %86
  %372 = fadd float %371, %352
  %373 = shl i32 %363, 4
  %374 = add i32 %373, 8
  %375 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %374)
  %376 = fmul float %375, %86
  %377 = fadd float %376, %357
  %378 = shl i32 %363, 4
  %379 = add i32 %378, 12
  %380 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %379)
  %381 = fmul float %380, %86
  %382 = fadd float %381, %362
  %383 = bitcast float %314 to i32
  %384 = shl i32 %383, 4
  %385 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %384)
  %386 = fmul float %385, %114
  %387 = fadd float %386, %367
  %388 = shl i32 %383, 4
  %389 = add i32 %388, 4
  %390 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %389)
  %391 = fmul float %390, %114
  %392 = fadd float %391, %372
  %393 = shl i32 %383, 4
  %394 = add i32 %393, 8
  %395 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %394)
  %396 = fmul float %395, %114
  %397 = fadd float %396, %377
  %398 = shl i32 %383, 4
  %399 = add i32 %398, 12
  %400 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %399)
  %401 = fmul float %400, %114
  %402 = fadd float %401, %382
  %403 = fmul float %57, %203
  %404 = fmul float %58, %208
  %405 = fadd float %403, %404
  %406 = fmul float %59, %213
  %407 = fadd float %405, %406
  %408 = fmul float %60, %218
  %409 = fadd float %407, %408
  %410 = fmul float %57, %295
  %411 = fmul float %58, %300
  %412 = fadd float %410, %411
  %413 = fmul float %59, %305
  %414 = fadd float %412, %413
  %415 = fmul float %60, %310
  %416 = fadd float %414, %415
  %417 = fmul float %57, %387
  %418 = fmul float %58, %392
  %419 = fadd float %417, %418
  %420 = fmul float %59, %397
  %421 = fadd float %419, %420
  %422 = fmul float %60, %402
  %423 = fadd float %421, %422
  %424 = fmul float %100, %203
  %425 = fmul float %105, %208
  %426 = fadd float %425, %424
  %427 = fmul float %104, %213
  %428 = fadd float %426, %427
  %429 = fmul float %100, %295
  %430 = fmul float %105, %300
  %431 = fadd float %430, %429
  %432 = fmul float %104, %305
  %433 = fadd float %431, %432
  %434 = fmul float %100, %387
  %435 = fmul float %105, %392
  %436 = fadd float %435, %434
  %437 = fmul float %104, %397
  %438 = fadd float %436, %437
  br label %ENDIF

ENDIF:                                            ; preds = %main_body, %IF
  %temp.0 = phi float [ %409, %IF ], [ %57, %main_body ]
  %temp1.0 = phi float [ %416, %IF ], [ %58, %main_body ]
  %temp2.0 = phi float [ %423, %IF ], [ %59, %main_body ]
  %temp8.0 = phi float [ %428, %IF ], [ %100, %main_body ]
  %temp9.0 = phi float [ %433, %IF ], [ %105, %main_body ]
  %temp10.0 = phi float [ %438, %IF ], [ %104, %main_body ]
  %439 = fmul float %temp.0, %12
  %440 = fmul float %temp1.0, %13
  %441 = fadd float %439, %440
  %442 = fmul float %temp2.0, %14
  %443 = fadd float %441, %442
  %444 = fmul float %60, %15
  %445 = fadd float %443, %444
  %446 = fmul float %temp.0, %16
  %447 = fmul float %temp1.0, %17
  %448 = fadd float %446, %447
  %449 = fmul float %temp2.0, %18
  %450 = fadd float %448, %449
  %451 = fmul float %60, %19
  %452 = fadd float %450, %451
  %453 = fmul float %temp.0, %20
  %454 = fmul float %temp1.0, %21
  %455 = fadd float %453, %454
  %456 = fmul float %temp2.0, %22
  %457 = fadd float %455, %456
  %458 = fmul float %60, %23
  %459 = fadd float %457, %458
  %460 = fmul float %temp.0, %24
  %461 = fmul float %temp1.0, %25
  %462 = fadd float %460, %461
  %463 = fmul float %temp2.0, %26
  %464 = fadd float %462, %463
  %465 = fmul float %60, %27
  %466 = fadd float %464, %465
  %467 = fmul float %temp8.0, %28
  %468 = fmul float %temp9.0, %29
  %469 = fadd float %468, %467
  %470 = fmul float %temp10.0, %30
  %471 = fadd float %469, %470
  %472 = fmul float %temp8.0, %31
  %473 = fmul float %temp9.0, %32
  %474 = fadd float %473, %472
  %475 = fmul float %temp10.0, %33
  %476 = fadd float %474, %475
  %477 = fmul float %temp8.0, %34
  %478 = fmul float %temp9.0, %35
  %479 = fadd float %478, %477
  %480 = fmul float %temp10.0, %36
  %481 = fadd float %479, %480
  %482 = fsub float -0.000000e+00, %476
  %483 = fmul float %temp.0, %45
  %484 = fmul float %temp1.0, %46
  %485 = fadd float %483, %484
  %486 = fmul float %temp2.0, %47
  %487 = fadd float %485, %486
  %488 = fmul float %60, %48
  %489 = fadd float %487, %488
  %490 = fadd float %489, 0xBFB99999A0000000
  %491 = fmul float %70, %37
  %492 = fmul float %71, %38
  %493 = fadd float %491, %492
  %494 = fmul float %72, %39
  %495 = fadd float %493, %494
  %496 = fmul float %73, %40
  %497 = fadd float %495, %496
  %498 = fmul float %70, %41
  %499 = fmul float %71, %42
  %500 = fadd float %498, %499
  %501 = fmul float %72, %43
  %502 = fadd float %500, %501
  %503 = fmul float %73, %44
  %504 = fadd float %502, %503
  %505 = fmul float %97, %49
  %506 = fadd float %505, %50
  %507 = fmul float %96, %49
  %508 = fadd float %507, %50
  %509 = fmul float %95, %49
  %510 = fadd float %509, %50
  %511 = fmul float %98, %49
  %512 = fadd float %511, %50
  %513 = fmul float %506, %506
  %514 = fmul float %508, %508
  %515 = fmul float %510, %510
  %516 = call float @llvm.AMDGPU.lrp(float %512, float %513, float 1.000000e+00)
  %517 = call float @llvm.AMDGPU.lrp(float %512, float %514, float 1.000000e+00)
  %518 = call float @llvm.AMDGPU.lrp(float %512, float %515, float 1.000000e+00)
  %519 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 16
  %520 = load <16 x i8> addrspace(2)* %519, !tbaa !0
  %521 = call float @llvm.SI.load.const(<16 x i8> %520, i32 0)
  %522 = fmul float %521, %445
  %523 = call float @llvm.SI.load.const(<16 x i8> %520, i32 4)
  %524 = fmul float %523, %452
  %525 = fadd float %522, %524
  %526 = call float @llvm.SI.load.const(<16 x i8> %520, i32 8)
  %527 = fmul float %526, %459
  %528 = fadd float %525, %527
  %529 = call float @llvm.SI.load.const(<16 x i8> %520, i32 12)
  %530 = fmul float %529, %466
  %531 = fadd float %528, %530
  %532 = call float @llvm.SI.load.const(<16 x i8> %520, i32 16)
  %533 = fmul float %532, %445
  %534 = call float @llvm.SI.load.const(<16 x i8> %520, i32 20)
  %535 = fmul float %534, %452
  %536 = fadd float %533, %535
  %537 = call float @llvm.SI.load.const(<16 x i8> %520, i32 24)
  %538 = fmul float %537, %459
  %539 = fadd float %536, %538
  %540 = call float @llvm.SI.load.const(<16 x i8> %520, i32 28)
  %541 = fmul float %540, %466
  %542 = fadd float %539, %541
  %543 = call float @llvm.SI.load.const(<16 x i8> %520, i32 32)
  %544 = fmul float %543, %445
  %545 = call float @llvm.SI.load.const(<16 x i8> %520, i32 36)
  %546 = fmul float %545, %452
  %547 = fadd float %544, %546
  %548 = call float @llvm.SI.load.const(<16 x i8> %520, i32 40)
  %549 = fmul float %548, %459
  %550 = fadd float %547, %549
  %551 = call float @llvm.SI.load.const(<16 x i8> %520, i32 44)
  %552 = fmul float %551, %466
  %553 = fadd float %550, %552
  %554 = call float @llvm.SI.load.const(<16 x i8> %520, i32 48)
  %555 = fmul float %554, %445
  %556 = call float @llvm.SI.load.const(<16 x i8> %520, i32 52)
  %557 = fmul float %556, %452
  %558 = fadd float %555, %557
  %559 = call float @llvm.SI.load.const(<16 x i8> %520, i32 56)
  %560 = fmul float %559, %459
  %561 = fadd float %558, %560
  %562 = call float @llvm.SI.load.const(<16 x i8> %520, i32 60)
  %563 = fmul float %562, %466
  %564 = fadd float %561, %563
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %497, float %504, float %90, float %91)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %471, float %482, float %481, float %490)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %516, float %517, float %518, float %512)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 12, i32 0, float %445, float %452, float %459, float %466)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 13, i32 0, float %531, float %542, float %553, float %564)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDGPU.lrp(float, float, float) #2

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg63, %SGPR6_SGPR7 in %vreg66, %VGPR0 in %vreg69

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%66](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%VGPR18_VGPR19_VGPR20_VGPR21<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1, 0; mem:LD16[%11](align=8)(tbaa=!"const")
	S_WAITCNT 112
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 43; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR22<def> = V_MOV_B32_e32 %SGPR2<kill>, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 42; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR23<def> = V_MOV_B32_e32 %SGPR2<kill>, %EXEC<imp-use>
	%VGPR36<def> = V_MAD_F32 %VGPR20, %VGPR23, %VGPR22, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_MAD_F32 %VGPR18, %VGPR23, %VGPR22, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 24; mem:LD16[%84](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%VGPR5_VGPR6_VGPR7_VGPR8<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %VGPR0, 0, %EXEC<imp-use>
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 20; mem:LD16[%79](align=8)(tbaa=!"const")
	S_WAITCNT 112
	%VGPR9_VGPR10_VGPR11_VGPR12<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %VGPR0, 0, %EXEC<imp-use>
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 8; mem:LD16[%74](align=8)(tbaa=!"const")
	S_WAITCNT 112
	%VGPR14_VGPR15_VGPR16_VGPR17<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %VGPR0, 0, %EXEC<imp-use>
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 0; mem:LD16[%57](align=8)(tbaa=!"const")
	S_WAITCNT 112
	%VGPR1_VGPR2_VGPR3_VGPR4<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %VGPR0, 0, %EXEC<imp-use>
	%VGPR18<def> = V_MAD_F32 %VGPR19, %VGPR23<kill>, %VGPR22<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR18_VGPR19_VGPR20_VGPR21<imp-use,kill>
	%VGPR56<def> = V_ADD_F32_e32 1.000000e-03, %VGPR18<kill>, %EXEC<imp-use>
	%SGPR2<def> = S_MOV_B32 3840
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_SGPR %SGPR8_SGPR9_SGPR10_SGPR11, %SGPR2<kill>; mem:LD4[<unknown>]
	S_WAITCNT 112
	%SGPR4_SGPR5<def> = V_CMP_NE_I32_e64 %SGPR2<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 41; mem:LD4[<unknown>]
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 40; mem:LD4[<unknown>]
	%SGPR12<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 39; mem:LD4[<unknown>]
	%SGPR13<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 38; mem:LD4[<unknown>]
	%SGPR14<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 37; mem:LD4[<unknown>]
	%SGPR15<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 36; mem:LD4[<unknown>]
	%SGPR16<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 35; mem:LD4[<unknown>]
	%SGPR17<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 34; mem:LD4[<unknown>]
	%SGPR18<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 33; mem:LD4[<unknown>]
	%SGPR19<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 32; mem:LD4[<unknown>]
	%SGPR20<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 31; mem:LD4[<unknown>]
	%SGPR21<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 30; mem:LD4[<unknown>]
	%SGPR22<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 29; mem:LD4[<unknown>]
	%SGPR23<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 28; mem:LD4[<unknown>]
	%SGPR24<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 26; mem:LD4[<unknown>]
	%SGPR25<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 25; mem:LD4[<unknown>]
	%SGPR26<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 24; mem:LD4[<unknown>]
	%SGPR27<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 22; mem:LD4[<unknown>]
	%SGPR28<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 21; mem:LD4[<unknown>]
	%SGPR29<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 20; mem:LD4[<unknown>]
	%SGPR30<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 18; mem:LD4[<unknown>]
	%SGPR31<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 17; mem:LD4[<unknown>]
	%SGPR32<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 16; mem:LD4[<unknown>]
	%SGPR33<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 15; mem:LD4[<unknown>]
	%SGPR34<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 14; mem:LD4[<unknown>]
	%SGPR35<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 13; mem:LD4[<unknown>]
	%SGPR36<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 12; mem:LD4[<unknown>]
	%SGPR37<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 11; mem:LD4[<unknown>]
	%SGPR38<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 10; mem:LD4[<unknown>]
	%SGPR39<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 9; mem:LD4[<unknown>]
	%SGPR40<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 8; mem:LD4[<unknown>]
	%SGPR41<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 7; mem:LD4[<unknown>]
	%SGPR42<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 6; mem:LD4[<unknown>]
	%SGPR43<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 5; mem:LD4[<unknown>]
	%SGPR44<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 4; mem:LD4[<unknown>]
	%SGPR45<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 3; mem:LD4[<unknown>]
	%SGPR46<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 2; mem:LD4[<unknown>]
	%SGPR47<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 1; mem:LD4[<unknown>]
	%SGPR48<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 0; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR26<def> = V_MOV_B32_e32 %SGPR12<kill>, %EXEC<imp-use>
	%VGPR35<def> = V_MOV_B32_e32 %SGPR13<kill>, %EXEC<imp-use>
	%VGPR38<def> = V_MOV_B32_e32 %SGPR14<kill>, %EXEC<imp-use>
	%VGPR37<def> = V_MOV_B32_e32 %SGPR15<kill>, %EXEC<imp-use>
	%VGPR45<def> = V_MOV_B32_e32 %SGPR16<kill>, %EXEC<imp-use>
	%VGPR50<def> = V_MOV_B32_e32 %SGPR17<kill>, %EXEC<imp-use>
	%VGPR55<def> = V_MOV_B32_e32 %SGPR18<kill>, %EXEC<imp-use>
	%VGPR54<def> = V_MOV_B32_e32 %SGPR19<kill>, %EXEC<imp-use>
	%VGPR44<def> = V_MOV_B32_e32 %SGPR20<kill>, %EXEC<imp-use>
	%VGPR48<def> = V_MOV_B32_e32 %SGPR21<kill>, %EXEC<imp-use>
	%VGPR53<def> = V_MOV_B32_e32 %SGPR22<kill>, %EXEC<imp-use>
	%VGPR52<def> = V_MOV_B32_e32 %SGPR23<kill>, %EXEC<imp-use>
	%VGPR41<def> = V_MOV_B32_e32 %SGPR24<kill>, %EXEC<imp-use>
	%VGPR43<def> = V_MOV_B32_e32 %SGPR25<kill>, %EXEC<imp-use>
	%VGPR47<def> = V_MOV_B32_e32 %SGPR26<kill>, %EXEC<imp-use>
	%VGPR39<def> = V_MOV_B32_e32 %SGPR27<kill>, %EXEC<imp-use>
	%VGPR40<def> = V_MOV_B32_e32 %SGPR28<kill>, %EXEC<imp-use>
	%VGPR42<def> = V_MOV_B32_e32 %SGPR29<kill>, %EXEC<imp-use>
	%VGPR46<def> = V_MOV_B32_e32 %SGPR30<kill>, %EXEC<imp-use>
	%VGPR49<def> = V_MOV_B32_e32 %SGPR31<kill>, %EXEC<imp-use>
	%VGPR51<def> = V_MOV_B32_e32 %SGPR32<kill>, %EXEC<imp-use>
	%VGPR21<def> = V_MOV_B32_e32 %SGPR33<kill>, %EXEC<imp-use>
	%VGPR25<def> = V_MOV_B32_e32 %SGPR34<kill>, %EXEC<imp-use>
	%VGPR34<def> = V_MOV_B32_e32 %SGPR35<kill>, %EXEC<imp-use>
	%VGPR33<def> = V_MOV_B32_e32 %SGPR36<kill>, %EXEC<imp-use>
	%VGPR20<def> = V_MOV_B32_e32 %SGPR37<kill>, %EXEC<imp-use>
	%VGPR24<def> = V_MOV_B32_e32 %SGPR38<kill>, %EXEC<imp-use>
	%VGPR32<def> = V_MOV_B32_e32 %SGPR39<kill>, %EXEC<imp-use>
	%VGPR31<def> = V_MOV_B32_e32 %SGPR40<kill>, %EXEC<imp-use>
	%VGPR19<def> = V_MOV_B32_e32 %SGPR41<kill>, %EXEC<imp-use>
	%VGPR23<def> = V_MOV_B32_e32 %SGPR42<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_MOV_B32_e32 %SGPR43<kill>, %EXEC<imp-use>
	%VGPR29<def> = V_MOV_B32_e32 %SGPR44<kill>, %EXEC<imp-use>
	%VGPR18<def> = V_MOV_B32_e32 %SGPR45<kill>, %EXEC<imp-use>
	%VGPR22<def> = V_MOV_B32_e32 %SGPR46<kill>, %EXEC<imp-use>
	%VGPR28<def> = V_MOV_B32_e32 %SGPR47<kill>, %EXEC<imp-use>
	%VGPR27<def> = V_MOV_B32_e32 %SGPR48<kill>, %EXEC<imp-use>
	%VGPR59<def> = V_MOV_B32_e32 %VGPR1, %EXEC<imp-use>
	%VGPR58<def> = V_MOV_B32_e32 %VGPR2, %EXEC<imp-use>
	%VGPR57<def> = V_MOV_B32_e32 %VGPR3, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = S_AND_SAVEEXEC_B64 %SGPR4_SGPR5, %EXEC<imp-def>, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = S_XOR_B64 %EXEC, %SGPR4_SGPR5
	S_CBRANCH_EXECZ <BB#2>, %EXEC
    Successors according to CFG: BB#1(16) BB#2(16)

BB#1: derived from LLVM BB %IF
    Live Ins: %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR27 %VGPR28 %VGPR22 %VGPR18 %VGPR29 %VGPR30 %VGPR23 %VGPR19 %VGPR31 %VGPR32 %VGPR24 %VGPR20 %VGPR33 %VGPR34 %VGPR25 %VGPR21 %VGPR51 %VGPR49 %VGPR46 %VGPR42 %VGPR40 %VGPR39 %VGPR47 %VGPR43 %VGPR41 %VGPR52 %VGPR53 %VGPR48 %VGPR44 %VGPR54 %VGPR55 %VGPR50 %VGPR45 %VGPR37 %VGPR38 %VGPR35 %VGPR26 %SGPR2 %SGPR3 %VGPR14_VGPR15_VGPR16_VGPR17 %VGPR9_VGPR10_VGPR11_VGPR12 %VGPR5_VGPR6_VGPR7_VGPR8 %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0 %VGPR1_VGPR2_VGPR3_VGPR4 %SGPR4_SGPR5 %VGPR13 %VGPR56 %VGPR36
    Predecessors according to CFG: BB#0
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 12; mem:LD16[%101](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%VGPR57_VGPR58_VGPR59_VGPR60<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %VGPR0, 0, %EXEC<imp-use>
	%VGPR61<def> = V_MOV_B32_e32 2.550100e+02, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR62<def> = V_MUL_F32_e32 %VGPR57, %VGPR61, %EXEC<imp-use>
	%VGPR62<def> = V_CVT_I32_F32_e32 %VGPR62<kill>, %EXEC<imp-use>
	%VGPR62<def> = V_MUL_LO_I32 3, %VGPR62<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR63<def> = V_ADD_I32_e32 43, %VGPR62, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR63<def> = V_LSHLREV_B32_e32 4, %VGPR63<kill>, %EXEC<imp-use>
	%VGPR64<def> = V_OR_B32_e64 4, %VGPR63, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR64<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR64<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 16; mem:LD16[%110](align=8)(tbaa=!"const")
	S_WAITCNT 112
	%VGPR65_VGPR66_VGPR67_VGPR68<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR0<def> = V_MUL_F32_e32 %VGPR64<kill>, %VGPR65, %EXEC<imp-use>
	%VGPR64<def> = V_MUL_F32_e32 %VGPR58, %VGPR61, %EXEC<imp-use>
	%VGPR64<def> = V_CVT_I32_F32_e32 %VGPR64<kill>, %EXEC<imp-use>
	%VGPR64<def> = V_MUL_LO_I32 3, %VGPR64<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR69<def> = V_ADD_I32_e32 43, %VGPR64, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR69<def> = V_LSHLREV_B32_e32 4, %VGPR69<kill>, %EXEC<imp-use>
	%VGPR70<def> = V_OR_B32_e64 4, %VGPR69, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR70<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR70<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR0<def> = V_MAD_F32 %VGPR70<kill>, %VGPR66, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR70<def> = V_MUL_F32_e32 %VGPR59, %VGPR61, %EXEC<imp-use>
	%VGPR70<def> = V_CVT_I32_F32_e32 %VGPR70<kill>, %EXEC<imp-use>
	%VGPR70<def> = V_MUL_LO_I32 3, %VGPR70<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR71<def> = V_ADD_I32_e32 43, %VGPR70, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR71<def> = V_LSHLREV_B32_e32 4, %VGPR71<kill>, %EXEC<imp-use>
	%VGPR72<def> = V_OR_B32_e64 4, %VGPR71, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR72<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR72<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR0<def> = V_MAD_F32 %VGPR72<kill>, %VGPR67, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR72<def> = V_ADD_F32_e32 %VGPR66, %VGPR65, %EXEC<imp-use>
	%VGPR72<def> = V_ADD_F32_e32 %VGPR72<kill>, %VGPR67, %EXEC<imp-use>
	%VGPR72<def> = V_SUB_F32_e32 1.000000e+00, %VGPR72<kill>, %EXEC<imp-use>
	%VGPR57<def> = V_MUL_F32_e32 %VGPR60, %VGPR61<kill>, %EXEC<imp-use>, %VGPR57_VGPR58_VGPR59_VGPR60<imp-use,kill>
	%VGPR57<def> = V_CVT_I32_F32_e32 %VGPR57<kill>, %EXEC<imp-use>
	%VGPR57<def> = V_MUL_LO_I32 3, %VGPR57<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR58<def> = V_ADD_I32_e32 43, %VGPR57, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR58<def> = V_LSHLREV_B32_e32 4, %VGPR58<kill>, %EXEC<imp-use>
	%VGPR59<def> = V_OR_B32_e64 4, %VGPR58, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR59<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR59<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR0<def> = V_MAD_F32 %VGPR59<kill>, %VGPR72, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR59<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR63, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR59<def> = V_MUL_F32_e32 %VGPR59<kill>, %VGPR65, %EXEC<imp-use>
	%VGPR60<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR69, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR59<def> = V_MAD_F32 %VGPR60<kill>, %VGPR66, %VGPR59<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR60<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR71, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR59<def> = V_MAD_F32 %VGPR60<kill>, %VGPR67, %VGPR59<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR60<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR58, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR59<def> = V_MAD_F32 %VGPR60<kill>, %VGPR72, %VGPR59<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR60<def> = V_MUL_F32_e32 %VGPR13, %VGPR59, %EXEC<imp-use>
	%VGPR60<def> = V_MAD_F32 %VGPR56, %VGPR0, %VGPR60<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR61<def> = V_OR_B32_e64 8, %VGPR63, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR61<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR61<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR61<def> = V_MUL_F32_e32 %VGPR61<kill>, %VGPR65, %EXEC<imp-use>
	%VGPR73<def> = V_OR_B32_e64 8, %VGPR69, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR73<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR73<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR61<def> = V_MAD_F32 %VGPR73<kill>, %VGPR66, %VGPR61<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR73<def> = V_OR_B32_e64 8, %VGPR71, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR73<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR73<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR61<def> = V_MAD_F32 %VGPR73<kill>, %VGPR67, %VGPR61<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR73<def> = V_OR_B32_e64 8, %VGPR58, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR73<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR73<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR61<def> = V_MAD_F32 %VGPR73<kill>, %VGPR72, %VGPR61<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR60<def> = V_MAD_F32 %VGPR36, %VGPR61, %VGPR60<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR73<def> = V_ADD_I32_e32 42, %VGPR62, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR73<def> = V_LSHLREV_B32_e32 4, %VGPR73<kill>, %EXEC<imp-use>
	%VGPR74<def> = V_OR_B32_e64 4, %VGPR73, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR74<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR74<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR74<def> = V_MUL_F32_e32 %VGPR74<kill>, %VGPR65, %EXEC<imp-use>
	%VGPR75<def> = V_ADD_I32_e32 42, %VGPR64, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR75<def> = V_LSHLREV_B32_e32 4, %VGPR75<kill>, %EXEC<imp-use>
	%VGPR76<def> = V_OR_B32_e64 4, %VGPR75, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR76<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR76<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR74<def> = V_MAD_F32 %VGPR76<kill>, %VGPR66, %VGPR74<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR76<def> = V_ADD_I32_e32 42, %VGPR70, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR76<def> = V_LSHLREV_B32_e32 4, %VGPR76<kill>, %EXEC<imp-use>
	%VGPR77<def> = V_OR_B32_e64 4, %VGPR76, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR77<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR77<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR74<def> = V_MAD_F32 %VGPR77<kill>, %VGPR67, %VGPR74<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR77<def> = V_ADD_I32_e32 42, %VGPR57, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR77<def> = V_LSHLREV_B32_e32 4, %VGPR77<kill>, %EXEC<imp-use>
	%VGPR78<def> = V_OR_B32_e64 4, %VGPR77, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR78<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR78<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR74<def> = V_MAD_F32 %VGPR78<kill>, %VGPR72, %VGPR74<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR78<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR73, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR78<def> = V_MUL_F32_e32 %VGPR78<kill>, %VGPR65, %EXEC<imp-use>
	%VGPR79<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR75, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR78<def> = V_MAD_F32 %VGPR79<kill>, %VGPR66, %VGPR78<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR79<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR76, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR78<def> = V_MAD_F32 %VGPR79<kill>, %VGPR67, %VGPR78<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR79<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR77, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR78<def> = V_MAD_F32 %VGPR79<kill>, %VGPR72, %VGPR78<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR79<def> = V_MUL_F32_e32 %VGPR13, %VGPR78, %EXEC<imp-use>
	%VGPR79<def> = V_MAD_F32 %VGPR56, %VGPR74, %VGPR79<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR80<def> = V_OR_B32_e64 8, %VGPR73, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR80<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR80<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR80<def> = V_MUL_F32_e32 %VGPR80<kill>, %VGPR65, %EXEC<imp-use>
	%VGPR81<def> = V_OR_B32_e64 8, %VGPR75, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR81<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR81<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR80<def> = V_MAD_F32 %VGPR81<kill>, %VGPR66, %VGPR80<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR81<def> = V_OR_B32_e64 8, %VGPR76, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR81<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR81<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR80<def> = V_MAD_F32 %VGPR81<kill>, %VGPR67, %VGPR80<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR81<def> = V_OR_B32_e64 8, %VGPR77, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR81<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR81<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR80<def> = V_MAD_F32 %VGPR81<kill>, %VGPR72, %VGPR80<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR79<def> = V_MAD_F32 %VGPR36, %VGPR80, %VGPR79<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR62<def> = V_ADD_I32_e32 41, %VGPR62<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR62<def> = V_LSHLREV_B32_e32 4, %VGPR62<kill>, %EXEC<imp-use>
	%VGPR81<def> = V_OR_B32_e64 4, %VGPR62, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR81<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR81<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR81<def> = V_MUL_F32_e32 %VGPR81<kill>, %VGPR65, %EXEC<imp-use>
	%VGPR64<def> = V_ADD_I32_e32 41, %VGPR64<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR64<def> = V_LSHLREV_B32_e32 4, %VGPR64<kill>, %EXEC<imp-use>
	%VGPR82<def> = V_OR_B32_e64 4, %VGPR64, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR82<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR82<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR81<def> = V_MAD_F32 %VGPR82<kill>, %VGPR66, %VGPR81<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR70<def> = V_ADD_I32_e32 41, %VGPR70<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR70<def> = V_LSHLREV_B32_e32 4, %VGPR70<kill>, %EXEC<imp-use>
	%VGPR82<def> = V_OR_B32_e64 4, %VGPR70, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR82<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR82<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR81<def> = V_MAD_F32 %VGPR82<kill>, %VGPR67, %VGPR81<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR57<def> = V_ADD_I32_e32 41, %VGPR57<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR82<def> = V_LSHLREV_B32_e32 4, %VGPR57<kill>, %EXEC<imp-use>
	%VGPR57<def> = V_OR_B32_e64 4, %VGPR82, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR57<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR57<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR81<def> = V_MAD_F32 %VGPR57<kill>, %VGPR72, %VGPR81<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR57<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR62, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR57<def> = V_MUL_F32_e32 %VGPR57<kill>, %VGPR65, %EXEC<imp-use>
	%VGPR83<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR64, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR57<def> = V_MAD_F32 %VGPR83<kill>, %VGPR66, %VGPR57<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR83<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR70, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR57<def> = V_MAD_F32 %VGPR83<kill>, %VGPR67, %VGPR57<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR83<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR82, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR83<def> = V_MAD_F32 %VGPR83<kill>, %VGPR72, %VGPR57<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_MUL_F32_e32 %VGPR13<kill>, %VGPR83, %EXEC<imp-use>
	%VGPR13<def> = V_MAD_F32 %VGPR56<kill>, %VGPR81, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR56<def> = V_OR_B32_e64 8, %VGPR62, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR56<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR56<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR56<def> = V_MUL_F32_e32 %VGPR56<kill>, %VGPR65, %EXEC<imp-use>
	%VGPR57<def> = V_OR_B32_e64 8, %VGPR64, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR57<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR57<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR56<def> = V_MAD_F32 %VGPR57<kill>, %VGPR66, %VGPR56<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR57<def> = V_OR_B32_e64 8, %VGPR70, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR57<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR57<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR56<def> = V_MAD_F32 %VGPR57<kill>, %VGPR67, %VGPR56<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR57<def> = V_OR_B32_e64 8, %VGPR82, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR57<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR57<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR56<def> = V_MAD_F32 %VGPR57<kill>, %VGPR72, %VGPR56<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_MAD_F32 %VGPR36<kill>, %VGPR56, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR2, %VGPR0<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR1, %VGPR59<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR3, %VGPR61<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR36<def> = V_OR_B32_e64 12, %VGPR63<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR36<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR36<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR36<def> = V_MUL_F32_e32 %VGPR36<kill>, %VGPR65, %EXEC<imp-use>
	%VGPR57<def> = V_OR_B32_e64 12, %VGPR69<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR57<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR57<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR36<def> = V_MAD_F32 %VGPR57<kill>, %VGPR66, %VGPR36<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR57<def> = V_OR_B32_e64 12, %VGPR71<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR57<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR57<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR36<def> = V_MAD_F32 %VGPR57<kill>, %VGPR67, %VGPR36<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR57<def> = V_OR_B32_e64 12, %VGPR58<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR57<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR57<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR36<def> = V_MAD_F32 %VGPR57<kill>, %VGPR72, %VGPR36<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR57<def> = V_MAD_F32 %VGPR4, %VGPR36<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR2, %VGPR74<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR1, %VGPR78<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR3, %VGPR80<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR36<def> = V_OR_B32_e64 12, %VGPR73<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR36<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR36<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR36<def> = V_MUL_F32_e32 %VGPR36<kill>, %VGPR65, %EXEC<imp-use>
	%VGPR58<def> = V_OR_B32_e64 12, %VGPR75<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR58<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR58<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR36<def> = V_MAD_F32 %VGPR58<kill>, %VGPR66, %VGPR36<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR58<def> = V_OR_B32_e64 12, %VGPR76<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR58<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR58<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR36<def> = V_MAD_F32 %VGPR58<kill>, %VGPR67, %VGPR36<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR58<def> = V_OR_B32_e64 12, %VGPR77<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR58<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR58<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR36<def> = V_MAD_F32 %VGPR58<kill>, %VGPR72, %VGPR36<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR58<def> = V_MAD_F32 %VGPR4, %VGPR36<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR2, %VGPR81<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR1, %VGPR83<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR3, %VGPR56<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR36<def> = V_OR_B32_e64 12, %VGPR62<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR36<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR36<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR36<def> = V_MUL_F32_e32 %VGPR36<kill>, %VGPR65, %EXEC<imp-use>
	%VGPR56<def> = V_OR_B32_e64 12, %VGPR64<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR56<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR56<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR36<def> = V_MAD_F32 %VGPR56<kill>, %VGPR66, %VGPR36<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR56<def> = V_OR_B32_e64 12, %VGPR70<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR56<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR56<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR36<def> = V_MAD_F32 %VGPR56<kill>, %VGPR67, %VGPR36<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR65_VGPR66_VGPR67_VGPR68<imp-use,kill>
	%VGPR56<def> = V_OR_B32_e64 12, %VGPR82<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR56<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR56<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR36<def> = V_MAD_F32 %VGPR56<kill>, %VGPR72<kill>, %VGPR36<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR59<def> = V_MAD_F32 %VGPR4, %VGPR36<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR56<def> = V_MOV_B32_e32 %VGPR79<kill>, %EXEC<imp-use>
	%VGPR36<def> = V_MOV_B32_e32 %VGPR60<kill>, %EXEC<imp-use>
    Successors according to CFG: BB#2

BB#2: derived from LLVM BB %ENDIF
    Live Ins: %VGPR27 %VGPR28 %VGPR22 %VGPR18 %VGPR29 %VGPR30 %VGPR23 %VGPR19 %VGPR31 %VGPR32 %VGPR24 %VGPR20 %VGPR33 %VGPR34 %VGPR25 %VGPR21 %VGPR51 %VGPR49 %VGPR46 %VGPR42 %VGPR40 %VGPR39 %VGPR47 %VGPR43 %VGPR41 %VGPR52 %VGPR53 %VGPR48 %VGPR44 %VGPR54 %VGPR55 %VGPR50 %VGPR45 %VGPR37 %VGPR38 %VGPR35 %VGPR26 %SGPR2 %SGPR3 %VGPR14_VGPR15_VGPR16_VGPR17 %VGPR9_VGPR10_VGPR11_VGPR12 %VGPR5_VGPR6_VGPR7_VGPR8 %SGPR0_SGPR1 %VGPR1_VGPR2_VGPR3_VGPR4 %SGPR4_SGPR5 %VGPR59 %VGPR58 %VGPR57 %VGPR13 %VGPR56 %VGPR36
    Predecessors according to CFG: BB#0 BB#1
	%EXEC<def> = S_OR_B64 %EXEC, %SGPR4_SGPR5
	%VGPR0<def> = V_MUL_F32_e64 %VGPR15, %VGPR55<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR14, %VGPR54<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR16, %VGPR50<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR17, %VGPR45<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR45<def> = V_MUL_F32_e64 %VGPR15, %VGPR53<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR45<def> = V_MAD_F32 %VGPR14, %VGPR52<kill>, %VGPR45<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR45<def> = V_MAD_F32 %VGPR16, %VGPR48<kill>, %VGPR45<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR14<def> = V_MAD_F32 %VGPR17, %VGPR44<kill>, %VGPR45<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17<imp-use,kill>
	EXP 15, 32, 0, 0, 0, %VGPR14<kill>, %VGPR0<kill>, %VGPR9, %VGPR10, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>
	S_WAITCNT 1807
	%VGPR0<def> = V_MUL_F32_e64 %VGPR13, %VGPR47<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR56, %VGPR43<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR36, %VGPR41<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_MUL_F32_e64 %VGPR13, %VGPR51<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_MAD_F32 %VGPR56, %VGPR49<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_MAD_F32 %VGPR36, %VGPR46<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR10<def> = V_MUL_F32_e64 %VGPR13<kill>, %VGPR42<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR10<def> = V_MAD_F32 %VGPR56<kill>, %VGPR40<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR10<def> = V_MAD_F32 %VGPR36<kill>, %VGPR39<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR10<def> = V_ADD_F32_e64 %VGPR10<kill>, 0, 0, 0, 0, 1, %EXEC<imp-use>
	%VGPR11<def> = V_MUL_F32_e64 %VGPR58, %VGPR38<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR11<def> = V_MAD_F32 %VGPR59, %VGPR37<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR11<def> = V_MAD_F32 %VGPR57, %VGPR35<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR11<def> = V_MAD_F32 %VGPR4, %VGPR26<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR11<def> = V_ADD_F32_e32 -1.000000e-01, %VGPR11<kill>, %EXEC<imp-use>
	EXP 15, 33, 0, 0, 0, %VGPR9<kill>, %VGPR10<kill>, %VGPR0<kill>, %VGPR11<kill>, %EXEC<imp-use>
	S_WAITCNT 1807
	%VGPR0<def> = V_MOV_B32_e32 %SGPR3<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_MOV_B32_e32 %SGPR2<kill>, %EXEC<imp-use>
	%VGPR10<def> = V_MAD_F32 %VGPR8, %VGPR9, %VGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR11<def> = V_SUB_F32_e32 1.000000e+00, %VGPR10, %EXEC<imp-use>
	%VGPR12<def> = V_MAD_F32 %VGPR5, %VGPR9, %VGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_MUL_F32_e32 %VGPR12<kill>, %VGPR12, %EXEC<imp-use>
	%VGPR12<def> = V_MAD_F32 %VGPR10, %VGPR12<kill>, %VGPR11, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_MAD_F32 %VGPR6, %VGPR9, %VGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_MUL_F32_e32 %VGPR13<kill>, %VGPR13, %EXEC<imp-use>
	%VGPR13<def> = V_MAD_F32 %VGPR10, %VGPR13<kill>, %VGPR11, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR7, %VGPR9<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-use,kill>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR0<kill>, %VGPR0, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR10, %VGPR0<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 34, 0, 0, 0, %VGPR0<kill>, %VGPR13<kill>, %VGPR12<kill>, %VGPR10<kill>, %EXEC<imp-use>
	S_WAITCNT 1807
	%VGPR0<def> = V_MUL_F32_e64 %VGPR58, %VGPR34<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR59, %VGPR33<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR57, %VGPR25<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR4, %VGPR21<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_MUL_F32_e64 %VGPR58, %VGPR32<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR59, %VGPR31<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR57, %VGPR24<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR4, %VGPR20<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e64 %VGPR58, %VGPR30<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR59, %VGPR29<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR57, %VGPR23<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR4, %VGPR19<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_MUL_F32_e64 %VGPR58<kill>, %VGPR28<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR59<kill>, %VGPR27<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR57<kill>, %VGPR22<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_MAD_F32 %VGPR4, %VGPR18<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR1_VGPR2_VGPR3_VGPR4<imp-use,kill>
	EXP 15, 12, 0, 0, 0, %VGPR1, %VGPR6, %VGPR5, %VGPR0, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 64; mem:LD16[%539](align=8)(tbaa=!"const")
	S_WAITCNT 15
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 13; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 12; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 14; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %SGPR4<kill>, %VGPR5, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 15; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %SGPR4<kill>, %VGPR0, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 9; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 8; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 10; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %SGPR4<kill>, %VGPR5, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 11; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %SGPR4<kill>, %VGPR0, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 5; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR4<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 4; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 6; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %SGPR4<kill>, %VGPR5, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 7; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %SGPR4<kill>, %VGPR0, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR6<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 0; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %SGPR4<kill>, %VGPR5<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 3; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR0<def> = V_MAD_F32 %SGPR0<kill>, %VGPR0<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 13, 0, 1, 0, %VGPR0<kill>, %VGPR4<kill>, %VGPR3<kill>, %VGPR2<kill>, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_LOAD_DWORDX4 s[8:11], s[6:7], 4                  ; C0840704
	S_WAITCNT lgkmcnt(0)                               ; BF8C007F
	BUFFER_LOAD_FORMAT_XYZW v[18:21], s[8:11][v0] + 0  ; E00C2000 80021200
	S_LOAD_DWORDX4 s[8:11], s[0:1], 0                  ; C0840100
	S_WAITCNT vmcnt(0) lgkmcnt(0)                      ; BF8C0070
	S_BUFFER_LOAD_DWORD s2, s[8:11], 43                ; C201092B
	S_WAITCNT lgkmcnt(0)                               ; BF8C007F
	V_MOV_B32_e32 v22, s2                              ; 7E2C0202
	S_BUFFER_LOAD_DWORD s2, s[8:11], 42                ; C201092A
	S_WAITCNT lgkmcnt(0)                               ; BF8C007F
	V_MOV_B32_e32 v23, s2                              ; 7E2E0202
	V_MAD_F32 v36, v20, v23, v22, 0, 0, 0, 0           ; D2820024 045A2F14
	V_MAD_F32 v13, v18, v23, v22, 0, 0, 0, 0           ; D282000D 045A2F12
	S_LOAD_DWORDX4 s[12:15], s[6:7], 24                ; C0860718
	S_WAITCNT lgkmcnt(0)                               ; BF8C007F
	BUFFER_LOAD_FORMAT_XYZW v[5:8], s[12:15][v0] + 0   ; E00C2000 80030500
	S_LOAD_DWORDX4 s[12:15], s[6:7], 20                ; C0860714
	S_WAITCNT vmcnt(0) lgkmcnt(0)                      ; BF8C0070
	BUFFER_LOAD_FORMAT_XYZW v[9:12], s[12:15][v0] + 0  ; E00C2000 80030900
	S_LOAD_DWORDX4 s[12:15], s[6:7], 8                 ; C0860708
	S_WAITCNT vmcnt(0) lgkmcnt(0)                      ; BF8C0070
	BUFFER_LOAD_FORMAT_XYZW v[14:17], s[12:15][v0] + 0 ; E00C2000 80030E00
	S_LOAD_DWORDX4 s[12:15], s[6:7], 0                 ; C0860700
	S_WAITCNT vmcnt(0) lgkmcnt(0)                      ; BF8C0070
	BUFFER_LOAD_FORMAT_XYZW v[1:4], s[12:15][v0] + 0   ; E00C2000 80030100
	V_MAD_F32 v18, v19, v23, v22, 0, 0, 0, 0           ; D2820012 045A2F13
	V_ADD_F32_e32 v56, 1.000000e-03, v18               ; 067024FF 3A83126F
	S_MOV_B32 s2, 3840                                 ; BE8203FF 00000F00
	S_BUFFER_LOAD_DWORD s2, s[8:11], s2                ; C2010802
	S_WAITCNT vmcnt(0) lgkmcnt(0)                      ; BF8C0070
	V_CMP_NE_I32_e64 s[4:5], s2, 0, 0, 0, 0, 0         ; D10A0004 02010002
	S_BUFFER_LOAD_DWORD s3, s[8:11], 41                ; C2018929
	S_BUFFER_LOAD_DWORD s2, s[8:11], 40                ; C2010928
	S_BUFFER_LOAD_DWORD s12, s[8:11], 39               ; C2060927
	S_BUFFER_LOAD_DWORD s13, s[8:11], 38               ; C2068926
	S_BUFFER_LOAD_DWORD s14, s[8:11], 37               ; C2070925
	S_BUFFER_LOAD_DWORD s15, s[8:11], 36               ; C2078924
	S_BUFFER_LOAD_DWORD s16, s[8:11], 35               ; C2080923
	S_BUFFER_LOAD_DWORD s17, s[8:11], 34               ; C2088922
	S_BUFFER_LOAD_DWORD s18, s[8:11], 33               ; C2090921
	S_BUFFER_LOAD_DWORD s19, s[8:11], 32               ; C2098920
	S_BUFFER_LOAD_DWORD s20, s[8:11], 31               ; C20A091F
	S_BUFFER_LOAD_DWORD s21, s[8:11], 30               ; C20A891E
	S_BUFFER_LOAD_DWORD s22, s[8:11], 29               ; C20B091D
	S_BUFFER_LOAD_DWORD s23, s[8:11], 28               ; C20B891C
	S_BUFFER_LOAD_DWORD s24, s[8:11], 26               ; C20C091A
	S_BUFFER_LOAD_DWORD s25, s[8:11], 25               ; C20C8919
	S_BUFFER_LOAD_DWORD s26, s[8:11], 24               ; C20D0918
	S_BUFFER_LOAD_DWORD s27, s[8:11], 22               ; C20D8916
	S_BUFFER_LOAD_DWORD s28, s[8:11], 21               ; C20E0915
	S_BUFFER_LOAD_DWORD s29, s[8:11], 20               ; C20E8914
	S_BUFFER_LOAD_DWORD s30, s[8:11], 18               ; C20F0912
	S_BUFFER_LOAD_DWORD s31, s[8:11], 17               ; C20F8911
	S_BUFFER_LOAD_DWORD s32, s[8:11], 16               ; C2100910
	S_BUFFER_LOAD_DWORD s33, s[8:11], 15               ; C210890F
	S_BUFFER_LOAD_DWORD s34, s[8:11], 14               ; C211090E
	S_BUFFER_LOAD_DWORD s35, s[8:11], 13               ; C211890D
	S_BUFFER_LOAD_DWORD s36, s[8:11], 12               ; C212090C
	S_BUFFER_LOAD_DWORD s37, s[8:11], 11               ; C212890B
	S_BUFFER_LOAD_DWORD s38, s[8:11], 10               ; C213090A
	S_BUFFER_LOAD_DWORD s39, s[8:11], 9                ; C2138909
	S_BUFFER_LOAD_DWORD s40, s[8:11], 8                ; C2140908
	S_BUFFER_LOAD_DWORD s41, s[8:11], 7                ; C2148907
	S_BUFFER_LOAD_DWORD s42, s[8:11], 6                ; C2150906
	S_BUFFER_LOAD_DWORD s43, s[8:11], 5                ; C2158905
	S_BUFFER_LOAD_DWORD s44, s[8:11], 4                ; C2160904
	S_BUFFER_LOAD_DWORD s45, s[8:11], 3                ; C2168903
	S_BUFFER_LOAD_DWORD s46, s[8:11], 2                ; C2170902
	S_BUFFER_LOAD_DWORD s47, s[8:11], 1                ; C2178901
	S_BUFFER_LOAD_DWORD s48, s[8:11], 0                ; C2180900
	S_WAITCNT lgkmcnt(0)                               ; BF8C007F
	V_MOV_B32_e32 v26, s12                             ; 7E34020C
	V_MOV_B32_e32 v35, s13                             ; 7E46020D
	V_MOV_B32_e32 v38, s14                             ; 7E4C020E
	V_MOV_B32_e32 v37, s15                             ; 7E4A020F
	V_MOV_B32_e32 v45, s16                             ; 7E5A0210
	V_MOV_B32_e32 v50, s17                             ; 7E640211
	V_MOV_B32_e32 v55, s18                             ; 7E6E0212
	V_MOV_B32_e32 v54, s19                             ; 7E6C0213
	V_MOV_B32_e32 v44, s20                             ; 7E580214
	V_MOV_B32_e32 v48, s21                             ; 7E600215
	V_MOV_B32_e32 v53, s22                             ; 7E6A0216
	V_MOV_B32_e32 v52, s23                             ; 7E680217
	V_MOV_B32_e32 v41, s24                             ; 7E520218
	V_MOV_B32_e32 v43, s25                             ; 7E560219
	V_MOV_B32_e32 v47, s26                             ; 7E5E021A
	V_MOV_B32_e32 v39, s27                             ; 7E4E021B
	V_MOV_B32_e32 v40, s28                             ; 7E50021C
	V_MOV_B32_e32 v42, s29                             ; 7E54021D
	V_MOV_B32_e32 v46, s30                             ; 7E5C021E
	V_MOV_B32_e32 v49, s31                             ; 7E62021F
	V_MOV_B32_e32 v51, s32                             ; 7E660220
	V_MOV_B32_e32 v21, s33                             ; 7E2A0221
	V_MOV_B32_e32 v25, s34                             ; 7E320222
	V_MOV_B32_e32 v34, s35                             ; 7E440223
	V_MOV_B32_e32 v33, s36                             ; 7E420224
	V_MOV_B32_e32 v20, s37                             ; 7E280225
	V_MOV_B32_e32 v24, s38                             ; 7E300226
	V_MOV_B32_e32 v32, s39                             ; 7E400227
	V_MOV_B32_e32 v31, s40                             ; 7E3E0228
	V_MOV_B32_e32 v19, s41                             ; 7E260229
	V_MOV_B32_e32 v23, s42                             ; 7E2E022A
	V_MOV_B32_e32 v30, s43                             ; 7E3C022B
	V_MOV_B32_e32 v29, s44                             ; 7E3A022C
	V_MOV_B32_e32 v18, s45                             ; 7E24022D
	V_MOV_B32_e32 v22, s46                             ; 7E2C022E
	V_MOV_B32_e32 v28, s47                             ; 7E38022F
	V_MOV_B32_e32 v27, s48                             ; 7E360230
	V_MOV_B32_e32 v59, v1                              ; 7E760301
	V_MOV_B32_e32 v58, v2                              ; 7E740302
	V_MOV_B32_e32 v57, v3                              ; 7E720303
	S_AND_SAVEEXEC_B64 s[4:5], s[4:5]                  ; BE842404
	S_XOR_B64 s[4:5], exec, s[4:5]                     ; 8984047E
	S_CBRANCH_EXECZ ";.BB0_2"                          ; BF880000
	S_LOAD_DWORDX4 s[12:15], s[6:7], 12                ; C086070C
	S_WAITCNT lgkmcnt(0)                               ; BF8C007F
	BUFFER_LOAD_FORMAT_XYZW v[57:60], s[12:15][v0] + 0 ; E00C2000 80033900
	V_MOV_B32_e32 v61, 2.550100e+02                    ; 7E7A02FF 437F028F
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MUL_F32_e32 v62, v57, v61                        ; 107C7B39
	V_CVT_I32_F32_e32 v62, v62                         ; 7E7C113E
	V_MUL_LO_I32 v62, 3, v62, 0, 0, 0, 0, 0            ; D2D6003E 02027C83
	V_ADD_I32_e32 v63, 43, v62                         ; 4A7E7CAB
	V_LSHLREV_B32_e32 v63, 4, v63                      ; 347E7E84
	V_OR_B32_e64 v64, 4, v63, 0, 0, 0, 0               ; D2380040 02027E84
	BUFFER_LOAD_DWORD v64, s[8:11] + v64               ; E0301000 80024040
	S_LOAD_DWORDX4 s[12:15], s[6:7], 16                ; C0860710
	S_WAITCNT vmcnt(0) lgkmcnt(0)                      ; BF8C0070
	BUFFER_LOAD_FORMAT_XYZW v[65:68], s[12:15][v0] + 0 ; E00C2000 80034100
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MUL_F32_e32 v0, v64, v65                         ; 10008340
	V_MUL_F32_e32 v64, v58, v61                        ; 10807B3A
	V_CVT_I32_F32_e32 v64, v64                         ; 7E801140
	V_MUL_LO_I32 v64, 3, v64, 0, 0, 0, 0, 0            ; D2D60040 02028083
	V_ADD_I32_e32 v69, 43, v64                         ; 4A8A80AB
	V_LSHLREV_B32_e32 v69, 4, v69                      ; 348A8A84
	V_OR_B32_e64 v70, 4, v69, 0, 0, 0, 0               ; D2380046 02028A84
	BUFFER_LOAD_DWORD v70, s[8:11] + v70               ; E0301000 80024646
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v0, v70, v66, v0, 0, 0, 0, 0             ; D2820000 04028546
	V_MUL_F32_e32 v70, v59, v61                        ; 108C7B3B
	V_CVT_I32_F32_e32 v70, v70                         ; 7E8C1146
	V_MUL_LO_I32 v70, 3, v70, 0, 0, 0, 0, 0            ; D2D60046 02028C83
	V_ADD_I32_e32 v71, 43, v70                         ; 4A8E8CAB
	V_LSHLREV_B32_e32 v71, 4, v71                      ; 348E8E84
	V_OR_B32_e64 v72, 4, v71, 0, 0, 0, 0               ; D2380048 02028E84
	BUFFER_LOAD_DWORD v72, s[8:11] + v72               ; E0301000 80024848
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v0, v72, v67, v0, 0, 0, 0, 0             ; D2820000 04028748
	V_ADD_F32_e32 v72, v66, v65                        ; 06908342
	V_ADD_F32_e32 v72, v72, v67                        ; 06908748
	V_SUB_F32_e32 v72, 1.000000e+00, v72               ; 089090F2
	V_MUL_F32_e32 v57, v60, v61                        ; 10727B3C
	V_CVT_I32_F32_e32 v57, v57                         ; 7E721139
	V_MUL_LO_I32 v57, 3, v57, 0, 0, 0, 0, 0            ; D2D60039 02027283
	V_ADD_I32_e32 v58, 43, v57                         ; 4A7472AB
	V_LSHLREV_B32_e32 v58, 4, v58                      ; 34747484
	V_OR_B32_e64 v59, 4, v58, 0, 0, 0, 0               ; D238003B 02027484
	BUFFER_LOAD_DWORD v59, s[8:11] + v59               ; E0301000 80023B3B
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v0, v59, v72, v0, 0, 0, 0, 0             ; D2820000 0402913B
	BUFFER_LOAD_DWORD v59, s[8:11] + v63               ; E0301000 80023B3F
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MUL_F32_e32 v59, v59, v65                        ; 1076833B
	BUFFER_LOAD_DWORD v60, s[8:11] + v69               ; E0301000 80023C45
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v59, v60, v66, v59, 0, 0, 0, 0           ; D282003B 04EE853C
	BUFFER_LOAD_DWORD v60, s[8:11] + v71               ; E0301000 80023C47
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v59, v60, v67, v59, 0, 0, 0, 0           ; D282003B 04EE873C
	BUFFER_LOAD_DWORD v60, s[8:11] + v58               ; E0301000 80023C3A
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v59, v60, v72, v59, 0, 0, 0, 0           ; D282003B 04EE913C
	V_MUL_F32_e32 v60, v13, v59                        ; 1078770D
	V_MAD_F32 v60, v56, v0, v60, 0, 0, 0, 0            ; D282003C 04F20138
	V_OR_B32_e64 v61, 8, v63, 0, 0, 0, 0               ; D238003D 02027E88
	BUFFER_LOAD_DWORD v61, s[8:11] + v61               ; E0301000 80023D3D
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MUL_F32_e32 v61, v61, v65                        ; 107A833D
	V_OR_B32_e64 v73, 8, v69, 0, 0, 0, 0               ; D2380049 02028A88
	BUFFER_LOAD_DWORD v73, s[8:11] + v73               ; E0301000 80024949
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v61, v73, v66, v61, 0, 0, 0, 0           ; D282003D 04F68549
	V_OR_B32_e64 v73, 8, v71, 0, 0, 0, 0               ; D2380049 02028E88
	BUFFER_LOAD_DWORD v73, s[8:11] + v73               ; E0301000 80024949
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v61, v73, v67, v61, 0, 0, 0, 0           ; D282003D 04F68749
	V_OR_B32_e64 v73, 8, v58, 0, 0, 0, 0               ; D2380049 02027488
	BUFFER_LOAD_DWORD v73, s[8:11] + v73               ; E0301000 80024949
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v61, v73, v72, v61, 0, 0, 0, 0           ; D282003D 04F69149
	V_MAD_F32 v60, v36, v61, v60, 0, 0, 0, 0           ; D282003C 04F27B24
	V_ADD_I32_e32 v73, 42, v62                         ; 4A927CAA
	V_LSHLREV_B32_e32 v73, 4, v73                      ; 34929284
	V_OR_B32_e64 v74, 4, v73, 0, 0, 0, 0               ; D238004A 02029284
	BUFFER_LOAD_DWORD v74, s[8:11] + v74               ; E0301000 80024A4A
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MUL_F32_e32 v74, v74, v65                        ; 1094834A
	V_ADD_I32_e32 v75, 42, v64                         ; 4A9680AA
	V_LSHLREV_B32_e32 v75, 4, v75                      ; 34969684
	V_OR_B32_e64 v76, 4, v75, 0, 0, 0, 0               ; D238004C 02029684
	BUFFER_LOAD_DWORD v76, s[8:11] + v76               ; E0301000 80024C4C
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v74, v76, v66, v74, 0, 0, 0, 0           ; D282004A 052A854C
	V_ADD_I32_e32 v76, 42, v70                         ; 4A988CAA
	V_LSHLREV_B32_e32 v76, 4, v76                      ; 34989884
	V_OR_B32_e64 v77, 4, v76, 0, 0, 0, 0               ; D238004D 02029884
	BUFFER_LOAD_DWORD v77, s[8:11] + v77               ; E0301000 80024D4D
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v74, v77, v67, v74, 0, 0, 0, 0           ; D282004A 052A874D
	V_ADD_I32_e32 v77, 42, v57                         ; 4A9A72AA
	V_LSHLREV_B32_e32 v77, 4, v77                      ; 349A9A84
	V_OR_B32_e64 v78, 4, v77, 0, 0, 0, 0               ; D238004E 02029A84
	BUFFER_LOAD_DWORD v78, s[8:11] + v78               ; E0301000 80024E4E
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v74, v78, v72, v74, 0, 0, 0, 0           ; D282004A 052A914E
	BUFFER_LOAD_DWORD v78, s[8:11] + v73               ; E0301000 80024E49
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MUL_F32_e32 v78, v78, v65                        ; 109C834E
	BUFFER_LOAD_DWORD v79, s[8:11] + v75               ; E0301000 80024F4B
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v78, v79, v66, v78, 0, 0, 0, 0           ; D282004E 053A854F
	BUFFER_LOAD_DWORD v79, s[8:11] + v76               ; E0301000 80024F4C
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v78, v79, v67, v78, 0, 0, 0, 0           ; D282004E 053A874F
	BUFFER_LOAD_DWORD v79, s[8:11] + v77               ; E0301000 80024F4D
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v78, v79, v72, v78, 0, 0, 0, 0           ; D282004E 053A914F
	V_MUL_F32_e32 v79, v13, v78                        ; 109E9D0D
	V_MAD_F32 v79, v56, v74, v79, 0, 0, 0, 0           ; D282004F 053E9538
	V_OR_B32_e64 v80, 8, v73, 0, 0, 0, 0               ; D2380050 02029288
	BUFFER_LOAD_DWORD v80, s[8:11] + v80               ; E0301000 80025050
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MUL_F32_e32 v80, v80, v65                        ; 10A08350
	V_OR_B32_e64 v81, 8, v75, 0, 0, 0, 0               ; D2380051 02029688
	BUFFER_LOAD_DWORD v81, s[8:11] + v81               ; E0301000 80025151
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v80, v81, v66, v80, 0, 0, 0, 0           ; D2820050 05428551
	V_OR_B32_e64 v81, 8, v76, 0, 0, 0, 0               ; D2380051 02029888
	BUFFER_LOAD_DWORD v81, s[8:11] + v81               ; E0301000 80025151
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v80, v81, v67, v80, 0, 0, 0, 0           ; D2820050 05428751
	V_OR_B32_e64 v81, 8, v77, 0, 0, 0, 0               ; D2380051 02029A88
	BUFFER_LOAD_DWORD v81, s[8:11] + v81               ; E0301000 80025151
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v80, v81, v72, v80, 0, 0, 0, 0           ; D2820050 05429151
	V_MAD_F32 v79, v36, v80, v79, 0, 0, 0, 0           ; D282004F 053EA124
	V_ADD_I32_e32 v62, 41, v62                         ; 4A7C7CA9
	V_LSHLREV_B32_e32 v62, 4, v62                      ; 347C7C84
	V_OR_B32_e64 v81, 4, v62, 0, 0, 0, 0               ; D2380051 02027C84
	BUFFER_LOAD_DWORD v81, s[8:11] + v81               ; E0301000 80025151
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MUL_F32_e32 v81, v81, v65                        ; 10A28351
	V_ADD_I32_e32 v64, 41, v64                         ; 4A8080A9
	V_LSHLREV_B32_e32 v64, 4, v64                      ; 34808084
	V_OR_B32_e64 v82, 4, v64, 0, 0, 0, 0               ; D2380052 02028084
	BUFFER_LOAD_DWORD v82, s[8:11] + v82               ; E0301000 80025252
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v81, v82, v66, v81, 0, 0, 0, 0           ; D2820051 05468552
	V_ADD_I32_e32 v70, 41, v70                         ; 4A8C8CA9
	V_LSHLREV_B32_e32 v70, 4, v70                      ; 348C8C84
	V_OR_B32_e64 v82, 4, v70, 0, 0, 0, 0               ; D2380052 02028C84
	BUFFER_LOAD_DWORD v82, s[8:11] + v82               ; E0301000 80025252
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v81, v82, v67, v81, 0, 0, 0, 0           ; D2820051 05468752
	V_ADD_I32_e32 v57, 41, v57                         ; 4A7272A9
	V_LSHLREV_B32_e32 v82, 4, v57                      ; 34A47284
	V_OR_B32_e64 v57, 4, v82, 0, 0, 0, 0               ; D2380039 0202A484
	BUFFER_LOAD_DWORD v57, s[8:11] + v57               ; E0301000 80023939
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v81, v57, v72, v81, 0, 0, 0, 0           ; D2820051 05469139
	BUFFER_LOAD_DWORD v57, s[8:11] + v62               ; E0301000 8002393E
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MUL_F32_e32 v57, v57, v65                        ; 10728339
	BUFFER_LOAD_DWORD v83, s[8:11] + v64               ; E0301000 80025340
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v57, v83, v66, v57, 0, 0, 0, 0           ; D2820039 04E68553
	BUFFER_LOAD_DWORD v83, s[8:11] + v70               ; E0301000 80025346
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v57, v83, v67, v57, 0, 0, 0, 0           ; D2820039 04E68753
	BUFFER_LOAD_DWORD v83, s[8:11] + v82               ; E0301000 80025352
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v83, v83, v72, v57, 0, 0, 0, 0           ; D2820053 04E69153
	V_MUL_F32_e32 v13, v13, v83                        ; 101AA70D
	V_MAD_F32 v13, v56, v81, v13, 0, 0, 0, 0           ; D282000D 0436A338
	V_OR_B32_e64 v56, 8, v62, 0, 0, 0, 0               ; D2380038 02027C88
	BUFFER_LOAD_DWORD v56, s[8:11] + v56               ; E0301000 80023838
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MUL_F32_e32 v56, v56, v65                        ; 10708338
	V_OR_B32_e64 v57, 8, v64, 0, 0, 0, 0               ; D2380039 02028088
	BUFFER_LOAD_DWORD v57, s[8:11] + v57               ; E0301000 80023939
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v56, v57, v66, v56, 0, 0, 0, 0           ; D2820038 04E28539
	V_OR_B32_e64 v57, 8, v70, 0, 0, 0, 0               ; D2380039 02028C88
	BUFFER_LOAD_DWORD v57, s[8:11] + v57               ; E0301000 80023939
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v56, v57, v67, v56, 0, 0, 0, 0           ; D2820038 04E28739
	V_OR_B32_e64 v57, 8, v82, 0, 0, 0, 0               ; D2380039 0202A488
	BUFFER_LOAD_DWORD v57, s[8:11] + v57               ; E0301000 80023939
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v56, v57, v72, v56, 0, 0, 0, 0           ; D2820038 04E29139
	V_MAD_F32 v13, v36, v56, v13, 0, 0, 0, 0           ; D282000D 04367124
	V_MUL_F32_e32 v0, v2, v0                           ; 10000102
	V_MAD_F32 v0, v1, v59, v0, 0, 0, 0, 0              ; D2820000 04027701
	V_MAD_F32 v0, v3, v61, v0, 0, 0, 0, 0              ; D2820000 04027B03
	V_OR_B32_e64 v36, 12, v63, 0, 0, 0, 0              ; D2380024 02027E8C
	BUFFER_LOAD_DWORD v36, s[8:11] + v36               ; E0301000 80022424
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MUL_F32_e32 v36, v36, v65                        ; 10488324
	V_OR_B32_e64 v57, 12, v69, 0, 0, 0, 0              ; D2380039 02028A8C
	BUFFER_LOAD_DWORD v57, s[8:11] + v57               ; E0301000 80023939
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v36, v57, v66, v36, 0, 0, 0, 0           ; D2820024 04928539
	V_OR_B32_e64 v57, 12, v71, 0, 0, 0, 0              ; D2380039 02028E8C
	BUFFER_LOAD_DWORD v57, s[8:11] + v57               ; E0301000 80023939
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v36, v57, v67, v36, 0, 0, 0, 0           ; D2820024 04928739
	V_OR_B32_e64 v57, 12, v58, 0, 0, 0, 0              ; D2380039 0202748C
	BUFFER_LOAD_DWORD v57, s[8:11] + v57               ; E0301000 80023939
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v36, v57, v72, v36, 0, 0, 0, 0           ; D2820024 04929139
	V_MAD_F32 v57, v4, v36, v0, 0, 0, 0, 0             ; D2820039 04024904
	V_MUL_F32_e32 v0, v2, v74                          ; 10009502
	V_MAD_F32 v0, v1, v78, v0, 0, 0, 0, 0              ; D2820000 04029D01
	V_MAD_F32 v0, v3, v80, v0, 0, 0, 0, 0              ; D2820000 0402A103
	V_OR_B32_e64 v36, 12, v73, 0, 0, 0, 0              ; D2380024 0202928C
	BUFFER_LOAD_DWORD v36, s[8:11] + v36               ; E0301000 80022424
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MUL_F32_e32 v36, v36, v65                        ; 10488324
	V_OR_B32_e64 v58, 12, v75, 0, 0, 0, 0              ; D238003A 0202968C
	BUFFER_LOAD_DWORD v58, s[8:11] + v58               ; E0301000 80023A3A
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v36, v58, v66, v36, 0, 0, 0, 0           ; D2820024 0492853A
	V_OR_B32_e64 v58, 12, v76, 0, 0, 0, 0              ; D238003A 0202988C
	BUFFER_LOAD_DWORD v58, s[8:11] + v58               ; E0301000 80023A3A
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v36, v58, v67, v36, 0, 0, 0, 0           ; D2820024 0492873A
	V_OR_B32_e64 v58, 12, v77, 0, 0, 0, 0              ; D238003A 02029A8C
	BUFFER_LOAD_DWORD v58, s[8:11] + v58               ; E0301000 80023A3A
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v36, v58, v72, v36, 0, 0, 0, 0           ; D2820024 0492913A
	V_MAD_F32 v58, v4, v36, v0, 0, 0, 0, 0             ; D282003A 04024904
	V_MUL_F32_e32 v0, v2, v81                          ; 1000A302
	V_MAD_F32 v0, v1, v83, v0, 0, 0, 0, 0              ; D2820000 0402A701
	V_MAD_F32 v0, v3, v56, v0, 0, 0, 0, 0              ; D2820000 04027103
	V_OR_B32_e64 v36, 12, v62, 0, 0, 0, 0              ; D2380024 02027C8C
	BUFFER_LOAD_DWORD v36, s[8:11] + v36               ; E0301000 80022424
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MUL_F32_e32 v36, v36, v65                        ; 10488324
	V_OR_B32_e64 v56, 12, v64, 0, 0, 0, 0              ; D2380038 0202808C
	BUFFER_LOAD_DWORD v56, s[8:11] + v56               ; E0301000 80023838
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v36, v56, v66, v36, 0, 0, 0, 0           ; D2820024 04928538
	V_OR_B32_e64 v56, 12, v70, 0, 0, 0, 0              ; D2380038 02028C8C
	BUFFER_LOAD_DWORD v56, s[8:11] + v56               ; E0301000 80023838
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v36, v56, v67, v36, 0, 0, 0, 0           ; D2820024 04928738
	V_OR_B32_e64 v56, 12, v82, 0, 0, 0, 0              ; D2380038 0202A48C
	BUFFER_LOAD_DWORD v56, s[8:11] + v56               ; E0301000 80023838
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v36, v56, v72, v36, 0, 0, 0, 0           ; D2820024 04929138
	V_MAD_F32 v59, v4, v36, v0, 0, 0, 0, 0             ; D282003B 04024904
	V_MOV_B32_e32 v56, v79                             ; 7E70034F
	V_MOV_B32_e32 v36, v60                             ; 7E48033C
	S_OR_B64 exec, exec, s[4:5]                        ; 88FE047E
	V_MUL_F32_e64 v0, v15, v55, 0, 0, 0, 0             ; D2100000 02026F0F
	V_MAD_F32 v0, v14, v54, v0, 0, 0, 0, 0             ; D2820000 04026D0E
	V_MAD_F32 v0, v16, v50, v0, 0, 0, 0, 0             ; D2820000 04026510
	V_MAD_F32 v0, v17, v45, v0, 0, 0, 0, 0             ; D2820000 04025B11
	V_MUL_F32_e64 v45, v15, v53, 0, 0, 0, 0            ; D210002D 02026B0F
	V_MAD_F32 v45, v14, v52, v45, 0, 0, 0, 0           ; D282002D 04B6690E
	V_MAD_F32 v45, v16, v48, v45, 0, 0, 0, 0           ; D282002D 04B66110
	V_MAD_F32 v14, v17, v44, v45, 0, 0, 0, 0           ; D282000E 04B65911
	EXP 15, 32, 0, 0, 0, v14, v0, v9, v10              ; F800020F 0A09000E
	S_WAITCNT expcnt(0)                                ; BF8C070F
	V_MUL_F32_e64 v0, v13, v47, 0, 0, 0, 0             ; D2100000 02025F0D
	V_MAD_F32 v0, v56, v43, v0, 0, 0, 0, 0             ; D2820000 04025738
	V_MAD_F32 v0, v36, v41, v0, 0, 0, 0, 0             ; D2820000 04025324
	V_MUL_F32_e64 v9, v13, v51, 0, 0, 0, 0             ; D2100009 0202670D
	V_MAD_F32 v9, v56, v49, v9, 0, 0, 0, 0             ; D2820009 04266338
	V_MAD_F32 v9, v36, v46, v9, 0, 0, 0, 0             ; D2820009 04265D24
	V_MUL_F32_e64 v10, v13, v42, 0, 0, 0, 0            ; D210000A 0202550D
	V_MAD_F32 v10, v56, v40, v10, 0, 0, 0, 0           ; D282000A 042A5138
	V_MAD_F32 v10, v36, v39, v10, 0, 0, 0, 0           ; D282000A 042A4F24
	V_ADD_F32_e64 v10, v10, 0, 0, 0, 0, 1              ; D206000A 2201010A
	V_MUL_F32_e64 v11, v58, v38, 0, 0, 0, 0            ; D210000B 02024D3A
	V_MAD_F32 v11, v59, v37, v11, 0, 0, 0, 0           ; D282000B 042E4B3B
	V_MAD_F32 v11, v57, v35, v11, 0, 0, 0, 0           ; D282000B 042E4739
	V_MAD_F32 v11, v4, v26, v11, 0, 0, 0, 0            ; D282000B 042E3504
	V_ADD_F32_e32 v11, -1.000000e-01, v11              ; 061616FF BDCCCCCD
	EXP 15, 33, 0, 0, 0, v9, v10, v0, v11              ; F800021F 0B000A09
	S_WAITCNT expcnt(0)                                ; BF8C070F
	V_MOV_B32_e32 v0, s3                               ; 7E000203
	V_MOV_B32_e32 v9, s2                               ; 7E120202
	V_MAD_F32 v10, v8, v9, v0, 0, 0, 0, 0              ; D282000A 04021308
	V_SUB_F32_e32 v11, 1.000000e+00, v10               ; 081614F2
	V_MAD_F32 v12, v5, v9, v0, 0, 0, 0, 0              ; D282000C 04021305
	V_MUL_F32_e32 v12, v12, v12                        ; 1018190C
	V_MAD_F32 v12, v10, v12, v11, 0, 0, 0, 0           ; D282000C 042E190A
	V_MAD_F32 v13, v6, v9, v0, 0, 0, 0, 0              ; D282000D 04021306
	V_MUL_F32_e32 v13, v13, v13                        ; 101A1B0D
	V_MAD_F32 v13, v10, v13, v11, 0, 0, 0, 0           ; D282000D 042E1B0A
	V_MAD_F32 v0, v7, v9, v0, 0, 0, 0, 0               ; D2820000 04021307
	V_MUL_F32_e32 v0, v0, v0                           ; 10000100
	V_MAD_F32 v0, v10, v0, v11, 0, 0, 0, 0             ; D2820000 042E010A
	EXP 15, 34, 0, 0, 0, v0, v13, v12, v10             ; F800022F 0A0C0D00
	S_WAITCNT expcnt(0)                                ; BF8C070F
	V_MUL_F32_e64 v0, v58, v34, 0, 0, 0, 0             ; D2100000 0202453A
	V_MAD_F32 v0, v59, v33, v0, 0, 0, 0, 0             ; D2820000 0402433B
	V_MAD_F32 v0, v57, v25, v0, 0, 0, 0, 0             ; D2820000 04023339
	V_MAD_F32 v0, v4, v21, v0, 0, 0, 0, 0              ; D2820000 04022B04
	V_MUL_F32_e64 v5, v58, v32, 0, 0, 0, 0             ; D2100005 0202413A
	V_MAD_F32 v5, v59, v31, v5, 0, 0, 0, 0             ; D2820005 04163F3B
	V_MAD_F32 v5, v57, v24, v5, 0, 0, 0, 0             ; D2820005 04163139
	V_MAD_F32 v5, v4, v20, v5, 0, 0, 0, 0              ; D2820005 04162904
	V_MUL_F32_e64 v6, v58, v30, 0, 0, 0, 0             ; D2100006 02023D3A
	V_MAD_F32 v6, v59, v29, v6, 0, 0, 0, 0             ; D2820006 041A3B3B
	V_MAD_F32 v6, v57, v23, v6, 0, 0, 0, 0             ; D2820006 041A2F39
	V_MAD_F32 v6, v4, v19, v6, 0, 0, 0, 0              ; D2820006 041A2704
	V_MUL_F32_e64 v7, v58, v28, 0, 0, 0, 0             ; D2100007 0202393A
	V_MAD_F32 v7, v59, v27, v7, 0, 0, 0, 0             ; D2820007 041E373B
	V_MAD_F32 v7, v57, v22, v7, 0, 0, 0, 0             ; D2820007 041E2D39
	V_MAD_F32 v1, v4, v18, v7, 0, 0, 0, 0              ; D2820001 041E2504
	EXP 15, 12, 0, 0, 0, v1, v6, v5, v0                ; F80000CF 00050601
	S_LOAD_DWORDX4 s[0:3], s[0:1], 64                  ; C0800140
	S_WAITCNT expcnt(0) lgkmcnt(0)                     ; BF8C000F
	S_BUFFER_LOAD_DWORD s4, s[0:3], 13                 ; C202010D
	S_WAITCNT lgkmcnt(0)                               ; BF8C007F
	V_MUL_F32_e32 v2, s4, v6                           ; 10040C04
	S_BUFFER_LOAD_DWORD s4, s[0:3], 12                 ; C202010C
	S_WAITCNT lgkmcnt(0)                               ; BF8C007F
	V_MAD_F32 v2, s4, v1, v2, 0, 0, 0, 0               ; D2820002 040A0204
	S_BUFFER_LOAD_DWORD s4, s[0:3], 14                 ; C202010E
	S_WAITCNT lgkmcnt(0)                               ; BF8C007F
	V_MAD_F32 v2, s4, v5, v2, 0, 0, 0, 0               ; D2820002 040A0A04
	S_BUFFER_LOAD_DWORD s4, s[0:3], 15                 ; C202010F
	S_WAITCNT lgkmcnt(0)                               ; BF8C007F
	V_MAD_F32 v2, s4, v0, v2, 0, 0, 0, 0               ; D2820002 040A0004
	S_BUFFER_LOAD_DWORD s4, s[0:3], 9                  ; C2020109
	S_WAITCNT lgkmcnt(0)                               ; BF8C007F
	V_MUL_F32_e32 v3, s4, v6                           ; 10060C04
	S_BUFFER_LOAD_DWORD s4, s[0:3], 8                  ; C2020108
	S_WAITCNT lgkmcnt(0)                               ; BF8C007F
	V_MAD_F32 v3, s4, v1, v3, 0, 0, 0, 0               ; D2820003 040E0204
	S_BUFFER_LOAD_DWORD s4, s[0:3], 10                 ; C202010A
	S_WAITCNT lgkmcnt(0)                               ; BF8C007F
	V_MAD_F32 v3, s4, v5, v3, 0, 0, 0, 0               ; D2820003 040E0A04
	S_BUFFER_LOAD_DWORD s4, s[0:3], 11                 ; C202010B
	S_WAITCNT lgkmcnt(0)                               ; BF8C007F
	V_MAD_F32 v3, s4, v0, v3, 0, 0, 0, 0               ; D2820003 040E0004
	S_BUFFER_LOAD_DWORD s4, s[0:3], 5                  ; C2020105
	S_WAITCNT lgkmcnt(0)                               ; BF8C007F
	V_MUL_F32_e32 v4, s4, v6                           ; 10080C04
	S_BUFFER_LOAD_DWORD s4, s[0:3], 4                  ; C2020104
	S_WAITCNT lgkmcnt(0)                               ; BF8C007F
	V_MAD_F32 v4, s4, v1, v4, 0, 0, 0, 0               ; D2820004 04120204
	S_BUFFER_LOAD_DWORD s4, s[0:3], 6                  ; C2020106
	S_WAITCNT lgkmcnt(0)                               ; BF8C007F
	V_MAD_F32 v4, s4, v5, v4, 0, 0, 0, 0               ; D2820004 04120A04
	S_BUFFER_LOAD_DWORD s4, s[0:3], 7                  ; C2020107
	S_WAITCNT lgkmcnt(0)                               ; BF8C007F
	V_MAD_F32 v4, s4, v0, v4, 0, 0, 0, 0               ; D2820004 04120004
	S_BUFFER_LOAD_DWORD s4, s[0:3], 1                  ; C2020101
	S_WAITCNT lgkmcnt(0)                               ; BF8C007F
	V_MUL_F32_e32 v6, s4, v6                           ; 100C0C04
	S_BUFFER_LOAD_DWORD s4, s[0:3], 0                  ; C2020100
	S_WAITCNT lgkmcnt(0)                               ; BF8C007F
	V_MAD_F32 v1, s4, v1, v6, 0, 0, 0, 0               ; D2820001 041A0204
	S_BUFFER_LOAD_DWORD s4, s[0:3], 2                  ; C2020102
	S_WAITCNT lgkmcnt(0)                               ; BF8C007F
	V_MAD_F32 v1, s4, v5, v1, 0, 0, 0, 0               ; D2820001 04060A04
	S_BUFFER_LOAD_DWORD s0, s[0:3], 3                  ; C2000103
	S_WAITCNT lgkmcnt(0)                               ; BF8C007F
	V_MAD_F32 v0, s0, v0, v1, 0, 0, 0, 0               ; D2820000 04060000
	EXP 15, 13, 0, 1, 0, v0, v4, v3, v2                ; F80008DF 02030400
	S_ENDPGM                                           ; BF810000

FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL OUT[0], COLOR
IMM[0] FLT32 {    1.0000,     0.0000,     0.0000,     0.0000}
  0: MOV OUT[0], IMM[0].xxxx
  1: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %21 = call i32 @llvm.SI.packf16(float 1.000000e+00, float 1.000000e+00)
  %22 = bitcast i32 %21 to float
  %23 = call i32 @llvm.SI.packf16(float 1.000000e+00, float 1.000000e+00)
  %24 = bitcast i32 %23 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %22, float %24, float %22, float %24)
  ret void
}

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
# Machine code for function main: Post SSA, not tracking liveness

BB#0: derived from LLVM BB %main_body
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e64 1.000000e+00, 1.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR0<kill>, %VGPR0, %VGPR0, %VGPR0, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	V_CVT_PKRTZ_F16_F32_e64 v0, 1.000000e+00, 1.000000e+00, 0, 0, 0, 0 ; D25E0000 0201E4F2
	EXP 15, 0, 1, 1, 1, v0, v0, v0, v0                                 ; F8001C0F 00000000
	S_ENDPGM                                                           ; BF810000

VERT
DCL IN[0]
DCL OUT[0], POSITION
DCL CONST[0..6]
DCL TEMP[0..2], LOCAL
IMM[0] FLT32 {    1.0000,     0.0000,     0.0000,     0.0000}
  0: DP4 TEMP[0].x, IN[0], CONST[0]
  1: DP4 TEMP[1].x, IN[0], CONST[1]
  2: MOV TEMP[0].y, TEMP[1].xxxx
  3: DP4 TEMP[1].x, IN[0], CONST[2]
  4: MOV TEMP[0].z, TEMP[1].xxxx
  5: MOV TEMP[0].xyz, TEMP[0].xyzx
  6: MOV TEMP[0].w, IMM[0].xxxx
  7: DP4 TEMP[1].x, TEMP[0], CONST[3]
  8: DP4 TEMP[2].x, TEMP[0], CONST[4]
  9: MOV TEMP[1].y, TEMP[2].xxxx
 10: DP4 TEMP[2].x, TEMP[0], CONST[5]
 11: MOV TEMP[1].z, TEMP[2].xxxx
 12: DP4 TEMP[0].x, TEMP[0], CONST[6]
 13: MOV TEMP[1].w, TEMP[0].xxxx
 14: MOV OUT[0], TEMP[1]
 15: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0)
  %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4)
  %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8)
  %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12)
  %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16)
  %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20)
  %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24)
  %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28)
  %20 = call float @llvm.SI.load.const(<16 x i8> %11, i32 32)
  %21 = call float @llvm.SI.load.const(<16 x i8> %11, i32 36)
  %22 = call float @llvm.SI.load.const(<16 x i8> %11, i32 40)
  %23 = call float @llvm.SI.load.const(<16 x i8> %11, i32 44)
  %24 = call float @llvm.SI.load.const(<16 x i8> %11, i32 48)
  %25 = call float @llvm.SI.load.const(<16 x i8> %11, i32 52)
  %26 = call float @llvm.SI.load.const(<16 x i8> %11, i32 56)
  %27 = call float @llvm.SI.load.const(<16 x i8> %11, i32 60)
  %28 = call float @llvm.SI.load.const(<16 x i8> %11, i32 64)
  %29 = call float @llvm.SI.load.const(<16 x i8> %11, i32 68)
  %30 = call float @llvm.SI.load.const(<16 x i8> %11, i32 72)
  %31 = call float @llvm.SI.load.const(<16 x i8> %11, i32 76)
  %32 = call float @llvm.SI.load.const(<16 x i8> %11, i32 80)
  %33 = call float @llvm.SI.load.const(<16 x i8> %11, i32 84)
  %34 = call float @llvm.SI.load.const(<16 x i8> %11, i32 88)
  %35 = call float @llvm.SI.load.const(<16 x i8> %11, i32 92)
  %36 = call float @llvm.SI.load.const(<16 x i8> %11, i32 96)
  %37 = call float @llvm.SI.load.const(<16 x i8> %11, i32 100)
  %38 = call float @llvm.SI.load.const(<16 x i8> %11, i32 104)
  %39 = call float @llvm.SI.load.const(<16 x i8> %11, i32 108)
  %40 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0
  %41 = load <16 x i8> addrspace(2)* %40, !tbaa !0
  %42 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %41, i32 0, i32 %6)
  %43 = extractelement <4 x float> %42, i32 0
  %44 = extractelement <4 x float> %42, i32 1
  %45 = extractelement <4 x float> %42, i32 2
  %46 = extractelement <4 x float> %42, i32 3
  %47 = fmul float %43, %12
  %48 = fmul float %44, %13
  %49 = fadd float %47, %48
  %50 = fmul float %45, %14
  %51 = fadd float %49, %50
  %52 = fmul float %46, %15
  %53 = fadd float %51, %52
  %54 = fmul float %43, %16
  %55 = fmul float %44, %17
  %56 = fadd float %54, %55
  %57 = fmul float %45, %18
  %58 = fadd float %56, %57
  %59 = fmul float %46, %19
  %60 = fadd float %58, %59
  %61 = fmul float %43, %20
  %62 = fmul float %44, %21
  %63 = fadd float %61, %62
  %64 = fmul float %45, %22
  %65 = fadd float %63, %64
  %66 = fmul float %46, %23
  %67 = fadd float %65, %66
  %68 = fmul float %53, %24
  %69 = fmul float %60, %25
  %70 = fadd float %68, %69
  %71 = fmul float %67, %26
  %72 = fadd float %70, %71
  %73 = fmul float 1.000000e+00, %27
  %74 = fadd float %72, %73
  %75 = fmul float %53, %28
  %76 = fmul float %60, %29
  %77 = fadd float %75, %76
  %78 = fmul float %67, %30
  %79 = fadd float %77, %78
  %80 = fmul float 1.000000e+00, %31
  %81 = fadd float %79, %80
  %82 = fmul float %53, %32
  %83 = fmul float %60, %33
  %84 = fadd float %82, %83
  %85 = fmul float %67, %34
  %86 = fadd float %84, %85
  %87 = fmul float 1.000000e+00, %35
  %88 = fadd float %86, %87
  %89 = fmul float %53, %36
  %90 = fmul float %60, %37
  %91 = fadd float %89, %90
  %92 = fmul float %67, %38
  %93 = fadd float %91, %92
  %94 = fmul float 1.000000e+00, %39
  %95 = fadd float %93, %94
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %74, float %81, float %88, float %95)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg6

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%43](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%11](align=8)(tbaa=!"const")
	S_WAITCNT 112
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR4<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e64 %VGPR1, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 0; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR0, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR2, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 3; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR3, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 5; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MUL_F32_e64 %VGPR1, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 4; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR0, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 6; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR2, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 7; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR3, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 25; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR5, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 24; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR4, %SGPR4<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 9; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MUL_F32_e64 %VGPR1, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 8; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR8<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR0, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 10; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR8<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR2, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 11; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR8<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR3, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 26; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR0, %SGPR4<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 27; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR1<def> = V_ADD_F32_e32 %SGPR4<kill>, %VGPR1<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 21; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR5, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 20; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR4, %SGPR4<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 22; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR0, %SGPR4<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 23; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR2<def> = V_ADD_F32_e32 %SGPR4<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 17; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR5, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 16; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR4, %SGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 18; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR0, %SGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 19; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR3<def> = V_ADD_F32_e32 %SGPR4<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 13; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR5<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 12; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR4<kill>, %SGPR4<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 14; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR0<def> = V_MAD_F32 %VGPR0<kill>, %SGPR4<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 15; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR0<def> = V_ADD_F32_e32 %SGPR0<kill>, %VGPR0<kill>, %EXEC<imp-use>
	EXP 15, 12, 0, 1, 0, %VGPR0<kill>, %VGPR3<kill>, %VGPR2<kill>, %VGPR1<kill>, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_LOAD_DWORDX4 s[4:7], s[6:7], 0               ; C0820700
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	BUFFER_LOAD_FORMAT_XYZW v[0:3], s[4:7][v0] + 0 ; E00C2000 80010000
	S_LOAD_DWORDX4 s[0:3], s[0:1], 0               ; C0800100
	S_WAITCNT vmcnt(0) lgkmcnt(0)                  ; BF8C0070
	S_BUFFER_LOAD_DWORD s4, s[0:3], 1              ; C2020101
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v4, s4                           ; 7E080204
	V_MUL_F32_e64 v4, v1, v4, 0, 0, 0, 0           ; D2100004 02020901
	S_BUFFER_LOAD_DWORD s4, s[0:3], 0              ; C2020100
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v5, s4                           ; 7E0A0204
	V_MAD_F32 v4, v0, v5, v4, 0, 0, 0, 0           ; D2820004 04120B00
	S_BUFFER_LOAD_DWORD s4, s[0:3], 2              ; C2020102
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v5, s4                           ; 7E0A0204
	V_MAD_F32 v4, v2, v5, v4, 0, 0, 0, 0           ; D2820004 04120B02
	S_BUFFER_LOAD_DWORD s4, s[0:3], 3              ; C2020103
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v5, s4                           ; 7E0A0204
	V_MAD_F32 v4, v3, v5, v4, 0, 0, 0, 0           ; D2820004 04120B03
	S_BUFFER_LOAD_DWORD s4, s[0:3], 5              ; C2020105
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v5, s4                           ; 7E0A0204
	V_MUL_F32_e64 v5, v1, v5, 0, 0, 0, 0           ; D2100005 02020B01
	S_BUFFER_LOAD_DWORD s4, s[0:3], 4              ; C2020104
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v6, s4                           ; 7E0C0204
	V_MAD_F32 v5, v0, v6, v5, 0, 0, 0, 0           ; D2820005 04160D00
	S_BUFFER_LOAD_DWORD s4, s[0:3], 6              ; C2020106
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v6, s4                           ; 7E0C0204
	V_MAD_F32 v5, v2, v6, v5, 0, 0, 0, 0           ; D2820005 04160D02
	S_BUFFER_LOAD_DWORD s4, s[0:3], 7              ; C2020107
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v6, s4                           ; 7E0C0204
	V_MAD_F32 v5, v3, v6, v5, 0, 0, 0, 0           ; D2820005 04160D03
	S_BUFFER_LOAD_DWORD s4, s[0:3], 25             ; C2020119
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MUL_F32_e32 v6, s4, v5                       ; 100C0A04
	S_BUFFER_LOAD_DWORD s4, s[0:3], 24             ; C2020118
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MAD_F32 v6, v4, s4, v6, 0, 0, 0, 0           ; D2820006 04180904
	S_BUFFER_LOAD_DWORD s4, s[0:3], 9              ; C2020109
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v7, s4                           ; 7E0E0204
	V_MUL_F32_e64 v7, v1, v7, 0, 0, 0, 0           ; D2100007 02020F01
	S_BUFFER_LOAD_DWORD s4, s[0:3], 8              ; C2020108
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v8, s4                           ; 7E100204
	V_MAD_F32 v7, v0, v8, v7, 0, 0, 0, 0           ; D2820007 041E1100
	S_BUFFER_LOAD_DWORD s4, s[0:3], 10             ; C202010A
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v8, s4                           ; 7E100204
	V_MAD_F32 v7, v2, v8, v7, 0, 0, 0, 0           ; D2820007 041E1102
	S_BUFFER_LOAD_DWORD s4, s[0:3], 11             ; C202010B
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v8, s4                           ; 7E100204
	V_MAD_F32 v0, v3, v8, v7, 0, 0, 0, 0           ; D2820000 041E1103
	S_BUFFER_LOAD_DWORD s4, s[0:3], 26             ; C202011A
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MAD_F32 v1, v0, s4, v6, 0, 0, 0, 0           ; D2820001 04180900
	S_BUFFER_LOAD_DWORD s4, s[0:3], 27             ; C202011B
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_ADD_F32_e32 v1, s4, v1                       ; 06020204
	S_BUFFER_LOAD_DWORD s4, s[0:3], 21             ; C2020115
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MUL_F32_e32 v2, s4, v5                       ; 10040A04
	S_BUFFER_LOAD_DWORD s4, s[0:3], 20             ; C2020114
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MAD_F32 v2, v4, s4, v2, 0, 0, 0, 0           ; D2820002 04080904
	S_BUFFER_LOAD_DWORD s4, s[0:3], 22             ; C2020116
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MAD_F32 v2, v0, s4, v2, 0, 0, 0, 0           ; D2820002 04080900
	S_BUFFER_LOAD_DWORD s4, s[0:3], 23             ; C2020117
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_ADD_F32_e32 v2, s4, v2                       ; 06040404
	S_BUFFER_LOAD_DWORD s4, s[0:3], 17             ; C2020111
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MUL_F32_e32 v3, s4, v5                       ; 10060A04
	S_BUFFER_LOAD_DWORD s4, s[0:3], 16             ; C2020110
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MAD_F32 v3, v4, s4, v3, 0, 0, 0, 0           ; D2820003 040C0904
	S_BUFFER_LOAD_DWORD s4, s[0:3], 18             ; C2020112
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MAD_F32 v3, v0, s4, v3, 0, 0, 0, 0           ; D2820003 040C0900
	S_BUFFER_LOAD_DWORD s4, s[0:3], 19             ; C2020113
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_ADD_F32_e32 v3, s4, v3                       ; 06060604
	S_BUFFER_LOAD_DWORD s4, s[0:3], 13             ; C202010D
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MUL_F32_e32 v5, s4, v5                       ; 100A0A04
	S_BUFFER_LOAD_DWORD s4, s[0:3], 12             ; C202010C
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MAD_F32 v4, v4, s4, v5, 0, 0, 0, 0           ; D2820004 04140904
	S_BUFFER_LOAD_DWORD s4, s[0:3], 14             ; C202010E
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MAD_F32 v0, v0, s4, v4, 0, 0, 0, 0           ; D2820000 04100900
	S_BUFFER_LOAD_DWORD s0, s[0:3], 15             ; C200010F
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_ADD_F32_e32 v0, s0, v0                       ; 06000000
	EXP 15, 12, 0, 1, 0, v0, v3, v2, v1            ; F80008CF 01020300
	S_ENDPGM                                       ; BF810000

FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL TEMP[0..2], LOCAL
IMM[0] FLT32 {32767.0000,     7.9688,     0.0000,   128.0000}
IMM[1] FLT32 {    0.0039,     0.0000,    32.0000,   -16.0000}
  0: MOV TEMP[0].xy, IN[0].xyyy
  1: TEX TEMP[0].xyz, TEMP[0], SAMP[0], 2D
  2: MIN TEMP[0].xyz, TEMP[0].xyzz, IMM[0].xxxx
  3: MAX TEMP[1].x, TEMP[0].xxxx, TEMP[0].yyyy
  4: MAX TEMP[1].x, TEMP[1].xxxx, TEMP[0].zzzz
  5: ADD TEMP[1].x, TEMP[1].xxxx, IMM[0].zzzz
  6: LG2 TEMP[1].x, TEMP[1].xxxx
  7: MAD TEMP[1].x, IMM[0].yyyy, TEMP[1].xxxx, IMM[0].wwww
  8: CEIL TEMP[1].x, TEMP[1].xxxx
  9: MUL TEMP[1].x, TEMP[1].xxxx, IMM[1].xxxx
 10: MAX TEMP[1].x, TEMP[1].xxxx, IMM[1].yyyy
 11: MAD TEMP[2].x, TEMP[1].xxxx, IMM[1].zzzz, IMM[1].wwww
 12: EX2 TEMP[2].x, TEMP[2].xxxx
 13: RCP TEMP[2].x, TEMP[2].xxxx
 14: MUL TEMP[0].xyz, TEMP[0].xyzz, TEMP[2].xxxx
 15: MOV TEMP[0].w, TEMP[1].xxxx
 16: MOV OUT[0], TEMP[0]
 17: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %21 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0
  %22 = load <32 x i8> addrspace(2)* %21, !tbaa !0
  %23 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0
  %24 = load <16 x i8> addrspace(2)* %23, !tbaa !0
  %25 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %4, <2 x i32> %6)
  %26 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %4, <2 x i32> %6)
  %27 = bitcast float %25 to i32
  %28 = bitcast float %26 to i32
  %29 = insertelement <2 x i32> undef, i32 %27, i32 0
  %30 = insertelement <2 x i32> %29, i32 %28, i32 1
  %31 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %30, <32 x i8> %22, <16 x i8> %24, i32 2)
  %32 = extractelement <4 x float> %31, i32 0
  %33 = extractelement <4 x float> %31, i32 1
  %34 = extractelement <4 x float> %31, i32 2
  %35 = fcmp uge float %32, 3.276700e+04
  %36 = select i1 %35, float 3.276700e+04, float %32
  %37 = fcmp uge float %33, 3.276700e+04
  %38 = select i1 %37, float 3.276700e+04, float %33
  %39 = fcmp uge float %34, 3.276700e+04
  %40 = select i1 %39, float 3.276700e+04, float %34
  %41 = fcmp uge float %36, %38
  %42 = select i1 %41, float %36, float %38
  %43 = fcmp uge float %42, %40
  %44 = select i1 %43, float %42, float %40
  %45 = fadd float %44, 0x3EE0000000000000
  %46 = call float @llvm.log2.f32(float %45)
  %47 = fmul float 7.968750e+00, %46
  %48 = fadd float %47, 1.280000e+02
  %49 = call float @ceil(float %48)
  %50 = fmul float %49, 0x3F70101020000000
  %51 = fcmp uge float %50, 0.000000e+00
  %52 = select i1 %51, float %50, float 0.000000e+00
  %53 = fmul float %52, 3.200000e+01
  %54 = fadd float %53, -1.600000e+01
  %55 = call float @llvm.AMDIL.exp.(float %54)
  %56 = fdiv float 1.000000e+00, %55
  %57 = fmul float %36, %56
  %58 = fmul float %38, %56
  %59 = fmul float %40, %56
  %60 = call i32 @llvm.SI.packf16(float %57, float %58)
  %61 = bitcast i32 %60 to float
  %62 = call i32 @llvm.SI.packf16(float %59, float %52)
  %63 = bitcast i32 %62 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %61, float %63, float %61, float %63)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readonly
declare float @llvm.log2.f32(float) #2

; Function Attrs: readonly
declare float @ceil(float) #3

; Function Attrs: readnone
declare float @llvm.AMDIL.exp.(float) #4

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { nounwind readonly }
attributes #3 = { readonly }
attributes #4 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR7 in %vreg4, %VGPR0 in %vreg5, %VGPR1 in %vreg6

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR7 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR7
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-def>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%24](align=8)(tbaa=!"const")
	%SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%21](tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2<def> = IMAGE_SAMPLE_V3_V2 7, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3<kill>, %SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<kill>, %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%SGPR0_SGPR1<def> = V_CMP_U_F32_e64 %VGPR1, %VGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_MOV_B32_e32 3.276700e+04, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR1, %VGPR3, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_OR_B64 %SGPR2_SGPR3<kill>, %SGPR0_SGPR1<kill>
	%VGPR4<def> = V_CNDMASK_B32_e64 %VGPR1, %VGPR3, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = V_CMP_U_F32_e64 %VGPR0, %VGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR0, %VGPR3, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_OR_B64 %SGPR2_SGPR3<kill>, %SGPR0_SGPR1<kill>
	%VGPR5<def> = V_CNDMASK_B32_e64 %VGPR0, %VGPR3, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = V_CMP_U_F32_e64 %VGPR5, %VGPR4, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR5, %VGPR4, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_OR_B64 %SGPR2_SGPR3<kill>, %SGPR0_SGPR1<kill>
	%VGPR6<def> = V_CNDMASK_B32_e64 %VGPR4, %VGPR5, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = V_CMP_U_F32_e64 %VGPR2, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR2, %VGPR3, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_OR_B64 %SGPR2_SGPR3<kill>, %SGPR0_SGPR1<kill>
	%VGPR0<def> = V_CNDMASK_B32_e64 %VGPR2, %VGPR3<kill>, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2<imp-use,kill>
	%SGPR0_SGPR1<def> = V_CMP_U_F32_e64 %VGPR6, %VGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR6, %VGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_OR_B64 %SGPR2_SGPR3<kill>, %SGPR0_SGPR1<kill>
	%VGPR1<def> = V_CNDMASK_B32_e64 %VGPR0, %VGPR6<kill>, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_ADD_F32_e32 7.629395e-06, %VGPR1<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_LOG_F32_e32 %VGPR1<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_MOV_B32_e32 1.280000e+02, %EXEC<imp-use>
	%VGPR3<def> = V_MOV_B32_e32 7.968750e+00, %EXEC<imp-use>
	%VGPR1<def> = V_MAD_F32 %VGPR1<kill>, %VGPR3<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_CEIL_F32_e32 %VGPR1<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_MUL_F32_e32 3.921569e-03, %VGPR1<kill>, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = V_CMP_U_F32_e64 %VGPR1, %VGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR1, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_OR_B64 %SGPR2_SGPR3<kill>, %SGPR0_SGPR1<kill>
	%VGPR1<def> = V_CNDMASK_B32_e64 0.000000e+00, %VGPR1<kill>, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR2<def> = V_MOV_B32_e32 -1.600000e+01, %EXEC<imp-use>
	%VGPR3<def> = V_MOV_B32_e32 3.200000e+01, %EXEC<imp-use>
	%VGPR2<def> = V_MAD_F32 %VGPR1, %VGPR3<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR2<def> = V_EXP_F32_e32 %VGPR2<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_RCP_F32_e32 %VGPR2<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR0<kill>, %VGPR2, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0<kill>, %VGPR1<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_MUL_F32_e32 %VGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%VGPR2<def> = V_MUL_F32_e32 %VGPR5<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR2<kill>, %VGPR1<kill>, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR1<kill>, %VGPR0<kill>, %VGPR1, %VGPR0, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_WQM_B64 exec, exec                                                 ; BEFE0A7E
	S_MOV_B32 m0, s7                                                     ; BEFC0307
	V_INTERP_P1_F32 v3, v0, 1, 0, [m0]                                   ; C80C0100
	V_INTERP_P2_F32 v3, [v3], v1, 1, 0, [m0]                             ; C80D0101
	V_INTERP_P1_F32 v2, v0, 0, 0, [m0]                                   ; C8080000
	V_INTERP_P2_F32 v2, [v2], v1, 0, 0, [m0]                             ; C8090001
	S_LOAD_DWORDX4 s[0:3], s[2:3], 0                                     ; C0800300
	S_LOAD_DWORDX8 s[4:11], s[4:5], 0                                    ; C0C20500
	S_WAITCNT lgkmcnt(0)                                                 ; BF8C007F
	IMAGE_SAMPLE v[0:2], 7, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[4:11], s[0:3] ; F0800700 00010002
	S_WAITCNT vmcnt(0)                                                   ; BF8C0770
	V_CMP_U_F32_e64 s[0:1], v1, v1, 0, 0, 0, 0                           ; D0100000 02020301
	V_MOV_B32_e32 v3, 3.276700e+04                                       ; 7E0602FF 46FFFE00
	V_CMP_GE_F32_e64 s[2:3], v1, v3, 0, 0, 0, 0                          ; D00C0002 02020701
	S_OR_B64 s[0:1], s[2:3], s[0:1]                                      ; 88800002
	V_CNDMASK_B32_e64 v4, v1, v3, s[0:1], 0, 0, 0, 0                     ; D2000004 00020701
	V_CMP_U_F32_e64 s[0:1], v0, v0, 0, 0, 0, 0                           ; D0100000 02020100
	V_CMP_GE_F32_e64 s[2:3], v0, v3, 0, 0, 0, 0                          ; D00C0002 02020700
	S_OR_B64 s[0:1], s[2:3], s[0:1]                                      ; 88800002
	V_CNDMASK_B32_e64 v5, v0, v3, s[0:1], 0, 0, 0, 0                     ; D2000005 00020700
	V_CMP_U_F32_e64 s[0:1], v5, v4, 0, 0, 0, 0                           ; D0100000 02020905
	V_CMP_GE_F32_e64 s[2:3], v5, v4, 0, 0, 0, 0                          ; D00C0002 02020905
	S_OR_B64 s[0:1], s[2:3], s[0:1]                                      ; 88800002
	V_CNDMASK_B32_e64 v6, v4, v5, s[0:1], 0, 0, 0, 0                     ; D2000006 00020B04
	V_CMP_U_F32_e64 s[0:1], v2, v2, 0, 0, 0, 0                           ; D0100000 02020502
	V_CMP_GE_F32_e64 s[2:3], v2, v3, 0, 0, 0, 0                          ; D00C0002 02020702
	S_OR_B64 s[0:1], s[2:3], s[0:1]                                      ; 88800002
	V_CNDMASK_B32_e64 v0, v2, v3, s[0:1], 0, 0, 0, 0                     ; D2000000 00020702
	V_CMP_U_F32_e64 s[0:1], v6, v0, 0, 0, 0, 0                           ; D0100000 02020106
	V_CMP_GE_F32_e64 s[2:3], v6, v0, 0, 0, 0, 0                          ; D00C0002 02020106
	S_OR_B64 s[0:1], s[2:3], s[0:1]                                      ; 88800002
	V_CNDMASK_B32_e64 v1, v0, v6, s[0:1], 0, 0, 0, 0                     ; D2000001 00020D00
	V_ADD_F32_e32 v1, 7.629395e-06, v1                                   ; 060202FF 37000000
	V_LOG_F32_e32 v1, v1                                                 ; 7E024F01
	V_MOV_B32_e32 v2, 1.280000e+02                                       ; 7E0402FF 43000000
	V_MOV_B32_e32 v3, 7.968750e+00                                       ; 7E0602FF 40FF0000
	V_MAD_F32 v1, v1, v3, v2, 0, 0, 0, 0                                 ; D2820001 040A0701
	V_CEIL_F32_e32 v1, v1                                                ; 7E024501
	V_MUL_F32_e32 v1, 3.921569e-03, v1                                   ; 100202FF 3B808081
	V_CMP_U_F32_e64 s[0:1], v1, v1, 0, 0, 0, 0                           ; D0100000 02020301
	V_CMP_GE_F32_e64 s[2:3], v1, 0.000000e+00, 0, 0, 0, 0                ; D00C0002 02010101
	S_OR_B64 s[0:1], s[2:3], s[0:1]                                      ; 88800002
	V_CNDMASK_B32_e64 v1, 0.000000e+00, v1, s[0:1], 0, 0, 0, 0           ; D2000001 00020280
	V_MOV_B32_e32 v2, -1.600000e+01                                      ; 7E0402FF C1800000
	V_MOV_B32_e32 v3, 3.200000e+01                                       ; 7E0602FF 42000000
	V_MAD_F32 v2, v1, v3, v2, 0, 0, 0, 0                                 ; D2820002 040A0701
	V_EXP_F32_e32 v2, v2                                                 ; 7E044B02
	V_RCP_F32_e32 v2, v2                                                 ; 7E045502
	V_MUL_F32_e32 v0, v0, v2                                             ; 10000500
	V_CVT_PKRTZ_F16_F32_e32 v0, v0, v1                                   ; 5E000300
	V_MUL_F32_e32 v1, v4, v2                                             ; 10020504
	V_MUL_F32_e32 v2, v5, v2                                             ; 10040505
	V_CVT_PKRTZ_F16_F32_e32 v1, v2, v1                                   ; 5E020302
	EXP 15, 0, 1, 1, 1, v1, v0, v1, v0                                   ; F8001C0F 00010001
	S_ENDPGM                                                             ; BF810000

VERT
DCL IN[0]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[19]
DCL CONST[0..1]
DCL TEMP[0..2], LOCAL
IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
  0: MOV TEMP[0].zw, IMM[0].yyxy
  1: MOV TEMP[0].xy, IN[0].xyxx
  2: MAD TEMP[1].xy, IN[0].zwww, CONST[0].xyyy, CONST[0].zwww
  3: MAD TEMP[2].xy, IN[0].zwww, CONST[1].xyyy, CONST[1].zwww
  4: MOV TEMP[1].zw, TEMP[2].yyxy
  5: MOV OUT[1], TEMP[1]
  6: MOV OUT[0], TEMP[0]
  7: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0)
  %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4)
  %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8)
  %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12)
  %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16)
  %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20)
  %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24)
  %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28)
  %20 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %21, i32 0, i32 %6)
  %23 = extractelement <4 x float> %22, i32 0
  %24 = extractelement <4 x float> %22, i32 1
  %25 = extractelement <4 x float> %22, i32 2
  %26 = extractelement <4 x float> %22, i32 3
  %27 = fmul float %25, %12
  %28 = fadd float %27, %14
  %29 = fmul float %26, %13
  %30 = fadd float %29, %15
  %31 = fmul float %25, %16
  %32 = fadd float %31, %18
  %33 = fmul float %26, %17
  %34 = fadd float %33, %19
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %28, float %30, float %32, float %34)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %23, float %24, float 0.000000e+00, float 1.000000e+00)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg6

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%23](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%11](align=8)(tbaa=!"const")
	S_WAITCNT 112
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 7; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR4<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 5; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR3, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 6; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 4; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR2, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 3; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR3, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 0; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR8<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR2, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 32, 0, 0, 0, %VGPR7<kill>, %VGPR6<kill>, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>
	S_WAITCNT 1807
	%VGPR4<def> = V_MOV_B32_e32 1.000000e+00, %EXEC<imp-use>
	%VGPR5<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR1, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_LOAD_DWORDX4 s[4:7], s[6:7], 0               ; C0820700
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	BUFFER_LOAD_FORMAT_XYZW v[0:3], s[4:7][v0] + 0 ; E00C2000 80010000
	S_LOAD_DWORDX4 s[0:3], s[0:1], 0               ; C0800100
	S_WAITCNT vmcnt(0) lgkmcnt(0)                  ; BF8C0070
	S_BUFFER_LOAD_DWORD s4, s[0:3], 7              ; C2020107
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v4, s4                           ; 7E080204
	S_BUFFER_LOAD_DWORD s4, s[0:3], 5              ; C2020105
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v5, s4                           ; 7E0A0204
	V_MAD_F32 v4, v3, v5, v4, 0, 0, 0, 0           ; D2820004 04120B03
	S_BUFFER_LOAD_DWORD s4, s[0:3], 6              ; C2020106
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v5, s4                           ; 7E0A0204
	S_BUFFER_LOAD_DWORD s4, s[0:3], 4              ; C2020104
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v6, s4                           ; 7E0C0204
	V_MAD_F32 v5, v2, v6, v5, 0, 0, 0, 0           ; D2820005 04160D02
	S_BUFFER_LOAD_DWORD s4, s[0:3], 3              ; C2020103
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v6, s4                           ; 7E0C0204
	S_BUFFER_LOAD_DWORD s4, s[0:3], 1              ; C2020101
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v7, s4                           ; 7E0E0204
	V_MAD_F32 v6, v3, v7, v6, 0, 0, 0, 0           ; D2820006 041A0F03
	S_BUFFER_LOAD_DWORD s4, s[0:3], 2              ; C2020102
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v7, s4                           ; 7E0E0204
	S_BUFFER_LOAD_DWORD s0, s[0:3], 0              ; C2000100
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v8, s0                           ; 7E100200
	V_MAD_F32 v7, v2, v8, v7, 0, 0, 0, 0           ; D2820007 041E1102
	EXP 15, 32, 0, 0, 0, v7, v6, v5, v4            ; F800020F 04050607
	S_WAITCNT expcnt(0)                            ; BF8C070F
	V_MOV_B32_e32 v4, 1.000000e+00                 ; 7E0802F2
	V_MOV_B32_e32 v5, 0.000000e+00                 ; 7E0A0280
	EXP 15, 12, 0, 1, 0, v0, v1, v5, v4            ; F80008CF 04050100
	S_ENDPGM                                       ; BF810000

VERT
DCL IN[0]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[19]
DCL CONST[0..1]
DCL TEMP[0..2], LOCAL
IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
  0: MOV TEMP[0].zw, IMM[0].yyxy
  1: MOV TEMP[0].xy, IN[0].xyxx
  2: MAD TEMP[1].xy, IN[0].zwww, CONST[0].xyyy, CONST[0].zwww
  3: MAD TEMP[2].xy, IN[0].zwww, CONST[1].xyyy, CONST[1].zwww
  4: MOV TEMP[1].zw, TEMP[2].yyxy
  5: MOV OUT[1], TEMP[1]
  6: MOV OUT[0], TEMP[0]
  7: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0)
  %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4)
  %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8)
  %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12)
  %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16)
  %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20)
  %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24)
  %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28)
  %20 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %21, i32 0, i32 %6)
  %23 = extractelement <4 x float> %22, i32 0
  %24 = extractelement <4 x float> %22, i32 1
  %25 = extractelement <4 x float> %22, i32 2
  %26 = extractelement <4 x float> %22, i32 3
  %27 = fmul float %25, %12
  %28 = fadd float %27, %14
  %29 = fmul float %26, %13
  %30 = fadd float %29, %15
  %31 = fmul float %25, %16
  %32 = fadd float %31, %18
  %33 = fmul float %26, %17
  %34 = fadd float %33, %19
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %28, float %30, float %32, float %34)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %23, float %24, float 0.000000e+00, float 1.000000e+00)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg6

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%23](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%11](align=8)(tbaa=!"const")
	S_WAITCNT 112
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 7; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR4<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 5; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR3, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 6; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 4; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR2, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 3; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR3, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 0; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR8<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR2, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 32, 0, 0, 0, %VGPR7<kill>, %VGPR6<kill>, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>
	S_WAITCNT 1807
	%VGPR4<def> = V_MOV_B32_e32 1.000000e+00, %EXEC<imp-use>
	%VGPR5<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR1, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_LOAD_DWORDX4 s[4:7], s[6:7], 0               ; C0820700
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	BUFFER_LOAD_FORMAT_XYZW v[0:3], s[4:7][v0] + 0 ; E00C2000 80010000
	S_LOAD_DWORDX4 s[0:3], s[0:1], 0               ; C0800100
	S_WAITCNT vmcnt(0) lgkmcnt(0)                  ; BF8C0070
	S_BUFFER_LOAD_DWORD s4, s[0:3], 7              ; C2020107
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v4, s4                           ; 7E080204
	S_BUFFER_LOAD_DWORD s4, s[0:3], 5              ; C2020105
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v5, s4                           ; 7E0A0204
	V_MAD_F32 v4, v3, v5, v4, 0, 0, 0, 0           ; D2820004 04120B03
	S_BUFFER_LOAD_DWORD s4, s[0:3], 6              ; C2020106
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v5, s4                           ; 7E0A0204
	S_BUFFER_LOAD_DWORD s4, s[0:3], 4              ; C2020104
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v6, s4                           ; 7E0C0204
	V_MAD_F32 v5, v2, v6, v5, 0, 0, 0, 0           ; D2820005 04160D02
	S_BUFFER_LOAD_DWORD s4, s[0:3], 3              ; C2020103
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v6, s4                           ; 7E0C0204
	S_BUFFER_LOAD_DWORD s4, s[0:3], 1              ; C2020101
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v7, s4                           ; 7E0E0204
	V_MAD_F32 v6, v3, v7, v6, 0, 0, 0, 0           ; D2820006 041A0F03
	S_BUFFER_LOAD_DWORD s4, s[0:3], 2              ; C2020102
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v7, s4                           ; 7E0E0204
	S_BUFFER_LOAD_DWORD s0, s[0:3], 0              ; C2000100
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v8, s0                           ; 7E100200
	V_MAD_F32 v7, v2, v8, v7, 0, 0, 0, 0           ; D2820007 041E1102
	EXP 15, 32, 0, 0, 0, v7, v6, v5, v4            ; F800020F 04050607
	S_WAITCNT expcnt(0)                            ; BF8C070F
	V_MOV_B32_e32 v4, 1.000000e+00                 ; 7E0802F2
	V_MOV_B32_e32 v5, 0.000000e+00                 ; 7E0A0280
	EXP 15, 12, 0, 1, 0, v0, v1, v5, v4            ; F80008CF 04050100
	S_ENDPGM                                       ; BF810000

FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL OUT[0], COLOR
DCL CONST[0..13]
DCL TEMP[0..1], LOCAL
IMM[0] FLT32 {    1.0000,     0.0000,     0.2500, -2048.0000}
IMM[1] FLT32 {   -0.0005,     0.0000,     0.0000,     0.0000}
  0: MOV TEMP[0].w, IMM[0].xxxx
  1: MOV TEMP[0].z, IMM[0].yyyy
  2: MAD TEMP[0].x, IN[0].zzzz, CONST[0].zzzz, CONST[0].yyyy
  3: MOV_SAT TEMP[0].x, TEMP[0].xxxx
  4: MOV TEMP[0].x, TEMP[0].xxxx
  5: POW TEMP[1].x, TEMP[0].xxxx, IMM[0].zzzz
  6: MUL TEMP[0].x, TEMP[1].xxxx, CONST[0].wwww
  7: MUL TEMP[1].x, TEMP[0].xxxx, IMM[0].wwww
  8: FRC TEMP[1].x, TEMP[1].xxxx
  9: MOV TEMP[0].y, TEMP[1].xxxx
 10: MUL TEMP[1].x, TEMP[1].xxxx, IMM[1].xxxx
 11: ADD TEMP[0].x, TEMP[0].xxxx, -TEMP[1].xxxx
 12: MOV OUT[0], TEMP[0]
 13: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %21 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
  %22 = load <16 x i8> addrspace(2)* %21, !tbaa !0
  %23 = call float @llvm.SI.load.const(<16 x i8> %22, i32 4)
  %24 = call float @llvm.SI.load.const(<16 x i8> %22, i32 8)
  %25 = call float @llvm.SI.load.const(<16 x i8> %22, i32 12)
  %26 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %4, <2 x i32> %6)
  %27 = fmul float %26, %24
  %28 = fadd float %27, %23
  %29 = call float @llvm.AMDIL.clamp.(float %28, float 0.000000e+00, float 1.000000e+00)
  %30 = call float @llvm.pow.f32(float %29, float 2.500000e-01)
  %31 = fmul float %30, %25
  %32 = fmul float %31, -2.048000e+03
  %33 = call float @llvm.AMDIL.fraction.(float %32)
  %34 = fmul float %33, 0xBF40000000000000
  %35 = fsub float -0.000000e+00, %34
  %36 = fadd float %31, %35
  %37 = call i32 @llvm.SI.packf16(float %36, float %33)
  %38 = bitcast i32 %37 to float
  %39 = call i32 @llvm.SI.packf16(float 0.000000e+00, float 1.000000e+00)
  %40 = bitcast i32 %39 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %38, float %40, float %38, float %40)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

; Function Attrs: nounwind readonly
declare float @llvm.pow.f32(float, float) #3

; Function Attrs: readnone
declare float @llvm.AMDIL.fraction.(float) #2

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }
attributes #3 = { nounwind readonly }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR7 in %vreg4, %VGPR0 in %vreg5, %VGPR1 in %vreg6

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR7 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR7
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<kill,tied0>, %VGPR1, 2, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%22](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2; mem:LD4[<unknown>]
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR0<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR2<kill>, %SGPR4<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_F32_e64 0, %VGPR0<kill>, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_LOG_F32_e32 %VGPR0<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_LEGACY_F32_e32 2.500000e-01, %VGPR0<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_EXP_F32_e32 %VGPR0<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 3; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR0, %VGPR0, %EXEC<imp-use>
	%VGPR1<def> = V_MUL_F32_e32 -2.048000e+03, %VGPR1<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_FRACT_F32_e32 %VGPR1<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_MUL_F32_e32 4.882812e-04, %VGPR1, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR0<kill>, %SGPR0<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0<kill>, %VGPR1<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_CVT_PKRTZ_F16_F32_e64 0.000000e+00, 1.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR0<kill>, %VGPR1<kill>, %VGPR0, %VGPR1, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_WQM_B64 exec, exec                                               ; BEFE0A7E
	S_MOV_B32 m0, s7                                                   ; BEFC0307
	V_INTERP_P1_F32 v2, v0, 2, 0, [m0]                                 ; C8080200
	V_INTERP_P2_F32 v2, [v2], v1, 2, 0, [m0]                           ; C8090201
	S_LOAD_DWORDX4 s[0:3], s[0:1], 0                                   ; C0800100
	S_WAITCNT lgkmcnt(0)                                               ; BF8C007F
	S_BUFFER_LOAD_DWORD s4, s[0:3], 2                                  ; C2020102
	S_BUFFER_LOAD_DWORD s5, s[0:3], 1                                  ; C2028101
	S_WAITCNT lgkmcnt(0)                                               ; BF8C007F
	V_MOV_B32_e32 v0, s5                                               ; 7E000205
	V_MAD_F32 v0, v2, s4, v0, 0, 0, 0, 0                               ; D2820000 04000902
	V_ADD_F32_e64 v0, 0, v0, 0, 1, 0, 0                                ; D2060800 02020080
	V_LOG_F32_e32 v0, v0                                               ; 7E004F00
	V_MUL_LEGACY_F32_e32 v0, 2.500000e-01, v0                          ; 0E0000FF 3E800000
	V_EXP_F32_e32 v0, v0                                               ; 7E004B00
	S_BUFFER_LOAD_DWORD s0, s[0:3], 3                                  ; C2000103
	S_WAITCNT lgkmcnt(0)                                               ; BF8C007F
	V_MUL_F32_e32 v1, s0, v0                                           ; 10020000
	V_MUL_F32_e32 v1, -2.048000e+03, v1                                ; 100202FF C5000000
	V_FRACT_F32_e32 v1, v1                                             ; 7E024101
	V_MUL_F32_e32 v2, 4.882812e-04, v1                                 ; 100402FF 3A000000
	V_MAD_F32 v0, v0, s0, v2, 0, 0, 0, 0                               ; D2820000 04080100
	V_CVT_PKRTZ_F16_F32_e32 v0, v0, v1                                 ; 5E000300
	V_CVT_PKRTZ_F16_F32_e64 v1, 0.000000e+00, 1.000000e+00, 0, 0, 0, 0 ; D25E0001 0201E480
	EXP 15, 0, 1, 1, 1, v0, v1, v0, v1                                 ; F8001C0F 01000100
	S_ENDPGM                                                           ; BF810000

VERT
DCL IN[0]
DCL IN[1]
DCL IN[2]
DCL IN[3]
DCL OUT[0], POSITION
DCL OUT[1], CLIPVERTEX
DCL OUT[2], GENERIC[19]
DCL CONST[0..240]
DCL TEMP[0..7], LOCAL
DCL ADDR[0]
IMM[0] FLT32 {    1.0000,   255.0100,     0.0000,     0.0000}
IMM[1] INT32 {3, 41, 42, 43}
  0: MOV TEMP[0], IN[0]
  1: UIF CONST[240].xxxx :0
  2:   DP3 TEMP[1].x, IN[3].xyzz, IMM[0].xxxx
  3:   ADD TEMP[1].x, IMM[0].xxxx, -TEMP[1].xxxx
  4:   MUL TEMP[2], IN[2], IMM[0].yyyy
  5:   F2I TEMP[2], TEMP[2]
  6:   UMAD TEMP[3].x, TEMP[2].wwww, IMM[1].xxxx, IMM[1].yyyy
  7:   UMAD TEMP[4].x, TEMP[2].zzzz, IMM[1].xxxx, IMM[1].yyyy
  8:   UMAD TEMP[5].x, TEMP[2].yyyy, IMM[1].xxxx, IMM[1].yyyy
  9:   UMAD TEMP[6].x, TEMP[2].xxxx, IMM[1].xxxx, IMM[1].yyyy
 10:   UARL ADDR[0].x, TEMP[6].xxxx
 11:   MUL TEMP[6], CONST[ADDR[0].x], IN[3].xxxx
 12:   UARL ADDR[0].x, TEMP[5].xxxx
 13:   MAD TEMP[5], CONST[ADDR[0].x], IN[3].yyyy, TEMP[6]
 14:   UARL ADDR[0].x, TEMP[4].xxxx
 15:   MAD TEMP[4], CONST[ADDR[0].x], IN[3].zzzz, TEMP[5]
 16:   UARL ADDR[0].x, TEMP[3].xxxx
 17:   MAD TEMP[3], CONST[ADDR[0].x], TEMP[1].xxxx, TEMP[4]
 18:   DP4 TEMP[3].x, IN[0], TEMP[3]
 19:   UMAD TEMP[4].x, TEMP[2].wwww, IMM[1].xxxx, IMM[1].zzzz
 20:   UMAD TEMP[5].x, TEMP[2].zzzz, IMM[1].xxxx, IMM[1].zzzz
 21:   UMAD TEMP[6].x, TEMP[2].yyyy, IMM[1].xxxx, IMM[1].zzzz
 22:   UMAD TEMP[7].x, TEMP[2].xxxx, IMM[1].xxxx, IMM[1].zzzz
 23:   UARL ADDR[0].x, TEMP[7].xxxx
 24:   MUL TEMP[7], CONST[ADDR[0].x], IN[3].xxxx
 25:   UARL ADDR[0].x, TEMP[6].xxxx
 26:   MAD TEMP[6], CONST[ADDR[0].x], IN[3].yyyy, TEMP[7]
 27:   UARL ADDR[0].x, TEMP[5].xxxx
 28:   MAD TEMP[5], CONST[ADDR[0].x], IN[3].zzzz, TEMP[6]
 29:   UARL ADDR[0].x, TEMP[4].xxxx
 30:   MAD TEMP[4], CONST[ADDR[0].x], TEMP[1].xxxx, TEMP[5]
 31:   DP4 TEMP[4].x, IN[0], TEMP[4]
 32:   MOV TEMP[3].y, TEMP[4].xxxx
 33:   UMAD TEMP[4].x, TEMP[2].wwww, IMM[1].xxxx, IMM[1].wwww
 34:   UMAD TEMP[5].x, TEMP[2].zzzz, IMM[1].xxxx, IMM[1].wwww
 35:   UMAD TEMP[6].x, TEMP[2].yyyy, IMM[1].xxxx, IMM[1].wwww
 36:   UMAD TEMP[2].x, TEMP[2].xxxx, IMM[1].xxxx, IMM[1].wwww
 37:   UARL ADDR[0].x, TEMP[2].xxxx
 38:   MUL TEMP[2], CONST[ADDR[0].x], IN[3].xxxx
 39:   UARL ADDR[0].x, TEMP[6].xxxx
 40:   MAD TEMP[2], CONST[ADDR[0].x], IN[3].yyyy, TEMP[2]
 41:   UARL ADDR[0].x, TEMP[5].xxxx
 42:   MAD TEMP[2], CONST[ADDR[0].x], IN[3].zzzz, TEMP[2]
 43:   UARL ADDR[0].x, TEMP[4].xxxx
 44:   MAD TEMP[1], CONST[ADDR[0].x], TEMP[1].xxxx, TEMP[2]
 45:   DP4 TEMP[1].x, IN[0], TEMP[1]
 46:   MOV TEMP[3].z, TEMP[1].xxxx
 47:   MOV TEMP[0].xyz, TEMP[3].xyzx
 48: ENDIF
 49: DP4 TEMP[1].x, TEMP[0], CONST[0]
 50: DP4 TEMP[2].x, TEMP[0], CONST[1]
 51: MOV TEMP[1].y, TEMP[2].xxxx
 52: DP4 TEMP[2].x, TEMP[0], CONST[2]
 53: MOV TEMP[1].z, TEMP[2].xxxx
 54: DP4 TEMP[2].x, TEMP[0], CONST[3]
 55: MOV TEMP[1].w, TEMP[2].xxxx
 56: DP4 TEMP[0].x, TEMP[0], CONST[9]
 57: MOV TEMP[0].z, TEMP[0].xxxx
 58: DP4 TEMP[2].x, IN[1], CONST[7]
 59: DP4 TEMP[3].x, IN[1], CONST[8]
 60: MOV TEMP[2].y, TEMP[3].xxxx
 61: MOV TEMP[0].xy, TEMP[2].xyxx
 62: MOV TEMP[0].w, IMM[0].xxxx
 63: MOV OUT[0], TEMP[1]
 64: MOV OUT[2], TEMP[0]
 65: MOV OUT[1], TEMP[1]
 66: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0)
  %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4)
  %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8)
  %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12)
  %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16)
  %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20)
  %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24)
  %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28)
  %20 = call float @llvm.SI.load.const(<16 x i8> %11, i32 32)
  %21 = call float @llvm.SI.load.const(<16 x i8> %11, i32 36)
  %22 = call float @llvm.SI.load.const(<16 x i8> %11, i32 40)
  %23 = call float @llvm.SI.load.const(<16 x i8> %11, i32 44)
  %24 = call float @llvm.SI.load.const(<16 x i8> %11, i32 48)
  %25 = call float @llvm.SI.load.const(<16 x i8> %11, i32 52)
  %26 = call float @llvm.SI.load.const(<16 x i8> %11, i32 56)
  %27 = call float @llvm.SI.load.const(<16 x i8> %11, i32 60)
  %28 = call float @llvm.SI.load.const(<16 x i8> %11, i32 112)
  %29 = call float @llvm.SI.load.const(<16 x i8> %11, i32 116)
  %30 = call float @llvm.SI.load.const(<16 x i8> %11, i32 120)
  %31 = call float @llvm.SI.load.const(<16 x i8> %11, i32 124)
  %32 = call float @llvm.SI.load.const(<16 x i8> %11, i32 128)
  %33 = call float @llvm.SI.load.const(<16 x i8> %11, i32 132)
  %34 = call float @llvm.SI.load.const(<16 x i8> %11, i32 136)
  %35 = call float @llvm.SI.load.const(<16 x i8> %11, i32 140)
  %36 = call float @llvm.SI.load.const(<16 x i8> %11, i32 144)
  %37 = call float @llvm.SI.load.const(<16 x i8> %11, i32 148)
  %38 = call float @llvm.SI.load.const(<16 x i8> %11, i32 152)
  %39 = call float @llvm.SI.load.const(<16 x i8> %11, i32 156)
  %40 = call float @llvm.SI.load.const(<16 x i8> %11, i32 3840)
  %41 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0
  %42 = load <16 x i8> addrspace(2)* %41, !tbaa !0
  %43 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %42, i32 0, i32 %6)
  %44 = extractelement <4 x float> %43, i32 0
  %45 = extractelement <4 x float> %43, i32 1
  %46 = extractelement <4 x float> %43, i32 2
  %47 = extractelement <4 x float> %43, i32 3
  %48 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 1
  %49 = load <16 x i8> addrspace(2)* %48, !tbaa !0
  %50 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %49, i32 0, i32 %6)
  %51 = extractelement <4 x float> %50, i32 0
  %52 = extractelement <4 x float> %50, i32 1
  %53 = extractelement <4 x float> %50, i32 2
  %54 = extractelement <4 x float> %50, i32 3
  %55 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 2
  %56 = load <16 x i8> addrspace(2)* %55, !tbaa !0
  %57 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %56, i32 0, i32 %6)
  %58 = extractelement <4 x float> %57, i32 0
  %59 = extractelement <4 x float> %57, i32 1
  %60 = extractelement <4 x float> %57, i32 2
  %61 = extractelement <4 x float> %57, i32 3
  %62 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 3
  %63 = load <16 x i8> addrspace(2)* %62, !tbaa !0
  %64 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %63, i32 0, i32 %6)
  %65 = extractelement <4 x float> %64, i32 0
  %66 = extractelement <4 x float> %64, i32 1
  %67 = extractelement <4 x float> %64, i32 2
  %68 = bitcast float %40 to i32
  %69 = icmp ne i32 %68, 0
  br i1 %69, label %IF, label %ENDIF

IF:                                               ; preds = %main_body
  %70 = fmul float %65, 1.000000e+00
  %71 = fmul float %66, 1.000000e+00
  %72 = fadd float %71, %70
  %73 = fmul float %67, 1.000000e+00
  %74 = fadd float %72, %73
  %75 = fsub float -0.000000e+00, %74
  %76 = fadd float 1.000000e+00, %75
  %77 = fmul float %58, 0x406FE051E0000000
  %78 = fmul float %59, 0x406FE051E0000000
  %79 = fmul float %60, 0x406FE051E0000000
  %80 = fmul float %61, 0x406FE051E0000000
  %81 = fptosi float %77 to i32
  %82 = fptosi float %78 to i32
  %83 = fptosi float %79 to i32
  %84 = fptosi float %80 to i32
  %85 = bitcast i32 %81 to float
  %86 = bitcast i32 %82 to float
  %87 = bitcast i32 %83 to float
  %88 = bitcast i32 %84 to float
  %89 = bitcast float %88 to i32
  %90 = mul i32 %89, 3
  %91 = add i32 %90, 41
  %92 = bitcast i32 %91 to float
  %93 = bitcast float %87 to i32
  %94 = mul i32 %93, 3
  %95 = add i32 %94, 41
  %96 = bitcast i32 %95 to float
  %97 = bitcast float %86 to i32
  %98 = mul i32 %97, 3
  %99 = add i32 %98, 41
  %100 = bitcast i32 %99 to float
  %101 = bitcast float %85 to i32
  %102 = mul i32 %101, 3
  %103 = add i32 %102, 41
  %104 = bitcast i32 %103 to float
  %105 = bitcast float %104 to i32
  %106 = shl i32 %105, 4
  %107 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %106)
  %108 = fmul float %107, %65
  %109 = shl i32 %105, 4
  %110 = add i32 %109, 4
  %111 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %110)
  %112 = fmul float %111, %65
  %113 = shl i32 %105, 4
  %114 = add i32 %113, 8
  %115 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %114)
  %116 = fmul float %115, %65
  %117 = shl i32 %105, 4
  %118 = add i32 %117, 12
  %119 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %118)
  %120 = fmul float %119, %65
  %121 = bitcast float %100 to i32
  %122 = shl i32 %121, 4
  %123 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %122)
  %124 = fmul float %123, %66
  %125 = fadd float %124, %108
  %126 = shl i32 %121, 4
  %127 = add i32 %126, 4
  %128 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %127)
  %129 = fmul float %128, %66
  %130 = fadd float %129, %112
  %131 = shl i32 %121, 4
  %132 = add i32 %131, 8
  %133 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %132)
  %134 = fmul float %133, %66
  %135 = fadd float %134, %116
  %136 = shl i32 %121, 4
  %137 = add i32 %136, 12
  %138 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %137)
  %139 = fmul float %138, %66
  %140 = fadd float %139, %120
  %141 = bitcast float %96 to i32
  %142 = shl i32 %141, 4
  %143 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %142)
  %144 = fmul float %143, %67
  %145 = fadd float %144, %125
  %146 = shl i32 %141, 4
  %147 = add i32 %146, 4
  %148 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %147)
  %149 = fmul float %148, %67
  %150 = fadd float %149, %130
  %151 = shl i32 %141, 4
  %152 = add i32 %151, 8
  %153 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %152)
  %154 = fmul float %153, %67
  %155 = fadd float %154, %135
  %156 = shl i32 %141, 4
  %157 = add i32 %156, 12
  %158 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %157)
  %159 = fmul float %158, %67
  %160 = fadd float %159, %140
  %161 = bitcast float %92 to i32
  %162 = shl i32 %161, 4
  %163 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %162)
  %164 = fmul float %163, %76
  %165 = fadd float %164, %145
  %166 = shl i32 %161, 4
  %167 = add i32 %166, 4
  %168 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %167)
  %169 = fmul float %168, %76
  %170 = fadd float %169, %150
  %171 = shl i32 %161, 4
  %172 = add i32 %171, 8
  %173 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %172)
  %174 = fmul float %173, %76
  %175 = fadd float %174, %155
  %176 = shl i32 %161, 4
  %177 = add i32 %176, 12
  %178 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %177)
  %179 = fmul float %178, %76
  %180 = fadd float %179, %160
  %181 = fmul float %44, %165
  %182 = fmul float %45, %170
  %183 = fadd float %181, %182
  %184 = fmul float %46, %175
  %185 = fadd float %183, %184
  %186 = fmul float %47, %180
  %187 = fadd float %185, %186
  %188 = bitcast float %88 to i32
  %189 = mul i32 %188, 3
  %190 = add i32 %189, 42
  %191 = bitcast i32 %190 to float
  %192 = bitcast float %87 to i32
  %193 = mul i32 %192, 3
  %194 = add i32 %193, 42
  %195 = bitcast i32 %194 to float
  %196 = bitcast float %86 to i32
  %197 = mul i32 %196, 3
  %198 = add i32 %197, 42
  %199 = bitcast i32 %198 to float
  %200 = bitcast float %85 to i32
  %201 = mul i32 %200, 3
  %202 = add i32 %201, 42
  %203 = bitcast i32 %202 to float
  %204 = bitcast float %203 to i32
  %205 = shl i32 %204, 4
  %206 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %205)
  %207 = fmul float %206, %65
  %208 = shl i32 %204, 4
  %209 = add i32 %208, 4
  %210 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %209)
  %211 = fmul float %210, %65
  %212 = shl i32 %204, 4
  %213 = add i32 %212, 8
  %214 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %213)
  %215 = fmul float %214, %65
  %216 = shl i32 %204, 4
  %217 = add i32 %216, 12
  %218 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %217)
  %219 = fmul float %218, %65
  %220 = bitcast float %199 to i32
  %221 = shl i32 %220, 4
  %222 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %221)
  %223 = fmul float %222, %66
  %224 = fadd float %223, %207
  %225 = shl i32 %220, 4
  %226 = add i32 %225, 4
  %227 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %226)
  %228 = fmul float %227, %66
  %229 = fadd float %228, %211
  %230 = shl i32 %220, 4
  %231 = add i32 %230, 8
  %232 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %231)
  %233 = fmul float %232, %66
  %234 = fadd float %233, %215
  %235 = shl i32 %220, 4
  %236 = add i32 %235, 12
  %237 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %236)
  %238 = fmul float %237, %66
  %239 = fadd float %238, %219
  %240 = bitcast float %195 to i32
  %241 = shl i32 %240, 4
  %242 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %241)
  %243 = fmul float %242, %67
  %244 = fadd float %243, %224
  %245 = shl i32 %240, 4
  %246 = add i32 %245, 4
  %247 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %246)
  %248 = fmul float %247, %67
  %249 = fadd float %248, %229
  %250 = shl i32 %240, 4
  %251 = add i32 %250, 8
  %252 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %251)
  %253 = fmul float %252, %67
  %254 = fadd float %253, %234
  %255 = shl i32 %240, 4
  %256 = add i32 %255, 12
  %257 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %256)
  %258 = fmul float %257, %67
  %259 = fadd float %258, %239
  %260 = bitcast float %191 to i32
  %261 = shl i32 %260, 4
  %262 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %261)
  %263 = fmul float %262, %76
  %264 = fadd float %263, %244
  %265 = shl i32 %260, 4
  %266 = add i32 %265, 4
  %267 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %266)
  %268 = fmul float %267, %76
  %269 = fadd float %268, %249
  %270 = shl i32 %260, 4
  %271 = add i32 %270, 8
  %272 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %271)
  %273 = fmul float %272, %76
  %274 = fadd float %273, %254
  %275 = shl i32 %260, 4
  %276 = add i32 %275, 12
  %277 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %276)
  %278 = fmul float %277, %76
  %279 = fadd float %278, %259
  %280 = fmul float %44, %264
  %281 = fmul float %45, %269
  %282 = fadd float %280, %281
  %283 = fmul float %46, %274
  %284 = fadd float %282, %283
  %285 = fmul float %47, %279
  %286 = fadd float %284, %285
  %287 = bitcast float %88 to i32
  %288 = mul i32 %287, 3
  %289 = add i32 %288, 43
  %290 = bitcast i32 %289 to float
  %291 = bitcast float %87 to i32
  %292 = mul i32 %291, 3
  %293 = add i32 %292, 43
  %294 = bitcast i32 %293 to float
  %295 = bitcast float %86 to i32
  %296 = mul i32 %295, 3
  %297 = add i32 %296, 43
  %298 = bitcast i32 %297 to float
  %299 = bitcast float %85 to i32
  %300 = mul i32 %299, 3
  %301 = add i32 %300, 43
  %302 = bitcast i32 %301 to float
  %303 = bitcast float %302 to i32
  %304 = shl i32 %303, 4
  %305 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %304)
  %306 = fmul float %305, %65
  %307 = shl i32 %303, 4
  %308 = add i32 %307, 4
  %309 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %308)
  %310 = fmul float %309, %65
  %311 = shl i32 %303, 4
  %312 = add i32 %311, 8
  %313 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %312)
  %314 = fmul float %313, %65
  %315 = shl i32 %303, 4
  %316 = add i32 %315, 12
  %317 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %316)
  %318 = fmul float %317, %65
  %319 = bitcast float %298 to i32
  %320 = shl i32 %319, 4
  %321 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %320)
  %322 = fmul float %321, %66
  %323 = fadd float %322, %306
  %324 = shl i32 %319, 4
  %325 = add i32 %324, 4
  %326 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %325)
  %327 = fmul float %326, %66
  %328 = fadd float %327, %310
  %329 = shl i32 %319, 4
  %330 = add i32 %329, 8
  %331 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %330)
  %332 = fmul float %331, %66
  %333 = fadd float %332, %314
  %334 = shl i32 %319, 4
  %335 = add i32 %334, 12
  %336 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %335)
  %337 = fmul float %336, %66
  %338 = fadd float %337, %318
  %339 = bitcast float %294 to i32
  %340 = shl i32 %339, 4
  %341 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %340)
  %342 = fmul float %341, %67
  %343 = fadd float %342, %323
  %344 = shl i32 %339, 4
  %345 = add i32 %344, 4
  %346 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %345)
  %347 = fmul float %346, %67
  %348 = fadd float %347, %328
  %349 = shl i32 %339, 4
  %350 = add i32 %349, 8
  %351 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %350)
  %352 = fmul float %351, %67
  %353 = fadd float %352, %333
  %354 = shl i32 %339, 4
  %355 = add i32 %354, 12
  %356 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %355)
  %357 = fmul float %356, %67
  %358 = fadd float %357, %338
  %359 = bitcast float %290 to i32
  %360 = shl i32 %359, 4
  %361 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %360)
  %362 = fmul float %361, %76
  %363 = fadd float %362, %343
  %364 = shl i32 %359, 4
  %365 = add i32 %364, 4
  %366 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %365)
  %367 = fmul float %366, %76
  %368 = fadd float %367, %348
  %369 = shl i32 %359, 4
  %370 = add i32 %369, 8
  %371 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %370)
  %372 = fmul float %371, %76
  %373 = fadd float %372, %353
  %374 = shl i32 %359, 4
  %375 = add i32 %374, 12
  %376 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %375)
  %377 = fmul float %376, %76
  %378 = fadd float %377, %358
  %379 = fmul float %44, %363
  %380 = fmul float %45, %368
  %381 = fadd float %379, %380
  %382 = fmul float %46, %373
  %383 = fadd float %381, %382
  %384 = fmul float %47, %378
  %385 = fadd float %383, %384
  br label %ENDIF

ENDIF:                                            ; preds = %main_body, %IF
  %temp.0 = phi float [ %187, %IF ], [ %44, %main_body ]
  %temp1.0 = phi float [ %286, %IF ], [ %45, %main_body ]
  %temp2.0 = phi float [ %385, %IF ], [ %46, %main_body ]
  %386 = fmul float %temp.0, %12
  %387 = fmul float %temp1.0, %13
  %388 = fadd float %386, %387
  %389 = fmul float %temp2.0, %14
  %390 = fadd float %388, %389
  %391 = fmul float %47, %15
  %392 = fadd float %390, %391
  %393 = fmul float %temp.0, %16
  %394 = fmul float %temp1.0, %17
  %395 = fadd float %393, %394
  %396 = fmul float %temp2.0, %18
  %397 = fadd float %395, %396
  %398 = fmul float %47, %19
  %399 = fadd float %397, %398
  %400 = fmul float %temp.0, %20
  %401 = fmul float %temp1.0, %21
  %402 = fadd float %400, %401
  %403 = fmul float %temp2.0, %22
  %404 = fadd float %402, %403
  %405 = fmul float %47, %23
  %406 = fadd float %404, %405
  %407 = fmul float %temp.0, %24
  %408 = fmul float %temp1.0, %25
  %409 = fadd float %407, %408
  %410 = fmul float %temp2.0, %26
  %411 = fadd float %409, %410
  %412 = fmul float %47, %27
  %413 = fadd float %411, %412
  %414 = fmul float %temp.0, %36
  %415 = fmul float %temp1.0, %37
  %416 = fadd float %414, %415
  %417 = fmul float %temp2.0, %38
  %418 = fadd float %416, %417
  %419 = fmul float %47, %39
  %420 = fadd float %418, %419
  %421 = fmul float %51, %28
  %422 = fmul float %52, %29
  %423 = fadd float %421, %422
  %424 = fmul float %53, %30
  %425 = fadd float %423, %424
  %426 = fmul float %54, %31
  %427 = fadd float %425, %426
  %428 = fmul float %51, %32
  %429 = fmul float %52, %33
  %430 = fadd float %428, %429
  %431 = fmul float %53, %34
  %432 = fadd float %430, %431
  %433 = fmul float %54, %35
  %434 = fadd float %432, %433
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %427, float %434, float %420, float 1.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %392, float %399, float %406, float %413)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg41, %SGPR6_SGPR7 in %vreg44, %VGPR0 in %vreg47

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%53](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%VGPR5_VGPR6_VGPR7_VGPR8<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 0; mem:LD16[%44](align=8)(tbaa=!"const")
	S_WAITCNT 112
	%VGPR1_VGPR2_VGPR3_VGPR4<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%11](align=8)(tbaa=!"const")
	%SGPR4<def> = S_MOV_B32 3840
	S_WAITCNT 112
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_SGPR %SGPR0_SGPR1_SGPR2_SGPR3, %SGPR4<kill>; mem:LD4[<unknown>]
	S_WAITCNT 127
	%SGPR4_SGPR5<def> = V_CMP_NE_I32_e64 %SGPR4<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 39; mem:LD4[<unknown>]
	%SGPR9<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 38; mem:LD4[<unknown>]
	%SGPR10<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 37; mem:LD4[<unknown>]
	%SGPR11<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 36; mem:LD4[<unknown>]
	%SGPR12<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 35; mem:LD4[<unknown>]
	%SGPR13<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 34; mem:LD4[<unknown>]
	%SGPR14<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 33; mem:LD4[<unknown>]
	%SGPR15<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 32; mem:LD4[<unknown>]
	%SGPR16<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 31; mem:LD4[<unknown>]
	%SGPR17<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 30; mem:LD4[<unknown>]
	%SGPR18<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 29; mem:LD4[<unknown>]
	%SGPR19<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 28; mem:LD4[<unknown>]
	%SGPR20<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 15; mem:LD4[<unknown>]
	%SGPR21<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 14; mem:LD4[<unknown>]
	%SGPR22<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 13; mem:LD4[<unknown>]
	%SGPR23<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 12; mem:LD4[<unknown>]
	%SGPR24<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 11; mem:LD4[<unknown>]
	%SGPR25<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 10; mem:LD4[<unknown>]
	%SGPR26<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 9; mem:LD4[<unknown>]
	%SGPR27<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 8; mem:LD4[<unknown>]
	%SGPR28<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 7; mem:LD4[<unknown>]
	%SGPR29<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 6; mem:LD4[<unknown>]
	%SGPR30<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 5; mem:LD4[<unknown>]
	%SGPR31<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 4; mem:LD4[<unknown>]
	%SGPR32<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 3; mem:LD4[<unknown>]
	%SGPR33<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2; mem:LD4[<unknown>]
	%SGPR34<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1; mem:LD4[<unknown>]
	%SGPR35<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 0; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR29<def> = V_MOV_B32_e32 %SGPR8<kill>, %EXEC<imp-use>
	%VGPR32<def> = V_MOV_B32_e32 %SGPR9<kill>, %EXEC<imp-use>
	%VGPR36<def> = V_MOV_B32_e32 %SGPR10<kill>, %EXEC<imp-use>
	%VGPR35<def> = V_MOV_B32_e32 %SGPR11<kill>, %EXEC<imp-use>
	%VGPR18<def> = V_MOV_B32_e32 %SGPR12<kill>, %EXEC<imp-use>
	%VGPR28<def> = V_MOV_B32_e32 %SGPR13<kill>, %EXEC<imp-use>
	%VGPR34<def> = V_MOV_B32_e32 %SGPR14<kill>, %EXEC<imp-use>
	%VGPR33<def> = V_MOV_B32_e32 %SGPR15<kill>, %EXEC<imp-use>
	%VGPR17<def> = V_MOV_B32_e32 %SGPR16<kill>, %EXEC<imp-use>
	%VGPR19<def> = V_MOV_B32_e32 %SGPR17<kill>, %EXEC<imp-use>
	%VGPR31<def> = V_MOV_B32_e32 %SGPR18<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_MOV_B32_e32 %SGPR19<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_MOV_B32_e32 %SGPR20<kill>, %EXEC<imp-use>
	%VGPR16<def> = V_MOV_B32_e32 %SGPR21<kill>, %EXEC<imp-use>
	%VGPR27<def> = V_MOV_B32_e32 %SGPR22<kill>, %EXEC<imp-use>
	%VGPR26<def> = V_MOV_B32_e32 %SGPR23<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_MOV_B32_e32 %SGPR24<kill>, %EXEC<imp-use>
	%VGPR15<def> = V_MOV_B32_e32 %SGPR25<kill>, %EXEC<imp-use>
	%VGPR25<def> = V_MOV_B32_e32 %SGPR26<kill>, %EXEC<imp-use>
	%VGPR24<def> = V_MOV_B32_e32 %SGPR27<kill>, %EXEC<imp-use>
	%VGPR10<def> = V_MOV_B32_e32 %SGPR28<kill>, %EXEC<imp-use>
	%VGPR14<def> = V_MOV_B32_e32 %SGPR29<kill>, %EXEC<imp-use>
	%VGPR23<def> = V_MOV_B32_e32 %SGPR30<kill>, %EXEC<imp-use>
	%VGPR22<def> = V_MOV_B32_e32 %SGPR31<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_MOV_B32_e32 %SGPR32<kill>, %EXEC<imp-use>
	%VGPR13<def> = V_MOV_B32_e32 %SGPR33<kill>, %EXEC<imp-use>
	%VGPR21<def> = V_MOV_B32_e32 %SGPR34<kill>, %EXEC<imp-use>
	%VGPR20<def> = V_MOV_B32_e32 %SGPR35<kill>, %EXEC<imp-use>
	%VGPR39<def> = V_MOV_B32_e32 %VGPR1, %EXEC<imp-use>
	%VGPR38<def> = V_MOV_B32_e32 %VGPR2, %EXEC<imp-use>
	%VGPR37<def> = V_MOV_B32_e32 %VGPR3, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = S_AND_SAVEEXEC_B64 %SGPR4_SGPR5, %EXEC<imp-def>, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = S_XOR_B64 %EXEC, %SGPR4_SGPR5
	S_CBRANCH_EXECZ <BB#2>, %EXEC
    Successors according to CFG: BB#1(16) BB#2(16)

BB#1: derived from LLVM BB %IF
    Live Ins: %SGPR0_SGPR1_SGPR2_SGPR3 %VGPR20 %VGPR21 %VGPR13 %VGPR9 %VGPR22 %VGPR23 %VGPR14 %VGPR10 %VGPR24 %VGPR25 %VGPR15 %VGPR11 %VGPR26 %VGPR27 %VGPR16 %VGPR12 %VGPR30 %VGPR31 %VGPR19 %VGPR17 %VGPR33 %VGPR34 %VGPR28 %VGPR18 %VGPR35 %VGPR36 %VGPR32 %VGPR29 %VGPR5_VGPR6_VGPR7_VGPR8 %SGPR6_SGPR7 %VGPR0 %VGPR1_VGPR2_VGPR3_VGPR4 %SGPR4_SGPR5
    Predecessors according to CFG: BB#0
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 8; mem:LD16[%63](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%VGPR37_VGPR38_VGPR39_VGPR40<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	%VGPR41<def> = V_MOV_B32_e32 2.550100e+02, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR42<def> = V_MUL_F32_e32 %VGPR37, %VGPR41, %EXEC<imp-use>
	%VGPR42<def> = V_CVT_I32_F32_e32 %VGPR42<kill>, %EXEC<imp-use>
	%VGPR42<def> = V_MUL_LO_I32 3, %VGPR42<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR43<def> = V_ADD_I32_e32 43, %VGPR42, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR43<def> = V_LSHLREV_B32_e32 4, %VGPR43<kill>, %EXEC<imp-use>
	%VGPR44<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR43, %EXEC<imp-use>; mem:LD4[<unknown>]
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 12; mem:LD16[%72](align=8)(tbaa=!"const")
	S_WAITCNT 112
	%VGPR45_VGPR46_VGPR47_VGPR48<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR0<def> = V_MUL_F32_e32 %VGPR44<kill>, %VGPR45, %EXEC<imp-use>
	%VGPR44<def> = V_MUL_F32_e32 %VGPR38, %VGPR41, %EXEC<imp-use>
	%VGPR44<def> = V_CVT_I32_F32_e32 %VGPR44<kill>, %EXEC<imp-use>
	%VGPR44<def> = V_MUL_LO_I32 3, %VGPR44<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR49<def> = V_ADD_I32_e32 43, %VGPR44, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR49<def> = V_LSHLREV_B32_e32 4, %VGPR49<kill>, %EXEC<imp-use>
	%VGPR50<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR49, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR0<def> = V_MAD_F32 %VGPR50<kill>, %VGPR46, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR50<def> = V_MUL_F32_e32 %VGPR39, %VGPR41, %EXEC<imp-use>
	%VGPR50<def> = V_CVT_I32_F32_e32 %VGPR50<kill>, %EXEC<imp-use>
	%VGPR50<def> = V_MUL_LO_I32 3, %VGPR50<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR51<def> = V_ADD_I32_e32 43, %VGPR50, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR51<def> = V_LSHLREV_B32_e32 4, %VGPR51<kill>, %EXEC<imp-use>
	%VGPR52<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR51, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR0<def> = V_MAD_F32 %VGPR52<kill>, %VGPR47, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR52<def> = V_ADD_F32_e32 %VGPR46, %VGPR45, %EXEC<imp-use>
	%VGPR52<def> = V_ADD_F32_e32 %VGPR52<kill>, %VGPR47, %EXEC<imp-use>
	%VGPR52<def> = V_SUB_F32_e32 1.000000e+00, %VGPR52<kill>, %EXEC<imp-use>
	%VGPR37<def> = V_MUL_F32_e32 %VGPR40, %VGPR41<kill>, %EXEC<imp-use>, %VGPR37_VGPR38_VGPR39_VGPR40<imp-use,kill>
	%VGPR37<def> = V_CVT_I32_F32_e32 %VGPR37<kill>, %EXEC<imp-use>
	%VGPR39<def> = V_MUL_LO_I32 3, %VGPR37<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR37<def> = V_ADD_I32_e32 43, %VGPR39, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR37<def> = V_LSHLREV_B32_e32 4, %VGPR37<kill>, %EXEC<imp-use>
	%VGPR38<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR37, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR0<def> = V_MAD_F32 %VGPR38<kill>, %VGPR52, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR38<def> = V_OR_B32_e64 4, %VGPR43, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR38<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR38<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR38<def> = V_MUL_F32_e32 %VGPR38<kill>, %VGPR45, %EXEC<imp-use>
	%VGPR40<def> = V_OR_B32_e64 4, %VGPR49, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR40<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR40<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR38<def> = V_MAD_F32 %VGPR40<kill>, %VGPR46, %VGPR38<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR40<def> = V_OR_B32_e64 4, %VGPR51, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR40<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR40<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR38<def> = V_MAD_F32 %VGPR40<kill>, %VGPR47, %VGPR38<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR40<def> = V_OR_B32_e64 4, %VGPR37, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR40<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR40<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR38<def> = V_MAD_F32 %VGPR40<kill>, %VGPR52, %VGPR38<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR38<def> = V_MUL_F32_e32 %VGPR2, %VGPR38<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR1, %VGPR0<kill>, %VGPR38<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR38<def> = V_OR_B32_e64 8, %VGPR43, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR38<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR38<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR38<def> = V_MUL_F32_e32 %VGPR38<kill>, %VGPR45, %EXEC<imp-use>
	%VGPR40<def> = V_OR_B32_e64 8, %VGPR49, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR40<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR40<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR38<def> = V_MAD_F32 %VGPR40<kill>, %VGPR46, %VGPR38<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR40<def> = V_OR_B32_e64 8, %VGPR51, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR40<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR40<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR38<def> = V_MAD_F32 %VGPR40<kill>, %VGPR47, %VGPR38<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR40<def> = V_OR_B32_e64 8, %VGPR37, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR40<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR40<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR38<def> = V_MAD_F32 %VGPR40<kill>, %VGPR52, %VGPR38<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR3, %VGPR38<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR38<def> = V_OR_B32_e64 12, %VGPR43<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR38<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR38<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR38<def> = V_MUL_F32_e32 %VGPR38<kill>, %VGPR45, %EXEC<imp-use>
	%VGPR40<def> = V_OR_B32_e64 12, %VGPR49<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR40<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR40<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR38<def> = V_MAD_F32 %VGPR40<kill>, %VGPR46, %VGPR38<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR40<def> = V_OR_B32_e64 12, %VGPR51<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR40<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR40<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR38<def> = V_MAD_F32 %VGPR40<kill>, %VGPR47, %VGPR38<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR37<def> = V_OR_B32_e64 12, %VGPR37<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR37<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR37<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR37<def> = V_MAD_F32 %VGPR37<kill>, %VGPR52, %VGPR38<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR37<def> = V_MAD_F32 %VGPR4, %VGPR37<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_I32_e32 42, %VGPR42, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR0<def> = V_LSHLREV_B32_e32 4, %VGPR0<kill>, %EXEC<imp-use>
	%VGPR38<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR0, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR38<def> = V_MUL_F32_e32 %VGPR38<kill>, %VGPR45, %EXEC<imp-use>
	%VGPR40<def> = V_ADD_I32_e32 42, %VGPR44, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR40<def> = V_LSHLREV_B32_e32 4, %VGPR40<kill>, %EXEC<imp-use>
	%VGPR41<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR40, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR38<def> = V_MAD_F32 %VGPR41<kill>, %VGPR46, %VGPR38<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR41<def> = V_ADD_I32_e32 42, %VGPR50, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR41<def> = V_LSHLREV_B32_e32 4, %VGPR41<kill>, %EXEC<imp-use>
	%VGPR43<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR41, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR38<def> = V_MAD_F32 %VGPR43<kill>, %VGPR47, %VGPR38<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR43<def> = V_ADD_I32_e32 42, %VGPR39, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR43<def> = V_LSHLREV_B32_e32 4, %VGPR43<kill>, %EXEC<imp-use>
	%VGPR49<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR43, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR38<def> = V_MAD_F32 %VGPR49<kill>, %VGPR52, %VGPR38<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR49<def> = V_OR_B32_e64 4, %VGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR49<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR49<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR49<def> = V_MUL_F32_e32 %VGPR49<kill>, %VGPR45, %EXEC<imp-use>
	%VGPR51<def> = V_OR_B32_e64 4, %VGPR40, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR51<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR51<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR49<def> = V_MAD_F32 %VGPR51<kill>, %VGPR46, %VGPR49<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR51<def> = V_OR_B32_e64 4, %VGPR41, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR51<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR51<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR49<def> = V_MAD_F32 %VGPR51<kill>, %VGPR47, %VGPR49<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR51<def> = V_OR_B32_e64 4, %VGPR43, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR51<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR51<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR49<def> = V_MAD_F32 %VGPR51<kill>, %VGPR52, %VGPR49<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR49<def> = V_MUL_F32_e32 %VGPR2, %VGPR49<kill>, %EXEC<imp-use>
	%VGPR38<def> = V_MAD_F32 %VGPR1, %VGPR38<kill>, %VGPR49<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR49<def> = V_OR_B32_e64 8, %VGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR49<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR49<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR49<def> = V_MUL_F32_e32 %VGPR49<kill>, %VGPR45, %EXEC<imp-use>
	%VGPR51<def> = V_OR_B32_e64 8, %VGPR40, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR51<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR51<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR49<def> = V_MAD_F32 %VGPR51<kill>, %VGPR46, %VGPR49<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR51<def> = V_OR_B32_e64 8, %VGPR41, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR51<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR51<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR49<def> = V_MAD_F32 %VGPR51<kill>, %VGPR47, %VGPR49<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR51<def> = V_OR_B32_e64 8, %VGPR43, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR51<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR51<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR49<def> = V_MAD_F32 %VGPR51<kill>, %VGPR52, %VGPR49<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR38<def> = V_MAD_F32 %VGPR3, %VGPR49<kill>, %VGPR38<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_OR_B32_e64 12, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR0<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR0<def> = V_MUL_F32_e32 %VGPR0<kill>, %VGPR45, %EXEC<imp-use>
	%VGPR40<def> = V_OR_B32_e64 12, %VGPR40<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR40<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR40<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR0<def> = V_MAD_F32 %VGPR40<kill>, %VGPR46, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR40<def> = V_OR_B32_e64 12, %VGPR41<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR40<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR40<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR0<def> = V_MAD_F32 %VGPR40<kill>, %VGPR47, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR40<def> = V_OR_B32_e64 12, %VGPR43<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR40<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR40<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR0<def> = V_MAD_F32 %VGPR40<kill>, %VGPR52, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR38<def> = V_MAD_F32 %VGPR4, %VGPR0<kill>, %VGPR38<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_I32_e32 41, %VGPR42<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR0<def> = V_LSHLREV_B32_e32 4, %VGPR0<kill>, %EXEC<imp-use>
	%VGPR40<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR0, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR40<def> = V_MUL_F32_e32 %VGPR40<kill>, %VGPR45, %EXEC<imp-use>
	%VGPR41<def> = V_ADD_I32_e32 41, %VGPR44<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR41<def> = V_LSHLREV_B32_e32 4, %VGPR41<kill>, %EXEC<imp-use>
	%VGPR42<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR41, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR40<def> = V_MAD_F32 %VGPR42<kill>, %VGPR46, %VGPR40<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR42<def> = V_ADD_I32_e32 41, %VGPR50<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR42<def> = V_LSHLREV_B32_e32 4, %VGPR42<kill>, %EXEC<imp-use>
	%VGPR43<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR42, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR40<def> = V_MAD_F32 %VGPR43<kill>, %VGPR47, %VGPR40<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR39<def> = V_ADD_I32_e32 41, %VGPR39<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR39<def> = V_LSHLREV_B32_e32 4, %VGPR39<kill>, %EXEC<imp-use>
	%VGPR43<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR39, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR40<def> = V_MAD_F32 %VGPR43<kill>, %VGPR52, %VGPR40<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR43<def> = V_OR_B32_e64 4, %VGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR43<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR43<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR43<def> = V_MUL_F32_e32 %VGPR43<kill>, %VGPR45, %EXEC<imp-use>
	%VGPR44<def> = V_OR_B32_e64 4, %VGPR41, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR44<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR44<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR43<def> = V_MAD_F32 %VGPR44<kill>, %VGPR46, %VGPR43<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR44<def> = V_OR_B32_e64 4, %VGPR42, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR44<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR44<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR43<def> = V_MAD_F32 %VGPR44<kill>, %VGPR47, %VGPR43<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR44<def> = V_OR_B32_e64 4, %VGPR39, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR44<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR44<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR43<def> = V_MAD_F32 %VGPR44<kill>, %VGPR52, %VGPR43<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR43<def> = V_MUL_F32_e32 %VGPR2, %VGPR43<kill>, %EXEC<imp-use>
	%VGPR40<def> = V_MAD_F32 %VGPR1, %VGPR40<kill>, %VGPR43<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR43<def> = V_OR_B32_e64 8, %VGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR43<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR43<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR43<def> = V_MUL_F32_e32 %VGPR43<kill>, %VGPR45, %EXEC<imp-use>
	%VGPR44<def> = V_OR_B32_e64 8, %VGPR41, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR44<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR44<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR43<def> = V_MAD_F32 %VGPR44<kill>, %VGPR46, %VGPR43<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR44<def> = V_OR_B32_e64 8, %VGPR42, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR44<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR44<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR43<def> = V_MAD_F32 %VGPR44<kill>, %VGPR47, %VGPR43<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR44<def> = V_OR_B32_e64 8, %VGPR39, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR44<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR44<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR43<def> = V_MAD_F32 %VGPR44<kill>, %VGPR52, %VGPR43<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR40<def> = V_MAD_F32 %VGPR3, %VGPR43<kill>, %VGPR40<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_OR_B32_e64 12, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR0<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR0<def> = V_MUL_F32_e32 %VGPR0<kill>, %VGPR45, %EXEC<imp-use>
	%VGPR41<def> = V_OR_B32_e64 12, %VGPR41<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR41<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR41<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR0<def> = V_MAD_F32 %VGPR41<kill>, %VGPR46, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR41<def> = V_OR_B32_e64 12, %VGPR42<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR41<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR41<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR0<def> = V_MAD_F32 %VGPR41<kill>, %VGPR47, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR45_VGPR46_VGPR47_VGPR48<imp-use,kill>
	%VGPR39<def> = V_OR_B32_e64 12, %VGPR39<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR39<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR39<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR0<def> = V_MAD_F32 %VGPR39<kill>, %VGPR52<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR39<def> = V_MAD_F32 %VGPR4, %VGPR0<kill>, %VGPR40<kill>, 0, 0, 0, 0, %EXEC<imp-use>
    Successors according to CFG: BB#2

BB#2: derived from LLVM BB %ENDIF
    Live Ins: %VGPR20 %VGPR21 %VGPR13 %VGPR9 %VGPR22 %VGPR23 %VGPR14 %VGPR10 %VGPR24 %VGPR25 %VGPR15 %VGPR11 %VGPR26 %VGPR27 %VGPR16 %VGPR12 %VGPR30 %VGPR31 %VGPR19 %VGPR17 %VGPR33 %VGPR34 %VGPR28 %VGPR18 %VGPR35 %VGPR36 %VGPR32 %VGPR29 %VGPR5_VGPR6_VGPR7_VGPR8 %VGPR1_VGPR2_VGPR3_VGPR4 %SGPR4_SGPR5 %VGPR39 %VGPR38 %VGPR37
    Predecessors according to CFG: BB#0 BB#1
	%EXEC<def> = S_OR_B64 %EXEC, %SGPR4_SGPR5
	%VGPR0<def> = V_MUL_F32_e64 %VGPR38, %VGPR36<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR39, %VGPR35<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR37, %VGPR32<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR4, %VGPR29<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR29<def> = V_MUL_F32_e64 %VGPR6, %VGPR34<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR29<def> = V_MAD_F32 %VGPR5, %VGPR33<kill>, %VGPR29<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR28<def> = V_MAD_F32 %VGPR7, %VGPR28<kill>, %VGPR29<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR18<def> = V_MAD_F32 %VGPR8, %VGPR18<kill>, %VGPR28<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR28<def> = V_MUL_F32_e64 %VGPR6, %VGPR31<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR28<def> = V_MAD_F32 %VGPR5, %VGPR30<kill>, %VGPR28<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR19<def> = V_MAD_F32 %VGPR7, %VGPR19<kill>, %VGPR28<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR8, %VGPR17<kill>, %VGPR19<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-use,kill>
	%VGPR6<def> = V_MOV_B32_e32 1.000000e+00, %EXEC<imp-use>
	EXP 15, 32, 0, 0, 0, %VGPR5<kill>, %VGPR18<kill>, %VGPR0<kill>, %VGPR6<kill>, %EXEC<imp-use>
	S_WAITCNT 1807
	%VGPR0<def> = V_MUL_F32_e64 %VGPR38, %VGPR27<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR39, %VGPR26<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR37, %VGPR16<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR4, %VGPR12<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_MUL_F32_e64 %VGPR38, %VGPR25<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR39, %VGPR24<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR37, %VGPR15<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR4, %VGPR11<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e64 %VGPR38, %VGPR23<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR39, %VGPR22<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR37, %VGPR14<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR4, %VGPR10<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_MUL_F32_e64 %VGPR38<kill>, %VGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR39<kill>, %VGPR20<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR37<kill>, %VGPR13<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_MAD_F32 %VGPR4, %VGPR9<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR1_VGPR2_VGPR3_VGPR4<imp-use,kill>
	EXP 15, 12, 0, 1, 0, %VGPR1<kill>, %VGPR6<kill>, %VGPR5<kill>, %VGPR0<kill>, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_LOAD_DWORDX4 s[8:11], s[6:7], 4                 ; C0840704
	S_WAITCNT lgkmcnt(0)                              ; BF8C007F
	BUFFER_LOAD_FORMAT_XYZW v[5:8], s[8:11][v0] + 0   ; E00C2000 80020500
	S_LOAD_DWORDX4 s[8:11], s[6:7], 0                 ; C0840700
	S_WAITCNT vmcnt(0) lgkmcnt(0)                     ; BF8C0070
	BUFFER_LOAD_FORMAT_XYZW v[1:4], s[8:11][v0] + 0   ; E00C2000 80020100
	S_LOAD_DWORDX4 s[0:3], s[0:1], 0                  ; C0800100
	S_MOV_B32 s4, 3840                                ; BE8403FF 00000F00
	S_WAITCNT vmcnt(0) lgkmcnt(0)                     ; BF8C0070
	S_BUFFER_LOAD_DWORD s4, s[0:3], s4                ; C2020004
	S_WAITCNT lgkmcnt(0)                              ; BF8C007F
	V_CMP_NE_I32_e64 s[4:5], s4, 0, 0, 0, 0, 0        ; D10A0004 02010004
	S_BUFFER_LOAD_DWORD s8, s[0:3], 39                ; C2040127
	S_BUFFER_LOAD_DWORD s9, s[0:3], 38                ; C2048126
	S_BUFFER_LOAD_DWORD s10, s[0:3], 37               ; C2050125
	S_BUFFER_LOAD_DWORD s11, s[0:3], 36               ; C2058124
	S_BUFFER_LOAD_DWORD s12, s[0:3], 35               ; C2060123
	S_BUFFER_LOAD_DWORD s13, s[0:3], 34               ; C2068122
	S_BUFFER_LOAD_DWORD s14, s[0:3], 33               ; C2070121
	S_BUFFER_LOAD_DWORD s15, s[0:3], 32               ; C2078120
	S_BUFFER_LOAD_DWORD s16, s[0:3], 31               ; C208011F
	S_BUFFER_LOAD_DWORD s17, s[0:3], 30               ; C208811E
	S_BUFFER_LOAD_DWORD s18, s[0:3], 29               ; C209011D
	S_BUFFER_LOAD_DWORD s19, s[0:3], 28               ; C209811C
	S_BUFFER_LOAD_DWORD s20, s[0:3], 15               ; C20A010F
	S_BUFFER_LOAD_DWORD s21, s[0:3], 14               ; C20A810E
	S_BUFFER_LOAD_DWORD s22, s[0:3], 13               ; C20B010D
	S_BUFFER_LOAD_DWORD s23, s[0:3], 12               ; C20B810C
	S_BUFFER_LOAD_DWORD s24, s[0:3], 11               ; C20C010B
	S_BUFFER_LOAD_DWORD s25, s[0:3], 10               ; C20C810A
	S_BUFFER_LOAD_DWORD s26, s[0:3], 9                ; C20D0109
	S_BUFFER_LOAD_DWORD s27, s[0:3], 8                ; C20D8108
	S_BUFFER_LOAD_DWORD s28, s[0:3], 7                ; C20E0107
	S_BUFFER_LOAD_DWORD s29, s[0:3], 6                ; C20E8106
	S_BUFFER_LOAD_DWORD s30, s[0:3], 5                ; C20F0105
	S_BUFFER_LOAD_DWORD s31, s[0:3], 4                ; C20F8104
	S_BUFFER_LOAD_DWORD s32, s[0:3], 3                ; C2100103
	S_BUFFER_LOAD_DWORD s33, s[0:3], 2                ; C2108102
	S_BUFFER_LOAD_DWORD s34, s[0:3], 1                ; C2110101
	S_BUFFER_LOAD_DWORD s35, s[0:3], 0                ; C2118100
	S_WAITCNT lgkmcnt(0)                              ; BF8C007F
	V_MOV_B32_e32 v29, s8                             ; 7E3A0208
	V_MOV_B32_e32 v32, s9                             ; 7E400209
	V_MOV_B32_e32 v36, s10                            ; 7E48020A
	V_MOV_B32_e32 v35, s11                            ; 7E46020B
	V_MOV_B32_e32 v18, s12                            ; 7E24020C
	V_MOV_B32_e32 v28, s13                            ; 7E38020D
	V_MOV_B32_e32 v34, s14                            ; 7E44020E
	V_MOV_B32_e32 v33, s15                            ; 7E42020F
	V_MOV_B32_e32 v17, s16                            ; 7E220210
	V_MOV_B32_e32 v19, s17                            ; 7E260211
	V_MOV_B32_e32 v31, s18                            ; 7E3E0212
	V_MOV_B32_e32 v30, s19                            ; 7E3C0213
	V_MOV_B32_e32 v12, s20                            ; 7E180214
	V_MOV_B32_e32 v16, s21                            ; 7E200215
	V_MOV_B32_e32 v27, s22                            ; 7E360216
	V_MOV_B32_e32 v26, s23                            ; 7E340217
	V_MOV_B32_e32 v11, s24                            ; 7E160218
	V_MOV_B32_e32 v15, s25                            ; 7E1E0219
	V_MOV_B32_e32 v25, s26                            ; 7E32021A
	V_MOV_B32_e32 v24, s27                            ; 7E30021B
	V_MOV_B32_e32 v10, s28                            ; 7E14021C
	V_MOV_B32_e32 v14, s29                            ; 7E1C021D
	V_MOV_B32_e32 v23, s30                            ; 7E2E021E
	V_MOV_B32_e32 v22, s31                            ; 7E2C021F
	V_MOV_B32_e32 v9, s32                             ; 7E120220
	V_MOV_B32_e32 v13, s33                            ; 7E1A0221
	V_MOV_B32_e32 v21, s34                            ; 7E2A0222
	V_MOV_B32_e32 v20, s35                            ; 7E280223
	V_MOV_B32_e32 v39, v1                             ; 7E4E0301
	V_MOV_B32_e32 v38, v2                             ; 7E4C0302
	V_MOV_B32_e32 v37, v3                             ; 7E4A0303
	S_AND_SAVEEXEC_B64 s[4:5], s[4:5]                 ; BE842404
	S_XOR_B64 s[4:5], exec, s[4:5]                    ; 8984047E
	S_CBRANCH_EXECZ ";.BB0_2"                         ; BF880000
	S_LOAD_DWORDX4 s[8:11], s[6:7], 8                 ; C0840708
	S_WAITCNT lgkmcnt(0)                              ; BF8C007F
	BUFFER_LOAD_FORMAT_XYZW v[37:40], s[8:11][v0] + 0 ; E00C2000 80022500
	V_MOV_B32_e32 v41, 2.550100e+02                   ; 7E5202FF 437F028F
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MUL_F32_e32 v42, v37, v41                       ; 10545325
	V_CVT_I32_F32_e32 v42, v42                        ; 7E54112A
	V_MUL_LO_I32 v42, 3, v42, 0, 0, 0, 0, 0           ; D2D6002A 02025483
	V_ADD_I32_e32 v43, 43, v42                        ; 4A5654AB
	V_LSHLREV_B32_e32 v43, 4, v43                     ; 34565684
	BUFFER_LOAD_DWORD v44, s[0:3] + v43               ; E0301000 80002C2B
	S_LOAD_DWORDX4 s[8:11], s[6:7], 12                ; C084070C
	S_WAITCNT vmcnt(0) lgkmcnt(0)                     ; BF8C0070
	BUFFER_LOAD_FORMAT_XYZW v[45:48], s[8:11][v0] + 0 ; E00C2000 80022D00
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MUL_F32_e32 v0, v44, v45                        ; 10005B2C
	V_MUL_F32_e32 v44, v38, v41                       ; 10585326
	V_CVT_I32_F32_e32 v44, v44                        ; 7E58112C
	V_MUL_LO_I32 v44, 3, v44, 0, 0, 0, 0, 0           ; D2D6002C 02025883
	V_ADD_I32_e32 v49, 43, v44                        ; 4A6258AB
	V_LSHLREV_B32_e32 v49, 4, v49                     ; 34626284
	BUFFER_LOAD_DWORD v50, s[0:3] + v49               ; E0301000 80003231
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MAD_F32 v0, v50, v46, v0, 0, 0, 0, 0            ; D2820000 04025D32
	V_MUL_F32_e32 v50, v39, v41                       ; 10645327
	V_CVT_I32_F32_e32 v50, v50                        ; 7E641132
	V_MUL_LO_I32 v50, 3, v50, 0, 0, 0, 0, 0           ; D2D60032 02026483
	V_ADD_I32_e32 v51, 43, v50                        ; 4A6664AB
	V_LSHLREV_B32_e32 v51, 4, v51                     ; 34666684
	BUFFER_LOAD_DWORD v52, s[0:3] + v51               ; E0301000 80003433
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MAD_F32 v0, v52, v47, v0, 0, 0, 0, 0            ; D2820000 04025F34
	V_ADD_F32_e32 v52, v46, v45                       ; 06685B2E
	V_ADD_F32_e32 v52, v52, v47                       ; 06685F34
	V_SUB_F32_e32 v52, 1.000000e+00, v52              ; 086868F2
	V_MUL_F32_e32 v37, v40, v41                       ; 104A5328
	V_CVT_I32_F32_e32 v37, v37                        ; 7E4A1125
	V_MUL_LO_I32 v39, 3, v37, 0, 0, 0, 0, 0           ; D2D60027 02024A83
	V_ADD_I32_e32 v37, 43, v39                        ; 4A4A4EAB
	V_LSHLREV_B32_e32 v37, 4, v37                     ; 344A4A84
	BUFFER_LOAD_DWORD v38, s[0:3] + v37               ; E0301000 80002625
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MAD_F32 v0, v38, v52, v0, 0, 0, 0, 0            ; D2820000 04026926
	V_OR_B32_e64 v38, 4, v43, 0, 0, 0, 0              ; D2380026 02025684
	BUFFER_LOAD_DWORD v38, s[0:3] + v38               ; E0301000 80002626
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MUL_F32_e32 v38, v38, v45                       ; 104C5B26
	V_OR_B32_e64 v40, 4, v49, 0, 0, 0, 0              ; D2380028 02026284
	BUFFER_LOAD_DWORD v40, s[0:3] + v40               ; E0301000 80002828
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MAD_F32 v38, v40, v46, v38, 0, 0, 0, 0          ; D2820026 049A5D28
	V_OR_B32_e64 v40, 4, v51, 0, 0, 0, 0              ; D2380028 02026684
	BUFFER_LOAD_DWORD v40, s[0:3] + v40               ; E0301000 80002828
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MAD_F32 v38, v40, v47, v38, 0, 0, 0, 0          ; D2820026 049A5F28
	V_OR_B32_e64 v40, 4, v37, 0, 0, 0, 0              ; D2380028 02024A84
	BUFFER_LOAD_DWORD v40, s[0:3] + v40               ; E0301000 80002828
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MAD_F32 v38, v40, v52, v38, 0, 0, 0, 0          ; D2820026 049A6928
	V_MUL_F32_e32 v38, v2, v38                        ; 104C4D02
	V_MAD_F32 v0, v1, v0, v38, 0, 0, 0, 0             ; D2820000 049A0101
	V_OR_B32_e64 v38, 8, v43, 0, 0, 0, 0              ; D2380026 02025688
	BUFFER_LOAD_DWORD v38, s[0:3] + v38               ; E0301000 80002626
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MUL_F32_e32 v38, v38, v45                       ; 104C5B26
	V_OR_B32_e64 v40, 8, v49, 0, 0, 0, 0              ; D2380028 02026288
	BUFFER_LOAD_DWORD v40, s[0:3] + v40               ; E0301000 80002828
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MAD_F32 v38, v40, v46, v38, 0, 0, 0, 0          ; D2820026 049A5D28
	V_OR_B32_e64 v40, 8, v51, 0, 0, 0, 0              ; D2380028 02026688
	BUFFER_LOAD_DWORD v40, s[0:3] + v40               ; E0301000 80002828
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MAD_F32 v38, v40, v47, v38, 0, 0, 0, 0          ; D2820026 049A5F28
	V_OR_B32_e64 v40, 8, v37, 0, 0, 0, 0              ; D2380028 02024A88
	BUFFER_LOAD_DWORD v40, s[0:3] + v40               ; E0301000 80002828
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MAD_F32 v38, v40, v52, v38, 0, 0, 0, 0          ; D2820026 049A6928
	V_MAD_F32 v0, v3, v38, v0, 0, 0, 0, 0             ; D2820000 04024D03
	V_OR_B32_e64 v38, 12, v43, 0, 0, 0, 0             ; D2380026 0202568C
	BUFFER_LOAD_DWORD v38, s[0:3] + v38               ; E0301000 80002626
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MUL_F32_e32 v38, v38, v45                       ; 104C5B26
	V_OR_B32_e64 v40, 12, v49, 0, 0, 0, 0             ; D2380028 0202628C
	BUFFER_LOAD_DWORD v40, s[0:3] + v40               ; E0301000 80002828
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MAD_F32 v38, v40, v46, v38, 0, 0, 0, 0          ; D2820026 049A5D28
	V_OR_B32_e64 v40, 12, v51, 0, 0, 0, 0             ; D2380028 0202668C
	BUFFER_LOAD_DWORD v40, s[0:3] + v40               ; E0301000 80002828
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MAD_F32 v38, v40, v47, v38, 0, 0, 0, 0          ; D2820026 049A5F28
	V_OR_B32_e64 v37, 12, v37, 0, 0, 0, 0             ; D2380025 02024A8C
	BUFFER_LOAD_DWORD v37, s[0:3] + v37               ; E0301000 80002525
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MAD_F32 v37, v37, v52, v38, 0, 0, 0, 0          ; D2820025 049A6925
	V_MAD_F32 v37, v4, v37, v0, 0, 0, 0, 0            ; D2820025 04024B04
	V_ADD_I32_e32 v0, 42, v42                         ; 4A0054AA
	V_LSHLREV_B32_e32 v0, 4, v0                       ; 34000084
	BUFFER_LOAD_DWORD v38, s[0:3] + v0                ; E0301000 80002600
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MUL_F32_e32 v38, v38, v45                       ; 104C5B26
	V_ADD_I32_e32 v40, 42, v44                        ; 4A5058AA
	V_LSHLREV_B32_e32 v40, 4, v40                     ; 34505084
	BUFFER_LOAD_DWORD v41, s[0:3] + v40               ; E0301000 80002928
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MAD_F32 v38, v41, v46, v38, 0, 0, 0, 0          ; D2820026 049A5D29
	V_ADD_I32_e32 v41, 42, v50                        ; 4A5264AA
	V_LSHLREV_B32_e32 v41, 4, v41                     ; 34525284
	BUFFER_LOAD_DWORD v43, s[0:3] + v41               ; E0301000 80002B29
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MAD_F32 v38, v43, v47, v38, 0, 0, 0, 0          ; D2820026 049A5F2B
	V_ADD_I32_e32 v43, 42, v39                        ; 4A564EAA
	V_LSHLREV_B32_e32 v43, 4, v43                     ; 34565684
	BUFFER_LOAD_DWORD v49, s[0:3] + v43               ; E0301000 8000312B
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MAD_F32 v38, v49, v52, v38, 0, 0, 0, 0          ; D2820026 049A6931
	V_OR_B32_e64 v49, 4, v0, 0, 0, 0, 0               ; D2380031 02020084
	BUFFER_LOAD_DWORD v49, s[0:3] + v49               ; E0301000 80003131
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MUL_F32_e32 v49, v49, v45                       ; 10625B31
	V_OR_B32_e64 v51, 4, v40, 0, 0, 0, 0              ; D2380033 02025084
	BUFFER_LOAD_DWORD v51, s[0:3] + v51               ; E0301000 80003333
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MAD_F32 v49, v51, v46, v49, 0, 0, 0, 0          ; D2820031 04C65D33
	V_OR_B32_e64 v51, 4, v41, 0, 0, 0, 0              ; D2380033 02025284
	BUFFER_LOAD_DWORD v51, s[0:3] + v51               ; E0301000 80003333
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MAD_F32 v49, v51, v47, v49, 0, 0, 0, 0          ; D2820031 04C65F33
	V_OR_B32_e64 v51, 4, v43, 0, 0, 0, 0              ; D2380033 02025684
	BUFFER_LOAD_DWORD v51, s[0:3] + v51               ; E0301000 80003333
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MAD_F32 v49, v51, v52, v49, 0, 0, 0, 0          ; D2820031 04C66933
	V_MUL_F32_e32 v49, v2, v49                        ; 10626302
	V_MAD_F32 v38, v1, v38, v49, 0, 0, 0, 0           ; D2820026 04C64D01
	V_OR_B32_e64 v49, 8, v0, 0, 0, 0, 0               ; D2380031 02020088
	BUFFER_LOAD_DWORD v49, s[0:3] + v49               ; E0301000 80003131
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MUL_F32_e32 v49, v49, v45                       ; 10625B31
	V_OR_B32_e64 v51, 8, v40, 0, 0, 0, 0              ; D2380033 02025088
	BUFFER_LOAD_DWORD v51, s[0:3] + v51               ; E0301000 80003333
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MAD_F32 v49, v51, v46, v49, 0, 0, 0, 0          ; D2820031 04C65D33
	V_OR_B32_e64 v51, 8, v41, 0, 0, 0, 0              ; D2380033 02025288
	BUFFER_LOAD_DWORD v51, s[0:3] + v51               ; E0301000 80003333
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MAD_F32 v49, v51, v47, v49, 0, 0, 0, 0          ; D2820031 04C65F33
	V_OR_B32_e64 v51, 8, v43, 0, 0, 0, 0              ; D2380033 02025688
	BUFFER_LOAD_DWORD v51, s[0:3] + v51               ; E0301000 80003333
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MAD_F32 v49, v51, v52, v49, 0, 0, 0, 0          ; D2820031 04C66933
	V_MAD_F32 v38, v3, v49, v38, 0, 0, 0, 0           ; D2820026 049A6303
	V_OR_B32_e64 v0, 12, v0, 0, 0, 0, 0               ; D2380000 0202008C
	BUFFER_LOAD_DWORD v0, s[0:3] + v0                 ; E0301000 80000000
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MUL_F32_e32 v0, v0, v45                         ; 10005B00
	V_OR_B32_e64 v40, 12, v40, 0, 0, 0, 0             ; D2380028 0202508C
	BUFFER_LOAD_DWORD v40, s[0:3] + v40               ; E0301000 80002828
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MAD_F32 v0, v40, v46, v0, 0, 0, 0, 0            ; D2820000 04025D28
	V_OR_B32_e64 v40, 12, v41, 0, 0, 0, 0             ; D2380028 0202528C
	BUFFER_LOAD_DWORD v40, s[0:3] + v40               ; E0301000 80002828
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MAD_F32 v0, v40, v47, v0, 0, 0, 0, 0            ; D2820000 04025F28
	V_OR_B32_e64 v40, 12, v43, 0, 0, 0, 0             ; D2380028 0202568C
	BUFFER_LOAD_DWORD v40, s[0:3] + v40               ; E0301000 80002828
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MAD_F32 v0, v40, v52, v0, 0, 0, 0, 0            ; D2820000 04026928
	V_MAD_F32 v38, v4, v0, v38, 0, 0, 0, 0            ; D2820026 049A0104
	V_ADD_I32_e32 v0, 41, v42                         ; 4A0054A9
	V_LSHLREV_B32_e32 v0, 4, v0                       ; 34000084
	BUFFER_LOAD_DWORD v40, s[0:3] + v0                ; E0301000 80002800
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MUL_F32_e32 v40, v40, v45                       ; 10505B28
	V_ADD_I32_e32 v41, 41, v44                        ; 4A5258A9
	V_LSHLREV_B32_e32 v41, 4, v41                     ; 34525284
	BUFFER_LOAD_DWORD v42, s[0:3] + v41               ; E0301000 80002A29
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MAD_F32 v40, v42, v46, v40, 0, 0, 0, 0          ; D2820028 04A25D2A
	V_ADD_I32_e32 v42, 41, v50                        ; 4A5464A9
	V_LSHLREV_B32_e32 v42, 4, v42                     ; 34545484
	BUFFER_LOAD_DWORD v43, s[0:3] + v42               ; E0301000 80002B2A
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MAD_F32 v40, v43, v47, v40, 0, 0, 0, 0          ; D2820028 04A25F2B
	V_ADD_I32_e32 v39, 41, v39                        ; 4A4E4EA9
	V_LSHLREV_B32_e32 v39, 4, v39                     ; 344E4E84
	BUFFER_LOAD_DWORD v43, s[0:3] + v39               ; E0301000 80002B27
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MAD_F32 v40, v43, v52, v40, 0, 0, 0, 0          ; D2820028 04A2692B
	V_OR_B32_e64 v43, 4, v0, 0, 0, 0, 0               ; D238002B 02020084
	BUFFER_LOAD_DWORD v43, s[0:3] + v43               ; E0301000 80002B2B
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MUL_F32_e32 v43, v43, v45                       ; 10565B2B
	V_OR_B32_e64 v44, 4, v41, 0, 0, 0, 0              ; D238002C 02025284
	BUFFER_LOAD_DWORD v44, s[0:3] + v44               ; E0301000 80002C2C
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MAD_F32 v43, v44, v46, v43, 0, 0, 0, 0          ; D282002B 04AE5D2C
	V_OR_B32_e64 v44, 4, v42, 0, 0, 0, 0              ; D238002C 02025484
	BUFFER_LOAD_DWORD v44, s[0:3] + v44               ; E0301000 80002C2C
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MAD_F32 v43, v44, v47, v43, 0, 0, 0, 0          ; D282002B 04AE5F2C
	V_OR_B32_e64 v44, 4, v39, 0, 0, 0, 0              ; D238002C 02024E84
	BUFFER_LOAD_DWORD v44, s[0:3] + v44               ; E0301000 80002C2C
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MAD_F32 v43, v44, v52, v43, 0, 0, 0, 0          ; D282002B 04AE692C
	V_MUL_F32_e32 v43, v2, v43                        ; 10565702
	V_MAD_F32 v40, v1, v40, v43, 0, 0, 0, 0           ; D2820028 04AE5101
	V_OR_B32_e64 v43, 8, v0, 0, 0, 0, 0               ; D238002B 02020088
	BUFFER_LOAD_DWORD v43, s[0:3] + v43               ; E0301000 80002B2B
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MUL_F32_e32 v43, v43, v45                       ; 10565B2B
	V_OR_B32_e64 v44, 8, v41, 0, 0, 0, 0              ; D238002C 02025288
	BUFFER_LOAD_DWORD v44, s[0:3] + v44               ; E0301000 80002C2C
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MAD_F32 v43, v44, v46, v43, 0, 0, 0, 0          ; D282002B 04AE5D2C
	V_OR_B32_e64 v44, 8, v42, 0, 0, 0, 0              ; D238002C 02025488
	BUFFER_LOAD_DWORD v44, s[0:3] + v44               ; E0301000 80002C2C
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MAD_F32 v43, v44, v47, v43, 0, 0, 0, 0          ; D282002B 04AE5F2C
	V_OR_B32_e64 v44, 8, v39, 0, 0, 0, 0              ; D238002C 02024E88
	BUFFER_LOAD_DWORD v44, s[0:3] + v44               ; E0301000 80002C2C
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MAD_F32 v43, v44, v52, v43, 0, 0, 0, 0          ; D282002B 04AE692C
	V_MAD_F32 v40, v3, v43, v40, 0, 0, 0, 0           ; D2820028 04A25703
	V_OR_B32_e64 v0, 12, v0, 0, 0, 0, 0               ; D2380000 0202008C
	BUFFER_LOAD_DWORD v0, s[0:3] + v0                 ; E0301000 80000000
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MUL_F32_e32 v0, v0, v45                         ; 10005B00
	V_OR_B32_e64 v41, 12, v41, 0, 0, 0, 0             ; D2380029 0202528C
	BUFFER_LOAD_DWORD v41, s[0:3] + v41               ; E0301000 80002929
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MAD_F32 v0, v41, v46, v0, 0, 0, 0, 0            ; D2820000 04025D29
	V_OR_B32_e64 v41, 12, v42, 0, 0, 0, 0             ; D2380029 0202548C
	BUFFER_LOAD_DWORD v41, s[0:3] + v41               ; E0301000 80002929
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MAD_F32 v0, v41, v47, v0, 0, 0, 0, 0            ; D2820000 04025F29
	V_OR_B32_e64 v39, 12, v39, 0, 0, 0, 0             ; D2380027 02024E8C
	BUFFER_LOAD_DWORD v39, s[0:3] + v39               ; E0301000 80002727
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MAD_F32 v0, v39, v52, v0, 0, 0, 0, 0            ; D2820000 04026927
	V_MAD_F32 v39, v4, v0, v40, 0, 0, 0, 0            ; D2820027 04A20104
	S_OR_B64 exec, exec, s[4:5]                       ; 88FE047E
	V_MUL_F32_e64 v0, v38, v36, 0, 0, 0, 0            ; D2100000 02024926
	V_MAD_F32 v0, v39, v35, v0, 0, 0, 0, 0            ; D2820000 04024727
	V_MAD_F32 v0, v37, v32, v0, 0, 0, 0, 0            ; D2820000 04024125
	V_MAD_F32 v0, v4, v29, v0, 0, 0, 0, 0             ; D2820000 04023B04
	V_MUL_F32_e64 v29, v6, v34, 0, 0, 0, 0            ; D210001D 02024506
	V_MAD_F32 v29, v5, v33, v29, 0, 0, 0, 0           ; D282001D 04764305
	V_MAD_F32 v28, v7, v28, v29, 0, 0, 0, 0           ; D282001C 04763907
	V_MAD_F32 v18, v8, v18, v28, 0, 0, 0, 0           ; D2820012 04722508
	V_MUL_F32_e64 v28, v6, v31, 0, 0, 0, 0            ; D210001C 02023F06
	V_MAD_F32 v28, v5, v30, v28, 0, 0, 0, 0           ; D282001C 04723D05
	V_MAD_F32 v19, v7, v19, v28, 0, 0, 0, 0           ; D2820013 04722707
	V_MAD_F32 v5, v8, v17, v19, 0, 0, 0, 0            ; D2820005 044E2308
	V_MOV_B32_e32 v6, 1.000000e+00                    ; 7E0C02F2
	EXP 15, 32, 0, 0, 0, v5, v18, v0, v6              ; F800020F 06001205
	S_WAITCNT expcnt(0)                               ; BF8C070F
	V_MUL_F32_e64 v0, v38, v27, 0, 0, 0, 0            ; D2100000 02023726
	V_MAD_F32 v0, v39, v26, v0, 0, 0, 0, 0            ; D2820000 04023527
	V_MAD_F32 v0, v37, v16, v0, 0, 0, 0, 0            ; D2820000 04022125
	V_MAD_F32 v0, v4, v12, v0, 0, 0, 0, 0             ; D2820000 04021904
	V_MUL_F32_e64 v5, v38, v25, 0, 0, 0, 0            ; D2100005 02023326
	V_MAD_F32 v5, v39, v24, v5, 0, 0, 0, 0            ; D2820005 04163127
	V_MAD_F32 v5, v37, v15, v5, 0, 0, 0, 0            ; D2820005 04161F25
	V_MAD_F32 v5, v4, v11, v5, 0, 0, 0, 0             ; D2820005 04161704
	V_MUL_F32_e64 v6, v38, v23, 0, 0, 0, 0            ; D2100006 02022F26
	V_MAD_F32 v6, v39, v22, v6, 0, 0, 0, 0            ; D2820006 041A2D27
	V_MAD_F32 v6, v37, v14, v6, 0, 0, 0, 0            ; D2820006 041A1D25
	V_MAD_F32 v6, v4, v10, v6, 0, 0, 0, 0             ; D2820006 041A1504
	V_MUL_F32_e64 v7, v38, v21, 0, 0, 0, 0            ; D2100007 02022B26
	V_MAD_F32 v7, v39, v20, v7, 0, 0, 0, 0            ; D2820007 041E2927
	V_MAD_F32 v7, v37, v13, v7, 0, 0, 0, 0            ; D2820007 041E1B25
	V_MAD_F32 v1, v4, v9, v7, 0, 0, 0, 0              ; D2820001 041E1304
	EXP 15, 12, 0, 1, 0, v1, v6, v5, v0               ; F80008CF 00050601
	S_ENDPGM                                          ; BF810000

FRAG
DCL IN[0], GENERIC[0], CONSTANT
DCL OUT[0], COLOR
  0: MOV OUT[0], IN[0]
  1: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %21 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %4)
  %22 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %4)
  %23 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %4)
  %24 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %4)
  %25 = call i32 @llvm.SI.packf16(float %21, float %22)
  %26 = bitcast i32 %25 to float
  %27 = call i32 @llvm.SI.packf16(float %23, float %24)
  %28 = bitcast i32 %27 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %26, float %28, float %26, float %28)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.constant(i32, i32, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR7 in %vreg4

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR7
	%EXEC<def> = S_WQM_B64 %EXEC
	%M0<def> = S_MOV_B32 %SGPR7
	%VGPR0<def> = V_INTERP_MOV_F32 2, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_INTERP_MOV_F32 2, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR1<kill>, %VGPR0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_INTERP_MOV_F32 2, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_INTERP_MOV_F32 2, 0, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR2<kill>, %VGPR1<kill>, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR1<kill>, %VGPR0<kill>, %VGPR1, %VGPR0, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_WQM_B64 exec, exec                ; BEFE0A7E
	S_MOV_B32 m0, s7                    ; BEFC0307
	V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302
	V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202
	V_CVT_PKRTZ_F16_F32_e32 v0, v1, v0  ; 5E000101
	V_INTERP_MOV_F32 v1, P0, 1, 0, [m0] ; C8060102
	V_INTERP_MOV_F32 v2, P0, 0, 0, [m0] ; C80A0002
	V_CVT_PKRTZ_F16_F32_e32 v1, v2, v1  ; 5E020302
	EXP 15, 0, 1, 1, 1, v1, v0, v1, v0  ; F8001C0F 00010001
	S_ENDPGM                            ; BF810000

FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL CONST[0]
DCL TEMP[0..2], LOCAL
  0: MOV TEMP[0].xy, IN[0].xyyy
  1: TEX TEMP[0].xyz, TEMP[0], SAMP[0], 2D
  2: DP3 TEMP[0].x, TEMP[0].xyzz, CONST[0].xyzz
  3: ABS TEMP[1].x, TEMP[0].xxxx
  4: POW TEMP[1].x, TEMP[1].xxxx, CONST[0].wwww
  5: SSG TEMP[2].x, TEMP[0].xxxx
  6: MUL TEMP[0].x, TEMP[1].xxxx, TEMP[2].xxxx
  7: MOV OUT[0], TEMP[0].xxxx
  8: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %21 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
  %22 = load <16 x i8> addrspace(2)* %21, !tbaa !0
  %23 = call float @llvm.SI.load.const(<16 x i8> %22, i32 0)
  %24 = call float @llvm.SI.load.const(<16 x i8> %22, i32 4)
  %25 = call float @llvm.SI.load.const(<16 x i8> %22, i32 8)
  %26 = call float @llvm.SI.load.const(<16 x i8> %22, i32 12)
  %27 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0
  %28 = load <32 x i8> addrspace(2)* %27, !tbaa !0
  %29 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0
  %30 = load <16 x i8> addrspace(2)* %29, !tbaa !0
  %31 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %4, <2 x i32> %6)
  %32 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %4, <2 x i32> %6)
  %33 = bitcast float %31 to i32
  %34 = bitcast float %32 to i32
  %35 = insertelement <2 x i32> undef, i32 %33, i32 0
  %36 = insertelement <2 x i32> %35, i32 %34, i32 1
  %37 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %36, <32 x i8> %28, <16 x i8> %30, i32 2)
  %38 = extractelement <4 x float> %37, i32 0
  %39 = extractelement <4 x float> %37, i32 1
  %40 = extractelement <4 x float> %37, i32 2
  %41 = fmul float %38, %23
  %42 = fmul float %39, %24
  %43 = fadd float %42, %41
  %44 = fmul float %40, %25
  %45 = fadd float %43, %44
  %46 = call float @fabs(float %45)
  %47 = call float @llvm.pow.f32(float %46, float %26)
  %48 = fcmp ugt float %45, 0.000000e+00
  %49 = select i1 %48, float 1.000000e+00, float %45
  %50 = fcmp uge float %49, 0.000000e+00
  %51 = select i1 %50, float %49, float -1.000000e+00
  %52 = fmul float %47, %51
  %53 = call i32 @llvm.SI.packf16(float %52, float %52)
  %54 = bitcast i32 %53 to float
  %55 = call i32 @llvm.SI.packf16(float %52, float %52)
  %56 = bitcast i32 %55 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %54, float %56, float %54, float %56)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readonly
declare float @fabs(float) #2

; Function Attrs: nounwind readonly
declare float @llvm.pow.f32(float, float) #3

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readonly }
attributes #3 = { nounwind readonly }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR7 in %vreg4, %VGPR0 in %vreg5, %VGPR1 in %vreg6

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR7 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR7
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-def>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%32](align=8)(tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%29](tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2<def> = IMAGE_SAMPLE_V3_V2 7, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%22](align=8)(tbaa=!"const")
	S_WAITCNT 112
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 0; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR3<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_MUL_F32_e64 %VGPR0, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR4<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_MAD_F32 %VGPR1, %VGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR4<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR2, %VGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2<imp-use,kill>
	%SGPR4_SGPR5<def> = V_CMP_U_F32_e64 %VGPR0, %VGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_GT_F32_e64 %VGPR0, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = S_OR_B64 %SGPR6_SGPR7<kill>, %SGPR4_SGPR5<kill>
	%VGPR1<def> = V_CNDMASK_B32_e64 %VGPR0, 1.000000e+00, %SGPR4_SGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_U_F32_e64 %VGPR1, %VGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %VGPR1, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = S_OR_B64 %SGPR6_SGPR7<kill>, %SGPR4_SGPR5<kill>
	%VGPR1<def> = V_CNDMASK_B32_e64 -1.000000e+00, %VGPR1<kill>, %SGPR4_SGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_F32_e64 %VGPR0<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_LOG_F32_e32 %VGPR0<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 3; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR0<def> = V_MUL_LEGACY_F32_e32 %SGPR0<kill>, %VGPR0<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_EXP_F32_e32 %VGPR0<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR0<kill>, %VGPR1<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0<kill>, %VGPR0, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR0<kill>, %VGPR0, %VGPR0, %VGPR0, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_WQM_B64 exec, exec                                                   ; BEFE0A7E
	S_MOV_B32 m0, s7                                                       ; BEFC0307
	V_INTERP_P1_F32 v3, v0, 1, 0, [m0]                                     ; C80C0100
	V_INTERP_P2_F32 v3, [v3], v1, 1, 0, [m0]                               ; C80D0101
	V_INTERP_P1_F32 v2, v0, 0, 0, [m0]                                     ; C8080000
	V_INTERP_P2_F32 v2, [v2], v1, 0, 0, [m0]                               ; C8090001
	S_LOAD_DWORDX4 s[8:11], s[2:3], 0                                      ; C0840300
	S_LOAD_DWORDX8 s[12:19], s[4:5], 0                                     ; C0C60500
	S_WAITCNT lgkmcnt(0)                                                   ; BF8C007F
	IMAGE_SAMPLE v[0:2], 7, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[12:19], s[8:11] ; F0800700 00430002
	S_LOAD_DWORDX4 s[0:3], s[0:1], 0                                       ; C0800100
	S_WAITCNT vmcnt(0) lgkmcnt(0)                                          ; BF8C0070
	S_BUFFER_LOAD_DWORD s4, s[0:3], 0                                      ; C2020100
	S_WAITCNT lgkmcnt(0)                                                   ; BF8C007F
	V_MOV_B32_e32 v3, s4                                                   ; 7E060204
	V_MUL_F32_e64 v3, v0, v3, 0, 0, 0, 0                                   ; D2100003 02020700
	S_BUFFER_LOAD_DWORD s4, s[0:3], 1                                      ; C2020101
	S_WAITCNT lgkmcnt(0)                                                   ; BF8C007F
	V_MOV_B32_e32 v4, s4                                                   ; 7E080204
	V_MAD_F32 v3, v1, v4, v3, 0, 0, 0, 0                                   ; D2820003 040E0901
	S_BUFFER_LOAD_DWORD s4, s[0:3], 2                                      ; C2020102
	S_WAITCNT lgkmcnt(0)                                                   ; BF8C007F
	V_MOV_B32_e32 v4, s4                                                   ; 7E080204
	V_MAD_F32 v0, v2, v4, v3, 0, 0, 0, 0                                   ; D2820000 040E0902
	V_CMP_U_F32_e64 s[4:5], v0, v0, 0, 0, 0, 0                             ; D0100004 02020100
	V_CMP_GT_F32_e64 s[6:7], v0, 0.000000e+00, 0, 0, 0, 0                  ; D0080006 02010100
	S_OR_B64 s[4:5], s[6:7], s[4:5]                                        ; 88840406
	V_CNDMASK_B32_e64 v1, v0, 1.000000e+00, s[4:5], 0, 0, 0, 0             ; D2000001 0011E500
	V_CMP_U_F32_e64 s[4:5], v1, v1, 0, 0, 0, 0                             ; D0100004 02020301
	V_CMP_GE_F32_e64 s[6:7], v1, 0.000000e+00, 0, 0, 0, 0                  ; D00C0006 02010101
	S_OR_B64 s[4:5], s[6:7], s[4:5]                                        ; 88840406
	V_CNDMASK_B32_e64 v1, -1.000000e+00, v1, s[4:5], 0, 0, 0, 0            ; D2000001 001202F3
	V_ADD_F32_e64 v0, v0, 0, 1, 0, 0, 0                                    ; D2060100 02010100
	V_LOG_F32_e32 v0, v0                                                   ; 7E004F00
	S_BUFFER_LOAD_DWORD s0, s[0:3], 3                                      ; C2000103
	S_WAITCNT lgkmcnt(0)                                                   ; BF8C007F
	V_MUL_LEGACY_F32_e32 v0, s0, v0                                        ; 0E000000
	V_EXP_F32_e32 v0, v0                                                   ; 7E004B00
	V_MUL_F32_e32 v0, v0, v1                                               ; 10000300
	V_CVT_PKRTZ_F16_F32_e32 v0, v0, v0                                     ; 5E000100
	EXP 15, 0, 1, 1, 1, v0, v0, v0, v0                                     ; F8001C0F 00000000
	S_ENDPGM                                                               ; BF810000

VERT
DCL IN[0]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[19]
DCL CONST[0..1]
DCL TEMP[0..2], LOCAL
IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
  0: MOV TEMP[0].zw, IMM[0].yyxy
  1: MOV TEMP[0].xy, IN[0].xyxx
  2: MAD TEMP[1].xy, IN[0].zwww, CONST[0].xyyy, CONST[0].zwww
  3: MAD TEMP[2].xy, IN[0].zwww, CONST[1].xyyy, CONST[1].zwww
  4: MOV TEMP[1].zw, TEMP[2].yyxy
  5: MOV OUT[1], TEMP[1]
  6: MOV OUT[0], TEMP[0]
  7: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0)
  %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4)
  %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8)
  %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12)
  %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16)
  %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20)
  %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24)
  %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28)
  %20 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %21, i32 0, i32 %6)
  %23 = extractelement <4 x float> %22, i32 0
  %24 = extractelement <4 x float> %22, i32 1
  %25 = extractelement <4 x float> %22, i32 2
  %26 = extractelement <4 x float> %22, i32 3
  %27 = fmul float %25, %12
  %28 = fadd float %27, %14
  %29 = fmul float %26, %13
  %30 = fadd float %29, %15
  %31 = fmul float %25, %16
  %32 = fadd float %31, %18
  %33 = fmul float %26, %17
  %34 = fadd float %33, %19
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %28, float %30, float %32, float %34)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %23, float %24, float 0.000000e+00, float 1.000000e+00)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg6

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%23](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%11](align=8)(tbaa=!"const")
	S_WAITCNT 112
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 7; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR4<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 5; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR3, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 6; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 4; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR2, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 3; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR3, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 0; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR8<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR2, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 32, 0, 0, 0, %VGPR7<kill>, %VGPR6<kill>, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>
	S_WAITCNT 1807
	%VGPR4<def> = V_MOV_B32_e32 1.000000e+00, %EXEC<imp-use>
	%VGPR5<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR1, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_LOAD_DWORDX4 s[4:7], s[6:7], 0               ; C0820700
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	BUFFER_LOAD_FORMAT_XYZW v[0:3], s[4:7][v0] + 0 ; E00C2000 80010000
	S_LOAD_DWORDX4 s[0:3], s[0:1], 0               ; C0800100
	S_WAITCNT vmcnt(0) lgkmcnt(0)                  ; BF8C0070
	S_BUFFER_LOAD_DWORD s4, s[0:3], 7              ; C2020107
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v4, s4                           ; 7E080204
	S_BUFFER_LOAD_DWORD s4, s[0:3], 5              ; C2020105
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v5, s4                           ; 7E0A0204
	V_MAD_F32 v4, v3, v5, v4, 0, 0, 0, 0           ; D2820004 04120B03
	S_BUFFER_LOAD_DWORD s4, s[0:3], 6              ; C2020106
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v5, s4                           ; 7E0A0204
	S_BUFFER_LOAD_DWORD s4, s[0:3], 4              ; C2020104
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v6, s4                           ; 7E0C0204
	V_MAD_F32 v5, v2, v6, v5, 0, 0, 0, 0           ; D2820005 04160D02
	S_BUFFER_LOAD_DWORD s4, s[0:3], 3              ; C2020103
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v6, s4                           ; 7E0C0204
	S_BUFFER_LOAD_DWORD s4, s[0:3], 1              ; C2020101
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v7, s4                           ; 7E0E0204
	V_MAD_F32 v6, v3, v7, v6, 0, 0, 0, 0           ; D2820006 041A0F03
	S_BUFFER_LOAD_DWORD s4, s[0:3], 2              ; C2020102
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v7, s4                           ; 7E0E0204
	S_BUFFER_LOAD_DWORD s0, s[0:3], 0              ; C2000100
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v8, s0                           ; 7E100200
	V_MAD_F32 v7, v2, v8, v7, 0, 0, 0, 0           ; D2820007 041E1102
	EXP 15, 32, 0, 0, 0, v7, v6, v5, v4            ; F800020F 04050607
	S_WAITCNT expcnt(0)                            ; BF8C070F
	V_MOV_B32_e32 v4, 1.000000e+00                 ; 7E0802F2
	V_MOV_B32_e32 v5, 0.000000e+00                 ; 7E0A0280
	EXP 15, 12, 0, 1, 0, v0, v1, v5, v4            ; F80008CF 04050100
	S_ENDPGM                                       ; BF810000

FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL CONST[0]
DCL TEMP[0..2], LOCAL
  0: MOV TEMP[0].xy, IN[0].xyyy
  1: TEX TEMP[0].xyz, TEMP[0], SAMP[0], 2D
  2: DP3 TEMP[0].x, TEMP[0].xyzz, CONST[0].xyzz
  3: ABS TEMP[1].x, TEMP[0].xxxx
  4: POW TEMP[1].x, TEMP[1].xxxx, CONST[0].wwww
  5: SSG TEMP[2].x, TEMP[0].xxxx
  6: MUL TEMP[0].x, TEMP[1].xxxx, TEMP[2].xxxx
  7: MOV OUT[0], TEMP[0].xxxx
  8: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %21 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
  %22 = load <16 x i8> addrspace(2)* %21, !tbaa !0
  %23 = call float @llvm.SI.load.const(<16 x i8> %22, i32 0)
  %24 = call float @llvm.SI.load.const(<16 x i8> %22, i32 4)
  %25 = call float @llvm.SI.load.const(<16 x i8> %22, i32 8)
  %26 = call float @llvm.SI.load.const(<16 x i8> %22, i32 12)
  %27 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0
  %28 = load <32 x i8> addrspace(2)* %27, !tbaa !0
  %29 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0
  %30 = load <16 x i8> addrspace(2)* %29, !tbaa !0
  %31 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %4, <2 x i32> %6)
  %32 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %4, <2 x i32> %6)
  %33 = bitcast float %31 to i32
  %34 = bitcast float %32 to i32
  %35 = insertelement <2 x i32> undef, i32 %33, i32 0
  %36 = insertelement <2 x i32> %35, i32 %34, i32 1
  %37 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %36, <32 x i8> %28, <16 x i8> %30, i32 2)
  %38 = extractelement <4 x float> %37, i32 0
  %39 = extractelement <4 x float> %37, i32 1
  %40 = extractelement <4 x float> %37, i32 2
  %41 = fmul float %38, %23
  %42 = fmul float %39, %24
  %43 = fadd float %42, %41
  %44 = fmul float %40, %25
  %45 = fadd float %43, %44
  %46 = call float @fabs(float %45)
  %47 = call float @llvm.pow.f32(float %46, float %26)
  %48 = fcmp ugt float %45, 0.000000e+00
  %49 = select i1 %48, float 1.000000e+00, float %45
  %50 = fcmp uge float %49, 0.000000e+00
  %51 = select i1 %50, float %49, float -1.000000e+00
  %52 = fmul float %47, %51
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %52, float %52, float %52, float %52)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readonly
declare float @fabs(float) #2

; Function Attrs: nounwind readonly
declare float @llvm.pow.f32(float, float) #3

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readonly }
attributes #3 = { nounwind readonly }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR7 in %vreg4, %VGPR0 in %vreg5, %VGPR1 in %vreg6

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR7 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR7
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-def>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%32](align=8)(tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%29](tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2<def> = IMAGE_SAMPLE_V3_V2 7, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%22](align=8)(tbaa=!"const")
	S_WAITCNT 112
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 0; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR3<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_MUL_F32_e64 %VGPR0, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR4<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_MAD_F32 %VGPR1, %VGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR4<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR2, %VGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2<imp-use,kill>
	%SGPR4_SGPR5<def> = V_CMP_U_F32_e64 %VGPR0, %VGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_GT_F32_e64 %VGPR0, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = S_OR_B64 %SGPR6_SGPR7<kill>, %SGPR4_SGPR5<kill>
	%VGPR1<def> = V_CNDMASK_B32_e64 %VGPR0, 1.000000e+00, %SGPR4_SGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_U_F32_e64 %VGPR1, %VGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %VGPR1, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = S_OR_B64 %SGPR6_SGPR7<kill>, %SGPR4_SGPR5<kill>
	%VGPR1<def> = V_CNDMASK_B32_e64 -1.000000e+00, %VGPR1<kill>, %SGPR4_SGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_F32_e64 %VGPR0<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_LOG_F32_e32 %VGPR0<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 3; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR0<def> = V_MUL_LEGACY_F32_e32 %SGPR0<kill>, %VGPR0<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_EXP_F32_e32 %VGPR0<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR0<kill>, %VGPR1<kill>, %EXEC<imp-use>
	EXP 15, 0, 0, 1, 1, %VGPR0<kill>, %VGPR0, %VGPR0, %VGPR0, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_WQM_B64 exec, exec                                                   ; BEFE0A7E
	S_MOV_B32 m0, s7                                                       ; BEFC0307
	V_INTERP_P1_F32 v3, v0, 1, 0, [m0]                                     ; C80C0100
	V_INTERP_P2_F32 v3, [v3], v1, 1, 0, [m0]                               ; C80D0101
	V_INTERP_P1_F32 v2, v0, 0, 0, [m0]                                     ; C8080000
	V_INTERP_P2_F32 v2, [v2], v1, 0, 0, [m0]                               ; C8090001
	S_LOAD_DWORDX4 s[8:11], s[2:3], 0                                      ; C0840300
	S_LOAD_DWORDX8 s[12:19], s[4:5], 0                                     ; C0C60500
	S_WAITCNT lgkmcnt(0)                                                   ; BF8C007F
	IMAGE_SAMPLE v[0:2], 7, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[12:19], s[8:11] ; F0800700 00430002
	S_LOAD_DWORDX4 s[0:3], s[0:1], 0                                       ; C0800100
	S_WAITCNT vmcnt(0) lgkmcnt(0)                                          ; BF8C0070
	S_BUFFER_LOAD_DWORD s4, s[0:3], 0                                      ; C2020100
	S_WAITCNT lgkmcnt(0)                                                   ; BF8C007F
	V_MOV_B32_e32 v3, s4                                                   ; 7E060204
	V_MUL_F32_e64 v3, v0, v3, 0, 0, 0, 0                                   ; D2100003 02020700
	S_BUFFER_LOAD_DWORD s4, s[0:3], 1                                      ; C2020101
	S_WAITCNT lgkmcnt(0)                                                   ; BF8C007F
	V_MOV_B32_e32 v4, s4                                                   ; 7E080204
	V_MAD_F32 v3, v1, v4, v3, 0, 0, 0, 0                                   ; D2820003 040E0901
	S_BUFFER_LOAD_DWORD s4, s[0:3], 2                                      ; C2020102
	S_WAITCNT lgkmcnt(0)                                                   ; BF8C007F
	V_MOV_B32_e32 v4, s4                                                   ; 7E080204
	V_MAD_F32 v0, v2, v4, v3, 0, 0, 0, 0                                   ; D2820000 040E0902
	V_CMP_U_F32_e64 s[4:5], v0, v0, 0, 0, 0, 0                             ; D0100004 02020100
	V_CMP_GT_F32_e64 s[6:7], v0, 0.000000e+00, 0, 0, 0, 0                  ; D0080006 02010100
	S_OR_B64 s[4:5], s[6:7], s[4:5]                                        ; 88840406
	V_CNDMASK_B32_e64 v1, v0, 1.000000e+00, s[4:5], 0, 0, 0, 0             ; D2000001 0011E500
	V_CMP_U_F32_e64 s[4:5], v1, v1, 0, 0, 0, 0                             ; D0100004 02020301
	V_CMP_GE_F32_e64 s[6:7], v1, 0.000000e+00, 0, 0, 0, 0                  ; D00C0006 02010101
	S_OR_B64 s[4:5], s[6:7], s[4:5]                                        ; 88840406
	V_CNDMASK_B32_e64 v1, -1.000000e+00, v1, s[4:5], 0, 0, 0, 0            ; D2000001 001202F3
	V_ADD_F32_e64 v0, v0, 0, 1, 0, 0, 0                                    ; D2060100 02010100
	V_LOG_F32_e32 v0, v0                                                   ; 7E004F00
	S_BUFFER_LOAD_DWORD s0, s[0:3], 3                                      ; C2000103
	S_WAITCNT lgkmcnt(0)                                                   ; BF8C007F
	V_MUL_LEGACY_F32_e32 v0, s0, v0                                        ; 0E000000
	V_EXP_F32_e32 v0, v0                                                   ; 7E004B00
	V_MUL_F32_e32 v0, v0, v1                                               ; 10000300
	EXP 15, 0, 0, 1, 1, v0, v0, v0, v0                                     ; F800180F 00000000
	S_ENDPGM                                                               ; BF810000

VERT
DCL IN[0]
DCL OUT[0], POSITION
DCL CONST[0..6]
DCL TEMP[0..2], LOCAL
IMM[0] FLT32 {    1.0000,     0.0000,     0.0000,     0.0000}
  0: DP4 TEMP[0].x, IN[0], CONST[0]
  1: DP4 TEMP[1].x, IN[0], CONST[1]
  2: MOV TEMP[0].y, TEMP[1].xxxx
  3: DP4 TEMP[1].x, IN[0], CONST[2]
  4: MOV TEMP[0].z, TEMP[1].xxxx
  5: MOV TEMP[0].xyz, TEMP[0].xyzx
  6: MOV TEMP[0].w, IMM[0].xxxx
  7: DP4 TEMP[1].x, TEMP[0], CONST[3]
  8: DP4 TEMP[2].x, TEMP[0], CONST[4]
  9: MOV TEMP[1].y, TEMP[2].xxxx
 10: DP4 TEMP[2].x, TEMP[0], CONST[5]
 11: MOV TEMP[1].z, TEMP[2].xxxx
 12: DP4 TEMP[0].x, TEMP[0], CONST[6]
 13: MOV TEMP[1].w, TEMP[0].xxxx
 14: MOV OUT[0], TEMP[1]
 15: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0)
  %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4)
  %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8)
  %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12)
  %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16)
  %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20)
  %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24)
  %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28)
  %20 = call float @llvm.SI.load.const(<16 x i8> %11, i32 32)
  %21 = call float @llvm.SI.load.const(<16 x i8> %11, i32 36)
  %22 = call float @llvm.SI.load.const(<16 x i8> %11, i32 40)
  %23 = call float @llvm.SI.load.const(<16 x i8> %11, i32 44)
  %24 = call float @llvm.SI.load.const(<16 x i8> %11, i32 48)
  %25 = call float @llvm.SI.load.const(<16 x i8> %11, i32 52)
  %26 = call float @llvm.SI.load.const(<16 x i8> %11, i32 56)
  %27 = call float @llvm.SI.load.const(<16 x i8> %11, i32 60)
  %28 = call float @llvm.SI.load.const(<16 x i8> %11, i32 64)
  %29 = call float @llvm.SI.load.const(<16 x i8> %11, i32 68)
  %30 = call float @llvm.SI.load.const(<16 x i8> %11, i32 72)
  %31 = call float @llvm.SI.load.const(<16 x i8> %11, i32 76)
  %32 = call float @llvm.SI.load.const(<16 x i8> %11, i32 80)
  %33 = call float @llvm.SI.load.const(<16 x i8> %11, i32 84)
  %34 = call float @llvm.SI.load.const(<16 x i8> %11, i32 88)
  %35 = call float @llvm.SI.load.const(<16 x i8> %11, i32 92)
  %36 = call float @llvm.SI.load.const(<16 x i8> %11, i32 96)
  %37 = call float @llvm.SI.load.const(<16 x i8> %11, i32 100)
  %38 = call float @llvm.SI.load.const(<16 x i8> %11, i32 104)
  %39 = call float @llvm.SI.load.const(<16 x i8> %11, i32 108)
  %40 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0
  %41 = load <16 x i8> addrspace(2)* %40, !tbaa !0
  %42 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %41, i32 0, i32 %6)
  %43 = extractelement <4 x float> %42, i32 0
  %44 = extractelement <4 x float> %42, i32 1
  %45 = extractelement <4 x float> %42, i32 2
  %46 = extractelement <4 x float> %42, i32 3
  %47 = fmul float %43, %12
  %48 = fmul float %44, %13
  %49 = fadd float %47, %48
  %50 = fmul float %45, %14
  %51 = fadd float %49, %50
  %52 = fmul float %46, %15
  %53 = fadd float %51, %52
  %54 = fmul float %43, %16
  %55 = fmul float %44, %17
  %56 = fadd float %54, %55
  %57 = fmul float %45, %18
  %58 = fadd float %56, %57
  %59 = fmul float %46, %19
  %60 = fadd float %58, %59
  %61 = fmul float %43, %20
  %62 = fmul float %44, %21
  %63 = fadd float %61, %62
  %64 = fmul float %45, %22
  %65 = fadd float %63, %64
  %66 = fmul float %46, %23
  %67 = fadd float %65, %66
  %68 = fmul float %53, %24
  %69 = fmul float %60, %25
  %70 = fadd float %68, %69
  %71 = fmul float %67, %26
  %72 = fadd float %70, %71
  %73 = fmul float 1.000000e+00, %27
  %74 = fadd float %72, %73
  %75 = fmul float %53, %28
  %76 = fmul float %60, %29
  %77 = fadd float %75, %76
  %78 = fmul float %67, %30
  %79 = fadd float %77, %78
  %80 = fmul float 1.000000e+00, %31
  %81 = fadd float %79, %80
  %82 = fmul float %53, %32
  %83 = fmul float %60, %33
  %84 = fadd float %82, %83
  %85 = fmul float %67, %34
  %86 = fadd float %84, %85
  %87 = fmul float 1.000000e+00, %35
  %88 = fadd float %86, %87
  %89 = fmul float %53, %36
  %90 = fmul float %60, %37
  %91 = fadd float %89, %90
  %92 = fmul float %67, %38
  %93 = fadd float %91, %92
  %94 = fmul float 1.000000e+00, %39
  %95 = fadd float %93, %94
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %74, float %81, float %88, float %95)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg6

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%43](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%11](align=8)(tbaa=!"const")
	S_WAITCNT 112
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR4<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e64 %VGPR1, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 0; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR0, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR2, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 3; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR3, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 5; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MUL_F32_e64 %VGPR1, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 4; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR0, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 6; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR2, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 7; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR3, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 25; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR5, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 24; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MAD_F32 %VGPR4, %SGPR4<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 9; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MUL_F32_e64 %VGPR1, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 8; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR8<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR0, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 10; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR8<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR2, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 11; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR8<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR3, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 26; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR0, %SGPR4<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 27; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR1<def> = V_ADD_F32_e32 %SGPR4<kill>, %VGPR1<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 21; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR5, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 20; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR4, %SGPR4<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 22; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR0, %SGPR4<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 23; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR2<def> = V_ADD_F32_e32 %SGPR4<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 17; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR5, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 16; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR4, %SGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 18; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %VGPR0, %SGPR4<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 19; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR3<def> = V_ADD_F32_e32 %SGPR4<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 13; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR5<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 12; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %VGPR4<kill>, %SGPR4<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 14; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR0<def> = V_MAD_F32 %VGPR0<kill>, %SGPR4<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 15; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR0<def> = V_ADD_F32_e32 %SGPR0<kill>, %VGPR0<kill>, %EXEC<imp-use>
	EXP 15, 12, 0, 1, 0, %VGPR0<kill>, %VGPR3<kill>, %VGPR2<kill>, %VGPR1<kill>, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_LOAD_DWORDX4 s[4:7], s[6:7], 0               ; C0820700
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	BUFFER_LOAD_FORMAT_XYZW v[0:3], s[4:7][v0] + 0 ; E00C2000 80010000
	S_LOAD_DWORDX4 s[0:3], s[0:1], 0               ; C0800100
	S_WAITCNT vmcnt(0) lgkmcnt(0)                  ; BF8C0070
	S_BUFFER_LOAD_DWORD s4, s[0:3], 1              ; C2020101
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v4, s4                           ; 7E080204
	V_MUL_F32_e64 v4, v1, v4, 0, 0, 0, 0           ; D2100004 02020901
	S_BUFFER_LOAD_DWORD s4, s[0:3], 0              ; C2020100
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v5, s4                           ; 7E0A0204
	V_MAD_F32 v4, v0, v5, v4, 0, 0, 0, 0           ; D2820004 04120B00
	S_BUFFER_LOAD_DWORD s4, s[0:3], 2              ; C2020102
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v5, s4                           ; 7E0A0204
	V_MAD_F32 v4, v2, v5, v4, 0, 0, 0, 0           ; D2820004 04120B02
	S_BUFFER_LOAD_DWORD s4, s[0:3], 3              ; C2020103
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v5, s4                           ; 7E0A0204
	V_MAD_F32 v4, v3, v5, v4, 0, 0, 0, 0           ; D2820004 04120B03
	S_BUFFER_LOAD_DWORD s4, s[0:3], 5              ; C2020105
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v5, s4                           ; 7E0A0204
	V_MUL_F32_e64 v5, v1, v5, 0, 0, 0, 0           ; D2100005 02020B01
	S_BUFFER_LOAD_DWORD s4, s[0:3], 4              ; C2020104
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v6, s4                           ; 7E0C0204
	V_MAD_F32 v5, v0, v6, v5, 0, 0, 0, 0           ; D2820005 04160D00
	S_BUFFER_LOAD_DWORD s4, s[0:3], 6              ; C2020106
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v6, s4                           ; 7E0C0204
	V_MAD_F32 v5, v2, v6, v5, 0, 0, 0, 0           ; D2820005 04160D02
	S_BUFFER_LOAD_DWORD s4, s[0:3], 7              ; C2020107
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v6, s4                           ; 7E0C0204
	V_MAD_F32 v5, v3, v6, v5, 0, 0, 0, 0           ; D2820005 04160D03
	S_BUFFER_LOAD_DWORD s4, s[0:3], 25             ; C2020119
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MUL_F32_e32 v6, s4, v5                       ; 100C0A04
	S_BUFFER_LOAD_DWORD s4, s[0:3], 24             ; C2020118
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MAD_F32 v6, v4, s4, v6, 0, 0, 0, 0           ; D2820006 04180904
	S_BUFFER_LOAD_DWORD s4, s[0:3], 9              ; C2020109
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v7, s4                           ; 7E0E0204
	V_MUL_F32_e64 v7, v1, v7, 0, 0, 0, 0           ; D2100007 02020F01
	S_BUFFER_LOAD_DWORD s4, s[0:3], 8              ; C2020108
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v8, s4                           ; 7E100204
	V_MAD_F32 v7, v0, v8, v7, 0, 0, 0, 0           ; D2820007 041E1100
	S_BUFFER_LOAD_DWORD s4, s[0:3], 10             ; C202010A
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v8, s4                           ; 7E100204
	V_MAD_F32 v7, v2, v8, v7, 0, 0, 0, 0           ; D2820007 041E1102
	S_BUFFER_LOAD_DWORD s4, s[0:3], 11             ; C202010B
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v8, s4                           ; 7E100204
	V_MAD_F32 v0, v3, v8, v7, 0, 0, 0, 0           ; D2820000 041E1103
	S_BUFFER_LOAD_DWORD s4, s[0:3], 26             ; C202011A
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MAD_F32 v1, v0, s4, v6, 0, 0, 0, 0           ; D2820001 04180900
	S_BUFFER_LOAD_DWORD s4, s[0:3], 27             ; C202011B
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_ADD_F32_e32 v1, s4, v1                       ; 06020204
	S_BUFFER_LOAD_DWORD s4, s[0:3], 21             ; C2020115
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MUL_F32_e32 v2, s4, v5                       ; 10040A04
	S_BUFFER_LOAD_DWORD s4, s[0:3], 20             ; C2020114
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MAD_F32 v2, v4, s4, v2, 0, 0, 0, 0           ; D2820002 04080904
	S_BUFFER_LOAD_DWORD s4, s[0:3], 22             ; C2020116
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MAD_F32 v2, v0, s4, v2, 0, 0, 0, 0           ; D2820002 04080900
	S_BUFFER_LOAD_DWORD s4, s[0:3], 23             ; C2020117
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_ADD_F32_e32 v2, s4, v2                       ; 06040404
	S_BUFFER_LOAD_DWORD s4, s[0:3], 17             ; C2020111
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MUL_F32_e32 v3, s4, v5                       ; 10060A04
	S_BUFFER_LOAD_DWORD s4, s[0:3], 16             ; C2020110
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MAD_F32 v3, v4, s4, v3, 0, 0, 0, 0           ; D2820003 040C0904
	S_BUFFER_LOAD_DWORD s4, s[0:3], 18             ; C2020112
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MAD_F32 v3, v0, s4, v3, 0, 0, 0, 0           ; D2820003 040C0900
	S_BUFFER_LOAD_DWORD s4, s[0:3], 19             ; C2020113
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_ADD_F32_e32 v3, s4, v3                       ; 06060604
	S_BUFFER_LOAD_DWORD s4, s[0:3], 13             ; C202010D
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MUL_F32_e32 v5, s4, v5                       ; 100A0A04
	S_BUFFER_LOAD_DWORD s4, s[0:3], 12             ; C202010C
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MAD_F32 v4, v4, s4, v5, 0, 0, 0, 0           ; D2820004 04140904
	S_BUFFER_LOAD_DWORD s4, s[0:3], 14             ; C202010E
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MAD_F32 v0, v0, s4, v4, 0, 0, 0, 0           ; D2820000 04100900
	S_BUFFER_LOAD_DWORD s0, s[0:3], 15             ; C200010F
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_ADD_F32_e32 v0, s0, v0                       ; 06000000
	EXP 15, 12, 0, 1, 0, v0, v3, v2, v1            ; F80008CF 01020300
	S_ENDPGM                                       ; BF810000

FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL SAMP[1]
DCL CONST[0..223]
DCL TEMP[0..26], LOCAL
IMM[0] FLT32 {    0.0000,     0.5000,     0.9500,    -1.0000}
IMM[1] FLT32 {    2.0000,    -2.0000,    -1.0000,     1.0000}
IMM[2] FLT32 {    0.2500,     0.5000,    -0.5000,     4.0000}
IMM[3] FLT32 {    0.0000,     1.0000,     2.0000,     3.0000}
IMM[4] INT32 {1, -1, 0, 0}
IMM[5] FLT32 {   16.0000,     0.0000,     0.0000,     0.0000}
  0: MOV TEMP[0].x, IMM[0].xxxx
  1: MAD TEMP[1].xy, IN[0].xyyy, CONST[4].xyyy, IMM[0].yyyy
  2: FRC TEMP[2].xy, TEMP[1].xyyy
  3: ADD TEMP[1].xy, TEMP[1].xyyy, -TEMP[2].xyyy
  4: ADD TEMP[1].xy, TEMP[1].xyyy, IMM[0].yyyy
  5: MUL TEMP[1].xy, TEMP[1].xyyy, CONST[4].zwww
  6: MOV TEMP[2].xy, TEMP[1].xyyy
  7: TEX TEMP[2].x, TEMP[2], SAMP[0], 2D
  8: ABS TEMP[3].x, TEMP[2].xxxx
  9: MAD TEMP[3].x, TEMP[3].xxxx, CONST[1].yyyy, -CONST[1].xxxx
 10: FSLT TEMP[4].x, TEMP[2].xxxx, IMM[0].zzzz
 11: UIF TEMP[4].xxxx :0
 12:   MOV TEMP[4].z, TEMP[3].xxxx
 13:   MAD TEMP[4].xy, TEMP[1].xyyy, IMM[1].xyyy, IMM[1].zwww
 14:   ADD TEMP[5].xy, TEMP[4].xyyy, CONST[2].ywww
 15:   MUL TEMP[5].xy, -TEMP[3].xxxx, TEMP[5].xyyy
 16:   RCP TEMP[6].x, CONST[2].xxxx
 17:   RCP TEMP[6].y, CONST[2].zzzz
 18:   MUL TEMP[4].xy, TEMP[5].xyyy, TEMP[6].xyyy
 19:   MOV TEMP[5].y, IMM[0].xxxx
 20:   MOV TEMP[5].x, -CONST[4].zzzz
 21:   MOV TEMP[5].z, CONST[4].zzzz
 22:   ADD TEMP[5].xyz, TEMP[1].xyxx, TEMP[5].xyzz
 23:   MOV TEMP[6].x, IMM[0].xxxx
 24:   MOV TEMP[6].y, -CONST[4].wwww
 25:   MOV TEMP[6].z, CONST[4].wwww
 26:   ADD TEMP[6].xyz, TEMP[1].xyyy, TEMP[6].xyzz
 27:   MOV TEMP[7].xy, TEMP[5].xyyy
 28:   TEX TEMP[7].x, TEMP[7], SAMP[0], 2D
 29:   MOV TEMP[7].x, TEMP[7].xxxx
 30:   MOV TEMP[8].xy, TEMP[5].zyyy
 31:   TEX TEMP[8].x, TEMP[8], SAMP[0], 2D
 32:   MOV TEMP[7].y, TEMP[8].xxxx
 33:   MOV TEMP[8].xy, TEMP[6].xyyy
 34:   TEX TEMP[8].x, TEMP[8], SAMP[0], 2D
 35:   MOV TEMP[7].z, TEMP[8].xxxx
 36:   MOV TEMP[8].xy, TEMP[6].xzzz
 37:   TEX TEMP[8].x, TEMP[8], SAMP[0], 2D
 38:   MOV TEMP[7].w, TEMP[8].xxxx
 39:   ABS TEMP[7], TEMP[7]
 40:   MAD TEMP[7], TEMP[7], CONST[1].yyyy, -CONST[1].xxxx
 41:   ADD TEMP[8], TEMP[7], -TEMP[3].xxxx
 42:   ABS TEMP[8], TEMP[8]
 43:   MOV TEMP[9].w, IMM[0].wwww
 44:   MOV TEMP[9].xy, TEMP[5].xyxx
 45:   MOV TEMP[9].z, TEMP[7].xxxx
 46:   MOV TEMP[10].w, IMM[1].wwww
 47:   MOV TEMP[10].xy, TEMP[5].zyzz
 48:   MOV TEMP[10].z, TEMP[7].yyyy
 49:   MOV TEMP[5].w, IMM[0].wwww
 50:   MOV TEMP[5].xy, TEMP[6].xyxx
 51:   MOV TEMP[5].z, TEMP[7].zzzz
 52:   MOV TEMP[11].w, IMM[1].wwww
 53:   MOV TEMP[11].xy, TEMP[6].xzxx
 54:   MOV TEMP[11].z, TEMP[7].wwww
 55:   FSLT TEMP[6].x, TEMP[8].xxxx, TEMP[8].yyyy
 56:   UIF TEMP[6].xxxx :0
 57:     MOV TEMP[6], TEMP[9]
 58:   ELSE :0
 59:     MOV TEMP[6], TEMP[10]
 60:   ENDIF
 61:   FSLT TEMP[7].x, TEMP[8].zzzz, TEMP[8].wwww
 62:   UIF TEMP[7].xxxx :0
 63:     MOV TEMP[5], TEMP[5]
 64:   ELSE :0
 65:     MOV TEMP[5], TEMP[11]
 66:   ENDIF
 67:   MOV TEMP[7].z, TEMP[6].zzzz
 68:   MAD TEMP[7].xy, TEMP[6].xyyy, IMM[1].xyyy, IMM[1].zwww
 69:   ADD TEMP[8].xy, TEMP[7].xyyy, CONST[2].ywww
 70:   MUL TEMP[8].xy, -TEMP[6].zzzz, TEMP[8].xyyy
 71:   RCP TEMP[9].x, CONST[2].xxxx
 72:   RCP TEMP[9].y, CONST[2].zzzz
 73:   MUL TEMP[7].xy, TEMP[8].xyyy, TEMP[9].xyyy
 74:   MOV TEMP[8].z, TEMP[5].zzzz
 75:   MAD TEMP[8].xy, TEMP[5].xyyy, IMM[1].xyyy, IMM[1].zwww
 76:   ADD TEMP[9].xy, TEMP[8].xyyy, CONST[2].ywww
 77:   MUL TEMP[9].xy, -TEMP[5].zzzz, TEMP[9].xyyy
 78:   RCP TEMP[10].x, CONST[2].xxxx
 79:   RCP TEMP[10].y, CONST[2].zzzz
 80:   MUL TEMP[8].xy, TEMP[9].xyyy, TEMP[10].xyyy
 81:   MOV TEMP[9].xyz, -TEMP[4].xyzx
 82:   ADD TEMP[7].xyz, TEMP[7].xyzz, TEMP[9].xyzz
 83:   MUL TEMP[6].xyz, TEMP[7].xyzz, TEMP[6].wwww
 84:   ADD TEMP[7].xyz, TEMP[8].xyzz, TEMP[9].xyzz
 85:   MUL TEMP[5].xyz, TEMP[7].xyzz, TEMP[5].wwww
 86:   MUL TEMP[7].xyz, TEMP[5].zxyy, TEMP[6].yzxx
 87:   MAD TEMP[5].xyz, TEMP[5].yzxx, TEMP[6].zxyy, -TEMP[7].xyzz
 88:   DP3 TEMP[6].x, TEMP[5].xyzz, TEMP[5].xyzz
 89:   RSQ TEMP[6].x, TEMP[6].xxxx
 90:   MUL TEMP[5].xyz, TEMP[5].xyzz, TEMP[6].xxxx
 91:   MUL TEMP[6].xyz, TEMP[5].xyzz, TEMP[3].xxxx
 92:   MUL TEMP[6].xyz, TEMP[6].xyzz, CONST[0].zzzz
 93:   ADD TEMP[4].xyz, TEMP[4].xyzz, -TEMP[6].xyzz
 94:   MUL TEMP[6].xy, CONST[3].xyyy, IMM[2].xxxx
 95:   MUL TEMP[1].xy, TEMP[1].xyyy, TEMP[6].xyyy
 96:   MOV TEMP[1].xy, TEMP[1].xyyy
 97:   TEX TEMP[1].xyz, TEMP[1], SAMP[1], 2D
 98:   MAD TEMP[1].xyz, TEMP[1].xyzz, IMM[1].xxxx, IMM[0].wwww
 99:   MUL TEMP[1].xyz, TEMP[1].xyzz, CONST[0].wwww
100:   ADD TEMP[6].x, -TEMP[3].xxxx, -CONST[5].xxxx
101:   MUL_SAT TEMP[6].x, TEMP[6].xxxx, CONST[5].wwww
102:   MAD TEMP[6].x, CONST[5].zzzz, TEMP[6].xxxx, IMM[1].wwww
103:   MUL_SAT TEMP[3].x, -TEMP[3].xxxx, CONST[5].yyyy
104:   MUL TEMP[3].x, TEMP[6].xxxx, TEMP[3].xxxx
105:   FSLT TEMP[6].x, TEMP[2].xxxx, IMM[0].xxxx
106:   UIF TEMP[6].xxxx :0
107:     MOV TEMP[6].x, CONST[6].xxxx
108:   ELSE :0
109:     MOV TEMP[6].x, TEMP[3].xxxx
110:   ENDIF
111:   MUL TEMP[3].x, TEMP[6].xxxx, CONST[6].zzzz
112:   MUL TEMP[6].x, CONST[0].yyyy, TEMP[3].xxxx
113:   FSGE TEMP[7].x, TEMP[2].xxxx, IMM[0].xxxx
114:   AND TEMP[7].x, TEMP[7].xxxx, IMM[1].wwww
115:   MUL TEMP[8], TEMP[6].xxxx, IMM[3]
116:   MAD TEMP[3], CONST[0].xxxx, TEMP[3].xxxx, -TEMP[8]
117:   DP3 TEMP[8].x, TEMP[1].xyzz, CONST[7].xyzz
118:   MUL TEMP[8].xyz, TEMP[8].xxxx, TEMP[1].xyzz
119:   MUL TEMP[8].xyz, IMM[1].xxxx, TEMP[8].xyzz
120:   ADD TEMP[8].xyz, CONST[7].xyzz, -TEMP[8].xyzz
121:   MUL TEMP[8].xyz, TEMP[8].xyzz, TEMP[3].xxxx
122:   DP3 TEMP[9].x, TEMP[1].xyzz, CONST[8].xyzz
123:   MUL TEMP[9].xyz, TEMP[9].xxxx, TEMP[1].xyzz
124:   MUL TEMP[9].xyz, IMM[1].xxxx, TEMP[9].xyzz
125:   ADD TEMP[9].xyz, CONST[8].xyzz, -TEMP[9].xyzz
126:   MUL TEMP[9].xyz, TEMP[9].xyzz, TEMP[3].yyyy
127:   DP3 TEMP[10].x, TEMP[1].xyzz, CONST[9].xyzz
128:   MUL TEMP[10].xyz, TEMP[10].xxxx, TEMP[1].xyzz
129:   MUL TEMP[10].xyz, IMM[1].xxxx, TEMP[10].xyzz
130:   ADD TEMP[10].xyz, CONST[9].xyzz, -TEMP[10].xyzz
131:   MUL TEMP[10].xyz, TEMP[10].xyzz, TEMP[3].zzzz
132:   DP3 TEMP[11].x, TEMP[1].xyzz, CONST[10].xyzz
133:   MUL TEMP[11].xyz, TEMP[11].xxxx, TEMP[1].xyzz
134:   MUL TEMP[11].xyz, IMM[1].xxxx, TEMP[11].xyzz
135:   ADD TEMP[11].xyz, CONST[10].xyzz, -TEMP[11].xyzz
136:   MUL TEMP[11].xyz, TEMP[11].xyzz, TEMP[3].wwww
137:   DP3 TEMP[12].x, TEMP[8].xyzz, TEMP[5].xyzz
138:   DP3 TEMP[13].x, TEMP[9].xyzz, TEMP[5].xyzz
139:   DP3 TEMP[14].x, TEMP[10].xyzz, TEMP[5].xyzz
140:   DP3 TEMP[15].x, TEMP[11].xyzz, TEMP[5].xyzz
141:   FSGE TEMP[12].x, TEMP[12].xxxx, IMM[0].xxxx
142:   UIF TEMP[12].xxxx :0
143:     MOV TEMP[12].x, IMM[4].xxxx
144:   ELSE :0
145:     MOV TEMP[12].x, IMM[4].yyyy
146:   ENDIF
147:   I2F TEMP[12].x, TEMP[12].xxxx
148:   MUL TEMP[8].xyz, TEMP[8].xyzz, TEMP[12].xxxx
149:   FSGE TEMP[12].x, TEMP[13].xxxx, IMM[0].xxxx
150:   UIF TEMP[12].xxxx :0
151:     MOV TEMP[12].x, IMM[4].xxxx
152:   ELSE :0
153:     MOV TEMP[12].x, IMM[4].yyyy
154:   ENDIF
155:   I2F TEMP[12].x, TEMP[12].xxxx
156:   MUL TEMP[9].xyz, TEMP[9].xyzz, TEMP[12].xxxx
157:   FSGE TEMP[12].x, TEMP[14].xxxx, IMM[0].xxxx
158:   UIF TEMP[12].xxxx :0
159:     MOV TEMP[12].x, IMM[4].xxxx
160:   ELSE :0
161:     MOV TEMP[12].x, IMM[4].yyyy
162:   ENDIF
163:   I2F TEMP[12].x, TEMP[12].xxxx
164:   MUL TEMP[10].xyz, TEMP[10].xyzz, TEMP[12].xxxx
165:   FSGE TEMP[12].x, TEMP[15].xxxx, IMM[0].xxxx
166:   UIF TEMP[12].xxxx :0
167:     MOV TEMP[12].x, IMM[4].xxxx
168:   ELSE :0
169:     MOV TEMP[12].x, IMM[4].yyyy
170:   ENDIF
171:   I2F TEMP[12].x, TEMP[12].xxxx
172:   MUL TEMP[11].xyz, TEMP[11].xyzz, TEMP[12].xxxx
173:   ADD TEMP[12].xy, TEMP[4].xyyy, TEMP[8].xyyy
174:   ADD TEMP[13].xy, TEMP[4].xyyy, TEMP[9].xyyy
175:   MOV TEMP[12].zw, TEMP[13].yyxy
176:   ADD TEMP[13].xy, TEMP[4].xyyy, TEMP[10].xyyy
177:   ADD TEMP[14].xy, TEMP[4].xyyy, TEMP[11].xyyy
178:   MOV TEMP[13].zw, TEMP[14].yyxy
179:   ADD TEMP[14].x, TEMP[4].zzzz, TEMP[8].zzzz
180:   ADD TEMP[15].x, TEMP[4].zzzz, TEMP[9].zzzz
181:   MOV TEMP[14].y, TEMP[15].xxxx
182:   ADD TEMP[16].x, TEMP[4].zzzz, TEMP[10].zzzz
183:   MOV TEMP[14].z, TEMP[16].xxxx
184:   ADD TEMP[17].x, TEMP[4].zzzz, TEMP[11].zzzz
185:   MOV TEMP[14].w, TEMP[17].xxxx
186:   RCP TEMP[18].xy, -TEMP[14].xxxx
187:   RCP TEMP[18].zw, -TEMP[15].xxxx
188:   MUL TEMP[15], TEMP[12], TEMP[18]
189:   MAD TEMP[15], TEMP[15], CONST[2].xzxz, -CONST[2].ywyw
190:   RCP TEMP[16].xy, -TEMP[16].xxxx
191:   RCP TEMP[16].zw, -TEMP[17].xxxx
192:   MUL TEMP[16], TEMP[13], TEMP[16]
193:   MAD TEMP[16], TEMP[16], CONST[2].xzxz, -CONST[2].ywyw
194:   MAD TEMP[15], TEMP[15], IMM[2].yzyz, IMM[0].yyyy
195:   MAD TEMP[16], TEMP[16], IMM[2].yzyz, IMM[0].yyyy
196:   MOV_SAT TEMP[17], TEMP[15]
197:   MOV_SAT TEMP[18], TEMP[16]
198:   MOV TEMP[19].xy, TEMP[17].xyyy
199:   TEX TEMP[19].x, TEMP[19], SAMP[0], 2D
200:   MOV TEMP[20].x, TEMP[19].xxxx
201:   MOV TEMP[17].xy, TEMP[17].zwww
202:   TEX TEMP[17].x, TEMP[17], SAMP[0], 2D
203:   MOV TEMP[20].y, TEMP[17].xxxx
204:   MOV TEMP[21].xy, TEMP[18].xyyy
205:   TEX TEMP[21].x, TEMP[21], SAMP[0], 2D
206:   MOV TEMP[20].z, TEMP[21].xxxx
207:   MOV TEMP[18].xy, TEMP[18].zwww
208:   TEX TEMP[18].x, TEMP[18], SAMP[0], 2D
209:   MOV TEMP[20].w, TEMP[18].xxxx
210:   ABS TEMP[20], TEMP[20]
211:   MAD TEMP[20], TEMP[20], CONST[1].yyyy, -CONST[1].xxxx
212:   ADD TEMP[22], TEMP[20], -TEMP[14]
213:   MUL TEMP[23], TEMP[3], IMM[1].xxxx
214:   FSGE TEMP[24].x, TEMP[22].xxxx, TEMP[23].xxxx
215:   AND TEMP[24].x, TEMP[24].xxxx, IMM[1].wwww
216:   FSGE TEMP[25].x, TEMP[22].yyyy, TEMP[23].yyyy
217:   AND TEMP[25].x, TEMP[25].xxxx, IMM[1].wwww
218:   MOV TEMP[24].y, TEMP[25].xxxx
219:   FSGE TEMP[25].x, TEMP[22].zzzz, TEMP[23].zzzz
220:   AND TEMP[25].x, TEMP[25].xxxx, IMM[1].wwww
221:   MOV TEMP[24].z, TEMP[25].xxxx
222:   FSGE TEMP[23].x, TEMP[22].wwww, TEMP[23].wwww
223:   AND TEMP[23].x, TEMP[23].xxxx, IMM[1].wwww
224:   MOV TEMP[24].w, TEMP[23].xxxx
225:   FSEQ TEMP[23].x, TEMP[20].xxxx, IMM[0].xxxx
226:   UIF TEMP[23].xxxx :0
227:     MOV TEMP[23].x, IMM[4].xxxx
228:   ELSE :0
229:     MOV TEMP[23].x, IMM[4].zzzz
230:   ENDIF
231:   FSEQ TEMP[25].x, TEMP[20].yyyy, IMM[0].xxxx
232:   UIF TEMP[25].xxxx :0
233:     MOV TEMP[25].x, IMM[4].xxxx
234:   ELSE :0
235:     MOV TEMP[25].x, IMM[4].zzzz
236:   ENDIF
237:   FSEQ TEMP[26].x, TEMP[20].zzzz, IMM[0].xxxx
238:   UIF TEMP[26].xxxx :0
239:     MOV TEMP[26].x, IMM[4].xxxx
240:   ELSE :0
241:     MOV TEMP[26].x, IMM[4].zzzz
242:   ENDIF
243:   FSEQ TEMP[20].x, TEMP[20].wwww, IMM[0].xxxx
244:   UIF TEMP[20].xxxx :0
245:     MOV TEMP[20].x, IMM[4].xxxx
246:   ELSE :0
247:     MOV TEMP[20].x, IMM[4].zzzz
248:   ENDIF
249:   I2F TEMP[23].x, TEMP[23].xxxx
250:   I2F TEMP[25].x, TEMP[25].xxxx
251:   MOV TEMP[23].y, TEMP[25].xxxx
252:   I2F TEMP[25].x, TEMP[26].xxxx
253:   MOV TEMP[23].z, TEMP[25].xxxx
254:   I2F TEMP[20].x, TEMP[20].xxxx
255:   MOV TEMP[23].w, TEMP[20].xxxx
256:   FSGE TEMP[19].x, IMM[0].xxxx, TEMP[19].xxxx
257:   AND TEMP[19].x, TEMP[19].xxxx, IMM[1].wwww
258:   FSGE TEMP[17].x, IMM[0].xxxx, TEMP[17].xxxx
259:   AND TEMP[17].x, TEMP[17].xxxx, IMM[1].wwww
260:   MOV TEMP[19].y, TEMP[17].xxxx
261:   FSGE TEMP[17].x, IMM[0].xxxx, TEMP[21].xxxx
262:   AND TEMP[17].x, TEMP[17].xxxx, IMM[1].wwww
263:   MOV TEMP[19].z, TEMP[17].xxxx
264:   FSGE TEMP[17].x, IMM[0].xxxx, TEMP[18].xxxx
265:   AND TEMP[17].x, TEMP[17].xxxx, IMM[1].wwww
266:   MOV TEMP[19].w, TEMP[17].xxxx
267:   ADD TEMP[17], TEMP[24], TEMP[23]
268:   MAD_SAT TEMP[17], TEMP[19], TEMP[7].xxxx, TEMP[17]
269:   DP4 TEMP[2].x, TEMP[17], IMM[1].wwww
270:   FSGE TEMP[18].x, TEMP[22].xxxx, IMM[0].xxxx
271:   AND TEMP[18].x, TEMP[18].xxxx, IMM[1].wwww
272:   FSGE TEMP[19].x, TEMP[22].yyyy, IMM[0].xxxx
273:   AND TEMP[19].x, TEMP[19].xxxx, IMM[1].wwww
274:   MOV TEMP[18].y, TEMP[19].xxxx
275:   FSGE TEMP[19].x, TEMP[22].zzzz, IMM[0].xxxx
276:   AND TEMP[19].x, TEMP[19].xxxx, IMM[1].wwww
277:   MOV TEMP[18].z, TEMP[19].xxxx
278:   FSGE TEMP[19].x, TEMP[22].wwww, IMM[0].xxxx
279:   AND TEMP[19].x, TEMP[19].xxxx, IMM[1].wwww
280:   MOV TEMP[18].w, TEMP[19].xxxx
281:   ADD TEMP[17], IMM[1].wwww, -TEMP[17]
282:   MUL TEMP[17], TEMP[18], TEMP[17]
283:   DP4 TEMP[0].x, TEMP[17], IMM[1].wwww
284:   MUL TEMP[17].x, TEMP[6].xxxx, IMM[2].wwww
285:   ADD TEMP[3], TEMP[3], -TEMP[17].xxxx
286:   DP3 TEMP[17].x, TEMP[1].xyzz, CONST[11].xyzz
287:   MUL TEMP[17].xyz, TEMP[17].xxxx, TEMP[1].xyzz
288:   MUL TEMP[17].xyz, IMM[1].xxxx, TEMP[17].xyzz
289:   ADD TEMP[17].xyz, CONST[11].xyzz, -TEMP[17].xyzz
290:   MUL TEMP[8].xyz, TEMP[17].xyzz, TEMP[3].xxxx
291:   DP3 TEMP[17].x, TEMP[1].xyzz, CONST[12].xyzz
292:   MUL TEMP[17].xyz, TEMP[17].xxxx, TEMP[1].xyzz
293:   MUL TEMP[17].xyz, IMM[1].xxxx, TEMP[17].xyzz
294:   ADD TEMP[17].xyz, CONST[12].xyzz, -TEMP[17].xyzz
295:   MUL TEMP[9].xyz, TEMP[17].xyzz, TEMP[3].yyyy
296:   DP3 TEMP[17].x, TEMP[1].xyzz, CONST[13].xyzz
297:   MUL TEMP[17].xyz, TEMP[17].xxxx, TEMP[1].xyzz
298:   MUL TEMP[17].xyz, IMM[1].xxxx, TEMP[17].xyzz
299:   ADD TEMP[17].xyz, CONST[13].xyzz, -TEMP[17].xyzz
300:   MUL TEMP[10].xyz, TEMP[17].xyzz, TEMP[3].zzzz
301:   DP3 TEMP[17].x, TEMP[1].xyzz, CONST[14].xyzz
302:   MUL TEMP[17].xyz, TEMP[17].xxxx, TEMP[1].xyzz
303:   MUL TEMP[17].xyz, IMM[1].xxxx, TEMP[17].xyzz
304:   ADD TEMP[17].xyz, CONST[14].xyzz, -TEMP[17].xyzz
305:   MUL TEMP[11].xyz, TEMP[17].xyzz, TEMP[3].wwww
306:   DP3 TEMP[17].x, TEMP[8].xyzz, TEMP[5].xyzz
307:   DP3 TEMP[18].x, TEMP[9].xyzz, TEMP[5].xyzz
308:   DP3 TEMP[19].x, TEMP[10].xyzz, TEMP[5].xyzz
309:   DP3 TEMP[20].x, TEMP[11].xyzz, TEMP[5].xyzz
310:   FSGE TEMP[17].x, TEMP[17].xxxx, IMM[0].xxxx
311:   UIF TEMP[17].xxxx :0
312:     MOV TEMP[17].x, IMM[4].xxxx
313:   ELSE :0
314:     MOV TEMP[17].x, IMM[4].yyyy
315:   ENDIF
316:   I2F TEMP[17].x, TEMP[17].xxxx
317:   MUL TEMP[8].xyz, TEMP[8].xyzz, TEMP[17].xxxx
318:   FSGE TEMP[17].x, TEMP[18].xxxx, IMM[0].xxxx
319:   UIF TEMP[17].xxxx :0
320:     MOV TEMP[17].x, IMM[4].xxxx
321:   ELSE :0
322:     MOV TEMP[17].x, IMM[4].yyyy
323:   ENDIF
324:   I2F TEMP[17].x, TEMP[17].xxxx
325:   MUL TEMP[9].xyz, TEMP[9].xyzz, TEMP[17].xxxx
326:   FSGE TEMP[17].x, TEMP[19].xxxx, IMM[0].xxxx
327:   UIF TEMP[17].xxxx :0
328:     MOV TEMP[17].x, IMM[4].xxxx
329:   ELSE :0
330:     MOV TEMP[17].x, IMM[4].yyyy
331:   ENDIF
332:   I2F TEMP[17].x, TEMP[17].xxxx
333:   MUL TEMP[10].xyz, TEMP[10].xyzz, TEMP[17].xxxx
334:   FSGE TEMP[17].x, TEMP[20].xxxx, IMM[0].xxxx
335:   UIF TEMP[17].xxxx :0
336:     MOV TEMP[17].x, IMM[4].xxxx
337:   ELSE :0
338:     MOV TEMP[17].x, IMM[4].yyyy
339:   ENDIF
340:   I2F TEMP[17].x, TEMP[17].xxxx
341:   MUL TEMP[11].xyz, TEMP[11].xyzz, TEMP[17].xxxx
342:   ADD TEMP[12].xy, TEMP[4].xyyy, TEMP[8].xyyy
343:   ADD TEMP[17].xy, TEMP[4].xyyy, TEMP[9].xyyy
344:   MOV TEMP[12].zw, TEMP[17].yyxy
345:   ADD TEMP[13].xy, TEMP[4].xyyy, TEMP[10].xyyy
346:   ADD TEMP[17].xy, TEMP[4].xyyy, TEMP[11].xyyy
347:   MOV TEMP[13].zw, TEMP[17].yyxy
348:   ADD TEMP[14].x, TEMP[4].zzzz, TEMP[8].zzzz
349:   ADD TEMP[17].x, TEMP[4].zzzz, TEMP[9].zzzz
350:   MOV TEMP[14].y, TEMP[17].xxxx
351:   ADD TEMP[18].x, TEMP[4].zzzz, TEMP[10].zzzz
352:   MOV TEMP[14].z, TEMP[18].xxxx
353:   ADD TEMP[19].x, TEMP[4].zzzz, TEMP[11].zzzz
354:   MOV TEMP[14].w, TEMP[19].xxxx
355:   RCP TEMP[20].xy, -TEMP[14].xxxx
356:   RCP TEMP[20].zw, -TEMP[17].xxxx
357:   MUL TEMP[17], TEMP[12], TEMP[20]
358:   MAD TEMP[15], TEMP[17], CONST[2].xzxz, -CONST[2].ywyw
359:   RCP TEMP[17].xy, -TEMP[18].xxxx
360:   RCP TEMP[17].zw, -TEMP[19].xxxx
361:   MUL TEMP[17], TEMP[13], TEMP[17]
362:   MAD TEMP[16], TEMP[17], CONST[2].xzxz, -CONST[2].ywyw
363:   MAD TEMP[15], TEMP[15], IMM[2].yzyz, IMM[0].yyyy
364:   MAD TEMP[16], TEMP[16], IMM[2].yzyz, IMM[0].yyyy
365:   MOV_SAT TEMP[17], TEMP[15]
366:   MOV_SAT TEMP[18], TEMP[16]
367:   MOV TEMP[19].xy, TEMP[17].xyyy
368:   TEX TEMP[19].x, TEMP[19], SAMP[0], 2D
369:   MOV TEMP[20].x, TEMP[19].xxxx
370:   MOV TEMP[17].xy, TEMP[17].zwww
371:   TEX TEMP[17].x, TEMP[17], SAMP[0], 2D
372:   MOV TEMP[20].y, TEMP[17].xxxx
373:   MOV TEMP[21].xy, TEMP[18].xyyy
374:   TEX TEMP[21].x, TEMP[21], SAMP[0], 2D
375:   MOV TEMP[20].z, TEMP[21].xxxx
376:   MOV TEMP[18].xy, TEMP[18].zwww
377:   TEX TEMP[18].x, TEMP[18], SAMP[0], 2D
378:   MOV TEMP[20].w, TEMP[18].xxxx
379:   ABS TEMP[20], TEMP[20]
380:   MAD TEMP[20], TEMP[20], CONST[1].yyyy, -CONST[1].xxxx
381:   ADD TEMP[22], TEMP[20], -TEMP[14]
382:   MUL TEMP[23], TEMP[3], IMM[1].xxxx
383:   FSGE TEMP[24].x, TEMP[22].xxxx, TEMP[23].xxxx
384:   AND TEMP[24].x, TEMP[24].xxxx, IMM[1].wwww
385:   FSGE TEMP[25].x, TEMP[22].yyyy, TEMP[23].yyyy
386:   AND TEMP[25].x, TEMP[25].xxxx, IMM[1].wwww
387:   MOV TEMP[24].y, TEMP[25].xxxx
388:   FSGE TEMP[25].x, TEMP[22].zzzz, TEMP[23].zzzz
389:   AND TEMP[25].x, TEMP[25].xxxx, IMM[1].wwww
390:   MOV TEMP[24].z, TEMP[25].xxxx
391:   FSGE TEMP[23].x, TEMP[22].wwww, TEMP[23].wwww
392:   AND TEMP[23].x, TEMP[23].xxxx, IMM[1].wwww
393:   MOV TEMP[24].w, TEMP[23].xxxx
394:   FSEQ TEMP[23].x, TEMP[20].xxxx, IMM[0].xxxx
395:   UIF TEMP[23].xxxx :0
396:     MOV TEMP[23].x, IMM[4].xxxx
397:   ELSE :0
398:     MOV TEMP[23].x, IMM[4].zzzz
399:   ENDIF
400:   FSEQ TEMP[25].x, TEMP[20].yyyy, IMM[0].xxxx
401:   UIF TEMP[25].xxxx :0
402:     MOV TEMP[25].x, IMM[4].xxxx
403:   ELSE :0
404:     MOV TEMP[25].x, IMM[4].zzzz
405:   ENDIF
406:   FSEQ TEMP[26].x, TEMP[20].zzzz, IMM[0].xxxx
407:   UIF TEMP[26].xxxx :0
408:     MOV TEMP[26].x, IMM[4].xxxx
409:   ELSE :0
410:     MOV TEMP[26].x, IMM[4].zzzz
411:   ENDIF
412:   FSEQ TEMP[20].x, TEMP[20].wwww, IMM[0].xxxx
413:   UIF TEMP[20].xxxx :0
414:     MOV TEMP[20].x, IMM[4].xxxx
415:   ELSE :0
416:     MOV TEMP[20].x, IMM[4].zzzz
417:   ENDIF
418:   I2F TEMP[23].x, TEMP[23].xxxx
419:   I2F TEMP[25].x, TEMP[25].xxxx
420:   MOV TEMP[23].y, TEMP[25].xxxx
421:   I2F TEMP[25].x, TEMP[26].xxxx
422:   MOV TEMP[23].z, TEMP[25].xxxx
423:   I2F TEMP[20].x, TEMP[20].xxxx
424:   MOV TEMP[23].w, TEMP[20].xxxx
425:   FSGE TEMP[19].x, IMM[0].xxxx, TEMP[19].xxxx
426:   AND TEMP[19].x, TEMP[19].xxxx, IMM[1].wwww
427:   FSGE TEMP[17].x, IMM[0].xxxx, TEMP[17].xxxx
428:   AND TEMP[17].x, TEMP[17].xxxx, IMM[1].wwww
429:   MOV TEMP[19].y, TEMP[17].xxxx
430:   FSGE TEMP[17].x, IMM[0].xxxx, TEMP[21].xxxx
431:   AND TEMP[17].x, TEMP[17].xxxx, IMM[1].wwww
432:   MOV TEMP[19].z, TEMP[17].xxxx
433:   FSGE TEMP[17].x, IMM[0].xxxx, TEMP[18].xxxx
434:   AND TEMP[17].x, TEMP[17].xxxx, IMM[1].wwww
435:   MOV TEMP[19].w, TEMP[17].xxxx
436:   ADD TEMP[17], TEMP[24], TEMP[23]
437:   MAD_SAT TEMP[17], TEMP[19], TEMP[7].xxxx, TEMP[17]
438:   DP4 TEMP[18].x, TEMP[17], IMM[1].wwww
439:   ADD TEMP[2].x, TEMP[2].xxxx, TEMP[18].xxxx
440:   FSGE TEMP[18].x, TEMP[22].xxxx, IMM[0].xxxx
441:   AND TEMP[18].x, TEMP[18].xxxx, IMM[1].wwww
442:   FSGE TEMP[19].x, TEMP[22].yyyy, IMM[0].xxxx
443:   AND TEMP[19].x, TEMP[19].xxxx, IMM[1].wwww
444:   MOV TEMP[18].y, TEMP[19].xxxx
445:   FSGE TEMP[19].x, TEMP[22].zzzz, IMM[0].xxxx
446:   AND TEMP[19].x, TEMP[19].xxxx, IMM[1].wwww
447:   MOV TEMP[18].z, TEMP[19].xxxx
448:   FSGE TEMP[19].x, TEMP[22].wwww, IMM[0].xxxx
449:   AND TEMP[19].x, TEMP[19].xxxx, IMM[1].wwww
450:   MOV TEMP[18].w, TEMP[19].xxxx
451:   ADD TEMP[17], IMM[1].wwww, -TEMP[17]
452:   MUL TEMP[17], TEMP[18], TEMP[17]
453:   DP4 TEMP[17].x, TEMP[17], IMM[1].wwww
454:   ADD TEMP[0].x, TEMP[0].xxxx, TEMP[17].xxxx
455:   MUL TEMP[17].x, TEMP[6].xxxx, IMM[2].wwww
456:   ADD TEMP[3], TEMP[3], -TEMP[17].xxxx
457:   DP3 TEMP[17].x, TEMP[1].xyzz, CONST[15].xyzz
458:   MUL TEMP[17].xyz, TEMP[17].xxxx, TEMP[1].xyzz
459:   MUL TEMP[17].xyz, IMM[1].xxxx, TEMP[17].xyzz
460:   ADD TEMP[17].xyz, CONST[15].xyzz, -TEMP[17].xyzz
461:   MUL TEMP[8].xyz, TEMP[17].xyzz, TEMP[3].xxxx
462:   DP3 TEMP[17].x, TEMP[1].xyzz, CONST[16].xyzz
463:   MUL TEMP[17].xyz, TEMP[17].xxxx, TEMP[1].xyzz
464:   MUL TEMP[17].xyz, IMM[1].xxxx, TEMP[17].xyzz
465:   ADD TEMP[17].xyz, CONST[16].xyzz, -TEMP[17].xyzz
466:   MUL TEMP[9].xyz, TEMP[17].xyzz, TEMP[3].yyyy
467:   DP3 TEMP[17].x, TEMP[1].xyzz, CONST[17].xyzz
468:   MUL TEMP[17].xyz, TEMP[17].xxxx, TEMP[1].xyzz
469:   MUL TEMP[17].xyz, IMM[1].xxxx, TEMP[17].xyzz
470:   ADD TEMP[17].xyz, CONST[17].xyzz, -TEMP[17].xyzz
471:   MUL TEMP[10].xyz, TEMP[17].xyzz, TEMP[3].zzzz
472:   DP3 TEMP[17].x, TEMP[1].xyzz, CONST[18].xyzz
473:   MUL TEMP[17].xyz, TEMP[17].xxxx, TEMP[1].xyzz
474:   MUL TEMP[17].xyz, IMM[1].xxxx, TEMP[17].xyzz
475:   ADD TEMP[17].xyz, CONST[18].xyzz, -TEMP[17].xyzz
476:   MUL TEMP[11].xyz, TEMP[17].xyzz, TEMP[3].wwww
477:   DP3 TEMP[17].x, TEMP[8].xyzz, TEMP[5].xyzz
478:   DP3 TEMP[18].x, TEMP[9].xyzz, TEMP[5].xyzz
479:   DP3 TEMP[19].x, TEMP[10].xyzz, TEMP[5].xyzz
480:   DP3 TEMP[20].x, TEMP[11].xyzz, TEMP[5].xyzz
481:   FSGE TEMP[17].x, TEMP[17].xxxx, IMM[0].xxxx
482:   UIF TEMP[17].xxxx :0
483:     MOV TEMP[17].x, IMM[4].xxxx
484:   ELSE :0
485:     MOV TEMP[17].x, IMM[4].yyyy
486:   ENDIF
487:   I2F TEMP[17].x, TEMP[17].xxxx
488:   MUL TEMP[8].xyz, TEMP[8].xyzz, TEMP[17].xxxx
489:   FSGE TEMP[17].x, TEMP[18].xxxx, IMM[0].xxxx
490:   UIF TEMP[17].xxxx :0
491:     MOV TEMP[17].x, IMM[4].xxxx
492:   ELSE :0
493:     MOV TEMP[17].x, IMM[4].yyyy
494:   ENDIF
495:   I2F TEMP[17].x, TEMP[17].xxxx
496:   MUL TEMP[9].xyz, TEMP[9].xyzz, TEMP[17].xxxx
497:   FSGE TEMP[17].x, TEMP[19].xxxx, IMM[0].xxxx
498:   UIF TEMP[17].xxxx :0
499:     MOV TEMP[17].x, IMM[4].xxxx
500:   ELSE :0
501:     MOV TEMP[17].x, IMM[4].yyyy
502:   ENDIF
503:   I2F TEMP[17].x, TEMP[17].xxxx
504:   MUL TEMP[10].xyz, TEMP[10].xyzz, TEMP[17].xxxx
505:   FSGE TEMP[17].x, TEMP[20].xxxx, IMM[0].xxxx
506:   UIF TEMP[17].xxxx :0
507:     MOV TEMP[17].x, IMM[4].xxxx
508:   ELSE :0
509:     MOV TEMP[17].x, IMM[4].yyyy
510:   ENDIF
511:   I2F TEMP[17].x, TEMP[17].xxxx
512:   MUL TEMP[11].xyz, TEMP[11].xyzz, TEMP[17].xxxx
513:   ADD TEMP[12].xy, TEMP[4].xyyy, TEMP[8].xyyy
514:   ADD TEMP[17].xy, TEMP[4].xyyy, TEMP[9].xyyy
515:   MOV TEMP[12].zw, TEMP[17].yyxy
516:   ADD TEMP[13].xy, TEMP[4].xyyy, TEMP[10].xyyy
517:   ADD TEMP[17].xy, TEMP[4].xyyy, TEMP[11].xyyy
518:   MOV TEMP[13].zw, TEMP[17].yyxy
519:   ADD TEMP[14].x, TEMP[4].zzzz, TEMP[8].zzzz
520:   ADD TEMP[17].x, TEMP[4].zzzz, TEMP[9].zzzz
521:   MOV TEMP[14].y, TEMP[17].xxxx
522:   ADD TEMP[18].x, TEMP[4].zzzz, TEMP[10].zzzz
523:   MOV TEMP[14].z, TEMP[18].xxxx
524:   ADD TEMP[19].x, TEMP[4].zzzz, TEMP[11].zzzz
525:   MOV TEMP[14].w, TEMP[19].xxxx
526:   RCP TEMP[20].xy, -TEMP[14].xxxx
527:   RCP TEMP[20].zw, -TEMP[17].xxxx
528:   MUL TEMP[17], TEMP[12], TEMP[20]
529:   MAD TEMP[15], TEMP[17], CONST[2].xzxz, -CONST[2].ywyw
530:   RCP TEMP[17].xy, -TEMP[18].xxxx
531:   RCP TEMP[17].zw, -TEMP[19].xxxx
532:   MUL TEMP[17], TEMP[13], TEMP[17]
533:   MAD TEMP[16], TEMP[17], CONST[2].xzxz, -CONST[2].ywyw
534:   MAD TEMP[15], TEMP[15], IMM[2].yzyz, IMM[0].yyyy
535:   MAD TEMP[16], TEMP[16], IMM[2].yzyz, IMM[0].yyyy
536:   MOV_SAT TEMP[17], TEMP[15]
537:   MOV_SAT TEMP[18], TEMP[16]
538:   MOV TEMP[19].xy, TEMP[17].xyyy
539:   TEX TEMP[19].x, TEMP[19], SAMP[0], 2D
540:   MOV TEMP[20].x, TEMP[19].xxxx
541:   MOV TEMP[17].xy, TEMP[17].zwww
542:   TEX TEMP[17].x, TEMP[17], SAMP[0], 2D
543:   MOV TEMP[20].y, TEMP[17].xxxx
544:   MOV TEMP[21].xy, TEMP[18].xyyy
545:   TEX TEMP[21].x, TEMP[21], SAMP[0], 2D
546:   MOV TEMP[20].z, TEMP[21].xxxx
547:   MOV TEMP[18].xy, TEMP[18].zwww
548:   TEX TEMP[18].x, TEMP[18], SAMP[0], 2D
549:   MOV TEMP[20].w, TEMP[18].xxxx
550:   ABS TEMP[20], TEMP[20]
551:   MAD TEMP[20], TEMP[20], CONST[1].yyyy, -CONST[1].xxxx
552:   ADD TEMP[22], TEMP[20], -TEMP[14]
553:   MUL TEMP[23], TEMP[3], IMM[1].xxxx
554:   FSGE TEMP[24].x, TEMP[22].xxxx, TEMP[23].xxxx
555:   AND TEMP[24].x, TEMP[24].xxxx, IMM[1].wwww
556:   FSGE TEMP[25].x, TEMP[22].yyyy, TEMP[23].yyyy
557:   AND TEMP[25].x, TEMP[25].xxxx, IMM[1].wwww
558:   MOV TEMP[24].y, TEMP[25].xxxx
559:   FSGE TEMP[25].x, TEMP[22].zzzz, TEMP[23].zzzz
560:   AND TEMP[25].x, TEMP[25].xxxx, IMM[1].wwww
561:   MOV TEMP[24].z, TEMP[25].xxxx
562:   FSGE TEMP[23].x, TEMP[22].wwww, TEMP[23].wwww
563:   AND TEMP[23].x, TEMP[23].xxxx, IMM[1].wwww
564:   MOV TEMP[24].w, TEMP[23].xxxx
565:   FSEQ TEMP[23].x, TEMP[20].xxxx, IMM[0].xxxx
566:   UIF TEMP[23].xxxx :0
567:     MOV TEMP[23].x, IMM[4].xxxx
568:   ELSE :0
569:     MOV TEMP[23].x, IMM[4].zzzz
570:   ENDIF
571:   FSEQ TEMP[25].x, TEMP[20].yyyy, IMM[0].xxxx
572:   UIF TEMP[25].xxxx :0
573:     MOV TEMP[25].x, IMM[4].xxxx
574:   ELSE :0
575:     MOV TEMP[25].x, IMM[4].zzzz
576:   ENDIF
577:   FSEQ TEMP[26].x, TEMP[20].zzzz, IMM[0].xxxx
578:   UIF TEMP[26].xxxx :0
579:     MOV TEMP[26].x, IMM[4].xxxx
580:   ELSE :0
581:     MOV TEMP[26].x, IMM[4].zzzz
582:   ENDIF
583:   FSEQ TEMP[20].x, TEMP[20].wwww, IMM[0].xxxx
584:   UIF TEMP[20].xxxx :0
585:     MOV TEMP[20].x, IMM[4].xxxx
586:   ELSE :0
587:     MOV TEMP[20].x, IMM[4].zzzz
588:   ENDIF
589:   I2F TEMP[23].x, TEMP[23].xxxx
590:   I2F TEMP[25].x, TEMP[25].xxxx
591:   MOV TEMP[23].y, TEMP[25].xxxx
592:   I2F TEMP[25].x, TEMP[26].xxxx
593:   MOV TEMP[23].z, TEMP[25].xxxx
594:   I2F TEMP[20].x, TEMP[20].xxxx
595:   MOV TEMP[23].w, TEMP[20].xxxx
596:   FSGE TEMP[19].x, IMM[0].xxxx, TEMP[19].xxxx
597:   AND TEMP[19].x, TEMP[19].xxxx, IMM[1].wwww
598:   FSGE TEMP[17].x, IMM[0].xxxx, TEMP[17].xxxx
599:   AND TEMP[17].x, TEMP[17].xxxx, IMM[1].wwww
600:   MOV TEMP[19].y, TEMP[17].xxxx
601:   FSGE TEMP[17].x, IMM[0].xxxx, TEMP[21].xxxx
602:   AND TEMP[17].x, TEMP[17].xxxx, IMM[1].wwww
603:   MOV TEMP[19].z, TEMP[17].xxxx
604:   FSGE TEMP[17].x, IMM[0].xxxx, TEMP[18].xxxx
605:   AND TEMP[17].x, TEMP[17].xxxx, IMM[1].wwww
606:   MOV TEMP[19].w, TEMP[17].xxxx
607:   ADD TEMP[17], TEMP[24], TEMP[23]
608:   MAD_SAT TEMP[17], TEMP[19], TEMP[7].xxxx, TEMP[17]
609:   DP4 TEMP[18].x, TEMP[17], IMM[1].wwww
610:   ADD TEMP[2].x, TEMP[2].xxxx, TEMP[18].xxxx
611:   FSGE TEMP[18].x, TEMP[22].xxxx, IMM[0].xxxx
612:   AND TEMP[18].x, TEMP[18].xxxx, IMM[1].wwww
613:   FSGE TEMP[19].x, TEMP[22].yyyy, IMM[0].xxxx
614:   AND TEMP[19].x, TEMP[19].xxxx, IMM[1].wwww
615:   MOV TEMP[18].y, TEMP[19].xxxx
616:   FSGE TEMP[19].x, TEMP[22].zzzz, IMM[0].xxxx
617:   AND TEMP[19].x, TEMP[19].xxxx, IMM[1].wwww
618:   MOV TEMP[18].z, TEMP[19].xxxx
619:   FSGE TEMP[19].x, TEMP[22].wwww, IMM[0].xxxx
620:   AND TEMP[19].x, TEMP[19].xxxx, IMM[1].wwww
621:   MOV TEMP[18].w, TEMP[19].xxxx
622:   ADD TEMP[17], IMM[1].wwww, -TEMP[17]
623:   MUL TEMP[17], TEMP[18], TEMP[17]
624:   DP4 TEMP[17].x, TEMP[17], IMM[1].wwww
625:   ADD TEMP[0].x, TEMP[0].xxxx, TEMP[17].xxxx
626:   MUL TEMP[6].x, TEMP[6].xxxx, IMM[2].wwww
627:   ADD TEMP[3], TEMP[3], -TEMP[6].xxxx
628:   DP3 TEMP[6].x, TEMP[1].xyzz, CONST[19].xyzz
629:   MUL TEMP[6].xyz, TEMP[6].xxxx, TEMP[1].xyzz
630:   MUL TEMP[6].xyz, IMM[1].xxxx, TEMP[6].xyzz
631:   ADD TEMP[6].xyz, CONST[19].xyzz, -TEMP[6].xyzz
632:   MUL TEMP[8].xyz, TEMP[6].xyzz, TEMP[3].xxxx
633:   DP3 TEMP[6].x, TEMP[1].xyzz, CONST[20].xyzz
634:   MUL TEMP[6].xyz, TEMP[6].xxxx, TEMP[1].xyzz
635:   MUL TEMP[6].xyz, IMM[1].xxxx, TEMP[6].xyzz
636:   ADD TEMP[6].xyz, CONST[20].xyzz, -TEMP[6].xyzz
637:   MUL TEMP[9].xyz, TEMP[6].xyzz, TEMP[3].yyyy
638:   DP3 TEMP[6].x, TEMP[1].xyzz, CONST[21].xyzz
639:   MUL TEMP[6].xyz, TEMP[6].xxxx, TEMP[1].xyzz
640:   MUL TEMP[6].xyz, IMM[1].xxxx, TEMP[6].xyzz
641:   ADD TEMP[6].xyz, CONST[21].xyzz, -TEMP[6].xyzz
642:   MUL TEMP[10].xyz, TEMP[6].xyzz, TEMP[3].zzzz
643:   DP3 TEMP[6].x, TEMP[1].xyzz, CONST[22].xyzz
644:   MUL TEMP[1].xyz, TEMP[6].xxxx, TEMP[1].xyzz
645:   MUL TEMP[1].xyz, IMM[1].xxxx, TEMP[1].xyzz
646:   ADD TEMP[1].xyz, CONST[22].xyzz, -TEMP[1].xyzz
647:   MUL TEMP[11].xyz, TEMP[1].xyzz, TEMP[3].wwww
648:   DP3 TEMP[1].x, TEMP[8].xyzz, TEMP[5].xyzz
649:   DP3 TEMP[6].x, TEMP[9].xyzz, TEMP[5].xyzz
650:   DP3 TEMP[17].x, TEMP[10].xyzz, TEMP[5].xyzz
651:   DP3 TEMP[5].x, TEMP[11].xyzz, TEMP[5].xyzz
652:   FSGE TEMP[1].x, TEMP[1].xxxx, IMM[0].xxxx
653:   UIF TEMP[1].xxxx :0
654:     MOV TEMP[1].x, IMM[4].xxxx
655:   ELSE :0
656:     MOV TEMP[1].x, IMM[4].yyyy
657:   ENDIF
658:   I2F TEMP[1].x, TEMP[1].xxxx
659:   MUL TEMP[8].xyz, TEMP[8].xyzz, TEMP[1].xxxx
660:   FSGE TEMP[1].x, TEMP[6].xxxx, IMM[0].xxxx
661:   UIF TEMP[1].xxxx :0
662:     MOV TEMP[1].x, IMM[4].xxxx
663:   ELSE :0
664:     MOV TEMP[1].x, IMM[4].yyyy
665:   ENDIF
666:   I2F TEMP[1].x, TEMP[1].xxxx
667:   MUL TEMP[9].xyz, TEMP[9].xyzz, TEMP[1].xxxx
668:   FSGE TEMP[1].x, TEMP[17].xxxx, IMM[0].xxxx
669:   UIF TEMP[1].xxxx :0
670:     MOV TEMP[1].x, IMM[4].xxxx
671:   ELSE :0
672:     MOV TEMP[1].x, IMM[4].yyyy
673:   ENDIF
674:   I2F TEMP[1].x, TEMP[1].xxxx
675:   MUL TEMP[10].xyz, TEMP[10].xyzz, TEMP[1].xxxx
676:   FSGE TEMP[1].x, TEMP[5].xxxx, IMM[0].xxxx
677:   UIF TEMP[1].xxxx :0
678:     MOV TEMP[1].x, IMM[4].xxxx
679:   ELSE :0
680:     MOV TEMP[1].x, IMM[4].yyyy
681:   ENDIF
682:   I2F TEMP[1].x, TEMP[1].xxxx
683:   MUL TEMP[11].xyz, TEMP[11].xyzz, TEMP[1].xxxx
684:   ADD TEMP[12].xy, TEMP[4].xyyy, TEMP[8].xyyy
685:   ADD TEMP[1].xy, TEMP[4].xyyy, TEMP[9].xyyy
686:   MOV TEMP[12].zw, TEMP[1].yyxy
687:   ADD TEMP[13].xy, TEMP[4].xyyy, TEMP[10].xyyy
688:   ADD TEMP[1].xy, TEMP[4].xyyy, TEMP[11].xyyy
689:   MOV TEMP[13].zw, TEMP[1].yyxy
690:   ADD TEMP[14].x, TEMP[4].zzzz, TEMP[8].zzzz
691:   ADD TEMP[1].x, TEMP[4].zzzz, TEMP[9].zzzz
692:   MOV TEMP[14].y, TEMP[1].xxxx
693:   ADD TEMP[5].x, TEMP[4].zzzz, TEMP[10].zzzz
694:   MOV TEMP[14].z, TEMP[5].xxxx
695:   ADD TEMP[4].x, TEMP[4].zzzz, TEMP[11].zzzz
696:   MOV TEMP[14].w, TEMP[4].xxxx
697:   RCP TEMP[6].xy, -TEMP[14].xxxx
698:   RCP TEMP[6].zw, -TEMP[1].xxxx
699:   MUL TEMP[1], TEMP[12], TEMP[6]
700:   MAD TEMP[15], TEMP[1], CONST[2].xzxz, -CONST[2].ywyw
701:   RCP TEMP[1].xy, -TEMP[5].xxxx
702:   RCP TEMP[1].zw, -TEMP[4].xxxx
703:   MUL TEMP[1], TEMP[13], TEMP[1]
704:   MAD TEMP[16], TEMP[1], CONST[2].xzxz, -CONST[2].ywyw
705:   MAD TEMP[15], TEMP[15], IMM[2].yzyz, IMM[0].yyyy
706:   MAD TEMP[16], TEMP[16], IMM[2].yzyz, IMM[0].yyyy
707:   MOV_SAT TEMP[1], TEMP[15]
708:   MOV_SAT TEMP[4], TEMP[16]
709:   MOV TEMP[5].xy, TEMP[1].xyyy
710:   TEX TEMP[5].x, TEMP[5], SAMP[0], 2D
711:   MOV TEMP[6].x, TEMP[5].xxxx
712:   MOV TEMP[1].xy, TEMP[1].zwww
713:   TEX TEMP[1].x, TEMP[1], SAMP[0], 2D
714:   MOV TEMP[6].y, TEMP[1].xxxx
715:   MOV TEMP[8].xy, TEMP[4].xyyy
716:   TEX TEMP[8].x, TEMP[8], SAMP[0], 2D
717:   MOV TEMP[6].z, TEMP[8].xxxx
718:   MOV TEMP[4].xy, TEMP[4].zwww
719:   TEX TEMP[4].x, TEMP[4], SAMP[0], 2D
720:   MOV TEMP[6].w, TEMP[4].xxxx
721:   ABS TEMP[6], TEMP[6]
722:   MAD TEMP[6], TEMP[6], CONST[1].yyyy, -CONST[1].xxxx
723:   ADD TEMP[9], TEMP[6], -TEMP[14]
724:   MUL TEMP[3], TEMP[3], IMM[1].xxxx
725:   FSGE TEMP[10].x, TEMP[9].xxxx, TEMP[3].xxxx
726:   AND TEMP[10].x, TEMP[10].xxxx, IMM[1].wwww
727:   FSGE TEMP[11].x, TEMP[9].yyyy, TEMP[3].yyyy
728:   AND TEMP[11].x, TEMP[11].xxxx, IMM[1].wwww
729:   MOV TEMP[10].y, TEMP[11].xxxx
730:   FSGE TEMP[11].x, TEMP[9].zzzz, TEMP[3].zzzz
731:   AND TEMP[11].x, TEMP[11].xxxx, IMM[1].wwww
732:   MOV TEMP[10].z, TEMP[11].xxxx
733:   FSGE TEMP[3].x, TEMP[9].wwww, TEMP[3].wwww
734:   AND TEMP[3].x, TEMP[3].xxxx, IMM[1].wwww
735:   MOV TEMP[10].w, TEMP[3].xxxx
736:   FSEQ TEMP[3].x, TEMP[6].xxxx, IMM[0].xxxx
737:   UIF TEMP[3].xxxx :0
738:     MOV TEMP[3].x, IMM[4].xxxx
739:   ELSE :0
740:     MOV TEMP[3].x, IMM[4].zzzz
741:   ENDIF
742:   FSEQ TEMP[11].x, TEMP[6].yyyy, IMM[0].xxxx
743:   UIF TEMP[11].xxxx :0
744:     MOV TEMP[11].x, IMM[4].xxxx
745:   ELSE :0
746:     MOV TEMP[11].x, IMM[4].zzzz
747:   ENDIF
748:   FSEQ TEMP[12].x, TEMP[6].zzzz, IMM[0].xxxx
749:   UIF TEMP[12].xxxx :0
750:     MOV TEMP[12].x, IMM[4].xxxx
751:   ELSE :0
752:     MOV TEMP[12].x, IMM[4].zzzz
753:   ENDIF
754:   FSEQ TEMP[6].x, TEMP[6].wwww, IMM[0].xxxx
755:   UIF TEMP[6].xxxx :0
756:     MOV TEMP[6].x, IMM[4].xxxx
757:   ELSE :0
758:     MOV TEMP[6].x, IMM[4].zzzz
759:   ENDIF
760:   I2F TEMP[3].x, TEMP[3].xxxx
761:   I2F TEMP[11].x, TEMP[11].xxxx
762:   MOV TEMP[3].y, TEMP[11].xxxx
763:   I2F TEMP[11].x, TEMP[12].xxxx
764:   MOV TEMP[3].z, TEMP[11].xxxx
765:   I2F TEMP[6].x, TEMP[6].xxxx
766:   MOV TEMP[3].w, TEMP[6].xxxx
767:   FSGE TEMP[5].x, IMM[0].xxxx, TEMP[5].xxxx
768:   AND TEMP[5].x, TEMP[5].xxxx, IMM[1].wwww
769:   FSGE TEMP[1].x, IMM[0].xxxx, TEMP[1].xxxx
770:   AND TEMP[1].x, TEMP[1].xxxx, IMM[1].wwww
771:   MOV TEMP[5].y, TEMP[1].xxxx
772:   FSGE TEMP[1].x, IMM[0].xxxx, TEMP[8].xxxx
773:   AND TEMP[1].x, TEMP[1].xxxx, IMM[1].wwww
774:   MOV TEMP[5].z, TEMP[1].xxxx
775:   FSGE TEMP[1].x, IMM[0].xxxx, TEMP[4].xxxx
776:   AND TEMP[1].x, TEMP[1].xxxx, IMM[1].wwww
777:   MOV TEMP[5].w, TEMP[1].xxxx
778:   ADD TEMP[1], TEMP[10], TEMP[3]
779:   MAD_SAT TEMP[1], TEMP[5], TEMP[7].xxxx, TEMP[1]
780:   DP4 TEMP[3].x, TEMP[1], IMM[1].wwww
781:   ADD TEMP[2].x, TEMP[2].xxxx, TEMP[3].xxxx
782:   FSGE TEMP[3].x, TEMP[9].xxxx, IMM[0].xxxx
783:   AND TEMP[3].x, TEMP[3].xxxx, IMM[1].wwww
784:   FSGE TEMP[4].x, TEMP[9].yyyy, IMM[0].xxxx
785:   AND TEMP[4].x, TEMP[4].xxxx, IMM[1].wwww
786:   MOV TEMP[3].y, TEMP[4].xxxx
787:   FSGE TEMP[4].x, TEMP[9].zzzz, IMM[0].xxxx
788:   AND TEMP[4].x, TEMP[4].xxxx, IMM[1].wwww
789:   MOV TEMP[3].z, TEMP[4].xxxx
790:   FSGE TEMP[4].x, TEMP[9].wwww, IMM[0].xxxx
791:   AND TEMP[4].x, TEMP[4].xxxx, IMM[1].wwww
792:   MOV TEMP[3].w, TEMP[4].xxxx
793:   ADD TEMP[1], IMM[1].wwww, -TEMP[1]
794:   MUL TEMP[1], TEMP[3], TEMP[1]
795:   DP4 TEMP[1].x, TEMP[1], IMM[1].wwww
796:   ADD TEMP[0].x, TEMP[0].xxxx, TEMP[1].xxxx
797:   ADD TEMP[1].x, IMM[5].xxxx, -TEMP[2].xxxx
798:   RCP TEMP[1].x, TEMP[1].xxxx
799:   MUL TEMP[0].x, TEMP[0].xxxx, TEMP[1].xxxx
800: ENDIF
801: MUL_SAT TEMP[0].x, TEMP[0].xxxx, CONST[6].yyyy
802: ADD TEMP[0].x, IMM[1].wwww, -TEMP[0].xxxx
803: MOV TEMP[1].xyz, IMM[0].xxxx
804: MUL TEMP[0].x, TEMP[0].xxxx, TEMP[0].xxxx
805: MOV TEMP[1].w, TEMP[0].xxxx
806: MOV OUT[0], TEMP[1]
807: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %21 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
  %22 = load <16 x i8> addrspace(2)* %21, !tbaa !0
  %23 = call float @llvm.SI.load.const(<16 x i8> %22, i32 0)
  %24 = call float @llvm.SI.load.const(<16 x i8> %22, i32 4)
  %25 = call float @llvm.SI.load.const(<16 x i8> %22, i32 8)
  %26 = call float @llvm.SI.load.const(<16 x i8> %22, i32 12)
  %27 = call float @llvm.SI.load.const(<16 x i8> %22, i32 16)
  %28 = call float @llvm.SI.load.const(<16 x i8> %22, i32 20)
  %29 = call float @llvm.SI.load.const(<16 x i8> %22, i32 32)
  %30 = call float @llvm.SI.load.const(<16 x i8> %22, i32 36)
  %31 = call float @llvm.SI.load.const(<16 x i8> %22, i32 40)
  %32 = call float @llvm.SI.load.const(<16 x i8> %22, i32 44)
  %33 = call float @llvm.SI.load.const(<16 x i8> %22, i32 48)
  %34 = call float @llvm.SI.load.const(<16 x i8> %22, i32 52)
  %35 = call float @llvm.SI.load.const(<16 x i8> %22, i32 64)
  %36 = call float @llvm.SI.load.const(<16 x i8> %22, i32 68)
  %37 = call float @llvm.SI.load.const(<16 x i8> %22, i32 72)
  %38 = call float @llvm.SI.load.const(<16 x i8> %22, i32 76)
  %39 = call float @llvm.SI.load.const(<16 x i8> %22, i32 80)
  %40 = call float @llvm.SI.load.const(<16 x i8> %22, i32 84)
  %41 = call float @llvm.SI.load.const(<16 x i8> %22, i32 88)
  %42 = call float @llvm.SI.load.const(<16 x i8> %22, i32 92)
  %43 = call float @llvm.SI.load.const(<16 x i8> %22, i32 96)
  %44 = call float @llvm.SI.load.const(<16 x i8> %22, i32 100)
  %45 = call float @llvm.SI.load.const(<16 x i8> %22, i32 104)
  %46 = call float @llvm.SI.load.const(<16 x i8> %22, i32 112)
  %47 = call float @llvm.SI.load.const(<16 x i8> %22, i32 116)
  %48 = call float @llvm.SI.load.const(<16 x i8> %22, i32 120)
  %49 = call float @llvm.SI.load.const(<16 x i8> %22, i32 128)
  %50 = call float @llvm.SI.load.const(<16 x i8> %22, i32 132)
  %51 = call float @llvm.SI.load.const(<16 x i8> %22, i32 136)
  %52 = call float @llvm.SI.load.const(<16 x i8> %22, i32 144)
  %53 = call float @llvm.SI.load.const(<16 x i8> %22, i32 148)
  %54 = call float @llvm.SI.load.const(<16 x i8> %22, i32 152)
  %55 = call float @llvm.SI.load.const(<16 x i8> %22, i32 160)
  %56 = call float @llvm.SI.load.const(<16 x i8> %22, i32 164)
  %57 = call float @llvm.SI.load.const(<16 x i8> %22, i32 168)
  %58 = call float @llvm.SI.load.const(<16 x i8> %22, i32 176)
  %59 = call float @llvm.SI.load.const(<16 x i8> %22, i32 180)
  %60 = call float @llvm.SI.load.const(<16 x i8> %22, i32 184)
  %61 = call float @llvm.SI.load.const(<16 x i8> %22, i32 192)
  %62 = call float @llvm.SI.load.const(<16 x i8> %22, i32 196)
  %63 = call float @llvm.SI.load.const(<16 x i8> %22, i32 200)
  %64 = call float @llvm.SI.load.const(<16 x i8> %22, i32 208)
  %65 = call float @llvm.SI.load.const(<16 x i8> %22, i32 212)
  %66 = call float @llvm.SI.load.const(<16 x i8> %22, i32 216)
  %67 = call float @llvm.SI.load.const(<16 x i8> %22, i32 224)
  %68 = call float @llvm.SI.load.const(<16 x i8> %22, i32 228)
  %69 = call float @llvm.SI.load.const(<16 x i8> %22, i32 232)
  %70 = call float @llvm.SI.load.const(<16 x i8> %22, i32 240)
  %71 = call float @llvm.SI.load.const(<16 x i8> %22, i32 244)
  %72 = call float @llvm.SI.load.const(<16 x i8> %22, i32 248)
  %73 = call float @llvm.SI.load.const(<16 x i8> %22, i32 256)
  %74 = call float @llvm.SI.load.const(<16 x i8> %22, i32 260)
  %75 = call float @llvm.SI.load.const(<16 x i8> %22, i32 264)
  %76 = call float @llvm.SI.load.const(<16 x i8> %22, i32 272)
  %77 = call float @llvm.SI.load.const(<16 x i8> %22, i32 276)
  %78 = call float @llvm.SI.load.const(<16 x i8> %22, i32 280)
  %79 = call float @llvm.SI.load.const(<16 x i8> %22, i32 288)
  %80 = call float @llvm.SI.load.const(<16 x i8> %22, i32 292)
  %81 = call float @llvm.SI.load.const(<16 x i8> %22, i32 296)
  %82 = call float @llvm.SI.load.const(<16 x i8> %22, i32 304)
  %83 = call float @llvm.SI.load.const(<16 x i8> %22, i32 308)
  %84 = call float @llvm.SI.load.const(<16 x i8> %22, i32 312)
  %85 = call float @llvm.SI.load.const(<16 x i8> %22, i32 320)
  %86 = call float @llvm.SI.load.const(<16 x i8> %22, i32 324)
  %87 = call float @llvm.SI.load.const(<16 x i8> %22, i32 328)
  %88 = call float @llvm.SI.load.const(<16 x i8> %22, i32 336)
  %89 = call float @llvm.SI.load.const(<16 x i8> %22, i32 340)
  %90 = call float @llvm.SI.load.const(<16 x i8> %22, i32 344)
  %91 = call float @llvm.SI.load.const(<16 x i8> %22, i32 352)
  %92 = call float @llvm.SI.load.const(<16 x i8> %22, i32 356)
  %93 = call float @llvm.SI.load.const(<16 x i8> %22, i32 360)
  %94 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0
  %95 = load <32 x i8> addrspace(2)* %94, !tbaa !0
  %96 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0
  %97 = load <16 x i8> addrspace(2)* %96, !tbaa !0
  %98 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 1
  %99 = load <32 x i8> addrspace(2)* %98, !tbaa !0
  %100 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 1
  %101 = load <16 x i8> addrspace(2)* %100, !tbaa !0
  %102 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %4, <2 x i32> %6)
  %103 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %4, <2 x i32> %6)
  %104 = fmul float %102, %35
  %105 = fadd float %104, 5.000000e-01
  %106 = fmul float %103, %36
  %107 = fadd float %106, 5.000000e-01
  %108 = call float @llvm.AMDIL.fraction.(float %105)
  %109 = call float @llvm.AMDIL.fraction.(float %107)
  %110 = fsub float -0.000000e+00, %108
  %111 = fadd float %105, %110
  %112 = fsub float -0.000000e+00, %109
  %113 = fadd float %107, %112
  %114 = fadd float %111, 5.000000e-01
  %115 = fadd float %113, 5.000000e-01
  %116 = fmul float %114, %37
  %117 = fmul float %115, %38
  %118 = bitcast float %116 to i32
  %119 = bitcast float %117 to i32
  %120 = insertelement <2 x i32> undef, i32 %118, i32 0
  %121 = insertelement <2 x i32> %120, i32 %119, i32 1
  %122 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %121, <32 x i8> %95, <16 x i8> %97, i32 2)
  %123 = extractelement <4 x float> %122, i32 0
  %124 = call float @fabs(float %123)
  %125 = fsub float -0.000000e+00, %27
  %126 = fmul float %124, %28
  %127 = fadd float %126, %125
  %128 = fcmp olt float %123, 0x3FEE666660000000
  %129 = sext i1 %128 to i32
  %130 = bitcast i32 %129 to float
  %131 = bitcast float %130 to i32
  %132 = icmp ne i32 %131, 0
  br i1 %132, label %IF, label %ENDIF

IF:                                               ; preds = %main_body
  %133 = fmul float %116, 2.000000e+00
  %134 = fadd float %133, -1.000000e+00
  %135 = fmul float %117, -2.000000e+00
  %136 = fadd float %135, 1.000000e+00
  %137 = fadd float %134, %30
  %138 = fadd float %136, %32
  %139 = fsub float -0.000000e+00, %127
  %140 = fmul float %139, %137
  %141 = fsub float -0.000000e+00, %127
  %142 = fmul float %141, %138
  %143 = fdiv float 1.000000e+00, %29
  %144 = fdiv float 1.000000e+00, %31
  %145 = fmul float %140, %143
  %146 = fmul float %142, %144
  %147 = fsub float -0.000000e+00, %37
  %148 = fadd float %116, %147
  %149 = fadd float %117, 0.000000e+00
  %150 = fadd float %116, %37
  %151 = fsub float -0.000000e+00, %38
  %152 = fadd float %116, 0.000000e+00
  %153 = fadd float %117, %151
  %154 = fadd float %117, %38
  %155 = bitcast float %148 to i32
  %156 = bitcast float %149 to i32
  %157 = insertelement <2 x i32> undef, i32 %155, i32 0
  %158 = insertelement <2 x i32> %157, i32 %156, i32 1
  %159 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %158, <32 x i8> %95, <16 x i8> %97, i32 2)
  %160 = extractelement <4 x float> %159, i32 0
  %161 = bitcast float %150 to i32
  %162 = bitcast float %149 to i32
  %163 = insertelement <2 x i32> undef, i32 %161, i32 0
  %164 = insertelement <2 x i32> %163, i32 %162, i32 1
  %165 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %164, <32 x i8> %95, <16 x i8> %97, i32 2)
  %166 = extractelement <4 x float> %165, i32 0
  %167 = bitcast float %152 to i32
  %168 = bitcast float %153 to i32
  %169 = insertelement <2 x i32> undef, i32 %167, i32 0
  %170 = insertelement <2 x i32> %169, i32 %168, i32 1
  %171 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %170, <32 x i8> %95, <16 x i8> %97, i32 2)
  %172 = extractelement <4 x float> %171, i32 0
  %173 = bitcast float %152 to i32
  %174 = bitcast float %154 to i32
  %175 = insertelement <2 x i32> undef, i32 %173, i32 0
  %176 = insertelement <2 x i32> %175, i32 %174, i32 1
  %177 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %176, <32 x i8> %95, <16 x i8> %97, i32 2)
  %178 = extractelement <4 x float> %177, i32 0
  %179 = call float @fabs(float %160)
  %180 = call float @fabs(float %166)
  %181 = call float @fabs(float %172)
  %182 = call float @fabs(float %178)
  %183 = fsub float -0.000000e+00, %27
  %184 = fmul float %179, %28
  %185 = fadd float %184, %183
  %186 = fsub float -0.000000e+00, %27
  %187 = fmul float %180, %28
  %188 = fadd float %187, %186
  %189 = fsub float -0.000000e+00, %27
  %190 = fmul float %181, %28
  %191 = fadd float %190, %189
  %192 = fsub float -0.000000e+00, %27
  %193 = fmul float %182, %28
  %194 = fadd float %193, %192
  %195 = fsub float -0.000000e+00, %127
  %196 = fadd float %185, %195
  %197 = fsub float -0.000000e+00, %127
  %198 = fadd float %188, %197
  %199 = fsub float -0.000000e+00, %127
  %200 = fadd float %191, %199
  %201 = fsub float -0.000000e+00, %127
  %202 = fadd float %194, %201
  %203 = call float @fabs(float %196)
  %204 = call float @fabs(float %198)
  %205 = call float @fabs(float %200)
  %206 = call float @fabs(float %202)
  %207 = fcmp olt float %203, %204
  %208 = sext i1 %207 to i32
  %209 = bitcast i32 %208 to float
  %210 = bitcast float %209 to i32
  %211 = icmp ne i32 %210, 0
  %. = select i1 %211, float %148, float %150
  %.213 = select i1 %211, float %185, float %188
  %.214 = select i1 %211, float -1.000000e+00, float 1.000000e+00
  %212 = fcmp olt float %205, %206
  %213 = sext i1 %212 to i32
  %214 = bitcast i32 %213 to float
  %215 = bitcast float %214 to i32
  %216 = icmp ne i32 %215, 0
  %temp21.0 = select i1 %216, float %153, float %154
  %temp22.0 = select i1 %216, float %191, float %194
  %temp23.0 = select i1 %216, float -1.000000e+00, float 1.000000e+00
  %217 = fmul float %., 2.000000e+00
  %218 = fadd float %217, -1.000000e+00
  %219 = fmul float %149, -2.000000e+00
  %220 = fadd float %219, 1.000000e+00
  %221 = fadd float %218, %30
  %222 = fadd float %220, %32
  %223 = fsub float -0.000000e+00, %.213
  %224 = fmul float %223, %221
  %225 = fsub float -0.000000e+00, %.213
  %226 = fmul float %225, %222
  %227 = fdiv float 1.000000e+00, %29
  %228 = fdiv float 1.000000e+00, %31
  %229 = fmul float %224, %227
  %230 = fmul float %226, %228
  %231 = fmul float %152, 2.000000e+00
  %232 = fadd float %231, -1.000000e+00
  %233 = fmul float %temp21.0, -2.000000e+00
  %234 = fadd float %233, 1.000000e+00
  %235 = fadd float %232, %30
  %236 = fadd float %234, %32
  %237 = fsub float -0.000000e+00, %temp22.0
  %238 = fmul float %237, %235
  %239 = fsub float -0.000000e+00, %temp22.0
  %240 = fmul float %239, %236
  %241 = fdiv float 1.000000e+00, %29
  %242 = fdiv float 1.000000e+00, %31
  %243 = fmul float %238, %241
  %244 = fmul float %240, %242
  %245 = fsub float -0.000000e+00, %145
  %246 = fsub float -0.000000e+00, %146
  %247 = fsub float -0.000000e+00, %127
  %248 = fadd float %229, %245
  %249 = fadd float %230, %246
  %250 = fadd float %.213, %247
  %251 = fmul float %248, %.214
  %252 = fmul float %249, %.214
  %253 = fmul float %250, %.214
  %254 = fadd float %243, %245
  %255 = fadd float %244, %246
  %256 = fadd float %temp22.0, %247
  %257 = fmul float %254, %temp23.0
  %258 = fmul float %255, %temp23.0
  %259 = fmul float %256, %temp23.0
  %260 = fmul float %259, %252
  %261 = fmul float %257, %253
  %262 = fmul float %258, %251
  %263 = fsub float -0.000000e+00, %260
  %264 = fmul float %258, %253
  %265 = fadd float %264, %263
  %266 = fsub float -0.000000e+00, %261
  %267 = fmul float %259, %251
  %268 = fadd float %267, %266
  %269 = fsub float -0.000000e+00, %262
  %270 = fmul float %257, %252
  %271 = fadd float %270, %269
  %272 = fmul float %265, %265
  %273 = fmul float %268, %268
  %274 = fadd float %273, %272
  %275 = fmul float %271, %271
  %276 = fadd float %274, %275
  %277 = call float @llvm.AMDGPU.rsq(float %276)
  %278 = fmul float %265, %277
  %279 = fmul float %268, %277
  %280 = fmul float %271, %277
  %281 = fmul float %278, %127
  %282 = fmul float %279, %127
  %283 = fmul float %280, %127
  %284 = fmul float %281, %25
  %285 = fmul float %282, %25
  %286 = fmul float %283, %25
  %287 = fsub float -0.000000e+00, %284
  %288 = fadd float %145, %287
  %289 = fsub float -0.000000e+00, %285
  %290 = fadd float %146, %289
  %291 = fsub float -0.000000e+00, %286
  %292 = fadd float %127, %291
  %293 = fmul float %33, 2.500000e-01
  %294 = fmul float %34, 2.500000e-01
  %295 = fmul float %116, %293
  %296 = fmul float %117, %294
  %297 = bitcast float %295 to i32
  %298 = bitcast float %296 to i32
  %299 = insertelement <2 x i32> undef, i32 %297, i32 0
  %300 = insertelement <2 x i32> %299, i32 %298, i32 1
  %301 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %300, <32 x i8> %99, <16 x i8> %101, i32 2)
  %302 = extractelement <4 x float> %301, i32 0
  %303 = extractelement <4 x float> %301, i32 1
  %304 = extractelement <4 x float> %301, i32 2
  %305 = fmul float %302, 2.000000e+00
  %306 = fadd float %305, -1.000000e+00
  %307 = fmul float %303, 2.000000e+00
  %308 = fadd float %307, -1.000000e+00
  %309 = fmul float %304, 2.000000e+00
  %310 = fadd float %309, -1.000000e+00
  %311 = fmul float %306, %26
  %312 = fmul float %308, %26
  %313 = fmul float %310, %26
  %314 = fsub float -0.000000e+00, %127
  %315 = fsub float -0.000000e+00, %39
  %316 = fadd float %314, %315
  %317 = fmul float %316, %42
  %318 = call float @llvm.AMDIL.clamp.(float %317, float 0.000000e+00, float 1.000000e+00)
  %319 = fmul float %41, %318
  %320 = fadd float %319, 1.000000e+00
  %321 = fsub float -0.000000e+00, %127
  %322 = fmul float %321, %40
  %323 = call float @llvm.AMDIL.clamp.(float %322, float 0.000000e+00, float 1.000000e+00)
  %324 = fmul float %320, %323
  %325 = fcmp olt float %123, 0.000000e+00
  %326 = sext i1 %325 to i32
  %327 = bitcast i32 %326 to float
  %328 = bitcast float %327 to i32
  %329 = icmp ne i32 %328, 0
  %.215 = select i1 %329, float %43, float %324
  %330 = fmul float %.215, %45
  %331 = fmul float %24, %330
  %332 = fcmp oge float %123, 0.000000e+00
  %333 = sext i1 %332 to i32
  %334 = bitcast i32 %333 to float
  %335 = bitcast float %334 to i32
  %336 = and i32 %335, 1065353216
  %337 = bitcast i32 %336 to float
  %338 = fmul float %331, 0.000000e+00
  %339 = fmul float %331, 1.000000e+00
  %340 = fmul float %331, 2.000000e+00
  %341 = fmul float %331, 3.000000e+00
  %342 = fsub float -0.000000e+00, %338
  %343 = fmul float %23, %330
  %344 = fadd float %343, %342
  %345 = fsub float -0.000000e+00, %339
  %346 = fmul float %23, %330
  %347 = fadd float %346, %345
  %348 = fsub float -0.000000e+00, %340
  %349 = fmul float %23, %330
  %350 = fadd float %349, %348
  %351 = fsub float -0.000000e+00, %341
  %352 = fmul float %23, %330
  %353 = fadd float %352, %351
  %354 = fmul float %311, %46
  %355 = fmul float %312, %47
  %356 = fadd float %355, %354
  %357 = fmul float %313, %48
  %358 = fadd float %356, %357
  %359 = fmul float %358, %311
  %360 = fmul float %358, %312
  %361 = fmul float %358, %313
  %362 = fmul float 2.000000e+00, %359
  %363 = fmul float 2.000000e+00, %360
  %364 = fmul float 2.000000e+00, %361
  %365 = fsub float -0.000000e+00, %362
  %366 = fadd float %46, %365
  %367 = fsub float -0.000000e+00, %363
  %368 = fadd float %47, %367
  %369 = fsub float -0.000000e+00, %364
  %370 = fadd float %48, %369
  %371 = fmul float %366, %344
  %372 = fmul float %368, %344
  %373 = fmul float %370, %344
  %374 = fmul float %311, %49
  %375 = fmul float %312, %50
  %376 = fadd float %375, %374
  %377 = fmul float %313, %51
  %378 = fadd float %376, %377
  %379 = fmul float %378, %311
  %380 = fmul float %378, %312
  %381 = fmul float %378, %313
  %382 = fmul float 2.000000e+00, %379
  %383 = fmul float 2.000000e+00, %380
  %384 = fmul float 2.000000e+00, %381
  %385 = fsub float -0.000000e+00, %382
  %386 = fadd float %49, %385
  %387 = fsub float -0.000000e+00, %383
  %388 = fadd float %50, %387
  %389 = fsub float -0.000000e+00, %384
  %390 = fadd float %51, %389
  %391 = fmul float %386, %347
  %392 = fmul float %388, %347
  %393 = fmul float %390, %347
  %394 = fmul float %311, %52
  %395 = fmul float %312, %53
  %396 = fadd float %395, %394
  %397 = fmul float %313, %54
  %398 = fadd float %396, %397
  %399 = fmul float %398, %311
  %400 = fmul float %398, %312
  %401 = fmul float %398, %313
  %402 = fmul float 2.000000e+00, %399
  %403 = fmul float 2.000000e+00, %400
  %404 = fmul float 2.000000e+00, %401
  %405 = fsub float -0.000000e+00, %402
  %406 = fadd float %52, %405
  %407 = fsub float -0.000000e+00, %403
  %408 = fadd float %53, %407
  %409 = fsub float -0.000000e+00, %404
  %410 = fadd float %54, %409
  %411 = fmul float %406, %350
  %412 = fmul float %408, %350
  %413 = fmul float %410, %350
  %414 = fmul float %311, %55
  %415 = fmul float %312, %56
  %416 = fadd float %415, %414
  %417 = fmul float %313, %57
  %418 = fadd float %416, %417
  %419 = fmul float %418, %311
  %420 = fmul float %418, %312
  %421 = fmul float %418, %313
  %422 = fmul float 2.000000e+00, %419
  %423 = fmul float 2.000000e+00, %420
  %424 = fmul float 2.000000e+00, %421
  %425 = fsub float -0.000000e+00, %422
  %426 = fadd float %55, %425
  %427 = fsub float -0.000000e+00, %423
  %428 = fadd float %56, %427
  %429 = fsub float -0.000000e+00, %424
  %430 = fadd float %57, %429
  %431 = fmul float %426, %353
  %432 = fmul float %428, %353
  %433 = fmul float %430, %353
  %434 = fmul float %371, %278
  %435 = fmul float %372, %279
  %436 = fadd float %435, %434
  %437 = fmul float %373, %280
  %438 = fadd float %436, %437
  %439 = fmul float %391, %278
  %440 = fmul float %392, %279
  %441 = fadd float %440, %439
  %442 = fmul float %393, %280
  %443 = fadd float %441, %442
  %444 = fmul float %411, %278
  %445 = fmul float %412, %279
  %446 = fadd float %445, %444
  %447 = fmul float %413, %280
  %448 = fadd float %446, %447
  %449 = fmul float %431, %278
  %450 = fmul float %432, %279
  %451 = fadd float %450, %449
  %452 = fmul float %433, %280
  %453 = fadd float %451, %452
  %454 = fcmp oge float %438, 0.000000e+00
  %455 = sext i1 %454 to i32
  %456 = bitcast i32 %455 to float
  %457 = bitcast float %456 to i32
  %458 = icmp ne i32 %457, 0
  %temp48.0 = select i1 %458, float 0x36A0000000000000, float 0xFFFFFFFFE0000000
  %459 = bitcast float %temp48.0 to i32
  %460 = sitofp i32 %459 to float
  %461 = fmul float %371, %460
  %462 = fmul float %372, %460
  %463 = fmul float %373, %460
  %464 = fcmp oge float %443, 0.000000e+00
  %465 = sext i1 %464 to i32
  %466 = bitcast i32 %465 to float
  %467 = bitcast float %466 to i32
  %468 = icmp ne i32 %467, 0
  %.216 = select i1 %468, float 0x36A0000000000000, float 0xFFFFFFFFE0000000
  %469 = bitcast float %.216 to i32
  %470 = sitofp i32 %469 to float
  %471 = fmul float %391, %470
  %472 = fmul float %392, %470
  %473 = fmul float %393, %470
  %474 = fcmp oge float %448, 0.000000e+00
  %475 = sext i1 %474 to i32
  %476 = bitcast i32 %475 to float
  %477 = bitcast float %476 to i32
  %478 = icmp ne i32 %477, 0
  %temp48.2 = select i1 %478, float 0x36A0000000000000, float 0xFFFFFFFFE0000000
  %479 = bitcast float %temp48.2 to i32
  %480 = sitofp i32 %479 to float
  %481 = fmul float %411, %480
  %482 = fmul float %412, %480
  %483 = fmul float %413, %480
  %484 = fcmp oge float %453, 0.000000e+00
  %485 = sext i1 %484 to i32
  %486 = bitcast i32 %485 to float
  %487 = bitcast float %486 to i32
  %488 = icmp ne i32 %487, 0
  %.217 = select i1 %488, float 0x36A0000000000000, float 0xFFFFFFFFE0000000
  %489 = bitcast float %.217 to i32
  %490 = sitofp i32 %489 to float
  %491 = fmul float %431, %490
  %492 = fmul float %432, %490
  %493 = fmul float %433, %490
  %494 = fadd float %288, %461
  %495 = fadd float %290, %462
  %496 = fadd float %288, %471
  %497 = fadd float %290, %472
  %498 = fadd float %288, %481
  %499 = fadd float %290, %482
  %500 = fadd float %288, %491
  %501 = fadd float %290, %492
  %502 = fadd float %292, %463
  %503 = fadd float %292, %473
  %504 = fadd float %292, %483
  %505 = fadd float %292, %493
  %506 = fsub float -0.000000e+00, %502
  %507 = fdiv float 1.000000e+00, %506
  %508 = fsub float -0.000000e+00, %503
  %509 = fdiv float 1.000000e+00, %508
  %510 = fmul float %494, %507
  %511 = fmul float %495, %507
  %512 = fmul float %496, %509
  %513 = fmul float %497, %509
  %514 = fsub float -0.000000e+00, %30
  %515 = fmul float %510, %29
  %516 = fadd float %515, %514
  %517 = fsub float -0.000000e+00, %32
  %518 = fmul float %511, %31
  %519 = fadd float %518, %517
  %520 = fsub float -0.000000e+00, %30
  %521 = fmul float %512, %29
  %522 = fadd float %521, %520
  %523 = fsub float -0.000000e+00, %32
  %524 = fmul float %513, %31
  %525 = fadd float %524, %523
  %526 = fsub float -0.000000e+00, %504
  %527 = fdiv float 1.000000e+00, %526
  %528 = fsub float -0.000000e+00, %505
  %529 = fdiv float 1.000000e+00, %528
  %530 = fmul float %498, %527
  %531 = fmul float %499, %527
  %532 = fmul float %500, %529
  %533 = fmul float %501, %529
  %534 = fsub float -0.000000e+00, %30
  %535 = fmul float %530, %29
  %536 = fadd float %535, %534
  %537 = fsub float -0.000000e+00, %32
  %538 = fmul float %531, %31
  %539 = fadd float %538, %537
  %540 = fsub float -0.000000e+00, %30
  %541 = fmul float %532, %29
  %542 = fadd float %541, %540
  %543 = fsub float -0.000000e+00, %32
  %544 = fmul float %533, %31
  %545 = fadd float %544, %543
  %546 = fmul float %516, 5.000000e-01
  %547 = fadd float %546, 5.000000e-01
  %548 = fmul float %519, -5.000000e-01
  %549 = fadd float %548, 5.000000e-01
  %550 = fmul float %522, 5.000000e-01
  %551 = fadd float %550, 5.000000e-01
  %552 = fmul float %525, -5.000000e-01
  %553 = fadd float %552, 5.000000e-01
  %554 = fmul float %536, 5.000000e-01
  %555 = fadd float %554, 5.000000e-01
  %556 = fmul float %539, -5.000000e-01
  %557 = fadd float %556, 5.000000e-01
  %558 = fmul float %542, 5.000000e-01
  %559 = fadd float %558, 5.000000e-01
  %560 = fmul float %545, -5.000000e-01
  %561 = fadd float %560, 5.000000e-01
  %562 = call float @llvm.AMDIL.clamp.(float %547, float 0.000000e+00, float 1.000000e+00)
  %563 = call float @llvm.AMDIL.clamp.(float %549, float 0.000000e+00, float 1.000000e+00)
  %564 = call float @llvm.AMDIL.clamp.(float %551, float 0.000000e+00, float 1.000000e+00)
  %565 = call float @llvm.AMDIL.clamp.(float %553, float 0.000000e+00, float 1.000000e+00)
  %566 = call float @llvm.AMDIL.clamp.(float %555, float 0.000000e+00, float 1.000000e+00)
  %567 = call float @llvm.AMDIL.clamp.(float %557, float 0.000000e+00, float 1.000000e+00)
  %568 = call float @llvm.AMDIL.clamp.(float %559, float 0.000000e+00, float 1.000000e+00)
  %569 = call float @llvm.AMDIL.clamp.(float %561, float 0.000000e+00, float 1.000000e+00)
  %570 = bitcast float %562 to i32
  %571 = bitcast float %563 to i32
  %572 = insertelement <2 x i32> undef, i32 %570, i32 0
  %573 = insertelement <2 x i32> %572, i32 %571, i32 1
  %574 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %573, <32 x i8> %95, <16 x i8> %97, i32 2)
  %575 = extractelement <4 x float> %574, i32 0
  %576 = bitcast float %564 to i32
  %577 = bitcast float %565 to i32
  %578 = insertelement <2 x i32> undef, i32 %576, i32 0
  %579 = insertelement <2 x i32> %578, i32 %577, i32 1
  %580 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %579, <32 x i8> %95, <16 x i8> %97, i32 2)
  %581 = extractelement <4 x float> %580, i32 0
  %582 = bitcast float %566 to i32
  %583 = bitcast float %567 to i32
  %584 = insertelement <2 x i32> undef, i32 %582, i32 0
  %585 = insertelement <2 x i32> %584, i32 %583, i32 1
  %586 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %585, <32 x i8> %95, <16 x i8> %97, i32 2)
  %587 = extractelement <4 x float> %586, i32 0
  %588 = bitcast float %568 to i32
  %589 = bitcast float %569 to i32
  %590 = insertelement <2 x i32> undef, i32 %588, i32 0
  %591 = insertelement <2 x i32> %590, i32 %589, i32 1
  %592 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %591, <32 x i8> %95, <16 x i8> %97, i32 2)
  %593 = extractelement <4 x float> %592, i32 0
  %594 = call float @fabs(float %575)
  %595 = call float @fabs(float %581)
  %596 = call float @fabs(float %587)
  %597 = call float @fabs(float %593)
  %598 = fsub float -0.000000e+00, %27
  %599 = fmul float %594, %28
  %600 = fadd float %599, %598
  %601 = fsub float -0.000000e+00, %27
  %602 = fmul float %595, %28
  %603 = fadd float %602, %601
  %604 = fsub float -0.000000e+00, %27
  %605 = fmul float %596, %28
  %606 = fadd float %605, %604
  %607 = fsub float -0.000000e+00, %27
  %608 = fmul float %597, %28
  %609 = fadd float %608, %607
  %610 = fsub float -0.000000e+00, %502
  %611 = fadd float %600, %610
  %612 = fsub float -0.000000e+00, %503
  %613 = fadd float %603, %612
  %614 = fsub float -0.000000e+00, %504
  %615 = fadd float %606, %614
  %616 = fsub float -0.000000e+00, %505
  %617 = fadd float %609, %616
  %618 = fmul float %344, 2.000000e+00
  %619 = fmul float %347, 2.000000e+00
  %620 = fmul float %350, 2.000000e+00
  %621 = fmul float %353, 2.000000e+00
  %622 = fcmp oge float %611, %618
  %623 = sext i1 %622 to i32
  %624 = bitcast i32 %623 to float
  %625 = bitcast float %624 to i32
  %626 = and i32 %625, 1065353216
  %627 = bitcast i32 %626 to float
  %628 = fcmp oge float %613, %619
  %629 = sext i1 %628 to i32
  %630 = bitcast i32 %629 to float
  %631 = bitcast float %630 to i32
  %632 = and i32 %631, 1065353216
  %633 = bitcast i32 %632 to float
  %634 = fcmp oge float %615, %620
  %635 = sext i1 %634 to i32
  %636 = bitcast i32 %635 to float
  %637 = bitcast float %636 to i32
  %638 = and i32 %637, 1065353216
  %639 = bitcast i32 %638 to float
  %640 = fcmp oge float %617, %621
  %641 = sext i1 %640 to i32
  %642 = bitcast i32 %641 to float
  %643 = bitcast float %642 to i32
  %644 = and i32 %643, 1065353216
  %645 = bitcast i32 %644 to float
  %646 = fcmp oeq float %600, 0.000000e+00
  %647 = sext i1 %646 to i32
  %648 = bitcast i32 %647 to float
  %649 = bitcast float %648 to i32
  %650 = icmp ne i32 %649, 0
  %temp92.0 = select i1 %650, float 0x36A0000000000000, float 0.000000e+00
  %651 = fcmp oeq float %603, 0.000000e+00
  %652 = sext i1 %651 to i32
  %653 = bitcast i32 %652 to float
  %654 = bitcast float %653 to i32
  %655 = icmp ne i32 %654, 0
  %.218 = select i1 %655, float 0x36A0000000000000, float 0.000000e+00
  %656 = fcmp oeq float %606, 0.000000e+00
  %657 = sext i1 %656 to i32
  %658 = bitcast i32 %657 to float
  %659 = bitcast float %658 to i32
  %660 = icmp ne i32 %659, 0
  %temp104.0 = select i1 %660, float 0x36A0000000000000, float 0.000000e+00
  %661 = fcmp oeq float %609, 0.000000e+00
  %662 = sext i1 %661 to i32
  %663 = bitcast i32 %662 to float
  %664 = bitcast float %663 to i32
  %665 = icmp ne i32 %664, 0
  %.219 = select i1 %665, float 0x36A0000000000000, float 0.000000e+00
  %666 = bitcast float %temp92.0 to i32
  %667 = sitofp i32 %666 to float
  %668 = bitcast float %.218 to i32
  %669 = sitofp i32 %668 to float
  %670 = bitcast float %temp104.0 to i32
  %671 = sitofp i32 %670 to float
  %672 = bitcast float %.219 to i32
  %673 = sitofp i32 %672 to float
  %674 = fcmp oge float 0.000000e+00, %575
  %675 = sext i1 %674 to i32
  %676 = bitcast i32 %675 to float
  %677 = bitcast float %676 to i32
  %678 = and i32 %677, 1065353216
  %679 = bitcast i32 %678 to float
  %680 = fcmp oge float 0.000000e+00, %581
  %681 = sext i1 %680 to i32
  %682 = bitcast i32 %681 to float
  %683 = bitcast float %682 to i32
  %684 = and i32 %683, 1065353216
  %685 = bitcast i32 %684 to float
  %686 = fcmp oge float 0.000000e+00, %587
  %687 = sext i1 %686 to i32
  %688 = bitcast i32 %687 to float
  %689 = bitcast float %688 to i32
  %690 = and i32 %689, 1065353216
  %691 = bitcast i32 %690 to float
  %692 = fcmp oge float 0.000000e+00, %593
  %693 = sext i1 %692 to i32
  %694 = bitcast i32 %693 to float
  %695 = bitcast float %694 to i32
  %696 = and i32 %695, 1065353216
  %697 = bitcast i32 %696 to float
  %698 = fadd float %627, %667
  %699 = fadd float %633, %669
  %700 = fadd float %639, %671
  %701 = fadd float %645, %673
  %702 = fmul float %679, %337
  %703 = fadd float %702, %698
  %704 = fmul float %685, %337
  %705 = fadd float %704, %699
  %706 = fmul float %691, %337
  %707 = fadd float %706, %700
  %708 = fmul float %697, %337
  %709 = fadd float %708, %701
  %710 = call float @llvm.AMDIL.clamp.(float %703, float 0.000000e+00, float 1.000000e+00)
  %711 = call float @llvm.AMDIL.clamp.(float %705, float 0.000000e+00, float 1.000000e+00)
  %712 = call float @llvm.AMDIL.clamp.(float %707, float 0.000000e+00, float 1.000000e+00)
  %713 = call float @llvm.AMDIL.clamp.(float %709, float 0.000000e+00, float 1.000000e+00)
  %714 = fmul float %710, 1.000000e+00
  %715 = fmul float %711, 1.000000e+00
  %716 = fadd float %714, %715
  %717 = fmul float %712, 1.000000e+00
  %718 = fadd float %716, %717
  %719 = fmul float %713, 1.000000e+00
  %720 = fadd float %718, %719
  %721 = fcmp oge float %611, 0.000000e+00
  %722 = sext i1 %721 to i32
  %723 = bitcast i32 %722 to float
  %724 = bitcast float %723 to i32
  %725 = and i32 %724, 1065353216
  %726 = bitcast i32 %725 to float
  %727 = fcmp oge float %613, 0.000000e+00
  %728 = sext i1 %727 to i32
  %729 = bitcast i32 %728 to float
  %730 = bitcast float %729 to i32
  %731 = and i32 %730, 1065353216
  %732 = bitcast i32 %731 to float
  %733 = fcmp oge float %615, 0.000000e+00
  %734 = sext i1 %733 to i32
  %735 = bitcast i32 %734 to float
  %736 = bitcast float %735 to i32
  %737 = and i32 %736, 1065353216
  %738 = bitcast i32 %737 to float
  %739 = fcmp oge float %617, 0.000000e+00
  %740 = sext i1 %739 to i32
  %741 = bitcast i32 %740 to float
  %742 = bitcast float %741 to i32
  %743 = and i32 %742, 1065353216
  %744 = bitcast i32 %743 to float
  %745 = fsub float -0.000000e+00, %710
  %746 = fadd float 1.000000e+00, %745
  %747 = fsub float -0.000000e+00, %711
  %748 = fadd float 1.000000e+00, %747
  %749 = fsub float -0.000000e+00, %712
  %750 = fadd float 1.000000e+00, %749
  %751 = fsub float -0.000000e+00, %713
  %752 = fadd float 1.000000e+00, %751
  %753 = fmul float %726, %746
  %754 = fmul float %732, %748
  %755 = fmul float %738, %750
  %756 = fmul float %744, %752
  %757 = fmul float %753, 1.000000e+00
  %758 = fmul float %754, 1.000000e+00
  %759 = fadd float %757, %758
  %760 = fmul float %755, 1.000000e+00
  %761 = fadd float %759, %760
  %762 = fmul float %756, 1.000000e+00
  %763 = fadd float %761, %762
  %764 = fmul float %331, 4.000000e+00
  %765 = fsub float -0.000000e+00, %764
  %766 = fadd float %344, %765
  %767 = fsub float -0.000000e+00, %764
  %768 = fadd float %347, %767
  %769 = fsub float -0.000000e+00, %764
  %770 = fadd float %350, %769
  %771 = fsub float -0.000000e+00, %764
  %772 = fadd float %353, %771
  %773 = fmul float %311, %58
  %774 = fmul float %312, %59
  %775 = fadd float %774, %773
  %776 = fmul float %313, %60
  %777 = fadd float %775, %776
  %778 = fmul float %777, %311
  %779 = fmul float %777, %312
  %780 = fmul float %777, %313
  %781 = fmul float 2.000000e+00, %778
  %782 = fmul float 2.000000e+00, %779
  %783 = fmul float 2.000000e+00, %780
  %784 = fsub float -0.000000e+00, %781
  %785 = fadd float %58, %784
  %786 = fsub float -0.000000e+00, %782
  %787 = fadd float %59, %786
  %788 = fsub float -0.000000e+00, %783
  %789 = fadd float %60, %788
  %790 = fmul float %785, %766
  %791 = fmul float %787, %766
  %792 = fmul float %789, %766
  %793 = fmul float %311, %61
  %794 = fmul float %312, %62
  %795 = fadd float %794, %793
  %796 = fmul float %313, %63
  %797 = fadd float %795, %796
  %798 = fmul float %797, %311
  %799 = fmul float %797, %312
  %800 = fmul float %797, %313
  %801 = fmul float 2.000000e+00, %798
  %802 = fmul float 2.000000e+00, %799
  %803 = fmul float 2.000000e+00, %800
  %804 = fsub float -0.000000e+00, %801
  %805 = fadd float %61, %804
  %806 = fsub float -0.000000e+00, %802
  %807 = fadd float %62, %806
  %808 = fsub float -0.000000e+00, %803
  %809 = fadd float %63, %808
  %810 = fmul float %805, %768
  %811 = fmul float %807, %768
  %812 = fmul float %809, %768
  %813 = fmul float %311, %64
  %814 = fmul float %312, %65
  %815 = fadd float %814, %813
  %816 = fmul float %313, %66
  %817 = fadd float %815, %816
  %818 = fmul float %817, %311
  %819 = fmul float %817, %312
  %820 = fmul float %817, %313
  %821 = fmul float 2.000000e+00, %818
  %822 = fmul float 2.000000e+00, %819
  %823 = fmul float 2.000000e+00, %820
  %824 = fsub float -0.000000e+00, %821
  %825 = fadd float %64, %824
  %826 = fsub float -0.000000e+00, %822
  %827 = fadd float %65, %826
  %828 = fsub float -0.000000e+00, %823
  %829 = fadd float %66, %828
  %830 = fmul float %825, %770
  %831 = fmul float %827, %770
  %832 = fmul float %829, %770
  %833 = fmul float %311, %67
  %834 = fmul float %312, %68
  %835 = fadd float %834, %833
  %836 = fmul float %313, %69
  %837 = fadd float %835, %836
  %838 = fmul float %837, %311
  %839 = fmul float %837, %312
  %840 = fmul float %837, %313
  %841 = fmul float 2.000000e+00, %838
  %842 = fmul float 2.000000e+00, %839
  %843 = fmul float 2.000000e+00, %840
  %844 = fsub float -0.000000e+00, %841
  %845 = fadd float %67, %844
  %846 = fsub float -0.000000e+00, %842
  %847 = fadd float %68, %846
  %848 = fsub float -0.000000e+00, %843
  %849 = fadd float %69, %848
  %850 = fmul float %845, %772
  %851 = fmul float %847, %772
  %852 = fmul float %849, %772
  %853 = fmul float %790, %278
  %854 = fmul float %791, %279
  %855 = fadd float %854, %853
  %856 = fmul float %792, %280
  %857 = fadd float %855, %856
  %858 = fmul float %810, %278
  %859 = fmul float %811, %279
  %860 = fadd float %859, %858
  %861 = fmul float %812, %280
  %862 = fadd float %860, %861
  %863 = fmul float %830, %278
  %864 = fmul float %831, %279
  %865 = fadd float %864, %863
  %866 = fmul float %832, %280
  %867 = fadd float %865, %866
  %868 = fmul float %850, %278
  %869 = fmul float %851, %279
  %870 = fadd float %869, %868
  %871 = fmul float %852, %280
  %872 = fadd float %870, %871
  %873 = fcmp oge float %857, 0.000000e+00
  %874 = sext i1 %873 to i32
  %875 = bitcast i32 %874 to float
  %876 = bitcast float %875 to i32
  %877 = icmp ne i32 %876, 0
  %temp68.0 = select i1 %877, float 0x36A0000000000000, float 0xFFFFFFFFE0000000
  %878 = bitcast float %temp68.0 to i32
  %879 = sitofp i32 %878 to float
  %880 = fmul float %790, %879
  %881 = fmul float %791, %879
  %882 = fmul float %792, %879
  %883 = fcmp oge float %862, 0.000000e+00
  %884 = sext i1 %883 to i32
  %885 = bitcast i32 %884 to float
  %886 = bitcast float %885 to i32
  %887 = icmp ne i32 %886, 0
  %.220 = select i1 %887, float 0x36A0000000000000, float 0xFFFFFFFFE0000000
  %888 = bitcast float %.220 to i32
  %889 = sitofp i32 %888 to float
  %890 = fmul float %810, %889
  %891 = fmul float %811, %889
  %892 = fmul float %812, %889
  %893 = fcmp oge float %867, 0.000000e+00
  %894 = sext i1 %893 to i32
  %895 = bitcast i32 %894 to float
  %896 = bitcast float %895 to i32
  %897 = icmp ne i32 %896, 0
  %temp68.2 = select i1 %897, float 0x36A0000000000000, float 0xFFFFFFFFE0000000
  %898 = bitcast float %temp68.2 to i32
  %899 = sitofp i32 %898 to float
  %900 = fmul float %830, %899
  %901 = fmul float %831, %899
  %902 = fmul float %832, %899
  %903 = fcmp oge float %872, 0.000000e+00
  %904 = sext i1 %903 to i32
  %905 = bitcast i32 %904 to float
  %906 = bitcast float %905 to i32
  %907 = icmp ne i32 %906, 0
  %.221 = select i1 %907, float 0x36A0000000000000, float 0xFFFFFFFFE0000000
  %908 = bitcast float %.221 to i32
  %909 = sitofp i32 %908 to float
  %910 = fmul float %850, %909
  %911 = fmul float %851, %909
  %912 = fmul float %852, %909
  %913 = fadd float %288, %880
  %914 = fadd float %290, %881
  %915 = fadd float %288, %890
  %916 = fadd float %290, %891
  %917 = fadd float %288, %900
  %918 = fadd float %290, %901
  %919 = fadd float %288, %910
  %920 = fadd float %290, %911
  %921 = fadd float %292, %882
  %922 = fadd float %292, %892
  %923 = fadd float %292, %902
  %924 = fadd float %292, %912
  %925 = fsub float -0.000000e+00, %921
  %926 = fdiv float 1.000000e+00, %925
  %927 = fsub float -0.000000e+00, %922
  %928 = fdiv float 1.000000e+00, %927
  %929 = fmul float %913, %926
  %930 = fmul float %914, %926
  %931 = fmul float %915, %928
  %932 = fmul float %916, %928
  %933 = fsub float -0.000000e+00, %30
  %934 = fmul float %929, %29
  %935 = fadd float %934, %933
  %936 = fsub float -0.000000e+00, %32
  %937 = fmul float %930, %31
  %938 = fadd float %937, %936
  %939 = fsub float -0.000000e+00, %30
  %940 = fmul float %931, %29
  %941 = fadd float %940, %939
  %942 = fsub float -0.000000e+00, %32
  %943 = fmul float %932, %31
  %944 = fadd float %943, %942
  %945 = fsub float -0.000000e+00, %923
  %946 = fdiv float 1.000000e+00, %945
  %947 = fsub float -0.000000e+00, %924
  %948 = fdiv float 1.000000e+00, %947
  %949 = fmul float %917, %946
  %950 = fmul float %918, %946
  %951 = fmul float %919, %948
  %952 = fmul float %920, %948
  %953 = fsub float -0.000000e+00, %30
  %954 = fmul float %949, %29
  %955 = fadd float %954, %953
  %956 = fsub float -0.000000e+00, %32
  %957 = fmul float %950, %31
  %958 = fadd float %957, %956
  %959 = fsub float -0.000000e+00, %30
  %960 = fmul float %951, %29
  %961 = fadd float %960, %959
  %962 = fsub float -0.000000e+00, %32
  %963 = fmul float %952, %31
  %964 = fadd float %963, %962
  %965 = fmul float %935, 5.000000e-01
  %966 = fadd float %965, 5.000000e-01
  %967 = fmul float %938, -5.000000e-01
  %968 = fadd float %967, 5.000000e-01
  %969 = fmul float %941, 5.000000e-01
  %970 = fadd float %969, 5.000000e-01
  %971 = fmul float %944, -5.000000e-01
  %972 = fadd float %971, 5.000000e-01
  %973 = fmul float %955, 5.000000e-01
  %974 = fadd float %973, 5.000000e-01
  %975 = fmul float %958, -5.000000e-01
  %976 = fadd float %975, 5.000000e-01
  %977 = fmul float %961, 5.000000e-01
  %978 = fadd float %977, 5.000000e-01
  %979 = fmul float %964, -5.000000e-01
  %980 = fadd float %979, 5.000000e-01
  %981 = call float @llvm.AMDIL.clamp.(float %966, float 0.000000e+00, float 1.000000e+00)
  %982 = call float @llvm.AMDIL.clamp.(float %968, float 0.000000e+00, float 1.000000e+00)
  %983 = call float @llvm.AMDIL.clamp.(float %970, float 0.000000e+00, float 1.000000e+00)
  %984 = call float @llvm.AMDIL.clamp.(float %972, float 0.000000e+00, float 1.000000e+00)
  %985 = call float @llvm.AMDIL.clamp.(float %974, float 0.000000e+00, float 1.000000e+00)
  %986 = call float @llvm.AMDIL.clamp.(float %976, float 0.000000e+00, float 1.000000e+00)
  %987 = call float @llvm.AMDIL.clamp.(float %978, float 0.000000e+00, float 1.000000e+00)
  %988 = call float @llvm.AMDIL.clamp.(float %980, float 0.000000e+00, float 1.000000e+00)
  %989 = bitcast float %981 to i32
  %990 = bitcast float %982 to i32
  %991 = insertelement <2 x i32> undef, i32 %989, i32 0
  %992 = insertelement <2 x i32> %991, i32 %990, i32 1
  %993 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %992, <32 x i8> %95, <16 x i8> %97, i32 2)
  %994 = extractelement <4 x float> %993, i32 0
  %995 = bitcast float %983 to i32
  %996 = bitcast float %984 to i32
  %997 = insertelement <2 x i32> undef, i32 %995, i32 0
  %998 = insertelement <2 x i32> %997, i32 %996, i32 1
  %999 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %998, <32 x i8> %95, <16 x i8> %97, i32 2)
  %1000 = extractelement <4 x float> %999, i32 0
  %1001 = bitcast float %985 to i32
  %1002 = bitcast float %986 to i32
  %1003 = insertelement <2 x i32> undef, i32 %1001, i32 0
  %1004 = insertelement <2 x i32> %1003, i32 %1002, i32 1
  %1005 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1004, <32 x i8> %95, <16 x i8> %97, i32 2)
  %1006 = extractelement <4 x float> %1005, i32 0
  %1007 = bitcast float %987 to i32
  %1008 = bitcast float %988 to i32
  %1009 = insertelement <2 x i32> undef, i32 %1007, i32 0
  %1010 = insertelement <2 x i32> %1009, i32 %1008, i32 1
  %1011 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1010, <32 x i8> %95, <16 x i8> %97, i32 2)
  %1012 = extractelement <4 x float> %1011, i32 0
  %1013 = call float @fabs(float %994)
  %1014 = call float @fabs(float %1000)
  %1015 = call float @fabs(float %1006)
  %1016 = call float @fabs(float %1012)
  %1017 = fsub float -0.000000e+00, %27
  %1018 = fmul float %1013, %28
  %1019 = fadd float %1018, %1017
  %1020 = fsub float -0.000000e+00, %27
  %1021 = fmul float %1014, %28
  %1022 = fadd float %1021, %1020
  %1023 = fsub float -0.000000e+00, %27
  %1024 = fmul float %1015, %28
  %1025 = fadd float %1024, %1023
  %1026 = fsub float -0.000000e+00, %27
  %1027 = fmul float %1016, %28
  %1028 = fadd float %1027, %1026
  %1029 = fsub float -0.000000e+00, %921
  %1030 = fadd float %1019, %1029
  %1031 = fsub float -0.000000e+00, %922
  %1032 = fadd float %1022, %1031
  %1033 = fsub float -0.000000e+00, %923
  %1034 = fadd float %1025, %1033
  %1035 = fsub float -0.000000e+00, %924
  %1036 = fadd float %1028, %1035
  %1037 = fmul float %766, 2.000000e+00
  %1038 = fmul float %768, 2.000000e+00
  %1039 = fmul float %770, 2.000000e+00
  %1040 = fmul float %772, 2.000000e+00
  %1041 = fcmp oge float %1030, %1037
  %1042 = sext i1 %1041 to i32
  %1043 = bitcast i32 %1042 to float
  %1044 = bitcast float %1043 to i32
  %1045 = and i32 %1044, 1065353216
  %1046 = bitcast i32 %1045 to float
  %1047 = fcmp oge float %1032, %1038
  %1048 = sext i1 %1047 to i32
  %1049 = bitcast i32 %1048 to float
  %1050 = bitcast float %1049 to i32
  %1051 = and i32 %1050, 1065353216
  %1052 = bitcast i32 %1051 to float
  %1053 = fcmp oge float %1034, %1039
  %1054 = sext i1 %1053 to i32
  %1055 = bitcast i32 %1054 to float
  %1056 = bitcast float %1055 to i32
  %1057 = and i32 %1056, 1065353216
  %1058 = bitcast i32 %1057 to float
  %1059 = fcmp oge float %1036, %1040
  %1060 = sext i1 %1059 to i32
  %1061 = bitcast i32 %1060 to float
  %1062 = bitcast float %1061 to i32
  %1063 = and i32 %1062, 1065353216
  %1064 = bitcast i32 %1063 to float
  %1065 = fcmp oeq float %1019, 0.000000e+00
  %1066 = sext i1 %1065 to i32
  %1067 = bitcast i32 %1066 to float
  %1068 = bitcast float %1067 to i32
  %1069 = icmp ne i32 %1068, 0
  %temp92.1 = select i1 %1069, float 0x36A0000000000000, float 0.000000e+00
  %1070 = fcmp oeq float %1022, 0.000000e+00
  %1071 = sext i1 %1070 to i32
  %1072 = bitcast i32 %1071 to float
  %1073 = bitcast float %1072 to i32
  %1074 = icmp ne i32 %1073, 0
  %.222 = select i1 %1074, float 0x36A0000000000000, float 0.000000e+00
  %1075 = fcmp oeq float %1025, 0.000000e+00
  %1076 = sext i1 %1075 to i32
  %1077 = bitcast i32 %1076 to float
  %1078 = bitcast float %1077 to i32
  %1079 = icmp ne i32 %1078, 0
  %temp104.1 = select i1 %1079, float 0x36A0000000000000, float 0.000000e+00
  %1080 = fcmp oeq float %1028, 0.000000e+00
  %1081 = sext i1 %1080 to i32
  %1082 = bitcast i32 %1081 to float
  %1083 = bitcast float %1082 to i32
  %1084 = icmp ne i32 %1083, 0
  %.223 = select i1 %1084, float 0x36A0000000000000, float 0.000000e+00
  %1085 = bitcast float %temp92.1 to i32
  %1086 = sitofp i32 %1085 to float
  %1087 = bitcast float %.222 to i32
  %1088 = sitofp i32 %1087 to float
  %1089 = bitcast float %temp104.1 to i32
  %1090 = sitofp i32 %1089 to float
  %1091 = bitcast float %.223 to i32
  %1092 = sitofp i32 %1091 to float
  %1093 = fcmp oge float 0.000000e+00, %994
  %1094 = sext i1 %1093 to i32
  %1095 = bitcast i32 %1094 to float
  %1096 = bitcast float %1095 to i32
  %1097 = and i32 %1096, 1065353216
  %1098 = bitcast i32 %1097 to float
  %1099 = fcmp oge float 0.000000e+00, %1000
  %1100 = sext i1 %1099 to i32
  %1101 = bitcast i32 %1100 to float
  %1102 = bitcast float %1101 to i32
  %1103 = and i32 %1102, 1065353216
  %1104 = bitcast i32 %1103 to float
  %1105 = fcmp oge float 0.000000e+00, %1006
  %1106 = sext i1 %1105 to i32
  %1107 = bitcast i32 %1106 to float
  %1108 = bitcast float %1107 to i32
  %1109 = and i32 %1108, 1065353216
  %1110 = bitcast i32 %1109 to float
  %1111 = fcmp oge float 0.000000e+00, %1012
  %1112 = sext i1 %1111 to i32
  %1113 = bitcast i32 %1112 to float
  %1114 = bitcast float %1113 to i32
  %1115 = and i32 %1114, 1065353216
  %1116 = bitcast i32 %1115 to float
  %1117 = fadd float %1046, %1086
  %1118 = fadd float %1052, %1088
  %1119 = fadd float %1058, %1090
  %1120 = fadd float %1064, %1092
  %1121 = fmul float %1098, %337
  %1122 = fadd float %1121, %1117
  %1123 = fmul float %1104, %337
  %1124 = fadd float %1123, %1118
  %1125 = fmul float %1110, %337
  %1126 = fadd float %1125, %1119
  %1127 = fmul float %1116, %337
  %1128 = fadd float %1127, %1120
  %1129 = call float @llvm.AMDIL.clamp.(float %1122, float 0.000000e+00, float 1.000000e+00)
  %1130 = call float @llvm.AMDIL.clamp.(float %1124, float 0.000000e+00, float 1.000000e+00)
  %1131 = call float @llvm.AMDIL.clamp.(float %1126, float 0.000000e+00, float 1.000000e+00)
  %1132 = call float @llvm.AMDIL.clamp.(float %1128, float 0.000000e+00, float 1.000000e+00)
  %1133 = fmul float %1129, 1.000000e+00
  %1134 = fmul float %1130, 1.000000e+00
  %1135 = fadd float %1133, %1134
  %1136 = fmul float %1131, 1.000000e+00
  %1137 = fadd float %1135, %1136
  %1138 = fmul float %1132, 1.000000e+00
  %1139 = fadd float %1137, %1138
  %1140 = fadd float %720, %1139
  %1141 = fcmp oge float %1030, 0.000000e+00
  %1142 = sext i1 %1141 to i32
  %1143 = bitcast i32 %1142 to float
  %1144 = bitcast float %1143 to i32
  %1145 = and i32 %1144, 1065353216
  %1146 = bitcast i32 %1145 to float
  %1147 = fcmp oge float %1032, 0.000000e+00
  %1148 = sext i1 %1147 to i32
  %1149 = bitcast i32 %1148 to float
  %1150 = bitcast float %1149 to i32
  %1151 = and i32 %1150, 1065353216
  %1152 = bitcast i32 %1151 to float
  %1153 = fcmp oge float %1034, 0.000000e+00
  %1154 = sext i1 %1153 to i32
  %1155 = bitcast i32 %1154 to float
  %1156 = bitcast float %1155 to i32
  %1157 = and i32 %1156, 1065353216
  %1158 = bitcast i32 %1157 to float
  %1159 = fcmp oge float %1036, 0.000000e+00
  %1160 = sext i1 %1159 to i32
  %1161 = bitcast i32 %1160 to float
  %1162 = bitcast float %1161 to i32
  %1163 = and i32 %1162, 1065353216
  %1164 = bitcast i32 %1163 to float
  %1165 = fsub float -0.000000e+00, %1129
  %1166 = fadd float 1.000000e+00, %1165
  %1167 = fsub float -0.000000e+00, %1130
  %1168 = fadd float 1.000000e+00, %1167
  %1169 = fsub float -0.000000e+00, %1131
  %1170 = fadd float 1.000000e+00, %1169
  %1171 = fsub float -0.000000e+00, %1132
  %1172 = fadd float 1.000000e+00, %1171
  %1173 = fmul float %1146, %1166
  %1174 = fmul float %1152, %1168
  %1175 = fmul float %1158, %1170
  %1176 = fmul float %1164, %1172
  %1177 = fmul float %1173, 1.000000e+00
  %1178 = fmul float %1174, 1.000000e+00
  %1179 = fadd float %1177, %1178
  %1180 = fmul float %1175, 1.000000e+00
  %1181 = fadd float %1179, %1180
  %1182 = fmul float %1176, 1.000000e+00
  %1183 = fadd float %1181, %1182
  %1184 = fadd float %763, %1183
  %1185 = fmul float %331, 4.000000e+00
  %1186 = fsub float -0.000000e+00, %1185
  %1187 = fadd float %766, %1186
  %1188 = fsub float -0.000000e+00, %1185
  %1189 = fadd float %768, %1188
  %1190 = fsub float -0.000000e+00, %1185
  %1191 = fadd float %770, %1190
  %1192 = fsub float -0.000000e+00, %1185
  %1193 = fadd float %772, %1192
  %1194 = fmul float %311, %70
  %1195 = fmul float %312, %71
  %1196 = fadd float %1195, %1194
  %1197 = fmul float %313, %72
  %1198 = fadd float %1196, %1197
  %1199 = fmul float %1198, %311
  %1200 = fmul float %1198, %312
  %1201 = fmul float %1198, %313
  %1202 = fmul float 2.000000e+00, %1199
  %1203 = fmul float 2.000000e+00, %1200
  %1204 = fmul float 2.000000e+00, %1201
  %1205 = fsub float -0.000000e+00, %1202
  %1206 = fadd float %70, %1205
  %1207 = fsub float -0.000000e+00, %1203
  %1208 = fadd float %71, %1207
  %1209 = fsub float -0.000000e+00, %1204
  %1210 = fadd float %72, %1209
  %1211 = fmul float %1206, %1187
  %1212 = fmul float %1208, %1187
  %1213 = fmul float %1210, %1187
  %1214 = fmul float %311, %73
  %1215 = fmul float %312, %74
  %1216 = fadd float %1215, %1214
  %1217 = fmul float %313, %75
  %1218 = fadd float %1216, %1217
  %1219 = fmul float %1218, %311
  %1220 = fmul float %1218, %312
  %1221 = fmul float %1218, %313
  %1222 = fmul float 2.000000e+00, %1219
  %1223 = fmul float 2.000000e+00, %1220
  %1224 = fmul float 2.000000e+00, %1221
  %1225 = fsub float -0.000000e+00, %1222
  %1226 = fadd float %73, %1225
  %1227 = fsub float -0.000000e+00, %1223
  %1228 = fadd float %74, %1227
  %1229 = fsub float -0.000000e+00, %1224
  %1230 = fadd float %75, %1229
  %1231 = fmul float %1226, %1189
  %1232 = fmul float %1228, %1189
  %1233 = fmul float %1230, %1189
  %1234 = fmul float %311, %76
  %1235 = fmul float %312, %77
  %1236 = fadd float %1235, %1234
  %1237 = fmul float %313, %78
  %1238 = fadd float %1236, %1237
  %1239 = fmul float %1238, %311
  %1240 = fmul float %1238, %312
  %1241 = fmul float %1238, %313
  %1242 = fmul float 2.000000e+00, %1239
  %1243 = fmul float 2.000000e+00, %1240
  %1244 = fmul float 2.000000e+00, %1241
  %1245 = fsub float -0.000000e+00, %1242
  %1246 = fadd float %76, %1245
  %1247 = fsub float -0.000000e+00, %1243
  %1248 = fadd float %77, %1247
  %1249 = fsub float -0.000000e+00, %1244
  %1250 = fadd float %78, %1249
  %1251 = fmul float %1246, %1191
  %1252 = fmul float %1248, %1191
  %1253 = fmul float %1250, %1191
  %1254 = fmul float %311, %79
  %1255 = fmul float %312, %80
  %1256 = fadd float %1255, %1254
  %1257 = fmul float %313, %81
  %1258 = fadd float %1256, %1257
  %1259 = fmul float %1258, %311
  %1260 = fmul float %1258, %312
  %1261 = fmul float %1258, %313
  %1262 = fmul float 2.000000e+00, %1259
  %1263 = fmul float 2.000000e+00, %1260
  %1264 = fmul float 2.000000e+00, %1261
  %1265 = fsub float -0.000000e+00, %1262
  %1266 = fadd float %79, %1265
  %1267 = fsub float -0.000000e+00, %1263
  %1268 = fadd float %80, %1267
  %1269 = fsub float -0.000000e+00, %1264
  %1270 = fadd float %81, %1269
  %1271 = fmul float %1266, %1193
  %1272 = fmul float %1268, %1193
  %1273 = fmul float %1270, %1193
  %1274 = fmul float %1211, %278
  %1275 = fmul float %1212, %279
  %1276 = fadd float %1275, %1274
  %1277 = fmul float %1213, %280
  %1278 = fadd float %1276, %1277
  %1279 = fmul float %1231, %278
  %1280 = fmul float %1232, %279
  %1281 = fadd float %1280, %1279
  %1282 = fmul float %1233, %280
  %1283 = fadd float %1281, %1282
  %1284 = fmul float %1251, %278
  %1285 = fmul float %1252, %279
  %1286 = fadd float %1285, %1284
  %1287 = fmul float %1253, %280
  %1288 = fadd float %1286, %1287
  %1289 = fmul float %1271, %278
  %1290 = fmul float %1272, %279
  %1291 = fadd float %1290, %1289
  %1292 = fmul float %1273, %280
  %1293 = fadd float %1291, %1292
  %1294 = fcmp oge float %1278, 0.000000e+00
  %1295 = sext i1 %1294 to i32
  %1296 = bitcast i32 %1295 to float
  %1297 = bitcast float %1296 to i32
  %1298 = icmp ne i32 %1297, 0
  %temp68.4 = select i1 %1298, float 0x36A0000000000000, float 0xFFFFFFFFE0000000
  %1299 = bitcast float %temp68.4 to i32
  %1300 = sitofp i32 %1299 to float
  %1301 = fmul float %1211, %1300
  %1302 = fmul float %1212, %1300
  %1303 = fmul float %1213, %1300
  %1304 = fcmp oge float %1283, 0.000000e+00
  %1305 = sext i1 %1304 to i32
  %1306 = bitcast i32 %1305 to float
  %1307 = bitcast float %1306 to i32
  %1308 = icmp ne i32 %1307, 0
  %.224 = select i1 %1308, float 0x36A0000000000000, float 0xFFFFFFFFE0000000
  %1309 = bitcast float %.224 to i32
  %1310 = sitofp i32 %1309 to float
  %1311 = fmul float %1231, %1310
  %1312 = fmul float %1232, %1310
  %1313 = fmul float %1233, %1310
  %1314 = fcmp oge float %1288, 0.000000e+00
  %1315 = sext i1 %1314 to i32
  %1316 = bitcast i32 %1315 to float
  %1317 = bitcast float %1316 to i32
  %1318 = icmp ne i32 %1317, 0
  %temp68.6 = select i1 %1318, float 0x36A0000000000000, float 0xFFFFFFFFE0000000
  %1319 = bitcast float %temp68.6 to i32
  %1320 = sitofp i32 %1319 to float
  %1321 = fmul float %1251, %1320
  %1322 = fmul float %1252, %1320
  %1323 = fmul float %1253, %1320
  %1324 = fcmp oge float %1293, 0.000000e+00
  %1325 = sext i1 %1324 to i32
  %1326 = bitcast i32 %1325 to float
  %1327 = bitcast float %1326 to i32
  %1328 = icmp ne i32 %1327, 0
  %.225 = select i1 %1328, float 0x36A0000000000000, float 0xFFFFFFFFE0000000
  %1329 = bitcast float %.225 to i32
  %1330 = sitofp i32 %1329 to float
  %1331 = fmul float %1271, %1330
  %1332 = fmul float %1272, %1330
  %1333 = fmul float %1273, %1330
  %1334 = fadd float %288, %1301
  %1335 = fadd float %290, %1302
  %1336 = fadd float %288, %1311
  %1337 = fadd float %290, %1312
  %1338 = fadd float %288, %1321
  %1339 = fadd float %290, %1322
  %1340 = fadd float %288, %1331
  %1341 = fadd float %290, %1332
  %1342 = fadd float %292, %1303
  %1343 = fadd float %292, %1313
  %1344 = fadd float %292, %1323
  %1345 = fadd float %292, %1333
  %1346 = fsub float -0.000000e+00, %1342
  %1347 = fdiv float 1.000000e+00, %1346
  %1348 = fsub float -0.000000e+00, %1343
  %1349 = fdiv float 1.000000e+00, %1348
  %1350 = fmul float %1334, %1347
  %1351 = fmul float %1335, %1347
  %1352 = fmul float %1336, %1349
  %1353 = fmul float %1337, %1349
  %1354 = fsub float -0.000000e+00, %30
  %1355 = fmul float %1350, %29
  %1356 = fadd float %1355, %1354
  %1357 = fsub float -0.000000e+00, %32
  %1358 = fmul float %1351, %31
  %1359 = fadd float %1358, %1357
  %1360 = fsub float -0.000000e+00, %30
  %1361 = fmul float %1352, %29
  %1362 = fadd float %1361, %1360
  %1363 = fsub float -0.000000e+00, %32
  %1364 = fmul float %1353, %31
  %1365 = fadd float %1364, %1363
  %1366 = fsub float -0.000000e+00, %1344
  %1367 = fdiv float 1.000000e+00, %1366
  %1368 = fsub float -0.000000e+00, %1345
  %1369 = fdiv float 1.000000e+00, %1368
  %1370 = fmul float %1338, %1367
  %1371 = fmul float %1339, %1367
  %1372 = fmul float %1340, %1369
  %1373 = fmul float %1341, %1369
  %1374 = fsub float -0.000000e+00, %30
  %1375 = fmul float %1370, %29
  %1376 = fadd float %1375, %1374
  %1377 = fsub float -0.000000e+00, %32
  %1378 = fmul float %1371, %31
  %1379 = fadd float %1378, %1377
  %1380 = fsub float -0.000000e+00, %30
  %1381 = fmul float %1372, %29
  %1382 = fadd float %1381, %1380
  %1383 = fsub float -0.000000e+00, %32
  %1384 = fmul float %1373, %31
  %1385 = fadd float %1384, %1383
  %1386 = fmul float %1356, 5.000000e-01
  %1387 = fadd float %1386, 5.000000e-01
  %1388 = fmul float %1359, -5.000000e-01
  %1389 = fadd float %1388, 5.000000e-01
  %1390 = fmul float %1362, 5.000000e-01
  %1391 = fadd float %1390, 5.000000e-01
  %1392 = fmul float %1365, -5.000000e-01
  %1393 = fadd float %1392, 5.000000e-01
  %1394 = fmul float %1376, 5.000000e-01
  %1395 = fadd float %1394, 5.000000e-01
  %1396 = fmul float %1379, -5.000000e-01
  %1397 = fadd float %1396, 5.000000e-01
  %1398 = fmul float %1382, 5.000000e-01
  %1399 = fadd float %1398, 5.000000e-01
  %1400 = fmul float %1385, -5.000000e-01
  %1401 = fadd float %1400, 5.000000e-01
  %1402 = call float @llvm.AMDIL.clamp.(float %1387, float 0.000000e+00, float 1.000000e+00)
  %1403 = call float @llvm.AMDIL.clamp.(float %1389, float 0.000000e+00, float 1.000000e+00)
  %1404 = call float @llvm.AMDIL.clamp.(float %1391, float 0.000000e+00, float 1.000000e+00)
  %1405 = call float @llvm.AMDIL.clamp.(float %1393, float 0.000000e+00, float 1.000000e+00)
  %1406 = call float @llvm.AMDIL.clamp.(float %1395, float 0.000000e+00, float 1.000000e+00)
  %1407 = call float @llvm.AMDIL.clamp.(float %1397, float 0.000000e+00, float 1.000000e+00)
  %1408 = call float @llvm.AMDIL.clamp.(float %1399, float 0.000000e+00, float 1.000000e+00)
  %1409 = call float @llvm.AMDIL.clamp.(float %1401, float 0.000000e+00, float 1.000000e+00)
  %1410 = bitcast float %1402 to i32
  %1411 = bitcast float %1403 to i32
  %1412 = insertelement <2 x i32> undef, i32 %1410, i32 0
  %1413 = insertelement <2 x i32> %1412, i32 %1411, i32 1
  %1414 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1413, <32 x i8> %95, <16 x i8> %97, i32 2)
  %1415 = extractelement <4 x float> %1414, i32 0
  %1416 = bitcast float %1404 to i32
  %1417 = bitcast float %1405 to i32
  %1418 = insertelement <2 x i32> undef, i32 %1416, i32 0
  %1419 = insertelement <2 x i32> %1418, i32 %1417, i32 1
  %1420 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1419, <32 x i8> %95, <16 x i8> %97, i32 2)
  %1421 = extractelement <4 x float> %1420, i32 0
  %1422 = bitcast float %1406 to i32
  %1423 = bitcast float %1407 to i32
  %1424 = insertelement <2 x i32> undef, i32 %1422, i32 0
  %1425 = insertelement <2 x i32> %1424, i32 %1423, i32 1
  %1426 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1425, <32 x i8> %95, <16 x i8> %97, i32 2)
  %1427 = extractelement <4 x float> %1426, i32 0
  %1428 = bitcast float %1408 to i32
  %1429 = bitcast float %1409 to i32
  %1430 = insertelement <2 x i32> undef, i32 %1428, i32 0
  %1431 = insertelement <2 x i32> %1430, i32 %1429, i32 1
  %1432 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1431, <32 x i8> %95, <16 x i8> %97, i32 2)
  %1433 = extractelement <4 x float> %1432, i32 0
  %1434 = call float @fabs(float %1415)
  %1435 = call float @fabs(float %1421)
  %1436 = call float @fabs(float %1427)
  %1437 = call float @fabs(float %1433)
  %1438 = fsub float -0.000000e+00, %27
  %1439 = fmul float %1434, %28
  %1440 = fadd float %1439, %1438
  %1441 = fsub float -0.000000e+00, %27
  %1442 = fmul float %1435, %28
  %1443 = fadd float %1442, %1441
  %1444 = fsub float -0.000000e+00, %27
  %1445 = fmul float %1436, %28
  %1446 = fadd float %1445, %1444
  %1447 = fsub float -0.000000e+00, %27
  %1448 = fmul float %1437, %28
  %1449 = fadd float %1448, %1447
  %1450 = fsub float -0.000000e+00, %1342
  %1451 = fadd float %1440, %1450
  %1452 = fsub float -0.000000e+00, %1343
  %1453 = fadd float %1443, %1452
  %1454 = fsub float -0.000000e+00, %1344
  %1455 = fadd float %1446, %1454
  %1456 = fsub float -0.000000e+00, %1345
  %1457 = fadd float %1449, %1456
  %1458 = fmul float %1187, 2.000000e+00
  %1459 = fmul float %1189, 2.000000e+00
  %1460 = fmul float %1191, 2.000000e+00
  %1461 = fmul float %1193, 2.000000e+00
  %1462 = fcmp oge float %1451, %1458
  %1463 = sext i1 %1462 to i32
  %1464 = bitcast i32 %1463 to float
  %1465 = bitcast float %1464 to i32
  %1466 = and i32 %1465, 1065353216
  %1467 = bitcast i32 %1466 to float
  %1468 = fcmp oge float %1453, %1459
  %1469 = sext i1 %1468 to i32
  %1470 = bitcast i32 %1469 to float
  %1471 = bitcast float %1470 to i32
  %1472 = and i32 %1471, 1065353216
  %1473 = bitcast i32 %1472 to float
  %1474 = fcmp oge float %1455, %1460
  %1475 = sext i1 %1474 to i32
  %1476 = bitcast i32 %1475 to float
  %1477 = bitcast float %1476 to i32
  %1478 = and i32 %1477, 1065353216
  %1479 = bitcast i32 %1478 to float
  %1480 = fcmp oge float %1457, %1461
  %1481 = sext i1 %1480 to i32
  %1482 = bitcast i32 %1481 to float
  %1483 = bitcast float %1482 to i32
  %1484 = and i32 %1483, 1065353216
  %1485 = bitcast i32 %1484 to float
  %1486 = fcmp oeq float %1440, 0.000000e+00
  %1487 = sext i1 %1486 to i32
  %1488 = bitcast i32 %1487 to float
  %1489 = bitcast float %1488 to i32
  %1490 = icmp ne i32 %1489, 0
  %temp92.2 = select i1 %1490, float 0x36A0000000000000, float 0.000000e+00
  %1491 = fcmp oeq float %1443, 0.000000e+00
  %1492 = sext i1 %1491 to i32
  %1493 = bitcast i32 %1492 to float
  %1494 = bitcast float %1493 to i32
  %1495 = icmp ne i32 %1494, 0
  %.226 = select i1 %1495, float 0x36A0000000000000, float 0.000000e+00
  %1496 = fcmp oeq float %1446, 0.000000e+00
  %1497 = sext i1 %1496 to i32
  %1498 = bitcast i32 %1497 to float
  %1499 = bitcast float %1498 to i32
  %1500 = icmp ne i32 %1499, 0
  %temp104.2 = select i1 %1500, float 0x36A0000000000000, float 0.000000e+00
  %1501 = fcmp oeq float %1449, 0.000000e+00
  %1502 = sext i1 %1501 to i32
  %1503 = bitcast i32 %1502 to float
  %1504 = bitcast float %1503 to i32
  %1505 = icmp ne i32 %1504, 0
  %.227 = select i1 %1505, float 0x36A0000000000000, float 0.000000e+00
  %1506 = bitcast float %temp92.2 to i32
  %1507 = sitofp i32 %1506 to float
  %1508 = bitcast float %.226 to i32
  %1509 = sitofp i32 %1508 to float
  %1510 = bitcast float %temp104.2 to i32
  %1511 = sitofp i32 %1510 to float
  %1512 = bitcast float %.227 to i32
  %1513 = sitofp i32 %1512 to float
  %1514 = fcmp oge float 0.000000e+00, %1415
  %1515 = sext i1 %1514 to i32
  %1516 = bitcast i32 %1515 to float
  %1517 = bitcast float %1516 to i32
  %1518 = and i32 %1517, 1065353216
  %1519 = bitcast i32 %1518 to float
  %1520 = fcmp oge float 0.000000e+00, %1421
  %1521 = sext i1 %1520 to i32
  %1522 = bitcast i32 %1521 to float
  %1523 = bitcast float %1522 to i32
  %1524 = and i32 %1523, 1065353216
  %1525 = bitcast i32 %1524 to float
  %1526 = fcmp oge float 0.000000e+00, %1427
  %1527 = sext i1 %1526 to i32
  %1528 = bitcast i32 %1527 to float
  %1529 = bitcast float %1528 to i32
  %1530 = and i32 %1529, 1065353216
  %1531 = bitcast i32 %1530 to float
  %1532 = fcmp oge float 0.000000e+00, %1433
  %1533 = sext i1 %1532 to i32
  %1534 = bitcast i32 %1533 to float
  %1535 = bitcast float %1534 to i32
  %1536 = and i32 %1535, 1065353216
  %1537 = bitcast i32 %1536 to float
  %1538 = fadd float %1467, %1507
  %1539 = fadd float %1473, %1509
  %1540 = fadd float %1479, %1511
  %1541 = fadd float %1485, %1513
  %1542 = fmul float %1519, %337
  %1543 = fadd float %1542, %1538
  %1544 = fmul float %1525, %337
  %1545 = fadd float %1544, %1539
  %1546 = fmul float %1531, %337
  %1547 = fadd float %1546, %1540
  %1548 = fmul float %1537, %337
  %1549 = fadd float %1548, %1541
  %1550 = call float @llvm.AMDIL.clamp.(float %1543, float 0.000000e+00, float 1.000000e+00)
  %1551 = call float @llvm.AMDIL.clamp.(float %1545, float 0.000000e+00, float 1.000000e+00)
  %1552 = call float @llvm.AMDIL.clamp.(float %1547, float 0.000000e+00, float 1.000000e+00)
  %1553 = call float @llvm.AMDIL.clamp.(float %1549, float 0.000000e+00, float 1.000000e+00)
  %1554 = fmul float %1550, 1.000000e+00
  %1555 = fmul float %1551, 1.000000e+00
  %1556 = fadd float %1554, %1555
  %1557 = fmul float %1552, 1.000000e+00
  %1558 = fadd float %1556, %1557
  %1559 = fmul float %1553, 1.000000e+00
  %1560 = fadd float %1558, %1559
  %1561 = fadd float %1140, %1560
  %1562 = fcmp oge float %1451, 0.000000e+00
  %1563 = sext i1 %1562 to i32
  %1564 = bitcast i32 %1563 to float
  %1565 = bitcast float %1564 to i32
  %1566 = and i32 %1565, 1065353216
  %1567 = bitcast i32 %1566 to float
  %1568 = fcmp oge float %1453, 0.000000e+00
  %1569 = sext i1 %1568 to i32
  %1570 = bitcast i32 %1569 to float
  %1571 = bitcast float %1570 to i32
  %1572 = and i32 %1571, 1065353216
  %1573 = bitcast i32 %1572 to float
  %1574 = fcmp oge float %1455, 0.000000e+00
  %1575 = sext i1 %1574 to i32
  %1576 = bitcast i32 %1575 to float
  %1577 = bitcast float %1576 to i32
  %1578 = and i32 %1577, 1065353216
  %1579 = bitcast i32 %1578 to float
  %1580 = fcmp oge float %1457, 0.000000e+00
  %1581 = sext i1 %1580 to i32
  %1582 = bitcast i32 %1581 to float
  %1583 = bitcast float %1582 to i32
  %1584 = and i32 %1583, 1065353216
  %1585 = bitcast i32 %1584 to float
  %1586 = fsub float -0.000000e+00, %1550
  %1587 = fadd float 1.000000e+00, %1586
  %1588 = fsub float -0.000000e+00, %1551
  %1589 = fadd float 1.000000e+00, %1588
  %1590 = fsub float -0.000000e+00, %1552
  %1591 = fadd float 1.000000e+00, %1590
  %1592 = fsub float -0.000000e+00, %1553
  %1593 = fadd float 1.000000e+00, %1592
  %1594 = fmul float %1567, %1587
  %1595 = fmul float %1573, %1589
  %1596 = fmul float %1579, %1591
  %1597 = fmul float %1585, %1593
  %1598 = fmul float %1594, 1.000000e+00
  %1599 = fmul float %1595, 1.000000e+00
  %1600 = fadd float %1598, %1599
  %1601 = fmul float %1596, 1.000000e+00
  %1602 = fadd float %1600, %1601
  %1603 = fmul float %1597, 1.000000e+00
  %1604 = fadd float %1602, %1603
  %1605 = fadd float %1184, %1604
  %1606 = fmul float %331, 4.000000e+00
  %1607 = fsub float -0.000000e+00, %1606
  %1608 = fadd float %1187, %1607
  %1609 = fsub float -0.000000e+00, %1606
  %1610 = fadd float %1189, %1609
  %1611 = fsub float -0.000000e+00, %1606
  %1612 = fadd float %1191, %1611
  %1613 = fsub float -0.000000e+00, %1606
  %1614 = fadd float %1193, %1613
  %1615 = fmul float %311, %82
  %1616 = fmul float %312, %83
  %1617 = fadd float %1616, %1615
  %1618 = fmul float %313, %84
  %1619 = fadd float %1617, %1618
  %1620 = fmul float %1619, %311
  %1621 = fmul float %1619, %312
  %1622 = fmul float %1619, %313
  %1623 = fmul float 2.000000e+00, %1620
  %1624 = fmul float 2.000000e+00, %1621
  %1625 = fmul float 2.000000e+00, %1622
  %1626 = fsub float -0.000000e+00, %1623
  %1627 = fadd float %82, %1626
  %1628 = fsub float -0.000000e+00, %1624
  %1629 = fadd float %83, %1628
  %1630 = fsub float -0.000000e+00, %1625
  %1631 = fadd float %84, %1630
  %1632 = fmul float %1627, %1608
  %1633 = fmul float %1629, %1608
  %1634 = fmul float %1631, %1608
  %1635 = fmul float %311, %85
  %1636 = fmul float %312, %86
  %1637 = fadd float %1636, %1635
  %1638 = fmul float %313, %87
  %1639 = fadd float %1637, %1638
  %1640 = fmul float %1639, %311
  %1641 = fmul float %1639, %312
  %1642 = fmul float %1639, %313
  %1643 = fmul float 2.000000e+00, %1640
  %1644 = fmul float 2.000000e+00, %1641
  %1645 = fmul float 2.000000e+00, %1642
  %1646 = fsub float -0.000000e+00, %1643
  %1647 = fadd float %85, %1646
  %1648 = fsub float -0.000000e+00, %1644
  %1649 = fadd float %86, %1648
  %1650 = fsub float -0.000000e+00, %1645
  %1651 = fadd float %87, %1650
  %1652 = fmul float %1647, %1610
  %1653 = fmul float %1649, %1610
  %1654 = fmul float %1651, %1610
  %1655 = fmul float %311, %88
  %1656 = fmul float %312, %89
  %1657 = fadd float %1656, %1655
  %1658 = fmul float %313, %90
  %1659 = fadd float %1657, %1658
  %1660 = fmul float %1659, %311
  %1661 = fmul float %1659, %312
  %1662 = fmul float %1659, %313
  %1663 = fmul float 2.000000e+00, %1660
  %1664 = fmul float 2.000000e+00, %1661
  %1665 = fmul float 2.000000e+00, %1662
  %1666 = fsub float -0.000000e+00, %1663
  %1667 = fadd float %88, %1666
  %1668 = fsub float -0.000000e+00, %1664
  %1669 = fadd float %89, %1668
  %1670 = fsub float -0.000000e+00, %1665
  %1671 = fadd float %90, %1670
  %1672 = fmul float %1667, %1612
  %1673 = fmul float %1669, %1612
  %1674 = fmul float %1671, %1612
  %1675 = fmul float %311, %91
  %1676 = fmul float %312, %92
  %1677 = fadd float %1676, %1675
  %1678 = fmul float %313, %93
  %1679 = fadd float %1677, %1678
  %1680 = fmul float %1679, %311
  %1681 = fmul float %1679, %312
  %1682 = fmul float %1679, %313
  %1683 = fmul float 2.000000e+00, %1680
  %1684 = fmul float 2.000000e+00, %1681
  %1685 = fmul float 2.000000e+00, %1682
  %1686 = fsub float -0.000000e+00, %1683
  %1687 = fadd float %91, %1686
  %1688 = fsub float -0.000000e+00, %1684
  %1689 = fadd float %92, %1688
  %1690 = fsub float -0.000000e+00, %1685
  %1691 = fadd float %93, %1690
  %1692 = fmul float %1687, %1614
  %1693 = fmul float %1689, %1614
  %1694 = fmul float %1691, %1614
  %1695 = fmul float %1632, %278
  %1696 = fmul float %1633, %279
  %1697 = fadd float %1696, %1695
  %1698 = fmul float %1634, %280
  %1699 = fadd float %1697, %1698
  %1700 = fmul float %1652, %278
  %1701 = fmul float %1653, %279
  %1702 = fadd float %1701, %1700
  %1703 = fmul float %1654, %280
  %1704 = fadd float %1702, %1703
  %1705 = fmul float %1672, %278
  %1706 = fmul float %1673, %279
  %1707 = fadd float %1706, %1705
  %1708 = fmul float %1674, %280
  %1709 = fadd float %1707, %1708
  %1710 = fmul float %1692, %278
  %1711 = fmul float %1693, %279
  %1712 = fadd float %1711, %1710
  %1713 = fmul float %1694, %280
  %1714 = fadd float %1712, %1713
  %1715 = fcmp oge float %1699, 0.000000e+00
  %1716 = sext i1 %1715 to i32
  %1717 = bitcast i32 %1716 to float
  %1718 = bitcast float %1717 to i32
  %1719 = icmp ne i32 %1718, 0
  %temp4.0 = select i1 %1719, float 0x36A0000000000000, float 0xFFFFFFFFE0000000
  %1720 = bitcast float %temp4.0 to i32
  %1721 = sitofp i32 %1720 to float
  %1722 = fmul float %1632, %1721
  %1723 = fmul float %1633, %1721
  %1724 = fmul float %1634, %1721
  %1725 = fcmp oge float %1704, 0.000000e+00
  %1726 = sext i1 %1725 to i32
  %1727 = bitcast i32 %1726 to float
  %1728 = bitcast float %1727 to i32
  %1729 = icmp ne i32 %1728, 0
  %.228 = select i1 %1729, float 0x36A0000000000000, float 0xFFFFFFFFE0000000
  %1730 = bitcast float %.228 to i32
  %1731 = sitofp i32 %1730 to float
  %1732 = fmul float %1652, %1731
  %1733 = fmul float %1653, %1731
  %1734 = fmul float %1654, %1731
  %1735 = fcmp oge float %1709, 0.000000e+00
  %1736 = sext i1 %1735 to i32
  %1737 = bitcast i32 %1736 to float
  %1738 = bitcast float %1737 to i32
  %1739 = icmp ne i32 %1738, 0
  %temp4.2 = select i1 %1739, float 0x36A0000000000000, float 0xFFFFFFFFE0000000
  %1740 = bitcast float %temp4.2 to i32
  %1741 = sitofp i32 %1740 to float
  %1742 = fmul float %1672, %1741
  %1743 = fmul float %1673, %1741
  %1744 = fmul float %1674, %1741
  %1745 = fcmp oge float %1714, 0.000000e+00
  %1746 = sext i1 %1745 to i32
  %1747 = bitcast i32 %1746 to float
  %1748 = bitcast float %1747 to i32
  %1749 = icmp ne i32 %1748, 0
  %.229 = select i1 %1749, float 0x36A0000000000000, float 0xFFFFFFFFE0000000
  %1750 = bitcast float %.229 to i32
  %1751 = sitofp i32 %1750 to float
  %1752 = fmul float %1692, %1751
  %1753 = fmul float %1693, %1751
  %1754 = fmul float %1694, %1751
  %1755 = fadd float %288, %1722
  %1756 = fadd float %290, %1723
  %1757 = fadd float %288, %1732
  %1758 = fadd float %290, %1733
  %1759 = fadd float %288, %1742
  %1760 = fadd float %290, %1743
  %1761 = fadd float %288, %1752
  %1762 = fadd float %290, %1753
  %1763 = fadd float %292, %1724
  %1764 = fadd float %292, %1734
  %1765 = fadd float %292, %1744
  %1766 = fadd float %292, %1754
  %1767 = fsub float -0.000000e+00, %1763
  %1768 = fdiv float 1.000000e+00, %1767
  %1769 = fsub float -0.000000e+00, %1764
  %1770 = fdiv float 1.000000e+00, %1769
  %1771 = fmul float %1755, %1768
  %1772 = fmul float %1756, %1768
  %1773 = fmul float %1757, %1770
  %1774 = fmul float %1758, %1770
  %1775 = fsub float -0.000000e+00, %30
  %1776 = fmul float %1771, %29
  %1777 = fadd float %1776, %1775
  %1778 = fsub float -0.000000e+00, %32
  %1779 = fmul float %1772, %31
  %1780 = fadd float %1779, %1778
  %1781 = fsub float -0.000000e+00, %30
  %1782 = fmul float %1773, %29
  %1783 = fadd float %1782, %1781
  %1784 = fsub float -0.000000e+00, %32
  %1785 = fmul float %1774, %31
  %1786 = fadd float %1785, %1784
  %1787 = fsub float -0.000000e+00, %1765
  %1788 = fdiv float 1.000000e+00, %1787
  %1789 = fsub float -0.000000e+00, %1766
  %1790 = fdiv float 1.000000e+00, %1789
  %1791 = fmul float %1759, %1788
  %1792 = fmul float %1760, %1788
  %1793 = fmul float %1761, %1790
  %1794 = fmul float %1762, %1790
  %1795 = fsub float -0.000000e+00, %30
  %1796 = fmul float %1791, %29
  %1797 = fadd float %1796, %1795
  %1798 = fsub float -0.000000e+00, %32
  %1799 = fmul float %1792, %31
  %1800 = fadd float %1799, %1798
  %1801 = fsub float -0.000000e+00, %30
  %1802 = fmul float %1793, %29
  %1803 = fadd float %1802, %1801
  %1804 = fsub float -0.000000e+00, %32
  %1805 = fmul float %1794, %31
  %1806 = fadd float %1805, %1804
  %1807 = fmul float %1777, 5.000000e-01
  %1808 = fadd float %1807, 5.000000e-01
  %1809 = fmul float %1780, -5.000000e-01
  %1810 = fadd float %1809, 5.000000e-01
  %1811 = fmul float %1783, 5.000000e-01
  %1812 = fadd float %1811, 5.000000e-01
  %1813 = fmul float %1786, -5.000000e-01
  %1814 = fadd float %1813, 5.000000e-01
  %1815 = fmul float %1797, 5.000000e-01
  %1816 = fadd float %1815, 5.000000e-01
  %1817 = fmul float %1800, -5.000000e-01
  %1818 = fadd float %1817, 5.000000e-01
  %1819 = fmul float %1803, 5.000000e-01
  %1820 = fadd float %1819, 5.000000e-01
  %1821 = fmul float %1806, -5.000000e-01
  %1822 = fadd float %1821, 5.000000e-01
  %1823 = call float @llvm.AMDIL.clamp.(float %1808, float 0.000000e+00, float 1.000000e+00)
  %1824 = call float @llvm.AMDIL.clamp.(float %1810, float 0.000000e+00, float 1.000000e+00)
  %1825 = call float @llvm.AMDIL.clamp.(float %1812, float 0.000000e+00, float 1.000000e+00)
  %1826 = call float @llvm.AMDIL.clamp.(float %1814, float 0.000000e+00, float 1.000000e+00)
  %1827 = call float @llvm.AMDIL.clamp.(float %1816, float 0.000000e+00, float 1.000000e+00)
  %1828 = call float @llvm.AMDIL.clamp.(float %1818, float 0.000000e+00, float 1.000000e+00)
  %1829 = call float @llvm.AMDIL.clamp.(float %1820, float 0.000000e+00, float 1.000000e+00)
  %1830 = call float @llvm.AMDIL.clamp.(float %1822, float 0.000000e+00, float 1.000000e+00)
  %1831 = bitcast float %1823 to i32
  %1832 = bitcast float %1824 to i32
  %1833 = insertelement <2 x i32> undef, i32 %1831, i32 0
  %1834 = insertelement <2 x i32> %1833, i32 %1832, i32 1
  %1835 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1834, <32 x i8> %95, <16 x i8> %97, i32 2)
  %1836 = extractelement <4 x float> %1835, i32 0
  %1837 = bitcast float %1825 to i32
  %1838 = bitcast float %1826 to i32
  %1839 = insertelement <2 x i32> undef, i32 %1837, i32 0
  %1840 = insertelement <2 x i32> %1839, i32 %1838, i32 1
  %1841 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1840, <32 x i8> %95, <16 x i8> %97, i32 2)
  %1842 = extractelement <4 x float> %1841, i32 0
  %1843 = bitcast float %1827 to i32
  %1844 = bitcast float %1828 to i32
  %1845 = insertelement <2 x i32> undef, i32 %1843, i32 0
  %1846 = insertelement <2 x i32> %1845, i32 %1844, i32 1
  %1847 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1846, <32 x i8> %95, <16 x i8> %97, i32 2)
  %1848 = extractelement <4 x float> %1847, i32 0
  %1849 = bitcast float %1829 to i32
  %1850 = bitcast float %1830 to i32
  %1851 = insertelement <2 x i32> undef, i32 %1849, i32 0
  %1852 = insertelement <2 x i32> %1851, i32 %1850, i32 1
  %1853 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1852, <32 x i8> %95, <16 x i8> %97, i32 2)
  %1854 = extractelement <4 x float> %1853, i32 0
  %1855 = call float @fabs(float %1836)
  %1856 = call float @fabs(float %1842)
  %1857 = call float @fabs(float %1848)
  %1858 = call float @fabs(float %1854)
  %1859 = fsub float -0.000000e+00, %27
  %1860 = fmul float %1855, %28
  %1861 = fadd float %1860, %1859
  %1862 = fsub float -0.000000e+00, %27
  %1863 = fmul float %1856, %28
  %1864 = fadd float %1863, %1862
  %1865 = fsub float -0.000000e+00, %27
  %1866 = fmul float %1857, %28
  %1867 = fadd float %1866, %1865
  %1868 = fsub float -0.000000e+00, %27
  %1869 = fmul float %1858, %28
  %1870 = fadd float %1869, %1868
  %1871 = fsub float -0.000000e+00, %1763
  %1872 = fadd float %1861, %1871
  %1873 = fsub float -0.000000e+00, %1764
  %1874 = fadd float %1864, %1873
  %1875 = fsub float -0.000000e+00, %1765
  %1876 = fadd float %1867, %1875
  %1877 = fsub float -0.000000e+00, %1766
  %1878 = fadd float %1870, %1877
  %1879 = fmul float %1608, 2.000000e+00
  %1880 = fmul float %1610, 2.000000e+00
  %1881 = fmul float %1612, 2.000000e+00
  %1882 = fmul float %1614, 2.000000e+00
  %1883 = fcmp oge float %1872, %1879
  %1884 = sext i1 %1883 to i32
  %1885 = bitcast i32 %1884 to float
  %1886 = bitcast float %1885 to i32
  %1887 = and i32 %1886, 1065353216
  %1888 = bitcast i32 %1887 to float
  %1889 = fcmp oge float %1874, %1880
  %1890 = sext i1 %1889 to i32
  %1891 = bitcast i32 %1890 to float
  %1892 = bitcast float %1891 to i32
  %1893 = and i32 %1892, 1065353216
  %1894 = bitcast i32 %1893 to float
  %1895 = fcmp oge float %1876, %1881
  %1896 = sext i1 %1895 to i32
  %1897 = bitcast i32 %1896 to float
  %1898 = bitcast float %1897 to i32
  %1899 = and i32 %1898, 1065353216
  %1900 = bitcast i32 %1899 to float
  %1901 = fcmp oge float %1878, %1882
  %1902 = sext i1 %1901 to i32
  %1903 = bitcast i32 %1902 to float
  %1904 = bitcast float %1903 to i32
  %1905 = and i32 %1904, 1065353216
  %1906 = bitcast i32 %1905 to float
  %1907 = fcmp oeq float %1861, 0.000000e+00
  %1908 = sext i1 %1907 to i32
  %1909 = bitcast i32 %1908 to float
  %1910 = bitcast float %1909 to i32
  %1911 = icmp ne i32 %1910, 0
  %temp12.0 = select i1 %1911, float 0x36A0000000000000, float 0.000000e+00
  %1912 = fcmp oeq float %1864, 0.000000e+00
  %1913 = sext i1 %1912 to i32
  %1914 = bitcast i32 %1913 to float
  %1915 = bitcast float %1914 to i32
  %1916 = icmp ne i32 %1915, 0
  %.230 = select i1 %1916, float 0x36A0000000000000, float 0.000000e+00
  %1917 = fcmp oeq float %1867, 0.000000e+00
  %1918 = sext i1 %1917 to i32
  %1919 = bitcast i32 %1918 to float
  %1920 = bitcast float %1919 to i32
  %1921 = icmp ne i32 %1920, 0
  %temp48.4 = select i1 %1921, float 0x36A0000000000000, float 0.000000e+00
  %1922 = fcmp oeq float %1870, 0.000000e+00
  %1923 = sext i1 %1922 to i32
  %1924 = bitcast i32 %1923 to float
  %1925 = bitcast float %1924 to i32
  %1926 = icmp ne i32 %1925, 0
  %.231 = select i1 %1926, float 0x36A0000000000000, float 0.000000e+00
  %1927 = bitcast float %temp12.0 to i32
  %1928 = sitofp i32 %1927 to float
  %1929 = bitcast float %.230 to i32
  %1930 = sitofp i32 %1929 to float
  %1931 = bitcast float %temp48.4 to i32
  %1932 = sitofp i32 %1931 to float
  %1933 = bitcast float %.231 to i32
  %1934 = sitofp i32 %1933 to float
  %1935 = fcmp oge float 0.000000e+00, %1836
  %1936 = sext i1 %1935 to i32
  %1937 = bitcast i32 %1936 to float
  %1938 = bitcast float %1937 to i32
  %1939 = and i32 %1938, 1065353216
  %1940 = bitcast i32 %1939 to float
  %1941 = fcmp oge float 0.000000e+00, %1842
  %1942 = sext i1 %1941 to i32
  %1943 = bitcast i32 %1942 to float
  %1944 = bitcast float %1943 to i32
  %1945 = and i32 %1944, 1065353216
  %1946 = bitcast i32 %1945 to float
  %1947 = fcmp oge float 0.000000e+00, %1848
  %1948 = sext i1 %1947 to i32
  %1949 = bitcast i32 %1948 to float
  %1950 = bitcast float %1949 to i32
  %1951 = and i32 %1950, 1065353216
  %1952 = bitcast i32 %1951 to float
  %1953 = fcmp oge float 0.000000e+00, %1854
  %1954 = sext i1 %1953 to i32
  %1955 = bitcast i32 %1954 to float
  %1956 = bitcast float %1955 to i32
  %1957 = and i32 %1956, 1065353216
  %1958 = bitcast i32 %1957 to float
  %1959 = fadd float %1888, %1928
  %1960 = fadd float %1894, %1930
  %1961 = fadd float %1900, %1932
  %1962 = fadd float %1906, %1934
  %1963 = fmul float %1940, %337
  %1964 = fadd float %1963, %1959
  %1965 = fmul float %1946, %337
  %1966 = fadd float %1965, %1960
  %1967 = fmul float %1952, %337
  %1968 = fadd float %1967, %1961
  %1969 = fmul float %1958, %337
  %1970 = fadd float %1969, %1962
  %1971 = call float @llvm.AMDIL.clamp.(float %1964, float 0.000000e+00, float 1.000000e+00)
  %1972 = call float @llvm.AMDIL.clamp.(float %1966, float 0.000000e+00, float 1.000000e+00)
  %1973 = call float @llvm.AMDIL.clamp.(float %1968, float 0.000000e+00, float 1.000000e+00)
  %1974 = call float @llvm.AMDIL.clamp.(float %1970, float 0.000000e+00, float 1.000000e+00)
  %1975 = fmul float %1971, 1.000000e+00
  %1976 = fmul float %1972, 1.000000e+00
  %1977 = fadd float %1975, %1976
  %1978 = fmul float %1973, 1.000000e+00
  %1979 = fadd float %1977, %1978
  %1980 = fmul float %1974, 1.000000e+00
  %1981 = fadd float %1979, %1980
  %1982 = fadd float %1561, %1981
  %1983 = fcmp oge float %1872, 0.000000e+00
  %1984 = sext i1 %1983 to i32
  %1985 = bitcast i32 %1984 to float
  %1986 = bitcast float %1985 to i32
  %1987 = and i32 %1986, 1065353216
  %1988 = bitcast i32 %1987 to float
  %1989 = fcmp oge float %1874, 0.000000e+00
  %1990 = sext i1 %1989 to i32
  %1991 = bitcast i32 %1990 to float
  %1992 = bitcast float %1991 to i32
  %1993 = and i32 %1992, 1065353216
  %1994 = bitcast i32 %1993 to float
  %1995 = fcmp oge float %1876, 0.000000e+00
  %1996 = sext i1 %1995 to i32
  %1997 = bitcast i32 %1996 to float
  %1998 = bitcast float %1997 to i32
  %1999 = and i32 %1998, 1065353216
  %2000 = bitcast i32 %1999 to float
  %2001 = fcmp oge float %1878, 0.000000e+00
  %2002 = sext i1 %2001 to i32
  %2003 = bitcast i32 %2002 to float
  %2004 = bitcast float %2003 to i32
  %2005 = and i32 %2004, 1065353216
  %2006 = bitcast i32 %2005 to float
  %2007 = fsub float -0.000000e+00, %1971
  %2008 = fadd float 1.000000e+00, %2007
  %2009 = fsub float -0.000000e+00, %1972
  %2010 = fadd float 1.000000e+00, %2009
  %2011 = fsub float -0.000000e+00, %1973
  %2012 = fadd float 1.000000e+00, %2011
  %2013 = fsub float -0.000000e+00, %1974
  %2014 = fadd float 1.000000e+00, %2013
  %2015 = fmul float %1988, %2008
  %2016 = fmul float %1994, %2010
  %2017 = fmul float %2000, %2012
  %2018 = fmul float %2006, %2014
  %2019 = fmul float %2015, 1.000000e+00
  %2020 = fmul float %2016, 1.000000e+00
  %2021 = fadd float %2019, %2020
  %2022 = fmul float %2017, 1.000000e+00
  %2023 = fadd float %2021, %2022
  %2024 = fmul float %2018, 1.000000e+00
  %2025 = fadd float %2023, %2024
  %2026 = fadd float %1605, %2025
  %2027 = fsub float -0.000000e+00, %1982
  %2028 = fadd float 1.600000e+01, %2027
  %2029 = fdiv float 1.000000e+00, %2028
  %2030 = fmul float %2026, %2029
  br label %ENDIF

ENDIF:                                            ; preds = %main_body, %IF
  %temp.0 = phi float [ %2030, %IF ], [ 0.000000e+00, %main_body ]
  %2031 = fmul float %temp.0, %44
  %2032 = call float @llvm.AMDIL.clamp.(float %2031, float 0.000000e+00, float 1.000000e+00)
  %2033 = fsub float -0.000000e+00, %2032
  %2034 = fadd float 1.000000e+00, %2033
  %2035 = fmul float %2034, %2034
  %2036 = call i32 @llvm.SI.packf16(float 0.000000e+00, float 0.000000e+00)
  %2037 = bitcast i32 %2036 to float
  %2038 = call i32 @llvm.SI.packf16(float 0.000000e+00, float %2035)
  %2039 = bitcast i32 %2038 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %2037, float %2039, float %2037, float %2039)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.fraction.(float) #2

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readonly
declare float @fabs(float) #3

; Function Attrs: readnone
declare float @llvm.AMDGPU.rsq(float) #2

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }
attributes #3 = { readonly }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg12, %SGPR2_SGPR3 in %vreg13, %SGPR4_SGPR5 in %vreg14, %SGPR7 in %vreg16, %VGPR0 in %vreg17, %VGPR1 in %vreg18

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR7 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR7
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<kill,tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>
	%SGPR20_SGPR21_SGPR22_SGPR23<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%22](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 17; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR2<kill>, %SGPR0<kill>, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_FRACT_F32_e32 %VGPR2, %EXEC<imp-use>
	%VGPR2<def> = V_SUB_F32_e32 %VGPR2<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_ADD_F32_e32 5.000000e-01, %VGPR2<kill>, %EXEC<imp-use>
	%SGPR6<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 19; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR6, %VGPR2<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-def>
	%VGPR4<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR4<def,tied1> = V_INTERP_P2_F32 %VGPR4<kill,tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 16; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR0<def> = V_MAD_F32 %VGPR4<kill>, %SGPR0<kill>, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_FRACT_F32_e32 %VGPR0, %EXEC<imp-use>
	%VGPR0<def> = V_SUB_F32_e32 %VGPR0<kill>, %VGPR1<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_F32_e32 5.000000e-01, %VGPR0<kill>, %EXEC<imp-use>
	%SGPR7<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 18; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR7, %VGPR0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 0; mem:LD16[%33](align=8)(tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 0; mem:LD32[%30](tbaa=!"const")
	S_WAITCNT 127
	%VGPR1<def> = IMAGE_SAMPLE_V1_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	%VGPR0<def> = V_MOV_B32_e32 9.500000e-01, %EXEC<imp-use>
	S_WAITCNT 1904
	%SGPR0_SGPR1<def> = V_CMP_LT_F32_e64 %VGPR1, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR24<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 25; mem:LD4[<unknown>]
	%VGPR4<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	S_WAITCNT 127
	%VGPR0<def> = V_MOV_B32_e32 %SGPR24<kill>, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_AND_SAVEEXEC_B64 %SGPR0_SGPR1, %EXEC<imp-def>, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_XOR_B64 %EXEC, %SGPR0_SGPR1
	S_CBRANCH_EXECZ <BB#2>, %EXEC
    Successors according to CFG: BB#1(16) BB#2(16)

BB#1: derived from LLVM BB %IF
    Live Ins: %SGPR20_SGPR21_SGPR22_SGPR23 %SGPR7 %SGPR6 %VGPR0 %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %VGPR2_VGPR3 %SGPR0_SGPR1
    Predecessors according to CFG: BB#0
	%VGPR4<def> = V_ADD_F32_e64 %VGPR1, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR24<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 5; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR4<def> = V_MUL_F32_e32 %SGPR24, %VGPR4<kill>, %EXEC<imp-use>
	%SGPR25<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 4; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR4<def> = V_SUBREV_F32_e32 %SGPR25, %VGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MOV_B32_e32 %SGPR7<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_ADD_F32_e64 %VGPR2, %VGPR5, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR6_VGPR7<imp-def>
	%VGPR7<def> = V_ADD_F32_e64 %VGPR3, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR6_VGPR7<imp-use,kill>, %VGPR6_VGPR7<imp-def>
	%VGPR8<def> = IMAGE_SAMPLE_V1_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR6_VGPR7, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR8<def> = V_ADD_F32_e64 %VGPR8<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_F32_e32 %SGPR24, %VGPR8<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_SUBREV_F32_e32 %SGPR25, %VGPR8<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_SUB_F32_e32 %VGPR8, %VGPR4, %EXEC<imp-use>
	%VGPR9<def> = V_ADD_F32_e64 %VGPR9<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%VGPR10<def> = V_SUB_F32_e64 %VGPR2, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR10_VGPR11<imp-def>
	%VGPR11<def> = V_MOV_B32_e32 %VGPR7, %EXEC<imp-use>, %VGPR10_VGPR11<imp-def>
	%VGPR5<def> = IMAGE_SAMPLE_V1_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR10_VGPR11, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR5<def> = V_ADD_F32_e64 %VGPR5<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_MUL_F32_e32 %SGPR24, %VGPR5<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_SUBREV_F32_e32 %SGPR25, %VGPR5<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_SUB_F32_e32 %VGPR5, %VGPR4, %EXEC<imp-use>
	%VGPR12<def> = V_ADD_F32_e64 %VGPR12<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR26_SGPR27<def> = V_CMP_LT_F32_e64 %VGPR12<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_CNDMASK_B32_e64 %VGPR8<kill>, %VGPR5<kill>, %SGPR26_SGPR27, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_SUB_F32_e32 %VGPR5, %VGPR4, %EXEC<imp-use>
	%VGPR9<def> = V_CNDMASK_B32_e64 1.000000e+00, -1.000000e+00, %SGPR26_SGPR27, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_F32_e32 %VGPR8<kill>, %VGPR9, %EXEC<imp-use>
	%VGPR12<def> = V_MOV_B32_e32 %SGPR6<kill>, %EXEC<imp-use>
	%VGPR14<def> = V_ADD_F32_e64 %VGPR3, %VGPR12, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR13_VGPR14<imp-def>
	%VGPR13<def> = V_ADD_F32_e64 %VGPR2, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR13_VGPR14<imp-use,kill>, %VGPR13_VGPR14<imp-def>
	%VGPR15<def> = IMAGE_SAMPLE_V1_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR13_VGPR14, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR15<def> = V_ADD_F32_e64 %VGPR15<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%VGPR15<def> = V_MUL_F32_e32 %SGPR24, %VGPR15<kill>, %EXEC<imp-use>
	%VGPR15<def> = V_SUBREV_F32_e32 %SGPR25, %VGPR15<kill>, %EXEC<imp-use>
	%VGPR16<def> = V_SUB_F32_e32 %VGPR15, %VGPR4, %EXEC<imp-use>
	%VGPR16<def> = V_ADD_F32_e64 %VGPR16<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_SUB_F32_e64 %VGPR3, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR17<def> = V_MOV_B32_e32 %VGPR13, %EXEC<imp-use>, %VGPR17_VGPR18<imp-def>
	%VGPR18<def> = V_MOV_B32_e32 %VGPR14, %EXEC<imp-use>
	%VGPR18<def> = V_MOV_B32_e32 %VGPR12, %EXEC<imp-use>, %VGPR17_VGPR18<imp-def>
	%VGPR17<def> = IMAGE_SAMPLE_V1_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR17_VGPR18<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR17<def> = V_ADD_F32_e64 %VGPR17<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%VGPR17<def> = V_MUL_F32_e32 %SGPR24, %VGPR17<kill>, %EXEC<imp-use>
	%VGPR17<def> = V_SUBREV_F32_e32 %SGPR25, %VGPR17<kill>, %EXEC<imp-use>
	%VGPR18<def> = V_SUB_F32_e32 %VGPR17, %VGPR4, %EXEC<imp-use>
	%VGPR18<def> = V_ADD_F32_e64 %VGPR18<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_LT_F32_e64 %VGPR18<kill>, %VGPR16<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR15<def> = V_CNDMASK_B32_e64 %VGPR15<kill>, %VGPR17<kill>, %SGPR6_SGPR7, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR16<def> = V_ADD_F32_e64 %VGPR15, 0, 0, 0, 0, 1, %EXEC<imp-use>
	%SGPR28<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 9; mem:LD4[<unknown>]
	%VGPR17<def> = V_ADD_F32_e32 %VGPR13, %VGPR13, %EXEC<imp-use>
	%VGPR17<def> = V_ADD_F32_e32 -1.000000e+00, %VGPR17<kill>, %EXEC<imp-use>
	S_WAITCNT 127
	%VGPR17<def> = V_ADD_F32_e32 %SGPR28, %VGPR17<kill>, %EXEC<imp-use>
	%VGPR17<def> = V_MUL_F32_e32 %VGPR16, %VGPR17<kill>, %EXEC<imp-use>
	%SGPR29<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 8; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR18<def> = V_RCP_F32_e32 %SGPR29, %EXEC<imp-use>
	%VGPR17<def> = V_MUL_F32_e32 %VGPR17<kill>, %VGPR18, %EXEC<imp-use>
	%VGPR19<def> = V_ADD_F32_e64 %VGPR2, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR19<def> = V_ADD_F32_e32 -1.000000e+00, %VGPR19<kill>, %EXEC<imp-use>
	%VGPR19<def> = V_ADD_F32_e32 %SGPR28, %VGPR19<kill>, %EXEC<imp-use>
	%VGPR20<def> = V_ADD_F32_e64 %VGPR4, 0, 0, 0, 0, 1, %EXEC<imp-use>
	%VGPR19<def> = V_MUL_F32_e32 %VGPR20, %VGPR19<kill>, %EXEC<imp-use>
	%VGPR19<def> = V_MUL_F32_e32 %VGPR19<kill>, %VGPR18, %EXEC<imp-use>
	%VGPR17<def> = V_SUB_F32_e32 %VGPR17<kill>, %VGPR19, %EXEC<imp-use>
	%VGPR21<def> = V_CNDMASK_B32_e64 1.000000e+00, -1.000000e+00, %SGPR6_SGPR7, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR17<def> = V_MUL_F32_e32 %VGPR17<kill>, %VGPR21, %EXEC<imp-use>
	%VGPR22<def> = V_MUL_F32_e32 %VGPR17, %VGPR8, %EXEC<imp-use>
	%VGPR15<def> = V_SUB_F32_e32 %VGPR15<kill>, %VGPR4, %EXEC<imp-use>
	%VGPR15<def> = V_MUL_F32_e32 %VGPR15<kill>, %VGPR21, %EXEC<imp-use>
	%VGPR10<def> = V_CNDMASK_B32_e64 %VGPR6, %VGPR10, %SGPR26_SGPR27<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR10_VGPR11<imp-use,kill>
	%VGPR10<def> = V_ADD_F32_e32 %VGPR10<kill>, %VGPR10, %EXEC<imp-use>
	%VGPR10<def> = V_ADD_F32_e32 -1.000000e+00, %VGPR10<kill>, %EXEC<imp-use>
	%VGPR10<def> = V_ADD_F32_e32 %SGPR28, %VGPR10<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_ADD_F32_e64 %VGPR5<kill>, 0, 0, 0, 0, 1, %EXEC<imp-use>
	%VGPR10<def> = V_MUL_F32_e32 %VGPR5, %VGPR10<kill>, %EXEC<imp-use>
	%VGPR10<def> = V_MUL_F32_e32 %VGPR10<kill>, %VGPR18<kill>, %EXEC<imp-use>
	%VGPR10<def> = V_SUB_F32_e32 %VGPR10<kill>, %VGPR19, %EXEC<imp-use>
	%VGPR10<def> = V_MUL_F32_e32 %VGPR10<kill>, %VGPR9, %EXEC<imp-use>
	%VGPR11<def> = V_MUL_F32_e32 %VGPR15, %VGPR10, %EXEC<imp-use>
	%VGPR11<def> = V_SUB_F32_e32 %VGPR11<kill>, %VGPR22<kill>, %EXEC<imp-use>
	%SGPR26<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 11; mem:LD4[<unknown>]
	%VGPR6<def> = V_MAD_F32 %VGPR7, -2.000000e+00, 1.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR6_VGPR7<imp-use,kill>
	S_WAITCNT 127
	%VGPR6<def> = V_ADD_F32_e32 %SGPR26, %VGPR6<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MUL_F32_e32 %VGPR5<kill>, %VGPR6<kill>, %EXEC<imp-use>
	%SGPR27<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 10; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_RCP_F32_e32 %SGPR27, %EXEC<imp-use>
	%VGPR5<def> = V_MUL_F32_e32 %VGPR5<kill>, %VGPR6, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR3, -2.000000e+00, 1.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_ADD_F32_e32 %SGPR26, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MUL_F32_e32 %VGPR20, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MUL_F32_e32 %VGPR7<kill>, %VGPR6, %EXEC<imp-use>
	%VGPR5<def> = V_SUB_F32_e32 %VGPR5<kill>, %VGPR7, %EXEC<imp-use>
	%VGPR5<def> = V_MUL_F32_e32 %VGPR5<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_MUL_F32_e32 %VGPR15<kill>, %VGPR5, %EXEC<imp-use>
	%VGPR12<def> = V_CNDMASK_B32_e64 %VGPR14, %VGPR12<kill>, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR13_VGPR14<imp-use,kill>
	%VGPR12<def> = V_MAD_F32 %VGPR12<kill>, -2.000000e+00, 1.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_ADD_F32_e32 %SGPR26, %VGPR12<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_MUL_F32_e32 %VGPR16<kill>, %VGPR12<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %VGPR12<kill>, %VGPR6<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_SUB_F32_e32 %VGPR6<kill>, %VGPR7, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %VGPR6<kill>, %VGPR21<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_F32_e32 %VGPR6, %VGPR8<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_SUB_F32_e32 %VGPR8<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_MUL_F32_e32 %VGPR8, %VGPR8, %EXEC<imp-use>
	%VGPR9<def> = V_MAD_F32 %VGPR11, %VGPR11, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_MUL_F32_e32 %VGPR17<kill>, %VGPR5<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %VGPR6<kill>, %VGPR10<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_SUB_F32_e32 %VGPR5<kill>, %VGPR6<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR5, %VGPR5, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_RSQ_LEGACY_F32_e32 %VGPR6<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_MUL_F32_e32 %VGPR11<kill>, %VGPR6, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_F32_e32 %VGPR8<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR6<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 13; mem:LD4[<unknown>]
	%VGPR10<def> = V_MOV_B32_e32 2.500000e-01, %EXEC<imp-use>
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR6<kill>, %VGPR10, %EXEC<imp-use>
	%VGPR12<def> = V_MUL_F32_e32 %VGPR3, %VGPR11<kill>, %EXEC<imp-use>, %VGPR11_VGPR12<imp-def>
	%SGPR6<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 12; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR6<kill>, %VGPR10<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_MUL_F32_e32 %VGPR2, %VGPR10<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR11_VGPR12<imp-use,kill>, %VGPR11_VGPR12<imp-def>
	%SGPR32_SGPR33_SGPR34_SGPR35<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 4; mem:LD16[%135](align=8)(tbaa=!"const")
	%SGPR36_SGPR37_SGPR38_SGPR39_SGPR40_SGPR41_SGPR42_SGPR43<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 8; mem:LD32[%132](tbaa=!"const")
	S_WAITCNT 127
	%VGPR10_VGPR11_VGPR12<def> = IMAGE_SAMPLE_V3_V2 7, 0, 0, 0, 0, 0, 0, 0, %VGPR11_VGPR12<kill>, %SGPR36_SGPR37_SGPR38_SGPR39_SGPR40_SGPR41_SGPR42_SGPR43<kill>, %SGPR32_SGPR33_SGPR34_SGPR35<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR2<def> = V_ADD_F32_e32 %VGPR11, %VGPR11, %EXEC<imp-use>
	%VGPR2<def> = V_ADD_F32_e32 -1.000000e+00, %VGPR2<kill>, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 3; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR2, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_ADD_F32_e32 %VGPR10, %VGPR10, %EXEC<imp-use>
	%VGPR3<def> = V_ADD_F32_e32 -1.000000e+00, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_MUL_F32_e32 %SGPR2, %VGPR3<kill>, %EXEC<imp-use>
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 48; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR13<def> = V_MUL_F32_e32 %SGPR3, %VGPR3, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 49; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR13<def> = V_MAD_F32 %VGPR2, %SGPR4, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR10<def> = V_ADD_F32_e32 %VGPR12, %VGPR12, %EXEC<imp-use>, %VGPR10_VGPR11_VGPR12<imp-use,kill>
	%VGPR10<def> = V_ADD_F32_e32 -1.000000e+00, %VGPR10<kill>, %EXEC<imp-use>
	%VGPR10<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR10<kill>, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 50; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %VGPR10, %SGPR2, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_MUL_F32_e32 %VGPR11, %VGPR3, %EXEC<imp-use>
	%VGPR12<def> = V_MAD_F32 %VGPR11, %VGPR3, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_SUB_F32_e32 %SGPR3<kill>, %VGPR12<kill>, %EXEC<imp-use>
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 20; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR13<def> = V_SUBREV_F32_e32 %SGPR3<kill>, %VGPR20, %EXEC<imp-use>
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 23; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR13<def> = V_MUL_F32_e32 %SGPR3<kill>, %VGPR13<kill>, %EXEC<imp-use>
	%VGPR13<def> = V_ADD_F32_e64 0, %VGPR13<kill>, 0, 1, 0, 0, %EXEC<imp-use>
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 22; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR13<def> = V_MAD_F32 %SGPR3<kill>, %VGPR13<kill>, 1.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 21; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR14<def> = V_MUL_F32_e32 %SGPR3<kill>, %VGPR20<kill>, %EXEC<imp-use>
	%VGPR14<def> = V_ADD_F32_e64 0, %VGPR14<kill>, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_MUL_F32_e32 %VGPR13<kill>, %VGPR14<kill>, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_LT_F32_e64 %VGPR1, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 24; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR14<def> = V_MOV_B32_e32 %SGPR3<kill>, %EXEC<imp-use>
	%VGPR13<def> = V_CNDMASK_B32_e64 %VGPR13<kill>, %VGPR14<kill>, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 26; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR13<def> = V_MUL_F32_e32 %SGPR3<kill>, %VGPR13<kill>, %EXEC<imp-use>
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 1; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR14<def> = V_MUL_F32_e32 %SGPR3, %VGPR13, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 0; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR15<def> = V_MUL_F32_e32 %SGPR5, %VGPR13, %EXEC<imp-use>
	%VGPR16<def> = V_SUB_F32_e32 %VGPR15, %VGPR14, %EXEC<imp-use>
	%VGPR17<def> = V_MAD_F32 %VGPR14, -4.000000e+00, %VGPR16, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_MUL_F32_e32 %VGPR12<kill>, %VGPR17, %EXEC<imp-use>
	%VGPR18<def> = V_MUL_F32_e32 %VGPR12, %VGPR8, %EXEC<imp-use>
	%VGPR20<def> = V_MUL_F32_e32 %VGPR11, %VGPR2, %EXEC<imp-use>
	%VGPR20<def> = V_MAD_F32 %VGPR11, %VGPR2, %VGPR20<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR20<def> = V_SUB_F32_e32 %SGPR4<kill>, %VGPR20<kill>, %EXEC<imp-use>
	%VGPR20<def> = V_MUL_F32_e32 %VGPR20<kill>, %VGPR17, %EXEC<imp-use>
	%VGPR18<def> = V_MAD_F32 %VGPR20, %VGPR9, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_MUL_F32_e32 %VGPR5<kill>, %VGPR6<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %VGPR11, %VGPR10, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR11<kill>, %VGPR10, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_SUB_F32_e32 %SGPR2<kill>, %VGPR6<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %VGPR6<kill>, %VGPR17, %EXEC<imp-use>
	%VGPR11<def> = V_MAD_F32 %VGPR6, %VGPR5, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %VGPR11<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR11<def> = V_CNDMASK_B32_e64 -nan, 1.401298e-45, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR11<def> = V_CVT_F32_I32_e32 %VGPR11<kill>, %EXEC<imp-use>
	%VGPR18<def> = V_MUL_F32_e32 %VGPR9, %VGPR4, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 2; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR18<def> = V_MUL_F32_e32 %SGPR2, %VGPR18<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_SUB_F32_e32 %VGPR7<kill>, %VGPR18<kill>, %EXEC<imp-use>
	%VGPR18<def> = V_MAD_F32 %VGPR20<kill>, %VGPR11, %VGPR7, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR20<def> = V_MUL_F32_e32 %VGPR5, %VGPR4, %EXEC<imp-use>
	%VGPR20<def> = V_MUL_F32_e32 %SGPR2, %VGPR20<kill>, %EXEC<imp-use>
	%VGPR20<def> = V_SUB_F32_e32 %VGPR4, %VGPR20<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR6<kill>, %VGPR11, %VGPR20, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR21<def> = V_ADD_F32_e64 %VGPR6, 0, 0, 0, 0, 1, %EXEC<imp-use>
	%VGPR21<def> = V_RCP_F32_e32 %VGPR21<kill>, %EXEC<imp-use>
	%VGPR18<def> = V_MUL_F32_e32 %VGPR18<kill>, %VGPR21, %EXEC<imp-use>
	%VGPR18<def> = V_MUL_F32_e32 %SGPR27, %VGPR18<kill>, %EXEC<imp-use>
	%VGPR18<def> = V_SUBREV_F32_e32 %SGPR26, %VGPR18<kill>, %EXEC<imp-use>
	%VGPR18<def> = V_MAD_F32 %VGPR18<kill>, -5.000000e-01, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR23<def> = V_ADD_F32_e64 0, %VGPR18<kill>, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR22_VGPR23<imp-def>
	%VGPR4<def> = V_MUL_F32_e32 %VGPR8, %VGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e32 %SGPR2<kill>, %VGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_SUB_F32_e32 %VGPR19<kill>, %VGPR4<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_MAD_F32 %VGPR12<kill>, %VGPR11<kill>, %VGPR4, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR11<def> = V_MUL_F32_e32 %VGPR11<kill>, %VGPR21<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_MUL_F32_e32 %SGPR29, %VGPR11<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_SUBREV_F32_e32 %SGPR28, %VGPR11<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_MAD_F32 %VGPR11<kill>, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR22<def> = V_ADD_F32_e64 0, %VGPR11<kill>, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR22_VGPR23<imp-use,kill>, %VGPR22_VGPR23<imp-def>
	%VGPR11<def> = IMAGE_SAMPLE_V1_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR22_VGPR23<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR12<def> = V_ADD_F32_e64 %VGPR11, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_MUL_F32_e32 %SGPR24, %VGPR12<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_SUBREV_F32_e32 %SGPR25, %VGPR12<kill>, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_EQ_F32_e64 %VGPR12, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR18<def> = V_CNDMASK_B32_e64 0.000000e+00, 1.401298e-45, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR18<def> = V_CVT_F32_I32_e32 %VGPR18<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_SUB_F32_e32 %VGPR12<kill>, %VGPR6<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_ADD_F32_e32 %VGPR17, %VGPR17, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %VGPR6, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_CNDMASK_B32_e64 0, -1, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_AND_B32_e32 1065353216, %VGPR12<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_ADD_F32_e32 %VGPR12<kill>, %VGPR18<kill>, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_LE_F32_e64 %VGPR11<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR11<def> = V_CNDMASK_B32_e64 0, -1, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR11<def> = V_AND_B32_e32 1065353216, %VGPR11<kill>, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %VGPR1<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_CNDMASK_B32_e64 0, -1, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_AND_B32_e32 1065353216, %VGPR1<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_MAD_F32 %VGPR11<kill>, %VGPR1, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR11<def> = V_ADD_F32_e64 0, %VGPR11<kill>, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_SUB_F32_e32 1.000000e+00, %VGPR11, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %VGPR6<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_CNDMASK_B32_e64 0, -1, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_AND_B32_e32 1065353216, %VGPR6<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %VGPR6<kill>, %VGPR12<kill>, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 44; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR12<def> = V_MUL_F32_e32 %SGPR2, %VGPR3, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 45; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %VGPR2, %SGPR4, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR6<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 46; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %VGPR10, %SGPR6, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR18<def> = V_MUL_F32_e32 %VGPR12, %VGPR3, %EXEC<imp-use>
	%VGPR18<def> = V_MAD_F32 %VGPR12, %VGPR3, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR18<def> = V_SUB_F32_e32 %SGPR2<kill>, %VGPR18<kill>, %EXEC<imp-use>
	%VGPR19<def> = V_MUL_F32_e32 0.000000e+00, %VGPR14, %EXEC<imp-use>
	%VGPR19<def> = V_SUB_F32_e32 %VGPR15, %VGPR19<kill>, %EXEC<imp-use>
	%VGPR21<def> = V_MAD_F32 %VGPR14, -4.000000e+00, %VGPR19, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR18<def> = V_MUL_F32_e32 %VGPR18<kill>, %VGPR21, %EXEC<imp-use>
	%VGPR22<def> = V_MUL_F32_e32 %VGPR18, %VGPR8, %EXEC<imp-use>
	%VGPR23<def> = V_MUL_F32_e32 %VGPR12, %VGPR2, %EXEC<imp-use>
	%VGPR23<def> = V_MAD_F32 %VGPR12, %VGPR2, %VGPR23<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR23<def> = V_SUB_F32_e32 %SGPR4<kill>, %VGPR23<kill>, %EXEC<imp-use>
	%VGPR23<def> = V_MUL_F32_e32 %VGPR23<kill>, %VGPR21, %EXEC<imp-use>
	%VGPR22<def> = V_MAD_F32 %VGPR23, %VGPR9, %VGPR22<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_MUL_F32_e32 %VGPR12, %VGPR10, %EXEC<imp-use>
	%VGPR12<def> = V_MAD_F32 %VGPR12<kill>, %VGPR10, %VGPR24<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_SUB_F32_e32 %SGPR6<kill>, %VGPR12<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_MUL_F32_e32 %VGPR12<kill>, %VGPR21, %EXEC<imp-use>
	%VGPR22<def> = V_MAD_F32 %VGPR12, %VGPR5, %VGPR22<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %VGPR22<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR22<def> = V_CNDMASK_B32_e64 -nan, 1.401298e-45, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR22<def> = V_CVT_F32_I32_e32 %VGPR22<kill>, %EXEC<imp-use>
	%VGPR23<def> = V_MAD_F32 %VGPR23<kill>, %VGPR22, %VGPR7, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_MAD_F32 %VGPR12<kill>, %VGPR22, %VGPR20, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_ADD_F32_e64 %VGPR12, 0, 0, 0, 0, 1, %EXEC<imp-use>
	%VGPR24<def> = V_RCP_F32_e32 %VGPR24<kill>, %EXEC<imp-use>
	%VGPR23<def> = V_MUL_F32_e32 %VGPR23<kill>, %VGPR24, %EXEC<imp-use>
	%VGPR23<def> = V_MUL_F32_e32 %SGPR27, %VGPR23<kill>, %EXEC<imp-use>
	%VGPR23<def> = V_SUBREV_F32_e32 %SGPR26, %VGPR23<kill>, %EXEC<imp-use>
	%VGPR23<def> = V_MAD_F32 %VGPR23<kill>, -5.000000e-01, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR26<def> = V_ADD_F32_e64 0, %VGPR23<kill>, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR25_VGPR26<imp-def>
	%VGPR18<def> = V_MAD_F32 %VGPR18<kill>, %VGPR22<kill>, %VGPR4, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR18<def> = V_MUL_F32_e32 %VGPR18<kill>, %VGPR24<kill>, %EXEC<imp-use>
	%VGPR18<def> = V_MUL_F32_e32 %SGPR29, %VGPR18<kill>, %EXEC<imp-use>
	%VGPR18<def> = V_SUBREV_F32_e32 %SGPR28, %VGPR18<kill>, %EXEC<imp-use>
	%VGPR18<def> = V_MAD_F32 %VGPR18<kill>, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR25<def> = V_ADD_F32_e64 0, %VGPR18<kill>, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR25_VGPR26<imp-use,kill>, %VGPR25_VGPR26<imp-def>
	%VGPR18<def> = IMAGE_SAMPLE_V1_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR25_VGPR26<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR22<def> = V_ADD_F32_e64 %VGPR18, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%VGPR22<def> = V_MUL_F32_e32 %SGPR24, %VGPR22<kill>, %EXEC<imp-use>
	%VGPR22<def> = V_SUBREV_F32_e32 %SGPR25, %VGPR22<kill>, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_EQ_F32_e64 %VGPR22, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR23<def> = V_CNDMASK_B32_e64 0.000000e+00, 1.401298e-45, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR23<def> = V_CVT_F32_I32_e32 %VGPR23<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_SUB_F32_e32 %VGPR22<kill>, %VGPR12<kill>, %EXEC<imp-use>
	%VGPR22<def> = V_ADD_F32_e32 %VGPR21, %VGPR21, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %VGPR12, %VGPR22<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR22<def> = V_CNDMASK_B32_e64 0, -1, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR22<def> = V_AND_B32_e32 1065353216, %VGPR22<kill>, %EXEC<imp-use>
	%VGPR22<def> = V_ADD_F32_e32 %VGPR22<kill>, %VGPR23<kill>, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_LE_F32_e64 %VGPR18<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR18<def> = V_CNDMASK_B32_e64 0, -1, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR18<def> = V_AND_B32_e32 1065353216, %VGPR18<kill>, %EXEC<imp-use>
	%VGPR18<def> = V_MAD_F32 %VGPR18<kill>, %VGPR1, %VGPR22<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR18<def> = V_ADD_F32_e64 0, %VGPR18<kill>, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR22<def> = V_SUB_F32_e32 1.000000e+00, %VGPR18, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %VGPR12<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_CNDMASK_B32_e64 0, -1, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_AND_B32_e32 1065353216, %VGPR12<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR12<kill>, %VGPR22<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 52; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR12<def> = V_MUL_F32_e32 %SGPR2, %VGPR3, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 53; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %VGPR2, %SGPR4, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR6<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 54; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %VGPR10, %SGPR6, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR22<def> = V_MUL_F32_e32 %VGPR12, %VGPR3, %EXEC<imp-use>
	%VGPR22<def> = V_MAD_F32 %VGPR12, %VGPR3, %VGPR22<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR22<def> = V_SUB_F32_e32 %SGPR2<kill>, %VGPR22<kill>, %EXEC<imp-use>
	%VGPR23<def> = V_MAD_F32 %SGPR3<kill>, %VGPR13, %VGPR14, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR15<def> = V_SUB_F32_e32 %VGPR15<kill>, %VGPR23<kill>, %EXEC<imp-use>
	%VGPR23<def> = V_MAD_F32 %VGPR14, -4.000000e+00, %VGPR15, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR22<def> = V_MUL_F32_e32 %VGPR22<kill>, %VGPR23, %EXEC<imp-use>
	%VGPR24<def> = V_MUL_F32_e32 %VGPR22, %VGPR8, %EXEC<imp-use>
	%VGPR25<def> = V_MUL_F32_e32 %VGPR12, %VGPR2, %EXEC<imp-use>
	%VGPR25<def> = V_MAD_F32 %VGPR12, %VGPR2, %VGPR25<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR25<def> = V_SUB_F32_e32 %SGPR4<kill>, %VGPR25<kill>, %EXEC<imp-use>
	%VGPR25<def> = V_MUL_F32_e32 %VGPR25<kill>, %VGPR23, %EXEC<imp-use>
	%VGPR24<def> = V_MAD_F32 %VGPR25, %VGPR9, %VGPR24<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR26<def> = V_MUL_F32_e32 %VGPR12, %VGPR10, %EXEC<imp-use>
	%VGPR12<def> = V_MAD_F32 %VGPR12<kill>, %VGPR10, %VGPR26<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_SUB_F32_e32 %SGPR6<kill>, %VGPR12<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_MUL_F32_e32 %VGPR12<kill>, %VGPR23, %EXEC<imp-use>
	%VGPR24<def> = V_MAD_F32 %VGPR12, %VGPR5, %VGPR24<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR24<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_CNDMASK_B32_e64 -nan, 1.401298e-45, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_CVT_F32_I32_e32 %VGPR24<kill>, %EXEC<imp-use>
	%VGPR25<def> = V_MAD_F32 %VGPR25<kill>, %VGPR24, %VGPR7, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_MAD_F32 %VGPR12<kill>, %VGPR24, %VGPR20, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR26<def> = V_ADD_F32_e64 %VGPR12, 0, 0, 0, 0, 1, %EXEC<imp-use>
	%VGPR26<def> = V_RCP_F32_e32 %VGPR26<kill>, %EXEC<imp-use>
	%VGPR25<def> = V_MUL_F32_e32 %VGPR25<kill>, %VGPR26, %EXEC<imp-use>
	%VGPR25<def> = V_MUL_F32_e32 %SGPR27, %VGPR25<kill>, %EXEC<imp-use>
	%VGPR25<def> = V_SUBREV_F32_e32 %SGPR26, %VGPR25<kill>, %EXEC<imp-use>
	%VGPR25<def> = V_MAD_F32 %VGPR25<kill>, -5.000000e-01, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR28<def> = V_ADD_F32_e64 0, %VGPR25<kill>, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR27_VGPR28<imp-def>
	%VGPR22<def> = V_MAD_F32 %VGPR22<kill>, %VGPR24<kill>, %VGPR4, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR22<def> = V_MUL_F32_e32 %VGPR22<kill>, %VGPR26<kill>, %EXEC<imp-use>
	%VGPR22<def> = V_MUL_F32_e32 %SGPR29, %VGPR22<kill>, %EXEC<imp-use>
	%VGPR22<def> = V_SUBREV_F32_e32 %SGPR28, %VGPR22<kill>, %EXEC<imp-use>
	%VGPR22<def> = V_MAD_F32 %VGPR22<kill>, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR27<def> = V_ADD_F32_e64 0, %VGPR22<kill>, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR27_VGPR28<imp-use,kill>, %VGPR27_VGPR28<imp-def>
	%VGPR22<def> = IMAGE_SAMPLE_V1_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR27_VGPR28<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR24<def> = V_ADD_F32_e64 %VGPR22, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_MUL_F32_e32 %SGPR24, %VGPR24<kill>, %EXEC<imp-use>
	%VGPR24<def> = V_SUBREV_F32_e32 %SGPR25, %VGPR24<kill>, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_EQ_F32_e64 %VGPR24, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR25<def> = V_CNDMASK_B32_e64 0.000000e+00, 1.401298e-45, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR25<def> = V_CVT_F32_I32_e32 %VGPR25<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_SUB_F32_e32 %VGPR24<kill>, %VGPR12<kill>, %EXEC<imp-use>
	%VGPR24<def> = V_ADD_F32_e32 %VGPR23, %VGPR23, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR12, %VGPR24<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_CNDMASK_B32_e64 0, -1, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_AND_B32_e32 1065353216, %VGPR24<kill>, %EXEC<imp-use>
	%VGPR24<def> = V_ADD_F32_e32 %VGPR24<kill>, %VGPR25<kill>, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_LE_F32_e64 %VGPR22<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR22<def> = V_CNDMASK_B32_e64 0, -1, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR22<def> = V_AND_B32_e32 1065353216, %VGPR22<kill>, %EXEC<imp-use>
	%VGPR22<def> = V_MAD_F32 %VGPR22<kill>, %VGPR1, %VGPR24<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR22<def> = V_ADD_F32_e64 0, %VGPR22<kill>, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_SUB_F32_e32 1.000000e+00, %VGPR22, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR12<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_CNDMASK_B32_e64 0, -1, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_AND_B32_e32 1065353216, %VGPR12<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR12<kill>, %VGPR24<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 56; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR12<def> = V_MUL_F32_e32 %SGPR2, %VGPR3, %EXEC<imp-use>
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 57; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %VGPR2, %SGPR3, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 58; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %VGPR10, %SGPR4, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_MUL_F32_e32 %VGPR12, %VGPR3, %EXEC<imp-use>
	%VGPR24<def> = V_MAD_F32 %VGPR12, %VGPR3, %VGPR24<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_SUB_F32_e32 %SGPR2<kill>, %VGPR24<kill>, %EXEC<imp-use>
	%VGPR25<def> = V_MUL_F32_e32 -3.000000e+00, %VGPR14, %EXEC<imp-use>
	%VGPR13<def> = V_MAD_F32 %SGPR5<kill>, %VGPR13<kill>, %VGPR25<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR25<def> = V_MAD_F32 %VGPR14, -4.000000e+00, %VGPR13, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_MUL_F32_e32 %VGPR24<kill>, %VGPR25, %EXEC<imp-use>
	%VGPR26<def> = V_MUL_F32_e32 %VGPR24, %VGPR8, %EXEC<imp-use>
	%VGPR27<def> = V_MUL_F32_e32 %VGPR12, %VGPR2, %EXEC<imp-use>
	%VGPR27<def> = V_MAD_F32 %VGPR12, %VGPR2, %VGPR27<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR27<def> = V_SUB_F32_e32 %SGPR3<kill>, %VGPR27<kill>, %EXEC<imp-use>
	%VGPR27<def> = V_MUL_F32_e32 %VGPR27<kill>, %VGPR25, %EXEC<imp-use>
	%VGPR26<def> = V_MAD_F32 %VGPR27, %VGPR9, %VGPR26<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR28<def> = V_MUL_F32_e32 %VGPR12, %VGPR10, %EXEC<imp-use>
	%VGPR12<def> = V_MAD_F32 %VGPR12<kill>, %VGPR10, %VGPR28<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_SUB_F32_e32 %SGPR4<kill>, %VGPR12<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_MUL_F32_e32 %VGPR12<kill>, %VGPR25, %EXEC<imp-use>
	%VGPR26<def> = V_MAD_F32 %VGPR12, %VGPR5, %VGPR26<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR26<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR26<def> = V_CNDMASK_B32_e64 -nan, 1.401298e-45, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR26<def> = V_CVT_F32_I32_e32 %VGPR26<kill>, %EXEC<imp-use>
	%VGPR27<def> = V_MAD_F32 %VGPR27<kill>, %VGPR26, %VGPR7, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_MAD_F32 %VGPR12<kill>, %VGPR26, %VGPR20, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR28<def> = V_ADD_F32_e64 %VGPR12, 0, 0, 0, 0, 1, %EXEC<imp-use>
	%VGPR28<def> = V_RCP_F32_e32 %VGPR28<kill>, %EXEC<imp-use>
	%VGPR27<def> = V_MUL_F32_e32 %VGPR27<kill>, %VGPR28, %EXEC<imp-use>
	%VGPR27<def> = V_MUL_F32_e32 %SGPR27, %VGPR27<kill>, %EXEC<imp-use>
	%VGPR27<def> = V_SUBREV_F32_e32 %SGPR26, %VGPR27<kill>, %EXEC<imp-use>
	%VGPR27<def> = V_MAD_F32 %VGPR27<kill>, -5.000000e-01, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e64 0, %VGPR27<kill>, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR29_VGPR30<imp-def>
	%VGPR24<def> = V_MAD_F32 %VGPR24<kill>, %VGPR26<kill>, %VGPR4, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_MUL_F32_e32 %VGPR24<kill>, %VGPR28<kill>, %EXEC<imp-use>
	%VGPR24<def> = V_MUL_F32_e32 %SGPR29, %VGPR24<kill>, %EXEC<imp-use>
	%VGPR24<def> = V_SUBREV_F32_e32 %SGPR28, %VGPR24<kill>, %EXEC<imp-use>
	%VGPR24<def> = V_MAD_F32 %VGPR24<kill>, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR29<def> = V_ADD_F32_e64 0, %VGPR24<kill>, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR29_VGPR30<imp-use,kill>, %VGPR29_VGPR30<imp-def>
	%VGPR24<def> = IMAGE_SAMPLE_V1_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR29_VGPR30<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR26<def> = V_ADD_F32_e64 %VGPR24, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%VGPR26<def> = V_MUL_F32_e32 %SGPR24, %VGPR26<kill>, %EXEC<imp-use>
	%VGPR26<def> = V_SUBREV_F32_e32 %SGPR25, %VGPR26<kill>, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_EQ_F32_e64 %VGPR26, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR27<def> = V_CNDMASK_B32_e64 0.000000e+00, 1.401298e-45, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR27<def> = V_CVT_F32_I32_e32 %VGPR27<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_SUB_F32_e32 %VGPR26<kill>, %VGPR12<kill>, %EXEC<imp-use>
	%VGPR26<def> = V_ADD_F32_e32 %VGPR25, %VGPR25, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR12, %VGPR26<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR26<def> = V_CNDMASK_B32_e64 0, -1, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR26<def> = V_AND_B32_e32 1065353216, %VGPR26<kill>, %EXEC<imp-use>
	%VGPR26<def> = V_ADD_F32_e32 %VGPR26<kill>, %VGPR27<kill>, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_LE_F32_e64 %VGPR24<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_CNDMASK_B32_e64 0, -1, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_AND_B32_e32 1065353216, %VGPR24<kill>, %EXEC<imp-use>
	%VGPR24<def> = V_MAD_F32 %VGPR24<kill>, %VGPR1, %VGPR26<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_ADD_F32_e64 0, %VGPR24<kill>, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR26<def> = V_SUB_F32_e32 1.000000e+00, %VGPR24, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR12<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_CNDMASK_B32_e64 0, -1, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_AND_B32_e32 1065353216, %VGPR12<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR12<kill>, %VGPR26<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 32; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR12<def> = V_MUL_F32_e32 %SGPR2, %VGPR3, %EXEC<imp-use>
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 33; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %VGPR2, %SGPR3, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 34; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %VGPR10, %SGPR4, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR26<def> = V_MUL_F32_e32 %VGPR12, %VGPR3, %EXEC<imp-use>
	%VGPR26<def> = V_MAD_F32 %VGPR12, %VGPR3, %VGPR26<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR26<def> = V_SUB_F32_e32 %SGPR2<kill>, %VGPR26<kill>, %EXEC<imp-use>
	%VGPR26<def> = V_MUL_F32_e32 %VGPR26<kill>, %VGPR16, %EXEC<imp-use>
	%VGPR27<def> = V_MUL_F32_e32 %VGPR26, %VGPR8, %EXEC<imp-use>
	%VGPR28<def> = V_MUL_F32_e32 %VGPR12, %VGPR2, %EXEC<imp-use>
	%VGPR28<def> = V_MAD_F32 %VGPR12, %VGPR2, %VGPR28<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR28<def> = V_SUB_F32_e32 %SGPR3<kill>, %VGPR28<kill>, %EXEC<imp-use>
	%VGPR28<def> = V_MUL_F32_e32 %VGPR28<kill>, %VGPR16, %EXEC<imp-use>
	%VGPR27<def> = V_MAD_F32 %VGPR28, %VGPR9, %VGPR27<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR29<def> = V_MUL_F32_e32 %VGPR12, %VGPR10, %EXEC<imp-use>
	%VGPR12<def> = V_MAD_F32 %VGPR12<kill>, %VGPR10, %VGPR29<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_SUB_F32_e32 %SGPR4<kill>, %VGPR12<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_MUL_F32_e32 %VGPR12<kill>, %VGPR16, %EXEC<imp-use>
	%VGPR27<def> = V_MAD_F32 %VGPR12, %VGPR5, %VGPR27<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR27<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR27<def> = V_CNDMASK_B32_e64 -nan, 1.401298e-45, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR27<def> = V_CVT_F32_I32_e32 %VGPR27<kill>, %EXEC<imp-use>
	%VGPR28<def> = V_MAD_F32 %VGPR28<kill>, %VGPR27, %VGPR7, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_MAD_F32 %VGPR12<kill>, %VGPR27, %VGPR20, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR29<def> = V_ADD_F32_e64 %VGPR12, 0, 0, 0, 0, 1, %EXEC<imp-use>
	%VGPR29<def> = V_RCP_F32_e32 %VGPR29<kill>, %EXEC<imp-use>
	%VGPR28<def> = V_MUL_F32_e32 %VGPR28<kill>, %VGPR29, %EXEC<imp-use>
	%VGPR28<def> = V_MUL_F32_e32 %SGPR27, %VGPR28<kill>, %EXEC<imp-use>
	%VGPR28<def> = V_SUBREV_F32_e32 %SGPR26, %VGPR28<kill>, %EXEC<imp-use>
	%VGPR28<def> = V_MAD_F32 %VGPR28<kill>, -5.000000e-01, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR31<def> = V_ADD_F32_e64 0, %VGPR28<kill>, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR30_VGPR31<imp-def>
	%VGPR26<def> = V_MAD_F32 %VGPR26<kill>, %VGPR27<kill>, %VGPR4, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR26<def> = V_MUL_F32_e32 %VGPR26<kill>, %VGPR29<kill>, %EXEC<imp-use>
	%VGPR26<def> = V_MUL_F32_e32 %SGPR29, %VGPR26<kill>, %EXEC<imp-use>
	%VGPR26<def> = V_SUBREV_F32_e32 %SGPR28, %VGPR26<kill>, %EXEC<imp-use>
	%VGPR26<def> = V_MAD_F32 %VGPR26<kill>, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e64 0, %VGPR26<kill>, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR30_VGPR31<imp-def>
	%VGPR26<def> = IMAGE_SAMPLE_V1_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR30_VGPR31<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR27<def> = V_ADD_F32_e64 %VGPR26, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%VGPR27<def> = V_MUL_F32_e32 %SGPR24, %VGPR27<kill>, %EXEC<imp-use>
	%VGPR27<def> = V_SUBREV_F32_e32 %SGPR25, %VGPR27<kill>, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_EQ_F32_e64 %VGPR27, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR28<def> = V_CNDMASK_B32_e64 0.000000e+00, 1.401298e-45, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR28<def> = V_CVT_F32_I32_e32 %VGPR28<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_SUB_F32_e32 %VGPR27<kill>, %VGPR12<kill>, %EXEC<imp-use>
	%VGPR16<def> = V_ADD_F32_e32 %VGPR16<kill>, %VGPR16, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR12, %VGPR16<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR16<def> = V_CNDMASK_B32_e64 0, -1, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR16<def> = V_AND_B32_e32 1065353216, %VGPR16<kill>, %EXEC<imp-use>
	%VGPR16<def> = V_ADD_F32_e32 %VGPR16<kill>, %VGPR28<kill>, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_LE_F32_e64 %VGPR26<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR26<def> = V_CNDMASK_B32_e64 0, -1, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR26<def> = V_AND_B32_e32 1065353216, %VGPR26<kill>, %EXEC<imp-use>
	%VGPR16<def> = V_MAD_F32 %VGPR26<kill>, %VGPR1, %VGPR16<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR16<def> = V_ADD_F32_e64 0, %VGPR16<kill>, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR26<def> = V_SUB_F32_e32 1.000000e+00, %VGPR16, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR12<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_CNDMASK_B32_e64 0, -1, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_AND_B32_e32 1065353216, %VGPR12<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_MUL_F32_e32 %VGPR12<kill>, %VGPR26<kill>, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 28; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR26<def> = V_MUL_F32_e32 %SGPR2, %VGPR3, %EXEC<imp-use>
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 29; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR26<def> = V_MAD_F32 %VGPR2, %SGPR3, %VGPR26<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 30; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR26<def> = V_MAD_F32 %VGPR10, %SGPR4, %VGPR26<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR27<def> = V_MUL_F32_e32 %VGPR26, %VGPR3, %EXEC<imp-use>
	%VGPR27<def> = V_MAD_F32 %VGPR26, %VGPR3, %VGPR27<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR27<def> = V_SUB_F32_e32 %SGPR2<kill>, %VGPR27<kill>, %EXEC<imp-use>
	%VGPR27<def> = V_MUL_F32_e32 %VGPR27<kill>, %VGPR19, %EXEC<imp-use>
	%VGPR28<def> = V_MUL_F32_e32 %VGPR27, %VGPR8, %EXEC<imp-use>
	%VGPR29<def> = V_MUL_F32_e32 %VGPR26, %VGPR2, %EXEC<imp-use>
	%VGPR29<def> = V_MAD_F32 %VGPR26, %VGPR2, %VGPR29<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR29<def> = V_SUB_F32_e32 %SGPR3<kill>, %VGPR29<kill>, %EXEC<imp-use>
	%VGPR29<def> = V_MUL_F32_e32 %VGPR29<kill>, %VGPR19, %EXEC<imp-use>
	%VGPR28<def> = V_MAD_F32 %VGPR29, %VGPR9, %VGPR28<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR30<def> = V_MUL_F32_e32 %VGPR26, %VGPR10, %EXEC<imp-use>
	%VGPR26<def> = V_MAD_F32 %VGPR26<kill>, %VGPR10, %VGPR30<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR26<def> = V_SUB_F32_e32 %SGPR4<kill>, %VGPR26<kill>, %EXEC<imp-use>
	%VGPR26<def> = V_MUL_F32_e32 %VGPR26<kill>, %VGPR19, %EXEC<imp-use>
	%VGPR28<def> = V_MAD_F32 %VGPR26, %VGPR5, %VGPR28<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR28<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR28<def> = V_CNDMASK_B32_e64 -nan, 1.401298e-45, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR28<def> = V_CVT_F32_I32_e32 %VGPR28<kill>, %EXEC<imp-use>
	%VGPR29<def> = V_MAD_F32 %VGPR29<kill>, %VGPR28, %VGPR7, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR26<def> = V_MAD_F32 %VGPR26<kill>, %VGPR28, %VGPR20, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e64 %VGPR26, 0, 0, 0, 0, 1, %EXEC<imp-use>
	%VGPR30<def> = V_RCP_F32_e32 %VGPR30<kill>, %EXEC<imp-use>
	%VGPR29<def> = V_MUL_F32_e32 %VGPR29<kill>, %VGPR30, %EXEC<imp-use>
	%VGPR29<def> = V_MUL_F32_e32 %SGPR27, %VGPR29<kill>, %EXEC<imp-use>
	%VGPR29<def> = V_SUBREV_F32_e32 %SGPR26, %VGPR29<kill>, %EXEC<imp-use>
	%VGPR29<def> = V_MAD_F32 %VGPR29<kill>, -5.000000e-01, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR32<def> = V_ADD_F32_e64 0, %VGPR29<kill>, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR31_VGPR32<imp-def>
	%VGPR27<def> = V_MAD_F32 %VGPR27<kill>, %VGPR28<kill>, %VGPR4, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR27<def> = V_MUL_F32_e32 %VGPR27<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR27<def> = V_MUL_F32_e32 %SGPR29, %VGPR27<kill>, %EXEC<imp-use>
	%VGPR27<def> = V_SUBREV_F32_e32 %SGPR28, %VGPR27<kill>, %EXEC<imp-use>
	%VGPR27<def> = V_MAD_F32 %VGPR27<kill>, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR31<def> = V_ADD_F32_e64 0, %VGPR27<kill>, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR31_VGPR32<imp-def>
	%VGPR27<def> = IMAGE_SAMPLE_V1_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR31_VGPR32<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR28<def> = V_ADD_F32_e64 %VGPR27, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%VGPR28<def> = V_MUL_F32_e32 %SGPR24, %VGPR28<kill>, %EXEC<imp-use>
	%VGPR28<def> = V_SUBREV_F32_e32 %SGPR25, %VGPR28<kill>, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_EQ_F32_e64 %VGPR28, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR29<def> = V_CNDMASK_B32_e64 0.000000e+00, 1.401298e-45, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR29<def> = V_CVT_F32_I32_e32 %VGPR29<kill>, %EXEC<imp-use>
	%VGPR26<def> = V_SUB_F32_e32 %VGPR28<kill>, %VGPR26<kill>, %EXEC<imp-use>
	%VGPR19<def> = V_ADD_F32_e32 %VGPR19<kill>, %VGPR19, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR26, %VGPR19<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR19<def> = V_CNDMASK_B32_e64 0, -1, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR19<def> = V_AND_B32_e32 1065353216, %VGPR19<kill>, %EXEC<imp-use>
	%VGPR19<def> = V_ADD_F32_e32 %VGPR19<kill>, %VGPR29<kill>, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_LE_F32_e64 %VGPR27<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR27<def> = V_CNDMASK_B32_e64 0, -1, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR27<def> = V_AND_B32_e32 1065353216, %VGPR27<kill>, %EXEC<imp-use>
	%VGPR19<def> = V_MAD_F32 %VGPR27<kill>, %VGPR1, %VGPR19<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR19<def> = V_ADD_F32_e64 0, %VGPR19<kill>, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR27<def> = V_SUB_F32_e32 1.000000e+00, %VGPR19, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR26<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR26<def> = V_CNDMASK_B32_e64 0, -1, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR26<def> = V_AND_B32_e32 1065353216, %VGPR26<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_MAD_F32 %VGPR26<kill>, %VGPR27<kill>, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 36; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR26<def> = V_MUL_F32_e32 %SGPR2, %VGPR3, %EXEC<imp-use>
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 37; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR26<def> = V_MAD_F32 %VGPR2, %SGPR3, %VGPR26<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 38; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR26<def> = V_MAD_F32 %VGPR10, %SGPR4, %VGPR26<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR27<def> = V_MUL_F32_e32 %VGPR26, %VGPR3, %EXEC<imp-use>
	%VGPR27<def> = V_MAD_F32 %VGPR26, %VGPR3, %VGPR27<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR27<def> = V_SUB_F32_e32 %SGPR2<kill>, %VGPR27<kill>, %EXEC<imp-use>
	%VGPR27<def> = V_MUL_F32_e32 %VGPR27<kill>, %VGPR15, %EXEC<imp-use>
	%VGPR28<def> = V_MUL_F32_e32 %VGPR27, %VGPR8, %EXEC<imp-use>
	%VGPR29<def> = V_MUL_F32_e32 %VGPR26, %VGPR2, %EXEC<imp-use>
	%VGPR29<def> = V_MAD_F32 %VGPR26, %VGPR2, %VGPR29<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR29<def> = V_SUB_F32_e32 %SGPR3<kill>, %VGPR29<kill>, %EXEC<imp-use>
	%VGPR29<def> = V_MUL_F32_e32 %VGPR29<kill>, %VGPR15, %EXEC<imp-use>
	%VGPR28<def> = V_MAD_F32 %VGPR29, %VGPR9, %VGPR28<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR30<def> = V_MUL_F32_e32 %VGPR26, %VGPR10, %EXEC<imp-use>
	%VGPR26<def> = V_MAD_F32 %VGPR26<kill>, %VGPR10, %VGPR30<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR26<def> = V_SUB_F32_e32 %SGPR4<kill>, %VGPR26<kill>, %EXEC<imp-use>
	%VGPR26<def> = V_MUL_F32_e32 %VGPR26<kill>, %VGPR15, %EXEC<imp-use>
	%VGPR28<def> = V_MAD_F32 %VGPR26, %VGPR5, %VGPR28<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR28<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR28<def> = V_CNDMASK_B32_e64 -nan, 1.401298e-45, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR28<def> = V_CVT_F32_I32_e32 %VGPR28<kill>, %EXEC<imp-use>
	%VGPR29<def> = V_MAD_F32 %VGPR29<kill>, %VGPR28, %VGPR7, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR26<def> = V_MAD_F32 %VGPR26<kill>, %VGPR28, %VGPR20, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e64 %VGPR26, 0, 0, 0, 0, 1, %EXEC<imp-use>
	%VGPR30<def> = V_RCP_F32_e32 %VGPR30<kill>, %EXEC<imp-use>
	%VGPR29<def> = V_MUL_F32_e32 %VGPR29<kill>, %VGPR30, %EXEC<imp-use>
	%VGPR29<def> = V_MUL_F32_e32 %SGPR27, %VGPR29<kill>, %EXEC<imp-use>
	%VGPR29<def> = V_SUBREV_F32_e32 %SGPR26, %VGPR29<kill>, %EXEC<imp-use>
	%VGPR29<def> = V_MAD_F32 %VGPR29<kill>, -5.000000e-01, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR32<def> = V_ADD_F32_e64 0, %VGPR29<kill>, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR31_VGPR32<imp-def>
	%VGPR27<def> = V_MAD_F32 %VGPR27<kill>, %VGPR28<kill>, %VGPR4, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR27<def> = V_MUL_F32_e32 %VGPR27<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR27<def> = V_MUL_F32_e32 %SGPR29, %VGPR27<kill>, %EXEC<imp-use>
	%VGPR27<def> = V_SUBREV_F32_e32 %SGPR28, %VGPR27<kill>, %EXEC<imp-use>
	%VGPR27<def> = V_MAD_F32 %VGPR27<kill>, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR31<def> = V_ADD_F32_e64 0, %VGPR27<kill>, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR31_VGPR32<imp-def>
	%VGPR27<def> = IMAGE_SAMPLE_V1_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR31_VGPR32<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR28<def> = V_ADD_F32_e64 %VGPR27, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%VGPR28<def> = V_MUL_F32_e32 %SGPR24, %VGPR28<kill>, %EXEC<imp-use>
	%VGPR28<def> = V_SUBREV_F32_e32 %SGPR25, %VGPR28<kill>, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_EQ_F32_e64 %VGPR28, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR29<def> = V_CNDMASK_B32_e64 0.000000e+00, 1.401298e-45, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR29<def> = V_CVT_F32_I32_e32 %VGPR29<kill>, %EXEC<imp-use>
	%VGPR26<def> = V_SUB_F32_e32 %VGPR28<kill>, %VGPR26<kill>, %EXEC<imp-use>
	%VGPR15<def> = V_ADD_F32_e32 %VGPR15<kill>, %VGPR15, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR26, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR15<def> = V_CNDMASK_B32_e64 0, -1, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR15<def> = V_AND_B32_e32 1065353216, %VGPR15<kill>, %EXEC<imp-use>
	%VGPR15<def> = V_ADD_F32_e32 %VGPR15<kill>, %VGPR29<kill>, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_LE_F32_e64 %VGPR27<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR27<def> = V_CNDMASK_B32_e64 0, -1, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR27<def> = V_AND_B32_e32 1065353216, %VGPR27<kill>, %EXEC<imp-use>
	%VGPR15<def> = V_MAD_F32 %VGPR27<kill>, %VGPR1, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR15<def> = V_ADD_F32_e64 0, %VGPR15<kill>, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR27<def> = V_SUB_F32_e32 1.000000e+00, %VGPR15, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR26<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR26<def> = V_CNDMASK_B32_e64 0, -1, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR26<def> = V_AND_B32_e32 1065353216, %VGPR26<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_MAD_F32 %VGPR26<kill>, %VGPR27<kill>, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 40; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR26<def> = V_MUL_F32_e32 %SGPR2, %VGPR3, %EXEC<imp-use>
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 41; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR26<def> = V_MAD_F32 %VGPR2, %SGPR3, %VGPR26<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 42; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR26<def> = V_MAD_F32 %VGPR10, %SGPR4, %VGPR26<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR27<def> = V_MUL_F32_e32 %VGPR26, %VGPR3, %EXEC<imp-use>
	%VGPR27<def> = V_MAD_F32 %VGPR26, %VGPR3, %VGPR27<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR27<def> = V_SUB_F32_e32 %SGPR2<kill>, %VGPR27<kill>, %EXEC<imp-use>
	%VGPR27<def> = V_MUL_F32_e32 %VGPR27<kill>, %VGPR13, %EXEC<imp-use>
	%VGPR28<def> = V_MUL_F32_e32 %VGPR27, %VGPR8, %EXEC<imp-use>
	%VGPR29<def> = V_MUL_F32_e32 %VGPR26, %VGPR2, %EXEC<imp-use>
	%VGPR29<def> = V_MAD_F32 %VGPR26, %VGPR2, %VGPR29<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR29<def> = V_SUB_F32_e32 %SGPR3<kill>, %VGPR29<kill>, %EXEC<imp-use>
	%VGPR29<def> = V_MUL_F32_e32 %VGPR29<kill>, %VGPR13, %EXEC<imp-use>
	%VGPR28<def> = V_MAD_F32 %VGPR29, %VGPR9, %VGPR28<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR30<def> = V_MUL_F32_e32 %VGPR26, %VGPR10, %EXEC<imp-use>
	%VGPR26<def> = V_MAD_F32 %VGPR26<kill>, %VGPR10, %VGPR30<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR26<def> = V_SUB_F32_e32 %SGPR4<kill>, %VGPR26<kill>, %EXEC<imp-use>
	%VGPR26<def> = V_MUL_F32_e32 %VGPR26<kill>, %VGPR13, %EXEC<imp-use>
	%VGPR28<def> = V_MAD_F32 %VGPR26, %VGPR5, %VGPR28<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR28<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR28<def> = V_CNDMASK_B32_e64 -nan, 1.401298e-45, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR28<def> = V_CVT_F32_I32_e32 %VGPR28<kill>, %EXEC<imp-use>
	%VGPR29<def> = V_MAD_F32 %VGPR29<kill>, %VGPR28, %VGPR7, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR26<def> = V_MAD_F32 %VGPR26<kill>, %VGPR28, %VGPR20, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e64 %VGPR26, 0, 0, 0, 0, 1, %EXEC<imp-use>
	%VGPR30<def> = V_RCP_F32_e32 %VGPR30<kill>, %EXEC<imp-use>
	%VGPR29<def> = V_MUL_F32_e32 %VGPR29<kill>, %VGPR30, %EXEC<imp-use>
	%VGPR29<def> = V_MUL_F32_e32 %SGPR27, %VGPR29<kill>, %EXEC<imp-use>
	%VGPR29<def> = V_SUBREV_F32_e32 %SGPR26, %VGPR29<kill>, %EXEC<imp-use>
	%VGPR29<def> = V_MAD_F32 %VGPR29<kill>, -5.000000e-01, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR32<def> = V_ADD_F32_e64 0, %VGPR29<kill>, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR31_VGPR32<imp-def>
	%VGPR27<def> = V_MAD_F32 %VGPR27<kill>, %VGPR28<kill>, %VGPR4, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR27<def> = V_MUL_F32_e32 %VGPR27<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR27<def> = V_MUL_F32_e32 %SGPR29, %VGPR27<kill>, %EXEC<imp-use>
	%VGPR27<def> = V_SUBREV_F32_e32 %SGPR28, %VGPR27<kill>, %EXEC<imp-use>
	%VGPR27<def> = V_MAD_F32 %VGPR27<kill>, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR31<def> = V_ADD_F32_e64 0, %VGPR27<kill>, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR31_VGPR32<imp-use,kill>, %VGPR31_VGPR32<imp-def>
	%VGPR27<def> = IMAGE_SAMPLE_V1_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR31_VGPR32<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR28<def> = V_ADD_F32_e64 %VGPR27, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%VGPR28<def> = V_MUL_F32_e32 %SGPR24, %VGPR28<kill>, %EXEC<imp-use>
	%VGPR28<def> = V_SUBREV_F32_e32 %SGPR25, %VGPR28<kill>, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_EQ_F32_e64 %VGPR28, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR29<def> = V_CNDMASK_B32_e64 0.000000e+00, 1.401298e-45, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR29<def> = V_CVT_F32_I32_e32 %VGPR29<kill>, %EXEC<imp-use>
	%VGPR26<def> = V_SUB_F32_e32 %VGPR28<kill>, %VGPR26<kill>, %EXEC<imp-use>
	%VGPR13<def> = V_ADD_F32_e32 %VGPR13<kill>, %VGPR13, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR26, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_CNDMASK_B32_e64 0, -1, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_AND_B32_e32 1065353216, %VGPR13<kill>, %EXEC<imp-use>
	%VGPR13<def> = V_ADD_F32_e32 %VGPR13<kill>, %VGPR29<kill>, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_LE_F32_e64 %VGPR27<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR27<def> = V_CNDMASK_B32_e64 0, -1, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR27<def> = V_AND_B32_e32 1065353216, %VGPR27<kill>, %EXEC<imp-use>
	%VGPR13<def> = V_MAD_F32 %VGPR27<kill>, %VGPR1, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_ADD_F32_e64 0, %VGPR13<kill>, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR27<def> = V_SUB_F32_e32 1.000000e+00, %VGPR13, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR26<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR26<def> = V_CNDMASK_B32_e64 0, -1, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR26<def> = V_AND_B32_e32 1065353216, %VGPR26<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_MAD_F32 %VGPR26<kill>, %VGPR27<kill>, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_ADD_F32_e32 %VGPR12<kill>, %VGPR6<kill>, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 64; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR12<def> = V_MUL_F32_e32 %SGPR2, %VGPR3, %EXEC<imp-use>
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 65; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %VGPR2, %SGPR3, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 66; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %VGPR10, %SGPR4, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR26<def> = V_MUL_F32_e32 %VGPR12, %VGPR3, %EXEC<imp-use>
	%VGPR26<def> = V_MAD_F32 %VGPR12, %VGPR3, %VGPR26<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR26<def> = V_SUB_F32_e32 %SGPR2<kill>, %VGPR26<kill>, %EXEC<imp-use>
	%VGPR17<def> = V_MAD_F32 %VGPR14, -4.000000e+00, %VGPR17<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR26<def> = V_MUL_F32_e32 %VGPR26<kill>, %VGPR17, %EXEC<imp-use>
	%VGPR27<def> = V_MUL_F32_e32 %VGPR26, %VGPR8, %EXEC<imp-use>
	%VGPR28<def> = V_MUL_F32_e32 %VGPR12, %VGPR2, %EXEC<imp-use>
	%VGPR28<def> = V_MAD_F32 %VGPR12, %VGPR2, %VGPR28<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR28<def> = V_SUB_F32_e32 %SGPR3<kill>, %VGPR28<kill>, %EXEC<imp-use>
	%VGPR28<def> = V_MUL_F32_e32 %VGPR28<kill>, %VGPR17, %EXEC<imp-use>
	%VGPR27<def> = V_MAD_F32 %VGPR28, %VGPR9, %VGPR27<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR29<def> = V_MUL_F32_e32 %VGPR12, %VGPR10, %EXEC<imp-use>
	%VGPR12<def> = V_MAD_F32 %VGPR12<kill>, %VGPR10, %VGPR29<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_SUB_F32_e32 %SGPR4<kill>, %VGPR12<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_MUL_F32_e32 %VGPR12<kill>, %VGPR17, %EXEC<imp-use>
	%VGPR27<def> = V_MAD_F32 %VGPR12, %VGPR5, %VGPR27<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR27<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR27<def> = V_CNDMASK_B32_e64 -nan, 1.401298e-45, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR27<def> = V_CVT_F32_I32_e32 %VGPR27<kill>, %EXEC<imp-use>
	%VGPR28<def> = V_MAD_F32 %VGPR28<kill>, %VGPR27, %VGPR7, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_MAD_F32 %VGPR12<kill>, %VGPR27, %VGPR20, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR29<def> = V_ADD_F32_e64 %VGPR12, 0, 0, 0, 0, 1, %EXEC<imp-use>
	%VGPR29<def> = V_RCP_F32_e32 %VGPR29<kill>, %EXEC<imp-use>
	%VGPR28<def> = V_MUL_F32_e32 %VGPR28<kill>, %VGPR29, %EXEC<imp-use>
	%VGPR28<def> = V_MUL_F32_e32 %SGPR27, %VGPR28<kill>, %EXEC<imp-use>
	%VGPR28<def> = V_SUBREV_F32_e32 %SGPR26, %VGPR28<kill>, %EXEC<imp-use>
	%VGPR28<def> = V_MAD_F32 %VGPR28<kill>, -5.000000e-01, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR31<def> = V_ADD_F32_e64 0, %VGPR28<kill>, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR30_VGPR31<imp-def>
	%VGPR26<def> = V_MAD_F32 %VGPR26<kill>, %VGPR27<kill>, %VGPR4, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR26<def> = V_MUL_F32_e32 %VGPR26<kill>, %VGPR29<kill>, %EXEC<imp-use>
	%VGPR26<def> = V_MUL_F32_e32 %SGPR29, %VGPR26<kill>, %EXEC<imp-use>
	%VGPR26<def> = V_SUBREV_F32_e32 %SGPR28, %VGPR26<kill>, %EXEC<imp-use>
	%VGPR26<def> = V_MAD_F32 %VGPR26<kill>, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e64 0, %VGPR26<kill>, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR30_VGPR31<imp-use,kill>, %VGPR30_VGPR31<imp-def>
	%VGPR26<def> = IMAGE_SAMPLE_V1_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR30_VGPR31<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR27<def> = V_ADD_F32_e64 %VGPR26, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%VGPR27<def> = V_MUL_F32_e32 %SGPR24, %VGPR27<kill>, %EXEC<imp-use>
	%VGPR27<def> = V_SUBREV_F32_e32 %SGPR25, %VGPR27<kill>, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_EQ_F32_e64 %VGPR27, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR28<def> = V_CNDMASK_B32_e64 0.000000e+00, 1.401298e-45, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR28<def> = V_CVT_F32_I32_e32 %VGPR28<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_SUB_F32_e32 %VGPR27<kill>, %VGPR12<kill>, %EXEC<imp-use>
	%VGPR27<def> = V_ADD_F32_e32 %VGPR17, %VGPR17, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR12, %VGPR27<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR27<def> = V_CNDMASK_B32_e64 0, -1, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR27<def> = V_AND_B32_e32 1065353216, %VGPR27<kill>, %EXEC<imp-use>
	%VGPR27<def> = V_ADD_F32_e32 %VGPR27<kill>, %VGPR28<kill>, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_LE_F32_e64 %VGPR26<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR26<def> = V_CNDMASK_B32_e64 0, -1, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR26<def> = V_AND_B32_e32 1065353216, %VGPR26<kill>, %EXEC<imp-use>
	%VGPR26<def> = V_MAD_F32 %VGPR26<kill>, %VGPR1, %VGPR27<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR26<def> = V_ADD_F32_e64 0, %VGPR26<kill>, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR27<def> = V_SUB_F32_e32 1.000000e+00, %VGPR26, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR12<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_CNDMASK_B32_e64 0, -1, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_AND_B32_e32 1065353216, %VGPR12<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_MUL_F32_e32 %VGPR12<kill>, %VGPR27<kill>, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 60; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR27<def> = V_MUL_F32_e32 %SGPR2, %VGPR3, %EXEC<imp-use>
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 61; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR27<def> = V_MAD_F32 %VGPR2, %SGPR3, %VGPR27<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 62; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR27<def> = V_MAD_F32 %VGPR10, %SGPR4, %VGPR27<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR28<def> = V_MUL_F32_e32 %VGPR27, %VGPR3, %EXEC<imp-use>
	%VGPR28<def> = V_MAD_F32 %VGPR27, %VGPR3, %VGPR28<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR28<def> = V_SUB_F32_e32 %SGPR2<kill>, %VGPR28<kill>, %EXEC<imp-use>
	%VGPR21<def> = V_MAD_F32 %VGPR14, -4.000000e+00, %VGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR28<def> = V_MUL_F32_e32 %VGPR28<kill>, %VGPR21, %EXEC<imp-use>
	%VGPR29<def> = V_MUL_F32_e32 %VGPR28, %VGPR8, %EXEC<imp-use>
	%VGPR30<def> = V_MUL_F32_e32 %VGPR27, %VGPR2, %EXEC<imp-use>
	%VGPR30<def> = V_MAD_F32 %VGPR27, %VGPR2, %VGPR30<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR30<def> = V_SUB_F32_e32 %SGPR3<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR21, %EXEC<imp-use>
	%VGPR29<def> = V_MAD_F32 %VGPR30, %VGPR9, %VGPR29<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR31<def> = V_MUL_F32_e32 %VGPR27, %VGPR10, %EXEC<imp-use>
	%VGPR27<def> = V_MAD_F32 %VGPR27<kill>, %VGPR10, %VGPR31<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR27<def> = V_SUB_F32_e32 %SGPR4<kill>, %VGPR27<kill>, %EXEC<imp-use>
	%VGPR27<def> = V_MUL_F32_e32 %VGPR27<kill>, %VGPR21, %EXEC<imp-use>
	%VGPR29<def> = V_MAD_F32 %VGPR27, %VGPR5, %VGPR29<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR29<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR29<def> = V_CNDMASK_B32_e64 -nan, 1.401298e-45, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR29<def> = V_CVT_F32_I32_e32 %VGPR29<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_MAD_F32 %VGPR30<kill>, %VGPR29, %VGPR7, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR27<def> = V_MAD_F32 %VGPR27<kill>, %VGPR29, %VGPR20, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR31<def> = V_ADD_F32_e64 %VGPR27, 0, 0, 0, 0, 1, %EXEC<imp-use>
	%VGPR31<def> = V_RCP_F32_e32 %VGPR31<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR31, %EXEC<imp-use>
	%VGPR30<def> = V_MUL_F32_e32 %SGPR27, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_SUBREV_F32_e32 %SGPR26, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_MAD_F32 %VGPR30<kill>, -5.000000e-01, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR33<def> = V_ADD_F32_e64 0, %VGPR30<kill>, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR32_VGPR33<imp-def>
	%VGPR28<def> = V_MAD_F32 %VGPR28<kill>, %VGPR29<kill>, %VGPR4, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR28<def> = V_MUL_F32_e32 %VGPR28<kill>, %VGPR31<kill>, %EXEC<imp-use>
	%VGPR28<def> = V_MUL_F32_e32 %SGPR29, %VGPR28<kill>, %EXEC<imp-use>
	%VGPR28<def> = V_SUBREV_F32_e32 %SGPR28, %VGPR28<kill>, %EXEC<imp-use>
	%VGPR28<def> = V_MAD_F32 %VGPR28<kill>, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR32<def> = V_ADD_F32_e64 0, %VGPR28<kill>, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR32_VGPR33<imp-use,kill>, %VGPR32_VGPR33<imp-def>
	%VGPR28<def> = IMAGE_SAMPLE_V1_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR32_VGPR33<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR29<def> = V_ADD_F32_e64 %VGPR28, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%VGPR29<def> = V_MUL_F32_e32 %SGPR24, %VGPR29<kill>, %EXEC<imp-use>
	%VGPR29<def> = V_SUBREV_F32_e32 %SGPR25, %VGPR29<kill>, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_EQ_F32_e64 %VGPR29, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR30<def> = V_CNDMASK_B32_e64 0.000000e+00, 1.401298e-45, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR30<def> = V_CVT_F32_I32_e32 %VGPR30<kill>, %EXEC<imp-use>
	%VGPR27<def> = V_SUB_F32_e32 %VGPR29<kill>, %VGPR27<kill>, %EXEC<imp-use>
	%VGPR29<def> = V_ADD_F32_e32 %VGPR21, %VGPR21, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR27, %VGPR29<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR29<def> = V_CNDMASK_B32_e64 0, -1, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR29<def> = V_AND_B32_e32 1065353216, %VGPR29<kill>, %EXEC<imp-use>
	%VGPR29<def> = V_ADD_F32_e32 %VGPR29<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_LE_F32_e64 %VGPR28<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR28<def> = V_CNDMASK_B32_e64 0, -1, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR28<def> = V_AND_B32_e32 1065353216, %VGPR28<kill>, %EXEC<imp-use>
	%VGPR28<def> = V_MAD_F32 %VGPR28<kill>, %VGPR1, %VGPR29<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR28<def> = V_ADD_F32_e64 0, %VGPR28<kill>, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR29<def> = V_SUB_F32_e32 1.000000e+00, %VGPR28, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR27<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR27<def> = V_CNDMASK_B32_e64 0, -1, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR27<def> = V_AND_B32_e32 1065353216, %VGPR27<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_MAD_F32 %VGPR27<kill>, %VGPR29<kill>, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 68; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR27<def> = V_MUL_F32_e32 %SGPR2, %VGPR3, %EXEC<imp-use>
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 69; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR27<def> = V_MAD_F32 %VGPR2, %SGPR3, %VGPR27<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 70; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR27<def> = V_MAD_F32 %VGPR10, %SGPR4, %VGPR27<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR29<def> = V_MUL_F32_e32 %VGPR27, %VGPR3, %EXEC<imp-use>
	%VGPR29<def> = V_MAD_F32 %VGPR27, %VGPR3, %VGPR29<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR29<def> = V_SUB_F32_e32 %SGPR2<kill>, %VGPR29<kill>, %EXEC<imp-use>
	%VGPR23<def> = V_MAD_F32 %VGPR14, -4.000000e+00, %VGPR23<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR29<def> = V_MUL_F32_e32 %VGPR29<kill>, %VGPR23, %EXEC<imp-use>
	%VGPR30<def> = V_MUL_F32_e32 %VGPR29, %VGPR8, %EXEC<imp-use>
	%VGPR31<def> = V_MUL_F32_e32 %VGPR27, %VGPR2, %EXEC<imp-use>
	%VGPR31<def> = V_MAD_F32 %VGPR27, %VGPR2, %VGPR31<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR31<def> = V_SUB_F32_e32 %SGPR3<kill>, %VGPR31<kill>, %EXEC<imp-use>
	%VGPR31<def> = V_MUL_F32_e32 %VGPR31<kill>, %VGPR23, %EXEC<imp-use>
	%VGPR30<def> = V_MAD_F32 %VGPR31, %VGPR9, %VGPR30<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR32<def> = V_MUL_F32_e32 %VGPR27, %VGPR10, %EXEC<imp-use>
	%VGPR27<def> = V_MAD_F32 %VGPR27<kill>, %VGPR10, %VGPR32<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR27<def> = V_SUB_F32_e32 %SGPR4<kill>, %VGPR27<kill>, %EXEC<imp-use>
	%VGPR27<def> = V_MUL_F32_e32 %VGPR27<kill>, %VGPR23, %EXEC<imp-use>
	%VGPR30<def> = V_MAD_F32 %VGPR27, %VGPR5, %VGPR30<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR30<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR30<def> = V_CNDMASK_B32_e64 -nan, 1.401298e-45, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR30<def> = V_CVT_F32_I32_e32 %VGPR30<kill>, %EXEC<imp-use>
	%VGPR31<def> = V_MAD_F32 %VGPR31<kill>, %VGPR30, %VGPR7, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR27<def> = V_MAD_F32 %VGPR27<kill>, %VGPR30, %VGPR20, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR32<def> = V_ADD_F32_e64 %VGPR27, 0, 0, 0, 0, 1, %EXEC<imp-use>
	%VGPR32<def> = V_RCP_F32_e32 %VGPR32<kill>, %EXEC<imp-use>
	%VGPR31<def> = V_MUL_F32_e32 %VGPR31<kill>, %VGPR32, %EXEC<imp-use>
	%VGPR31<def> = V_MUL_F32_e32 %SGPR27, %VGPR31<kill>, %EXEC<imp-use>
	%VGPR31<def> = V_SUBREV_F32_e32 %SGPR26, %VGPR31<kill>, %EXEC<imp-use>
	%VGPR31<def> = V_MAD_F32 %VGPR31<kill>, -5.000000e-01, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR34<def> = V_ADD_F32_e64 0, %VGPR31<kill>, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR33_VGPR34<imp-def>
	%VGPR29<def> = V_MAD_F32 %VGPR29<kill>, %VGPR30<kill>, %VGPR4, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR29<def> = V_MUL_F32_e32 %VGPR29<kill>, %VGPR32<kill>, %EXEC<imp-use>
	%VGPR29<def> = V_MUL_F32_e32 %SGPR29, %VGPR29<kill>, %EXEC<imp-use>
	%VGPR29<def> = V_SUBREV_F32_e32 %SGPR28, %VGPR29<kill>, %EXEC<imp-use>
	%VGPR29<def> = V_MAD_F32 %VGPR29<kill>, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR33<def> = V_ADD_F32_e64 0, %VGPR29<kill>, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR29<def> = IMAGE_SAMPLE_V1_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR33_VGPR34<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR30<def> = V_ADD_F32_e64 %VGPR29, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%VGPR30<def> = V_MUL_F32_e32 %SGPR24, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_SUBREV_F32_e32 %SGPR25, %VGPR30<kill>, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_EQ_F32_e64 %VGPR30, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR31<def> = V_CNDMASK_B32_e64 0.000000e+00, 1.401298e-45, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR31<def> = V_CVT_F32_I32_e32 %VGPR31<kill>, %EXEC<imp-use>
	%VGPR27<def> = V_SUB_F32_e32 %VGPR30<kill>, %VGPR27<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR23, %VGPR23, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR27, %VGPR30<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR30<def> = V_CNDMASK_B32_e64 0, -1, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR30<def> = V_AND_B32_e32 1065353216, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e32 %VGPR30<kill>, %VGPR31<kill>, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_LE_F32_e64 %VGPR29<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR29<def> = V_CNDMASK_B32_e64 0, -1, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR29<def> = V_AND_B32_e32 1065353216, %VGPR29<kill>, %EXEC<imp-use>
	%VGPR29<def> = V_MAD_F32 %VGPR29<kill>, %VGPR1, %VGPR30<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR29<def> = V_ADD_F32_e64 0, %VGPR29<kill>, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR30<def> = V_SUB_F32_e32 1.000000e+00, %VGPR29, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR27<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR27<def> = V_CNDMASK_B32_e64 0, -1, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR27<def> = V_AND_B32_e32 1065353216, %VGPR27<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_MAD_F32 %VGPR27<kill>, %VGPR30<kill>, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 72; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR27<def> = V_MUL_F32_e32 %SGPR2, %VGPR3, %EXEC<imp-use>
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 73; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR27<def> = V_MAD_F32 %VGPR2, %SGPR3, %VGPR27<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 74; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR27<def> = V_MAD_F32 %VGPR10, %SGPR4, %VGPR27<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR30<def> = V_MUL_F32_e32 %VGPR27, %VGPR3, %EXEC<imp-use>
	%VGPR30<def> = V_MAD_F32 %VGPR27, %VGPR3, %VGPR30<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR30<def> = V_SUB_F32_e32 %SGPR2<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR25<def> = V_MAD_F32 %VGPR14, -4.000000e+00, %VGPR25<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR30<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR25, %EXEC<imp-use>
	%VGPR31<def> = V_MUL_F32_e32 %VGPR30, %VGPR8, %EXEC<imp-use>
	%VGPR32<def> = V_MUL_F32_e32 %VGPR27, %VGPR2, %EXEC<imp-use>
	%VGPR32<def> = V_MAD_F32 %VGPR27, %VGPR2, %VGPR32<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR32<def> = V_SUB_F32_e32 %SGPR3<kill>, %VGPR32<kill>, %EXEC<imp-use>
	%VGPR32<def> = V_MUL_F32_e32 %VGPR32<kill>, %VGPR25, %EXEC<imp-use>
	%VGPR31<def> = V_MAD_F32 %VGPR32, %VGPR9, %VGPR31<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR33<def> = V_MUL_F32_e32 %VGPR27, %VGPR10, %EXEC<imp-use>
	%VGPR27<def> = V_MAD_F32 %VGPR27<kill>, %VGPR10, %VGPR33<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR27<def> = V_SUB_F32_e32 %SGPR4<kill>, %VGPR27<kill>, %EXEC<imp-use>
	%VGPR27<def> = V_MUL_F32_e32 %VGPR27<kill>, %VGPR25, %EXEC<imp-use>
	%VGPR31<def> = V_MAD_F32 %VGPR27, %VGPR5, %VGPR31<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR31<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR31<def> = V_CNDMASK_B32_e64 -nan, 1.401298e-45, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR31<def> = V_CVT_F32_I32_e32 %VGPR31<kill>, %EXEC<imp-use>
	%VGPR32<def> = V_MAD_F32 %VGPR32<kill>, %VGPR31, %VGPR7, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR27<def> = V_MAD_F32 %VGPR27<kill>, %VGPR31, %VGPR20, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR33<def> = V_ADD_F32_e64 %VGPR27, 0, 0, 0, 0, 1, %EXEC<imp-use>
	%VGPR33<def> = V_RCP_F32_e32 %VGPR33<kill>, %EXEC<imp-use>
	%VGPR32<def> = V_MUL_F32_e32 %VGPR32<kill>, %VGPR33, %EXEC<imp-use>
	%VGPR32<def> = V_MUL_F32_e32 %SGPR27, %VGPR32<kill>, %EXEC<imp-use>
	%VGPR32<def> = V_SUBREV_F32_e32 %SGPR26, %VGPR32<kill>, %EXEC<imp-use>
	%VGPR32<def> = V_MAD_F32 %VGPR32<kill>, -5.000000e-01, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR35<def> = V_ADD_F32_e64 0, %VGPR32<kill>, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR34_VGPR35<imp-def>
	%VGPR30<def> = V_MAD_F32 %VGPR30<kill>, %VGPR31<kill>, %VGPR4, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR30<def> = V_MUL_F32_e32 %VGPR30<kill>, %VGPR33<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_MUL_F32_e32 %SGPR29, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_SUBREV_F32_e32 %SGPR28, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_MAD_F32 %VGPR30<kill>, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR34<def> = V_ADD_F32_e64 0, %VGPR30<kill>, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR34_VGPR35<imp-use,kill>, %VGPR34_VGPR35<imp-def>
	%VGPR30<def> = IMAGE_SAMPLE_V1_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR34_VGPR35<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR31<def> = V_ADD_F32_e64 %VGPR30, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%VGPR31<def> = V_MUL_F32_e32 %SGPR24, %VGPR31<kill>, %EXEC<imp-use>
	%VGPR31<def> = V_SUBREV_F32_e32 %SGPR25, %VGPR31<kill>, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_EQ_F32_e64 %VGPR31, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR32<def> = V_CNDMASK_B32_e64 0.000000e+00, 1.401298e-45, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR32<def> = V_CVT_F32_I32_e32 %VGPR32<kill>, %EXEC<imp-use>
	%VGPR27<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR27<kill>, %EXEC<imp-use>
	%VGPR31<def> = V_ADD_F32_e32 %VGPR25, %VGPR25, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR27, %VGPR31<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR31<def> = V_CNDMASK_B32_e64 0, -1, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR31<def> = V_AND_B32_e32 1065353216, %VGPR31<kill>, %EXEC<imp-use>
	%VGPR31<def> = V_ADD_F32_e32 %VGPR31<kill>, %VGPR32<kill>, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_LE_F32_e64 %VGPR30<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR30<def> = V_CNDMASK_B32_e64 0, -1, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR30<def> = V_AND_B32_e32 1065353216, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_MAD_F32 %VGPR30<kill>, %VGPR1, %VGPR31<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR30<def> = V_ADD_F32_e64 0, %VGPR30<kill>, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR31<def> = V_SUB_F32_e32 1.000000e+00, %VGPR30, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR27<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR27<def> = V_CNDMASK_B32_e64 0, -1, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR27<def> = V_AND_B32_e32 1065353216, %VGPR27<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_MAD_F32 %VGPR27<kill>, %VGPR31<kill>, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_ADD_F32_e32 %VGPR6<kill>, %VGPR12<kill>, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 80; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR12<def> = V_MUL_F32_e32 %SGPR2, %VGPR3, %EXEC<imp-use>
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 81; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %VGPR2, %SGPR3, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 82; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR12<def> = V_MAD_F32 %VGPR10, %SGPR4, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR27<def> = V_MUL_F32_e32 %VGPR12, %VGPR3, %EXEC<imp-use>
	%VGPR27<def> = V_MAD_F32 %VGPR12, %VGPR3, %VGPR27<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR27<def> = V_SUB_F32_e32 %SGPR2<kill>, %VGPR27<kill>, %EXEC<imp-use>
	%VGPR17<def> = V_MAD_F32 %VGPR14, -4.000000e+00, %VGPR17<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR27<def> = V_MUL_F32_e32 %VGPR27<kill>, %VGPR17, %EXEC<imp-use>
	%VGPR31<def> = V_MUL_F32_e32 %VGPR27, %VGPR8, %EXEC<imp-use>
	%VGPR32<def> = V_MUL_F32_e32 %VGPR12, %VGPR2, %EXEC<imp-use>
	%VGPR32<def> = V_MAD_F32 %VGPR12, %VGPR2, %VGPR32<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR32<def> = V_SUB_F32_e32 %SGPR3<kill>, %VGPR32<kill>, %EXEC<imp-use>
	%VGPR32<def> = V_MUL_F32_e32 %VGPR32<kill>, %VGPR17, %EXEC<imp-use>
	%VGPR31<def> = V_MAD_F32 %VGPR32, %VGPR9, %VGPR31<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR33<def> = V_MUL_F32_e32 %VGPR12, %VGPR10, %EXEC<imp-use>
	%VGPR12<def> = V_MAD_F32 %VGPR12<kill>, %VGPR10, %VGPR33<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_SUB_F32_e32 %SGPR4<kill>, %VGPR12<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_MUL_F32_e32 %VGPR12<kill>, %VGPR17, %EXEC<imp-use>
	%VGPR31<def> = V_MAD_F32 %VGPR12, %VGPR5, %VGPR31<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR31<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR31<def> = V_CNDMASK_B32_e64 -nan, 1.401298e-45, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR31<def> = V_CVT_F32_I32_e32 %VGPR31<kill>, %EXEC<imp-use>
	%VGPR32<def> = V_MAD_F32 %VGPR32<kill>, %VGPR31, %VGPR7, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_MAD_F32 %VGPR12<kill>, %VGPR31, %VGPR20, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR33<def> = V_ADD_F32_e64 %VGPR12, 0, 0, 0, 0, 1, %EXEC<imp-use>
	%VGPR33<def> = V_RCP_F32_e32 %VGPR33<kill>, %EXEC<imp-use>
	%VGPR32<def> = V_MUL_F32_e32 %VGPR32<kill>, %VGPR33, %EXEC<imp-use>
	%VGPR32<def> = V_MUL_F32_e32 %SGPR27, %VGPR32<kill>, %EXEC<imp-use>
	%VGPR32<def> = V_SUBREV_F32_e32 %SGPR26, %VGPR32<kill>, %EXEC<imp-use>
	%VGPR32<def> = V_MAD_F32 %VGPR32<kill>, -5.000000e-01, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR35<def> = V_ADD_F32_e64 0, %VGPR32<kill>, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR34_VGPR35<imp-def>
	%VGPR27<def> = V_MAD_F32 %VGPR27<kill>, %VGPR31<kill>, %VGPR4, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR27<def> = V_MUL_F32_e32 %VGPR27<kill>, %VGPR33<kill>, %EXEC<imp-use>
	%VGPR27<def> = V_MUL_F32_e32 %SGPR29, %VGPR27<kill>, %EXEC<imp-use>
	%VGPR27<def> = V_SUBREV_F32_e32 %SGPR28, %VGPR27<kill>, %EXEC<imp-use>
	%VGPR27<def> = V_MAD_F32 %VGPR27<kill>, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR34<def> = V_ADD_F32_e64 0, %VGPR27<kill>, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR34_VGPR35<imp-use,kill>, %VGPR34_VGPR35<imp-def>
	%VGPR27<def> = IMAGE_SAMPLE_V1_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR34_VGPR35<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR31<def> = V_ADD_F32_e64 %VGPR27, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%VGPR31<def> = V_MUL_F32_e32 %SGPR24, %VGPR31<kill>, %EXEC<imp-use>
	%VGPR31<def> = V_SUBREV_F32_e32 %SGPR25, %VGPR31<kill>, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_EQ_F32_e64 %VGPR31, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR32<def> = V_CNDMASK_B32_e64 0.000000e+00, 1.401298e-45, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR32<def> = V_CVT_F32_I32_e32 %VGPR32<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_SUB_F32_e32 %VGPR31<kill>, %VGPR12<kill>, %EXEC<imp-use>
	%VGPR17<def> = V_ADD_F32_e32 %VGPR17<kill>, %VGPR17, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR12, %VGPR17<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR17<def> = V_CNDMASK_B32_e64 0, -1, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR17<def> = V_AND_B32_e32 1065353216, %VGPR17<kill>, %EXEC<imp-use>
	%VGPR17<def> = V_ADD_F32_e32 %VGPR17<kill>, %VGPR32<kill>, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_LE_F32_e64 %VGPR27<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR27<def> = V_CNDMASK_B32_e64 0, -1, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR27<def> = V_AND_B32_e32 1065353216, %VGPR27<kill>, %EXEC<imp-use>
	%VGPR17<def> = V_MAD_F32 %VGPR27<kill>, %VGPR1, %VGPR17<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR17<def> = V_ADD_F32_e64 0, %VGPR17<kill>, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR27<def> = V_SUB_F32_e32 1.000000e+00, %VGPR17, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR12<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_CNDMASK_B32_e64 0, -1, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_AND_B32_e32 1065353216, %VGPR12<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_MUL_F32_e32 %VGPR12<kill>, %VGPR27<kill>, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 76; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR27<def> = V_MUL_F32_e32 %SGPR2, %VGPR3, %EXEC<imp-use>
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 77; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR27<def> = V_MAD_F32 %VGPR2, %SGPR3, %VGPR27<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 78; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR27<def> = V_MAD_F32 %VGPR10, %SGPR4, %VGPR27<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR31<def> = V_MUL_F32_e32 %VGPR27, %VGPR3, %EXEC<imp-use>
	%VGPR31<def> = V_MAD_F32 %VGPR27, %VGPR3, %VGPR31<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR31<def> = V_SUB_F32_e32 %SGPR2<kill>, %VGPR31<kill>, %EXEC<imp-use>
	%VGPR21<def> = V_MAD_F32 %VGPR14, -4.000000e+00, %VGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR31<def> = V_MUL_F32_e32 %VGPR31<kill>, %VGPR21, %EXEC<imp-use>
	%VGPR32<def> = V_MUL_F32_e32 %VGPR31, %VGPR8, %EXEC<imp-use>
	%VGPR33<def> = V_MUL_F32_e32 %VGPR27, %VGPR2, %EXEC<imp-use>
	%VGPR33<def> = V_MAD_F32 %VGPR27, %VGPR2, %VGPR33<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR33<def> = V_SUB_F32_e32 %SGPR3<kill>, %VGPR33<kill>, %EXEC<imp-use>
	%VGPR33<def> = V_MUL_F32_e32 %VGPR33<kill>, %VGPR21, %EXEC<imp-use>
	%VGPR32<def> = V_MAD_F32 %VGPR33, %VGPR9, %VGPR32<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR34<def> = V_MUL_F32_e32 %VGPR27, %VGPR10, %EXEC<imp-use>
	%VGPR27<def> = V_MAD_F32 %VGPR27<kill>, %VGPR10, %VGPR34<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR27<def> = V_SUB_F32_e32 %SGPR4<kill>, %VGPR27<kill>, %EXEC<imp-use>
	%VGPR27<def> = V_MUL_F32_e32 %VGPR27<kill>, %VGPR21, %EXEC<imp-use>
	%VGPR32<def> = V_MAD_F32 %VGPR27, %VGPR5, %VGPR32<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR32<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR32<def> = V_CNDMASK_B32_e64 -nan, 1.401298e-45, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR32<def> = V_CVT_F32_I32_e32 %VGPR32<kill>, %EXEC<imp-use>
	%VGPR33<def> = V_MAD_F32 %VGPR33<kill>, %VGPR32, %VGPR7, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR27<def> = V_MAD_F32 %VGPR27<kill>, %VGPR32, %VGPR20, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR34<def> = V_ADD_F32_e64 %VGPR27, 0, 0, 0, 0, 1, %EXEC<imp-use>
	%VGPR34<def> = V_RCP_F32_e32 %VGPR34<kill>, %EXEC<imp-use>
	%VGPR33<def> = V_MUL_F32_e32 %VGPR33<kill>, %VGPR34, %EXEC<imp-use>
	%VGPR33<def> = V_MUL_F32_e32 %SGPR27, %VGPR33<kill>, %EXEC<imp-use>
	%VGPR33<def> = V_SUBREV_F32_e32 %SGPR26, %VGPR33<kill>, %EXEC<imp-use>
	%VGPR33<def> = V_MAD_F32 %VGPR33<kill>, -5.000000e-01, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR36<def> = V_ADD_F32_e64 0, %VGPR33<kill>, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR35_VGPR36<imp-def>
	%VGPR31<def> = V_MAD_F32 %VGPR31<kill>, %VGPR32<kill>, %VGPR4, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR31<def> = V_MUL_F32_e32 %VGPR31<kill>, %VGPR34<kill>, %EXEC<imp-use>
	%VGPR31<def> = V_MUL_F32_e32 %SGPR29, %VGPR31<kill>, %EXEC<imp-use>
	%VGPR31<def> = V_SUBREV_F32_e32 %SGPR28, %VGPR31<kill>, %EXEC<imp-use>
	%VGPR31<def> = V_MAD_F32 %VGPR31<kill>, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR35<def> = V_ADD_F32_e64 0, %VGPR31<kill>, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR35_VGPR36<imp-use,kill>, %VGPR35_VGPR36<imp-def>
	%VGPR31<def> = IMAGE_SAMPLE_V1_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR35_VGPR36<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR32<def> = V_ADD_F32_e64 %VGPR31, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%VGPR32<def> = V_MUL_F32_e32 %SGPR24, %VGPR32<kill>, %EXEC<imp-use>
	%VGPR32<def> = V_SUBREV_F32_e32 %SGPR25, %VGPR32<kill>, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_EQ_F32_e64 %VGPR32, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR33<def> = V_CNDMASK_B32_e64 0.000000e+00, 1.401298e-45, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR33<def> = V_CVT_F32_I32_e32 %VGPR33<kill>, %EXEC<imp-use>
	%VGPR27<def> = V_SUB_F32_e32 %VGPR32<kill>, %VGPR27<kill>, %EXEC<imp-use>
	%VGPR21<def> = V_ADD_F32_e32 %VGPR21<kill>, %VGPR21, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR27, %VGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR21<def> = V_CNDMASK_B32_e64 0, -1, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR21<def> = V_AND_B32_e32 1065353216, %VGPR21<kill>, %EXEC<imp-use>
	%VGPR21<def> = V_ADD_F32_e32 %VGPR21<kill>, %VGPR33<kill>, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_LE_F32_e64 %VGPR31<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR31<def> = V_CNDMASK_B32_e64 0, -1, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR31<def> = V_AND_B32_e32 1065353216, %VGPR31<kill>, %EXEC<imp-use>
	%VGPR21<def> = V_MAD_F32 %VGPR31<kill>, %VGPR1, %VGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR21<def> = V_ADD_F32_e64 0, %VGPR21<kill>, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR31<def> = V_SUB_F32_e32 1.000000e+00, %VGPR21, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR27<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR27<def> = V_CNDMASK_B32_e64 0, -1, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR27<def> = V_AND_B32_e32 1065353216, %VGPR27<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_MAD_F32 %VGPR27<kill>, %VGPR31<kill>, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 84; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR27<def> = V_MUL_F32_e32 %SGPR2, %VGPR3, %EXEC<imp-use>
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 85; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR27<def> = V_MAD_F32 %VGPR2, %SGPR3, %VGPR27<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 86; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR27<def> = V_MAD_F32 %VGPR10, %SGPR4, %VGPR27<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR31<def> = V_MUL_F32_e32 %VGPR27, %VGPR3, %EXEC<imp-use>
	%VGPR31<def> = V_MAD_F32 %VGPR27, %VGPR3, %VGPR31<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR31<def> = V_SUB_F32_e32 %SGPR2<kill>, %VGPR31<kill>, %EXEC<imp-use>
	%VGPR23<def> = V_MAD_F32 %VGPR14, -4.000000e+00, %VGPR23<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR31<def> = V_MUL_F32_e32 %VGPR31<kill>, %VGPR23, %EXEC<imp-use>
	%VGPR32<def> = V_MUL_F32_e32 %VGPR31, %VGPR8, %EXEC<imp-use>
	%VGPR33<def> = V_MUL_F32_e32 %VGPR27, %VGPR2, %EXEC<imp-use>
	%VGPR33<def> = V_MAD_F32 %VGPR27, %VGPR2, %VGPR33<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR33<def> = V_SUB_F32_e32 %SGPR3<kill>, %VGPR33<kill>, %EXEC<imp-use>
	%VGPR33<def> = V_MUL_F32_e32 %VGPR33<kill>, %VGPR23, %EXEC<imp-use>
	%VGPR32<def> = V_MAD_F32 %VGPR33, %VGPR9, %VGPR32<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR34<def> = V_MUL_F32_e32 %VGPR27, %VGPR10, %EXEC<imp-use>
	%VGPR27<def> = V_MAD_F32 %VGPR27<kill>, %VGPR10, %VGPR34<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR27<def> = V_SUB_F32_e32 %SGPR4<kill>, %VGPR27<kill>, %EXEC<imp-use>
	%VGPR27<def> = V_MUL_F32_e32 %VGPR27<kill>, %VGPR23, %EXEC<imp-use>
	%VGPR32<def> = V_MAD_F32 %VGPR27, %VGPR5, %VGPR32<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR32<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR32<def> = V_CNDMASK_B32_e64 -nan, 1.401298e-45, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR32<def> = V_CVT_F32_I32_e32 %VGPR32<kill>, %EXEC<imp-use>
	%VGPR33<def> = V_MAD_F32 %VGPR33<kill>, %VGPR32, %VGPR7, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR27<def> = V_MAD_F32 %VGPR27<kill>, %VGPR32, %VGPR20, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR34<def> = V_ADD_F32_e64 %VGPR27, 0, 0, 0, 0, 1, %EXEC<imp-use>
	%VGPR34<def> = V_RCP_F32_e32 %VGPR34<kill>, %EXEC<imp-use>
	%VGPR33<def> = V_MUL_F32_e32 %VGPR33<kill>, %VGPR34, %EXEC<imp-use>
	%VGPR33<def> = V_MUL_F32_e32 %SGPR27, %VGPR33<kill>, %EXEC<imp-use>
	%VGPR33<def> = V_SUBREV_F32_e32 %SGPR26, %VGPR33<kill>, %EXEC<imp-use>
	%VGPR33<def> = V_MAD_F32 %VGPR33<kill>, -5.000000e-01, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR36<def> = V_ADD_F32_e64 0, %VGPR33<kill>, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR35_VGPR36<imp-def>
	%VGPR31<def> = V_MAD_F32 %VGPR31<kill>, %VGPR32<kill>, %VGPR4, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR31<def> = V_MUL_F32_e32 %VGPR31<kill>, %VGPR34<kill>, %EXEC<imp-use>
	%VGPR31<def> = V_MUL_F32_e32 %SGPR29, %VGPR31<kill>, %EXEC<imp-use>
	%VGPR31<def> = V_SUBREV_F32_e32 %SGPR28, %VGPR31<kill>, %EXEC<imp-use>
	%VGPR31<def> = V_MAD_F32 %VGPR31<kill>, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR35<def> = V_ADD_F32_e64 0, %VGPR31<kill>, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR35_VGPR36<imp-use,kill>, %VGPR35_VGPR36<imp-def>
	%VGPR31<def> = IMAGE_SAMPLE_V1_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR35_VGPR36<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR32<def> = V_ADD_F32_e64 %VGPR31, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%VGPR32<def> = V_MUL_F32_e32 %SGPR24, %VGPR32<kill>, %EXEC<imp-use>
	%VGPR32<def> = V_SUBREV_F32_e32 %SGPR25, %VGPR32<kill>, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_EQ_F32_e64 %VGPR32, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR33<def> = V_CNDMASK_B32_e64 0.000000e+00, 1.401298e-45, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR33<def> = V_CVT_F32_I32_e32 %VGPR33<kill>, %EXEC<imp-use>
	%VGPR27<def> = V_SUB_F32_e32 %VGPR32<kill>, %VGPR27<kill>, %EXEC<imp-use>
	%VGPR23<def> = V_ADD_F32_e32 %VGPR23<kill>, %VGPR23, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR27, %VGPR23<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR23<def> = V_CNDMASK_B32_e64 0, -1, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR23<def> = V_AND_B32_e32 1065353216, %VGPR23<kill>, %EXEC<imp-use>
	%VGPR23<def> = V_ADD_F32_e32 %VGPR23<kill>, %VGPR33<kill>, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_LE_F32_e64 %VGPR31<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR31<def> = V_CNDMASK_B32_e64 0, -1, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR31<def> = V_AND_B32_e32 1065353216, %VGPR31<kill>, %EXEC<imp-use>
	%VGPR23<def> = V_MAD_F32 %VGPR31<kill>, %VGPR1, %VGPR23<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR23<def> = V_ADD_F32_e64 0, %VGPR23<kill>, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR31<def> = V_SUB_F32_e32 1.000000e+00, %VGPR23, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR27<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR27<def> = V_CNDMASK_B32_e64 0, -1, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR27<def> = V_AND_B32_e32 1065353216, %VGPR27<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_MAD_F32 %VGPR27<kill>, %VGPR31<kill>, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 88; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR27<def> = V_MUL_F32_e32 %SGPR2, %VGPR3, %EXEC<imp-use>
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23, 89; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR27<def> = V_MAD_F32 %VGPR2, %SGPR3, %VGPR27<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR20_SGPR21_SGPR22_SGPR23<kill>, 90; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR27<def> = V_MAD_F32 %VGPR10, %SGPR4, %VGPR27<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR31<def> = V_MUL_F32_e32 %VGPR27, %VGPR3, %EXEC<imp-use>
	%VGPR3<def> = V_MAD_F32 %VGPR27, %VGPR3<kill>, %VGPR31<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_SUB_F32_e32 %SGPR2<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR14<def> = V_MAD_F32 %VGPR14<kill>, -4.000000e+00, %VGPR25<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_MUL_F32_e32 %VGPR3<kill>, %VGPR14, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_F32_e32 %VGPR3, %VGPR8<kill>, %EXEC<imp-use>
	%VGPR25<def> = V_MUL_F32_e32 %VGPR27, %VGPR2, %EXEC<imp-use>
	%VGPR2<def> = V_MAD_F32 %VGPR27, %VGPR2<kill>, %VGPR25<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR2<def> = V_SUB_F32_e32 %SGPR3<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_MUL_F32_e32 %VGPR2<kill>, %VGPR14, %EXEC<imp-use>
	%VGPR8<def> = V_MAD_F32 %VGPR2, %VGPR9<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_MUL_F32_e32 %VGPR27, %VGPR10, %EXEC<imp-use>
	%VGPR9<def> = V_MAD_F32 %VGPR27<kill>, %VGPR10<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_SUB_F32_e32 %SGPR4<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_MUL_F32_e32 %VGPR9<kill>, %VGPR14, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR9, %VGPR5<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR5<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_CNDMASK_B32_e64 -nan, 1.401298e-45, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_CVT_F32_I32_e32 %VGPR5<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_MAD_F32 %VGPR2<kill>, %VGPR5, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR9<kill>, %VGPR5, %VGPR20<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_ADD_F32_e64 %VGPR7, 0, 0, 0, 0, 1, %EXEC<imp-use>
	%VGPR8<def> = V_RCP_F32_e32 %VGPR8<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_MUL_F32_e32 %VGPR2<kill>, %VGPR8, %EXEC<imp-use>
	%VGPR2<def> = V_MUL_F32_e32 %SGPR27<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_SUBREV_F32_e32 %SGPR26<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_MAD_F32 %VGPR2<kill>, -5.000000e-01, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR10<def> = V_ADD_F32_e64 0, %VGPR2<kill>, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR9_VGPR10<imp-def>
	%VGPR2<def> = V_MAD_F32 %VGPR3<kill>, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR2<def> = V_MUL_F32_e32 %VGPR2<kill>, %VGPR8<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_MUL_F32_e32 %SGPR29<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_SUBREV_F32_e32 %SGPR28<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_MAD_F32 %VGPR2<kill>, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_ADD_F32_e64 0, %VGPR2<kill>, 0, 1, 0, 0, %EXEC<imp-use>, %VGPR9_VGPR10<imp-use,kill>, %VGPR9_VGPR10<imp-def>
	%VGPR2<def> = IMAGE_SAMPLE_V1_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR9_VGPR10<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR3<def> = V_ADD_F32_e64 %VGPR2, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_MUL_F32_e32 %SGPR24<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_SUBREV_F32_e32 %SGPR25<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_EQ_F32_e64 %VGPR3, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_CNDMASK_B32_e64 0.000000e+00, 1.401298e-45, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_CVT_F32_I32_e32 %VGPR4<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_SUB_F32_e32 %VGPR3<kill>, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_ADD_F32_e32 %VGPR14<kill>, %VGPR14, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR3, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_CNDMASK_B32_e64 0, -1, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_AND_B32_e32 1065353216, %VGPR5<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_ADD_F32_e32 %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_LE_F32_e64 %VGPR2<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR2<def> = V_CNDMASK_B32_e64 0, -1, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR2<def> = V_AND_B32_e32 1065353216, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_MAD_F32 %VGPR2<kill>, %VGPR1<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_ADD_F32_e64 0, %VGPR1<kill>, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR2<def> = V_SUB_F32_e32 1.000000e+00, %VGPR1, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR3<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_CNDMASK_B32_e64 0, -1, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_AND_B32_e32 1065353216, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_MAD_F32 %VGPR3<kill>, %VGPR2<kill>, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR2<def> = V_ADD_F32_e32 %VGPR6<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_ADD_F32_e32 %VGPR18<kill>, %VGPR11<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_ADD_F32_e32 %VGPR3<kill>, %VGPR22<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_ADD_F32_e32 %VGPR3<kill>, %VGPR24<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_ADD_F32_e32 %VGPR19<kill>, %VGPR16<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_ADD_F32_e32 %VGPR4<kill>, %VGPR15<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_ADD_F32_e32 %VGPR4<kill>, %VGPR13<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_ADD_F32_e32 %VGPR4<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_ADD_F32_e32 %VGPR28<kill>, %VGPR26<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_ADD_F32_e32 %VGPR4<kill>, %VGPR29<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_ADD_F32_e32 %VGPR4<kill>, %VGPR30<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_ADD_F32_e32 %VGPR3<kill>, %VGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_ADD_F32_e32 %VGPR21<kill>, %VGPR17<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_ADD_F32_e32 %VGPR4<kill>, %VGPR23<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_ADD_F32_e32 %VGPR4<kill>, %VGPR1<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_ADD_F32_e32 %VGPR3<kill>, %VGPR1<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_SUB_F32_e32 1.600000e+01, %VGPR1<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_RCP_F32_e32 %VGPR1<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e32 %VGPR2<kill>, %VGPR1<kill>, %EXEC<imp-use>
    Successors according to CFG: BB#2

BB#2: derived from LLVM BB %ENDIF
    Live Ins: %VGPR0 %SGPR0_SGPR1 %VGPR4
    Predecessors according to CFG: BB#0 BB#1
	%EXEC<def> = S_OR_B64 %EXEC, %SGPR0_SGPR1
	%VGPR0<def> = V_MUL_F32_e64 %VGPR4<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_F32_e64 0, %VGPR0<kill>, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_SUB_F32_e32 1.000000e+00, %VGPR0<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR0<kill>, %VGPR0, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 0.000000e+00, %VGPR0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_CVT_PKRTZ_F16_F32_e64 0.000000e+00, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR1<kill>, %VGPR0<kill>, %VGPR1, %VGPR0, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_WQM_B64 exec, exec                                                        ; BEFE0A7E
	S_MOV_B32 m0, s7                                                            ; BEFC0307
	V_INTERP_P1_F32 v2, v0, 1, 0, [m0]                                          ; C8080100
	V_INTERP_P2_F32 v2, [v2], v1, 1, 0, [m0]                                    ; C8090101
	S_LOAD_DWORDX4 s[20:23], s[0:1], 0                                          ; C08A0100
	S_WAITCNT lgkmcnt(0)                                                        ; BF8C007F
	S_BUFFER_LOAD_DWORD s0, s[20:23], 17                                        ; C2001511
	S_WAITCNT lgkmcnt(0)                                                        ; BF8C007F
	V_MAD_F32 v2, v2, s0, 5.000000e-01, 0, 0, 0, 0                              ; D2820002 03C00102
	V_FRACT_F32_e32 v3, v2                                                      ; 7E064102
	V_SUB_F32_e32 v2, v2, v3                                                    ; 08040702
	V_ADD_F32_e32 v2, 5.000000e-01, v2                                          ; 060404F0
	S_BUFFER_LOAD_DWORD s6, s[20:23], 19                                        ; C2031513
	S_WAITCNT lgkmcnt(0)                                                        ; BF8C007F
	V_MUL_F32_e32 v3, s6, v2                                                    ; 10060406
	V_INTERP_P1_F32 v4, v0, 0, 0, [m0]                                          ; C8100000
	V_INTERP_P2_F32 v4, [v4], v1, 0, 0, [m0]                                    ; C8110001
	S_BUFFER_LOAD_DWORD s0, s[20:23], 16                                        ; C2001510
	S_WAITCNT lgkmcnt(0)                                                        ; BF8C007F
	V_MAD_F32 v0, v4, s0, 5.000000e-01, 0, 0, 0, 0                              ; D2820000 03C00104
	V_FRACT_F32_e32 v1, v0                                                      ; 7E024100
	V_SUB_F32_e32 v0, v0, v1                                                    ; 08000300
	V_ADD_F32_e32 v0, 5.000000e-01, v0                                          ; 060000F0
	S_BUFFER_LOAD_DWORD s7, s[20:23], 18                                        ; C2039512
	S_WAITCNT lgkmcnt(0)                                                        ; BF8C007F
	V_MUL_F32_e32 v2, s7, v0                                                    ; 10040007
	S_LOAD_DWORDX4 s[8:11], s[2:3], 0                                           ; C0840300
	S_LOAD_DWORDX8 s[12:19], s[4:5], 0                                          ; C0C60500
	S_WAITCNT lgkmcnt(0)                                                        ; BF8C007F
	IMAGE_SAMPLE v1, 1, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[12:19], s[8:11]          ; F0800100 00430102
	V_MOV_B32_e32 v0, 9.500000e-01                                              ; 7E0002FF 3F733333
	S_WAITCNT vmcnt(0)                                                          ; BF8C0770
	V_CMP_LT_F32_e64 s[0:1], v1, v0, 0, 0, 0, 0                                 ; D0020000 02020101
	S_BUFFER_LOAD_DWORD s24, s[20:23], 25                                       ; C20C1519
	V_MOV_B32_e32 v4, 0.000000e+00                                              ; 7E080280
	S_WAITCNT lgkmcnt(0)                                                        ; BF8C007F
	V_MOV_B32_e32 v0, s24                                                       ; 7E000218
	S_AND_SAVEEXEC_B64 s[0:1], s[0:1]                                           ; BE802400
	S_XOR_B64 s[0:1], exec, s[0:1]                                              ; 8980007E
	S_CBRANCH_EXECZ ";.BB0_2"                                                   ; BF880000
	V_ADD_F32_e64 v4, v1, 0, 1, 0, 0, 0                                         ; D2060104 02010101
	S_BUFFER_LOAD_DWORD s24, s[20:23], 5                                        ; C20C1505
	S_WAITCNT lgkmcnt(0)                                                        ; BF8C007F
	V_MUL_F32_e32 v4, s24, v4                                                   ; 10080818
	S_BUFFER_LOAD_DWORD s25, s[20:23], 4                                        ; C20C9504
	S_WAITCNT lgkmcnt(0)                                                        ; BF8C007F
	V_SUBREV_F32_e32 v4, s25, v4                                                ; 0A080819
	V_MOV_B32_e32 v5, s7                                                        ; 7E0A0207
	V_ADD_F32_e64 v6, v2, v5, 0, 0, 0, 0                                        ; D2060006 02020B02
	V_ADD_F32_e64 v7, v3, 0.000000e+00, 0, 0, 0, 0                              ; D2060007 02010103
	IMAGE_SAMPLE v8, 1, 0, 0, 0, 0, 0, 0, 0, v[6:7], s[12:19], s[8:11]          ; F0800100 00430806
	S_WAITCNT vmcnt(0)                                                          ; BF8C0770
	V_ADD_F32_e64 v8, v8, 0, 1, 0, 0, 0                                         ; D2060108 02010108
	V_MUL_F32_e32 v8, s24, v8                                                   ; 10101018
	V_SUBREV_F32_e32 v8, s25, v8                                                ; 0A101019
	V_SUB_F32_e32 v9, v8, v4                                                    ; 08120908
	V_ADD_F32_e64 v9, v9, 0, 1, 0, 0, 0                                         ; D2060109 02010109
	V_SUB_F32_e64 v10, v2, v5, 0, 0, 0, 0                                       ; D208000A 02020B02
	V_MOV_B32_e32 v11, v7                                                       ; 7E160307
	IMAGE_SAMPLE v5, 1, 0, 0, 0, 0, 0, 0, 0, v[10:11], s[12:19], s[8:11]        ; F0800100 0043050A
	S_WAITCNT vmcnt(0)                                                          ; BF8C0770
	V_ADD_F32_e64 v5, v5, 0, 1, 0, 0, 0                                         ; D2060105 02010105
	V_MUL_F32_e32 v5, s24, v5                                                   ; 100A0A18
	V_SUBREV_F32_e32 v5, s25, v5                                                ; 0A0A0A19
	V_SUB_F32_e32 v12, v5, v4                                                   ; 08180905
	V_ADD_F32_e64 v12, v12, 0, 1, 0, 0, 0                                       ; D206010C 0201010C
	V_CMP_LT_F32_e64 s[26:27], v12, v9, 0, 0, 0, 0                              ; D002001A 0202130C
	V_CNDMASK_B32_e64 v5, v8, v5, s[26:27], 0, 0, 0, 0                          ; D2000005 006A0B08
	V_SUB_F32_e32 v8, v5, v4                                                    ; 08100905
	V_CNDMASK_B32_e64 v9, 1.000000e+00, -1.000000e+00, s[26:27], 0, 0, 0, 0     ; D2000009 0069E6F2
	V_MUL_F32_e32 v8, v8, v9                                                    ; 10101308
	V_MOV_B32_e32 v12, s6                                                       ; 7E180206
	V_ADD_F32_e64 v14, v3, v12, 0, 0, 0, 0                                      ; D206000E 02021903
	V_ADD_F32_e64 v13, v2, 0.000000e+00, 0, 0, 0, 0                             ; D206000D 02010102
	IMAGE_SAMPLE v15, 1, 0, 0, 0, 0, 0, 0, 0, v[13:14], s[12:19], s[8:11]       ; F0800100 00430F0D
	S_WAITCNT vmcnt(0)                                                          ; BF8C0770
	V_ADD_F32_e64 v15, v15, 0, 1, 0, 0, 0                                       ; D206010F 0201010F
	V_MUL_F32_e32 v15, s24, v15                                                 ; 101E1E18
	V_SUBREV_F32_e32 v15, s25, v15                                              ; 0A1E1E19
	V_SUB_F32_e32 v16, v15, v4                                                  ; 0820090F
	V_ADD_F32_e64 v16, v16, 0, 1, 0, 0, 0                                       ; D2060110 02010110
	V_SUB_F32_e64 v12, v3, v12, 0, 0, 0, 0                                      ; D208000C 02021903
	V_MOV_B32_e32 v17, v13                                                      ; 7E22030D
	V_MOV_B32_e32 v18, v14                                                      ; 7E24030E
	V_MOV_B32_e32 v18, v12                                                      ; 7E24030C
	IMAGE_SAMPLE v17, 1, 0, 0, 0, 0, 0, 0, 0, v[17:18], s[12:19], s[8:11]       ; F0800100 00431111
	S_WAITCNT vmcnt(0)                                                          ; BF8C0770
	V_ADD_F32_e64 v17, v17, 0, 1, 0, 0, 0                                       ; D2060111 02010111
	V_MUL_F32_e32 v17, s24, v17                                                 ; 10222218
	V_SUBREV_F32_e32 v17, s25, v17                                              ; 0A222219
	V_SUB_F32_e32 v18, v17, v4                                                  ; 08240911
	V_ADD_F32_e64 v18, v18, 0, 1, 0, 0, 0                                       ; D2060112 02010112
	V_CMP_LT_F32_e64 s[6:7], v18, v16, 0, 0, 0, 0                               ; D0020006 02022112
	V_CNDMASK_B32_e64 v15, v15, v17, s[6:7], 0, 0, 0, 0                         ; D200000F 001A230F
	V_ADD_F32_e64 v16, v15, 0, 0, 0, 0, 1                                       ; D2060010 2201010F
	S_BUFFER_LOAD_DWORD s28, s[20:23], 9                                        ; C20E1509
	V_ADD_F32_e32 v17, v13, v13                                                 ; 06221B0D
	V_ADD_F32_e32 v17, -1.000000e+00, v17                                       ; 062222F3
	S_WAITCNT lgkmcnt(0)                                                        ; BF8C007F
	V_ADD_F32_e32 v17, s28, v17                                                 ; 0622221C
	V_MUL_F32_e32 v17, v16, v17                                                 ; 10222310
	S_BUFFER_LOAD_DWORD s29, s[20:23], 8                                        ; C20E9508
	S_WAITCNT lgkmcnt(0)                                                        ; BF8C007F
	V_RCP_F32_e32 v18, s29                                                      ; 7E24541D
	V_MUL_F32_e32 v17, v17, v18                                                 ; 10222511
	V_ADD_F32_e64 v19, v2, v2, 0, 0, 0, 0                                       ; D2060013 02020502
	V_ADD_F32_e32 v19, -1.000000e+00, v19                                       ; 062626F3
	V_ADD_F32_e32 v19, s28, v19                                                 ; 0626261C
	V_ADD_F32_e64 v20, v4, 0, 0, 0, 0, 1                                        ; D2060014 22010104
	V_MUL_F32_e32 v19, v20, v19                                                 ; 10262714
	V_MUL_F32_e32 v19, v19, v18                                                 ; 10262513
	V_SUB_F32_e32 v17, v17, v19                                                 ; 08222711
	V_CNDMASK_B32_e64 v21, 1.000000e+00, -1.000000e+00, s[6:7], 0, 0, 0, 0      ; D2000015 0019E6F2
	V_MUL_F32_e32 v17, v17, v21                                                 ; 10222B11
	V_MUL_F32_e32 v22, v17, v8                                                  ; 102C1111
	V_SUB_F32_e32 v15, v15, v4                                                  ; 081E090F
	V_MUL_F32_e32 v15, v15, v21                                                 ; 101E2B0F
	V_CNDMASK_B32_e64 v10, v6, v10, s[26:27], 0, 0, 0, 0                        ; D200000A 006A1506
	V_ADD_F32_e32 v10, v10, v10                                                 ; 0614150A
	V_ADD_F32_e32 v10, -1.000000e+00, v10                                       ; 061414F3
	V_ADD_F32_e32 v10, s28, v10                                                 ; 0614141C
	V_ADD_F32_e64 v5, v5, 0, 0, 0, 0, 1                                         ; D2060005 22010105
	V_MUL_F32_e32 v10, v5, v10                                                  ; 10141505
	V_MUL_F32_e32 v10, v10, v18                                                 ; 1014250A
	V_SUB_F32_e32 v10, v10, v19                                                 ; 0814270A
	V_MUL_F32_e32 v10, v10, v9                                                  ; 1014130A
	V_MUL_F32_e32 v11, v15, v10                                                 ; 1016150F
	V_SUB_F32_e32 v11, v11, v22                                                 ; 08162D0B
	S_BUFFER_LOAD_DWORD s26, s[20:23], 11                                       ; C20D150B
	V_MAD_F32 v6, v7, -2.000000e+00, 1.000000e+00, 0, 0, 0, 0                   ; D2820006 03C9EB07
	S_WAITCNT lgkmcnt(0)                                                        ; BF8C007F
	V_ADD_F32_e32 v6, s26, v6                                                   ; 060C0C1A
	V_MUL_F32_e32 v5, v5, v6                                                    ; 100A0D05
	S_BUFFER_LOAD_DWORD s27, s[20:23], 10                                       ; C20D950A
	S_WAITCNT lgkmcnt(0)                                                        ; BF8C007F
	V_RCP_F32_e32 v6, s27                                                       ; 7E0C541B
	V_MUL_F32_e32 v5, v5, v6                                                    ; 100A0D05
	V_MAD_F32 v7, v3, -2.000000e+00, 1.000000e+00, 0, 0, 0, 0                   ; D2820007 03C9EB03
	V_ADD_F32_e32 v7, s26, v7                                                   ; 060E0E1A
	V_MUL_F32_e32 v7, v20, v7                                                   ; 100E0F14
	V_MUL_F32_e32 v7, v7, v6                                                    ; 100E0D07
	V_SUB_F32_e32 v5, v5, v7                                                    ; 080A0F05
	V_MUL_F32_e32 v5, v5, v9                                                    ; 100A1305
	V_MUL_F32_e32 v9, v15, v5                                                   ; 10120B0F
	V_CNDMASK_B32_e64 v12, v14, v12, s[6:7], 0, 0, 0, 0                         ; D200000C 001A190E
	V_MAD_F32 v12, v12, -2.000000e+00, 1.000000e+00, 0, 0, 0, 0                 ; D282000C 03C9EB0C
	V_ADD_F32_e32 v12, s26, v12                                                 ; 0618181A
	V_MUL_F32_e32 v12, v16, v12                                                 ; 10181910
	V_MUL_F32_e32 v6, v12, v6                                                   ; 100C0D0C
	V_SUB_F32_e32 v6, v6, v7                                                    ; 080C0F06
	V_MUL_F32_e32 v6, v6, v21                                                   ; 100C2B06
	V_MUL_F32_e32 v8, v6, v8                                                    ; 10101106
	V_SUB_F32_e32 v8, v8, v9                                                    ; 08101308
	V_MUL_F32_e32 v9, v8, v8                                                    ; 10121108
	V_MAD_F32 v9, v11, v11, v9, 0, 0, 0, 0                                      ; D2820009 0426170B
	V_MUL_F32_e32 v5, v17, v5                                                   ; 100A0B11
	V_MUL_F32_e32 v6, v6, v10                                                   ; 100C1506
	V_SUB_F32_e32 v5, v5, v6                                                    ; 080A0D05
	V_MAD_F32 v6, v5, v5, v9, 0, 0, 0, 0                                        ; D2820006 04260B05
	V_RSQ_LEGACY_F32_e32 v6, v6                                                 ; 7E0C5B06
	V_MUL_F32_e32 v9, v11, v6                                                   ; 10120D0B
	V_MUL_F32_e32 v8, v8, v6                                                    ; 10100D08
	S_BUFFER_LOAD_DWORD s6, s[20:23], 13                                        ; C203150D
	V_MOV_B32_e32 v10, 2.500000e-01                                             ; 7E1402FF 3E800000
	S_WAITCNT lgkmcnt(0)                                                        ; BF8C007F
	V_MUL_F32_e32 v11, s6, v10                                                  ; 10161406
	V_MUL_F32_e32 v12, v3, v11                                                  ; 10181703
	S_BUFFER_LOAD_DWORD s6, s[20:23], 12                                        ; C203150C
	S_WAITCNT lgkmcnt(0)                                                        ; BF8C007F
	V_MUL_F32_e32 v10, s6, v10                                                  ; 10141406
	V_MUL_F32_e32 v11, v2, v10                                                  ; 10161502
	S_LOAD_DWORDX4 s[32:35], s[2:3], 4                                          ; C0900304
	S_LOAD_DWORDX8 s[36:43], s[4:5], 8                                          ; C0D20508
	S_WAITCNT lgkmcnt(0)                                                        ; BF8C007F
	IMAGE_SAMPLE v[10:12], 7, 0, 0, 0, 0, 0, 0, 0, v[11:12], s[36:43], s[32:35] ; F0800700 01090A0B
	S_WAITCNT vmcnt(0)                                                          ; BF8C0770
	V_ADD_F32_e32 v2, v11, v11                                                  ; 0604170B
	V_ADD_F32_e32 v2, -1.000000e+00, v2                                         ; 060404F3
	S_BUFFER_LOAD_DWORD s2, s[20:23], 3                                         ; C2011503
	S_WAITCNT lgkmcnt(0)                                                        ; BF8C007F
	V_MUL_F32_e32 v2, s2, v2                                                    ; 10040402
	V_ADD_F32_e32 v3, v10, v10                                                  ; 0606150A
	V_ADD_F32_e32 v3, -1.000000e+00, v3                                         ; 060606F3
	V_MUL_F32_e32 v3, s2, v3                                                    ; 10060602
	S_BUFFER_LOAD_DWORD s3, s[20:23], 48                                        ; C2019530
	S_WAITCNT lgkmcnt(0)                                                        ; BF8C007F
	V_MUL_F32_e32 v13, s3, v3                                                   ; 101A0603
	S_BUFFER_LOAD_DWORD s4, s[20:23], 49                                        ; C2021531
	S_WAITCNT lgkmcnt(0)                                                        ; BF8C007F
	V_MAD_F32 v13, v2, s4, v13, 0, 0, 0, 0                                      ; D282000D 04340902
	V_ADD_F32_e32 v10, v12, v12                                                 ; 0614190C
	V_ADD_F32_e32 v10, -1.000000e+00, v10                                       ; 061414F3
	V_MUL_F32_e32 v10, s2, v10                                                  ; 10141402
	S_BUFFER_LOAD_DWORD s2, s[20:23], 50                                        ; C2011532
	S_WAITCNT lgkmcnt(0)                                                        ; BF8C007F
	V_MAD_F32 v11, v10, s2, v13, 0, 0, 0, 0                                     ; D282000B 0434050A
	V_MUL_F32_e32 v12, v11, v3                                                  ; 1018070B
	V_MAD_F32 v12, v11, v3, v12, 0, 0, 0, 0                                     ; D282000C 0432070B
	V_SUB_F32_e32 v12, s3, v12                                                  ; 08181803
	S_BUFFER_LOAD_DWORD s3, s[20:23], 20                                        ; C2019514
	S_WAITCNT lgkmcnt(0)                                                        ; BF8C007F
	V_SUBREV_F32_e32 v13, s3, v20                                               ; 0A1A2803
	S_BUFFER_LOAD_DWORD s3, s[20:23], 23                                        ; C2019517
	S_WAITCNT lgkmcnt(0)                                                        ; BF8C007F
	V_MUL_F32_e32 v13, s3, v13                                                  ; 101A1A03
	V_ADD_F32_e64 v13, 0, v13, 0, 1, 0, 0                                       ; D206080D 02021A80
	S_BUFFER_LOAD_DWORD s3, s[20:23], 22                                        ; C2019516
	S_WAITCNT lgkmcnt(0)                                                        ; BF8C007F
	V_MAD_F32 v13, s3, v13, 1.000000e+00, 0, 0, 0, 0                            ; D282000D 03CA1A03
	S_BUFFER_LOAD_DWORD s3, s[20:23], 21                                        ; C2019515
	S_WAITCNT lgkmcnt(0)                                                        ; BF8C007F
	V_MUL_F32_e32 v14, s3, v20                                                  ; 101C2803
	V_ADD_F32_e64 v14, 0, v14, 0, 1, 0, 0                                       ; D206080E 02021C80
	V_MUL_F32_e32 v13, v13, v14                                                 ; 101A1D0D
	V_CMP_LT_F32_e64 s[6:7], v1, 0.000000e+00, 0, 0, 0, 0                       ; D0020006 02010101
	S_BUFFER_LOAD_DWORD s3, s[20:23], 24                                        ; C2019518
	S_WAITCNT lgkmcnt(0)                                                        ; BF8C007F
	V_MOV_B32_e32 v14, s3                                                       ; 7E1C0203
	V_CNDMASK_B32_e64 v13, v13, v14, s[6:7], 0, 0, 0, 0                         ; D200000D 001A1D0D
	S_BUFFER_LOAD_DWORD s3, s[20:23], 26                                        ; C201951A
	S_WAITCNT lgkmcnt(0)                                                        ; BF8C007F
	V_MUL_F32_e32 v13, s3, v13                                                  ; 101A1A03
	S_BUFFER_LOAD_DWORD s3, s[20:23], 1                                         ; C2019501
	S_WAITCNT lgkmcnt(0)                                                        ; BF8C007F
	V_MUL_F32_e32 v14, s3, v13                                                  ; 101C1A03
	S_BUFFER_LOAD_DWORD s5, s[20:23], 0                                         ; C2029500
	S_WAITCNT lgkmcnt(0)                                                        ; BF8C007F
	V_MUL_F32_e32 v15, s5, v13                                                  ; 101E1A05
	V_SUB_F32_e32 v16, v15, v14                                                 ; 08201D0F
	V_MAD_F32 v17, v14, -4.000000e+00, v16, 0, 0, 0, 0                          ; D2820011 0441EF0E
	V_MUL_F32_e32 v12, v12, v17                                                 ; 1018230C
	V_MUL_F32_e32 v18, v12, v8                                                  ; 1024110C
	V_MUL_F32_e32 v20, v11, v2                                                  ; 1028050B
	V_MAD_F32 v20, v11, v2, v20, 0, 0, 0, 0                                     ; D2820014 0452050B
	V_SUB_F32_e32 v20, s4, v20                                                  ; 08282804
	V_MUL_F32_e32 v20, v20, v17                                                 ; 10282314
	V_MAD_F32 v18, v20, v9, v18, 0, 0, 0, 0                                     ; D2820012 044A1314
	V_MUL_F32_e32 v5, v5, v6                                                    ; 100A0D05
	V_MUL_F32_e32 v6, v11, v10                                                  ; 100C150B
	V_MAD_F32 v6, v11, v10, v6, 0, 0, 0, 0                                      ; D2820006 041A150B
	V_SUB_F32_e32 v6, s2, v6                                                    ; 080C0C02
	V_MUL_F32_e32 v6, v6, v17                                                   ; 100C2306
	V_MAD_F32 v11, v6, v5, v18, 0, 0, 0, 0                                      ; D282000B 044A0B06
	V_CMP_GE_F32_e64 s[6:7], v11, 0.000000e+00, 0, 0, 0, 0                      ; D00C0006 0201010B
	V_CNDMASK_B32_e64 v11, -nan, 1.401298e-45, s[6:7], 0, 0, 0, 0               ; D200000B 001902C1
	V_CVT_F32_I32_e32 v11, v11                                                  ; 7E160B0B
	V_MUL_F32_e32 v18, v9, v4                                                   ; 10240909
	S_BUFFER_LOAD_DWORD s2, s[20:23], 2                                         ; C2011502
	S_WAITCNT lgkmcnt(0)                                                        ; BF8C007F
	V_MUL_F32_e32 v18, s2, v18                                                  ; 10242402
	V_SUB_F32_e32 v7, v7, v18                                                   ; 080E2507
	V_MAD_F32 v18, v20, v11, v7, 0, 0, 0, 0                                     ; D2820012 041E1714
	V_MUL_F32_e32 v20, v5, v4                                                   ; 10280905
	V_MUL_F32_e32 v20, s2, v20                                                  ; 10282802
	V_SUB_F32_e32 v20, v4, v20                                                  ; 08282904
	V_MAD_F32 v6, v6, v11, v20, 0, 0, 0, 0                                      ; D2820006 04521706
	V_ADD_F32_e64 v21, v6, 0, 0, 0, 0, 1                                        ; D2060015 22010106
	V_RCP_F32_e32 v21, v21                                                      ; 7E2A5515
	V_MUL_F32_e32 v18, v18, v21                                                 ; 10242B12
	V_MUL_F32_e32 v18, s27, v18                                                 ; 1024241B
	V_SUBREV_F32_e32 v18, s26, v18                                              ; 0A24241A
	V_MAD_F32 v18, v18, -5.000000e-01, 5.000000e-01, 0, 0, 0, 0                 ; D2820012 03C1E312
	V_ADD_F32_e64 v23, 0, v18, 0, 1, 0, 0                                       ; D2060817 02022480
	V_MUL_F32_e32 v4, v8, v4                                                    ; 10080908
	V_MUL_F32_e32 v4, s2, v4                                                    ; 10080802
	V_SUB_F32_e32 v4, v19, v4                                                   ; 08080913
	V_MAD_F32 v11, v12, v11, v4, 0, 0, 0, 0                                     ; D282000B 0412170C
	V_MUL_F32_e32 v11, v11, v21                                                 ; 10162B0B
	V_MUL_F32_e32 v11, s29, v11                                                 ; 1016161D
	V_SUBREV_F32_e32 v11, s28, v11                                              ; 0A16161C
	V_MAD_F32 v11, v11, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0                  ; D282000B 03C1E10B
	V_ADD_F32_e64 v22, 0, v11, 0, 1, 0, 0                                       ; D2060816 02021680
	IMAGE_SAMPLE v11, 1, 0, 0, 0, 0, 0, 0, 0, v[22:23], s[12:19], s[8:11]       ; F0800100 00430B16
	S_WAITCNT vmcnt(0)                                                          ; BF8C0770
	V_ADD_F32_e64 v12, v11, 0, 1, 0, 0, 0                                       ; D206010C 0201010B
	V_MUL_F32_e32 v12, s24, v12                                                 ; 10181818
	V_SUBREV_F32_e32 v12, s25, v12                                              ; 0A181819
	V_CMP_EQ_F32_e64 s[6:7], v12, 0.000000e+00, 0, 0, 0, 0                      ; D0040006 0201010C
	V_CNDMASK_B32_e64 v18, 0.000000e+00, 1.401298e-45, s[6:7], 0, 0, 0, 0       ; D2000012 00190280
	V_CVT_F32_I32_e32 v18, v18                                                  ; 7E240B12
	V_SUB_F32_e32 v6, v12, v6                                                   ; 080C0D0C
	V_ADD_F32_e32 v12, v17, v17                                                 ; 06182311
	V_CMP_GE_F32_e64 s[6:7], v6, v12, 0, 0, 0, 0                                ; D00C0006 02021906
	V_CNDMASK_B32_e64 v12, 0, -1, s[6:7], 0, 0, 0, 0                            ; D200000C 00198280
	V_AND_B32_e32 v12, 1065353216, v12                                          ; 361818F2
	V_ADD_F32_e32 v12, v12, v18                                                 ; 0618250C
	V_CMP_LE_F32_e64 s[6:7], v11, 0.000000e+00, 0, 0, 0, 0                      ; D0060006 0201010B
	V_CNDMASK_B32_e64 v11, 0, -1, s[6:7], 0, 0, 0, 0                            ; D200000B 00198280
	V_AND_B32_e32 v11, 1065353216, v11                                          ; 361616F2
	V_CMP_GE_F32_e64 s[6:7], v1, 0.000000e+00, 0, 0, 0, 0                       ; D00C0006 02010101
	V_CNDMASK_B32_e64 v1, 0, -1, s[6:7], 0, 0, 0, 0                             ; D2000001 00198280
	V_AND_B32_e32 v1, 1065353216, v1                                            ; 360202F2
	V_MAD_F32 v11, v11, v1, v12, 0, 0, 0, 0                                     ; D282000B 0432030B
	V_ADD_F32_e64 v11, 0, v11, 0, 1, 0, 0                                       ; D206080B 02021680
	V_SUB_F32_e32 v12, 1.000000e+00, v11                                        ; 081816F2
	V_CMP_GE_F32_e64 s[6:7], v6, 0.000000e+00, 0, 0, 0, 0                       ; D00C0006 02010106
	V_CNDMASK_B32_e64 v6, 0, -1, s[6:7], 0, 0, 0, 0                             ; D2000006 00198280
	V_AND_B32_e32 v6, 1065353216, v6                                            ; 360C0CF2
	V_MUL_F32_e32 v6, v6, v12                                                   ; 100C1906
	S_BUFFER_LOAD_DWORD s2, s[20:23], 44                                        ; C201152C
	S_WAITCNT lgkmcnt(0)                                                        ; BF8C007F
	V_MUL_F32_e32 v12, s2, v3                                                   ; 10180602
	S_BUFFER_LOAD_DWORD s4, s[20:23], 45                                        ; C202152D
	S_WAITCNT lgkmcnt(0)                                                        ; BF8C007F
	V_MAD_F32 v12, v2, s4, v12, 0, 0, 0, 0                                      ; D282000C 04300902
	S_BUFFER_LOAD_DWORD s6, s[20:23], 46                                        ; C203152E
	S_WAITCNT lgkmcnt(0)                                                        ; BF8C007F
	V_MAD_F32 v12, v10, s6, v12, 0, 0, 0, 0                                     ; D282000C 04300D0A
	V_MUL_F32_e32 v18, v12, v3                                                  ; 1024070C
	V_MAD_F32 v18, v12, v3, v18, 0, 0, 0, 0                                     ; D2820012 044A070C
	V_SUB_F32_e32 v18, s2, v18                                                  ; 08242402
	V_MUL_F32_e32 v19, 0.000000e+00, v14                                        ; 10261C80
	V_SUB_F32_e32 v19, v15, v19                                                 ; 0826270F
	V_MAD_F32 v21, v14, -4.000000e+00, v19, 0, 0, 0, 0                          ; D2820015 044DEF0E
	V_MUL_F32_e32 v18, v18, v21                                                 ; 10242B12
	V_MUL_F32_e32 v22, v18, v8                                                  ; 102C1112
	V_MUL_F32_e32 v23, v12, v2                                                  ; 102E050C
	V_MAD_F32 v23, v12, v2, v23, 0, 0, 0, 0                                     ; D2820017 045E050C
	V_SUB_F32_e32 v23, s4, v23                                                  ; 082E2E04
	V_MUL_F32_e32 v23, v23, v21                                                 ; 102E2B17
	V_MAD_F32 v22, v23, v9, v22, 0, 0, 0, 0                                     ; D2820016 045A1317
	V_MUL_F32_e32 v24, v12, v10                                                 ; 1030150C
	V_MAD_F32 v12, v12, v10, v24, 0, 0, 0, 0                                    ; D282000C 0462150C
	V_SUB_F32_e32 v12, s6, v12                                                  ; 08181806
	V_MUL_F32_e32 v12, v12, v21                                                 ; 10182B0C
	V_MAD_F32 v22, v12, v5, v22, 0, 0, 0, 0                                     ; D2820016 045A0B0C
	V_CMP_GE_F32_e64 s[6:7], v22, 0.000000e+00, 0, 0, 0, 0                      ; D00C0006 02010116
	V_CNDMASK_B32_e64 v22, -nan, 1.401298e-45, s[6:7], 0, 0, 0, 0               ; D2000016 001902C1
	V_CVT_F32_I32_e32 v22, v22                                                  ; 7E2C0B16
	V_MAD_F32 v23, v23, v22, v7, 0, 0, 0, 0                                     ; D2820017 041E2D17
	V_MAD_F32 v12, v12, v22, v20, 0, 0, 0, 0                                    ; D282000C 04522D0C
	V_ADD_F32_e64 v24, v12, 0, 0, 0, 0, 1                                       ; D2060018 2201010C
	V_RCP_F32_e32 v24, v24                                                      ; 7E305518
	V_MUL_F32_e32 v23, v23, v24                                                 ; 102E3117
	V_MUL_F32_e32 v23, s27, v23                                                 ; 102E2E1B
	V_SUBREV_F32_e32 v23, s26, v23                                              ; 0A2E2E1A
	V_MAD_F32 v23, v23, -5.000000e-01, 5.000000e-01, 0, 0, 0, 0                 ; D2820017 03C1E317
	V_ADD_F32_e64 v26, 0, v23, 0, 1, 0, 0                                       ; D206081A 02022E80
	V_MAD_F32 v18, v18, v22, v4, 0, 0, 0, 0                                     ; D2820012 04122D12
	V_MUL_F32_e32 v18, v18, v24                                                 ; 10243112
	V_MUL_F32_e32 v18, s29, v18                                                 ; 1024241D
	V_SUBREV_F32_e32 v18, s28, v18                                              ; 0A24241C
	V_MAD_F32 v18, v18, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0                  ; D2820012 03C1E112
	V_ADD_F32_e64 v25, 0, v18, 0, 1, 0, 0                                       ; D2060819 02022480
	IMAGE_SAMPLE v18, 1, 0, 0, 0, 0, 0, 0, 0, v[25:26], s[12:19], s[8:11]       ; F0800100 00431219
	S_WAITCNT vmcnt(0)                                                          ; BF8C0770
	V_ADD_F32_e64 v22, v18, 0, 1, 0, 0, 0                                       ; D2060116 02010112
	V_MUL_F32_e32 v22, s24, v22                                                 ; 102C2C18
	V_SUBREV_F32_e32 v22, s25, v22                                              ; 0A2C2C19
	V_CMP_EQ_F32_e64 s[6:7], v22, 0.000000e+00, 0, 0, 0, 0                      ; D0040006 02010116
	V_CNDMASK_B32_e64 v23, 0.000000e+00, 1.401298e-45, s[6:7], 0, 0, 0, 0       ; D2000017 00190280
	V_CVT_F32_I32_e32 v23, v23                                                  ; 7E2E0B17
	V_SUB_F32_e32 v12, v22, v12                                                 ; 08181916
	V_ADD_F32_e32 v22, v21, v21                                                 ; 062C2B15
	V_CMP_GE_F32_e64 s[6:7], v12, v22, 0, 0, 0, 0                               ; D00C0006 02022D0C
	V_CNDMASK_B32_e64 v22, 0, -1, s[6:7], 0, 0, 0, 0                            ; D2000016 00198280
	V_AND_B32_e32 v22, 1065353216, v22                                          ; 362C2CF2
	V_ADD_F32_e32 v22, v22, v23                                                 ; 062C2F16
	V_CMP_LE_F32_e64 s[6:7], v18, 0.000000e+00, 0, 0, 0, 0                      ; D0060006 02010112
	V_CNDMASK_B32_e64 v18, 0, -1, s[6:7], 0, 0, 0, 0                            ; D2000012 00198280
	V_AND_B32_e32 v18, 1065353216, v18                                          ; 362424F2
	V_MAD_F32 v18, v18, v1, v22, 0, 0, 0, 0                                     ; D2820012 045A0312
	V_ADD_F32_e64 v18, 0, v18, 0, 1, 0, 0                                       ; D2060812 02022480
	V_SUB_F32_e32 v22, 1.000000e+00, v18                                        ; 082C24F2
	V_CMP_GE_F32_e64 s[6:7], v12, 0.000000e+00, 0, 0, 0, 0                      ; D00C0006 0201010C
	V_CNDMASK_B32_e64 v12, 0, -1, s[6:7], 0, 0, 0, 0                            ; D200000C 00198280
	V_AND_B32_e32 v12, 1065353216, v12                                          ; 361818F2
	V_MAD_F32 v6, v12, v22, v6, 0, 0, 0, 0                                      ; D2820006 041A2D0C
	S_BUFFER_LOAD_DWORD s2, s[20:23], 52                                        ; C2011534
	S_WAITCNT lgkmcnt(0)                                                        ; BF8C007F
	V_MUL_F32_e32 v12, s2, v3                                                   ; 10180602
	S_BUFFER_LOAD_DWORD s4, s[20:23], 53                                        ; C2021535
	S_WAITCNT lgkmcnt(0)                                                        ; BF8C007F
	V_MAD_F32 v12, v2, s4, v12, 0, 0, 0, 0                                      ; D282000C 04300902
	S_BUFFER_LOAD_DWORD s6, s[20:23], 54                                        ; C2031536
	S_WAITCNT lgkmcnt(0)                                                        ; BF8C007F
	V_MAD_F32 v12, v10, s6, v12, 0, 0, 0, 0                                     ; D282000C 04300D0A
	V_MUL_F32_e32 v22, v12, v3                                                  ; 102C070C
	V_MAD_F32 v22, v12, v3, v22, 0, 0, 0, 0                                     ; D2820016 045A070C
	V_SUB_F32_e32 v22, s2, v22                                                  ; 082C2C02
	V_MAD_F32 v23, s3, v13, v14, 0, 0, 0, 0                                     ; D2820017 043A1A03
	V_SUB_F32_e32 v15, v15, v23                                                 ; 081E2F0F
	V_MAD_F32 v23, v14, -4.000000e+00, v15, 0, 0, 0, 0                          ; D2820017 043DEF0E
	V_MUL_F32_e32 v22, v22, v23                                                 ; 102C2F16
	V_MUL_F32_e32 v24, v22, v8                                                  ; 10301116
	V_MUL_F32_e32 v25, v12, v2                                                  ; 1032050C
	V_MAD_F32 v25, v12, v2, v25, 0, 0, 0, 0                                     ; D2820019 0466050C
	V_SUB_F32_e32 v25, s4, v25                                                  ; 08323204
	V_MUL_F32_e32 v25, v25, v23                                                 ; 10322F19
	V_MAD_F32 v24, v25, v9, v24, 0, 0, 0, 0                                     ; D2820018 04621319
	V_MUL_F32_e32 v26, v12, v10                                                 ; 1034150C
	V_MAD_F32 v12, v12, v10, v26, 0, 0, 0, 0                                    ; D282000C 046A150C
	V_SUB_F32_e32 v12, s6, v12                                                  ; 08181806
	V_MUL_F32_e32 v12, v12, v23                                                 ; 10182F0C
	V_MAD_F32 v24, v12, v5, v24, 0, 0, 0, 0                                     ; D2820018 04620B0C
	V_CMP_GE_F32_e64 s[2:3], v24, 0.000000e+00, 0, 0, 0, 0                      ; D00C0002 02010118
	V_CNDMASK_B32_e64 v24, -nan, 1.401298e-45, s[2:3], 0, 0, 0, 0               ; D2000018 000902C1
	V_CVT_F32_I32_e32 v24, v24                                                  ; 7E300B18
	V_MAD_F32 v25, v25, v24, v7, 0, 0, 0, 0                                     ; D2820019 041E3119
	V_MAD_F32 v12, v12, v24, v20, 0, 0, 0, 0                                    ; D282000C 0452310C
	V_ADD_F32_e64 v26, v12, 0, 0, 0, 0, 1                                       ; D206001A 2201010C
	V_RCP_F32_e32 v26, v26                                                      ; 7E34551A
	V_MUL_F32_e32 v25, v25, v26                                                 ; 10323519
	V_MUL_F32_e32 v25, s27, v25                                                 ; 1032321B
	V_SUBREV_F32_e32 v25, s26, v25                                              ; 0A32321A
	V_MAD_F32 v25, v25, -5.000000e-01, 5.000000e-01, 0, 0, 0, 0                 ; D2820019 03C1E319
	V_ADD_F32_e64 v28, 0, v25, 0, 1, 0, 0                                       ; D206081C 02023280
	V_MAD_F32 v22, v22, v24, v4, 0, 0, 0, 0                                     ; D2820016 04123116
	V_MUL_F32_e32 v22, v22, v26                                                 ; 102C3516
	V_MUL_F32_e32 v22, s29, v22                                                 ; 102C2C1D
	V_SUBREV_F32_e32 v22, s28, v22                                              ; 0A2C2C1C
	V_MAD_F32 v22, v22, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0                  ; D2820016 03C1E116
	V_ADD_F32_e64 v27, 0, v22, 0, 1, 0, 0                                       ; D206081B 02022C80
	IMAGE_SAMPLE v22, 1, 0, 0, 0, 0, 0, 0, 0, v[27:28], s[12:19], s[8:11]       ; F0800100 0043161B
	S_WAITCNT vmcnt(0)                                                          ; BF8C0770
	V_ADD_F32_e64 v24, v22, 0, 1, 0, 0, 0                                       ; D2060118 02010116
	V_MUL_F32_e32 v24, s24, v24                                                 ; 10303018
	V_SUBREV_F32_e32 v24, s25, v24                                              ; 0A303019
	V_CMP_EQ_F32_e64 s[2:3], v24, 0.000000e+00, 0, 0, 0, 0                      ; D0040002 02010118
	V_CNDMASK_B32_e64 v25, 0.000000e+00, 1.401298e-45, s[2:3], 0, 0, 0, 0       ; D2000019 00090280
	V_CVT_F32_I32_e32 v25, v25                                                  ; 7E320B19
	V_SUB_F32_e32 v12, v24, v12                                                 ; 08181918
	V_ADD_F32_e32 v24, v23, v23                                                 ; 06302F17
	V_CMP_GE_F32_e64 s[2:3], v12, v24, 0, 0, 0, 0                               ; D00C0002 0202310C
	V_CNDMASK_B32_e64 v24, 0, -1, s[2:3], 0, 0, 0, 0                            ; D2000018 00098280
	V_AND_B32_e32 v24, 1065353216, v24                                          ; 363030F2
	V_ADD_F32_e32 v24, v24, v25                                                 ; 06303318
	V_CMP_LE_F32_e64 s[2:3], v22, 0.000000e+00, 0, 0, 0, 0                      ; D0060002 02010116
	V_CNDMASK_B32_e64 v22, 0, -1, s[2:3], 0, 0, 0, 0                            ; D2000016 00098280
	V_AND_B32_e32 v22, 1065353216, v22                                          ; 362C2CF2
	V_MAD_F32 v22, v22, v1, v24, 0, 0, 0, 0                                     ; D2820016 04620316
	V_ADD_F32_e64 v22, 0, v22, 0, 1, 0, 0                                       ; D2060816 02022C80
	V_SUB_F32_e32 v24, 1.000000e+00, v22                                        ; 08302CF2
	V_CMP_GE_F32_e64 s[2:3], v12, 0.000000e+00, 0, 0, 0, 0                      ; D00C0002 0201010C
	V_CNDMASK_B32_e64 v12, 0, -1, s[2:3], 0, 0, 0, 0                            ; D200000C 00098280
	V_AND_B32_e32 v12, 1065353216, v12                                          ; 361818F2
	V_MAD_F32 v6, v12, v24, v6, 0, 0, 0, 0                                      ; D2820006 041A310C
	S_BUFFER_LOAD_DWORD s2, s[20:23], 56                                        ; C2011538
	S_WAITCNT lgkmcnt(0)                                                        ; BF8C007F
	V_MUL_F32_e32 v12, s2, v3                                                   ; 10180602
	S_BUFFER_LOAD_DWORD s3, s[20:23], 57                                        ; C2019539
	S_WAITCNT lgkmcnt(0)                                                        ; BF8C007F
	V_MAD_F32 v12, v2, s3, v12, 0, 0, 0, 0                                      ; D282000C 04300702
	S_BUFFER_LOAD_DWORD s4, s[20:23], 58                                        ; C202153A
	S_WAITCNT lgkmcnt(0)                                                        ; BF8C007F
	V_MAD_F32 v12, v10, s4, v12, 0, 0, 0, 0                                     ; D282000C 0430090A
	V_MUL_F32_e32 v24, v12, v3                                                  ; 1030070C
	V_MAD_F32 v24, v12, v3, v24, 0, 0, 0, 0                                     ; D2820018 0462070C
	V_SUB_F32_e32 v24, s2, v24                                                  ; 08303002
	V_MUL_F32_e32 v25, -3.000000e+00, v14                                       ; 10321CFF C0400000
	V_MAD_F32 v13, s5, v13, v25, 0, 0, 0, 0                                     ; D282000D 04661A05
	V_MAD_F32 v25, v14, -4.000000e+00, v13, 0, 0, 0, 0                          ; D2820019 0435EF0E
	V_MUL_F32_e32 v24, v24, v25                                                 ; 10303318
	V_MUL_F32_e32 v26, v24, v8                                                  ; 10341118
	V_MUL_F32_e32 v27, v12, v2                                                  ; 1036050C
	V_MAD_F32 v27, v12, v2, v27, 0, 0, 0, 0                                     ; D282001B 046E050C
	V_SUB_F32_e32 v27, s3, v27                                                  ; 08363603
	V_MUL_F32_e32 v27, v27, v25                                                 ; 1036331B
	V_MAD_F32 v26, v27, v9, v26, 0, 0, 0, 0                                     ; D282001A 046A131B
	V_MUL_F32_e32 v28, v12, v10                                                 ; 1038150C
	V_MAD_F32 v12, v12, v10, v28, 0, 0, 0, 0                                    ; D282000C 0472150C
	V_SUB_F32_e32 v12, s4, v12                                                  ; 08181804
	V_MUL_F32_e32 v12, v12, v25                                                 ; 1018330C
	V_MAD_F32 v26, v12, v5, v26, 0, 0, 0, 0                                     ; D282001A 046A0B0C
	V_CMP_GE_F32_e64 s[2:3], v26, 0.000000e+00, 0, 0, 0, 0                      ; D00C0002 0201011A
	V_CNDMASK_B32_e64 v26, -nan, 1.401298e-45, s[2:3], 0, 0, 0, 0               ; D200001A 000902C1
	V_CVT_F32_I32_e32 v26, v26                                                  ; 7E340B1A
	V_MAD_F32 v27, v27, v26, v7, 0, 0, 0, 0                                     ; D282001B 041E351B
	V_MAD_F32 v12, v12, v26, v20, 0, 0, 0, 0                                    ; D282000C 0452350C
	V_ADD_F32_e64 v28, v12, 0, 0, 0, 0, 1                                       ; D206001C 2201010C
	V_RCP_F32_e32 v28, v28                                                      ; 7E38551C
	V_MUL_F32_e32 v27, v27, v28                                                 ; 1036391B
	V_MUL_F32_e32 v27, s27, v27                                                 ; 1036361B
	V_SUBREV_F32_e32 v27, s26, v27                                              ; 0A36361A
	V_MAD_F32 v27, v27, -5.000000e-01, 5.000000e-01, 0, 0, 0, 0                 ; D282001B 03C1E31B
	V_ADD_F32_e64 v30, 0, v27, 0, 1, 0, 0                                       ; D206081E 02023680
	V_MAD_F32 v24, v24, v26, v4, 0, 0, 0, 0                                     ; D2820018 04123518
	V_MUL_F32_e32 v24, v24, v28                                                 ; 10303918
	V_MUL_F32_e32 v24, s29, v24                                                 ; 1030301D
	V_SUBREV_F32_e32 v24, s28, v24                                              ; 0A30301C
	V_MAD_F32 v24, v24, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0                  ; D2820018 03C1E118
	V_ADD_F32_e64 v29, 0, v24, 0, 1, 0, 0                                       ; D206081D 02023080
	IMAGE_SAMPLE v24, 1, 0, 0, 0, 0, 0, 0, 0, v[29:30], s[12:19], s[8:11]       ; F0800100 0043181D
	S_WAITCNT vmcnt(0)                                                          ; BF8C0770
	V_ADD_F32_e64 v26, v24, 0, 1, 0, 0, 0                                       ; D206011A 02010118
	V_MUL_F32_e32 v26, s24, v26                                                 ; 10343418
	V_SUBREV_F32_e32 v26, s25, v26                                              ; 0A343419
	V_CMP_EQ_F32_e64 s[2:3], v26, 0.000000e+00, 0, 0, 0, 0                      ; D0040002 0201011A
	V_CNDMASK_B32_e64 v27, 0.000000e+00, 1.401298e-45, s[2:3], 0, 0, 0, 0       ; D200001B 00090280
	V_CVT_F32_I32_e32 v27, v27                                                  ; 7E360B1B
	V_SUB_F32_e32 v12, v26, v12                                                 ; 0818191A
	V_ADD_F32_e32 v26, v25, v25                                                 ; 06343319
	V_CMP_GE_F32_e64 s[2:3], v12, v26, 0, 0, 0, 0                               ; D00C0002 0202350C
	V_CNDMASK_B32_e64 v26, 0, -1, s[2:3], 0, 0, 0, 0                            ; D200001A 00098280
	V_AND_B32_e32 v26, 1065353216, v26                                          ; 363434F2
	V_ADD_F32_e32 v26, v26, v27                                                 ; 0634371A
	V_CMP_LE_F32_e64 s[2:3], v24, 0.000000e+00, 0, 0, 0, 0                      ; D0060002 02010118
	V_CNDMASK_B32_e64 v24, 0, -1, s[2:3], 0, 0, 0, 0                            ; D2000018 00098280
	V_AND_B32_e32 v24, 1065353216, v24                                          ; 363030F2
	V_MAD_F32 v24, v24, v1, v26, 0, 0, 0, 0                                     ; D2820018 046A0318
	V_ADD_F32_e64 v24, 0, v24, 0, 1, 0, 0                                       ; D2060818 02023080
	V_SUB_F32_e32 v26, 1.000000e+00, v24                                        ; 083430F2
	V_CMP_GE_F32_e64 s[2:3], v12, 0.000000e+00, 0, 0, 0, 0                      ; D00C0002 0201010C
	V_CNDMASK_B32_e64 v12, 0, -1, s[2:3], 0, 0, 0, 0                            ; D200000C 00098280
	V_AND_B32_e32 v12, 1065353216, v12                                          ; 361818F2
	V_MAD_F32 v6, v12, v26, v6, 0, 0, 0, 0                                      ; D2820006 041A350C
	S_BUFFER_LOAD_DWORD s2, s[20:23], 32                                        ; C2011520
	S_WAITCNT lgkmcnt(0)                                                        ; BF8C007F
	V_MUL_F32_e32 v12, s2, v3                                                   ; 10180602
	S_BUFFER_LOAD_DWORD s3, s[20:23], 33                                        ; C2019521
	S_WAITCNT lgkmcnt(0)                                                        ; BF8C007F
	V_MAD_F32 v12, v2, s3, v12, 0, 0, 0, 0                                      ; D282000C 04300702
	S_BUFFER_LOAD_DWORD s4, s[20:23], 34                                        ; C2021522
	S_WAITCNT lgkmcnt(0)                                                        ; BF8C007F
	V_MAD_F32 v12, v10, s4, v12, 0, 0, 0, 0                                     ; D282000C 0430090A
	V_MUL_F32_e32 v26, v12, v3                                                  ; 1034070C
	V_MAD_F32 v26, v12, v3, v26, 0, 0, 0, 0                                     ; D282001A 046A070C
	V_SUB_F32_e32 v26, s2, v26                                                  ; 08343402
	V_MUL_F32_e32 v26, v26, v16                                                 ; 1034211A
	V_MUL_F32_e32 v27, v26, v8                                                  ; 1036111A
	V_MUL_F32_e32 v28, v12, v2                                                  ; 1038050C
	V_MAD_F32 v28, v12, v2, v28, 0, 0, 0, 0                                     ; D282001C 0472050C
	V_SUB_F32_e32 v28, s3, v28                                                  ; 08383803
	V_MUL_F32_e32 v28, v28, v16                                                 ; 1038211C
	V_MAD_F32 v27, v28, v9, v27, 0, 0, 0, 0                                     ; D282001B 046E131C
	V_MUL_F32_e32 v29, v12, v10                                                 ; 103A150C
	V_MAD_F32 v12, v12, v10, v29, 0, 0, 0, 0                                    ; D282000C 0476150C
	V_SUB_F32_e32 v12, s4, v12                                                  ; 08181804
	V_MUL_F32_e32 v12, v12, v16                                                 ; 1018210C
	V_MAD_F32 v27, v12, v5, v27, 0, 0, 0, 0                                     ; D282001B 046E0B0C
	V_CMP_GE_F32_e64 s[2:3], v27, 0.000000e+00, 0, 0, 0, 0                      ; D00C0002 0201011B
	V_CNDMASK_B32_e64 v27, -nan, 1.401298e-45, s[2:3], 0, 0, 0, 0               ; D200001B 000902C1
	V_CVT_F32_I32_e32 v27, v27                                                  ; 7E360B1B
	V_MAD_F32 v28, v28, v27, v7, 0, 0, 0, 0                                     ; D282001C 041E371C
	V_MAD_F32 v12, v12, v27, v20, 0, 0, 0, 0                                    ; D282000C 0452370C
	V_ADD_F32_e64 v29, v12, 0, 0, 0, 0, 1                                       ; D206001D 2201010C
	V_RCP_F32_e32 v29, v29                                                      ; 7E3A551D
	V_MUL_F32_e32 v28, v28, v29                                                 ; 10383B1C
	V_MUL_F32_e32 v28, s27, v28                                                 ; 1038381B
	V_SUBREV_F32_e32 v28, s26, v28                                              ; 0A38381A
	V_MAD_F32 v28, v28, -5.000000e-01, 5.000000e-01, 0, 0, 0, 0                 ; D282001C 03C1E31C
	V_ADD_F32_e64 v31, 0, v28, 0, 1, 0, 0                                       ; D206081F 02023880
	V_MAD_F32 v26, v26, v27, v4, 0, 0, 0, 0                                     ; D282001A 0412371A
	V_MUL_F32_e32 v26, v26, v29                                                 ; 10343B1A
	V_MUL_F32_e32 v26, s29, v26                                                 ; 1034341D
	V_SUBREV_F32_e32 v26, s28, v26                                              ; 0A34341C
	V_MAD_F32 v26, v26, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0                  ; D282001A 03C1E11A
	V_ADD_F32_e64 v30, 0, v26, 0, 1, 0, 0                                       ; D206081E 02023480
	IMAGE_SAMPLE v26, 1, 0, 0, 0, 0, 0, 0, 0, v[30:31], s[12:19], s[8:11]       ; F0800100 00431A1E
	S_WAITCNT vmcnt(0)                                                          ; BF8C0770
	V_ADD_F32_e64 v27, v26, 0, 1, 0, 0, 0                                       ; D206011B 0201011A
	V_MUL_F32_e32 v27, s24, v27                                                 ; 10363618
	V_SUBREV_F32_e32 v27, s25, v27                                              ; 0A363619
	V_CMP_EQ_F32_e64 s[2:3], v27, 0.000000e+00, 0, 0, 0, 0                      ; D0040002 0201011B
	V_CNDMASK_B32_e64 v28, 0.000000e+00, 1.401298e-45, s[2:3], 0, 0, 0, 0       ; D200001C 00090280
	V_CVT_F32_I32_e32 v28, v28                                                  ; 7E380B1C
	V_SUB_F32_e32 v12, v27, v12                                                 ; 0818191B
	V_ADD_F32_e32 v16, v16, v16                                                 ; 06202110
	V_CMP_GE_F32_e64 s[2:3], v12, v16, 0, 0, 0, 0                               ; D00C0002 0202210C
	V_CNDMASK_B32_e64 v16, 0, -1, s[2:3], 0, 0, 0, 0                            ; D2000010 00098280
	V_AND_B32_e32 v16, 1065353216, v16                                          ; 362020F2
	V_ADD_F32_e32 v16, v16, v28                                                 ; 06203910
	V_CMP_LE_F32_e64 s[2:3], v26, 0.000000e+00, 0, 0, 0, 0                      ; D0060002 0201011A
	V_CNDMASK_B32_e64 v26, 0, -1, s[2:3], 0, 0, 0, 0                            ; D200001A 00098280
	V_AND_B32_e32 v26, 1065353216, v26                                          ; 363434F2
	V_MAD_F32 v16, v26, v1, v16, 0, 0, 0, 0                                     ; D2820010 0442031A
	V_ADD_F32_e64 v16, 0, v16, 0, 1, 0, 0                                       ; D2060810 02022080
	V_SUB_F32_e32 v26, 1.000000e+00, v16                                        ; 083420F2
	V_CMP_GE_F32_e64 s[2:3], v12, 0.000000e+00, 0, 0, 0, 0                      ; D00C0002 0201010C
	V_CNDMASK_B32_e64 v12, 0, -1, s[2:3], 0, 0, 0, 0                            ; D200000C 00098280
	V_AND_B32_e32 v12, 1065353216, v12                                          ; 361818F2
	V_MUL_F32_e32 v12, v12, v26                                                 ; 1018350C
	S_BUFFER_LOAD_DWORD s2, s[20:23], 28                                        ; C201151C
	S_WAITCNT lgkmcnt(0)                                                        ; BF8C007F
	V_MUL_F32_e32 v26, s2, v3                                                   ; 10340602
	S_BUFFER_LOAD_DWORD s3, s[20:23], 29                                        ; C201951D
	S_WAITCNT lgkmcnt(0)                                                        ; BF8C007F
	V_MAD_F32 v26, v2, s3, v26, 0, 0, 0, 0                                      ; D282001A 04680702
	S_BUFFER_LOAD_DWORD s4, s[20:23], 30                                        ; C202151E
	S_WAITCNT lgkmcnt(0)                                                        ; BF8C007F
	V_MAD_F32 v26, v10, s4, v26, 0, 0, 0, 0                                     ; D282001A 0468090A
	V_MUL_F32_e32 v27, v26, v3                                                  ; 1036071A
	V_MAD_F32 v27, v26, v3, v27, 0, 0, 0, 0                                     ; D282001B 046E071A
	V_SUB_F32_e32 v27, s2, v27                                                  ; 08363602
	V_MUL_F32_e32 v27, v27, v19                                                 ; 1036271B
	V_MUL_F32_e32 v28, v27, v8                                                  ; 1038111B
	V_MUL_F32_e32 v29, v26, v2                                                  ; 103A051A
	V_MAD_F32 v29, v26, v2, v29, 0, 0, 0, 0                                     ; D282001D 0476051A
	V_SUB_F32_e32 v29, s3, v29                                                  ; 083A3A03
	V_MUL_F32_e32 v29, v29, v19                                                 ; 103A271D
	V_MAD_F32 v28, v29, v9, v28, 0, 0, 0, 0                                     ; D282001C 0472131D
	V_MUL_F32_e32 v30, v26, v10                                                 ; 103C151A
	V_MAD_F32 v26, v26, v10, v30, 0, 0, 0, 0                                    ; D282001A 047A151A
	V_SUB_F32_e32 v26, s4, v26                                                  ; 08343404
	V_MUL_F32_e32 v26, v26, v19                                                 ; 1034271A
	V_MAD_F32 v28, v26, v5, v28, 0, 0, 0, 0                                     ; D282001C 04720B1A
	V_CMP_GE_F32_e64 s[2:3], v28, 0.000000e+00, 0, 0, 0, 0                      ; D00C0002 0201011C
	V_CNDMASK_B32_e64 v28, -nan, 1.401298e-45, s[2:3], 0, 0, 0, 0               ; D200001C 000902C1
	V_CVT_F32_I32_e32 v28, v28                                                  ; 7E380B1C
	V_MAD_F32 v29, v29, v28, v7, 0, 0, 0, 0                                     ; D282001D 041E391D
	V_MAD_F32 v26, v26, v28, v20, 0, 0, 0, 0                                    ; D282001A 0452391A
	V_ADD_F32_e64 v30, v26, 0, 0, 0, 0, 1                                       ; D206001E 2201011A
	V_RCP_F32_e32 v30, v30                                                      ; 7E3C551E
	V_MUL_F32_e32 v29, v29, v30                                                 ; 103A3D1D
	V_MUL_F32_e32 v29, s27, v29                                                 ; 103A3A1B
	V_SUBREV_F32_e32 v29, s26, v29                                              ; 0A3A3A1A
	V_MAD_F32 v29, v29, -5.000000e-01, 5.000000e-01, 0, 0, 0, 0                 ; D282001D 03C1E31D
	V_ADD_F32_e64 v32, 0, v29, 0, 1, 0, 0                                       ; D2060820 02023A80
	V_MAD_F32 v27, v27, v28, v4, 0, 0, 0, 0                                     ; D282001B 0412391B
	V_MUL_F32_e32 v27, v27, v30                                                 ; 10363D1B
	V_MUL_F32_e32 v27, s29, v27                                                 ; 1036361D
	V_SUBREV_F32_e32 v27, s28, v27                                              ; 0A36361C
	V_MAD_F32 v27, v27, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0                  ; D282001B 03C1E11B
	V_ADD_F32_e64 v31, 0, v27, 0, 1, 0, 0                                       ; D206081F 02023680
	IMAGE_SAMPLE v27, 1, 0, 0, 0, 0, 0, 0, 0, v[31:32], s[12:19], s[8:11]       ; F0800100 00431B1F
	S_WAITCNT vmcnt(0)                                                          ; BF8C0770
	V_ADD_F32_e64 v28, v27, 0, 1, 0, 0, 0                                       ; D206011C 0201011B
	V_MUL_F32_e32 v28, s24, v28                                                 ; 10383818
	V_SUBREV_F32_e32 v28, s25, v28                                              ; 0A383819
	V_CMP_EQ_F32_e64 s[2:3], v28, 0.000000e+00, 0, 0, 0, 0                      ; D0040002 0201011C
	V_CNDMASK_B32_e64 v29, 0.000000e+00, 1.401298e-45, s[2:3], 0, 0, 0, 0       ; D200001D 00090280
	V_CVT_F32_I32_e32 v29, v29                                                  ; 7E3A0B1D
	V_SUB_F32_e32 v26, v28, v26                                                 ; 0834351C
	V_ADD_F32_e32 v19, v19, v19                                                 ; 06262713
	V_CMP_GE_F32_e64 s[2:3], v26, v19, 0, 0, 0, 0                               ; D00C0002 0202271A
	V_CNDMASK_B32_e64 v19, 0, -1, s[2:3], 0, 0, 0, 0                            ; D2000013 00098280
	V_AND_B32_e32 v19, 1065353216, v19                                          ; 362626F2
	V_ADD_F32_e32 v19, v19, v29                                                 ; 06263B13
	V_CMP_LE_F32_e64 s[2:3], v27, 0.000000e+00, 0, 0, 0, 0                      ; D0060002 0201011B
	V_CNDMASK_B32_e64 v27, 0, -1, s[2:3], 0, 0, 0, 0                            ; D200001B 00098280
	V_AND_B32_e32 v27, 1065353216, v27                                          ; 363636F2
	V_MAD_F32 v19, v27, v1, v19, 0, 0, 0, 0                                     ; D2820013 044E031B
	V_ADD_F32_e64 v19, 0, v19, 0, 1, 0, 0                                       ; D2060813 02022680
	V_SUB_F32_e32 v27, 1.000000e+00, v19                                        ; 083626F2
	V_CMP_GE_F32_e64 s[2:3], v26, 0.000000e+00, 0, 0, 0, 0                      ; D00C0002 0201011A
	V_CNDMASK_B32_e64 v26, 0, -1, s[2:3], 0, 0, 0, 0                            ; D200001A 00098280
	V_AND_B32_e32 v26, 1065353216, v26                                          ; 363434F2
	V_MAD_F32 v12, v26, v27, v12, 0, 0, 0, 0                                    ; D282000C 0432371A
	S_BUFFER_LOAD_DWORD s2, s[20:23], 36                                        ; C2011524
	S_WAITCNT lgkmcnt(0)                                                        ; BF8C007F
	V_MUL_F32_e32 v26, s2, v3                                                   ; 10340602
	S_BUFFER_LOAD_DWORD s3, s[20:23], 37                                        ; C2019525
	S_WAITCNT lgkmcnt(0)                                                        ; BF8C007F
	V_MAD_F32 v26, v2, s3, v26, 0, 0, 0, 0                                      ; D282001A 04680702
	S_BUFFER_LOAD_DWORD s4, s[20:23], 38                                        ; C2021526
	S_WAITCNT lgkmcnt(0)                                                        ; BF8C007F
	V_MAD_F32 v26, v10, s4, v26, 0, 0, 0, 0                                     ; D282001A 0468090A
	V_MUL_F32_e32 v27, v26, v3                                                  ; 1036071A
	V_MAD_F32 v27, v26, v3, v27, 0, 0, 0, 0                                     ; D282001B 046E071A
	V_SUB_F32_e32 v27, s2, v27                                                  ; 08363602
	V_MUL_F32_e32 v27, v27, v15                                                 ; 10361F1B
	V_MUL_F32_e32 v28, v27, v8                                                  ; 1038111B
	V_MUL_F32_e32 v29, v26, v2                                                  ; 103A051A
	V_MAD_F32 v29, v26, v2, v29, 0, 0, 0, 0                                     ; D282001D 0476051A
	V_SUB_F32_e32 v29, s3, v29                                                  ; 083A3A03
	V_MUL_F32_e32 v29, v29, v15                                                 ; 103A1F1D
	V_MAD_F32 v28, v29, v9, v28, 0, 0, 0, 0                                     ; D282001C 0472131D
	V_MUL_F32_e32 v30, v26, v10                                                 ; 103C151A
	V_MAD_F32 v26, v26, v10, v30, 0, 0, 0, 0                                    ; D282001A 047A151A
	V_SUB_F32_e32 v26, s4, v26                                                  ; 08343404
	V_MUL_F32_e32 v26, v26, v15                                                 ; 10341F1A
	V_MAD_F32 v28, v26, v5, v28, 0, 0, 0, 0                                     ; D282001C 04720B1A
	V_CMP_GE_F32_e64 s[2:3], v28, 0.000000e+00, 0, 0, 0, 0                      ; D00C0002 0201011C
	V_CNDMASK_B32_e64 v28, -nan, 1.401298e-45, s[2:3], 0, 0, 0, 0               ; D200001C 000902C1
	V_CVT_F32_I32_e32 v28, v28                                                  ; 7E380B1C
	V_MAD_F32 v29, v29, v28, v7, 0, 0, 0, 0                                     ; D282001D 041E391D
	V_MAD_F32 v26, v26, v28, v20, 0, 0, 0, 0                                    ; D282001A 0452391A
	V_ADD_F32_e64 v30, v26, 0, 0, 0, 0, 1                                       ; D206001E 2201011A
	V_RCP_F32_e32 v30, v30                                                      ; 7E3C551E
	V_MUL_F32_e32 v29, v29, v30                                                 ; 103A3D1D
	V_MUL_F32_e32 v29, s27, v29                                                 ; 103A3A1B
	V_SUBREV_F32_e32 v29, s26, v29                                              ; 0A3A3A1A
	V_MAD_F32 v29, v29, -5.000000e-01, 5.000000e-01, 0, 0, 0, 0                 ; D282001D 03C1E31D
	V_ADD_F32_e64 v32, 0, v29, 0, 1, 0, 0                                       ; D2060820 02023A80
	V_MAD_F32 v27, v27, v28, v4, 0, 0, 0, 0                                     ; D282001B 0412391B
	V_MUL_F32_e32 v27, v27, v30                                                 ; 10363D1B
	V_MUL_F32_e32 v27, s29, v27                                                 ; 1036361D
	V_SUBREV_F32_e32 v27, s28, v27                                              ; 0A36361C
	V_MAD_F32 v27, v27, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0                  ; D282001B 03C1E11B
	V_ADD_F32_e64 v31, 0, v27, 0, 1, 0, 0                                       ; D206081F 02023680
	IMAGE_SAMPLE v27, 1, 0, 0, 0, 0, 0, 0, 0, v[31:32], s[12:19], s[8:11]       ; F0800100 00431B1F
	S_WAITCNT vmcnt(0)                                                          ; BF8C0770
	V_ADD_F32_e64 v28, v27, 0, 1, 0, 0, 0                                       ; D206011C 0201011B
	V_MUL_F32_e32 v28, s24, v28                                                 ; 10383818
	V_SUBREV_F32_e32 v28, s25, v28                                              ; 0A383819
	V_CMP_EQ_F32_e64 s[2:3], v28, 0.000000e+00, 0, 0, 0, 0                      ; D0040002 0201011C
	V_CNDMASK_B32_e64 v29, 0.000000e+00, 1.401298e-45, s[2:3], 0, 0, 0, 0       ; D200001D 00090280
	V_CVT_F32_I32_e32 v29, v29                                                  ; 7E3A0B1D
	V_SUB_F32_e32 v26, v28, v26                                                 ; 0834351C
	V_ADD_F32_e32 v15, v15, v15                                                 ; 061E1F0F
	V_CMP_GE_F32_e64 s[2:3], v26, v15, 0, 0, 0, 0                               ; D00C0002 02021F1A
	V_CNDMASK_B32_e64 v15, 0, -1, s[2:3], 0, 0, 0, 0                            ; D200000F 00098280
	V_AND_B32_e32 v15, 1065353216, v15                                          ; 361E1EF2
	V_ADD_F32_e32 v15, v15, v29                                                 ; 061E3B0F
	V_CMP_LE_F32_e64 s[2:3], v27, 0.000000e+00, 0, 0, 0, 0                      ; D0060002 0201011B
	V_CNDMASK_B32_e64 v27, 0, -1, s[2:3], 0, 0, 0, 0                            ; D200001B 00098280
	V_AND_B32_e32 v27, 1065353216, v27                                          ; 363636F2
	V_MAD_F32 v15, v27, v1, v15, 0, 0, 0, 0                                     ; D282000F 043E031B
	V_ADD_F32_e64 v15, 0, v15, 0, 1, 0, 0                                       ; D206080F 02021E80
	V_SUB_F32_e32 v27, 1.000000e+00, v15                                        ; 08361EF2
	V_CMP_GE_F32_e64 s[2:3], v26, 0.000000e+00, 0, 0, 0, 0                      ; D00C0002 0201011A
	V_CNDMASK_B32_e64 v26, 0, -1, s[2:3], 0, 0, 0, 0                            ; D200001A 00098280
	V_AND_B32_e32 v26, 1065353216, v26                                          ; 363434F2
	V_MAD_F32 v12, v26, v27, v12, 0, 0, 0, 0                                    ; D282000C 0432371A
	S_BUFFER_LOAD_DWORD s2, s[20:23], 40                                        ; C2011528
	S_WAITCNT lgkmcnt(0)                                                        ; BF8C007F
	V_MUL_F32_e32 v26, s2, v3                                                   ; 10340602
	S_BUFFER_LOAD_DWORD s3, s[20:23], 41                                        ; C2019529
	S_WAITCNT lgkmcnt(0)                                                        ; BF8C007F
	V_MAD_F32 v26, v2, s3, v26, 0, 0, 0, 0                                      ; D282001A 04680702
	S_BUFFER_LOAD_DWORD s4, s[20:23], 42                                        ; C202152A
	S_WAITCNT lgkmcnt(0)                                                        ; BF8C007F
	V_MAD_F32 v26, v10, s4, v26, 0, 0, 0, 0                                     ; D282001A 0468090A
	V_MUL_F32_e32 v27, v26, v3                                                  ; 1036071A
	V_MAD_F32 v27, v26, v3, v27, 0, 0, 0, 0                                     ; D282001B 046E071A
	V_SUB_F32_e32 v27, s2, v27                                                  ; 08363602
	V_MUL_F32_e32 v27, v27, v13                                                 ; 10361B1B
	V_MUL_F32_e32 v28, v27, v8                                                  ; 1038111B
	V_MUL_F32_e32 v29, v26, v2                                                  ; 103A051A
	V_MAD_F32 v29, v26, v2, v29, 0, 0, 0, 0                                     ; D282001D 0476051A
	V_SUB_F32_e32 v29, s3, v29                                                  ; 083A3A03
	V_MUL_F32_e32 v29, v29, v13                                                 ; 103A1B1D
	V_MAD_F32 v28, v29, v9, v28, 0, 0, 0, 0                                     ; D282001C 0472131D
	V_MUL_F32_e32 v30, v26, v10                                                 ; 103C151A
	V_MAD_F32 v26, v26, v10, v30, 0, 0, 0, 0                                    ; D282001A 047A151A
	V_SUB_F32_e32 v26, s4, v26                                                  ; 08343404
	V_MUL_F32_e32 v26, v26, v13                                                 ; 10341B1A
	V_MAD_F32 v28, v26, v5, v28, 0, 0, 0, 0                                     ; D282001C 04720B1A
	V_CMP_GE_F32_e64 s[2:3], v28, 0.000000e+00, 0, 0, 0, 0                      ; D00C0002 0201011C
	V_CNDMASK_B32_e64 v28, -nan, 1.401298e-45, s[2:3], 0, 0, 0, 0               ; D200001C 000902C1
	V_CVT_F32_I32_e32 v28, v28                                                  ; 7E380B1C
	V_MAD_F32 v29, v29, v28, v7, 0, 0, 0, 0                                     ; D282001D 041E391D
	V_MAD_F32 v26, v26, v28, v20, 0, 0, 0, 0                                    ; D282001A 0452391A
	V_ADD_F32_e64 v30, v26, 0, 0, 0, 0, 1                                       ; D206001E 2201011A
	V_RCP_F32_e32 v30, v30                                                      ; 7E3C551E
	V_MUL_F32_e32 v29, v29, v30                                                 ; 103A3D1D
	V_MUL_F32_e32 v29, s27, v29                                                 ; 103A3A1B
	V_SUBREV_F32_e32 v29, s26, v29                                              ; 0A3A3A1A
	V_MAD_F32 v29, v29, -5.000000e-01, 5.000000e-01, 0, 0, 0, 0                 ; D282001D 03C1E31D
	V_ADD_F32_e64 v32, 0, v29, 0, 1, 0, 0                                       ; D2060820 02023A80
	V_MAD_F32 v27, v27, v28, v4, 0, 0, 0, 0                                     ; D282001B 0412391B
	V_MUL_F32_e32 v27, v27, v30                                                 ; 10363D1B
	V_MUL_F32_e32 v27, s29, v27                                                 ; 1036361D
	V_SUBREV_F32_e32 v27, s28, v27                                              ; 0A36361C
	V_MAD_F32 v27, v27, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0                  ; D282001B 03C1E11B
	V_ADD_F32_e64 v31, 0, v27, 0, 1, 0, 0                                       ; D206081F 02023680
	IMAGE_SAMPLE v27, 1, 0, 0, 0, 0, 0, 0, 0, v[31:32], s[12:19], s[8:11]       ; F0800100 00431B1F
	S_WAITCNT vmcnt(0)                                                          ; BF8C0770
	V_ADD_F32_e64 v28, v27, 0, 1, 0, 0, 0                                       ; D206011C 0201011B
	V_MUL_F32_e32 v28, s24, v28                                                 ; 10383818
	V_SUBREV_F32_e32 v28, s25, v28                                              ; 0A383819
	V_CMP_EQ_F32_e64 s[2:3], v28, 0.000000e+00, 0, 0, 0, 0                      ; D0040002 0201011C
	V_CNDMASK_B32_e64 v29, 0.000000e+00, 1.401298e-45, s[2:3], 0, 0, 0, 0       ; D200001D 00090280
	V_CVT_F32_I32_e32 v29, v29                                                  ; 7E3A0B1D
	V_SUB_F32_e32 v26, v28, v26                                                 ; 0834351C
	V_ADD_F32_e32 v13, v13, v13                                                 ; 061A1B0D
	V_CMP_GE_F32_e64 s[2:3], v26, v13, 0, 0, 0, 0                               ; D00C0002 02021B1A
	V_CNDMASK_B32_e64 v13, 0, -1, s[2:3], 0, 0, 0, 0                            ; D200000D 00098280
	V_AND_B32_e32 v13, 1065353216, v13                                          ; 361A1AF2
	V_ADD_F32_e32 v13, v13, v29                                                 ; 061A3B0D
	V_CMP_LE_F32_e64 s[2:3], v27, 0.000000e+00, 0, 0, 0, 0                      ; D0060002 0201011B
	V_CNDMASK_B32_e64 v27, 0, -1, s[2:3], 0, 0, 0, 0                            ; D200001B 00098280
	V_AND_B32_e32 v27, 1065353216, v27                                          ; 363636F2
	V_MAD_F32 v13, v27, v1, v13, 0, 0, 0, 0                                     ; D282000D 0436031B
	V_ADD_F32_e64 v13, 0, v13, 0, 1, 0, 0                                       ; D206080D 02021A80
	V_SUB_F32_e32 v27, 1.000000e+00, v13                                        ; 08361AF2
	V_CMP_GE_F32_e64 s[2:3], v26, 0.000000e+00, 0, 0, 0, 0                      ; D00C0002 0201011A
	V_CNDMASK_B32_e64 v26, 0, -1, s[2:3], 0, 0, 0, 0                            ; D200001A 00098280
	V_AND_B32_e32 v26, 1065353216, v26                                          ; 363434F2
	V_MAD_F32 v12, v26, v27, v12, 0, 0, 0, 0                                    ; D282000C 0432371A
	V_ADD_F32_e32 v6, v12, v6                                                   ; 060C0D0C
	S_BUFFER_LOAD_DWORD s2, s[20:23], 64                                        ; C2011540
	S_WAITCNT lgkmcnt(0)                                                        ; BF8C007F
	V_MUL_F32_e32 v12, s2, v3                                                   ; 10180602
	S_BUFFER_LOAD_DWORD s3, s[20:23], 65                                        ; C2019541
	S_WAITCNT lgkmcnt(0)                                                        ; BF8C007F
	V_MAD_F32 v12, v2, s3, v12, 0, 0, 0, 0                                      ; D282000C 04300702
	S_BUFFER_LOAD_DWORD s4, s[20:23], 66                                        ; C2021542
	S_WAITCNT lgkmcnt(0)                                                        ; BF8C007F
	V_MAD_F32 v12, v10, s4, v12, 0, 0, 0, 0                                     ; D282000C 0430090A
	V_MUL_F32_e32 v26, v12, v3                                                  ; 1034070C
	V_MAD_F32 v26, v12, v3, v26, 0, 0, 0, 0                                     ; D282001A 046A070C
	V_SUB_F32_e32 v26, s2, v26                                                  ; 08343402
	V_MAD_F32 v17, v14, -4.000000e+00, v17, 0, 0, 0, 0                          ; D2820011 0445EF0E
	V_MUL_F32_e32 v26, v26, v17                                                 ; 1034231A
	V_MUL_F32_e32 v27, v26, v8                                                  ; 1036111A
	V_MUL_F32_e32 v28, v12, v2                                                  ; 1038050C
	V_MAD_F32 v28, v12, v2, v28, 0, 0, 0, 0                                     ; D282001C 0472050C
	V_SUB_F32_e32 v28, s3, v28                                                  ; 08383803
	V_MUL_F32_e32 v28, v28, v17                                                 ; 1038231C
	V_MAD_F32 v27, v28, v9, v27, 0, 0, 0, 0                                     ; D282001B 046E131C
	V_MUL_F32_e32 v29, v12, v10                                                 ; 103A150C
	V_MAD_F32 v12, v12, v10, v29, 0, 0, 0, 0                                    ; D282000C 0476150C
	V_SUB_F32_e32 v12, s4, v12                                                  ; 08181804
	V_MUL_F32_e32 v12, v12, v17                                                 ; 1018230C
	V_MAD_F32 v27, v12, v5, v27, 0, 0, 0, 0                                     ; D282001B 046E0B0C
	V_CMP_GE_F32_e64 s[2:3], v27, 0.000000e+00, 0, 0, 0, 0                      ; D00C0002 0201011B
	V_CNDMASK_B32_e64 v27, -nan, 1.401298e-45, s[2:3], 0, 0, 0, 0               ; D200001B 000902C1
	V_CVT_F32_I32_e32 v27, v27                                                  ; 7E360B1B
	V_MAD_F32 v28, v28, v27, v7, 0, 0, 0, 0                                     ; D282001C 041E371C
	V_MAD_F32 v12, v12, v27, v20, 0, 0, 0, 0                                    ; D282000C 0452370C
	V_ADD_F32_e64 v29, v12, 0, 0, 0, 0, 1                                       ; D206001D 2201010C
	V_RCP_F32_e32 v29, v29                                                      ; 7E3A551D
	V_MUL_F32_e32 v28, v28, v29                                                 ; 10383B1C
	V_MUL_F32_e32 v28, s27, v28                                                 ; 1038381B
	V_SUBREV_F32_e32 v28, s26, v28                                              ; 0A38381A
	V_MAD_F32 v28, v28, -5.000000e-01, 5.000000e-01, 0, 0, 0, 0                 ; D282001C 03C1E31C
	V_ADD_F32_e64 v31, 0, v28, 0, 1, 0, 0                                       ; D206081F 02023880
	V_MAD_F32 v26, v26, v27, v4, 0, 0, 0, 0                                     ; D282001A 0412371A
	V_MUL_F32_e32 v26, v26, v29                                                 ; 10343B1A
	V_MUL_F32_e32 v26, s29, v26                                                 ; 1034341D
	V_SUBREV_F32_e32 v26, s28, v26                                              ; 0A34341C
	V_MAD_F32 v26, v26, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0                  ; D282001A 03C1E11A
	V_ADD_F32_e64 v30, 0, v26, 0, 1, 0, 0                                       ; D206081E 02023480
	IMAGE_SAMPLE v26, 1, 0, 0, 0, 0, 0, 0, 0, v[30:31], s[12:19], s[8:11]       ; F0800100 00431A1E
	S_WAITCNT vmcnt(0)                                                          ; BF8C0770
	V_ADD_F32_e64 v27, v26, 0, 1, 0, 0, 0                                       ; D206011B 0201011A
	V_MUL_F32_e32 v27, s24, v27                                                 ; 10363618
	V_SUBREV_F32_e32 v27, s25, v27                                              ; 0A363619
	V_CMP_EQ_F32_e64 s[2:3], v27, 0.000000e+00, 0, 0, 0, 0                      ; D0040002 0201011B
	V_CNDMASK_B32_e64 v28, 0.000000e+00, 1.401298e-45, s[2:3], 0, 0, 0, 0       ; D200001C 00090280
	V_CVT_F32_I32_e32 v28, v28                                                  ; 7E380B1C
	V_SUB_F32_e32 v12, v27, v12                                                 ; 0818191B
	V_ADD_F32_e32 v27, v17, v17                                                 ; 06362311
	V_CMP_GE_F32_e64 s[2:3], v12, v27, 0, 0, 0, 0                               ; D00C0002 0202370C
	V_CNDMASK_B32_e64 v27, 0, -1, s[2:3], 0, 0, 0, 0                            ; D200001B 00098280
	V_AND_B32_e32 v27, 1065353216, v27                                          ; 363636F2
	V_ADD_F32_e32 v27, v27, v28                                                 ; 0636391B
	V_CMP_LE_F32_e64 s[2:3], v26, 0.000000e+00, 0, 0, 0, 0                      ; D0060002 0201011A
	V_CNDMASK_B32_e64 v26, 0, -1, s[2:3], 0, 0, 0, 0                            ; D200001A 00098280
	V_AND_B32_e32 v26, 1065353216, v26                                          ; 363434F2
	V_MAD_F32 v26, v26, v1, v27, 0, 0, 0, 0                                     ; D282001A 046E031A
	V_ADD_F32_e64 v26, 0, v26, 0, 1, 0, 0                                       ; D206081A 02023480
	V_SUB_F32_e32 v27, 1.000000e+00, v26                                        ; 083634F2
	V_CMP_GE_F32_e64 s[2:3], v12, 0.000000e+00, 0, 0, 0, 0                      ; D00C0002 0201010C
	V_CNDMASK_B32_e64 v12, 0, -1, s[2:3], 0, 0, 0, 0                            ; D200000C 00098280
	V_AND_B32_e32 v12, 1065353216, v12                                          ; 361818F2
	V_MUL_F32_e32 v12, v12, v27                                                 ; 1018370C
	S_BUFFER_LOAD_DWORD s2, s[20:23], 60                                        ; C201153C
	S_WAITCNT lgkmcnt(0)                                                        ; BF8C007F
	V_MUL_F32_e32 v27, s2, v3                                                   ; 10360602
	S_BUFFER_LOAD_DWORD s3, s[20:23], 61                                        ; C201953D
	S_WAITCNT lgkmcnt(0)                                                        ; BF8C007F
	V_MAD_F32 v27, v2, s3, v27, 0, 0, 0, 0                                      ; D282001B 046C0702
	S_BUFFER_LOAD_DWORD s4, s[20:23], 62                                        ; C202153E
	S_WAITCNT lgkmcnt(0)                                                        ; BF8C007F
	V_MAD_F32 v27, v10, s4, v27, 0, 0, 0, 0                                     ; D282001B 046C090A
	V_MUL_F32_e32 v28, v27, v3                                                  ; 1038071B
	V_MAD_F32 v28, v27, v3, v28, 0, 0, 0, 0                                     ; D282001C 0472071B
	V_SUB_F32_e32 v28, s2, v28                                                  ; 08383802
	V_MAD_F32 v21, v14, -4.000000e+00, v21, 0, 0, 0, 0                          ; D2820015 0455EF0E
	V_MUL_F32_e32 v28, v28, v21                                                 ; 10382B1C
	V_MUL_F32_e32 v29, v28, v8                                                  ; 103A111C
	V_MUL_F32_e32 v30, v27, v2                                                  ; 103C051B
	V_MAD_F32 v30, v27, v2, v30, 0, 0, 0, 0                                     ; D282001E 047A051B
	V_SUB_F32_e32 v30, s3, v30                                                  ; 083C3C03
	V_MUL_F32_e32 v30, v30, v21                                                 ; 103C2B1E
	V_MAD_F32 v29, v30, v9, v29, 0, 0, 0, 0                                     ; D282001D 0476131E
	V_MUL_F32_e32 v31, v27, v10                                                 ; 103E151B
	V_MAD_F32 v27, v27, v10, v31, 0, 0, 0, 0                                    ; D282001B 047E151B
	V_SUB_F32_e32 v27, s4, v27                                                  ; 08363604
	V_MUL_F32_e32 v27, v27, v21                                                 ; 10362B1B
	V_MAD_F32 v29, v27, v5, v29, 0, 0, 0, 0                                     ; D282001D 04760B1B
	V_CMP_GE_F32_e64 s[2:3], v29, 0.000000e+00, 0, 0, 0, 0                      ; D00C0002 0201011D
	V_CNDMASK_B32_e64 v29, -nan, 1.401298e-45, s[2:3], 0, 0, 0, 0               ; D200001D 000902C1
	V_CVT_F32_I32_e32 v29, v29                                                  ; 7E3A0B1D
	V_MAD_F32 v30, v30, v29, v7, 0, 0, 0, 0                                     ; D282001E 041E3B1E
	V_MAD_F32 v27, v27, v29, v20, 0, 0, 0, 0                                    ; D282001B 04523B1B
	V_ADD_F32_e64 v31, v27, 0, 0, 0, 0, 1                                       ; D206001F 2201011B
	V_RCP_F32_e32 v31, v31                                                      ; 7E3E551F
	V_MUL_F32_e32 v30, v30, v31                                                 ; 103C3F1E
	V_MUL_F32_e32 v30, s27, v30                                                 ; 103C3C1B
	V_SUBREV_F32_e32 v30, s26, v30                                              ; 0A3C3C1A
	V_MAD_F32 v30, v30, -5.000000e-01, 5.000000e-01, 0, 0, 0, 0                 ; D282001E 03C1E31E
	V_ADD_F32_e64 v33, 0, v30, 0, 1, 0, 0                                       ; D2060821 02023C80
	V_MAD_F32 v28, v28, v29, v4, 0, 0, 0, 0                                     ; D282001C 04123B1C
	V_MUL_F32_e32 v28, v28, v31                                                 ; 10383F1C
	V_MUL_F32_e32 v28, s29, v28                                                 ; 1038381D
	V_SUBREV_F32_e32 v28, s28, v28                                              ; 0A38381C
	V_MAD_F32 v28, v28, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0                  ; D282001C 03C1E11C
	V_ADD_F32_e64 v32, 0, v28, 0, 1, 0, 0                                       ; D2060820 02023880
	IMAGE_SAMPLE v28, 1, 0, 0, 0, 0, 0, 0, 0, v[32:33], s[12:19], s[8:11]       ; F0800100 00431C20
	S_WAITCNT vmcnt(0)                                                          ; BF8C0770
	V_ADD_F32_e64 v29, v28, 0, 1, 0, 0, 0                                       ; D206011D 0201011C
	V_MUL_F32_e32 v29, s24, v29                                                 ; 103A3A18
	V_SUBREV_F32_e32 v29, s25, v29                                              ; 0A3A3A19
	V_CMP_EQ_F32_e64 s[2:3], v29, 0.000000e+00, 0, 0, 0, 0                      ; D0040002 0201011D
	V_CNDMASK_B32_e64 v30, 0.000000e+00, 1.401298e-45, s[2:3], 0, 0, 0, 0       ; D200001E 00090280
	V_CVT_F32_I32_e32 v30, v30                                                  ; 7E3C0B1E
	V_SUB_F32_e32 v27, v29, v27                                                 ; 0836371D
	V_ADD_F32_e32 v29, v21, v21                                                 ; 063A2B15
	V_CMP_GE_F32_e64 s[2:3], v27, v29, 0, 0, 0, 0                               ; D00C0002 02023B1B
	V_CNDMASK_B32_e64 v29, 0, -1, s[2:3], 0, 0, 0, 0                            ; D200001D 00098280
	V_AND_B32_e32 v29, 1065353216, v29                                          ; 363A3AF2
	V_ADD_F32_e32 v29, v29, v30                                                 ; 063A3D1D
	V_CMP_LE_F32_e64 s[2:3], v28, 0.000000e+00, 0, 0, 0, 0                      ; D0060002 0201011C
	V_CNDMASK_B32_e64 v28, 0, -1, s[2:3], 0, 0, 0, 0                            ; D200001C 00098280
	V_AND_B32_e32 v28, 1065353216, v28                                          ; 363838F2
	V_MAD_F32 v28, v28, v1, v29, 0, 0, 0, 0                                     ; D282001C 0476031C
	V_ADD_F32_e64 v28, 0, v28, 0, 1, 0, 0                                       ; D206081C 02023880
	V_SUB_F32_e32 v29, 1.000000e+00, v28                                        ; 083A38F2
	V_CMP_GE_F32_e64 s[2:3], v27, 0.000000e+00, 0, 0, 0, 0                      ; D00C0002 0201011B
	V_CNDMASK_B32_e64 v27, 0, -1, s[2:3], 0, 0, 0, 0                            ; D200001B 00098280
	V_AND_B32_e32 v27, 1065353216, v27                                          ; 363636F2
	V_MAD_F32 v12, v27, v29, v12, 0, 0, 0, 0                                    ; D282000C 04323B1B
	S_BUFFER_LOAD_DWORD s2, s[20:23], 68                                        ; C2011544
	S_WAITCNT lgkmcnt(0)                                                        ; BF8C007F
	V_MUL_F32_e32 v27, s2, v3                                                   ; 10360602
	S_BUFFER_LOAD_DWORD s3, s[20:23], 69                                        ; C2019545
	S_WAITCNT lgkmcnt(0)                                                        ; BF8C007F
	V_MAD_F32 v27, v2, s3, v27, 0, 0, 0, 0                                      ; D282001B 046C0702
	S_BUFFER_LOAD_DWORD s4, s[20:23], 70                                        ; C2021546
	S_WAITCNT lgkmcnt(0)                                                        ; BF8C007F
	V_MAD_F32 v27, v10, s4, v27, 0, 0, 0, 0                                     ; D282001B 046C090A
	V_MUL_F32_e32 v29, v27, v3                                                  ; 103A071B
	V_MAD_F32 v29, v27, v3, v29, 0, 0, 0, 0                                     ; D282001D 0476071B
	V_SUB_F32_e32 v29, s2, v29                                                  ; 083A3A02
	V_MAD_F32 v23, v14, -4.000000e+00, v23, 0, 0, 0, 0                          ; D2820017 045DEF0E
	V_MUL_F32_e32 v29, v29, v23                                                 ; 103A2F1D
	V_MUL_F32_e32 v30, v29, v8                                                  ; 103C111D
	V_MUL_F32_e32 v31, v27, v2                                                  ; 103E051B
	V_MAD_F32 v31, v27, v2, v31, 0, 0, 0, 0                                     ; D282001F 047E051B
	V_SUB_F32_e32 v31, s3, v31                                                  ; 083E3E03
	V_MUL_F32_e32 v31, v31, v23                                                 ; 103E2F1F
	V_MAD_F32 v30, v31, v9, v30, 0, 0, 0, 0                                     ; D282001E 047A131F
	V_MUL_F32_e32 v32, v27, v10                                                 ; 1040151B
	V_MAD_F32 v27, v27, v10, v32, 0, 0, 0, 0                                    ; D282001B 0482151B
	V_SUB_F32_e32 v27, s4, v27                                                  ; 08363604
	V_MUL_F32_e32 v27, v27, v23                                                 ; 10362F1B
	V_MAD_F32 v30, v27, v5, v30, 0, 0, 0, 0                                     ; D282001E 047A0B1B
	V_CMP_GE_F32_e64 s[2:3], v30, 0.000000e+00, 0, 0, 0, 0                      ; D00C0002 0201011E
	V_CNDMASK_B32_e64 v30, -nan, 1.401298e-45, s[2:3], 0, 0, 0, 0               ; D200001E 000902C1
	V_CVT_F32_I32_e32 v30, v30                                                  ; 7E3C0B1E
	V_MAD_F32 v31, v31, v30, v7, 0, 0, 0, 0                                     ; D282001F 041E3D1F
	V_MAD_F32 v27, v27, v30, v20, 0, 0, 0, 0                                    ; D282001B 04523D1B
	V_ADD_F32_e64 v32, v27, 0, 0, 0, 0, 1                                       ; D2060020 2201011B
	V_RCP_F32_e32 v32, v32                                                      ; 7E405520
	V_MUL_F32_e32 v31, v31, v32                                                 ; 103E411F
	V_MUL_F32_e32 v31, s27, v31                                                 ; 103E3E1B
	V_SUBREV_F32_e32 v31, s26, v31                                              ; 0A3E3E1A
	V_MAD_F32 v31, v31, -5.000000e-01, 5.000000e-01, 0, 0, 0, 0                 ; D282001F 03C1E31F
	V_ADD_F32_e64 v34, 0, v31, 0, 1, 0, 0                                       ; D2060822 02023E80
	V_MAD_F32 v29, v29, v30, v4, 0, 0, 0, 0                                     ; D282001D 04123D1D
	V_MUL_F32_e32 v29, v29, v32                                                 ; 103A411D
	V_MUL_F32_e32 v29, s29, v29                                                 ; 103A3A1D
	V_SUBREV_F32_e32 v29, s28, v29                                              ; 0A3A3A1C
	V_MAD_F32 v29, v29, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0                  ; D282001D 03C1E11D
	V_ADD_F32_e64 v33, 0, v29, 0, 1, 0, 0                                       ; D2060821 02023A80
	IMAGE_SAMPLE v29, 1, 0, 0, 0, 0, 0, 0, 0, v[33:34], s[12:19], s[8:11]       ; F0800100 00431D21
	S_WAITCNT vmcnt(0)                                                          ; BF8C0770
	V_ADD_F32_e64 v30, v29, 0, 1, 0, 0, 0                                       ; D206011E 0201011D
	V_MUL_F32_e32 v30, s24, v30                                                 ; 103C3C18
	V_SUBREV_F32_e32 v30, s25, v30                                              ; 0A3C3C19
	V_CMP_EQ_F32_e64 s[2:3], v30, 0.000000e+00, 0, 0, 0, 0                      ; D0040002 0201011E
	V_CNDMASK_B32_e64 v31, 0.000000e+00, 1.401298e-45, s[2:3], 0, 0, 0, 0       ; D200001F 00090280
	V_CVT_F32_I32_e32 v31, v31                                                  ; 7E3E0B1F
	V_SUB_F32_e32 v27, v30, v27                                                 ; 0836371E
	V_ADD_F32_e32 v30, v23, v23                                                 ; 063C2F17
	V_CMP_GE_F32_e64 s[2:3], v27, v30, 0, 0, 0, 0                               ; D00C0002 02023D1B
	V_CNDMASK_B32_e64 v30, 0, -1, s[2:3], 0, 0, 0, 0                            ; D200001E 00098280
	V_AND_B32_e32 v30, 1065353216, v30                                          ; 363C3CF2
	V_ADD_F32_e32 v30, v30, v31                                                 ; 063C3F1E
	V_CMP_LE_F32_e64 s[2:3], v29, 0.000000e+00, 0, 0, 0, 0                      ; D0060002 0201011D
	V_CNDMASK_B32_e64 v29, 0, -1, s[2:3], 0, 0, 0, 0                            ; D200001D 00098280
	V_AND_B32_e32 v29, 1065353216, v29                                          ; 363A3AF2
	V_MAD_F32 v29, v29, v1, v30, 0, 0, 0, 0                                     ; D282001D 047A031D
	V_ADD_F32_e64 v29, 0, v29, 0, 1, 0, 0                                       ; D206081D 02023A80
	V_SUB_F32_e32 v30, 1.000000e+00, v29                                        ; 083C3AF2
	V_CMP_GE_F32_e64 s[2:3], v27, 0.000000e+00, 0, 0, 0, 0                      ; D00C0002 0201011B
	V_CNDMASK_B32_e64 v27, 0, -1, s[2:3], 0, 0, 0, 0                            ; D200001B 00098280
	V_AND_B32_e32 v27, 1065353216, v27                                          ; 363636F2
	V_MAD_F32 v12, v27, v30, v12, 0, 0, 0, 0                                    ; D282000C 04323D1B
	S_BUFFER_LOAD_DWORD s2, s[20:23], 72                                        ; C2011548
	S_WAITCNT lgkmcnt(0)                                                        ; BF8C007F
	V_MUL_F32_e32 v27, s2, v3                                                   ; 10360602
	S_BUFFER_LOAD_DWORD s3, s[20:23], 73                                        ; C2019549
	S_WAITCNT lgkmcnt(0)                                                        ; BF8C007F
	V_MAD_F32 v27, v2, s3, v27, 0, 0, 0, 0                                      ; D282001B 046C0702
	S_BUFFER_LOAD_DWORD s4, s[20:23], 74                                        ; C202154A
	S_WAITCNT lgkmcnt(0)                                                        ; BF8C007F
	V_MAD_F32 v27, v10, s4, v27, 0, 0, 0, 0                                     ; D282001B 046C090A
	V_MUL_F32_e32 v30, v27, v3                                                  ; 103C071B
	V_MAD_F32 v30, v27, v3, v30, 0, 0, 0, 0                                     ; D282001E 047A071B
	V_SUB_F32_e32 v30, s2, v30                                                  ; 083C3C02
	V_MAD_F32 v25, v14, -4.000000e+00, v25, 0, 0, 0, 0                          ; D2820019 0465EF0E
	V_MUL_F32_e32 v30, v30, v25                                                 ; 103C331E
	V_MUL_F32_e32 v31, v30, v8                                                  ; 103E111E
	V_MUL_F32_e32 v32, v27, v2                                                  ; 1040051B
	V_MAD_F32 v32, v27, v2, v32, 0, 0, 0, 0                                     ; D2820020 0482051B
	V_SUB_F32_e32 v32, s3, v32                                                  ; 08404003
	V_MUL_F32_e32 v32, v32, v25                                                 ; 10403320
	V_MAD_F32 v31, v32, v9, v31, 0, 0, 0, 0                                     ; D282001F 047E1320
	V_MUL_F32_e32 v33, v27, v10                                                 ; 1042151B
	V_MAD_F32 v27, v27, v10, v33, 0, 0, 0, 0                                    ; D282001B 0486151B
	V_SUB_F32_e32 v27, s4, v27                                                  ; 08363604
	V_MUL_F32_e32 v27, v27, v25                                                 ; 1036331B
	V_MAD_F32 v31, v27, v5, v31, 0, 0, 0, 0                                     ; D282001F 047E0B1B
	V_CMP_GE_F32_e64 s[2:3], v31, 0.000000e+00, 0, 0, 0, 0                      ; D00C0002 0201011F
	V_CNDMASK_B32_e64 v31, -nan, 1.401298e-45, s[2:3], 0, 0, 0, 0               ; D200001F 000902C1
	V_CVT_F32_I32_e32 v31, v31                                                  ; 7E3E0B1F
	V_MAD_F32 v32, v32, v31, v7, 0, 0, 0, 0                                     ; D2820020 041E3F20
	V_MAD_F32 v27, v27, v31, v20, 0, 0, 0, 0                                    ; D282001B 04523F1B
	V_ADD_F32_e64 v33, v27, 0, 0, 0, 0, 1                                       ; D2060021 2201011B
	V_RCP_F32_e32 v33, v33                                                      ; 7E425521
	V_MUL_F32_e32 v32, v32, v33                                                 ; 10404320
	V_MUL_F32_e32 v32, s27, v32                                                 ; 1040401B
	V_SUBREV_F32_e32 v32, s26, v32                                              ; 0A40401A
	V_MAD_F32 v32, v32, -5.000000e-01, 5.000000e-01, 0, 0, 0, 0                 ; D2820020 03C1E320
	V_ADD_F32_e64 v35, 0, v32, 0, 1, 0, 0                                       ; D2060823 02024080
	V_MAD_F32 v30, v30, v31, v4, 0, 0, 0, 0                                     ; D282001E 04123F1E
	V_MUL_F32_e32 v30, v30, v33                                                 ; 103C431E
	V_MUL_F32_e32 v30, s29, v30                                                 ; 103C3C1D
	V_SUBREV_F32_e32 v30, s28, v30                                              ; 0A3C3C1C
	V_MAD_F32 v30, v30, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0                  ; D282001E 03C1E11E
	V_ADD_F32_e64 v34, 0, v30, 0, 1, 0, 0                                       ; D2060822 02023C80
	IMAGE_SAMPLE v30, 1, 0, 0, 0, 0, 0, 0, 0, v[34:35], s[12:19], s[8:11]       ; F0800100 00431E22
	S_WAITCNT vmcnt(0)                                                          ; BF8C0770
	V_ADD_F32_e64 v31, v30, 0, 1, 0, 0, 0                                       ; D206011F 0201011E
	V_MUL_F32_e32 v31, s24, v31                                                 ; 103E3E18
	V_SUBREV_F32_e32 v31, s25, v31                                              ; 0A3E3E19
	V_CMP_EQ_F32_e64 s[2:3], v31, 0.000000e+00, 0, 0, 0, 0                      ; D0040002 0201011F
	V_CNDMASK_B32_e64 v32, 0.000000e+00, 1.401298e-45, s[2:3], 0, 0, 0, 0       ; D2000020 00090280
	V_CVT_F32_I32_e32 v32, v32                                                  ; 7E400B20
	V_SUB_F32_e32 v27, v31, v27                                                 ; 0836371F
	V_ADD_F32_e32 v31, v25, v25                                                 ; 063E3319
	V_CMP_GE_F32_e64 s[2:3], v27, v31, 0, 0, 0, 0                               ; D00C0002 02023F1B
	V_CNDMASK_B32_e64 v31, 0, -1, s[2:3], 0, 0, 0, 0                            ; D200001F 00098280
	V_AND_B32_e32 v31, 1065353216, v31                                          ; 363E3EF2
	V_ADD_F32_e32 v31, v31, v32                                                 ; 063E411F
	V_CMP_LE_F32_e64 s[2:3], v30, 0.000000e+00, 0, 0, 0, 0                      ; D0060002 0201011E
	V_CNDMASK_B32_e64 v30, 0, -1, s[2:3], 0, 0, 0, 0                            ; D200001E 00098280
	V_AND_B32_e32 v30, 1065353216, v30                                          ; 363C3CF2
	V_MAD_F32 v30, v30, v1, v31, 0, 0, 0, 0                                     ; D282001E 047E031E
	V_ADD_F32_e64 v30, 0, v30, 0, 1, 0, 0                                       ; D206081E 02023C80
	V_SUB_F32_e32 v31, 1.000000e+00, v30                                        ; 083E3CF2
	V_CMP_GE_F32_e64 s[2:3], v27, 0.000000e+00, 0, 0, 0, 0                      ; D00C0002 0201011B
	V_CNDMASK_B32_e64 v27, 0, -1, s[2:3], 0, 0, 0, 0                            ; D200001B 00098280
	V_AND_B32_e32 v27, 1065353216, v27                                          ; 363636F2
	V_MAD_F32 v12, v27, v31, v12, 0, 0, 0, 0                                    ; D282000C 04323F1B
	V_ADD_F32_e32 v6, v6, v12                                                   ; 060C1906
	S_BUFFER_LOAD_DWORD s2, s[20:23], 80                                        ; C2011550
	S_WAITCNT lgkmcnt(0)                                                        ; BF8C007F
	V_MUL_F32_e32 v12, s2, v3                                                   ; 10180602
	S_BUFFER_LOAD_DWORD s3, s[20:23], 81                                        ; C2019551
	S_WAITCNT lgkmcnt(0)                                                        ; BF8C007F
	V_MAD_F32 v12, v2, s3, v12, 0, 0, 0, 0                                      ; D282000C 04300702
	S_BUFFER_LOAD_DWORD s4, s[20:23], 82                                        ; C2021552
	S_WAITCNT lgkmcnt(0)                                                        ; BF8C007F
	V_MAD_F32 v12, v10, s4, v12, 0, 0, 0, 0                                     ; D282000C 0430090A
	V_MUL_F32_e32 v27, v12, v3                                                  ; 1036070C
	V_MAD_F32 v27, v12, v3, v27, 0, 0, 0, 0                                     ; D282001B 046E070C
	V_SUB_F32_e32 v27, s2, v27                                                  ; 08363602
	V_MAD_F32 v17, v14, -4.000000e+00, v17, 0, 0, 0, 0                          ; D2820011 0445EF0E
	V_MUL_F32_e32 v27, v27, v17                                                 ; 1036231B
	V_MUL_F32_e32 v31, v27, v8                                                  ; 103E111B
	V_MUL_F32_e32 v32, v12, v2                                                  ; 1040050C
	V_MAD_F32 v32, v12, v2, v32, 0, 0, 0, 0                                     ; D2820020 0482050C
	V_SUB_F32_e32 v32, s3, v32                                                  ; 08404003
	V_MUL_F32_e32 v32, v32, v17                                                 ; 10402320
	V_MAD_F32 v31, v32, v9, v31, 0, 0, 0, 0                                     ; D282001F 047E1320
	V_MUL_F32_e32 v33, v12, v10                                                 ; 1042150C
	V_MAD_F32 v12, v12, v10, v33, 0, 0, 0, 0                                    ; D282000C 0486150C
	V_SUB_F32_e32 v12, s4, v12                                                  ; 08181804
	V_MUL_F32_e32 v12, v12, v17                                                 ; 1018230C
	V_MAD_F32 v31, v12, v5, v31, 0, 0, 0, 0                                     ; D282001F 047E0B0C
	V_CMP_GE_F32_e64 s[2:3], v31, 0.000000e+00, 0, 0, 0, 0                      ; D00C0002 0201011F
	V_CNDMASK_B32_e64 v31, -nan, 1.401298e-45, s[2:3], 0, 0, 0, 0               ; D200001F 000902C1
	V_CVT_F32_I32_e32 v31, v31                                                  ; 7E3E0B1F
	V_MAD_F32 v32, v32, v31, v7, 0, 0, 0, 0                                     ; D2820020 041E3F20
	V_MAD_F32 v12, v12, v31, v20, 0, 0, 0, 0                                    ; D282000C 04523F0C
	V_ADD_F32_e64 v33, v12, 0, 0, 0, 0, 1                                       ; D2060021 2201010C
	V_RCP_F32_e32 v33, v33                                                      ; 7E425521
	V_MUL_F32_e32 v32, v32, v33                                                 ; 10404320
	V_MUL_F32_e32 v32, s27, v32                                                 ; 1040401B
	V_SUBREV_F32_e32 v32, s26, v32                                              ; 0A40401A
	V_MAD_F32 v32, v32, -5.000000e-01, 5.000000e-01, 0, 0, 0, 0                 ; D2820020 03C1E320
	V_ADD_F32_e64 v35, 0, v32, 0, 1, 0, 0                                       ; D2060823 02024080
	V_MAD_F32 v27, v27, v31, v4, 0, 0, 0, 0                                     ; D282001B 04123F1B
	V_MUL_F32_e32 v27, v27, v33                                                 ; 1036431B
	V_MUL_F32_e32 v27, s29, v27                                                 ; 1036361D
	V_SUBREV_F32_e32 v27, s28, v27                                              ; 0A36361C
	V_MAD_F32 v27, v27, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0                  ; D282001B 03C1E11B
	V_ADD_F32_e64 v34, 0, v27, 0, 1, 0, 0                                       ; D2060822 02023680
	IMAGE_SAMPLE v27, 1, 0, 0, 0, 0, 0, 0, 0, v[34:35], s[12:19], s[8:11]       ; F0800100 00431B22
	S_WAITCNT vmcnt(0)                                                          ; BF8C0770
	V_ADD_F32_e64 v31, v27, 0, 1, 0, 0, 0                                       ; D206011F 0201011B
	V_MUL_F32_e32 v31, s24, v31                                                 ; 103E3E18
	V_SUBREV_F32_e32 v31, s25, v31                                              ; 0A3E3E19
	V_CMP_EQ_F32_e64 s[2:3], v31, 0.000000e+00, 0, 0, 0, 0                      ; D0040002 0201011F
	V_CNDMASK_B32_e64 v32, 0.000000e+00, 1.401298e-45, s[2:3], 0, 0, 0, 0       ; D2000020 00090280
	V_CVT_F32_I32_e32 v32, v32                                                  ; 7E400B20
	V_SUB_F32_e32 v12, v31, v12                                                 ; 0818191F
	V_ADD_F32_e32 v17, v17, v17                                                 ; 06222311
	V_CMP_GE_F32_e64 s[2:3], v12, v17, 0, 0, 0, 0                               ; D00C0002 0202230C
	V_CNDMASK_B32_e64 v17, 0, -1, s[2:3], 0, 0, 0, 0                            ; D2000011 00098280
	V_AND_B32_e32 v17, 1065353216, v17                                          ; 362222F2
	V_ADD_F32_e32 v17, v17, v32                                                 ; 06224111
	V_CMP_LE_F32_e64 s[2:3], v27, 0.000000e+00, 0, 0, 0, 0                      ; D0060002 0201011B
	V_CNDMASK_B32_e64 v27, 0, -1, s[2:3], 0, 0, 0, 0                            ; D200001B 00098280
	V_AND_B32_e32 v27, 1065353216, v27                                          ; 363636F2
	V_MAD_F32 v17, v27, v1, v17, 0, 0, 0, 0                                     ; D2820011 0446031B
	V_ADD_F32_e64 v17, 0, v17, 0, 1, 0, 0                                       ; D2060811 02022280
	V_SUB_F32_e32 v27, 1.000000e+00, v17                                        ; 083622F2
	V_CMP_GE_F32_e64 s[2:3], v12, 0.000000e+00, 0, 0, 0, 0                      ; D00C0002 0201010C
	V_CNDMASK_B32_e64 v12, 0, -1, s[2:3], 0, 0, 0, 0                            ; D200000C 00098280
	V_AND_B32_e32 v12, 1065353216, v12                                          ; 361818F2
	V_MUL_F32_e32 v12, v12, v27                                                 ; 1018370C
	S_BUFFER_LOAD_DWORD s2, s[20:23], 76                                        ; C201154C
	S_WAITCNT lgkmcnt(0)                                                        ; BF8C007F
	V_MUL_F32_e32 v27, s2, v3                                                   ; 10360602
	S_BUFFER_LOAD_DWORD s3, s[20:23], 77                                        ; C201954D
	S_WAITCNT lgkmcnt(0)                                                        ; BF8C007F
	V_MAD_F32 v27, v2, s3, v27, 0, 0, 0, 0                                      ; D282001B 046C0702
	S_BUFFER_LOAD_DWORD s4, s[20:23], 78                                        ; C202154E
	S_WAITCNT lgkmcnt(0)                                                        ; BF8C007F
	V_MAD_F32 v27, v10, s4, v27, 0, 0, 0, 0                                     ; D282001B 046C090A
	V_MUL_F32_e32 v31, v27, v3                                                  ; 103E071B
	V_MAD_F32 v31, v27, v3, v31, 0, 0, 0, 0                                     ; D282001F 047E071B
	V_SUB_F32_e32 v31, s2, v31                                                  ; 083E3E02
	V_MAD_F32 v21, v14, -4.000000e+00, v21, 0, 0, 0, 0                          ; D2820015 0455EF0E
	V_MUL_F32_e32 v31, v31, v21                                                 ; 103E2B1F
	V_MUL_F32_e32 v32, v31, v8                                                  ; 1040111F
	V_MUL_F32_e32 v33, v27, v2                                                  ; 1042051B
	V_MAD_F32 v33, v27, v2, v33, 0, 0, 0, 0                                     ; D2820021 0486051B
	V_SUB_F32_e32 v33, s3, v33                                                  ; 08424203
	V_MUL_F32_e32 v33, v33, v21                                                 ; 10422B21
	V_MAD_F32 v32, v33, v9, v32, 0, 0, 0, 0                                     ; D2820020 04821321
	V_MUL_F32_e32 v34, v27, v10                                                 ; 1044151B
	V_MAD_F32 v27, v27, v10, v34, 0, 0, 0, 0                                    ; D282001B 048A151B
	V_SUB_F32_e32 v27, s4, v27                                                  ; 08363604
	V_MUL_F32_e32 v27, v27, v21                                                 ; 10362B1B
	V_MAD_F32 v32, v27, v5, v32, 0, 0, 0, 0                                     ; D2820020 04820B1B
	V_CMP_GE_F32_e64 s[2:3], v32, 0.000000e+00, 0, 0, 0, 0                      ; D00C0002 02010120
	V_CNDMASK_B32_e64 v32, -nan, 1.401298e-45, s[2:3], 0, 0, 0, 0               ; D2000020 000902C1
	V_CVT_F32_I32_e32 v32, v32                                                  ; 7E400B20
	V_MAD_F32 v33, v33, v32, v7, 0, 0, 0, 0                                     ; D2820021 041E4121
	V_MAD_F32 v27, v27, v32, v20, 0, 0, 0, 0                                    ; D282001B 0452411B
	V_ADD_F32_e64 v34, v27, 0, 0, 0, 0, 1                                       ; D2060022 2201011B
	V_RCP_F32_e32 v34, v34                                                      ; 7E445522
	V_MUL_F32_e32 v33, v33, v34                                                 ; 10424521
	V_MUL_F32_e32 v33, s27, v33                                                 ; 1042421B
	V_SUBREV_F32_e32 v33, s26, v33                                              ; 0A42421A
	V_MAD_F32 v33, v33, -5.000000e-01, 5.000000e-01, 0, 0, 0, 0                 ; D2820021 03C1E321
	V_ADD_F32_e64 v36, 0, v33, 0, 1, 0, 0                                       ; D2060824 02024280
	V_MAD_F32 v31, v31, v32, v4, 0, 0, 0, 0                                     ; D282001F 0412411F
	V_MUL_F32_e32 v31, v31, v34                                                 ; 103E451F
	V_MUL_F32_e32 v31, s29, v31                                                 ; 103E3E1D
	V_SUBREV_F32_e32 v31, s28, v31                                              ; 0A3E3E1C
	V_MAD_F32 v31, v31, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0                  ; D282001F 03C1E11F
	V_ADD_F32_e64 v35, 0, v31, 0, 1, 0, 0                                       ; D2060823 02023E80
	IMAGE_SAMPLE v31, 1, 0, 0, 0, 0, 0, 0, 0, v[35:36], s[12:19], s[8:11]       ; F0800100 00431F23
	S_WAITCNT vmcnt(0)                                                          ; BF8C0770
	V_ADD_F32_e64 v32, v31, 0, 1, 0, 0, 0                                       ; D2060120 0201011F
	V_MUL_F32_e32 v32, s24, v32                                                 ; 10404018
	V_SUBREV_F32_e32 v32, s25, v32                                              ; 0A404019
	V_CMP_EQ_F32_e64 s[2:3], v32, 0.000000e+00, 0, 0, 0, 0                      ; D0040002 02010120
	V_CNDMASK_B32_e64 v33, 0.000000e+00, 1.401298e-45, s[2:3], 0, 0, 0, 0       ; D2000021 00090280
	V_CVT_F32_I32_e32 v33, v33                                                  ; 7E420B21
	V_SUB_F32_e32 v27, v32, v27                                                 ; 08363720
	V_ADD_F32_e32 v21, v21, v21                                                 ; 062A2B15
	V_CMP_GE_F32_e64 s[2:3], v27, v21, 0, 0, 0, 0                               ; D00C0002 02022B1B
	V_CNDMASK_B32_e64 v21, 0, -1, s[2:3], 0, 0, 0, 0                            ; D2000015 00098280
	V_AND_B32_e32 v21, 1065353216, v21                                          ; 362A2AF2
	V_ADD_F32_e32 v21, v21, v33                                                 ; 062A4315
	V_CMP_LE_F32_e64 s[2:3], v31, 0.000000e+00, 0, 0, 0, 0                      ; D0060002 0201011F
	V_CNDMASK_B32_e64 v31, 0, -1, s[2:3], 0, 0, 0, 0                            ; D200001F 00098280
	V_AND_B32_e32 v31, 1065353216, v31                                          ; 363E3EF2
	V_MAD_F32 v21, v31, v1, v21, 0, 0, 0, 0                                     ; D2820015 0456031F
	V_ADD_F32_e64 v21, 0, v21, 0, 1, 0, 0                                       ; D2060815 02022A80
	V_SUB_F32_e32 v31, 1.000000e+00, v21                                        ; 083E2AF2
	V_CMP_GE_F32_e64 s[2:3], v27, 0.000000e+00, 0, 0, 0, 0                      ; D00C0002 0201011B
	V_CNDMASK_B32_e64 v27, 0, -1, s[2:3], 0, 0, 0, 0                            ; D200001B 00098280
	V_AND_B32_e32 v27, 1065353216, v27                                          ; 363636F2
	V_MAD_F32 v12, v27, v31, v12, 0, 0, 0, 0                                    ; D282000C 04323F1B
	S_BUFFER_LOAD_DWORD s2, s[20:23], 84                                        ; C2011554
	S_WAITCNT lgkmcnt(0)                                                        ; BF8C007F
	V_MUL_F32_e32 v27, s2, v3                                                   ; 10360602
	S_BUFFER_LOAD_DWORD s3, s[20:23], 85                                        ; C2019555
	S_WAITCNT lgkmcnt(0)                                                        ; BF8C007F
	V_MAD_F32 v27, v2, s3, v27, 0, 0, 0, 0                                      ; D282001B 046C0702
	S_BUFFER_LOAD_DWORD s4, s[20:23], 86                                        ; C2021556
	S_WAITCNT lgkmcnt(0)                                                        ; BF8C007F
	V_MAD_F32 v27, v10, s4, v27, 0, 0, 0, 0                                     ; D282001B 046C090A
	V_MUL_F32_e32 v31, v27, v3                                                  ; 103E071B
	V_MAD_F32 v31, v27, v3, v31, 0, 0, 0, 0                                     ; D282001F 047E071B
	V_SUB_F32_e32 v31, s2, v31                                                  ; 083E3E02
	V_MAD_F32 v23, v14, -4.000000e+00, v23, 0, 0, 0, 0                          ; D2820017 045DEF0E
	V_MUL_F32_e32 v31, v31, v23                                                 ; 103E2F1F
	V_MUL_F32_e32 v32, v31, v8                                                  ; 1040111F
	V_MUL_F32_e32 v33, v27, v2                                                  ; 1042051B
	V_MAD_F32 v33, v27, v2, v33, 0, 0, 0, 0                                     ; D2820021 0486051B
	V_SUB_F32_e32 v33, s3, v33                                                  ; 08424203
	V_MUL_F32_e32 v33, v33, v23                                                 ; 10422F21
	V_MAD_F32 v32, v33, v9, v32, 0, 0, 0, 0                                     ; D2820020 04821321
	V_MUL_F32_e32 v34, v27, v10                                                 ; 1044151B
	V_MAD_F32 v27, v27, v10, v34, 0, 0, 0, 0                                    ; D282001B 048A151B
	V_SUB_F32_e32 v27, s4, v27                                                  ; 08363604
	V_MUL_F32_e32 v27, v27, v23                                                 ; 10362F1B
	V_MAD_F32 v32, v27, v5, v32, 0, 0, 0, 0                                     ; D2820020 04820B1B
	V_CMP_GE_F32_e64 s[2:3], v32, 0.000000e+00, 0, 0, 0, 0                      ; D00C0002 02010120
	V_CNDMASK_B32_e64 v32, -nan, 1.401298e-45, s[2:3], 0, 0, 0, 0               ; D2000020 000902C1
	V_CVT_F32_I32_e32 v32, v32                                                  ; 7E400B20
	V_MAD_F32 v33, v33, v32, v7, 0, 0, 0, 0                                     ; D2820021 041E4121
	V_MAD_F32 v27, v27, v32, v20, 0, 0, 0, 0                                    ; D282001B 0452411B
	V_ADD_F32_e64 v34, v27, 0, 0, 0, 0, 1                                       ; D2060022 2201011B
	V_RCP_F32_e32 v34, v34                                                      ; 7E445522
	V_MUL_F32_e32 v33, v33, v34                                                 ; 10424521
	V_MUL_F32_e32 v33, s27, v33                                                 ; 1042421B
	V_SUBREV_F32_e32 v33, s26, v33                                              ; 0A42421A
	V_MAD_F32 v33, v33, -5.000000e-01, 5.000000e-01, 0, 0, 0, 0                 ; D2820021 03C1E321
	V_ADD_F32_e64 v36, 0, v33, 0, 1, 0, 0                                       ; D2060824 02024280
	V_MAD_F32 v31, v31, v32, v4, 0, 0, 0, 0                                     ; D282001F 0412411F
	V_MUL_F32_e32 v31, v31, v34                                                 ; 103E451F
	V_MUL_F32_e32 v31, s29, v31                                                 ; 103E3E1D
	V_SUBREV_F32_e32 v31, s28, v31                                              ; 0A3E3E1C
	V_MAD_F32 v31, v31, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0                  ; D282001F 03C1E11F
	V_ADD_F32_e64 v35, 0, v31, 0, 1, 0, 0                                       ; D2060823 02023E80
	IMAGE_SAMPLE v31, 1, 0, 0, 0, 0, 0, 0, 0, v[35:36], s[12:19], s[8:11]       ; F0800100 00431F23
	S_WAITCNT vmcnt(0)                                                          ; BF8C0770
	V_ADD_F32_e64 v32, v31, 0, 1, 0, 0, 0                                       ; D2060120 0201011F
	V_MUL_F32_e32 v32, s24, v32                                                 ; 10404018
	V_SUBREV_F32_e32 v32, s25, v32                                              ; 0A404019
	V_CMP_EQ_F32_e64 s[2:3], v32, 0.000000e+00, 0, 0, 0, 0                      ; D0040002 02010120
	V_CNDMASK_B32_e64 v33, 0.000000e+00, 1.401298e-45, s[2:3], 0, 0, 0, 0       ; D2000021 00090280
	V_CVT_F32_I32_e32 v33, v33                                                  ; 7E420B21
	V_SUB_F32_e32 v27, v32, v27                                                 ; 08363720
	V_ADD_F32_e32 v23, v23, v23                                                 ; 062E2F17
	V_CMP_GE_F32_e64 s[2:3], v27, v23, 0, 0, 0, 0                               ; D00C0002 02022F1B
	V_CNDMASK_B32_e64 v23, 0, -1, s[2:3], 0, 0, 0, 0                            ; D2000017 00098280
	V_AND_B32_e32 v23, 1065353216, v23                                          ; 362E2EF2
	V_ADD_F32_e32 v23, v23, v33                                                 ; 062E4317
	V_CMP_LE_F32_e64 s[2:3], v31, 0.000000e+00, 0, 0, 0, 0                      ; D0060002 0201011F
	V_CNDMASK_B32_e64 v31, 0, -1, s[2:3], 0, 0, 0, 0                            ; D200001F 00098280
	V_AND_B32_e32 v31, 1065353216, v31                                          ; 363E3EF2
	V_MAD_F32 v23, v31, v1, v23, 0, 0, 0, 0                                     ; D2820017 045E031F
	V_ADD_F32_e64 v23, 0, v23, 0, 1, 0, 0                                       ; D2060817 02022E80
	V_SUB_F32_e32 v31, 1.000000e+00, v23                                        ; 083E2EF2
	V_CMP_GE_F32_e64 s[2:3], v27, 0.000000e+00, 0, 0, 0, 0                      ; D00C0002 0201011B
	V_CNDMASK_B32_e64 v27, 0, -1, s[2:3], 0, 0, 0, 0                            ; D200001B 00098280
	V_AND_B32_e32 v27, 1065353216, v27                                          ; 363636F2
	V_MAD_F32 v12, v27, v31, v12, 0, 0, 0, 0                                    ; D282000C 04323F1B
	S_BUFFER_LOAD_DWORD s2, s[20:23], 88                                        ; C2011558
	S_WAITCNT lgkmcnt(0)                                                        ; BF8C007F
	V_MUL_F32_e32 v27, s2, v3                                                   ; 10360602
	S_BUFFER_LOAD_DWORD s3, s[20:23], 89                                        ; C2019559
	S_WAITCNT lgkmcnt(0)                                                        ; BF8C007F
	V_MAD_F32 v27, v2, s3, v27, 0, 0, 0, 0                                      ; D282001B 046C0702
	S_BUFFER_LOAD_DWORD s4, s[20:23], 90                                        ; C202155A
	S_WAITCNT lgkmcnt(0)                                                        ; BF8C007F
	V_MAD_F32 v27, v10, s4, v27, 0, 0, 0, 0                                     ; D282001B 046C090A
	V_MUL_F32_e32 v31, v27, v3                                                  ; 103E071B
	V_MAD_F32 v3, v27, v3, v31, 0, 0, 0, 0                                      ; D2820003 047E071B
	V_SUB_F32_e32 v3, s2, v3                                                    ; 08060602
	V_MAD_F32 v14, v14, -4.000000e+00, v25, 0, 0, 0, 0                          ; D282000E 0465EF0E
	V_MUL_F32_e32 v3, v3, v14                                                   ; 10061D03
	V_MUL_F32_e32 v8, v3, v8                                                    ; 10101103
	V_MUL_F32_e32 v25, v27, v2                                                  ; 1032051B
	V_MAD_F32 v2, v27, v2, v25, 0, 0, 0, 0                                      ; D2820002 0466051B
	V_SUB_F32_e32 v2, s3, v2                                                    ; 08040403
	V_MUL_F32_e32 v2, v2, v14                                                   ; 10041D02
	V_MAD_F32 v8, v2, v9, v8, 0, 0, 0, 0                                        ; D2820008 04221302
	V_MUL_F32_e32 v9, v27, v10                                                  ; 1012151B
	V_MAD_F32 v9, v27, v10, v9, 0, 0, 0, 0                                      ; D2820009 0426151B
	V_SUB_F32_e32 v9, s4, v9                                                    ; 08121204
	V_MUL_F32_e32 v9, v9, v14                                                   ; 10121D09
	V_MAD_F32 v5, v9, v5, v8, 0, 0, 0, 0                                        ; D2820005 04220B09
	V_CMP_GE_F32_e64 s[2:3], v5, 0.000000e+00, 0, 0, 0, 0                       ; D00C0002 02010105
	V_CNDMASK_B32_e64 v5, -nan, 1.401298e-45, s[2:3], 0, 0, 0, 0                ; D2000005 000902C1
	V_CVT_F32_I32_e32 v5, v5                                                    ; 7E0A0B05
	V_MAD_F32 v2, v2, v5, v7, 0, 0, 0, 0                                        ; D2820002 041E0B02
	V_MAD_F32 v7, v9, v5, v20, 0, 0, 0, 0                                       ; D2820007 04520B09
	V_ADD_F32_e64 v8, v7, 0, 0, 0, 0, 1                                         ; D2060008 22010107
	V_RCP_F32_e32 v8, v8                                                        ; 7E105508
	V_MUL_F32_e32 v2, v2, v8                                                    ; 10041102
	V_MUL_F32_e32 v2, s27, v2                                                   ; 1004041B
	V_SUBREV_F32_e32 v2, s26, v2                                                ; 0A04041A
	V_MAD_F32 v2, v2, -5.000000e-01, 5.000000e-01, 0, 0, 0, 0                   ; D2820002 03C1E302
	V_ADD_F32_e64 v10, 0, v2, 0, 1, 0, 0                                        ; D206080A 02020480
	V_MAD_F32 v2, v3, v5, v4, 0, 0, 0, 0                                        ; D2820002 04120B03
	V_MUL_F32_e32 v2, v2, v8                                                    ; 10041102
	V_MUL_F32_e32 v2, s29, v2                                                   ; 1004041D
	V_SUBREV_F32_e32 v2, s28, v2                                                ; 0A04041C
	V_MAD_F32 v2, v2, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0                    ; D2820002 03C1E102
	V_ADD_F32_e64 v9, 0, v2, 0, 1, 0, 0                                         ; D2060809 02020480
	IMAGE_SAMPLE v2, 1, 0, 0, 0, 0, 0, 0, 0, v[9:10], s[12:19], s[8:11]         ; F0800100 00430209
	S_WAITCNT vmcnt(0)                                                          ; BF8C0770
	V_ADD_F32_e64 v3, v2, 0, 1, 0, 0, 0                                         ; D2060103 02010102
	V_MUL_F32_e32 v3, s24, v3                                                   ; 10060618
	V_SUBREV_F32_e32 v3, s25, v3                                                ; 0A060619
	V_CMP_EQ_F32_e64 s[2:3], v3, 0.000000e+00, 0, 0, 0, 0                       ; D0040002 02010103
	V_CNDMASK_B32_e64 v4, 0.000000e+00, 1.401298e-45, s[2:3], 0, 0, 0, 0        ; D2000004 00090280
	V_CVT_F32_I32_e32 v4, v4                                                    ; 7E080B04
	V_SUB_F32_e32 v3, v3, v7                                                    ; 08060F03
	V_ADD_F32_e32 v5, v14, v14                                                  ; 060A1D0E
	V_CMP_GE_F32_e64 s[2:3], v3, v5, 0, 0, 0, 0                                 ; D00C0002 02020B03
	V_CNDMASK_B32_e64 v5, 0, -1, s[2:3], 0, 0, 0, 0                             ; D2000005 00098280
	V_AND_B32_e32 v5, 1065353216, v5                                            ; 360A0AF2
	V_ADD_F32_e32 v4, v5, v4                                                    ; 06080905
	V_CMP_LE_F32_e64 s[2:3], v2, 0.000000e+00, 0, 0, 0, 0                       ; D0060002 02010102
	V_CNDMASK_B32_e64 v2, 0, -1, s[2:3], 0, 0, 0, 0                             ; D2000002 00098280
	V_AND_B32_e32 v2, 1065353216, v2                                            ; 360404F2
	V_MAD_F32 v1, v2, v1, v4, 0, 0, 0, 0                                        ; D2820001 04120302
	V_ADD_F32_e64 v1, 0, v1, 0, 1, 0, 0                                         ; D2060801 02020280
	V_SUB_F32_e32 v2, 1.000000e+00, v1                                          ; 080402F2
	V_CMP_GE_F32_e64 s[2:3], v3, 0.000000e+00, 0, 0, 0, 0                       ; D00C0002 02010103
	V_CNDMASK_B32_e64 v3, 0, -1, s[2:3], 0, 0, 0, 0                             ; D2000003 00098280
	V_AND_B32_e32 v3, 1065353216, v3                                            ; 360606F2
	V_MAD_F32 v2, v3, v2, v12, 0, 0, 0, 0                                       ; D2820002 04320503
	V_ADD_F32_e32 v2, v6, v2                                                    ; 06040506
	V_ADD_F32_e32 v3, v18, v11                                                  ; 06061712
	V_ADD_F32_e32 v3, v3, v22                                                   ; 06062D03
	V_ADD_F32_e32 v3, v3, v24                                                   ; 06063103
	V_ADD_F32_e32 v4, v19, v16                                                  ; 06082113
	V_ADD_F32_e32 v4, v4, v15                                                   ; 06081F04
	V_ADD_F32_e32 v4, v4, v13                                                   ; 06081B04
	V_ADD_F32_e32 v3, v4, v3                                                    ; 06060704
	V_ADD_F32_e32 v4, v28, v26                                                  ; 0608351C
	V_ADD_F32_e32 v4, v4, v29                                                   ; 06083B04
	V_ADD_F32_e32 v4, v4, v30                                                   ; 06083D04
	V_ADD_F32_e32 v3, v3, v4                                                    ; 06060903
	V_ADD_F32_e32 v4, v21, v17                                                  ; 06082315
	V_ADD_F32_e32 v4, v4, v23                                                   ; 06082F04
	V_ADD_F32_e32 v1, v4, v1                                                    ; 06020304
	V_ADD_F32_e32 v1, v3, v1                                                    ; 06020303
	V_SUB_F32_e32 v1, 1.600000e+01, v1                                          ; 080202FF 41800000
	V_RCP_F32_e32 v1, v1                                                        ; 7E025501
	V_MUL_F32_e32 v4, v2, v1                                                    ; 10080302
	S_OR_B64 exec, exec, s[0:1]                                                 ; 88FE007E
	V_MUL_F32_e64 v0, v4, v0, 0, 0, 0, 0                                        ; D2100000 02020104
	V_ADD_F32_e64 v0, 0, v0, 0, 1, 0, 0                                         ; D2060800 02020080
	V_SUB_F32_e32 v0, 1.000000e+00, v0                                          ; 080000F2
	V_MUL_F32_e32 v0, v0, v0                                                    ; 10000100
	V_CVT_PKRTZ_F16_F32_e32 v0, 0.000000e+00, v0                                ; 5E000080
	V_CVT_PKRTZ_F16_F32_e64 v1, 0.000000e+00, 0.000000e+00, 0, 0, 0, 0          ; D25E0001 02010080
	EXP 15, 0, 1, 1, 1, v1, v0, v1, v0                                          ; F8001C0F 00010001
	S_ENDPGM                                                                    ; BF810000

VERT
DCL IN[0]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[19]
DCL CONST[0..1]
DCL TEMP[0..2], LOCAL
IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
  0: MOV TEMP[0].zw, IMM[0].yyxy
  1: MOV TEMP[0].xy, IN[0].xyxx
  2: MAD TEMP[1].xy, IN[0].zwww, CONST[0].xyyy, CONST[0].zwww
  3: MAD TEMP[2].xy, IN[0].zwww, CONST[1].xyyy, CONST[1].zwww
  4: MOV TEMP[1].zw, TEMP[2].yyxy
  5: MOV OUT[1], TEMP[1]
  6: MOV OUT[0], TEMP[0]
  7: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0)
  %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4)
  %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8)
  %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12)
  %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16)
  %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20)
  %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24)
  %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28)
  %20 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %21, i32 0, i32 %6)
  %23 = extractelement <4 x float> %22, i32 0
  %24 = extractelement <4 x float> %22, i32 1
  %25 = extractelement <4 x float> %22, i32 2
  %26 = extractelement <4 x float> %22, i32 3
  %27 = fmul float %25, %12
  %28 = fadd float %27, %14
  %29 = fmul float %26, %13
  %30 = fadd float %29, %15
  %31 = fmul float %25, %16
  %32 = fadd float %31, %18
  %33 = fmul float %26, %17
  %34 = fadd float %33, %19
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %28, float %30, float %32, float %34)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %23, float %24, float 0.000000e+00, float 1.000000e+00)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg6

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%23](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%11](align=8)(tbaa=!"const")
	S_WAITCNT 112
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 7; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR4<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 5; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR3, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 6; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 4; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR2, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 3; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR3, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 0; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR8<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR2, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 32, 0, 0, 0, %VGPR7<kill>, %VGPR6<kill>, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>
	S_WAITCNT 1807
	%VGPR4<def> = V_MOV_B32_e32 1.000000e+00, %EXEC<imp-use>
	%VGPR5<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR1, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_LOAD_DWORDX4 s[4:7], s[6:7], 0               ; C0820700
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	BUFFER_LOAD_FORMAT_XYZW v[0:3], s[4:7][v0] + 0 ; E00C2000 80010000
	S_LOAD_DWORDX4 s[0:3], s[0:1], 0               ; C0800100
	S_WAITCNT vmcnt(0) lgkmcnt(0)                  ; BF8C0070
	S_BUFFER_LOAD_DWORD s4, s[0:3], 7              ; C2020107
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v4, s4                           ; 7E080204
	S_BUFFER_LOAD_DWORD s4, s[0:3], 5              ; C2020105
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v5, s4                           ; 7E0A0204
	V_MAD_F32 v4, v3, v5, v4, 0, 0, 0, 0           ; D2820004 04120B03
	S_BUFFER_LOAD_DWORD s4, s[0:3], 6              ; C2020106
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v5, s4                           ; 7E0A0204
	S_BUFFER_LOAD_DWORD s4, s[0:3], 4              ; C2020104
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v6, s4                           ; 7E0C0204
	V_MAD_F32 v5, v2, v6, v5, 0, 0, 0, 0           ; D2820005 04160D02
	S_BUFFER_LOAD_DWORD s4, s[0:3], 3              ; C2020103
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v6, s4                           ; 7E0C0204
	S_BUFFER_LOAD_DWORD s4, s[0:3], 1              ; C2020101
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v7, s4                           ; 7E0E0204
	V_MAD_F32 v6, v3, v7, v6, 0, 0, 0, 0           ; D2820006 041A0F03
	S_BUFFER_LOAD_DWORD s4, s[0:3], 2              ; C2020102
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v7, s4                           ; 7E0E0204
	S_BUFFER_LOAD_DWORD s0, s[0:3], 0              ; C2000100
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v8, s0                           ; 7E100200
	V_MAD_F32 v7, v2, v8, v7, 0, 0, 0, 0           ; D2820007 041E1102
	EXP 15, 32, 0, 0, 0, v7, v6, v5, v4            ; F800020F 04050607
	S_WAITCNT expcnt(0)                            ; BF8C070F
	V_MOV_B32_e32 v4, 1.000000e+00                 ; 7E0802F2
	V_MOV_B32_e32 v5, 0.000000e+00                 ; 7E0A0280
	EXP 15, 12, 0, 1, 0, v0, v1, v5, v4            ; F80008CF 04050100
	S_ENDPGM                                       ; BF810000

FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL CONST[0..223]
DCL TEMP[0..11], LOCAL
IMM[0] FLT32 {   -1.0000,     0.0000,     1.0000,     0.0000}
  0: MAD TEMP[0], CONST[3].zwzw, IMM[0].xxyx, IN[0].xyxy
  1: MOV TEMP[1].xy, TEMP[0].xyyy
  2: TEX TEMP[1].w, TEMP[1], SAMP[0], 2D
  3: MOV TEMP[0].xy, TEMP[0].zwww
  4: TEX TEMP[0].w, TEMP[0], SAMP[0], 2D
  5: MAD TEMP[2], CONST[3].zwzw, IMM[0].zxxy, IN[0].xyxy
  6: MOV TEMP[3].xy, TEMP[2].xyyy
  7: TEX TEMP[3].w, TEMP[3], SAMP[0], 2D
  8: MOV TEMP[2].xy, TEMP[2].zwww
  9: TEX TEMP[2].w, TEMP[2], SAMP[0], 2D
 10: MOV TEMP[4].xy, IN[0].xyyy
 11: TEX TEMP[4].w, TEMP[4], SAMP[0], 2D
 12: MAD TEMP[5], CONST[3].zwzw, IMM[0].zyxz, IN[0].xyxy
 13: MOV TEMP[6].xy, TEMP[5].xyyy
 14: TEX TEMP[6].w, TEMP[6], SAMP[0], 2D
 15: MAD TEMP[7], CONST[3].zwzw, IMM[0].yzzz, IN[0].xyxy
 16: MOV TEMP[8].xy, TEMP[7].xyyy
 17: TEX TEMP[8].w, TEMP[8], SAMP[0], 2D
 18: MOV TEMP[7].xy, TEMP[7].zwww
 19: TEX TEMP[7].w, TEMP[7], SAMP[0], 2D
 20: MIN TEMP[9].x, TEMP[1].wwww, TEMP[2].wwww
 21: MIN TEMP[10].x, TEMP[0].wwww, TEMP[4].wwww
 22: MAX TEMP[0].x, TEMP[0].wwww, TEMP[4].wwww
 23: MAX TEMP[4].x, TEMP[3].wwww, TEMP[6].wwww
 24: MAX TEMP[11].x, TEMP[9].xxxx, TEMP[10].xxxx
 25: MIN TEMP[9].x, TEMP[9].xxxx, TEMP[10].xxxx
 26: MIN TEMP[3].x, TEMP[3].wwww, TEMP[6].wwww
 27: MAX TEMP[3].x, TEMP[9].xxxx, TEMP[3].xxxx
 28: MIN TEMP[6].x, TEMP[0].xxxx, TEMP[4].xxxx
 29: MAX TEMP[1].x, TEMP[1].wwww, TEMP[2].wwww
 30: MAX TEMP[0].x, TEMP[0].xxxx, TEMP[4].xxxx
 31: MIN TEMP[0].x, TEMP[1].xxxx, TEMP[0].xxxx
 32: MIN TEMP[1].x, TEMP[11].xxxx, TEMP[3].xxxx
 33: MIN TEMP[2].x, TEMP[0].xxxx, TEMP[6].xxxx
 34: MAX TEMP[0].x, TEMP[0].xxxx, TEMP[6].xxxx
 35: MAX TEMP[4].x, TEMP[1].xxxx, TEMP[2].xxxx
 36: MIN TEMP[1].x, TEMP[1].xxxx, TEMP[2].xxxx
 37: MOV TEMP[2].xy, TEMP[5].zwww
 38: TEX TEMP[2].w, TEMP[2], SAMP[0], 2D
 39: MAX TEMP[1].x, TEMP[1].xxxx, TEMP[2].wwww
 40: MIN TEMP[2].x, TEMP[0].xxxx, TEMP[1].xxxx
 41: MAX TEMP[3].x, TEMP[11].xxxx, TEMP[3].xxxx
 42: MAX TEMP[0].x, TEMP[0].xxxx, TEMP[1].xxxx
 43: MIN TEMP[0].x, TEMP[3].xxxx, TEMP[0].xxxx
 44: MIN TEMP[1].x, TEMP[0].xxxx, TEMP[4].xxxx
 45: MIN TEMP[3].x, TEMP[2].xxxx, TEMP[8].wwww
 46: MAX TEMP[1].x, TEMP[1].xxxx, TEMP[3].xxxx
 47: MOV TEMP[3].xyz, IMM[0].yyyy
 48: MAX TEMP[0].x, TEMP[0].xxxx, TEMP[4].xxxx
 49: MAX TEMP[2].x, TEMP[2].xxxx, TEMP[8].wwww
 50: MIN TEMP[0].x, TEMP[0].xxxx, TEMP[2].xxxx
 51: MAX TEMP[2].x, TEMP[1].xxxx, TEMP[7].wwww
 52: MIN TEMP[0].x, TEMP[0].xxxx, TEMP[2].xxxx
 53: MIN TEMP[1].x, TEMP[1].xxxx, TEMP[7].wwww
 54: MAX TEMP[0].x, TEMP[0].xxxx, TEMP[1].xxxx
 55: MOV TEMP[3].w, TEMP[0].xxxx
 56: MOV OUT[0], TEMP[3]
 57: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %21 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
  %22 = load <16 x i8> addrspace(2)* %21, !tbaa !0
  %23 = call float @llvm.SI.load.const(<16 x i8> %22, i32 56)
  %24 = call float @llvm.SI.load.const(<16 x i8> %22, i32 60)
  %25 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0
  %26 = load <32 x i8> addrspace(2)* %25, !tbaa !0
  %27 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0
  %28 = load <16 x i8> addrspace(2)* %27, !tbaa !0
  %29 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %4, <2 x i32> %6)
  %30 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %4, <2 x i32> %6)
  %31 = fmul float %23, -1.000000e+00
  %32 = fadd float %31, %29
  %33 = fmul float %24, -1.000000e+00
  %34 = fadd float %33, %30
  %35 = fmul float %23, 0.000000e+00
  %36 = fadd float %35, %29
  %37 = fmul float %24, -1.000000e+00
  %38 = fadd float %37, %30
  %39 = bitcast float %32 to i32
  %40 = bitcast float %34 to i32
  %41 = insertelement <2 x i32> undef, i32 %39, i32 0
  %42 = insertelement <2 x i32> %41, i32 %40, i32 1
  %43 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %42, <32 x i8> %26, <16 x i8> %28, i32 2)
  %44 = extractelement <4 x float> %43, i32 3
  %45 = bitcast float %36 to i32
  %46 = bitcast float %38 to i32
  %47 = insertelement <2 x i32> undef, i32 %45, i32 0
  %48 = insertelement <2 x i32> %47, i32 %46, i32 1
  %49 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %48, <32 x i8> %26, <16 x i8> %28, i32 2)
  %50 = extractelement <4 x float> %49, i32 3
  %51 = fmul float %23, 1.000000e+00
  %52 = fadd float %51, %29
  %53 = fmul float %24, -1.000000e+00
  %54 = fadd float %53, %30
  %55 = fmul float %23, -1.000000e+00
  %56 = fadd float %55, %29
  %57 = fmul float %24, 0.000000e+00
  %58 = fadd float %57, %30
  %59 = bitcast float %52 to i32
  %60 = bitcast float %54 to i32
  %61 = insertelement <2 x i32> undef, i32 %59, i32 0
  %62 = insertelement <2 x i32> %61, i32 %60, i32 1
  %63 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %62, <32 x i8> %26, <16 x i8> %28, i32 2)
  %64 = extractelement <4 x float> %63, i32 3
  %65 = bitcast float %56 to i32
  %66 = bitcast float %58 to i32
  %67 = insertelement <2 x i32> undef, i32 %65, i32 0
  %68 = insertelement <2 x i32> %67, i32 %66, i32 1
  %69 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %68, <32 x i8> %26, <16 x i8> %28, i32 2)
  %70 = extractelement <4 x float> %69, i32 3
  %71 = bitcast float %29 to i32
  %72 = bitcast float %30 to i32
  %73 = insertelement <2 x i32> undef, i32 %71, i32 0
  %74 = insertelement <2 x i32> %73, i32 %72, i32 1
  %75 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %74, <32 x i8> %26, <16 x i8> %28, i32 2)
  %76 = extractelement <4 x float> %75, i32 3
  %77 = fmul float %23, 1.000000e+00
  %78 = fadd float %77, %29
  %79 = fmul float %24, 0.000000e+00
  %80 = fadd float %79, %30
  %81 = fmul float %23, -1.000000e+00
  %82 = fadd float %81, %29
  %83 = fmul float %24, 1.000000e+00
  %84 = fadd float %83, %30
  %85 = bitcast float %78 to i32
  %86 = bitcast float %80 to i32
  %87 = insertelement <2 x i32> undef, i32 %85, i32 0
  %88 = insertelement <2 x i32> %87, i32 %86, i32 1
  %89 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %88, <32 x i8> %26, <16 x i8> %28, i32 2)
  %90 = extractelement <4 x float> %89, i32 3
  %91 = fmul float %23, 0.000000e+00
  %92 = fadd float %91, %29
  %93 = fmul float %24, 1.000000e+00
  %94 = fadd float %93, %30
  %95 = fmul float %23, 1.000000e+00
  %96 = fadd float %95, %29
  %97 = fmul float %24, 1.000000e+00
  %98 = fadd float %97, %30
  %99 = bitcast float %92 to i32
  %100 = bitcast float %94 to i32
  %101 = insertelement <2 x i32> undef, i32 %99, i32 0
  %102 = insertelement <2 x i32> %101, i32 %100, i32 1
  %103 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %102, <32 x i8> %26, <16 x i8> %28, i32 2)
  %104 = extractelement <4 x float> %103, i32 3
  %105 = bitcast float %96 to i32
  %106 = bitcast float %98 to i32
  %107 = insertelement <2 x i32> undef, i32 %105, i32 0
  %108 = insertelement <2 x i32> %107, i32 %106, i32 1
  %109 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %108, <32 x i8> %26, <16 x i8> %28, i32 2)
  %110 = extractelement <4 x float> %109, i32 3
  %111 = fcmp uge float %44, %70
  %112 = select i1 %111, float %70, float %44
  %113 = fcmp uge float %50, %76
  %114 = select i1 %113, float %76, float %50
  %115 = fcmp uge float %50, %76
  %116 = select i1 %115, float %50, float %76
  %117 = fcmp uge float %64, %90
  %118 = select i1 %117, float %64, float %90
  %119 = fcmp uge float %112, %114
  %120 = select i1 %119, float %112, float %114
  %121 = fcmp uge float %112, %114
  %122 = select i1 %121, float %114, float %112
  %123 = fcmp uge float %64, %90
  %124 = select i1 %123, float %90, float %64
  %125 = fcmp uge float %122, %124
  %126 = select i1 %125, float %122, float %124
  %127 = fcmp uge float %116, %118
  %128 = select i1 %127, float %118, float %116
  %129 = fcmp uge float %44, %70
  %130 = select i1 %129, float %44, float %70
  %131 = fcmp uge float %116, %118
  %132 = select i1 %131, float %116, float %118
  %133 = fcmp uge float %130, %132
  %134 = select i1 %133, float %132, float %130
  %135 = fcmp uge float %120, %126
  %136 = select i1 %135, float %126, float %120
  %137 = fcmp uge float %134, %128
  %138 = select i1 %137, float %128, float %134
  %139 = fcmp uge float %134, %128
  %140 = select i1 %139, float %134, float %128
  %141 = fcmp uge float %136, %138
  %142 = select i1 %141, float %136, float %138
  %143 = fcmp uge float %136, %138
  %144 = select i1 %143, float %138, float %136
  %145 = bitcast float %82 to i32
  %146 = bitcast float %84 to i32
  %147 = insertelement <2 x i32> undef, i32 %145, i32 0
  %148 = insertelement <2 x i32> %147, i32 %146, i32 1
  %149 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %148, <32 x i8> %26, <16 x i8> %28, i32 2)
  %150 = extractelement <4 x float> %149, i32 3
  %151 = fcmp uge float %144, %150
  %152 = select i1 %151, float %144, float %150
  %153 = fcmp uge float %140, %152
  %154 = select i1 %153, float %152, float %140
  %155 = fcmp uge float %120, %126
  %156 = select i1 %155, float %120, float %126
  %157 = fcmp uge float %140, %152
  %158 = select i1 %157, float %140, float %152
  %159 = fcmp uge float %156, %158
  %160 = select i1 %159, float %158, float %156
  %161 = fcmp uge float %160, %142
  %162 = select i1 %161, float %142, float %160
  %163 = fcmp uge float %154, %104
  %164 = select i1 %163, float %104, float %154
  %165 = fcmp uge float %162, %164
  %166 = select i1 %165, float %162, float %164
  %167 = fcmp uge float %160, %142
  %168 = select i1 %167, float %160, float %142
  %169 = fcmp uge float %154, %104
  %170 = select i1 %169, float %154, float %104
  %171 = fcmp uge float %168, %170
  %172 = select i1 %171, float %170, float %168
  %173 = fcmp uge float %166, %110
  %174 = select i1 %173, float %166, float %110
  %175 = fcmp uge float %172, %174
  %176 = select i1 %175, float %174, float %172
  %177 = fcmp uge float %166, %110
  %178 = select i1 %177, float %110, float %166
  %179 = fcmp uge float %176, %178
  %180 = select i1 %179, float %176, float %178
  %181 = call i32 @llvm.SI.packf16(float 0.000000e+00, float 0.000000e+00)
  %182 = bitcast i32 %181 to float
  %183 = call i32 @llvm.SI.packf16(float 0.000000e+00, float %180)
  %184 = bitcast i32 %183 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %182, float %184, float %182, float %184)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR7 in %vreg4, %VGPR0 in %vreg5, %VGPR1 in %vreg6

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR7 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR7
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-def>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%22](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 15; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MAD_F32 %SGPR0, 0.000000e+00, %VGPR3, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR4_VGPR5<imp-def>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11<kill>, 14; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR4<def> = V_ADD_F32_e32 %SGPR1, %VGPR2, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%30](align=8)(tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%27](tbaa=!"const")
	S_WAITCNT 127
	%VGPR0<def> = IMAGE_SAMPLE_V1_V2 8, 0, 0, 0, 0, 0, 0, 0, %VGPR4_VGPR5, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	%VGPR7<def> = V_SUBREV_F32_e32 %SGPR0, %VGPR3, %EXEC<imp-use>, %VGPR6_VGPR7<imp-def>
	%VGPR8<def> = V_MOV_B32_e32 %VGPR4, %EXEC<imp-use>, %VGPR8_VGPR9<imp-def>
	%VGPR9<def> = V_MOV_B32_e32 %VGPR5, %EXEC<imp-use>
	%VGPR9<def> = V_MOV_B32_e32 %VGPR7, %EXEC<imp-use>, %VGPR8_VGPR9<imp-def>
	%VGPR1<def> = IMAGE_SAMPLE_V1_V2 8, 0, 0, 0, 0, 0, 0, 0, %VGPR8_VGPR9<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	S_WAITCNT 1904
	%SGPR2_SGPR3<def> = V_CMP_U_F32_e64 %VGPR1, %VGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_GE_F32_e64 %VGPR1, %VGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_OR_B64 %SGPR4_SGPR5<kill>, %SGPR2_SGPR3<kill>
	%VGPR8<def> = V_CNDMASK_B32_e64 %VGPR0, %VGPR1, %SGPR2_SGPR3, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = IMAGE_SAMPLE_V1_V2 8, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %SGPR1, 0.000000e+00, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR6_VGPR7<imp-use,kill>, %VGPR6_VGPR7<imp-def>
	%VGPR10<def> = IMAGE_SAMPLE_V1_V2 8, 0, 0, 0, 0, 0, 0, 0, %VGPR6_VGPR7, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	S_WAITCNT 1904
	%SGPR4_SGPR5<def> = V_CMP_U_F32_e64 %VGPR10, %VGPR9, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %VGPR10, %VGPR9, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = S_OR_B64 %SGPR6_SGPR7<kill>, %SGPR4_SGPR5<kill>
	%VGPR11<def> = V_CNDMASK_B32_e64 %VGPR9, %VGPR10, %SGPR4_SGPR5, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_U_F32_e64 %VGPR11, %VGPR8, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR20_SGPR21<def> = V_CMP_GE_F32_e64 %VGPR11, %VGPR8, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = S_OR_B64 %SGPR20_SGPR21<kill>, %SGPR6_SGPR7<kill>
	%VGPR12<def> = V_CNDMASK_B32_e64 %VGPR8, %VGPR11, %SGPR6_SGPR7, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_SUBREV_F32_e32 %SGPR1<kill>, %VGPR2, %EXEC<imp-use>, %VGPR13_VGPR14<imp-def>
	%VGPR14<def> = V_MOV_B32_e32 %VGPR5, %EXEC<imp-use>, %VGPR13_VGPR14<imp-def>
	%VGPR15<def> = IMAGE_SAMPLE_V1_V2 8, 0, 0, 0, 0, 0, 0, 0, %VGPR13_VGPR14, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	%VGPR14<def> = V_MOV_B32_e32 %VGPR7, %EXEC<imp-use>, %VGPR13_VGPR14<imp-def>
	%VGPR16<def> = IMAGE_SAMPLE_V1_V2 8, 0, 0, 0, 0, 0, 0, 0, %VGPR13_VGPR14, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	S_WAITCNT 1904
	%SGPR20_SGPR21<def> = V_CMP_U_F32_e64 %VGPR16, %VGPR15, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR22_SGPR23<def> = V_CMP_GE_F32_e64 %VGPR16, %VGPR15, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR20_SGPR21<def> = S_OR_B64 %SGPR22_SGPR23<kill>, %SGPR20_SGPR21<kill>
	%VGPR17<def> = V_CNDMASK_B32_e64 %VGPR15, %VGPR16, %SGPR20_SGPR21, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR22_SGPR23<def> = V_CMP_U_F32_e64 %VGPR17, %VGPR12, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR24_SGPR25<def> = V_CMP_GE_F32_e64 %VGPR17, %VGPR12, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR22_SGPR23<def> = S_OR_B64 %SGPR24_SGPR25<kill>, %SGPR22_SGPR23<kill>
	%VGPR12<def> = V_CNDMASK_B32_e64 %VGPR17<kill>, %VGPR12<kill>, %SGPR22_SGPR23<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_CNDMASK_B32_e64 %VGPR11<kill>, %VGPR8<kill>, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_U_F32_e64 %VGPR12, %VGPR8, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR22_SGPR23<def> = V_CMP_GE_F32_e64 %VGPR12, %VGPR8, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = S_OR_B64 %SGPR22_SGPR23<kill>, %SGPR6_SGPR7<kill>
	%VGPR11<def> = V_CNDMASK_B32_e64 %VGPR12, %VGPR8, %SGPR6_SGPR7, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_CNDMASK_B32_e64 %VGPR10<kill>, %VGPR9<kill>, %SGPR4_SGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR10<def> = V_CNDMASK_B32_e64 %VGPR16<kill>, %VGPR15<kill>, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_U_F32_e64 %VGPR10, %VGPR9, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR20_SGPR21<def> = V_CMP_GE_F32_e64 %VGPR10, %VGPR9, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = S_OR_B64 %SGPR20_SGPR21<kill>, %SGPR4_SGPR5<kill>
	%VGPR15<def> = V_CNDMASK_B32_e64 %VGPR10, %VGPR9, %SGPR4_SGPR5, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_CNDMASK_B32_e64 %VGPR1<kill>, %VGPR0<kill>, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_U_F32_e64 %VGPR15, %VGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR20_SGPR21<def> = V_CMP_GE_F32_e64 %VGPR15, %VGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_OR_B64 %SGPR20_SGPR21<kill>, %SGPR2_SGPR3<kill>
	%VGPR0<def> = V_CNDMASK_B32_e64 %VGPR0<kill>, %VGPR15<kill>, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_CNDMASK_B32_e64 %VGPR9<kill>, %VGPR10<kill>, %SGPR4_SGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_U_F32_e64 %VGPR1, %VGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_GE_F32_e64 %VGPR1, %VGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_OR_B64 %SGPR4_SGPR5<kill>, %SGPR2_SGPR3<kill>
	%VGPR9<def> = V_CNDMASK_B32_e64 %VGPR1, %VGPR0, %SGPR2_SGPR3, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_U_F32_e64 %VGPR9, %VGPR11, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR20_SGPR21<def> = V_CMP_GE_F32_e64 %VGPR9, %VGPR11, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = S_OR_B64 %SGPR20_SGPR21<kill>, %SGPR4_SGPR5<kill>
	%VGPR10<def> = V_CNDMASK_B32_e64 %VGPR9, %VGPR11, %SGPR4_SGPR5, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR14<def> = V_ADD_F32_e32 %SGPR0<kill>, %VGPR3, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR13_VGPR14<imp-use,kill>, %VGPR13_VGPR14<imp-def>
	%VGPR2<def> = IMAGE_SAMPLE_V1_V2 8, 0, 0, 0, 0, 0, 0, 0, %VGPR13_VGPR14, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	S_WAITCNT 1904
	%SGPR0_SGPR1<def> = V_CMP_U_F32_e64 %VGPR10, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR20_SGPR21<def> = V_CMP_GE_F32_e64 %VGPR10, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_OR_B64 %SGPR20_SGPR21<kill>, %SGPR0_SGPR1<kill>
	%VGPR2<def> = V_CNDMASK_B32_e64 %VGPR2<kill>, %VGPR10<kill>, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_CNDMASK_B32_e64 %VGPR8<kill>, %VGPR12<kill>, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = V_CMP_U_F32_e64 %VGPR3, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %VGPR3, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_OR_B64 %SGPR6_SGPR7<kill>, %SGPR0_SGPR1<kill>
	%VGPR8<def> = V_CNDMASK_B32_e64 %VGPR2, %VGPR3, %SGPR0_SGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_CNDMASK_B32_e64 %VGPR0<kill>, %VGPR1<kill>, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_U_F32_e64 %VGPR0, %VGPR8, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %VGPR0, %VGPR8, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_OR_B64 %SGPR6_SGPR7<kill>, %SGPR2_SGPR3<kill>
	%VGPR0<def> = V_CNDMASK_B32_e64 %VGPR0<kill>, %VGPR8<kill>, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_CNDMASK_B32_e64 %VGPR11<kill>, %VGPR9<kill>, %SGPR4_SGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_U_F32_e64 %VGPR0, %VGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_GE_F32_e64 %VGPR0, %VGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_OR_B64 %SGPR4_SGPR5<kill>, %SGPR2_SGPR3<kill>
	%VGPR8<def> = V_CNDMASK_B32_e64 %VGPR0, %VGPR1, %SGPR2_SGPR3, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR2<def> = V_CNDMASK_B32_e64 %VGPR3<kill>, %VGPR2<kill>, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_MOV_B32_e32 %VGPR14, %EXEC<imp-use>, %VGPR6_VGPR7<imp-def>
	%VGPR3<def> = IMAGE_SAMPLE_V1_V2 8, 0, 0, 0, 0, 0, 0, 0, %VGPR6_VGPR7<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	S_WAITCNT 1904
	%SGPR0_SGPR1<def> = V_CMP_U_F32_e64 %VGPR2, %VGPR3, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_GE_F32_e64 %VGPR2, %VGPR3, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_OR_B64 %SGPR4_SGPR5<kill>, %SGPR0_SGPR1<kill>
	%VGPR6<def> = V_CNDMASK_B32_e64 %VGPR2, %VGPR3, %SGPR0_SGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_U_F32_e64 %VGPR8, %VGPR6, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %VGPR8, %VGPR6, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = S_OR_B64 %SGPR6_SGPR7<kill>, %SGPR4_SGPR5<kill>
	%VGPR6<def> = V_CNDMASK_B32_e64 %VGPR6<kill>, %VGPR8<kill>, %SGPR4_SGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_MOV_B32_e32 %VGPR14, %EXEC<imp-use>, %VGPR4_VGPR5<imp-def>
	%VGPR4<def> = IMAGE_SAMPLE_V1_V2 8, 0, 0, 0, 0, 0, 0, 0, %VGPR4_VGPR5<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%SGPR4_SGPR5<def> = V_CMP_U_F32_e64 %VGPR6, %VGPR4, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %VGPR6, %VGPR4, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = S_OR_B64 %SGPR6_SGPR7<kill>, %SGPR4_SGPR5<kill>
	%VGPR5<def> = V_CNDMASK_B32_e64 %VGPR4, %VGPR6, %SGPR4_SGPR5, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_CNDMASK_B32_e64 %VGPR1<kill>, %VGPR0<kill>, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_CNDMASK_B32_e64 %VGPR3<kill>, %VGPR2<kill>, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = V_CMP_U_F32_e64 %VGPR0, %VGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR0, %VGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_OR_B64 %SGPR2_SGPR3<kill>, %SGPR0_SGPR1<kill>
	%VGPR0<def> = V_CNDMASK_B32_e64 %VGPR0<kill>, %VGPR1<kill>, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = V_CMP_U_F32_e64 %VGPR0, %VGPR5, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR0, %VGPR5, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_OR_B64 %SGPR2_SGPR3<kill>, %SGPR0_SGPR1<kill>
	%VGPR0<def> = V_CNDMASK_B32_e64 %VGPR0<kill>, %VGPR5<kill>, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_CNDMASK_B32_e64 %VGPR6<kill>, %VGPR4<kill>, %SGPR4_SGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = V_CMP_U_F32_e64 %VGPR0, %VGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR0, %VGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_OR_B64 %SGPR2_SGPR3<kill>, %SGPR0_SGPR1<kill>
	%VGPR0<def> = V_CNDMASK_B32_e64 %VGPR1<kill>, %VGPR0<kill>, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 0.000000e+00, %VGPR0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_CVT_PKRTZ_F16_F32_e64 0.000000e+00, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR1<kill>, %VGPR0<kill>, %VGPR1, %VGPR0, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_WQM_B64 exec, exec                                                  ; BEFE0A7E
	S_MOV_B32 m0, s7                                                      ; BEFC0307
	V_INTERP_P1_F32 v3, v0, 1, 0, [m0]                                    ; C80C0100
	V_INTERP_P2_F32 v3, [v3], v1, 1, 0, [m0]                              ; C80D0101
	S_LOAD_DWORDX4 s[8:11], s[0:1], 0                                     ; C0840100
	S_WAITCNT lgkmcnt(0)                                                  ; BF8C007F
	S_BUFFER_LOAD_DWORD s0, s[8:11], 15                                   ; C200090F
	S_WAITCNT lgkmcnt(0)                                                  ; BF8C007F
	V_MAD_F32 v5, s0, 0.000000e+00, v3, 0, 0, 0, 0                        ; D2820005 040D0000
	V_INTERP_P1_F32 v2, v0, 0, 0, [m0]                                    ; C8080000
	V_INTERP_P2_F32 v2, [v2], v1, 0, 0, [m0]                              ; C8090001
	S_BUFFER_LOAD_DWORD s1, s[8:11], 14                                   ; C200890E
	S_WAITCNT lgkmcnt(0)                                                  ; BF8C007F
	V_ADD_F32_e32 v4, s1, v2                                              ; 06080401
	S_LOAD_DWORDX4 s[8:11], s[2:3], 0                                     ; C0840300
	S_LOAD_DWORDX8 s[12:19], s[4:5], 0                                    ; C0C60500
	S_WAITCNT lgkmcnt(0)                                                  ; BF8C007F
	IMAGE_SAMPLE v0, 8, 0, 0, 0, 0, 0, 0, 0, v[4:5], s[12:19], s[8:11]    ; F0800800 00430004
	V_SUBREV_F32_e32 v7, s0, v3                                           ; 0A0E0600
	V_MOV_B32_e32 v8, v4                                                  ; 7E100304
	V_MOV_B32_e32 v9, v5                                                  ; 7E120305
	V_MOV_B32_e32 v9, v7                                                  ; 7E120307
	IMAGE_SAMPLE v1, 8, 0, 0, 0, 0, 0, 0, 0, v[8:9], s[12:19], s[8:11]    ; F0800800 00430108
	S_WAITCNT vmcnt(0)                                                    ; BF8C0770
	V_CMP_U_F32_e64 s[2:3], v1, v0, 0, 0, 0, 0                            ; D0100002 02020101
	V_CMP_GE_F32_e64 s[4:5], v1, v0, 0, 0, 0, 0                           ; D00C0004 02020101
	S_OR_B64 s[2:3], s[4:5], s[2:3]                                       ; 88820204
	V_CNDMASK_B32_e64 v8, v0, v1, s[2:3], 0, 0, 0, 0                      ; D2000008 000A0300
	IMAGE_SAMPLE v9, 8, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[12:19], s[8:11]    ; F0800800 00430902
	V_MAD_F32 v6, s1, 0.000000e+00, v2, 0, 0, 0, 0                        ; D2820006 04090001
	IMAGE_SAMPLE v10, 8, 0, 0, 0, 0, 0, 0, 0, v[6:7], s[12:19], s[8:11]   ; F0800800 00430A06
	S_WAITCNT vmcnt(0)                                                    ; BF8C0770
	V_CMP_U_F32_e64 s[4:5], v10, v9, 0, 0, 0, 0                           ; D0100004 0202130A
	V_CMP_GE_F32_e64 s[6:7], v10, v9, 0, 0, 0, 0                          ; D00C0006 0202130A
	S_OR_B64 s[4:5], s[6:7], s[4:5]                                       ; 88840406
	V_CNDMASK_B32_e64 v11, v9, v10, s[4:5], 0, 0, 0, 0                    ; D200000B 00121509
	V_CMP_U_F32_e64 s[6:7], v11, v8, 0, 0, 0, 0                           ; D0100006 0202110B
	V_CMP_GE_F32_e64 s[20:21], v11, v8, 0, 0, 0, 0                        ; D00C0014 0202110B
	S_OR_B64 s[6:7], s[20:21], s[6:7]                                     ; 88860614
	V_CNDMASK_B32_e64 v12, v8, v11, s[6:7], 0, 0, 0, 0                    ; D200000C 001A1708
	V_SUBREV_F32_e32 v13, s1, v2                                          ; 0A1A0401
	V_MOV_B32_e32 v14, v5                                                 ; 7E1C0305
	IMAGE_SAMPLE v15, 8, 0, 0, 0, 0, 0, 0, 0, v[13:14], s[12:19], s[8:11] ; F0800800 00430F0D
	V_MOV_B32_e32 v14, v7                                                 ; 7E1C0307
	IMAGE_SAMPLE v16, 8, 0, 0, 0, 0, 0, 0, 0, v[13:14], s[12:19], s[8:11] ; F0800800 0043100D
	S_WAITCNT vmcnt(0)                                                    ; BF8C0770
	V_CMP_U_F32_e64 s[20:21], v16, v15, 0, 0, 0, 0                        ; D0100014 02021F10
	V_CMP_GE_F32_e64 s[22:23], v16, v15, 0, 0, 0, 0                       ; D00C0016 02021F10
	S_OR_B64 s[20:21], s[22:23], s[20:21]                                 ; 88941416
	V_CNDMASK_B32_e64 v17, v15, v16, s[20:21], 0, 0, 0, 0                 ; D2000011 0052210F
	V_CMP_U_F32_e64 s[22:23], v17, v12, 0, 0, 0, 0                        ; D0100016 02021911
	V_CMP_GE_F32_e64 s[24:25], v17, v12, 0, 0, 0, 0                       ; D00C0018 02021911
	S_OR_B64 s[22:23], s[24:25], s[22:23]                                 ; 88961618
	V_CNDMASK_B32_e64 v12, v17, v12, s[22:23], 0, 0, 0, 0                 ; D200000C 005A1911
	V_CNDMASK_B32_e64 v8, v11, v8, s[6:7], 0, 0, 0, 0                     ; D2000008 001A110B
	V_CMP_U_F32_e64 s[6:7], v12, v8, 0, 0, 0, 0                           ; D0100006 0202110C
	V_CMP_GE_F32_e64 s[22:23], v12, v8, 0, 0, 0, 0                        ; D00C0016 0202110C
	S_OR_B64 s[6:7], s[22:23], s[6:7]                                     ; 88860616
	V_CNDMASK_B32_e64 v11, v12, v8, s[6:7], 0, 0, 0, 0                    ; D200000B 001A110C
	V_CNDMASK_B32_e64 v9, v10, v9, s[4:5], 0, 0, 0, 0                     ; D2000009 0012130A
	V_CNDMASK_B32_e64 v10, v16, v15, s[20:21], 0, 0, 0, 0                 ; D200000A 00521F10
	V_CMP_U_F32_e64 s[4:5], v10, v9, 0, 0, 0, 0                           ; D0100004 0202130A
	V_CMP_GE_F32_e64 s[20:21], v10, v9, 0, 0, 0, 0                        ; D00C0014 0202130A
	S_OR_B64 s[4:5], s[20:21], s[4:5]                                     ; 88840414
	V_CNDMASK_B32_e64 v15, v10, v9, s[4:5], 0, 0, 0, 0                    ; D200000F 0012130A
	V_CNDMASK_B32_e64 v0, v1, v0, s[2:3], 0, 0, 0, 0                      ; D2000000 000A0101
	V_CMP_U_F32_e64 s[2:3], v15, v0, 0, 0, 0, 0                           ; D0100002 0202010F
	V_CMP_GE_F32_e64 s[20:21], v15, v0, 0, 0, 0, 0                        ; D00C0014 0202010F
	S_OR_B64 s[2:3], s[20:21], s[2:3]                                     ; 88820214
	V_CNDMASK_B32_e64 v0, v0, v15, s[2:3], 0, 0, 0, 0                     ; D2000000 000A1F00
	V_CNDMASK_B32_e64 v1, v9, v10, s[4:5], 0, 0, 0, 0                     ; D2000001 00121509
	V_CMP_U_F32_e64 s[2:3], v1, v0, 0, 0, 0, 0                            ; D0100002 02020101
	V_CMP_GE_F32_e64 s[4:5], v1, v0, 0, 0, 0, 0                           ; D00C0004 02020101
	S_OR_B64 s[2:3], s[4:5], s[2:3]                                       ; 88820204
	V_CNDMASK_B32_e64 v9, v1, v0, s[2:3], 0, 0, 0, 0                      ; D2000009 000A0101
	V_CMP_U_F32_e64 s[4:5], v9, v11, 0, 0, 0, 0                           ; D0100004 02021709
	V_CMP_GE_F32_e64 s[20:21], v9, v11, 0, 0, 0, 0                        ; D00C0014 02021709
	S_OR_B64 s[4:5], s[20:21], s[4:5]                                     ; 88840414
	V_CNDMASK_B32_e64 v10, v9, v11, s[4:5], 0, 0, 0, 0                    ; D200000A 00121709
	V_ADD_F32_e32 v14, s0, v3                                             ; 061C0600
	IMAGE_SAMPLE v2, 8, 0, 0, 0, 0, 0, 0, 0, v[13:14], s[12:19], s[8:11]  ; F0800800 0043020D
	S_WAITCNT vmcnt(0)                                                    ; BF8C0770
	V_CMP_U_F32_e64 s[0:1], v10, v2, 0, 0, 0, 0                           ; D0100000 0202050A
	V_CMP_GE_F32_e64 s[20:21], v10, v2, 0, 0, 0, 0                        ; D00C0014 0202050A
	S_OR_B64 s[0:1], s[20:21], s[0:1]                                     ; 88800014
	V_CNDMASK_B32_e64 v2, v2, v10, s[0:1], 0, 0, 0, 0                     ; D2000002 00021502
	V_CNDMASK_B32_e64 v3, v8, v12, s[6:7], 0, 0, 0, 0                     ; D2000003 001A1908
	V_CMP_U_F32_e64 s[0:1], v3, v2, 0, 0, 0, 0                            ; D0100000 02020503
	V_CMP_GE_F32_e64 s[6:7], v3, v2, 0, 0, 0, 0                           ; D00C0006 02020503
	S_OR_B64 s[0:1], s[6:7], s[0:1]                                       ; 88800006
	V_CNDMASK_B32_e64 v8, v2, v3, s[0:1], 0, 0, 0, 0                      ; D2000008 00020702
	V_CNDMASK_B32_e64 v0, v0, v1, s[2:3], 0, 0, 0, 0                      ; D2000000 000A0300
	V_CMP_U_F32_e64 s[2:3], v0, v8, 0, 0, 0, 0                            ; D0100002 02021100
	V_CMP_GE_F32_e64 s[6:7], v0, v8, 0, 0, 0, 0                           ; D00C0006 02021100
	S_OR_B64 s[2:3], s[6:7], s[2:3]                                       ; 88820206
	V_CNDMASK_B32_e64 v0, v0, v8, s[2:3], 0, 0, 0, 0                      ; D2000000 000A1100
	V_CNDMASK_B32_e64 v1, v11, v9, s[4:5], 0, 0, 0, 0                     ; D2000001 0012130B
	V_CMP_U_F32_e64 s[2:3], v0, v1, 0, 0, 0, 0                            ; D0100002 02020300
	V_CMP_GE_F32_e64 s[4:5], v0, v1, 0, 0, 0, 0                           ; D00C0004 02020300
	S_OR_B64 s[2:3], s[4:5], s[2:3]                                       ; 88820204
	V_CNDMASK_B32_e64 v8, v0, v1, s[2:3], 0, 0, 0, 0                      ; D2000008 000A0300
	V_CNDMASK_B32_e64 v2, v3, v2, s[0:1], 0, 0, 0, 0                      ; D2000002 00020503
	V_MOV_B32_e32 v7, v14                                                 ; 7E0E030E
	IMAGE_SAMPLE v3, 8, 0, 0, 0, 0, 0, 0, 0, v[6:7], s[12:19], s[8:11]    ; F0800800 00430306
	S_WAITCNT vmcnt(0)                                                    ; BF8C0770
	V_CMP_U_F32_e64 s[0:1], v2, v3, 0, 0, 0, 0                            ; D0100000 02020702
	V_CMP_GE_F32_e64 s[4:5], v2, v3, 0, 0, 0, 0                           ; D00C0004 02020702
	S_OR_B64 s[0:1], s[4:5], s[0:1]                                       ; 88800004
	V_CNDMASK_B32_e64 v6, v2, v3, s[0:1], 0, 0, 0, 0                      ; D2000006 00020702
	V_CMP_U_F32_e64 s[4:5], v8, v6, 0, 0, 0, 0                            ; D0100004 02020D08
	V_CMP_GE_F32_e64 s[6:7], v8, v6, 0, 0, 0, 0                           ; D00C0006 02020D08
	S_OR_B64 s[4:5], s[6:7], s[4:5]                                       ; 88840406
	V_CNDMASK_B32_e64 v6, v6, v8, s[4:5], 0, 0, 0, 0                      ; D2000006 00121106
	V_MOV_B32_e32 v5, v14                                                 ; 7E0A030E
	IMAGE_SAMPLE v4, 8, 0, 0, 0, 0, 0, 0, 0, v[4:5], s[12:19], s[8:11]    ; F0800800 00430404
	S_WAITCNT vmcnt(0)                                                    ; BF8C0770
	V_CMP_U_F32_e64 s[4:5], v6, v4, 0, 0, 0, 0                            ; D0100004 02020906
	V_CMP_GE_F32_e64 s[6:7], v6, v4, 0, 0, 0, 0                           ; D00C0006 02020906
	S_OR_B64 s[4:5], s[6:7], s[4:5]                                       ; 88840406
	V_CNDMASK_B32_e64 v5, v4, v6, s[4:5], 0, 0, 0, 0                      ; D2000005 00120D04
	V_CNDMASK_B32_e64 v0, v1, v0, s[2:3], 0, 0, 0, 0                      ; D2000000 000A0101
	V_CNDMASK_B32_e64 v1, v3, v2, s[0:1], 0, 0, 0, 0                      ; D2000001 00020503
	V_CMP_U_F32_e64 s[0:1], v0, v1, 0, 0, 0, 0                            ; D0100000 02020300
	V_CMP_GE_F32_e64 s[2:3], v0, v1, 0, 0, 0, 0                           ; D00C0002 02020300
	S_OR_B64 s[0:1], s[2:3], s[0:1]                                       ; 88800002
	V_CNDMASK_B32_e64 v0, v0, v1, s[0:1], 0, 0, 0, 0                      ; D2000000 00020300
	V_CMP_U_F32_e64 s[0:1], v0, v5, 0, 0, 0, 0                            ; D0100000 02020B00
	V_CMP_GE_F32_e64 s[2:3], v0, v5, 0, 0, 0, 0                           ; D00C0002 02020B00
	S_OR_B64 s[0:1], s[2:3], s[0:1]                                       ; 88800002
	V_CNDMASK_B32_e64 v0, v0, v5, s[0:1], 0, 0, 0, 0                      ; D2000000 00020B00
	V_CNDMASK_B32_e64 v1, v6, v4, s[4:5], 0, 0, 0, 0                      ; D2000001 00120906
	V_CMP_U_F32_e64 s[0:1], v0, v1, 0, 0, 0, 0                            ; D0100000 02020300
	V_CMP_GE_F32_e64 s[2:3], v0, v1, 0, 0, 0, 0                           ; D00C0002 02020300
	S_OR_B64 s[0:1], s[2:3], s[0:1]                                       ; 88800002
	V_CNDMASK_B32_e64 v0, v1, v0, s[0:1], 0, 0, 0, 0                      ; D2000000 00020101
	V_CVT_PKRTZ_F16_F32_e32 v0, 0.000000e+00, v0                          ; 5E000080
	V_CVT_PKRTZ_F16_F32_e64 v1, 0.000000e+00, 0.000000e+00, 0, 0, 0, 0    ; D25E0001 02010080
	EXP 15, 0, 1, 1, 1, v1, v0, v1, v0                                    ; F8001C0F 00010001
	S_ENDPGM                                                              ; BF810000

VERT
DCL IN[0]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[19]
DCL CONST[0..1]
DCL TEMP[0..2], LOCAL
IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
  0: MOV TEMP[0].zw, IMM[0].yyxy
  1: MOV TEMP[0].xy, IN[0].xyxx
  2: MAD TEMP[1].xy, IN[0].zwww, CONST[0].xyyy, CONST[0].zwww
  3: MAD TEMP[2].xy, IN[0].zwww, CONST[1].xyyy, CONST[1].zwww
  4: MOV TEMP[1].zw, TEMP[2].yyxy
  5: MOV OUT[1], TEMP[1]
  6: MOV OUT[0], TEMP[0]
  7: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0)
  %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4)
  %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8)
  %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12)
  %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16)
  %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20)
  %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24)
  %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28)
  %20 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %21, i32 0, i32 %6)
  %23 = extractelement <4 x float> %22, i32 0
  %24 = extractelement <4 x float> %22, i32 1
  %25 = extractelement <4 x float> %22, i32 2
  %26 = extractelement <4 x float> %22, i32 3
  %27 = fmul float %25, %12
  %28 = fadd float %27, %14
  %29 = fmul float %26, %13
  %30 = fadd float %29, %15
  %31 = fmul float %25, %16
  %32 = fadd float %31, %18
  %33 = fmul float %26, %17
  %34 = fadd float %33, %19
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %28, float %30, float %32, float %34)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %23, float %24, float 0.000000e+00, float 1.000000e+00)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg6

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%23](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%11](align=8)(tbaa=!"const")
	S_WAITCNT 112
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 7; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR4<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 5; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR3, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 6; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 4; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR2, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 3; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR3, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 0; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR8<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR2, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 32, 0, 0, 0, %VGPR7<kill>, %VGPR6<kill>, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>
	S_WAITCNT 1807
	%VGPR4<def> = V_MOV_B32_e32 1.000000e+00, %EXEC<imp-use>
	%VGPR5<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR1, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_LOAD_DWORDX4 s[4:7], s[6:7], 0               ; C0820700
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	BUFFER_LOAD_FORMAT_XYZW v[0:3], s[4:7][v0] + 0 ; E00C2000 80010000
	S_LOAD_DWORDX4 s[0:3], s[0:1], 0               ; C0800100
	S_WAITCNT vmcnt(0) lgkmcnt(0)                  ; BF8C0070
	S_BUFFER_LOAD_DWORD s4, s[0:3], 7              ; C2020107
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v4, s4                           ; 7E080204
	S_BUFFER_LOAD_DWORD s4, s[0:3], 5              ; C2020105
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v5, s4                           ; 7E0A0204
	V_MAD_F32 v4, v3, v5, v4, 0, 0, 0, 0           ; D2820004 04120B03
	S_BUFFER_LOAD_DWORD s4, s[0:3], 6              ; C2020106
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v5, s4                           ; 7E0A0204
	S_BUFFER_LOAD_DWORD s4, s[0:3], 4              ; C2020104
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v6, s4                           ; 7E0C0204
	V_MAD_F32 v5, v2, v6, v5, 0, 0, 0, 0           ; D2820005 04160D02
	S_BUFFER_LOAD_DWORD s4, s[0:3], 3              ; C2020103
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v6, s4                           ; 7E0C0204
	S_BUFFER_LOAD_DWORD s4, s[0:3], 1              ; C2020101
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v7, s4                           ; 7E0E0204
	V_MAD_F32 v6, v3, v7, v6, 0, 0, 0, 0           ; D2820006 041A0F03
	S_BUFFER_LOAD_DWORD s4, s[0:3], 2              ; C2020102
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v7, s4                           ; 7E0E0204
	S_BUFFER_LOAD_DWORD s0, s[0:3], 0              ; C2000100
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v8, s0                           ; 7E100200
	V_MAD_F32 v7, v2, v8, v7, 0, 0, 0, 0           ; D2820007 041E1102
	EXP 15, 32, 0, 0, 0, v7, v6, v5, v4            ; F800020F 04050607
	S_WAITCNT expcnt(0)                            ; BF8C070F
	V_MOV_B32_e32 v4, 1.000000e+00                 ; 7E0802F2
	V_MOV_B32_e32 v5, 0.000000e+00                 ; 7E0A0280
	EXP 15, 12, 0, 1, 0, v0, v1, v5, v4            ; F80008CF 04050100
	S_ENDPGM                                       ; BF810000

FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL SAMP[1]
DCL CONST[0..3]
DCL TEMP[0..9], LOCAL
IMM[0] FLT32 {    0.0000,     0.9500,     1.0000,     0.2955}
IMM[1] FLT32 {   -1.5000,     1.5000,    -1.0000,     1.0000}
IMM[2] FLT32 {   -2.0000,     2.0000,     0.2246,     0.0986}
  0: MOV TEMP[0].xyz, IMM[0].xxxx
  1: MOV TEMP[1].xy, IN[0].xyyy
  2: TEX TEMP[1].w, TEMP[1], SAMP[1], 2D
  3: MOV TEMP[0].w, TEMP[1].wwww
  4: MOV TEMP[2].xy, IN[0].zwww
  5: TEX TEMP[2].x, TEMP[2], SAMP[0], 2D
  6: FSLT TEMP[3].x, IMM[0].yyyy, TEMP[2].xxxx
  7: UIF TEMP[3].xxxx :0
  8:   MOV TEMP[3], TEMP[0]
  9: ELSE :0
 10:   ABS TEMP[4].x, TEMP[2].xxxx
 11:   MAD TEMP[4].x, TEMP[4].xxxx, CONST[1].yyyy, -CONST[1].xxxx
 12:   ADD TEMP[5].x, -TEMP[4].xxxx, -CONST[3].xxxx
 13:   MUL_SAT TEMP[5].x, TEMP[5].xxxx, CONST[3].wwww
 14:   MAD TEMP[5].x, CONST[3].zzzz, TEMP[5].xxxx, IMM[0].zzzz
 15:   MUL_SAT TEMP[6].x, -TEMP[4].xxxx, CONST[3].yyyy
 16:   MUL TEMP[5].x, TEMP[5].xxxx, TEMP[6].xxxx
 17:   FSLT TEMP[2].x, TEMP[2].xxxx, IMM[0].xxxx
 18:   UIF TEMP[2].xxxx :0
 19:     MOV TEMP[2].x, CONST[0].yyyy
 20:   ELSE :0
 21:     MOV TEMP[2].x, TEMP[5].xxxx
 22:   ENDIF
 23:   MUL TEMP[2].x, TEMP[2].xxxx, CONST[0].zzzz
 24:   MUL TEMP[2].x, CONST[0].xxxx, TEMP[2].xxxx
 25:   MUL TEMP[5].x, TEMP[1].wwww, IMM[0].wwww
 26:   MAD TEMP[6], CONST[2].xyxy, IMM[1].xxyy, IN[0].xyxy
 27:   MAD TEMP[7], CONST[2].zwzw, IMM[1].zzww, IN[0].zwzw
 28:   MAD TEMP[8], CONST[2].zwzw, IMM[2].xxyy, IN[0].zwzw
 29:   MOV TEMP[9].xy, TEMP[7].xyyy
 30:   TEX TEMP[9].x, TEMP[9], SAMP[0], 2D
 31:   MOV TEMP[9].x, TEMP[9].xxxx
 32:   MOV TEMP[7].xy, TEMP[7].zwww
 33:   TEX TEMP[7].x, TEMP[7], SAMP[0], 2D
 34:   MOV TEMP[9].y, TEMP[7].xxxx
 35:   MOV TEMP[7].xy, TEMP[8].xyyy
 36:   TEX TEMP[7].x, TEMP[7], SAMP[0], 2D
 37:   MOV TEMP[9].z, TEMP[7].xxxx
 38:   MOV TEMP[7].xy, TEMP[8].zwww
 39:   TEX TEMP[7].x, TEMP[7], SAMP[0], 2D
 40:   MOV TEMP[9].w, TEMP[7].xxxx
 41:   MOV TEMP[7].xy, TEMP[6].xyyy
 42:   TEX TEMP[7].w, TEMP[7], SAMP[1], 2D
 43:   MOV TEMP[7].x, TEMP[7].wwww
 44:   MOV TEMP[6].xy, TEMP[6].zwww
 45:   TEX TEMP[6].w, TEMP[6], SAMP[1], 2D
 46:   MOV TEMP[7].y, TEMP[6].wwww
 47:   ABS TEMP[6], TEMP[9]
 48:   MAD TEMP[6], TEMP[6], CONST[1].yyyy, -CONST[1].xxxx
 49:   ADD TEMP[4], TEMP[6], -TEMP[4].xxxx
 50:   ABS TEMP[4], TEMP[4]
 51:   FSGE TEMP[6].x, TEMP[4].xxxx, TEMP[2].xxxx
 52:   UIF TEMP[6].xxxx :0
 53:     MOV TEMP[6].x, IMM[0].xxxx
 54:   ELSE :0
 55:     MOV TEMP[6].x, IMM[2].zzzz
 56:   ENDIF
 57:   MOV TEMP[6].x, TEMP[6].xxxx
 58:   FSGE TEMP[8].x, TEMP[4].yyyy, TEMP[2].xxxx
 59:   UIF TEMP[8].xxxx :0
 60:     MOV TEMP[8].x, IMM[0].xxxx
 61:   ELSE :0
 62:     MOV TEMP[8].x, IMM[2].zzzz
 63:   ENDIF
 64:   MOV TEMP[6].y, TEMP[8].xxxx
 65:   FSGE TEMP[8].x, TEMP[4].zzzz, TEMP[2].xxxx
 66:   UIF TEMP[8].xxxx :0
 67:     MOV TEMP[8].x, IMM[0].xxxx
 68:   ELSE :0
 69:     MOV TEMP[8].x, IMM[2].wwww
 70:   ENDIF
 71:   MOV TEMP[6].z, TEMP[8].xxxx
 72:   FSGE TEMP[2].x, TEMP[4].wwww, TEMP[2].xxxx
 73:   UIF TEMP[2].xxxx :0
 74:     MOV TEMP[2].x, IMM[0].xxxx
 75:   ELSE :0
 76:     MOV TEMP[2].x, IMM[2].wwww
 77:   ENDIF
 78:   MOV TEMP[6].w, TEMP[2].xxxx
 79:   DP4 TEMP[2].x, TEMP[7].xyxy, TEMP[6]
 80:   ADD TEMP[2].x, TEMP[5].xxxx, TEMP[2].xxxx
 81:   ADD TEMP[1], IMM[0].wxxx, TEMP[6]
 82:   DP4 TEMP[1].x, TEMP[1], IMM[0].zzzz
 83:   RCP TEMP[1].x, TEMP[1].xxxx
 84:   MUL TEMP[1].x, TEMP[2].xxxx, TEMP[1].xxxx
 85:   MOV TEMP[0].w, TEMP[1].xxxx
 86:   MOV TEMP[3], TEMP[0]
 87: ENDIF
 88: MOV OUT[0], TEMP[3]
 89: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %21 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
  %22 = load <16 x i8> addrspace(2)* %21, !tbaa !0
  %23 = call float @llvm.SI.load.const(<16 x i8> %22, i32 0)
  %24 = call float @llvm.SI.load.const(<16 x i8> %22, i32 4)
  %25 = call float @llvm.SI.load.const(<16 x i8> %22, i32 8)
  %26 = call float @llvm.SI.load.const(<16 x i8> %22, i32 16)
  %27 = call float @llvm.SI.load.const(<16 x i8> %22, i32 20)
  %28 = call float @llvm.SI.load.const(<16 x i8> %22, i32 32)
  %29 = call float @llvm.SI.load.const(<16 x i8> %22, i32 36)
  %30 = call float @llvm.SI.load.const(<16 x i8> %22, i32 40)
  %31 = call float @llvm.SI.load.const(<16 x i8> %22, i32 44)
  %32 = call float @llvm.SI.load.const(<16 x i8> %22, i32 48)
  %33 = call float @llvm.SI.load.const(<16 x i8> %22, i32 52)
  %34 = call float @llvm.SI.load.const(<16 x i8> %22, i32 56)
  %35 = call float @llvm.SI.load.const(<16 x i8> %22, i32 60)
  %36 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0
  %37 = load <32 x i8> addrspace(2)* %36, !tbaa !0
  %38 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0
  %39 = load <16 x i8> addrspace(2)* %38, !tbaa !0
  %40 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 1
  %41 = load <32 x i8> addrspace(2)* %40, !tbaa !0
  %42 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 1
  %43 = load <16 x i8> addrspace(2)* %42, !tbaa !0
  %44 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %4, <2 x i32> %6)
  %45 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %4, <2 x i32> %6)
  %46 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %4, <2 x i32> %6)
  %47 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %4, <2 x i32> %6)
  %48 = bitcast float %44 to i32
  %49 = bitcast float %45 to i32
  %50 = insertelement <2 x i32> undef, i32 %48, i32 0
  %51 = insertelement <2 x i32> %50, i32 %49, i32 1
  %52 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %51, <32 x i8> %41, <16 x i8> %43, i32 2)
  %53 = extractelement <4 x float> %52, i32 3
  %54 = bitcast float %46 to i32
  %55 = bitcast float %47 to i32
  %56 = insertelement <2 x i32> undef, i32 %54, i32 0
  %57 = insertelement <2 x i32> %56, i32 %55, i32 1
  %58 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %57, <32 x i8> %37, <16 x i8> %39, i32 2)
  %59 = extractelement <4 x float> %58, i32 0
  %60 = fcmp olt float 0x3FEE666660000000, %59
  %61 = sext i1 %60 to i32
  %62 = bitcast i32 %61 to float
  %63 = bitcast float %62 to i32
  %64 = icmp ne i32 %63, 0
  br i1 %64, label %ENDIF, label %ELSE

ELSE:                                             ; preds = %main_body
  %65 = call float @fabs(float %59)
  %66 = fsub float -0.000000e+00, %26
  %67 = fmul float %65, %27
  %68 = fadd float %67, %66
  %69 = fsub float -0.000000e+00, %68
  %70 = fsub float -0.000000e+00, %32
  %71 = fadd float %69, %70
  %72 = fmul float %71, %35
  %73 = call float @llvm.AMDIL.clamp.(float %72, float 0.000000e+00, float 1.000000e+00)
  %74 = fmul float %34, %73
  %75 = fadd float %74, 1.000000e+00
  %76 = fsub float -0.000000e+00, %68
  %77 = fmul float %76, %33
  %78 = call float @llvm.AMDIL.clamp.(float %77, float 0.000000e+00, float 1.000000e+00)
  %79 = fmul float %75, %78
  %80 = fcmp olt float %59, 0.000000e+00
  %81 = sext i1 %80 to i32
  %82 = bitcast i32 %81 to float
  %83 = bitcast float %82 to i32
  %84 = icmp ne i32 %83, 0
  %. = select i1 %84, float %24, float %79
  %85 = fmul float %., %25
  %86 = fmul float %23, %85
  %87 = fmul float %53, 0x3FD2E9AF60000000
  %88 = fmul float %28, -1.500000e+00
  %89 = fadd float %88, %44
  %90 = fmul float %29, -1.500000e+00
  %91 = fadd float %90, %45
  %92 = fmul float %28, 1.500000e+00
  %93 = fadd float %92, %44
  %94 = fmul float %29, 1.500000e+00
  %95 = fadd float %94, %45
  %96 = fmul float %30, -1.000000e+00
  %97 = fadd float %96, %46
  %98 = fmul float %31, -1.000000e+00
  %99 = fadd float %98, %47
  %100 = fmul float %30, 1.000000e+00
  %101 = fadd float %100, %46
  %102 = fmul float %31, 1.000000e+00
  %103 = fadd float %102, %47
  %104 = fmul float %30, -2.000000e+00
  %105 = fadd float %104, %46
  %106 = fmul float %31, -2.000000e+00
  %107 = fadd float %106, %47
  %108 = fmul float %30, 2.000000e+00
  %109 = fadd float %108, %46
  %110 = fmul float %31, 2.000000e+00
  %111 = fadd float %110, %47
  %112 = bitcast float %97 to i32
  %113 = bitcast float %99 to i32
  %114 = insertelement <2 x i32> undef, i32 %112, i32 0
  %115 = insertelement <2 x i32> %114, i32 %113, i32 1
  %116 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %115, <32 x i8> %37, <16 x i8> %39, i32 2)
  %117 = extractelement <4 x float> %116, i32 0
  %118 = bitcast float %101 to i32
  %119 = bitcast float %103 to i32
  %120 = insertelement <2 x i32> undef, i32 %118, i32 0
  %121 = insertelement <2 x i32> %120, i32 %119, i32 1
  %122 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %121, <32 x i8> %37, <16 x i8> %39, i32 2)
  %123 = extractelement <4 x float> %122, i32 0
  %124 = bitcast float %105 to i32
  %125 = bitcast float %107 to i32
  %126 = insertelement <2 x i32> undef, i32 %124, i32 0
  %127 = insertelement <2 x i32> %126, i32 %125, i32 1
  %128 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %127, <32 x i8> %37, <16 x i8> %39, i32 2)
  %129 = extractelement <4 x float> %128, i32 0
  %130 = bitcast float %109 to i32
  %131 = bitcast float %111 to i32
  %132 = insertelement <2 x i32> undef, i32 %130, i32 0
  %133 = insertelement <2 x i32> %132, i32 %131, i32 1
  %134 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %133, <32 x i8> %37, <16 x i8> %39, i32 2)
  %135 = extractelement <4 x float> %134, i32 0
  %136 = bitcast float %89 to i32
  %137 = bitcast float %91 to i32
  %138 = insertelement <2 x i32> undef, i32 %136, i32 0
  %139 = insertelement <2 x i32> %138, i32 %137, i32 1
  %140 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %139, <32 x i8> %41, <16 x i8> %43, i32 2)
  %141 = extractelement <4 x float> %140, i32 3
  %142 = bitcast float %93 to i32
  %143 = bitcast float %95 to i32
  %144 = insertelement <2 x i32> undef, i32 %142, i32 0
  %145 = insertelement <2 x i32> %144, i32 %143, i32 1
  %146 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %145, <32 x i8> %41, <16 x i8> %43, i32 2)
  %147 = extractelement <4 x float> %146, i32 3
  %148 = call float @fabs(float %117)
  %149 = call float @fabs(float %123)
  %150 = call float @fabs(float %129)
  %151 = call float @fabs(float %135)
  %152 = fsub float -0.000000e+00, %26
  %153 = fmul float %148, %27
  %154 = fadd float %153, %152
  %155 = fsub float -0.000000e+00, %26
  %156 = fmul float %149, %27
  %157 = fadd float %156, %155
  %158 = fsub float -0.000000e+00, %26
  %159 = fmul float %150, %27
  %160 = fadd float %159, %158
  %161 = fsub float -0.000000e+00, %26
  %162 = fmul float %151, %27
  %163 = fadd float %162, %161
  %164 = fsub float -0.000000e+00, %68
  %165 = fadd float %154, %164
  %166 = fsub float -0.000000e+00, %68
  %167 = fadd float %157, %166
  %168 = fsub float -0.000000e+00, %68
  %169 = fadd float %160, %168
  %170 = fsub float -0.000000e+00, %68
  %171 = fadd float %163, %170
  %172 = call float @fabs(float %165)
  %173 = call float @fabs(float %167)
  %174 = call float @fabs(float %169)
  %175 = call float @fabs(float %171)
  %176 = fcmp oge float %172, %86
  %177 = sext i1 %176 to i32
  %178 = bitcast i32 %177 to float
  %179 = bitcast float %178 to i32
  %180 = icmp ne i32 %179, 0
  %temp24.0 = select i1 %180, float 0.000000e+00, float 0x3FCCC00540000000
  %181 = fcmp oge float %173, %86
  %182 = sext i1 %181 to i32
  %183 = bitcast i32 %182 to float
  %184 = bitcast float %183 to i32
  %185 = icmp ne i32 %184, 0
  %.55 = select i1 %185, float 0.000000e+00, float 0x3FCCC00540000000
  %186 = fcmp oge float %174, %86
  %187 = sext i1 %186 to i32
  %188 = bitcast i32 %187 to float
  %189 = bitcast float %188 to i32
  %190 = icmp ne i32 %189, 0
  %temp32.1 = select i1 %190, float 0.000000e+00, float 0x3FB93F72E0000000
  %191 = fcmp oge float %175, %86
  %192 = sext i1 %191 to i32
  %193 = bitcast i32 %192 to float
  %194 = bitcast float %193 to i32
  %195 = icmp ne i32 %194, 0
  %.56 = select i1 %195, float 0.000000e+00, float 0x3FB93F72E0000000
  %196 = fmul float %141, %temp24.0
  %197 = fmul float %147, %.55
  %198 = fadd float %196, %197
  %199 = fmul float %141, %temp32.1
  %200 = fadd float %198, %199
  %201 = fmul float %147, %.56
  %202 = fadd float %200, %201
  %203 = fadd float %87, %202
  %204 = fadd float 0x3FD2E9AF60000000, %temp24.0
  %205 = fadd float 0.000000e+00, %.55
  %206 = fadd float 0.000000e+00, %temp32.1
  %207 = fadd float 0.000000e+00, %.56
  %208 = fmul float %204, 1.000000e+00
  %209 = fmul float %205, 1.000000e+00
  %210 = fadd float %208, %209
  %211 = fmul float %206, 1.000000e+00
  %212 = fadd float %210, %211
  %213 = fmul float %207, 1.000000e+00
  %214 = fadd float %212, %213
  %215 = fdiv float 1.000000e+00, %214
  %216 = fmul float %203, %215
  br label %ENDIF

ENDIF:                                            ; preds = %main_body, %ELSE
  %temp15.0 = phi float [ %216, %ELSE ], [ %53, %main_body ]
  %217 = call i32 @llvm.SI.packf16(float 0.000000e+00, float 0.000000e+00)
  %218 = bitcast i32 %217 to float
  %219 = call i32 @llvm.SI.packf16(float 0.000000e+00, float %temp15.0)
  %220 = bitcast i32 %219 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %218, float %220, float %218, float %220)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readonly
declare float @fabs(float) #2

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #3

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readonly }
attributes #3 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg13, %SGPR2_SGPR3 in %vreg14, %SGPR4_SGPR5 in %vreg15, %SGPR7 in %vreg17, %VGPR0 in %vreg18, %VGPR1 in %vreg19

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR7 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR7
	%VGPR6<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR5_VGPR6<imp-def>
	%VGPR6<def,tied1> = V_INTERP_P2_F32 %VGPR6<tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR5_VGPR6<imp-use,kill>, %VGPR5_VGPR6<imp-def>
	%VGPR5<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR5_VGPR6<imp-use,kill>, %VGPR5_VGPR6<imp-def>
	%VGPR5<def,tied1> = V_INTERP_P2_F32 %VGPR5<tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR5_VGPR6<imp-use,kill>, %VGPR5_VGPR6<imp-def>
	%SGPR20_SGPR21_SGPR22_SGPR23<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 4; mem:LD16[%30](align=8)(tbaa=!"const")
	%SGPR24_SGPR25_SGPR26_SGPR27_SGPR28_SGPR29_SGPR30_SGPR31<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 8; mem:LD32[%27](tbaa=!"const")
	S_WAITCNT 127
	%VGPR2<def> = IMAGE_SAMPLE_V1_V2 8, 0, 0, 0, 0, 0, 0, 0, %VGPR5_VGPR6, %SGPR24_SGPR25_SGPR26_SGPR27_SGPR28_SGPR29_SGPR30_SGPR31, %SGPR20_SGPR21_SGPR22_SGPR23, %EXEC<imp-use>
	%VGPR4<def> = V_INTERP_P1_F32 %VGPR0, 3, 0, %M0<kill>, %EXEC<imp-use>, %VGPR3_VGPR4<imp-def>
	%VGPR4<def,tied1> = V_INTERP_P2_F32 %VGPR4<tied0>, %VGPR1, 3, 0, %M0<kill>, %EXEC<imp-use>, %VGPR3_VGPR4<imp-use,kill>, %VGPR3_VGPR4<imp-def>
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 2, 0, %M0<kill>, %EXEC<imp-use>, %VGPR3_VGPR4<imp-use,kill>, %VGPR3_VGPR4<imp-def>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 2, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR3_VGPR4<imp-use,kill>, %VGPR3_VGPR4<imp-def>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%24](align=8)(tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%21](tbaa=!"const")
	S_WAITCNT 112
	%VGPR0<def> = IMAGE_SAMPLE_V1_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR3_VGPR4, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	%VGPR1<def> = V_MOV_B32_e32 9.500000e-01, %EXEC<imp-use>
	S_WAITCNT 1904
	%SGPR2_SGPR3<def> = V_CMP_GT_F32_e64 %VGPR0, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_CNDMASK_B32_e64 0, -1, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_EQ_I32_e64 %VGPR1<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_AND_SAVEEXEC_B64 %SGPR2_SGPR3, %EXEC<imp-def>, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_XOR_B64 %EXEC, %SGPR2_SGPR3
	S_CBRANCH_EXECZ <BB#2>, %EXEC
    Successors according to CFG: BB#1(16) BB#2(16)

BB#1: derived from LLVM BB %ELSE
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %SGPR24_SGPR25_SGPR26_SGPR27_SGPR28_SGPR29_SGPR30_SGPR31 %SGPR20_SGPR21_SGPR22_SGPR23 %VGPR0 %SGPR0_SGPR1 %VGPR5_VGPR6 %VGPR3_VGPR4 %SGPR2_SGPR3 %VGPR2
    Predecessors according to CFG: BB#0
	%VGPR1<def> = V_ADD_F32_e64 %VGPR0, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%59](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR4_SGPR5_SGPR6_SGPR7, 5; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR0, %VGPR1<kill>, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR4_SGPR5_SGPR6_SGPR7, 4; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR1<def> = V_SUBREV_F32_e32 %SGPR1, %VGPR1<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_ADD_F32_e64 %VGPR1, 0, 0, 0, 0, 1, %EXEC<imp-use>
	%SGPR32<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR4_SGPR5_SGPR6_SGPR7, 12; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR8<def> = V_SUBREV_F32_e32 %SGPR32<kill>, %VGPR7, %EXEC<imp-use>
	%SGPR32<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR4_SGPR5_SGPR6_SGPR7, 15; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR8<def> = V_MUL_F32_e32 %SGPR32<kill>, %VGPR8<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_ADD_F32_e64 0, %VGPR8<kill>, 0, 1, 0, 0, %EXEC<imp-use>
	%SGPR32<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR4_SGPR5_SGPR6_SGPR7, 14; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR8<def> = V_MAD_F32 %SGPR32<kill>, %VGPR8<kill>, 1.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR32<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR4_SGPR5_SGPR6_SGPR7, 13; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MUL_F32_e32 %SGPR32<kill>, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_ADD_F32_e64 0, %VGPR7<kill>, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_MUL_F32_e32 %VGPR8<kill>, %VGPR7<kill>, %EXEC<imp-use>
	%SGPR32_SGPR33<def> = V_CMP_LT_F32_e64 %VGPR0<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR34<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR4_SGPR5_SGPR6_SGPR7, 1; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR0<def> = V_MOV_B32_e32 %SGPR34<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_CNDMASK_B32_e64 %VGPR7<kill>, %VGPR0<kill>, %SGPR32_SGPR33<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR32<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR4_SGPR5_SGPR6_SGPR7, 2; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR0<def> = V_MUL_F32_e32 %SGPR32<kill>, %VGPR0<kill>, %EXEC<imp-use>
	%SGPR32<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR4_SGPR5_SGPR6_SGPR7, 0; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR0<def> = V_MUL_F32_e32 %SGPR32<kill>, %VGPR0<kill>, %EXEC<imp-use>
	%SGPR32<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR4_SGPR5_SGPR6_SGPR7, 11; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR8<def> = V_ADD_F32_e64 %SGPR32, %VGPR4, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR7_VGPR8<imp-def>
	%SGPR33<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR4_SGPR5_SGPR6_SGPR7, 10; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_ADD_F32_e64 %SGPR33, %VGPR3, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR7_VGPR8<imp-use,kill>, %VGPR7_VGPR8<imp-def>
	%VGPR7<def> = IMAGE_SAMPLE_V1_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR7_VGPR8<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR7<def> = V_ADD_F32_e64 %VGPR7<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_MUL_F32_e32 %SGPR0, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_SUBREV_F32_e32 %SGPR1, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_SUB_F32_e32 %VGPR7<kill>, %VGPR1, %EXEC<imp-use>
	%VGPR7<def> = V_ADD_F32_e64 %VGPR7<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR34_SGPR35<def> = V_CMP_GE_F32_e64 %VGPR7<kill>, %VGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_MOV_B32_e32 2.246100e-01, %EXEC<imp-use>
	%VGPR8<def> = V_CNDMASK_B32_e64 %VGPR7, 0.000000e+00, %SGPR34_SGPR35<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR34<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR4_SGPR5_SGPR6_SGPR7, 9; mem:LD4[<unknown>]
	%VGPR9<def> = V_MOV_B32_e32 1.500000e+00, %EXEC<imp-use>
	S_WAITCNT 127
	%VGPR11<def> = V_MAD_F32 %SGPR34, %VGPR9, %VGPR6, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR10_VGPR11<imp-def>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR4_SGPR5_SGPR6_SGPR7<kill>, 8; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %SGPR4, %VGPR9<kill>, %VGPR5, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR10_VGPR11<imp-use,kill>, %VGPR10_VGPR11<imp-def>
	%VGPR9<def> = IMAGE_SAMPLE_V1_V2 8, 0, 0, 0, 0, 0, 0, 0, %VGPR10_VGPR11<kill>, %SGPR24_SGPR25_SGPR26_SGPR27_SGPR28_SGPR29_SGPR30_SGPR31, %SGPR20_SGPR21_SGPR22_SGPR23, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR10<def> = V_MUL_F32_e32 %VGPR9, %VGPR8, %EXEC<imp-use>
	%VGPR11<def> = V_MOV_B32_e32 %SGPR32, %EXEC<imp-use>
	%VGPR13<def> = V_SUB_F32_e64 %VGPR4, %VGPR11, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR12_VGPR13<imp-def>
	%VGPR14<def> = V_MOV_B32_e32 %SGPR33, %EXEC<imp-use>
	%VGPR12<def> = V_SUB_F32_e64 %VGPR3, %VGPR14, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR12_VGPR13<imp-use,kill>, %VGPR12_VGPR13<imp-def>
	%VGPR12<def> = IMAGE_SAMPLE_V1_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR12_VGPR13<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR12<def> = V_ADD_F32_e64 %VGPR12<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_MUL_F32_e32 %SGPR0, %VGPR12<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_SUBREV_F32_e32 %SGPR1, %VGPR12<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_SUB_F32_e32 %VGPR12<kill>, %VGPR1, %EXEC<imp-use>
	%VGPR12<def> = V_ADD_F32_e64 %VGPR12<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %VGPR12<kill>, %VGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_CNDMASK_B32_e64 %VGPR7<kill>, 0.000000e+00, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_MOV_B32_e32 -1.500000e+00, %EXEC<imp-use>
	%VGPR16<def> = V_MAD_F32 %SGPR34<kill>, %VGPR12, %VGPR6, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR15_VGPR16<imp-def>
	%VGPR15<def> = V_MAD_F32 %SGPR4<kill>, %VGPR12<kill>, %VGPR5, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR5_VGPR6<imp-use,kill>, %VGPR15_VGPR16<imp-use,kill>, %VGPR15_VGPR16<imp-def>
	%VGPR5<def> = IMAGE_SAMPLE_V1_V2 8, 0, 0, 0, 0, 0, 0, 0, %VGPR15_VGPR16<kill>, %SGPR24_SGPR25_SGPR26_SGPR27_SGPR28_SGPR29_SGPR30_SGPR31<kill>, %SGPR20_SGPR21_SGPR22_SGPR23<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR6<def> = V_MAD_F32 %VGPR5, %VGPR7, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_MAD_F32 %SGPR32, -2.000000e+00, %VGPR4, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR12_VGPR13<imp-def>
	%VGPR12<def> = V_MAD_F32 %SGPR33, -2.000000e+00, %VGPR3, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR12_VGPR13<imp-use,kill>, %VGPR12_VGPR13<imp-def>
	%VGPR10<def> = IMAGE_SAMPLE_V1_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR12_VGPR13<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR10<def> = V_ADD_F32_e64 %VGPR10<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%VGPR10<def> = V_MUL_F32_e32 %SGPR0, %VGPR10<kill>, %EXEC<imp-use>
	%VGPR10<def> = V_SUBREV_F32_e32 %SGPR1, %VGPR10<kill>, %EXEC<imp-use>
	%VGPR10<def> = V_SUB_F32_e32 %VGPR10<kill>, %VGPR1, %EXEC<imp-use>
	%VGPR10<def> = V_ADD_F32_e64 %VGPR10<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_GE_F32_e64 %VGPR10<kill>, %VGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR10<def> = V_MOV_B32_e32 9.862440e-02, %EXEC<imp-use>
	%VGPR12<def> = V_CNDMASK_B32_e64 %VGPR10, 0.000000e+00, %SGPR4_SGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR5<kill>, %VGPR12, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_ADD_F32_e64 %SGPR32<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR16<def> = V_ADD_F32_e32 %VGPR4, %VGPR6<kill>, %EXEC<imp-use>, %VGPR15_VGPR16<imp-def>
	%VGPR6<def> = V_ADD_F32_e64 %SGPR33<kill>, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR15<def> = V_ADD_F32_e32 %VGPR3, %VGPR6<kill>, %EXEC<imp-use>, %VGPR3_VGPR4<imp-use,kill>, %VGPR15_VGPR16<imp-use,kill>, %VGPR15_VGPR16<imp-def>
	%VGPR3<def> = IMAGE_SAMPLE_V1_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR15_VGPR16<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR3<def> = V_ADD_F32_e64 %VGPR3<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_SUBREV_F32_e32 %SGPR1<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_SUB_F32_e32 %VGPR3<kill>, %VGPR1<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_ADD_F32_e64 %VGPR1<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = V_CMP_GE_F32_e64 %VGPR1<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_CNDMASK_B32_e64 %VGPR10<kill>, 0.000000e+00, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_MAD_F32 %VGPR9<kill>, %VGPR0, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_MOV_B32_e32 2.955130e-01, %EXEC<imp-use>
	%VGPR1<def> = V_MAD_F32 %VGPR2<kill>, %VGPR3<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR2<def> = V_ADD_F32_e32 0.000000e+00, %VGPR8<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_ADD_F32_e32 2.955130e-01, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_ADD_F32_e32 %VGPR3<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_ADD_F32_e32 0.000000e+00, %VGPR12<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_ADD_F32_e32 %VGPR2<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_F32_e32 0.000000e+00, %VGPR0<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_F32_e32 %VGPR2<kill>, %VGPR0<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_RCP_F32_e32 %VGPR0<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_MUL_F32_e32 %VGPR1<kill>, %VGPR0<kill>, %EXEC<imp-use>
    Successors according to CFG: BB#2

BB#2: derived from LLVM BB %ENDIF
    Live Ins: %SGPR2_SGPR3 %VGPR2
    Predecessors according to CFG: BB#0 BB#1
	%EXEC<def> = S_OR_B64 %EXEC, %SGPR2_SGPR3
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e64 0.000000e+00, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_CVT_PKRTZ_F16_F32_e64 0.000000e+00, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR1<kill>, %VGPR0<kill>, %VGPR1, %VGPR0, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_WQM_B64 exec, exec                                                  ; BEFE0A7E
	S_MOV_B32 m0, s7                                                      ; BEFC0307
	V_INTERP_P1_F32 v6, v0, 1, 0, [m0]                                    ; C8180100
	V_INTERP_P2_F32 v6, [v6], v1, 1, 0, [m0]                              ; C8190101
	V_INTERP_P1_F32 v5, v0, 0, 0, [m0]                                    ; C8140000
	V_INTERP_P2_F32 v5, [v5], v1, 0, 0, [m0]                              ; C8150001
	S_LOAD_DWORDX4 s[20:23], s[2:3], 4                                    ; C08A0304
	S_LOAD_DWORDX8 s[24:31], s[4:5], 8                                    ; C0CC0508
	S_WAITCNT lgkmcnt(0)                                                  ; BF8C007F
	IMAGE_SAMPLE v2, 8, 0, 0, 0, 0, 0, 0, 0, v[5:6], s[24:31], s[20:23]   ; F0800800 00A60205
	V_INTERP_P1_F32 v4, v0, 3, 0, [m0]                                    ; C8100300
	V_INTERP_P2_F32 v4, [v4], v1, 3, 0, [m0]                              ; C8110301
	V_INTERP_P1_F32 v3, v0, 2, 0, [m0]                                    ; C80C0200
	V_INTERP_P2_F32 v3, [v3], v1, 2, 0, [m0]                              ; C80D0201
	S_LOAD_DWORDX4 s[8:11], s[2:3], 0                                     ; C0840300
	S_LOAD_DWORDX8 s[12:19], s[4:5], 0                                    ; C0C60500
	S_WAITCNT vmcnt(0) lgkmcnt(0)                                         ; BF8C0070
	IMAGE_SAMPLE v0, 1, 0, 0, 0, 0, 0, 0, 0, v[3:4], s[12:19], s[8:11]    ; F0800100 00430003
	V_MOV_B32_e32 v1, 9.500000e-01                                        ; 7E0202FF 3F733333
	S_WAITCNT vmcnt(0)                                                    ; BF8C0770
	V_CMP_GT_F32_e64 s[2:3], v0, v1, 0, 0, 0, 0                           ; D0080002 02020300
	V_CNDMASK_B32_e64 v1, 0, -1, s[2:3], 0, 0, 0, 0                       ; D2000001 00098280
	V_CMP_EQ_I32_e64 s[2:3], v1, 0, 0, 0, 0, 0                            ; D1040002 02010101
	S_AND_SAVEEXEC_B64 s[2:3], s[2:3]                                     ; BE822402
	S_XOR_B64 s[2:3], exec, s[2:3]                                        ; 8982027E
	S_CBRANCH_EXECZ ";.BB0_2"                                             ; BF880000
	V_ADD_F32_e64 v1, v0, 0, 1, 0, 0, 0                                   ; D2060101 02010100
	S_LOAD_DWORDX4 s[4:7], s[0:1], 0                                      ; C0820100
	S_WAITCNT lgkmcnt(0)                                                  ; BF8C007F
	S_BUFFER_LOAD_DWORD s0, s[4:7], 5                                     ; C2000505
	S_WAITCNT lgkmcnt(0)                                                  ; BF8C007F
	V_MUL_F32_e32 v1, s0, v1                                              ; 10020200
	S_BUFFER_LOAD_DWORD s1, s[4:7], 4                                     ; C2008504
	S_WAITCNT lgkmcnt(0)                                                  ; BF8C007F
	V_SUBREV_F32_e32 v1, s1, v1                                           ; 0A020201
	V_ADD_F32_e64 v7, v1, 0, 0, 0, 0, 1                                   ; D2060007 22010101
	S_BUFFER_LOAD_DWORD s32, s[4:7], 12                                   ; C210050C
	S_WAITCNT lgkmcnt(0)                                                  ; BF8C007F
	V_SUBREV_F32_e32 v8, s32, v7                                          ; 0A100E20
	S_BUFFER_LOAD_DWORD s32, s[4:7], 15                                   ; C210050F
	S_WAITCNT lgkmcnt(0)                                                  ; BF8C007F
	V_MUL_F32_e32 v8, s32, v8                                             ; 10101020
	V_ADD_F32_e64 v8, 0, v8, 0, 1, 0, 0                                   ; D2060808 02021080
	S_BUFFER_LOAD_DWORD s32, s[4:7], 14                                   ; C210050E
	S_WAITCNT lgkmcnt(0)                                                  ; BF8C007F
	V_MAD_F32 v8, s32, v8, 1.000000e+00, 0, 0, 0, 0                       ; D2820008 03CA1020
	S_BUFFER_LOAD_DWORD s32, s[4:7], 13                                   ; C210050D
	S_WAITCNT lgkmcnt(0)                                                  ; BF8C007F
	V_MUL_F32_e32 v7, s32, v7                                             ; 100E0E20
	V_ADD_F32_e64 v7, 0, v7, 0, 1, 0, 0                                   ; D2060807 02020E80
	V_MUL_F32_e32 v7, v8, v7                                              ; 100E0F08
	V_CMP_LT_F32_e64 s[32:33], v0, 0.000000e+00, 0, 0, 0, 0               ; D0020020 02010100
	S_BUFFER_LOAD_DWORD s34, s[4:7], 1                                    ; C2110501
	S_WAITCNT lgkmcnt(0)                                                  ; BF8C007F
	V_MOV_B32_e32 v0, s34                                                 ; 7E000222
	V_CNDMASK_B32_e64 v0, v7, v0, s[32:33], 0, 0, 0, 0                    ; D2000000 00820107
	S_BUFFER_LOAD_DWORD s32, s[4:7], 2                                    ; C2100502
	S_WAITCNT lgkmcnt(0)                                                  ; BF8C007F
	V_MUL_F32_e32 v0, s32, v0                                             ; 10000020
	S_BUFFER_LOAD_DWORD s32, s[4:7], 0                                    ; C2100500
	S_WAITCNT lgkmcnt(0)                                                  ; BF8C007F
	V_MUL_F32_e32 v0, s32, v0                                             ; 10000020
	S_BUFFER_LOAD_DWORD s32, s[4:7], 11                                   ; C210050B
	S_WAITCNT lgkmcnt(0)                                                  ; BF8C007F
	V_ADD_F32_e64 v8, s32, v4, 0, 0, 0, 0                                 ; D2060008 02020820
	S_BUFFER_LOAD_DWORD s33, s[4:7], 10                                   ; C210850A
	S_WAITCNT lgkmcnt(0)                                                  ; BF8C007F
	V_ADD_F32_e64 v7, s33, v3, 0, 0, 0, 0                                 ; D2060007 02020621
	IMAGE_SAMPLE v7, 1, 0, 0, 0, 0, 0, 0, 0, v[7:8], s[12:19], s[8:11]    ; F0800100 00430707
	S_WAITCNT vmcnt(0)                                                    ; BF8C0770
	V_ADD_F32_e64 v7, v7, 0, 1, 0, 0, 0                                   ; D2060107 02010107
	V_MUL_F32_e32 v7, s0, v7                                              ; 100E0E00
	V_SUBREV_F32_e32 v7, s1, v7                                           ; 0A0E0E01
	V_SUB_F32_e32 v7, v7, v1                                              ; 080E0307
	V_ADD_F32_e64 v7, v7, 0, 1, 0, 0, 0                                   ; D2060107 02010107
	V_CMP_GE_F32_e64 s[34:35], v7, v0, 0, 0, 0, 0                         ; D00C0022 02020107
	V_MOV_B32_e32 v7, 2.246100e-01                                        ; 7E0E02FF 3E66002A
	V_CNDMASK_B32_e64 v8, v7, 0.000000e+00, s[34:35], 0, 0, 0, 0          ; D2000008 00890107
	S_BUFFER_LOAD_DWORD s34, s[4:7], 9                                    ; C2110509
	V_MOV_B32_e32 v9, 1.500000e+00                                        ; 7E1202FF 3FC00000
	S_WAITCNT lgkmcnt(0)                                                  ; BF8C007F
	V_MAD_F32 v11, s34, v9, v6, 0, 0, 0, 0                                ; D282000B 041A1222
	S_BUFFER_LOAD_DWORD s4, s[4:7], 8                                     ; C2020508
	S_WAITCNT lgkmcnt(0)                                                  ; BF8C007F
	V_MAD_F32 v10, s4, v9, v5, 0, 0, 0, 0                                 ; D282000A 04161204
	IMAGE_SAMPLE v9, 8, 0, 0, 0, 0, 0, 0, 0, v[10:11], s[24:31], s[20:23] ; F0800800 00A6090A
	S_WAITCNT vmcnt(0)                                                    ; BF8C0770
	V_MUL_F32_e32 v10, v9, v8                                             ; 10141109
	V_MOV_B32_e32 v11, s32                                                ; 7E160220
	V_SUB_F32_e64 v13, v4, v11, 0, 0, 0, 0                                ; D208000D 02021704
	V_MOV_B32_e32 v14, s33                                                ; 7E1C0221
	V_SUB_F32_e64 v12, v3, v14, 0, 0, 0, 0                                ; D208000C 02021D03
	IMAGE_SAMPLE v12, 1, 0, 0, 0, 0, 0, 0, 0, v[12:13], s[12:19], s[8:11] ; F0800100 00430C0C
	S_WAITCNT vmcnt(0)                                                    ; BF8C0770
	V_ADD_F32_e64 v12, v12, 0, 1, 0, 0, 0                                 ; D206010C 0201010C
	V_MUL_F32_e32 v12, s0, v12                                            ; 10181800
	V_SUBREV_F32_e32 v12, s1, v12                                         ; 0A181801
	V_SUB_F32_e32 v12, v12, v1                                            ; 0818030C
	V_ADD_F32_e64 v12, v12, 0, 1, 0, 0, 0                                 ; D206010C 0201010C
	V_CMP_GE_F32_e64 s[6:7], v12, v0, 0, 0, 0, 0                          ; D00C0006 0202010C
	V_CNDMASK_B32_e64 v7, v7, 0.000000e+00, s[6:7], 0, 0, 0, 0            ; D2000007 00190107
	V_MOV_B32_e32 v12, -1.500000e+00                                      ; 7E1802FF BFC00000
	V_MAD_F32 v16, s34, v12, v6, 0, 0, 0, 0                               ; D2820010 041A1822
	V_MAD_F32 v15, s4, v12, v5, 0, 0, 0, 0                                ; D282000F 04161804
	IMAGE_SAMPLE v5, 8, 0, 0, 0, 0, 0, 0, 0, v[15:16], s[24:31], s[20:23] ; F0800800 00A6050F
	S_WAITCNT vmcnt(0)                                                    ; BF8C0770
	V_MAD_F32 v6, v5, v7, v10, 0, 0, 0, 0                                 ; D2820006 042A0F05
	V_MAD_F32 v13, s32, -2.000000e+00, v4, 0, 0, 0, 0                     ; D282000D 0411EA20
	V_MAD_F32 v12, s33, -2.000000e+00, v3, 0, 0, 0, 0                     ; D282000C 040DEA21
	IMAGE_SAMPLE v10, 1, 0, 0, 0, 0, 0, 0, 0, v[12:13], s[12:19], s[8:11] ; F0800100 00430A0C
	S_WAITCNT vmcnt(0)                                                    ; BF8C0770
	V_ADD_F32_e64 v10, v10, 0, 1, 0, 0, 0                                 ; D206010A 0201010A
	V_MUL_F32_e32 v10, s0, v10                                            ; 10141400
	V_SUBREV_F32_e32 v10, s1, v10                                         ; 0A141401
	V_SUB_F32_e32 v10, v10, v1                                            ; 0814030A
	V_ADD_F32_e64 v10, v10, 0, 1, 0, 0, 0                                 ; D206010A 0201010A
	V_CMP_GE_F32_e64 s[4:5], v10, v0, 0, 0, 0, 0                          ; D00C0004 0202010A
	V_MOV_B32_e32 v10, 9.862440e-02                                       ; 7E1402FF 3DC9FB97
	V_CNDMASK_B32_e64 v12, v10, 0.000000e+00, s[4:5], 0, 0, 0, 0          ; D200000C 0011010A
	V_MAD_F32 v5, v5, v12, v6, 0, 0, 0, 0                                 ; D2820005 041A1905
	V_ADD_F32_e64 v6, s32, v11, 0, 0, 0, 0                                ; D2060006 02021620
	V_ADD_F32_e32 v16, v4, v6                                             ; 06200D04
	V_ADD_F32_e64 v6, s33, v14, 0, 0, 0, 0                                ; D2060006 02021C21
	V_ADD_F32_e32 v15, v3, v6                                             ; 061E0D03
	IMAGE_SAMPLE v3, 1, 0, 0, 0, 0, 0, 0, 0, v[15:16], s[12:19], s[8:11]  ; F0800100 0043030F
	S_WAITCNT vmcnt(0)                                                    ; BF8C0770
	V_ADD_F32_e64 v3, v3, 0, 1, 0, 0, 0                                   ; D2060103 02010103
	V_MUL_F32_e32 v3, s0, v3                                              ; 10060600
	V_SUBREV_F32_e32 v3, s1, v3                                           ; 0A060601
	V_SUB_F32_e32 v1, v3, v1                                              ; 08020303
	V_ADD_F32_e64 v1, v1, 0, 1, 0, 0, 0                                   ; D2060101 02010101
	V_CMP_GE_F32_e64 s[0:1], v1, v0, 0, 0, 0, 0                           ; D00C0000 02020101
	V_CNDMASK_B32_e64 v0, v10, 0.000000e+00, s[0:1], 0, 0, 0, 0           ; D2000000 0001010A
	V_MAD_F32 v1, v9, v0, v5, 0, 0, 0, 0                                  ; D2820001 04160109
	V_MOV_B32_e32 v3, 2.955130e-01                                        ; 7E0602FF 3E974D7B
	V_MAD_F32 v1, v2, v3, v1, 0, 0, 0, 0                                  ; D2820001 04060702
	V_ADD_F32_e32 v2, 0.000000e+00, v8                                    ; 06041080
	V_ADD_F32_e32 v3, 2.955130e-01, v7                                    ; 06060EFF 3E974D7B
	V_ADD_F32_e32 v2, v3, v2                                              ; 06040503
	V_ADD_F32_e32 v3, 0.000000e+00, v12                                   ; 06061880
	V_ADD_F32_e32 v2, v2, v3                                              ; 06040702
	V_ADD_F32_e32 v0, 0.000000e+00, v0                                    ; 06000080
	V_ADD_F32_e32 v0, v2, v0                                              ; 06000102
	V_RCP_F32_e32 v0, v0                                                  ; 7E005500
	V_MUL_F32_e32 v2, v1, v0                                              ; 10040101
	S_OR_B64 exec, exec, s[2:3]                                           ; 88FE027E
	V_CVT_PKRTZ_F16_F32_e64 v0, 0.000000e+00, v2, 0, 0, 0, 0              ; D25E0000 02020480
	V_CVT_PKRTZ_F16_F32_e64 v1, 0.000000e+00, 0.000000e+00, 0, 0, 0, 0    ; D25E0001 02010080
	EXP 15, 0, 1, 1, 1, v1, v0, v1, v0                                    ; F8001C0F 00010001
	S_ENDPGM                                                              ; BF810000

VERT
DCL IN[0]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[19]
DCL CONST[0..1]
DCL TEMP[0..2], LOCAL
IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
  0: MOV TEMP[0].zw, IMM[0].yyxy
  1: MOV TEMP[0].xy, IN[0].xyxx
  2: MAD TEMP[1].xy, IN[0].zwww, CONST[0].xyyy, CONST[0].zwww
  3: MAD TEMP[2].xy, IN[0].zwww, CONST[1].xyyy, CONST[1].zwww
  4: MOV TEMP[1].zw, TEMP[2].yyxy
  5: MOV OUT[1], TEMP[1]
  6: MOV OUT[0], TEMP[0]
  7: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0)
  %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4)
  %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8)
  %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12)
  %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16)
  %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20)
  %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24)
  %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28)
  %20 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %21, i32 0, i32 %6)
  %23 = extractelement <4 x float> %22, i32 0
  %24 = extractelement <4 x float> %22, i32 1
  %25 = extractelement <4 x float> %22, i32 2
  %26 = extractelement <4 x float> %22, i32 3
  %27 = fmul float %25, %12
  %28 = fadd float %27, %14
  %29 = fmul float %26, %13
  %30 = fadd float %29, %15
  %31 = fmul float %25, %16
  %32 = fadd float %31, %18
  %33 = fmul float %26, %17
  %34 = fadd float %33, %19
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %28, float %30, float %32, float %34)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %23, float %24, float 0.000000e+00, float 1.000000e+00)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg6

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%23](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%11](align=8)(tbaa=!"const")
	S_WAITCNT 112
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 7; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR4<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 5; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR3, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 6; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 4; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR2, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 3; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR3, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 0; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR8<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR2, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 32, 0, 0, 0, %VGPR7<kill>, %VGPR6<kill>, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>
	S_WAITCNT 1807
	%VGPR4<def> = V_MOV_B32_e32 1.000000e+00, %EXEC<imp-use>
	%VGPR5<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR1, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_LOAD_DWORDX4 s[4:7], s[6:7], 0               ; C0820700
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	BUFFER_LOAD_FORMAT_XYZW v[0:3], s[4:7][v0] + 0 ; E00C2000 80010000
	S_LOAD_DWORDX4 s[0:3], s[0:1], 0               ; C0800100
	S_WAITCNT vmcnt(0) lgkmcnt(0)                  ; BF8C0070
	S_BUFFER_LOAD_DWORD s4, s[0:3], 7              ; C2020107
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v4, s4                           ; 7E080204
	S_BUFFER_LOAD_DWORD s4, s[0:3], 5              ; C2020105
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v5, s4                           ; 7E0A0204
	V_MAD_F32 v4, v3, v5, v4, 0, 0, 0, 0           ; D2820004 04120B03
	S_BUFFER_LOAD_DWORD s4, s[0:3], 6              ; C2020106
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v5, s4                           ; 7E0A0204
	S_BUFFER_LOAD_DWORD s4, s[0:3], 4              ; C2020104
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v6, s4                           ; 7E0C0204
	V_MAD_F32 v5, v2, v6, v5, 0, 0, 0, 0           ; D2820005 04160D02
	S_BUFFER_LOAD_DWORD s4, s[0:3], 3              ; C2020103
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v6, s4                           ; 7E0C0204
	S_BUFFER_LOAD_DWORD s4, s[0:3], 1              ; C2020101
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v7, s4                           ; 7E0E0204
	V_MAD_F32 v6, v3, v7, v6, 0, 0, 0, 0           ; D2820006 041A0F03
	S_BUFFER_LOAD_DWORD s4, s[0:3], 2              ; C2020102
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v7, s4                           ; 7E0E0204
	S_BUFFER_LOAD_DWORD s0, s[0:3], 0              ; C2000100
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v8, s0                           ; 7E100200
	V_MAD_F32 v7, v2, v8, v7, 0, 0, 0, 0           ; D2820007 041E1102
	EXP 15, 32, 0, 0, 0, v7, v6, v5, v4            ; F800020F 04050607
	S_WAITCNT expcnt(0)                            ; BF8C070F
	V_MOV_B32_e32 v4, 1.000000e+00                 ; 7E0802F2
	V_MOV_B32_e32 v5, 0.000000e+00                 ; 7E0A0280
	EXP 15, 12, 0, 1, 0, v0, v1, v5, v4            ; F80008CF 04050100
	S_ENDPGM                                       ; BF810000

FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL IN[1], GENERIC[20], PERSPECTIVE
DCL IN[2], GENERIC[21], PERSPECTIVE
DCL IN[3], GENERIC[22], PERSPECTIVE
DCL IN[4], GENERIC[23], PERSPECTIVE
DCL IN[5], GENERIC[24], PERSPECTIVE
DCL IN[6], GENERIC[25], PERSPECTIVE
DCL IN[7], GENERIC[26], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL SAMP[1]
DCL SAMP[2]
DCL SAMP[3]
DCL SAMP[4]
DCL SAMP[5]
DCL CONST[0..12]
DCL TEMP[0..7], LOCAL
IMM[0] FLT32 {    0.0000,     2.0000,    -1.0000,     1.0001}
IMM[1] FLT32 {   32.0000,   -16.0000,     1.0000,     0.0000}
IMM[2] FLT32 {65504.0000,     0.0000,     0.0000,     0.0000}
  0: MOV TEMP[0].x, IN[5].wwww
  1: MOV TEMP[0].yz, IN[6].yxyy
  2: MOV TEMP[1].xy, IN[6].zwzz
  3: MOV TEMP[1].z, IN[7].xxxx
  4: MOV TEMP[2].xy, IN[4].xyyy
  5: TEX TEMP[2].xw, TEMP[2], SAMP[1], 2D
  6: MUL TEMP[2].xy, TEMP[2].wxxx, IN[4].zwww
  7: RCP TEMP[3].xy, IN[1].wwww
  8: MUL TEMP[3].xy, IN[0].xyyy, TEMP[3].xyyy
  9: MOV TEMP[4].xy, IN[2].xyyy
 10: TEX TEMP[4], TEMP[4], SAMP[2], 2D
 11: FSLT TEMP[5].x, IMM[0].xxxx, TEMP[4].zzzz
 12: UIF TEMP[5].xxxx :0
 13:   MOV TEMP[5].xy, TEMP[4].ywyy
 14: ELSE :0
 15:   MOV TEMP[5].xy, TEMP[4].xyxx
 16: ENDIF
 17: MOV TEMP[4].xy, TEMP[5].xyxx
 18: MOV TEMP[5].xy, IN[2].zwww
 19: TEX TEMP[5], TEMP[5], SAMP[3], 2D
 20: FSLT TEMP[6].x, IMM[0].xxxx, TEMP[5].zzzz
 21: UIF TEMP[6].xxxx :0
 22:   MOV TEMP[6].xy, TEMP[5].ywyy
 23: ELSE :0
 24:   MOV TEMP[6].xy, TEMP[5].xyxx
 25: ENDIF
 26: MOV TEMP[4].zw, TEMP[6].yyxy
 27: MOV TEMP[5].xy, IN[3].xyyy
 28: TEX TEMP[5], TEMP[5], SAMP[4], 2D
 29: FSLT TEMP[6].x, IMM[0].xxxx, TEMP[5].zzzz
 30: UIF TEMP[6].xxxx :0
 31:   MOV TEMP[6].xy, TEMP[5].ywyy
 32: ELSE :0
 33:   MOV TEMP[6].xy, TEMP[5].xyxx
 34: ENDIF
 35: MOV TEMP[5].xy, TEMP[6].xyxx
 36: MOV TEMP[6].xy, IN[3].zwww
 37: TEX TEMP[6], TEMP[6], SAMP[5], 2D
 38: FSLT TEMP[7].x, IMM[0].xxxx, TEMP[6].zzzz
 39: UIF TEMP[7].xxxx :0
 40:   MOV TEMP[7].xy, TEMP[6].ywyy
 41: ELSE :0
 42:   MOV TEMP[7].xy, TEMP[6].xyxx
 43: ENDIF
 44: MOV TEMP[5].zw, TEMP[7].yyxy
 45: MAD TEMP[6], TEMP[4], IMM[0].yyyy, IMM[0].zzzz
 46: MOV TEMP[4], -TEMP[6]
 47: MAD TEMP[6], TEMP[5], IMM[0].yyyy, IMM[0].zzzz
 48: MOV TEMP[5], -TEMP[6]
 49: MUL TEMP[4], TEMP[4], CONST[1].xxyy
 50: MUL TEMP[5], TEMP[5], CONST[1].zzww
 51: ADD TEMP[4], TEMP[4], TEMP[5]
 52: ADD TEMP[4].xy, TEMP[4].xyyy, TEMP[4].zwww
 53: MUL TEMP[4].xy, TEMP[4].xyyy, TEMP[2].xxxx
 54: MOV TEMP[5].xy, TEMP[4].xyxx
 55: DP2 TEMP[6].x, TEMP[4].xyyy, TEMP[4].xyyy
 56: ADD_SAT TEMP[6].x, IMM[0].wwww, -TEMP[6].xxxx
 57: RSQ TEMP[7].x, TEMP[6].xxxx
 58: MUL TEMP[7].x, TEMP[7].xxxx, TEMP[6].xxxx
 59: CMP TEMP[7].x, -TEMP[6].xxxx, TEMP[7].xxxx, IMM[0].xxxx
 60: MOV TEMP[5].z, TEMP[7].xxxx
 61: DP3 TEMP[6].x, TEMP[5].xyzz, TEMP[5].xyzz
 62: RSQ TEMP[6].x, TEMP[6].xxxx
 63: MUL TEMP[5].xyz, TEMP[5].xyzz, TEMP[6].xxxx
 64: ADD TEMP[6].xyz, CONST[12].xyzz, -IN[1].xyzz
 65: MUL TEMP[7].xyz, IN[5].xyzz, TEMP[5].xxxx
 66: MAD TEMP[0].xyz, TEMP[0].xyzz, TEMP[5].yyyy, TEMP[7].xyzz
 67: MAD TEMP[0].xyz, TEMP[1].xyzz, TEMP[5].zzzz, TEMP[0].xyzz
 68: ADD TEMP[1].xy, TEMP[3].xyyy, TEMP[4].xyyy
 69: MOV TEMP[1].xy, TEMP[1].xyyy
 70: MOV TEMP[1].w, CONST[2].zzzz
 71: TXL TEMP[1], TEMP[1], SAMP[0], 2D
 72: MAD TEMP[3].x, TEMP[1].wwww, IMM[1].xxxx, IMM[1].yyyy
 73: EX2 TEMP[3].x, TEMP[3].xxxx
 74: MUL TEMP[1].xyz, TEMP[1].xyzz, TEMP[3].xxxx
 75: MUL TEMP[1].xyz, CONST[0].xyzz, TEMP[1].xyzz
 76: MOV TEMP[1].w, IMM[1].zzzz
 77: MUL TEMP[2].x, CONST[0].wwww, TEMP[2].yyyy
 78: DP3 TEMP[3].x, TEMP[6].xyzz, TEMP[6].xyzz
 79: RSQ TEMP[3].x, TEMP[3].xxxx
 80: MUL TEMP[3].xyz, TEMP[6].xyzz, TEMP[3].xxxx
 81: DP3 TEMP[4].x, TEMP[0].xyzz, TEMP[0].xyzz
 82: RSQ TEMP[4].x, TEMP[4].xxxx
 83: MUL TEMP[0].xyz, TEMP[0].xyzz, TEMP[4].xxxx
 84: DP3_SAT TEMP[0].x, TEMP[3].xyzz, TEMP[0].xyzz
 85: ADD TEMP[0].x, IMM[1].zzzz, -TEMP[0].xxxx
 86: POW TEMP[0].x, TEMP[0].xxxx, CONST[2].xxxx
 87: MUL TEMP[0].x, TEMP[2].xxxx, TEMP[0].xxxx
 88: MOV TEMP[2].xz, IN[0].zzwz
 89: MUL TEMP[3].xy, IN[0].zwww, IN[0].zwww
 90: MAD TEMP[3].xy, IMM[0].yyyy, IN[0].zwww, -TEMP[3].xyyy
 91: MOV TEMP[2].yw, TEMP[3].yxyy
 92: MUL TEMP[2], TEMP[2], CONST[5]
 93: ADD TEMP[0].x, IMM[1].zzzz, -TEMP[0].xxxx
 94: MUL TEMP[0], CONST[3].zzzw, TEMP[0].xxxx
 95: LRP TEMP[0], TEMP[0], CONST[3].xxxy, TEMP[1]
 96: LRP TEMP[0], TEMP[2].zzzw, CONST[7], TEMP[0]
 97: LRP TEMP[0], TEMP[2].xxxy, CONST[6], TEMP[0]
 98: MAX TEMP[2].xyz, TEMP[0].xyzz, IMM[1].wwww
 99: MIN TEMP[1].xyz, TEMP[2].xyzz, IMM[2].xxxx
100: MAD_SAT TEMP[0].x, TEMP[0].wwww, CONST[4].xxxx, CONST[4].yyyy
101: MOV TEMP[1].w, TEMP[0].xxxx
102: MOV OUT[0], TEMP[1]
103: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %21 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
  %22 = load <16 x i8> addrspace(2)* %21, !tbaa !0
  %23 = call float @llvm.SI.load.const(<16 x i8> %22, i32 0)
  %24 = call float @llvm.SI.load.const(<16 x i8> %22, i32 4)
  %25 = call float @llvm.SI.load.const(<16 x i8> %22, i32 8)
  %26 = call float @llvm.SI.load.const(<16 x i8> %22, i32 12)
  %27 = call float @llvm.SI.load.const(<16 x i8> %22, i32 16)
  %28 = call float @llvm.SI.load.const(<16 x i8> %22, i32 20)
  %29 = call float @llvm.SI.load.const(<16 x i8> %22, i32 24)
  %30 = call float @llvm.SI.load.const(<16 x i8> %22, i32 28)
  %31 = call float @llvm.SI.load.const(<16 x i8> %22, i32 32)
  %32 = call float @llvm.SI.load.const(<16 x i8> %22, i32 40)
  %33 = call float @llvm.SI.load.const(<16 x i8> %22, i32 48)
  %34 = call float @llvm.SI.load.const(<16 x i8> %22, i32 52)
  %35 = call float @llvm.SI.load.const(<16 x i8> %22, i32 56)
  %36 = call float @llvm.SI.load.const(<16 x i8> %22, i32 60)
  %37 = call float @llvm.SI.load.const(<16 x i8> %22, i32 64)
  %38 = call float @llvm.SI.load.const(<16 x i8> %22, i32 68)
  %39 = call float @llvm.SI.load.const(<16 x i8> %22, i32 80)
  %40 = call float @llvm.SI.load.const(<16 x i8> %22, i32 84)
  %41 = call float @llvm.SI.load.const(<16 x i8> %22, i32 88)
  %42 = call float @llvm.SI.load.const(<16 x i8> %22, i32 92)
  %43 = call float @llvm.SI.load.const(<16 x i8> %22, i32 96)
  %44 = call float @llvm.SI.load.const(<16 x i8> %22, i32 100)
  %45 = call float @llvm.SI.load.const(<16 x i8> %22, i32 104)
  %46 = call float @llvm.SI.load.const(<16 x i8> %22, i32 108)
  %47 = call float @llvm.SI.load.const(<16 x i8> %22, i32 112)
  %48 = call float @llvm.SI.load.const(<16 x i8> %22, i32 116)
  %49 = call float @llvm.SI.load.const(<16 x i8> %22, i32 120)
  %50 = call float @llvm.SI.load.const(<16 x i8> %22, i32 124)
  %51 = call float @llvm.SI.load.const(<16 x i8> %22, i32 192)
  %52 = call float @llvm.SI.load.const(<16 x i8> %22, i32 196)
  %53 = call float @llvm.SI.load.const(<16 x i8> %22, i32 200)
  %54 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0
  %55 = load <32 x i8> addrspace(2)* %54, !tbaa !0
  %56 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0
  %57 = load <16 x i8> addrspace(2)* %56, !tbaa !0
  %58 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 1
  %59 = load <32 x i8> addrspace(2)* %58, !tbaa !0
  %60 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 1
  %61 = load <16 x i8> addrspace(2)* %60, !tbaa !0
  %62 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 2
  %63 = load <32 x i8> addrspace(2)* %62, !tbaa !0
  %64 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 2
  %65 = load <16 x i8> addrspace(2)* %64, !tbaa !0
  %66 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 3
  %67 = load <32 x i8> addrspace(2)* %66, !tbaa !0
  %68 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 3
  %69 = load <16 x i8> addrspace(2)* %68, !tbaa !0
  %70 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 4
  %71 = load <32 x i8> addrspace(2)* %70, !tbaa !0
  %72 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 4
  %73 = load <16 x i8> addrspace(2)* %72, !tbaa !0
  %74 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 5
  %75 = load <32 x i8> addrspace(2)* %74, !tbaa !0
  %76 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 5
  %77 = load <16 x i8> addrspace(2)* %76, !tbaa !0
  %78 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %4, <2 x i32> %6)
  %79 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %4, <2 x i32> %6)
  %80 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %4, <2 x i32> %6)
  %81 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %4, <2 x i32> %6)
  %82 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %4, <2 x i32> %6)
  %83 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %4, <2 x i32> %6)
  %84 = call float @llvm.SI.fs.interp(i32 2, i32 1, i32 %4, <2 x i32> %6)
  %85 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %4, <2 x i32> %6)
  %86 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %4, <2 x i32> %6)
  %87 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %4, <2 x i32> %6)
  %88 = call float @llvm.SI.fs.interp(i32 2, i32 2, i32 %4, <2 x i32> %6)
  %89 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %4, <2 x i32> %6)
  %90 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %4, <2 x i32> %6)
  %91 = call float @llvm.SI.fs.interp(i32 1, i32 3, i32 %4, <2 x i32> %6)
  %92 = call float @llvm.SI.fs.interp(i32 2, i32 3, i32 %4, <2 x i32> %6)
  %93 = call float @llvm.SI.fs.interp(i32 3, i32 3, i32 %4, <2 x i32> %6)
  %94 = call float @llvm.SI.fs.interp(i32 0, i32 4, i32 %4, <2 x i32> %6)
  %95 = call float @llvm.SI.fs.interp(i32 1, i32 4, i32 %4, <2 x i32> %6)
  %96 = call float @llvm.SI.fs.interp(i32 2, i32 4, i32 %4, <2 x i32> %6)
  %97 = call float @llvm.SI.fs.interp(i32 3, i32 4, i32 %4, <2 x i32> %6)
  %98 = call float @llvm.SI.fs.interp(i32 0, i32 5, i32 %4, <2 x i32> %6)
  %99 = call float @llvm.SI.fs.interp(i32 1, i32 5, i32 %4, <2 x i32> %6)
  %100 = call float @llvm.SI.fs.interp(i32 2, i32 5, i32 %4, <2 x i32> %6)
  %101 = call float @llvm.SI.fs.interp(i32 3, i32 5, i32 %4, <2 x i32> %6)
  %102 = call float @llvm.SI.fs.interp(i32 0, i32 6, i32 %4, <2 x i32> %6)
  %103 = call float @llvm.SI.fs.interp(i32 1, i32 6, i32 %4, <2 x i32> %6)
  %104 = call float @llvm.SI.fs.interp(i32 2, i32 6, i32 %4, <2 x i32> %6)
  %105 = call float @llvm.SI.fs.interp(i32 3, i32 6, i32 %4, <2 x i32> %6)
  %106 = call float @llvm.SI.fs.interp(i32 0, i32 7, i32 %4, <2 x i32> %6)
  %107 = bitcast float %94 to i32
  %108 = bitcast float %95 to i32
  %109 = insertelement <2 x i32> undef, i32 %107, i32 0
  %110 = insertelement <2 x i32> %109, i32 %108, i32 1
  %111 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %110, <32 x i8> %59, <16 x i8> %61, i32 2)
  %112 = extractelement <4 x float> %111, i32 0
  %113 = extractelement <4 x float> %111, i32 3
  %114 = fmul float %113, %96
  %115 = fmul float %112, %97
  %116 = fdiv float 1.000000e+00, %85
  %117 = fmul float %78, %116
  %118 = fmul float %79, %116
  %119 = bitcast float %86 to i32
  %120 = bitcast float %87 to i32
  %121 = insertelement <2 x i32> undef, i32 %119, i32 0
  %122 = insertelement <2 x i32> %121, i32 %120, i32 1
  %123 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %122, <32 x i8> %63, <16 x i8> %65, i32 2)
  %124 = extractelement <4 x float> %123, i32 0
  %125 = extractelement <4 x float> %123, i32 1
  %126 = extractelement <4 x float> %123, i32 2
  %127 = extractelement <4 x float> %123, i32 3
  %128 = fcmp olt float 0.000000e+00, %126
  %129 = sext i1 %128 to i32
  %130 = bitcast i32 %129 to float
  %131 = bitcast float %130 to i32
  %132 = icmp ne i32 %131, 0
  %. = select i1 %132, float %125, float %124
  %.41 = select i1 %132, float %127, float %125
  %133 = bitcast float %88 to i32
  %134 = bitcast float %89 to i32
  %135 = insertelement <2 x i32> undef, i32 %133, i32 0
  %136 = insertelement <2 x i32> %135, i32 %134, i32 1
  %137 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %136, <32 x i8> %67, <16 x i8> %69, i32 2)
  %138 = extractelement <4 x float> %137, i32 0
  %139 = extractelement <4 x float> %137, i32 1
  %140 = extractelement <4 x float> %137, i32 2
  %141 = extractelement <4 x float> %137, i32 3
  %142 = fcmp olt float 0.000000e+00, %140
  %143 = sext i1 %142 to i32
  %144 = bitcast i32 %143 to float
  %145 = bitcast float %144 to i32
  %146 = icmp ne i32 %145, 0
  %temp24.0 = select i1 %146, float %139, float %138
  %temp25.0 = select i1 %146, float %141, float %139
  %147 = bitcast float %90 to i32
  %148 = bitcast float %91 to i32
  %149 = insertelement <2 x i32> undef, i32 %147, i32 0
  %150 = insertelement <2 x i32> %149, i32 %148, i32 1
  %151 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %150, <32 x i8> %71, <16 x i8> %73, i32 2)
  %152 = extractelement <4 x float> %151, i32 0
  %153 = extractelement <4 x float> %151, i32 1
  %154 = extractelement <4 x float> %151, i32 2
  %155 = extractelement <4 x float> %151, i32 3
  %156 = fcmp olt float 0.000000e+00, %154
  %157 = sext i1 %156 to i32
  %158 = bitcast i32 %157 to float
  %159 = bitcast float %158 to i32
  %160 = icmp ne i32 %159, 0
  %.42 = select i1 %160, float %153, float %152
  %.43 = select i1 %160, float %155, float %153
  %161 = bitcast float %92 to i32
  %162 = bitcast float %93 to i32
  %163 = insertelement <2 x i32> undef, i32 %161, i32 0
  %164 = insertelement <2 x i32> %163, i32 %162, i32 1
  %165 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %164, <32 x i8> %75, <16 x i8> %77, i32 2)
  %166 = extractelement <4 x float> %165, i32 0
  %167 = extractelement <4 x float> %165, i32 1
  %168 = extractelement <4 x float> %165, i32 2
  %169 = extractelement <4 x float> %165, i32 3
  %170 = fcmp olt float 0.000000e+00, %168
  %171 = sext i1 %170 to i32
  %172 = bitcast i32 %171 to float
  %173 = bitcast float %172 to i32
  %174 = icmp ne i32 %173, 0
  %temp28.0 = select i1 %174, float %167, float %166
  %temp29.0 = select i1 %174, float %169, float %167
  %175 = fmul float %., 2.000000e+00
  %176 = fadd float %175, -1.000000e+00
  %177 = fmul float %.41, 2.000000e+00
  %178 = fadd float %177, -1.000000e+00
  %179 = fmul float %temp24.0, 2.000000e+00
  %180 = fadd float %179, -1.000000e+00
  %181 = fmul float %temp25.0, 2.000000e+00
  %182 = fadd float %181, -1.000000e+00
  %183 = fsub float -0.000000e+00, %176
  %184 = fsub float -0.000000e+00, %178
  %185 = fsub float -0.000000e+00, %180
  %186 = fsub float -0.000000e+00, %182
  %187 = fmul float %.42, 2.000000e+00
  %188 = fadd float %187, -1.000000e+00
  %189 = fmul float %.43, 2.000000e+00
  %190 = fadd float %189, -1.000000e+00
  %191 = fmul float %temp28.0, 2.000000e+00
  %192 = fadd float %191, -1.000000e+00
  %193 = fmul float %temp29.0, 2.000000e+00
  %194 = fadd float %193, -1.000000e+00
  %195 = fsub float -0.000000e+00, %188
  %196 = fsub float -0.000000e+00, %190
  %197 = fsub float -0.000000e+00, %192
  %198 = fsub float -0.000000e+00, %194
  %199 = fmul float %183, %27
  %200 = fmul float %184, %27
  %201 = fmul float %185, %28
  %202 = fmul float %186, %28
  %203 = fmul float %195, %29
  %204 = fmul float %196, %29
  %205 = fmul float %197, %30
  %206 = fmul float %198, %30
  %207 = fadd float %199, %203
  %208 = fadd float %200, %204
  %209 = fadd float %201, %205
  %210 = fadd float %202, %206
  %211 = fadd float %207, %209
  %212 = fadd float %208, %210
  %213 = fmul float %211, %114
  %214 = fmul float %212, %114
  %215 = fmul float %213, %213
  %216 = fmul float %214, %214
  %217 = fadd float %215, %216
  %218 = fsub float -0.000000e+00, %217
  %219 = fadd float 0x3FF00068E0000000, %218
  %220 = call float @llvm.AMDIL.clamp.(float %219, float 0.000000e+00, float 1.000000e+00)
  %221 = call float @llvm.AMDGPU.rsq(float %220)
  %222 = fmul float %221, %220
  %223 = fsub float -0.000000e+00, %220
  %224 = call float @llvm.AMDGPU.cndlt(float %223, float %222, float 0.000000e+00)
  %225 = fmul float %213, %213
  %226 = fmul float %214, %214
  %227 = fadd float %226, %225
  %228 = fmul float %224, %224
  %229 = fadd float %227, %228
  %230 = call float @llvm.AMDGPU.rsq(float %229)
  %231 = fmul float %213, %230
  %232 = fmul float %214, %230
  %233 = fmul float %224, %230
  %234 = fsub float -0.000000e+00, %82
  %235 = fadd float %51, %234
  %236 = fsub float -0.000000e+00, %83
  %237 = fadd float %52, %236
  %238 = fsub float -0.000000e+00, %84
  %239 = fadd float %53, %238
  %240 = fmul float %98, %231
  %241 = fmul float %99, %231
  %242 = fmul float %100, %231
  %243 = fmul float %101, %232
  %244 = fadd float %243, %240
  %245 = fmul float %102, %232
  %246 = fadd float %245, %241
  %247 = fmul float %103, %232
  %248 = fadd float %247, %242
  %249 = fmul float %104, %233
  %250 = fadd float %249, %244
  %251 = fmul float %105, %233
  %252 = fadd float %251, %246
  %253 = fmul float %106, %233
  %254 = fadd float %253, %248
  %255 = fadd float %117, %213
  %256 = fadd float %118, %214
  %257 = bitcast float %255 to i32
  %258 = bitcast float %256 to i32
  %259 = bitcast float %32 to i32
  %260 = insertelement <4 x i32> undef, i32 %257, i32 0
  %261 = insertelement <4 x i32> %260, i32 %258, i32 1
  %262 = insertelement <4 x i32> %261, i32 %259, i32 2
  %263 = insertelement <4 x i32> %262, i32 undef, i32 3
  %264 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %263, <32 x i8> %55, <16 x i8> %57, i32 2)
  %265 = extractelement <4 x float> %264, i32 0
  %266 = extractelement <4 x float> %264, i32 1
  %267 = extractelement <4 x float> %264, i32 2
  %268 = extractelement <4 x float> %264, i32 3
  %269 = fmul float %268, 3.200000e+01
  %270 = fadd float %269, -1.600000e+01
  %271 = call float @llvm.AMDIL.exp.(float %270)
  %272 = fmul float %265, %271
  %273 = fmul float %266, %271
  %274 = fmul float %267, %271
  %275 = fmul float %23, %272
  %276 = fmul float %24, %273
  %277 = fmul float %25, %274
  %278 = fmul float %26, %115
  %279 = fmul float %235, %235
  %280 = fmul float %237, %237
  %281 = fadd float %280, %279
  %282 = fmul float %239, %239
  %283 = fadd float %281, %282
  %284 = call float @llvm.AMDGPU.rsq(float %283)
  %285 = fmul float %235, %284
  %286 = fmul float %237, %284
  %287 = fmul float %239, %284
  %288 = fmul float %250, %250
  %289 = fmul float %252, %252
  %290 = fadd float %289, %288
  %291 = fmul float %254, %254
  %292 = fadd float %290, %291
  %293 = call float @llvm.AMDGPU.rsq(float %292)
  %294 = fmul float %250, %293
  %295 = fmul float %252, %293
  %296 = fmul float %254, %293
  %297 = fmul float %285, %294
  %298 = fmul float %286, %295
  %299 = fadd float %298, %297
  %300 = fmul float %287, %296
  %301 = fadd float %299, %300
  %302 = call float @llvm.AMDIL.clamp.(float %301, float 0.000000e+00, float 1.000000e+00)
  %303 = fsub float -0.000000e+00, %302
  %304 = fadd float 1.000000e+00, %303
  %305 = call float @llvm.pow.f32(float %304, float %31)
  %306 = fmul float %278, %305
  %307 = fmul float %80, %80
  %308 = fmul float %81, %81
  %309 = fsub float -0.000000e+00, %307
  %310 = fmul float 2.000000e+00, %80
  %311 = fadd float %310, %309
  %312 = fsub float -0.000000e+00, %308
  %313 = fmul float 2.000000e+00, %81
  %314 = fadd float %313, %312
  %315 = fmul float %80, %39
  %316 = fmul float %311, %40
  %317 = fmul float %81, %41
  %318 = fmul float %314, %42
  %319 = fsub float -0.000000e+00, %306
  %320 = fadd float 1.000000e+00, %319
  %321 = fmul float %35, %320
  %322 = fmul float %35, %320
  %323 = fmul float %35, %320
  %324 = fmul float %36, %320
  %325 = call float @llvm.AMDGPU.lrp(float %321, float %33, float %275)
  %326 = call float @llvm.AMDGPU.lrp(float %322, float %33, float %276)
  %327 = call float @llvm.AMDGPU.lrp(float %323, float %33, float %277)
  %328 = call float @llvm.AMDGPU.lrp(float %324, float %34, float 1.000000e+00)
  %329 = call float @llvm.AMDGPU.lrp(float %317, float %47, float %325)
  %330 = call float @llvm.AMDGPU.lrp(float %317, float %48, float %326)
  %331 = call float @llvm.AMDGPU.lrp(float %317, float %49, float %327)
  %332 = call float @llvm.AMDGPU.lrp(float %318, float %50, float %328)
  %333 = call float @llvm.AMDGPU.lrp(float %315, float %43, float %329)
  %334 = call float @llvm.AMDGPU.lrp(float %315, float %44, float %330)
  %335 = call float @llvm.AMDGPU.lrp(float %315, float %45, float %331)
  %336 = call float @llvm.AMDGPU.lrp(float %316, float %46, float %332)
  %337 = fcmp uge float %333, 0x3E6FFFFE60000000
  %338 = select i1 %337, float %333, float 0x3E6FFFFE60000000
  %339 = fcmp uge float %334, 0x3E6FFFFE60000000
  %340 = select i1 %339, float %334, float 0x3E6FFFFE60000000
  %341 = fcmp uge float %335, 0x3E6FFFFE60000000
  %342 = select i1 %341, float %335, float 0x3E6FFFFE60000000
  %343 = fcmp uge float %338, 6.550400e+04
  %344 = select i1 %343, float 6.550400e+04, float %338
  %345 = fcmp uge float %340, 6.550400e+04
  %346 = select i1 %345, float 6.550400e+04, float %340
  %347 = fcmp uge float %342, 6.550400e+04
  %348 = select i1 %347, float 6.550400e+04, float %342
  %349 = fmul float %336, %37
  %350 = fadd float %349, %38
  %351 = call float @llvm.AMDIL.clamp.(float %350, float 0.000000e+00, float 1.000000e+00)
  %352 = call i32 @llvm.SI.packf16(float %344, float %346)
  %353 = bitcast i32 %352 to float
  %354 = call i32 @llvm.SI.packf16(float %348, float %351)
  %355 = bitcast i32 %354 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %353, float %355, float %353, float %355)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

; Function Attrs: readnone
declare float @llvm.AMDGPU.rsq(float) #2

; Function Attrs: readnone
declare float @llvm.AMDGPU.cndlt(float, float, float) #2

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.samplel.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.exp.(float) #2

; Function Attrs: nounwind readonly
declare float @llvm.pow.f32(float, float) #3

; Function Attrs: readnone
declare float @llvm.AMDGPU.lrp(float, float, float) #2

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }
attributes #3 = { nounwind readonly }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR7 in %vreg4, %VGPR0 in %vreg5, %VGPR1 in %vreg6

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR7 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR7
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 3, 3, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-def>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 3, 3, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 2, 3, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<tied0>, %VGPR1, 2, 3, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 20; mem:LD16[%89](align=8)(tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 40; mem:LD32[%86](tbaa=!"const")
	S_WAITCNT 127
	%VGPR2_VGPR3_VGPR4_VGPR5<def> = IMAGE_SAMPLE_V4_V2 15, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%SGPR8_SGPR9<def> = V_CMP_GT_F32_e64 %VGPR4, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_CNDMASK_B32_e64 %VGPR2, %VGPR3, %SGPR8_SGPR9, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_ADD_F32_e32 %VGPR6<kill>, %VGPR6, %EXEC<imp-use>
	%VGPR6<def> = V_ADD_F32_e32 -1.000000e+00, %VGPR6<kill>, %EXEC<imp-use>
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%22](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 7; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR0, %VGPR6<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_INTERP_P1_F32 %VGPR0, 3, 2, %M0<kill>, %EXEC<imp-use>, %VGPR7_VGPR8<imp-def>
	%VGPR8<def,tied1> = V_INTERP_P2_F32 %VGPR8<tied0>, %VGPR1, 3, 2, %M0<kill>, %EXEC<imp-use>, %VGPR7_VGPR8<imp-use,kill>, %VGPR7_VGPR8<imp-def>
	%VGPR7<def> = V_INTERP_P1_F32 %VGPR0, 2, 2, %M0<kill>, %EXEC<imp-use>, %VGPR7_VGPR8<imp-use,kill>, %VGPR7_VGPR8<imp-def>
	%VGPR7<def,tied1> = V_INTERP_P2_F32 %VGPR7<tied0>, %VGPR1, 2, 2, %M0<kill>, %EXEC<imp-use>, %VGPR7_VGPR8<imp-use,kill>, %VGPR7_VGPR8<imp-def>
	%SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 12; mem:LD16[%77](align=8)(tbaa=!"const")
	%SGPR20_SGPR21_SGPR22_SGPR23_SGPR24_SGPR25_SGPR26_SGPR27<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 24; mem:LD32[%74](tbaa=!"const")
	S_WAITCNT 127
	%VGPR7_VGPR8_VGPR9_VGPR10<def> = IMAGE_SAMPLE_V4_V2 15, 0, 0, 0, 0, 0, 0, 0, %VGPR7_VGPR8<kill>, %SGPR20_SGPR21_SGPR22_SGPR23_SGPR24_SGPR25_SGPR26_SGPR27<kill>, %SGPR16_SGPR17_SGPR18_SGPR19<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%SGPR10_SGPR11<def> = V_CMP_GT_F32_e64 %VGPR9, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR11<def> = V_CNDMASK_B32_e64 %VGPR7, %VGPR8, %SGPR10_SGPR11, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR11<def> = V_ADD_F32_e32 %VGPR11<kill>, %VGPR11, %EXEC<imp-use>
	%VGPR11<def> = V_ADD_F32_e32 -1.000000e+00, %VGPR11<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_ADD_F32_e64 %VGPR11<kill>, 0, 0, 0, 0, 1, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 5; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR11<def> = V_MUL_F32_e32 %SGPR1, %VGPR11<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_SUB_F32_e32 %VGPR11<kill>, %VGPR6<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_INTERP_P1_F32 %VGPR0, 1, 3, %M0<kill>, %EXEC<imp-use>, %VGPR11_VGPR12<imp-def>
	%VGPR12<def,tied1> = V_INTERP_P2_F32 %VGPR12<tied0>, %VGPR1, 1, 3, %M0<kill>, %EXEC<imp-use>, %VGPR11_VGPR12<imp-use,kill>, %VGPR11_VGPR12<imp-def>
	%VGPR11<def> = V_INTERP_P1_F32 %VGPR0, 0, 3, %M0<kill>, %EXEC<imp-use>, %VGPR11_VGPR12<imp-use,kill>, %VGPR11_VGPR12<imp-def>
	%VGPR11<def,tied1> = V_INTERP_P2_F32 %VGPR11<tied0>, %VGPR1, 0, 3, %M0<kill>, %EXEC<imp-use>, %VGPR11_VGPR12<imp-use,kill>, %VGPR11_VGPR12<imp-def>
	%SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 16; mem:LD16[%83](align=8)(tbaa=!"const")
	%SGPR20_SGPR21_SGPR22_SGPR23_SGPR24_SGPR25_SGPR26_SGPR27<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 32; mem:LD32[%80](tbaa=!"const")
	S_WAITCNT 127
	%VGPR11_VGPR12_VGPR13_VGPR14<def> = IMAGE_SAMPLE_V4_V2 15, 0, 0, 0, 0, 0, 0, 0, %VGPR11_VGPR12<kill>, %SGPR20_SGPR21_SGPR22_SGPR23_SGPR24_SGPR25_SGPR26_SGPR27<kill>, %SGPR16_SGPR17_SGPR18_SGPR19<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%SGPR16_SGPR17<def> = V_CMP_GT_F32_e64 %VGPR13, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR15<def> = V_CNDMASK_B32_e64 %VGPR11, %VGPR12, %SGPR16_SGPR17, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR15<def> = V_ADD_F32_e32 %VGPR15<kill>, %VGPR15, %EXEC<imp-use>
	%VGPR15<def> = V_ADD_F32_e32 -1.000000e+00, %VGPR15<kill>, %EXEC<imp-use>
	%SGPR6<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 6; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR15<def> = V_MUL_F32_e32 %SGPR6, %VGPR15<kill>, %EXEC<imp-use>
	%VGPR17<def> = V_INTERP_P1_F32 %VGPR0, 1, 2, %M0<kill>, %EXEC<imp-use>, %VGPR16_VGPR17<imp-def>
	%VGPR17<def,tied1> = V_INTERP_P2_F32 %VGPR17<tied0>, %VGPR1, 1, 2, %M0<kill>, %EXEC<imp-use>, %VGPR16_VGPR17<imp-use,kill>, %VGPR16_VGPR17<imp-def>
	%VGPR16<def> = V_INTERP_P1_F32 %VGPR0, 0, 2, %M0<kill>, %EXEC<imp-use>, %VGPR16_VGPR17<imp-use,kill>, %VGPR16_VGPR17<imp-def>
	%VGPR16<def,tied1> = V_INTERP_P2_F32 %VGPR16<tied0>, %VGPR1, 0, 2, %M0<kill>, %EXEC<imp-use>, %VGPR16_VGPR17<imp-use,kill>, %VGPR16_VGPR17<imp-def>
	%SGPR20_SGPR21_SGPR22_SGPR23<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 8; mem:LD16[%71](align=8)(tbaa=!"const")
	%SGPR24_SGPR25_SGPR26_SGPR27_SGPR28_SGPR29_SGPR30_SGPR31<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 16; mem:LD32[%68](tbaa=!"const")
	S_WAITCNT 127
	%VGPR16_VGPR17_VGPR18_VGPR19<def> = IMAGE_SAMPLE_V4_V2 15, 0, 0, 0, 0, 0, 0, 0, %VGPR16_VGPR17<kill>, %SGPR24_SGPR25_SGPR26_SGPR27_SGPR28_SGPR29_SGPR30_SGPR31<kill>, %SGPR20_SGPR21_SGPR22_SGPR23<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%SGPR18_SGPR19<def> = V_CMP_GT_F32_e64 %VGPR18, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR20<def> = V_CNDMASK_B32_e64 %VGPR16, %VGPR17, %SGPR18_SGPR19, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR20<def> = V_ADD_F32_e32 %VGPR20<kill>, %VGPR20, %EXEC<imp-use>
	%VGPR20<def> = V_ADD_F32_e32 -1.000000e+00, %VGPR20<kill>, %EXEC<imp-use>
	%VGPR20<def> = V_ADD_F32_e64 %VGPR20<kill>, 0, 0, 0, 0, 1, %EXEC<imp-use>
	%SGPR20<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 4; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR20<def> = V_MUL_F32_e32 %SGPR20, %VGPR20<kill>, %EXEC<imp-use>
	%VGPR15<def> = V_SUB_F32_e32 %VGPR20<kill>, %VGPR15<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_ADD_F32_e32 %VGPR15<kill>, %VGPR6<kill>, %EXEC<imp-use>
	%VGPR21<def> = V_INTERP_P1_F32 %VGPR0, 1, 4, %M0<kill>, %EXEC<imp-use>, %VGPR20_VGPR21<imp-def>
	%VGPR21<def,tied1> = V_INTERP_P2_F32 %VGPR21<tied0>, %VGPR1, 1, 4, %M0<kill>, %EXEC<imp-use>, %VGPR20_VGPR21<imp-use,kill>, %VGPR20_VGPR21<imp-def>
	%VGPR20<def> = V_INTERP_P1_F32 %VGPR0, 0, 4, %M0<kill>, %EXEC<imp-use>, %VGPR20_VGPR21<imp-use,kill>, %VGPR20_VGPR21<imp-def>
	%VGPR20<def,tied1> = V_INTERP_P2_F32 %VGPR20<tied0>, %VGPR1, 0, 4, %M0<kill>, %EXEC<imp-use>, %VGPR20_VGPR21<imp-use,kill>, %VGPR20_VGPR21<imp-def>
	%SGPR24_SGPR25_SGPR26_SGPR27<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 4; mem:LD16[%65](align=8)(tbaa=!"const")
	%SGPR28_SGPR29_SGPR30_SGPR31_SGPR32_SGPR33_SGPR34_SGPR35<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 8; mem:LD32[%62](tbaa=!"const")
	S_WAITCNT 127
	%VGPR20_VGPR21<def> = IMAGE_SAMPLE_V2_V2 9, 0, 0, 0, 0, 0, 0, 0, %VGPR20_VGPR21<kill>, %SGPR28_SGPR29_SGPR30_SGPR31_SGPR32_SGPR33_SGPR34_SGPR35<kill>, %SGPR24_SGPR25_SGPR26_SGPR27<kill>, %EXEC<imp-use>
	%VGPR15<def> = V_INTERP_P1_F32 %VGPR0, 2, 4, %M0<kill>, %EXEC<imp-use>
	%VGPR15<def,tied1> = V_INTERP_P2_F32 %VGPR15<kill,tied0>, %VGPR1, 2, 4, %M0<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR15<def> = V_MUL_F32_e32 %VGPR21, %VGPR15<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %VGPR6<kill>, %VGPR15, %EXEC<imp-use>
	%VGPR2<def> = V_CNDMASK_B32_e64 %VGPR3, %VGPR5, %SGPR8_SGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>
	%VGPR2<def> = V_ADD_F32_e32 %VGPR2<kill>, %VGPR2, %EXEC<imp-use>
	%VGPR2<def> = V_ADD_F32_e32 -1.000000e+00, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_CNDMASK_B32_e64 %VGPR8, %VGPR10, %SGPR10_SGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR7_VGPR8_VGPR9_VGPR10<imp-use,kill>
	%VGPR3<def> = V_ADD_F32_e32 %VGPR3<kill>, %VGPR3, %EXEC<imp-use>
	%VGPR3<def> = V_ADD_F32_e32 -1.000000e+00, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_ADD_F32_e64 %VGPR3<kill>, 0, 0, 0, 0, 1, %EXEC<imp-use>
	%VGPR3<def> = V_MUL_F32_e32 %SGPR1<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_SUB_F32_e32 %VGPR3<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_CNDMASK_B32_e64 %VGPR12, %VGPR14, %SGPR16_SGPR17<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR11_VGPR12_VGPR13_VGPR14<imp-use,kill>
	%VGPR3<def> = V_ADD_F32_e32 %VGPR3<kill>, %VGPR3, %EXEC<imp-use>
	%VGPR3<def> = V_ADD_F32_e32 -1.000000e+00, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_MUL_F32_e32 %SGPR6<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_CNDMASK_B32_e64 %VGPR17, %VGPR19, %SGPR18_SGPR19<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR16_VGPR17_VGPR18_VGPR19<imp-use,kill>
	%VGPR4<def> = V_ADD_F32_e32 %VGPR4<kill>, %VGPR4, %EXEC<imp-use>
	%VGPR4<def> = V_ADD_F32_e32 -1.000000e+00, %VGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_ADD_F32_e64 %VGPR4<kill>, 0, 0, 0, 0, 1, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e32 %SGPR20<kill>, %VGPR4<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_SUB_F32_e32 %VGPR4<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_ADD_F32_e32 %VGPR3<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_MUL_F32_e32 %VGPR2<kill>, %VGPR15<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_MUL_F32_e32 %VGPR2, %VGPR2, %EXEC<imp-use>
	%VGPR3<def> = V_MAD_F32 %VGPR6, %VGPR6, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_SUB_F32_e32 1.000100e+00, %VGPR3, %EXEC<imp-use>
	%VGPR4<def> = V_ADD_F32_e64 0, %VGPR4<kill>, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_RSQ_LEGACY_F32_e32 %VGPR4, %EXEC<imp-use>
	%VGPR5<def> = V_MUL_F32_e32 %VGPR5<kill>, %VGPR4, %EXEC<imp-use>
	%VGPR4<def> = V_ADD_F32_e64 %VGPR4<kill>, 0, 0, 0, 0, 1, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = V_CMP_GT_F32_e64 0, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_CNDMASK_B32_e64 0.000000e+00, %VGPR5<kill>, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_MAD_F32 %VGPR4, %VGPR4, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_RSQ_LEGACY_F32_e32 %VGPR3<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MUL_F32_e32 %VGPR2, %VGPR3, %EXEC<imp-use>
	%VGPR7<def> = V_MUL_F32_e32 %VGPR6, %VGPR3, %EXEC<imp-use>
	%VGPR8<def> = V_INTERP_P1_F32 %VGPR0, 1, 5, %M0<kill>, %EXEC<imp-use>
	%VGPR8<def,tied1> = V_INTERP_P2_F32 %VGPR8<kill,tied0>, %VGPR1, 1, 5, %M0<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_F32_e32 %VGPR8<kill>, %VGPR7, %EXEC<imp-use>
	%VGPR9<def> = V_INTERP_P1_F32 %VGPR0, 0, 6, %M0<kill>, %EXEC<imp-use>
	%VGPR9<def,tied1> = V_INTERP_P2_F32 %VGPR9<kill,tied0>, %VGPR1, 0, 6, %M0<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_MAD_F32 %VGPR9<kill>, %VGPR5, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_MUL_F32_e32 %VGPR4<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_INTERP_P1_F32 %VGPR0, 3, 6, %M0<kill>, %EXEC<imp-use>
	%VGPR4<def,tied1> = V_INTERP_P2_F32 %VGPR4<kill,tied0>, %VGPR1, 3, 6, %M0<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR4<kill>, %VGPR3, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_INTERP_P1_F32 %VGPR0, 0, 5, %M0<kill>, %EXEC<imp-use>
	%VGPR8<def,tied1> = V_INTERP_P2_F32 %VGPR8<kill,tied0>, %VGPR1, 0, 5, %M0<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_F32_e32 %VGPR8<kill>, %VGPR7, %EXEC<imp-use>
	%VGPR9<def> = V_INTERP_P1_F32 %VGPR0, 3, 5, %M0<kill>, %EXEC<imp-use>
	%VGPR9<def,tied1> = V_INTERP_P2_F32 %VGPR9<kill,tied0>, %VGPR1, 3, 5, %M0<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_MAD_F32 %VGPR9<kill>, %VGPR5, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_INTERP_P1_F32 %VGPR0, 2, 6, %M0<kill>, %EXEC<imp-use>
	%VGPR9<def,tied1> = V_INTERP_P2_F32 %VGPR9<kill,tied0>, %VGPR1, 2, 6, %M0<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_MAD_F32 %VGPR9<kill>, %VGPR3, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_MUL_F32_e32 %VGPR8, %VGPR8, %EXEC<imp-use>
	%VGPR9<def> = V_MAD_F32 %VGPR4, %VGPR4, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR10<def> = V_INTERP_P1_F32 %VGPR0, 2, 5, %M0<kill>, %EXEC<imp-use>
	%VGPR10<def,tied1> = V_INTERP_P2_F32 %VGPR10<kill,tied0>, %VGPR1, 2, 5, %M0<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MUL_F32_e32 %VGPR10<kill>, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR10<def> = V_INTERP_P1_F32 %VGPR0, 1, 6, %M0<kill>, %EXEC<imp-use>
	%VGPR10<def,tied1> = V_INTERP_P2_F32 %VGPR10<kill,tied0>, %VGPR1, 1, 6, %M0<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR10<kill>, %VGPR5<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_INTERP_P1_F32 %VGPR0, 0, 7, %M0<kill>, %EXEC<imp-use>
	%VGPR7<def,tied1> = V_INTERP_P2_F32 %VGPR7<kill,tied0>, %VGPR1, 0, 7, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_MAD_F32 %VGPR7<kill>, %VGPR3<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR3, %VGPR3, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_RSQ_LEGACY_F32_e32 %VGPR5<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e32 %VGPR4<kill>, %VGPR5, %EXEC<imp-use>
	%VGPR7<def> = V_MUL_F32_e32 %VGPR8<kill>, %VGPR5, %EXEC<imp-use>
	%VGPR8<def> = V_INTERP_P1_F32 %VGPR0, 1, 1, %M0<kill>, %EXEC<imp-use>
	%VGPR8<def,tied1> = V_INTERP_P2_F32 %VGPR8<kill,tied0>, %VGPR1, 1, 1, %M0<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 49; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR8<def> = V_SUB_F32_e32 %SGPR0<kill>, %VGPR8<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_INTERP_P1_F32 %VGPR0, 0, 1, %M0<kill>, %EXEC<imp-use>
	%VGPR9<def,tied1> = V_INTERP_P2_F32 %VGPR9<kill,tied0>, %VGPR1, 0, 1, %M0<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 48; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR9<def> = V_SUB_F32_e32 %SGPR0<kill>, %VGPR9<kill>, %EXEC<imp-use>
	%VGPR10<def> = V_MUL_F32_e32 %VGPR9, %VGPR9, %EXEC<imp-use>
	%VGPR10<def> = V_MAD_F32 %VGPR8, %VGPR8, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR11<def> = V_INTERP_P1_F32 %VGPR0, 2, 1, %M0<kill>, %EXEC<imp-use>
	%VGPR11<def,tied1> = V_INTERP_P2_F32 %VGPR11<kill,tied0>, %VGPR1, 2, 1, %M0<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 50; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR11<def> = V_SUB_F32_e32 %SGPR0<kill>, %VGPR11<kill>, %EXEC<imp-use>
	%VGPR10<def> = V_MAD_F32 %VGPR11, %VGPR11, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR10<def> = V_RSQ_LEGACY_F32_e32 %VGPR10<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_MUL_F32_e32 %VGPR9<kill>, %VGPR10, %EXEC<imp-use>
	%VGPR7<def> = V_MUL_F32_e32 %VGPR9<kill>, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_F32_e32 %VGPR8<kill>, %VGPR10, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR8<kill>, %VGPR4<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_MUL_F32_e32 %VGPR3<kill>, %VGPR5<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MUL_F32_e32 %VGPR11<kill>, %VGPR10<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_MAD_F32 %VGPR5<kill>, %VGPR3<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_ADD_F32_e64 0, %VGPR3<kill>, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_SUB_F32_e32 1.000000e+00, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_LOG_F32_e32 %VGPR3<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 8; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_LEGACY_F32_e32 %SGPR0<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_EXP_F32_e32 %VGPR3<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_INTERP_P1_F32 %VGPR0, 3, 4, %M0<kill>, %EXEC<imp-use>
	%VGPR4<def,tied1> = V_INTERP_P2_F32 %VGPR4<kill,tied0>, %VGPR1, 3, 4, %M0<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e32 %VGPR20, %VGPR4<kill>, %EXEC<imp-use>, %VGPR20_VGPR21<imp-use,kill>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 3; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR4<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR4<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_MUL_F32_e32 %VGPR4<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_SUB_F32_e32 1.000000e+00, %VGPR3<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 14; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR4<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR3, %EXEC<imp-use>
	%VGPR5<def> = V_SUB_F32_e32 1.000000e+00, %VGPR4, %EXEC<imp-use>
	%VGPR7<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR7<def,tied1> = V_INTERP_P2_F32 %VGPR7<kill,tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_INTERP_P1_F32 %VGPR0, 3, 1, %M0<kill>, %EXEC<imp-use>
	%VGPR8<def,tied1> = V_INTERP_P2_F32 %VGPR8<kill,tied0>, %VGPR1, 3, 1, %M0<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_RCP_F32_e32 %VGPR8<kill>, %EXEC<imp-use>
	%VGPR10<def> = V_MAD_F32 %VGPR7<kill>, %VGPR8, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-def>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<kill,tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_MAD_F32 %VGPR2<kill>, %VGPR8<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-def>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 10; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR11<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-def>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%59](align=8)(tbaa=!"const")
	%SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%56](tbaa=!"const")
	S_WAITCNT 127
	%VGPR6_VGPR7_VGPR8_VGPR9<def> = IMAGE_SAMPLE_L_V4_V4 15, 0, 0, 0, 0, 0, 0, 0, %VGPR9_VGPR10_VGPR11_VGPR12<kill>, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23<kill>, %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_MOV_B32_e32 -1.600000e+01, %EXEC<imp-use>
	%VGPR10<def> = V_MOV_B32_e32 3.200000e+01, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR2<def> = V_MAD_F32 %VGPR9, %VGPR10<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR2<def> = V_EXP_F32_e32 %VGPR2<kill>, %EXEC<imp-use>
	%VGPR10<def> = V_MUL_F32_e32 %VGPR7, %VGPR2, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 1; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR10<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR10<kill>, %EXEC<imp-use>
	%VGPR10<def> = V_MUL_F32_e32 %VGPR5, %VGPR10<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 12; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %VGPR4, %SGPR0, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR11<def> = V_INTERP_P1_F32 %VGPR0, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR11<def,tied1> = V_INTERP_P2_F32 %VGPR11<kill,tied0>, %VGPR1, 3, 0, %M0<kill>, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 22; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR12<def> = V_MUL_F32_e32 %SGPR1<kill>, %VGPR11, %EXEC<imp-use>
	%VGPR13<def> = V_SUB_F32_e32 1.000000e+00, %VGPR12, %EXEC<imp-use>
	%VGPR10<def> = V_MUL_F32_e32 %VGPR13, %VGPR10<kill>, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 29; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %VGPR12, %SGPR1<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR14<def> = V_INTERP_P1_F32 %VGPR0, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR14<def,tied1> = V_INTERP_P2_F32 %VGPR14<kill,tied0>, %VGPR1, 2, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 20; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR0<def> = V_MUL_F32_e32 %SGPR1<kill>, %VGPR14, %EXEC<imp-use>
	%VGPR1<def> = V_SUB_F32_e32 1.000000e+00, %VGPR0, %EXEC<imp-use>
	%VGPR10<def> = V_MUL_F32_e32 %VGPR1, %VGPR10<kill>, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 25; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR10<def> = V_MAD_F32 %VGPR0, %SGPR1<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR15<def> = V_MOV_B32_e32 5.960460e-08, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR10, %VGPR15, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_U_F32_e64 %VGPR10, %VGPR10, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_OR_B64 %SGPR2_SGPR3<kill>, %SGPR4_SGPR5<kill>
	%VGPR10<def> = V_CNDMASK_B32_e64 %VGPR15, %VGPR10<kill>, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR16<def> = V_MOV_B32_e32 6.550400e+04, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR10, %VGPR16, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_U_F32_e64 %VGPR10, %VGPR10, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_OR_B64 %SGPR2_SGPR3<kill>, %SGPR4_SGPR5<kill>
	%VGPR10<def> = V_CNDMASK_B32_e64 %VGPR10<kill>, %VGPR16, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR17<def> = V_MUL_F32_e32 %VGPR6, %VGPR2, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 0; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR17<def> = V_MUL_F32_e32 %SGPR1<kill>, %VGPR17<kill>, %EXEC<imp-use>
	%VGPR17<def> = V_MUL_F32_e32 %VGPR5, %VGPR17<kill>, %EXEC<imp-use>
	%VGPR17<def> = V_MAD_F32 %VGPR4, %SGPR0, %VGPR17<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR17<def> = V_MUL_F32_e32 %VGPR13, %VGPR17<kill>, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 28; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR17<def> = V_MAD_F32 %VGPR12, %SGPR1<kill>, %VGPR17<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR17<def> = V_MUL_F32_e32 %VGPR1, %VGPR17<kill>, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 24; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR17<def> = V_MAD_F32 %VGPR0, %SGPR1<kill>, %VGPR17<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR17, %VGPR15, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_U_F32_e64 %VGPR17, %VGPR17, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_OR_B64 %SGPR2_SGPR3<kill>, %SGPR4_SGPR5<kill>
	%VGPR17<def> = V_CNDMASK_B32_e64 %VGPR15, %VGPR17<kill>, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR17, %VGPR16, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_U_F32_e64 %VGPR17, %VGPR17, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_OR_B64 %SGPR2_SGPR3<kill>, %SGPR4_SGPR5<kill>
	%VGPR17<def> = V_CNDMASK_B32_e64 %VGPR17<kill>, %VGPR16, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR10<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR17<kill>, %VGPR10<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_MUL_F32_e32 %VGPR8, %VGPR2<kill>, %EXEC<imp-use>, %VGPR6_VGPR7_VGPR8_VGPR9<imp-use,kill>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 2; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR1<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_MUL_F32_e32 %VGPR5<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_MAD_F32 %VGPR4<kill>, %SGPR0<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR2<def> = V_MUL_F32_e32 %VGPR13<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 30; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %VGPR12<kill>, %SGPR0<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_MUL_F32_e32 %VGPR1<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 26; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR0<def> = V_MAD_F32 %VGPR0<kill>, %SGPR0<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = V_CMP_GE_F32_e64 %VGPR0, %VGPR15, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_U_F32_e64 %VGPR0, %VGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_OR_B64 %SGPR0_SGPR1<kill>, %SGPR2_SGPR3<kill>
	%VGPR0<def> = V_CNDMASK_B32_e64 %VGPR15<kill>, %VGPR0<kill>, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = V_CMP_GE_F32_e64 %VGPR0, %VGPR16, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_U_F32_e64 %VGPR0, %VGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_OR_B64 %SGPR0_SGPR1<kill>, %SGPR2_SGPR3<kill>
	%VGPR0<def> = V_CNDMASK_B32_e64 %VGPR0<kill>, %VGPR16<kill>, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 15; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_SUB_F32_e32 1.000000e+00, %VGPR1, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 13; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR1<kill>, %SGPR0<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR2<def> = V_MUL_F32_e32 %VGPR11, %VGPR11, %EXEC<imp-use>
	%VGPR3<def> = V_ADD_F32_e32 %VGPR11<kill>, %VGPR11, %EXEC<imp-use>
	%VGPR2<def> = V_SUB_F32_e32 %VGPR3<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 23; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_SUB_F32_e32 1.000000e+00, %VGPR2, %EXEC<imp-use>
	%VGPR1<def> = V_MUL_F32_e32 %VGPR3<kill>, %VGPR1<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 31; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR2<kill>, %SGPR0<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR2<def> = V_MUL_F32_e32 %VGPR14, %VGPR14, %EXEC<imp-use>
	%VGPR3<def> = V_ADD_F32_e32 %VGPR14<kill>, %VGPR14, %EXEC<imp-use>
	%VGPR2<def> = V_SUB_F32_e32 %VGPR3<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 21; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_SUB_F32_e32 1.000000e+00, %VGPR2, %EXEC<imp-use>
	%VGPR1<def> = V_MUL_F32_e32 %VGPR3<kill>, %VGPR1<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 27; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %VGPR2<kill>, %SGPR0<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15, 16; mem:LD4[<unknown>]
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR12_SGPR13_SGPR14_SGPR15<kill>, 17; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR2<def> = V_MOV_B32_e32 %SGPR1<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_MAD_F32 %VGPR1<kill>, %SGPR0<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_ADD_F32_e64 0, %VGPR1<kill>, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0<kill>, %VGPR1<kill>, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR10<kill>, %VGPR0<kill>, %VGPR10, %VGPR0, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_WQM_B64 exec, exec                                                         ; BEFE0A7E
	S_MOV_B32 m0, s7                                                             ; BEFC0307
	V_INTERP_P1_F32 v3, v0, 3, 3, [m0]                                           ; C80C0F00
	V_INTERP_P2_F32 v3, [v3], v1, 3, 3, [m0]                                     ; C80D0F01
	V_INTERP_P1_F32 v2, v0, 2, 3, [m0]                                           ; C8080E00
	V_INTERP_P2_F32 v2, [v2], v1, 2, 3, [m0]                                     ; C8090E01
	S_LOAD_DWORDX4 s[8:11], s[2:3], 20                                           ; C0840314
	S_LOAD_DWORDX8 s[12:19], s[4:5], 40                                          ; C0C60528
	S_WAITCNT lgkmcnt(0)                                                         ; BF8C007F
	IMAGE_SAMPLE v[2:5], 15, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[12:19], s[8:11]      ; F0800F00 00430202
	S_WAITCNT vmcnt(0)                                                           ; BF8C0770
	V_CMP_GT_F32_e64 s[8:9], v4, 0.000000e+00, 0, 0, 0, 0                        ; D0080008 02010104
	V_CNDMASK_B32_e64 v6, v2, v3, s[8:9], 0, 0, 0, 0                             ; D2000006 00220702
	V_ADD_F32_e32 v6, v6, v6                                                     ; 060C0D06
	V_ADD_F32_e32 v6, -1.000000e+00, v6                                          ; 060C0CF3
	S_LOAD_DWORDX4 s[12:15], s[0:1], 0                                           ; C0860100
	S_WAITCNT lgkmcnt(0)                                                         ; BF8C007F
	S_BUFFER_LOAD_DWORD s0, s[12:15], 7                                          ; C2000D07
	S_WAITCNT lgkmcnt(0)                                                         ; BF8C007F
	V_MUL_F32_e32 v6, s0, v6                                                     ; 100C0C00
	V_INTERP_P1_F32 v8, v0, 3, 2, [m0]                                           ; C8200B00
	V_INTERP_P2_F32 v8, [v8], v1, 3, 2, [m0]                                     ; C8210B01
	V_INTERP_P1_F32 v7, v0, 2, 2, [m0]                                           ; C81C0A00
	V_INTERP_P2_F32 v7, [v7], v1, 2, 2, [m0]                                     ; C81D0A01
	S_LOAD_DWORDX4 s[16:19], s[2:3], 12                                          ; C088030C
	S_LOAD_DWORDX8 s[20:27], s[4:5], 24                                          ; C0CA0518
	S_WAITCNT lgkmcnt(0)                                                         ; BF8C007F
	IMAGE_SAMPLE v[7:10], 15, 0, 0, 0, 0, 0, 0, 0, v[7:8], s[20:27], s[16:19]    ; F0800F00 00850707
	S_WAITCNT vmcnt(0)                                                           ; BF8C0770
	V_CMP_GT_F32_e64 s[10:11], v9, 0.000000e+00, 0, 0, 0, 0                      ; D008000A 02010109
	V_CNDMASK_B32_e64 v11, v7, v8, s[10:11], 0, 0, 0, 0                          ; D200000B 002A1107
	V_ADD_F32_e32 v11, v11, v11                                                  ; 0616170B
	V_ADD_F32_e32 v11, -1.000000e+00, v11                                        ; 061616F3
	V_ADD_F32_e64 v11, v11, 0, 0, 0, 0, 1                                        ; D206000B 2201010B
	S_BUFFER_LOAD_DWORD s1, s[12:15], 5                                          ; C2008D05
	S_WAITCNT lgkmcnt(0)                                                         ; BF8C007F
	V_MUL_F32_e32 v11, s1, v11                                                   ; 10161601
	V_SUB_F32_e32 v6, v11, v6                                                    ; 080C0D0B
	V_INTERP_P1_F32 v12, v0, 1, 3, [m0]                                          ; C8300D00
	V_INTERP_P2_F32 v12, [v12], v1, 1, 3, [m0]                                   ; C8310D01
	V_INTERP_P1_F32 v11, v0, 0, 3, [m0]                                          ; C82C0C00
	V_INTERP_P2_F32 v11, [v11], v1, 0, 3, [m0]                                   ; C82D0C01
	S_LOAD_DWORDX4 s[16:19], s[2:3], 16                                          ; C0880310
	S_LOAD_DWORDX8 s[20:27], s[4:5], 32                                          ; C0CA0520
	S_WAITCNT lgkmcnt(0)                                                         ; BF8C007F
	IMAGE_SAMPLE v[11:14], 15, 0, 0, 0, 0, 0, 0, 0, v[11:12], s[20:27], s[16:19] ; F0800F00 00850B0B
	S_WAITCNT vmcnt(0)                                                           ; BF8C0770
	V_CMP_GT_F32_e64 s[16:17], v13, 0.000000e+00, 0, 0, 0, 0                     ; D0080010 0201010D
	V_CNDMASK_B32_e64 v15, v11, v12, s[16:17], 0, 0, 0, 0                        ; D200000F 0042190B
	V_ADD_F32_e32 v15, v15, v15                                                  ; 061E1F0F
	V_ADD_F32_e32 v15, -1.000000e+00, v15                                        ; 061E1EF3
	S_BUFFER_LOAD_DWORD s6, s[12:15], 6                                          ; C2030D06
	S_WAITCNT lgkmcnt(0)                                                         ; BF8C007F
	V_MUL_F32_e32 v15, s6, v15                                                   ; 101E1E06
	V_INTERP_P1_F32 v17, v0, 1, 2, [m0]                                          ; C8440900
	V_INTERP_P2_F32 v17, [v17], v1, 1, 2, [m0]                                   ; C8450901
	V_INTERP_P1_F32 v16, v0, 0, 2, [m0]                                          ; C8400800
	V_INTERP_P2_F32 v16, [v16], v1, 0, 2, [m0]                                   ; C8410801
	S_LOAD_DWORDX4 s[20:23], s[2:3], 8                                           ; C08A0308
	S_LOAD_DWORDX8 s[24:31], s[4:5], 16                                          ; C0CC0510
	S_WAITCNT lgkmcnt(0)                                                         ; BF8C007F
	IMAGE_SAMPLE v[16:19], 15, 0, 0, 0, 0, 0, 0, 0, v[16:17], s[24:31], s[20:23] ; F0800F00 00A61010
	S_WAITCNT vmcnt(0)                                                           ; BF8C0770
	V_CMP_GT_F32_e64 s[18:19], v18, 0.000000e+00, 0, 0, 0, 0                     ; D0080012 02010112
	V_CNDMASK_B32_e64 v20, v16, v17, s[18:19], 0, 0, 0, 0                        ; D2000014 004A2310
	V_ADD_F32_e32 v20, v20, v20                                                  ; 06282914
	V_ADD_F32_e32 v20, -1.000000e+00, v20                                        ; 062828F3
	V_ADD_F32_e64 v20, v20, 0, 0, 0, 0, 1                                        ; D2060014 22010114
	S_BUFFER_LOAD_DWORD s20, s[12:15], 4                                         ; C20A0D04
	S_WAITCNT lgkmcnt(0)                                                         ; BF8C007F
	V_MUL_F32_e32 v20, s20, v20                                                  ; 10282814
	V_SUB_F32_e32 v15, v20, v15                                                  ; 081E1F14
	V_ADD_F32_e32 v6, v15, v6                                                    ; 060C0D0F
	V_INTERP_P1_F32 v21, v0, 1, 4, [m0]                                          ; C8541100
	V_INTERP_P2_F32 v21, [v21], v1, 1, 4, [m0]                                   ; C8551101
	V_INTERP_P1_F32 v20, v0, 0, 4, [m0]                                          ; C8501000
	V_INTERP_P2_F32 v20, [v20], v1, 0, 4, [m0]                                   ; C8511001
	S_LOAD_DWORDX4 s[24:27], s[2:3], 4                                           ; C08C0304
	S_LOAD_DWORDX8 s[28:35], s[4:5], 8                                           ; C0CE0508
	S_WAITCNT lgkmcnt(0)                                                         ; BF8C007F
	IMAGE_SAMPLE v[20:21], 9, 0, 0, 0, 0, 0, 0, 0, v[20:21], s[28:35], s[24:27]  ; F0800900 00C71414
	V_INTERP_P1_F32 v15, v0, 2, 4, [m0]                                          ; C83C1200
	V_INTERP_P2_F32 v15, [v15], v1, 2, 4, [m0]                                   ; C83D1201
	S_WAITCNT vmcnt(0)                                                           ; BF8C0770
	V_MUL_F32_e32 v15, v21, v15                                                  ; 101E1F15
	V_MUL_F32_e32 v6, v6, v15                                                    ; 100C1F06
	V_CNDMASK_B32_e64 v2, v3, v5, s[8:9], 0, 0, 0, 0                             ; D2000002 00220B03
	V_ADD_F32_e32 v2, v2, v2                                                     ; 06040502
	V_ADD_F32_e32 v2, -1.000000e+00, v2                                          ; 060404F3
	V_MUL_F32_e32 v2, s0, v2                                                     ; 10040400
	V_CNDMASK_B32_e64 v3, v8, v10, s[10:11], 0, 0, 0, 0                          ; D2000003 002A1508
	V_ADD_F32_e32 v3, v3, v3                                                     ; 06060703
	V_ADD_F32_e32 v3, -1.000000e+00, v3                                          ; 060606F3
	V_ADD_F32_e64 v3, v3, 0, 0, 0, 0, 1                                          ; D2060003 22010103
	V_MUL_F32_e32 v3, s1, v3                                                     ; 10060601
	V_SUB_F32_e32 v2, v3, v2                                                     ; 08040503
	V_CNDMASK_B32_e64 v3, v12, v14, s[16:17], 0, 0, 0, 0                         ; D2000003 00421D0C
	V_ADD_F32_e32 v3, v3, v3                                                     ; 06060703
	V_ADD_F32_e32 v3, -1.000000e+00, v3                                          ; 060606F3
	V_MUL_F32_e32 v3, s6, v3                                                     ; 10060606
	V_CNDMASK_B32_e64 v4, v17, v19, s[18:19], 0, 0, 0, 0                         ; D2000004 004A2711
	V_ADD_F32_e32 v4, v4, v4                                                     ; 06080904
	V_ADD_F32_e32 v4, -1.000000e+00, v4                                          ; 060808F3
	V_ADD_F32_e64 v4, v4, 0, 0, 0, 0, 1                                          ; D2060004 22010104
	V_MUL_F32_e32 v4, s20, v4                                                    ; 10080814
	V_SUB_F32_e32 v3, v4, v3                                                     ; 08060704
	V_ADD_F32_e32 v2, v3, v2                                                     ; 06040503
	V_MUL_F32_e32 v2, v2, v15                                                    ; 10041F02
	V_MUL_F32_e32 v3, v2, v2                                                     ; 10060502
	V_MAD_F32 v3, v6, v6, v3, 0, 0, 0, 0                                         ; D2820003 040E0D06
	V_SUB_F32_e32 v4, 1.000100e+00, v3                                           ; 080806FF 3F800347
	V_ADD_F32_e64 v4, 0, v4, 0, 1, 0, 0                                          ; D2060804 02020880
	V_RSQ_LEGACY_F32_e32 v5, v4                                                  ; 7E0A5B04
	V_MUL_F32_e32 v5, v5, v4                                                     ; 100A0905
	V_ADD_F32_e64 v4, v4, 0, 0, 0, 0, 1                                          ; D2060004 22010104
	V_CMP_GT_F32_e64 s[0:1], 0, v4, 0, 0, 0, 0                                   ; D0080000 02020880
	V_CNDMASK_B32_e64 v4, 0.000000e+00, v5, s[0:1], 0, 0, 0, 0                   ; D2000004 00020A80
	V_MAD_F32 v3, v4, v4, v3, 0, 0, 0, 0                                         ; D2820003 040E0904
	V_RSQ_LEGACY_F32_e32 v3, v3                                                  ; 7E065B03
	V_MUL_F32_e32 v5, v2, v3                                                     ; 100A0702
	V_MUL_F32_e32 v7, v6, v3                                                     ; 100E0706
	V_INTERP_P1_F32 v8, v0, 1, 5, [m0]                                           ; C8201500
	V_INTERP_P2_F32 v8, [v8], v1, 1, 5, [m0]                                     ; C8211501
	V_MUL_F32_e32 v8, v8, v7                                                     ; 10100F08
	V_INTERP_P1_F32 v9, v0, 0, 6, [m0]                                           ; C8241800
	V_INTERP_P2_F32 v9, [v9], v1, 0, 6, [m0]                                     ; C8251801
	V_MAD_F32 v8, v9, v5, v8, 0, 0, 0, 0                                         ; D2820008 04220B09
	V_MUL_F32_e32 v3, v4, v3                                                     ; 10060704
	V_INTERP_P1_F32 v4, v0, 3, 6, [m0]                                           ; C8101B00
	V_INTERP_P2_F32 v4, [v4], v1, 3, 6, [m0]                                     ; C8111B01
	V_MAD_F32 v4, v4, v3, v8, 0, 0, 0, 0                                         ; D2820004 04220704
	V_INTERP_P1_F32 v8, v0, 0, 5, [m0]                                           ; C8201400
	V_INTERP_P2_F32 v8, [v8], v1, 0, 5, [m0]                                     ; C8211401
	V_MUL_F32_e32 v8, v8, v7                                                     ; 10100F08
	V_INTERP_P1_F32 v9, v0, 3, 5, [m0]                                           ; C8241700
	V_INTERP_P2_F32 v9, [v9], v1, 3, 5, [m0]                                     ; C8251701
	V_MAD_F32 v8, v9, v5, v8, 0, 0, 0, 0                                         ; D2820008 04220B09
	V_INTERP_P1_F32 v9, v0, 2, 6, [m0]                                           ; C8241A00
	V_INTERP_P2_F32 v9, [v9], v1, 2, 6, [m0]                                     ; C8251A01
	V_MAD_F32 v8, v9, v3, v8, 0, 0, 0, 0                                         ; D2820008 04220709
	V_MUL_F32_e32 v9, v8, v8                                                     ; 10121108
	V_MAD_F32 v9, v4, v4, v9, 0, 0, 0, 0                                         ; D2820009 04260904
	V_INTERP_P1_F32 v10, v0, 2, 5, [m0]                                          ; C8281600
	V_INTERP_P2_F32 v10, [v10], v1, 2, 5, [m0]                                   ; C8291601
	V_MUL_F32_e32 v7, v10, v7                                                    ; 100E0F0A
	V_INTERP_P1_F32 v10, v0, 1, 6, [m0]                                          ; C8281900
	V_INTERP_P2_F32 v10, [v10], v1, 1, 6, [m0]                                   ; C8291901
	V_MAD_F32 v5, v10, v5, v7, 0, 0, 0, 0                                        ; D2820005 041E0B0A
	V_INTERP_P1_F32 v7, v0, 0, 7, [m0]                                           ; C81C1C00
	V_INTERP_P2_F32 v7, [v7], v1, 0, 7, [m0]                                     ; C81D1C01
	V_MAD_F32 v3, v7, v3, v5, 0, 0, 0, 0                                         ; D2820003 04160707
	V_MAD_F32 v5, v3, v3, v9, 0, 0, 0, 0                                         ; D2820005 04260703
	V_RSQ_LEGACY_F32_e32 v5, v5                                                  ; 7E0A5B05
	V_MUL_F32_e32 v4, v4, v5                                                     ; 10080B04
	V_MUL_F32_e32 v7, v8, v5                                                     ; 100E0B08
	V_INTERP_P1_F32 v8, v0, 1, 1, [m0]                                           ; C8200500
	V_INTERP_P2_F32 v8, [v8], v1, 1, 1, [m0]                                     ; C8210501
	S_BUFFER_LOAD_DWORD s0, s[12:15], 49                                         ; C2000D31
	S_WAITCNT lgkmcnt(0)                                                         ; BF8C007F
	V_SUB_F32_e32 v8, s0, v8                                                     ; 08101000
	V_INTERP_P1_F32 v9, v0, 0, 1, [m0]                                           ; C8240400
	V_INTERP_P2_F32 v9, [v9], v1, 0, 1, [m0]                                     ; C8250401
	S_BUFFER_LOAD_DWORD s0, s[12:15], 48                                         ; C2000D30
	S_WAITCNT lgkmcnt(0)                                                         ; BF8C007F
	V_SUB_F32_e32 v9, s0, v9                                                     ; 08121200
	V_MUL_F32_e32 v10, v9, v9                                                    ; 10141309
	V_MAD_F32 v10, v8, v8, v10, 0, 0, 0, 0                                       ; D282000A 042A1108
	V_INTERP_P1_F32 v11, v0, 2, 1, [m0]                                          ; C82C0600
	V_INTERP_P2_F32 v11, [v11], v1, 2, 1, [m0]                                   ; C82D0601
	S_BUFFER_LOAD_DWORD s0, s[12:15], 50                                         ; C2000D32
	S_WAITCNT lgkmcnt(0)                                                         ; BF8C007F
	V_SUB_F32_e32 v11, s0, v11                                                   ; 08161600
	V_MAD_F32 v10, v11, v11, v10, 0, 0, 0, 0                                     ; D282000A 042A170B
	V_RSQ_LEGACY_F32_e32 v10, v10                                                ; 7E145B0A
	V_MUL_F32_e32 v9, v9, v10                                                    ; 10121509
	V_MUL_F32_e32 v7, v9, v7                                                     ; 100E0F09
	V_MUL_F32_e32 v8, v8, v10                                                    ; 10101508
	V_MAD_F32 v4, v8, v4, v7, 0, 0, 0, 0                                         ; D2820004 041E0908
	V_MUL_F32_e32 v3, v3, v5                                                     ; 10060B03
	V_MUL_F32_e32 v5, v11, v10                                                   ; 100A150B
	V_MAD_F32 v3, v5, v3, v4, 0, 0, 0, 0                                         ; D2820003 04120705
	V_ADD_F32_e64 v3, 0, v3, 0, 1, 0, 0                                          ; D2060803 02020680
	V_SUB_F32_e32 v3, 1.000000e+00, v3                                           ; 080606F2
	V_LOG_F32_e32 v3, v3                                                         ; 7E064F03
	S_BUFFER_LOAD_DWORD s0, s[12:15], 8                                          ; C2000D08
	S_WAITCNT lgkmcnt(0)                                                         ; BF8C007F
	V_MUL_LEGACY_F32_e32 v3, s0, v3                                              ; 0E060600
	V_EXP_F32_e32 v3, v3                                                         ; 7E064B03
	V_INTERP_P1_F32 v4, v0, 3, 4, [m0]                                           ; C8101300
	V_INTERP_P2_F32 v4, [v4], v1, 3, 4, [m0]                                     ; C8111301
	V_MUL_F32_e32 v4, v20, v4                                                    ; 10080914
	S_BUFFER_LOAD_DWORD s0, s[12:15], 3                                          ; C2000D03
	S_WAITCNT lgkmcnt(0)                                                         ; BF8C007F
	V_MUL_F32_e32 v4, s0, v4                                                     ; 10080800
	V_MUL_F32_e32 v3, v4, v3                                                     ; 10060704
	V_SUB_F32_e32 v3, 1.000000e+00, v3                                           ; 080606F2
	S_BUFFER_LOAD_DWORD s0, s[12:15], 14                                         ; C2000D0E
	S_WAITCNT lgkmcnt(0)                                                         ; BF8C007F
	V_MUL_F32_e32 v4, s0, v3                                                     ; 10080600
	V_SUB_F32_e32 v5, 1.000000e+00, v4                                           ; 080A08F2
	V_INTERP_P1_F32 v7, v0, 1, 0, [m0]                                           ; C81C0100
	V_INTERP_P2_F32 v7, [v7], v1, 1, 0, [m0]                                     ; C81D0101
	V_INTERP_P1_F32 v8, v0, 3, 1, [m0]                                           ; C8200700
	V_INTERP_P2_F32 v8, [v8], v1, 3, 1, [m0]                                     ; C8210701
	V_RCP_F32_e32 v8, v8                                                         ; 7E105508
	V_MAD_F32 v10, v7, v8, v2, 0, 0, 0, 0                                        ; D282000A 040A1107
	V_INTERP_P1_F32 v2, v0, 0, 0, [m0]                                           ; C8080000
	V_INTERP_P2_F32 v2, [v2], v1, 0, 0, [m0]                                     ; C8090001
	V_MAD_F32 v9, v2, v8, v6, 0, 0, 0, 0                                         ; D2820009 041A1102
	S_BUFFER_LOAD_DWORD s0, s[12:15], 10                                         ; C2000D0A
	S_WAITCNT lgkmcnt(0)                                                         ; BF8C007F
	V_MOV_B32_e32 v11, s0                                                        ; 7E160200
	S_LOAD_DWORDX4 s[0:3], s[2:3], 0                                             ; C0800300
	S_LOAD_DWORDX8 s[16:23], s[4:5], 0                                           ; C0C80500
	S_WAITCNT lgkmcnt(0)                                                         ; BF8C007F
	IMAGE_SAMPLE_L v[6:9], 15, 0, 0, 0, 0, 0, 0, 0, v[9:12], s[16:23], s[0:3]    ; F0900F00 00040609
	V_MOV_B32_e32 v2, -1.600000e+01                                              ; 7E0402FF C1800000
	V_MOV_B32_e32 v10, 3.200000e+01                                              ; 7E1402FF 42000000
	S_WAITCNT vmcnt(0)                                                           ; BF8C0770
	V_MAD_F32 v2, v9, v10, v2, 0, 0, 0, 0                                        ; D2820002 040A1509
	V_EXP_F32_e32 v2, v2                                                         ; 7E044B02
	V_MUL_F32_e32 v10, v7, v2                                                    ; 10140507
	S_BUFFER_LOAD_DWORD s0, s[12:15], 1                                          ; C2000D01
	S_WAITCNT lgkmcnt(0)                                                         ; BF8C007F
	V_MUL_F32_e32 v10, s0, v10                                                   ; 10141400
	V_MUL_F32_e32 v10, v5, v10                                                   ; 10141505
	S_BUFFER_LOAD_DWORD s0, s[12:15], 12                                         ; C2000D0C
	S_WAITCNT lgkmcnt(0)                                                         ; BF8C007F
	V_MAD_F32 v10, v4, s0, v10, 0, 0, 0, 0                                       ; D282000A 04280104
	V_INTERP_P1_F32 v11, v0, 3, 0, [m0]                                          ; C82C0300
	V_INTERP_P2_F32 v11, [v11], v1, 3, 0, [m0]                                   ; C82D0301
	S_BUFFER_LOAD_DWORD s1, s[12:15], 22                                         ; C2008D16
	S_WAITCNT lgkmcnt(0)                                                         ; BF8C007F
	V_MUL_F32_e32 v12, s1, v11                                                   ; 10181601
	V_SUB_F32_e32 v13, 1.000000e+00, v12                                         ; 081A18F2
	V_MUL_F32_e32 v10, v13, v10                                                  ; 1014150D
	S_BUFFER_LOAD_DWORD s1, s[12:15], 29                                         ; C2008D1D
	S_WAITCNT lgkmcnt(0)                                                         ; BF8C007F
	V_MAD_F32 v10, v12, s1, v10, 0, 0, 0, 0                                      ; D282000A 0428030C
	V_INTERP_P1_F32 v14, v0, 2, 0, [m0]                                          ; C8380200
	V_INTERP_P2_F32 v14, [v14], v1, 2, 0, [m0]                                   ; C8390201
	S_BUFFER_LOAD_DWORD s1, s[12:15], 20                                         ; C2008D14
	S_WAITCNT lgkmcnt(0)                                                         ; BF8C007F
	V_MUL_F32_e32 v0, s1, v14                                                    ; 10001C01
	V_SUB_F32_e32 v1, 1.000000e+00, v0                                           ; 080200F2
	V_MUL_F32_e32 v10, v1, v10                                                   ; 10141501
	S_BUFFER_LOAD_DWORD s1, s[12:15], 25                                         ; C2008D19
	S_WAITCNT lgkmcnt(0)                                                         ; BF8C007F
	V_MAD_F32 v10, v0, s1, v10, 0, 0, 0, 0                                       ; D282000A 04280300
	V_MOV_B32_e32 v15, 5.960460e-08                                              ; 7E1E02FF 337FFFF3
	V_CMP_GE_F32_e64 s[2:3], v10, v15, 0, 0, 0, 0                                ; D00C0002 02021F0A
	V_CMP_U_F32_e64 s[4:5], v10, v10, 0, 0, 0, 0                                 ; D0100004 0202150A
	S_OR_B64 s[2:3], s[2:3], s[4:5]                                              ; 88820402
	V_CNDMASK_B32_e64 v10, v15, v10, s[2:3], 0, 0, 0, 0                          ; D200000A 000A150F
	V_MOV_B32_e32 v16, 6.550400e+04                                              ; 7E2002FF 477FE000
	V_CMP_GE_F32_e64 s[2:3], v10, v16, 0, 0, 0, 0                                ; D00C0002 0202210A
	V_CMP_U_F32_e64 s[4:5], v10, v10, 0, 0, 0, 0                                 ; D0100004 0202150A
	S_OR_B64 s[2:3], s[2:3], s[4:5]                                              ; 88820402
	V_CNDMASK_B32_e64 v10, v10, v16, s[2:3], 0, 0, 0, 0                          ; D200000A 000A210A
	V_MUL_F32_e32 v17, v6, v2                                                    ; 10220506
	S_BUFFER_LOAD_DWORD s1, s[12:15], 0                                          ; C2008D00
	S_WAITCNT lgkmcnt(0)                                                         ; BF8C007F
	V_MUL_F32_e32 v17, s1, v17                                                   ; 10222201
	V_MUL_F32_e32 v17, v5, v17                                                   ; 10222305
	V_MAD_F32 v17, v4, s0, v17, 0, 0, 0, 0                                       ; D2820011 04440104
	V_MUL_F32_e32 v17, v13, v17                                                  ; 1022230D
	S_BUFFER_LOAD_DWORD s1, s[12:15], 28                                         ; C2008D1C
	S_WAITCNT lgkmcnt(0)                                                         ; BF8C007F
	V_MAD_F32 v17, v12, s1, v17, 0, 0, 0, 0                                      ; D2820011 0444030C
	V_MUL_F32_e32 v17, v1, v17                                                   ; 10222301
	S_BUFFER_LOAD_DWORD s1, s[12:15], 24                                         ; C2008D18
	S_WAITCNT lgkmcnt(0)                                                         ; BF8C007F
	V_MAD_F32 v17, v0, s1, v17, 0, 0, 0, 0                                       ; D2820011 04440300
	V_CMP_GE_F32_e64 s[2:3], v17, v15, 0, 0, 0, 0                                ; D00C0002 02021F11
	V_CMP_U_F32_e64 s[4:5], v17, v17, 0, 0, 0, 0                                 ; D0100004 02022311
	S_OR_B64 s[2:3], s[2:3], s[4:5]                                              ; 88820402
	V_CNDMASK_B32_e64 v17, v15, v17, s[2:3], 0, 0, 0, 0                          ; D2000011 000A230F
	V_CMP_GE_F32_e64 s[2:3], v17, v16, 0, 0, 0, 0                                ; D00C0002 02022111
	V_CMP_U_F32_e64 s[4:5], v17, v17, 0, 0, 0, 0                                 ; D0100004 02022311
	S_OR_B64 s[2:3], s[2:3], s[4:5]                                              ; 88820402
	V_CNDMASK_B32_e64 v17, v17, v16, s[2:3], 0, 0, 0, 0                          ; D2000011 000A2111
	V_CVT_PKRTZ_F16_F32_e32 v10, v17, v10                                        ; 5E141511
	V_MUL_F32_e32 v2, v8, v2                                                     ; 10040508
	S_BUFFER_LOAD_DWORD s1, s[12:15], 2                                          ; C2008D02
	S_WAITCNT lgkmcnt(0)                                                         ; BF8C007F
	V_MUL_F32_e32 v2, s1, v2                                                     ; 10040401
	V_MUL_F32_e32 v2, v5, v2                                                     ; 10040505
	V_MAD_F32 v2, v4, s0, v2, 0, 0, 0, 0                                         ; D2820002 04080104
	V_MUL_F32_e32 v2, v13, v2                                                    ; 1004050D
	S_BUFFER_LOAD_DWORD s0, s[12:15], 30                                         ; C2000D1E
	S_WAITCNT lgkmcnt(0)                                                         ; BF8C007F
	V_MAD_F32 v2, v12, s0, v2, 0, 0, 0, 0                                        ; D2820002 0408010C
	V_MUL_F32_e32 v1, v1, v2                                                     ; 10020501
	S_BUFFER_LOAD_DWORD s0, s[12:15], 26                                         ; C2000D1A
	S_WAITCNT lgkmcnt(0)                                                         ; BF8C007F
	V_MAD_F32 v0, v0, s0, v1, 0, 0, 0, 0                                         ; D2820000 04040100
	V_CMP_GE_F32_e64 s[0:1], v0, v15, 0, 0, 0, 0                                 ; D00C0000 02021F00
	V_CMP_U_F32_e64 s[2:3], v0, v0, 0, 0, 0, 0                                   ; D0100002 02020100
	S_OR_B64 s[0:1], s[0:1], s[2:3]                                              ; 88800200
	V_CNDMASK_B32_e64 v0, v15, v0, s[0:1], 0, 0, 0, 0                            ; D2000000 0002010F
	V_CMP_GE_F32_e64 s[0:1], v0, v16, 0, 0, 0, 0                                 ; D00C0000 02022100
	V_CMP_U_F32_e64 s[2:3], v0, v0, 0, 0, 0, 0                                   ; D0100002 02020100
	S_OR_B64 s[0:1], s[0:1], s[2:3]                                              ; 88800200
	V_CNDMASK_B32_e64 v0, v0, v16, s[0:1], 0, 0, 0, 0                            ; D2000000 00022100
	S_BUFFER_LOAD_DWORD s0, s[12:15], 15                                         ; C2000D0F
	S_WAITCNT lgkmcnt(0)                                                         ; BF8C007F
	V_MUL_F32_e32 v1, s0, v3                                                     ; 10020600
	V_SUB_F32_e32 v2, 1.000000e+00, v1                                           ; 080402F2
	S_BUFFER_LOAD_DWORD s0, s[12:15], 13                                         ; C2000D0D
	S_WAITCNT lgkmcnt(0)                                                         ; BF8C007F
	V_MAD_F32 v1, v1, s0, v2, 0, 0, 0, 0                                         ; D2820001 04080101
	V_MUL_F32_e32 v2, v11, v11                                                   ; 1004170B
	V_ADD_F32_e32 v3, v11, v11                                                   ; 0606170B
	V_SUB_F32_e32 v2, v3, v2                                                     ; 08040503
	S_BUFFER_LOAD_DWORD s0, s[12:15], 23                                         ; C2000D17
	S_WAITCNT lgkmcnt(0)                                                         ; BF8C007F
	V_MUL_F32_e32 v2, s0, v2                                                     ; 10040400
	V_SUB_F32_e32 v3, 1.000000e+00, v2                                           ; 080604F2
	V_MUL_F32_e32 v1, v3, v1                                                     ; 10020303
	S_BUFFER_LOAD_DWORD s0, s[12:15], 31                                         ; C2000D1F
	S_WAITCNT lgkmcnt(0)                                                         ; BF8C007F
	V_MAD_F32 v1, v2, s0, v1, 0, 0, 0, 0                                         ; D2820001 04040102
	V_MUL_F32_e32 v2, v14, v14                                                   ; 10041D0E
	V_ADD_F32_e32 v3, v14, v14                                                   ; 06061D0E
	V_SUB_F32_e32 v2, v3, v2                                                     ; 08040503
	S_BUFFER_LOAD_DWORD s0, s[12:15], 21                                         ; C2000D15
	S_WAITCNT lgkmcnt(0)                                                         ; BF8C007F
	V_MUL_F32_e32 v2, s0, v2                                                     ; 10040400
	V_SUB_F32_e32 v3, 1.000000e+00, v2                                           ; 080604F2
	V_MUL_F32_e32 v1, v3, v1                                                     ; 10020303
	S_BUFFER_LOAD_DWORD s0, s[12:15], 27                                         ; C2000D1B
	S_WAITCNT lgkmcnt(0)                                                         ; BF8C007F
	V_MAD_F32 v1, v2, s0, v1, 0, 0, 0, 0                                         ; D2820001 04040102
	S_BUFFER_LOAD_DWORD s0, s[12:15], 16                                         ; C2000D10
	S_BUFFER_LOAD_DWORD s1, s[12:15], 17                                         ; C2008D11
	S_WAITCNT lgkmcnt(0)                                                         ; BF8C007F
	V_MOV_B32_e32 v2, s1                                                         ; 7E040201
	V_MAD_F32 v1, v1, s0, v2, 0, 0, 0, 0                                         ; D2820001 04080101
	V_ADD_F32_e64 v1, 0, v1, 0, 1, 0, 0                                          ; D2060801 02020280
	V_CVT_PKRTZ_F16_F32_e32 v0, v0, v1                                           ; 5E000300
	EXP 15, 0, 1, 1, 1, v10, v0, v10, v0                                         ; F8001C0F 000A000A
	S_ENDPGM                                                                     ; BF810000

VERT
DCL IN[0]
DCL IN[1]
DCL IN[2]
DCL IN[3]
DCL IN[4]
DCL IN[5]
DCL IN[6]
DCL IN[7]
DCL IN[8]
DCL OUT[0], POSITION
DCL OUT[1], CLIPVERTEX
DCL OUT[2], GENERIC[19]
DCL OUT[3], GENERIC[20]
DCL OUT[4], GENERIC[21]
DCL OUT[5], GENERIC[22]
DCL OUT[6], GENERIC[23]
DCL OUT[7], GENERIC[24]
DCL OUT[8], GENERIC[25]
DCL OUT[9], GENERIC[26]
DCL CONST[0..22]
DCL TEMP[0..15], LOCAL
IMM[0] FLT32 {    0.5000,     0.0010,     0.0000,     1.0000}
IMM[1] FLT32 {    0.0001,     1.4427,     0.0000,     0.0000}
  0: DP4 TEMP[0].x, IN[0], CONST[0]
  1: DP4 TEMP[1].x, IN[0], CONST[1]
  2: MOV TEMP[0].y, TEMP[1].xxxx
  3: DP4 TEMP[1].x, IN[0], CONST[2]
  4: MOV TEMP[0].z, TEMP[1].xxxx
  5: DP4 TEMP[1].x, IN[0], CONST[3]
  6: MOV TEMP[0].w, TEMP[1].xxxx
  7: MUL TEMP[2].xy, TEMP[0].xyyy, IMM[0].xxxx
  8: MAD TEMP[2].xy, TEMP[1].xxxx, IMM[0].xxxx, TEMP[2].xyyy
  9: DP4 TEMP[3].x, IN[0], CONST[4]
 10: DP4 TEMP[4].x, IN[0], CONST[5]
 11: MOV TEMP[3].y, TEMP[4].xxxx
 12: DP4 TEMP[4].x, IN[0], CONST[6]
 13: MOV TEMP[3].z, TEMP[4].xxxx
 14: MOV TEMP[4].xyz, TEMP[3].xyzx
 15: MOV TEMP[4].w, TEMP[1].xxxx
 16: DP4 TEMP[1].x, IN[4], CONST[14]
 17: DP4 TEMP[5].x, IN[4], CONST[15]
 18: MOV TEMP[1].y, TEMP[5].xxxx
 19: MOV TEMP[1].xy, TEMP[1].xyxx
 20: DP4 TEMP[5].x, IN[5], CONST[16]
 21: DP4 TEMP[6].x, IN[5], CONST[17]
 22: MOV TEMP[5].y, TEMP[6].xxxx
 23: MOV TEMP[1].zw, TEMP[5].yyxy
 24: DP4 TEMP[5].x, IN[6], CONST[18]
 25: DP4 TEMP[6].x, IN[6], CONST[19]
 26: MOV TEMP[5].y, TEMP[6].xxxx
 27: MOV TEMP[5].xy, TEMP[5].xyxx
 28: DP4 TEMP[6].x, IN[7], CONST[20]
 29: DP4 TEMP[7].x, IN[7], CONST[21]
 30: MOV TEMP[6].y, TEMP[7].xxxx
 31: MOV TEMP[5].zw, TEMP[6].yyxy
 32: MAD TEMP[6].xy, IN[3].xyyy, CONST[7].xxxx, CONST[7].yyyy
 33: MOV TEMP[6].zw, TEMP[6].yyxy
 34: MOV TEMP[6].xy, IN[8].xyxx
 35: MAD TEMP[7].xyz, IN[1].xyzz, CONST[22].xxxx, CONST[22].yyyy
 36: MOV TEMP[8].xz, TEMP[7].xxzx
 37: ADD TEMP[9].x, TEMP[7].yyyy, IMM[0].yyyy
 38: MOV TEMP[8].y, TEMP[9].xxxx
 39: MAD TEMP[10], IN[2], CONST[22].zzzz, CONST[22].wwww
 40: MOV TEMP[11].yz, TEMP[10].zyzw
 41: ADD TEMP[11].x, TEMP[10].xxxx, IMM[0].yyyy
 42: MUL TEMP[8].xyz, TEMP[8].xyzz, TEMP[10].wwww
 43: MUL TEMP[12].xyz, TEMP[8].zxyy, TEMP[11].yzxx
 44: MAD TEMP[8].xyz, TEMP[8].yzxx, TEMP[11].zxyy, -TEMP[12].xyzz
 45: MOV TEMP[12].x, CONST[4].xxxx
 46: MOV TEMP[13].x, CONST[4].yyyy
 47: MOV TEMP[14].x, CONST[4].zzzz
 48: MOV TEMP[12].y, CONST[5].xxxx
 49: MOV TEMP[13].y, CONST[5].yyyy
 50: MOV TEMP[14].y, CONST[5].zzzz
 51: MOV TEMP[12].z, CONST[6].xxxx
 52: MOV TEMP[13].z, CONST[6].yyyy
 53: MOV TEMP[14].z, CONST[6].zzzz
 54: DP3 TEMP[15].x, TEMP[12].xyzz, TEMP[12].xyzz
 55: RCP TEMP[15].x, TEMP[15].xxxx
 56: MUL TEMP[12].xyz, TEMP[12].xyzz, TEMP[15].xxxx
 57: DP3 TEMP[15].x, TEMP[13].xyzz, TEMP[13].xyzz
 58: RCP TEMP[15].x, TEMP[15].xxxx
 59: MUL TEMP[13].xyz, TEMP[13].xyzz, TEMP[15].xxxx
 60: DP3 TEMP[15].x, TEMP[14].xyzz, TEMP[14].xyzz
 61: RCP TEMP[15].x, TEMP[15].xxxx
 62: MUL TEMP[14].xyz, TEMP[14].xyzz, TEMP[15].xxxx
 63: MUL TEMP[11].xyz, TEMP[12].xyzz, TEMP[11].xxxx
 64: MAD TEMP[11].xyz, TEMP[13].xyzz, TEMP[10].yyyy, TEMP[11].xyzz
 65: MAD TEMP[10].xyz, TEMP[14].xyzz, TEMP[10].zzzz, TEMP[11].xyzz
 66: MUL TEMP[11].xyz, TEMP[12].xyzz, TEMP[8].xxxx
 67: MAD TEMP[11].xyz, TEMP[13].xyzz, TEMP[8].yyyy, TEMP[11].xyzz
 68: MAD TEMP[8].xyz, TEMP[14].xyzz, TEMP[8].zzzz, TEMP[11].xyzz
 69: MUL TEMP[11].xyz, TEMP[12].xyzz, TEMP[7].xxxx
 70: MAD TEMP[9].xyz, TEMP[13].xyzz, TEMP[9].xxxx, TEMP[11].xyzz
 71: MAD TEMP[7].xyz, TEMP[14].xyzz, TEMP[7].zzzz, TEMP[9].xyzz
 72: DP3 TEMP[9].x, TEMP[10].xyzz, TEMP[10].xyzz
 73: RSQ TEMP[9].x, TEMP[9].xxxx
 74: MUL TEMP[9].xyz, TEMP[10].xyzz, TEMP[9].xxxx
 75: DP3 TEMP[10].x, TEMP[8].xyzz, TEMP[8].xyzz
 76: RSQ TEMP[10].x, TEMP[10].xxxx
 77: MUL TEMP[8].xyz, TEMP[8].xyzz, TEMP[10].xxxx
 78: DP3 TEMP[10].x, TEMP[7].xyzz, TEMP[7].xyzz
 79: RSQ TEMP[10].x, TEMP[10].xxxx
 80: MUL TEMP[7].xyz, TEMP[7].xyzz, TEMP[10].xxxx
 81: ADD TEMP[10].xyz, TEMP[3].xyzz, -CONST[8].xyzz
 82: DP3 TEMP[11].x, TEMP[10].xyzz, TEMP[10].xyzz
 83: RSQ TEMP[12].x, TEMP[11].xxxx
 84: MUL TEMP[12].x, TEMP[12].xxxx, TEMP[11].xxxx
 85: CMP TEMP[11].x, -TEMP[11].xxxx, TEMP[12].xxxx, IMM[0].zzzz
 86: MOV TEMP[12].w, IMM[0].wwww
 87: MOV TEMP[12].xyz, TEMP[3].xyzx
 88: MOV TEMP[3].x, IMM[0].zzzz
 89: FSLT TEMP[13].x, IMM[0].zzzz, CONST[10].xxxx
 90: UIF TEMP[13].xxxx :0
 91:   DP4 TEMP[12].x, TEMP[12], CONST[12]
 92:   MOV TEMP[13].x, TEMP[12].xxxx
 93:   DP4 TEMP[14].x, CONST[8], CONST[12]
 94:   MOV TEMP[13].y, TEMP[14].xxxx
 95:   ADD TEMP[12].x, TEMP[12].xxxx, -TEMP[14].xxxx
 96:   FSGE TEMP[14].x, TEMP[12].xxxx, IMM[0].zzzz
 97:   UIF TEMP[14].xxxx :0
 98:     MOV TEMP[14].xy, TEMP[13].yxyy
 99:   ELSE :0
100:     MOV TEMP[14].xy, TEMP[13].xyxx
101:   ENDIF
102:   ADD TEMP[13].xy, TEMP[14].xyyy, -CONST[11].xxxx
103:   ADD TEMP[14].xy, CONST[11].zwww, -TEMP[13].xxxx
104:   ABS TEMP[12].x, TEMP[12].xxxx
105:   ADD TEMP[12].x, TEMP[12].xxxx, IMM[0].yyyy
106:   RCP TEMP[12].x, TEMP[12].xxxx
107:   MUL_SAT TEMP[12].xy, TEMP[14].xyyy, TEMP[12].xxxx
108:   MUL TEMP[13].xy, TEMP[13].xyyy, CONST[10].yyyy
109:   ADD_SAT TEMP[13].xy, IMM[0].wwww, -TEMP[13].xyyy
110:   MUL TEMP[14].x, TEMP[11].xxxx, CONST[10].xxxx
111:   ADD_SAT TEMP[12].x, TEMP[12].xxxx, -TEMP[12].yyyy
112:   ADD TEMP[13].x, TEMP[13].xxxx, TEMP[13].yyyy
113:   MUL_SAT TEMP[13].x, TEMP[13].xxxx, CONST[11].yyyy
114:   MUL TEMP[12].x, TEMP[12].xxxx, TEMP[13].xxxx
115:   MUL_SAT TEMP[12].x, TEMP[14].xxxx, TEMP[12].xxxx
116:   MOV TEMP[3].x, TEMP[12].xxxx
117: ENDIF
118: MOV TEMP[2].z, TEMP[3].xxxx
119: MOV TEMP[3].x, TEMP[10].yyyy
120: MOV TEMP[12].x, IMM[0].zzzz
121: FSLT TEMP[13].x, IMM[0].zzzz, CONST[13].xxxx
122: UIF TEMP[13].xxxx :0
123:   MUL_SAT TEMP[13].x, TEMP[11].xxxx, IMM[1].xxxx
124:   MUL TEMP[13].x, CONST[13].wwww, TEMP[13].xxxx
125:   ADD TEMP[13].x, IMM[0].wwww, -TEMP[13].xxxx
126:   MUL TEMP[3].x, TEMP[10].yyyy, TEMP[13].xxxx
127:   MUL TEMP[3].x, TEMP[3].xxxx, CONST[13].yyyy
128:   ADD_SAT TEMP[3].x, IMM[0].wwww, -TEMP[3].xxxx
129:   MUL TEMP[3].x, TEMP[3].xxxx, TEMP[3].xxxx
130:   ADD TEMP[10].x, TEMP[11].xxxx, -CONST[13].zzzz
131:   MUL TEMP[10].x, -CONST[13].xxxx, TEMP[10].xxxx
132:   MUL TEMP[10].x, TEMP[10].xxxx, IMM[1].yyyy
133:   EX2 TEMP[10].x, TEMP[10].xxxx
134:   ADD_SAT TEMP[10].x, IMM[0].wwww, -TEMP[10].xxxx
135:   MUL TEMP[12].x, TEMP[10].xxxx, TEMP[3].xxxx
136: ENDIF
137: MOV TEMP[2].w, TEMP[12].xxxx
138: MOV TEMP[3].xyz, TEMP[9].xyzx
139: MOV TEMP[3].w, TEMP[8].xxxx
140: MOV TEMP[8].xy, TEMP[8].yzyy
141: MOV TEMP[8].zw, TEMP[7].yyxy
142: MOV TEMP[7].x, TEMP[7].zzzz
143: MOV OUT[6], TEMP[6]
144: MOV OUT[5], TEMP[5]
145: MOV OUT[9], TEMP[7]
146: MOV OUT[3], TEMP[4]
147: MOV OUT[2], TEMP[2]
148: MOV OUT[8], TEMP[8]
149: MOV OUT[7], TEMP[3]
150: MOV OUT[0], TEMP[0]
151: MOV OUT[4], TEMP[1]
152: MOV OUT[1], TEMP[0]
153: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0)
  %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4)
  %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8)
  %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12)
  %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16)
  %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20)
  %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24)
  %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28)
  %20 = call float @llvm.SI.load.const(<16 x i8> %11, i32 32)
  %21 = call float @llvm.SI.load.const(<16 x i8> %11, i32 36)
  %22 = call float @llvm.SI.load.const(<16 x i8> %11, i32 40)
  %23 = call float @llvm.SI.load.const(<16 x i8> %11, i32 44)
  %24 = call float @llvm.SI.load.const(<16 x i8> %11, i32 48)
  %25 = call float @llvm.SI.load.const(<16 x i8> %11, i32 52)
  %26 = call float @llvm.SI.load.const(<16 x i8> %11, i32 56)
  %27 = call float @llvm.SI.load.const(<16 x i8> %11, i32 60)
  %28 = call float @llvm.SI.load.const(<16 x i8> %11, i32 64)
  %29 = call float @llvm.SI.load.const(<16 x i8> %11, i32 68)
  %30 = call float @llvm.SI.load.const(<16 x i8> %11, i32 72)
  %31 = call float @llvm.SI.load.const(<16 x i8> %11, i32 76)
  %32 = call float @llvm.SI.load.const(<16 x i8> %11, i32 80)
  %33 = call float @llvm.SI.load.const(<16 x i8> %11, i32 84)
  %34 = call float @llvm.SI.load.const(<16 x i8> %11, i32 88)
  %35 = call float @llvm.SI.load.const(<16 x i8> %11, i32 92)
  %36 = call float @llvm.SI.load.const(<16 x i8> %11, i32 96)
  %37 = call float @llvm.SI.load.const(<16 x i8> %11, i32 100)
  %38 = call float @llvm.SI.load.const(<16 x i8> %11, i32 104)
  %39 = call float @llvm.SI.load.const(<16 x i8> %11, i32 108)
  %40 = call float @llvm.SI.load.const(<16 x i8> %11, i32 112)
  %41 = call float @llvm.SI.load.const(<16 x i8> %11, i32 116)
  %42 = call float @llvm.SI.load.const(<16 x i8> %11, i32 128)
  %43 = call float @llvm.SI.load.const(<16 x i8> %11, i32 132)
  %44 = call float @llvm.SI.load.const(<16 x i8> %11, i32 136)
  %45 = call float @llvm.SI.load.const(<16 x i8> %11, i32 140)
  %46 = call float @llvm.SI.load.const(<16 x i8> %11, i32 160)
  %47 = call float @llvm.SI.load.const(<16 x i8> %11, i32 164)
  %48 = call float @llvm.SI.load.const(<16 x i8> %11, i32 176)
  %49 = call float @llvm.SI.load.const(<16 x i8> %11, i32 180)
  %50 = call float @llvm.SI.load.const(<16 x i8> %11, i32 184)
  %51 = call float @llvm.SI.load.const(<16 x i8> %11, i32 188)
  %52 = call float @llvm.SI.load.const(<16 x i8> %11, i32 192)
  %53 = call float @llvm.SI.load.const(<16 x i8> %11, i32 196)
  %54 = call float @llvm.SI.load.const(<16 x i8> %11, i32 200)
  %55 = call float @llvm.SI.load.const(<16 x i8> %11, i32 204)
  %56 = call float @llvm.SI.load.const(<16 x i8> %11, i32 208)
  %57 = call float @llvm.SI.load.const(<16 x i8> %11, i32 212)
  %58 = call float @llvm.SI.load.const(<16 x i8> %11, i32 216)
  %59 = call float @llvm.SI.load.const(<16 x i8> %11, i32 220)
  %60 = call float @llvm.SI.load.const(<16 x i8> %11, i32 224)
  %61 = call float @llvm.SI.load.const(<16 x i8> %11, i32 228)
  %62 = call float @llvm.SI.load.const(<16 x i8> %11, i32 232)
  %63 = call float @llvm.SI.load.const(<16 x i8> %11, i32 236)
  %64 = call float @llvm.SI.load.const(<16 x i8> %11, i32 240)
  %65 = call float @llvm.SI.load.const(<16 x i8> %11, i32 244)
  %66 = call float @llvm.SI.load.const(<16 x i8> %11, i32 248)
  %67 = call float @llvm.SI.load.const(<16 x i8> %11, i32 252)
  %68 = call float @llvm.SI.load.const(<16 x i8> %11, i32 256)
  %69 = call float @llvm.SI.load.const(<16 x i8> %11, i32 260)
  %70 = call float @llvm.SI.load.const(<16 x i8> %11, i32 264)
  %71 = call float @llvm.SI.load.const(<16 x i8> %11, i32 268)
  %72 = call float @llvm.SI.load.const(<16 x i8> %11, i32 272)
  %73 = call float @llvm.SI.load.const(<16 x i8> %11, i32 276)
  %74 = call float @llvm.SI.load.const(<16 x i8> %11, i32 280)
  %75 = call float @llvm.SI.load.const(<16 x i8> %11, i32 284)
  %76 = call float @llvm.SI.load.const(<16 x i8> %11, i32 288)
  %77 = call float @llvm.SI.load.const(<16 x i8> %11, i32 292)
  %78 = call float @llvm.SI.load.const(<16 x i8> %11, i32 296)
  %79 = call float @llvm.SI.load.const(<16 x i8> %11, i32 300)
  %80 = call float @llvm.SI.load.const(<16 x i8> %11, i32 304)
  %81 = call float @llvm.SI.load.const(<16 x i8> %11, i32 308)
  %82 = call float @llvm.SI.load.const(<16 x i8> %11, i32 312)
  %83 = call float @llvm.SI.load.const(<16 x i8> %11, i32 316)
  %84 = call float @llvm.SI.load.const(<16 x i8> %11, i32 320)
  %85 = call float @llvm.SI.load.const(<16 x i8> %11, i32 324)
  %86 = call float @llvm.SI.load.const(<16 x i8> %11, i32 328)
  %87 = call float @llvm.SI.load.const(<16 x i8> %11, i32 332)
  %88 = call float @llvm.SI.load.const(<16 x i8> %11, i32 336)
  %89 = call float @llvm.SI.load.const(<16 x i8> %11, i32 340)
  %90 = call float @llvm.SI.load.const(<16 x i8> %11, i32 344)
  %91 = call float @llvm.SI.load.const(<16 x i8> %11, i32 348)
  %92 = call float @llvm.SI.load.const(<16 x i8> %11, i32 352)
  %93 = call float @llvm.SI.load.const(<16 x i8> %11, i32 356)
  %94 = call float @llvm.SI.load.const(<16 x i8> %11, i32 360)
  %95 = call float @llvm.SI.load.const(<16 x i8> %11, i32 364)
  %96 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0
  %97 = load <16 x i8> addrspace(2)* %96, !tbaa !0
  %98 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %97, i32 0, i32 %6)
  %99 = extractelement <4 x float> %98, i32 0
  %100 = extractelement <4 x float> %98, i32 1
  %101 = extractelement <4 x float> %98, i32 2
  %102 = extractelement <4 x float> %98, i32 3
  %103 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 1
  %104 = load <16 x i8> addrspace(2)* %103, !tbaa !0
  %105 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %104, i32 0, i32 %6)
  %106 = extractelement <4 x float> %105, i32 0
  %107 = extractelement <4 x float> %105, i32 1
  %108 = extractelement <4 x float> %105, i32 2
  %109 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 2
  %110 = load <16 x i8> addrspace(2)* %109, !tbaa !0
  %111 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %110, i32 0, i32 %6)
  %112 = extractelement <4 x float> %111, i32 0
  %113 = extractelement <4 x float> %111, i32 1
  %114 = extractelement <4 x float> %111, i32 2
  %115 = extractelement <4 x float> %111, i32 3
  %116 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 3
  %117 = load <16 x i8> addrspace(2)* %116, !tbaa !0
  %118 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %117, i32 0, i32 %6)
  %119 = extractelement <4 x float> %118, i32 0
  %120 = extractelement <4 x float> %118, i32 1
  %121 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 4
  %122 = load <16 x i8> addrspace(2)* %121, !tbaa !0
  %123 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %122, i32 0, i32 %6)
  %124 = extractelement <4 x float> %123, i32 0
  %125 = extractelement <4 x float> %123, i32 1
  %126 = extractelement <4 x float> %123, i32 2
  %127 = extractelement <4 x float> %123, i32 3
  %128 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 5
  %129 = load <16 x i8> addrspace(2)* %128, !tbaa !0
  %130 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %129, i32 0, i32 %6)
  %131 = extractelement <4 x float> %130, i32 0
  %132 = extractelement <4 x float> %130, i32 1
  %133 = extractelement <4 x float> %130, i32 2
  %134 = extractelement <4 x float> %130, i32 3
  %135 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 6
  %136 = load <16 x i8> addrspace(2)* %135, !tbaa !0
  %137 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %136, i32 0, i32 %6)
  %138 = extractelement <4 x float> %137, i32 0
  %139 = extractelement <4 x float> %137, i32 1
  %140 = extractelement <4 x float> %137, i32 2
  %141 = extractelement <4 x float> %137, i32 3
  %142 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 7
  %143 = load <16 x i8> addrspace(2)* %142, !tbaa !0
  %144 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %143, i32 0, i32 %6)
  %145 = extractelement <4 x float> %144, i32 0
  %146 = extractelement <4 x float> %144, i32 1
  %147 = extractelement <4 x float> %144, i32 2
  %148 = extractelement <4 x float> %144, i32 3
  %149 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 8
  %150 = load <16 x i8> addrspace(2)* %149, !tbaa !0
  %151 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %150, i32 0, i32 %6)
  %152 = extractelement <4 x float> %151, i32 0
  %153 = extractelement <4 x float> %151, i32 1
  %154 = fmul float %99, %12
  %155 = fmul float %100, %13
  %156 = fadd float %154, %155
  %157 = fmul float %101, %14
  %158 = fadd float %156, %157
  %159 = fmul float %102, %15
  %160 = fadd float %158, %159
  %161 = fmul float %99, %16
  %162 = fmul float %100, %17
  %163 = fadd float %161, %162
  %164 = fmul float %101, %18
  %165 = fadd float %163, %164
  %166 = fmul float %102, %19
  %167 = fadd float %165, %166
  %168 = fmul float %99, %20
  %169 = fmul float %100, %21
  %170 = fadd float %168, %169
  %171 = fmul float %101, %22
  %172 = fadd float %170, %171
  %173 = fmul float %102, %23
  %174 = fadd float %172, %173
  %175 = fmul float %99, %24
  %176 = fmul float %100, %25
  %177 = fadd float %175, %176
  %178 = fmul float %101, %26
  %179 = fadd float %177, %178
  %180 = fmul float %102, %27
  %181 = fadd float %179, %180
  %182 = fmul float %160, 5.000000e-01
  %183 = fmul float %167, 5.000000e-01
  %184 = fmul float %181, 5.000000e-01
  %185 = fadd float %184, %182
  %186 = fmul float %181, 5.000000e-01
  %187 = fadd float %186, %183
  %188 = fmul float %99, %28
  %189 = fmul float %100, %29
  %190 = fadd float %188, %189
  %191 = fmul float %101, %30
  %192 = fadd float %190, %191
  %193 = fmul float %102, %31
  %194 = fadd float %192, %193
  %195 = fmul float %99, %32
  %196 = fmul float %100, %33
  %197 = fadd float %195, %196
  %198 = fmul float %101, %34
  %199 = fadd float %197, %198
  %200 = fmul float %102, %35
  %201 = fadd float %199, %200
  %202 = fmul float %99, %36
  %203 = fmul float %100, %37
  %204 = fadd float %202, %203
  %205 = fmul float %101, %38
  %206 = fadd float %204, %205
  %207 = fmul float %102, %39
  %208 = fadd float %206, %207
  %209 = fmul float %124, %60
  %210 = fmul float %125, %61
  %211 = fadd float %209, %210
  %212 = fmul float %126, %62
  %213 = fadd float %211, %212
  %214 = fmul float %127, %63
  %215 = fadd float %213, %214
  %216 = fmul float %124, %64
  %217 = fmul float %125, %65
  %218 = fadd float %216, %217
  %219 = fmul float %126, %66
  %220 = fadd float %218, %219
  %221 = fmul float %127, %67
  %222 = fadd float %220, %221
  %223 = fmul float %131, %68
  %224 = fmul float %132, %69
  %225 = fadd float %223, %224
  %226 = fmul float %133, %70
  %227 = fadd float %225, %226
  %228 = fmul float %134, %71
  %229 = fadd float %227, %228
  %230 = fmul float %131, %72
  %231 = fmul float %132, %73
  %232 = fadd float %230, %231
  %233 = fmul float %133, %74
  %234 = fadd float %232, %233
  %235 = fmul float %134, %75
  %236 = fadd float %234, %235
  %237 = fmul float %138, %76
  %238 = fmul float %139, %77
  %239 = fadd float %237, %238
  %240 = fmul float %140, %78
  %241 = fadd float %239, %240
  %242 = fmul float %141, %79
  %243 = fadd float %241, %242
  %244 = fmul float %138, %80
  %245 = fmul float %139, %81
  %246 = fadd float %244, %245
  %247 = fmul float %140, %82
  %248 = fadd float %246, %247
  %249 = fmul float %141, %83
  %250 = fadd float %248, %249
  %251 = fmul float %145, %84
  %252 = fmul float %146, %85
  %253 = fadd float %251, %252
  %254 = fmul float %147, %86
  %255 = fadd float %253, %254
  %256 = fmul float %148, %87
  %257 = fadd float %255, %256
  %258 = fmul float %145, %88
  %259 = fmul float %146, %89
  %260 = fadd float %258, %259
  %261 = fmul float %147, %90
  %262 = fadd float %260, %261
  %263 = fmul float %148, %91
  %264 = fadd float %262, %263
  %265 = fmul float %119, %40
  %266 = fadd float %265, %41
  %267 = fmul float %120, %40
  %268 = fadd float %267, %41
  %269 = fmul float %106, %92
  %270 = fadd float %269, %93
  %271 = fmul float %107, %92
  %272 = fadd float %271, %93
  %273 = fmul float %108, %92
  %274 = fadd float %273, %93
  %275 = fadd float %272, 0x3F50624DE0000000
  %276 = fmul float %112, %94
  %277 = fadd float %276, %95
  %278 = fmul float %113, %94
  %279 = fadd float %278, %95
  %280 = fmul float %114, %94
  %281 = fadd float %280, %95
  %282 = fmul float %115, %94
  %283 = fadd float %282, %95
  %284 = fadd float %277, 0x3F50624DE0000000
  %285 = fmul float %270, %283
  %286 = fmul float %275, %283
  %287 = fmul float %274, %283
  %288 = fmul float %287, %279
  %289 = fmul float %285, %281
  %290 = fmul float %286, %284
  %291 = fsub float -0.000000e+00, %288
  %292 = fmul float %286, %281
  %293 = fadd float %292, %291
  %294 = fsub float -0.000000e+00, %289
  %295 = fmul float %287, %284
  %296 = fadd float %295, %294
  %297 = fsub float -0.000000e+00, %290
  %298 = fmul float %285, %279
  %299 = fadd float %298, %297
  %300 = fmul float %28, %28
  %301 = fmul float %32, %32
  %302 = fadd float %301, %300
  %303 = fmul float %36, %36
  %304 = fadd float %302, %303
  %305 = fdiv float 1.000000e+00, %304
  %306 = fmul float %28, %305
  %307 = fmul float %32, %305
  %308 = fmul float %36, %305
  %309 = fmul float %29, %29
  %310 = fmul float %33, %33
  %311 = fadd float %310, %309
  %312 = fmul float %37, %37
  %313 = fadd float %311, %312
  %314 = fdiv float 1.000000e+00, %313
  %315 = fmul float %29, %314
  %316 = fmul float %33, %314
  %317 = fmul float %37, %314
  %318 = fmul float %30, %30
  %319 = fmul float %34, %34
  %320 = fadd float %319, %318
  %321 = fmul float %38, %38
  %322 = fadd float %320, %321
  %323 = fdiv float 1.000000e+00, %322
  %324 = fmul float %30, %323
  %325 = fmul float %34, %323
  %326 = fmul float %38, %323
  %327 = fmul float %306, %284
  %328 = fmul float %307, %284
  %329 = fmul float %308, %284
  %330 = fmul float %315, %279
  %331 = fadd float %330, %327
  %332 = fmul float %316, %279
  %333 = fadd float %332, %328
  %334 = fmul float %317, %279
  %335 = fadd float %334, %329
  %336 = fmul float %324, %281
  %337 = fadd float %336, %331
  %338 = fmul float %325, %281
  %339 = fadd float %338, %333
  %340 = fmul float %326, %281
  %341 = fadd float %340, %335
  %342 = fmul float %306, %293
  %343 = fmul float %307, %293
  %344 = fmul float %308, %293
  %345 = fmul float %315, %296
  %346 = fadd float %345, %342
  %347 = fmul float %316, %296
  %348 = fadd float %347, %343
  %349 = fmul float %317, %296
  %350 = fadd float %349, %344
  %351 = fmul float %324, %299
  %352 = fadd float %351, %346
  %353 = fmul float %325, %299
  %354 = fadd float %353, %348
  %355 = fmul float %326, %299
  %356 = fadd float %355, %350
  %357 = fmul float %306, %270
  %358 = fmul float %307, %270
  %359 = fmul float %308, %270
  %360 = fmul float %315, %275
  %361 = fadd float %360, %357
  %362 = fmul float %316, %275
  %363 = fadd float %362, %358
  %364 = fmul float %317, %275
  %365 = fadd float %364, %359
  %366 = fmul float %324, %274
  %367 = fadd float %366, %361
  %368 = fmul float %325, %274
  %369 = fadd float %368, %363
  %370 = fmul float %326, %274
  %371 = fadd float %370, %365
  %372 = fmul float %337, %337
  %373 = fmul float %339, %339
  %374 = fadd float %373, %372
  %375 = fmul float %341, %341
  %376 = fadd float %374, %375
  %377 = call float @llvm.AMDGPU.rsq(float %376)
  %378 = fmul float %337, %377
  %379 = fmul float %339, %377
  %380 = fmul float %341, %377
  %381 = fmul float %352, %352
  %382 = fmul float %354, %354
  %383 = fadd float %382, %381
  %384 = fmul float %356, %356
  %385 = fadd float %383, %384
  %386 = call float @llvm.AMDGPU.rsq(float %385)
  %387 = fmul float %352, %386
  %388 = fmul float %354, %386
  %389 = fmul float %356, %386
  %390 = fmul float %367, %367
  %391 = fmul float %369, %369
  %392 = fadd float %391, %390
  %393 = fmul float %371, %371
  %394 = fadd float %392, %393
  %395 = call float @llvm.AMDGPU.rsq(float %394)
  %396 = fmul float %367, %395
  %397 = fmul float %369, %395
  %398 = fmul float %371, %395
  %399 = fsub float -0.000000e+00, %42
  %400 = fadd float %194, %399
  %401 = fsub float -0.000000e+00, %43
  %402 = fadd float %201, %401
  %403 = fsub float -0.000000e+00, %44
  %404 = fadd float %208, %403
  %405 = fmul float %400, %400
  %406 = fmul float %402, %402
  %407 = fadd float %406, %405
  %408 = fmul float %404, %404
  %409 = fadd float %407, %408
  %410 = call float @llvm.AMDGPU.rsq(float %409)
  %411 = fmul float %410, %409
  %412 = fsub float -0.000000e+00, %409
  %413 = call float @llvm.AMDGPU.cndlt(float %412, float %411, float 0.000000e+00)
  %414 = fcmp olt float 0.000000e+00, %46
  %415 = sext i1 %414 to i32
  %416 = bitcast i32 %415 to float
  %417 = bitcast float %416 to i32
  %418 = icmp ne i32 %417, 0
  br i1 %418, label %IF, label %ENDIF

IF:                                               ; preds = %main_body
  %419 = fmul float %194, %52
  %420 = fmul float %201, %53
  %421 = fadd float %419, %420
  %422 = fmul float %208, %54
  %423 = fadd float %421, %422
  %424 = fmul float 1.000000e+00, %55
  %425 = fadd float %423, %424
  %426 = fmul float %42, %52
  %427 = fmul float %43, %53
  %428 = fadd float %426, %427
  %429 = fmul float %44, %54
  %430 = fadd float %428, %429
  %431 = fmul float %45, %55
  %432 = fadd float %430, %431
  %433 = fsub float -0.000000e+00, %432
  %434 = fadd float %425, %433
  %435 = fcmp oge float %434, 0.000000e+00
  %436 = sext i1 %435 to i32
  %437 = bitcast i32 %436 to float
  %438 = bitcast float %437 to i32
  %439 = icmp ne i32 %438, 0
  %. = select i1 %439, float %432, float %425
  %.70 = select i1 %439, float %425, float %432
  %440 = fsub float -0.000000e+00, %48
  %441 = fadd float %., %440
  %442 = fsub float -0.000000e+00, %48
  %443 = fadd float %.70, %442
  %444 = fsub float -0.000000e+00, %441
  %445 = fadd float %50, %444
  %446 = fsub float -0.000000e+00, %441
  %447 = fadd float %51, %446
  %448 = call float @fabs(float %434)
  %449 = fadd float %448, 0x3F50624DE0000000
  %450 = fdiv float 1.000000e+00, %449
  %451 = fmul float %445, %450
  %452 = fmul float %447, %450
  %453 = call float @llvm.AMDIL.clamp.(float %451, float 0.000000e+00, float 1.000000e+00)
  %454 = call float @llvm.AMDIL.clamp.(float %452, float 0.000000e+00, float 1.000000e+00)
  %455 = fmul float %441, %47
  %456 = fmul float %443, %47
  %457 = fsub float -0.000000e+00, %455
  %458 = fadd float 1.000000e+00, %457
  %459 = fsub float -0.000000e+00, %456
  %460 = fadd float 1.000000e+00, %459
  %461 = call float @llvm.AMDIL.clamp.(float %458, float 0.000000e+00, float 1.000000e+00)
  %462 = call float @llvm.AMDIL.clamp.(float %460, float 0.000000e+00, float 1.000000e+00)
  %463 = fmul float %413, %46
  %464 = fsub float -0.000000e+00, %454
  %465 = fadd float %453, %464
  %466 = call float @llvm.AMDIL.clamp.(float %465, float 0.000000e+00, float 1.000000e+00)
  %467 = fadd float %461, %462
  %468 = fmul float %467, %49
  %469 = call float @llvm.AMDIL.clamp.(float %468, float 0.000000e+00, float 1.000000e+00)
  %470 = fmul float %466, %469
  %471 = fmul float %463, %470
  %472 = call float @llvm.AMDIL.clamp.(float %471, float 0.000000e+00, float 1.000000e+00)
  br label %ENDIF

ENDIF:                                            ; preds = %main_body, %IF
  %temp12.0 = phi float [ %472, %IF ], [ 0.000000e+00, %main_body ]
  %473 = fcmp olt float 0.000000e+00, %56
  %474 = sext i1 %473 to i32
  %475 = bitcast i32 %474 to float
  %476 = bitcast float %475 to i32
  %477 = icmp ne i32 %476, 0
  br i1 %477, label %IF68, label %ENDIF67

IF68:                                             ; preds = %ENDIF
  %478 = fmul float %413, 0x3F1D745260000000
  %479 = call float @llvm.AMDIL.clamp.(float %478, float 0.000000e+00, float 1.000000e+00)
  %480 = fmul float %59, %479
  %481 = fsub float -0.000000e+00, %480
  %482 = fadd float 1.000000e+00, %481
  %483 = fmul float %402, %482
  %484 = fmul float %483, %57
  %485 = fsub float -0.000000e+00, %484
  %486 = fadd float 1.000000e+00, %485
  %487 = call float @llvm.AMDIL.clamp.(float %486, float 0.000000e+00, float 1.000000e+00)
  %488 = fmul float %487, %487
  %489 = fsub float -0.000000e+00, %58
  %490 = fadd float %413, %489
  %491 = fsub float -0.000000e+00, %56
  %492 = fmul float %491, %490
  %493 = fmul float %492, 0x3FF7154760000000
  %494 = call float @llvm.AMDIL.exp.(float %493)
  %495 = fsub float -0.000000e+00, %494
  %496 = fadd float 1.000000e+00, %495
  %497 = call float @llvm.AMDIL.clamp.(float %496, float 0.000000e+00, float 1.000000e+00)
  %498 = fmul float %497, %488
  br label %ENDIF67

ENDIF67:                                          ; preds = %ENDIF, %IF68
  %temp48.0 = phi float [ %498, %IF68 ], [ 0.000000e+00, %ENDIF ]
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %185, float %187, float %temp12.0, float %temp48.0)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %194, float %201, float %208, float %181)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %215, float %222, float %229, float %236)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %243, float %250, float %257, float %264)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 36, i32 0, float %152, float %153, float %266, float %268)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 37, i32 0, float %378, float %379, float %380, float %387)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 38, i32 0, float %388, float %389, float %396, float %397)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 39, i32 0, float %398, float %397, float %398, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %160, float %167, float %174, float %181)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDGPU.rsq(float) #2

; Function Attrs: readnone
declare float @llvm.AMDGPU.cndlt(float, float, float) #2

; Function Attrs: readonly
declare float @fabs(float) #3

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

; Function Attrs: readnone
declare float @llvm.AMDIL.exp.(float) #2

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }
attributes #3 = { readonly }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg92, %SGPR6_SGPR7 in %vreg95, %VGPR0 in %vreg98

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 8; mem:LD16[%106](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%VGPR1_VGPR2_VGPR3_VGPR4<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%11](align=8)(tbaa=!"const")
	S_WAITCNT 112
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 91; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 90; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR4, %VGPR6, %VGPR5, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%98](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%VGPR8_VGPR9_VGPR10_VGPR11<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 89; mem:LD4[<unknown>]
	S_WAITCNT 112
	%VGPR12<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 88; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR13<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR14<def> = V_MAD_F32 %VGPR8, %VGPR13, %VGPR12, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR15<def> = V_MUL_F32_e32 %VGPR14, %VGPR7, %EXEC<imp-use>
	%VGPR16<def> = V_MAD_F32 %VGPR3, %VGPR6, %VGPR5, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR17<def> = V_MUL_F32_e32 %VGPR15, %VGPR16, %EXEC<imp-use>
	%VGPR18<def> = V_MAD_F32 %VGPR10, %VGPR13, %VGPR12, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR19<def> = V_MUL_F32_e32 %VGPR18, %VGPR7, %EXEC<imp-use>
	%VGPR20<def> = V_MAD_F32 %VGPR1, %VGPR6, %VGPR5, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR20<def> = V_ADD_F32_e32 1.000000e-03, %VGPR20<kill>, %EXEC<imp-use>
	%VGPR21<def> = V_MUL_F32_e32 %VGPR19, %VGPR20, %EXEC<imp-use>
	%VGPR17<def> = V_SUB_F32_e32 %VGPR21<kill>, %VGPR17<kill>, %EXEC<imp-use>
	%VGPR22<def> = V_MAD_F32 %VGPR2, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR1_VGPR2_VGPR3_VGPR4<imp-use,kill>
	%VGPR1<def> = V_MUL_F32_e32 %VGPR19<kill>, %VGPR22, %EXEC<imp-use>
	%VGPR2<def> = V_MAD_F32 %VGPR9, %VGPR13<kill>, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR8_VGPR9_VGPR10_VGPR11<imp-use,kill>
	%VGPR11<def> = V_ADD_F32_e32 1.000000e-03, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_MUL_F32_e32 %VGPR11, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_MUL_F32_e32 %VGPR2, %VGPR16, %EXEC<imp-use>
	%VGPR3<def> = V_SUB_F32_e32 %VGPR3<kill>, %VGPR1<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 16; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR9<def> = V_MOV_B32_e32 %SGPR4, %EXEC<imp-use>
	%VGPR1<def> = V_MUL_F32_e64 %SGPR4, %VGPR9, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 20; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR10<def> = V_MOV_B32_e32 %SGPR5, %EXEC<imp-use>
	%VGPR1<def> = V_MAD_F32 %SGPR5, %VGPR10, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 24; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR12<def> = V_MOV_B32_e32 %SGPR8, %EXEC<imp-use>
	%VGPR1<def> = V_MAD_F32 %SGPR8, %VGPR12, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_RCP_F32_e32 %VGPR1<kill>, %EXEC<imp-use>
	%VGPR13<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR4, %EXEC<imp-use>
	%VGPR1<def> = V_MUL_F32_e32 %VGPR13, %VGPR3, %EXEC<imp-use>
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 17; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR19<def> = V_MOV_B32_e32 %SGPR5, %EXEC<imp-use>
	%VGPR5<def> = V_MUL_F32_e64 %SGPR5, %VGPR19, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR9<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 21; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR21<def> = V_MOV_B32_e32 %SGPR9, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %SGPR9, %VGPR21, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR10<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 25; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR23<def> = V_MOV_B32_e32 %SGPR10, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %SGPR10, %VGPR23, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_RCP_F32_e32 %VGPR5<kill>, %EXEC<imp-use>
	%VGPR24<def> = V_MUL_F32_e32 %SGPR9<kill>, %VGPR5, %EXEC<imp-use>
	%VGPR1<def> = V_MAD_F32 %VGPR24, %VGPR17, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %VGPR15<kill>, %VGPR22, %EXEC<imp-use>
	%VGPR2<def> = V_MUL_F32_e32 %VGPR2<kill>, %VGPR20, %EXEC<imp-use>
	%VGPR2<def> = V_SUB_F32_e32 %VGPR6<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%SGPR9<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 18; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR15<def> = V_MOV_B32_e32 %SGPR9, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e64 %SGPR9, %VGPR15, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR11<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 22; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR25<def> = V_MOV_B32_e32 %SGPR11, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %SGPR11, %VGPR25, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR12<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 26; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR27<def> = V_MOV_B32_e32 %SGPR12, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %SGPR12, %VGPR27, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_RCP_F32_e32 %VGPR6<kill>, %EXEC<imp-use>
	%VGPR28<def> = V_MUL_F32_e32 %SGPR11<kill>, %VGPR6, %EXEC<imp-use>
	%VGPR1<def> = V_MAD_F32 %VGPR28, %VGPR2, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR29<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR4, %EXEC<imp-use>
	%VGPR7<def> = V_MUL_F32_e32 %VGPR29, %VGPR3, %EXEC<imp-use>
	%VGPR30<def> = V_MUL_F32_e32 %SGPR5<kill>, %VGPR5, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR30, %VGPR17, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR32<def> = V_MUL_F32_e32 %SGPR9<kill>, %VGPR6, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR32, %VGPR2, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_F32_e32 %VGPR7, %VGPR7, %EXEC<imp-use>
	%VGPR8<def> = V_MAD_F32 %VGPR1, %VGPR1, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR33<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR4<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_MUL_F32_e32 %VGPR33, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR34<def> = V_MUL_F32_e32 %SGPR10<kill>, %VGPR5<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_MAD_F32 %VGPR34, %VGPR17<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR17<def> = V_MUL_F32_e32 %SGPR12<kill>, %VGPR6<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR17, %VGPR2<kill>, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR2<def> = V_MAD_F32 %VGPR6, %VGPR6, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_RSQ_LEGACY_F32_e32 %VGPR2<kill>, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 0; mem:LD16[%89](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%VGPR2_VGPR3_VGPR4_VGPR5<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR21<def> = V_MUL_F32_e64 %VGPR3, %VGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR10<def> = V_MAD_F32 %VGPR2, %VGPR10<kill>, %VGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR10<def> = V_MAD_F32 %VGPR4, %VGPR25<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 23; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR21<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR21<def> = V_MAD_F32 %VGPR5, %VGPR21<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 33; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR36<def> = V_SUBREV_F32_e32 %SGPR8, %VGPR21, %EXEC<imp-use>
	%VGPR10<def> = V_MUL_F32_e64 %VGPR3, %VGPR19<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_MAD_F32 %VGPR2, %VGPR9<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_MAD_F32 %VGPR4, %VGPR15<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 19; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR10<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR26<def> = V_MAD_F32 %VGPR5, %VGPR10<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR9<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 32; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR9<def> = V_SUBREV_F32_e32 %SGPR9, %VGPR26, %EXEC<imp-use>
	%VGPR9<def> = V_MUL_F32_e32 %VGPR9<kill>, %VGPR9, %EXEC<imp-use>
	%VGPR9<def> = V_MAD_F32 %VGPR36, %VGPR36, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR10<def> = V_MUL_F32_e64 %VGPR3, %VGPR23<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR10<def> = V_MAD_F32 %VGPR2, %VGPR12<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR10<def> = V_MAD_F32 %VGPR4, %VGPR27<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 27; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR12<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR31<def> = V_MAD_F32 %VGPR5, %VGPR12<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR57<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 34; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR10<def> = V_SUBREV_F32_e32 %SGPR57, %VGPR31, %EXEC<imp-use>
	%VGPR9<def> = V_MAD_F32 %VGPR10<kill>, %VGPR10, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR10<def> = V_RSQ_LEGACY_F32_e32 %VGPR9, %EXEC<imp-use>
	%VGPR10<def> = V_MUL_F32_e32 %VGPR10<kill>, %VGPR9, %EXEC<imp-use>
	%VGPR9<def> = V_ADD_F32_e64 %VGPR9<kill>, 0, 0, 0, 0, 1, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_GT_F32_e64 0, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR45<def> = V_CNDMASK_B32_e64 0.000000e+00, %VGPR10<kill>, %SGPR4_SGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_MUL_F32_e32 %VGPR13, %VGPR14, %EXEC<imp-use>
	%VGPR9<def> = V_MAD_F32 %VGPR24, %VGPR11, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_MAD_F32 %VGPR28, %VGPR18, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR10<def> = V_MUL_F32_e32 %VGPR29, %VGPR14, %EXEC<imp-use>
	%VGPR10<def> = V_MAD_F32 %VGPR30, %VGPR11, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR10<def> = V_MAD_F32 %VGPR32, %VGPR18, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_MUL_F32_e32 %VGPR10, %VGPR10, %EXEC<imp-use>
	%VGPR12<def> = V_MAD_F32 %VGPR9, %VGPR9, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR14<def> = V_MUL_F32_e32 %VGPR33, %VGPR14<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_MAD_F32 %VGPR34, %VGPR11<kill>, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR11<def> = V_MAD_F32 %VGPR17, %VGPR18<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_MAD_F32 %VGPR11, %VGPR11, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_RSQ_LEGACY_F32_e32 %VGPR12<kill>, %EXEC<imp-use>
	%VGPR13<def> = V_MUL_F32_e32 %VGPR13<kill>, %VGPR20, %EXEC<imp-use>
	%VGPR13<def> = V_MAD_F32 %VGPR24<kill>, %VGPR22, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_MAD_F32 %VGPR28<kill>, %VGPR16, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR14<def> = V_MUL_F32_e32 %VGPR29<kill>, %VGPR20, %EXEC<imp-use>
	%VGPR14<def> = V_MAD_F32 %VGPR30<kill>, %VGPR22, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR14<def> = V_MAD_F32 %VGPR32<kill>, %VGPR16, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR15<def> = V_MUL_F32_e32 %VGPR14, %VGPR14, %EXEC<imp-use>
	%VGPR18<def> = V_MAD_F32 %VGPR13, %VGPR13, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR15<def> = V_MUL_F32_e32 %VGPR33<kill>, %VGPR20<kill>, %EXEC<imp-use>
	%VGPR15<def> = V_MAD_F32 %VGPR34<kill>, %VGPR22<kill>, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR15<def> = V_MAD_F32 %VGPR17<kill>, %VGPR16<kill>, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR16<def> = V_MAD_F32 %VGPR15, %VGPR15, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR16<def> = V_RSQ_LEGACY_F32_e32 %VGPR16<kill>, %EXEC<imp-use>
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 32; mem:LD16[%140](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%VGPR17_VGPR18_VGPR19_VGPR20<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %VGPR0, 0, %EXEC<imp-use>
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 28; mem:LD16[%135](align=8)(tbaa=!"const")
	S_WAITCNT 112
	%VGPR32_VGPR33_VGPR34_VGPR35<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %VGPR0, 0, %EXEC<imp-use>
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 24; mem:LD16[%130](align=8)(tbaa=!"const")
	S_WAITCNT 112
	%VGPR27_VGPR28_VGPR29_VGPR30<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %VGPR0, 0, %EXEC<imp-use>
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 20; mem:LD16[%125](align=8)(tbaa=!"const")
	S_WAITCNT 112
	%VGPR41_VGPR42_VGPR43_VGPR44<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %VGPR0, 0, %EXEC<imp-use>
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 16; mem:LD16[%120](align=8)(tbaa=!"const")
	S_WAITCNT 112
	%VGPR37_VGPR38_VGPR39_VGPR40<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %VGPR0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 12; mem:LD16[%115](align=8)(tbaa=!"const")
	S_WAITCNT 112
	%VGPR22_VGPR23_VGPR24_VGPR25<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	%SGPR7<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 87; mem:LD4[<unknown>]
	%SGPR10<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 86; mem:LD4[<unknown>]
	%SGPR11<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 85; mem:LD4[<unknown>]
	%SGPR12<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 84; mem:LD4[<unknown>]
	%SGPR13<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 83; mem:LD4[<unknown>]
	%SGPR14<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 82; mem:LD4[<unknown>]
	%SGPR15<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 81; mem:LD4[<unknown>]
	%SGPR16<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 80; mem:LD4[<unknown>]
	%SGPR17<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 79; mem:LD4[<unknown>]
	%SGPR18<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 78; mem:LD4[<unknown>]
	%SGPR19<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 77; mem:LD4[<unknown>]
	%SGPR20<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 76; mem:LD4[<unknown>]
	%SGPR21<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 75; mem:LD4[<unknown>]
	%SGPR22<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 74; mem:LD4[<unknown>]
	%SGPR23<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 73; mem:LD4[<unknown>]
	%SGPR24<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 72; mem:LD4[<unknown>]
	%SGPR25<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 71; mem:LD4[<unknown>]
	%SGPR26<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 70; mem:LD4[<unknown>]
	%SGPR27<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 69; mem:LD4[<unknown>]
	%SGPR28<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 68; mem:LD4[<unknown>]
	%SGPR29<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 67; mem:LD4[<unknown>]
	%SGPR30<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 66; mem:LD4[<unknown>]
	%SGPR31<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 65; mem:LD4[<unknown>]
	%SGPR32<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 64; mem:LD4[<unknown>]
	%SGPR33<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 63; mem:LD4[<unknown>]
	%SGPR34<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 62; mem:LD4[<unknown>]
	%SGPR35<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 61; mem:LD4[<unknown>]
	%SGPR36<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 60; mem:LD4[<unknown>]
	%SGPR37<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 59; mem:LD4[<unknown>]
	%SGPR38<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 58; mem:LD4[<unknown>]
	%SGPR39<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 57; mem:LD4[<unknown>]
	%SGPR40<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 56; mem:LD4[<unknown>]
	%SGPR6<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 52; mem:LD4[<unknown>]
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 29; mem:LD4[<unknown>]
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 28; mem:LD4[<unknown>]
	%SGPR41<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 15; mem:LD4[<unknown>]
	%SGPR42<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 14; mem:LD4[<unknown>]
	%SGPR43<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 13; mem:LD4[<unknown>]
	%SGPR44<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 12; mem:LD4[<unknown>]
	%SGPR45<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 11; mem:LD4[<unknown>]
	%SGPR46<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 10; mem:LD4[<unknown>]
	%SGPR47<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 9; mem:LD4[<unknown>]
	%SGPR48<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 8; mem:LD4[<unknown>]
	%SGPR49<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 7; mem:LD4[<unknown>]
	%SGPR50<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 6; mem:LD4[<unknown>]
	%SGPR51<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 5; mem:LD4[<unknown>]
	%SGPR52<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 4; mem:LD4[<unknown>]
	%SGPR53<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 3; mem:LD4[<unknown>]
	%SGPR54<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2; mem:LD4[<unknown>]
	%SGPR55<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1; mem:LD4[<unknown>]
	%SGPR56<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 0; mem:LD4[<unknown>]
	%SGPR60<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 40; mem:LD4[<unknown>]
	S_WAITCNT 112
	%SGPR58_SGPR59<def> = V_CMP_GT_F32_e64 %SGPR60, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR65<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	%SGPR58_SGPR59<def> = S_AND_SAVEEXEC_B64 %SGPR58_SGPR59, %EXEC<imp-def>, %EXEC<imp-use>
	%SGPR58_SGPR59<def> = S_XOR_B64 %EXEC, %SGPR58_SGPR59
	S_CBRANCH_EXECZ <BB#2>, %EXEC
    Successors according to CFG: BB#1(16) BB#2(16)

BB#1: derived from LLVM BB %IF
    Live Ins: %SGPR0_SGPR1_SGPR2_SGPR3 %SGPR4 %SGPR5 %SGPR6 %VGPR22_VGPR23_VGPR24_VGPR25 %VGPR37_VGPR38_VGPR39_VGPR40 %VGPR41_VGPR42_VGPR43_VGPR44 %VGPR27_VGPR28_VGPR29_VGPR30 %VGPR32_VGPR33_VGPR34_VGPR35 %VGPR17_VGPR18_VGPR19_VGPR20 %VGPR26 %VGPR21 %VGPR31 %VGPR45 %VGPR1 %VGPR7 %VGPR6 %VGPR2_VGPR3_VGPR4_VGPR5 %SGPR8 %VGPR36 %SGPR9 %SGPR57 %VGPR9 %VGPR10 %VGPR11 %VGPR13 %VGPR14 %VGPR15 %SGPR7 %SGPR10 %SGPR11 %SGPR12 %SGPR13 %SGPR14 %SGPR15 %SGPR16 %SGPR17 %SGPR18 %SGPR19 %SGPR20 %SGPR21 %SGPR22 %SGPR23 %SGPR24 %SGPR25 %SGPR26 %SGPR27 %SGPR28 %SGPR29 %SGPR30 %SGPR31 %SGPR32 %SGPR33 %SGPR34 %SGPR35 %SGPR36 %SGPR37 %SGPR38 %SGPR39 %SGPR40 %SGPR41 %SGPR42 %SGPR43 %SGPR44 %SGPR45 %SGPR46 %SGPR47 %SGPR48 %SGPR49 %SGPR50 %SGPR51 %SGPR52 %SGPR53 %SGPR54 %SGPR55 %SGPR56 %SGPR60 %SGPR58_SGPR59 %VGPR8 %VGPR16 %VGPR12
    Predecessors according to CFG: BB#0
	%VGPR0<def> = V_MOV_B32_e32 %SGPR60<kill>, %EXEC<imp-use>
	%SGPR60<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 49; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR46<def> = V_MOV_B32_e32 %SGPR60<kill>, %EXEC<imp-use>
	%VGPR47<def> = V_MUL_F32_e64 %SGPR8<kill>, %VGPR46, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 48; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR48<def> = V_MOV_B32_e32 %SGPR8<kill>, %EXEC<imp-use>
	%VGPR47<def> = V_MAD_F32 %SGPR9<kill>, %VGPR48, %VGPR47<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 50; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR49<def> = V_MOV_B32_e32 %SGPR8<kill>, %EXEC<imp-use>
	%VGPR47<def> = V_MAD_F32 %SGPR57<kill>, %VGPR49, %VGPR47<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 35; mem:LD4[<unknown>]
	%SGPR9<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 51; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR50<def> = V_MOV_B32_e32 %SGPR9, %EXEC<imp-use>
	%VGPR47<def> = V_MAD_F32 %SGPR8<kill>, %VGPR50<kill>, %VGPR47<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR46<def> = V_MUL_F32_e64 %VGPR21, %VGPR46<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR46<def> = V_MAD_F32 %VGPR26, %VGPR48<kill>, %VGPR46<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR46<def> = V_MAD_F32 %VGPR31, %VGPR49<kill>, %VGPR46<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR46<def> = V_ADD_F32_e32 %SGPR9<kill>, %VGPR46<kill>, %EXEC<imp-use>
	%VGPR48<def> = V_SUB_F32_e32 %VGPR46, %VGPR47, %EXEC<imp-use>
	%SGPR8_SGPR9<def> = V_CMP_GE_F32_e64 %VGPR48, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR49<def> = V_CNDMASK_B32_e64 %VGPR46, %VGPR47, %SGPR8_SGPR9, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR57<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 44; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR49<def> = V_SUBREV_F32_e32 %SGPR57, %VGPR49<kill>, %EXEC<imp-use>
	%SGPR60<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 47; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR50<def> = V_SUB_F32_e32 %SGPR60<kill>, %VGPR49, %EXEC<imp-use>
	%VGPR48<def> = V_ADD_F32_e64 %VGPR48<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%VGPR48<def> = V_ADD_F32_e32 1.000000e-03, %VGPR48<kill>, %EXEC<imp-use>
	%VGPR48<def> = V_RCP_F32_e32 %VGPR48<kill>, %EXEC<imp-use>
	%VGPR50<def> = V_MUL_F32_e32 %VGPR50<kill>, %VGPR48, %EXEC<imp-use>
	%VGPR50<def> = V_ADD_F32_e64 0, %VGPR50<kill>, 0, 1, 0, 0, %EXEC<imp-use>
	%SGPR60<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 46; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR51<def> = V_SUB_F32_e32 %SGPR60<kill>, %VGPR49, %EXEC<imp-use>
	%VGPR48<def> = V_MUL_F32_e32 %VGPR51<kill>, %VGPR48<kill>, %EXEC<imp-use>
	%VGPR48<def> = V_ADD_F32_e64 0, %VGPR48<kill>, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR48<def> = V_SUB_F32_e32 %VGPR48<kill>, %VGPR50<kill>, %EXEC<imp-use>
	%VGPR48<def> = V_ADD_F32_e64 0, %VGPR48<kill>, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR46<def> = V_CNDMASK_B32_e64 %VGPR47<kill>, %VGPR46<kill>, %SGPR8_SGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR46<def> = V_SUBREV_F32_e32 %SGPR57<kill>, %VGPR46<kill>, %EXEC<imp-use>
	%SGPR8<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 41; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR46<def> = V_MUL_F32_e32 %SGPR8, %VGPR46<kill>, %EXEC<imp-use>
	%VGPR46<def> = V_SUB_F32_e32 1.000000e+00, %VGPR46<kill>, %EXEC<imp-use>
	%VGPR46<def> = V_ADD_F32_e64 0, %VGPR46<kill>, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR47<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR49<kill>, %EXEC<imp-use>
	%VGPR47<def> = V_SUB_F32_e32 1.000000e+00, %VGPR47<kill>, %EXEC<imp-use>
	%VGPR47<def> = V_ADD_F32_e64 0, %VGPR47<kill>, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR46<def> = V_ADD_F32_e32 %VGPR47<kill>, %VGPR46<kill>, %EXEC<imp-use>
	%SGPR8<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 45; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR46<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR46<kill>, %EXEC<imp-use>
	%VGPR46<def> = V_ADD_F32_e64 0, %VGPR46<kill>, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR46<def> = V_MUL_F32_e32 %VGPR48<kill>, %VGPR46<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_F32_e64 %VGPR45, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR0<kill>, %VGPR46<kill>, %EXEC<imp-use>
	%VGPR65<def> = V_ADD_F32_e64 0, %VGPR0<kill>, 0, 1, 0, 0, %EXEC<imp-use>
    Successors according to CFG: BB#2

BB#2: derived from LLVM BB %ENDIF
    Live Ins: %SGPR0_SGPR1_SGPR2_SGPR3 %SGPR4 %SGPR5 %SGPR6 %VGPR22_VGPR23_VGPR24_VGPR25 %VGPR37_VGPR38_VGPR39_VGPR40 %VGPR41_VGPR42_VGPR43_VGPR44 %VGPR27_VGPR28_VGPR29_VGPR30 %VGPR32_VGPR33_VGPR34_VGPR35 %VGPR17_VGPR18_VGPR19_VGPR20 %VGPR26 %VGPR21 %VGPR31 %VGPR45 %VGPR1 %VGPR7 %VGPR6 %VGPR2_VGPR3_VGPR4_VGPR5 %VGPR36 %VGPR9 %VGPR10 %VGPR11 %VGPR13 %VGPR14 %VGPR15 %SGPR7 %SGPR10 %SGPR11 %SGPR12 %SGPR13 %SGPR14 %SGPR15 %SGPR16 %SGPR17 %SGPR18 %SGPR19 %SGPR20 %SGPR21 %SGPR22 %SGPR23 %SGPR24 %SGPR25 %SGPR26 %SGPR27 %SGPR28 %SGPR29 %SGPR30 %SGPR31 %SGPR32 %SGPR33 %SGPR34 %SGPR35 %SGPR36 %SGPR37 %SGPR38 %SGPR39 %SGPR40 %SGPR41 %SGPR42 %SGPR43 %SGPR44 %SGPR45 %SGPR46 %SGPR47 %SGPR48 %SGPR49 %SGPR50 %SGPR51 %SGPR52 %SGPR53 %SGPR54 %SGPR55 %SGPR56 %SGPR58_SGPR59 %VGPR8 %VGPR16 %VGPR12 %VGPR65
    Predecessors according to CFG: BB#0 BB#1
	%EXEC<def> = S_OR_B64 %EXEC, %SGPR58_SGPR59
	%VGPR54<def> = V_MOV_B32_e32 %SGPR7<kill>, %EXEC<imp-use>
	%VGPR59<def> = V_MOV_B32_e32 %SGPR10<kill>, %EXEC<imp-use>
	%VGPR64<def> = V_MOV_B32_e32 %SGPR11<kill>, %EXEC<imp-use>
	%VGPR63<def> = V_MOV_B32_e32 %SGPR12<kill>, %EXEC<imp-use>
	%VGPR53<def> = V_MOV_B32_e32 %SGPR13<kill>, %EXEC<imp-use>
	%VGPR57<def> = V_MOV_B32_e32 %SGPR14<kill>, %EXEC<imp-use>
	%VGPR62<def> = V_MOV_B32_e32 %SGPR15<kill>, %EXEC<imp-use>
	%VGPR61<def> = V_MOV_B32_e32 %SGPR16<kill>, %EXEC<imp-use>
	%VGPR48<def> = V_MOV_B32_e32 %SGPR17<kill>, %EXEC<imp-use>
	%VGPR52<def> = V_MOV_B32_e32 %SGPR18<kill>, %EXEC<imp-use>
	%VGPR60<def> = V_MOV_B32_e32 %SGPR19<kill>, %EXEC<imp-use>
	%VGPR58<def> = V_MOV_B32_e32 %SGPR20<kill>, %EXEC<imp-use>
	%VGPR47<def> = V_MOV_B32_e32 %SGPR21<kill>, %EXEC<imp-use>
	%VGPR51<def> = V_MOV_B32_e32 %SGPR22<kill>, %EXEC<imp-use>
	%VGPR56<def> = V_MOV_B32_e32 %SGPR23<kill>, %EXEC<imp-use>
	%VGPR55<def> = V_MOV_B32_e32 %SGPR24<kill>, %EXEC<imp-use>
	%VGPR71<def> = V_MOV_B32_e32 %SGPR25<kill>, %EXEC<imp-use>
	%VGPR76<def> = V_MOV_B32_e32 %SGPR26<kill>, %EXEC<imp-use>
	%VGPR81<def> = V_MOV_B32_e32 %SGPR27<kill>, %EXEC<imp-use>
	%VGPR80<def> = V_MOV_B32_e32 %SGPR28<kill>, %EXEC<imp-use>
	%VGPR70<def> = V_MOV_B32_e32 %SGPR29<kill>, %EXEC<imp-use>
	%VGPR74<def> = V_MOV_B32_e32 %SGPR30<kill>, %EXEC<imp-use>
	%VGPR79<def> = V_MOV_B32_e32 %SGPR31<kill>, %EXEC<imp-use>
	%VGPR78<def> = V_MOV_B32_e32 %SGPR32<kill>, %EXEC<imp-use>
	%VGPR67<def> = V_MOV_B32_e32 %SGPR33<kill>, %EXEC<imp-use>
	%VGPR69<def> = V_MOV_B32_e32 %SGPR34<kill>, %EXEC<imp-use>
	%VGPR77<def> = V_MOV_B32_e32 %SGPR35<kill>, %EXEC<imp-use>
	%VGPR75<def> = V_MOV_B32_e32 %SGPR36<kill>, %EXEC<imp-use>
	%VGPR66<def> = V_MOV_B32_e32 %SGPR37<kill>, %EXEC<imp-use>
	%VGPR68<def> = V_MOV_B32_e32 %SGPR38<kill>, %EXEC<imp-use>
	%VGPR73<def> = V_MOV_B32_e32 %SGPR39<kill>, %EXEC<imp-use>
	%VGPR72<def> = V_MOV_B32_e32 %SGPR40<kill>, %EXEC<imp-use>
	%VGPR82<def> = V_MOV_B32_e32 %SGPR41<kill>, %EXEC<imp-use>
	%VGPR84<def> = V_MOV_B32_e32 %SGPR42<kill>, %EXEC<imp-use>
	%VGPR88<def> = V_MOV_B32_e32 %SGPR43<kill>, %EXEC<imp-use>
	%VGPR87<def> = V_MOV_B32_e32 %SGPR44<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MOV_B32_e32 %SGPR45<kill>, %EXEC<imp-use>
	%VGPR46<def> = V_MOV_B32_e32 %SGPR46<kill>, %EXEC<imp-use>
	%VGPR50<def> = V_MOV_B32_e32 %SGPR47<kill>, %EXEC<imp-use>
	%VGPR49<def> = V_MOV_B32_e32 %SGPR48<kill>, %EXEC<imp-use>
	%VGPR86<def> = V_MOV_B32_e32 %SGPR49<kill>, %EXEC<imp-use>
	%VGPR89<def> = V_MOV_B32_e32 %SGPR50<kill>, %EXEC<imp-use>
	%VGPR93<def> = V_MOV_B32_e32 %SGPR51<kill>, %EXEC<imp-use>
	%VGPR92<def> = V_MOV_B32_e32 %SGPR52<kill>, %EXEC<imp-use>
	%VGPR83<def> = V_MOV_B32_e32 %SGPR53<kill>, %EXEC<imp-use>
	%VGPR85<def> = V_MOV_B32_e32 %SGPR54<kill>, %EXEC<imp-use>
	%VGPR91<def> = V_MOV_B32_e32 %SGPR55<kill>, %EXEC<imp-use>
	%VGPR90<def> = V_MOV_B32_e32 %SGPR56<kill>, %EXEC<imp-use>
	%SGPR8_SGPR9<def> = V_CMP_GT_F32_e64 %SGPR6, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR94<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	%SGPR8_SGPR9<def> = S_AND_SAVEEXEC_B64 %SGPR8_SGPR9, %EXEC<imp-def>, %EXEC<imp-use>
	%SGPR8_SGPR9<def> = S_XOR_B64 %EXEC, %SGPR8_SGPR9
	S_CBRANCH_EXECZ <BB#4>, %EXEC
    Successors according to CFG: BB#3(16) BB#4(16)

BB#3: derived from LLVM BB %IF68
    Live Ins: %SGPR0_SGPR1_SGPR2_SGPR3 %VGPR90 %VGPR91 %VGPR85 %VGPR83 %VGPR92 %VGPR93 %VGPR89 %VGPR86 %VGPR49 %VGPR50 %VGPR46 %VGPR0 %VGPR87 %VGPR88 %VGPR84 %VGPR82 %SGPR4 %SGPR5 %SGPR6 %VGPR72 %VGPR73 %VGPR68 %VGPR66 %VGPR75 %VGPR77 %VGPR69 %VGPR67 %VGPR78 %VGPR79 %VGPR74 %VGPR70 %VGPR80 %VGPR81 %VGPR76 %VGPR71 %VGPR55 %VGPR56 %VGPR51 %VGPR47 %VGPR58 %VGPR60 %VGPR52 %VGPR48 %VGPR61 %VGPR62 %VGPR57 %VGPR53 %VGPR63 %VGPR64 %VGPR59 %VGPR54 %VGPR22_VGPR23_VGPR24_VGPR25 %VGPR37_VGPR38_VGPR39_VGPR40 %VGPR41_VGPR42_VGPR43_VGPR44 %VGPR27_VGPR28_VGPR29_VGPR30 %VGPR32_VGPR33_VGPR34_VGPR35 %VGPR17_VGPR18_VGPR19_VGPR20 %VGPR26 %VGPR21 %VGPR31 %VGPR45 %VGPR1 %VGPR7 %VGPR6 %VGPR2_VGPR3_VGPR4_VGPR5 %VGPR36 %VGPR9 %VGPR10 %VGPR11 %VGPR13 %VGPR14 %VGPR15 %SGPR8_SGPR9 %VGPR8 %VGPR16 %VGPR12 %VGPR65
    Predecessors according to CFG: BB#2
	%SGPR7<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 54; mem:LD4[<unknown>]
	%SGPR10<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 55; mem:LD4[<unknown>]
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 53; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR94<def> = V_MOV_B32_e32 %SGPR7<kill>, %EXEC<imp-use>
	%VGPR94<def> = V_SUB_F32_e64 %VGPR45, %VGPR94<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR94<def> = V_MUL_F32_e32 %SGPR6<kill>, %VGPR94<kill>, %EXEC<imp-use>
	%VGPR94<def> = V_MUL_F32_e32 -1.442695e+00, %VGPR94<kill>, %EXEC<imp-use>
	%VGPR94<def> = V_EXP_F32_e32 %VGPR94<kill>, %EXEC<imp-use>
	%VGPR94<def> = V_SUB_F32_e32 1.000000e+00, %VGPR94<kill>, %EXEC<imp-use>
	%VGPR94<def> = V_ADD_F32_e64 0, %VGPR94<kill>, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR95<def> = V_MOV_B32_e32 1.123596e-04, %EXEC<imp-use>
	%VGPR45<def> = V_MUL_F32_e32 %VGPR45<kill>, %VGPR95<kill>, %EXEC<imp-use>
	%VGPR45<def> = V_ADD_F32_e64 0, %VGPR45<kill>, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR45<def> = V_MUL_F32_e32 %SGPR10<kill>, %VGPR45<kill>, %EXEC<imp-use>
	%VGPR45<def> = V_SUB_F32_e32 1.000000e+00, %VGPR45<kill>, %EXEC<imp-use>
	%VGPR36<def> = V_MUL_F32_e32 %VGPR36<kill>, %VGPR45<kill>, %EXEC<imp-use>
	%VGPR36<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR36<kill>, %EXEC<imp-use>
	%VGPR36<def> = V_SUB_F32_e32 1.000000e+00, %VGPR36<kill>, %EXEC<imp-use>
	%VGPR36<def> = V_ADD_F32_e64 0, %VGPR36<kill>, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR36<def> = V_MUL_F32_e32 %VGPR36<kill>, %VGPR36, %EXEC<imp-use>
	%VGPR94<def> = V_MUL_F32_e32 %VGPR94<kill>, %VGPR36<kill>, %EXEC<imp-use>
    Successors according to CFG: BB#4

BB#4: derived from LLVM BB %ENDIF67
    Live Ins: %VGPR90 %VGPR91 %VGPR85 %VGPR83 %VGPR92 %VGPR93 %VGPR89 %VGPR86 %VGPR49 %VGPR50 %VGPR46 %VGPR0 %VGPR87 %VGPR88 %VGPR84 %VGPR82 %SGPR4 %SGPR5 %VGPR72 %VGPR73 %VGPR68 %VGPR66 %VGPR75 %VGPR77 %VGPR69 %VGPR67 %VGPR78 %VGPR79 %VGPR74 %VGPR70 %VGPR80 %VGPR81 %VGPR76 %VGPR71 %VGPR55 %VGPR56 %VGPR51 %VGPR47 %VGPR58 %VGPR60 %VGPR52 %VGPR48 %VGPR61 %VGPR62 %VGPR57 %VGPR53 %VGPR63 %VGPR64 %VGPR59 %VGPR54 %VGPR22_VGPR23_VGPR24_VGPR25 %VGPR37_VGPR38_VGPR39_VGPR40 %VGPR41_VGPR42_VGPR43_VGPR44 %VGPR27_VGPR28_VGPR29_VGPR30 %VGPR32_VGPR33_VGPR34_VGPR35 %VGPR17_VGPR18_VGPR19_VGPR20 %VGPR26 %VGPR21 %VGPR31 %VGPR1 %VGPR7 %VGPR6 %VGPR2_VGPR3_VGPR4_VGPR5 %VGPR9 %VGPR10 %VGPR11 %VGPR13 %VGPR14 %VGPR15 %SGPR8_SGPR9 %VGPR8 %VGPR16 %VGPR12 %VGPR65 %VGPR94
    Predecessors according to CFG: BB#2 BB#3
	%EXEC<def> = S_OR_B64 %EXEC, %SGPR8_SGPR9
	%VGPR36<def> = V_MUL_F32_e64 %VGPR3, %VGPR88<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR36<def> = V_MAD_F32 %VGPR2, %VGPR87<kill>, %VGPR36<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR36<def> = V_MAD_F32 %VGPR4, %VGPR84<kill>, %VGPR36<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR36<def> = V_MAD_F32 %VGPR5, %VGPR82<kill>, %VGPR36<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR45<def> = V_MUL_F32_e64 %VGPR3, %VGPR93<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR45<def> = V_MAD_F32 %VGPR2, %VGPR92<kill>, %VGPR45<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR45<def> = V_MAD_F32 %VGPR4, %VGPR89<kill>, %VGPR45<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR45<def> = V_MAD_F32 %VGPR5, %VGPR86<kill>, %VGPR45<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR82<def> = V_MUL_F32_e32 5.000000e-01, %VGPR45, %EXEC<imp-use>
	%VGPR82<def> = V_MAD_F32 %VGPR36, 5.000000e-01, %VGPR82<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR84<def> = V_MUL_F32_e64 %VGPR3, %VGPR91<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR84<def> = V_MAD_F32 %VGPR2, %VGPR90<kill>, %VGPR84<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR84<def> = V_MAD_F32 %VGPR4, %VGPR85<kill>, %VGPR84<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR83<def> = V_MAD_F32 %VGPR5, %VGPR83<kill>, %VGPR84<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR84<def> = V_MUL_F32_e32 5.000000e-01, %VGPR83, %EXEC<imp-use>
	%VGPR84<def> = V_MAD_F32 %VGPR36, 5.000000e-01, %VGPR84<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 32, 0, 0, 0, %VGPR84<kill>, %VGPR82<kill>, %VGPR65<kill>, %VGPR94<kill>, %EXEC<imp-use>
	EXP 15, 33, 0, 0, 0, %VGPR26<kill>, %VGPR21<kill>, %VGPR31<kill>, %VGPR36, %EXEC<imp-use>
	S_WAITCNT 1807
	%VGPR21<def> = V_MUL_F32_e64 %VGPR42, %VGPR81<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR21<def> = V_MAD_F32 %VGPR41, %VGPR80<kill>, %VGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR21<def> = V_MAD_F32 %VGPR43, %VGPR76<kill>, %VGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR21<def> = V_MAD_F32 %VGPR44, %VGPR71<kill>, %VGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR26<def> = V_MUL_F32_e64 %VGPR42, %VGPR79<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR26<def> = V_MAD_F32 %VGPR41, %VGPR78<kill>, %VGPR26<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR26<def> = V_MAD_F32 %VGPR43, %VGPR74<kill>, %VGPR26<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR26<def> = V_MAD_F32 %VGPR44, %VGPR70<kill>, %VGPR26<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR41_VGPR42_VGPR43_VGPR44<imp-use,kill>
	%VGPR31<def> = V_MUL_F32_e64 %VGPR38, %VGPR77<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR31<def> = V_MAD_F32 %VGPR37, %VGPR75<kill>, %VGPR31<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR31<def> = V_MAD_F32 %VGPR39, %VGPR69<kill>, %VGPR31<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR31<def> = V_MAD_F32 %VGPR40, %VGPR67<kill>, %VGPR31<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR41<def> = V_MUL_F32_e64 %VGPR38, %VGPR73<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR41<def> = V_MAD_F32 %VGPR37, %VGPR72<kill>, %VGPR41<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR41<def> = V_MAD_F32 %VGPR39, %VGPR68<kill>, %VGPR41<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR37<def> = V_MAD_F32 %VGPR40, %VGPR66<kill>, %VGPR41<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR37_VGPR38_VGPR39_VGPR40<imp-use,kill>
	EXP 15, 34, 0, 0, 0, %VGPR37<kill>, %VGPR31<kill>, %VGPR26<kill>, %VGPR21<kill>, %EXEC<imp-use>
	S_WAITCNT 1807
	%VGPR21<def> = V_MUL_F32_e64 %VGPR33, %VGPR64<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR21<def> = V_MAD_F32 %VGPR32, %VGPR63<kill>, %VGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR21<def> = V_MAD_F32 %VGPR34, %VGPR59<kill>, %VGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR21<def> = V_MAD_F32 %VGPR35, %VGPR54<kill>, %VGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR26<def> = V_MUL_F32_e64 %VGPR33, %VGPR62<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR26<def> = V_MAD_F32 %VGPR32, %VGPR61<kill>, %VGPR26<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR26<def> = V_MAD_F32 %VGPR34, %VGPR57<kill>, %VGPR26<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR26<def> = V_MAD_F32 %VGPR35, %VGPR53<kill>, %VGPR26<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR32_VGPR33_VGPR34_VGPR35<imp-use,kill>
	%VGPR31<def> = V_MUL_F32_e64 %VGPR28, %VGPR60<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR31<def> = V_MAD_F32 %VGPR27, %VGPR58<kill>, %VGPR31<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR31<def> = V_MAD_F32 %VGPR29, %VGPR52<kill>, %VGPR31<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR31<def> = V_MAD_F32 %VGPR30, %VGPR48<kill>, %VGPR31<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR32<def> = V_MUL_F32_e64 %VGPR28, %VGPR56<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR32<def> = V_MAD_F32 %VGPR27, %VGPR55<kill>, %VGPR32<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR32<def> = V_MAD_F32 %VGPR29, %VGPR51<kill>, %VGPR32<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR27<def> = V_MAD_F32 %VGPR30, %VGPR47<kill>, %VGPR32<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR27_VGPR28_VGPR29_VGPR30<imp-use,kill>
	EXP 15, 35, 0, 0, 0, %VGPR27<kill>, %VGPR31<kill>, %VGPR26<kill>, %VGPR21<kill>, %EXEC<imp-use>
	S_WAITCNT 1807
	%VGPR21<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
	%VGPR26<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR27<def> = V_MAD_F32 %VGPR23, %VGPR26, %VGPR21, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR21<def> = V_MAD_F32 %VGPR22, %VGPR26<kill>, %VGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR22_VGPR23_VGPR24_VGPR25<imp-use,kill>
	EXP 15, 36, 0, 0, 0, %VGPR17, %VGPR18, %VGPR21<kill>, %VGPR27<kill>, %EXEC<imp-use>, %VGPR17_VGPR18_VGPR19_VGPR20<imp-use,kill>
	%VGPR7<def> = V_MUL_F32_e64 %VGPR7<kill>, %VGPR8, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR15<def> = V_MUL_F32_e64 %VGPR15<kill>, %VGPR16, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_MUL_F32_e64 %VGPR13<kill>, %VGPR16, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR14<def> = V_MUL_F32_e64 %VGPR14<kill>, %VGPR16<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 37, 0, 0, 0, %VGPR14<kill>, %VGPR13<kill>, %VGPR15<kill>, %VGPR7<kill>, %EXEC<imp-use>
	S_WAITCNT 1807
	%VGPR7<def> = V_MUL_F32_e64 %VGPR9<kill>, %VGPR12, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_MUL_F32_e64 %VGPR10<kill>, %VGPR12, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e64 %VGPR6<kill>, %VGPR8, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_MUL_F32_e64 %VGPR1<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 38, 0, 0, 0, %VGPR1<kill>, %VGPR6<kill>, %VGPR9<kill>, %VGPR7, %EXEC<imp-use>
	S_WAITCNT 1807
	%VGPR1<def> = V_MUL_F32_e64 %VGPR11<kill>, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	EXP 15, 39, 0, 0, 0, %VGPR1<kill>, %VGPR7<kill>, %VGPR1, %VGPR6<kill>, %EXEC<imp-use>
	S_WAITCNT 1807
	%VGPR1<def> = V_MUL_F32_e64 %VGPR3, %VGPR50<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_MAD_F32 %VGPR2, %VGPR49<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_MAD_F32 %VGPR4, %VGPR46<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR5, %VGPR0<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>
	EXP 15, 12, 0, 1, 0, %VGPR83<kill>, %VGPR45<kill>, %VGPR0<kill>, %VGPR36<kill>, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_LOAD_DWORDX4 s[8:11], s[6:7], 8                            ; C0840708
	S_WAITCNT lgkmcnt(0)                                         ; BF8C007F
	BUFFER_LOAD_FORMAT_XYZW v[1:4], s[8:11][v0] + 0              ; E00C2000 80020100
	S_LOAD_DWORDX4 s[0:3], s[0:1], 0                             ; C0800100
	S_WAITCNT vmcnt(0) lgkmcnt(0)                                ; BF8C0070
	S_BUFFER_LOAD_DWORD s4, s[0:3], 91                           ; C202015B
	S_WAITCNT lgkmcnt(0)                                         ; BF8C007F
	V_MOV_B32_e32 v5, s4                                         ; 7E0A0204
	S_BUFFER_LOAD_DWORD s4, s[0:3], 90                           ; C202015A
	S_WAITCNT lgkmcnt(0)                                         ; BF8C007F
	V_MOV_B32_e32 v6, s4                                         ; 7E0C0204
	V_MAD_F32 v7, v4, v6, v5, 0, 0, 0, 0                         ; D2820007 04160D04
	S_LOAD_DWORDX4 s[8:11], s[6:7], 4                            ; C0840704
	S_WAITCNT lgkmcnt(0)                                         ; BF8C007F
	BUFFER_LOAD_FORMAT_XYZW v[8:11], s[8:11][v0] + 0             ; E00C2000 80020800
	S_BUFFER_LOAD_DWORD s4, s[0:3], 89                           ; C2020159
	S_WAITCNT vmcnt(0) lgkmcnt(0)                                ; BF8C0070
	V_MOV_B32_e32 v12, s4                                        ; 7E180204
	S_BUFFER_LOAD_DWORD s4, s[0:3], 88                           ; C2020158
	S_WAITCNT lgkmcnt(0)                                         ; BF8C007F
	V_MOV_B32_e32 v13, s4                                        ; 7E1A0204
	V_MAD_F32 v14, v8, v13, v12, 0, 0, 0, 0                      ; D282000E 04321B08
	V_MUL_F32_e32 v15, v14, v7                                   ; 101E0F0E
	V_MAD_F32 v16, v3, v6, v5, 0, 0, 0, 0                        ; D2820010 04160D03
	V_MUL_F32_e32 v17, v15, v16                                  ; 1022210F
	V_MAD_F32 v18, v10, v13, v12, 0, 0, 0, 0                     ; D2820012 04321B0A
	V_MUL_F32_e32 v19, v18, v7                                   ; 10260F12
	V_MAD_F32 v20, v1, v6, v5, 0, 0, 0, 0                        ; D2820014 04160D01
	V_ADD_F32_e32 v20, 1.000000e-03, v20                         ; 062828FF 3A83126F
	V_MUL_F32_e32 v21, v19, v20                                  ; 102A2913
	V_SUB_F32_e32 v17, v21, v17                                  ; 08222315
	V_MAD_F32 v22, v2, v6, v5, 0, 0, 0, 0                        ; D2820016 04160D02
	V_MUL_F32_e32 v1, v19, v22                                   ; 10022D13
	V_MAD_F32 v2, v9, v13, v12, 0, 0, 0, 0                       ; D2820002 04321B09
	V_ADD_F32_e32 v11, 1.000000e-03, v2                          ; 061604FF 3A83126F
	V_MUL_F32_e32 v2, v11, v7                                    ; 10040F0B
	V_MUL_F32_e32 v3, v2, v16                                    ; 10062102
	V_SUB_F32_e32 v3, v3, v1                                     ; 08060303
	S_BUFFER_LOAD_DWORD s4, s[0:3], 16                           ; C2020110
	S_WAITCNT lgkmcnt(0)                                         ; BF8C007F
	V_MOV_B32_e32 v9, s4                                         ; 7E120204
	V_MUL_F32_e64 v1, s4, v9, 0, 0, 0, 0                         ; D2100001 02021204
	S_BUFFER_LOAD_DWORD s5, s[0:3], 20                           ; C2028114
	S_WAITCNT lgkmcnt(0)                                         ; BF8C007F
	V_MOV_B32_e32 v10, s5                                        ; 7E140205
	V_MAD_F32 v1, s5, v10, v1, 0, 0, 0, 0                        ; D2820001 04061405
	S_BUFFER_LOAD_DWORD s8, s[0:3], 24                           ; C2040118
	S_WAITCNT lgkmcnt(0)                                         ; BF8C007F
	V_MOV_B32_e32 v12, s8                                        ; 7E180208
	V_MAD_F32 v1, s8, v12, v1, 0, 0, 0, 0                        ; D2820001 04061808
	V_RCP_F32_e32 v4, v1                                         ; 7E085501
	V_MUL_F32_e32 v13, s5, v4                                    ; 101A0805
	V_MUL_F32_e32 v1, v13, v3                                    ; 1002070D
	S_BUFFER_LOAD_DWORD s5, s[0:3], 17                           ; C2028111
	S_WAITCNT lgkmcnt(0)                                         ; BF8C007F
	V_MOV_B32_e32 v19, s5                                        ; 7E260205
	V_MUL_F32_e64 v5, s5, v19, 0, 0, 0, 0                        ; D2100005 02022605
	S_BUFFER_LOAD_DWORD s9, s[0:3], 21                           ; C2048115
	S_WAITCNT lgkmcnt(0)                                         ; BF8C007F
	V_MOV_B32_e32 v21, s9                                        ; 7E2A0209
	V_MAD_F32 v5, s9, v21, v5, 0, 0, 0, 0                        ; D2820005 04162A09
	S_BUFFER_LOAD_DWORD s10, s[0:3], 25                          ; C2050119
	S_WAITCNT lgkmcnt(0)                                         ; BF8C007F
	V_MOV_B32_e32 v23, s10                                       ; 7E2E020A
	V_MAD_F32 v5, s10, v23, v5, 0, 0, 0, 0                       ; D2820005 04162E0A
	V_RCP_F32_e32 v5, v5                                         ; 7E0A5505
	V_MUL_F32_e32 v24, s9, v5                                    ; 10300A09
	V_MAD_F32 v1, v24, v17, v1, 0, 0, 0, 0                       ; D2820001 04062318
	V_MUL_F32_e32 v6, v15, v22                                   ; 100C2D0F
	V_MUL_F32_e32 v2, v2, v20                                    ; 10042902
	V_SUB_F32_e32 v2, v6, v2                                     ; 08040506
	S_BUFFER_LOAD_DWORD s9, s[0:3], 18                           ; C2048112
	S_WAITCNT lgkmcnt(0)                                         ; BF8C007F
	V_MOV_B32_e32 v15, s9                                        ; 7E1E0209
	V_MUL_F32_e64 v6, s9, v15, 0, 0, 0, 0                        ; D2100006 02021E09
	S_BUFFER_LOAD_DWORD s11, s[0:3], 22                          ; C2058116
	S_WAITCNT lgkmcnt(0)                                         ; BF8C007F
	V_MOV_B32_e32 v25, s11                                       ; 7E32020B
	V_MAD_F32 v6, s11, v25, v6, 0, 0, 0, 0                       ; D2820006 041A320B
	S_BUFFER_LOAD_DWORD s12, s[0:3], 26                          ; C206011A
	S_WAITCNT lgkmcnt(0)                                         ; BF8C007F
	V_MOV_B32_e32 v27, s12                                       ; 7E36020C
	V_MAD_F32 v6, s12, v27, v6, 0, 0, 0, 0                       ; D2820006 041A360C
	V_RCP_F32_e32 v6, v6                                         ; 7E0C5506
	V_MUL_F32_e32 v28, s11, v6                                   ; 10380C0B
	V_MAD_F32 v1, v28, v2, v1, 0, 0, 0, 0                        ; D2820001 0406051C
	V_MUL_F32_e32 v29, s4, v4                                    ; 103A0804
	V_MUL_F32_e32 v7, v29, v3                                    ; 100E071D
	V_MUL_F32_e32 v30, s5, v5                                    ; 103C0A05
	V_MAD_F32 v7, v30, v17, v7, 0, 0, 0, 0                       ; D2820007 041E231E
	V_MUL_F32_e32 v32, s9, v6                                    ; 10400C09
	V_MAD_F32 v7, v32, v2, v7, 0, 0, 0, 0                        ; D2820007 041E0520
	V_MUL_F32_e32 v8, v7, v7                                     ; 10100F07
	V_MAD_F32 v8, v1, v1, v8, 0, 0, 0, 0                         ; D2820008 04220301
	V_MUL_F32_e32 v33, s8, v4                                    ; 10420808
	V_MUL_F32_e32 v3, v33, v3                                    ; 10060721
	V_MUL_F32_e32 v34, s10, v5                                   ; 10440A0A
	V_MAD_F32 v3, v34, v17, v3, 0, 0, 0, 0                       ; D2820003 040E2322
	V_MUL_F32_e32 v17, s12, v6                                   ; 10220C0C
	V_MAD_F32 v6, v17, v2, v3, 0, 0, 0, 0                        ; D2820006 040E0511
	V_MAD_F32 v2, v6, v6, v8, 0, 0, 0, 0                         ; D2820002 04220D06
	V_RSQ_LEGACY_F32_e32 v8, v2                                  ; 7E105B02
	S_LOAD_DWORDX4 s[8:11], s[6:7], 0                            ; C0840700
	S_WAITCNT lgkmcnt(0)                                         ; BF8C007F
	BUFFER_LOAD_FORMAT_XYZW v[2:5], s[8:11][v0] + 0              ; E00C2000 80020200
	S_WAITCNT vmcnt(0)                                           ; BF8C0770
	V_MUL_F32_e64 v21, v3, v21, 0, 0, 0, 0                       ; D2100015 02022B03
	V_MAD_F32 v10, v2, v10, v21, 0, 0, 0, 0                      ; D282000A 04561502
	V_MAD_F32 v10, v4, v25, v10, 0, 0, 0, 0                      ; D282000A 042A3304
	S_BUFFER_LOAD_DWORD s4, s[0:3], 23                           ; C2020117
	S_WAITCNT lgkmcnt(0)                                         ; BF8C007F
	V_MOV_B32_e32 v21, s4                                        ; 7E2A0204
	V_MAD_F32 v21, v5, v21, v10, 0, 0, 0, 0                      ; D2820015 042A2B05
	S_BUFFER_LOAD_DWORD s8, s[0:3], 33                           ; C2040121
	S_WAITCNT lgkmcnt(0)                                         ; BF8C007F
	V_SUBREV_F32_e32 v36, s8, v21                                ; 0A482A08
	V_MUL_F32_e64 v10, v3, v19, 0, 0, 0, 0                       ; D210000A 02022703
	V_MAD_F32 v9, v2, v9, v10, 0, 0, 0, 0                        ; D2820009 042A1302
	V_MAD_F32 v9, v4, v15, v9, 0, 0, 0, 0                        ; D2820009 04261F04
	S_BUFFER_LOAD_DWORD s4, s[0:3], 19                           ; C2020113
	S_WAITCNT lgkmcnt(0)                                         ; BF8C007F
	V_MOV_B32_e32 v10, s4                                        ; 7E140204
	V_MAD_F32 v26, v5, v10, v9, 0, 0, 0, 0                       ; D282001A 04261505
	S_BUFFER_LOAD_DWORD s9, s[0:3], 32                           ; C2048120
	S_WAITCNT lgkmcnt(0)                                         ; BF8C007F
	V_SUBREV_F32_e32 v9, s9, v26                                 ; 0A123409
	V_MUL_F32_e32 v9, v9, v9                                     ; 10121309
	V_MAD_F32 v9, v36, v36, v9, 0, 0, 0, 0                       ; D2820009 04264924
	V_MUL_F32_e64 v10, v3, v23, 0, 0, 0, 0                       ; D210000A 02022F03
	V_MAD_F32 v10, v2, v12, v10, 0, 0, 0, 0                      ; D282000A 042A1902
	V_MAD_F32 v10, v4, v27, v10, 0, 0, 0, 0                      ; D282000A 042A3704
	S_BUFFER_LOAD_DWORD s4, s[0:3], 27                           ; C202011B
	S_WAITCNT lgkmcnt(0)                                         ; BF8C007F
	V_MOV_B32_e32 v12, s4                                        ; 7E180204
	V_MAD_F32 v31, v5, v12, v10, 0, 0, 0, 0                      ; D282001F 042A1905
	S_BUFFER_LOAD_DWORD s57, s[0:3], 34                          ; C21C8122
	S_WAITCNT lgkmcnt(0)                                         ; BF8C007F
	V_SUBREV_F32_e32 v10, s57, v31                               ; 0A143E39
	V_MAD_F32 v9, v10, v10, v9, 0, 0, 0, 0                       ; D2820009 0426150A
	V_RSQ_LEGACY_F32_e32 v10, v9                                 ; 7E145B09
	V_MUL_F32_e32 v10, v10, v9                                   ; 1014130A
	V_ADD_F32_e64 v9, v9, 0, 0, 0, 0, 1                          ; D2060009 22010109
	V_CMP_GT_F32_e64 s[4:5], 0, v9, 0, 0, 0, 0                   ; D0080004 02021280
	V_CNDMASK_B32_e64 v45, 0.000000e+00, v10, s[4:5], 0, 0, 0, 0 ; D200002D 00121480
	V_MUL_F32_e32 v9, v13, v14                                   ; 10121D0D
	V_MAD_F32 v9, v24, v11, v9, 0, 0, 0, 0                       ; D2820009 04261718
	V_MAD_F32 v9, v28, v18, v9, 0, 0, 0, 0                       ; D2820009 0426251C
	V_MUL_F32_e32 v10, v29, v14                                  ; 10141D1D
	V_MAD_F32 v10, v30, v11, v10, 0, 0, 0, 0                     ; D282000A 042A171E
	V_MAD_F32 v10, v32, v18, v10, 0, 0, 0, 0                     ; D282000A 042A2520
	V_MUL_F32_e32 v12, v10, v10                                  ; 1018150A
	V_MAD_F32 v12, v9, v9, v12, 0, 0, 0, 0                       ; D282000C 04321309
	V_MUL_F32_e32 v14, v33, v14                                  ; 101C1D21
	V_MAD_F32 v11, v34, v11, v14, 0, 0, 0, 0                     ; D282000B 043A1722
	V_MAD_F32 v11, v17, v18, v11, 0, 0, 0, 0                     ; D282000B 042E2511
	V_MAD_F32 v12, v11, v11, v12, 0, 0, 0, 0                     ; D282000C 0432170B
	V_RSQ_LEGACY_F32_e32 v12, v12                                ; 7E185B0C
	V_MUL_F32_e32 v13, v13, v20                                  ; 101A290D
	V_MAD_F32 v13, v24, v22, v13, 0, 0, 0, 0                     ; D282000D 04362D18
	V_MAD_F32 v13, v28, v16, v13, 0, 0, 0, 0                     ; D282000D 0436211C
	V_MUL_F32_e32 v14, v29, v20                                  ; 101C291D
	V_MAD_F32 v14, v30, v22, v14, 0, 0, 0, 0                     ; D282000E 043A2D1E
	V_MAD_F32 v14, v32, v16, v14, 0, 0, 0, 0                     ; D282000E 043A2120
	V_MUL_F32_e32 v15, v14, v14                                  ; 101E1D0E
	V_MAD_F32 v18, v13, v13, v15, 0, 0, 0, 0                     ; D2820012 043E1B0D
	V_MUL_F32_e32 v15, v33, v20                                  ; 101E2921
	V_MAD_F32 v15, v34, v22, v15, 0, 0, 0, 0                     ; D282000F 043E2D22
	V_MAD_F32 v15, v17, v16, v15, 0, 0, 0, 0                     ; D282000F 043E2111
	V_MAD_F32 v16, v15, v15, v18, 0, 0, 0, 0                     ; D2820010 044A1F0F
	V_RSQ_LEGACY_F32_e32 v16, v16                                ; 7E205B10
	S_LOAD_DWORDX4 s[12:15], s[6:7], 32                          ; C0860720
	S_WAITCNT lgkmcnt(0)                                         ; BF8C007F
	BUFFER_LOAD_FORMAT_XYZW v[17:20], s[12:15][v0] + 0           ; E00C2000 80031100
	S_LOAD_DWORDX4 s[12:15], s[6:7], 28                          ; C086071C
	S_WAITCNT vmcnt(0) lgkmcnt(0)                                ; BF8C0070
	BUFFER_LOAD_FORMAT_XYZW v[32:35], s[12:15][v0] + 0           ; E00C2000 80032000
	S_LOAD_DWORDX4 s[12:15], s[6:7], 24                          ; C0860718
	S_WAITCNT vmcnt(0) lgkmcnt(0)                                ; BF8C0070
	BUFFER_LOAD_FORMAT_XYZW v[27:30], s[12:15][v0] + 0           ; E00C2000 80031B00
	S_LOAD_DWORDX4 s[12:15], s[6:7], 20                          ; C0860714
	S_WAITCNT vmcnt(0) lgkmcnt(0)                                ; BF8C0070
	BUFFER_LOAD_FORMAT_XYZW v[41:44], s[12:15][v0] + 0           ; E00C2000 80032900
	S_LOAD_DWORDX4 s[12:15], s[6:7], 16                          ; C0860710
	S_WAITCNT vmcnt(0) lgkmcnt(0)                                ; BF8C0070
	BUFFER_LOAD_FORMAT_XYZW v[37:40], s[12:15][v0] + 0           ; E00C2000 80032500
	S_LOAD_DWORDX4 s[4:7], s[6:7], 12                            ; C082070C
	S_WAITCNT vmcnt(0) lgkmcnt(0)                                ; BF8C0070
	BUFFER_LOAD_FORMAT_XYZW v[22:25], s[4:7][v0] + 0             ; E00C2000 80011600
	S_BUFFER_LOAD_DWORD s7, s[0:3], 87                           ; C2038157
	S_BUFFER_LOAD_DWORD s10, s[0:3], 86                          ; C2050156
	S_BUFFER_LOAD_DWORD s11, s[0:3], 85                          ; C2058155
	S_BUFFER_LOAD_DWORD s12, s[0:3], 84                          ; C2060154
	S_BUFFER_LOAD_DWORD s13, s[0:3], 83                          ; C2068153
	S_BUFFER_LOAD_DWORD s14, s[0:3], 82                          ; C2070152
	S_BUFFER_LOAD_DWORD s15, s[0:3], 81                          ; C2078151
	S_BUFFER_LOAD_DWORD s16, s[0:3], 80                          ; C2080150
	S_BUFFER_LOAD_DWORD s17, s[0:3], 79                          ; C208814F
	S_BUFFER_LOAD_DWORD s18, s[0:3], 78                          ; C209014E
	S_BUFFER_LOAD_DWORD s19, s[0:3], 77                          ; C209814D
	S_BUFFER_LOAD_DWORD s20, s[0:3], 76                          ; C20A014C
	S_BUFFER_LOAD_DWORD s21, s[0:3], 75                          ; C20A814B
	S_BUFFER_LOAD_DWORD s22, s[0:3], 74                          ; C20B014A
	S_BUFFER_LOAD_DWORD s23, s[0:3], 73                          ; C20B8149
	S_BUFFER_LOAD_DWORD s24, s[0:3], 72                          ; C20C0148
	S_BUFFER_LOAD_DWORD s25, s[0:3], 71                          ; C20C8147
	S_BUFFER_LOAD_DWORD s26, s[0:3], 70                          ; C20D0146
	S_BUFFER_LOAD_DWORD s27, s[0:3], 69                          ; C20D8145
	S_BUFFER_LOAD_DWORD s28, s[0:3], 68                          ; C20E0144
	S_BUFFER_LOAD_DWORD s29, s[0:3], 67                          ; C20E8143
	S_BUFFER_LOAD_DWORD s30, s[0:3], 66                          ; C20F0142
	S_BUFFER_LOAD_DWORD s31, s[0:3], 65                          ; C20F8141
	S_BUFFER_LOAD_DWORD s32, s[0:3], 64                          ; C2100140
	S_BUFFER_LOAD_DWORD s33, s[0:3], 63                          ; C210813F
	S_BUFFER_LOAD_DWORD s34, s[0:3], 62                          ; C211013E
	S_BUFFER_LOAD_DWORD s35, s[0:3], 61                          ; C211813D
	S_BUFFER_LOAD_DWORD s36, s[0:3], 60                          ; C212013C
	S_BUFFER_LOAD_DWORD s37, s[0:3], 59                          ; C212813B
	S_BUFFER_LOAD_DWORD s38, s[0:3], 58                          ; C213013A
	S_BUFFER_LOAD_DWORD s39, s[0:3], 57                          ; C2138139
	S_BUFFER_LOAD_DWORD s40, s[0:3], 56                          ; C2140138
	S_BUFFER_LOAD_DWORD s6, s[0:3], 52                           ; C2030134
	S_BUFFER_LOAD_DWORD s5, s[0:3], 29                           ; C202811D
	S_BUFFER_LOAD_DWORD s4, s[0:3], 28                           ; C202011C
	S_BUFFER_LOAD_DWORD s41, s[0:3], 15                          ; C214810F
	S_BUFFER_LOAD_DWORD s42, s[0:3], 14                          ; C215010E
	S_BUFFER_LOAD_DWORD s43, s[0:3], 13                          ; C215810D
	S_BUFFER_LOAD_DWORD s44, s[0:3], 12                          ; C216010C
	S_BUFFER_LOAD_DWORD s45, s[0:3], 11                          ; C216810B
	S_BUFFER_LOAD_DWORD s46, s[0:3], 10                          ; C217010A
	S_BUFFER_LOAD_DWORD s47, s[0:3], 9                           ; C2178109
	S_BUFFER_LOAD_DWORD s48, s[0:3], 8                           ; C2180108
	S_BUFFER_LOAD_DWORD s49, s[0:3], 7                           ; C2188107
	S_BUFFER_LOAD_DWORD s50, s[0:3], 6                           ; C2190106
	S_BUFFER_LOAD_DWORD s51, s[0:3], 5                           ; C2198105
	S_BUFFER_LOAD_DWORD s52, s[0:3], 4                           ; C21A0104
	S_BUFFER_LOAD_DWORD s53, s[0:3], 3                           ; C21A8103
	S_BUFFER_LOAD_DWORD s54, s[0:3], 2                           ; C21B0102
	S_BUFFER_LOAD_DWORD s55, s[0:3], 1                           ; C21B8101
	S_BUFFER_LOAD_DWORD s56, s[0:3], 0                           ; C21C0100
	S_BUFFER_LOAD_DWORD s60, s[0:3], 40                          ; C21E0128
	S_WAITCNT vmcnt(0) lgkmcnt(0)                                ; BF8C0070
	V_CMP_GT_F32_e64 s[58:59], s60, 0.000000e+00, 0, 0, 0, 0     ; D008003A 0201003C
	V_MOV_B32_e32 v65, 0.000000e+00                              ; 7E820280
	S_AND_SAVEEXEC_B64 s[58:59], s[58:59]                        ; BEBA243A
	S_XOR_B64 s[58:59], exec, s[58:59]                           ; 89BA3A7E
	S_CBRANCH_EXECZ ";.BB0_2"                                    ; BF880000
	V_MOV_B32_e32 v0, s60                                        ; 7E00023C
	S_BUFFER_LOAD_DWORD s60, s[0:3], 49                          ; C21E0131
	S_WAITCNT lgkmcnt(0)                                         ; BF8C007F
	V_MOV_B32_e32 v46, s60                                       ; 7E5C023C
	V_MUL_F32_e64 v47, s8, v46, 0, 0, 0, 0                       ; D210002F 02025C08
	S_BUFFER_LOAD_DWORD s8, s[0:3], 48                           ; C2040130
	S_WAITCNT lgkmcnt(0)                                         ; BF8C007F
	V_MOV_B32_e32 v48, s8                                        ; 7E600208
	V_MAD_F32 v47, s9, v48, v47, 0, 0, 0, 0                      ; D282002F 04BE6009
	S_BUFFER_LOAD_DWORD s8, s[0:3], 50                           ; C2040132
	S_WAITCNT lgkmcnt(0)                                         ; BF8C007F
	V_MOV_B32_e32 v49, s8                                        ; 7E620208
	V_MAD_F32 v47, s57, v49, v47, 0, 0, 0, 0                     ; D282002F 04BE6239
	S_BUFFER_LOAD_DWORD s8, s[0:3], 35                           ; C2040123
	S_BUFFER_LOAD_DWORD s9, s[0:3], 51                           ; C2048133
	S_WAITCNT lgkmcnt(0)                                         ; BF8C007F
	V_MOV_B32_e32 v50, s9                                        ; 7E640209
	V_MAD_F32 v47, s8, v50, v47, 0, 0, 0, 0                      ; D282002F 04BE6408
	V_MUL_F32_e64 v46, v21, v46, 0, 0, 0, 0                      ; D210002E 02025D15
	V_MAD_F32 v46, v26, v48, v46, 0, 0, 0, 0                     ; D282002E 04BA611A
	V_MAD_F32 v46, v31, v49, v46, 0, 0, 0, 0                     ; D282002E 04BA631F
	V_ADD_F32_e32 v46, s9, v46                                   ; 065C5C09
	V_SUB_F32_e32 v48, v46, v47                                  ; 08605F2E
	V_CMP_GE_F32_e64 s[8:9], v48, 0.000000e+00, 0, 0, 0, 0       ; D00C0008 02010130
	V_CNDMASK_B32_e64 v49, v46, v47, s[8:9], 0, 0, 0, 0          ; D2000031 00225F2E
	S_BUFFER_LOAD_DWORD s57, s[0:3], 44                          ; C21C812C
	S_WAITCNT lgkmcnt(0)                                         ; BF8C007F
	V_SUBREV_F32_e32 v49, s57, v49                               ; 0A626239
	S_BUFFER_LOAD_DWORD s60, s[0:3], 47                          ; C21E012F
	S_WAITCNT lgkmcnt(0)                                         ; BF8C007F
	V_SUB_F32_e32 v50, s60, v49                                  ; 0864623C
	V_ADD_F32_e64 v48, v48, 0, 1, 0, 0, 0                        ; D2060130 02010130
	V_ADD_F32_e32 v48, 1.000000e-03, v48                         ; 066060FF 3A83126F
	V_RCP_F32_e32 v48, v48                                       ; 7E605530
	V_MUL_F32_e32 v50, v50, v48                                  ; 10646132
	V_ADD_F32_e64 v50, 0, v50, 0, 1, 0, 0                        ; D2060832 02026480
	S_BUFFER_LOAD_DWORD s60, s[0:3], 46                          ; C21E012E
	S_WAITCNT lgkmcnt(0)                                         ; BF8C007F
	V_SUB_F32_e32 v51, s60, v49                                  ; 0866623C
	V_MUL_F32_e32 v48, v51, v48                                  ; 10606133
	V_ADD_F32_e64 v48, 0, v48, 0, 1, 0, 0                        ; D2060830 02026080
	V_SUB_F32_e32 v48, v48, v50                                  ; 08606530
	V_ADD_F32_e64 v48, 0, v48, 0, 1, 0, 0                        ; D2060830 02026080
	V_CNDMASK_B32_e64 v46, v47, v46, s[8:9], 0, 0, 0, 0          ; D200002E 00225D2F
	V_SUBREV_F32_e32 v46, s57, v46                               ; 0A5C5C39
	S_BUFFER_LOAD_DWORD s8, s[0:3], 41                           ; C2040129
	S_WAITCNT lgkmcnt(0)                                         ; BF8C007F
	V_MUL_F32_e32 v46, s8, v46                                   ; 105C5C08
	V_SUB_F32_e32 v46, 1.000000e+00, v46                         ; 085C5CF2
	V_ADD_F32_e64 v46, 0, v46, 0, 1, 0, 0                        ; D206082E 02025C80
	V_MUL_F32_e32 v47, s8, v49                                   ; 105E6208
	V_SUB_F32_e32 v47, 1.000000e+00, v47                         ; 085E5EF2
	V_ADD_F32_e64 v47, 0, v47, 0, 1, 0, 0                        ; D206082F 02025E80
	V_ADD_F32_e32 v46, v47, v46                                  ; 065C5D2F
	S_BUFFER_LOAD_DWORD s8, s[0:3], 45                           ; C204012D
	S_WAITCNT lgkmcnt(0)                                         ; BF8C007F
	V_MUL_F32_e32 v46, s8, v46                                   ; 105C5C08
	V_ADD_F32_e64 v46, 0, v46, 0, 1, 0, 0                        ; D206082E 02025C80
	V_MUL_F32_e32 v46, v48, v46                                  ; 105C5D30
	V_MUL_F32_e64 v0, v45, v0, 0, 0, 0, 0                        ; D2100000 0202012D
	V_MUL_F32_e32 v0, v0, v46                                    ; 10005D00
	V_ADD_F32_e64 v65, 0, v0, 0, 1, 0, 0                         ; D2060841 02020080
	S_OR_B64 exec, exec, s[58:59]                                ; 88FE3A7E
	V_MOV_B32_e32 v54, s7                                        ; 7E6C0207
	V_MOV_B32_e32 v59, s10                                       ; 7E76020A
	V_MOV_B32_e32 v64, s11                                       ; 7E80020B
	V_MOV_B32_e32 v63, s12                                       ; 7E7E020C
	V_MOV_B32_e32 v53, s13                                       ; 7E6A020D
	V_MOV_B32_e32 v57, s14                                       ; 7E72020E
	V_MOV_B32_e32 v62, s15                                       ; 7E7C020F
	V_MOV_B32_e32 v61, s16                                       ; 7E7A0210
	V_MOV_B32_e32 v48, s17                                       ; 7E600211
	V_MOV_B32_e32 v52, s18                                       ; 7E680212
	V_MOV_B32_e32 v60, s19                                       ; 7E780213
	V_MOV_B32_e32 v58, s20                                       ; 7E740214
	V_MOV_B32_e32 v47, s21                                       ; 7E5E0215
	V_MOV_B32_e32 v51, s22                                       ; 7E660216
	V_MOV_B32_e32 v56, s23                                       ; 7E700217
	V_MOV_B32_e32 v55, s24                                       ; 7E6E0218
	V_MOV_B32_e32 v71, s25                                       ; 7E8E0219
	V_MOV_B32_e32 v76, s26                                       ; 7E98021A
	V_MOV_B32_e32 v81, s27                                       ; 7EA2021B
	V_MOV_B32_e32 v80, s28                                       ; 7EA0021C
	V_MOV_B32_e32 v70, s29                                       ; 7E8C021D
	V_MOV_B32_e32 v74, s30                                       ; 7E94021E
	V_MOV_B32_e32 v79, s31                                       ; 7E9E021F
	V_MOV_B32_e32 v78, s32                                       ; 7E9C0220
	V_MOV_B32_e32 v67, s33                                       ; 7E860221
	V_MOV_B32_e32 v69, s34                                       ; 7E8A0222
	V_MOV_B32_e32 v77, s35                                       ; 7E9A0223
	V_MOV_B32_e32 v75, s36                                       ; 7E960224
	V_MOV_B32_e32 v66, s37                                       ; 7E840225
	V_MOV_B32_e32 v68, s38                                       ; 7E880226
	V_MOV_B32_e32 v73, s39                                       ; 7E920227
	V_MOV_B32_e32 v72, s40                                       ; 7E900228
	V_MOV_B32_e32 v82, s41                                       ; 7EA40229
	V_MOV_B32_e32 v84, s42                                       ; 7EA8022A
	V_MOV_B32_e32 v88, s43                                       ; 7EB0022B
	V_MOV_B32_e32 v87, s44                                       ; 7EAE022C
	V_MOV_B32_e32 v0, s45                                        ; 7E00022D
	V_MOV_B32_e32 v46, s46                                       ; 7E5C022E
	V_MOV_B32_e32 v50, s47                                       ; 7E64022F
	V_MOV_B32_e32 v49, s48                                       ; 7E620230
	V_MOV_B32_e32 v86, s49                                       ; 7EAC0231
	V_MOV_B32_e32 v89, s50                                       ; 7EB20232
	V_MOV_B32_e32 v93, s51                                       ; 7EBA0233
	V_MOV_B32_e32 v92, s52                                       ; 7EB80234
	V_MOV_B32_e32 v83, s53                                       ; 7EA60235
	V_MOV_B32_e32 v85, s54                                       ; 7EAA0236
	V_MOV_B32_e32 v91, s55                                       ; 7EB60237
	V_MOV_B32_e32 v90, s56                                       ; 7EB40238
	V_CMP_GT_F32_e64 s[8:9], s6, 0.000000e+00, 0, 0, 0, 0        ; D0080008 02010006
	V_MOV_B32_e32 v94, 0.000000e+00                              ; 7EBC0280
	S_AND_SAVEEXEC_B64 s[8:9], s[8:9]                            ; BE882408
	S_XOR_B64 s[8:9], exec, s[8:9]                               ; 8988087E
	S_CBRANCH_EXECZ ";.BB0_4"                                    ; BF880000
	S_BUFFER_LOAD_DWORD s7, s[0:3], 54                           ; C2038136
	S_BUFFER_LOAD_DWORD s10, s[0:3], 55                          ; C2050137
	S_BUFFER_LOAD_DWORD s0, s[0:3], 53                           ; C2000135
	S_WAITCNT lgkmcnt(0)                                         ; BF8C007F
	V_MOV_B32_e32 v94, s7                                        ; 7EBC0207
	V_SUB_F32_e64 v94, v45, v94, 0, 0, 0, 0                      ; D208005E 0202BD2D
	V_MUL_F32_e32 v94, s6, v94                                   ; 10BCBC06
	V_MUL_F32_e32 v94, -1.442695e+00, v94                        ; 10BCBCFF BFB8AA3B
	V_EXP_F32_e32 v94, v94                                       ; 7EBC4B5E
	V_SUB_F32_e32 v94, 1.000000e+00, v94                         ; 08BCBCF2
	V_ADD_F32_e64 v94, 0, v94, 0, 1, 0, 0                        ; D206085E 0202BC80
	V_MOV_B32_e32 v95, 1.123596e-04                              ; 7EBE02FF 38EBA293
	V_MUL_F32_e32 v45, v45, v95                                  ; 105ABF2D
	V_ADD_F32_e64 v45, 0, v45, 0, 1, 0, 0                        ; D206082D 02025A80
	V_MUL_F32_e32 v45, s10, v45                                  ; 105A5A0A
	V_SUB_F32_e32 v45, 1.000000e+00, v45                         ; 085A5AF2
	V_MUL_F32_e32 v36, v36, v45                                  ; 10485B24
	V_MUL_F32_e32 v36, s0, v36                                   ; 10484800
	V_SUB_F32_e32 v36, 1.000000e+00, v36                         ; 084848F2
	V_ADD_F32_e64 v36, 0, v36, 0, 1, 0, 0                        ; D2060824 02024880
	V_MUL_F32_e32 v36, v36, v36                                  ; 10484924
	V_MUL_F32_e32 v94, v94, v36                                  ; 10BC495E
	S_OR_B64 exec, exec, s[8:9]                                  ; 88FE087E
	V_MUL_F32_e64 v36, v3, v88, 0, 0, 0, 0                       ; D2100024 0202B103
	V_MAD_F32 v36, v2, v87, v36, 0, 0, 0, 0                      ; D2820024 0492AF02
	V_MAD_F32 v36, v4, v84, v36, 0, 0, 0, 0                      ; D2820024 0492A904
	V_MAD_F32 v36, v5, v82, v36, 0, 0, 0, 0                      ; D2820024 0492A505
	V_MUL_F32_e64 v45, v3, v93, 0, 0, 0, 0                       ; D210002D 0202BB03
	V_MAD_F32 v45, v2, v92, v45, 0, 0, 0, 0                      ; D282002D 04B6B902
	V_MAD_F32 v45, v4, v89, v45, 0, 0, 0, 0                      ; D282002D 04B6B304
	V_MAD_F32 v45, v5, v86, v45, 0, 0, 0, 0                      ; D282002D 04B6AD05
	V_MUL_F32_e32 v82, 5.000000e-01, v45                         ; 10A45AF0
	V_MAD_F32 v82, v36, 5.000000e-01, v82, 0, 0, 0, 0            ; D2820052 0549E124
	V_MUL_F32_e64 v84, v3, v91, 0, 0, 0, 0                       ; D2100054 0202B703
	V_MAD_F32 v84, v2, v90, v84, 0, 0, 0, 0                      ; D2820054 0552B502
	V_MAD_F32 v84, v4, v85, v84, 0, 0, 0, 0                      ; D2820054 0552AB04
	V_MAD_F32 v83, v5, v83, v84, 0, 0, 0, 0                      ; D2820053 0552A705
	V_MUL_F32_e32 v84, 5.000000e-01, v83                         ; 10A8A6F0
	V_MAD_F32 v84, v36, 5.000000e-01, v84, 0, 0, 0, 0            ; D2820054 0551E124
	EXP 15, 32, 0, 0, 0, v84, v82, v65, v94                      ; F800020F 5E415254
	EXP 15, 33, 0, 0, 0, v26, v21, v31, v36                      ; F800021F 241F151A
	S_WAITCNT expcnt(0)                                          ; BF8C070F
	V_MUL_F32_e64 v21, v42, v81, 0, 0, 0, 0                      ; D2100015 0202A32A
	V_MAD_F32 v21, v41, v80, v21, 0, 0, 0, 0                     ; D2820015 0456A129
	V_MAD_F32 v21, v43, v76, v21, 0, 0, 0, 0                     ; D2820015 0456992B
	V_MAD_F32 v21, v44, v71, v21, 0, 0, 0, 0                     ; D2820015 04568F2C
	V_MUL_F32_e64 v26, v42, v79, 0, 0, 0, 0                      ; D210001A 02029F2A
	V_MAD_F32 v26, v41, v78, v26, 0, 0, 0, 0                     ; D282001A 046A9D29
	V_MAD_F32 v26, v43, v74, v26, 0, 0, 0, 0                     ; D282001A 046A952B
	V_MAD_F32 v26, v44, v70, v26, 0, 0, 0, 0                     ; D282001A 046A8D2C
	V_MUL_F32_e64 v31, v38, v77, 0, 0, 0, 0                      ; D210001F 02029B26
	V_MAD_F32 v31, v37, v75, v31, 0, 0, 0, 0                     ; D282001F 047E9725
	V_MAD_F32 v31, v39, v69, v31, 0, 0, 0, 0                     ; D282001F 047E8B27
	V_MAD_F32 v31, v40, v67, v31, 0, 0, 0, 0                     ; D282001F 047E8728
	V_MUL_F32_e64 v41, v38, v73, 0, 0, 0, 0                      ; D2100029 02029326
	V_MAD_F32 v41, v37, v72, v41, 0, 0, 0, 0                     ; D2820029 04A69125
	V_MAD_F32 v41, v39, v68, v41, 0, 0, 0, 0                     ; D2820029 04A68927
	V_MAD_F32 v37, v40, v66, v41, 0, 0, 0, 0                     ; D2820025 04A68528
	EXP 15, 34, 0, 0, 0, v37, v31, v26, v21                      ; F800022F 151A1F25
	S_WAITCNT expcnt(0)                                          ; BF8C070F
	V_MUL_F32_e64 v21, v33, v64, 0, 0, 0, 0                      ; D2100015 02028121
	V_MAD_F32 v21, v32, v63, v21, 0, 0, 0, 0                     ; D2820015 04567F20
	V_MAD_F32 v21, v34, v59, v21, 0, 0, 0, 0                     ; D2820015 04567722
	V_MAD_F32 v21, v35, v54, v21, 0, 0, 0, 0                     ; D2820015 04566D23
	V_MUL_F32_e64 v26, v33, v62, 0, 0, 0, 0                      ; D210001A 02027D21
	V_MAD_F32 v26, v32, v61, v26, 0, 0, 0, 0                     ; D282001A 046A7B20
	V_MAD_F32 v26, v34, v57, v26, 0, 0, 0, 0                     ; D282001A 046A7322
	V_MAD_F32 v26, v35, v53, v26, 0, 0, 0, 0                     ; D282001A 046A6B23
	V_MUL_F32_e64 v31, v28, v60, 0, 0, 0, 0                      ; D210001F 0202791C
	V_MAD_F32 v31, v27, v58, v31, 0, 0, 0, 0                     ; D282001F 047E751B
	V_MAD_F32 v31, v29, v52, v31, 0, 0, 0, 0                     ; D282001F 047E691D
	V_MAD_F32 v31, v30, v48, v31, 0, 0, 0, 0                     ; D282001F 047E611E
	V_MUL_F32_e64 v32, v28, v56, 0, 0, 0, 0                      ; D2100020 0202711C
	V_MAD_F32 v32, v27, v55, v32, 0, 0, 0, 0                     ; D2820020 04826F1B
	V_MAD_F32 v32, v29, v51, v32, 0, 0, 0, 0                     ; D2820020 0482671D
	V_MAD_F32 v27, v30, v47, v32, 0, 0, 0, 0                     ; D282001B 04825F1E
	EXP 15, 35, 0, 0, 0, v27, v31, v26, v21                      ; F800023F 151A1F1B
	S_WAITCNT expcnt(0)                                          ; BF8C070F
	V_MOV_B32_e32 v21, s5                                        ; 7E2A0205
	V_MOV_B32_e32 v26, s4                                        ; 7E340204
	V_MAD_F32 v27, v23, v26, v21, 0, 0, 0, 0                     ; D282001B 04563517
	V_MAD_F32 v21, v22, v26, v21, 0, 0, 0, 0                     ; D2820015 04563516
	EXP 15, 36, 0, 0, 0, v17, v18, v21, v27                      ; F800024F 1B151211
	V_MUL_F32_e64 v7, v7, v8, 0, 0, 0, 0                         ; D2100007 02021107
	V_MUL_F32_e64 v15, v15, v16, 0, 0, 0, 0                      ; D210000F 0202210F
	V_MUL_F32_e64 v13, v13, v16, 0, 0, 0, 0                      ; D210000D 0202210D
	V_MUL_F32_e64 v14, v14, v16, 0, 0, 0, 0                      ; D210000E 0202210E
	EXP 15, 37, 0, 0, 0, v14, v13, v15, v7                       ; F800025F 070F0D0E
	S_WAITCNT expcnt(0)                                          ; BF8C070F
	V_MUL_F32_e64 v7, v9, v12, 0, 0, 0, 0                        ; D2100007 02021909
	V_MUL_F32_e64 v9, v10, v12, 0, 0, 0, 0                       ; D2100009 0202190A
	V_MUL_F32_e64 v6, v6, v8, 0, 0, 0, 0                         ; D2100006 02021106
	V_MUL_F32_e64 v1, v1, v8, 0, 0, 0, 0                         ; D2100001 02021101
	EXP 15, 38, 0, 0, 0, v1, v6, v9, v7                          ; F800026F 07090601
	S_WAITCNT expcnt(0)                                          ; BF8C070F
	V_MUL_F32_e64 v1, v11, v12, 0, 0, 0, 0                       ; D2100001 0202190B
	V_MOV_B32_e32 v6, 0.000000e+00                               ; 7E0C0280
	EXP 15, 39, 0, 0, 0, v1, v7, v1, v6                          ; F800027F 06010701
	S_WAITCNT expcnt(0)                                          ; BF8C070F
	V_MUL_F32_e64 v1, v3, v50, 0, 0, 0, 0                        ; D2100001 02026503
	V_MAD_F32 v1, v2, v49, v1, 0, 0, 0, 0                        ; D2820001 04066302
	V_MAD_F32 v1, v4, v46, v1, 0, 0, 0, 0                        ; D2820001 04065D04
	V_MAD_F32 v0, v5, v0, v1, 0, 0, 0, 0                         ; D2820000 04060105
	EXP 15, 12, 0, 1, 0, v83, v45, v0, v36                       ; F80008CF 24002D53
	S_ENDPGM                                                     ; BF810000

FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], POSITION, LINEAR
DCL IN[1], FACE, CONSTANT
DCL IN[2], GENERIC[19], PERSPECTIVE
DCL IN[3], GENERIC[20], PERSPECTIVE
DCL IN[4], GENERIC[21], PERSPECTIVE
DCL IN[5], GENERIC[22], PERSPECTIVE
DCL IN[6], GENERIC[23], PERSPECTIVE
DCL IN[7], GENERIC[24], PERSPECTIVE
DCL IN[8], GENERIC[25], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL SAMP[1]
DCL SAMP[2]
DCL SAMP[3]
DCL SAMP[4]
DCL SAMP[5]
DCL SAMP[6]
DCL SAMP[7]
DCL SAMP[8]
DCL CONST[54]
DCL CONST[0..44]
DCL TEMP[0..1]
DCL TEMP[2..22], LOCAL
IMM[0] FLT32 {    0.0000,     1.0000,    -1.0000,     4.5948}
IMM[1] FLT32 {   32.0000,   -16.0000,     0.5000,     4.0000}
IMM[2] FLT32 {    2.0000,    -0.0010,     0.0000,     0.0000}
IMM[3] FLT32 {    0.0000,     0.0100,     0.2500,     3.0000}
IMM[4] FLT32 {    0.0000, 65504.0000,     0.0000,     0.0000}
  0: MOV TEMP[0], IN[0]
  1: MAD TEMP[0].y, IN[0], CONST[54].xxxx, CONST[54].yyyy
  2: MOV_SAT TEMP[1], IN[1]
  3: MOV TEMP[2].x, IN[7].wwww
  4: MOV TEMP[2].yz, IN[8].yxyy
  5: UIF TEMP[1].xxxx :3
  6:   MOV TEMP[3].x, IMM[0].zzzz
  7: ELSE :3
  8:   MOV TEMP[3].x, IMM[0].yyyy
  9: ENDIF
 10: ADD TEMP[4].xyz, CONST[11].xyzz, -IN[2].xyzz
 11: DP3 TEMP[5].x, TEMP[4].xyzz, TEMP[4].xyzz
 12: RSQ TEMP[5].x, TEMP[5].xxxx
 13: MUL TEMP[4].xyz, TEMP[4].xyzz, TEMP[5].xxxx
 14: MUL TEMP[5].x, TEMP[3].xxxx, CONST[14].wwww
 15: MUL TEMP[6].xy, TEMP[0].xyyy, CONST[12].xyyy
 16: MOV TEMP[7].xy, IN[4].zwww
 17: TEX TEMP[7], TEMP[7], SAMP[2], 2D
 18: MOV TEMP[8].w, TEMP[7].wwww
 19: MUL TEMP[8].xyz, TEMP[7].xyzz, IMM[0].wwww
 20: LRP TEMP[8].xyz, CONST[1].wwww, TEMP[8].xyzz, IMM[0].yyyy
 21: MOV TEMP[9].xy, IN[5].xyyy
 22: TEX TEMP[9], TEMP[9], SAMP[4], 2D
 23: MOV TEMP[10].xyz, TEMP[9]
 24: MOV TEMP[11].xy, IN[3].xyyy
 25: TEX TEMP[11], TEMP[11], SAMP[3], 2D
 26: MUL TEMP[12], TEMP[11], CONST[0]
 27: MUL TEMP[12], TEMP[12], IN[6]
 28: MOV TEMP[13].w, TEMP[12].wwww
 29: ADD TEMP[14].x, IMM[0].yyyy, -TEMP[11].wwww
 30: MUL TEMP[14].x, TEMP[14].xxxx, CONST[12].zzzz
 31: LRP TEMP[13].xyz, TEMP[14].xxxx, TEMP[11].xyzz, TEMP[12].xyzz
 32: MOV TEMP[11].xy, IN[3].zwww
 33: TEX TEMP[11].xyw, TEMP[11], SAMP[5], 2D
 34: MUL TEMP[12].xy, CONST[14].xyyy, TEMP[11].wxxx
 35: ADD TEMP[12].xy, IMM[0].yyyy, -TEMP[12].xyyy
 36: MUL TEMP[13], TEMP[13], TEMP[8]
 37: DP3 TEMP[8].x, IN[7].xyzz, IN[7].xyzz
 38: RSQ TEMP[8].x, TEMP[8].xxxx
 39: MUL TEMP[8].xyz, IN[7].xyzz, TEMP[8].xxxx
 40: FSLT TEMP[5].x, IMM[0].xxxx, TEMP[5].xxxx
 41: UIF TEMP[5].xxxx :3
 42:   MOV TEMP[5].xyz, -TEMP[8].xyzx
 43: ELSE :3
 44:   MOV TEMP[5].xyz, TEMP[8].xyzx
 45: ENDIF
 46: MOV TEMP[8].w, TEMP[13].wwww
 47: MOV TEMP[6].xy, TEMP[6].xyyy
 48: TEX TEMP[6], TEMP[6], SAMP[8], 2D
 49: MAD TEMP[3], TEMP[6], CONST[10].xxxz, CONST[10].yyyw
 50: MOV TEMP[6].xy, IN[4].xyyy
 51: TEX TEMP[6], TEMP[6], SAMP[6], 2D
 52: MAD TEMP[14].x, TEMP[6].wwww, IMM[1].xxxx, IMM[1].yyyy
 53: EX2 TEMP[14].x, TEMP[14].xxxx
 54: MUL TEMP[6].xyz, TEMP[6].xyzz, TEMP[14].xxxx
 55: MAD TEMP[2].xyz, CONST[3].xyzz, TEMP[6].xyzz, TEMP[2].xyzz
 56: MUL TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].wwww
 57: MAD TEMP[6].x, TEMP[3].wwww, IMM[1].zzzz, IMM[1].zzzz
 58: DP3_SAT TEMP[14].x, TEMP[5].xyzz, TEMP[4].xyzz
 59: ADD TEMP[14].x, IMM[0].yyyy, -TEMP[14].xxxx
 60: POW TEMP[14].x, TEMP[14].xxxx, IMM[1].wwww
 61: MUL TEMP[14].x, TEMP[14].xxxx, CONST[3].wwww
 62: MUL TEMP[15].xy, TEMP[12].xyyy, TEMP[14].xxxx
 63: ADD TEMP[15].y, TEMP[12].xyyy, -TEMP[15].xyyy
 64: DP3 TEMP[16].x, TEMP[5].xyzz, TEMP[4].xyzz
 65: MUL TEMP[16].xyz, TEMP[16].xxxx, TEMP[5].xyzz
 66: MUL TEMP[16].xyz, IMM[2].xxxx, TEMP[16].xyzz
 67: ADD TEMP[16].xyz, TEMP[4].xyzz, -TEMP[16].xyzz
 68: LRP TEMP[17].xyz, TEMP[15].yyyy, -TEMP[5].xyzz, TEMP[16].xyzz
 69: ABS TEMP[18].xyz, TEMP[17].xyzz
 70: MAX TEMP[19].x, TEMP[18].yyyy, TEMP[18].zzzz
 71: MAX TEMP[19].x, TEMP[18].xxxx, TEMP[19].xxxx
 72: ADD TEMP[20].x, TEMP[19].xxxx, IMM[2].yyyy
 73: FSGE TEMP[21].x, TEMP[20].xxxx, TEMP[18].xxxx
 74: AND TEMP[21].x, TEMP[21].xxxx, IMM[0].yyyy
 75: FSGE TEMP[22].x, TEMP[20].xxxx, TEMP[18].yyyy
 76: AND TEMP[22].x, TEMP[22].xxxx, IMM[0].yyyy
 77: MOV TEMP[21].y, TEMP[22].xxxx
 78: FSGE TEMP[18].x, TEMP[20].xxxx, TEMP[18].zzzz
 79: AND TEMP[18].x, TEMP[18].xxxx, IMM[0].yyyy
 80: MOV TEMP[21].z, TEMP[18].xxxx
 81: RCP TEMP[18].x, TEMP[19].xxxx
 82: MUL TEMP[18].xyz, IMM[0].zzyy, TEMP[18].xxxx
 83: MUL TEMP[16].xyz, TEMP[17].xyzz, TEMP[18].xyzz
 84: ADD TEMP[17].x, CONST[14].zzzz, IMM[0].zzzz
 85: MUL TEMP[17].x, TEMP[15].yyyy, TEMP[17].xxxx
 86: MUL TEMP[18].xyz, TEMP[16].xyzz, TEMP[21].xyzz
 87: FLR TEMP[19].x, TEMP[17].xxxx
 88: ADD TEMP[19].x, CONST[14].zzzz, -TEMP[19].xxxx
 89: EX2 TEMP[19].x, TEMP[19].xxxx
 90: RCP TEMP[19].x, TEMP[19].xxxx
 91: MUL TEMP[18].xyz, TEMP[18].xyzz, TEMP[19].xxxx
 92: ADD TEMP[16].xyz, TEMP[16].xyzz, -TEMP[18].xyzz
 93: MOV TEMP[16].xyz, TEMP[16].xyzz
 94: MOV TEMP[16].w, TEMP[17].xxxx
 95: TXL TEMP[16], TEMP[16], SAMP[7], CUBE
 96: MAD TEMP[17].x, TEMP[16].wwww, IMM[1].xxxx, IMM[1].yyyy
 97: EX2 TEMP[17].x, TEMP[17].xxxx
 98: MUL TEMP[16].xyz, TEMP[16].xyzz, TEMP[17].xxxx
 99: MUL TEMP[17].xyz, CONST[1].xyzz, TEMP[11].yyyy
100: MUL TEMP[17].xyz, TEMP[17].xyzz, TEMP[11].yyyy
101: MAD_SAT TEMP[15].x, TEMP[15].yyyy, IMM[2].xxxx, IMM[0].zzzz
102: MUL TEMP[3].xyz, TEMP[3].xyzz, TEMP[6].xxxx
103: MUL TEMP[16].xyz, TEMP[16].xyzz, CONST[2].xyzz
104: MUL TEMP[16].xyz, TEMP[17].xyzz, TEMP[16].xyzz
105: LRP TEMP[15].xyz, TEMP[15].xxxx, TEMP[17].xyzz, TEMP[16].xyzz
106: LRP TEMP[14].xyz, TEMP[14].xxxx, IMM[0].yyyy, TEMP[17].xyzz
107: LRP TEMP[14].xyz, TEMP[14].xyzz, TEMP[15].xyzz, TEMP[13].xyzz
108: MUL TEMP[2].xyz, TEMP[2].xyzz, TEMP[14].xyzz
109: MAD TEMP[2].xyz, TEMP[3].xyzz, TEMP[13].xyzz, TEMP[2].xyzz
110: ADD TEMP[3].xyz, IN[2].xyzz, -CONST[30].xyzz
111: DP3 TEMP[14].x, TEMP[3].xyzz, TEMP[3].xyzz
112: RSQ TEMP[14].x, TEMP[14].xxxx
113: MUL TEMP[15].x, CONST[31].wwww, TEMP[14].xxxx
114: RCP TEMP[15].x, TEMP[15].xxxx
115: MOV_SAT TEMP[15].x, TEMP[15].xxxx
116: ADD TEMP[15].x, IMM[0].yyyy, -TEMP[15].xxxx
117: MUL TEMP[15].x, TEMP[15].xxxx, TEMP[14].xxxx
118: MUL TEMP[3].xyz, -TEMP[3].xyzz, TEMP[14].xxxx
119: DP3 TEMP[14].x, TEMP[3].xyzz, -CONST[31].xyzz
120: MUL TEMP[14].x, TEMP[14].xxxx, CONST[29].wwww
121: ADD_SAT TEMP[14].x, CONST[30].wwww, -TEMP[14].xxxx
122: MUL TEMP[15].x, TEMP[15].xxxx, TEMP[14].xxxx
123: DP3_SAT TEMP[14].x, TEMP[5].xyzz, TEMP[3].xyzz
124: ADD TEMP[3].xyz, TEMP[4].xyzz, TEMP[3].xyzz
125: DP3 TEMP[16].x, TEMP[3].xyzz, TEMP[3].xyzz
126: RSQ TEMP[16].x, TEMP[16].xxxx
127: MUL TEMP[3].xyz, TEMP[3].xyzz, TEMP[16].xxxx
128: DP3 TEMP[16].x, TEMP[3].xyzz, TEMP[5].xyzz
129: DDX TEMP[17].x, TEMP[16].xxxx
130: ABS TEMP[17].x, TEMP[17].xxxx
131: MUL TEMP[19], CONST[54].xxxx, TEMP[16].xxxx
132: DDY TEMP[18].x, TEMP[19]
133: ABS TEMP[18].x, TEMP[18].xxxx
134: ADD TEMP[17].x, TEMP[17].xxxx, TEMP[18].xxxx
135: MAD TEMP[17].x, TEMP[17].xxxx, IMM[1].zzzz, IMM[2].zzzz
136: MAD_SAT TEMP[16].xy, TEMP[17].xxxx, IMM[0].zyyy, TEMP[16].xxxx
137: DP3_SAT TEMP[3].x, TEMP[3].xyzz, TEMP[4].xyzz
138: ADD TEMP[3].x, IMM[0].yyyy, -TEMP[3].xxxx
139: POW TEMP[3].x, TEMP[3].xxxx, IMM[1].wwww
140: MUL TEMP[3].x, TEMP[3].xxxx, CONST[3].wwww
141: MUL TEMP[3].xy, TEMP[12].xyyy, TEMP[3].xxxx
142: ADD TEMP[3].xy, TEMP[12].xyyy, -TEMP[3].xyyy
143: POW TEMP[12].x, TEMP[3].xxxx, IMM[1].wwww
144: POW TEMP[12].y, TEMP[3].yyyy, IMM[1].wwww
145: ADD_SAT TEMP[3].xy, TEMP[12].xyyy, IMM[2].wwww
146: MUL TEMP[12], TEMP[16].xyxy, TEMP[3].xxyy
147: ADD TEMP[17], TEMP[3].xxyy, IMM[0].zzzz
148: MAD TEMP[17], TEMP[16].xyxy, TEMP[17], IMM[0].yyyy
149: RCP TEMP[18].x, TEMP[17].xxxx
150: RCP TEMP[18].y, TEMP[17].yyyy
151: RCP TEMP[18].z, TEMP[17].zzzz
152: RCP TEMP[18].w, TEMP[17].wwww
153: MUL_SAT TEMP[12], TEMP[12], TEMP[18]
154: ADD TEMP[12].xy, TEMP[12].ywww, -TEMP[12].xzzz
155: ADD TEMP[16].x, TEMP[16].yyyy, -TEMP[16].xxxx
156: ADD TEMP[16].x, TEMP[16].xxxx, IMM[3].xxxx
157: DP3_SAT TEMP[17].x, TEMP[5].xyzz, TEMP[4].xyzz
158: MUL TEMP[17].x, TEMP[17].xxxx, TEMP[14].xxxx
159: MAX TEMP[17].x, TEMP[17].xxxx, IMM[3].yyyy
160: RSQ TEMP[18].x, TEMP[17].xxxx
161: MUL TEMP[18].x, TEMP[18].xxxx, TEMP[17].xxxx
162: CMP TEMP[18].x, -TEMP[17].xxxx, TEMP[18].xxxx, IMM[0].xxxx
163: LRP TEMP[3].xy, TEMP[3].xyyy, IMM[0].yyyy, TEMP[18].xxxx
164: MUL TEMP[3].xy, TEMP[16].xxxx, TEMP[3].xyyy
165: RCP TEMP[16].x, TEMP[3].xxxx
166: RCP TEMP[16].y, TEMP[3].yyyy
167: MUL TEMP[3].y, TEMP[12].xyyy, TEMP[16].xyyy
168: MUL TEMP[12].xyz, CONST[1].xyzz, TEMP[11].yyyy
169: MUL TEMP[11].xyz, TEMP[12].xyzz, TEMP[11].yyyy
170: LRP TEMP[3].xyz, TEMP[11].xyzz, TEMP[3].yyyy, TEMP[13].xyzz
171: MUL TEMP[3].xyz, TEMP[3].xyzz, TEMP[14].xxxx
172: MUL TEMP[3].xyz, TEMP[3].xyzz, CONST[29].xyzz
173: MUL TEMP[3].xyz, TEMP[3].xyzz, TEMP[15].xxxx
174: DP4 TEMP[11].x, IN[2], CONST[35]
175: DP4 TEMP[12].x, IN[2], CONST[36]
176: MOV TEMP[11].y, TEMP[12].xxxx
177: DP4 TEMP[12].x, IN[2], CONST[37]
178: DP4 TEMP[13].x, IN[2], CONST[38]
179: RCP TEMP[13].x, TEMP[13].xxxx
180: MUL TEMP[11].xy, TEMP[11].xyyy, TEMP[13].xxxx
181: MAD TEMP[11].xy, TEMP[11].xyyy, IMM[1].zzzz, IMM[1].zzzz
182: MAD TEMP[13].xy, TEMP[11].xyyy, CONST[34].xyyy, CONST[34].zwww
183: MOV TEMP[13].xy, TEMP[13].xyyy
184: TEX TEMP[13].xyz, TEMP[13], SAMP[1], 2D
185: MOV TEMP[11].xy, TEMP[11].xyyy
186: MOV TEMP[11].w, IMM[0].xxxx
187: TXL TEMP[11].xy, TEMP[11], SAMP[0], 2D
188: ADD TEMP[14].x, IMM[0].yyyy, -TEMP[11].yyyy
189: MUL TEMP[14].x, TEMP[14].xxxx, IMM[3].zzzz
190: ADD TEMP[14].x, TEMP[11].xxxx, -TEMP[14].xxxx
191: ADD TEMP[12].x, TEMP[11].xxxx, -TEMP[12].xxxx
192: MUL TEMP[11].x, TEMP[11].xxxx, TEMP[11].xxxx
193: ADD TEMP[11].x, TEMP[14].xxxx, -TEMP[11].xxxx
194: MAX TEMP[11].x, TEMP[11].xxxx, CONST[32].xxxx
195: MAD TEMP[14].x, TEMP[12].xxxx, TEMP[12].xxxx, TEMP[11].xxxx
196: RCP TEMP[14].x, TEMP[14].xxxx
197: MUL TEMP[11].x, TEMP[11].xxxx, TEMP[14].xxxx
198: POW TEMP[11].x, TEMP[11].xxxx, CONST[32].yyyy
199: MAD_SAT TEMP[11].x, TEMP[11].xxxx, CONST[33].zzzz, CONST[33].wwww
200: MUL TEMP[14].x, TEMP[11].xxxx, TEMP[11].xxxx
201: MUL TEMP[11].x, IMM[2].xxxx, TEMP[11].xxxx
202: ADD TEMP[11].x, IMM[3].wwww, -TEMP[11].xxxx
203: MUL TEMP[11].x, TEMP[14].xxxx, TEMP[11].xxxx
204: FSGE TEMP[12].x, TEMP[12].xxxx, IMM[0].xxxx
205: UIF TEMP[12].xxxx :3
206:   MOV TEMP[12].x, IMM[0].yyyy
207: ELSE :3
208:   MOV TEMP[12].x, TEMP[11].xxxx
209: ENDIF
210: MUL TEMP[11].xyz, TEMP[13].xyzz, TEMP[12].xxxx
211: MUL TEMP[3].xyz, TEMP[3].xyzz, TEMP[11].xyzz
212: MAD TEMP[8].xyz, TEMP[3].xyzz, TEMP[6].xxxx, TEMP[2].xyzz
213: LRP TEMP[2].x, TEMP[7].wwww, TEMP[9].wwww, IMM[0].yyyy
214: MOV TEMP[10].w, TEMP[2].xxxx
215: LRP TEMP[2], CONST[9].xxxy, TEMP[10], IMM[0].yyyy
216: MUL TEMP[2].xyz, TEMP[2].xyzz, TEMP[2].wwww
217: MUL TEMP[8].xyz, TEMP[8].xyzz, TEMP[2].xyzz
218: DP3 TEMP[2].x, TEMP[5].xyzz, TEMP[4].xyzz
219: ABS TEMP[2].x, TEMP[2].xxxx
220: MUL TEMP[2].x, TEMP[2].xxxx, TEMP[2].xxxx
221: MAD_SAT TEMP[2].x, TEMP[2].xxxx, CONST[13].xxxx, CONST[13].yyyy
222: ADD TEMP[2].x, IMM[0].yyyy, -TEMP[2].xxxx
223: MUL TEMP[2], CONST[4].zzzw, TEMP[2].xxxx
224: LRP TEMP[2], TEMP[2], CONST[4].xxxy, TEMP[8]
225: MAX TEMP[3].xyz, TEMP[2].xyzz, IMM[4].xxxx
226: MIN TEMP[8].xyz, TEMP[3].xyzz, IMM[4].yyyy
227: MAD_SAT TEMP[2].x, TEMP[2].wwww, CONST[13].zzzz, CONST[13].wwww
228: MOV TEMP[8].w, TEMP[2].xxxx
229: MOV OUT[0], TEMP[8]
230: END
; ModuleID = 'tgsi'

@ddxy_lds = external addrspace(3) global [64 x i32]

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %21 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
  %22 = load <16 x i8> addrspace(2)* %21, !tbaa !0
  %23 = call float @llvm.SI.load.const(<16 x i8> %22, i32 0)
  %24 = call float @llvm.SI.load.const(<16 x i8> %22, i32 4)
  %25 = call float @llvm.SI.load.const(<16 x i8> %22, i32 8)
  %26 = call float @llvm.SI.load.const(<16 x i8> %22, i32 12)
  %27 = call float @llvm.SI.load.const(<16 x i8> %22, i32 16)
  %28 = call float @llvm.SI.load.const(<16 x i8> %22, i32 20)
  %29 = call float @llvm.SI.load.const(<16 x i8> %22, i32 24)
  %30 = call float @llvm.SI.load.const(<16 x i8> %22, i32 28)
  %31 = call float @llvm.SI.load.const(<16 x i8> %22, i32 32)
  %32 = call float @llvm.SI.load.const(<16 x i8> %22, i32 36)
  %33 = call float @llvm.SI.load.const(<16 x i8> %22, i32 40)
  %34 = call float @llvm.SI.load.const(<16 x i8> %22, i32 48)
  %35 = call float @llvm.SI.load.const(<16 x i8> %22, i32 52)
  %36 = call float @llvm.SI.load.const(<16 x i8> %22, i32 56)
  %37 = call float @llvm.SI.load.const(<16 x i8> %22, i32 60)
  %38 = call float @llvm.SI.load.const(<16 x i8> %22, i32 64)
  %39 = call float @llvm.SI.load.const(<16 x i8> %22, i32 68)
  %40 = call float @llvm.SI.load.const(<16 x i8> %22, i32 72)
  %41 = call float @llvm.SI.load.const(<16 x i8> %22, i32 76)
  %42 = call float @llvm.SI.load.const(<16 x i8> %22, i32 144)
  %43 = call float @llvm.SI.load.const(<16 x i8> %22, i32 148)
  %44 = call float @llvm.SI.load.const(<16 x i8> %22, i32 160)
  %45 = call float @llvm.SI.load.const(<16 x i8> %22, i32 164)
  %46 = call float @llvm.SI.load.const(<16 x i8> %22, i32 168)
  %47 = call float @llvm.SI.load.const(<16 x i8> %22, i32 172)
  %48 = call float @llvm.SI.load.const(<16 x i8> %22, i32 176)
  %49 = call float @llvm.SI.load.const(<16 x i8> %22, i32 180)
  %50 = call float @llvm.SI.load.const(<16 x i8> %22, i32 184)
  %51 = call float @llvm.SI.load.const(<16 x i8> %22, i32 192)
  %52 = call float @llvm.SI.load.const(<16 x i8> %22, i32 196)
  %53 = call float @llvm.SI.load.const(<16 x i8> %22, i32 200)
  %54 = call float @llvm.SI.load.const(<16 x i8> %22, i32 208)
  %55 = call float @llvm.SI.load.const(<16 x i8> %22, i32 212)
  %56 = call float @llvm.SI.load.const(<16 x i8> %22, i32 216)
  %57 = call float @llvm.SI.load.const(<16 x i8> %22, i32 220)
  %58 = call float @llvm.SI.load.const(<16 x i8> %22, i32 224)
  %59 = call float @llvm.SI.load.const(<16 x i8> %22, i32 228)
  %60 = call float @llvm.SI.load.const(<16 x i8> %22, i32 232)
  %61 = call float @llvm.SI.load.const(<16 x i8> %22, i32 236)
  %62 = call float @llvm.SI.load.const(<16 x i8> %22, i32 464)
  %63 = call float @llvm.SI.load.const(<16 x i8> %22, i32 468)
  %64 = call float @llvm.SI.load.const(<16 x i8> %22, i32 472)
  %65 = call float @llvm.SI.load.const(<16 x i8> %22, i32 476)
  %66 = call float @llvm.SI.load.const(<16 x i8> %22, i32 480)
  %67 = call float @llvm.SI.load.const(<16 x i8> %22, i32 484)
  %68 = call float @llvm.SI.load.const(<16 x i8> %22, i32 488)
  %69 = call float @llvm.SI.load.const(<16 x i8> %22, i32 492)
  %70 = call float @llvm.SI.load.const(<16 x i8> %22, i32 496)
  %71 = call float @llvm.SI.load.const(<16 x i8> %22, i32 500)
  %72 = call float @llvm.SI.load.const(<16 x i8> %22, i32 504)
  %73 = call float @llvm.SI.load.const(<16 x i8> %22, i32 508)
  %74 = call float @llvm.SI.load.const(<16 x i8> %22, i32 512)
  %75 = call float @llvm.SI.load.const(<16 x i8> %22, i32 516)
  %76 = call float @llvm.SI.load.const(<16 x i8> %22, i32 536)
  %77 = call float @llvm.SI.load.const(<16 x i8> %22, i32 540)
  %78 = call float @llvm.SI.load.const(<16 x i8> %22, i32 544)
  %79 = call float @llvm.SI.load.const(<16 x i8> %22, i32 548)
  %80 = call float @llvm.SI.load.const(<16 x i8> %22, i32 552)
  %81 = call float @llvm.SI.load.const(<16 x i8> %22, i32 556)
  %82 = call float @llvm.SI.load.const(<16 x i8> %22, i32 560)
  %83 = call float @llvm.SI.load.const(<16 x i8> %22, i32 564)
  %84 = call float @llvm.SI.load.const(<16 x i8> %22, i32 568)
  %85 = call float @llvm.SI.load.const(<16 x i8> %22, i32 572)
  %86 = call float @llvm.SI.load.const(<16 x i8> %22, i32 576)
  %87 = call float @llvm.SI.load.const(<16 x i8> %22, i32 580)
  %88 = call float @llvm.SI.load.const(<16 x i8> %22, i32 584)
  %89 = call float @llvm.SI.load.const(<16 x i8> %22, i32 588)
  %90 = call float @llvm.SI.load.const(<16 x i8> %22, i32 592)
  %91 = call float @llvm.SI.load.const(<16 x i8> %22, i32 596)
  %92 = call float @llvm.SI.load.const(<16 x i8> %22, i32 600)
  %93 = call float @llvm.SI.load.const(<16 x i8> %22, i32 604)
  %94 = call float @llvm.SI.load.const(<16 x i8> %22, i32 608)
  %95 = call float @llvm.SI.load.const(<16 x i8> %22, i32 612)
  %96 = call float @llvm.SI.load.const(<16 x i8> %22, i32 616)
  %97 = call float @llvm.SI.load.const(<16 x i8> %22, i32 620)
  %98 = call float @llvm.SI.load.const(<16 x i8> %22, i32 864)
  %99 = call float @llvm.SI.load.const(<16 x i8> %22, i32 868)
  %100 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0
  %101 = load <32 x i8> addrspace(2)* %100, !tbaa !0
  %102 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0
  %103 = load <16 x i8> addrspace(2)* %102, !tbaa !0
  %104 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 1
  %105 = load <32 x i8> addrspace(2)* %104, !tbaa !0
  %106 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 1
  %107 = load <16 x i8> addrspace(2)* %106, !tbaa !0
  %108 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 2
  %109 = load <32 x i8> addrspace(2)* %108, !tbaa !0
  %110 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 2
  %111 = load <16 x i8> addrspace(2)* %110, !tbaa !0
  %112 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 3
  %113 = load <32 x i8> addrspace(2)* %112, !tbaa !0
  %114 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 3
  %115 = load <16 x i8> addrspace(2)* %114, !tbaa !0
  %116 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 4
  %117 = load <32 x i8> addrspace(2)* %116, !tbaa !0
  %118 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 4
  %119 = load <16 x i8> addrspace(2)* %118, !tbaa !0
  %120 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 5
  %121 = load <32 x i8> addrspace(2)* %120, !tbaa !0
  %122 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 5
  %123 = load <16 x i8> addrspace(2)* %122, !tbaa !0
  %124 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 6
  %125 = load <32 x i8> addrspace(2)* %124, !tbaa !0
  %126 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 6
  %127 = load <16 x i8> addrspace(2)* %126, !tbaa !0
  %128 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 7
  %129 = load <32 x i8> addrspace(2)* %128, !tbaa !0
  %130 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 7
  %131 = load <16 x i8> addrspace(2)* %130, !tbaa !0
  %132 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 8
  %133 = load <32 x i8> addrspace(2)* %132, !tbaa !0
  %134 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 8
  %135 = load <16 x i8> addrspace(2)* %134, !tbaa !0
  %136 = fcmp ugt float %17, 0.000000e+00
  %137 = select i1 %136, float 1.000000e+00, float 0.000000e+00
  %138 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %4, <2 x i32> %6)
  %139 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %4, <2 x i32> %6)
  %140 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %4, <2 x i32> %6)
  %141 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %4, <2 x i32> %6)
  %142 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %4, <2 x i32> %6)
  %143 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %4, <2 x i32> %6)
  %144 = call float @llvm.SI.fs.interp(i32 2, i32 1, i32 %4, <2 x i32> %6)
  %145 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %4, <2 x i32> %6)
  %146 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %4, <2 x i32> %6)
  %147 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %4, <2 x i32> %6)
  %148 = call float @llvm.SI.fs.interp(i32 2, i32 2, i32 %4, <2 x i32> %6)
  %149 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %4, <2 x i32> %6)
  %150 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %4, <2 x i32> %6)
  %151 = call float @llvm.SI.fs.interp(i32 1, i32 3, i32 %4, <2 x i32> %6)
  %152 = call float @llvm.SI.fs.interp(i32 0, i32 4, i32 %4, <2 x i32> %6)
  %153 = call float @llvm.SI.fs.interp(i32 1, i32 4, i32 %4, <2 x i32> %6)
  %154 = call float @llvm.SI.fs.interp(i32 2, i32 4, i32 %4, <2 x i32> %6)
  %155 = call float @llvm.SI.fs.interp(i32 3, i32 4, i32 %4, <2 x i32> %6)
  %156 = call float @llvm.SI.fs.interp(i32 0, i32 5, i32 %4, <2 x i32> %6)
  %157 = call float @llvm.SI.fs.interp(i32 1, i32 5, i32 %4, <2 x i32> %6)
  %158 = call float @llvm.SI.fs.interp(i32 2, i32 5, i32 %4, <2 x i32> %6)
  %159 = call float @llvm.SI.fs.interp(i32 3, i32 5, i32 %4, <2 x i32> %6)
  %160 = call float @llvm.SI.fs.interp(i32 0, i32 6, i32 %4, <2 x i32> %6)
  %161 = call float @llvm.SI.fs.interp(i32 1, i32 6, i32 %4, <2 x i32> %6)
  %162 = fmul float %14, %98
  %163 = fadd float %162, %99
  %164 = call float @llvm.AMDIL.clamp.(float %137, float 0.000000e+00, float 1.000000e+00)
  %165 = call float @llvm.AMDIL.clamp.(float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
  %166 = call float @llvm.AMDIL.clamp.(float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
  %167 = call float @llvm.AMDIL.clamp.(float 1.000000e+00, float 0.000000e+00, float 1.000000e+00)
  %168 = bitcast float %164 to i32
  %169 = icmp ne i32 %168, 0
  %. = select i1 %169, float -1.000000e+00, float 1.000000e+00
  %170 = fsub float -0.000000e+00, %138
  %171 = fadd float %48, %170
  %172 = fsub float -0.000000e+00, %139
  %173 = fadd float %49, %172
  %174 = fsub float -0.000000e+00, %140
  %175 = fadd float %50, %174
  %176 = fmul float %171, %171
  %177 = fmul float %173, %173
  %178 = fadd float %177, %176
  %179 = fmul float %175, %175
  %180 = fadd float %178, %179
  %181 = call float @llvm.AMDGPU.rsq(float %180)
  %182 = fmul float %171, %181
  %183 = fmul float %173, %181
  %184 = fmul float %175, %181
  %185 = fmul float %., %61
  %186 = fmul float %13, %51
  %187 = fmul float %163, %52
  %188 = bitcast float %148 to i32
  %189 = bitcast float %149 to i32
  %190 = insertelement <2 x i32> undef, i32 %188, i32 0
  %191 = insertelement <2 x i32> %190, i32 %189, i32 1
  %192 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %191, <32 x i8> %109, <16 x i8> %111, i32 2)
  %193 = extractelement <4 x float> %192, i32 0
  %194 = extractelement <4 x float> %192, i32 1
  %195 = extractelement <4 x float> %192, i32 2
  %196 = extractelement <4 x float> %192, i32 3
  %197 = fmul float %193, 0x4012611180000000
  %198 = fmul float %194, 0x4012611180000000
  %199 = fmul float %195, 0x4012611180000000
  %200 = call float @llvm.AMDGPU.lrp(float %30, float %197, float 1.000000e+00)
  %201 = call float @llvm.AMDGPU.lrp(float %30, float %198, float 1.000000e+00)
  %202 = call float @llvm.AMDGPU.lrp(float %30, float %199, float 1.000000e+00)
  %203 = bitcast float %150 to i32
  %204 = bitcast float %151 to i32
  %205 = insertelement <2 x i32> undef, i32 %203, i32 0
  %206 = insertelement <2 x i32> %205, i32 %204, i32 1
  %207 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %206, <32 x i8> %117, <16 x i8> %119, i32 2)
  %208 = extractelement <4 x float> %207, i32 0
  %209 = extractelement <4 x float> %207, i32 1
  %210 = extractelement <4 x float> %207, i32 2
  %211 = extractelement <4 x float> %207, i32 3
  %212 = bitcast float %142 to i32
  %213 = bitcast float %143 to i32
  %214 = insertelement <2 x i32> undef, i32 %212, i32 0
  %215 = insertelement <2 x i32> %214, i32 %213, i32 1
  %216 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %215, <32 x i8> %113, <16 x i8> %115, i32 2)
  %217 = extractelement <4 x float> %216, i32 0
  %218 = extractelement <4 x float> %216, i32 1
  %219 = extractelement <4 x float> %216, i32 2
  %220 = extractelement <4 x float> %216, i32 3
  %221 = fmul float %217, %23
  %222 = fmul float %218, %24
  %223 = fmul float %219, %25
  %224 = fmul float %220, %26
  %225 = fmul float %221, %152
  %226 = fmul float %222, %153
  %227 = fmul float %223, %154
  %228 = fmul float %224, %155
  %229 = fsub float -0.000000e+00, %220
  %230 = fadd float 1.000000e+00, %229
  %231 = fmul float %230, %53
  %232 = call float @llvm.AMDGPU.lrp(float %231, float %217, float %225)
  %233 = call float @llvm.AMDGPU.lrp(float %231, float %218, float %226)
  %234 = call float @llvm.AMDGPU.lrp(float %231, float %219, float %227)
  %235 = bitcast float %144 to i32
  %236 = bitcast float %145 to i32
  %237 = insertelement <2 x i32> undef, i32 %235, i32 0
  %238 = insertelement <2 x i32> %237, i32 %236, i32 1
  %239 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %238, <32 x i8> %121, <16 x i8> %123, i32 2)
  %240 = extractelement <4 x float> %239, i32 0
  %241 = extractelement <4 x float> %239, i32 1
  %242 = extractelement <4 x float> %239, i32 3
  %243 = fmul float %58, %242
  %244 = fmul float %59, %240
  %245 = fsub float -0.000000e+00, %243
  %246 = fadd float 1.000000e+00, %245
  %247 = fsub float -0.000000e+00, %244
  %248 = fadd float 1.000000e+00, %247
  %249 = fmul float %232, %200
  %250 = fmul float %233, %201
  %251 = fmul float %234, %202
  %252 = fmul float %228, %196
  %253 = fmul float %156, %156
  %254 = fmul float %157, %157
  %255 = fadd float %254, %253
  %256 = fmul float %158, %158
  %257 = fadd float %255, %256
  %258 = call float @llvm.AMDGPU.rsq(float %257)
  %259 = fmul float %156, %258
  %260 = fmul float %157, %258
  %261 = fmul float %158, %258
  %262 = fcmp olt float 0.000000e+00, %185
  %263 = sext i1 %262 to i32
  %264 = bitcast i32 %263 to float
  %265 = bitcast float %264 to i32
  %266 = icmp ne i32 %265, 0
  br i1 %266, label %IF93, label %ENDIF92

IF93:                                             ; preds = %main_body
  %267 = fsub float -0.000000e+00, %259
  %268 = fsub float -0.000000e+00, %260
  %269 = fsub float -0.000000e+00, %261
  br label %ENDIF92

ENDIF92:                                          ; preds = %main_body, %IF93
  %temp20.0 = phi float [ %267, %IF93 ], [ %259, %main_body ]
  %temp21.0 = phi float [ %268, %IF93 ], [ %260, %main_body ]
  %temp22.0 = phi float [ %269, %IF93 ], [ %261, %main_body ]
  %270 = bitcast float %186 to i32
  %271 = bitcast float %187 to i32
  %272 = insertelement <2 x i32> undef, i32 %270, i32 0
  %273 = insertelement <2 x i32> %272, i32 %271, i32 1
  %274 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %273, <32 x i8> %133, <16 x i8> %135, i32 2)
  %275 = extractelement <4 x float> %274, i32 0
  %276 = extractelement <4 x float> %274, i32 1
  %277 = extractelement <4 x float> %274, i32 2
  %278 = extractelement <4 x float> %274, i32 3
  %279 = fmul float %275, %44
  %280 = fadd float %279, %45
  %281 = fmul float %276, %44
  %282 = fadd float %281, %45
  %283 = fmul float %277, %44
  %284 = fadd float %283, %45
  %285 = fmul float %278, %46
  %286 = fadd float %285, %47
  %287 = bitcast float %146 to i32
  %288 = bitcast float %147 to i32
  %289 = insertelement <2 x i32> undef, i32 %287, i32 0
  %290 = insertelement <2 x i32> %289, i32 %288, i32 1
  %291 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %290, <32 x i8> %125, <16 x i8> %127, i32 2)
  %292 = extractelement <4 x float> %291, i32 0
  %293 = extractelement <4 x float> %291, i32 1
  %294 = extractelement <4 x float> %291, i32 2
  %295 = extractelement <4 x float> %291, i32 3
  %296 = fmul float %295, 3.200000e+01
  %297 = fadd float %296, -1.600000e+01
  %298 = call float @llvm.AMDIL.exp.(float %297)
  %299 = fmul float %292, %298
  %300 = fmul float %293, %298
  %301 = fmul float %294, %298
  %302 = fmul float %34, %299
  %303 = fadd float %302, %159
  %304 = fmul float %35, %300
  %305 = fadd float %304, %160
  %306 = fmul float %36, %301
  %307 = fadd float %306, %161
  %308 = fmul float %303, %286
  %309 = fmul float %305, %286
  %310 = fmul float %307, %286
  %311 = fmul float %286, 5.000000e-01
  %312 = fadd float %311, 5.000000e-01
  %313 = fmul float %temp20.0, %182
  %314 = fmul float %temp21.0, %183
  %315 = fadd float %314, %313
  %316 = fmul float %temp22.0, %184
  %317 = fadd float %315, %316
  %318 = call float @llvm.AMDIL.clamp.(float %317, float 0.000000e+00, float 1.000000e+00)
  %319 = fsub float -0.000000e+00, %318
  %320 = fadd float 1.000000e+00, %319
  %321 = call float @llvm.pow.f32(float %320, float 4.000000e+00)
  %322 = fmul float %321, %37
  %323 = fmul float %248, %322
  %324 = fsub float -0.000000e+00, %323
  %325 = fadd float %248, %324
  %326 = fmul float %temp20.0, %182
  %327 = fmul float %temp21.0, %183
  %328 = fadd float %327, %326
  %329 = fmul float %temp22.0, %184
  %330 = fadd float %328, %329
  %331 = fmul float %330, %temp20.0
  %332 = fmul float %330, %temp21.0
  %333 = fmul float %330, %temp22.0
  %334 = fmul float 2.000000e+00, %331
  %335 = fmul float 2.000000e+00, %332
  %336 = fmul float 2.000000e+00, %333
  %337 = fsub float -0.000000e+00, %334
  %338 = fadd float %182, %337
  %339 = fsub float -0.000000e+00, %335
  %340 = fadd float %183, %339
  %341 = fsub float -0.000000e+00, %336
  %342 = fadd float %184, %341
  %343 = fsub float -0.000000e+00, %temp20.0
  %344 = call float @llvm.AMDGPU.lrp(float %325, float %343, float %338)
  %345 = fsub float -0.000000e+00, %temp21.0
  %346 = call float @llvm.AMDGPU.lrp(float %325, float %345, float %340)
  %347 = fsub float -0.000000e+00, %temp22.0
  %348 = call float @llvm.AMDGPU.lrp(float %325, float %347, float %342)
  %349 = call float @fabs(float %344)
  %350 = call float @fabs(float %346)
  %351 = call float @fabs(float %348)
  %352 = fcmp uge float %350, %351
  %353 = select i1 %352, float %350, float %351
  %354 = fcmp uge float %349, %353
  %355 = select i1 %354, float %349, float %353
  %356 = fadd float %355, 0xBF50624DE0000000
  %357 = fcmp oge float %356, %349
  %358 = sext i1 %357 to i32
  %359 = bitcast i32 %358 to float
  %360 = bitcast float %359 to i32
  %361 = and i32 %360, 1065353216
  %362 = bitcast i32 %361 to float
  %363 = fcmp oge float %356, %350
  %364 = sext i1 %363 to i32
  %365 = bitcast i32 %364 to float
  %366 = bitcast float %365 to i32
  %367 = and i32 %366, 1065353216
  %368 = bitcast i32 %367 to float
  %369 = fcmp oge float %356, %351
  %370 = sext i1 %369 to i32
  %371 = bitcast i32 %370 to float
  %372 = bitcast float %371 to i32
  %373 = and i32 %372, 1065353216
  %374 = bitcast i32 %373 to float
  %375 = fdiv float 1.000000e+00, %355
  %376 = fmul float -1.000000e+00, %375
  %377 = fmul float -1.000000e+00, %375
  %378 = fmul float 1.000000e+00, %375
  %379 = fmul float %344, %376
  %380 = fmul float %346, %377
  %381 = fmul float %348, %378
  %382 = fadd float %60, -1.000000e+00
  %383 = fmul float %325, %382
  %384 = fmul float %379, %362
  %385 = fmul float %380, %368
  %386 = fmul float %381, %374
  %387 = call float @floor(float %383)
  %388 = fsub float -0.000000e+00, %387
  %389 = fadd float %60, %388
  %390 = call float @llvm.AMDIL.exp.(float %389)
  %391 = fdiv float 1.000000e+00, %390
  %392 = fmul float %384, %391
  %393 = fmul float %385, %391
  %394 = fmul float %386, %391
  %395 = fsub float -0.000000e+00, %392
  %396 = fadd float %379, %395
  %397 = fsub float -0.000000e+00, %393
  %398 = fadd float %380, %397
  %399 = fsub float -0.000000e+00, %394
  %400 = fadd float %381, %399
  %401 = insertelement <4 x float> undef, float %396, i32 0
  %402 = insertelement <4 x float> %401, float %398, i32 1
  %403 = insertelement <4 x float> %402, float %400, i32 2
  %404 = insertelement <4 x float> %403, float %383, i32 3
  %405 = call <4 x float> @llvm.AMDGPU.cube(<4 x float> %404)
  %406 = extractelement <4 x float> %405, i32 0
  %407 = extractelement <4 x float> %405, i32 1
  %408 = extractelement <4 x float> %405, i32 2
  %409 = extractelement <4 x float> %405, i32 3
  %410 = call float @fabs(float %408)
  %411 = fdiv float 1.000000e+00, %410
  %412 = fmul float %406, %411
  %413 = fadd float %412, 1.500000e+00
  %414 = fmul float %407, %411
  %415 = fadd float %414, 1.500000e+00
  %416 = bitcast float %415 to i32
  %417 = bitcast float %413 to i32
  %418 = bitcast float %409 to i32
  %419 = bitcast float %383 to i32
  %420 = insertelement <4 x i32> undef, i32 %416, i32 0
  %421 = insertelement <4 x i32> %420, i32 %417, i32 1
  %422 = insertelement <4 x i32> %421, i32 %418, i32 2
  %423 = insertelement <4 x i32> %422, i32 %419, i32 3
  %424 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %423, <32 x i8> %129, <16 x i8> %131, i32 4)
  %425 = extractelement <4 x float> %424, i32 0
  %426 = extractelement <4 x float> %424, i32 1
  %427 = extractelement <4 x float> %424, i32 2
  %428 = extractelement <4 x float> %424, i32 3
  %429 = fmul float %428, 3.200000e+01
  %430 = fadd float %429, -1.600000e+01
  %431 = call float @llvm.AMDIL.exp.(float %430)
  %432 = fmul float %425, %431
  %433 = fmul float %426, %431
  %434 = fmul float %427, %431
  %435 = fmul float %27, %241
  %436 = fmul float %28, %241
  %437 = fmul float %29, %241
  %438 = fmul float %435, %241
  %439 = fmul float %436, %241
  %440 = fmul float %437, %241
  %441 = fmul float %325, 2.000000e+00
  %442 = fadd float %441, -1.000000e+00
  %443 = call float @llvm.AMDIL.clamp.(float %442, float 0.000000e+00, float 1.000000e+00)
  %444 = fmul float %280, %312
  %445 = fmul float %282, %312
  %446 = fmul float %284, %312
  %447 = fmul float %432, %31
  %448 = fmul float %433, %32
  %449 = fmul float %434, %33
  %450 = fmul float %438, %447
  %451 = fmul float %439, %448
  %452 = fmul float %440, %449
  %453 = call float @llvm.AMDGPU.lrp(float %443, float %438, float %450)
  %454 = call float @llvm.AMDGPU.lrp(float %443, float %439, float %451)
  %455 = call float @llvm.AMDGPU.lrp(float %443, float %440, float %452)
  %456 = call float @llvm.AMDGPU.lrp(float %322, float 1.000000e+00, float %438)
  %457 = call float @llvm.AMDGPU.lrp(float %322, float 1.000000e+00, float %439)
  %458 = call float @llvm.AMDGPU.lrp(float %322, float 1.000000e+00, float %440)
  %459 = call float @llvm.AMDGPU.lrp(float %456, float %453, float %249)
  %460 = call float @llvm.AMDGPU.lrp(float %457, float %454, float %250)
  %461 = call float @llvm.AMDGPU.lrp(float %458, float %455, float %251)
  %462 = fmul float %308, %459
  %463 = fmul float %309, %460
  %464 = fmul float %310, %461
  %465 = fmul float %444, %249
  %466 = fadd float %465, %462
  %467 = fmul float %445, %250
  %468 = fadd float %467, %463
  %469 = fmul float %446, %251
  %470 = fadd float %469, %464
  %471 = fsub float -0.000000e+00, %66
  %472 = fadd float %138, %471
  %473 = fsub float -0.000000e+00, %67
  %474 = fadd float %139, %473
  %475 = fsub float -0.000000e+00, %68
  %476 = fadd float %140, %475
  %477 = fmul float %472, %472
  %478 = fmul float %474, %474
  %479 = fadd float %478, %477
  %480 = fmul float %476, %476
  %481 = fadd float %479, %480
  %482 = call float @llvm.AMDGPU.rsq(float %481)
  %483 = fmul float %73, %482
  %484 = fdiv float 1.000000e+00, %483
  %485 = call float @llvm.AMDIL.clamp.(float %484, float 0.000000e+00, float 1.000000e+00)
  %486 = fsub float -0.000000e+00, %485
  %487 = fadd float 1.000000e+00, %486
  %488 = fmul float %487, %482
  %489 = fsub float -0.000000e+00, %472
  %490 = fmul float %489, %482
  %491 = fsub float -0.000000e+00, %474
  %492 = fmul float %491, %482
  %493 = fsub float -0.000000e+00, %476
  %494 = fmul float %493, %482
  %495 = fsub float -0.000000e+00, %70
  %496 = fsub float -0.000000e+00, %71
  %497 = fsub float -0.000000e+00, %72
  %498 = fmul float %490, %495
  %499 = fmul float %492, %496
  %500 = fadd float %499, %498
  %501 = fmul float %494, %497
  %502 = fadd float %500, %501
  %503 = fmul float %502, %65
  %504 = fsub float -0.000000e+00, %503
  %505 = fadd float %69, %504
  %506 = call float @llvm.AMDIL.clamp.(float %505, float 0.000000e+00, float 1.000000e+00)
  %507 = fmul float %488, %506
  %508 = fmul float %temp20.0, %490
  %509 = fmul float %temp21.0, %492
  %510 = fadd float %509, %508
  %511 = fmul float %temp22.0, %494
  %512 = fadd float %510, %511
  %513 = call float @llvm.AMDIL.clamp.(float %512, float 0.000000e+00, float 1.000000e+00)
  %514 = fadd float %182, %490
  %515 = fadd float %183, %492
  %516 = fadd float %184, %494
  %517 = fmul float %514, %514
  %518 = fmul float %515, %515
  %519 = fadd float %518, %517
  %520 = fmul float %516, %516
  %521 = fadd float %519, %520
  %522 = call float @llvm.AMDGPU.rsq(float %521)
  %523 = fmul float %514, %522
  %524 = fmul float %515, %522
  %525 = fmul float %516, %522
  %526 = fmul float %523, %temp20.0
  %527 = fmul float %524, %temp21.0
  %528 = fadd float %527, %526
  %529 = fmul float %525, %temp22.0
  %530 = fadd float %528, %529
  %531 = call i32 @llvm.SI.tid()
  %532 = getelementptr [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %531
  %533 = and i32 %531, -4
  %534 = getelementptr [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %533
  %535 = add i32 %533, 1
  %536 = getelementptr [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %535
  %537 = bitcast float %530 to i32
  store i32 %537, i32 addrspace(3)* %532
  %538 = load i32 addrspace(3)* %534
  %539 = bitcast i32 %538 to float
  %540 = load i32 addrspace(3)* %536
  %541 = bitcast i32 %540 to float
  %542 = fsub float %541, %539
  %543 = insertelement <4 x float> undef, float %542, i32 0
  %544 = insertelement <4 x float> %543, float %542, i32 1
  %545 = insertelement <4 x float> %544, float %542, i32 2
  %546 = insertelement <4 x float> %545, float %542, i32 3
  %547 = extractelement <4 x float> %546, i32 0
  %548 = call float @fabs(float %547)
  %549 = fmul float %98, %530
  %550 = fmul float %98, %530
  %551 = fmul float %98, %530
  %552 = fmul float %98, %530
  %553 = call i32 @llvm.SI.tid()
  %554 = getelementptr [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %553
  %555 = and i32 %553, -4
  %556 = getelementptr [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %555
  %557 = add i32 %555, 2
  %558 = getelementptr [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %557
  %559 = bitcast float %549 to i32
  store i32 %559, i32 addrspace(3)* %554
  %560 = load i32 addrspace(3)* %556
  %561 = bitcast i32 %560 to float
  %562 = load i32 addrspace(3)* %558
  %563 = bitcast i32 %562 to float
  %564 = fsub float %563, %561
  %565 = bitcast float %550 to i32
  store i32 %565, i32 addrspace(3)* %554
  %566 = load i32 addrspace(3)* %556
  %567 = bitcast i32 %566 to float
  %568 = load i32 addrspace(3)* %558
  %569 = bitcast i32 %568 to float
  %570 = fsub float %569, %567
  %571 = bitcast float %551 to i32
  store i32 %571, i32 addrspace(3)* %554
  %572 = load i32 addrspace(3)* %556
  %573 = bitcast i32 %572 to float
  %574 = load i32 addrspace(3)* %558
  %575 = bitcast i32 %574 to float
  %576 = fsub float %575, %573
  %577 = bitcast float %552 to i32
  store i32 %577, i32 addrspace(3)* %554
  %578 = load i32 addrspace(3)* %556
  %579 = bitcast i32 %578 to float
  %580 = load i32 addrspace(3)* %558
  %581 = bitcast i32 %580 to float
  %582 = fsub float %581, %579
  %583 = insertelement <4 x float> undef, float %564, i32 0
  %584 = insertelement <4 x float> %583, float %570, i32 1
  %585 = insertelement <4 x float> %584, float %576, i32 2
  %586 = insertelement <4 x float> %585, float %582, i32 3
  %587 = extractelement <4 x float> %586, i32 0
  %588 = call float @fabs(float %587)
  %589 = fadd float %548, %588
  %590 = fmul float %589, 5.000000e-01
  %591 = fadd float %590, 0x3EE4F8B580000000
  %592 = fmul float %591, -1.000000e+00
  %593 = fadd float %592, %530
  %594 = fmul float %591, 1.000000e+00
  %595 = fadd float %594, %530
  %596 = call float @llvm.AMDIL.clamp.(float %593, float 0.000000e+00, float 1.000000e+00)
  %597 = call float @llvm.AMDIL.clamp.(float %595, float 0.000000e+00, float 1.000000e+00)
  %598 = fmul float %523, %182
  %599 = fmul float %524, %183
  %600 = fadd float %599, %598
  %601 = fmul float %525, %184
  %602 = fadd float %600, %601
  %603 = call float @llvm.AMDIL.clamp.(float %602, float 0.000000e+00, float 1.000000e+00)
  %604 = fsub float -0.000000e+00, %603
  %605 = fadd float 1.000000e+00, %604
  %606 = call float @llvm.pow.f32(float %605, float 4.000000e+00)
  %607 = fmul float %606, %37
  %608 = fmul float %246, %607
  %609 = fmul float %248, %607
  %610 = fsub float -0.000000e+00, %608
  %611 = fadd float %246, %610
  %612 = fsub float -0.000000e+00, %609
  %613 = fadd float %248, %612
  %614 = call float @llvm.pow.f32(float %611, float 4.000000e+00)
  %615 = call float @llvm.pow.f32(float %613, float 4.000000e+00)
  %616 = fadd float %614, 0x3E7AD7F2A0000000
  %617 = fadd float %615, 0x3E7AD7F2A0000000
  %618 = call float @llvm.AMDIL.clamp.(float %616, float 0.000000e+00, float 1.000000e+00)
  %619 = call float @llvm.AMDIL.clamp.(float %617, float 0.000000e+00, float 1.000000e+00)
  %620 = fmul float %596, %618
  %621 = fmul float %597, %618
  %622 = fmul float %596, %619
  %623 = fmul float %597, %619
  %624 = fadd float %618, -1.000000e+00
  %625 = fadd float %618, -1.000000e+00
  %626 = fadd float %619, -1.000000e+00
  %627 = fadd float %619, -1.000000e+00
  %628 = fmul float %596, %624
  %629 = fadd float %628, 1.000000e+00
  %630 = fmul float %597, %625
  %631 = fadd float %630, 1.000000e+00
  %632 = fmul float %596, %626
  %633 = fadd float %632, 1.000000e+00
  %634 = fmul float %597, %627
  %635 = fadd float %634, 1.000000e+00
  %636 = fdiv float 1.000000e+00, %629
  %637 = fdiv float 1.000000e+00, %631
  %638 = fdiv float 1.000000e+00, %633
  %639 = fdiv float 1.000000e+00, %635
  %640 = fmul float %620, %636
  %641 = fmul float %621, %637
  %642 = fmul float %622, %638
  %643 = fmul float %623, %639
  %644 = call float @llvm.AMDIL.clamp.(float %640, float 0.000000e+00, float 1.000000e+00)
  %645 = call float @llvm.AMDIL.clamp.(float %641, float 0.000000e+00, float 1.000000e+00)
  %646 = call float @llvm.AMDIL.clamp.(float %642, float 0.000000e+00, float 1.000000e+00)
  %647 = call float @llvm.AMDIL.clamp.(float %643, float 0.000000e+00, float 1.000000e+00)
  %648 = fsub float -0.000000e+00, %646
  %649 = fadd float %647, %648
  %650 = fsub float -0.000000e+00, %596
  %651 = fadd float %597, %650
  %652 = fadd float %651, 0x3EB0C6F7A0000000
  %653 = fmul float %temp20.0, %182
  %654 = fmul float %temp21.0, %183
  %655 = fadd float %654, %653
  %656 = fmul float %temp22.0, %184
  %657 = fadd float %655, %656
  %658 = call float @llvm.AMDIL.clamp.(float %657, float 0.000000e+00, float 1.000000e+00)
  %659 = fmul float %658, %513
  %660 = fcmp uge float %659, 0x3F847AE140000000
  %661 = select i1 %660, float %659, float 0x3F847AE140000000
  %662 = call float @llvm.AMDGPU.rsq(float %661)
  %663 = fmul float %662, %661
  %664 = fsub float -0.000000e+00, %661
  %665 = call float @llvm.AMDGPU.cndlt(float %664, float %663, float 0.000000e+00)
  %666 = call float @llvm.AMDGPU.lrp(float %618, float 1.000000e+00, float %665)
  %667 = call float @llvm.AMDGPU.lrp(float %619, float 1.000000e+00, float %665)
  %668 = fmul float %652, %667
  %669 = fdiv float 1.000000e+00, %668
  %670 = fmul float %649, %669
  %671 = fmul float %27, %241
  %672 = fmul float %28, %241
  %673 = fmul float %29, %241
  %674 = fmul float %671, %241
  %675 = fmul float %672, %241
  %676 = fmul float %673, %241
  %677 = call float @llvm.AMDGPU.lrp(float %674, float %670, float %249)
  %678 = call float @llvm.AMDGPU.lrp(float %675, float %670, float %250)
  %679 = call float @llvm.AMDGPU.lrp(float %676, float %670, float %251)
  %680 = fmul float %677, %513
  %681 = fmul float %678, %513
  %682 = fmul float %679, %513
  %683 = fmul float %680, %62
  %684 = fmul float %681, %63
  %685 = fmul float %682, %64
  %686 = fmul float %683, %507
  %687 = fmul float %684, %507
  %688 = fmul float %685, %507
  %689 = fmul float %138, %82
  %690 = fmul float %139, %83
  %691 = fadd float %689, %690
  %692 = fmul float %140, %84
  %693 = fadd float %691, %692
  %694 = fmul float %141, %85
  %695 = fadd float %693, %694
  %696 = fmul float %138, %86
  %697 = fmul float %139, %87
  %698 = fadd float %696, %697
  %699 = fmul float %140, %88
  %700 = fadd float %698, %699
  %701 = fmul float %141, %89
  %702 = fadd float %700, %701
  %703 = fmul float %138, %90
  %704 = fmul float %139, %91
  %705 = fadd float %703, %704
  %706 = fmul float %140, %92
  %707 = fadd float %705, %706
  %708 = fmul float %141, %93
  %709 = fadd float %707, %708
  %710 = fmul float %138, %94
  %711 = fmul float %139, %95
  %712 = fadd float %710, %711
  %713 = fmul float %140, %96
  %714 = fadd float %712, %713
  %715 = fmul float %141, %97
  %716 = fadd float %714, %715
  %717 = fdiv float 1.000000e+00, %716
  %718 = fmul float %695, %717
  %719 = fmul float %702, %717
  %720 = fmul float %718, 5.000000e-01
  %721 = fadd float %720, 5.000000e-01
  %722 = fmul float %719, 5.000000e-01
  %723 = fadd float %722, 5.000000e-01
  %724 = fmul float %721, %78
  %725 = fadd float %724, %80
  %726 = fmul float %723, %79
  %727 = fadd float %726, %81
  %728 = bitcast float %725 to i32
  %729 = bitcast float %727 to i32
  %730 = insertelement <2 x i32> undef, i32 %728, i32 0
  %731 = insertelement <2 x i32> %730, i32 %729, i32 1
  %732 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %731, <32 x i8> %105, <16 x i8> %107, i32 2)
  %733 = extractelement <4 x float> %732, i32 0
  %734 = extractelement <4 x float> %732, i32 1
  %735 = extractelement <4 x float> %732, i32 2
  %736 = bitcast float %721 to i32
  %737 = bitcast float %723 to i32
  %738 = bitcast float 0.000000e+00 to i32
  %739 = insertelement <4 x i32> undef, i32 %736, i32 0
  %740 = insertelement <4 x i32> %739, i32 %737, i32 1
  %741 = insertelement <4 x i32> %740, i32 %738, i32 2
  %742 = insertelement <4 x i32> %741, i32 undef, i32 3
  %743 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %742, <32 x i8> %101, <16 x i8> %103, i32 2)
  %744 = extractelement <4 x float> %743, i32 0
  %745 = extractelement <4 x float> %743, i32 1
  %746 = fsub float -0.000000e+00, %745
  %747 = fadd float 1.000000e+00, %746
  %748 = fmul float %747, 2.500000e-01
  %749 = fsub float -0.000000e+00, %748
  %750 = fadd float %744, %749
  %751 = fsub float -0.000000e+00, %709
  %752 = fadd float %744, %751
  %753 = fmul float %744, %744
  %754 = fsub float -0.000000e+00, %753
  %755 = fadd float %750, %754
  %756 = fcmp uge float %755, %74
  %757 = select i1 %756, float %755, float %74
  %758 = fmul float %752, %752
  %759 = fadd float %758, %757
  %760 = fdiv float 1.000000e+00, %759
  %761 = fmul float %757, %760
  %762 = call float @llvm.pow.f32(float %761, float %75)
  %763 = fmul float %762, %76
  %764 = fadd float %763, %77
  %765 = call float @llvm.AMDIL.clamp.(float %764, float 0.000000e+00, float 1.000000e+00)
  %766 = fmul float %765, %765
  %767 = fmul float 2.000000e+00, %765
  %768 = fsub float -0.000000e+00, %767
  %769 = fadd float 3.000000e+00, %768
  %770 = fmul float %766, %769
  %771 = fcmp oge float %752, 0.000000e+00
  %772 = sext i1 %771 to i32
  %773 = bitcast i32 %772 to float
  %774 = bitcast float %773 to i32
  %775 = icmp ne i32 %774, 0
  %.98 = select i1 %775, float 1.000000e+00, float %770
  %776 = fmul float %733, %.98
  %777 = fmul float %734, %.98
  %778 = fmul float %735, %.98
  %779 = fmul float %686, %776
  %780 = fmul float %687, %777
  %781 = fmul float %688, %778
  %782 = fmul float %779, %312
  %783 = fadd float %782, %466
  %784 = fmul float %780, %312
  %785 = fadd float %784, %468
  %786 = fmul float %781, %312
  %787 = fadd float %786, %470
  %788 = call float @llvm.AMDGPU.lrp(float %196, float %211, float 1.000000e+00)
  %789 = call float @llvm.AMDGPU.lrp(float %42, float %208, float 1.000000e+00)
  %790 = call float @llvm.AMDGPU.lrp(float %42, float %209, float 1.000000e+00)
  %791 = call float @llvm.AMDGPU.lrp(float %42, float %210, float 1.000000e+00)
  %792 = call float @llvm.AMDGPU.lrp(float %43, float %788, float 1.000000e+00)
  %793 = fmul float %789, %792
  %794 = fmul float %790, %792
  %795 = fmul float %791, %792
  %796 = fmul float %783, %793
  %797 = fmul float %785, %794
  %798 = fmul float %787, %795
  %799 = fmul float %temp20.0, %182
  %800 = fmul float %temp21.0, %183
  %801 = fadd float %800, %799
  %802 = fmul float %temp22.0, %184
  %803 = fadd float %801, %802
  %804 = call float @fabs(float %803)
  %805 = fmul float %804, %804
  %806 = fmul float %805, %54
  %807 = fadd float %806, %55
  %808 = call float @llvm.AMDIL.clamp.(float %807, float 0.000000e+00, float 1.000000e+00)
  %809 = fsub float -0.000000e+00, %808
  %810 = fadd float 1.000000e+00, %809
  %811 = fmul float %40, %810
  %812 = fmul float %40, %810
  %813 = fmul float %40, %810
  %814 = fmul float %41, %810
  %815 = call float @llvm.AMDGPU.lrp(float %811, float %38, float %796)
  %816 = call float @llvm.AMDGPU.lrp(float %812, float %38, float %797)
  %817 = call float @llvm.AMDGPU.lrp(float %813, float %38, float %798)
  %818 = call float @llvm.AMDGPU.lrp(float %814, float %39, float %252)
  %819 = fcmp uge float %815, 0x3E6FFFFE60000000
  %820 = select i1 %819, float %815, float 0x3E6FFFFE60000000
  %821 = fcmp uge float %816, 0x3E6FFFFE60000000
  %822 = select i1 %821, float %816, float 0x3E6FFFFE60000000
  %823 = fcmp uge float %817, 0x3E6FFFFE60000000
  %824 = select i1 %823, float %817, float 0x3E6FFFFE60000000
  %825 = fcmp uge float %820, 6.550400e+04
  %826 = select i1 %825, float 6.550400e+04, float %820
  %827 = fcmp uge float %822, 6.550400e+04
  %828 = select i1 %827, float 6.550400e+04, float %822
  %829 = fcmp uge float %824, 6.550400e+04
  %830 = select i1 %829, float 6.550400e+04, float %824
  %831 = fmul float %818, %56
  %832 = fadd float %831, %57
  %833 = call float @llvm.AMDIL.clamp.(float %832, float 0.000000e+00, float 1.000000e+00)
  %834 = call i32 @llvm.SI.packf16(float %826, float %828)
  %835 = bitcast i32 %834 to float
  %836 = call i32 @llvm.SI.packf16(float %830, float %833)
  %837 = bitcast i32 %836 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %835, float %837, float %835, float %837)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

; Function Attrs: readnone
declare float @llvm.AMDGPU.rsq(float) #2

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDGPU.lrp(float, float, float) #2

; Function Attrs: readnone
declare float @llvm.AMDIL.exp.(float) #2

; Function Attrs: nounwind readonly
declare float @llvm.pow.f32(float, float) #3

; Function Attrs: readonly
declare float @fabs(float) #4

; Function Attrs: readonly
declare float @floor(float) #4

; Function Attrs: readnone
declare <4 x float> @llvm.AMDGPU.cube(<4 x float>) #2

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.samplel.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readnone
declare i32 @llvm.SI.tid() #2

; Function Attrs: readnone
declare float @llvm.AMDGPU.cndlt(float, float, float) #2

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }
attributes #3 = { nounwind readonly }
attributes #4 = { readonly }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg104, %SGPR2_SGPR3 in %vreg105, %SGPR4_SGPR5 in %vreg106, %SGPR7 in %vreg108, %VGPR0 in %vreg109, %VGPR1 in %vreg110, %VGPR2 in %vreg111, %VGPR3 in %vreg112, %VGPR4 in %vreg113

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR7 %VGPR0 %VGPR1 %VGPR2 %VGPR3 %VGPR4
    Successors according to CFG: BB#1(16) BB#2(16)

BB#1: derived from LLVM BB %IF93
    Live Ins: %SGPR12 %SGPR8 %SGPR9 %SGPR25 %SGPR46 %SGPR47 %VGPR65 %VGPR63 %VGPR1 %VGPR0 %SGPR53 %VGPR67 %VGPR68 %VGPR66 %VGPR46 %VGPR45 %VGPR4 %VGPR40 %VGPR53 %VGPR54 %VGPR52 %VGPR49 %VGPR57 %VGPR58 %VGPR56 %VGPR55 %VGPR43 %VGPR44 %VGPR42 %VGPR41 %VGPR50 %VGPR51 %VGPR48 %VGPR47 %SGPR45 %VGPR59 %SGPR36_SGPR37_SGPR38_SGPR39_SGPR40_SGPR41_SGPR42_SGPR43 %SGPR32_SGPR33_SGPR34_SGPR35 %VGPR61 %VGPR60 %VGPR62 %VGPR10_VGPR11_VGPR12_VGPR13 %VGPR26 %VGPR35 %VGPR23 %VGPR14_VGPR15_VGPR16_VGPR17 %VGPR18_VGPR19_VGPR20_VGPR21 %SGPR2_SGPR3 %SGPR4_SGPR5 %VGPR2 %VGPR3 %VGPR5_VGPR6_VGPR7_VGPR8 %VGPR9 %VGPR31 %VGPR22 %VGPR32 %VGPR33 %VGPR34 %VGPR25 %VGPR37 %VGPR27 %VGPR24 %VGPR36 %SGPR29 %SGPR30 %SGPR31 %SGPR44 %SGPR27 %SGPR20 %SGPR23 %SGPR26 %SGPR21 %SGPR24 %SGPR7 %SGPR28 %SGPR13 %SGPR54 %SGPR0 %SGPR17 %SGPR49 %SGPR50 %SGPR6 %SGPR22 %SGPR1 %SGPR11 %SGPR48 %SGPR16 %SGPR14 %SGPR51 %SGPR18 %SGPR15 %SGPR52 %SGPR19 %SGPR10 %SGPR56_SGPR57 %VGPR64 %VGPR38_VGPR39 %VGPR30 %VGPR29 %VGPR28
    Predecessors according to CFG: BB#0
    Successors according to CFG: BB#2

BB#2: derived from LLVM BB %ENDIF92
    Live Ins: %SGPR12 %SGPR8 %SGPR9 %SGPR25 %SGPR46 %SGPR47 %VGPR65 %VGPR63 %VGPR1 %VGPR0 %SGPR53 %VGPR67 %VGPR68 %VGPR66 %VGPR46 %VGPR45 %VGPR4 %VGPR40 %VGPR53 %VGPR54 %VGPR52 %VGPR49 %VGPR57 %VGPR58 %VGPR56 %VGPR55 %VGPR43 %VGPR44 %VGPR42 %VGPR41 %VGPR50 %VGPR51 %VGPR48 %VGPR47 %SGPR45 %VGPR59 %SGPR36_SGPR37_SGPR38_SGPR39_SGPR40_SGPR41_SGPR42_SGPR43 %SGPR32_SGPR33_SGPR34_SGPR35 %VGPR61 %VGPR60 %VGPR62 %VGPR10_VGPR11_VGPR12_VGPR13 %VGPR26 %VGPR35 %VGPR23 %VGPR14_VGPR15_VGPR16_VGPR17 %VGPR18_VGPR19_VGPR20_VGPR21 %SGPR2_SGPR3 %SGPR4_SGPR5 %VGPR2 %VGPR3 %VGPR5_VGPR6_VGPR7_VGPR8 %VGPR9 %VGPR31 %VGPR22 %VGPR32 %VGPR33 %VGPR34 %VGPR25 %VGPR37 %VGPR27 %VGPR24 %VGPR36 %SGPR29 %SGPR30 %SGPR31 %SGPR44 %SGPR27 %SGPR20 %SGPR23 %SGPR26 %SGPR21 %SGPR24 %SGPR7 %SGPR28 %SGPR13 %SGPR54 %SGPR0 %SGPR17 %SGPR49 %SGPR50 %SGPR6 %SGPR22 %SGPR1 %SGPR11 %SGPR48 %SGPR16 %SGPR14 %SGPR51 %SGPR18 %SGPR15 %SGPR52 %SGPR19 %SGPR10 %SGPR56_SGPR57 %VGPR64 %VGPR38_VGPR39 %VGPR30 %VGPR29 %VGPR28
    Predecessors according to CFG: BB#0 BB#1
	EXP 0, 9, 0, 1, 1, %VGPR0, %VGPR0, %VGPR0, %VGPR0, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	EXP 0, 9, 0, 1, 1, v0, v0, v0, v0 ; F8001890 00000000
	S_ENDPGM                          ; BF810000

VERT
DCL IN[0]
DCL IN[1]
DCL IN[2]
DCL IN[3]
DCL IN[4]
DCL IN[5]
DCL IN[6]
DCL IN[7]
DCL IN[8]
DCL IN[9]
DCL OUT[0], POSITION
DCL OUT[1], CLIPVERTEX
DCL OUT[2], GENERIC[19]
DCL OUT[3], GENERIC[20]
DCL OUT[4], GENERIC[21]
DCL OUT[5], GENERIC[22]
DCL OUT[6], GENERIC[23]
DCL OUT[7], GENERIC[24]
DCL OUT[8], GENERIC[25]
DCL CONST[0..240]
DCL TEMP[0..10], LOCAL
DCL ADDR[0]
IMM[0] FLT32 {    0.0010,     1.0000,   255.0100,     0.0000}
IMM[1] INT32 {3, 41, 42, 43}
  0: MAD TEMP[0].xyz, IN[1].xyzz, CONST[36].zzzz, CONST[36].xyxx
  1: MOV TEMP[1].xz, TEMP[0].xxzx
  2: ADD TEMP[0].x, TEMP[0].yyyy, IMM[0].xxxx
  3: MOV TEMP[1].y, TEMP[0].xxxx
  4: MOV TEMP[0], IN[0]
  5: MOV TEMP[2].xyz, TEMP[1].xyzx
  6: UIF CONST[240].xxxx :0
  7:   DP3 TEMP[3].x, IN[9].xyzz, IMM[0].yyyy
  8:   ADD TEMP[3].x, IMM[0].yyyy, -TEMP[3].xxxx
  9:   MUL TEMP[4], IN[8], IMM[0].zzzz
 10:   F2I TEMP[4], TEMP[4]
 11:   UMAD TEMP[5].x, TEMP[4].wwww, IMM[1].xxxx, IMM[1].yyyy
 12:   UMAD TEMP[6].x, TEMP[4].zzzz, IMM[1].xxxx, IMM[1].yyyy
 13:   UMAD TEMP[7].x, TEMP[4].yyyy, IMM[1].xxxx, IMM[1].yyyy
 14:   UMAD TEMP[8].x, TEMP[4].xxxx, IMM[1].xxxx, IMM[1].yyyy
 15:   UARL ADDR[0].x, TEMP[8].xxxx
 16:   MUL TEMP[8], CONST[ADDR[0].x], IN[9].xxxx
 17:   UARL ADDR[0].x, TEMP[7].xxxx
 18:   MAD TEMP[7], CONST[ADDR[0].x], IN[9].yyyy, TEMP[8]
 19:   UARL ADDR[0].x, TEMP[6].xxxx
 20:   MAD TEMP[6], CONST[ADDR[0].x], IN[9].zzzz, TEMP[7]
 21:   UARL ADDR[0].x, TEMP[5].xxxx
 22:   UARL ADDR[0].x, TEMP[5].xxxx
 23:   MAD TEMP[5], CONST[ADDR[0].x], TEMP[3].xxxx, TEMP[6]
 24:   UMAD TEMP[6].x, TEMP[4].wwww, IMM[1].xxxx, IMM[1].zzzz
 25:   UMAD TEMP[7].x, TEMP[4].zzzz, IMM[1].xxxx, IMM[1].zzzz
 26:   UMAD TEMP[8].x, TEMP[4].yyyy, IMM[1].xxxx, IMM[1].zzzz
 27:   UMAD TEMP[9].x, TEMP[4].xxxx, IMM[1].xxxx, IMM[1].zzzz
 28:   UARL ADDR[0].x, TEMP[9].xxxx
 29:   MUL TEMP[9], CONST[ADDR[0].x], IN[9].xxxx
 30:   UARL ADDR[0].x, TEMP[8].xxxx
 31:   MAD TEMP[8], CONST[ADDR[0].x], IN[9].yyyy, TEMP[9]
 32:   UARL ADDR[0].x, TEMP[7].xxxx
 33:   MAD TEMP[7], CONST[ADDR[0].x], IN[9].zzzz, TEMP[8]
 34:   UARL ADDR[0].x, TEMP[6].xxxx
 35:   UARL ADDR[0].x, TEMP[6].xxxx
 36:   MAD TEMP[6], CONST[ADDR[0].x], TEMP[3].xxxx, TEMP[7]
 37:   UMAD TEMP[7].x, TEMP[4].wwww, IMM[1].xxxx, IMM[1].wwww
 38:   UMAD TEMP[8].x, TEMP[4].zzzz, IMM[1].xxxx, IMM[1].wwww
 39:   UMAD TEMP[9].x, TEMP[4].yyyy, IMM[1].xxxx, IMM[1].wwww
 40:   UMAD TEMP[4].x, TEMP[4].xxxx, IMM[1].xxxx, IMM[1].wwww
 41:   UARL ADDR[0].x, TEMP[4].xxxx
 42:   MUL TEMP[4], CONST[ADDR[0].x], IN[9].xxxx
 43:   UARL ADDR[0].x, TEMP[9].xxxx
 44:   MAD TEMP[4], CONST[ADDR[0].x], IN[9].yyyy, TEMP[4]
 45:   UARL ADDR[0].x, TEMP[8].xxxx
 46:   MAD TEMP[4], CONST[ADDR[0].x], IN[9].zzzz, TEMP[4]
 47:   UARL ADDR[0].x, TEMP[7].xxxx
 48:   UARL ADDR[0].x, TEMP[7].xxxx
 49:   MAD TEMP[3], CONST[ADDR[0].x], TEMP[3].xxxx, TEMP[4]
 50:   DP4 TEMP[4].x, IN[0], TEMP[5]
 51:   DP4 TEMP[7].x, IN[0], TEMP[6]
 52:   MOV TEMP[4].y, TEMP[7].xxxx
 53:   DP4 TEMP[7].x, IN[0], TEMP[3]
 54:   MOV TEMP[4].z, TEMP[7].xxxx
 55:   MOV TEMP[0].xyz, TEMP[4].xyzx
 56:   DP3 TEMP[4].x, TEMP[1].xyzz, TEMP[5].xyzz
 57:   DP3 TEMP[5].x, TEMP[1].xyzz, TEMP[6].xyzz
 58:   MOV TEMP[4].y, TEMP[5].xxxx
 59:   DP3 TEMP[1].x, TEMP[1].xyzz, TEMP[3].xyzz
 60:   MOV TEMP[4].z, TEMP[1].xxxx
 61:   MOV TEMP[2].xyz, TEMP[4].xyzx
 62: ENDIF
 63: DP4 TEMP[1].x, TEMP[0], CONST[0]
 64: DP4 TEMP[3].x, TEMP[0], CONST[1]
 65: MOV TEMP[1].y, TEMP[3].xxxx
 66: DP4 TEMP[3].x, TEMP[0], CONST[2]
 67: MOV TEMP[1].z, TEMP[3].xxxx
 68: DP4 TEMP[3].x, TEMP[0], CONST[3]
 69: MOV TEMP[1].w, TEMP[3].xxxx
 70: DP4 TEMP[3].x, TEMP[0], CONST[4]
 71: DP4 TEMP[4].x, TEMP[0], CONST[5]
 72: MOV TEMP[3].y, TEMP[4].xxxx
 73: DP4 TEMP[0].x, TEMP[0], CONST[6]
 74: MOV TEMP[3].z, TEMP[0].xxxx
 75: MOV TEMP[0].xyz, TEMP[3].xyzx
 76: MOV TEMP[0].w, IMM[0].yyyy
 77: DP3 TEMP[4].x, CONST[4].xyzz, CONST[4].xyzz
 78: RCP TEMP[4].x, TEMP[4].xxxx
 79: MUL TEMP[4].xyz, CONST[4].xyzz, TEMP[4].xxxx
 80: DP3 TEMP[4].x, TEMP[2].xyzz, TEMP[4].xyzz
 81: DP3 TEMP[5].x, CONST[5].xyzz, CONST[5].xyzz
 82: RCP TEMP[5].x, TEMP[5].xxxx
 83: MUL TEMP[5].xyz, CONST[5].xyzz, TEMP[5].xxxx
 84: DP3 TEMP[5].x, TEMP[2].xyzz, TEMP[5].xyzz
 85: MOV TEMP[4].y, TEMP[5].xxxx
 86: DP3 TEMP[5].x, CONST[6].xyzz, CONST[6].xyzz
 87: RCP TEMP[5].x, TEMP[5].xxxx
 88: MUL TEMP[5].xyz, CONST[6].xyzz, TEMP[5].xxxx
 89: DP3 TEMP[2].x, TEMP[2].xyzz, TEMP[5].xyzz
 90: MOV TEMP[4].z, TEMP[2].xxxx
 91: DP3 TEMP[2].x, TEMP[4].xyzz, TEMP[4].xyzz
 92: RSQ TEMP[2].x, TEMP[2].xxxx
 93: MUL TEMP[2].xyz, TEMP[4].xyzz, TEMP[2].xxxx
 94: FSGE TEMP[5].x, CONST[31].zzzz, IMM[0].wwww
 95: UIF TEMP[5].xxxx :0
 96:   MOV TEMP[5].x, TEMP[3].xxxx
 97: ELSE :0
 98:   MOV TEMP[5].x, IN[5].xxxx
 99: ENDIF
100: FSGE TEMP[6].x, CONST[31].zzzz, IMM[0].wwww
101: UIF TEMP[6].xxxx :0
102:   MOV TEMP[6].x, TEMP[3].yyyy
103: ELSE :0
104:   MOV TEMP[6].x, IN[5].yyyy
105: ENDIF
106: FSGE TEMP[7].x, CONST[31].xxxx, IMM[0].wwww
107: UIF TEMP[7].xxxx :0
108:   MOV TEMP[7].x, TEMP[3].zzzz
109: ELSE :0
110:   MOV TEMP[7].x, TEMP[5].xxxx
111: ENDIF
112: MOV TEMP[4].x, TEMP[7].xxxx
113: FSGE TEMP[5].x, CONST[31].yyyy, IMM[0].wwww
114: UIF TEMP[5].xxxx :0
115:   MOV TEMP[5].x, TEMP[3].zzzz
116: ELSE :0
117:   MOV TEMP[5].x, TEMP[6].xxxx
118: ENDIF
119: MOV TEMP[4].y, TEMP[5].xxxx
120: MOV TEMP[5].zw, IMM[0].yywy
121: MOV TEMP[5].xy, TEMP[4].xyxx
122: FSGE TEMP[6].x, CONST[32].zzzz, IMM[0].wwww
123: UIF TEMP[6].xxxx :0
124:   MOV TEMP[6].x, TEMP[3].xxxx
125: ELSE :0
126:   MOV TEMP[6].x, IN[2].xxxx
127: ENDIF
128: FSGE TEMP[7].x, CONST[32].zzzz, IMM[0].wwww
129: UIF TEMP[7].xxxx :0
130:   MOV TEMP[7].x, TEMP[3].yyyy
131: ELSE :0
132:   MOV TEMP[7].x, IN[2].yyyy
133: ENDIF
134: FSGE TEMP[8].x, CONST[32].xxxx, IMM[0].wwww
135: UIF TEMP[8].xxxx :0
136:   MOV TEMP[8].x, TEMP[3].zzzz
137: ELSE :0
138:   MOV TEMP[8].x, TEMP[6].xxxx
139: ENDIF
140: MOV TEMP[4].x, TEMP[8].xxxx
141: FSGE TEMP[6].x, CONST[32].yyyy, IMM[0].wwww
142: UIF TEMP[6].xxxx :0
143:   MOV TEMP[6].x, TEMP[3].zzzz
144: ELSE :0
145:   MOV TEMP[6].x, TEMP[7].xxxx
146: ENDIF
147: MOV TEMP[4].y, TEMP[6].xxxx
148: MOV TEMP[6].zw, IMM[0].yywy
149: MOV TEMP[6].xy, TEMP[4].xyxx
150: FSGE TEMP[7].x, CONST[33].zzzz, IMM[0].wwww
151: UIF TEMP[7].xxxx :0
152:   MOV TEMP[7].x, TEMP[3].xxxx
153: ELSE :0
154:   MOV TEMP[7].x, IN[6].xxxx
155: ENDIF
156: FSGE TEMP[8].x, CONST[33].zzzz, IMM[0].wwww
157: UIF TEMP[8].xxxx :0
158:   MOV TEMP[8].x, TEMP[3].yyyy
159: ELSE :0
160:   MOV TEMP[8].x, IN[6].yyyy
161: ENDIF
162: FSGE TEMP[9].x, CONST[33].xxxx, IMM[0].wwww
163: UIF TEMP[9].xxxx :0
164:   MOV TEMP[9].x, TEMP[3].zzzz
165: ELSE :0
166:   MOV TEMP[9].x, TEMP[7].xxxx
167: ENDIF
168: MOV TEMP[4].x, TEMP[9].xxxx
169: FSGE TEMP[7].x, CONST[33].yyyy, IMM[0].wwww
170: UIF TEMP[7].xxxx :0
171:   MOV TEMP[7].x, TEMP[3].zzzz
172: ELSE :0
173:   MOV TEMP[7].x, TEMP[8].xxxx
174: ENDIF
175: MOV TEMP[4].y, TEMP[7].xxxx
176: MOV TEMP[7].zw, IMM[0].yywy
177: MOV TEMP[7].xy, TEMP[4].xyxx
178: FSGE TEMP[8].x, CONST[34].zzzz, IMM[0].wwww
179: UIF TEMP[8].xxxx :0
180:   MOV TEMP[8].x, TEMP[3].xxxx
181: ELSE :0
182:   MOV TEMP[8].x, IN[3].xxxx
183: ENDIF
184: FSGE TEMP[9].x, CONST[34].zzzz, IMM[0].wwww
185: UIF TEMP[9].xxxx :0
186:   MOV TEMP[9].x, TEMP[3].yyyy
187: ELSE :0
188:   MOV TEMP[9].x, IN[3].yyyy
189: ENDIF
190: FSGE TEMP[10].x, CONST[34].xxxx, IMM[0].wwww
191: UIF TEMP[10].xxxx :0
192:   MOV TEMP[10].x, TEMP[3].zzzz
193: ELSE :0
194:   MOV TEMP[10].x, TEMP[8].xxxx
195: ENDIF
196: MOV TEMP[4].x, TEMP[10].xxxx
197: FSGE TEMP[8].x, CONST[34].yyyy, IMM[0].wwww
198: UIF TEMP[8].xxxx :0
199:   MOV TEMP[3].x, TEMP[3].zzzz
200: ELSE :0
201:   MOV TEMP[3].x, TEMP[9].xxxx
202: ENDIF
203: MOV TEMP[4].y, TEMP[3].xxxx
204: MOV TEMP[3].zw, IMM[0].yywy
205: MOV TEMP[3].xy, TEMP[4].xyxx
206: MAD TEMP[4].xy, IN[4].xyyy, CONST[29].xyyy, CONST[29].zwww
207: DP4 TEMP[8].x, TEMP[5], CONST[27]
208: DP4 TEMP[5].x, TEMP[5], CONST[28]
209: MOV TEMP[8].y, TEMP[5].xxxx
210: MOV TEMP[4].zw, TEMP[8].yyxy
211: DP4 TEMP[5].x, TEMP[6], CONST[7]
212: DP4 TEMP[6].x, TEMP[6], CONST[8]
213: MOV TEMP[5].y, TEMP[6].xxxx
214: MOV TEMP[5].xy, TEMP[5].xyxx
215: DP4 TEMP[6].x, TEMP[7], CONST[25]
216: DP4 TEMP[7].x, TEMP[7], CONST[26]
217: MOV TEMP[6].y, TEMP[7].xxxx
218: MOV TEMP[5].zw, TEMP[6].yyxy
219: DP4 TEMP[6].x, TEMP[3], CONST[23]
220: DP4 TEMP[3].x, TEMP[3], CONST[24]
221: MOV TEMP[6].y, TEMP[3].xxxx
222: MOV TEMP[3].xy, TEMP[6].xyxx
223: MOV TEMP[3].zw, IMM[0].wwww
224: MAD TEMP[6], IN[7].zyxw, CONST[30].xxxy, CONST[30].zzzz
225: MOV TEMP[7].w, TEMP[6].wwww
226: MUL TEMP[7].xyz, TEMP[6].xyzz, TEMP[6].xyzz
227: MOV TEMP[2].xyz, TEMP[2].xyzx
228: MOV TEMP[2].w, IMM[0].wwww
229: MOV TEMP[6].xy, IMM[0].wwww
230: MOV OUT[3], TEMP[5]
231: MOV OUT[7], TEMP[2]
232: MOV OUT[2], TEMP[0]
233: MOV OUT[4], TEMP[4]
234: MOV OUT[0], TEMP[1]
235: MOV OUT[8], TEMP[6]
236: MOV OUT[6], TEMP[7]
237: MOV OUT[1], TEMP[1]
238: MOV OUT[5], TEMP[3]
239: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0)
  %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4)
  %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8)
  %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12)
  %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16)
  %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20)
  %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24)
  %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28)
  %20 = call float @llvm.SI.load.const(<16 x i8> %11, i32 32)
  %21 = call float @llvm.SI.load.const(<16 x i8> %11, i32 36)
  %22 = call float @llvm.SI.load.const(<16 x i8> %11, i32 40)
  %23 = call float @llvm.SI.load.const(<16 x i8> %11, i32 44)
  %24 = call float @llvm.SI.load.const(<16 x i8> %11, i32 48)
  %25 = call float @llvm.SI.load.const(<16 x i8> %11, i32 52)
  %26 = call float @llvm.SI.load.const(<16 x i8> %11, i32 56)
  %27 = call float @llvm.SI.load.const(<16 x i8> %11, i32 60)
  %28 = call float @llvm.SI.load.const(<16 x i8> %11, i32 64)
  %29 = call float @llvm.SI.load.const(<16 x i8> %11, i32 68)
  %30 = call float @llvm.SI.load.const(<16 x i8> %11, i32 72)
  %31 = call float @llvm.SI.load.const(<16 x i8> %11, i32 76)
  %32 = call float @llvm.SI.load.const(<16 x i8> %11, i32 80)
  %33 = call float @llvm.SI.load.const(<16 x i8> %11, i32 84)
  %34 = call float @llvm.SI.load.const(<16 x i8> %11, i32 88)
  %35 = call float @llvm.SI.load.const(<16 x i8> %11, i32 92)
  %36 = call float @llvm.SI.load.const(<16 x i8> %11, i32 96)
  %37 = call float @llvm.SI.load.const(<16 x i8> %11, i32 100)
  %38 = call float @llvm.SI.load.const(<16 x i8> %11, i32 104)
  %39 = call float @llvm.SI.load.const(<16 x i8> %11, i32 108)
  %40 = call float @llvm.SI.load.const(<16 x i8> %11, i32 112)
  %41 = call float @llvm.SI.load.const(<16 x i8> %11, i32 116)
  %42 = call float @llvm.SI.load.const(<16 x i8> %11, i32 120)
  %43 = call float @llvm.SI.load.const(<16 x i8> %11, i32 124)
  %44 = call float @llvm.SI.load.const(<16 x i8> %11, i32 128)
  %45 = call float @llvm.SI.load.const(<16 x i8> %11, i32 132)
  %46 = call float @llvm.SI.load.const(<16 x i8> %11, i32 136)
  %47 = call float @llvm.SI.load.const(<16 x i8> %11, i32 140)
  %48 = call float @llvm.SI.load.const(<16 x i8> %11, i32 368)
  %49 = call float @llvm.SI.load.const(<16 x i8> %11, i32 372)
  %50 = call float @llvm.SI.load.const(<16 x i8> %11, i32 376)
  %51 = call float @llvm.SI.load.const(<16 x i8> %11, i32 380)
  %52 = call float @llvm.SI.load.const(<16 x i8> %11, i32 384)
  %53 = call float @llvm.SI.load.const(<16 x i8> %11, i32 388)
  %54 = call float @llvm.SI.load.const(<16 x i8> %11, i32 392)
  %55 = call float @llvm.SI.load.const(<16 x i8> %11, i32 396)
  %56 = call float @llvm.SI.load.const(<16 x i8> %11, i32 400)
  %57 = call float @llvm.SI.load.const(<16 x i8> %11, i32 404)
  %58 = call float @llvm.SI.load.const(<16 x i8> %11, i32 408)
  %59 = call float @llvm.SI.load.const(<16 x i8> %11, i32 412)
  %60 = call float @llvm.SI.load.const(<16 x i8> %11, i32 416)
  %61 = call float @llvm.SI.load.const(<16 x i8> %11, i32 420)
  %62 = call float @llvm.SI.load.const(<16 x i8> %11, i32 424)
  %63 = call float @llvm.SI.load.const(<16 x i8> %11, i32 428)
  %64 = call float @llvm.SI.load.const(<16 x i8> %11, i32 432)
  %65 = call float @llvm.SI.load.const(<16 x i8> %11, i32 436)
  %66 = call float @llvm.SI.load.const(<16 x i8> %11, i32 440)
  %67 = call float @llvm.SI.load.const(<16 x i8> %11, i32 444)
  %68 = call float @llvm.SI.load.const(<16 x i8> %11, i32 448)
  %69 = call float @llvm.SI.load.const(<16 x i8> %11, i32 452)
  %70 = call float @llvm.SI.load.const(<16 x i8> %11, i32 456)
  %71 = call float @llvm.SI.load.const(<16 x i8> %11, i32 460)
  %72 = call float @llvm.SI.load.const(<16 x i8> %11, i32 464)
  %73 = call float @llvm.SI.load.const(<16 x i8> %11, i32 468)
  %74 = call float @llvm.SI.load.const(<16 x i8> %11, i32 472)
  %75 = call float @llvm.SI.load.const(<16 x i8> %11, i32 476)
  %76 = call float @llvm.SI.load.const(<16 x i8> %11, i32 480)
  %77 = call float @llvm.SI.load.const(<16 x i8> %11, i32 484)
  %78 = call float @llvm.SI.load.const(<16 x i8> %11, i32 488)
  %79 = call float @llvm.SI.load.const(<16 x i8> %11, i32 496)
  %80 = call float @llvm.SI.load.const(<16 x i8> %11, i32 500)
  %81 = call float @llvm.SI.load.const(<16 x i8> %11, i32 504)
  %82 = call float @llvm.SI.load.const(<16 x i8> %11, i32 512)
  %83 = call float @llvm.SI.load.const(<16 x i8> %11, i32 516)
  %84 = call float @llvm.SI.load.const(<16 x i8> %11, i32 520)
  %85 = call float @llvm.SI.load.const(<16 x i8> %11, i32 528)
  %86 = call float @llvm.SI.load.const(<16 x i8> %11, i32 532)
  %87 = call float @llvm.SI.load.const(<16 x i8> %11, i32 536)
  %88 = call float @llvm.SI.load.const(<16 x i8> %11, i32 544)
  %89 = call float @llvm.SI.load.const(<16 x i8> %11, i32 548)
  %90 = call float @llvm.SI.load.const(<16 x i8> %11, i32 552)
  %91 = call float @llvm.SI.load.const(<16 x i8> %11, i32 576)
  %92 = call float @llvm.SI.load.const(<16 x i8> %11, i32 580)
  %93 = call float @llvm.SI.load.const(<16 x i8> %11, i32 584)
  %94 = call float @llvm.SI.load.const(<16 x i8> %11, i32 3840)
  %95 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0
  %96 = load <16 x i8> addrspace(2)* %95, !tbaa !0
  %97 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %96, i32 0, i32 %6)
  %98 = extractelement <4 x float> %97, i32 0
  %99 = extractelement <4 x float> %97, i32 1
  %100 = extractelement <4 x float> %97, i32 2
  %101 = extractelement <4 x float> %97, i32 3
  %102 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 1
  %103 = load <16 x i8> addrspace(2)* %102, !tbaa !0
  %104 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %103, i32 0, i32 %6)
  %105 = extractelement <4 x float> %104, i32 0
  %106 = extractelement <4 x float> %104, i32 1
  %107 = extractelement <4 x float> %104, i32 2
  %108 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 2
  %109 = load <16 x i8> addrspace(2)* %108, !tbaa !0
  %110 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %109, i32 0, i32 %6)
  %111 = extractelement <4 x float> %110, i32 0
  %112 = extractelement <4 x float> %110, i32 1
  %113 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 3
  %114 = load <16 x i8> addrspace(2)* %113, !tbaa !0
  %115 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %114, i32 0, i32 %6)
  %116 = extractelement <4 x float> %115, i32 0
  %117 = extractelement <4 x float> %115, i32 1
  %118 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 4
  %119 = load <16 x i8> addrspace(2)* %118, !tbaa !0
  %120 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %119, i32 0, i32 %6)
  %121 = extractelement <4 x float> %120, i32 0
  %122 = extractelement <4 x float> %120, i32 1
  %123 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 5
  %124 = load <16 x i8> addrspace(2)* %123, !tbaa !0
  %125 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %124, i32 0, i32 %6)
  %126 = extractelement <4 x float> %125, i32 0
  %127 = extractelement <4 x float> %125, i32 1
  %128 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 6
  %129 = load <16 x i8> addrspace(2)* %128, !tbaa !0
  %130 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %129, i32 0, i32 %6)
  %131 = extractelement <4 x float> %130, i32 0
  %132 = extractelement <4 x float> %130, i32 1
  %133 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 7
  %134 = load <16 x i8> addrspace(2)* %133, !tbaa !0
  %135 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %134, i32 0, i32 %6)
  %136 = extractelement <4 x float> %135, i32 0
  %137 = extractelement <4 x float> %135, i32 1
  %138 = extractelement <4 x float> %135, i32 2
  %139 = extractelement <4 x float> %135, i32 3
  %140 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 8
  %141 = load <16 x i8> addrspace(2)* %140, !tbaa !0
  %142 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %141, i32 0, i32 %6)
  %143 = extractelement <4 x float> %142, i32 0
  %144 = extractelement <4 x float> %142, i32 1
  %145 = extractelement <4 x float> %142, i32 2
  %146 = extractelement <4 x float> %142, i32 3
  %147 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 9
  %148 = load <16 x i8> addrspace(2)* %147, !tbaa !0
  %149 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %148, i32 0, i32 %6)
  %150 = extractelement <4 x float> %149, i32 0
  %151 = extractelement <4 x float> %149, i32 1
  %152 = extractelement <4 x float> %149, i32 2
  %153 = fmul float %105, %93
  %154 = fadd float %153, %91
  %155 = fmul float %106, %93
  %156 = fadd float %155, %92
  %157 = fmul float %107, %93
  %158 = fadd float %157, %91
  %159 = fadd float %156, 0x3F50624DE0000000
  %160 = bitcast float %94 to i32
  %161 = icmp ne i32 %160, 0
  br i1 %161, label %IF, label %ENDIF

IF:                                               ; preds = %main_body
  %162 = fmul float %150, 1.000000e+00
  %163 = fmul float %151, 1.000000e+00
  %164 = fadd float %163, %162
  %165 = fmul float %152, 1.000000e+00
  %166 = fadd float %164, %165
  %167 = fsub float -0.000000e+00, %166
  %168 = fadd float 1.000000e+00, %167
  %169 = fmul float %143, 0x406FE051E0000000
  %170 = fmul float %144, 0x406FE051E0000000
  %171 = fmul float %145, 0x406FE051E0000000
  %172 = fmul float %146, 0x406FE051E0000000
  %173 = fptosi float %169 to i32
  %174 = fptosi float %170 to i32
  %175 = fptosi float %171 to i32
  %176 = fptosi float %172 to i32
  %177 = bitcast i32 %173 to float
  %178 = bitcast i32 %174 to float
  %179 = bitcast i32 %175 to float
  %180 = bitcast i32 %176 to float
  %181 = bitcast float %180 to i32
  %182 = mul i32 %181, 3
  %183 = add i32 %182, 41
  %184 = bitcast i32 %183 to float
  %185 = bitcast float %179 to i32
  %186 = mul i32 %185, 3
  %187 = add i32 %186, 41
  %188 = bitcast i32 %187 to float
  %189 = bitcast float %178 to i32
  %190 = mul i32 %189, 3
  %191 = add i32 %190, 41
  %192 = bitcast i32 %191 to float
  %193 = bitcast float %177 to i32
  %194 = mul i32 %193, 3
  %195 = add i32 %194, 41
  %196 = bitcast i32 %195 to float
  %197 = bitcast float %196 to i32
  %198 = shl i32 %197, 4
  %199 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %198)
  %200 = fmul float %199, %150
  %201 = shl i32 %197, 4
  %202 = add i32 %201, 4
  %203 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %202)
  %204 = fmul float %203, %150
  %205 = shl i32 %197, 4
  %206 = add i32 %205, 8
  %207 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %206)
  %208 = fmul float %207, %150
  %209 = shl i32 %197, 4
  %210 = add i32 %209, 12
  %211 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %210)
  %212 = fmul float %211, %150
  %213 = bitcast float %192 to i32
  %214 = shl i32 %213, 4
  %215 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %214)
  %216 = fmul float %215, %151
  %217 = fadd float %216, %200
  %218 = shl i32 %213, 4
  %219 = add i32 %218, 4
  %220 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %219)
  %221 = fmul float %220, %151
  %222 = fadd float %221, %204
  %223 = shl i32 %213, 4
  %224 = add i32 %223, 8
  %225 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %224)
  %226 = fmul float %225, %151
  %227 = fadd float %226, %208
  %228 = shl i32 %213, 4
  %229 = add i32 %228, 12
  %230 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %229)
  %231 = fmul float %230, %151
  %232 = fadd float %231, %212
  %233 = bitcast float %188 to i32
  %234 = shl i32 %233, 4
  %235 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %234)
  %236 = fmul float %235, %152
  %237 = fadd float %236, %217
  %238 = shl i32 %233, 4
  %239 = add i32 %238, 4
  %240 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %239)
  %241 = fmul float %240, %152
  %242 = fadd float %241, %222
  %243 = shl i32 %233, 4
  %244 = add i32 %243, 8
  %245 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %244)
  %246 = fmul float %245, %152
  %247 = fadd float %246, %227
  %248 = shl i32 %233, 4
  %249 = add i32 %248, 12
  %250 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %249)
  %251 = fmul float %250, %152
  %252 = fadd float %251, %232
  %253 = bitcast float %184 to i32
  %254 = shl i32 %253, 4
  %255 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %254)
  %256 = fmul float %255, %168
  %257 = fadd float %256, %237
  %258 = shl i32 %253, 4
  %259 = add i32 %258, 4
  %260 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %259)
  %261 = fmul float %260, %168
  %262 = fadd float %261, %242
  %263 = shl i32 %253, 4
  %264 = add i32 %263, 8
  %265 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %264)
  %266 = fmul float %265, %168
  %267 = fadd float %266, %247
  %268 = shl i32 %253, 4
  %269 = add i32 %268, 12
  %270 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %269)
  %271 = fmul float %270, %168
  %272 = fadd float %271, %252
  %273 = bitcast float %180 to i32
  %274 = mul i32 %273, 3
  %275 = add i32 %274, 42
  %276 = bitcast i32 %275 to float
  %277 = bitcast float %179 to i32
  %278 = mul i32 %277, 3
  %279 = add i32 %278, 42
  %280 = bitcast i32 %279 to float
  %281 = bitcast float %178 to i32
  %282 = mul i32 %281, 3
  %283 = add i32 %282, 42
  %284 = bitcast i32 %283 to float
  %285 = bitcast float %177 to i32
  %286 = mul i32 %285, 3
  %287 = add i32 %286, 42
  %288 = bitcast i32 %287 to float
  %289 = bitcast float %288 to i32
  %290 = shl i32 %289, 4
  %291 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %290)
  %292 = fmul float %291, %150
  %293 = shl i32 %289, 4
  %294 = add i32 %293, 4
  %295 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %294)
  %296 = fmul float %295, %150
  %297 = shl i32 %289, 4
  %298 = add i32 %297, 8
  %299 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %298)
  %300 = fmul float %299, %150
  %301 = shl i32 %289, 4
  %302 = add i32 %301, 12
  %303 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %302)
  %304 = fmul float %303, %150
  %305 = bitcast float %284 to i32
  %306 = shl i32 %305, 4
  %307 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %306)
  %308 = fmul float %307, %151
  %309 = fadd float %308, %292
  %310 = shl i32 %305, 4
  %311 = add i32 %310, 4
  %312 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %311)
  %313 = fmul float %312, %151
  %314 = fadd float %313, %296
  %315 = shl i32 %305, 4
  %316 = add i32 %315, 8
  %317 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %316)
  %318 = fmul float %317, %151
  %319 = fadd float %318, %300
  %320 = shl i32 %305, 4
  %321 = add i32 %320, 12
  %322 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %321)
  %323 = fmul float %322, %151
  %324 = fadd float %323, %304
  %325 = bitcast float %280 to i32
  %326 = shl i32 %325, 4
  %327 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %326)
  %328 = fmul float %327, %152
  %329 = fadd float %328, %309
  %330 = shl i32 %325, 4
  %331 = add i32 %330, 4
  %332 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %331)
  %333 = fmul float %332, %152
  %334 = fadd float %333, %314
  %335 = shl i32 %325, 4
  %336 = add i32 %335, 8
  %337 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %336)
  %338 = fmul float %337, %152
  %339 = fadd float %338, %319
  %340 = shl i32 %325, 4
  %341 = add i32 %340, 12
  %342 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %341)
  %343 = fmul float %342, %152
  %344 = fadd float %343, %324
  %345 = bitcast float %276 to i32
  %346 = shl i32 %345, 4
  %347 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %346)
  %348 = fmul float %347, %168
  %349 = fadd float %348, %329
  %350 = shl i32 %345, 4
  %351 = add i32 %350, 4
  %352 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %351)
  %353 = fmul float %352, %168
  %354 = fadd float %353, %334
  %355 = shl i32 %345, 4
  %356 = add i32 %355, 8
  %357 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %356)
  %358 = fmul float %357, %168
  %359 = fadd float %358, %339
  %360 = shl i32 %345, 4
  %361 = add i32 %360, 12
  %362 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %361)
  %363 = fmul float %362, %168
  %364 = fadd float %363, %344
  %365 = bitcast float %180 to i32
  %366 = mul i32 %365, 3
  %367 = add i32 %366, 43
  %368 = bitcast i32 %367 to float
  %369 = bitcast float %179 to i32
  %370 = mul i32 %369, 3
  %371 = add i32 %370, 43
  %372 = bitcast i32 %371 to float
  %373 = bitcast float %178 to i32
  %374 = mul i32 %373, 3
  %375 = add i32 %374, 43
  %376 = bitcast i32 %375 to float
  %377 = bitcast float %177 to i32
  %378 = mul i32 %377, 3
  %379 = add i32 %378, 43
  %380 = bitcast i32 %379 to float
  %381 = bitcast float %380 to i32
  %382 = shl i32 %381, 4
  %383 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %382)
  %384 = fmul float %383, %150
  %385 = shl i32 %381, 4
  %386 = add i32 %385, 4
  %387 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %386)
  %388 = fmul float %387, %150
  %389 = shl i32 %381, 4
  %390 = add i32 %389, 8
  %391 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %390)
  %392 = fmul float %391, %150
  %393 = shl i32 %381, 4
  %394 = add i32 %393, 12
  %395 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %394)
  %396 = fmul float %395, %150
  %397 = bitcast float %376 to i32
  %398 = shl i32 %397, 4
  %399 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %398)
  %400 = fmul float %399, %151
  %401 = fadd float %400, %384
  %402 = shl i32 %397, 4
  %403 = add i32 %402, 4
  %404 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %403)
  %405 = fmul float %404, %151
  %406 = fadd float %405, %388
  %407 = shl i32 %397, 4
  %408 = add i32 %407, 8
  %409 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %408)
  %410 = fmul float %409, %151
  %411 = fadd float %410, %392
  %412 = shl i32 %397, 4
  %413 = add i32 %412, 12
  %414 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %413)
  %415 = fmul float %414, %151
  %416 = fadd float %415, %396
  %417 = bitcast float %372 to i32
  %418 = shl i32 %417, 4
  %419 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %418)
  %420 = fmul float %419, %152
  %421 = fadd float %420, %401
  %422 = shl i32 %417, 4
  %423 = add i32 %422, 4
  %424 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %423)
  %425 = fmul float %424, %152
  %426 = fadd float %425, %406
  %427 = shl i32 %417, 4
  %428 = add i32 %427, 8
  %429 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %428)
  %430 = fmul float %429, %152
  %431 = fadd float %430, %411
  %432 = shl i32 %417, 4
  %433 = add i32 %432, 12
  %434 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %433)
  %435 = fmul float %434, %152
  %436 = fadd float %435, %416
  %437 = bitcast float %368 to i32
  %438 = shl i32 %437, 4
  %439 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %438)
  %440 = fmul float %439, %168
  %441 = fadd float %440, %421
  %442 = shl i32 %437, 4
  %443 = add i32 %442, 4
  %444 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %443)
  %445 = fmul float %444, %168
  %446 = fadd float %445, %426
  %447 = shl i32 %437, 4
  %448 = add i32 %447, 8
  %449 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %448)
  %450 = fmul float %449, %168
  %451 = fadd float %450, %431
  %452 = shl i32 %437, 4
  %453 = add i32 %452, 12
  %454 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %453)
  %455 = fmul float %454, %168
  %456 = fadd float %455, %436
  %457 = fmul float %98, %257
  %458 = fmul float %99, %262
  %459 = fadd float %457, %458
  %460 = fmul float %100, %267
  %461 = fadd float %459, %460
  %462 = fmul float %101, %272
  %463 = fadd float %461, %462
  %464 = fmul float %98, %349
  %465 = fmul float %99, %354
  %466 = fadd float %464, %465
  %467 = fmul float %100, %359
  %468 = fadd float %466, %467
  %469 = fmul float %101, %364
  %470 = fadd float %468, %469
  %471 = fmul float %98, %441
  %472 = fmul float %99, %446
  %473 = fadd float %471, %472
  %474 = fmul float %100, %451
  %475 = fadd float %473, %474
  %476 = fmul float %101, %456
  %477 = fadd float %475, %476
  %478 = fmul float %154, %257
  %479 = fmul float %159, %262
  %480 = fadd float %479, %478
  %481 = fmul float %158, %267
  %482 = fadd float %480, %481
  %483 = fmul float %154, %349
  %484 = fmul float %159, %354
  %485 = fadd float %484, %483
  %486 = fmul float %158, %359
  %487 = fadd float %485, %486
  %488 = fmul float %154, %441
  %489 = fmul float %159, %446
  %490 = fadd float %489, %488
  %491 = fmul float %158, %451
  %492 = fadd float %490, %491
  br label %ENDIF

ENDIF:                                            ; preds = %main_body, %IF
  %temp.0 = phi float [ %463, %IF ], [ %98, %main_body ]
  %temp1.0 = phi float [ %470, %IF ], [ %99, %main_body ]
  %temp2.0 = phi float [ %477, %IF ], [ %100, %main_body ]
  %temp8.0 = phi float [ %482, %IF ], [ %154, %main_body ]
  %temp9.0 = phi float [ %487, %IF ], [ %159, %main_body ]
  %temp10.0 = phi float [ %492, %IF ], [ %158, %main_body ]
  %493 = fmul float %temp.0, %12
  %494 = fmul float %temp1.0, %13
  %495 = fadd float %493, %494
  %496 = fmul float %temp2.0, %14
  %497 = fadd float %495, %496
  %498 = fmul float %101, %15
  %499 = fadd float %497, %498
  %500 = fmul float %temp.0, %16
  %501 = fmul float %temp1.0, %17
  %502 = fadd float %500, %501
  %503 = fmul float %temp2.0, %18
  %504 = fadd float %502, %503
  %505 = fmul float %101, %19
  %506 = fadd float %504, %505
  %507 = fmul float %temp.0, %20
  %508 = fmul float %temp1.0, %21
  %509 = fadd float %507, %508
  %510 = fmul float %temp2.0, %22
  %511 = fadd float %509, %510
  %512 = fmul float %101, %23
  %513 = fadd float %511, %512
  %514 = fmul float %temp.0, %24
  %515 = fmul float %temp1.0, %25
  %516 = fadd float %514, %515
  %517 = fmul float %temp2.0, %26
  %518 = fadd float %516, %517
  %519 = fmul float %101, %27
  %520 = fadd float %518, %519
  %521 = fmul float %temp.0, %28
  %522 = fmul float %temp1.0, %29
  %523 = fadd float %521, %522
  %524 = fmul float %temp2.0, %30
  %525 = fadd float %523, %524
  %526 = fmul float %101, %31
  %527 = fadd float %525, %526
  %528 = fmul float %temp.0, %32
  %529 = fmul float %temp1.0, %33
  %530 = fadd float %528, %529
  %531 = fmul float %temp2.0, %34
  %532 = fadd float %530, %531
  %533 = fmul float %101, %35
  %534 = fadd float %532, %533
  %535 = fmul float %temp.0, %36
  %536 = fmul float %temp1.0, %37
  %537 = fadd float %535, %536
  %538 = fmul float %temp2.0, %38
  %539 = fadd float %537, %538
  %540 = fmul float %101, %39
  %541 = fadd float %539, %540
  %542 = fmul float %28, %28
  %543 = fmul float %29, %29
  %544 = fadd float %543, %542
  %545 = fmul float %30, %30
  %546 = fadd float %544, %545
  %547 = fdiv float 1.000000e+00, %546
  %548 = fmul float %28, %547
  %549 = fmul float %29, %547
  %550 = fmul float %30, %547
  %551 = fmul float %temp8.0, %548
  %552 = fmul float %temp9.0, %549
  %553 = fadd float %552, %551
  %554 = fmul float %temp10.0, %550
  %555 = fadd float %553, %554
  %556 = fmul float %32, %32
  %557 = fmul float %33, %33
  %558 = fadd float %557, %556
  %559 = fmul float %34, %34
  %560 = fadd float %558, %559
  %561 = fdiv float 1.000000e+00, %560
  %562 = fmul float %32, %561
  %563 = fmul float %33, %561
  %564 = fmul float %34, %561
  %565 = fmul float %temp8.0, %562
  %566 = fmul float %temp9.0, %563
  %567 = fadd float %566, %565
  %568 = fmul float %temp10.0, %564
  %569 = fadd float %567, %568
  %570 = fmul float %36, %36
  %571 = fmul float %37, %37
  %572 = fadd float %571, %570
  %573 = fmul float %38, %38
  %574 = fadd float %572, %573
  %575 = fdiv float 1.000000e+00, %574
  %576 = fmul float %36, %575
  %577 = fmul float %37, %575
  %578 = fmul float %38, %575
  %579 = fmul float %temp8.0, %576
  %580 = fmul float %temp9.0, %577
  %581 = fadd float %580, %579
  %582 = fmul float %temp10.0, %578
  %583 = fadd float %581, %582
  %584 = fmul float %555, %555
  %585 = fmul float %569, %569
  %586 = fadd float %585, %584
  %587 = fmul float %583, %583
  %588 = fadd float %586, %587
  %589 = call float @llvm.AMDGPU.rsq(float %588)
  %590 = fmul float %555, %589
  %591 = fmul float %569, %589
  %592 = fmul float %583, %589
  %593 = fcmp oge float %81, 0.000000e+00
  %594 = sext i1 %593 to i32
  %595 = bitcast i32 %594 to float
  %596 = bitcast float %595 to i32
  %597 = icmp ne i32 %596, 0
  %. = select i1 %597, float %527, float %126
  %598 = fcmp oge float %81, 0.000000e+00
  %599 = sext i1 %598 to i32
  %600 = bitcast i32 %599 to float
  %601 = bitcast float %600 to i32
  %602 = icmp ne i32 %601, 0
  %temp24.0 = select i1 %602, float %534, float %127
  %603 = fcmp oge float %79, 0.000000e+00
  %604 = sext i1 %603 to i32
  %605 = bitcast i32 %604 to float
  %606 = bitcast float %605 to i32
  %607 = icmp ne i32 %606, 0
  %.. = select i1 %607, float %541, float %.
  %608 = fcmp oge float %80, 0.000000e+00
  %609 = sext i1 %608 to i32
  %610 = bitcast i32 %609 to float
  %611 = bitcast float %610 to i32
  %612 = icmp ne i32 %611, 0
  %temp20.1 = select i1 %612, float %541, float %temp24.0
  %613 = fcmp oge float %84, 0.000000e+00
  %614 = sext i1 %613 to i32
  %615 = bitcast i32 %614 to float
  %616 = bitcast float %615 to i32
  %617 = icmp ne i32 %616, 0
  %.139 = select i1 %617, float %527, float %111
  %618 = fcmp oge float %84, 0.000000e+00
  %619 = sext i1 %618 to i32
  %620 = bitcast i32 %619 to float
  %621 = bitcast float %620 to i32
  %622 = icmp ne i32 %621, 0
  %temp28.1 = select i1 %622, float %534, float %112
  %623 = fcmp oge float %82, 0.000000e+00
  %624 = sext i1 %623 to i32
  %625 = bitcast i32 %624 to float
  %626 = bitcast float %625 to i32
  %627 = icmp ne i32 %626, 0
  %..139 = select i1 %627, float %541, float %.139
  %628 = fcmp oge float %83, 0.000000e+00
  %629 = sext i1 %628 to i32
  %630 = bitcast i32 %629 to float
  %631 = bitcast float %630 to i32
  %632 = icmp ne i32 %631, 0
  %temp24.2 = select i1 %632, float %541, float %temp28.1
  %633 = fcmp oge float %87, 0.000000e+00
  %634 = sext i1 %633 to i32
  %635 = bitcast i32 %634 to float
  %636 = bitcast float %635 to i32
  %637 = icmp ne i32 %636, 0
  %.140 = select i1 %637, float %527, float %131
  %638 = fcmp oge float %87, 0.000000e+00
  %639 = sext i1 %638 to i32
  %640 = bitcast i32 %639 to float
  %641 = bitcast float %640 to i32
  %642 = icmp ne i32 %641, 0
  %temp32.1 = select i1 %642, float %534, float %132
  %643 = fcmp oge float %85, 0.000000e+00
  %644 = sext i1 %643 to i32
  %645 = bitcast i32 %644 to float
  %646 = bitcast float %645 to i32
  %647 = icmp ne i32 %646, 0
  %..140 = select i1 %647, float %541, float %.140
  %648 = fcmp oge float %86, 0.000000e+00
  %649 = sext i1 %648 to i32
  %650 = bitcast i32 %649 to float
  %651 = bitcast float %650 to i32
  %652 = icmp ne i32 %651, 0
  %temp28.3 = select i1 %652, float %541, float %temp32.1
  %653 = fcmp oge float %90, 0.000000e+00
  %654 = sext i1 %653 to i32
  %655 = bitcast i32 %654 to float
  %656 = bitcast float %655 to i32
  %657 = icmp ne i32 %656, 0
  %.141 = select i1 %657, float %527, float %116
  %658 = fcmp oge float %90, 0.000000e+00
  %659 = sext i1 %658 to i32
  %660 = bitcast i32 %659 to float
  %661 = bitcast float %660 to i32
  %662 = icmp ne i32 %661, 0
  %temp36.1 = select i1 %662, float %534, float %117
  %663 = fcmp oge float %88, 0.000000e+00
  %664 = sext i1 %663 to i32
  %665 = bitcast i32 %664 to float
  %666 = bitcast float %665 to i32
  %667 = icmp ne i32 %666, 0
  %..141 = select i1 %667, float %541, float %.141
  %668 = fcmp oge float %89, 0.000000e+00
  %669 = sext i1 %668 to i32
  %670 = bitcast i32 %669 to float
  %671 = bitcast float %670 to i32
  %672 = icmp ne i32 %671, 0
  %temp12.0 = select i1 %672, float %541, float %temp36.1
  %673 = fmul float %121, %72
  %674 = fadd float %673, %74
  %675 = fmul float %122, %73
  %676 = fadd float %675, %75
  %677 = fmul float %.., %64
  %678 = fmul float %temp20.1, %65
  %679 = fadd float %677, %678
  %680 = fmul float 0.000000e+00, %66
  %681 = fadd float %679, %680
  %682 = fmul float 1.000000e+00, %67
  %683 = fadd float %681, %682
  %684 = fmul float %.., %68
  %685 = fmul float %temp20.1, %69
  %686 = fadd float %684, %685
  %687 = fmul float 0.000000e+00, %70
  %688 = fadd float %686, %687
  %689 = fmul float 1.000000e+00, %71
  %690 = fadd float %688, %689
  %691 = fmul float %..139, %40
  %692 = fmul float %temp24.2, %41
  %693 = fadd float %691, %692
  %694 = fmul float 0.000000e+00, %42
  %695 = fadd float %693, %694
  %696 = fmul float 1.000000e+00, %43
  %697 = fadd float %695, %696
  %698 = fmul float %..139, %44
  %699 = fmul float %temp24.2, %45
  %700 = fadd float %698, %699
  %701 = fmul float 0.000000e+00, %46
  %702 = fadd float %700, %701
  %703 = fmul float 1.000000e+00, %47
  %704 = fadd float %702, %703
  %705 = fmul float %..140, %56
  %706 = fmul float %temp28.3, %57
  %707 = fadd float %705, %706
  %708 = fmul float 0.000000e+00, %58
  %709 = fadd float %707, %708
  %710 = fmul float 1.000000e+00, %59
  %711 = fadd float %709, %710
  %712 = fmul float %..140, %60
  %713 = fmul float %temp28.3, %61
  %714 = fadd float %712, %713
  %715 = fmul float 0.000000e+00, %62
  %716 = fadd float %714, %715
  %717 = fmul float 1.000000e+00, %63
  %718 = fadd float %716, %717
  %719 = fmul float %..141, %48
  %720 = fmul float %temp12.0, %49
  %721 = fadd float %719, %720
  %722 = fmul float 0.000000e+00, %50
  %723 = fadd float %721, %722
  %724 = fmul float 1.000000e+00, %51
  %725 = fadd float %723, %724
  %726 = fmul float %..141, %52
  %727 = fmul float %temp12.0, %53
  %728 = fadd float %726, %727
  %729 = fmul float 0.000000e+00, %54
  %730 = fadd float %728, %729
  %731 = fmul float 1.000000e+00, %55
  %732 = fadd float %730, %731
  %733 = fmul float %138, %76
  %734 = fadd float %733, %78
  %735 = fmul float %137, %76
  %736 = fadd float %735, %78
  %737 = fmul float %136, %76
  %738 = fadd float %737, %78
  %739 = fmul float %139, %77
  %740 = fadd float %739, %78
  %741 = fmul float %734, %734
  %742 = fmul float %736, %736
  %743 = fmul float %738, %738
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %527, float %534, float %541, float 1.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %697, float %704, float %711, float %718)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %674, float %676, float %683, float %690)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %725, float %732, float 0.000000e+00, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 36, i32 0, float %741, float %742, float %743, float %740)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 37, i32 0, float %590, float %591, float %592, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 38, i32 0, float 0.000000e+00, float 0.000000e+00, float %738, float %740)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %499, float %506, float %513, float %520)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDGPU.rsq(float) #2

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg106, %SGPR6_SGPR7 in %vreg109, %VGPR0 in %vreg112

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%107](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%VGPR28_VGPR29_VGPR30_VGPR31<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	%SGPR44_SGPR45_SGPR46_SGPR47<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%11](align=8)(tbaa=!"const")
	S_WAITCNT 112
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 144; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR1<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 146; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR23<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
	%VGPR10<def> = V_MAD_F32 %VGPR30, %VGPR23, %VGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR28, %VGPR23, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 28; mem:LD16[%140](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%VGPR6_VGPR7_VGPR8_VGPR9<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 24; mem:LD16[%135](align=8)(tbaa=!"const")
	S_WAITCNT 112
	%VGPR44_VGPR45_VGPR46_VGPR47<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 20; mem:LD16[%130](align=8)(tbaa=!"const")
	S_WAITCNT 112
	%VGPR19_VGPR20_VGPR21_VGPR22<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 16; mem:LD16[%125](align=8)(tbaa=!"const")
	S_WAITCNT 112
	%VGPR15_VGPR16_VGPR17_VGPR18<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 12; mem:LD16[%120](align=8)(tbaa=!"const")
	S_WAITCNT 112
	%VGPR11_VGPR12_VGPR13_VGPR14<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 8; mem:LD16[%115](align=8)(tbaa=!"const")
	S_WAITCNT 112
	%VGPR24_VGPR25_VGPR26_VGPR27<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 0; mem:LD16[%98](align=8)(tbaa=!"const")
	S_WAITCNT 112
	%VGPR1_VGPR2_VGPR3_VGPR4<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 145; mem:LD4[<unknown>]
	S_WAITCNT 112
	%VGPR32<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
	%VGPR23<def> = V_MAD_F32 %VGPR29, %VGPR23<kill>, %VGPR32<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR28_VGPR29_VGPR30_VGPR31<imp-use,kill>
	%VGPR23<def> = V_ADD_F32_e32 1.000000e-03, %VGPR23<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_MOV_B32 3840
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_SGPR %SGPR44_SGPR45_SGPR46_SGPR47, %SGPR0<kill>; mem:LD4[<unknown>]
	S_WAITCNT 127
	%SGPR62_SGPR63<def> = V_CMP_NE_I32_e64 %SGPR0<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR9<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 138; mem:LD4[<unknown>]
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 137; mem:LD4[<unknown>]
	%SGPR8<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 136; mem:LD4[<unknown>]
	%SGPR40<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 134; mem:LD4[<unknown>]
	%SGPR38<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 133; mem:LD4[<unknown>]
	%SGPR39<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 132; mem:LD4[<unknown>]
	%SGPR37<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 130; mem:LD4[<unknown>]
	%SGPR35<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 129; mem:LD4[<unknown>]
	%SGPR36<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 128; mem:LD4[<unknown>]
	%SGPR28<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 126; mem:LD4[<unknown>]
	%SGPR18<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 125; mem:LD4[<unknown>]
	%SGPR27<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 124; mem:LD4[<unknown>]
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 122; mem:LD4[<unknown>]
	%SGPR61<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 121; mem:LD4[<unknown>]
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 120; mem:LD4[<unknown>]
	%SGPR64<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 119; mem:LD4[<unknown>]
	%SGPR65<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 118; mem:LD4[<unknown>]
	%SGPR66<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 117; mem:LD4[<unknown>]
	%SGPR67<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 116; mem:LD4[<unknown>]
	%SGPR25<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 115; mem:LD4[<unknown>]
	%SGPR29<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 114; mem:LD4[<unknown>]
	%SGPR31<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 113; mem:LD4[<unknown>]
	%SGPR32<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 112; mem:LD4[<unknown>]
	%SGPR26<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 111; mem:LD4[<unknown>]
	%SGPR30<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 110; mem:LD4[<unknown>]
	%SGPR33<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 109; mem:LD4[<unknown>]
	%SGPR34<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 108; mem:LD4[<unknown>]
	%SGPR43<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 107; mem:LD4[<unknown>]
	%SGPR51<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 106; mem:LD4[<unknown>]
	%SGPR57<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 105; mem:LD4[<unknown>]
	%SGPR58<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 104; mem:LD4[<unknown>]
	%SGPR48<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 103; mem:LD4[<unknown>]
	%SGPR52<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 102; mem:LD4[<unknown>]
	%SGPR59<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 101; mem:LD4[<unknown>]
	%SGPR60<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 100; mem:LD4[<unknown>]
	%SGPR16<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 99; mem:LD4[<unknown>]
	%SGPR19<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 98; mem:LD4[<unknown>]
	%SGPR21<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 97; mem:LD4[<unknown>]
	%SGPR22<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 96; mem:LD4[<unknown>]
	%SGPR17<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 95; mem:LD4[<unknown>]
	%SGPR20<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 94; mem:LD4[<unknown>]
	%SGPR23<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 93; mem:LD4[<unknown>]
	%SGPR24<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 92; mem:LD4[<unknown>]
	%SGPR41<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 35; mem:LD4[<unknown>]
	%SGPR49<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 34; mem:LD4[<unknown>]
	%SGPR53<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 33; mem:LD4[<unknown>]
	%SGPR54<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 32; mem:LD4[<unknown>]
	%SGPR42<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 31; mem:LD4[<unknown>]
	%SGPR50<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 30; mem:LD4[<unknown>]
	%SGPR55<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 29; mem:LD4[<unknown>]
	%SGPR56<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 28; mem:LD4[<unknown>]
	%SGPR68<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 27; mem:LD4[<unknown>]
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 26; mem:LD4[<unknown>]
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 25; mem:LD4[<unknown>]
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 24; mem:LD4[<unknown>]
	%SGPR69<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 23; mem:LD4[<unknown>]
	%SGPR13<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 22; mem:LD4[<unknown>]
	%SGPR15<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 21; mem:LD4[<unknown>]
	%SGPR14<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 20; mem:LD4[<unknown>]
	%SGPR70<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 19; mem:LD4[<unknown>]
	%SGPR10<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 18; mem:LD4[<unknown>]
	%SGPR12<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 17; mem:LD4[<unknown>]
	%SGPR11<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 16; mem:LD4[<unknown>]
	%SGPR71<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 15; mem:LD4[<unknown>]
	%SGPR72<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 14; mem:LD4[<unknown>]
	%SGPR73<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 13; mem:LD4[<unknown>]
	%SGPR74<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 12; mem:LD4[<unknown>]
	%SGPR75<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 11; mem:LD4[<unknown>]
	%SGPR76<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 10; mem:LD4[<unknown>]
	%SGPR77<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 9; mem:LD4[<unknown>]
	%SGPR78<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 8; mem:LD4[<unknown>]
	%SGPR79<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 7; mem:LD4[<unknown>]
	%SGPR80<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 6; mem:LD4[<unknown>]
	%SGPR81<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 5; mem:LD4[<unknown>]
	%SGPR82<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 4; mem:LD4[<unknown>]
	%SGPR83<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 3; mem:LD4[<unknown>]
	%SGPR84<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 2; mem:LD4[<unknown>]
	%SGPR85<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 1; mem:LD4[<unknown>]
	%SGPR86<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR44_SGPR45_SGPR46_SGPR47, 0; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR48<def> = V_MOV_B32_e32 %SGPR61<kill>, %EXEC<imp-use>
	%VGPR50<def> = V_MOV_B32_e32 %SGPR64<kill>, %EXEC<imp-use>
	%VGPR49<def> = V_MOV_B32_e32 %SGPR65<kill>, %EXEC<imp-use>
	%VGPR52<def> = V_MOV_B32_e32 %SGPR66<kill>, %EXEC<imp-use>
	%VGPR51<def> = V_MOV_B32_e32 %SGPR67<kill>, %EXEC<imp-use>
	%VGPR55<def> = V_MOV_B32_e32 %SGPR68<kill>, %EXEC<imp-use>
	%VGPR54<def> = V_MOV_B32_e32 %SGPR69<kill>, %EXEC<imp-use>
	%VGPR53<def> = V_MOV_B32_e32 %SGPR70<kill>, %EXEC<imp-use>
	%VGPR31<def> = V_MOV_B32_e32 %SGPR71<kill>, %EXEC<imp-use>
	%VGPR35<def> = V_MOV_B32_e32 %SGPR72<kill>, %EXEC<imp-use>
	%VGPR43<def> = V_MOV_B32_e32 %SGPR73<kill>, %EXEC<imp-use>
	%VGPR42<def> = V_MOV_B32_e32 %SGPR74<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_MOV_B32_e32 %SGPR75<kill>, %EXEC<imp-use>
	%VGPR34<def> = V_MOV_B32_e32 %SGPR76<kill>, %EXEC<imp-use>
	%VGPR41<def> = V_MOV_B32_e32 %SGPR77<kill>, %EXEC<imp-use>
	%VGPR40<def> = V_MOV_B32_e32 %SGPR78<kill>, %EXEC<imp-use>
	%VGPR29<def> = V_MOV_B32_e32 %SGPR79<kill>, %EXEC<imp-use>
	%VGPR33<def> = V_MOV_B32_e32 %SGPR80<kill>, %EXEC<imp-use>
	%VGPR39<def> = V_MOV_B32_e32 %SGPR81<kill>, %EXEC<imp-use>
	%VGPR38<def> = V_MOV_B32_e32 %SGPR82<kill>, %EXEC<imp-use>
	%VGPR28<def> = V_MOV_B32_e32 %SGPR83<kill>, %EXEC<imp-use>
	%VGPR32<def> = V_MOV_B32_e32 %SGPR84<kill>, %EXEC<imp-use>
	%VGPR37<def> = V_MOV_B32_e32 %SGPR85<kill>, %EXEC<imp-use>
	%VGPR36<def> = V_MOV_B32_e32 %SGPR86<kill>, %EXEC<imp-use>
	%VGPR58<def> = V_MOV_B32_e32 %VGPR1, %EXEC<imp-use>
	%VGPR57<def> = V_MOV_B32_e32 %VGPR2, %EXEC<imp-use>
	%VGPR56<def> = V_MOV_B32_e32 %VGPR3, %EXEC<imp-use>
	%SGPR62_SGPR63<def> = S_AND_SAVEEXEC_B64 %SGPR62_SGPR63, %EXEC<imp-def>, %EXEC<imp-use>
	%SGPR62_SGPR63<def> = S_XOR_B64 %EXEC, %SGPR62_SGPR63
	S_CBRANCH_EXECZ <BB#2>, %EXEC
    Successors according to CFG: BB#1(16) BB#2(16)

BB#1: derived from LLVM BB %IF
    Live Ins: %SGPR44_SGPR45_SGPR46_SGPR47 %VGPR36 %VGPR37 %VGPR32 %VGPR28 %VGPR38 %VGPR39 %VGPR33 %VGPR29 %VGPR40 %VGPR41 %VGPR34 %VGPR30 %VGPR42 %VGPR43 %VGPR35 %VGPR31 %SGPR11 %SGPR12 %SGPR10 %VGPR53 %SGPR14 %SGPR15 %SGPR13 %VGPR54 %SGPR3 %SGPR4 %SGPR0 %VGPR55 %VGPR51 %VGPR52 %VGPR49 %VGPR50 %SGPR1 %VGPR48 %SGPR2 %VGPR24_VGPR25_VGPR26_VGPR27 %VGPR11_VGPR12_VGPR13_VGPR14 %VGPR15_VGPR16_VGPR17_VGPR18 %VGPR19_VGPR20_VGPR21_VGPR22 %VGPR44_VGPR45_VGPR46_VGPR47 %VGPR6_VGPR7_VGPR8_VGPR9 %SGPR6_SGPR7 %VGPR0 %VGPR1_VGPR2_VGPR3_VGPR4 %SGPR9 %SGPR5 %SGPR8 %SGPR40 %SGPR38 %SGPR39 %SGPR37 %SGPR35 %SGPR36 %SGPR28 %SGPR18 %SGPR27 %SGPR25 %SGPR29 %SGPR31 %SGPR32 %SGPR26 %SGPR30 %SGPR33 %SGPR34 %SGPR43 %SGPR51 %SGPR57 %SGPR58 %SGPR48 %SGPR52 %SGPR59 %SGPR60 %SGPR16 %SGPR19 %SGPR21 %SGPR22 %SGPR17 %SGPR20 %SGPR23 %SGPR24 %SGPR41 %SGPR49 %SGPR53 %SGPR54 %SGPR42 %SGPR50 %SGPR55 %SGPR56 %SGPR62_SGPR63 %VGPR5 %VGPR23 %VGPR10
    Predecessors according to CFG: BB#0
	%SGPR64_SGPR65_SGPR66_SGPR67<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 32; mem:LD16[%157](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%VGPR56_VGPR57_VGPR58_VGPR59<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR64_SGPR65_SGPR66_SGPR67<kill>, %VGPR0, 0, %EXEC<imp-use>
	%VGPR60<def> = V_MOV_B32_e32 2.550100e+02, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR61<def> = V_MUL_F32_e32 %VGPR56, %VGPR60, %EXEC<imp-use>
	%VGPR61<def> = V_CVT_I32_F32_e32 %VGPR61<kill>, %EXEC<imp-use>
	%VGPR61<def> = V_MUL_LO_I32 3, %VGPR61<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR62<def> = V_ADD_I32_e32 43, %VGPR61, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR62<def> = V_LSHLREV_B32_e32 4, %VGPR62<kill>, %EXEC<imp-use>
	%VGPR63<def> = V_OR_B32_e64 4, %VGPR62, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR63<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR44_SGPR45_SGPR46_SGPR47, %VGPR63<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	%SGPR64_SGPR65_SGPR66_SGPR67<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 36; mem:LD16[%166](align=8)(tbaa=!"const")
	S_WAITCNT 112
	%VGPR64_VGPR65_VGPR66_VGPR67<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR64_SGPR65_SGPR66_SGPR67<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR0<def> = V_MUL_F32_e32 %VGPR63<kill>, %VGPR64, %EXEC<imp-use>
	%VGPR63<def> = V_MUL_F32_e32 %VGPR57, %VGPR60, %EXEC<imp-use>
	%VGPR63<def> = V_CVT_I32_F32_e32 %VGPR63<kill>, %EXEC<imp-use>
	%VGPR63<def> = V_MUL_LO_I32 3, %VGPR63<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR68<def> = V_ADD_I32_e32 43, %VGPR63, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR68<def> = V_LSHLREV_B32_e32 4, %VGPR68<kill>, %EXEC<imp-use>
	%VGPR69<def> = V_OR_B32_e64 4, %VGPR68, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR69<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR44_SGPR45_SGPR46_SGPR47, %VGPR69<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR0<def> = V_MAD_F32 %VGPR69<kill>, %VGPR65, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR69<def> = V_MUL_F32_e32 %VGPR58, %VGPR60, %EXEC<imp-use>
	%VGPR69<def> = V_CVT_I32_F32_e32 %VGPR69<kill>, %EXEC<imp-use>
	%VGPR69<def> = V_MUL_LO_I32 3, %VGPR69<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR70<def> = V_ADD_I32_e32 43, %VGPR69, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR70<def> = V_LSHLREV_B32_e32 4, %VGPR70<kill>, %EXEC<imp-use>
	%VGPR71<def> = V_OR_B32_e64 4, %VGPR70, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR71<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR44_SGPR45_SGPR46_SGPR47, %VGPR71<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR0<def> = V_MAD_F32 %VGPR71<kill>, %VGPR66, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR71<def> = V_ADD_F32_e32 %VGPR65, %VGPR64, %EXEC<imp-use>
	%VGPR71<def> = V_ADD_F32_e32 %VGPR71<kill>, %VGPR66, %EXEC<imp-use>
	%VGPR71<def> = V_SUB_F32_e32 1.000000e+00, %VGPR71<kill>, %EXEC<imp-use>
	%VGPR56<def> = V_MUL_F32_e32 %VGPR59, %VGPR60<kill>, %EXEC<imp-use>, %VGPR56_VGPR57_VGPR58_VGPR59<imp-use,kill>
	%VGPR56<def> = V_CVT_I32_F32_e32 %VGPR56<kill>, %EXEC<imp-use>
	%VGPR56<def> = V_MUL_LO_I32 3, %VGPR56<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR57<def> = V_ADD_I32_e32 43, %VGPR56, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR57<def> = V_LSHLREV_B32_e32 4, %VGPR57<kill>, %EXEC<imp-use>
	%VGPR58<def> = V_OR_B32_e64 4, %VGPR57, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR58<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR44_SGPR45_SGPR46_SGPR47, %VGPR58<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR0<def> = V_MAD_F32 %VGPR58<kill>, %VGPR71, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR58<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR44_SGPR45_SGPR46_SGPR47, %VGPR62, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR58<def> = V_MUL_F32_e32 %VGPR58<kill>, %VGPR64, %EXEC<imp-use>
	%VGPR59<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR44_SGPR45_SGPR46_SGPR47, %VGPR68, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR58<def> = V_MAD_F32 %VGPR59<kill>, %VGPR65, %VGPR58<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR59<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR44_SGPR45_SGPR46_SGPR47, %VGPR70, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR58<def> = V_MAD_F32 %VGPR59<kill>, %VGPR66, %VGPR58<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR59<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR44_SGPR45_SGPR46_SGPR47, %VGPR57, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR58<def> = V_MAD_F32 %VGPR59<kill>, %VGPR71, %VGPR58<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR59<def> = V_MUL_F32_e32 %VGPR5, %VGPR58, %EXEC<imp-use>
	%VGPR59<def> = V_MAD_F32 %VGPR23, %VGPR0, %VGPR59<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR60<def> = V_OR_B32_e64 8, %VGPR62, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR60<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR44_SGPR45_SGPR46_SGPR47, %VGPR60<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR60<def> = V_MUL_F32_e32 %VGPR60<kill>, %VGPR64, %EXEC<imp-use>
	%VGPR72<def> = V_OR_B32_e64 8, %VGPR68, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR72<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR44_SGPR45_SGPR46_SGPR47, %VGPR72<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR60<def> = V_MAD_F32 %VGPR72<kill>, %VGPR65, %VGPR60<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR72<def> = V_OR_B32_e64 8, %VGPR70, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR72<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR44_SGPR45_SGPR46_SGPR47, %VGPR72<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR60<def> = V_MAD_F32 %VGPR72<kill>, %VGPR66, %VGPR60<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR72<def> = V_OR_B32_e64 8, %VGPR57, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR72<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR44_SGPR45_SGPR46_SGPR47, %VGPR72<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR60<def> = V_MAD_F32 %VGPR72<kill>, %VGPR71, %VGPR60<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR59<def> = V_MAD_F32 %VGPR10, %VGPR60, %VGPR59<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR72<def> = V_ADD_I32_e32 42, %VGPR61, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR72<def> = V_LSHLREV_B32_e32 4, %VGPR72<kill>, %EXEC<imp-use>
	%VGPR73<def> = V_OR_B32_e64 4, %VGPR72, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR73<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR44_SGPR45_SGPR46_SGPR47, %VGPR73<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR73<def> = V_MUL_F32_e32 %VGPR73<kill>, %VGPR64, %EXEC<imp-use>
	%VGPR74<def> = V_ADD_I32_e32 42, %VGPR63, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR74<def> = V_LSHLREV_B32_e32 4, %VGPR74<kill>, %EXEC<imp-use>
	%VGPR75<def> = V_OR_B32_e64 4, %VGPR74, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR75<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR44_SGPR45_SGPR46_SGPR47, %VGPR75<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR73<def> = V_MAD_F32 %VGPR75<kill>, %VGPR65, %VGPR73<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR75<def> = V_ADD_I32_e32 42, %VGPR69, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR75<def> = V_LSHLREV_B32_e32 4, %VGPR75<kill>, %EXEC<imp-use>
	%VGPR76<def> = V_OR_B32_e64 4, %VGPR75, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR76<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR44_SGPR45_SGPR46_SGPR47, %VGPR76<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR73<def> = V_MAD_F32 %VGPR76<kill>, %VGPR66, %VGPR73<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR76<def> = V_ADD_I32_e32 42, %VGPR56, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR76<def> = V_LSHLREV_B32_e32 4, %VGPR76<kill>, %EXEC<imp-use>
	%VGPR77<def> = V_OR_B32_e64 4, %VGPR76, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR77<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR44_SGPR45_SGPR46_SGPR47, %VGPR77<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR73<def> = V_MAD_F32 %VGPR77<kill>, %VGPR71, %VGPR73<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR77<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR44_SGPR45_SGPR46_SGPR47, %VGPR72, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR77<def> = V_MUL_F32_e32 %VGPR77<kill>, %VGPR64, %EXEC<imp-use>
	%VGPR78<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR44_SGPR45_SGPR46_SGPR47, %VGPR74, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR77<def> = V_MAD_F32 %VGPR78<kill>, %VGPR65, %VGPR77<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR78<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR44_SGPR45_SGPR46_SGPR47, %VGPR75, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR77<def> = V_MAD_F32 %VGPR78<kill>, %VGPR66, %VGPR77<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR78<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR44_SGPR45_SGPR46_SGPR47, %VGPR76, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR77<def> = V_MAD_F32 %VGPR78<kill>, %VGPR71, %VGPR77<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR78<def> = V_MUL_F32_e32 %VGPR5, %VGPR77, %EXEC<imp-use>
	%VGPR78<def> = V_MAD_F32 %VGPR23, %VGPR73, %VGPR78<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR79<def> = V_OR_B32_e64 8, %VGPR72, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR79<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR44_SGPR45_SGPR46_SGPR47, %VGPR79<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR79<def> = V_MUL_F32_e32 %VGPR79<kill>, %VGPR64, %EXEC<imp-use>
	%VGPR80<def> = V_OR_B32_e64 8, %VGPR74, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR80<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR44_SGPR45_SGPR46_SGPR47, %VGPR80<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR79<def> = V_MAD_F32 %VGPR80<kill>, %VGPR65, %VGPR79<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR80<def> = V_OR_B32_e64 8, %VGPR75, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR80<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR44_SGPR45_SGPR46_SGPR47, %VGPR80<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR79<def> = V_MAD_F32 %VGPR80<kill>, %VGPR66, %VGPR79<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR80<def> = V_OR_B32_e64 8, %VGPR76, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR80<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR44_SGPR45_SGPR46_SGPR47, %VGPR80<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR79<def> = V_MAD_F32 %VGPR80<kill>, %VGPR71, %VGPR79<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR78<def> = V_MAD_F32 %VGPR10, %VGPR79, %VGPR78<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR61<def> = V_ADD_I32_e32 41, %VGPR61<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR61<def> = V_LSHLREV_B32_e32 4, %VGPR61<kill>, %EXEC<imp-use>
	%VGPR80<def> = V_OR_B32_e64 4, %VGPR61, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR80<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR44_SGPR45_SGPR46_SGPR47, %VGPR80<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR80<def> = V_MUL_F32_e32 %VGPR80<kill>, %VGPR64, %EXEC<imp-use>
	%VGPR63<def> = V_ADD_I32_e32 41, %VGPR63<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR63<def> = V_LSHLREV_B32_e32 4, %VGPR63<kill>, %EXEC<imp-use>
	%VGPR81<def> = V_OR_B32_e64 4, %VGPR63, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR81<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR44_SGPR45_SGPR46_SGPR47, %VGPR81<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR80<def> = V_MAD_F32 %VGPR81<kill>, %VGPR65, %VGPR80<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR69<def> = V_ADD_I32_e32 41, %VGPR69<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR69<def> = V_LSHLREV_B32_e32 4, %VGPR69<kill>, %EXEC<imp-use>
	%VGPR81<def> = V_OR_B32_e64 4, %VGPR69, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR81<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR44_SGPR45_SGPR46_SGPR47, %VGPR81<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR80<def> = V_MAD_F32 %VGPR81<kill>, %VGPR66, %VGPR80<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR56<def> = V_ADD_I32_e32 41, %VGPR56<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR81<def> = V_LSHLREV_B32_e32 4, %VGPR56<kill>, %EXEC<imp-use>
	%VGPR56<def> = V_OR_B32_e64 4, %VGPR81, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR56<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR44_SGPR45_SGPR46_SGPR47, %VGPR56<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR80<def> = V_MAD_F32 %VGPR56<kill>, %VGPR71, %VGPR80<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR56<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR44_SGPR45_SGPR46_SGPR47, %VGPR61, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR56<def> = V_MUL_F32_e32 %VGPR56<kill>, %VGPR64, %EXEC<imp-use>
	%VGPR82<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR44_SGPR45_SGPR46_SGPR47, %VGPR63, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR56<def> = V_MAD_F32 %VGPR82<kill>, %VGPR65, %VGPR56<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR82<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR44_SGPR45_SGPR46_SGPR47, %VGPR69, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR56<def> = V_MAD_F32 %VGPR82<kill>, %VGPR66, %VGPR56<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR82<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR44_SGPR45_SGPR46_SGPR47, %VGPR81, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR82<def> = V_MAD_F32 %VGPR82<kill>, %VGPR71, %VGPR56<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_MUL_F32_e32 %VGPR5<kill>, %VGPR82, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR23<kill>, %VGPR80, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR23<def> = V_OR_B32_e64 8, %VGPR61, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR23<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR44_SGPR45_SGPR46_SGPR47, %VGPR23<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR23<def> = V_MUL_F32_e32 %VGPR23<kill>, %VGPR64, %EXEC<imp-use>
	%VGPR56<def> = V_OR_B32_e64 8, %VGPR63, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR56<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR44_SGPR45_SGPR46_SGPR47, %VGPR56<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR23<def> = V_MAD_F32 %VGPR56<kill>, %VGPR65, %VGPR23<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR56<def> = V_OR_B32_e64 8, %VGPR69, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR56<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR44_SGPR45_SGPR46_SGPR47, %VGPR56<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR23<def> = V_MAD_F32 %VGPR56<kill>, %VGPR66, %VGPR23<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR56<def> = V_OR_B32_e64 8, %VGPR81, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR56<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR44_SGPR45_SGPR46_SGPR47, %VGPR56<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR23<def> = V_MAD_F32 %VGPR56<kill>, %VGPR71, %VGPR23<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR10<kill>, %VGPR23, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR2, %VGPR0<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR1, %VGPR58<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR3, %VGPR60<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR10<def> = V_OR_B32_e64 12, %VGPR62<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR10<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR44_SGPR45_SGPR46_SGPR47, %VGPR10<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR10<def> = V_MUL_F32_e32 %VGPR10<kill>, %VGPR64, %EXEC<imp-use>
	%VGPR56<def> = V_OR_B32_e64 12, %VGPR68<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR56<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR44_SGPR45_SGPR46_SGPR47, %VGPR56<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR10<def> = V_MAD_F32 %VGPR56<kill>, %VGPR65, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR56<def> = V_OR_B32_e64 12, %VGPR70<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR56<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR44_SGPR45_SGPR46_SGPR47, %VGPR56<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR10<def> = V_MAD_F32 %VGPR56<kill>, %VGPR66, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR56<def> = V_OR_B32_e64 12, %VGPR57<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR56<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR44_SGPR45_SGPR46_SGPR47, %VGPR56<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR10<def> = V_MAD_F32 %VGPR56<kill>, %VGPR71, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR56<def> = V_MAD_F32 %VGPR4, %VGPR10<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR2, %VGPR73<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR1, %VGPR77<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR3, %VGPR79<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR10<def> = V_OR_B32_e64 12, %VGPR72<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR10<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR44_SGPR45_SGPR46_SGPR47, %VGPR10<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR10<def> = V_MUL_F32_e32 %VGPR10<kill>, %VGPR64, %EXEC<imp-use>
	%VGPR57<def> = V_OR_B32_e64 12, %VGPR74<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR57<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR44_SGPR45_SGPR46_SGPR47, %VGPR57<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR10<def> = V_MAD_F32 %VGPR57<kill>, %VGPR65, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR57<def> = V_OR_B32_e64 12, %VGPR75<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR57<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR44_SGPR45_SGPR46_SGPR47, %VGPR57<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR10<def> = V_MAD_F32 %VGPR57<kill>, %VGPR66, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR57<def> = V_OR_B32_e64 12, %VGPR76<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR57<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR44_SGPR45_SGPR46_SGPR47, %VGPR57<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR10<def> = V_MAD_F32 %VGPR57<kill>, %VGPR71, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR57<def> = V_MAD_F32 %VGPR4, %VGPR10<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR2, %VGPR80<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR1, %VGPR82<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR3, %VGPR23<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR10<def> = V_OR_B32_e64 12, %VGPR61<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR10<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR44_SGPR45_SGPR46_SGPR47, %VGPR10<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR10<def> = V_MUL_F32_e32 %VGPR10<kill>, %VGPR64, %EXEC<imp-use>
	%VGPR23<def> = V_OR_B32_e64 12, %VGPR63<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR23<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR44_SGPR45_SGPR46_SGPR47, %VGPR23<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR10<def> = V_MAD_F32 %VGPR23<kill>, %VGPR65, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR23<def> = V_OR_B32_e64 12, %VGPR69<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR23<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR44_SGPR45_SGPR46_SGPR47, %VGPR23<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR10<def> = V_MAD_F32 %VGPR23<kill>, %VGPR66, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR64_VGPR65_VGPR66_VGPR67<imp-use,kill>
	%VGPR23<def> = V_OR_B32_e64 12, %VGPR81<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR23<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR44_SGPR45_SGPR46_SGPR47<kill>, %VGPR23<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR10<def> = V_MAD_F32 %VGPR23<kill>, %VGPR71<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR58<def> = V_MAD_F32 %VGPR4, %VGPR10<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR23<def> = V_MOV_B32_e32 %VGPR78<kill>, %EXEC<imp-use>
	%VGPR10<def> = V_MOV_B32_e32 %VGPR59<kill>, %EXEC<imp-use>
    Successors according to CFG: BB#2

BB#2: derived from LLVM BB %ENDIF
    Live Ins: %VGPR36 %VGPR37 %VGPR32 %VGPR28 %VGPR38 %VGPR39 %VGPR33 %VGPR29 %VGPR40 %VGPR41 %VGPR34 %VGPR30 %VGPR42 %VGPR43 %VGPR35 %VGPR31 %SGPR11 %SGPR12 %SGPR10 %VGPR53 %SGPR14 %SGPR15 %SGPR13 %VGPR54 %SGPR3 %SGPR4 %SGPR0 %VGPR55 %VGPR51 %VGPR52 %VGPR49 %VGPR50 %SGPR1 %VGPR48 %SGPR2 %VGPR24_VGPR25_VGPR26_VGPR27 %VGPR11_VGPR12_VGPR13_VGPR14 %VGPR15_VGPR16_VGPR17_VGPR18 %VGPR19_VGPR20_VGPR21_VGPR22 %VGPR44_VGPR45_VGPR46_VGPR47 %VGPR6_VGPR7_VGPR8_VGPR9 %VGPR1_VGPR2_VGPR3_VGPR4 %SGPR9 %SGPR5 %SGPR8 %SGPR40 %SGPR38 %SGPR39 %SGPR37 %SGPR35 %SGPR36 %SGPR28 %SGPR18 %SGPR27 %SGPR25 %SGPR29 %SGPR31 %SGPR32 %SGPR26 %SGPR30 %SGPR33 %SGPR34 %SGPR43 %SGPR51 %SGPR57 %SGPR58 %SGPR48 %SGPR52 %SGPR59 %SGPR60 %SGPR16 %SGPR19 %SGPR21 %SGPR22 %SGPR17 %SGPR20 %SGPR23 %SGPR24 %SGPR41 %SGPR49 %SGPR53 %SGPR54 %SGPR42 %SGPR50 %SGPR55 %SGPR56 %SGPR62_SGPR63 %VGPR58 %VGPR57 %VGPR56 %VGPR5 %VGPR23 %VGPR10
    Predecessors according to CFG: BB#0 BB#1
	%EXEC<def> = S_OR_B64 %EXEC, %SGPR62_SGPR63
	%VGPR0<def> = V_MOV_B32_e32 %SGPR4, %EXEC<imp-use>
	%VGPR59<def> = V_MUL_F32_e64 %VGPR57, %VGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR60<def> = V_MOV_B32_e32 %SGPR3, %EXEC<imp-use>
	%VGPR59<def> = V_MAD_F32 %VGPR58, %VGPR60, %VGPR59<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR61<def> = V_MOV_B32_e32 %SGPR0, %EXEC<imp-use>
	%VGPR59<def> = V_MAD_F32 %VGPR56, %VGPR61, %VGPR59<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR55<def> = V_MAD_F32 %VGPR4, %VGPR55<kill>, %VGPR59<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR59<def> = V_MOV_B32_e32 %SGPR15, %EXEC<imp-use>
	%VGPR62<def> = V_MUL_F32_e64 %VGPR57, %VGPR59, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR63<def> = V_MOV_B32_e32 %SGPR14, %EXEC<imp-use>
	%VGPR62<def> = V_MAD_F32 %VGPR58, %VGPR63, %VGPR62<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR64<def> = V_MOV_B32_e32 %SGPR13, %EXEC<imp-use>
	%VGPR62<def> = V_MAD_F32 %VGPR56, %VGPR64, %VGPR62<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR54<def> = V_MAD_F32 %VGPR4, %VGPR54<kill>, %VGPR62<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR62<def> = V_MOV_B32_e32 %SGPR12, %EXEC<imp-use>
	%VGPR65<def> = V_MUL_F32_e64 %VGPR57, %VGPR62, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR66<def> = V_MOV_B32_e32 %SGPR11, %EXEC<imp-use>
	%VGPR65<def> = V_MAD_F32 %VGPR58, %VGPR66, %VGPR65<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR67<def> = V_MOV_B32_e32 %SGPR10, %EXEC<imp-use>
	%VGPR65<def> = V_MAD_F32 %VGPR56, %VGPR67, %VGPR65<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR53<def> = V_MAD_F32 %VGPR4, %VGPR53<kill>, %VGPR65<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR65<def> = V_MOV_B32_e32 1.000000e+00, %EXEC<imp-use>
	EXP 15, 32, 0, 0, 0, %VGPR53, %VGPR54, %VGPR55, %VGPR65<kill>, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %SGPR40<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	S_WAITCNT 1807
	%VGPR65<def> = V_CNDMASK_B32_e64 %VGPR44, %VGPR53, %SGPR6_SGPR7, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR44_SGPR45<def> = V_CMP_GE_F32_e64 %SGPR39<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR65<def> = V_CNDMASK_B32_e64 %VGPR65<kill>, %VGPR55, %SGPR44_SGPR45<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR44<def> = V_CNDMASK_B32_e64 %VGPR45, %VGPR54, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR44_VGPR45_VGPR46_VGPR47<imp-use,kill>
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %SGPR38<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR44<def> = V_CNDMASK_B32_e64 %VGPR44<kill>, %VGPR55, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR45<def> = V_MUL_F32_e32 %SGPR57<kill>, %VGPR44, %EXEC<imp-use>
	%VGPR45<def> = V_MAD_F32 %VGPR65, %SGPR58<kill>, %VGPR45<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR45<def> = V_MAD_F32 %SGPR51<kill>, 0.000000e+00, %VGPR45<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR45<def> = V_ADD_F32_e32 %SGPR43<kill>, %VGPR45<kill>, %EXEC<imp-use>
	%VGPR44<def> = V_MUL_F32_e32 %SGPR59<kill>, %VGPR44<kill>, %EXEC<imp-use>
	%VGPR44<def> = V_MAD_F32 %VGPR65<kill>, %SGPR60<kill>, %VGPR44<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR44<def> = V_MAD_F32 %SGPR52<kill>, 0.000000e+00, %VGPR44<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR44<def> = V_ADD_F32_e32 %SGPR48<kill>, %VGPR44<kill>, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %SGPR37<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR46<def> = V_CNDMASK_B32_e64 %VGPR24, %VGPR53, %SGPR6_SGPR7, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR36_SGPR37<def> = V_CMP_GE_F32_e64 %SGPR36<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR46<def> = V_CNDMASK_B32_e64 %VGPR46<kill>, %VGPR55, %SGPR36_SGPR37<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_CNDMASK_B32_e64 %VGPR25, %VGPR54, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR24_VGPR25_VGPR26_VGPR27<imp-use,kill>
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %SGPR35<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_CNDMASK_B32_e64 %VGPR24<kill>, %VGPR55, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR25<def> = V_MUL_F32_e32 %SGPR53<kill>, %VGPR24, %EXEC<imp-use>
	%VGPR25<def> = V_MAD_F32 %VGPR46, %SGPR54<kill>, %VGPR25<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR25<def> = V_MAD_F32 %SGPR49<kill>, 0.000000e+00, %VGPR25<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR25<def> = V_ADD_F32_e32 %SGPR41<kill>, %VGPR25<kill>, %EXEC<imp-use>
	%VGPR24<def> = V_MUL_F32_e32 %SGPR55<kill>, %VGPR24<kill>, %EXEC<imp-use>
	%VGPR24<def> = V_MAD_F32 %VGPR46<kill>, %SGPR56<kill>, %VGPR24<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_MAD_F32 %SGPR50<kill>, 0.000000e+00, %VGPR24<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_ADD_F32_e32 %SGPR42<kill>, %VGPR24<kill>, %EXEC<imp-use>
	EXP 15, 33, 0, 0, 0, %VGPR24<kill>, %VGPR25<kill>, %VGPR44<kill>, %VGPR45<kill>, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %SGPR28<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	S_WAITCNT 1807
	%VGPR24<def> = V_CNDMASK_B32_e64 %VGPR19, %VGPR53, %SGPR6_SGPR7, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR36_SGPR37<def> = V_CMP_GE_F32_e64 %SGPR27<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_CNDMASK_B32_e64 %VGPR24<kill>, %VGPR55, %SGPR36_SGPR37<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR19<def> = V_CNDMASK_B32_e64 %VGPR20, %VGPR54, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR19_VGPR20_VGPR21_VGPR22<imp-use,kill>
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %SGPR18<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR19<def> = V_CNDMASK_B32_e64 %VGPR19<kill>, %VGPR55, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR20<def> = V_MUL_F32_e32 %SGPR31<kill>, %VGPR19, %EXEC<imp-use>
	%VGPR20<def> = V_MAD_F32 %VGPR24, %SGPR32<kill>, %VGPR20<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR20<def> = V_MAD_F32 %SGPR29<kill>, 0.000000e+00, %VGPR20<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR20<def> = V_ADD_F32_e32 %SGPR25<kill>, %VGPR20<kill>, %EXEC<imp-use>
	%VGPR19<def> = V_MUL_F32_e32 %SGPR33<kill>, %VGPR19<kill>, %EXEC<imp-use>
	%VGPR19<def> = V_MAD_F32 %VGPR24<kill>, %SGPR34<kill>, %VGPR19<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR19<def> = V_MAD_F32 %SGPR30<kill>, 0.000000e+00, %VGPR19<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR19<def> = V_ADD_F32_e32 %SGPR26<kill>, %VGPR19<kill>, %EXEC<imp-use>
	%VGPR21<def> = V_MAD_F32 %VGPR16, %VGPR52<kill>, %VGPR50<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR15<def> = V_MAD_F32 %VGPR15, %VGPR51<kill>, %VGPR49<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR15_VGPR16_VGPR17_VGPR18<imp-use,kill>
	EXP 15, 34, 0, 0, 0, %VGPR15<kill>, %VGPR21<kill>, %VGPR19<kill>, %VGPR20<kill>, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %SGPR9<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	S_WAITCNT 1807
	%VGPR15<def> = V_CNDMASK_B32_e64 %VGPR11, %VGPR53<kill>, %SGPR6_SGPR7, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8_SGPR9<def> = V_CMP_GE_F32_e64 %SGPR8<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR15<def> = V_CNDMASK_B32_e64 %VGPR15<kill>, %VGPR55, %SGPR8_SGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR11<def> = V_CNDMASK_B32_e64 %VGPR12, %VGPR54<kill>, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR11_VGPR12_VGPR13_VGPR14<imp-use,kill>
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %SGPR5<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR11<def> = V_CNDMASK_B32_e64 %VGPR11<kill>, %VGPR55<kill>, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_MUL_F32_e32 %SGPR21<kill>, %VGPR11, %EXEC<imp-use>
	%VGPR12<def> = V_MAD_F32 %VGPR15, %SGPR22<kill>, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_MAD_F32 %SGPR19<kill>, 0.000000e+00, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_ADD_F32_e32 %SGPR16<kill>, %VGPR12<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_MUL_F32_e32 %SGPR23<kill>, %VGPR11<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_MAD_F32 %VGPR15<kill>, %SGPR24<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR11<def> = V_MAD_F32 %SGPR20<kill>, 0.000000e+00, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR11<def> = V_ADD_F32_e32 %SGPR17<kill>, %VGPR11<kill>, %EXEC<imp-use>
	%VGPR13<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	EXP 15, 35, 0, 0, 0, %VGPR11<kill>, %VGPR12<kill>, %VGPR13, %VGPR13, %EXEC<imp-use>
	S_WAITCNT 1807
	%VGPR11<def> = V_MOV_B32_e32 %SGPR2<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_MAD_F32 %VGPR9, %VGPR48<kill>, %VGPR11, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR14<def> = V_MOV_B32_e32 %SGPR1<kill>, %EXEC<imp-use>
	%VGPR15<def> = V_MAD_F32 %VGPR6, %VGPR14, %VGPR11, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR16<def> = V_MUL_F32_e32 %VGPR15, %VGPR15, %EXEC<imp-use>
	%VGPR17<def> = V_MAD_F32 %VGPR7, %VGPR14, %VGPR11, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR17<def> = V_MUL_F32_e32 %VGPR17<kill>, %VGPR17, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR8, %VGPR14<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR6_VGPR7_VGPR8_VGPR9<imp-use,kill>
	%VGPR6<def> = V_MUL_F32_e32 %VGPR6<kill>, %VGPR6, %EXEC<imp-use>
	EXP 15, 36, 0, 0, 0, %VGPR6<kill>, %VGPR17<kill>, %VGPR16<kill>, %VGPR12, %EXEC<imp-use>
	S_WAITCNT 1807
	%VGPR6<def> = V_MUL_F32_e64 %SGPR14, %VGPR63<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %SGPR15, %VGPR59<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %SGPR13, %VGPR64<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_RCP_F32_e32 %VGPR6<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MUL_F32_e32 %SGPR15<kill>, %VGPR6, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_F32_e32 %SGPR14<kill>, %VGPR6, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_F32_e32 %VGPR5, %VGPR8<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR23, %VGPR7<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %SGPR13<kill>, %VGPR6<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR10, %VGPR6<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_MUL_F32_e64 %SGPR11, %VGPR66<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %SGPR12, %VGPR62<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %SGPR10, %VGPR67<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_RCP_F32_e32 %VGPR7<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_F32_e32 %SGPR12<kill>, %VGPR7, %EXEC<imp-use>
	%VGPR9<def> = V_MUL_F32_e32 %SGPR11<kill>, %VGPR7, %EXEC<imp-use>
	%VGPR9<def> = V_MUL_F32_e32 %VGPR5, %VGPR9<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_MAD_F32 %VGPR23, %VGPR8<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_MUL_F32_e32 %SGPR10<kill>, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR10, %VGPR7<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_F32_e32 %VGPR7, %VGPR7, %EXEC<imp-use>
	%VGPR8<def> = V_MAD_F32 %VGPR6, %VGPR6, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_MUL_F32_e64 %SGPR3, %VGPR60<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %SGPR4, %VGPR0<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %SGPR0, %VGPR61<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_RCP_F32_e32 %VGPR0<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR0, %EXEC<imp-use>
	%VGPR11<def> = V_MUL_F32_e32 %SGPR3<kill>, %VGPR0, %EXEC<imp-use>
	%VGPR5<def> = V_MUL_F32_e32 %VGPR5<kill>, %VGPR11<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR23<kill>, %VGPR9<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR0<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR10<kill>, %VGPR0<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR0, %VGPR0, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_RSQ_LEGACY_F32_e32 %VGPR5<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR0<kill>, %VGPR5, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %VGPR6<kill>, %VGPR5, %EXEC<imp-use>
	%VGPR5<def> = V_MUL_F32_e32 %VGPR7<kill>, %VGPR5<kill>, %EXEC<imp-use>
	EXP 15, 37, 0, 0, 0, %VGPR5<kill>, %VGPR6<kill>, %VGPR0<kill>, %VGPR13, %EXEC<imp-use>
	EXP 15, 38, 0, 0, 0, %VGPR13<kill>, %VGPR13, %VGPR15<kill>, %VGPR12<kill>, %EXEC<imp-use>
	S_WAITCNT 1807
	%VGPR0<def> = V_MUL_F32_e64 %VGPR57, %VGPR43<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR58, %VGPR42<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR56, %VGPR35<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR4, %VGPR31<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_MUL_F32_e64 %VGPR57, %VGPR41<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR58, %VGPR40<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR56, %VGPR34<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR4, %VGPR30<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e64 %VGPR57, %VGPR39<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR58, %VGPR38<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR56, %VGPR33<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR4, %VGPR29<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_MUL_F32_e64 %VGPR57<kill>, %VGPR37<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR58<kill>, %VGPR36<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR56<kill>, %VGPR32<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_MAD_F32 %VGPR4, %VGPR28<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR1_VGPR2_VGPR3_VGPR4<imp-use,kill>
	EXP 15, 12, 0, 1, 0, %VGPR1<kill>, %VGPR6<kill>, %VGPR5<kill>, %VGPR0<kill>, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_LOAD_DWORDX4 s[8:11], s[6:7], 4                        ; C0840704
	S_WAITCNT lgkmcnt(0)                                     ; BF8C007F
	BUFFER_LOAD_FORMAT_XYZW v[28:31], s[8:11][v0] + 0        ; E00C2000 80021C00
	S_LOAD_DWORDX4 s[44:47], s[0:1], 0                       ; C0960100
	S_WAITCNT vmcnt(0) lgkmcnt(0)                            ; BF8C0070
	S_BUFFER_LOAD_DWORD s0, s[44:47], 144                    ; C2002D90
	S_WAITCNT lgkmcnt(0)                                     ; BF8C007F
	V_MOV_B32_e32 v1, s0                                     ; 7E020200
	S_BUFFER_LOAD_DWORD s0, s[44:47], 146                    ; C2002D92
	S_WAITCNT lgkmcnt(0)                                     ; BF8C007F
	V_MOV_B32_e32 v23, s0                                    ; 7E2E0200
	V_MAD_F32 v10, v30, v23, v1, 0, 0, 0, 0                  ; D282000A 04062F1E
	V_MAD_F32 v5, v28, v23, v1, 0, 0, 0, 0                   ; D2820005 04062F1C
	S_LOAD_DWORDX4 s[0:3], s[6:7], 28                        ; C080071C
	S_WAITCNT lgkmcnt(0)                                     ; BF8C007F
	BUFFER_LOAD_FORMAT_XYZW v[6:9], s[0:3][v0] + 0           ; E00C2000 80000600
	S_LOAD_DWORDX4 s[0:3], s[6:7], 24                        ; C0800718
	S_WAITCNT vmcnt(0) lgkmcnt(0)                            ; BF8C0070
	BUFFER_LOAD_FORMAT_XYZW v[44:47], s[0:3][v0] + 0         ; E00C2000 80002C00
	S_LOAD_DWORDX4 s[0:3], s[6:7], 20                        ; C0800714
	S_WAITCNT vmcnt(0) lgkmcnt(0)                            ; BF8C0070
	BUFFER_LOAD_FORMAT_XYZW v[19:22], s[0:3][v0] + 0         ; E00C2000 80001300
	S_LOAD_DWORDX4 s[0:3], s[6:7], 16                        ; C0800710
	S_WAITCNT vmcnt(0) lgkmcnt(0)                            ; BF8C0070
	BUFFER_LOAD_FORMAT_XYZW v[15:18], s[0:3][v0] + 0         ; E00C2000 80000F00
	S_LOAD_DWORDX4 s[0:3], s[6:7], 12                        ; C080070C
	S_WAITCNT vmcnt(0) lgkmcnt(0)                            ; BF8C0070
	BUFFER_LOAD_FORMAT_XYZW v[11:14], s[0:3][v0] + 0         ; E00C2000 80000B00
	S_LOAD_DWORDX4 s[0:3], s[6:7], 8                         ; C0800708
	S_WAITCNT vmcnt(0) lgkmcnt(0)                            ; BF8C0070
	BUFFER_LOAD_FORMAT_XYZW v[24:27], s[0:3][v0] + 0         ; E00C2000 80001800
	S_LOAD_DWORDX4 s[0:3], s[6:7], 0                         ; C0800700
	S_WAITCNT vmcnt(0) lgkmcnt(0)                            ; BF8C0070
	BUFFER_LOAD_FORMAT_XYZW v[1:4], s[0:3][v0] + 0           ; E00C2000 80000100
	S_BUFFER_LOAD_DWORD s0, s[44:47], 145                    ; C2002D91
	S_WAITCNT vmcnt(0) lgkmcnt(0)                            ; BF8C0070
	V_MOV_B32_e32 v32, s0                                    ; 7E400200
	V_MAD_F32 v23, v29, v23, v32, 0, 0, 0, 0                 ; D2820017 04822F1D
	V_ADD_F32_e32 v23, 1.000000e-03, v23                     ; 062E2EFF 3A83126F
	S_MOV_B32 s0, 3840                                       ; BE8003FF 00000F00
	S_BUFFER_LOAD_DWORD s0, s[44:47], s0                     ; C2002C00
	S_WAITCNT lgkmcnt(0)                                     ; BF8C007F
	V_CMP_NE_I32_e64 s[62:63], s0, 0, 0, 0, 0, 0             ; D10A003E 02010000
	S_BUFFER_LOAD_DWORD s9, s[44:47], 138                    ; C204AD8A
	S_BUFFER_LOAD_DWORD s5, s[44:47], 137                    ; C202AD89
	S_BUFFER_LOAD_DWORD s8, s[44:47], 136                    ; C2042D88
	S_BUFFER_LOAD_DWORD s40, s[44:47], 134                   ; C2142D86
	S_BUFFER_LOAD_DWORD s38, s[44:47], 133                   ; C2132D85
	S_BUFFER_LOAD_DWORD s39, s[44:47], 132                   ; C213AD84
	S_BUFFER_LOAD_DWORD s37, s[44:47], 130                   ; C212AD82
	S_BUFFER_LOAD_DWORD s35, s[44:47], 129                   ; C211AD81
	S_BUFFER_LOAD_DWORD s36, s[44:47], 128                   ; C2122D80
	S_BUFFER_LOAD_DWORD s28, s[44:47], 126                   ; C20E2D7E
	S_BUFFER_LOAD_DWORD s18, s[44:47], 125                   ; C2092D7D
	S_BUFFER_LOAD_DWORD s27, s[44:47], 124                   ; C20DAD7C
	S_BUFFER_LOAD_DWORD s2, s[44:47], 122                    ; C2012D7A
	S_BUFFER_LOAD_DWORD s61, s[44:47], 121                   ; C21EAD79
	S_BUFFER_LOAD_DWORD s1, s[44:47], 120                    ; C200AD78
	S_BUFFER_LOAD_DWORD s64, s[44:47], 119                   ; C2202D77
	S_BUFFER_LOAD_DWORD s65, s[44:47], 118                   ; C220AD76
	S_BUFFER_LOAD_DWORD s66, s[44:47], 117                   ; C2212D75
	S_BUFFER_LOAD_DWORD s67, s[44:47], 116                   ; C221AD74
	S_BUFFER_LOAD_DWORD s25, s[44:47], 115                   ; C20CAD73
	S_BUFFER_LOAD_DWORD s29, s[44:47], 114                   ; C20EAD72
	S_BUFFER_LOAD_DWORD s31, s[44:47], 113                   ; C20FAD71
	S_BUFFER_LOAD_DWORD s32, s[44:47], 112                   ; C2102D70
	S_BUFFER_LOAD_DWORD s26, s[44:47], 111                   ; C20D2D6F
	S_BUFFER_LOAD_DWORD s30, s[44:47], 110                   ; C20F2D6E
	S_BUFFER_LOAD_DWORD s33, s[44:47], 109                   ; C210AD6D
	S_BUFFER_LOAD_DWORD s34, s[44:47], 108                   ; C2112D6C
	S_BUFFER_LOAD_DWORD s43, s[44:47], 107                   ; C215AD6B
	S_BUFFER_LOAD_DWORD s51, s[44:47], 106                   ; C219AD6A
	S_BUFFER_LOAD_DWORD s57, s[44:47], 105                   ; C21CAD69
	S_BUFFER_LOAD_DWORD s58, s[44:47], 104                   ; C21D2D68
	S_BUFFER_LOAD_DWORD s48, s[44:47], 103                   ; C2182D67
	S_BUFFER_LOAD_DWORD s52, s[44:47], 102                   ; C21A2D66
	S_BUFFER_LOAD_DWORD s59, s[44:47], 101                   ; C21DAD65
	S_BUFFER_LOAD_DWORD s60, s[44:47], 100                   ; C21E2D64
	S_BUFFER_LOAD_DWORD s16, s[44:47], 99                    ; C2082D63
	S_BUFFER_LOAD_DWORD s19, s[44:47], 98                    ; C209AD62
	S_BUFFER_LOAD_DWORD s21, s[44:47], 97                    ; C20AAD61
	S_BUFFER_LOAD_DWORD s22, s[44:47], 96                    ; C20B2D60
	S_BUFFER_LOAD_DWORD s17, s[44:47], 95                    ; C208AD5F
	S_BUFFER_LOAD_DWORD s20, s[44:47], 94                    ; C20A2D5E
	S_BUFFER_LOAD_DWORD s23, s[44:47], 93                    ; C20BAD5D
	S_BUFFER_LOAD_DWORD s24, s[44:47], 92                    ; C20C2D5C
	S_BUFFER_LOAD_DWORD s41, s[44:47], 35                    ; C214AD23
	S_BUFFER_LOAD_DWORD s49, s[44:47], 34                    ; C218AD22
	S_BUFFER_LOAD_DWORD s53, s[44:47], 33                    ; C21AAD21
	S_BUFFER_LOAD_DWORD s54, s[44:47], 32                    ; C21B2D20
	S_BUFFER_LOAD_DWORD s42, s[44:47], 31                    ; C2152D1F
	S_BUFFER_LOAD_DWORD s50, s[44:47], 30                    ; C2192D1E
	S_BUFFER_LOAD_DWORD s55, s[44:47], 29                    ; C21BAD1D
	S_BUFFER_LOAD_DWORD s56, s[44:47], 28                    ; C21C2D1C
	S_BUFFER_LOAD_DWORD s68, s[44:47], 27                    ; C2222D1B
	S_BUFFER_LOAD_DWORD s0, s[44:47], 26                     ; C2002D1A
	S_BUFFER_LOAD_DWORD s4, s[44:47], 25                     ; C2022D19
	S_BUFFER_LOAD_DWORD s3, s[44:47], 24                     ; C201AD18
	S_BUFFER_LOAD_DWORD s69, s[44:47], 23                    ; C222AD17
	S_BUFFER_LOAD_DWORD s13, s[44:47], 22                    ; C206AD16
	S_BUFFER_LOAD_DWORD s15, s[44:47], 21                    ; C207AD15
	S_BUFFER_LOAD_DWORD s14, s[44:47], 20                    ; C2072D14
	S_BUFFER_LOAD_DWORD s70, s[44:47], 19                    ; C2232D13
	S_BUFFER_LOAD_DWORD s10, s[44:47], 18                    ; C2052D12
	S_BUFFER_LOAD_DWORD s12, s[44:47], 17                    ; C2062D11
	S_BUFFER_LOAD_DWORD s11, s[44:47], 16                    ; C205AD10
	S_BUFFER_LOAD_DWORD s71, s[44:47], 15                    ; C223AD0F
	S_BUFFER_LOAD_DWORD s72, s[44:47], 14                    ; C2242D0E
	S_BUFFER_LOAD_DWORD s73, s[44:47], 13                    ; C224AD0D
	S_BUFFER_LOAD_DWORD s74, s[44:47], 12                    ; C2252D0C
	S_BUFFER_LOAD_DWORD s75, s[44:47], 11                    ; C225AD0B
	S_BUFFER_LOAD_DWORD s76, s[44:47], 10                    ; C2262D0A
	S_BUFFER_LOAD_DWORD s77, s[44:47], 9                     ; C226AD09
	S_BUFFER_LOAD_DWORD s78, s[44:47], 8                     ; C2272D08
	S_BUFFER_LOAD_DWORD s79, s[44:47], 7                     ; C227AD07
	S_BUFFER_LOAD_DWORD s80, s[44:47], 6                     ; C2282D06
	S_BUFFER_LOAD_DWORD s81, s[44:47], 5                     ; C228AD05
	S_BUFFER_LOAD_DWORD s82, s[44:47], 4                     ; C2292D04
	S_BUFFER_LOAD_DWORD s83, s[44:47], 3                     ; C229AD03
	S_BUFFER_LOAD_DWORD s84, s[44:47], 2                     ; C22A2D02
	S_BUFFER_LOAD_DWORD s85, s[44:47], 1                     ; C22AAD01
	S_BUFFER_LOAD_DWORD s86, s[44:47], 0                     ; C22B2D00
	S_WAITCNT lgkmcnt(0)                                     ; BF8C007F
	V_MOV_B32_e32 v48, s61                                   ; 7E60023D
	V_MOV_B32_e32 v50, s64                                   ; 7E640240
	V_MOV_B32_e32 v49, s65                                   ; 7E620241
	V_MOV_B32_e32 v52, s66                                   ; 7E680242
	V_MOV_B32_e32 v51, s67                                   ; 7E660243
	V_MOV_B32_e32 v55, s68                                   ; 7E6E0244
	V_MOV_B32_e32 v54, s69                                   ; 7E6C0245
	V_MOV_B32_e32 v53, s70                                   ; 7E6A0246
	V_MOV_B32_e32 v31, s71                                   ; 7E3E0247
	V_MOV_B32_e32 v35, s72                                   ; 7E460248
	V_MOV_B32_e32 v43, s73                                   ; 7E560249
	V_MOV_B32_e32 v42, s74                                   ; 7E54024A
	V_MOV_B32_e32 v30, s75                                   ; 7E3C024B
	V_MOV_B32_e32 v34, s76                                   ; 7E44024C
	V_MOV_B32_e32 v41, s77                                   ; 7E52024D
	V_MOV_B32_e32 v40, s78                                   ; 7E50024E
	V_MOV_B32_e32 v29, s79                                   ; 7E3A024F
	V_MOV_B32_e32 v33, s80                                   ; 7E420250
	V_MOV_B32_e32 v39, s81                                   ; 7E4E0251
	V_MOV_B32_e32 v38, s82                                   ; 7E4C0252
	V_MOV_B32_e32 v28, s83                                   ; 7E380253
	V_MOV_B32_e32 v32, s84                                   ; 7E400254
	V_MOV_B32_e32 v37, s85                                   ; 7E4A0255
	V_MOV_B32_e32 v36, s86                                   ; 7E480256
	V_MOV_B32_e32 v58, v1                                    ; 7E740301
	V_MOV_B32_e32 v57, v2                                    ; 7E720302
	V_MOV_B32_e32 v56, v3                                    ; 7E700303
	S_AND_SAVEEXEC_B64 s[62:63], s[62:63]                    ; BEBE243E
	S_XOR_B64 s[62:63], exec, s[62:63]                       ; 89BE3E7E
	S_CBRANCH_EXECZ ";.BB0_2"                                ; BF880000
	S_LOAD_DWORDX4 s[64:67], s[6:7], 32                      ; C0A00720
	S_WAITCNT lgkmcnt(0)                                     ; BF8C007F
	BUFFER_LOAD_FORMAT_XYZW v[56:59], s[64:67][v0] + 0       ; E00C2000 80103800
	V_MOV_B32_e32 v60, 2.550100e+02                          ; 7E7802FF 437F028F
	S_WAITCNT vmcnt(0)                                       ; BF8C0770
	V_MUL_F32_e32 v61, v56, v60                              ; 107A7938
	V_CVT_I32_F32_e32 v61, v61                               ; 7E7A113D
	V_MUL_LO_I32 v61, 3, v61, 0, 0, 0, 0, 0                  ; D2D6003D 02027A83
	V_ADD_I32_e32 v62, 43, v61                               ; 4A7C7AAB
	V_LSHLREV_B32_e32 v62, 4, v62                            ; 347C7C84
	V_OR_B32_e64 v63, 4, v62, 0, 0, 0, 0                     ; D238003F 02027C84
	BUFFER_LOAD_DWORD v63, s[44:47] + v63                    ; E0301000 800B3F3F
	S_LOAD_DWORDX4 s[64:67], s[6:7], 36                      ; C0A00724
	S_WAITCNT vmcnt(0) lgkmcnt(0)                            ; BF8C0070
	BUFFER_LOAD_FORMAT_XYZW v[64:67], s[64:67][v0] + 0       ; E00C2000 80104000
	S_WAITCNT vmcnt(0)                                       ; BF8C0770
	V_MUL_F32_e32 v0, v63, v64                               ; 1000813F
	V_MUL_F32_e32 v63, v57, v60                              ; 107E7939
	V_CVT_I32_F32_e32 v63, v63                               ; 7E7E113F
	V_MUL_LO_I32 v63, 3, v63, 0, 0, 0, 0, 0                  ; D2D6003F 02027E83
	V_ADD_I32_e32 v68, 43, v63                               ; 4A887EAB
	V_LSHLREV_B32_e32 v68, 4, v68                            ; 34888884
	V_OR_B32_e64 v69, 4, v68, 0, 0, 0, 0                     ; D2380045 02028884
	BUFFER_LOAD_DWORD v69, s[44:47] + v69                    ; E0301000 800B4545
	S_WAITCNT vmcnt(0)                                       ; BF8C0770
	V_MAD_F32 v0, v69, v65, v0, 0, 0, 0, 0                   ; D2820000 04028345
	V_MUL_F32_e32 v69, v58, v60                              ; 108A793A
	V_CVT_I32_F32_e32 v69, v69                               ; 7E8A1145
	V_MUL_LO_I32 v69, 3, v69, 0, 0, 0, 0, 0                  ; D2D60045 02028A83
	V_ADD_I32_e32 v70, 43, v69                               ; 4A8C8AAB
	V_LSHLREV_B32_e32 v70, 4, v70                            ; 348C8C84
	V_OR_B32_e64 v71, 4, v70, 0, 0, 0, 0                     ; D2380047 02028C84
	BUFFER_LOAD_DWORD v71, s[44:47] + v71                    ; E0301000 800B4747
	S_WAITCNT vmcnt(0)                                       ; BF8C0770
	V_MAD_F32 v0, v71, v66, v0, 0, 0, 0, 0                   ; D2820000 04028547
	V_ADD_F32_e32 v71, v65, v64                              ; 068E8141
	V_ADD_F32_e32 v71, v71, v66                              ; 068E8547
	V_SUB_F32_e32 v71, 1.000000e+00, v71                     ; 088E8EF2
	V_MUL_F32_e32 v56, v59, v60                              ; 1070793B
	V_CVT_I32_F32_e32 v56, v56                               ; 7E701138
	V_MUL_LO_I32 v56, 3, v56, 0, 0, 0, 0, 0                  ; D2D60038 02027083
	V_ADD_I32_e32 v57, 43, v56                               ; 4A7270AB
	V_LSHLREV_B32_e32 v57, 4, v57                            ; 34727284
	V_OR_B32_e64 v58, 4, v57, 0, 0, 0, 0                     ; D238003A 02027284
	BUFFER_LOAD_DWORD v58, s[44:47] + v58                    ; E0301000 800B3A3A
	S_WAITCNT vmcnt(0)                                       ; BF8C0770
	V_MAD_F32 v0, v58, v71, v0, 0, 0, 0, 0                   ; D2820000 04028F3A
	BUFFER_LOAD_DWORD v58, s[44:47] + v62                    ; E0301000 800B3A3E
	S_WAITCNT vmcnt(0)                                       ; BF8C0770
	V_MUL_F32_e32 v58, v58, v64                              ; 1074813A
	BUFFER_LOAD_DWORD v59, s[44:47] + v68                    ; E0301000 800B3B44
	S_WAITCNT vmcnt(0)                                       ; BF8C0770
	V_MAD_F32 v58, v59, v65, v58, 0, 0, 0, 0                 ; D282003A 04EA833B
	BUFFER_LOAD_DWORD v59, s[44:47] + v70                    ; E0301000 800B3B46
	S_WAITCNT vmcnt(0)                                       ; BF8C0770
	V_MAD_F32 v58, v59, v66, v58, 0, 0, 0, 0                 ; D282003A 04EA853B
	BUFFER_LOAD_DWORD v59, s[44:47] + v57                    ; E0301000 800B3B39
	S_WAITCNT vmcnt(0)                                       ; BF8C0770
	V_MAD_F32 v58, v59, v71, v58, 0, 0, 0, 0                 ; D282003A 04EA8F3B
	V_MUL_F32_e32 v59, v5, v58                               ; 10767505
	V_MAD_F32 v59, v23, v0, v59, 0, 0, 0, 0                  ; D282003B 04EE0117
	V_OR_B32_e64 v60, 8, v62, 0, 0, 0, 0                     ; D238003C 02027C88
	BUFFER_LOAD_DWORD v60, s[44:47] + v60                    ; E0301000 800B3C3C
	S_WAITCNT vmcnt(0)                                       ; BF8C0770
	V_MUL_F32_e32 v60, v60, v64                              ; 1078813C
	V_OR_B32_e64 v72, 8, v68, 0, 0, 0, 0                     ; D2380048 02028888
	BUFFER_LOAD_DWORD v72, s[44:47] + v72                    ; E0301000 800B4848
	S_WAITCNT vmcnt(0)                                       ; BF8C0770
	V_MAD_F32 v60, v72, v65, v60, 0, 0, 0, 0                 ; D282003C 04F28348
	V_OR_B32_e64 v72, 8, v70, 0, 0, 0, 0                     ; D2380048 02028C88
	BUFFER_LOAD_DWORD v72, s[44:47] + v72                    ; E0301000 800B4848
	S_WAITCNT vmcnt(0)                                       ; BF8C0770
	V_MAD_F32 v60, v72, v66, v60, 0, 0, 0, 0                 ; D282003C 04F28548
	V_OR_B32_e64 v72, 8, v57, 0, 0, 0, 0                     ; D2380048 02027288
	BUFFER_LOAD_DWORD v72, s[44:47] + v72                    ; E0301000 800B4848
	S_WAITCNT vmcnt(0)                                       ; BF8C0770
	V_MAD_F32 v60, v72, v71, v60, 0, 0, 0, 0                 ; D282003C 04F28F48
	V_MAD_F32 v59, v10, v60, v59, 0, 0, 0, 0                 ; D282003B 04EE790A
	V_ADD_I32_e32 v72, 42, v61                               ; 4A907AAA
	V_LSHLREV_B32_e32 v72, 4, v72                            ; 34909084
	V_OR_B32_e64 v73, 4, v72, 0, 0, 0, 0                     ; D2380049 02029084
	BUFFER_LOAD_DWORD v73, s[44:47] + v73                    ; E0301000 800B4949
	S_WAITCNT vmcnt(0)                                       ; BF8C0770
	V_MUL_F32_e32 v73, v73, v64                              ; 10928149
	V_ADD_I32_e32 v74, 42, v63                               ; 4A947EAA
	V_LSHLREV_B32_e32 v74, 4, v74                            ; 34949484
	V_OR_B32_e64 v75, 4, v74, 0, 0, 0, 0                     ; D238004B 02029484
	BUFFER_LOAD_DWORD v75, s[44:47] + v75                    ; E0301000 800B4B4B
	S_WAITCNT vmcnt(0)                                       ; BF8C0770
	V_MAD_F32 v73, v75, v65, v73, 0, 0, 0, 0                 ; D2820049 0526834B
	V_ADD_I32_e32 v75, 42, v69                               ; 4A968AAA
	V_LSHLREV_B32_e32 v75, 4, v75                            ; 34969684
	V_OR_B32_e64 v76, 4, v75, 0, 0, 0, 0                     ; D238004C 02029684
	BUFFER_LOAD_DWORD v76, s[44:47] + v76                    ; E0301000 800B4C4C
	S_WAITCNT vmcnt(0)                                       ; BF8C0770
	V_MAD_F32 v73, v76, v66, v73, 0, 0, 0, 0                 ; D2820049 0526854C
	V_ADD_I32_e32 v76, 42, v56                               ; 4A9870AA
	V_LSHLREV_B32_e32 v76, 4, v76                            ; 34989884
	V_OR_B32_e64 v77, 4, v76, 0, 0, 0, 0                     ; D238004D 02029884
	BUFFER_LOAD_DWORD v77, s[44:47] + v77                    ; E0301000 800B4D4D
	S_WAITCNT vmcnt(0)                                       ; BF8C0770
	V_MAD_F32 v73, v77, v71, v73, 0, 0, 0, 0                 ; D2820049 05268F4D
	BUFFER_LOAD_DWORD v77, s[44:47] + v72                    ; E0301000 800B4D48
	S_WAITCNT vmcnt(0)                                       ; BF8C0770
	V_MUL_F32_e32 v77, v77, v64                              ; 109A814D
	BUFFER_LOAD_DWORD v78, s[44:47] + v74                    ; E0301000 800B4E4A
	S_WAITCNT vmcnt(0)                                       ; BF8C0770
	V_MAD_F32 v77, v78, v65, v77, 0, 0, 0, 0                 ; D282004D 0536834E
	BUFFER_LOAD_DWORD v78, s[44:47] + v75                    ; E0301000 800B4E4B
	S_WAITCNT vmcnt(0)                                       ; BF8C0770
	V_MAD_F32 v77, v78, v66, v77, 0, 0, 0, 0                 ; D282004D 0536854E
	BUFFER_LOAD_DWORD v78, s[44:47] + v76                    ; E0301000 800B4E4C
	S_WAITCNT vmcnt(0)                                       ; BF8C0770
	V_MAD_F32 v77, v78, v71, v77, 0, 0, 0, 0                 ; D282004D 05368F4E
	V_MUL_F32_e32 v78, v5, v77                               ; 109C9B05
	V_MAD_F32 v78, v23, v73, v78, 0, 0, 0, 0                 ; D282004E 053A9317
	V_OR_B32_e64 v79, 8, v72, 0, 0, 0, 0                     ; D238004F 02029088
	BUFFER_LOAD_DWORD v79, s[44:47] + v79                    ; E0301000 800B4F4F
	S_WAITCNT vmcnt(0)                                       ; BF8C0770
	V_MUL_F32_e32 v79, v79, v64                              ; 109E814F
	V_OR_B32_e64 v80, 8, v74, 0, 0, 0, 0                     ; D2380050 02029488
	BUFFER_LOAD_DWORD v80, s[44:47] + v80                    ; E0301000 800B5050
	S_WAITCNT vmcnt(0)                                       ; BF8C0770
	V_MAD_F32 v79, v80, v65, v79, 0, 0, 0, 0                 ; D282004F 053E8350
	V_OR_B32_e64 v80, 8, v75, 0, 0, 0, 0                     ; D2380050 02029688
	BUFFER_LOAD_DWORD v80, s[44:47] + v80                    ; E0301000 800B5050
	S_WAITCNT vmcnt(0)                                       ; BF8C0770
	V_MAD_F32 v79, v80, v66, v79, 0, 0, 0, 0                 ; D282004F 053E8550
	V_OR_B32_e64 v80, 8, v76, 0, 0, 0, 0                     ; D2380050 02029888
	BUFFER_LOAD_DWORD v80, s[44:47] + v80                    ; E0301000 800B5050
	S_WAITCNT vmcnt(0)                                       ; BF8C0770
	V_MAD_F32 v79, v80, v71, v79, 0, 0, 0, 0                 ; D282004F 053E8F50
	V_MAD_F32 v78, v10, v79, v78, 0, 0, 0, 0                 ; D282004E 053A9F0A
	V_ADD_I32_e32 v61, 41, v61                               ; 4A7A7AA9
	V_LSHLREV_B32_e32 v61, 4, v61                            ; 347A7A84
	V_OR_B32_e64 v80, 4, v61, 0, 0, 0, 0                     ; D2380050 02027A84
	BUFFER_LOAD_DWORD v80, s[44:47] + v80                    ; E0301000 800B5050
	S_WAITCNT vmcnt(0)                                       ; BF8C0770
	V_MUL_F32_e32 v80, v80, v64                              ; 10A08150
	V_ADD_I32_e32 v63, 41, v63                               ; 4A7E7EA9
	V_LSHLREV_B32_e32 v63, 4, v63                            ; 347E7E84
	V_OR_B32_e64 v81, 4, v63, 0, 0, 0, 0                     ; D2380051 02027E84
	BUFFER_LOAD_DWORD v81, s[44:47] + v81                    ; E0301000 800B5151
	S_WAITCNT vmcnt(0)                                       ; BF8C0770
	V_MAD_F32 v80, v81, v65, v80, 0, 0, 0, 0                 ; D2820050 05428351
	V_ADD_I32_e32 v69, 41, v69                               ; 4A8A8AA9
	V_LSHLREV_B32_e32 v69, 4, v69                            ; 348A8A84
	V_OR_B32_e64 v81, 4, v69, 0, 0, 0, 0                     ; D2380051 02028A84
	BUFFER_LOAD_DWORD v81, s[44:47] + v81                    ; E0301000 800B5151
	S_WAITCNT vmcnt(0)                                       ; BF8C0770
	V_MAD_F32 v80, v81, v66, v80, 0, 0, 0, 0                 ; D2820050 05428551
	V_ADD_I32_e32 v56, 41, v56                               ; 4A7070A9
	V_LSHLREV_B32_e32 v81, 4, v56                            ; 34A27084
	V_OR_B32_e64 v56, 4, v81, 0, 0, 0, 0                     ; D2380038 0202A284
	BUFFER_LOAD_DWORD v56, s[44:47] + v56                    ; E0301000 800B3838
	S_WAITCNT vmcnt(0)                                       ; BF8C0770
	V_MAD_F32 v80, v56, v71, v80, 0, 0, 0, 0                 ; D2820050 05428F38
	BUFFER_LOAD_DWORD v56, s[44:47] + v61                    ; E0301000 800B383D
	S_WAITCNT vmcnt(0)                                       ; BF8C0770
	V_MUL_F32_e32 v56, v56, v64                              ; 10708138
	BUFFER_LOAD_DWORD v82, s[44:47] + v63                    ; E0301000 800B523F
	S_WAITCNT vmcnt(0)                                       ; BF8C0770
	V_MAD_F32 v56, v82, v65, v56, 0, 0, 0, 0                 ; D2820038 04E28352
	BUFFER_LOAD_DWORD v82, s[44:47] + v69                    ; E0301000 800B5245
	S_WAITCNT vmcnt(0)                                       ; BF8C0770
	V_MAD_F32 v56, v82, v66, v56, 0, 0, 0, 0                 ; D2820038 04E28552
	BUFFER_LOAD_DWORD v82, s[44:47] + v81                    ; E0301000 800B5251
	S_WAITCNT vmcnt(0)                                       ; BF8C0770
	V_MAD_F32 v82, v82, v71, v56, 0, 0, 0, 0                 ; D2820052 04E28F52
	V_MUL_F32_e32 v5, v5, v82                                ; 100AA505
	V_MAD_F32 v5, v23, v80, v5, 0, 0, 0, 0                   ; D2820005 0416A117
	V_OR_B32_e64 v23, 8, v61, 0, 0, 0, 0                     ; D2380017 02027A88
	BUFFER_LOAD_DWORD v23, s[44:47] + v23                    ; E0301000 800B1717
	S_WAITCNT vmcnt(0)                                       ; BF8C0770
	V_MUL_F32_e32 v23, v23, v64                              ; 102E8117
	V_OR_B32_e64 v56, 8, v63, 0, 0, 0, 0                     ; D2380038 02027E88
	BUFFER_LOAD_DWORD v56, s[44:47] + v56                    ; E0301000 800B3838
	S_WAITCNT vmcnt(0)                                       ; BF8C0770
	V_MAD_F32 v23, v56, v65, v23, 0, 0, 0, 0                 ; D2820017 045E8338
	V_OR_B32_e64 v56, 8, v69, 0, 0, 0, 0                     ; D2380038 02028A88
	BUFFER_LOAD_DWORD v56, s[44:47] + v56                    ; E0301000 800B3838
	S_WAITCNT vmcnt(0)                                       ; BF8C0770
	V_MAD_F32 v23, v56, v66, v23, 0, 0, 0, 0                 ; D2820017 045E8538
	V_OR_B32_e64 v56, 8, v81, 0, 0, 0, 0                     ; D2380038 0202A288
	BUFFER_LOAD_DWORD v56, s[44:47] + v56                    ; E0301000 800B3838
	S_WAITCNT vmcnt(0)                                       ; BF8C0770
	V_MAD_F32 v23, v56, v71, v23, 0, 0, 0, 0                 ; D2820017 045E8F38
	V_MAD_F32 v5, v10, v23, v5, 0, 0, 0, 0                   ; D2820005 04162F0A
	V_MUL_F32_e32 v0, v2, v0                                 ; 10000102
	V_MAD_F32 v0, v1, v58, v0, 0, 0, 0, 0                    ; D2820000 04027501
	V_MAD_F32 v0, v3, v60, v0, 0, 0, 0, 0                    ; D2820000 04027903
	V_OR_B32_e64 v10, 12, v62, 0, 0, 0, 0                    ; D238000A 02027C8C
	BUFFER_LOAD_DWORD v10, s[44:47] + v10                    ; E0301000 800B0A0A
	S_WAITCNT vmcnt(0)                                       ; BF8C0770
	V_MUL_F32_e32 v10, v10, v64                              ; 1014810A
	V_OR_B32_e64 v56, 12, v68, 0, 0, 0, 0                    ; D2380038 0202888C
	BUFFER_LOAD_DWORD v56, s[44:47] + v56                    ; E0301000 800B3838
	S_WAITCNT vmcnt(0)                                       ; BF8C0770
	V_MAD_F32 v10, v56, v65, v10, 0, 0, 0, 0                 ; D282000A 042A8338
	V_OR_B32_e64 v56, 12, v70, 0, 0, 0, 0                    ; D2380038 02028C8C
	BUFFER_LOAD_DWORD v56, s[44:47] + v56                    ; E0301000 800B3838
	S_WAITCNT vmcnt(0)                                       ; BF8C0770
	V_MAD_F32 v10, v56, v66, v10, 0, 0, 0, 0                 ; D282000A 042A8538
	V_OR_B32_e64 v56, 12, v57, 0, 0, 0, 0                    ; D2380038 0202728C
	BUFFER_LOAD_DWORD v56, s[44:47] + v56                    ; E0301000 800B3838
	S_WAITCNT vmcnt(0)                                       ; BF8C0770
	V_MAD_F32 v10, v56, v71, v10, 0, 0, 0, 0                 ; D282000A 042A8F38
	V_MAD_F32 v56, v4, v10, v0, 0, 0, 0, 0                   ; D2820038 04021504
	V_MUL_F32_e32 v0, v2, v73                                ; 10009302
	V_MAD_F32 v0, v1, v77, v0, 0, 0, 0, 0                    ; D2820000 04029B01
	V_MAD_F32 v0, v3, v79, v0, 0, 0, 0, 0                    ; D2820000 04029F03
	V_OR_B32_e64 v10, 12, v72, 0, 0, 0, 0                    ; D238000A 0202908C
	BUFFER_LOAD_DWORD v10, s[44:47] + v10                    ; E0301000 800B0A0A
	S_WAITCNT vmcnt(0)                                       ; BF8C0770
	V_MUL_F32_e32 v10, v10, v64                              ; 1014810A
	V_OR_B32_e64 v57, 12, v74, 0, 0, 0, 0                    ; D2380039 0202948C
	BUFFER_LOAD_DWORD v57, s[44:47] + v57                    ; E0301000 800B3939
	S_WAITCNT vmcnt(0)                                       ; BF8C0770
	V_MAD_F32 v10, v57, v65, v10, 0, 0, 0, 0                 ; D282000A 042A8339
	V_OR_B32_e64 v57, 12, v75, 0, 0, 0, 0                    ; D2380039 0202968C
	BUFFER_LOAD_DWORD v57, s[44:47] + v57                    ; E0301000 800B3939
	S_WAITCNT vmcnt(0)                                       ; BF8C0770
	V_MAD_F32 v10, v57, v66, v10, 0, 0, 0, 0                 ; D282000A 042A8539
	V_OR_B32_e64 v57, 12, v76, 0, 0, 0, 0                    ; D2380039 0202988C
	BUFFER_LOAD_DWORD v57, s[44:47] + v57                    ; E0301000 800B3939
	S_WAITCNT vmcnt(0)                                       ; BF8C0770
	V_MAD_F32 v10, v57, v71, v10, 0, 0, 0, 0                 ; D282000A 042A8F39
	V_MAD_F32 v57, v4, v10, v0, 0, 0, 0, 0                   ; D2820039 04021504
	V_MUL_F32_e32 v0, v2, v80                                ; 1000A102
	V_MAD_F32 v0, v1, v82, v0, 0, 0, 0, 0                    ; D2820000 0402A501
	V_MAD_F32 v0, v3, v23, v0, 0, 0, 0, 0                    ; D2820000 04022F03
	V_OR_B32_e64 v10, 12, v61, 0, 0, 0, 0                    ; D238000A 02027A8C
	BUFFER_LOAD_DWORD v10, s[44:47] + v10                    ; E0301000 800B0A0A
	S_WAITCNT vmcnt(0)                                       ; BF8C0770
	V_MUL_F32_e32 v10, v10, v64                              ; 1014810A
	V_OR_B32_e64 v23, 12, v63, 0, 0, 0, 0                    ; D2380017 02027E8C
	BUFFER_LOAD_DWORD v23, s[44:47] + v23                    ; E0301000 800B1717
	S_WAITCNT vmcnt(0)                                       ; BF8C0770
	V_MAD_F32 v10, v23, v65, v10, 0, 0, 0, 0                 ; D282000A 042A8317
	V_OR_B32_e64 v23, 12, v69, 0, 0, 0, 0                    ; D2380017 02028A8C
	BUFFER_LOAD_DWORD v23, s[44:47] + v23                    ; E0301000 800B1717
	S_WAITCNT vmcnt(0)                                       ; BF8C0770
	V_MAD_F32 v10, v23, v66, v10, 0, 0, 0, 0                 ; D282000A 042A8517
	V_OR_B32_e64 v23, 12, v81, 0, 0, 0, 0                    ; D2380017 0202A28C
	BUFFER_LOAD_DWORD v23, s[44:47] + v23                    ; E0301000 800B1717
	S_WAITCNT vmcnt(0)                                       ; BF8C0770
	V_MAD_F32 v10, v23, v71, v10, 0, 0, 0, 0                 ; D282000A 042A8F17
	V_MAD_F32 v58, v4, v10, v0, 0, 0, 0, 0                   ; D282003A 04021504
	V_MOV_B32_e32 v23, v78                                   ; 7E2E034E
	V_MOV_B32_e32 v10, v59                                   ; 7E14033B
	S_OR_B64 exec, exec, s[62:63]                            ; 88FE3E7E
	V_MOV_B32_e32 v0, s4                                     ; 7E000204
	V_MUL_F32_e64 v59, v57, v0, 0, 0, 0, 0                   ; D210003B 02020139
	V_MOV_B32_e32 v60, s3                                    ; 7E780203
	V_MAD_F32 v59, v58, v60, v59, 0, 0, 0, 0                 ; D282003B 04EE793A
	V_MOV_B32_e32 v61, s0                                    ; 7E7A0200
	V_MAD_F32 v59, v56, v61, v59, 0, 0, 0, 0                 ; D282003B 04EE7B38
	V_MAD_F32 v55, v4, v55, v59, 0, 0, 0, 0                  ; D2820037 04EE6F04
	V_MOV_B32_e32 v59, s15                                   ; 7E76020F
	V_MUL_F32_e64 v62, v57, v59, 0, 0, 0, 0                  ; D210003E 02027739
	V_MOV_B32_e32 v63, s14                                   ; 7E7E020E
	V_MAD_F32 v62, v58, v63, v62, 0, 0, 0, 0                 ; D282003E 04FA7F3A
	V_MOV_B32_e32 v64, s13                                   ; 7E80020D
	V_MAD_F32 v62, v56, v64, v62, 0, 0, 0, 0                 ; D282003E 04FA8138
	V_MAD_F32 v54, v4, v54, v62, 0, 0, 0, 0                  ; D2820036 04FA6D04
	V_MOV_B32_e32 v62, s12                                   ; 7E7C020C
	V_MUL_F32_e64 v65, v57, v62, 0, 0, 0, 0                  ; D2100041 02027D39
	V_MOV_B32_e32 v66, s11                                   ; 7E84020B
	V_MAD_F32 v65, v58, v66, v65, 0, 0, 0, 0                 ; D2820041 0506853A
	V_MOV_B32_e32 v67, s10                                   ; 7E86020A
	V_MAD_F32 v65, v56, v67, v65, 0, 0, 0, 0                 ; D2820041 05068738
	V_MAD_F32 v53, v4, v53, v65, 0, 0, 0, 0                  ; D2820035 05066B04
	V_MOV_B32_e32 v65, 1.000000e+00                          ; 7E8202F2
	EXP 15, 32, 0, 0, 0, v53, v54, v55, v65                  ; F800020F 41373635
	V_CMP_GE_F32_e64 s[6:7], s40, 0.000000e+00, 0, 0, 0, 0   ; D00C0006 02010028
	S_WAITCNT expcnt(0)                                      ; BF8C070F
	V_CNDMASK_B32_e64 v65, v44, v53, s[6:7], 0, 0, 0, 0      ; D2000041 001A6B2C
	V_CMP_GE_F32_e64 s[44:45], s39, 0.000000e+00, 0, 0, 0, 0 ; D00C002C 02010027
	V_CNDMASK_B32_e64 v65, v65, v55, s[44:45], 0, 0, 0, 0    ; D2000041 00B26F41
	V_CNDMASK_B32_e64 v44, v45, v54, s[6:7], 0, 0, 0, 0      ; D200002C 001A6D2D
	V_CMP_GE_F32_e64 s[6:7], s38, 0.000000e+00, 0, 0, 0, 0   ; D00C0006 02010026
	V_CNDMASK_B32_e64 v44, v44, v55, s[6:7], 0, 0, 0, 0      ; D200002C 001A6F2C
	V_MUL_F32_e32 v45, s57, v44                              ; 105A5839
	V_MAD_F32 v45, v65, s58, v45, 0, 0, 0, 0                 ; D282002D 04B47541
	V_MAD_F32 v45, s51, 0.000000e+00, v45, 0, 0, 0, 0        ; D282002D 04B50033
	V_ADD_F32_e32 v45, s43, v45                              ; 065A5A2B
	V_MUL_F32_e32 v44, s59, v44                              ; 1058583B
	V_MAD_F32 v44, v65, s60, v44, 0, 0, 0, 0                 ; D282002C 04B07941
	V_MAD_F32 v44, s52, 0.000000e+00, v44, 0, 0, 0, 0        ; D282002C 04B10034
	V_ADD_F32_e32 v44, s48, v44                              ; 06585830
	V_CMP_GE_F32_e64 s[6:7], s37, 0.000000e+00, 0, 0, 0, 0   ; D00C0006 02010025
	V_CNDMASK_B32_e64 v46, v24, v53, s[6:7], 0, 0, 0, 0      ; D200002E 001A6B18
	V_CMP_GE_F32_e64 s[36:37], s36, 0.000000e+00, 0, 0, 0, 0 ; D00C0024 02010024
	V_CNDMASK_B32_e64 v46, v46, v55, s[36:37], 0, 0, 0, 0    ; D200002E 00926F2E
	V_CNDMASK_B32_e64 v24, v25, v54, s[6:7], 0, 0, 0, 0      ; D2000018 001A6D19
	V_CMP_GE_F32_e64 s[6:7], s35, 0.000000e+00, 0, 0, 0, 0   ; D00C0006 02010023
	V_CNDMASK_B32_e64 v24, v24, v55, s[6:7], 0, 0, 0, 0      ; D2000018 001A6F18
	V_MUL_F32_e32 v25, s53, v24                              ; 10323035
	V_MAD_F32 v25, v46, s54, v25, 0, 0, 0, 0                 ; D2820019 04646D2E
	V_MAD_F32 v25, s49, 0.000000e+00, v25, 0, 0, 0, 0        ; D2820019 04650031
	V_ADD_F32_e32 v25, s41, v25                              ; 06323229
	V_MUL_F32_e32 v24, s55, v24                              ; 10303037
	V_MAD_F32 v24, v46, s56, v24, 0, 0, 0, 0                 ; D2820018 0460712E
	V_MAD_F32 v24, s50, 0.000000e+00, v24, 0, 0, 0, 0        ; D2820018 04610032
	V_ADD_F32_e32 v24, s42, v24                              ; 0630302A
	EXP 15, 33, 0, 0, 0, v24, v25, v44, v45                  ; F800021F 2D2C1918
	V_CMP_GE_F32_e64 s[6:7], s28, 0.000000e+00, 0, 0, 0, 0   ; D00C0006 0201001C
	S_WAITCNT expcnt(0)                                      ; BF8C070F
	V_CNDMASK_B32_e64 v24, v19, v53, s[6:7], 0, 0, 0, 0      ; D2000018 001A6B13
	V_CMP_GE_F32_e64 s[36:37], s27, 0.000000e+00, 0, 0, 0, 0 ; D00C0024 0201001B
	V_CNDMASK_B32_e64 v24, v24, v55, s[36:37], 0, 0, 0, 0    ; D2000018 00926F18
	V_CNDMASK_B32_e64 v19, v20, v54, s[6:7], 0, 0, 0, 0      ; D2000013 001A6D14
	V_CMP_GE_F32_e64 s[6:7], s18, 0.000000e+00, 0, 0, 0, 0   ; D00C0006 02010012
	V_CNDMASK_B32_e64 v19, v19, v55, s[6:7], 0, 0, 0, 0      ; D2000013 001A6F13
	V_MUL_F32_e32 v20, s31, v19                              ; 1028261F
	V_MAD_F32 v20, v24, s32, v20, 0, 0, 0, 0                 ; D2820014 04504118
	V_MAD_F32 v20, s29, 0.000000e+00, v20, 0, 0, 0, 0        ; D2820014 0451001D
	V_ADD_F32_e32 v20, s25, v20                              ; 06282819
	V_MUL_F32_e32 v19, s33, v19                              ; 10262621
	V_MAD_F32 v19, v24, s34, v19, 0, 0, 0, 0                 ; D2820013 044C4518
	V_MAD_F32 v19, s30, 0.000000e+00, v19, 0, 0, 0, 0        ; D2820013 044D001E
	V_ADD_F32_e32 v19, s26, v19                              ; 0626261A
	V_MAD_F32 v21, v16, v52, v50, 0, 0, 0, 0                 ; D2820015 04CA6910
	V_MAD_F32 v15, v15, v51, v49, 0, 0, 0, 0                 ; D282000F 04C6670F
	EXP 15, 34, 0, 0, 0, v15, v21, v19, v20                  ; F800022F 1413150F
	V_CMP_GE_F32_e64 s[6:7], s9, 0.000000e+00, 0, 0, 0, 0    ; D00C0006 02010009
	S_WAITCNT expcnt(0)                                      ; BF8C070F
	V_CNDMASK_B32_e64 v15, v11, v53, s[6:7], 0, 0, 0, 0      ; D200000F 001A6B0B
	V_CMP_GE_F32_e64 s[8:9], s8, 0.000000e+00, 0, 0, 0, 0    ; D00C0008 02010008
	V_CNDMASK_B32_e64 v15, v15, v55, s[8:9], 0, 0, 0, 0      ; D200000F 00226F0F
	V_CNDMASK_B32_e64 v11, v12, v54, s[6:7], 0, 0, 0, 0      ; D200000B 001A6D0C
	V_CMP_GE_F32_e64 s[6:7], s5, 0.000000e+00, 0, 0, 0, 0    ; D00C0006 02010005
	V_CNDMASK_B32_e64 v11, v11, v55, s[6:7], 0, 0, 0, 0      ; D200000B 001A6F0B
	V_MUL_F32_e32 v12, s21, v11                              ; 10181615
	V_MAD_F32 v12, v15, s22, v12, 0, 0, 0, 0                 ; D282000C 04302D0F
	V_MAD_F32 v12, s19, 0.000000e+00, v12, 0, 0, 0, 0        ; D282000C 04310013
	V_ADD_F32_e32 v12, s16, v12                              ; 06181810
	V_MUL_F32_e32 v11, s23, v11                              ; 10161617
	V_MAD_F32 v11, v15, s24, v11, 0, 0, 0, 0                 ; D282000B 042C310F
	V_MAD_F32 v11, s20, 0.000000e+00, v11, 0, 0, 0, 0        ; D282000B 042D0014
	V_ADD_F32_e32 v11, s17, v11                              ; 06161611
	V_MOV_B32_e32 v13, 0.000000e+00                          ; 7E1A0280
	EXP 15, 35, 0, 0, 0, v11, v12, v13, v13                  ; F800023F 0D0D0C0B
	S_WAITCNT expcnt(0)                                      ; BF8C070F
	V_MOV_B32_e32 v11, s2                                    ; 7E160202
	V_MAD_F32 v12, v9, v48, v11, 0, 0, 0, 0                  ; D282000C 042E6109
	V_MOV_B32_e32 v14, s1                                    ; 7E1C0201
	V_MAD_F32 v15, v6, v14, v11, 0, 0, 0, 0                  ; D282000F 042E1D06
	V_MUL_F32_e32 v16, v15, v15                              ; 10201F0F
	V_MAD_F32 v17, v7, v14, v11, 0, 0, 0, 0                  ; D2820011 042E1D07
	V_MUL_F32_e32 v17, v17, v17                              ; 10222311
	V_MAD_F32 v6, v8, v14, v11, 0, 0, 0, 0                   ; D2820006 042E1D08
	V_MUL_F32_e32 v6, v6, v6                                 ; 100C0D06
	EXP 15, 36, 0, 0, 0, v6, v17, v16, v12                   ; F800024F 0C101106
	S_WAITCNT expcnt(0)                                      ; BF8C070F
	V_MUL_F32_e64 v6, s14, v63, 0, 0, 0, 0                   ; D2100006 02027E0E
	V_MAD_F32 v6, s15, v59, v6, 0, 0, 0, 0                   ; D2820006 041A760F
	V_MAD_F32 v6, s13, v64, v6, 0, 0, 0, 0                   ; D2820006 041A800D
	V_RCP_F32_e32 v6, v6                                     ; 7E0C5506
	V_MUL_F32_e32 v7, s15, v6                                ; 100E0C0F
	V_MUL_F32_e32 v8, s14, v6                                ; 10100C0E
	V_MUL_F32_e32 v8, v5, v8                                 ; 10101105
	V_MAD_F32 v7, v23, v7, v8, 0, 0, 0, 0                    ; D2820007 04220F17
	V_MUL_F32_e32 v6, s13, v6                                ; 100C0C0D
	V_MAD_F32 v6, v10, v6, v7, 0, 0, 0, 0                    ; D2820006 041E0D0A
	V_MUL_F32_e64 v7, s11, v66, 0, 0, 0, 0                   ; D2100007 0202840B
	V_MAD_F32 v7, s12, v62, v7, 0, 0, 0, 0                   ; D2820007 041E7C0C
	V_MAD_F32 v7, s10, v67, v7, 0, 0, 0, 0                   ; D2820007 041E860A
	V_RCP_F32_e32 v7, v7                                     ; 7E0E5507
	V_MUL_F32_e32 v8, s12, v7                                ; 10100E0C
	V_MUL_F32_e32 v9, s11, v7                                ; 10120E0B
	V_MUL_F32_e32 v9, v5, v9                                 ; 10121305
	V_MAD_F32 v8, v23, v8, v9, 0, 0, 0, 0                    ; D2820008 04261117
	V_MUL_F32_e32 v7, s10, v7                                ; 100E0E0A
	V_MAD_F32 v7, v10, v7, v8, 0, 0, 0, 0                    ; D2820007 04220F0A
	V_MUL_F32_e32 v8, v7, v7                                 ; 10100F07
	V_MAD_F32 v8, v6, v6, v8, 0, 0, 0, 0                     ; D2820008 04220D06
	V_MUL_F32_e64 v9, s3, v60, 0, 0, 0, 0                    ; D2100009 02027803
	V_MAD_F32 v0, s4, v0, v9, 0, 0, 0, 0                     ; D2820000 04260004
	V_MAD_F32 v0, s0, v61, v0, 0, 0, 0, 0                    ; D2820000 04027A00
	V_RCP_F32_e32 v0, v0                                     ; 7E005500
	V_MUL_F32_e32 v9, s4, v0                                 ; 10120004
	V_MUL_F32_e32 v11, s3, v0                                ; 10160003
	V_MUL_F32_e32 v5, v5, v11                                ; 100A1705
	V_MAD_F32 v5, v23, v9, v5, 0, 0, 0, 0                    ; D2820005 04161317
	V_MUL_F32_e32 v0, s0, v0                                 ; 10000000
	V_MAD_F32 v0, v10, v0, v5, 0, 0, 0, 0                    ; D2820000 0416010A
	V_MAD_F32 v5, v0, v0, v8, 0, 0, 0, 0                     ; D2820005 04220100
	V_RSQ_LEGACY_F32_e32 v5, v5                              ; 7E0A5B05
	V_MUL_F32_e32 v0, v0, v5                                 ; 10000B00
	V_MUL_F32_e32 v6, v6, v5                                 ; 100C0B06
	V_MUL_F32_e32 v5, v7, v5                                 ; 100A0B07
	EXP 15, 37, 0, 0, 0, v5, v6, v0, v13                     ; F800025F 0D000605
	EXP 15, 38, 0, 0, 0, v13, v13, v15, v12                  ; F800026F 0C0F0D0D
	S_WAITCNT expcnt(0)                                      ; BF8C070F
	V_MUL_F32_e64 v0, v57, v43, 0, 0, 0, 0                   ; D2100000 02025739
	V_MAD_F32 v0, v58, v42, v0, 0, 0, 0, 0                   ; D2820000 0402553A
	V_MAD_F32 v0, v56, v35, v0, 0, 0, 0, 0                   ; D2820000 04024738
	V_MAD_F32 v0, v4, v31, v0, 0, 0, 0, 0                    ; D2820000 04023F04
	V_MUL_F32_e64 v5, v57, v41, 0, 0, 0, 0                   ; D2100005 02025339
	V_MAD_F32 v5, v58, v40, v5, 0, 0, 0, 0                   ; D2820005 0416513A
	V_MAD_F32 v5, v56, v34, v5, 0, 0, 0, 0                   ; D2820005 04164538
	V_MAD_F32 v5, v4, v30, v5, 0, 0, 0, 0                    ; D2820005 04163D04
	V_MUL_F32_e64 v6, v57, v39, 0, 0, 0, 0                   ; D2100006 02024F39
	V_MAD_F32 v6, v58, v38, v6, 0, 0, 0, 0                   ; D2820006 041A4D3A
	V_MAD_F32 v6, v56, v33, v6, 0, 0, 0, 0                   ; D2820006 041A4338
	V_MAD_F32 v6, v4, v29, v6, 0, 0, 0, 0                    ; D2820006 041A3B04
	V_MUL_F32_e64 v7, v57, v37, 0, 0, 0, 0                   ; D2100007 02024B39
	V_MAD_F32 v7, v58, v36, v7, 0, 0, 0, 0                   ; D2820007 041E493A
	V_MAD_F32 v7, v56, v32, v7, 0, 0, 0, 0                   ; D2820007 041E4138
	V_MAD_F32 v1, v4, v28, v7, 0, 0, 0, 0                    ; D2820001 041E3904
	EXP 15, 12, 0, 1, 0, v1, v6, v5, v0                      ; F80008CF 00050601
	S_ENDPGM                                                 ; BF810000

VERT
DCL IN[0]
DCL IN[1]
DCL IN[2]
DCL IN[3]
DCL IN[4]
DCL IN[5]
DCL IN[6]
DCL OUT[0], POSITION
DCL OUT[1], CLIPVERTEX
DCL OUT[2], GENERIC[19]
DCL OUT[3], GENERIC[20]
DCL OUT[4], GENERIC[21]
DCL CONST[0..240]
DCL TEMP[0..9], LOCAL
DCL ADDR[0]
IMM[0] FLT32 {    0.0010,     1.0000,   255.0100,    -0.1000}
IMM[1] INT32 {3, 41, 42, 43}
  0: MAD TEMP[0].xyz, IN[1].xyzz, CONST[10].zzzz, CONST[10].wwww
  1: MOV TEMP[1].xz, TEMP[0].xxzx
  2: ADD TEMP[0].x, TEMP[0].yyyy, IMM[0].xxxx
  3: MOV TEMP[1].y, TEMP[0].xxxx
  4: MOV TEMP[0], IN[0]
  5: MOV TEMP[2].xyz, TEMP[1].xyzx
  6: UIF CONST[240].xxxx :0
  7:   DP3 TEMP[3].x, IN[4].xyzz, IMM[0].yyyy
  8:   ADD TEMP[3].x, IMM[0].yyyy, -TEMP[3].xxxx
  9:   MUL TEMP[4], IN[3], IMM[0].zzzz
 10:   F2I TEMP[4], TEMP[4]
 11:   UMAD TEMP[5].x, TEMP[4].wwww, IMM[1].xxxx, IMM[1].yyyy
 12:   UMAD TEMP[6].x, TEMP[4].zzzz, IMM[1].xxxx, IMM[1].yyyy
 13:   UMAD TEMP[7].x, TEMP[4].yyyy, IMM[1].xxxx, IMM[1].yyyy
 14:   UMAD TEMP[8].x, TEMP[4].xxxx, IMM[1].xxxx, IMM[1].yyyy
 15:   UARL ADDR[0].x, TEMP[8].xxxx
 16:   MUL TEMP[8], CONST[ADDR[0].x], IN[4].xxxx
 17:   UARL ADDR[0].x, TEMP[7].xxxx
 18:   MAD TEMP[7], CONST[ADDR[0].x], IN[4].yyyy, TEMP[8]
 19:   UARL ADDR[0].x, TEMP[6].xxxx
 20:   MAD TEMP[6], CONST[ADDR[0].x], IN[4].zzzz, TEMP[7]
 21:   UARL ADDR[0].x, TEMP[5].xxxx
 22:   UARL ADDR[0].x, TEMP[5].xxxx
 23:   MAD TEMP[5], CONST[ADDR[0].x], TEMP[3].xxxx, TEMP[6]
 24:   UMAD TEMP[6].x, TEMP[4].wwww, IMM[1].xxxx, IMM[1].zzzz
 25:   UMAD TEMP[7].x, TEMP[4].zzzz, IMM[1].xxxx, IMM[1].zzzz
 26:   UMAD TEMP[8].x, TEMP[4].yyyy, IMM[1].xxxx, IMM[1].zzzz
 27:   UMAD TEMP[9].x, TEMP[4].xxxx, IMM[1].xxxx, IMM[1].zzzz
 28:   UARL ADDR[0].x, TEMP[9].xxxx
 29:   MUL TEMP[9], CONST[ADDR[0].x], IN[4].xxxx
 30:   UARL ADDR[0].x, TEMP[8].xxxx
 31:   MAD TEMP[8], CONST[ADDR[0].x], IN[4].yyyy, TEMP[9]
 32:   UARL ADDR[0].x, TEMP[7].xxxx
 33:   MAD TEMP[7], CONST[ADDR[0].x], IN[4].zzzz, TEMP[8]
 34:   UARL ADDR[0].x, TEMP[6].xxxx
 35:   UARL ADDR[0].x, TEMP[6].xxxx
 36:   MAD TEMP[6], CONST[ADDR[0].x], TEMP[3].xxxx, TEMP[7]
 37:   UMAD TEMP[7].x, TEMP[4].wwww, IMM[1].xxxx, IMM[1].wwww
 38:   UMAD TEMP[8].x, TEMP[4].zzzz, IMM[1].xxxx, IMM[1].wwww
 39:   UMAD TEMP[9].x, TEMP[4].yyyy, IMM[1].xxxx, IMM[1].wwww
 40:   UMAD TEMP[4].x, TEMP[4].xxxx, IMM[1].xxxx, IMM[1].wwww
 41:   UARL ADDR[0].x, TEMP[4].xxxx
 42:   MUL TEMP[4], CONST[ADDR[0].x], IN[4].xxxx
 43:   UARL ADDR[0].x, TEMP[9].xxxx
 44:   MAD TEMP[4], CONST[ADDR[0].x], IN[4].yyyy, TEMP[4]
 45:   UARL ADDR[0].x, TEMP[8].xxxx
 46:   MAD TEMP[4], CONST[ADDR[0].x], IN[4].zzzz, TEMP[4]
 47:   UARL ADDR[0].x, TEMP[7].xxxx
 48:   UARL ADDR[0].x, TEMP[7].xxxx
 49:   MAD TEMP[3], CONST[ADDR[0].x], TEMP[3].xxxx, TEMP[4]
 50:   DP4 TEMP[4].x, IN[0], TEMP[5]
 51:   DP4 TEMP[7].x, IN[0], TEMP[6]
 52:   MOV TEMP[4].y, TEMP[7].xxxx
 53:   DP4 TEMP[7].x, IN[0], TEMP[3]
 54:   MOV TEMP[4].z, TEMP[7].xxxx
 55:   MOV TEMP[0].xyz, TEMP[4].xyzx
 56:   DP3 TEMP[4].x, TEMP[1].xyzz, TEMP[5].xyzz
 57:   DP3 TEMP[5].x, TEMP[1].xyzz, TEMP[6].xyzz
 58:   MOV TEMP[4].y, TEMP[5].xxxx
 59:   DP3 TEMP[1].x, TEMP[1].xyzz, TEMP[3].xyzz
 60:   MOV TEMP[4].z, TEMP[1].xxxx
 61:   MOV TEMP[2].xyz, TEMP[4].xyzx
 62: ENDIF
 63: DP4 TEMP[1].x, TEMP[0], CONST[0]
 64: DP4 TEMP[3].x, TEMP[0], CONST[1]
 65: MOV TEMP[1].y, TEMP[3].xxxx
 66: DP4 TEMP[3].x, TEMP[0], CONST[2]
 67: MOV TEMP[1].z, TEMP[3].xxxx
 68: DP4 TEMP[3].x, TEMP[0], CONST[3]
 69: MOV TEMP[1].w, TEMP[3].xxxx
 70: DP3 TEMP[3].x, TEMP[2].xyzz, CONST[4].xyzz
 71: DP3 TEMP[4].x, TEMP[2].xyzz, CONST[5].xyzz
 72: DP3 TEMP[2].x, TEMP[2].xyzz, CONST[6].xyzz
 73: MOV TEMP[3].z, TEMP[2].xxxx
 74: MOV TEMP[2].xz, TEMP[3].xxzx
 75: MOV TEMP[2].y, -TEMP[4].xxxx
 76: DP4 TEMP[0].x, TEMP[0], CONST[9]
 77: ADD TEMP[0].x, TEMP[0].xxxx, IMM[0].wwww
 78: MOV TEMP[2].w, TEMP[0].xxxx
 79: DP4 TEMP[0].x, IN[2], CONST[7]
 80: DP4 TEMP[3].x, IN[2], CONST[8]
 81: MOV TEMP[0].y, TEMP[3].xxxx
 82: MOV TEMP[0].xy, TEMP[0].xyxx
 83: MOV TEMP[0].zw, IN[5].yyxy
 84: MAD TEMP[3], IN[6].zyxw, CONST[10].xxxx, CONST[10].yyyy
 85: MOV TEMP[4].w, TEMP[3].wwww
 86: MUL TEMP[4].xyz, TEMP[3].xyzz, TEMP[3].xyzz
 87: LRP TEMP[4].xyz, TEMP[3].wwww, TEMP[4].xyzz, IMM[0].yyyy
 88: MOV OUT[2], TEMP[0]
 89: MOV OUT[3], TEMP[2]
 90: MOV OUT[0], TEMP[1]
 91: MOV OUT[4], TEMP[4]
 92: MOV OUT[1], TEMP[1]
 93: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0)
  %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4)
  %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8)
  %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12)
  %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16)
  %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20)
  %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24)
  %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28)
  %20 = call float @llvm.SI.load.const(<16 x i8> %11, i32 32)
  %21 = call float @llvm.SI.load.const(<16 x i8> %11, i32 36)
  %22 = call float @llvm.SI.load.const(<16 x i8> %11, i32 40)
  %23 = call float @llvm.SI.load.const(<16 x i8> %11, i32 44)
  %24 = call float @llvm.SI.load.const(<16 x i8> %11, i32 48)
  %25 = call float @llvm.SI.load.const(<16 x i8> %11, i32 52)
  %26 = call float @llvm.SI.load.const(<16 x i8> %11, i32 56)
  %27 = call float @llvm.SI.load.const(<16 x i8> %11, i32 60)
  %28 = call float @llvm.SI.load.const(<16 x i8> %11, i32 64)
  %29 = call float @llvm.SI.load.const(<16 x i8> %11, i32 68)
  %30 = call float @llvm.SI.load.const(<16 x i8> %11, i32 72)
  %31 = call float @llvm.SI.load.const(<16 x i8> %11, i32 80)
  %32 = call float @llvm.SI.load.const(<16 x i8> %11, i32 84)
  %33 = call float @llvm.SI.load.const(<16 x i8> %11, i32 88)
  %34 = call float @llvm.SI.load.const(<16 x i8> %11, i32 96)
  %35 = call float @llvm.SI.load.const(<16 x i8> %11, i32 100)
  %36 = call float @llvm.SI.load.const(<16 x i8> %11, i32 104)
  %37 = call float @llvm.SI.load.const(<16 x i8> %11, i32 112)
  %38 = call float @llvm.SI.load.const(<16 x i8> %11, i32 116)
  %39 = call float @llvm.SI.load.const(<16 x i8> %11, i32 120)
  %40 = call float @llvm.SI.load.const(<16 x i8> %11, i32 124)
  %41 = call float @llvm.SI.load.const(<16 x i8> %11, i32 128)
  %42 = call float @llvm.SI.load.const(<16 x i8> %11, i32 132)
  %43 = call float @llvm.SI.load.const(<16 x i8> %11, i32 136)
  %44 = call float @llvm.SI.load.const(<16 x i8> %11, i32 140)
  %45 = call float @llvm.SI.load.const(<16 x i8> %11, i32 144)
  %46 = call float @llvm.SI.load.const(<16 x i8> %11, i32 148)
  %47 = call float @llvm.SI.load.const(<16 x i8> %11, i32 152)
  %48 = call float @llvm.SI.load.const(<16 x i8> %11, i32 156)
  %49 = call float @llvm.SI.load.const(<16 x i8> %11, i32 160)
  %50 = call float @llvm.SI.load.const(<16 x i8> %11, i32 164)
  %51 = call float @llvm.SI.load.const(<16 x i8> %11, i32 168)
  %52 = call float @llvm.SI.load.const(<16 x i8> %11, i32 172)
  %53 = call float @llvm.SI.load.const(<16 x i8> %11, i32 3840)
  %54 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0
  %55 = load <16 x i8> addrspace(2)* %54, !tbaa !0
  %56 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %55, i32 0, i32 %6)
  %57 = extractelement <4 x float> %56, i32 0
  %58 = extractelement <4 x float> %56, i32 1
  %59 = extractelement <4 x float> %56, i32 2
  %60 = extractelement <4 x float> %56, i32 3
  %61 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 1
  %62 = load <16 x i8> addrspace(2)* %61, !tbaa !0
  %63 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %62, i32 0, i32 %6)
  %64 = extractelement <4 x float> %63, i32 0
  %65 = extractelement <4 x float> %63, i32 1
  %66 = extractelement <4 x float> %63, i32 2
  %67 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 2
  %68 = load <16 x i8> addrspace(2)* %67, !tbaa !0
  %69 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %68, i32 0, i32 %6)
  %70 = extractelement <4 x float> %69, i32 0
  %71 = extractelement <4 x float> %69, i32 1
  %72 = extractelement <4 x float> %69, i32 2
  %73 = extractelement <4 x float> %69, i32 3
  %74 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 3
  %75 = load <16 x i8> addrspace(2)* %74, !tbaa !0
  %76 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %75, i32 0, i32 %6)
  %77 = extractelement <4 x float> %76, i32 0
  %78 = extractelement <4 x float> %76, i32 1
  %79 = extractelement <4 x float> %76, i32 2
  %80 = extractelement <4 x float> %76, i32 3
  %81 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 4
  %82 = load <16 x i8> addrspace(2)* %81, !tbaa !0
  %83 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %82, i32 0, i32 %6)
  %84 = extractelement <4 x float> %83, i32 0
  %85 = extractelement <4 x float> %83, i32 1
  %86 = extractelement <4 x float> %83, i32 2
  %87 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 5
  %88 = load <16 x i8> addrspace(2)* %87, !tbaa !0
  %89 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %88, i32 0, i32 %6)
  %90 = extractelement <4 x float> %89, i32 0
  %91 = extractelement <4 x float> %89, i32 1
  %92 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 6
  %93 = load <16 x i8> addrspace(2)* %92, !tbaa !0
  %94 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %93, i32 0, i32 %6)
  %95 = extractelement <4 x float> %94, i32 0
  %96 = extractelement <4 x float> %94, i32 1
  %97 = extractelement <4 x float> %94, i32 2
  %98 = extractelement <4 x float> %94, i32 3
  %99 = fmul float %64, %51
  %100 = fadd float %99, %52
  %101 = fmul float %65, %51
  %102 = fadd float %101, %52
  %103 = fmul float %66, %51
  %104 = fadd float %103, %52
  %105 = fadd float %102, 0x3F50624DE0000000
  %106 = bitcast float %53 to i32
  %107 = icmp ne i32 %106, 0
  br i1 %107, label %IF, label %ENDIF

IF:                                               ; preds = %main_body
  %108 = fmul float %84, 1.000000e+00
  %109 = fmul float %85, 1.000000e+00
  %110 = fadd float %109, %108
  %111 = fmul float %86, 1.000000e+00
  %112 = fadd float %110, %111
  %113 = fsub float -0.000000e+00, %112
  %114 = fadd float 1.000000e+00, %113
  %115 = fmul float %77, 0x406FE051E0000000
  %116 = fmul float %78, 0x406FE051E0000000
  %117 = fmul float %79, 0x406FE051E0000000
  %118 = fmul float %80, 0x406FE051E0000000
  %119 = fptosi float %115 to i32
  %120 = fptosi float %116 to i32
  %121 = fptosi float %117 to i32
  %122 = fptosi float %118 to i32
  %123 = bitcast i32 %119 to float
  %124 = bitcast i32 %120 to float
  %125 = bitcast i32 %121 to float
  %126 = bitcast i32 %122 to float
  %127 = bitcast float %126 to i32
  %128 = mul i32 %127, 3
  %129 = add i32 %128, 41
  %130 = bitcast i32 %129 to float
  %131 = bitcast float %125 to i32
  %132 = mul i32 %131, 3
  %133 = add i32 %132, 41
  %134 = bitcast i32 %133 to float
  %135 = bitcast float %124 to i32
  %136 = mul i32 %135, 3
  %137 = add i32 %136, 41
  %138 = bitcast i32 %137 to float
  %139 = bitcast float %123 to i32
  %140 = mul i32 %139, 3
  %141 = add i32 %140, 41
  %142 = bitcast i32 %141 to float
  %143 = bitcast float %142 to i32
  %144 = shl i32 %143, 4
  %145 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %144)
  %146 = fmul float %145, %84
  %147 = shl i32 %143, 4
  %148 = add i32 %147, 4
  %149 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %148)
  %150 = fmul float %149, %84
  %151 = shl i32 %143, 4
  %152 = add i32 %151, 8
  %153 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %152)
  %154 = fmul float %153, %84
  %155 = shl i32 %143, 4
  %156 = add i32 %155, 12
  %157 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %156)
  %158 = fmul float %157, %84
  %159 = bitcast float %138 to i32
  %160 = shl i32 %159, 4
  %161 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %160)
  %162 = fmul float %161, %85
  %163 = fadd float %162, %146
  %164 = shl i32 %159, 4
  %165 = add i32 %164, 4
  %166 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %165)
  %167 = fmul float %166, %85
  %168 = fadd float %167, %150
  %169 = shl i32 %159, 4
  %170 = add i32 %169, 8
  %171 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %170)
  %172 = fmul float %171, %85
  %173 = fadd float %172, %154
  %174 = shl i32 %159, 4
  %175 = add i32 %174, 12
  %176 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %175)
  %177 = fmul float %176, %85
  %178 = fadd float %177, %158
  %179 = bitcast float %134 to i32
  %180 = shl i32 %179, 4
  %181 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %180)
  %182 = fmul float %181, %86
  %183 = fadd float %182, %163
  %184 = shl i32 %179, 4
  %185 = add i32 %184, 4
  %186 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %185)
  %187 = fmul float %186, %86
  %188 = fadd float %187, %168
  %189 = shl i32 %179, 4
  %190 = add i32 %189, 8
  %191 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %190)
  %192 = fmul float %191, %86
  %193 = fadd float %192, %173
  %194 = shl i32 %179, 4
  %195 = add i32 %194, 12
  %196 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %195)
  %197 = fmul float %196, %86
  %198 = fadd float %197, %178
  %199 = bitcast float %130 to i32
  %200 = shl i32 %199, 4
  %201 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %200)
  %202 = fmul float %201, %114
  %203 = fadd float %202, %183
  %204 = shl i32 %199, 4
  %205 = add i32 %204, 4
  %206 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %205)
  %207 = fmul float %206, %114
  %208 = fadd float %207, %188
  %209 = shl i32 %199, 4
  %210 = add i32 %209, 8
  %211 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %210)
  %212 = fmul float %211, %114
  %213 = fadd float %212, %193
  %214 = shl i32 %199, 4
  %215 = add i32 %214, 12
  %216 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %215)
  %217 = fmul float %216, %114
  %218 = fadd float %217, %198
  %219 = bitcast float %126 to i32
  %220 = mul i32 %219, 3
  %221 = add i32 %220, 42
  %222 = bitcast i32 %221 to float
  %223 = bitcast float %125 to i32
  %224 = mul i32 %223, 3
  %225 = add i32 %224, 42
  %226 = bitcast i32 %225 to float
  %227 = bitcast float %124 to i32
  %228 = mul i32 %227, 3
  %229 = add i32 %228, 42
  %230 = bitcast i32 %229 to float
  %231 = bitcast float %123 to i32
  %232 = mul i32 %231, 3
  %233 = add i32 %232, 42
  %234 = bitcast i32 %233 to float
  %235 = bitcast float %234 to i32
  %236 = shl i32 %235, 4
  %237 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %236)
  %238 = fmul float %237, %84
  %239 = shl i32 %235, 4
  %240 = add i32 %239, 4
  %241 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %240)
  %242 = fmul float %241, %84
  %243 = shl i32 %235, 4
  %244 = add i32 %243, 8
  %245 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %244)
  %246 = fmul float %245, %84
  %247 = shl i32 %235, 4
  %248 = add i32 %247, 12
  %249 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %248)
  %250 = fmul float %249, %84
  %251 = bitcast float %230 to i32
  %252 = shl i32 %251, 4
  %253 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %252)
  %254 = fmul float %253, %85
  %255 = fadd float %254, %238
  %256 = shl i32 %251, 4
  %257 = add i32 %256, 4
  %258 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %257)
  %259 = fmul float %258, %85
  %260 = fadd float %259, %242
  %261 = shl i32 %251, 4
  %262 = add i32 %261, 8
  %263 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %262)
  %264 = fmul float %263, %85
  %265 = fadd float %264, %246
  %266 = shl i32 %251, 4
  %267 = add i32 %266, 12
  %268 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %267)
  %269 = fmul float %268, %85
  %270 = fadd float %269, %250
  %271 = bitcast float %226 to i32
  %272 = shl i32 %271, 4
  %273 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %272)
  %274 = fmul float %273, %86
  %275 = fadd float %274, %255
  %276 = shl i32 %271, 4
  %277 = add i32 %276, 4
  %278 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %277)
  %279 = fmul float %278, %86
  %280 = fadd float %279, %260
  %281 = shl i32 %271, 4
  %282 = add i32 %281, 8
  %283 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %282)
  %284 = fmul float %283, %86
  %285 = fadd float %284, %265
  %286 = shl i32 %271, 4
  %287 = add i32 %286, 12
  %288 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %287)
  %289 = fmul float %288, %86
  %290 = fadd float %289, %270
  %291 = bitcast float %222 to i32
  %292 = shl i32 %291, 4
  %293 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %292)
  %294 = fmul float %293, %114
  %295 = fadd float %294, %275
  %296 = shl i32 %291, 4
  %297 = add i32 %296, 4
  %298 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %297)
  %299 = fmul float %298, %114
  %300 = fadd float %299, %280
  %301 = shl i32 %291, 4
  %302 = add i32 %301, 8
  %303 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %302)
  %304 = fmul float %303, %114
  %305 = fadd float %304, %285
  %306 = shl i32 %291, 4
  %307 = add i32 %306, 12
  %308 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %307)
  %309 = fmul float %308, %114
  %310 = fadd float %309, %290
  %311 = bitcast float %126 to i32
  %312 = mul i32 %311, 3
  %313 = add i32 %312, 43
  %314 = bitcast i32 %313 to float
  %315 = bitcast float %125 to i32
  %316 = mul i32 %315, 3
  %317 = add i32 %316, 43
  %318 = bitcast i32 %317 to float
  %319 = bitcast float %124 to i32
  %320 = mul i32 %319, 3
  %321 = add i32 %320, 43
  %322 = bitcast i32 %321 to float
  %323 = bitcast float %123 to i32
  %324 = mul i32 %323, 3
  %325 = add i32 %324, 43
  %326 = bitcast i32 %325 to float
  %327 = bitcast float %326 to i32
  %328 = shl i32 %327, 4
  %329 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %328)
  %330 = fmul float %329, %84
  %331 = shl i32 %327, 4
  %332 = add i32 %331, 4
  %333 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %332)
  %334 = fmul float %333, %84
  %335 = shl i32 %327, 4
  %336 = add i32 %335, 8
  %337 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %336)
  %338 = fmul float %337, %84
  %339 = shl i32 %327, 4
  %340 = add i32 %339, 12
  %341 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %340)
  %342 = fmul float %341, %84
  %343 = bitcast float %322 to i32
  %344 = shl i32 %343, 4
  %345 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %344)
  %346 = fmul float %345, %85
  %347 = fadd float %346, %330
  %348 = shl i32 %343, 4
  %349 = add i32 %348, 4
  %350 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %349)
  %351 = fmul float %350, %85
  %352 = fadd float %351, %334
  %353 = shl i32 %343, 4
  %354 = add i32 %353, 8
  %355 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %354)
  %356 = fmul float %355, %85
  %357 = fadd float %356, %338
  %358 = shl i32 %343, 4
  %359 = add i32 %358, 12
  %360 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %359)
  %361 = fmul float %360, %85
  %362 = fadd float %361, %342
  %363 = bitcast float %318 to i32
  %364 = shl i32 %363, 4
  %365 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %364)
  %366 = fmul float %365, %86
  %367 = fadd float %366, %347
  %368 = shl i32 %363, 4
  %369 = add i32 %368, 4
  %370 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %369)
  %371 = fmul float %370, %86
  %372 = fadd float %371, %352
  %373 = shl i32 %363, 4
  %374 = add i32 %373, 8
  %375 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %374)
  %376 = fmul float %375, %86
  %377 = fadd float %376, %357
  %378 = shl i32 %363, 4
  %379 = add i32 %378, 12
  %380 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %379)
  %381 = fmul float %380, %86
  %382 = fadd float %381, %362
  %383 = bitcast float %314 to i32
  %384 = shl i32 %383, 4
  %385 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %384)
  %386 = fmul float %385, %114
  %387 = fadd float %386, %367
  %388 = shl i32 %383, 4
  %389 = add i32 %388, 4
  %390 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %389)
  %391 = fmul float %390, %114
  %392 = fadd float %391, %372
  %393 = shl i32 %383, 4
  %394 = add i32 %393, 8
  %395 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %394)
  %396 = fmul float %395, %114
  %397 = fadd float %396, %377
  %398 = shl i32 %383, 4
  %399 = add i32 %398, 12
  %400 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %399)
  %401 = fmul float %400, %114
  %402 = fadd float %401, %382
  %403 = fmul float %57, %203
  %404 = fmul float %58, %208
  %405 = fadd float %403, %404
  %406 = fmul float %59, %213
  %407 = fadd float %405, %406
  %408 = fmul float %60, %218
  %409 = fadd float %407, %408
  %410 = fmul float %57, %295
  %411 = fmul float %58, %300
  %412 = fadd float %410, %411
  %413 = fmul float %59, %305
  %414 = fadd float %412, %413
  %415 = fmul float %60, %310
  %416 = fadd float %414, %415
  %417 = fmul float %57, %387
  %418 = fmul float %58, %392
  %419 = fadd float %417, %418
  %420 = fmul float %59, %397
  %421 = fadd float %419, %420
  %422 = fmul float %60, %402
  %423 = fadd float %421, %422
  %424 = fmul float %100, %203
  %425 = fmul float %105, %208
  %426 = fadd float %425, %424
  %427 = fmul float %104, %213
  %428 = fadd float %426, %427
  %429 = fmul float %100, %295
  %430 = fmul float %105, %300
  %431 = fadd float %430, %429
  %432 = fmul float %104, %305
  %433 = fadd float %431, %432
  %434 = fmul float %100, %387
  %435 = fmul float %105, %392
  %436 = fadd float %435, %434
  %437 = fmul float %104, %397
  %438 = fadd float %436, %437
  br label %ENDIF

ENDIF:                                            ; preds = %main_body, %IF
  %temp.0 = phi float [ %409, %IF ], [ %57, %main_body ]
  %temp1.0 = phi float [ %416, %IF ], [ %58, %main_body ]
  %temp2.0 = phi float [ %423, %IF ], [ %59, %main_body ]
  %temp8.0 = phi float [ %428, %IF ], [ %100, %main_body ]
  %temp9.0 = phi float [ %433, %IF ], [ %105, %main_body ]
  %temp10.0 = phi float [ %438, %IF ], [ %104, %main_body ]
  %439 = fmul float %temp.0, %12
  %440 = fmul float %temp1.0, %13
  %441 = fadd float %439, %440
  %442 = fmul float %temp2.0, %14
  %443 = fadd float %441, %442
  %444 = fmul float %60, %15
  %445 = fadd float %443, %444
  %446 = fmul float %temp.0, %16
  %447 = fmul float %temp1.0, %17
  %448 = fadd float %446, %447
  %449 = fmul float %temp2.0, %18
  %450 = fadd float %448, %449
  %451 = fmul float %60, %19
  %452 = fadd float %450, %451
  %453 = fmul float %temp.0, %20
  %454 = fmul float %temp1.0, %21
  %455 = fadd float %453, %454
  %456 = fmul float %temp2.0, %22
  %457 = fadd float %455, %456
  %458 = fmul float %60, %23
  %459 = fadd float %457, %458
  %460 = fmul float %temp.0, %24
  %461 = fmul float %temp1.0, %25
  %462 = fadd float %460, %461
  %463 = fmul float %temp2.0, %26
  %464 = fadd float %462, %463
  %465 = fmul float %60, %27
  %466 = fadd float %464, %465
  %467 = fmul float %temp8.0, %28
  %468 = fmul float %temp9.0, %29
  %469 = fadd float %468, %467
  %470 = fmul float %temp10.0, %30
  %471 = fadd float %469, %470
  %472 = fmul float %temp8.0, %31
  %473 = fmul float %temp9.0, %32
  %474 = fadd float %473, %472
  %475 = fmul float %temp10.0, %33
  %476 = fadd float %474, %475
  %477 = fmul float %temp8.0, %34
  %478 = fmul float %temp9.0, %35
  %479 = fadd float %478, %477
  %480 = fmul float %temp10.0, %36
  %481 = fadd float %479, %480
  %482 = fsub float -0.000000e+00, %476
  %483 = fmul float %temp.0, %45
  %484 = fmul float %temp1.0, %46
  %485 = fadd float %483, %484
  %486 = fmul float %temp2.0, %47
  %487 = fadd float %485, %486
  %488 = fmul float %60, %48
  %489 = fadd float %487, %488
  %490 = fadd float %489, 0xBFB99999A0000000
  %491 = fmul float %70, %37
  %492 = fmul float %71, %38
  %493 = fadd float %491, %492
  %494 = fmul float %72, %39
  %495 = fadd float %493, %494
  %496 = fmul float %73, %40
  %497 = fadd float %495, %496
  %498 = fmul float %70, %41
  %499 = fmul float %71, %42
  %500 = fadd float %498, %499
  %501 = fmul float %72, %43
  %502 = fadd float %500, %501
  %503 = fmul float %73, %44
  %504 = fadd float %502, %503
  %505 = fmul float %97, %49
  %506 = fadd float %505, %50
  %507 = fmul float %96, %49
  %508 = fadd float %507, %50
  %509 = fmul float %95, %49
  %510 = fadd float %509, %50
  %511 = fmul float %98, %49
  %512 = fadd float %511, %50
  %513 = fmul float %506, %506
  %514 = fmul float %508, %508
  %515 = fmul float %510, %510
  %516 = call float @llvm.AMDGPU.lrp(float %512, float %513, float 1.000000e+00)
  %517 = call float @llvm.AMDGPU.lrp(float %512, float %514, float 1.000000e+00)
  %518 = call float @llvm.AMDGPU.lrp(float %512, float %515, float 1.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %497, float %504, float %90, float %91)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %471, float %482, float %481, float %490)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %516, float %517, float %518, float %512)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %445, float %452, float %459, float %466)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDGPU.lrp(float, float, float) #2

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg63, %SGPR6_SGPR7 in %vreg66, %VGPR0 in %vreg69

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%66](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%VGPR18_VGPR19_VGPR20_VGPR21<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%11](align=8)(tbaa=!"const")
	S_WAITCNT 112
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 43; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR22<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 42; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR23<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
	%VGPR36<def> = V_MAD_F32 %VGPR20, %VGPR23, %VGPR22, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_MAD_F32 %VGPR18, %VGPR23, %VGPR22, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 24; mem:LD16[%84](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%VGPR5_VGPR6_VGPR7_VGPR8<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 20; mem:LD16[%79](align=8)(tbaa=!"const")
	S_WAITCNT 112
	%VGPR9_VGPR10_VGPR11_VGPR12<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 8; mem:LD16[%74](align=8)(tbaa=!"const")
	S_WAITCNT 112
	%VGPR14_VGPR15_VGPR16_VGPR17<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 0; mem:LD16[%57](align=8)(tbaa=!"const")
	S_WAITCNT 112
	%VGPR1_VGPR2_VGPR3_VGPR4<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR0, 0, %EXEC<imp-use>
	%VGPR18<def> = V_MAD_F32 %VGPR19, %VGPR23<kill>, %VGPR22<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR18_VGPR19_VGPR20_VGPR21<imp-use,kill>
	%VGPR56<def> = V_ADD_F32_e32 1.000000e-03, %VGPR18<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_MOV_B32 3840
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_SGPR %SGPR8_SGPR9_SGPR10_SGPR11, %SGPR0<kill>; mem:LD4[<unknown>]
	S_WAITCNT 112
	%SGPR2_SGPR3<def> = V_CMP_NE_I32_e64 %SGPR0<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 41; mem:LD4[<unknown>]
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 40; mem:LD4[<unknown>]
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 39; mem:LD4[<unknown>]
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 38; mem:LD4[<unknown>]
	%SGPR12<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 37; mem:LD4[<unknown>]
	%SGPR13<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 36; mem:LD4[<unknown>]
	%SGPR14<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 35; mem:LD4[<unknown>]
	%SGPR15<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 34; mem:LD4[<unknown>]
	%SGPR16<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 33; mem:LD4[<unknown>]
	%SGPR17<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 32; mem:LD4[<unknown>]
	%SGPR18<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 31; mem:LD4[<unknown>]
	%SGPR19<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 30; mem:LD4[<unknown>]
	%SGPR20<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 29; mem:LD4[<unknown>]
	%SGPR21<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 28; mem:LD4[<unknown>]
	%SGPR22<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 26; mem:LD4[<unknown>]
	%SGPR23<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 25; mem:LD4[<unknown>]
	%SGPR24<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 24; mem:LD4[<unknown>]
	%SGPR25<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 22; mem:LD4[<unknown>]
	%SGPR26<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 21; mem:LD4[<unknown>]
	%SGPR27<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 20; mem:LD4[<unknown>]
	%SGPR28<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 18; mem:LD4[<unknown>]
	%SGPR29<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 17; mem:LD4[<unknown>]
	%SGPR30<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 16; mem:LD4[<unknown>]
	%SGPR31<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 15; mem:LD4[<unknown>]
	%SGPR32<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 14; mem:LD4[<unknown>]
	%SGPR33<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 13; mem:LD4[<unknown>]
	%SGPR34<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 12; mem:LD4[<unknown>]
	%SGPR35<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 11; mem:LD4[<unknown>]
	%SGPR36<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 10; mem:LD4[<unknown>]
	%SGPR37<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 9; mem:LD4[<unknown>]
	%SGPR38<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 8; mem:LD4[<unknown>]
	%SGPR39<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 7; mem:LD4[<unknown>]
	%SGPR40<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 6; mem:LD4[<unknown>]
	%SGPR41<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 5; mem:LD4[<unknown>]
	%SGPR42<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 4; mem:LD4[<unknown>]
	%SGPR43<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 3; mem:LD4[<unknown>]
	%SGPR44<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 2; mem:LD4[<unknown>]
	%SGPR45<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 1; mem:LD4[<unknown>]
	%SGPR46<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 0; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR26<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR35<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
	%VGPR38<def> = V_MOV_B32_e32 %SGPR12<kill>, %EXEC<imp-use>
	%VGPR37<def> = V_MOV_B32_e32 %SGPR13<kill>, %EXEC<imp-use>
	%VGPR45<def> = V_MOV_B32_e32 %SGPR14<kill>, %EXEC<imp-use>
	%VGPR50<def> = V_MOV_B32_e32 %SGPR15<kill>, %EXEC<imp-use>
	%VGPR55<def> = V_MOV_B32_e32 %SGPR16<kill>, %EXEC<imp-use>
	%VGPR54<def> = V_MOV_B32_e32 %SGPR17<kill>, %EXEC<imp-use>
	%VGPR44<def> = V_MOV_B32_e32 %SGPR18<kill>, %EXEC<imp-use>
	%VGPR48<def> = V_MOV_B32_e32 %SGPR19<kill>, %EXEC<imp-use>
	%VGPR53<def> = V_MOV_B32_e32 %SGPR20<kill>, %EXEC<imp-use>
	%VGPR52<def> = V_MOV_B32_e32 %SGPR21<kill>, %EXEC<imp-use>
	%VGPR41<def> = V_MOV_B32_e32 %SGPR22<kill>, %EXEC<imp-use>
	%VGPR43<def> = V_MOV_B32_e32 %SGPR23<kill>, %EXEC<imp-use>
	%VGPR47<def> = V_MOV_B32_e32 %SGPR24<kill>, %EXEC<imp-use>
	%VGPR39<def> = V_MOV_B32_e32 %SGPR25<kill>, %EXEC<imp-use>
	%VGPR40<def> = V_MOV_B32_e32 %SGPR26<kill>, %EXEC<imp-use>
	%VGPR42<def> = V_MOV_B32_e32 %SGPR27<kill>, %EXEC<imp-use>
	%VGPR46<def> = V_MOV_B32_e32 %SGPR28<kill>, %EXEC<imp-use>
	%VGPR49<def> = V_MOV_B32_e32 %SGPR29<kill>, %EXEC<imp-use>
	%VGPR51<def> = V_MOV_B32_e32 %SGPR30<kill>, %EXEC<imp-use>
	%VGPR21<def> = V_MOV_B32_e32 %SGPR31<kill>, %EXEC<imp-use>
	%VGPR25<def> = V_MOV_B32_e32 %SGPR32<kill>, %EXEC<imp-use>
	%VGPR34<def> = V_MOV_B32_e32 %SGPR33<kill>, %EXEC<imp-use>
	%VGPR33<def> = V_MOV_B32_e32 %SGPR34<kill>, %EXEC<imp-use>
	%VGPR20<def> = V_MOV_B32_e32 %SGPR35<kill>, %EXEC<imp-use>
	%VGPR24<def> = V_MOV_B32_e32 %SGPR36<kill>, %EXEC<imp-use>
	%VGPR32<def> = V_MOV_B32_e32 %SGPR37<kill>, %EXEC<imp-use>
	%VGPR31<def> = V_MOV_B32_e32 %SGPR38<kill>, %EXEC<imp-use>
	%VGPR19<def> = V_MOV_B32_e32 %SGPR39<kill>, %EXEC<imp-use>
	%VGPR23<def> = V_MOV_B32_e32 %SGPR40<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_MOV_B32_e32 %SGPR41<kill>, %EXEC<imp-use>
	%VGPR29<def> = V_MOV_B32_e32 %SGPR42<kill>, %EXEC<imp-use>
	%VGPR18<def> = V_MOV_B32_e32 %SGPR43<kill>, %EXEC<imp-use>
	%VGPR22<def> = V_MOV_B32_e32 %SGPR44<kill>, %EXEC<imp-use>
	%VGPR28<def> = V_MOV_B32_e32 %SGPR45<kill>, %EXEC<imp-use>
	%VGPR27<def> = V_MOV_B32_e32 %SGPR46<kill>, %EXEC<imp-use>
	%VGPR59<def> = V_MOV_B32_e32 %VGPR1, %EXEC<imp-use>
	%VGPR58<def> = V_MOV_B32_e32 %VGPR2, %EXEC<imp-use>
	%VGPR57<def> = V_MOV_B32_e32 %VGPR3, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_AND_SAVEEXEC_B64 %SGPR2_SGPR3, %EXEC<imp-def>, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_XOR_B64 %EXEC, %SGPR2_SGPR3
	S_CBRANCH_EXECZ <BB#2>, %EXEC
    Successors according to CFG: BB#1(16) BB#2(16)

BB#1: derived from LLVM BB %IF
    Live Ins: %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR27 %VGPR28 %VGPR22 %VGPR18 %VGPR29 %VGPR30 %VGPR23 %VGPR19 %VGPR31 %VGPR32 %VGPR24 %VGPR20 %VGPR33 %VGPR34 %VGPR25 %VGPR21 %VGPR51 %VGPR49 %VGPR46 %VGPR42 %VGPR40 %VGPR39 %VGPR47 %VGPR43 %VGPR41 %VGPR52 %VGPR53 %VGPR48 %VGPR44 %VGPR54 %VGPR55 %VGPR50 %VGPR45 %VGPR37 %VGPR38 %VGPR35 %VGPR26 %SGPR0 %SGPR1 %VGPR14_VGPR15_VGPR16_VGPR17 %VGPR9_VGPR10_VGPR11_VGPR12 %VGPR5_VGPR6_VGPR7_VGPR8 %SGPR6_SGPR7 %VGPR0 %VGPR1_VGPR2_VGPR3_VGPR4 %SGPR2_SGPR3 %VGPR13 %VGPR56 %VGPR36
    Predecessors according to CFG: BB#0
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 12; mem:LD16[%101](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%VGPR57_VGPR58_VGPR59_VGPR60<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %VGPR0, 0, %EXEC<imp-use>
	%VGPR61<def> = V_MOV_B32_e32 2.550100e+02, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR62<def> = V_MUL_F32_e32 %VGPR57, %VGPR61, %EXEC<imp-use>
	%VGPR62<def> = V_CVT_I32_F32_e32 %VGPR62<kill>, %EXEC<imp-use>
	%VGPR62<def> = V_MUL_LO_I32 3, %VGPR62<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR63<def> = V_ADD_I32_e32 43, %VGPR62, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR63<def> = V_LSHLREV_B32_e32 4, %VGPR63<kill>, %EXEC<imp-use>
	%VGPR64<def> = V_OR_B32_e64 4, %VGPR63, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR64<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR64<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 16; mem:LD16[%110](align=8)(tbaa=!"const")
	S_WAITCNT 112
	%VGPR65_VGPR66_VGPR67_VGPR68<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR0<def> = V_MUL_F32_e32 %VGPR64<kill>, %VGPR65, %EXEC<imp-use>
	%VGPR64<def> = V_MUL_F32_e32 %VGPR58, %VGPR61, %EXEC<imp-use>
	%VGPR64<def> = V_CVT_I32_F32_e32 %VGPR64<kill>, %EXEC<imp-use>
	%VGPR64<def> = V_MUL_LO_I32 3, %VGPR64<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR69<def> = V_ADD_I32_e32 43, %VGPR64, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR69<def> = V_LSHLREV_B32_e32 4, %VGPR69<kill>, %EXEC<imp-use>
	%VGPR70<def> = V_OR_B32_e64 4, %VGPR69, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR70<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR70<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR0<def> = V_MAD_F32 %VGPR70<kill>, %VGPR66, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR70<def> = V_MUL_F32_e32 %VGPR59, %VGPR61, %EXEC<imp-use>
	%VGPR70<def> = V_CVT_I32_F32_e32 %VGPR70<kill>, %EXEC<imp-use>
	%VGPR70<def> = V_MUL_LO_I32 3, %VGPR70<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR71<def> = V_ADD_I32_e32 43, %VGPR70, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR71<def> = V_LSHLREV_B32_e32 4, %VGPR71<kill>, %EXEC<imp-use>
	%VGPR72<def> = V_OR_B32_e64 4, %VGPR71, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR72<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR72<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR0<def> = V_MAD_F32 %VGPR72<kill>, %VGPR67, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR72<def> = V_ADD_F32_e32 %VGPR66, %VGPR65, %EXEC<imp-use>
	%VGPR72<def> = V_ADD_F32_e32 %VGPR72<kill>, %VGPR67, %EXEC<imp-use>
	%VGPR72<def> = V_SUB_F32_e32 1.000000e+00, %VGPR72<kill>, %EXEC<imp-use>
	%VGPR57<def> = V_MUL_F32_e32 %VGPR60, %VGPR61<kill>, %EXEC<imp-use>, %VGPR57_VGPR58_VGPR59_VGPR60<imp-use,kill>
	%VGPR57<def> = V_CVT_I32_F32_e32 %VGPR57<kill>, %EXEC<imp-use>
	%VGPR57<def> = V_MUL_LO_I32 3, %VGPR57<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR58<def> = V_ADD_I32_e32 43, %VGPR57, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR58<def> = V_LSHLREV_B32_e32 4, %VGPR58<kill>, %EXEC<imp-use>
	%VGPR59<def> = V_OR_B32_e64 4, %VGPR58, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR59<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR59<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR0<def> = V_MAD_F32 %VGPR59<kill>, %VGPR72, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR59<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR63, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR59<def> = V_MUL_F32_e32 %VGPR59<kill>, %VGPR65, %EXEC<imp-use>
	%VGPR60<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR69, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR59<def> = V_MAD_F32 %VGPR60<kill>, %VGPR66, %VGPR59<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR60<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR71, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR59<def> = V_MAD_F32 %VGPR60<kill>, %VGPR67, %VGPR59<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR60<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR58, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR59<def> = V_MAD_F32 %VGPR60<kill>, %VGPR72, %VGPR59<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR60<def> = V_MUL_F32_e32 %VGPR13, %VGPR59, %EXEC<imp-use>
	%VGPR60<def> = V_MAD_F32 %VGPR56, %VGPR0, %VGPR60<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR61<def> = V_OR_B32_e64 8, %VGPR63, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR61<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR61<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR61<def> = V_MUL_F32_e32 %VGPR61<kill>, %VGPR65, %EXEC<imp-use>
	%VGPR73<def> = V_OR_B32_e64 8, %VGPR69, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR73<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR73<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR61<def> = V_MAD_F32 %VGPR73<kill>, %VGPR66, %VGPR61<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR73<def> = V_OR_B32_e64 8, %VGPR71, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR73<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR73<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR61<def> = V_MAD_F32 %VGPR73<kill>, %VGPR67, %VGPR61<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR73<def> = V_OR_B32_e64 8, %VGPR58, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR73<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR73<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR61<def> = V_MAD_F32 %VGPR73<kill>, %VGPR72, %VGPR61<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR60<def> = V_MAD_F32 %VGPR36, %VGPR61, %VGPR60<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR73<def> = V_ADD_I32_e32 42, %VGPR62, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR73<def> = V_LSHLREV_B32_e32 4, %VGPR73<kill>, %EXEC<imp-use>
	%VGPR74<def> = V_OR_B32_e64 4, %VGPR73, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR74<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR74<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR74<def> = V_MUL_F32_e32 %VGPR74<kill>, %VGPR65, %EXEC<imp-use>
	%VGPR75<def> = V_ADD_I32_e32 42, %VGPR64, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR75<def> = V_LSHLREV_B32_e32 4, %VGPR75<kill>, %EXEC<imp-use>
	%VGPR76<def> = V_OR_B32_e64 4, %VGPR75, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR76<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR76<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR74<def> = V_MAD_F32 %VGPR76<kill>, %VGPR66, %VGPR74<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR76<def> = V_ADD_I32_e32 42, %VGPR70, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR76<def> = V_LSHLREV_B32_e32 4, %VGPR76<kill>, %EXEC<imp-use>
	%VGPR77<def> = V_OR_B32_e64 4, %VGPR76, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR77<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR77<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR74<def> = V_MAD_F32 %VGPR77<kill>, %VGPR67, %VGPR74<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR77<def> = V_ADD_I32_e32 42, %VGPR57, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR77<def> = V_LSHLREV_B32_e32 4, %VGPR77<kill>, %EXEC<imp-use>
	%VGPR78<def> = V_OR_B32_e64 4, %VGPR77, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR78<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR78<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR74<def> = V_MAD_F32 %VGPR78<kill>, %VGPR72, %VGPR74<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR78<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR73, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR78<def> = V_MUL_F32_e32 %VGPR78<kill>, %VGPR65, %EXEC<imp-use>
	%VGPR79<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR75, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR78<def> = V_MAD_F32 %VGPR79<kill>, %VGPR66, %VGPR78<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR79<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR76, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR78<def> = V_MAD_F32 %VGPR79<kill>, %VGPR67, %VGPR78<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR79<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR77, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR78<def> = V_MAD_F32 %VGPR79<kill>, %VGPR72, %VGPR78<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR79<def> = V_MUL_F32_e32 %VGPR13, %VGPR78, %EXEC<imp-use>
	%VGPR79<def> = V_MAD_F32 %VGPR56, %VGPR74, %VGPR79<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR80<def> = V_OR_B32_e64 8, %VGPR73, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR80<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR80<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR80<def> = V_MUL_F32_e32 %VGPR80<kill>, %VGPR65, %EXEC<imp-use>
	%VGPR81<def> = V_OR_B32_e64 8, %VGPR75, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR81<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR81<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR80<def> = V_MAD_F32 %VGPR81<kill>, %VGPR66, %VGPR80<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR81<def> = V_OR_B32_e64 8, %VGPR76, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR81<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR81<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR80<def> = V_MAD_F32 %VGPR81<kill>, %VGPR67, %VGPR80<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR81<def> = V_OR_B32_e64 8, %VGPR77, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR81<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR81<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR80<def> = V_MAD_F32 %VGPR81<kill>, %VGPR72, %VGPR80<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR79<def> = V_MAD_F32 %VGPR36, %VGPR80, %VGPR79<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR62<def> = V_ADD_I32_e32 41, %VGPR62<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR62<def> = V_LSHLREV_B32_e32 4, %VGPR62<kill>, %EXEC<imp-use>
	%VGPR81<def> = V_OR_B32_e64 4, %VGPR62, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR81<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR81<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR81<def> = V_MUL_F32_e32 %VGPR81<kill>, %VGPR65, %EXEC<imp-use>
	%VGPR64<def> = V_ADD_I32_e32 41, %VGPR64<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR64<def> = V_LSHLREV_B32_e32 4, %VGPR64<kill>, %EXEC<imp-use>
	%VGPR82<def> = V_OR_B32_e64 4, %VGPR64, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR82<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR82<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR81<def> = V_MAD_F32 %VGPR82<kill>, %VGPR66, %VGPR81<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR70<def> = V_ADD_I32_e32 41, %VGPR70<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR70<def> = V_LSHLREV_B32_e32 4, %VGPR70<kill>, %EXEC<imp-use>
	%VGPR82<def> = V_OR_B32_e64 4, %VGPR70, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR82<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR82<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR81<def> = V_MAD_F32 %VGPR82<kill>, %VGPR67, %VGPR81<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR57<def> = V_ADD_I32_e32 41, %VGPR57<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR82<def> = V_LSHLREV_B32_e32 4, %VGPR57<kill>, %EXEC<imp-use>
	%VGPR57<def> = V_OR_B32_e64 4, %VGPR82, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR57<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR57<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR81<def> = V_MAD_F32 %VGPR57<kill>, %VGPR72, %VGPR81<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR57<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR62, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR57<def> = V_MUL_F32_e32 %VGPR57<kill>, %VGPR65, %EXEC<imp-use>
	%VGPR83<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR64, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR57<def> = V_MAD_F32 %VGPR83<kill>, %VGPR66, %VGPR57<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR83<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR70, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR57<def> = V_MAD_F32 %VGPR83<kill>, %VGPR67, %VGPR57<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR83<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR82, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR83<def> = V_MAD_F32 %VGPR83<kill>, %VGPR72, %VGPR57<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_MUL_F32_e32 %VGPR13<kill>, %VGPR83, %EXEC<imp-use>
	%VGPR13<def> = V_MAD_F32 %VGPR56<kill>, %VGPR81, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR56<def> = V_OR_B32_e64 8, %VGPR62, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR56<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR56<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR56<def> = V_MUL_F32_e32 %VGPR56<kill>, %VGPR65, %EXEC<imp-use>
	%VGPR57<def> = V_OR_B32_e64 8, %VGPR64, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR57<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR57<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR56<def> = V_MAD_F32 %VGPR57<kill>, %VGPR66, %VGPR56<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR57<def> = V_OR_B32_e64 8, %VGPR70, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR57<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR57<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR56<def> = V_MAD_F32 %VGPR57<kill>, %VGPR67, %VGPR56<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR57<def> = V_OR_B32_e64 8, %VGPR82, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR57<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR57<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR56<def> = V_MAD_F32 %VGPR57<kill>, %VGPR72, %VGPR56<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_MAD_F32 %VGPR36<kill>, %VGPR56, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR2, %VGPR0<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR1, %VGPR59<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR3, %VGPR61<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR36<def> = V_OR_B32_e64 12, %VGPR63<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR36<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR36<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR36<def> = V_MUL_F32_e32 %VGPR36<kill>, %VGPR65, %EXEC<imp-use>
	%VGPR57<def> = V_OR_B32_e64 12, %VGPR69<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR57<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR57<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR36<def> = V_MAD_F32 %VGPR57<kill>, %VGPR66, %VGPR36<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR57<def> = V_OR_B32_e64 12, %VGPR71<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR57<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR57<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR36<def> = V_MAD_F32 %VGPR57<kill>, %VGPR67, %VGPR36<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR57<def> = V_OR_B32_e64 12, %VGPR58<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR57<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR57<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR36<def> = V_MAD_F32 %VGPR57<kill>, %VGPR72, %VGPR36<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR57<def> = V_MAD_F32 %VGPR4, %VGPR36<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR2, %VGPR74<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR1, %VGPR78<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR3, %VGPR80<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR36<def> = V_OR_B32_e64 12, %VGPR73<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR36<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR36<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR36<def> = V_MUL_F32_e32 %VGPR36<kill>, %VGPR65, %EXEC<imp-use>
	%VGPR58<def> = V_OR_B32_e64 12, %VGPR75<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR58<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR58<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR36<def> = V_MAD_F32 %VGPR58<kill>, %VGPR66, %VGPR36<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR58<def> = V_OR_B32_e64 12, %VGPR76<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR58<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR58<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR36<def> = V_MAD_F32 %VGPR58<kill>, %VGPR67, %VGPR36<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR58<def> = V_OR_B32_e64 12, %VGPR77<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR58<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR58<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR36<def> = V_MAD_F32 %VGPR58<kill>, %VGPR72, %VGPR36<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR58<def> = V_MAD_F32 %VGPR4, %VGPR36<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR2, %VGPR81<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR1, %VGPR83<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR3, %VGPR56<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR36<def> = V_OR_B32_e64 12, %VGPR62<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR36<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR36<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR36<def> = V_MUL_F32_e32 %VGPR36<kill>, %VGPR65, %EXEC<imp-use>
	%VGPR56<def> = V_OR_B32_e64 12, %VGPR64<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR56<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR56<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR36<def> = V_MAD_F32 %VGPR56<kill>, %VGPR66, %VGPR36<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR56<def> = V_OR_B32_e64 12, %VGPR70<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR56<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR56<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR36<def> = V_MAD_F32 %VGPR56<kill>, %VGPR67, %VGPR36<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR65_VGPR66_VGPR67_VGPR68<imp-use,kill>
	%VGPR56<def> = V_OR_B32_e64 12, %VGPR82<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR56<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR56<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR36<def> = V_MAD_F32 %VGPR56<kill>, %VGPR72<kill>, %VGPR36<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR59<def> = V_MAD_F32 %VGPR4, %VGPR36<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR56<def> = V_MOV_B32_e32 %VGPR79<kill>, %EXEC<imp-use>
	%VGPR36<def> = V_MOV_B32_e32 %VGPR60<kill>, %EXEC<imp-use>
    Successors according to CFG: BB#2

BB#2: derived from LLVM BB %ENDIF
    Live Ins: %VGPR27 %VGPR28 %VGPR22 %VGPR18 %VGPR29 %VGPR30 %VGPR23 %VGPR19 %VGPR31 %VGPR32 %VGPR24 %VGPR20 %VGPR33 %VGPR34 %VGPR25 %VGPR21 %VGPR51 %VGPR49 %VGPR46 %VGPR42 %VGPR40 %VGPR39 %VGPR47 %VGPR43 %VGPR41 %VGPR52 %VGPR53 %VGPR48 %VGPR44 %VGPR54 %VGPR55 %VGPR50 %VGPR45 %VGPR37 %VGPR38 %VGPR35 %VGPR26 %SGPR0 %SGPR1 %VGPR14_VGPR15_VGPR16_VGPR17 %VGPR9_VGPR10_VGPR11_VGPR12 %VGPR5_VGPR6_VGPR7_VGPR8 %VGPR1_VGPR2_VGPR3_VGPR4 %SGPR2_SGPR3 %VGPR59 %VGPR58 %VGPR57 %VGPR13 %VGPR56 %VGPR36
    Predecessors according to CFG: BB#0 BB#1
	%EXEC<def> = S_OR_B64 %EXEC, %SGPR2_SGPR3
	%VGPR0<def> = V_MUL_F32_e64 %VGPR15, %VGPR55<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR14, %VGPR54<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR16, %VGPR50<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR17, %VGPR45<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR45<def> = V_MUL_F32_e64 %VGPR15, %VGPR53<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR45<def> = V_MAD_F32 %VGPR14, %VGPR52<kill>, %VGPR45<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR45<def> = V_MAD_F32 %VGPR16, %VGPR48<kill>, %VGPR45<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR14<def> = V_MAD_F32 %VGPR17, %VGPR44<kill>, %VGPR45<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17<imp-use,kill>
	EXP 15, 32, 0, 0, 0, %VGPR14<kill>, %VGPR0<kill>, %VGPR9, %VGPR10, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11_VGPR12<imp-use,kill>
	S_WAITCNT 1807
	%VGPR0<def> = V_MUL_F32_e64 %VGPR13, %VGPR47<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR56, %VGPR43<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR36, %VGPR41<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_MUL_F32_e64 %VGPR13, %VGPR51<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_MAD_F32 %VGPR56, %VGPR49<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_MAD_F32 %VGPR36, %VGPR46<kill>, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR10<def> = V_MUL_F32_e64 %VGPR13<kill>, %VGPR42<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR10<def> = V_MAD_F32 %VGPR56<kill>, %VGPR40<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR10<def> = V_MAD_F32 %VGPR36<kill>, %VGPR39<kill>, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR10<def> = V_ADD_F32_e64 %VGPR10<kill>, 0, 0, 0, 0, 1, %EXEC<imp-use>
	%VGPR11<def> = V_MUL_F32_e64 %VGPR58, %VGPR38<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR11<def> = V_MAD_F32 %VGPR59, %VGPR37<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR11<def> = V_MAD_F32 %VGPR57, %VGPR35<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR11<def> = V_MAD_F32 %VGPR4, %VGPR26<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR11<def> = V_ADD_F32_e32 -1.000000e-01, %VGPR11<kill>, %EXEC<imp-use>
	EXP 15, 33, 0, 0, 0, %VGPR9<kill>, %VGPR10<kill>, %VGPR0<kill>, %VGPR11<kill>, %EXEC<imp-use>
	S_WAITCNT 1807
	%VGPR0<def> = V_MOV_B32_e32 %SGPR1<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
	%VGPR10<def> = V_MAD_F32 %VGPR8, %VGPR9, %VGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR11<def> = V_SUB_F32_e32 1.000000e+00, %VGPR10, %EXEC<imp-use>
	%VGPR12<def> = V_MAD_F32 %VGPR5, %VGPR9, %VGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_MUL_F32_e32 %VGPR12<kill>, %VGPR12, %EXEC<imp-use>
	%VGPR12<def> = V_MAD_F32 %VGPR10, %VGPR12<kill>, %VGPR11, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_MAD_F32 %VGPR6, %VGPR9, %VGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_MUL_F32_e32 %VGPR13<kill>, %VGPR13, %EXEC<imp-use>
	%VGPR13<def> = V_MAD_F32 %VGPR10, %VGPR13<kill>, %VGPR11, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR7, %VGPR9<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-use,kill>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR0<kill>, %VGPR0, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR10, %VGPR0<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 34, 0, 0, 0, %VGPR0<kill>, %VGPR13<kill>, %VGPR12<kill>, %VGPR10<kill>, %EXEC<imp-use>
	S_WAITCNT 1807
	%VGPR0<def> = V_MUL_F32_e64 %VGPR58, %VGPR34<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR59, %VGPR33<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR57, %VGPR25<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR4, %VGPR21<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_MUL_F32_e64 %VGPR58, %VGPR32<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR59, %VGPR31<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR57, %VGPR24<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR4, %VGPR20<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e64 %VGPR58, %VGPR30<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR59, %VGPR29<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR57, %VGPR23<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR4, %VGPR19<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_MUL_F32_e64 %VGPR58<kill>, %VGPR28<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR59<kill>, %VGPR27<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR57<kill>, %VGPR22<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_MAD_F32 %VGPR4, %VGPR18<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR1_VGPR2_VGPR3_VGPR4<imp-use,kill>
	EXP 15, 12, 0, 1, 0, %VGPR1<kill>, %VGPR6<kill>, %VGPR5<kill>, %VGPR0<kill>, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_LOAD_DWORDX4 s[8:11], s[6:7], 4                  ; C0840704
	S_WAITCNT lgkmcnt(0)                               ; BF8C007F
	BUFFER_LOAD_FORMAT_XYZW v[18:21], s[8:11][v0] + 0  ; E00C2000 80021200
	S_LOAD_DWORDX4 s[8:11], s[0:1], 0                  ; C0840100
	S_WAITCNT vmcnt(0) lgkmcnt(0)                      ; BF8C0070
	S_BUFFER_LOAD_DWORD s0, s[8:11], 43                ; C200092B
	S_WAITCNT lgkmcnt(0)                               ; BF8C007F
	V_MOV_B32_e32 v22, s0                              ; 7E2C0200
	S_BUFFER_LOAD_DWORD s0, s[8:11], 42                ; C200092A
	S_WAITCNT lgkmcnt(0)                               ; BF8C007F
	V_MOV_B32_e32 v23, s0                              ; 7E2E0200
	V_MAD_F32 v36, v20, v23, v22, 0, 0, 0, 0           ; D2820024 045A2F14
	V_MAD_F32 v13, v18, v23, v22, 0, 0, 0, 0           ; D282000D 045A2F12
	S_LOAD_DWORDX4 s[0:3], s[6:7], 24                  ; C0800718
	S_WAITCNT lgkmcnt(0)                               ; BF8C007F
	BUFFER_LOAD_FORMAT_XYZW v[5:8], s[0:3][v0] + 0     ; E00C2000 80000500
	S_LOAD_DWORDX4 s[0:3], s[6:7], 20                  ; C0800714
	S_WAITCNT vmcnt(0) lgkmcnt(0)                      ; BF8C0070
	BUFFER_LOAD_FORMAT_XYZW v[9:12], s[0:3][v0] + 0    ; E00C2000 80000900
	S_LOAD_DWORDX4 s[0:3], s[6:7], 8                   ; C0800708
	S_WAITCNT vmcnt(0) lgkmcnt(0)                      ; BF8C0070
	BUFFER_LOAD_FORMAT_XYZW v[14:17], s[0:3][v0] + 0   ; E00C2000 80000E00
	S_LOAD_DWORDX4 s[0:3], s[6:7], 0                   ; C0800700
	S_WAITCNT vmcnt(0) lgkmcnt(0)                      ; BF8C0070
	BUFFER_LOAD_FORMAT_XYZW v[1:4], s[0:3][v0] + 0     ; E00C2000 80000100
	V_MAD_F32 v18, v19, v23, v22, 0, 0, 0, 0           ; D2820012 045A2F13
	V_ADD_F32_e32 v56, 1.000000e-03, v18               ; 067024FF 3A83126F
	S_MOV_B32 s0, 3840                                 ; BE8003FF 00000F00
	S_BUFFER_LOAD_DWORD s0, s[8:11], s0                ; C2000800
	S_WAITCNT vmcnt(0) lgkmcnt(0)                      ; BF8C0070
	V_CMP_NE_I32_e64 s[2:3], s0, 0, 0, 0, 0, 0         ; D10A0002 02010000
	S_BUFFER_LOAD_DWORD s1, s[8:11], 41                ; C2008929
	S_BUFFER_LOAD_DWORD s0, s[8:11], 40                ; C2000928
	S_BUFFER_LOAD_DWORD s4, s[8:11], 39                ; C2020927
	S_BUFFER_LOAD_DWORD s5, s[8:11], 38                ; C2028926
	S_BUFFER_LOAD_DWORD s12, s[8:11], 37               ; C2060925
	S_BUFFER_LOAD_DWORD s13, s[8:11], 36               ; C2068924
	S_BUFFER_LOAD_DWORD s14, s[8:11], 35               ; C2070923
	S_BUFFER_LOAD_DWORD s15, s[8:11], 34               ; C2078922
	S_BUFFER_LOAD_DWORD s16, s[8:11], 33               ; C2080921
	S_BUFFER_LOAD_DWORD s17, s[8:11], 32               ; C2088920
	S_BUFFER_LOAD_DWORD s18, s[8:11], 31               ; C209091F
	S_BUFFER_LOAD_DWORD s19, s[8:11], 30               ; C209891E
	S_BUFFER_LOAD_DWORD s20, s[8:11], 29               ; C20A091D
	S_BUFFER_LOAD_DWORD s21, s[8:11], 28               ; C20A891C
	S_BUFFER_LOAD_DWORD s22, s[8:11], 26               ; C20B091A
	S_BUFFER_LOAD_DWORD s23, s[8:11], 25               ; C20B8919
	S_BUFFER_LOAD_DWORD s24, s[8:11], 24               ; C20C0918
	S_BUFFER_LOAD_DWORD s25, s[8:11], 22               ; C20C8916
	S_BUFFER_LOAD_DWORD s26, s[8:11], 21               ; C20D0915
	S_BUFFER_LOAD_DWORD s27, s[8:11], 20               ; C20D8914
	S_BUFFER_LOAD_DWORD s28, s[8:11], 18               ; C20E0912
	S_BUFFER_LOAD_DWORD s29, s[8:11], 17               ; C20E8911
	S_BUFFER_LOAD_DWORD s30, s[8:11], 16               ; C20F0910
	S_BUFFER_LOAD_DWORD s31, s[8:11], 15               ; C20F890F
	S_BUFFER_LOAD_DWORD s32, s[8:11], 14               ; C210090E
	S_BUFFER_LOAD_DWORD s33, s[8:11], 13               ; C210890D
	S_BUFFER_LOAD_DWORD s34, s[8:11], 12               ; C211090C
	S_BUFFER_LOAD_DWORD s35, s[8:11], 11               ; C211890B
	S_BUFFER_LOAD_DWORD s36, s[8:11], 10               ; C212090A
	S_BUFFER_LOAD_DWORD s37, s[8:11], 9                ; C2128909
	S_BUFFER_LOAD_DWORD s38, s[8:11], 8                ; C2130908
	S_BUFFER_LOAD_DWORD s39, s[8:11], 7                ; C2138907
	S_BUFFER_LOAD_DWORD s40, s[8:11], 6                ; C2140906
	S_BUFFER_LOAD_DWORD s41, s[8:11], 5                ; C2148905
	S_BUFFER_LOAD_DWORD s42, s[8:11], 4                ; C2150904
	S_BUFFER_LOAD_DWORD s43, s[8:11], 3                ; C2158903
	S_BUFFER_LOAD_DWORD s44, s[8:11], 2                ; C2160902
	S_BUFFER_LOAD_DWORD s45, s[8:11], 1                ; C2168901
	S_BUFFER_LOAD_DWORD s46, s[8:11], 0                ; C2170900
	S_WAITCNT lgkmcnt(0)                               ; BF8C007F
	V_MOV_B32_e32 v26, s4                              ; 7E340204
	V_MOV_B32_e32 v35, s5                              ; 7E460205
	V_MOV_B32_e32 v38, s12                             ; 7E4C020C
	V_MOV_B32_e32 v37, s13                             ; 7E4A020D
	V_MOV_B32_e32 v45, s14                             ; 7E5A020E
	V_MOV_B32_e32 v50, s15                             ; 7E64020F
	V_MOV_B32_e32 v55, s16                             ; 7E6E0210
	V_MOV_B32_e32 v54, s17                             ; 7E6C0211
	V_MOV_B32_e32 v44, s18                             ; 7E580212
	V_MOV_B32_e32 v48, s19                             ; 7E600213
	V_MOV_B32_e32 v53, s20                             ; 7E6A0214
	V_MOV_B32_e32 v52, s21                             ; 7E680215
	V_MOV_B32_e32 v41, s22                             ; 7E520216
	V_MOV_B32_e32 v43, s23                             ; 7E560217
	V_MOV_B32_e32 v47, s24                             ; 7E5E0218
	V_MOV_B32_e32 v39, s25                             ; 7E4E0219
	V_MOV_B32_e32 v40, s26                             ; 7E50021A
	V_MOV_B32_e32 v42, s27                             ; 7E54021B
	V_MOV_B32_e32 v46, s28                             ; 7E5C021C
	V_MOV_B32_e32 v49, s29                             ; 7E62021D
	V_MOV_B32_e32 v51, s30                             ; 7E66021E
	V_MOV_B32_e32 v21, s31                             ; 7E2A021F
	V_MOV_B32_e32 v25, s32                             ; 7E320220
	V_MOV_B32_e32 v34, s33                             ; 7E440221
	V_MOV_B32_e32 v33, s34                             ; 7E420222
	V_MOV_B32_e32 v20, s35                             ; 7E280223
	V_MOV_B32_e32 v24, s36                             ; 7E300224
	V_MOV_B32_e32 v32, s37                             ; 7E400225
	V_MOV_B32_e32 v31, s38                             ; 7E3E0226
	V_MOV_B32_e32 v19, s39                             ; 7E260227
	V_MOV_B32_e32 v23, s40                             ; 7E2E0228
	V_MOV_B32_e32 v30, s41                             ; 7E3C0229
	V_MOV_B32_e32 v29, s42                             ; 7E3A022A
	V_MOV_B32_e32 v18, s43                             ; 7E24022B
	V_MOV_B32_e32 v22, s44                             ; 7E2C022C
	V_MOV_B32_e32 v28, s45                             ; 7E38022D
	V_MOV_B32_e32 v27, s46                             ; 7E36022E
	V_MOV_B32_e32 v59, v1                              ; 7E760301
	V_MOV_B32_e32 v58, v2                              ; 7E740302
	V_MOV_B32_e32 v57, v3                              ; 7E720303
	S_AND_SAVEEXEC_B64 s[2:3], s[2:3]                  ; BE822402
	S_XOR_B64 s[2:3], exec, s[2:3]                     ; 8982027E
	S_CBRANCH_EXECZ ";.BB0_2"                          ; BF880000
	S_LOAD_DWORDX4 s[12:15], s[6:7], 12                ; C086070C
	S_WAITCNT lgkmcnt(0)                               ; BF8C007F
	BUFFER_LOAD_FORMAT_XYZW v[57:60], s[12:15][v0] + 0 ; E00C2000 80033900
	V_MOV_B32_e32 v61, 2.550100e+02                    ; 7E7A02FF 437F028F
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MUL_F32_e32 v62, v57, v61                        ; 107C7B39
	V_CVT_I32_F32_e32 v62, v62                         ; 7E7C113E
	V_MUL_LO_I32 v62, 3, v62, 0, 0, 0, 0, 0            ; D2D6003E 02027C83
	V_ADD_I32_e32 v63, 43, v62                         ; 4A7E7CAB
	V_LSHLREV_B32_e32 v63, 4, v63                      ; 347E7E84
	V_OR_B32_e64 v64, 4, v63, 0, 0, 0, 0               ; D2380040 02027E84
	BUFFER_LOAD_DWORD v64, s[8:11] + v64               ; E0301000 80024040
	S_LOAD_DWORDX4 s[4:7], s[6:7], 16                  ; C0820710
	S_WAITCNT vmcnt(0) lgkmcnt(0)                      ; BF8C0070
	BUFFER_LOAD_FORMAT_XYZW v[65:68], s[4:7][v0] + 0   ; E00C2000 80014100
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MUL_F32_e32 v0, v64, v65                         ; 10008340
	V_MUL_F32_e32 v64, v58, v61                        ; 10807B3A
	V_CVT_I32_F32_e32 v64, v64                         ; 7E801140
	V_MUL_LO_I32 v64, 3, v64, 0, 0, 0, 0, 0            ; D2D60040 02028083
	V_ADD_I32_e32 v69, 43, v64                         ; 4A8A80AB
	V_LSHLREV_B32_e32 v69, 4, v69                      ; 348A8A84
	V_OR_B32_e64 v70, 4, v69, 0, 0, 0, 0               ; D2380046 02028A84
	BUFFER_LOAD_DWORD v70, s[8:11] + v70               ; E0301000 80024646
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v0, v70, v66, v0, 0, 0, 0, 0             ; D2820000 04028546
	V_MUL_F32_e32 v70, v59, v61                        ; 108C7B3B
	V_CVT_I32_F32_e32 v70, v70                         ; 7E8C1146
	V_MUL_LO_I32 v70, 3, v70, 0, 0, 0, 0, 0            ; D2D60046 02028C83
	V_ADD_I32_e32 v71, 43, v70                         ; 4A8E8CAB
	V_LSHLREV_B32_e32 v71, 4, v71                      ; 348E8E84
	V_OR_B32_e64 v72, 4, v71, 0, 0, 0, 0               ; D2380048 02028E84
	BUFFER_LOAD_DWORD v72, s[8:11] + v72               ; E0301000 80024848
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v0, v72, v67, v0, 0, 0, 0, 0             ; D2820000 04028748
	V_ADD_F32_e32 v72, v66, v65                        ; 06908342
	V_ADD_F32_e32 v72, v72, v67                        ; 06908748
	V_SUB_F32_e32 v72, 1.000000e+00, v72               ; 089090F2
	V_MUL_F32_e32 v57, v60, v61                        ; 10727B3C
	V_CVT_I32_F32_e32 v57, v57                         ; 7E721139
	V_MUL_LO_I32 v57, 3, v57, 0, 0, 0, 0, 0            ; D2D60039 02027283
	V_ADD_I32_e32 v58, 43, v57                         ; 4A7472AB
	V_LSHLREV_B32_e32 v58, 4, v58                      ; 34747484
	V_OR_B32_e64 v59, 4, v58, 0, 0, 0, 0               ; D238003B 02027484
	BUFFER_LOAD_DWORD v59, s[8:11] + v59               ; E0301000 80023B3B
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v0, v59, v72, v0, 0, 0, 0, 0             ; D2820000 0402913B
	BUFFER_LOAD_DWORD v59, s[8:11] + v63               ; E0301000 80023B3F
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MUL_F32_e32 v59, v59, v65                        ; 1076833B
	BUFFER_LOAD_DWORD v60, s[8:11] + v69               ; E0301000 80023C45
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v59, v60, v66, v59, 0, 0, 0, 0           ; D282003B 04EE853C
	BUFFER_LOAD_DWORD v60, s[8:11] + v71               ; E0301000 80023C47
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v59, v60, v67, v59, 0, 0, 0, 0           ; D282003B 04EE873C
	BUFFER_LOAD_DWORD v60, s[8:11] + v58               ; E0301000 80023C3A
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v59, v60, v72, v59, 0, 0, 0, 0           ; D282003B 04EE913C
	V_MUL_F32_e32 v60, v13, v59                        ; 1078770D
	V_MAD_F32 v60, v56, v0, v60, 0, 0, 0, 0            ; D282003C 04F20138
	V_OR_B32_e64 v61, 8, v63, 0, 0, 0, 0               ; D238003D 02027E88
	BUFFER_LOAD_DWORD v61, s[8:11] + v61               ; E0301000 80023D3D
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MUL_F32_e32 v61, v61, v65                        ; 107A833D
	V_OR_B32_e64 v73, 8, v69, 0, 0, 0, 0               ; D2380049 02028A88
	BUFFER_LOAD_DWORD v73, s[8:11] + v73               ; E0301000 80024949
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v61, v73, v66, v61, 0, 0, 0, 0           ; D282003D 04F68549
	V_OR_B32_e64 v73, 8, v71, 0, 0, 0, 0               ; D2380049 02028E88
	BUFFER_LOAD_DWORD v73, s[8:11] + v73               ; E0301000 80024949
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v61, v73, v67, v61, 0, 0, 0, 0           ; D282003D 04F68749
	V_OR_B32_e64 v73, 8, v58, 0, 0, 0, 0               ; D2380049 02027488
	BUFFER_LOAD_DWORD v73, s[8:11] + v73               ; E0301000 80024949
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v61, v73, v72, v61, 0, 0, 0, 0           ; D282003D 04F69149
	V_MAD_F32 v60, v36, v61, v60, 0, 0, 0, 0           ; D282003C 04F27B24
	V_ADD_I32_e32 v73, 42, v62                         ; 4A927CAA
	V_LSHLREV_B32_e32 v73, 4, v73                      ; 34929284
	V_OR_B32_e64 v74, 4, v73, 0, 0, 0, 0               ; D238004A 02029284
	BUFFER_LOAD_DWORD v74, s[8:11] + v74               ; E0301000 80024A4A
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MUL_F32_e32 v74, v74, v65                        ; 1094834A
	V_ADD_I32_e32 v75, 42, v64                         ; 4A9680AA
	V_LSHLREV_B32_e32 v75, 4, v75                      ; 34969684
	V_OR_B32_e64 v76, 4, v75, 0, 0, 0, 0               ; D238004C 02029684
	BUFFER_LOAD_DWORD v76, s[8:11] + v76               ; E0301000 80024C4C
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v74, v76, v66, v74, 0, 0, 0, 0           ; D282004A 052A854C
	V_ADD_I32_e32 v76, 42, v70                         ; 4A988CAA
	V_LSHLREV_B32_e32 v76, 4, v76                      ; 34989884
	V_OR_B32_e64 v77, 4, v76, 0, 0, 0, 0               ; D238004D 02029884
	BUFFER_LOAD_DWORD v77, s[8:11] + v77               ; E0301000 80024D4D
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v74, v77, v67, v74, 0, 0, 0, 0           ; D282004A 052A874D
	V_ADD_I32_e32 v77, 42, v57                         ; 4A9A72AA
	V_LSHLREV_B32_e32 v77, 4, v77                      ; 349A9A84
	V_OR_B32_e64 v78, 4, v77, 0, 0, 0, 0               ; D238004E 02029A84
	BUFFER_LOAD_DWORD v78, s[8:11] + v78               ; E0301000 80024E4E
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v74, v78, v72, v74, 0, 0, 0, 0           ; D282004A 052A914E
	BUFFER_LOAD_DWORD v78, s[8:11] + v73               ; E0301000 80024E49
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MUL_F32_e32 v78, v78, v65                        ; 109C834E
	BUFFER_LOAD_DWORD v79, s[8:11] + v75               ; E0301000 80024F4B
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v78, v79, v66, v78, 0, 0, 0, 0           ; D282004E 053A854F
	BUFFER_LOAD_DWORD v79, s[8:11] + v76               ; E0301000 80024F4C
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v78, v79, v67, v78, 0, 0, 0, 0           ; D282004E 053A874F
	BUFFER_LOAD_DWORD v79, s[8:11] + v77               ; E0301000 80024F4D
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v78, v79, v72, v78, 0, 0, 0, 0           ; D282004E 053A914F
	V_MUL_F32_e32 v79, v13, v78                        ; 109E9D0D
	V_MAD_F32 v79, v56, v74, v79, 0, 0, 0, 0           ; D282004F 053E9538
	V_OR_B32_e64 v80, 8, v73, 0, 0, 0, 0               ; D2380050 02029288
	BUFFER_LOAD_DWORD v80, s[8:11] + v80               ; E0301000 80025050
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MUL_F32_e32 v80, v80, v65                        ; 10A08350
	V_OR_B32_e64 v81, 8, v75, 0, 0, 0, 0               ; D2380051 02029688
	BUFFER_LOAD_DWORD v81, s[8:11] + v81               ; E0301000 80025151
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v80, v81, v66, v80, 0, 0, 0, 0           ; D2820050 05428551
	V_OR_B32_e64 v81, 8, v76, 0, 0, 0, 0               ; D2380051 02029888
	BUFFER_LOAD_DWORD v81, s[8:11] + v81               ; E0301000 80025151
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v80, v81, v67, v80, 0, 0, 0, 0           ; D2820050 05428751
	V_OR_B32_e64 v81, 8, v77, 0, 0, 0, 0               ; D2380051 02029A88
	BUFFER_LOAD_DWORD v81, s[8:11] + v81               ; E0301000 80025151
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v80, v81, v72, v80, 0, 0, 0, 0           ; D2820050 05429151
	V_MAD_F32 v79, v36, v80, v79, 0, 0, 0, 0           ; D282004F 053EA124
	V_ADD_I32_e32 v62, 41, v62                         ; 4A7C7CA9
	V_LSHLREV_B32_e32 v62, 4, v62                      ; 347C7C84
	V_OR_B32_e64 v81, 4, v62, 0, 0, 0, 0               ; D2380051 02027C84
	BUFFER_LOAD_DWORD v81, s[8:11] + v81               ; E0301000 80025151
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MUL_F32_e32 v81, v81, v65                        ; 10A28351
	V_ADD_I32_e32 v64, 41, v64                         ; 4A8080A9
	V_LSHLREV_B32_e32 v64, 4, v64                      ; 34808084
	V_OR_B32_e64 v82, 4, v64, 0, 0, 0, 0               ; D2380052 02028084
	BUFFER_LOAD_DWORD v82, s[8:11] + v82               ; E0301000 80025252
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v81, v82, v66, v81, 0, 0, 0, 0           ; D2820051 05468552
	V_ADD_I32_e32 v70, 41, v70                         ; 4A8C8CA9
	V_LSHLREV_B32_e32 v70, 4, v70                      ; 348C8C84
	V_OR_B32_e64 v82, 4, v70, 0, 0, 0, 0               ; D2380052 02028C84
	BUFFER_LOAD_DWORD v82, s[8:11] + v82               ; E0301000 80025252
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v81, v82, v67, v81, 0, 0, 0, 0           ; D2820051 05468752
	V_ADD_I32_e32 v57, 41, v57                         ; 4A7272A9
	V_LSHLREV_B32_e32 v82, 4, v57                      ; 34A47284
	V_OR_B32_e64 v57, 4, v82, 0, 0, 0, 0               ; D2380039 0202A484
	BUFFER_LOAD_DWORD v57, s[8:11] + v57               ; E0301000 80023939
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v81, v57, v72, v81, 0, 0, 0, 0           ; D2820051 05469139
	BUFFER_LOAD_DWORD v57, s[8:11] + v62               ; E0301000 8002393E
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MUL_F32_e32 v57, v57, v65                        ; 10728339
	BUFFER_LOAD_DWORD v83, s[8:11] + v64               ; E0301000 80025340
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v57, v83, v66, v57, 0, 0, 0, 0           ; D2820039 04E68553
	BUFFER_LOAD_DWORD v83, s[8:11] + v70               ; E0301000 80025346
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v57, v83, v67, v57, 0, 0, 0, 0           ; D2820039 04E68753
	BUFFER_LOAD_DWORD v83, s[8:11] + v82               ; E0301000 80025352
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v83, v83, v72, v57, 0, 0, 0, 0           ; D2820053 04E69153
	V_MUL_F32_e32 v13, v13, v83                        ; 101AA70D
	V_MAD_F32 v13, v56, v81, v13, 0, 0, 0, 0           ; D282000D 0436A338
	V_OR_B32_e64 v56, 8, v62, 0, 0, 0, 0               ; D2380038 02027C88
	BUFFER_LOAD_DWORD v56, s[8:11] + v56               ; E0301000 80023838
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MUL_F32_e32 v56, v56, v65                        ; 10708338
	V_OR_B32_e64 v57, 8, v64, 0, 0, 0, 0               ; D2380039 02028088
	BUFFER_LOAD_DWORD v57, s[8:11] + v57               ; E0301000 80023939
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v56, v57, v66, v56, 0, 0, 0, 0           ; D2820038 04E28539
	V_OR_B32_e64 v57, 8, v70, 0, 0, 0, 0               ; D2380039 02028C88
	BUFFER_LOAD_DWORD v57, s[8:11] + v57               ; E0301000 80023939
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v56, v57, v67, v56, 0, 0, 0, 0           ; D2820038 04E28739
	V_OR_B32_e64 v57, 8, v82, 0, 0, 0, 0               ; D2380039 0202A488
	BUFFER_LOAD_DWORD v57, s[8:11] + v57               ; E0301000 80023939
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v56, v57, v72, v56, 0, 0, 0, 0           ; D2820038 04E29139
	V_MAD_F32 v13, v36, v56, v13, 0, 0, 0, 0           ; D282000D 04367124
	V_MUL_F32_e32 v0, v2, v0                           ; 10000102
	V_MAD_F32 v0, v1, v59, v0, 0, 0, 0, 0              ; D2820000 04027701
	V_MAD_F32 v0, v3, v61, v0, 0, 0, 0, 0              ; D2820000 04027B03
	V_OR_B32_e64 v36, 12, v63, 0, 0, 0, 0              ; D2380024 02027E8C
	BUFFER_LOAD_DWORD v36, s[8:11] + v36               ; E0301000 80022424
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MUL_F32_e32 v36, v36, v65                        ; 10488324
	V_OR_B32_e64 v57, 12, v69, 0, 0, 0, 0              ; D2380039 02028A8C
	BUFFER_LOAD_DWORD v57, s[8:11] + v57               ; E0301000 80023939
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v36, v57, v66, v36, 0, 0, 0, 0           ; D2820024 04928539
	V_OR_B32_e64 v57, 12, v71, 0, 0, 0, 0              ; D2380039 02028E8C
	BUFFER_LOAD_DWORD v57, s[8:11] + v57               ; E0301000 80023939
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v36, v57, v67, v36, 0, 0, 0, 0           ; D2820024 04928739
	V_OR_B32_e64 v57, 12, v58, 0, 0, 0, 0              ; D2380039 0202748C
	BUFFER_LOAD_DWORD v57, s[8:11] + v57               ; E0301000 80023939
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v36, v57, v72, v36, 0, 0, 0, 0           ; D2820024 04929139
	V_MAD_F32 v57, v4, v36, v0, 0, 0, 0, 0             ; D2820039 04024904
	V_MUL_F32_e32 v0, v2, v74                          ; 10009502
	V_MAD_F32 v0, v1, v78, v0, 0, 0, 0, 0              ; D2820000 04029D01
	V_MAD_F32 v0, v3, v80, v0, 0, 0, 0, 0              ; D2820000 0402A103
	V_OR_B32_e64 v36, 12, v73, 0, 0, 0, 0              ; D2380024 0202928C
	BUFFER_LOAD_DWORD v36, s[8:11] + v36               ; E0301000 80022424
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MUL_F32_e32 v36, v36, v65                        ; 10488324
	V_OR_B32_e64 v58, 12, v75, 0, 0, 0, 0              ; D238003A 0202968C
	BUFFER_LOAD_DWORD v58, s[8:11] + v58               ; E0301000 80023A3A
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v36, v58, v66, v36, 0, 0, 0, 0           ; D2820024 0492853A
	V_OR_B32_e64 v58, 12, v76, 0, 0, 0, 0              ; D238003A 0202988C
	BUFFER_LOAD_DWORD v58, s[8:11] + v58               ; E0301000 80023A3A
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v36, v58, v67, v36, 0, 0, 0, 0           ; D2820024 0492873A
	V_OR_B32_e64 v58, 12, v77, 0, 0, 0, 0              ; D238003A 02029A8C
	BUFFER_LOAD_DWORD v58, s[8:11] + v58               ; E0301000 80023A3A
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v36, v58, v72, v36, 0, 0, 0, 0           ; D2820024 0492913A
	V_MAD_F32 v58, v4, v36, v0, 0, 0, 0, 0             ; D282003A 04024904
	V_MUL_F32_e32 v0, v2, v81                          ; 1000A302
	V_MAD_F32 v0, v1, v83, v0, 0, 0, 0, 0              ; D2820000 0402A701
	V_MAD_F32 v0, v3, v56, v0, 0, 0, 0, 0              ; D2820000 04027103
	V_OR_B32_e64 v36, 12, v62, 0, 0, 0, 0              ; D2380024 02027C8C
	BUFFER_LOAD_DWORD v36, s[8:11] + v36               ; E0301000 80022424
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MUL_F32_e32 v36, v36, v65                        ; 10488324
	V_OR_B32_e64 v56, 12, v64, 0, 0, 0, 0              ; D2380038 0202808C
	BUFFER_LOAD_DWORD v56, s[8:11] + v56               ; E0301000 80023838
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v36, v56, v66, v36, 0, 0, 0, 0           ; D2820024 04928538
	V_OR_B32_e64 v56, 12, v70, 0, 0, 0, 0              ; D2380038 02028C8C
	BUFFER_LOAD_DWORD v56, s[8:11] + v56               ; E0301000 80023838
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v36, v56, v67, v36, 0, 0, 0, 0           ; D2820024 04928738
	V_OR_B32_e64 v56, 12, v82, 0, 0, 0, 0              ; D2380038 0202A48C
	BUFFER_LOAD_DWORD v56, s[8:11] + v56               ; E0301000 80023838
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v36, v56, v72, v36, 0, 0, 0, 0           ; D2820024 04929138
	V_MAD_F32 v59, v4, v36, v0, 0, 0, 0, 0             ; D282003B 04024904
	V_MOV_B32_e32 v56, v79                             ; 7E70034F
	V_MOV_B32_e32 v36, v60                             ; 7E48033C
	S_OR_B64 exec, exec, s[2:3]                        ; 88FE027E
	V_MUL_F32_e64 v0, v15, v55, 0, 0, 0, 0             ; D2100000 02026F0F
	V_MAD_F32 v0, v14, v54, v0, 0, 0, 0, 0             ; D2820000 04026D0E
	V_MAD_F32 v0, v16, v50, v0, 0, 0, 0, 0             ; D2820000 04026510
	V_MAD_F32 v0, v17, v45, v0, 0, 0, 0, 0             ; D2820000 04025B11
	V_MUL_F32_e64 v45, v15, v53, 0, 0, 0, 0            ; D210002D 02026B0F
	V_MAD_F32 v45, v14, v52, v45, 0, 0, 0, 0           ; D282002D 04B6690E
	V_MAD_F32 v45, v16, v48, v45, 0, 0, 0, 0           ; D282002D 04B66110
	V_MAD_F32 v14, v17, v44, v45, 0, 0, 0, 0           ; D282000E 04B65911
	EXP 15, 32, 0, 0, 0, v14, v0, v9, v10              ; F800020F 0A09000E
	S_WAITCNT expcnt(0)                                ; BF8C070F
	V_MUL_F32_e64 v0, v13, v47, 0, 0, 0, 0             ; D2100000 02025F0D
	V_MAD_F32 v0, v56, v43, v0, 0, 0, 0, 0             ; D2820000 04025738
	V_MAD_F32 v0, v36, v41, v0, 0, 0, 0, 0             ; D2820000 04025324
	V_MUL_F32_e64 v9, v13, v51, 0, 0, 0, 0             ; D2100009 0202670D
	V_MAD_F32 v9, v56, v49, v9, 0, 0, 0, 0             ; D2820009 04266338
	V_MAD_F32 v9, v36, v46, v9, 0, 0, 0, 0             ; D2820009 04265D24
	V_MUL_F32_e64 v10, v13, v42, 0, 0, 0, 0            ; D210000A 0202550D
	V_MAD_F32 v10, v56, v40, v10, 0, 0, 0, 0           ; D282000A 042A5138
	V_MAD_F32 v10, v36, v39, v10, 0, 0, 0, 0           ; D282000A 042A4F24
	V_ADD_F32_e64 v10, v10, 0, 0, 0, 0, 1              ; D206000A 2201010A
	V_MUL_F32_e64 v11, v58, v38, 0, 0, 0, 0            ; D210000B 02024D3A
	V_MAD_F32 v11, v59, v37, v11, 0, 0, 0, 0           ; D282000B 042E4B3B
	V_MAD_F32 v11, v57, v35, v11, 0, 0, 0, 0           ; D282000B 042E4739
	V_MAD_F32 v11, v4, v26, v11, 0, 0, 0, 0            ; D282000B 042E3504
	V_ADD_F32_e32 v11, -1.000000e-01, v11              ; 061616FF BDCCCCCD
	EXP 15, 33, 0, 0, 0, v9, v10, v0, v11              ; F800021F 0B000A09
	S_WAITCNT expcnt(0)                                ; BF8C070F
	V_MOV_B32_e32 v0, s1                               ; 7E000201
	V_MOV_B32_e32 v9, s0                               ; 7E120200
	V_MAD_F32 v10, v8, v9, v0, 0, 0, 0, 0              ; D282000A 04021308
	V_SUB_F32_e32 v11, 1.000000e+00, v10               ; 081614F2
	V_MAD_F32 v12, v5, v9, v0, 0, 0, 0, 0              ; D282000C 04021305
	V_MUL_F32_e32 v12, v12, v12                        ; 1018190C
	V_MAD_F32 v12, v10, v12, v11, 0, 0, 0, 0           ; D282000C 042E190A
	V_MAD_F32 v13, v6, v9, v0, 0, 0, 0, 0              ; D282000D 04021306
	V_MUL_F32_e32 v13, v13, v13                        ; 101A1B0D
	V_MAD_F32 v13, v10, v13, v11, 0, 0, 0, 0           ; D282000D 042E1B0A
	V_MAD_F32 v0, v7, v9, v0, 0, 0, 0, 0               ; D2820000 04021307
	V_MUL_F32_e32 v0, v0, v0                           ; 10000100
	V_MAD_F32 v0, v10, v0, v11, 0, 0, 0, 0             ; D2820000 042E010A
	EXP 15, 34, 0, 0, 0, v0, v13, v12, v10             ; F800022F 0A0C0D00
	S_WAITCNT expcnt(0)                                ; BF8C070F
	V_MUL_F32_e64 v0, v58, v34, 0, 0, 0, 0             ; D2100000 0202453A
	V_MAD_F32 v0, v59, v33, v0, 0, 0, 0, 0             ; D2820000 0402433B
	V_MAD_F32 v0, v57, v25, v0, 0, 0, 0, 0             ; D2820000 04023339
	V_MAD_F32 v0, v4, v21, v0, 0, 0, 0, 0              ; D2820000 04022B04
	V_MUL_F32_e64 v5, v58, v32, 0, 0, 0, 0             ; D2100005 0202413A
	V_MAD_F32 v5, v59, v31, v5, 0, 0, 0, 0             ; D2820005 04163F3B
	V_MAD_F32 v5, v57, v24, v5, 0, 0, 0, 0             ; D2820005 04163139
	V_MAD_F32 v5, v4, v20, v5, 0, 0, 0, 0              ; D2820005 04162904
	V_MUL_F32_e64 v6, v58, v30, 0, 0, 0, 0             ; D2100006 02023D3A
	V_MAD_F32 v6, v59, v29, v6, 0, 0, 0, 0             ; D2820006 041A3B3B
	V_MAD_F32 v6, v57, v23, v6, 0, 0, 0, 0             ; D2820006 041A2F39
	V_MAD_F32 v6, v4, v19, v6, 0, 0, 0, 0              ; D2820006 041A2704
	V_MUL_F32_e64 v7, v58, v28, 0, 0, 0, 0             ; D2100007 0202393A
	V_MAD_F32 v7, v59, v27, v7, 0, 0, 0, 0             ; D2820007 041E373B
	V_MAD_F32 v7, v57, v22, v7, 0, 0, 0, 0             ; D2820007 041E2D39
	V_MAD_F32 v1, v4, v18, v7, 0, 0, 0, 0              ; D2820001 041E2504
	EXP 15, 12, 0, 1, 0, v1, v6, v5, v0                ; F80008CF 00050601
	S_ENDPGM                                           ; BF810000

FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL SAMP[1]
DCL CONST[0..1]
DCL TEMP[0..4], LOCAL
IMM[0] FLT32 {    0.0000, 65504.0000,     0.5000,    12.9200}
IMM[1] FLT32 {    0.4167,     1.0550,    -0.0550,     0.0031}
IMM[2] FLT32 {    0.2125,     0.7154,     0.0721,     0.0000}
  0: MOV TEMP[0].xy, IN[0].xyyy
  1: TEX TEMP[0], TEMP[0], SAMP[0], 2D
  2: MAX TEMP[0], TEMP[0], IMM[0].xxxx
  3: MIN TEMP[0], TEMP[0], IMM[0].yyyy
  4: MOV TEMP[1].w, TEMP[0].wwww
  5: MUL TEMP[1].xyz, TEMP[0].xyzz, CONST[0].xxxx
  6: MOV TEMP[0].xy, IMM[0].zzzz
  7: TEX TEMP[0].x, TEMP[0], SAMP[1], 2D
  8: MUL TEMP[1].xyz, TEMP[1].xyzz, TEMP[0].xxxx
  9: MUL TEMP[2].xyz, TEMP[1].xyzz, IMM[0].wwww
 10: POW TEMP[3].x, TEMP[1].xxxx, IMM[1].xxxx
 11: POW TEMP[3].y, TEMP[1].yyyy, IMM[1].xxxx
 12: POW TEMP[3].z, TEMP[1].zzzz, IMM[1].xxxx
 13: MAD TEMP[3].xyz, TEMP[3].xyzz, IMM[1].yyyy, IMM[1].zzzz
 14: FSLT TEMP[4].x, TEMP[1].xxxx, IMM[1].wwww
 15: UIF TEMP[4].xxxx :0
 16:   MOV TEMP[4].x, TEMP[2].xxxx
 17: ELSE :0
 18:   MOV TEMP[4].x, TEMP[3].xxxx
 19: ENDIF
 20: MOV TEMP[0].x, TEMP[4].xxxx
 21: FSLT TEMP[4].x, TEMP[1].yyyy, IMM[1].wwww
 22: UIF TEMP[4].xxxx :0
 23:   MOV TEMP[4].x, TEMP[2].yyyy
 24: ELSE :0
 25:   MOV TEMP[4].x, TEMP[3].yyyy
 26: ENDIF
 27: MOV TEMP[0].y, TEMP[4].xxxx
 28: FSLT TEMP[4].x, TEMP[1].zzzz, IMM[1].wwww
 29: UIF TEMP[4].xxxx :0
 30:   MOV TEMP[2].x, TEMP[2].zzzz
 31: ELSE :0
 32:   MOV TEMP[2].x, TEMP[3].zzzz
 33: ENDIF
 34: MOV TEMP[0].z, TEMP[2].xxxx
 35: MOV_SAT TEMP[1].xyz, TEMP[0].xyzz
 36: DP3 TEMP[0].x, TEMP[1].xyzz, IMM[2].xyzz
 37: LRP TEMP[0].xyz, CONST[1].yyyy, TEMP[1].xyzz, TEMP[0].xxxx
 38: LRP TEMP[1].xyz, CONST[1].zzzz, CONST[1].wwww, TEMP[0].xyzz
 39: MOV_SAT TEMP[1].xyz, TEMP[1].xyzz
 40: MOV OUT[0], TEMP[1]
 41: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %21 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
  %22 = load <16 x i8> addrspace(2)* %21, !tbaa !0
  %23 = call float @llvm.SI.load.const(<16 x i8> %22, i32 0)
  %24 = call float @llvm.SI.load.const(<16 x i8> %22, i32 20)
  %25 = call float @llvm.SI.load.const(<16 x i8> %22, i32 24)
  %26 = call float @llvm.SI.load.const(<16 x i8> %22, i32 28)
  %27 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0
  %28 = load <32 x i8> addrspace(2)* %27, !tbaa !0
  %29 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0
  %30 = load <16 x i8> addrspace(2)* %29, !tbaa !0
  %31 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 1
  %32 = load <32 x i8> addrspace(2)* %31, !tbaa !0
  %33 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 1
  %34 = load <16 x i8> addrspace(2)* %33, !tbaa !0
  %35 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %4, <2 x i32> %6)
  %36 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %4, <2 x i32> %6)
  %37 = bitcast float %35 to i32
  %38 = bitcast float %36 to i32
  %39 = insertelement <2 x i32> undef, i32 %37, i32 0
  %40 = insertelement <2 x i32> %39, i32 %38, i32 1
  %41 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %40, <32 x i8> %28, <16 x i8> %30, i32 2)
  %42 = extractelement <4 x float> %41, i32 0
  %43 = extractelement <4 x float> %41, i32 1
  %44 = extractelement <4 x float> %41, i32 2
  %45 = extractelement <4 x float> %41, i32 3
  %46 = fcmp uge float %42, 0.000000e+00
  %47 = select i1 %46, float %42, float 0.000000e+00
  %48 = fcmp uge float %43, 0.000000e+00
  %49 = select i1 %48, float %43, float 0.000000e+00
  %50 = fcmp uge float %44, 0.000000e+00
  %51 = select i1 %50, float %44, float 0.000000e+00
  %52 = fcmp uge float %45, 0.000000e+00
  %53 = select i1 %52, float %45, float 0.000000e+00
  %54 = fcmp uge float %47, 6.550400e+04
  %55 = select i1 %54, float 6.550400e+04, float %47
  %56 = fcmp uge float %49, 6.550400e+04
  %57 = select i1 %56, float 6.550400e+04, float %49
  %58 = fcmp uge float %51, 6.550400e+04
  %59 = select i1 %58, float 6.550400e+04, float %51
  %60 = fcmp uge float %53, 6.550400e+04
  %61 = select i1 %60, float 6.550400e+04, float %53
  %62 = fmul float %55, %23
  %63 = fmul float %57, %23
  %64 = fmul float %59, %23
  %65 = bitcast float 5.000000e-01 to i32
  %66 = bitcast float 5.000000e-01 to i32
  %67 = insertelement <2 x i32> undef, i32 %65, i32 0
  %68 = insertelement <2 x i32> %67, i32 %66, i32 1
  %69 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %68, <32 x i8> %32, <16 x i8> %34, i32 2)
  %70 = extractelement <4 x float> %69, i32 0
  %71 = fmul float %62, %70
  %72 = fmul float %63, %70
  %73 = fmul float %64, %70
  %74 = fmul float %71, 0x4029D70A40000000
  %75 = fmul float %72, 0x4029D70A40000000
  %76 = fmul float %73, 0x4029D70A40000000
  %77 = call float @llvm.pow.f32(float %71, float 0x3FDAAAAAA0000000)
  %78 = call float @llvm.pow.f32(float %72, float 0x3FDAAAAAA0000000)
  %79 = call float @llvm.pow.f32(float %73, float 0x3FDAAAAAA0000000)
  %80 = fmul float %77, 0x3FF0E147A0000000
  %81 = fadd float %80, 0xBFAC28F5C0000000
  %82 = fmul float %78, 0x3FF0E147A0000000
  %83 = fadd float %82, 0xBFAC28F5C0000000
  %84 = fmul float %79, 0x3FF0E147A0000000
  %85 = fadd float %84, 0xBFAC28F5C0000000
  %86 = fcmp olt float %71, 0x3F69A5C380000000
  %87 = sext i1 %86 to i32
  %88 = bitcast i32 %87 to float
  %89 = bitcast float %88 to i32
  %90 = icmp ne i32 %89, 0
  %. = select i1 %90, float %74, float %81
  %91 = fcmp olt float %72, 0x3F69A5C380000000
  %92 = sext i1 %91 to i32
  %93 = bitcast i32 %92 to float
  %94 = bitcast float %93 to i32
  %95 = icmp ne i32 %94, 0
  %temp16.1 = select i1 %95, float %75, float %83
  %96 = fcmp olt float %73, 0x3F69A5C380000000
  %97 = sext i1 %96 to i32
  %98 = bitcast i32 %97 to float
  %99 = bitcast float %98 to i32
  %100 = icmp ne i32 %99, 0
  %.26 = select i1 %100, float %76, float %85
  %101 = call float @llvm.AMDIL.clamp.(float %., float 0.000000e+00, float 1.000000e+00)
  %102 = call float @llvm.AMDIL.clamp.(float %temp16.1, float 0.000000e+00, float 1.000000e+00)
  %103 = call float @llvm.AMDIL.clamp.(float %.26, float 0.000000e+00, float 1.000000e+00)
  %104 = fmul float %101, 0x3FCB333340000000
  %105 = fmul float %102, 0x3FE6E48E80000000
  %106 = fadd float %105, %104
  %107 = fmul float %103, 0x3FB2752540000000
  %108 = fadd float %106, %107
  %109 = call float @llvm.AMDGPU.lrp(float %24, float %101, float %108)
  %110 = call float @llvm.AMDGPU.lrp(float %24, float %102, float %108)
  %111 = call float @llvm.AMDGPU.lrp(float %24, float %103, float %108)
  %112 = call float @llvm.AMDGPU.lrp(float %25, float %26, float %109)
  %113 = call float @llvm.AMDGPU.lrp(float %25, float %26, float %110)
  %114 = call float @llvm.AMDGPU.lrp(float %25, float %26, float %111)
  %115 = call float @llvm.AMDIL.clamp.(float %112, float 0.000000e+00, float 1.000000e+00)
  %116 = call float @llvm.AMDIL.clamp.(float %113, float 0.000000e+00, float 1.000000e+00)
  %117 = call float @llvm.AMDIL.clamp.(float %114, float 0.000000e+00, float 1.000000e+00)
  %118 = call i32 @llvm.SI.packf16(float %115, float %116)
  %119 = bitcast i32 %118 to float
  %120 = call i32 @llvm.SI.packf16(float %117, float %61)
  %121 = bitcast i32 %120 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %119, float %121, float %119, float %121)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readonly
declare float @llvm.pow.f32(float, float) #2

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #3

; Function Attrs: readnone
declare float @llvm.AMDGPU.lrp(float, float, float) #3

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { nounwind readonly }
attributes #3 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR7 in %vreg4, %VGPR0 in %vreg5, %VGPR1 in %vreg6

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR7 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR7
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-def>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 0; mem:LD16[%32](align=8)(tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 0; mem:LD32[%29](tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = IMAGE_SAMPLE_V4_V2 15, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%SGPR6_SGPR7<def> = V_CMP_U_F32_e64 %VGPR1, %VGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8_SGPR9<def> = V_CMP_GE_F32_e64 %VGPR1, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = S_OR_B64 %SGPR8_SGPR9<kill>, %SGPR6_SGPR7<kill>
	%VGPR4<def> = V_CNDMASK_B32_e64 0.000000e+00, %VGPR1, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_MOV_B32_e32 6.550400e+04, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %VGPR4, %VGPR5, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8_SGPR9<def> = V_CMP_U_F32_e64 %VGPR4, %VGPR4, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = S_OR_B64 %SGPR6_SGPR7<kill>, %SGPR8_SGPR9<kill>
	%VGPR4<def> = V_CNDMASK_B32_e64 %VGPR4<kill>, %VGPR5, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%22](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 0; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR4<def> = V_MUL_F32_e32 %SGPR0, %VGPR4<kill>, %EXEC<imp-use>
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 4; mem:LD16[%38](align=8)(tbaa=!"const")
	%SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 8; mem:LD32[%35](tbaa=!"const")
	%VGPR6<def> = V_MOV_B32_e32 1056964608, %EXEC<imp-use>, %VGPR6_VGPR7<imp-def>
	%VGPR7<def> = V_MOV_B32_e32 %VGPR6, %EXEC<imp-use>, %VGPR6_VGPR7<imp-def>
	S_WAITCNT 127
	%VGPR6<def> = IMAGE_SAMPLE_V1_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR6_VGPR7<kill>, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23<kill>, %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR4<def> = V_MUL_F32_e32 %VGPR4<kill>, %VGPR6, %EXEC<imp-use>
	%VGPR7<def> = V_LOG_F32_e32 %VGPR4, %EXEC<imp-use>
	%VGPR7<def> = V_MUL_LEGACY_F32_e32 4.166667e-01, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_EXP_F32_e32 %VGPR7<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_MOV_B32_e32 -5.500000e-02, %EXEC<imp-use>
	%VGPR9<def> = V_MOV_B32_e32 1.055000e+00, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR7<kill>, %VGPR9, %VGPR8, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR10<def> = V_MOV_B32_e32 3.130800e-03, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_LT_F32_e64 %VGPR4, %VGPR10, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e32 1.292000e+01, %VGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_CNDMASK_B32_e64 %VGPR7<kill>, %VGPR4<kill>, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_ADD_F32_e64 0, %VGPR4<kill>, 0, 1, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_U_F32_e64 %VGPR0, %VGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_GE_F32_e64 %VGPR0, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_OR_B64 %SGPR4_SGPR5<kill>, %SGPR2_SGPR3<kill>
	%VGPR7<def> = V_CNDMASK_B32_e64 0.000000e+00, %VGPR0, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR7, %VGPR5, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_U_F32_e64 %VGPR7, %VGPR7, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_OR_B64 %SGPR2_SGPR3<kill>, %SGPR4_SGPR5<kill>
	%VGPR7<def> = V_CNDMASK_B32_e64 %VGPR7<kill>, %VGPR5, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_MUL_F32_e32 %SGPR0, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MUL_F32_e32 %VGPR7<kill>, %VGPR6, %EXEC<imp-use>
	%VGPR11<def> = V_LOG_F32_e32 %VGPR7, %EXEC<imp-use>
	%VGPR11<def> = V_MUL_LEGACY_F32_e32 4.166667e-01, %VGPR11<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_EXP_F32_e32 %VGPR11<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_MAD_F32 %VGPR11<kill>, %VGPR9, %VGPR8, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_LT_F32_e64 %VGPR7, %VGPR10, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_MUL_F32_e32 1.292000e+01, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_CNDMASK_B32_e64 %VGPR11<kill>, %VGPR7<kill>, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_ADD_F32_e64 0, %VGPR7<kill>, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR11<def> = V_MUL_F32_e32 2.125000e-01, %VGPR7, %EXEC<imp-use>
	%VGPR12<def> = V_MOV_B32_e32 7.154000e-01, %EXEC<imp-use>
	%VGPR11<def> = V_MAD_F32 %VGPR4, %VGPR12<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_U_F32_e64 %VGPR2, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_GE_F32_e64 %VGPR2, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_OR_B64 %SGPR4_SGPR5<kill>, %SGPR2_SGPR3<kill>
	%VGPR12<def> = V_CNDMASK_B32_e64 0.000000e+00, %VGPR2, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR12, %VGPR5, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_U_F32_e64 %VGPR12, %VGPR12, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_OR_B64 %SGPR2_SGPR3<kill>, %SGPR4_SGPR5<kill>
	%VGPR12<def> = V_CNDMASK_B32_e64 %VGPR12<kill>, %VGPR5, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR12<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %VGPR12<kill>, %VGPR6<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_LOG_F32_e32 %VGPR6, %EXEC<imp-use>
	%VGPR12<def> = V_MUL_LEGACY_F32_e32 4.166667e-01, %VGPR12<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_EXP_F32_e32 %VGPR12<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_MAD_F32 %VGPR12<kill>, %VGPR9<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = V_CMP_LT_F32_e64 %VGPR6, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 1.292000e+01, %VGPR6<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_CNDMASK_B32_e64 %VGPR8<kill>, %VGPR6<kill>, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_ADD_F32_e64 0, %VGPR6<kill>, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_MOV_B32_e32 7.210000e-02, %EXEC<imp-use>
	%VGPR8<def> = V_MAD_F32 %VGPR6, %VGPR8<kill>, %VGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 5; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR9<def> = V_SUB_F32_e64 1.000000e+00, %SGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_F32_e32 %VGPR9<kill>, %VGPR8<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %SGPR0, %VGPR4<kill>, %VGPR8, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 6; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR9<def> = V_SUB_F32_e64 1.000000e+00, %SGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e32 %VGPR9, %VGPR4<kill>, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11<kill>, 7; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR10<def> = V_MOV_B32_e32 %SGPR2<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %SGPR1, %VGPR10, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_ADD_F32_e64 0, %VGPR4<kill>, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %SGPR0, %VGPR7<kill>, %VGPR8, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_MUL_F32_e32 %VGPR9, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %SGPR1, %VGPR10, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_ADD_F32_e64 0, %VGPR7<kill>, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR7<kill>, %VGPR4<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %SGPR0<kill>, %VGPR6<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %VGPR9<kill>, %VGPR6<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %SGPR1<kill>, %VGPR10<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_ADD_F32_e64 0, %VGPR6<kill>, 0, 1, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = V_CMP_U_F32_e64 %VGPR3, %VGPR3, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR3, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_OR_B64 %SGPR2_SGPR3<kill>, %SGPR0_SGPR1<kill>
	%VGPR0<def> = V_CNDMASK_B32_e64 0.000000e+00, %VGPR3, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	%SGPR0_SGPR1<def> = V_CMP_GE_F32_e64 %VGPR0, %VGPR5, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_U_F32_e64 %VGPR0, %VGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_OR_B64 %SGPR0_SGPR1<kill>, %SGPR2_SGPR3<kill>
	%VGPR0<def> = V_CNDMASK_B32_e64 %VGPR0<kill>, %VGPR5<kill>, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR6<kill>, %VGPR0<kill>, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR4<kill>, %VGPR0<kill>, %VGPR4, %VGPR0, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_WQM_B64 exec, exec                                                    ; BEFE0A7E
	S_MOV_B32 m0, s7                                                        ; BEFC0307
	V_INTERP_P1_F32 v3, v0, 1, 0, [m0]                                      ; C80C0100
	V_INTERP_P2_F32 v3, [v3], v1, 1, 0, [m0]                                ; C80D0101
	V_INTERP_P1_F32 v2, v0, 0, 0, [m0]                                      ; C8080000
	V_INTERP_P2_F32 v2, [v2], v1, 0, 0, [m0]                                ; C8090001
	S_LOAD_DWORDX4 s[8:11], s[2:3], 0                                       ; C0840300
	S_LOAD_DWORDX8 s[12:19], s[4:5], 0                                      ; C0C60500
	S_WAITCNT lgkmcnt(0)                                                    ; BF8C007F
	IMAGE_SAMPLE v[0:3], 15, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[12:19], s[8:11] ; F0800F00 00430002
	S_WAITCNT vmcnt(0)                                                      ; BF8C0770
	V_CMP_U_F32_e64 s[6:7], v1, v1, 0, 0, 0, 0                              ; D0100006 02020301
	V_CMP_GE_F32_e64 s[8:9], v1, 0.000000e+00, 0, 0, 0, 0                   ; D00C0008 02010101
	S_OR_B64 s[6:7], s[8:9], s[6:7]                                         ; 88860608
	V_CNDMASK_B32_e64 v4, 0.000000e+00, v1, s[6:7], 0, 0, 0, 0              ; D2000004 001A0280
	V_MOV_B32_e32 v5, 6.550400e+04                                          ; 7E0A02FF 477FE000
	V_CMP_GE_F32_e64 s[6:7], v4, v5, 0, 0, 0, 0                             ; D00C0006 02020B04
	V_CMP_U_F32_e64 s[8:9], v4, v4, 0, 0, 0, 0                              ; D0100008 02020904
	S_OR_B64 s[6:7], s[6:7], s[8:9]                                         ; 88860806
	V_CNDMASK_B32_e64 v4, v4, v5, s[6:7], 0, 0, 0, 0                        ; D2000004 001A0B04
	S_LOAD_DWORDX4 s[8:11], s[0:1], 0                                       ; C0840100
	S_WAITCNT lgkmcnt(0)                                                    ; BF8C007F
	S_BUFFER_LOAD_DWORD s0, s[8:11], 0                                      ; C2000900
	S_WAITCNT lgkmcnt(0)                                                    ; BF8C007F
	V_MUL_F32_e32 v4, s0, v4                                                ; 10080800
	S_LOAD_DWORDX4 s[12:15], s[2:3], 4                                      ; C0860304
	S_LOAD_DWORDX8 s[16:23], s[4:5], 8                                      ; C0C80508
	V_MOV_B32_e32 v6, 1056964608                                            ; 7E0C02F0
	V_MOV_B32_e32 v7, v6                                                    ; 7E0E0306
	S_WAITCNT lgkmcnt(0)                                                    ; BF8C007F
	IMAGE_SAMPLE v6, 1, 0, 0, 0, 0, 0, 0, 0, v[6:7], s[16:23], s[12:15]     ; F0800100 00640606
	S_WAITCNT vmcnt(0)                                                      ; BF8C0770
	V_MUL_F32_e32 v4, v4, v6                                                ; 10080D04
	V_LOG_F32_e32 v7, v4                                                    ; 7E0E4F04
	V_MUL_LEGACY_F32_e32 v7, 4.166667e-01, v7                               ; 0E0E0EFF 3ED55555
	V_EXP_F32_e32 v7, v7                                                    ; 7E0E4B07
	V_MOV_B32_e32 v8, -5.500000e-02                                         ; 7E1002FF BD6147AE
	V_MOV_B32_e32 v9, 1.055000e+00                                          ; 7E1202FF 3F870A3D
	V_MAD_F32 v7, v7, v9, v8, 0, 0, 0, 0                                    ; D2820007 04221307
	V_MOV_B32_e32 v10, 3.130800e-03                                         ; 7E1402FF 3B4D2E1C
	V_CMP_LT_F32_e64 s[2:3], v4, v10, 0, 0, 0, 0                            ; D0020002 02021504
	V_MUL_F32_e32 v4, 1.292000e+01, v4                                      ; 100808FF 414EB852
	V_CNDMASK_B32_e64 v4, v7, v4, s[2:3], 0, 0, 0, 0                        ; D2000004 000A0907
	V_ADD_F32_e64 v4, 0, v4, 0, 1, 0, 0                                     ; D2060804 02020880
	V_CMP_U_F32_e64 s[2:3], v0, v0, 0, 0, 0, 0                              ; D0100002 02020100
	V_CMP_GE_F32_e64 s[4:5], v0, 0.000000e+00, 0, 0, 0, 0                   ; D00C0004 02010100
	S_OR_B64 s[2:3], s[4:5], s[2:3]                                         ; 88820204
	V_CNDMASK_B32_e64 v7, 0.000000e+00, v0, s[2:3], 0, 0, 0, 0              ; D2000007 000A0080
	V_CMP_GE_F32_e64 s[2:3], v7, v5, 0, 0, 0, 0                             ; D00C0002 02020B07
	V_CMP_U_F32_e64 s[4:5], v7, v7, 0, 0, 0, 0                              ; D0100004 02020F07
	S_OR_B64 s[2:3], s[2:3], s[4:5]                                         ; 88820402
	V_CNDMASK_B32_e64 v7, v7, v5, s[2:3], 0, 0, 0, 0                        ; D2000007 000A0B07
	V_MUL_F32_e32 v7, s0, v7                                                ; 100E0E00
	V_MUL_F32_e32 v7, v7, v6                                                ; 100E0D07
	V_LOG_F32_e32 v11, v7                                                   ; 7E164F07
	V_MUL_LEGACY_F32_e32 v11, 4.166667e-01, v11                             ; 0E1616FF 3ED55555
	V_EXP_F32_e32 v11, v11                                                  ; 7E164B0B
	V_MAD_F32 v11, v11, v9, v8, 0, 0, 0, 0                                  ; D282000B 0422130B
	V_CMP_LT_F32_e64 s[2:3], v7, v10, 0, 0, 0, 0                            ; D0020002 02021507
	V_MUL_F32_e32 v7, 1.292000e+01, v7                                      ; 100E0EFF 414EB852
	V_CNDMASK_B32_e64 v7, v11, v7, s[2:3], 0, 0, 0, 0                       ; D2000007 000A0F0B
	V_ADD_F32_e64 v7, 0, v7, 0, 1, 0, 0                                     ; D2060807 02020E80
	V_MUL_F32_e32 v11, 2.125000e-01, v7                                     ; 10160EFF 3E59999A
	V_MOV_B32_e32 v12, 7.154000e-01                                         ; 7E1802FF 3F372474
	V_MAD_F32 v11, v4, v12, v11, 0, 0, 0, 0                                 ; D282000B 042E1904
	V_CMP_U_F32_e64 s[2:3], v2, v2, 0, 0, 0, 0                              ; D0100002 02020502
	V_CMP_GE_F32_e64 s[4:5], v2, 0.000000e+00, 0, 0, 0, 0                   ; D00C0004 02010102
	S_OR_B64 s[2:3], s[4:5], s[2:3]                                         ; 88820204
	V_CNDMASK_B32_e64 v12, 0.000000e+00, v2, s[2:3], 0, 0, 0, 0             ; D200000C 000A0480
	V_CMP_GE_F32_e64 s[2:3], v12, v5, 0, 0, 0, 0                            ; D00C0002 02020B0C
	V_CMP_U_F32_e64 s[4:5], v12, v12, 0, 0, 0, 0                            ; D0100004 0202190C
	S_OR_B64 s[2:3], s[2:3], s[4:5]                                         ; 88820402
	V_CNDMASK_B32_e64 v12, v12, v5, s[2:3], 0, 0, 0, 0                      ; D200000C 000A0B0C
	V_MUL_F32_e32 v12, s0, v12                                              ; 10181800
	V_MUL_F32_e32 v6, v12, v6                                               ; 100C0D0C
	V_LOG_F32_e32 v12, v6                                                   ; 7E184F06
	V_MUL_LEGACY_F32_e32 v12, 4.166667e-01, v12                             ; 0E1818FF 3ED55555
	V_EXP_F32_e32 v12, v12                                                  ; 7E184B0C
	V_MAD_F32 v8, v12, v9, v8, 0, 0, 0, 0                                   ; D2820008 0422130C
	V_CMP_LT_F32_e64 s[0:1], v6, v10, 0, 0, 0, 0                            ; D0020000 02021506
	V_MUL_F32_e32 v6, 1.292000e+01, v6                                      ; 100C0CFF 414EB852
	V_CNDMASK_B32_e64 v6, v8, v6, s[0:1], 0, 0, 0, 0                        ; D2000006 00020D08
	V_ADD_F32_e64 v6, 0, v6, 0, 1, 0, 0                                     ; D2060806 02020C80
	V_MOV_B32_e32 v8, 7.210000e-02                                          ; 7E1002FF 3D93A92A
	V_MAD_F32 v8, v6, v8, v11, 0, 0, 0, 0                                   ; D2820008 042E1106
	S_BUFFER_LOAD_DWORD s0, s[8:11], 5                                      ; C2000905
	S_WAITCNT lgkmcnt(0)                                                    ; BF8C007F
	V_SUB_F32_e64 v9, 1.000000e+00, s0, 0, 0, 0, 0                          ; D2080009 020000F2
	V_MUL_F32_e32 v8, v9, v8                                                ; 10101109
	V_MAD_F32 v4, s0, v4, v8, 0, 0, 0, 0                                    ; D2820004 04220800
	S_BUFFER_LOAD_DWORD s1, s[8:11], 6                                      ; C2008906
	S_WAITCNT lgkmcnt(0)                                                    ; BF8C007F
	V_SUB_F32_e64 v9, 1.000000e+00, s1, 0, 0, 0, 0                          ; D2080009 020002F2
	V_MUL_F32_e32 v4, v9, v4                                                ; 10080909
	S_BUFFER_LOAD_DWORD s2, s[8:11], 7                                      ; C2010907
	S_WAITCNT lgkmcnt(0)                                                    ; BF8C007F
	V_MOV_B32_e32 v10, s2                                                   ; 7E140202
	V_MAD_F32 v4, s1, v10, v4, 0, 0, 0, 0                                   ; D2820004 04121401
	V_ADD_F32_e64 v4, 0, v4, 0, 1, 0, 0                                     ; D2060804 02020880
	V_MAD_F32 v7, s0, v7, v8, 0, 0, 0, 0                                    ; D2820007 04220E00
	V_MUL_F32_e32 v7, v9, v7                                                ; 100E0F09
	V_MAD_F32 v7, s1, v10, v7, 0, 0, 0, 0                                   ; D2820007 041E1401
	V_ADD_F32_e64 v7, 0, v7, 0, 1, 0, 0                                     ; D2060807 02020E80
	V_CVT_PKRTZ_F16_F32_e32 v4, v7, v4                                      ; 5E080907
	V_MAD_F32 v6, s0, v6, v8, 0, 0, 0, 0                                    ; D2820006 04220C00
	V_MUL_F32_e32 v6, v9, v6                                                ; 100C0D09
	V_MAD_F32 v6, s1, v10, v6, 0, 0, 0, 0                                   ; D2820006 041A1401
	V_ADD_F32_e64 v6, 0, v6, 0, 1, 0, 0                                     ; D2060806 02020C80
	V_CMP_U_F32_e64 s[0:1], v3, v3, 0, 0, 0, 0                              ; D0100000 02020703
	V_CMP_GE_F32_e64 s[2:3], v3, 0.000000e+00, 0, 0, 0, 0                   ; D00C0002 02010103
	S_OR_B64 s[0:1], s[2:3], s[0:1]                                         ; 88800002
	V_CNDMASK_B32_e64 v0, 0.000000e+00, v3, s[0:1], 0, 0, 0, 0              ; D2000000 00020680
	V_CMP_GE_F32_e64 s[0:1], v0, v5, 0, 0, 0, 0                             ; D00C0000 02020B00
	V_CMP_U_F32_e64 s[2:3], v0, v0, 0, 0, 0, 0                              ; D0100002 02020100
	S_OR_B64 s[0:1], s[0:1], s[2:3]                                         ; 88800200
	V_CNDMASK_B32_e64 v0, v0, v5, s[0:1], 0, 0, 0, 0                        ; D2000000 00020B00
	V_CVT_PKRTZ_F16_F32_e32 v0, v6, v0                                      ; 5E000106
	EXP 15, 0, 1, 1, 1, v4, v0, v4, v0                                      ; F8001C0F 00040004
	S_ENDPGM                                                                ; BF810000

VERT
DCL IN[0]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[19]
DCL CONST[0..1]
DCL TEMP[0..2], LOCAL
IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
  0: MOV TEMP[0].zw, IMM[0].yyxy
  1: MOV TEMP[0].xy, IN[0].xyxx
  2: MAD TEMP[1].xy, IN[0].zwww, CONST[0].xyyy, CONST[0].zwww
  3: MAD TEMP[2].xy, IN[0].zwww, CONST[1].xyyy, CONST[1].zwww
  4: MOV TEMP[1].zw, TEMP[2].yyxy
  5: MOV OUT[1], TEMP[1]
  6: MOV OUT[0], TEMP[0]
  7: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0)
  %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4)
  %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8)
  %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12)
  %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16)
  %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20)
  %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24)
  %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28)
  %20 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %21, i32 0, i32 %6)
  %23 = extractelement <4 x float> %22, i32 0
  %24 = extractelement <4 x float> %22, i32 1
  %25 = extractelement <4 x float> %22, i32 2
  %26 = extractelement <4 x float> %22, i32 3
  %27 = fmul float %25, %12
  %28 = fadd float %27, %14
  %29 = fmul float %26, %13
  %30 = fadd float %29, %15
  %31 = fmul float %25, %16
  %32 = fadd float %31, %18
  %33 = fmul float %26, %17
  %34 = fadd float %33, %19
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %28, float %30, float %32, float %34)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %23, float %24, float 0.000000e+00, float 1.000000e+00)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg6

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%23](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%11](align=8)(tbaa=!"const")
	S_WAITCNT 112
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 7; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR4<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 5; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR3, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 6; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 4; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR2, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 3; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR3, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 0; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR8<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR2, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 32, 0, 0, 0, %VGPR7<kill>, %VGPR6<kill>, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>
	S_WAITCNT 1807
	%VGPR4<def> = V_MOV_B32_e32 1.000000e+00, %EXEC<imp-use>
	%VGPR5<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR1, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_LOAD_DWORDX4 s[4:7], s[6:7], 0               ; C0820700
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	BUFFER_LOAD_FORMAT_XYZW v[0:3], s[4:7][v0] + 0 ; E00C2000 80010000
	S_LOAD_DWORDX4 s[0:3], s[0:1], 0               ; C0800100
	S_WAITCNT vmcnt(0) lgkmcnt(0)                  ; BF8C0070
	S_BUFFER_LOAD_DWORD s4, s[0:3], 7              ; C2020107
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v4, s4                           ; 7E080204
	S_BUFFER_LOAD_DWORD s4, s[0:3], 5              ; C2020105
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v5, s4                           ; 7E0A0204
	V_MAD_F32 v4, v3, v5, v4, 0, 0, 0, 0           ; D2820004 04120B03
	S_BUFFER_LOAD_DWORD s4, s[0:3], 6              ; C2020106
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v5, s4                           ; 7E0A0204
	S_BUFFER_LOAD_DWORD s4, s[0:3], 4              ; C2020104
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v6, s4                           ; 7E0C0204
	V_MAD_F32 v5, v2, v6, v5, 0, 0, 0, 0           ; D2820005 04160D02
	S_BUFFER_LOAD_DWORD s4, s[0:3], 3              ; C2020103
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v6, s4                           ; 7E0C0204
	S_BUFFER_LOAD_DWORD s4, s[0:3], 1              ; C2020101
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v7, s4                           ; 7E0E0204
	V_MAD_F32 v6, v3, v7, v6, 0, 0, 0, 0           ; D2820006 041A0F03
	S_BUFFER_LOAD_DWORD s4, s[0:3], 2              ; C2020102
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v7, s4                           ; 7E0E0204
	S_BUFFER_LOAD_DWORD s0, s[0:3], 0              ; C2000100
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v8, s0                           ; 7E100200
	V_MAD_F32 v7, v2, v8, v7, 0, 0, 0, 0           ; D2820007 041E1102
	EXP 15, 32, 0, 0, 0, v7, v6, v5, v4            ; F800020F 04050607
	S_WAITCNT expcnt(0)                            ; BF8C070F
	V_MOV_B32_e32 v4, 1.000000e+00                 ; 7E0802F2
	V_MOV_B32_e32 v5, 0.000000e+00                 ; 7E0A0280
	EXP 15, 12, 0, 1, 0, v0, v1, v5, v4            ; F80008CF 04050100
	S_ENDPGM                                       ; BF810000

FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL SAMP[1]
DCL CONST[0..3]
DCL TEMP[0..5], LOCAL
IMM[0] FLT32 {    0.0286,    12.9898,    78.2330, 43758.5469}
IMM[1] FLT32 {    0.0000,     1.0000,     0.9500,     0.9025}
IMM[2] FLT32 {    0.8574,     0.8145,     0.7738,     0.7351}
IMM[3] FLT32 {    0.6983,     0.6634,     0.6302,     0.5987}
IMM[4] FLT32 {    0.5688,     0.5404,     0.5133,     0.4877}
IMM[5] FLT32 {    0.4633,     0.4401,     0.4181,     0.3972}
IMM[6] FLT32 {    0.3774,     0.3585,     0.3406,     0.3235}
IMM[7] FLT32 {    0.3074,     0.2920,     0.2774,     0.2635}
IMM[8] FLT32 {    0.2503,     0.2378,     0.2259,     0.2146}
IMM[9] FLT32 {    0.2039,     0.1937,     0.1840,     0.1748}
  0: MOV TEMP[0].xy, IN[0].xyxx
  1: ADD TEMP[1].xy, IN[0].xyyy, -CONST[0].xyyy
  2: MUL TEMP[2].x, IMM[0].xxxx, CONST[2].wwww
  3: MUL TEMP[1].xy, TEMP[1].xyyy, TEMP[2].xxxx
  4: DP2 TEMP[2].x, IN[0].xyyy, IMM[0].yzzz
  5: SIN TEMP[2].x, TEMP[2].xxxx
  6: MUL TEMP[2].x, TEMP[2].xxxx, IMM[0].wwww
  7: FRC TEMP[2].x, TEMP[2].xxxx
  8: MAD TEMP[2].x, TEMP[2].xxxx, CONST[1].xxxx, CONST[1].yyyy
  9: MUL TEMP[1].xy, TEMP[1].xyyy, TEMP[2].xxxx
 10: MUL TEMP[2].xy, IN[0].xyyy, CONST[1].zwww
 11: MOV TEMP[0].zw, TEMP[2].yyxy
 12: MUL TEMP[2].xy, TEMP[1].xyyy, CONST[1].zwww
 13: MOV TEMP[1].zw, TEMP[2].yyxy
 14: MOV TEMP[2].w, IMM[1].xxxx
 15: ADD TEMP[0], TEMP[0], -TEMP[1]
 16: MOV TEMP[3].xy, TEMP[0].xyyy
 17: TEX TEMP[3].xyz, TEMP[3], SAMP[0], 2D
 18: MOV TEMP[4].xy, TEMP[0].zwww
 19: TEX TEMP[4].x, TEMP[4], SAMP[1], 2D
 20: ABS TEMP[4].x, TEMP[4].xxxx
 21: FSGE TEMP[4].x, TEMP[4].xxxx, CONST[0].zzzz
 22: AND TEMP[4].x, TEMP[4].xxxx, IMM[1].yyyy
 23: MUL TEMP[3].xyz, TEMP[3].xyzz, TEMP[4].xxxx
 24: MOV TEMP[2].xyz, TEMP[3].xyzx
 25: ADD TEMP[0], TEMP[0], -TEMP[1]
 26: MOV TEMP[4].xy, TEMP[0].xyyy
 27: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
 28: MOV TEMP[5].xy, TEMP[0].zwww
 29: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
 30: ABS TEMP[5].x, TEMP[5].xxxx
 31: FSGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
 32: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
 33: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
 34: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[1].zzzz
 35: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
 36: ADD TEMP[0], TEMP[0], -TEMP[1]
 37: MOV TEMP[4].xy, TEMP[0].xyyy
 38: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
 39: MOV TEMP[5].xy, TEMP[0].zwww
 40: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
 41: ABS TEMP[5].x, TEMP[5].xxxx
 42: FSGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
 43: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
 44: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
 45: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[1].wwww
 46: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
 47: ADD TEMP[0], TEMP[0], -TEMP[1]
 48: MOV TEMP[4].xy, TEMP[0].xyyy
 49: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
 50: MOV TEMP[5].xy, TEMP[0].zwww
 51: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
 52: ABS TEMP[5].x, TEMP[5].xxxx
 53: FSGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
 54: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
 55: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
 56: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[2].xxxx
 57: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
 58: ADD TEMP[0], TEMP[0], -TEMP[1]
 59: MOV TEMP[4].xy, TEMP[0].xyyy
 60: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
 61: MOV TEMP[5].xy, TEMP[0].zwww
 62: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
 63: ABS TEMP[5].x, TEMP[5].xxxx
 64: FSGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
 65: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
 66: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
 67: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[2].yyyy
 68: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
 69: ADD TEMP[0], TEMP[0], -TEMP[1]
 70: MOV TEMP[4].xy, TEMP[0].xyyy
 71: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
 72: MOV TEMP[5].xy, TEMP[0].zwww
 73: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
 74: ABS TEMP[5].x, TEMP[5].xxxx
 75: FSGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
 76: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
 77: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
 78: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[2].zzzz
 79: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
 80: ADD TEMP[0], TEMP[0], -TEMP[1]
 81: MOV TEMP[4].xy, TEMP[0].xyyy
 82: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
 83: MOV TEMP[5].xy, TEMP[0].zwww
 84: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
 85: ABS TEMP[5].x, TEMP[5].xxxx
 86: FSGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
 87: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
 88: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
 89: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[2].wwww
 90: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
 91: ADD TEMP[0], TEMP[0], -TEMP[1]
 92: MOV TEMP[4].xy, TEMP[0].xyyy
 93: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
 94: MOV TEMP[5].xy, TEMP[0].zwww
 95: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
 96: ABS TEMP[5].x, TEMP[5].xxxx
 97: FSGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
 98: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
 99: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
100: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[3].xxxx
101: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
102: ADD TEMP[0], TEMP[0], -TEMP[1]
103: MOV TEMP[4].xy, TEMP[0].xyyy
104: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
105: MOV TEMP[5].xy, TEMP[0].zwww
106: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
107: ABS TEMP[5].x, TEMP[5].xxxx
108: FSGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
109: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
110: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
111: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[3].yyyy
112: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
113: ADD TEMP[0], TEMP[0], -TEMP[1]
114: MOV TEMP[4].xy, TEMP[0].xyyy
115: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
116: MOV TEMP[5].xy, TEMP[0].zwww
117: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
118: ABS TEMP[5].x, TEMP[5].xxxx
119: FSGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
120: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
121: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
122: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[3].zzzz
123: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
124: ADD TEMP[0], TEMP[0], -TEMP[1]
125: MOV TEMP[4].xy, TEMP[0].xyyy
126: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
127: MOV TEMP[5].xy, TEMP[0].zwww
128: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
129: ABS TEMP[5].x, TEMP[5].xxxx
130: FSGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
131: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
132: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
133: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[3].wwww
134: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
135: ADD TEMP[0], TEMP[0], -TEMP[1]
136: MOV TEMP[4].xy, TEMP[0].xyyy
137: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
138: MOV TEMP[5].xy, TEMP[0].zwww
139: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
140: ABS TEMP[5].x, TEMP[5].xxxx
141: FSGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
142: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
143: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
144: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[4].xxxx
145: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
146: ADD TEMP[0], TEMP[0], -TEMP[1]
147: MOV TEMP[4].xy, TEMP[0].xyyy
148: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
149: MOV TEMP[5].xy, TEMP[0].zwww
150: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
151: ABS TEMP[5].x, TEMP[5].xxxx
152: FSGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
153: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
154: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
155: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[4].yyyy
156: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
157: ADD TEMP[0], TEMP[0], -TEMP[1]
158: MOV TEMP[4].xy, TEMP[0].xyyy
159: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
160: MOV TEMP[5].xy, TEMP[0].zwww
161: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
162: ABS TEMP[5].x, TEMP[5].xxxx
163: FSGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
164: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
165: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
166: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[4].zzzz
167: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
168: ADD TEMP[0], TEMP[0], -TEMP[1]
169: MOV TEMP[4].xy, TEMP[0].xyyy
170: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
171: MOV TEMP[5].xy, TEMP[0].zwww
172: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
173: ABS TEMP[5].x, TEMP[5].xxxx
174: FSGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
175: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
176: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
177: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[4].wwww
178: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
179: ADD TEMP[0], TEMP[0], -TEMP[1]
180: MOV TEMP[4].xy, TEMP[0].xyyy
181: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
182: MOV TEMP[5].xy, TEMP[0].zwww
183: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
184: ABS TEMP[5].x, TEMP[5].xxxx
185: FSGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
186: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
187: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
188: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[5].xxxx
189: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
190: ADD TEMP[0], TEMP[0], -TEMP[1]
191: MOV TEMP[4].xy, TEMP[0].xyyy
192: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
193: MOV TEMP[5].xy, TEMP[0].zwww
194: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
195: ABS TEMP[5].x, TEMP[5].xxxx
196: FSGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
197: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
198: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
199: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[5].yyyy
200: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
201: ADD TEMP[0], TEMP[0], -TEMP[1]
202: MOV TEMP[4].xy, TEMP[0].xyyy
203: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
204: MOV TEMP[5].xy, TEMP[0].zwww
205: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
206: ABS TEMP[5].x, TEMP[5].xxxx
207: FSGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
208: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
209: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
210: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[5].zzzz
211: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
212: ADD TEMP[0], TEMP[0], -TEMP[1]
213: MOV TEMP[4].xy, TEMP[0].xyyy
214: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
215: MOV TEMP[5].xy, TEMP[0].zwww
216: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
217: ABS TEMP[5].x, TEMP[5].xxxx
218: FSGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
219: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
220: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
221: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[5].wwww
222: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
223: ADD TEMP[0], TEMP[0], -TEMP[1]
224: MOV TEMP[4].xy, TEMP[0].xyyy
225: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
226: MOV TEMP[5].xy, TEMP[0].zwww
227: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
228: ABS TEMP[5].x, TEMP[5].xxxx
229: FSGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
230: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
231: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
232: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[6].xxxx
233: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
234: ADD TEMP[0], TEMP[0], -TEMP[1]
235: MOV TEMP[4].xy, TEMP[0].xyyy
236: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
237: MOV TEMP[5].xy, TEMP[0].zwww
238: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
239: ABS TEMP[5].x, TEMP[5].xxxx
240: FSGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
241: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
242: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
243: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[6].yyyy
244: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
245: ADD TEMP[0], TEMP[0], -TEMP[1]
246: MOV TEMP[4].xy, TEMP[0].xyyy
247: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
248: MOV TEMP[5].xy, TEMP[0].zwww
249: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
250: ABS TEMP[5].x, TEMP[5].xxxx
251: FSGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
252: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
253: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
254: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[6].zzzz
255: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
256: ADD TEMP[0], TEMP[0], -TEMP[1]
257: MOV TEMP[4].xy, TEMP[0].xyyy
258: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
259: MOV TEMP[5].xy, TEMP[0].zwww
260: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
261: ABS TEMP[5].x, TEMP[5].xxxx
262: FSGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
263: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
264: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
265: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[6].wwww
266: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
267: ADD TEMP[0], TEMP[0], -TEMP[1]
268: MOV TEMP[4].xy, TEMP[0].xyyy
269: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
270: MOV TEMP[5].xy, TEMP[0].zwww
271: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
272: ABS TEMP[5].x, TEMP[5].xxxx
273: FSGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
274: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
275: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
276: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[7].xxxx
277: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
278: ADD TEMP[0], TEMP[0], -TEMP[1]
279: MOV TEMP[4].xy, TEMP[0].xyyy
280: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
281: MOV TEMP[5].xy, TEMP[0].zwww
282: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
283: ABS TEMP[5].x, TEMP[5].xxxx
284: FSGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
285: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
286: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
287: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[7].yyyy
288: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
289: ADD TEMP[0], TEMP[0], -TEMP[1]
290: MOV TEMP[4].xy, TEMP[0].xyyy
291: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
292: MOV TEMP[5].xy, TEMP[0].zwww
293: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
294: ABS TEMP[5].x, TEMP[5].xxxx
295: FSGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
296: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
297: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
298: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[7].zzzz
299: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
300: ADD TEMP[0], TEMP[0], -TEMP[1]
301: MOV TEMP[4].xy, TEMP[0].xyyy
302: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
303: MOV TEMP[5].xy, TEMP[0].zwww
304: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
305: ABS TEMP[5].x, TEMP[5].xxxx
306: FSGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
307: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
308: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
309: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[7].wwww
310: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
311: ADD TEMP[0], TEMP[0], -TEMP[1]
312: MOV TEMP[4].xy, TEMP[0].xyyy
313: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
314: MOV TEMP[5].xy, TEMP[0].zwww
315: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
316: ABS TEMP[5].x, TEMP[5].xxxx
317: FSGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
318: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
319: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
320: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[8].xxxx
321: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
322: ADD TEMP[0], TEMP[0], -TEMP[1]
323: MOV TEMP[4].xy, TEMP[0].xyyy
324: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
325: MOV TEMP[5].xy, TEMP[0].zwww
326: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
327: ABS TEMP[5].x, TEMP[5].xxxx
328: FSGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
329: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
330: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
331: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[8].yyyy
332: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
333: ADD TEMP[0], TEMP[0], -TEMP[1]
334: MOV TEMP[4].xy, TEMP[0].xyyy
335: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
336: MOV TEMP[5].xy, TEMP[0].zwww
337: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
338: ABS TEMP[5].x, TEMP[5].xxxx
339: FSGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
340: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
341: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
342: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[8].zzzz
343: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
344: ADD TEMP[0], TEMP[0], -TEMP[1]
345: MOV TEMP[4].xy, TEMP[0].xyyy
346: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
347: MOV TEMP[5].xy, TEMP[0].zwww
348: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
349: ABS TEMP[5].x, TEMP[5].xxxx
350: FSGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
351: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
352: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
353: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[8].wwww
354: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
355: ADD TEMP[0], TEMP[0], -TEMP[1]
356: MOV TEMP[4].xy, TEMP[0].xyyy
357: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
358: MOV TEMP[5].xy, TEMP[0].zwww
359: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
360: ABS TEMP[5].x, TEMP[5].xxxx
361: FSGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
362: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
363: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
364: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[9].xxxx
365: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
366: ADD TEMP[0], TEMP[0], -TEMP[1]
367: MOV TEMP[4].xy, TEMP[0].xyyy
368: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
369: MOV TEMP[5].xy, TEMP[0].zwww
370: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
371: ABS TEMP[5].x, TEMP[5].xxxx
372: FSGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
373: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
374: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
375: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[9].yyyy
376: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
377: ADD TEMP[0], TEMP[0], -TEMP[1]
378: MOV TEMP[4].xy, TEMP[0].xyyy
379: TEX TEMP[4].xyz, TEMP[4], SAMP[0], 2D
380: MOV TEMP[5].xy, TEMP[0].zwww
381: TEX TEMP[5].x, TEMP[5], SAMP[1], 2D
382: ABS TEMP[5].x, TEMP[5].xxxx
383: FSGE TEMP[5].x, TEMP[5].xxxx, CONST[0].zzzz
384: AND TEMP[5].x, TEMP[5].xxxx, IMM[1].yyyy
385: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[5].xxxx
386: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[9].zzzz
387: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
388: ADD TEMP[0], TEMP[0], -TEMP[1]
389: MOV TEMP[1].xy, TEMP[0].xyyy
390: TEX TEMP[1].xyz, TEMP[1], SAMP[0], 2D
391: MOV TEMP[0].xy, TEMP[0].zwww
392: TEX TEMP[0].x, TEMP[0], SAMP[1], 2D
393: ABS TEMP[0].x, TEMP[0].xxxx
394: FSGE TEMP[0].x, TEMP[0].xxxx, CONST[0].zzzz
395: AND TEMP[0].x, TEMP[0].xxxx, IMM[1].yyyy
396: MUL TEMP[3].xyz, TEMP[1].xyzz, TEMP[0].xxxx
397: MUL TEMP[3].xyz, TEMP[3].xyzz, IMM[9].wwww
398: ADD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz
399: MUL TEMP[2].xyz, TEMP[2].xyzz, CONST[2].xyzz
400: MOV OUT[0], TEMP[2]
401: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %21 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
  %22 = load <16 x i8> addrspace(2)* %21, !tbaa !0
  %23 = call float @llvm.SI.load.const(<16 x i8> %22, i32 0)
  %24 = call float @llvm.SI.load.const(<16 x i8> %22, i32 4)
  %25 = call float @llvm.SI.load.const(<16 x i8> %22, i32 8)
  %26 = call float @llvm.SI.load.const(<16 x i8> %22, i32 16)
  %27 = call float @llvm.SI.load.const(<16 x i8> %22, i32 20)
  %28 = call float @llvm.SI.load.const(<16 x i8> %22, i32 24)
  %29 = call float @llvm.SI.load.const(<16 x i8> %22, i32 28)
  %30 = call float @llvm.SI.load.const(<16 x i8> %22, i32 32)
  %31 = call float @llvm.SI.load.const(<16 x i8> %22, i32 36)
  %32 = call float @llvm.SI.load.const(<16 x i8> %22, i32 40)
  %33 = call float @llvm.SI.load.const(<16 x i8> %22, i32 44)
  %34 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0
  %35 = load <32 x i8> addrspace(2)* %34, !tbaa !0
  %36 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0
  %37 = load <16 x i8> addrspace(2)* %36, !tbaa !0
  %38 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 1
  %39 = load <32 x i8> addrspace(2)* %38, !tbaa !0
  %40 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 1
  %41 = load <16 x i8> addrspace(2)* %40, !tbaa !0
  %42 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %4, <2 x i32> %6)
  %43 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %4, <2 x i32> %6)
  %44 = fsub float -0.000000e+00, %23
  %45 = fadd float %42, %44
  %46 = fsub float -0.000000e+00, %24
  %47 = fadd float %43, %46
  %48 = fmul float 0x3F9D41D420000000, %33
  %49 = fmul float %45, %48
  %50 = fmul float %47, %48
  %51 = fmul float %42, 0x4029FAC720000000
  %52 = fmul float %43, 0x40538EE980000000
  %53 = fadd float %51, %52
  %54 = call float @llvm.sin.f32(float %53)
  %55 = fmul float %54, 0x40E55DD180000000
  %56 = call float @llvm.AMDIL.fraction.(float %55)
  %57 = fmul float %56, %26
  %58 = fadd float %57, %27
  %59 = fmul float %49, %58
  %60 = fmul float %50, %58
  %61 = fmul float %42, %28
  %62 = fmul float %43, %29
  %63 = fmul float %59, %28
  %64 = fmul float %60, %29
  %65 = fsub float -0.000000e+00, %59
  %66 = fadd float %42, %65
  %67 = fsub float -0.000000e+00, %60
  %68 = fadd float %43, %67
  %69 = fsub float -0.000000e+00, %63
  %70 = fadd float %61, %69
  %71 = fsub float -0.000000e+00, %64
  %72 = fadd float %62, %71
  %73 = bitcast float %66 to i32
  %74 = bitcast float %68 to i32
  %75 = insertelement <2 x i32> undef, i32 %73, i32 0
  %76 = insertelement <2 x i32> %75, i32 %74, i32 1
  %77 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %76, <32 x i8> %35, <16 x i8> %37, i32 2)
  %78 = extractelement <4 x float> %77, i32 0
  %79 = extractelement <4 x float> %77, i32 1
  %80 = extractelement <4 x float> %77, i32 2
  %81 = bitcast float %70 to i32
  %82 = bitcast float %72 to i32
  %83 = insertelement <2 x i32> undef, i32 %81, i32 0
  %84 = insertelement <2 x i32> %83, i32 %82, i32 1
  %85 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %84, <32 x i8> %39, <16 x i8> %41, i32 2)
  %86 = extractelement <4 x float> %85, i32 0
  %87 = call float @fabs(float %86)
  %88 = fcmp oge float %87, %25
  %89 = sext i1 %88 to i32
  %90 = bitcast i32 %89 to float
  %91 = bitcast float %90 to i32
  %92 = and i32 %91, 1065353216
  %93 = bitcast i32 %92 to float
  %94 = fmul float %78, %93
  %95 = fmul float %79, %93
  %96 = fmul float %80, %93
  %97 = fsub float -0.000000e+00, %59
  %98 = fadd float %66, %97
  %99 = fsub float -0.000000e+00, %60
  %100 = fadd float %68, %99
  %101 = fsub float -0.000000e+00, %63
  %102 = fadd float %70, %101
  %103 = fsub float -0.000000e+00, %64
  %104 = fadd float %72, %103
  %105 = bitcast float %98 to i32
  %106 = bitcast float %100 to i32
  %107 = insertelement <2 x i32> undef, i32 %105, i32 0
  %108 = insertelement <2 x i32> %107, i32 %106, i32 1
  %109 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %108, <32 x i8> %35, <16 x i8> %37, i32 2)
  %110 = extractelement <4 x float> %109, i32 0
  %111 = extractelement <4 x float> %109, i32 1
  %112 = extractelement <4 x float> %109, i32 2
  %113 = bitcast float %102 to i32
  %114 = bitcast float %104 to i32
  %115 = insertelement <2 x i32> undef, i32 %113, i32 0
  %116 = insertelement <2 x i32> %115, i32 %114, i32 1
  %117 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %116, <32 x i8> %39, <16 x i8> %41, i32 2)
  %118 = extractelement <4 x float> %117, i32 0
  %119 = call float @fabs(float %118)
  %120 = fcmp oge float %119, %25
  %121 = sext i1 %120 to i32
  %122 = bitcast i32 %121 to float
  %123 = bitcast float %122 to i32
  %124 = and i32 %123, 1065353216
  %125 = bitcast i32 %124 to float
  %126 = fmul float %110, %125
  %127 = fmul float %111, %125
  %128 = fmul float %112, %125
  %129 = fmul float %126, 0x3FEE666660000000
  %130 = fmul float %127, 0x3FEE666660000000
  %131 = fmul float %128, 0x3FEE666660000000
  %132 = fadd float %94, %129
  %133 = fadd float %95, %130
  %134 = fadd float %96, %131
  %135 = fsub float -0.000000e+00, %59
  %136 = fadd float %98, %135
  %137 = fsub float -0.000000e+00, %60
  %138 = fadd float %100, %137
  %139 = fsub float -0.000000e+00, %63
  %140 = fadd float %102, %139
  %141 = fsub float -0.000000e+00, %64
  %142 = fadd float %104, %141
  %143 = bitcast float %136 to i32
  %144 = bitcast float %138 to i32
  %145 = insertelement <2 x i32> undef, i32 %143, i32 0
  %146 = insertelement <2 x i32> %145, i32 %144, i32 1
  %147 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %146, <32 x i8> %35, <16 x i8> %37, i32 2)
  %148 = extractelement <4 x float> %147, i32 0
  %149 = extractelement <4 x float> %147, i32 1
  %150 = extractelement <4 x float> %147, i32 2
  %151 = bitcast float %140 to i32
  %152 = bitcast float %142 to i32
  %153 = insertelement <2 x i32> undef, i32 %151, i32 0
  %154 = insertelement <2 x i32> %153, i32 %152, i32 1
  %155 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %154, <32 x i8> %39, <16 x i8> %41, i32 2)
  %156 = extractelement <4 x float> %155, i32 0
  %157 = call float @fabs(float %156)
  %158 = fcmp oge float %157, %25
  %159 = sext i1 %158 to i32
  %160 = bitcast i32 %159 to float
  %161 = bitcast float %160 to i32
  %162 = and i32 %161, 1065353216
  %163 = bitcast i32 %162 to float
  %164 = fmul float %148, %163
  %165 = fmul float %149, %163
  %166 = fmul float %150, %163
  %167 = fmul float %164, 0x3FECE147A0000000
  %168 = fmul float %165, 0x3FECE147A0000000
  %169 = fmul float %166, 0x3FECE147A0000000
  %170 = fadd float %132, %167
  %171 = fadd float %133, %168
  %172 = fadd float %134, %169
  %173 = fsub float -0.000000e+00, %59
  %174 = fadd float %136, %173
  %175 = fsub float -0.000000e+00, %60
  %176 = fadd float %138, %175
  %177 = fsub float -0.000000e+00, %63
  %178 = fadd float %140, %177
  %179 = fsub float -0.000000e+00, %64
  %180 = fadd float %142, %179
  %181 = bitcast float %174 to i32
  %182 = bitcast float %176 to i32
  %183 = insertelement <2 x i32> undef, i32 %181, i32 0
  %184 = insertelement <2 x i32> %183, i32 %182, i32 1
  %185 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %184, <32 x i8> %35, <16 x i8> %37, i32 2)
  %186 = extractelement <4 x float> %185, i32 0
  %187 = extractelement <4 x float> %185, i32 1
  %188 = extractelement <4 x float> %185, i32 2
  %189 = bitcast float %178 to i32
  %190 = bitcast float %180 to i32
  %191 = insertelement <2 x i32> undef, i32 %189, i32 0
  %192 = insertelement <2 x i32> %191, i32 %190, i32 1
  %193 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %192, <32 x i8> %39, <16 x i8> %41, i32 2)
  %194 = extractelement <4 x float> %193, i32 0
  %195 = call float @fabs(float %194)
  %196 = fcmp oge float %195, %25
  %197 = sext i1 %196 to i32
  %198 = bitcast i32 %197 to float
  %199 = bitcast float %198 to i32
  %200 = and i32 %199, 1065353216
  %201 = bitcast i32 %200 to float
  %202 = fmul float %186, %201
  %203 = fmul float %187, %201
  %204 = fmul float %188, %201
  %205 = fmul float %202, 0x3FEB6F9DA0000000
  %206 = fmul float %203, 0x3FEB6F9DA0000000
  %207 = fmul float %204, 0x3FEB6F9DA0000000
  %208 = fadd float %170, %205
  %209 = fadd float %171, %206
  %210 = fadd float %172, %207
  %211 = fsub float -0.000000e+00, %59
  %212 = fadd float %174, %211
  %213 = fsub float -0.000000e+00, %60
  %214 = fadd float %176, %213
  %215 = fsub float -0.000000e+00, %63
  %216 = fadd float %178, %215
  %217 = fsub float -0.000000e+00, %64
  %218 = fadd float %180, %217
  %219 = bitcast float %212 to i32
  %220 = bitcast float %214 to i32
  %221 = insertelement <2 x i32> undef, i32 %219, i32 0
  %222 = insertelement <2 x i32> %221, i32 %220, i32 1
  %223 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %222, <32 x i8> %35, <16 x i8> %37, i32 2)
  %224 = extractelement <4 x float> %223, i32 0
  %225 = extractelement <4 x float> %223, i32 1
  %226 = extractelement <4 x float> %223, i32 2
  %227 = bitcast float %216 to i32
  %228 = bitcast float %218 to i32
  %229 = insertelement <2 x i32> undef, i32 %227, i32 0
  %230 = insertelement <2 x i32> %229, i32 %228, i32 1
  %231 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %230, <32 x i8> %39, <16 x i8> %41, i32 2)
  %232 = extractelement <4 x float> %231, i32 0
  %233 = call float @fabs(float %232)
  %234 = fcmp oge float %233, %25
  %235 = sext i1 %234 to i32
  %236 = bitcast i32 %235 to float
  %237 = bitcast float %236 to i32
  %238 = and i32 %237, 1065353216
  %239 = bitcast i32 %238 to float
  %240 = fmul float %224, %239
  %241 = fmul float %225, %239
  %242 = fmul float %226, %239
  %243 = fmul float %240, 0x3FEA106F60000000
  %244 = fmul float %241, 0x3FEA106F60000000
  %245 = fmul float %242, 0x3FEA106F60000000
  %246 = fadd float %208, %243
  %247 = fadd float %209, %244
  %248 = fadd float %210, %245
  %249 = fsub float -0.000000e+00, %59
  %250 = fadd float %212, %249
  %251 = fsub float -0.000000e+00, %60
  %252 = fadd float %214, %251
  %253 = fsub float -0.000000e+00, %63
  %254 = fadd float %216, %253
  %255 = fsub float -0.000000e+00, %64
  %256 = fadd float %218, %255
  %257 = bitcast float %250 to i32
  %258 = bitcast float %252 to i32
  %259 = insertelement <2 x i32> undef, i32 %257, i32 0
  %260 = insertelement <2 x i32> %259, i32 %258, i32 1
  %261 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %260, <32 x i8> %35, <16 x i8> %37, i32 2)
  %262 = extractelement <4 x float> %261, i32 0
  %263 = extractelement <4 x float> %261, i32 1
  %264 = extractelement <4 x float> %261, i32 2
  %265 = bitcast float %254 to i32
  %266 = bitcast float %256 to i32
  %267 = insertelement <2 x i32> undef, i32 %265, i32 0
  %268 = insertelement <2 x i32> %267, i32 %266, i32 1
  %269 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %268, <32 x i8> %39, <16 x i8> %41, i32 2)
  %270 = extractelement <4 x float> %269, i32 0
  %271 = call float @fabs(float %270)
  %272 = fcmp oge float %271, %25
  %273 = sext i1 %272 to i32
  %274 = bitcast i32 %273 to float
  %275 = bitcast float %274 to i32
  %276 = and i32 %275, 1065353216
  %277 = bitcast i32 %276 to float
  %278 = fmul float %262, %277
  %279 = fmul float %263, %277
  %280 = fmul float %264, %277
  %281 = fmul float %278, 0x3FE8C2D020000000
  %282 = fmul float %279, 0x3FE8C2D020000000
  %283 = fmul float %280, 0x3FE8C2D020000000
  %284 = fadd float %246, %281
  %285 = fadd float %247, %282
  %286 = fadd float %248, %283
  %287 = fsub float -0.000000e+00, %59
  %288 = fadd float %250, %287
  %289 = fsub float -0.000000e+00, %60
  %290 = fadd float %252, %289
  %291 = fsub float -0.000000e+00, %63
  %292 = fadd float %254, %291
  %293 = fsub float -0.000000e+00, %64
  %294 = fadd float %256, %293
  %295 = bitcast float %288 to i32
  %296 = bitcast float %290 to i32
  %297 = insertelement <2 x i32> undef, i32 %295, i32 0
  %298 = insertelement <2 x i32> %297, i32 %296, i32 1
  %299 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %298, <32 x i8> %35, <16 x i8> %37, i32 2)
  %300 = extractelement <4 x float> %299, i32 0
  %301 = extractelement <4 x float> %299, i32 1
  %302 = extractelement <4 x float> %299, i32 2
  %303 = bitcast float %292 to i32
  %304 = bitcast float %294 to i32
  %305 = insertelement <2 x i32> undef, i32 %303, i32 0
  %306 = insertelement <2 x i32> %305, i32 %304, i32 1
  %307 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %306, <32 x i8> %39, <16 x i8> %41, i32 2)
  %308 = extractelement <4 x float> %307, i32 0
  %309 = call float @fabs(float %308)
  %310 = fcmp oge float %309, %25
  %311 = sext i1 %310 to i32
  %312 = bitcast i32 %311 to float
  %313 = bitcast float %312 to i32
  %314 = and i32 %313, 1065353216
  %315 = bitcast i32 %314 to float
  %316 = fmul float %300, %315
  %317 = fmul float %301, %315
  %318 = fmul float %302, %315
  %319 = fmul float %316, 0x3FE785DF40000000
  %320 = fmul float %317, 0x3FE785DF40000000
  %321 = fmul float %318, 0x3FE785DF40000000
  %322 = fadd float %284, %319
  %323 = fadd float %285, %320
  %324 = fadd float %286, %321
  %325 = fsub float -0.000000e+00, %59
  %326 = fadd float %288, %325
  %327 = fsub float -0.000000e+00, %60
  %328 = fadd float %290, %327
  %329 = fsub float -0.000000e+00, %63
  %330 = fadd float %292, %329
  %331 = fsub float -0.000000e+00, %64
  %332 = fadd float %294, %331
  %333 = bitcast float %326 to i32
  %334 = bitcast float %328 to i32
  %335 = insertelement <2 x i32> undef, i32 %333, i32 0
  %336 = insertelement <2 x i32> %335, i32 %334, i32 1
  %337 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %336, <32 x i8> %35, <16 x i8> %37, i32 2)
  %338 = extractelement <4 x float> %337, i32 0
  %339 = extractelement <4 x float> %337, i32 1
  %340 = extractelement <4 x float> %337, i32 2
  %341 = bitcast float %330 to i32
  %342 = bitcast float %332 to i32
  %343 = insertelement <2 x i32> undef, i32 %341, i32 0
  %344 = insertelement <2 x i32> %343, i32 %342, i32 1
  %345 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %344, <32 x i8> %39, <16 x i8> %41, i32 2)
  %346 = extractelement <4 x float> %345, i32 0
  %347 = call float @fabs(float %346)
  %348 = fcmp oge float %347, %25
  %349 = sext i1 %348 to i32
  %350 = bitcast i32 %349 to float
  %351 = bitcast float %350 to i32
  %352 = and i32 %351, 1065353216
  %353 = bitcast i32 %352 to float
  %354 = fmul float %338, %353
  %355 = fmul float %339, %353
  %356 = fmul float %340, %353
  %357 = fmul float %354, 0x3FE658C740000000
  %358 = fmul float %355, 0x3FE658C740000000
  %359 = fmul float %356, 0x3FE658C740000000
  %360 = fadd float %322, %357
  %361 = fadd float %323, %358
  %362 = fadd float %324, %359
  %363 = fsub float -0.000000e+00, %59
  %364 = fadd float %326, %363
  %365 = fsub float -0.000000e+00, %60
  %366 = fadd float %328, %365
  %367 = fsub float -0.000000e+00, %63
  %368 = fadd float %330, %367
  %369 = fsub float -0.000000e+00, %64
  %370 = fadd float %332, %369
  %371 = bitcast float %364 to i32
  %372 = bitcast float %366 to i32
  %373 = insertelement <2 x i32> undef, i32 %371, i32 0
  %374 = insertelement <2 x i32> %373, i32 %372, i32 1
  %375 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %374, <32 x i8> %35, <16 x i8> %37, i32 2)
  %376 = extractelement <4 x float> %375, i32 0
  %377 = extractelement <4 x float> %375, i32 1
  %378 = extractelement <4 x float> %375, i32 2
  %379 = bitcast float %368 to i32
  %380 = bitcast float %370 to i32
  %381 = insertelement <2 x i32> undef, i32 %379, i32 0
  %382 = insertelement <2 x i32> %381, i32 %380, i32 1
  %383 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %382, <32 x i8> %39, <16 x i8> %41, i32 2)
  %384 = extractelement <4 x float> %383, i32 0
  %385 = call float @fabs(float %384)
  %386 = fcmp oge float %385, %25
  %387 = sext i1 %386 to i32
  %388 = bitcast i32 %387 to float
  %389 = bitcast float %388 to i32
  %390 = and i32 %389, 1065353216
  %391 = bitcast i32 %390 to float
  %392 = fmul float %376, %391
  %393 = fmul float %377, %391
  %394 = fmul float %378, %391
  %395 = fmul float %392, 0x3FE53ABD40000000
  %396 = fmul float %393, 0x3FE53ABD40000000
  %397 = fmul float %394, 0x3FE53ABD40000000
  %398 = fadd float %360, %395
  %399 = fadd float %361, %396
  %400 = fadd float %362, %397
  %401 = fsub float -0.000000e+00, %59
  %402 = fadd float %364, %401
  %403 = fsub float -0.000000e+00, %60
  %404 = fadd float %366, %403
  %405 = fsub float -0.000000e+00, %63
  %406 = fadd float %368, %405
  %407 = fsub float -0.000000e+00, %64
  %408 = fadd float %370, %407
  %409 = bitcast float %402 to i32
  %410 = bitcast float %404 to i32
  %411 = insertelement <2 x i32> undef, i32 %409, i32 0
  %412 = insertelement <2 x i32> %411, i32 %410, i32 1
  %413 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %412, <32 x i8> %35, <16 x i8> %37, i32 2)
  %414 = extractelement <4 x float> %413, i32 0
  %415 = extractelement <4 x float> %413, i32 1
  %416 = extractelement <4 x float> %413, i32 2
  %417 = bitcast float %406 to i32
  %418 = bitcast float %408 to i32
  %419 = insertelement <2 x i32> undef, i32 %417, i32 0
  %420 = insertelement <2 x i32> %419, i32 %418, i32 1
  %421 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %420, <32 x i8> %39, <16 x i8> %41, i32 2)
  %422 = extractelement <4 x float> %421, i32 0
  %423 = call float @fabs(float %422)
  %424 = fcmp oge float %423, %25
  %425 = sext i1 %424 to i32
  %426 = bitcast i32 %425 to float
  %427 = bitcast float %426 to i32
  %428 = and i32 %427, 1065353216
  %429 = bitcast i32 %428 to float
  %430 = fmul float %414, %429
  %431 = fmul float %415, %429
  %432 = fmul float %416, %429
  %433 = fmul float %430, 0x3FE42B00A0000000
  %434 = fmul float %431, 0x3FE42B00A0000000
  %435 = fmul float %432, 0x3FE42B00A0000000
  %436 = fadd float %398, %433
  %437 = fadd float %399, %434
  %438 = fadd float %400, %435
  %439 = fsub float -0.000000e+00, %59
  %440 = fadd float %402, %439
  %441 = fsub float -0.000000e+00, %60
  %442 = fadd float %404, %441
  %443 = fsub float -0.000000e+00, %63
  %444 = fadd float %406, %443
  %445 = fsub float -0.000000e+00, %64
  %446 = fadd float %408, %445
  %447 = bitcast float %440 to i32
  %448 = bitcast float %442 to i32
  %449 = insertelement <2 x i32> undef, i32 %447, i32 0
  %450 = insertelement <2 x i32> %449, i32 %448, i32 1
  %451 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %450, <32 x i8> %35, <16 x i8> %37, i32 2)
  %452 = extractelement <4 x float> %451, i32 0
  %453 = extractelement <4 x float> %451, i32 1
  %454 = extractelement <4 x float> %451, i32 2
  %455 = bitcast float %444 to i32
  %456 = bitcast float %446 to i32
  %457 = insertelement <2 x i32> undef, i32 %455, i32 0
  %458 = insertelement <2 x i32> %457, i32 %456, i32 1
  %459 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %458, <32 x i8> %39, <16 x i8> %41, i32 2)
  %460 = extractelement <4 x float> %459, i32 0
  %461 = call float @fabs(float %460)
  %462 = fcmp oge float %461, %25
  %463 = sext i1 %462 to i32
  %464 = bitcast i32 %463 to float
  %465 = bitcast float %464 to i32
  %466 = and i32 %465, 1065353216
  %467 = bitcast i32 %466 to float
  %468 = fmul float %452, %467
  %469 = fmul float %453, %467
  %470 = fmul float %454, %467
  %471 = fmul float %468, 0x3FE328DA20000000
  %472 = fmul float %469, 0x3FE328DA20000000
  %473 = fmul float %470, 0x3FE328DA20000000
  %474 = fadd float %436, %471
  %475 = fadd float %437, %472
  %476 = fadd float %438, %473
  %477 = fsub float -0.000000e+00, %59
  %478 = fadd float %440, %477
  %479 = fsub float -0.000000e+00, %60
  %480 = fadd float %442, %479
  %481 = fsub float -0.000000e+00, %63
  %482 = fadd float %444, %481
  %483 = fsub float -0.000000e+00, %64
  %484 = fadd float %446, %483
  %485 = bitcast float %478 to i32
  %486 = bitcast float %480 to i32
  %487 = insertelement <2 x i32> undef, i32 %485, i32 0
  %488 = insertelement <2 x i32> %487, i32 %486, i32 1
  %489 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %488, <32 x i8> %35, <16 x i8> %37, i32 2)
  %490 = extractelement <4 x float> %489, i32 0
  %491 = extractelement <4 x float> %489, i32 1
  %492 = extractelement <4 x float> %489, i32 2
  %493 = bitcast float %482 to i32
  %494 = bitcast float %484 to i32
  %495 = insertelement <2 x i32> undef, i32 %493, i32 0
  %496 = insertelement <2 x i32> %495, i32 %494, i32 1
  %497 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %496, <32 x i8> %39, <16 x i8> %41, i32 2)
  %498 = extractelement <4 x float> %497, i32 0
  %499 = call float @fabs(float %498)
  %500 = fcmp oge float %499, %25
  %501 = sext i1 %500 to i32
  %502 = bitcast i32 %501 to float
  %503 = bitcast float %502 to i32
  %504 = and i32 %503, 1065353216
  %505 = bitcast i32 %504 to float
  %506 = fmul float %490, %505
  %507 = fmul float %491, %505
  %508 = fmul float %492, %505
  %509 = fmul float %506, 0x3FE2339C00000000
  %510 = fmul float %507, 0x3FE2339C00000000
  %511 = fmul float %508, 0x3FE2339C00000000
  %512 = fadd float %474, %509
  %513 = fadd float %475, %510
  %514 = fadd float %476, %511
  %515 = fsub float -0.000000e+00, %59
  %516 = fadd float %478, %515
  %517 = fsub float -0.000000e+00, %60
  %518 = fadd float %480, %517
  %519 = fsub float -0.000000e+00, %63
  %520 = fadd float %482, %519
  %521 = fsub float -0.000000e+00, %64
  %522 = fadd float %484, %521
  %523 = bitcast float %516 to i32
  %524 = bitcast float %518 to i32
  %525 = insertelement <2 x i32> undef, i32 %523, i32 0
  %526 = insertelement <2 x i32> %525, i32 %524, i32 1
  %527 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %526, <32 x i8> %35, <16 x i8> %37, i32 2)
  %528 = extractelement <4 x float> %527, i32 0
  %529 = extractelement <4 x float> %527, i32 1
  %530 = extractelement <4 x float> %527, i32 2
  %531 = bitcast float %520 to i32
  %532 = bitcast float %522 to i32
  %533 = insertelement <2 x i32> undef, i32 %531, i32 0
  %534 = insertelement <2 x i32> %533, i32 %532, i32 1
  %535 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %534, <32 x i8> %39, <16 x i8> %41, i32 2)
  %536 = extractelement <4 x float> %535, i32 0
  %537 = call float @fabs(float %536)
  %538 = fcmp oge float %537, %25
  %539 = sext i1 %538 to i32
  %540 = bitcast i32 %539 to float
  %541 = bitcast float %540 to i32
  %542 = and i32 %541, 1065353216
  %543 = bitcast i32 %542 to float
  %544 = fmul float %528, %543
  %545 = fmul float %529, %543
  %546 = fmul float %530, %543
  %547 = fmul float %544, 0x3FE14AA100000000
  %548 = fmul float %545, 0x3FE14AA100000000
  %549 = fmul float %546, 0x3FE14AA100000000
  %550 = fadd float %512, %547
  %551 = fadd float %513, %548
  %552 = fadd float %514, %549
  %553 = fsub float -0.000000e+00, %59
  %554 = fadd float %516, %553
  %555 = fsub float -0.000000e+00, %60
  %556 = fadd float %518, %555
  %557 = fsub float -0.000000e+00, %63
  %558 = fadd float %520, %557
  %559 = fsub float -0.000000e+00, %64
  %560 = fadd float %522, %559
  %561 = bitcast float %554 to i32
  %562 = bitcast float %556 to i32
  %563 = insertelement <2 x i32> undef, i32 %561, i32 0
  %564 = insertelement <2 x i32> %563, i32 %562, i32 1
  %565 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %564, <32 x i8> %35, <16 x i8> %37, i32 2)
  %566 = extractelement <4 x float> %565, i32 0
  %567 = extractelement <4 x float> %565, i32 1
  %568 = extractelement <4 x float> %565, i32 2
  %569 = bitcast float %558 to i32
  %570 = bitcast float %560 to i32
  %571 = insertelement <2 x i32> undef, i32 %569, i32 0
  %572 = insertelement <2 x i32> %571, i32 %570, i32 1
  %573 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %572, <32 x i8> %39, <16 x i8> %41, i32 2)
  %574 = extractelement <4 x float> %573, i32 0
  %575 = call float @fabs(float %574)
  %576 = fcmp oge float %575, %25
  %577 = sext i1 %576 to i32
  %578 = bitcast i32 %577 to float
  %579 = bitcast float %578 to i32
  %580 = and i32 %579, 1065353216
  %581 = bitcast i32 %580 to float
  %582 = fmul float %566, %581
  %583 = fmul float %567, %581
  %584 = fmul float %568, %581
  %585 = fmul float %582, 0x3FE06D4C20000000
  %586 = fmul float %583, 0x3FE06D4C20000000
  %587 = fmul float %584, 0x3FE06D4C20000000
  %588 = fadd float %550, %585
  %589 = fadd float %551, %586
  %590 = fadd float %552, %587
  %591 = fsub float -0.000000e+00, %59
  %592 = fadd float %554, %591
  %593 = fsub float -0.000000e+00, %60
  %594 = fadd float %556, %593
  %595 = fsub float -0.000000e+00, %63
  %596 = fadd float %558, %595
  %597 = fsub float -0.000000e+00, %64
  %598 = fadd float %560, %597
  %599 = bitcast float %592 to i32
  %600 = bitcast float %594 to i32
  %601 = insertelement <2 x i32> undef, i32 %599, i32 0
  %602 = insertelement <2 x i32> %601, i32 %600, i32 1
  %603 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %602, <32 x i8> %35, <16 x i8> %37, i32 2)
  %604 = extractelement <4 x float> %603, i32 0
  %605 = extractelement <4 x float> %603, i32 1
  %606 = extractelement <4 x float> %603, i32 2
  %607 = bitcast float %596 to i32
  %608 = bitcast float %598 to i32
  %609 = insertelement <2 x i32> undef, i32 %607, i32 0
  %610 = insertelement <2 x i32> %609, i32 %608, i32 1
  %611 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %610, <32 x i8> %39, <16 x i8> %41, i32 2)
  %612 = extractelement <4 x float> %611, i32 0
  %613 = call float @fabs(float %612)
  %614 = fcmp oge float %613, %25
  %615 = sext i1 %614 to i32
  %616 = bitcast i32 %615 to float
  %617 = bitcast float %616 to i32
  %618 = and i32 %617, 1065353216
  %619 = bitcast i32 %618 to float
  %620 = fmul float %604, %619
  %621 = fmul float %605, %619
  %622 = fmul float %606, %619
  %623 = fmul float %620, 0x3FDF3610A0000000
  %624 = fmul float %621, 0x3FDF3610A0000000
  %625 = fmul float %622, 0x3FDF3610A0000000
  %626 = fadd float %588, %623
  %627 = fadd float %589, %624
  %628 = fadd float %590, %625
  %629 = fsub float -0.000000e+00, %59
  %630 = fadd float %592, %629
  %631 = fsub float -0.000000e+00, %60
  %632 = fadd float %594, %631
  %633 = fsub float -0.000000e+00, %63
  %634 = fadd float %596, %633
  %635 = fsub float -0.000000e+00, %64
  %636 = fadd float %598, %635
  %637 = bitcast float %630 to i32
  %638 = bitcast float %632 to i32
  %639 = insertelement <2 x i32> undef, i32 %637, i32 0
  %640 = insertelement <2 x i32> %639, i32 %638, i32 1
  %641 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %640, <32 x i8> %35, <16 x i8> %37, i32 2)
  %642 = extractelement <4 x float> %641, i32 0
  %643 = extractelement <4 x float> %641, i32 1
  %644 = extractelement <4 x float> %641, i32 2
  %645 = bitcast float %634 to i32
  %646 = bitcast float %636 to i32
  %647 = insertelement <2 x i32> undef, i32 %645, i32 0
  %648 = insertelement <2 x i32> %647, i32 %646, i32 1
  %649 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %648, <32 x i8> %39, <16 x i8> %41, i32 2)
  %650 = extractelement <4 x float> %649, i32 0
  %651 = call float @fabs(float %650)
  %652 = fcmp oge float %651, %25
  %653 = sext i1 %652 to i32
  %654 = bitcast i32 %653 to float
  %655 = bitcast float %654 to i32
  %656 = and i32 %655, 1065353216
  %657 = bitcast i32 %656 to float
  %658 = fmul float %642, %657
  %659 = fmul float %643, %657
  %660 = fmul float %644, %657
  %661 = fmul float %658, 0x3FDDA68FC0000000
  %662 = fmul float %659, 0x3FDDA68FC0000000
  %663 = fmul float %660, 0x3FDDA68FC0000000
  %664 = fadd float %626, %661
  %665 = fadd float %627, %662
  %666 = fadd float %628, %663
  %667 = fsub float -0.000000e+00, %59
  %668 = fadd float %630, %667
  %669 = fsub float -0.000000e+00, %60
  %670 = fadd float %632, %669
  %671 = fsub float -0.000000e+00, %63
  %672 = fadd float %634, %671
  %673 = fsub float -0.000000e+00, %64
  %674 = fadd float %636, %673
  %675 = bitcast float %668 to i32
  %676 = bitcast float %670 to i32
  %677 = insertelement <2 x i32> undef, i32 %675, i32 0
  %678 = insertelement <2 x i32> %677, i32 %676, i32 1
  %679 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %678, <32 x i8> %35, <16 x i8> %37, i32 2)
  %680 = extractelement <4 x float> %679, i32 0
  %681 = extractelement <4 x float> %679, i32 1
  %682 = extractelement <4 x float> %679, i32 2
  %683 = bitcast float %672 to i32
  %684 = bitcast float %674 to i32
  %685 = insertelement <2 x i32> undef, i32 %683, i32 0
  %686 = insertelement <2 x i32> %685, i32 %684, i32 1
  %687 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %686, <32 x i8> %39, <16 x i8> %41, i32 2)
  %688 = extractelement <4 x float> %687, i32 0
  %689 = call float @fabs(float %688)
  %690 = fcmp oge float %689, %25
  %691 = sext i1 %690 to i32
  %692 = bitcast i32 %691 to float
  %693 = bitcast float %692 to i32
  %694 = and i32 %693, 1065353216
  %695 = bitcast i32 %694 to float
  %696 = fmul float %680, %695
  %697 = fmul float %681, %695
  %698 = fmul float %682, %695
  %699 = fmul float %696, 0x3FDC2B0880000000
  %700 = fmul float %697, 0x3FDC2B0880000000
  %701 = fmul float %698, 0x3FDC2B0880000000
  %702 = fadd float %664, %699
  %703 = fadd float %665, %700
  %704 = fadd float %666, %701
  %705 = fsub float -0.000000e+00, %59
  %706 = fadd float %668, %705
  %707 = fsub float -0.000000e+00, %60
  %708 = fadd float %670, %707
  %709 = fsub float -0.000000e+00, %63
  %710 = fadd float %672, %709
  %711 = fsub float -0.000000e+00, %64
  %712 = fadd float %674, %711
  %713 = bitcast float %706 to i32
  %714 = bitcast float %708 to i32
  %715 = insertelement <2 x i32> undef, i32 %713, i32 0
  %716 = insertelement <2 x i32> %715, i32 %714, i32 1
  %717 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %716, <32 x i8> %35, <16 x i8> %37, i32 2)
  %718 = extractelement <4 x float> %717, i32 0
  %719 = extractelement <4 x float> %717, i32 1
  %720 = extractelement <4 x float> %717, i32 2
  %721 = bitcast float %710 to i32
  %722 = bitcast float %712 to i32
  %723 = insertelement <2 x i32> undef, i32 %721, i32 0
  %724 = insertelement <2 x i32> %723, i32 %722, i32 1
  %725 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %724, <32 x i8> %39, <16 x i8> %41, i32 2)
  %726 = extractelement <4 x float> %725, i32 0
  %727 = call float @fabs(float %726)
  %728 = fcmp oge float %727, %25
  %729 = sext i1 %728 to i32
  %730 = bitcast i32 %729 to float
  %731 = bitcast float %730 to i32
  %732 = and i32 %731, 1065353216
  %733 = bitcast i32 %732 to float
  %734 = fmul float %718, %733
  %735 = fmul float %719, %733
  %736 = fmul float %720, %733
  %737 = fmul float %734, 0x3FDAC27B40000000
  %738 = fmul float %735, 0x3FDAC27B40000000
  %739 = fmul float %736, 0x3FDAC27B40000000
  %740 = fadd float %702, %737
  %741 = fadd float %703, %738
  %742 = fadd float %704, %739
  %743 = fsub float -0.000000e+00, %59
  %744 = fadd float %706, %743
  %745 = fsub float -0.000000e+00, %60
  %746 = fadd float %708, %745
  %747 = fsub float -0.000000e+00, %63
  %748 = fadd float %710, %747
  %749 = fsub float -0.000000e+00, %64
  %750 = fadd float %712, %749
  %751 = bitcast float %744 to i32
  %752 = bitcast float %746 to i32
  %753 = insertelement <2 x i32> undef, i32 %751, i32 0
  %754 = insertelement <2 x i32> %753, i32 %752, i32 1
  %755 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %754, <32 x i8> %35, <16 x i8> %37, i32 2)
  %756 = extractelement <4 x float> %755, i32 0
  %757 = extractelement <4 x float> %755, i32 1
  %758 = extractelement <4 x float> %755, i32 2
  %759 = bitcast float %748 to i32
  %760 = bitcast float %750 to i32
  %761 = insertelement <2 x i32> undef, i32 %759, i32 0
  %762 = insertelement <2 x i32> %761, i32 %760, i32 1
  %763 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %762, <32 x i8> %39, <16 x i8> %41, i32 2)
  %764 = extractelement <4 x float> %763, i32 0
  %765 = call float @fabs(float %764)
  %766 = fcmp oge float %765, %25
  %767 = sext i1 %766 to i32
  %768 = bitcast i32 %767 to float
  %769 = bitcast float %768 to i32
  %770 = and i32 %769, 1065353216
  %771 = bitcast i32 %770 to float
  %772 = fmul float %756, %771
  %773 = fmul float %757, %771
  %774 = fmul float %758, %771
  %775 = fmul float %772, 0x3FD96BF520000000
  %776 = fmul float %773, 0x3FD96BF520000000
  %777 = fmul float %774, 0x3FD96BF520000000
  %778 = fadd float %740, %775
  %779 = fadd float %741, %776
  %780 = fadd float %742, %777
  %781 = fsub float -0.000000e+00, %59
  %782 = fadd float %744, %781
  %783 = fsub float -0.000000e+00, %60
  %784 = fadd float %746, %783
  %785 = fsub float -0.000000e+00, %63
  %786 = fadd float %748, %785
  %787 = fsub float -0.000000e+00, %64
  %788 = fadd float %750, %787
  %789 = bitcast float %782 to i32
  %790 = bitcast float %784 to i32
  %791 = insertelement <2 x i32> undef, i32 %789, i32 0
  %792 = insertelement <2 x i32> %791, i32 %790, i32 1
  %793 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %792, <32 x i8> %35, <16 x i8> %37, i32 2)
  %794 = extractelement <4 x float> %793, i32 0
  %795 = extractelement <4 x float> %793, i32 1
  %796 = extractelement <4 x float> %793, i32 2
  %797 = bitcast float %786 to i32
  %798 = bitcast float %788 to i32
  %799 = insertelement <2 x i32> undef, i32 %797, i32 0
  %800 = insertelement <2 x i32> %799, i32 %798, i32 1
  %801 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %800, <32 x i8> %39, <16 x i8> %41, i32 2)
  %802 = extractelement <4 x float> %801, i32 0
  %803 = call float @fabs(float %802)
  %804 = fcmp oge float %803, %25
  %805 = sext i1 %804 to i32
  %806 = bitcast i32 %805 to float
  %807 = bitcast float %806 to i32
  %808 = and i32 %807, 1065353216
  %809 = bitcast i32 %808 to float
  %810 = fmul float %794, %809
  %811 = fmul float %795, %809
  %812 = fmul float %796, %809
  %813 = fmul float %810, 0x3FD8268F40000000
  %814 = fmul float %811, 0x3FD8268F40000000
  %815 = fmul float %812, 0x3FD8268F40000000
  %816 = fadd float %778, %813
  %817 = fadd float %779, %814
  %818 = fadd float %780, %815
  %819 = fsub float -0.000000e+00, %59
  %820 = fadd float %782, %819
  %821 = fsub float -0.000000e+00, %60
  %822 = fadd float %784, %821
  %823 = fsub float -0.000000e+00, %63
  %824 = fadd float %786, %823
  %825 = fsub float -0.000000e+00, %64
  %826 = fadd float %788, %825
  %827 = bitcast float %820 to i32
  %828 = bitcast float %822 to i32
  %829 = insertelement <2 x i32> undef, i32 %827, i32 0
  %830 = insertelement <2 x i32> %829, i32 %828, i32 1
  %831 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %830, <32 x i8> %35, <16 x i8> %37, i32 2)
  %832 = extractelement <4 x float> %831, i32 0
  %833 = extractelement <4 x float> %831, i32 1
  %834 = extractelement <4 x float> %831, i32 2
  %835 = bitcast float %824 to i32
  %836 = bitcast float %826 to i32
  %837 = insertelement <2 x i32> undef, i32 %835, i32 0
  %838 = insertelement <2 x i32> %837, i32 %836, i32 1
  %839 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %838, <32 x i8> %39, <16 x i8> %41, i32 2)
  %840 = extractelement <4 x float> %839, i32 0
  %841 = call float @fabs(float %840)
  %842 = fcmp oge float %841, %25
  %843 = sext i1 %842 to i32
  %844 = bitcast i32 %843 to float
  %845 = bitcast float %844 to i32
  %846 = and i32 %845, 1065353216
  %847 = bitcast i32 %846 to float
  %848 = fmul float %832, %847
  %849 = fmul float %833, %847
  %850 = fmul float %834, %847
  %851 = fmul float %848, 0x3FD6F16E80000000
  %852 = fmul float %849, 0x3FD6F16E80000000
  %853 = fmul float %850, 0x3FD6F16E80000000
  %854 = fadd float %816, %851
  %855 = fadd float %817, %852
  %856 = fadd float %818, %853
  %857 = fsub float -0.000000e+00, %59
  %858 = fadd float %820, %857
  %859 = fsub float -0.000000e+00, %60
  %860 = fadd float %822, %859
  %861 = fsub float -0.000000e+00, %63
  %862 = fadd float %824, %861
  %863 = fsub float -0.000000e+00, %64
  %864 = fadd float %826, %863
  %865 = bitcast float %858 to i32
  %866 = bitcast float %860 to i32
  %867 = insertelement <2 x i32> undef, i32 %865, i32 0
  %868 = insertelement <2 x i32> %867, i32 %866, i32 1
  %869 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %868, <32 x i8> %35, <16 x i8> %37, i32 2)
  %870 = extractelement <4 x float> %869, i32 0
  %871 = extractelement <4 x float> %869, i32 1
  %872 = extractelement <4 x float> %869, i32 2
  %873 = bitcast float %862 to i32
  %874 = bitcast float %864 to i32
  %875 = insertelement <2 x i32> undef, i32 %873, i32 0
  %876 = insertelement <2 x i32> %875, i32 %874, i32 1
  %877 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %876, <32 x i8> %39, <16 x i8> %41, i32 2)
  %878 = extractelement <4 x float> %877, i32 0
  %879 = call float @fabs(float %878)
  %880 = fcmp oge float %879, %25
  %881 = sext i1 %880 to i32
  %882 = bitcast i32 %881 to float
  %883 = bitcast float %882 to i32
  %884 = and i32 %883, 1065353216
  %885 = bitcast i32 %884 to float
  %886 = fmul float %870, %885
  %887 = fmul float %871, %885
  %888 = fmul float %872, %885
  %889 = fmul float %886, 0x3FD5CBC280000000
  %890 = fmul float %887, 0x3FD5CBC280000000
  %891 = fmul float %888, 0x3FD5CBC280000000
  %892 = fadd float %854, %889
  %893 = fadd float %855, %890
  %894 = fadd float %856, %891
  %895 = fsub float -0.000000e+00, %59
  %896 = fadd float %858, %895
  %897 = fsub float -0.000000e+00, %60
  %898 = fadd float %860, %897
  %899 = fsub float -0.000000e+00, %63
  %900 = fadd float %862, %899
  %901 = fsub float -0.000000e+00, %64
  %902 = fadd float %864, %901
  %903 = bitcast float %896 to i32
  %904 = bitcast float %898 to i32
  %905 = insertelement <2 x i32> undef, i32 %903, i32 0
  %906 = insertelement <2 x i32> %905, i32 %904, i32 1
  %907 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %906, <32 x i8> %35, <16 x i8> %37, i32 2)
  %908 = extractelement <4 x float> %907, i32 0
  %909 = extractelement <4 x float> %907, i32 1
  %910 = extractelement <4 x float> %907, i32 2
  %911 = bitcast float %900 to i32
  %912 = bitcast float %902 to i32
  %913 = insertelement <2 x i32> undef, i32 %911, i32 0
  %914 = insertelement <2 x i32> %913, i32 %912, i32 1
  %915 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %914, <32 x i8> %39, <16 x i8> %41, i32 2)
  %916 = extractelement <4 x float> %915, i32 0
  %917 = call float @fabs(float %916)
  %918 = fcmp oge float %917, %25
  %919 = sext i1 %918 to i32
  %920 = bitcast i32 %919 to float
  %921 = bitcast float %920 to i32
  %922 = and i32 %921, 1065353216
  %923 = bitcast i32 %922 to float
  %924 = fmul float %908, %923
  %925 = fmul float %909, %923
  %926 = fmul float %910, %923
  %927 = fmul float %924, 0x3FD4B4C580000000
  %928 = fmul float %925, 0x3FD4B4C580000000
  %929 = fmul float %926, 0x3FD4B4C580000000
  %930 = fadd float %892, %927
  %931 = fadd float %893, %928
  %932 = fadd float %894, %929
  %933 = fsub float -0.000000e+00, %59
  %934 = fadd float %896, %933
  %935 = fsub float -0.000000e+00, %60
  %936 = fadd float %898, %935
  %937 = fsub float -0.000000e+00, %63
  %938 = fadd float %900, %937
  %939 = fsub float -0.000000e+00, %64
  %940 = fadd float %902, %939
  %941 = bitcast float %934 to i32
  %942 = bitcast float %936 to i32
  %943 = insertelement <2 x i32> undef, i32 %941, i32 0
  %944 = insertelement <2 x i32> %943, i32 %942, i32 1
  %945 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %944, <32 x i8> %35, <16 x i8> %37, i32 2)
  %946 = extractelement <4 x float> %945, i32 0
  %947 = extractelement <4 x float> %945, i32 1
  %948 = extractelement <4 x float> %945, i32 2
  %949 = bitcast float %938 to i32
  %950 = bitcast float %940 to i32
  %951 = insertelement <2 x i32> undef, i32 %949, i32 0
  %952 = insertelement <2 x i32> %951, i32 %950, i32 1
  %953 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %952, <32 x i8> %39, <16 x i8> %41, i32 2)
  %954 = extractelement <4 x float> %953, i32 0
  %955 = call float @fabs(float %954)
  %956 = fcmp oge float %955, %25
  %957 = sext i1 %956 to i32
  %958 = bitcast i32 %957 to float
  %959 = bitcast float %958 to i32
  %960 = and i32 %959, 1065353216
  %961 = bitcast i32 %960 to float
  %962 = fmul float %946, %961
  %963 = fmul float %947, %961
  %964 = fmul float %948, %961
  %965 = fmul float %962, 0x3FD3ABBBA0000000
  %966 = fmul float %963, 0x3FD3ABBBA0000000
  %967 = fmul float %964, 0x3FD3ABBBA0000000
  %968 = fadd float %930, %965
  %969 = fadd float %931, %966
  %970 = fadd float %932, %967
  %971 = fsub float -0.000000e+00, %59
  %972 = fadd float %934, %971
  %973 = fsub float -0.000000e+00, %60
  %974 = fadd float %936, %973
  %975 = fsub float -0.000000e+00, %63
  %976 = fadd float %938, %975
  %977 = fsub float -0.000000e+00, %64
  %978 = fadd float %940, %977
  %979 = bitcast float %972 to i32
  %980 = bitcast float %974 to i32
  %981 = insertelement <2 x i32> undef, i32 %979, i32 0
  %982 = insertelement <2 x i32> %981, i32 %980, i32 1
  %983 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %982, <32 x i8> %35, <16 x i8> %37, i32 2)
  %984 = extractelement <4 x float> %983, i32 0
  %985 = extractelement <4 x float> %983, i32 1
  %986 = extractelement <4 x float> %983, i32 2
  %987 = bitcast float %976 to i32
  %988 = bitcast float %978 to i32
  %989 = insertelement <2 x i32> undef, i32 %987, i32 0
  %990 = insertelement <2 x i32> %989, i32 %988, i32 1
  %991 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %990, <32 x i8> %39, <16 x i8> %41, i32 2)
  %992 = extractelement <4 x float> %991, i32 0
  %993 = call float @fabs(float %992)
  %994 = fcmp oge float %993, %25
  %995 = sext i1 %994 to i32
  %996 = bitcast i32 %995 to float
  %997 = bitcast float %996 to i32
  %998 = and i32 %997, 1065353216
  %999 = bitcast i32 %998 to float
  %1000 = fmul float %984, %999
  %1001 = fmul float %985, %999
  %1002 = fmul float %986, %999
  %1003 = fmul float %1000, 0x3FD2AFF240000000
  %1004 = fmul float %1001, 0x3FD2AFF240000000
  %1005 = fmul float %1002, 0x3FD2AFF240000000
  %1006 = fadd float %968, %1003
  %1007 = fadd float %969, %1004
  %1008 = fadd float %970, %1005
  %1009 = fsub float -0.000000e+00, %59
  %1010 = fadd float %972, %1009
  %1011 = fsub float -0.000000e+00, %60
  %1012 = fadd float %974, %1011
  %1013 = fsub float -0.000000e+00, %63
  %1014 = fadd float %976, %1013
  %1015 = fsub float -0.000000e+00, %64
  %1016 = fadd float %978, %1015
  %1017 = bitcast float %1010 to i32
  %1018 = bitcast float %1012 to i32
  %1019 = insertelement <2 x i32> undef, i32 %1017, i32 0
  %1020 = insertelement <2 x i32> %1019, i32 %1018, i32 1
  %1021 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1020, <32 x i8> %35, <16 x i8> %37, i32 2)
  %1022 = extractelement <4 x float> %1021, i32 0
  %1023 = extractelement <4 x float> %1021, i32 1
  %1024 = extractelement <4 x float> %1021, i32 2
  %1025 = bitcast float %1014 to i32
  %1026 = bitcast float %1016 to i32
  %1027 = insertelement <2 x i32> undef, i32 %1025, i32 0
  %1028 = insertelement <2 x i32> %1027, i32 %1026, i32 1
  %1029 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1028, <32 x i8> %39, <16 x i8> %41, i32 2)
  %1030 = extractelement <4 x float> %1029, i32 0
  %1031 = call float @fabs(float %1030)
  %1032 = fcmp oge float %1031, %25
  %1033 = sext i1 %1032 to i32
  %1034 = bitcast i32 %1033 to float
  %1035 = bitcast float %1034 to i32
  %1036 = and i32 %1035, 1065353216
  %1037 = bitcast i32 %1036 to float
  %1038 = fmul float %1022, %1037
  %1039 = fmul float %1023, %1037
  %1040 = fmul float %1024, %1037
  %1041 = fmul float %1038, 0x3FD1C0BFC0000000
  %1042 = fmul float %1039, 0x3FD1C0BFC0000000
  %1043 = fmul float %1040, 0x3FD1C0BFC0000000
  %1044 = fadd float %1006, %1041
  %1045 = fadd float %1007, %1042
  %1046 = fadd float %1008, %1043
  %1047 = fsub float -0.000000e+00, %59
  %1048 = fadd float %1010, %1047
  %1049 = fsub float -0.000000e+00, %60
  %1050 = fadd float %1012, %1049
  %1051 = fsub float -0.000000e+00, %63
  %1052 = fadd float %1014, %1051
  %1053 = fsub float -0.000000e+00, %64
  %1054 = fadd float %1016, %1053
  %1055 = bitcast float %1048 to i32
  %1056 = bitcast float %1050 to i32
  %1057 = insertelement <2 x i32> undef, i32 %1055, i32 0
  %1058 = insertelement <2 x i32> %1057, i32 %1056, i32 1
  %1059 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1058, <32 x i8> %35, <16 x i8> %37, i32 2)
  %1060 = extractelement <4 x float> %1059, i32 0
  %1061 = extractelement <4 x float> %1059, i32 1
  %1062 = extractelement <4 x float> %1059, i32 2
  %1063 = bitcast float %1052 to i32
  %1064 = bitcast float %1054 to i32
  %1065 = insertelement <2 x i32> undef, i32 %1063, i32 0
  %1066 = insertelement <2 x i32> %1065, i32 %1064, i32 1
  %1067 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1066, <32 x i8> %39, <16 x i8> %41, i32 2)
  %1068 = extractelement <4 x float> %1067, i32 0
  %1069 = call float @fabs(float %1068)
  %1070 = fcmp oge float %1069, %25
  %1071 = sext i1 %1070 to i32
  %1072 = bitcast i32 %1071 to float
  %1073 = bitcast float %1072 to i32
  %1074 = and i32 %1073, 1065353216
  %1075 = bitcast i32 %1074 to float
  %1076 = fmul float %1060, %1075
  %1077 = fmul float %1061, %1075
  %1078 = fmul float %1062, %1075
  %1079 = fmul float %1076, 0x3FD0DD8300000000
  %1080 = fmul float %1077, 0x3FD0DD8300000000
  %1081 = fmul float %1078, 0x3FD0DD8300000000
  %1082 = fadd float %1044, %1079
  %1083 = fadd float %1045, %1080
  %1084 = fadd float %1046, %1081
  %1085 = fsub float -0.000000e+00, %59
  %1086 = fadd float %1048, %1085
  %1087 = fsub float -0.000000e+00, %60
  %1088 = fadd float %1050, %1087
  %1089 = fsub float -0.000000e+00, %63
  %1090 = fadd float %1052, %1089
  %1091 = fsub float -0.000000e+00, %64
  %1092 = fadd float %1054, %1091
  %1093 = bitcast float %1086 to i32
  %1094 = bitcast float %1088 to i32
  %1095 = insertelement <2 x i32> undef, i32 %1093, i32 0
  %1096 = insertelement <2 x i32> %1095, i32 %1094, i32 1
  %1097 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1096, <32 x i8> %35, <16 x i8> %37, i32 2)
  %1098 = extractelement <4 x float> %1097, i32 0
  %1099 = extractelement <4 x float> %1097, i32 1
  %1100 = extractelement <4 x float> %1097, i32 2
  %1101 = bitcast float %1090 to i32
  %1102 = bitcast float %1092 to i32
  %1103 = insertelement <2 x i32> undef, i32 %1101, i32 0
  %1104 = insertelement <2 x i32> %1103, i32 %1102, i32 1
  %1105 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1104, <32 x i8> %39, <16 x i8> %41, i32 2)
  %1106 = extractelement <4 x float> %1105, i32 0
  %1107 = call float @fabs(float %1106)
  %1108 = fcmp oge float %1107, %25
  %1109 = sext i1 %1108 to i32
  %1110 = bitcast i32 %1109 to float
  %1111 = bitcast float %1110 to i32
  %1112 = and i32 %1111, 1065353216
  %1113 = bitcast i32 %1112 to float
  %1114 = fmul float %1098, %1113
  %1115 = fmul float %1099, %1113
  %1116 = fmul float %1100, %1113
  %1117 = fmul float %1114, 0x3FD005A2E0000000
  %1118 = fmul float %1115, 0x3FD005A2E0000000
  %1119 = fmul float %1116, 0x3FD005A2E0000000
  %1120 = fadd float %1082, %1117
  %1121 = fadd float %1083, %1118
  %1122 = fadd float %1084, %1119
  %1123 = fsub float -0.000000e+00, %59
  %1124 = fadd float %1086, %1123
  %1125 = fsub float -0.000000e+00, %60
  %1126 = fadd float %1088, %1125
  %1127 = fsub float -0.000000e+00, %63
  %1128 = fadd float %1090, %1127
  %1129 = fsub float -0.000000e+00, %64
  %1130 = fadd float %1092, %1129
  %1131 = bitcast float %1124 to i32
  %1132 = bitcast float %1126 to i32
  %1133 = insertelement <2 x i32> undef, i32 %1131, i32 0
  %1134 = insertelement <2 x i32> %1133, i32 %1132, i32 1
  %1135 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1134, <32 x i8> %35, <16 x i8> %37, i32 2)
  %1136 = extractelement <4 x float> %1135, i32 0
  %1137 = extractelement <4 x float> %1135, i32 1
  %1138 = extractelement <4 x float> %1135, i32 2
  %1139 = bitcast float %1128 to i32
  %1140 = bitcast float %1130 to i32
  %1141 = insertelement <2 x i32> undef, i32 %1139, i32 0
  %1142 = insertelement <2 x i32> %1141, i32 %1140, i32 1
  %1143 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1142, <32 x i8> %39, <16 x i8> %41, i32 2)
  %1144 = extractelement <4 x float> %1143, i32 0
  %1145 = call float @fabs(float %1144)
  %1146 = fcmp oge float %1145, %25
  %1147 = sext i1 %1146 to i32
  %1148 = bitcast i32 %1147 to float
  %1149 = bitcast float %1148 to i32
  %1150 = and i32 %1149, 1065353216
  %1151 = bitcast i32 %1150 to float
  %1152 = fmul float %1136, %1151
  %1153 = fmul float %1137, %1151
  %1154 = fmul float %1138, %1151
  %1155 = fmul float %1152, 0x3FCE711BE0000000
  %1156 = fmul float %1153, 0x3FCE711BE0000000
  %1157 = fmul float %1154, 0x3FCE711BE0000000
  %1158 = fadd float %1120, %1155
  %1159 = fadd float %1121, %1156
  %1160 = fadd float %1122, %1157
  %1161 = fsub float -0.000000e+00, %59
  %1162 = fadd float %1124, %1161
  %1163 = fsub float -0.000000e+00, %60
  %1164 = fadd float %1126, %1163
  %1165 = fsub float -0.000000e+00, %63
  %1166 = fadd float %1128, %1165
  %1167 = fsub float -0.000000e+00, %64
  %1168 = fadd float %1130, %1167
  %1169 = bitcast float %1162 to i32
  %1170 = bitcast float %1164 to i32
  %1171 = insertelement <2 x i32> undef, i32 %1169, i32 0
  %1172 = insertelement <2 x i32> %1171, i32 %1170, i32 1
  %1173 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1172, <32 x i8> %35, <16 x i8> %37, i32 2)
  %1174 = extractelement <4 x float> %1173, i32 0
  %1175 = extractelement <4 x float> %1173, i32 1
  %1176 = extractelement <4 x float> %1173, i32 2
  %1177 = bitcast float %1166 to i32
  %1178 = bitcast float %1168 to i32
  %1179 = insertelement <2 x i32> undef, i32 %1177, i32 0
  %1180 = insertelement <2 x i32> %1179, i32 %1178, i32 1
  %1181 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1180, <32 x i8> %39, <16 x i8> %41, i32 2)
  %1182 = extractelement <4 x float> %1181, i32 0
  %1183 = call float @fabs(float %1182)
  %1184 = fcmp oge float %1183, %25
  %1185 = sext i1 %1184 to i32
  %1186 = bitcast i32 %1185 to float
  %1187 = bitcast float %1186 to i32
  %1188 = and i32 %1187, 1065353216
  %1189 = bitcast i32 %1188 to float
  %1190 = fmul float %1174, %1189
  %1191 = fmul float %1175, %1189
  %1192 = fmul float %1176, %1189
  %1193 = fmul float %1190, 0x3FCCEB7400000000
  %1194 = fmul float %1191, 0x3FCCEB7400000000
  %1195 = fmul float %1192, 0x3FCCEB7400000000
  %1196 = fadd float %1158, %1193
  %1197 = fadd float %1159, %1194
  %1198 = fadd float %1160, %1195
  %1199 = fsub float -0.000000e+00, %59
  %1200 = fadd float %1162, %1199
  %1201 = fsub float -0.000000e+00, %60
  %1202 = fadd float %1164, %1201
  %1203 = fsub float -0.000000e+00, %63
  %1204 = fadd float %1166, %1203
  %1205 = fsub float -0.000000e+00, %64
  %1206 = fadd float %1168, %1205
  %1207 = bitcast float %1200 to i32
  %1208 = bitcast float %1202 to i32
  %1209 = insertelement <2 x i32> undef, i32 %1207, i32 0
  %1210 = insertelement <2 x i32> %1209, i32 %1208, i32 1
  %1211 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1210, <32 x i8> %35, <16 x i8> %37, i32 2)
  %1212 = extractelement <4 x float> %1211, i32 0
  %1213 = extractelement <4 x float> %1211, i32 1
  %1214 = extractelement <4 x float> %1211, i32 2
  %1215 = bitcast float %1204 to i32
  %1216 = bitcast float %1206 to i32
  %1217 = insertelement <2 x i32> undef, i32 %1215, i32 0
  %1218 = insertelement <2 x i32> %1217, i32 %1216, i32 1
  %1219 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1218, <32 x i8> %39, <16 x i8> %41, i32 2)
  %1220 = extractelement <4 x float> %1219, i32 0
  %1221 = call float @fabs(float %1220)
  %1222 = fcmp oge float %1221, %25
  %1223 = sext i1 %1222 to i32
  %1224 = bitcast i32 %1223 to float
  %1225 = bitcast float %1224 to i32
  %1226 = and i32 %1225, 1065353216
  %1227 = bitcast i32 %1226 to float
  %1228 = fmul float %1212, %1227
  %1229 = fmul float %1213, %1227
  %1230 = fmul float %1214, %1227
  %1231 = fmul float %1228, 0x3FCB7947C0000000
  %1232 = fmul float %1229, 0x3FCB7947C0000000
  %1233 = fmul float %1230, 0x3FCB7947C0000000
  %1234 = fadd float %1196, %1231
  %1235 = fadd float %1197, %1232
  %1236 = fadd float %1198, %1233
  %1237 = fsub float -0.000000e+00, %59
  %1238 = fadd float %1200, %1237
  %1239 = fsub float -0.000000e+00, %60
  %1240 = fadd float %1202, %1239
  %1241 = fsub float -0.000000e+00, %63
  %1242 = fadd float %1204, %1241
  %1243 = fsub float -0.000000e+00, %64
  %1244 = fadd float %1206, %1243
  %1245 = bitcast float %1238 to i32
  %1246 = bitcast float %1240 to i32
  %1247 = insertelement <2 x i32> undef, i32 %1245, i32 0
  %1248 = insertelement <2 x i32> %1247, i32 %1246, i32 1
  %1249 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1248, <32 x i8> %35, <16 x i8> %37, i32 2)
  %1250 = extractelement <4 x float> %1249, i32 0
  %1251 = extractelement <4 x float> %1249, i32 1
  %1252 = extractelement <4 x float> %1249, i32 2
  %1253 = bitcast float %1242 to i32
  %1254 = bitcast float %1244 to i32
  %1255 = insertelement <2 x i32> undef, i32 %1253, i32 0
  %1256 = insertelement <2 x i32> %1255, i32 %1254, i32 1
  %1257 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1256, <32 x i8> %39, <16 x i8> %41, i32 2)
  %1258 = extractelement <4 x float> %1257, i32 0
  %1259 = call float @fabs(float %1258)
  %1260 = fcmp oge float %1259, %25
  %1261 = sext i1 %1260 to i32
  %1262 = bitcast i32 %1261 to float
  %1263 = bitcast float %1262 to i32
  %1264 = and i32 %1263, 1065353216
  %1265 = bitcast i32 %1264 to float
  %1266 = fmul float %1250, %1265
  %1267 = fmul float %1251, %1265
  %1268 = fmul float %1252, %1265
  %1269 = fmul float %1266, 0x3FCA199DC0000000
  %1270 = fmul float %1267, 0x3FCA199DC0000000
  %1271 = fmul float %1268, 0x3FCA199DC0000000
  %1272 = fadd float %1234, %1269
  %1273 = fadd float %1235, %1270
  %1274 = fadd float %1236, %1271
  %1275 = fsub float -0.000000e+00, %59
  %1276 = fadd float %1238, %1275
  %1277 = fsub float -0.000000e+00, %60
  %1278 = fadd float %1240, %1277
  %1279 = fsub float -0.000000e+00, %63
  %1280 = fadd float %1242, %1279
  %1281 = fsub float -0.000000e+00, %64
  %1282 = fadd float %1244, %1281
  %1283 = bitcast float %1276 to i32
  %1284 = bitcast float %1278 to i32
  %1285 = insertelement <2 x i32> undef, i32 %1283, i32 0
  %1286 = insertelement <2 x i32> %1285, i32 %1284, i32 1
  %1287 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1286, <32 x i8> %35, <16 x i8> %37, i32 2)
  %1288 = extractelement <4 x float> %1287, i32 0
  %1289 = extractelement <4 x float> %1287, i32 1
  %1290 = extractelement <4 x float> %1287, i32 2
  %1291 = bitcast float %1280 to i32
  %1292 = bitcast float %1282 to i32
  %1293 = insertelement <2 x i32> undef, i32 %1291, i32 0
  %1294 = insertelement <2 x i32> %1293, i32 %1292, i32 1
  %1295 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1294, <32 x i8> %39, <16 x i8> %41, i32 2)
  %1296 = extractelement <4 x float> %1295, i32 0
  %1297 = call float @fabs(float %1296)
  %1298 = fcmp oge float %1297, %25
  %1299 = sext i1 %1298 to i32
  %1300 = bitcast i32 %1299 to float
  %1301 = bitcast float %1300 to i32
  %1302 = and i32 %1301, 1065353216
  %1303 = bitcast i32 %1302 to float
  %1304 = fmul float %1288, %1303
  %1305 = fmul float %1289, %1303
  %1306 = fmul float %1290, %1303
  %1307 = fmul float %1304, 0x3FC8CB8900000000
  %1308 = fmul float %1305, 0x3FC8CB8900000000
  %1309 = fmul float %1306, 0x3FC8CB8900000000
  %1310 = fadd float %1272, %1307
  %1311 = fadd float %1273, %1308
  %1312 = fadd float %1274, %1309
  %1313 = fsub float -0.000000e+00, %59
  %1314 = fadd float %1276, %1313
  %1315 = fsub float -0.000000e+00, %60
  %1316 = fadd float %1278, %1315
  %1317 = fsub float -0.000000e+00, %63
  %1318 = fadd float %1280, %1317
  %1319 = fsub float -0.000000e+00, %64
  %1320 = fadd float %1282, %1319
  %1321 = bitcast float %1314 to i32
  %1322 = bitcast float %1316 to i32
  %1323 = insertelement <2 x i32> undef, i32 %1321, i32 0
  %1324 = insertelement <2 x i32> %1323, i32 %1322, i32 1
  %1325 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1324, <32 x i8> %35, <16 x i8> %37, i32 2)
  %1326 = extractelement <4 x float> %1325, i32 0
  %1327 = extractelement <4 x float> %1325, i32 1
  %1328 = extractelement <4 x float> %1325, i32 2
  %1329 = bitcast float %1318 to i32
  %1330 = bitcast float %1320 to i32
  %1331 = insertelement <2 x i32> undef, i32 %1329, i32 0
  %1332 = insertelement <2 x i32> %1331, i32 %1330, i32 1
  %1333 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1332, <32 x i8> %39, <16 x i8> %41, i32 2)
  %1334 = extractelement <4 x float> %1333, i32 0
  %1335 = call float @fabs(float %1334)
  %1336 = fcmp oge float %1335, %25
  %1337 = sext i1 %1336 to i32
  %1338 = bitcast i32 %1337 to float
  %1339 = bitcast float %1338 to i32
  %1340 = and i32 %1339, 1065353216
  %1341 = bitcast i32 %1340 to float
  %1342 = fmul float %1326, %1341
  %1343 = fmul float %1327, %1341
  %1344 = fmul float %1328, %1341
  %1345 = fmul float %1342, 0x3FC78E2880000000
  %1346 = fmul float %1343, 0x3FC78E2880000000
  %1347 = fmul float %1344, 0x3FC78E2880000000
  %1348 = fadd float %1310, %1345
  %1349 = fadd float %1311, %1346
  %1350 = fadd float %1312, %1347
  %1351 = fsub float -0.000000e+00, %59
  %1352 = fadd float %1314, %1351
  %1353 = fsub float -0.000000e+00, %60
  %1354 = fadd float %1316, %1353
  %1355 = fsub float -0.000000e+00, %63
  %1356 = fadd float %1318, %1355
  %1357 = fsub float -0.000000e+00, %64
  %1358 = fadd float %1320, %1357
  %1359 = bitcast float %1352 to i32
  %1360 = bitcast float %1354 to i32
  %1361 = insertelement <2 x i32> undef, i32 %1359, i32 0
  %1362 = insertelement <2 x i32> %1361, i32 %1360, i32 1
  %1363 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1362, <32 x i8> %35, <16 x i8> %37, i32 2)
  %1364 = extractelement <4 x float> %1363, i32 0
  %1365 = extractelement <4 x float> %1363, i32 1
  %1366 = extractelement <4 x float> %1363, i32 2
  %1367 = bitcast float %1356 to i32
  %1368 = bitcast float %1358 to i32
  %1369 = insertelement <2 x i32> undef, i32 %1367, i32 0
  %1370 = insertelement <2 x i32> %1369, i32 %1368, i32 1
  %1371 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1370, <32 x i8> %39, <16 x i8> %41, i32 2)
  %1372 = extractelement <4 x float> %1371, i32 0
  %1373 = call float @fabs(float %1372)
  %1374 = fcmp oge float %1373, %25
  %1375 = sext i1 %1374 to i32
  %1376 = bitcast i32 %1375 to float
  %1377 = bitcast float %1376 to i32
  %1378 = and i32 %1377, 1065353216
  %1379 = bitcast i32 %1378 to float
  %1380 = fmul float %1364, %1379
  %1381 = fmul float %1365, %1379
  %1382 = fmul float %1366, %1379
  %1383 = fmul float %1380, 0x3FC660A680000000
  %1384 = fmul float %1381, 0x3FC660A680000000
  %1385 = fmul float %1382, 0x3FC660A680000000
  %1386 = fadd float %1348, %1383
  %1387 = fadd float %1349, %1384
  %1388 = fadd float %1350, %1385
  %1389 = fmul float %1386, %30
  %1390 = fmul float %1387, %31
  %1391 = fmul float %1388, %32
  %1392 = call i32 @llvm.SI.packf16(float %1389, float %1390)
  %1393 = bitcast i32 %1392 to float
  %1394 = call i32 @llvm.SI.packf16(float %1391, float 0.000000e+00)
  %1395 = bitcast i32 %1394 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %1393, float %1395, float %1393, float %1395)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readonly
declare float @llvm.sin.f32(float) #2

; Function Attrs: readnone
declare float @llvm.AMDIL.fraction.(float) #3

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readonly
declare float @fabs(float) #4

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { nounwind readonly }
attributes #3 = { readnone }
attributes #4 = { readonly }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR7 in %vreg4, %VGPR0 in %vreg5, %VGPR1 in %vreg6

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR7 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR7
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<kill,tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<kill,tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>
	%VGPR0<def> = V_MUL_F32_e32 7.823300e+01, %VGPR3, %EXEC<imp-use>
	%VGPR1<def> = V_MOV_B32_e32 1.298980e+01, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR2, %VGPR1<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_F32_e32 1042479491, %VGPR0<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_SIN_F32_e32 %VGPR0<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_F32_e32 4.375855e+04, %VGPR0<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_FRACT_F32_e32 %VGPR0<kill>, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%22](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 4; mem:LD4[<unknown>]
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 5; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR1<def> = V_MOV_B32_e32 %SGPR1<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR0<kill>, %SGPR0<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 1; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR1<def> = V_SUBREV_F32_e32 %SGPR0<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 11; mem:LD4[<unknown>]
	%VGPR4<def> = V_MOV_B32_e32 2.857143e-02, %EXEC<imp-use>
	S_WAITCNT 127
	%VGPR4<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR4<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_MUL_F32_e32 %VGPR1<kill>, %VGPR4, %EXEC<imp-use>
	%VGPR1<def> = V_MUL_F32_e32 %VGPR1<kill>, %VGPR0, %EXEC<imp-use>
	%VGPR6<def> = V_SUB_F32_e32 %VGPR3, %VGPR1, %EXEC<imp-use>, %VGPR5_VGPR6<imp-def>
	%VGPR8<def> = V_SUB_F32_e32 %VGPR6, %VGPR1, %EXEC<imp-use>, %VGPR7_VGPR8<imp-def>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 0; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR9<def> = V_SUBREV_F32_e32 %SGPR0<kill>, %VGPR2, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e32 %VGPR9<kill>, %VGPR4<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR4<kill>, %VGPR0<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_SUB_F32_e32 %VGPR2, %VGPR0, %EXEC<imp-use>, %VGPR5_VGPR6<imp-use,kill>, %VGPR5_VGPR6<imp-def>
	%VGPR7<def> = V_SUB_F32_e32 %VGPR5, %VGPR0, %EXEC<imp-use>, %VGPR7_VGPR8<imp-use,kill>, %VGPR7_VGPR8<imp-def>
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 0; mem:LD16[%39](align=8)(tbaa=!"const")
	%SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 0; mem:LD32[%36](tbaa=!"const")
	S_WAITCNT 127
	%VGPR9_VGPR10_VGPR11<def> = IMAGE_SAMPLE_V3_V2 7, 0, 0, 0, 0, 0, 0, 0, %VGPR7_VGPR8, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23, %SGPR12_SGPR13_SGPR14_SGPR15, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 7; mem:LD4[<unknown>]
	S_WAITCNT 112
	%VGPR4<def> = V_MUL_F32_e32 %SGPR0, %VGPR1, %EXEC<imp-use>
	%VGPR3<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%VGPR13<def> = V_SUB_F32_e32 %VGPR3<kill>, %VGPR4, %EXEC<imp-use>, %VGPR12_VGPR13<imp-def>
	%VGPR15<def> = V_SUB_F32_e32 %VGPR13, %VGPR4, %EXEC<imp-use>, %VGPR14_VGPR15<imp-def>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 6; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR0, %VGPR0, %EXEC<imp-use>
	%VGPR2<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_SUB_F32_e32 %VGPR2<kill>, %VGPR3, %EXEC<imp-use>, %VGPR12_VGPR13<imp-use,kill>, %VGPR12_VGPR13<imp-def>
	%VGPR14<def> = V_SUB_F32_e32 %VGPR12, %VGPR3, %EXEC<imp-use>, %VGPR14_VGPR15<imp-use,kill>, %VGPR14_VGPR15<imp-def>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 4; mem:LD16[%45](align=8)(tbaa=!"const")
	%SGPR24_SGPR25_SGPR26_SGPR27_SGPR28_SGPR29_SGPR30_SGPR31<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 8; mem:LD32[%42](tbaa=!"const")
	S_WAITCNT 127
	%VGPR2<def> = IMAGE_SAMPLE_V1_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR14_VGPR15, %SGPR24_SGPR25_SGPR26_SGPR27_SGPR28_SGPR29_SGPR30_SGPR31, %SGPR0_SGPR1_SGPR2_SGPR3, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR2<def> = V_ADD_F32_e64 %VGPR2<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 2; mem:LD4[<unknown>]
	S_WAITCNT 127
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %VGPR2<kill>, %SGPR4, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR2<def> = V_CNDMASK_B32_e64 0, -1, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR2<def> = V_AND_B32_e32 1065353216, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR16<def> = V_MUL_F32_e32 %VGPR10, %VGPR2, %EXEC<imp-use>
	%VGPR16<def> = V_MUL_F32_e32 9.500000e-01, %VGPR16<kill>, %EXEC<imp-use>
	%VGPR17_VGPR18_VGPR19<def> = IMAGE_SAMPLE_V3_V2 7, 0, 0, 0, 0, 0, 0, 0, %VGPR5_VGPR6<kill>, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23, %SGPR12_SGPR13_SGPR14_SGPR15, %EXEC<imp-use>
	%VGPR5<def> = IMAGE_SAMPLE_V1_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR12_VGPR13<kill>, %SGPR24_SGPR25_SGPR26_SGPR27_SGPR28_SGPR29_SGPR30_SGPR31, %SGPR0_SGPR1_SGPR2_SGPR3, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR5<def> = V_ADD_F32_e64 %VGPR5<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %VGPR5<kill>, %SGPR4, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_CNDMASK_B32_e64 0, -1, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_AND_B32_e32 1065353216, %VGPR5<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR18, %VGPR5, %VGPR16<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_SUB_F32_e32 %VGPR8, %VGPR1, %EXEC<imp-use>, %VGPR12_VGPR13<imp-def>
	%VGPR12<def> = V_SUB_F32_e32 %VGPR7, %VGPR0, %EXEC<imp-use>, %VGPR7_VGPR8<imp-use,kill>, %VGPR12_VGPR13<imp-use,kill>, %VGPR12_VGPR13<imp-def>
	%VGPR20_VGPR21_VGPR22<def> = IMAGE_SAMPLE_V3_V2 7, 0, 0, 0, 0, 0, 0, 0, %VGPR12_VGPR13, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23, %SGPR12_SGPR13_SGPR14_SGPR15, %EXEC<imp-use>
	%VGPR8<def> = V_SUB_F32_e32 %VGPR15, %VGPR4, %EXEC<imp-use>, %VGPR7_VGPR8<imp-def>
	%VGPR7<def> = V_SUB_F32_e32 %VGPR14, %VGPR3, %EXEC<imp-use>, %VGPR14_VGPR15<imp-use,kill>, %VGPR7_VGPR8<imp-use,kill>, %VGPR7_VGPR8<imp-def>
	%VGPR14<def> = IMAGE_SAMPLE_V1_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR7_VGPR8, %SGPR24_SGPR25_SGPR26_SGPR27_SGPR28_SGPR29_SGPR30_SGPR31, %SGPR0_SGPR1_SGPR2_SGPR3, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR14<def> = V_ADD_F32_e64 %VGPR14<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %VGPR14<kill>, %SGPR4, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR14<def> = V_CNDMASK_B32_e64 0, -1, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR14<def> = V_AND_B32_e32 1065353216, %VGPR14<kill>, %EXEC<imp-use>
	%VGPR15<def> = V_MUL_F32_e32 %VGPR21, %VGPR14, %EXEC<imp-use>
	%VGPR16<def> = V_MOV_B32_e32 9.025000e-01, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR15<kill>, %VGPR16, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_SUB_F32_e32 %VGPR13, %VGPR1, %EXEC<imp-use>, %VGPR23_VGPR24<imp-def>
	%VGPR23<def> = V_SUB_F32_e32 %VGPR12, %VGPR0, %EXEC<imp-use>, %VGPR12_VGPR13<imp-use,kill>, %VGPR23_VGPR24<imp-use,kill>, %VGPR23_VGPR24<imp-def>
	%VGPR25_VGPR26_VGPR27<def> = IMAGE_SAMPLE_V3_V2 7, 0, 0, 0, 0, 0, 0, 0, %VGPR23_VGPR24, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23, %SGPR12_SGPR13_SGPR14_SGPR15, %EXEC<imp-use>
	%VGPR13<def> = V_SUB_F32_e32 %VGPR8, %VGPR4, %EXEC<imp-use>, %VGPR12_VGPR13<imp-def>
	%VGPR12<def> = V_SUB_F32_e32 %VGPR7, %VGPR3, %EXEC<imp-use>, %VGPR7_VGPR8<imp-use,kill>, %VGPR12_VGPR13<imp-use,kill>, %VGPR12_VGPR13<imp-def>
	%VGPR7<def> = IMAGE_SAMPLE_V1_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR12_VGPR13, %SGPR24_SGPR25_SGPR26_SGPR27_SGPR28_SGPR29_SGPR30_SGPR31, %SGPR0_SGPR1_SGPR2_SGPR3, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR7<def> = V_ADD_F32_e64 %VGPR7<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %VGPR7<kill>, %SGPR4, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_CNDMASK_B32_e64 0, -1, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_AND_B32_e32 1065353216, %VGPR7<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_F32_e32 %VGPR26, %VGPR7, %EXEC<imp-use>
	%VGPR15<def> = V_MOV_B32_e32 8.573750e-01, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR8<kill>, %VGPR15, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR29<def> = V_SUB_F32_e32 %VGPR24, %VGPR1, %EXEC<imp-use>, %VGPR28_VGPR29<imp-def>
	%VGPR28<def> = V_SUB_F32_e32 %VGPR23, %VGPR0, %EXEC<imp-use>, %VGPR23_VGPR24<imp-use,kill>, %VGPR28_VGPR29<imp-use,kill>, %VGPR28_VGPR29<imp-def>
	%VGPR30_VGPR31_VGPR32<def> = IMAGE_SAMPLE_V3_V2 7, 0, 0, 0, 0, 0, 0, 0, %VGPR28_VGPR29, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23, %SGPR12_SGPR13_SGPR14_SGPR15, %EXEC<imp-use>
	%VGPR24<def> = V_SUB_F32_e32 %VGPR13, %VGPR4, %EXEC<imp-use>, %VGPR23_VGPR24<imp-def>
	%VGPR23<def> = V_SUB_F32_e32 %VGPR12, %VGPR3, %EXEC<imp-use>, %VGPR12_VGPR13<imp-use,kill>, %VGPR23_VGPR24<imp-use,kill>, %VGPR23_VGPR24<imp-def>
	%VGPR8<def> = IMAGE_SAMPLE_V1_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR23_VGPR24, %SGPR24_SGPR25_SGPR26_SGPR27_SGPR28_SGPR29_SGPR30_SGPR31, %SGPR0_SGPR1_SGPR2_SGPR3, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR8<def> = V_ADD_F32_e64 %VGPR8<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %VGPR8<kill>, %SGPR4, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_CNDMASK_B32_e64 0, -1, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_AND_B32_e32 1065353216, %VGPR8<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_MUL_F32_e32 %VGPR31, %VGPR8, %EXEC<imp-use>
	%VGPR13<def> = V_MOV_B32_e32 8.145062e-01, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR12<kill>, %VGPR13, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR34<def> = V_SUB_F32_e32 %VGPR29, %VGPR1, %EXEC<imp-use>, %VGPR33_VGPR34<imp-def>
	%VGPR33<def> = V_SUB_F32_e32 %VGPR28, %VGPR0, %EXEC<imp-use>, %VGPR28_VGPR29<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR35_VGPR36_VGPR37<def> = IMAGE_SAMPLE_V3_V2 7, 0, 0, 0, 0, 0, 0, 0, %VGPR33_VGPR34, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23, %SGPR12_SGPR13_SGPR14_SGPR15, %EXEC<imp-use>
	%VGPR29<def> = V_SUB_F32_e32 %VGPR24, %VGPR4, %EXEC<imp-use>, %VGPR28_VGPR29<imp-def>
	%VGPR28<def> = V_SUB_F32_e32 %VGPR23, %VGPR3, %EXEC<imp-use>, %VGPR23_VGPR24<imp-use,kill>, %VGPR28_VGPR29<imp-use,kill>, %VGPR28_VGPR29<imp-def>
	%VGPR12<def> = IMAGE_SAMPLE_V1_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR28_VGPR29, %SGPR24_SGPR25_SGPR26_SGPR27_SGPR28_SGPR29_SGPR30_SGPR31, %SGPR0_SGPR1_SGPR2_SGPR3, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR12<def> = V_ADD_F32_e64 %VGPR12<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %VGPR12<kill>, %SGPR4, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_CNDMASK_B32_e64 0, -1, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_AND_B32_e32 1065353216, %VGPR12<kill>, %EXEC<imp-use>
	%VGPR23<def> = V_MUL_F32_e32 %VGPR36, %VGPR12, %EXEC<imp-use>
	%VGPR24<def> = V_MOV_B32_e32 7.737809e-01, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR23<kill>, %VGPR24, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR39<def> = V_SUB_F32_e32 %VGPR34, %VGPR1, %EXEC<imp-use>, %VGPR38_VGPR39<imp-def>
	%VGPR38<def> = V_SUB_F32_e32 %VGPR33, %VGPR0, %EXEC<imp-use>, %VGPR33_VGPR34<imp-use,kill>, %VGPR38_VGPR39<imp-use,kill>, %VGPR38_VGPR39<imp-def>
	%VGPR40_VGPR41_VGPR42<def> = IMAGE_SAMPLE_V3_V2 7, 0, 0, 0, 0, 0, 0, 0, %VGPR38_VGPR39, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23, %SGPR12_SGPR13_SGPR14_SGPR15, %EXEC<imp-use>
	%VGPR34<def> = V_SUB_F32_e32 %VGPR29, %VGPR4, %EXEC<imp-use>, %VGPR33_VGPR34<imp-def>
	%VGPR33<def> = V_SUB_F32_e32 %VGPR28, %VGPR3, %EXEC<imp-use>, %VGPR28_VGPR29<imp-use,kill>, %VGPR33_VGPR34<imp-use,kill>, %VGPR33_VGPR34<imp-def>
	%VGPR23<def> = IMAGE_SAMPLE_V1_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR33_VGPR34, %SGPR24_SGPR25_SGPR26_SGPR27_SGPR28_SGPR29_SGPR30_SGPR31, %SGPR0_SGPR1_SGPR2_SGPR3, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR23<def> = V_ADD_F32_e64 %VGPR23<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %VGPR23<kill>, %SGPR4, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR23<def> = V_CNDMASK_B32_e64 0, -1, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR23<def> = V_AND_B32_e32 1065353216, %VGPR23<kill>, %EXEC<imp-use>
	%VGPR28<def> = V_MUL_F32_e32 %VGPR41, %VGPR23, %EXEC<imp-use>
	%VGPR29<def> = V_MOV_B32_e32 7.350918e-01, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR28<kill>, %VGPR29, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR44<def> = V_SUB_F32_e32 %VGPR39, %VGPR1, %EXEC<imp-use>, %VGPR43_VGPR44<imp-def>
	%VGPR43<def> = V_SUB_F32_e32 %VGPR38, %VGPR0, %EXEC<imp-use>, %VGPR38_VGPR39<imp-use,kill>, %VGPR43_VGPR44<imp-use,kill>, %VGPR43_VGPR44<imp-def>
	%VGPR45_VGPR46_VGPR47<def> = IMAGE_SAMPLE_V3_V2 7, 0, 0, 0, 0, 0, 0, 0, %VGPR43_VGPR44, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23, %SGPR12_SGPR13_SGPR14_SGPR15, %EXEC<imp-use>
	%VGPR39<def> = V_SUB_F32_e32 %VGPR34, %VGPR4, %EXEC<imp-use>, %VGPR38_VGPR39<imp-def>
	%VGPR38<def> = V_SUB_F32_e32 %VGPR33, %VGPR3, %EXEC<imp-use>, %VGPR33_VGPR34<imp-use,kill>, %VGPR38_VGPR39<imp-use,kill>, %VGPR38_VGPR39<imp-def>
	%VGPR28<def> = IMAGE_SAMPLE_V1_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR38_VGPR39, %SGPR24_SGPR25_SGPR26_SGPR27_SGPR28_SGPR29_SGPR30_SGPR31, %SGPR0_SGPR1_SGPR2_SGPR3, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR28<def> = V_ADD_F32_e64 %VGPR28<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %VGPR28<kill>, %SGPR4, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR28<def> = V_CNDMASK_B32_e64 0, -1, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR28<def> = V_AND_B32_e32 1065353216, %VGPR28<kill>, %EXEC<imp-use>
	%VGPR33<def> = V_MUL_F32_e32 %VGPR46, %VGPR28, %EXEC<imp-use>
	%VGPR34<def> = V_MOV_B32_e32 6.983372e-01, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR33<kill>, %VGPR34, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR49<def> = V_SUB_F32_e32 %VGPR44, %VGPR1, %EXEC<imp-use>, %VGPR48_VGPR49<imp-def>
	%VGPR48<def> = V_SUB_F32_e32 %VGPR43, %VGPR0, %EXEC<imp-use>, %VGPR43_VGPR44<imp-use,kill>, %VGPR48_VGPR49<imp-use,kill>, %VGPR48_VGPR49<imp-def>
	%VGPR50_VGPR51_VGPR52<def> = IMAGE_SAMPLE_V3_V2 7, 0, 0, 0, 0, 0, 0, 0, %VGPR48_VGPR49, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23, %SGPR12_SGPR13_SGPR14_SGPR15, %EXEC<imp-use>
	%VGPR44<def> = V_SUB_F32_e32 %VGPR39, %VGPR4, %EXEC<imp-use>, %VGPR43_VGPR44<imp-def>
	%VGPR43<def> = V_SUB_F32_e32 %VGPR38, %VGPR3, %EXEC<imp-use>, %VGPR38_VGPR39<imp-use,kill>, %VGPR43_VGPR44<imp-use,kill>, %VGPR43_VGPR44<imp-def>
	%VGPR33<def> = IMAGE_SAMPLE_V1_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR43_VGPR44, %SGPR24_SGPR25_SGPR26_SGPR27_SGPR28_SGPR29_SGPR30_SGPR31, %SGPR0_SGPR1_SGPR2_SGPR3, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR33<def> = V_ADD_F32_e64 %VGPR33<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %VGPR33<kill>, %SGPR4, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR33<def> = V_CNDMASK_B32_e64 0, -1, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR33<def> = V_AND_B32_e32 1065353216, %VGPR33<kill>, %EXEC<imp-use>
	%VGPR38<def> = V_MUL_F32_e32 %VGPR51, %VGPR33, %EXEC<imp-use>
	%VGPR39<def> = V_MOV_B32_e32 6.634203e-01, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR38<kill>, %VGPR39, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR54<def> = V_SUB_F32_e32 %VGPR49, %VGPR1, %EXEC<imp-use>, %VGPR53_VGPR54<imp-def>
	%VGPR53<def> = V_SUB_F32_e32 %VGPR48, %VGPR0, %EXEC<imp-use>, %VGPR48_VGPR49<imp-use,kill>, %VGPR53_VGPR54<imp-use,kill>, %VGPR53_VGPR54<imp-def>
	%VGPR55_VGPR56_VGPR57<def> = IMAGE_SAMPLE_V3_V2 7, 0, 0, 0, 0, 0, 0, 0, %VGPR53_VGPR54, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23, %SGPR12_SGPR13_SGPR14_SGPR15, %EXEC<imp-use>
	%VGPR49<def> = V_SUB_F32_e32 %VGPR44, %VGPR4, %EXEC<imp-use>, %VGPR48_VGPR49<imp-def>
	%VGPR48<def> = V_SUB_F32_e32 %VGPR43, %VGPR3, %EXEC<imp-use>, %VGPR43_VGPR44<imp-use,kill>, %VGPR48_VGPR49<imp-use,kill>, %VGPR48_VGPR49<imp-def>
	%VGPR38<def> = IMAGE_SAMPLE_V1_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR48_VGPR49, %SGPR24_SGPR25_SGPR26_SGPR27_SGPR28_SGPR29_SGPR30_SGPR31, %SGPR0_SGPR1_SGPR2_SGPR3, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR38<def> = V_ADD_F32_e64 %VGPR38<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %VGPR38<kill>, %SGPR4, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR38<def> = V_CNDMASK_B32_e64 0, -1, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR38<def> = V_AND_B32_e32 1065353216, %VGPR38<kill>, %EXEC<imp-use>
	%VGPR43<def> = V_MUL_F32_e32 %VGPR56, %VGPR38, %EXEC<imp-use>
	%VGPR44<def> = V_MOV_B32_e32 6.302493e-01, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR43<kill>, %VGPR44, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR59<def> = V_SUB_F32_e32 %VGPR54, %VGPR1, %EXEC<imp-use>, %VGPR58_VGPR59<imp-def>
	%VGPR58<def> = V_SUB_F32_e32 %VGPR53, %VGPR0, %EXEC<imp-use>, %VGPR53_VGPR54<imp-use,kill>, %VGPR58_VGPR59<imp-use,kill>, %VGPR58_VGPR59<imp-def>
	%VGPR60_VGPR61_VGPR62<def> = IMAGE_SAMPLE_V3_V2 7, 0, 0, 0, 0, 0, 0, 0, %VGPR58_VGPR59, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23, %SGPR12_SGPR13_SGPR14_SGPR15, %EXEC<imp-use>
	%VGPR54<def> = V_SUB_F32_e32 %VGPR49, %VGPR4, %EXEC<imp-use>, %VGPR53_VGPR54<imp-def>
	%VGPR53<def> = V_SUB_F32_e32 %VGPR48, %VGPR3, %EXEC<imp-use>, %VGPR48_VGPR49<imp-use,kill>, %VGPR53_VGPR54<imp-use,kill>, %VGPR53_VGPR54<imp-def>
	%VGPR43<def> = IMAGE_SAMPLE_V1_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR53_VGPR54, %SGPR24_SGPR25_SGPR26_SGPR27_SGPR28_SGPR29_SGPR30_SGPR31, %SGPR0_SGPR1_SGPR2_SGPR3, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR43<def> = V_ADD_F32_e64 %VGPR43<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %VGPR43<kill>, %SGPR4, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR43<def> = V_CNDMASK_B32_e64 0, -1, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR43<def> = V_AND_B32_e32 1065353216, %VGPR43<kill>, %EXEC<imp-use>
	%VGPR48<def> = V_MUL_F32_e32 %VGPR61, %VGPR43, %EXEC<imp-use>
	%VGPR49<def> = V_MOV_B32_e32 5.987368e-01, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR48<kill>, %VGPR49, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR64<def> = V_SUB_F32_e32 %VGPR59, %VGPR1, %EXEC<imp-use>, %VGPR63_VGPR64<imp-def>
	%VGPR63<def> = V_SUB_F32_e32 %VGPR58, %VGPR0, %EXEC<imp-use>, %VGPR58_VGPR59<imp-use,kill>, %VGPR63_VGPR64<imp-use,kill>, %VGPR63_VGPR64<imp-def>
	%VGPR65_VGPR66_VGPR67<def> = IMAGE_SAMPLE_V3_V2 7, 0, 0, 0, 0, 0, 0, 0, %VGPR63_VGPR64, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23, %SGPR12_SGPR13_SGPR14_SGPR15, %EXEC<imp-use>
	%VGPR59<def> = V_SUB_F32_e32 %VGPR54, %VGPR4, %EXEC<imp-use>, %VGPR58_VGPR59<imp-def>
	%VGPR58<def> = V_SUB_F32_e32 %VGPR53, %VGPR3, %EXEC<imp-use>, %VGPR53_VGPR54<imp-use,kill>, %VGPR58_VGPR59<imp-use,kill>, %VGPR58_VGPR59<imp-def>
	%VGPR48<def> = IMAGE_SAMPLE_V1_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR58_VGPR59, %SGPR24_SGPR25_SGPR26_SGPR27_SGPR28_SGPR29_SGPR30_SGPR31, %SGPR0_SGPR1_SGPR2_SGPR3, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR48<def> = V_ADD_F32_e64 %VGPR48<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %VGPR48<kill>, %SGPR4, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR48<def> = V_CNDMASK_B32_e64 0, -1, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR48<def> = V_AND_B32_e32 1065353216, %VGPR48<kill>, %EXEC<imp-use>
	%VGPR53<def> = V_MUL_F32_e32 %VGPR66, %VGPR48, %EXEC<imp-use>
	%VGPR54<def> = V_MOV_B32_e32 5.688000e-01, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR53<kill>, %VGPR54, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR69<def> = V_SUB_F32_e32 %VGPR64, %VGPR1, %EXEC<imp-use>, %VGPR68_VGPR69<imp-def>
	%VGPR68<def> = V_SUB_F32_e32 %VGPR63, %VGPR0, %EXEC<imp-use>, %VGPR63_VGPR64<imp-use,kill>, %VGPR68_VGPR69<imp-use,kill>, %VGPR68_VGPR69<imp-def>
	%VGPR70_VGPR71_VGPR72<def> = IMAGE_SAMPLE_V3_V2 7, 0, 0, 0, 0, 0, 0, 0, %VGPR68_VGPR69, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23, %SGPR12_SGPR13_SGPR14_SGPR15, %EXEC<imp-use>
	%VGPR64<def> = V_SUB_F32_e32 %VGPR59, %VGPR4, %EXEC<imp-use>, %VGPR63_VGPR64<imp-def>
	%VGPR63<def> = V_SUB_F32_e32 %VGPR58, %VGPR3, %EXEC<imp-use>, %VGPR58_VGPR59<imp-use,kill>, %VGPR63_VGPR64<imp-use,kill>, %VGPR63_VGPR64<imp-def>
	%VGPR53<def> = IMAGE_SAMPLE_V1_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR63_VGPR64, %SGPR24_SGPR25_SGPR26_SGPR27_SGPR28_SGPR29_SGPR30_SGPR31, %SGPR0_SGPR1_SGPR2_SGPR3, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR53<def> = V_ADD_F32_e64 %VGPR53<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %VGPR53<kill>, %SGPR4, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR53<def> = V_CNDMASK_B32_e64 0, -1, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR53<def> = V_AND_B32_e32 1065353216, %VGPR53<kill>, %EXEC<imp-use>
	%VGPR58<def> = V_MUL_F32_e32 %VGPR71, %VGPR53, %EXEC<imp-use>
	%VGPR59<def> = V_MOV_B32_e32 5.403600e-01, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR58<kill>, %VGPR59, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR74<def> = V_SUB_F32_e32 %VGPR69, %VGPR1, %EXEC<imp-use>, %VGPR73_VGPR74<imp-def>
	%VGPR73<def> = V_SUB_F32_e32 %VGPR68, %VGPR0, %EXEC<imp-use>, %VGPR68_VGPR69<imp-use,kill>, %VGPR73_VGPR74<imp-use,kill>, %VGPR73_VGPR74<imp-def>
	%VGPR75_VGPR76_VGPR77<def> = IMAGE_SAMPLE_V3_V2 7, 0, 0, 0, 0, 0, 0, 0, %VGPR73_VGPR74, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23, %SGPR12_SGPR13_SGPR14_SGPR15, %EXEC<imp-use>
	%VGPR69<def> = V_SUB_F32_e32 %VGPR64, %VGPR4, %EXEC<imp-use>, %VGPR68_VGPR69<imp-def>
	%VGPR68<def> = V_SUB_F32_e32 %VGPR63, %VGPR3, %EXEC<imp-use>, %VGPR63_VGPR64<imp-use,kill>, %VGPR68_VGPR69<imp-use,kill>, %VGPR68_VGPR69<imp-def>
	%VGPR58<def> = IMAGE_SAMPLE_V1_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR68_VGPR69, %SGPR24_SGPR25_SGPR26_SGPR27_SGPR28_SGPR29_SGPR30_SGPR31, %SGPR0_SGPR1_SGPR2_SGPR3, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR58<def> = V_ADD_F32_e64 %VGPR58<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %VGPR58<kill>, %SGPR4, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR58<def> = V_CNDMASK_B32_e64 0, -1, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR58<def> = V_AND_B32_e32 1065353216, %VGPR58<kill>, %EXEC<imp-use>
	%VGPR63<def> = V_MUL_F32_e32 %VGPR76, %VGPR58, %EXEC<imp-use>
	%VGPR64<def> = V_MOV_B32_e32 5.133420e-01, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR63<kill>, %VGPR64, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR79<def> = V_SUB_F32_e32 %VGPR74, %VGPR1, %EXEC<imp-use>, %VGPR78_VGPR79<imp-def>
	%VGPR78<def> = V_SUB_F32_e32 %VGPR73, %VGPR0, %EXEC<imp-use>, %VGPR73_VGPR74<imp-use,kill>, %VGPR78_VGPR79<imp-use,kill>, %VGPR78_VGPR79<imp-def>
	%VGPR80_VGPR81_VGPR82<def> = IMAGE_SAMPLE_V3_V2 7, 0, 0, 0, 0, 0, 0, 0, %VGPR78_VGPR79, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23, %SGPR12_SGPR13_SGPR14_SGPR15, %EXEC<imp-use>
	%VGPR74<def> = V_SUB_F32_e32 %VGPR69, %VGPR4, %EXEC<imp-use>, %VGPR73_VGPR74<imp-def>
	%VGPR73<def> = V_SUB_F32_e32 %VGPR68, %VGPR3, %EXEC<imp-use>, %VGPR68_VGPR69<imp-use,kill>, %VGPR73_VGPR74<imp-use,kill>, %VGPR73_VGPR74<imp-def>
	%VGPR63<def> = IMAGE_SAMPLE_V1_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR73_VGPR74, %SGPR24_SGPR25_SGPR26_SGPR27_SGPR28_SGPR29_SGPR30_SGPR31, %SGPR0_SGPR1_SGPR2_SGPR3, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR63<def> = V_ADD_F32_e64 %VGPR63<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %VGPR63<kill>, %SGPR4, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR63<def> = V_CNDMASK_B32_e64 0, -1, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR63<def> = V_AND_B32_e32 1065353216, %VGPR63<kill>, %EXEC<imp-use>
	%VGPR68<def> = V_MUL_F32_e32 %VGPR81, %VGPR63, %EXEC<imp-use>
	%VGPR69<def> = V_MOV_B32_e32 4.876749e-01, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR68<kill>, %VGPR69, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR84<def> = V_SUB_F32_e32 %VGPR79, %VGPR1, %EXEC<imp-use>, %VGPR83_VGPR84<imp-def>
	%VGPR83<def> = V_SUB_F32_e32 %VGPR78, %VGPR0, %EXEC<imp-use>, %VGPR78_VGPR79<imp-use,kill>, %VGPR83_VGPR84<imp-use,kill>, %VGPR83_VGPR84<imp-def>
	%VGPR85_VGPR86_VGPR87<def> = IMAGE_SAMPLE_V3_V2 7, 0, 0, 0, 0, 0, 0, 0, %VGPR83_VGPR84, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23, %SGPR12_SGPR13_SGPR14_SGPR15, %EXEC<imp-use>
	%VGPR79<def> = V_SUB_F32_e32 %VGPR74, %VGPR4, %EXEC<imp-use>, %VGPR78_VGPR79<imp-def>
	%VGPR78<def> = V_SUB_F32_e32 %VGPR73, %VGPR3, %EXEC<imp-use>, %VGPR73_VGPR74<imp-use,kill>, %VGPR78_VGPR79<imp-use,kill>, %VGPR78_VGPR79<imp-def>
	%VGPR68<def> = IMAGE_SAMPLE_V1_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR78_VGPR79, %SGPR24_SGPR25_SGPR26_SGPR27_SGPR28_SGPR29_SGPR30_SGPR31, %SGPR0_SGPR1_SGPR2_SGPR3, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR68<def> = V_ADD_F32_e64 %VGPR68<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %VGPR68<kill>, %SGPR4, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR68<def> = V_CNDMASK_B32_e64 0, -1, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR68<def> = V_AND_B32_e32 1065353216, %VGPR68<kill>, %EXEC<imp-use>
	%VGPR73<def> = V_MUL_F32_e32 %VGPR86, %VGPR68, %EXEC<imp-use>
	%VGPR74<def> = V_MOV_B32_e32 4.632911e-01, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR73<kill>, %VGPR74, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR89<def> = V_SUB_F32_e32 %VGPR84, %VGPR1, %EXEC<imp-use>, %VGPR88_VGPR89<imp-def>
	%VGPR88<def> = V_SUB_F32_e32 %VGPR83, %VGPR0, %EXEC<imp-use>, %VGPR83_VGPR84<imp-use,kill>, %VGPR88_VGPR89<imp-use,kill>, %VGPR88_VGPR89<imp-def>
	%VGPR90_VGPR91_VGPR92<def> = IMAGE_SAMPLE_V3_V2 7, 0, 0, 0, 0, 0, 0, 0, %VGPR88_VGPR89, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23, %SGPR12_SGPR13_SGPR14_SGPR15, %EXEC<imp-use>
	%VGPR84<def> = V_SUB_F32_e32 %VGPR79, %VGPR4, %EXEC<imp-use>, %VGPR83_VGPR84<imp-def>
	%VGPR83<def> = V_SUB_F32_e32 %VGPR78, %VGPR3, %EXEC<imp-use>, %VGPR78_VGPR79<imp-use,kill>, %VGPR83_VGPR84<imp-use,kill>, %VGPR83_VGPR84<imp-def>
	%VGPR73<def> = IMAGE_SAMPLE_V1_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR83_VGPR84, %SGPR24_SGPR25_SGPR26_SGPR27_SGPR28_SGPR29_SGPR30_SGPR31, %SGPR0_SGPR1_SGPR2_SGPR3, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR73<def> = V_ADD_F32_e64 %VGPR73<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %VGPR73<kill>, %SGPR4, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR73<def> = V_CNDMASK_B32_e64 0, -1, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR73<def> = V_AND_B32_e32 1065353216, %VGPR73<kill>, %EXEC<imp-use>
	%VGPR78<def> = V_MUL_F32_e32 %VGPR91, %VGPR73, %EXEC<imp-use>
	%VGPR79<def> = V_MOV_B32_e32 4.401265e-01, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR78<kill>, %VGPR79, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR94<def> = V_SUB_F32_e32 %VGPR89, %VGPR1, %EXEC<imp-use>, %VGPR93_VGPR94<imp-def>
	%VGPR93<def> = V_SUB_F32_e32 %VGPR88, %VGPR0, %EXEC<imp-use>, %VGPR88_VGPR89<imp-use,kill>, %VGPR93_VGPR94<imp-use,kill>, %VGPR93_VGPR94<imp-def>
	%VGPR95_VGPR96_VGPR97<def> = IMAGE_SAMPLE_V3_V2 7, 0, 0, 0, 0, 0, 0, 0, %VGPR93_VGPR94, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23, %SGPR12_SGPR13_SGPR14_SGPR15, %EXEC<imp-use>
	%VGPR89<def> = V_SUB_F32_e32 %VGPR84, %VGPR4, %EXEC<imp-use>, %VGPR88_VGPR89<imp-def>
	%VGPR88<def> = V_SUB_F32_e32 %VGPR83, %VGPR3, %EXEC<imp-use>, %VGPR83_VGPR84<imp-use,kill>, %VGPR88_VGPR89<imp-use,kill>, %VGPR88_VGPR89<imp-def>
	%VGPR78<def> = IMAGE_SAMPLE_V1_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR88_VGPR89, %SGPR24_SGPR25_SGPR26_SGPR27_SGPR28_SGPR29_SGPR30_SGPR31, %SGPR0_SGPR1_SGPR2_SGPR3, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR78<def> = V_ADD_F32_e64 %VGPR78<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %VGPR78<kill>, %SGPR4, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR78<def> = V_CNDMASK_B32_e64 0, -1, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR78<def> = V_AND_B32_e32 1065353216, %VGPR78<kill>, %EXEC<imp-use>
	%VGPR83<def> = V_MUL_F32_e32 %VGPR96, %VGPR78, %EXEC<imp-use>
	%VGPR84<def> = V_MOV_B32_e32 4.181202e-01, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR83<kill>, %VGPR84, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR99<def> = V_SUB_F32_e32 %VGPR94, %VGPR1, %EXEC<imp-use>, %VGPR98_VGPR99<imp-def>
	%VGPR98<def> = V_SUB_F32_e32 %VGPR93, %VGPR0, %EXEC<imp-use>, %VGPR93_VGPR94<imp-use,kill>, %VGPR98_VGPR99<imp-use,kill>, %VGPR98_VGPR99<imp-def>
	%VGPR100_VGPR101_VGPR102<def> = IMAGE_SAMPLE_V3_V2 7, 0, 0, 0, 0, 0, 0, 0, %VGPR98_VGPR99, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23, %SGPR12_SGPR13_SGPR14_SGPR15, %EXEC<imp-use>
	%VGPR94<def> = V_SUB_F32_e32 %VGPR89, %VGPR4, %EXEC<imp-use>, %VGPR93_VGPR94<imp-def>
	%VGPR93<def> = V_SUB_F32_e32 %VGPR88, %VGPR3, %EXEC<imp-use>, %VGPR88_VGPR89<imp-use,kill>, %VGPR93_VGPR94<imp-use,kill>, %VGPR93_VGPR94<imp-def>
	%VGPR83<def> = IMAGE_SAMPLE_V1_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR93_VGPR94, %SGPR24_SGPR25_SGPR26_SGPR27_SGPR28_SGPR29_SGPR30_SGPR31, %SGPR0_SGPR1_SGPR2_SGPR3, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR83<def> = V_ADD_F32_e64 %VGPR83<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %VGPR83<kill>, %SGPR4, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR83<def> = V_CNDMASK_B32_e64 0, -1, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR83<def> = V_AND_B32_e32 1065353216, %VGPR83<kill>, %EXEC<imp-use>
	%VGPR88<def> = V_MUL_F32_e32 %VGPR101, %VGPR83, %EXEC<imp-use>
	%VGPR89<def> = V_MOV_B32_e32 3.972142e-01, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR88<kill>, %VGPR89, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR104<def> = V_SUB_F32_e32 %VGPR99, %VGPR1, %EXEC<imp-use>, %VGPR103_VGPR104<imp-def>
	%VGPR103<def> = V_SUB_F32_e32 %VGPR98, %VGPR0, %EXEC<imp-use>, %VGPR98_VGPR99<imp-use,kill>, %VGPR103_VGPR104<imp-use,kill>, %VGPR103_VGPR104<imp-def>
	%VGPR105_VGPR106_VGPR107<def> = IMAGE_SAMPLE_V3_V2 7, 0, 0, 0, 0, 0, 0, 0, %VGPR103_VGPR104, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23, %SGPR12_SGPR13_SGPR14_SGPR15, %EXEC<imp-use>
	%VGPR99<def> = V_SUB_F32_e32 %VGPR94, %VGPR4, %EXEC<imp-use>, %VGPR98_VGPR99<imp-def>
	%VGPR98<def> = V_SUB_F32_e32 %VGPR93, %VGPR3, %EXEC<imp-use>, %VGPR93_VGPR94<imp-use,kill>, %VGPR98_VGPR99<imp-use,kill>, %VGPR98_VGPR99<imp-def>
	%VGPR88<def> = IMAGE_SAMPLE_V1_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR98_VGPR99, %SGPR24_SGPR25_SGPR26_SGPR27_SGPR28_SGPR29_SGPR30_SGPR31, %SGPR0_SGPR1_SGPR2_SGPR3, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR88<def> = V_ADD_F32_e64 %VGPR88<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %VGPR88<kill>, %SGPR4, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR88<def> = V_CNDMASK_B32_e64 0, -1, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR88<def> = V_AND_B32_e32 1065353216, %VGPR88<kill>, %EXEC<imp-use>
	%VGPR93<def> = V_MUL_F32_e32 %VGPR106, %VGPR88, %EXEC<imp-use>
	%VGPR94<def> = V_MOV_B32_e32 3.773535e-01, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR93<kill>, %VGPR94, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR109<def> = V_SUB_F32_e32 %VGPR104, %VGPR1, %EXEC<imp-use>, %VGPR108_VGPR109<imp-def>
	%VGPR108<def> = V_SUB_F32_e32 %VGPR103, %VGPR0, %EXEC<imp-use>, %VGPR103_VGPR104<imp-use,kill>, %VGPR108_VGPR109<imp-use,kill>, %VGPR108_VGPR109<imp-def>
	%VGPR110_VGPR111_VGPR112<def> = IMAGE_SAMPLE_V3_V2 7, 0, 0, 0, 0, 0, 0, 0, %VGPR108_VGPR109, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23, %SGPR12_SGPR13_SGPR14_SGPR15, %EXEC<imp-use>
	%VGPR104<def> = V_SUB_F32_e32 %VGPR99, %VGPR4, %EXEC<imp-use>, %VGPR103_VGPR104<imp-def>
	%VGPR103<def> = V_SUB_F32_e32 %VGPR98, %VGPR3, %EXEC<imp-use>, %VGPR98_VGPR99<imp-use,kill>, %VGPR103_VGPR104<imp-use,kill>, %VGPR103_VGPR104<imp-def>
	%VGPR93<def> = IMAGE_SAMPLE_V1_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR103_VGPR104, %SGPR24_SGPR25_SGPR26_SGPR27_SGPR28_SGPR29_SGPR30_SGPR31, %SGPR0_SGPR1_SGPR2_SGPR3, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR93<def> = V_ADD_F32_e64 %VGPR93<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %VGPR93<kill>, %SGPR4, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR93<def> = V_CNDMASK_B32_e64 0, -1, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR93<def> = V_AND_B32_e32 1065353216, %VGPR93<kill>, %EXEC<imp-use>
	%VGPR98<def> = V_MUL_F32_e32 %VGPR111, %VGPR93, %EXEC<imp-use>
	%VGPR99<def> = V_MOV_B32_e32 3.584858e-01, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR98<kill>, %VGPR99, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR114<def> = V_SUB_F32_e32 %VGPR109, %VGPR1, %EXEC<imp-use>, %VGPR113_VGPR114<imp-def>
	%VGPR113<def> = V_SUB_F32_e32 %VGPR108, %VGPR0, %EXEC<imp-use>, %VGPR108_VGPR109<imp-use,kill>, %VGPR113_VGPR114<imp-use,kill>, %VGPR113_VGPR114<imp-def>
	%VGPR115_VGPR116_VGPR117<def> = IMAGE_SAMPLE_V3_V2 7, 0, 0, 0, 0, 0, 0, 0, %VGPR113_VGPR114, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23, %SGPR12_SGPR13_SGPR14_SGPR15, %EXEC<imp-use>
	%VGPR109<def> = V_SUB_F32_e32 %VGPR104, %VGPR4, %EXEC<imp-use>, %VGPR108_VGPR109<imp-def>
	%VGPR108<def> = V_SUB_F32_e32 %VGPR103, %VGPR3, %EXEC<imp-use>, %VGPR103_VGPR104<imp-use,kill>, %VGPR108_VGPR109<imp-use,kill>, %VGPR108_VGPR109<imp-def>
	%VGPR98<def> = IMAGE_SAMPLE_V1_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR108_VGPR109, %SGPR24_SGPR25_SGPR26_SGPR27_SGPR28_SGPR29_SGPR30_SGPR31, %SGPR0_SGPR1_SGPR2_SGPR3, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR98<def> = V_ADD_F32_e64 %VGPR98<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %VGPR98<kill>, %SGPR4, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR98<def> = V_CNDMASK_B32_e64 0, -1, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR98<def> = V_AND_B32_e32 1065353216, %VGPR98<kill>, %EXEC<imp-use>
	%VGPR103<def> = V_MUL_F32_e32 %VGPR116, %VGPR98, %EXEC<imp-use>
	%VGPR104<def> = V_MOV_B32_e32 3.405615e-01, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR103<kill>, %VGPR104, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR119<def> = V_SUB_F32_e32 %VGPR114, %VGPR1, %EXEC<imp-use>, %VGPR118_VGPR119<imp-def>
	%VGPR118<def> = V_SUB_F32_e32 %VGPR113, %VGPR0, %EXEC<imp-use>, %VGPR113_VGPR114<imp-use,kill>, %VGPR118_VGPR119<imp-use,kill>, %VGPR118_VGPR119<imp-def>
	%VGPR120_VGPR121_VGPR122<def> = IMAGE_SAMPLE_V3_V2 7, 0, 0, 0, 0, 0, 0, 0, %VGPR118_VGPR119, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23, %SGPR12_SGPR13_SGPR14_SGPR15, %EXEC<imp-use>
	%VGPR114<def> = V_SUB_F32_e32 %VGPR109, %VGPR4, %EXEC<imp-use>, %VGPR113_VGPR114<imp-def>
	%VGPR113<def> = V_SUB_F32_e32 %VGPR108, %VGPR3, %EXEC<imp-use>, %VGPR108_VGPR109<imp-use,kill>, %VGPR113_VGPR114<imp-use,kill>, %VGPR113_VGPR114<imp-def>
	%VGPR103<def> = IMAGE_SAMPLE_V1_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR113_VGPR114, %SGPR24_SGPR25_SGPR26_SGPR27_SGPR28_SGPR29_SGPR30_SGPR31, %SGPR0_SGPR1_SGPR2_SGPR3, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR103<def> = V_ADD_F32_e64 %VGPR103<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %VGPR103<kill>, %SGPR4, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR103<def> = V_CNDMASK_B32_e64 0, -1, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR103<def> = V_AND_B32_e32 1065353216, %VGPR103<kill>, %EXEC<imp-use>
	%VGPR108<def> = V_MUL_F32_e32 %VGPR121, %VGPR103, %EXEC<imp-use>
	%VGPR109<def> = V_MOV_B32_e32 3.235334e-01, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR108<kill>, %VGPR109, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR124<def> = V_SUB_F32_e32 %VGPR119, %VGPR1, %EXEC<imp-use>, %VGPR123_VGPR124<imp-def>
	%VGPR123<def> = V_SUB_F32_e32 %VGPR118, %VGPR0, %EXEC<imp-use>, %VGPR118_VGPR119<imp-use,kill>, %VGPR123_VGPR124<imp-use,kill>, %VGPR123_VGPR124<imp-def>
	%VGPR125_VGPR126_VGPR127<def> = IMAGE_SAMPLE_V3_V2 7, 0, 0, 0, 0, 0, 0, 0, %VGPR123_VGPR124, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23, %SGPR12_SGPR13_SGPR14_SGPR15, %EXEC<imp-use>
	%VGPR119<def> = V_SUB_F32_e32 %VGPR114, %VGPR4, %EXEC<imp-use>, %VGPR118_VGPR119<imp-def>
	%VGPR118<def> = V_SUB_F32_e32 %VGPR113, %VGPR3, %EXEC<imp-use>, %VGPR113_VGPR114<imp-use,kill>, %VGPR118_VGPR119<imp-use,kill>, %VGPR118_VGPR119<imp-def>
	%VGPR108<def> = IMAGE_SAMPLE_V1_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR118_VGPR119, %SGPR24_SGPR25_SGPR26_SGPR27_SGPR28_SGPR29_SGPR30_SGPR31, %SGPR0_SGPR1_SGPR2_SGPR3, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR108<def> = V_ADD_F32_e64 %VGPR108<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %VGPR108<kill>, %SGPR4, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR108<def> = V_CNDMASK_B32_e64 0, -1, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR108<def> = V_AND_B32_e32 1065353216, %VGPR108<kill>, %EXEC<imp-use>
	%VGPR113<def> = V_MUL_F32_e32 %VGPR126, %VGPR108, %EXEC<imp-use>
	%VGPR114<def> = V_MOV_B32_e32 3.073567e-01, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR113<kill>, %VGPR114, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR129<def> = V_SUB_F32_e32 %VGPR124, %VGPR1, %EXEC<imp-use>, %VGPR128_VGPR129<imp-def>
	%VGPR128<def> = V_SUB_F32_e32 %VGPR123, %VGPR0, %EXEC<imp-use>, %VGPR123_VGPR124<imp-use,kill>, %VGPR128_VGPR129<imp-use,kill>, %VGPR128_VGPR129<imp-def>
	%VGPR130_VGPR131_VGPR132<def> = IMAGE_SAMPLE_V3_V2 7, 0, 0, 0, 0, 0, 0, 0, %VGPR128_VGPR129, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23, %SGPR12_SGPR13_SGPR14_SGPR15, %EXEC<imp-use>
	%VGPR124<def> = V_SUB_F32_e32 %VGPR119, %VGPR4, %EXEC<imp-use>, %VGPR123_VGPR124<imp-def>
	%VGPR123<def> = V_SUB_F32_e32 %VGPR118, %VGPR3, %EXEC<imp-use>, %VGPR118_VGPR119<imp-use,kill>, %VGPR123_VGPR124<imp-use,kill>, %VGPR123_VGPR124<imp-def>
	%VGPR113<def> = IMAGE_SAMPLE_V1_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR123_VGPR124, %SGPR24_SGPR25_SGPR26_SGPR27_SGPR28_SGPR29_SGPR30_SGPR31, %SGPR0_SGPR1_SGPR2_SGPR3, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR113<def> = V_ADD_F32_e64 %VGPR113<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %VGPR113<kill>, %SGPR4, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR113<def> = V_CNDMASK_B32_e64 0, -1, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR113<def> = V_AND_B32_e32 1065353216, %VGPR113<kill>, %EXEC<imp-use>
	%VGPR118<def> = V_MUL_F32_e32 %VGPR131, %VGPR113, %EXEC<imp-use>
	%VGPR119<def> = V_MOV_B32_e32 2.919889e-01, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR118<kill>, %VGPR119, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR134<def> = V_SUB_F32_e32 %VGPR129, %VGPR1, %EXEC<imp-use>, %VGPR133_VGPR134<imp-def>
	%VGPR133<def> = V_SUB_F32_e32 %VGPR128, %VGPR0, %EXEC<imp-use>, %VGPR128_VGPR129<imp-use,kill>, %VGPR133_VGPR134<imp-use,kill>, %VGPR133_VGPR134<imp-def>
	%VGPR135_VGPR136_VGPR137<def> = IMAGE_SAMPLE_V3_V2 7, 0, 0, 0, 0, 0, 0, 0, %VGPR133_VGPR134, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23, %SGPR12_SGPR13_SGPR14_SGPR15, %EXEC<imp-use>
	%VGPR129<def> = V_SUB_F32_e32 %VGPR124, %VGPR4, %EXEC<imp-use>, %VGPR128_VGPR129<imp-def>
	%VGPR128<def> = V_SUB_F32_e32 %VGPR123, %VGPR3, %EXEC<imp-use>, %VGPR123_VGPR124<imp-use,kill>, %VGPR128_VGPR129<imp-use,kill>, %VGPR128_VGPR129<imp-def>
	%VGPR118<def> = IMAGE_SAMPLE_V1_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR128_VGPR129, %SGPR24_SGPR25_SGPR26_SGPR27_SGPR28_SGPR29_SGPR30_SGPR31, %SGPR0_SGPR1_SGPR2_SGPR3, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR118<def> = V_ADD_F32_e64 %VGPR118<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %VGPR118<kill>, %SGPR4, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR118<def> = V_CNDMASK_B32_e64 0, -1, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR118<def> = V_AND_B32_e32 1065353216, %VGPR118<kill>, %EXEC<imp-use>
	%VGPR123<def> = V_MUL_F32_e32 %VGPR136, %VGPR118, %EXEC<imp-use>
	%VGPR124<def> = V_MOV_B32_e32 2.773895e-01, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR123<kill>, %VGPR124, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR139<def> = V_SUB_F32_e32 %VGPR134, %VGPR1, %EXEC<imp-use>, %VGPR138_VGPR139<imp-def>
	%VGPR138<def> = V_SUB_F32_e32 %VGPR133, %VGPR0, %EXEC<imp-use>, %VGPR133_VGPR134<imp-use,kill>, %VGPR138_VGPR139<imp-use,kill>, %VGPR138_VGPR139<imp-def>
	%VGPR140_VGPR141_VGPR142<def> = IMAGE_SAMPLE_V3_V2 7, 0, 0, 0, 0, 0, 0, 0, %VGPR138_VGPR139, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23, %SGPR12_SGPR13_SGPR14_SGPR15, %EXEC<imp-use>
	%VGPR134<def> = V_SUB_F32_e32 %VGPR129, %VGPR4, %EXEC<imp-use>, %VGPR133_VGPR134<imp-def>
	%VGPR133<def> = V_SUB_F32_e32 %VGPR128, %VGPR3, %EXEC<imp-use>, %VGPR128_VGPR129<imp-use,kill>, %VGPR133_VGPR134<imp-use,kill>, %VGPR133_VGPR134<imp-def>
	%VGPR123<def> = IMAGE_SAMPLE_V1_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR133_VGPR134, %SGPR24_SGPR25_SGPR26_SGPR27_SGPR28_SGPR29_SGPR30_SGPR31, %SGPR0_SGPR1_SGPR2_SGPR3, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR123<def> = V_ADD_F32_e64 %VGPR123<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %VGPR123<kill>, %SGPR4, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR123<def> = V_CNDMASK_B32_e64 0, -1, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR123<def> = V_AND_B32_e32 1065353216, %VGPR123<kill>, %EXEC<imp-use>
	%VGPR128<def> = V_MUL_F32_e32 %VGPR141, %VGPR123, %EXEC<imp-use>
	%VGPR129<def> = V_MOV_B32_e32 2.635200e-01, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR128<kill>, %VGPR129, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR144<def> = V_SUB_F32_e32 %VGPR139, %VGPR1, %EXEC<imp-use>, %VGPR143_VGPR144<imp-def>
	%VGPR143<def> = V_SUB_F32_e32 %VGPR138, %VGPR0, %EXEC<imp-use>, %VGPR138_VGPR139<imp-use,kill>, %VGPR143_VGPR144<imp-use,kill>, %VGPR143_VGPR144<imp-def>
	%VGPR145_VGPR146_VGPR147<def> = IMAGE_SAMPLE_V3_V2 7, 0, 0, 0, 0, 0, 0, 0, %VGPR143_VGPR144, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23, %SGPR12_SGPR13_SGPR14_SGPR15, %EXEC<imp-use>
	%VGPR139<def> = V_SUB_F32_e32 %VGPR134, %VGPR4, %EXEC<imp-use>, %VGPR138_VGPR139<imp-def>
	%VGPR138<def> = V_SUB_F32_e32 %VGPR133, %VGPR3, %EXEC<imp-use>, %VGPR133_VGPR134<imp-use,kill>, %VGPR138_VGPR139<imp-use,kill>, %VGPR138_VGPR139<imp-def>
	%VGPR128<def> = IMAGE_SAMPLE_V1_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR138_VGPR139, %SGPR24_SGPR25_SGPR26_SGPR27_SGPR28_SGPR29_SGPR30_SGPR31, %SGPR0_SGPR1_SGPR2_SGPR3, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR128<def> = V_ADD_F32_e64 %VGPR128<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %VGPR128<kill>, %SGPR4, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR128<def> = V_CNDMASK_B32_e64 0, -1, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR128<def> = V_AND_B32_e32 1065353216, %VGPR128<kill>, %EXEC<imp-use>
	%VGPR133<def> = V_MUL_F32_e32 %VGPR146, %VGPR128, %EXEC<imp-use>
	%VGPR134<def> = V_MOV_B32_e32 2.503440e-01, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR133<kill>, %VGPR134, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR149<def> = V_SUB_F32_e32 %VGPR144, %VGPR1, %EXEC<imp-use>, %VGPR148_VGPR149<imp-def>
	%VGPR148<def> = V_SUB_F32_e32 %VGPR143, %VGPR0, %EXEC<imp-use>, %VGPR143_VGPR144<imp-use,kill>, %VGPR148_VGPR149<imp-use,kill>, %VGPR148_VGPR149<imp-def>
	%VGPR150_VGPR151_VGPR152<def> = IMAGE_SAMPLE_V3_V2 7, 0, 0, 0, 0, 0, 0, 0, %VGPR148_VGPR149, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23, %SGPR12_SGPR13_SGPR14_SGPR15, %EXEC<imp-use>
	%VGPR144<def> = V_SUB_F32_e32 %VGPR139, %VGPR4, %EXEC<imp-use>, %VGPR143_VGPR144<imp-def>
	%VGPR143<def> = V_SUB_F32_e32 %VGPR138, %VGPR3, %EXEC<imp-use>, %VGPR138_VGPR139<imp-use,kill>, %VGPR143_VGPR144<imp-use,kill>, %VGPR143_VGPR144<imp-def>
	%VGPR133<def> = IMAGE_SAMPLE_V1_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR143_VGPR144, %SGPR24_SGPR25_SGPR26_SGPR27_SGPR28_SGPR29_SGPR30_SGPR31, %SGPR0_SGPR1_SGPR2_SGPR3, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR133<def> = V_ADD_F32_e64 %VGPR133<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %VGPR133<kill>, %SGPR4, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR133<def> = V_CNDMASK_B32_e64 0, -1, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR133<def> = V_AND_B32_e32 1065353216, %VGPR133<kill>, %EXEC<imp-use>
	%VGPR138<def> = V_MUL_F32_e32 %VGPR151, %VGPR133, %EXEC<imp-use>
	%VGPR139<def> = V_MOV_B32_e32 2.378268e-01, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR138<kill>, %VGPR139, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR154<def> = V_SUB_F32_e32 %VGPR149, %VGPR1, %EXEC<imp-use>, %VGPR153_VGPR154<imp-def>
	%VGPR153<def> = V_SUB_F32_e32 %VGPR148, %VGPR0, %EXEC<imp-use>, %VGPR148_VGPR149<imp-use,kill>, %VGPR153_VGPR154<imp-use,kill>, %VGPR153_VGPR154<imp-def>
	%VGPR155_VGPR156_VGPR157<def> = IMAGE_SAMPLE_V3_V2 7, 0, 0, 0, 0, 0, 0, 0, %VGPR153_VGPR154, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23, %SGPR12_SGPR13_SGPR14_SGPR15, %EXEC<imp-use>
	%VGPR149<def> = V_SUB_F32_e32 %VGPR144, %VGPR4, %EXEC<imp-use>, %VGPR148_VGPR149<imp-def>
	%VGPR148<def> = V_SUB_F32_e32 %VGPR143, %VGPR3, %EXEC<imp-use>, %VGPR143_VGPR144<imp-use,kill>, %VGPR148_VGPR149<imp-use,kill>, %VGPR148_VGPR149<imp-def>
	%VGPR138<def> = IMAGE_SAMPLE_V1_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR148_VGPR149, %SGPR24_SGPR25_SGPR26_SGPR27_SGPR28_SGPR29_SGPR30_SGPR31, %SGPR0_SGPR1_SGPR2_SGPR3, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR138<def> = V_ADD_F32_e64 %VGPR138<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %VGPR138<kill>, %SGPR4, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR138<def> = V_CNDMASK_B32_e64 0, -1, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR138<def> = V_AND_B32_e32 1065353216, %VGPR138<kill>, %EXEC<imp-use>
	%VGPR143<def> = V_MUL_F32_e32 %VGPR156, %VGPR138, %EXEC<imp-use>
	%VGPR144<def> = V_MOV_B32_e32 2.259355e-01, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR143<kill>, %VGPR144, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR159<def> = V_SUB_F32_e32 %VGPR154, %VGPR1, %EXEC<imp-use>, %VGPR158_VGPR159<imp-def>
	%VGPR158<def> = V_SUB_F32_e32 %VGPR153, %VGPR0, %EXEC<imp-use>, %VGPR153_VGPR154<imp-use,kill>, %VGPR158_VGPR159<imp-use,kill>, %VGPR158_VGPR159<imp-def>
	%VGPR160_VGPR161_VGPR162<def> = IMAGE_SAMPLE_V3_V2 7, 0, 0, 0, 0, 0, 0, 0, %VGPR158_VGPR159, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23, %SGPR12_SGPR13_SGPR14_SGPR15, %EXEC<imp-use>
	%VGPR154<def> = V_SUB_F32_e32 %VGPR149, %VGPR4, %EXEC<imp-use>, %VGPR153_VGPR154<imp-def>
	%VGPR153<def> = V_SUB_F32_e32 %VGPR148, %VGPR3, %EXEC<imp-use>, %VGPR148_VGPR149<imp-use,kill>, %VGPR153_VGPR154<imp-use,kill>, %VGPR153_VGPR154<imp-def>
	%VGPR143<def> = IMAGE_SAMPLE_V1_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR153_VGPR154, %SGPR24_SGPR25_SGPR26_SGPR27_SGPR28_SGPR29_SGPR30_SGPR31, %SGPR0_SGPR1_SGPR2_SGPR3, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR143<def> = V_ADD_F32_e64 %VGPR143<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %VGPR143<kill>, %SGPR4, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR143<def> = V_CNDMASK_B32_e64 0, -1, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR143<def> = V_AND_B32_e32 1065353216, %VGPR143<kill>, %EXEC<imp-use>
	%VGPR148<def> = V_MUL_F32_e32 %VGPR161, %VGPR143, %EXEC<imp-use>
	%VGPR149<def> = V_MOV_B32_e32 2.146387e-01, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR148<kill>, %VGPR149, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR164<def> = V_SUB_F32_e32 %VGPR159, %VGPR1, %EXEC<imp-use>, %VGPR163_VGPR164<imp-def>
	%VGPR163<def> = V_SUB_F32_e32 %VGPR158, %VGPR0, %EXEC<imp-use>, %VGPR158_VGPR159<imp-use,kill>, %VGPR163_VGPR164<imp-use,kill>, %VGPR163_VGPR164<imp-def>
	%VGPR165_VGPR166_VGPR167<def> = IMAGE_SAMPLE_V3_V2 7, 0, 0, 0, 0, 0, 0, 0, %VGPR163_VGPR164, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23, %SGPR12_SGPR13_SGPR14_SGPR15, %EXEC<imp-use>
	%VGPR159<def> = V_SUB_F32_e32 %VGPR154, %VGPR4, %EXEC<imp-use>, %VGPR158_VGPR159<imp-def>
	%VGPR158<def> = V_SUB_F32_e32 %VGPR153, %VGPR3, %EXEC<imp-use>, %VGPR153_VGPR154<imp-use,kill>, %VGPR158_VGPR159<imp-use,kill>, %VGPR158_VGPR159<imp-def>
	%VGPR148<def> = IMAGE_SAMPLE_V1_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR158_VGPR159, %SGPR24_SGPR25_SGPR26_SGPR27_SGPR28_SGPR29_SGPR30_SGPR31, %SGPR0_SGPR1_SGPR2_SGPR3, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR148<def> = V_ADD_F32_e64 %VGPR148<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %VGPR148<kill>, %SGPR4, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR148<def> = V_CNDMASK_B32_e64 0, -1, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR148<def> = V_AND_B32_e32 1065353216, %VGPR148<kill>, %EXEC<imp-use>
	%VGPR153<def> = V_MUL_F32_e32 %VGPR166, %VGPR148, %EXEC<imp-use>
	%VGPR154<def> = V_MOV_B32_e32 2.039067e-01, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR153<kill>, %VGPR154, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR169<def> = V_SUB_F32_e32 %VGPR164, %VGPR1, %EXEC<imp-use>, %VGPR168_VGPR169<imp-def>
	%VGPR168<def> = V_SUB_F32_e32 %VGPR163, %VGPR0, %EXEC<imp-use>, %VGPR163_VGPR164<imp-use,kill>, %VGPR168_VGPR169<imp-use,kill>, %VGPR168_VGPR169<imp-def>
	%VGPR170_VGPR171_VGPR172<def> = IMAGE_SAMPLE_V3_V2 7, 0, 0, 0, 0, 0, 0, 0, %VGPR168_VGPR169, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23, %SGPR12_SGPR13_SGPR14_SGPR15, %EXEC<imp-use>
	%VGPR164<def> = V_SUB_F32_e32 %VGPR159, %VGPR4, %EXEC<imp-use>, %VGPR163_VGPR164<imp-def>
	%VGPR163<def> = V_SUB_F32_e32 %VGPR158, %VGPR3, %EXEC<imp-use>, %VGPR158_VGPR159<imp-use,kill>, %VGPR163_VGPR164<imp-use,kill>, %VGPR163_VGPR164<imp-def>
	%VGPR153<def> = IMAGE_SAMPLE_V1_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR163_VGPR164, %SGPR24_SGPR25_SGPR26_SGPR27_SGPR28_SGPR29_SGPR30_SGPR31, %SGPR0_SGPR1_SGPR2_SGPR3, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR153<def> = V_ADD_F32_e64 %VGPR153<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %VGPR153<kill>, %SGPR4, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR153<def> = V_CNDMASK_B32_e64 0, -1, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR153<def> = V_AND_B32_e32 1065353216, %VGPR153<kill>, %EXEC<imp-use>
	%VGPR158<def> = V_MUL_F32_e32 %VGPR171, %VGPR153, %EXEC<imp-use>
	%VGPR159<def> = V_MOV_B32_e32 1.937114e-01, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR158<kill>, %VGPR159, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR174<def> = V_SUB_F32_e32 %VGPR169, %VGPR1, %EXEC<imp-use>, %VGPR173_VGPR174<imp-def>
	%VGPR173<def> = V_SUB_F32_e32 %VGPR168, %VGPR0, %EXEC<imp-use>, %VGPR168_VGPR169<imp-use,kill>, %VGPR173_VGPR174<imp-use,kill>, %VGPR173_VGPR174<imp-def>
	%VGPR175_VGPR176_VGPR177<def> = IMAGE_SAMPLE_V3_V2 7, 0, 0, 0, 0, 0, 0, 0, %VGPR173_VGPR174, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23, %SGPR12_SGPR13_SGPR14_SGPR15, %EXEC<imp-use>
	%VGPR169<def> = V_SUB_F32_e32 %VGPR164, %VGPR4, %EXEC<imp-use>, %VGPR168_VGPR169<imp-def>
	%VGPR168<def> = V_SUB_F32_e32 %VGPR163, %VGPR3, %EXEC<imp-use>, %VGPR163_VGPR164<imp-use,kill>, %VGPR168_VGPR169<imp-use,kill>, %VGPR168_VGPR169<imp-def>
	%VGPR158<def> = IMAGE_SAMPLE_V1_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR168_VGPR169, %SGPR24_SGPR25_SGPR26_SGPR27_SGPR28_SGPR29_SGPR30_SGPR31, %SGPR0_SGPR1_SGPR2_SGPR3, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR158<def> = V_ADD_F32_e64 %VGPR158<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %VGPR158<kill>, %SGPR4, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR158<def> = V_CNDMASK_B32_e64 0, -1, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR158<def> = V_AND_B32_e32 1065353216, %VGPR158<kill>, %EXEC<imp-use>
	%VGPR163<def> = V_MUL_F32_e32 %VGPR176, %VGPR158, %EXEC<imp-use>
	%VGPR164<def> = V_MOV_B32_e32 1.840258e-01, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR163<kill>, %VGPR164, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR179<def> = V_SUB_F32_e32 %VGPR174, %VGPR1<kill>, %EXEC<imp-use>, %VGPR178_VGPR179<imp-def>
	%VGPR178<def> = V_SUB_F32_e32 %VGPR173, %VGPR0<kill>, %EXEC<imp-use>, %VGPR173_VGPR174<imp-use,kill>, %VGPR178_VGPR179<imp-use,kill>, %VGPR178_VGPR179<imp-def>
	%VGPR178_VGPR179_VGPR180<def> = IMAGE_SAMPLE_V3_V2 7, 0, 0, 0, 0, 0, 0, 0, %VGPR178_VGPR179<kill>, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23<kill>, %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_SUB_F32_e32 %VGPR169, %VGPR4<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = V_SUB_F32_e32 %VGPR168, %VGPR3<kill>, %EXEC<imp-use>, %VGPR168_VGPR169<imp-use,kill>, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = IMAGE_SAMPLE_V1_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR0_VGPR1<kill>, %SGPR24_SGPR25_SGPR26_SGPR27_SGPR28_SGPR29_SGPR30_SGPR31<kill>, %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR0<def> = V_ADD_F32_e64 %VGPR0<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = V_CMP_GE_F32_e64 %VGPR0<kill>, %SGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_CNDMASK_B32_e64 0, -1, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_AND_B32_e32 1065353216, %VGPR0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_MUL_F32_e32 %VGPR179, %VGPR0, %EXEC<imp-use>
	%VGPR3<def> = V_MOV_B32_e32 1.748245e-01, %EXEC<imp-use>
	%VGPR1<def> = V_MAD_F32 %VGPR1<kill>, %VGPR3, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 9; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR1<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR1<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e32 %VGPR9, %VGPR2, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e32 9.500000e-01, %VGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR17, %VGPR5, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %VGPR20, %VGPR14, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR6<kill>, %VGPR16, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %VGPR25, %VGPR7, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR6<kill>, %VGPR15, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %VGPR30, %VGPR8, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR6<kill>, %VGPR13, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %VGPR35, %VGPR12, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR6<kill>, %VGPR24, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %VGPR40, %VGPR23, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR6<kill>, %VGPR29, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %VGPR45, %VGPR28, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR6<kill>, %VGPR34, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %VGPR50, %VGPR33, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR6<kill>, %VGPR39, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %VGPR55, %VGPR38, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR6<kill>, %VGPR44, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %VGPR60, %VGPR43, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR6<kill>, %VGPR49, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %VGPR65, %VGPR48, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR6<kill>, %VGPR54, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %VGPR70, %VGPR53, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR6<kill>, %VGPR59, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %VGPR75, %VGPR58, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR6<kill>, %VGPR64, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %VGPR80, %VGPR63, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR6<kill>, %VGPR69, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %VGPR85, %VGPR68, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR6<kill>, %VGPR74, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %VGPR90, %VGPR73, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR6<kill>, %VGPR79, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %VGPR95, %VGPR78, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR6<kill>, %VGPR84, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %VGPR100, %VGPR83, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR6<kill>, %VGPR89, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %VGPR105, %VGPR88, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR6<kill>, %VGPR94, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %VGPR110, %VGPR93, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR6<kill>, %VGPR99, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %VGPR115, %VGPR98, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR6<kill>, %VGPR104, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %VGPR120, %VGPR103, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR6<kill>, %VGPR109, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %VGPR125, %VGPR108, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR6<kill>, %VGPR114, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %VGPR130, %VGPR113, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR6<kill>, %VGPR119, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %VGPR135, %VGPR118, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR6<kill>, %VGPR124, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %VGPR140, %VGPR123, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR6<kill>, %VGPR129, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %VGPR145, %VGPR128, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR6<kill>, %VGPR134, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %VGPR150, %VGPR133, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR6<kill>, %VGPR139, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %VGPR155, %VGPR138, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR6<kill>, %VGPR144, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %VGPR160, %VGPR143, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR6<kill>, %VGPR149, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %VGPR165, %VGPR148, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR6<kill>, %VGPR154, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %VGPR170, %VGPR153, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR6<kill>, %VGPR159, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %VGPR175, %VGPR158, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR6<kill>, %VGPR164, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %VGPR178, %VGPR0, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR6<kill>, %VGPR3, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 8; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR4<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR4<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR4<kill>, %VGPR1<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_MUL_F32_e32 %VGPR11, %VGPR2<kill>, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11<imp-use,kill>
	%VGPR2<def> = V_MUL_F32_e32 9.500000e-01, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_MAD_F32 %VGPR19, %VGPR5<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR17_VGPR18_VGPR19<imp-use,kill>
	%VGPR4<def> = V_MUL_F32_e32 %VGPR22, %VGPR14<kill>, %EXEC<imp-use>, %VGPR20_VGPR21_VGPR22<imp-use,kill>
	%VGPR2<def> = V_MAD_F32 %VGPR4<kill>, %VGPR16<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e32 %VGPR27, %VGPR7<kill>, %EXEC<imp-use>, %VGPR25_VGPR26_VGPR27<imp-use,kill>
	%VGPR2<def> = V_MAD_F32 %VGPR4<kill>, %VGPR15<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e32 %VGPR32, %VGPR8<kill>, %EXEC<imp-use>, %VGPR30_VGPR31_VGPR32<imp-use,kill>
	%VGPR2<def> = V_MAD_F32 %VGPR4<kill>, %VGPR13<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e32 %VGPR37, %VGPR12<kill>, %EXEC<imp-use>, %VGPR35_VGPR36_VGPR37<imp-use,kill>
	%VGPR2<def> = V_MAD_F32 %VGPR4<kill>, %VGPR24<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e32 %VGPR42, %VGPR23<kill>, %EXEC<imp-use>, %VGPR40_VGPR41_VGPR42<imp-use,kill>
	%VGPR2<def> = V_MAD_F32 %VGPR4<kill>, %VGPR29<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e32 %VGPR47, %VGPR28<kill>, %EXEC<imp-use>, %VGPR45_VGPR46_VGPR47<imp-use,kill>
	%VGPR2<def> = V_MAD_F32 %VGPR4<kill>, %VGPR34<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e32 %VGPR52, %VGPR33<kill>, %EXEC<imp-use>, %VGPR50_VGPR51_VGPR52<imp-use,kill>
	%VGPR2<def> = V_MAD_F32 %VGPR4<kill>, %VGPR39<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e32 %VGPR57, %VGPR38<kill>, %EXEC<imp-use>, %VGPR55_VGPR56_VGPR57<imp-use,kill>
	%VGPR2<def> = V_MAD_F32 %VGPR4<kill>, %VGPR44<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e32 %VGPR62, %VGPR43<kill>, %EXEC<imp-use>, %VGPR60_VGPR61_VGPR62<imp-use,kill>
	%VGPR2<def> = V_MAD_F32 %VGPR4<kill>, %VGPR49<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e32 %VGPR67, %VGPR48<kill>, %EXEC<imp-use>, %VGPR65_VGPR66_VGPR67<imp-use,kill>
	%VGPR2<def> = V_MAD_F32 %VGPR4<kill>, %VGPR54<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e32 %VGPR72, %VGPR53<kill>, %EXEC<imp-use>, %VGPR70_VGPR71_VGPR72<imp-use,kill>
	%VGPR2<def> = V_MAD_F32 %VGPR4<kill>, %VGPR59<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e32 %VGPR77, %VGPR58<kill>, %EXEC<imp-use>, %VGPR75_VGPR76_VGPR77<imp-use,kill>
	%VGPR2<def> = V_MAD_F32 %VGPR4<kill>, %VGPR64<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e32 %VGPR82, %VGPR63<kill>, %EXEC<imp-use>, %VGPR80_VGPR81_VGPR82<imp-use,kill>
	%VGPR2<def> = V_MAD_F32 %VGPR4<kill>, %VGPR69<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e32 %VGPR87, %VGPR68<kill>, %EXEC<imp-use>, %VGPR85_VGPR86_VGPR87<imp-use,kill>
	%VGPR2<def> = V_MAD_F32 %VGPR4<kill>, %VGPR74<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e32 %VGPR92, %VGPR73<kill>, %EXEC<imp-use>, %VGPR90_VGPR91_VGPR92<imp-use,kill>
	%VGPR2<def> = V_MAD_F32 %VGPR4<kill>, %VGPR79<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e32 %VGPR97, %VGPR78<kill>, %EXEC<imp-use>, %VGPR95_VGPR96_VGPR97<imp-use,kill>
	%VGPR2<def> = V_MAD_F32 %VGPR4<kill>, %VGPR84<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e32 %VGPR102, %VGPR83<kill>, %EXEC<imp-use>, %VGPR100_VGPR101_VGPR102<imp-use,kill>
	%VGPR2<def> = V_MAD_F32 %VGPR4<kill>, %VGPR89<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e32 %VGPR107, %VGPR88<kill>, %EXEC<imp-use>, %VGPR105_VGPR106_VGPR107<imp-use,kill>
	%VGPR2<def> = V_MAD_F32 %VGPR4<kill>, %VGPR94<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e32 %VGPR112, %VGPR93<kill>, %EXEC<imp-use>, %VGPR110_VGPR111_VGPR112<imp-use,kill>
	%VGPR2<def> = V_MAD_F32 %VGPR4<kill>, %VGPR99<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e32 %VGPR117, %VGPR98<kill>, %EXEC<imp-use>, %VGPR115_VGPR116_VGPR117<imp-use,kill>
	%VGPR2<def> = V_MAD_F32 %VGPR4<kill>, %VGPR104<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e32 %VGPR122, %VGPR103<kill>, %EXEC<imp-use>, %VGPR120_VGPR121_VGPR122<imp-use,kill>
	%VGPR2<def> = V_MAD_F32 %VGPR4<kill>, %VGPR109<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e32 %VGPR127, %VGPR108<kill>, %EXEC<imp-use>, %VGPR125_VGPR126_VGPR127<imp-use,kill>
	%VGPR2<def> = V_MAD_F32 %VGPR4<kill>, %VGPR114<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e32 %VGPR132, %VGPR113<kill>, %EXEC<imp-use>, %VGPR130_VGPR131_VGPR132<imp-use,kill>
	%VGPR2<def> = V_MAD_F32 %VGPR4<kill>, %VGPR119<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e32 %VGPR137, %VGPR118<kill>, %EXEC<imp-use>, %VGPR135_VGPR136_VGPR137<imp-use,kill>
	%VGPR2<def> = V_MAD_F32 %VGPR4<kill>, %VGPR124<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e32 %VGPR142, %VGPR123<kill>, %EXEC<imp-use>, %VGPR140_VGPR141_VGPR142<imp-use,kill>
	%VGPR2<def> = V_MAD_F32 %VGPR4<kill>, %VGPR129<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e32 %VGPR147, %VGPR128<kill>, %EXEC<imp-use>, %VGPR145_VGPR146_VGPR147<imp-use,kill>
	%VGPR2<def> = V_MAD_F32 %VGPR4<kill>, %VGPR134<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e32 %VGPR152, %VGPR133<kill>, %EXEC<imp-use>, %VGPR150_VGPR151_VGPR152<imp-use,kill>
	%VGPR2<def> = V_MAD_F32 %VGPR4<kill>, %VGPR139<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e32 %VGPR157, %VGPR138<kill>, %EXEC<imp-use>, %VGPR155_VGPR156_VGPR157<imp-use,kill>
	%VGPR2<def> = V_MAD_F32 %VGPR4<kill>, %VGPR144<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e32 %VGPR162, %VGPR143<kill>, %EXEC<imp-use>, %VGPR160_VGPR161_VGPR162<imp-use,kill>
	%VGPR2<def> = V_MAD_F32 %VGPR4<kill>, %VGPR149<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e32 %VGPR167, %VGPR148<kill>, %EXEC<imp-use>, %VGPR165_VGPR166_VGPR167<imp-use,kill>
	%VGPR2<def> = V_MAD_F32 %VGPR4<kill>, %VGPR154<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e32 %VGPR172, %VGPR153<kill>, %EXEC<imp-use>, %VGPR170_VGPR171_VGPR172<imp-use,kill>
	%VGPR2<def> = V_MAD_F32 %VGPR4<kill>, %VGPR159<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MUL_F32_e32 %VGPR177, %VGPR158<kill>, %EXEC<imp-use>, %VGPR175_VGPR176_VGPR177<imp-use,kill>
	%VGPR2<def> = V_MAD_F32 %VGPR4<kill>, %VGPR164<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR180, %VGPR0<kill>, %EXEC<imp-use>, %VGPR178_VGPR179_VGPR180<imp-use,kill>
	%VGPR0<def> = V_MAD_F32 %VGPR0<kill>, %VGPR3<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11<kill>, 10; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR0<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR0<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e64 %VGPR0<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR1<kill>, %VGPR0<kill>, %VGPR1, %VGPR0, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_WQM_B64 exec, exec                                                            ; BEFE0A7E
	S_MOV_B32 m0, s7                                                                ; BEFC0307
	V_INTERP_P1_F32 v2, v0, 0, 0, [m0]                                              ; C8080000
	V_INTERP_P2_F32 v2, [v2], v1, 0, 0, [m0]                                        ; C8090001
	V_INTERP_P1_F32 v3, v0, 1, 0, [m0]                                              ; C80C0100
	V_INTERP_P2_F32 v3, [v3], v1, 1, 0, [m0]                                        ; C80D0101
	V_MUL_F32_e32 v0, 7.823300e+01, v3                                              ; 100006FF 429C774C
	V_MOV_B32_e32 v1, 1.298980e+01                                                  ; 7E0202FF 414FD639
	V_MAD_F32 v0, v2, v1, v0, 0, 0, 0, 0                                            ; D2820000 04020302
	V_MUL_F32_e32 v0, 1042479491, v0                                                ; 100000FF 3E22F983
	V_SIN_F32_e32 v0, v0                                                            ; 7E006B00
	V_MUL_F32_e32 v0, 4.375855e+04, v0                                              ; 100000FF 472AEE8C
	V_FRACT_F32_e32 v0, v0                                                          ; 7E004100
	S_LOAD_DWORDX4 s[8:11], s[0:1], 0                                               ; C0840100
	S_WAITCNT lgkmcnt(0)                                                            ; BF8C007F
	S_BUFFER_LOAD_DWORD s0, s[8:11], 4                                              ; C2000904
	S_BUFFER_LOAD_DWORD s1, s[8:11], 5                                              ; C2008905
	S_WAITCNT lgkmcnt(0)                                                            ; BF8C007F
	V_MOV_B32_e32 v1, s1                                                            ; 7E020201
	V_MAD_F32 v0, v0, s0, v1, 0, 0, 0, 0                                            ; D2820000 04040100
	S_BUFFER_LOAD_DWORD s0, s[8:11], 1                                              ; C2000901
	S_WAITCNT lgkmcnt(0)                                                            ; BF8C007F
	V_SUBREV_F32_e32 v1, s0, v3                                                     ; 0A020600
	S_BUFFER_LOAD_DWORD s0, s[8:11], 11                                             ; C200090B
	V_MOV_B32_e32 v4, 2.857143e-02                                                  ; 7E0802FF 3CEA0EA1
	S_WAITCNT lgkmcnt(0)                                                            ; BF8C007F
	V_MUL_F32_e32 v4, s0, v4                                                        ; 10080800
	V_MUL_F32_e32 v1, v1, v4                                                        ; 10020901
	V_MUL_F32_e32 v1, v1, v0                                                        ; 10020101
	V_SUB_F32_e32 v6, v3, v1                                                        ; 080C0303
	V_SUB_F32_e32 v8, v6, v1                                                        ; 08100306
	S_BUFFER_LOAD_DWORD s0, s[8:11], 0                                              ; C2000900
	S_WAITCNT lgkmcnt(0)                                                            ; BF8C007F
	V_SUBREV_F32_e32 v9, s0, v2                                                     ; 0A120400
	V_MUL_F32_e32 v4, v9, v4                                                        ; 10080909
	V_MUL_F32_e32 v0, v4, v0                                                        ; 10000104
	V_SUB_F32_e32 v5, v2, v0                                                        ; 080A0102
	V_SUB_F32_e32 v7, v5, v0                                                        ; 080E0105
	S_LOAD_DWORDX4 s[12:15], s[2:3], 0                                              ; C0860300
	S_LOAD_DWORDX8 s[16:23], s[4:5], 0                                              ; C0C80500
	S_WAITCNT lgkmcnt(0)                                                            ; BF8C007F
	IMAGE_SAMPLE v[9:11], 7, 0, 0, 0, 0, 0, 0, 0, v[7:8], s[16:23], s[12:15]        ; F0800700 00640907
	S_BUFFER_LOAD_DWORD s0, s[8:11], 7                                              ; C2000907
	S_WAITCNT vmcnt(0) lgkmcnt(0)                                                   ; BF8C0070
	V_MUL_F32_e32 v4, s0, v1                                                        ; 10080200
	V_MUL_F32_e32 v3, s0, v3                                                        ; 10060600
	V_SUB_F32_e32 v13, v3, v4                                                       ; 081A0903
	V_SUB_F32_e32 v15, v13, v4                                                      ; 081E090D
	S_BUFFER_LOAD_DWORD s0, s[8:11], 6                                              ; C2000906
	S_WAITCNT lgkmcnt(0)                                                            ; BF8C007F
	V_MUL_F32_e32 v3, s0, v0                                                        ; 10060000
	V_MUL_F32_e32 v2, s0, v2                                                        ; 10040400
	V_SUB_F32_e32 v12, v2, v3                                                       ; 08180702
	V_SUB_F32_e32 v14, v12, v3                                                      ; 081C070C
	S_LOAD_DWORDX4 s[0:3], s[2:3], 4                                                ; C0800304
	S_LOAD_DWORDX8 s[24:31], s[4:5], 8                                              ; C0CC0508
	S_WAITCNT lgkmcnt(0)                                                            ; BF8C007F
	IMAGE_SAMPLE v2, 1, 0, 0, 0, 0, 0, 0, 0, v[14:15], s[24:31], s[0:3]             ; F0800100 0006020E
	S_WAITCNT vmcnt(0)                                                              ; BF8C0770
	V_ADD_F32_e64 v2, v2, 0, 1, 0, 0, 0                                             ; D2060102 02010102
	S_BUFFER_LOAD_DWORD s4, s[8:11], 2                                              ; C2020902
	S_WAITCNT lgkmcnt(0)                                                            ; BF8C007F
	V_CMP_GE_F32_e64 s[6:7], v2, s4, 0, 0, 0, 0                                     ; D00C0006 02000902
	V_CNDMASK_B32_e64 v2, 0, -1, s[6:7], 0, 0, 0, 0                                 ; D2000002 00198280
	V_AND_B32_e32 v2, 1065353216, v2                                                ; 360404F2
	V_MUL_F32_e32 v16, v10, v2                                                      ; 1020050A
	V_MUL_F32_e32 v16, 9.500000e-01, v16                                            ; 102020FF 3F733333
	IMAGE_SAMPLE v[17:19], 7, 0, 0, 0, 0, 0, 0, 0, v[5:6], s[16:23], s[12:15]       ; F0800700 00641105
	IMAGE_SAMPLE v5, 1, 0, 0, 0, 0, 0, 0, 0, v[12:13], s[24:31], s[0:3]             ; F0800100 0006050C
	S_WAITCNT vmcnt(0)                                                              ; BF8C0770
	V_ADD_F32_e64 v5, v5, 0, 1, 0, 0, 0                                             ; D2060105 02010105
	V_CMP_GE_F32_e64 s[6:7], v5, s4, 0, 0, 0, 0                                     ; D00C0006 02000905
	V_CNDMASK_B32_e64 v5, 0, -1, s[6:7], 0, 0, 0, 0                                 ; D2000005 00198280
	V_AND_B32_e32 v5, 1065353216, v5                                                ; 360A0AF2
	V_MAD_F32 v6, v18, v5, v16, 0, 0, 0, 0                                          ; D2820006 04420B12
	V_SUB_F32_e32 v13, v8, v1                                                       ; 081A0308
	V_SUB_F32_e32 v12, v7, v0                                                       ; 08180107
	IMAGE_SAMPLE v[20:22], 7, 0, 0, 0, 0, 0, 0, 0, v[12:13], s[16:23], s[12:15]     ; F0800700 0064140C
	V_SUB_F32_e32 v8, v15, v4                                                       ; 0810090F
	V_SUB_F32_e32 v7, v14, v3                                                       ; 080E070E
	IMAGE_SAMPLE v14, 1, 0, 0, 0, 0, 0, 0, 0, v[7:8], s[24:31], s[0:3]              ; F0800100 00060E07
	S_WAITCNT vmcnt(0)                                                              ; BF8C0770
	V_ADD_F32_e64 v14, v14, 0, 1, 0, 0, 0                                           ; D206010E 0201010E
	V_CMP_GE_F32_e64 s[6:7], v14, s4, 0, 0, 0, 0                                    ; D00C0006 0200090E
	V_CNDMASK_B32_e64 v14, 0, -1, s[6:7], 0, 0, 0, 0                                ; D200000E 00198280
	V_AND_B32_e32 v14, 1065353216, v14                                              ; 361C1CF2
	V_MUL_F32_e32 v15, v21, v14                                                     ; 101E1D15
	V_MOV_B32_e32 v16, 9.025000e-01                                                 ; 7E2002FF 3F670A3D
	V_MAD_F32 v6, v15, v16, v6, 0, 0, 0, 0                                          ; D2820006 041A210F
	V_SUB_F32_e32 v24, v13, v1                                                      ; 0830030D
	V_SUB_F32_e32 v23, v12, v0                                                      ; 082E010C
	IMAGE_SAMPLE v[25:27], 7, 0, 0, 0, 0, 0, 0, 0, v[23:24], s[16:23], s[12:15]     ; F0800700 00641917
	V_SUB_F32_e32 v13, v8, v4                                                       ; 081A0908
	V_SUB_F32_e32 v12, v7, v3                                                       ; 08180707
	IMAGE_SAMPLE v7, 1, 0, 0, 0, 0, 0, 0, 0, v[12:13], s[24:31], s[0:3]             ; F0800100 0006070C
	S_WAITCNT vmcnt(0)                                                              ; BF8C0770
	V_ADD_F32_e64 v7, v7, 0, 1, 0, 0, 0                                             ; D2060107 02010107
	V_CMP_GE_F32_e64 s[6:7], v7, s4, 0, 0, 0, 0                                     ; D00C0006 02000907
	V_CNDMASK_B32_e64 v7, 0, -1, s[6:7], 0, 0, 0, 0                                 ; D2000007 00198280
	V_AND_B32_e32 v7, 1065353216, v7                                                ; 360E0EF2
	V_MUL_F32_e32 v8, v26, v7                                                       ; 10100F1A
	V_MOV_B32_e32 v15, 8.573750e-01                                                 ; 7E1E02FF 3F5B7CED
	V_MAD_F32 v6, v8, v15, v6, 0, 0, 0, 0                                           ; D2820006 041A1F08
	V_SUB_F32_e32 v29, v24, v1                                                      ; 083A0318
	V_SUB_F32_e32 v28, v23, v0                                                      ; 08380117
	IMAGE_SAMPLE v[30:32], 7, 0, 0, 0, 0, 0, 0, 0, v[28:29], s[16:23], s[12:15]     ; F0800700 00641E1C
	V_SUB_F32_e32 v24, v13, v4                                                      ; 0830090D
	V_SUB_F32_e32 v23, v12, v3                                                      ; 082E070C
	IMAGE_SAMPLE v8, 1, 0, 0, 0, 0, 0, 0, 0, v[23:24], s[24:31], s[0:3]             ; F0800100 00060817
	S_WAITCNT vmcnt(0)                                                              ; BF8C0770
	V_ADD_F32_e64 v8, v8, 0, 1, 0, 0, 0                                             ; D2060108 02010108
	V_CMP_GE_F32_e64 s[6:7], v8, s4, 0, 0, 0, 0                                     ; D00C0006 02000908
	V_CNDMASK_B32_e64 v8, 0, -1, s[6:7], 0, 0, 0, 0                                 ; D2000008 00198280
	V_AND_B32_e32 v8, 1065353216, v8                                                ; 361010F2
	V_MUL_F32_e32 v12, v31, v8                                                      ; 1018111F
	V_MOV_B32_e32 v13, 8.145062e-01                                                 ; 7E1A02FF 3F50837B
	V_MAD_F32 v6, v12, v13, v6, 0, 0, 0, 0                                          ; D2820006 041A1B0C
	V_SUB_F32_e32 v34, v29, v1                                                      ; 0844031D
	V_SUB_F32_e32 v33, v28, v0                                                      ; 0842011C
	IMAGE_SAMPLE v[35:37], 7, 0, 0, 0, 0, 0, 0, 0, v[33:34], s[16:23], s[12:15]     ; F0800700 00642321
	V_SUB_F32_e32 v29, v24, v4                                                      ; 083A0918
	V_SUB_F32_e32 v28, v23, v3                                                      ; 08380717
	IMAGE_SAMPLE v12, 1, 0, 0, 0, 0, 0, 0, 0, v[28:29], s[24:31], s[0:3]            ; F0800100 00060C1C
	S_WAITCNT vmcnt(0)                                                              ; BF8C0770
	V_ADD_F32_e64 v12, v12, 0, 1, 0, 0, 0                                           ; D206010C 0201010C
	V_CMP_GE_F32_e64 s[6:7], v12, s4, 0, 0, 0, 0                                    ; D00C0006 0200090C
	V_CNDMASK_B32_e64 v12, 0, -1, s[6:7], 0, 0, 0, 0                                ; D200000C 00198280
	V_AND_B32_e32 v12, 1065353216, v12                                              ; 361818F2
	V_MUL_F32_e32 v23, v36, v12                                                     ; 102E1924
	V_MOV_B32_e32 v24, 7.737809e-01                                                 ; 7E3002FF 3F461681
	V_MAD_F32 v6, v23, v24, v6, 0, 0, 0, 0                                          ; D2820006 041A3117
	V_SUB_F32_e32 v39, v34, v1                                                      ; 084E0322
	V_SUB_F32_e32 v38, v33, v0                                                      ; 084C0121
	IMAGE_SAMPLE v[40:42], 7, 0, 0, 0, 0, 0, 0, 0, v[38:39], s[16:23], s[12:15]     ; F0800700 00642826
	V_SUB_F32_e32 v34, v29, v4                                                      ; 0844091D
	V_SUB_F32_e32 v33, v28, v3                                                      ; 0842071C
	IMAGE_SAMPLE v23, 1, 0, 0, 0, 0, 0, 0, 0, v[33:34], s[24:31], s[0:3]            ; F0800100 00061721
	S_WAITCNT vmcnt(0)                                                              ; BF8C0770
	V_ADD_F32_e64 v23, v23, 0, 1, 0, 0, 0                                           ; D2060117 02010117
	V_CMP_GE_F32_e64 s[6:7], v23, s4, 0, 0, 0, 0                                    ; D00C0006 02000917
	V_CNDMASK_B32_e64 v23, 0, -1, s[6:7], 0, 0, 0, 0                                ; D2000017 00198280
	V_AND_B32_e32 v23, 1065353216, v23                                              ; 362E2EF2
	V_MUL_F32_e32 v28, v41, v23                                                     ; 10382F29
	V_MOV_B32_e32 v29, 7.350918e-01                                                 ; 7E3A02FF 3F3C2EFA
	V_MAD_F32 v6, v28, v29, v6, 0, 0, 0, 0                                          ; D2820006 041A3B1C
	V_SUB_F32_e32 v44, v39, v1                                                      ; 08580327
	V_SUB_F32_e32 v43, v38, v0                                                      ; 08560126
	IMAGE_SAMPLE v[45:47], 7, 0, 0, 0, 0, 0, 0, 0, v[43:44], s[16:23], s[12:15]     ; F0800700 00642D2B
	V_SUB_F32_e32 v39, v34, v4                                                      ; 084E0922
	V_SUB_F32_e32 v38, v33, v3                                                      ; 084C0721
	IMAGE_SAMPLE v28, 1, 0, 0, 0, 0, 0, 0, 0, v[38:39], s[24:31], s[0:3]            ; F0800100 00061C26
	S_WAITCNT vmcnt(0)                                                              ; BF8C0770
	V_ADD_F32_e64 v28, v28, 0, 1, 0, 0, 0                                           ; D206011C 0201011C
	V_CMP_GE_F32_e64 s[6:7], v28, s4, 0, 0, 0, 0                                    ; D00C0006 0200091C
	V_CNDMASK_B32_e64 v28, 0, -1, s[6:7], 0, 0, 0, 0                                ; D200001C 00198280
	V_AND_B32_e32 v28, 1065353216, v28                                              ; 363838F2
	V_MUL_F32_e32 v33, v46, v28                                                     ; 1042392E
	V_MOV_B32_e32 v34, 6.983372e-01                                                 ; 7E4402FF 3F32C63A
	V_MAD_F32 v6, v33, v34, v6, 0, 0, 0, 0                                          ; D2820006 041A4521
	V_SUB_F32_e32 v49, v44, v1                                                      ; 0862032C
	V_SUB_F32_e32 v48, v43, v0                                                      ; 0860012B
	IMAGE_SAMPLE v[50:52], 7, 0, 0, 0, 0, 0, 0, 0, v[48:49], s[16:23], s[12:15]     ; F0800700 00643230
	V_SUB_F32_e32 v44, v39, v4                                                      ; 08580927
	V_SUB_F32_e32 v43, v38, v3                                                      ; 08560726
	IMAGE_SAMPLE v33, 1, 0, 0, 0, 0, 0, 0, 0, v[43:44], s[24:31], s[0:3]            ; F0800100 0006212B
	S_WAITCNT vmcnt(0)                                                              ; BF8C0770
	V_ADD_F32_e64 v33, v33, 0, 1, 0, 0, 0                                           ; D2060121 02010121
	V_CMP_GE_F32_e64 s[6:7], v33, s4, 0, 0, 0, 0                                    ; D00C0006 02000921
	V_CNDMASK_B32_e64 v33, 0, -1, s[6:7], 0, 0, 0, 0                                ; D2000021 00198280
	V_AND_B32_e32 v33, 1065353216, v33                                              ; 364242F2
	V_MUL_F32_e32 v38, v51, v33                                                     ; 104C4333
	V_MOV_B32_e32 v39, 6.634203e-01                                                 ; 7E4E02FF 3F29D5EA
	V_MAD_F32 v6, v38, v39, v6, 0, 0, 0, 0                                          ; D2820006 041A4F26
	V_SUB_F32_e32 v54, v49, v1                                                      ; 086C0331
	V_SUB_F32_e32 v53, v48, v0                                                      ; 086A0130
	IMAGE_SAMPLE v[55:57], 7, 0, 0, 0, 0, 0, 0, 0, v[53:54], s[16:23], s[12:15]     ; F0800700 00643735
	V_SUB_F32_e32 v49, v44, v4                                                      ; 0862092C
	V_SUB_F32_e32 v48, v43, v3                                                      ; 0860072B
	IMAGE_SAMPLE v38, 1, 0, 0, 0, 0, 0, 0, 0, v[48:49], s[24:31], s[0:3]            ; F0800100 00062630
	S_WAITCNT vmcnt(0)                                                              ; BF8C0770
	V_ADD_F32_e64 v38, v38, 0, 1, 0, 0, 0                                           ; D2060126 02010126
	V_CMP_GE_F32_e64 s[6:7], v38, s4, 0, 0, 0, 0                                    ; D00C0006 02000926
	V_CNDMASK_B32_e64 v38, 0, -1, s[6:7], 0, 0, 0, 0                                ; D2000026 00198280
	V_AND_B32_e32 v38, 1065353216, v38                                              ; 364C4CF2
	V_MUL_F32_e32 v43, v56, v38                                                     ; 10564D38
	V_MOV_B32_e32 v44, 6.302493e-01                                                 ; 7E5802FF 3F215805
	V_MAD_F32 v6, v43, v44, v6, 0, 0, 0, 0                                          ; D2820006 041A592B
	V_SUB_F32_e32 v59, v54, v1                                                      ; 08760336
	V_SUB_F32_e32 v58, v53, v0                                                      ; 08740135
	IMAGE_SAMPLE v[60:62], 7, 0, 0, 0, 0, 0, 0, 0, v[58:59], s[16:23], s[12:15]     ; F0800700 00643C3A
	V_SUB_F32_e32 v54, v49, v4                                                      ; 086C0931
	V_SUB_F32_e32 v53, v48, v3                                                      ; 086A0730
	IMAGE_SAMPLE v43, 1, 0, 0, 0, 0, 0, 0, 0, v[53:54], s[24:31], s[0:3]            ; F0800100 00062B35
	S_WAITCNT vmcnt(0)                                                              ; BF8C0770
	V_ADD_F32_e64 v43, v43, 0, 1, 0, 0, 0                                           ; D206012B 0201012B
	V_CMP_GE_F32_e64 s[6:7], v43, s4, 0, 0, 0, 0                                    ; D00C0006 0200092B
	V_CNDMASK_B32_e64 v43, 0, -1, s[6:7], 0, 0, 0, 0                                ; D200002B 00198280
	V_AND_B32_e32 v43, 1065353216, v43                                              ; 365656F2
	V_MUL_F32_e32 v48, v61, v43                                                     ; 1060573D
	V_MOV_B32_e32 v49, 5.987368e-01                                                 ; 7E6202FF 3F1946D1
	V_MAD_F32 v6, v48, v49, v6, 0, 0, 0, 0                                          ; D2820006 041A6330
	V_SUB_F32_e32 v64, v59, v1                                                      ; 0880033B
	V_SUB_F32_e32 v63, v58, v0                                                      ; 087E013A
	IMAGE_SAMPLE v[65:67], 7, 0, 0, 0, 0, 0, 0, 0, v[63:64], s[16:23], s[12:15]     ; F0800700 0064413F
	V_SUB_F32_e32 v59, v54, v4                                                      ; 08760936
	V_SUB_F32_e32 v58, v53, v3                                                      ; 08740735
	IMAGE_SAMPLE v48, 1, 0, 0, 0, 0, 0, 0, 0, v[58:59], s[24:31], s[0:3]            ; F0800100 0006303A
	S_WAITCNT vmcnt(0)                                                              ; BF8C0770
	V_ADD_F32_e64 v48, v48, 0, 1, 0, 0, 0                                           ; D2060130 02010130
	V_CMP_GE_F32_e64 s[6:7], v48, s4, 0, 0, 0, 0                                    ; D00C0006 02000930
	V_CNDMASK_B32_e64 v48, 0, -1, s[6:7], 0, 0, 0, 0                                ; D2000030 00198280
	V_AND_B32_e32 v48, 1065353216, v48                                              ; 366060F2
	V_MUL_F32_e32 v53, v66, v48                                                     ; 106A6142
	V_MOV_B32_e32 v54, 5.688000e-01                                                 ; 7E6C02FF 3F119CE0
	V_MAD_F32 v6, v53, v54, v6, 0, 0, 0, 0                                          ; D2820006 041A6D35
	V_SUB_F32_e32 v69, v64, v1                                                      ; 088A0340
	V_SUB_F32_e32 v68, v63, v0                                                      ; 0888013F
	IMAGE_SAMPLE v[70:72], 7, 0, 0, 0, 0, 0, 0, 0, v[68:69], s[16:23], s[12:15]     ; F0800700 00644644
	V_SUB_F32_e32 v64, v59, v4                                                      ; 0880093B
	V_SUB_F32_e32 v63, v58, v3                                                      ; 087E073A
	IMAGE_SAMPLE v53, 1, 0, 0, 0, 0, 0, 0, 0, v[63:64], s[24:31], s[0:3]            ; F0800100 0006353F
	S_WAITCNT vmcnt(0)                                                              ; BF8C0770
	V_ADD_F32_e64 v53, v53, 0, 1, 0, 0, 0                                           ; D2060135 02010135
	V_CMP_GE_F32_e64 s[6:7], v53, s4, 0, 0, 0, 0                                    ; D00C0006 02000935
	V_CNDMASK_B32_e64 v53, 0, -1, s[6:7], 0, 0, 0, 0                                ; D2000035 00198280
	V_AND_B32_e32 v53, 1065353216, v53                                              ; 366A6AF2
	V_MUL_F32_e32 v58, v71, v53                                                     ; 10746B47
	V_MOV_B32_e32 v59, 5.403600e-01                                                 ; 7E7602FF 3F0A5508
	V_MAD_F32 v6, v58, v59, v6, 0, 0, 0, 0                                          ; D2820006 041A773A
	V_SUB_F32_e32 v74, v69, v1                                                      ; 08940345
	V_SUB_F32_e32 v73, v68, v0                                                      ; 08920144
	IMAGE_SAMPLE v[75:77], 7, 0, 0, 0, 0, 0, 0, 0, v[73:74], s[16:23], s[12:15]     ; F0800700 00644B49
	V_SUB_F32_e32 v69, v64, v4                                                      ; 088A0940
	V_SUB_F32_e32 v68, v63, v3                                                      ; 0888073F
	IMAGE_SAMPLE v58, 1, 0, 0, 0, 0, 0, 0, 0, v[68:69], s[24:31], s[0:3]            ; F0800100 00063A44
	S_WAITCNT vmcnt(0)                                                              ; BF8C0770
	V_ADD_F32_e64 v58, v58, 0, 1, 0, 0, 0                                           ; D206013A 0201013A
	V_CMP_GE_F32_e64 s[6:7], v58, s4, 0, 0, 0, 0                                    ; D00C0006 0200093A
	V_CNDMASK_B32_e64 v58, 0, -1, s[6:7], 0, 0, 0, 0                                ; D200003A 00198280
	V_AND_B32_e32 v58, 1065353216, v58                                              ; 367474F2
	V_MUL_F32_e32 v63, v76, v58                                                     ; 107E754C
	V_MOV_B32_e32 v64, 5.133420e-01                                                 ; 7E8002FF 3F036A61
	V_MAD_F32 v6, v63, v64, v6, 0, 0, 0, 0                                          ; D2820006 041A813F
	V_SUB_F32_e32 v79, v74, v1                                                      ; 089E034A
	V_SUB_F32_e32 v78, v73, v0                                                      ; 089C0149
	IMAGE_SAMPLE v[80:82], 7, 0, 0, 0, 0, 0, 0, 0, v[78:79], s[16:23], s[12:15]     ; F0800700 0064504E
	V_SUB_F32_e32 v74, v69, v4                                                      ; 08940945
	V_SUB_F32_e32 v73, v68, v3                                                      ; 08920744
	IMAGE_SAMPLE v63, 1, 0, 0, 0, 0, 0, 0, 0, v[73:74], s[24:31], s[0:3]            ; F0800100 00063F49
	S_WAITCNT vmcnt(0)                                                              ; BF8C0770
	V_ADD_F32_e64 v63, v63, 0, 1, 0, 0, 0                                           ; D206013F 0201013F
	V_CMP_GE_F32_e64 s[6:7], v63, s4, 0, 0, 0, 0                                    ; D00C0006 0200093F
	V_CNDMASK_B32_e64 v63, 0, -1, s[6:7], 0, 0, 0, 0                                ; D200003F 00198280
	V_AND_B32_e32 v63, 1065353216, v63                                              ; 367E7EF2
	V_MUL_F32_e32 v68, v81, v63                                                     ; 10887F51
	V_MOV_B32_e32 v69, 4.876749e-01                                                 ; 7E8A02FF 3EF9B085
	V_MAD_F32 v6, v68, v69, v6, 0, 0, 0, 0                                          ; D2820006 041A8B44
	V_SUB_F32_e32 v84, v79, v1                                                      ; 08A8034F
	V_SUB_F32_e32 v83, v78, v0                                                      ; 08A6014E
	IMAGE_SAMPLE v[85:87], 7, 0, 0, 0, 0, 0, 0, 0, v[83:84], s[16:23], s[12:15]     ; F0800700 00645553
	V_SUB_F32_e32 v79, v74, v4                                                      ; 089E094A
	V_SUB_F32_e32 v78, v73, v3                                                      ; 089C0749
	IMAGE_SAMPLE v68, 1, 0, 0, 0, 0, 0, 0, 0, v[78:79], s[24:31], s[0:3]            ; F0800100 0006444E
	S_WAITCNT vmcnt(0)                                                              ; BF8C0770
	V_ADD_F32_e64 v68, v68, 0, 1, 0, 0, 0                                           ; D2060144 02010144
	V_CMP_GE_F32_e64 s[6:7], v68, s4, 0, 0, 0, 0                                    ; D00C0006 02000944
	V_CNDMASK_B32_e64 v68, 0, -1, s[6:7], 0, 0, 0, 0                                ; D2000044 00198280
	V_AND_B32_e32 v68, 1065353216, v68                                              ; 368888F2
	V_MUL_F32_e32 v73, v86, v68                                                     ; 10928956
	V_MOV_B32_e32 v74, 4.632911e-01                                                 ; 7E9402FF 3EED347E
	V_MAD_F32 v6, v73, v74, v6, 0, 0, 0, 0                                          ; D2820006 041A9549
	V_SUB_F32_e32 v89, v84, v1                                                      ; 08B20354
	V_SUB_F32_e32 v88, v83, v0                                                      ; 08B00153
	IMAGE_SAMPLE v[90:92], 7, 0, 0, 0, 0, 0, 0, 0, v[88:89], s[16:23], s[12:15]     ; F0800700 00645A58
	V_SUB_F32_e32 v84, v79, v4                                                      ; 08A8094F
	V_SUB_F32_e32 v83, v78, v3                                                      ; 08A6074E
	IMAGE_SAMPLE v73, 1, 0, 0, 0, 0, 0, 0, 0, v[83:84], s[24:31], s[0:3]            ; F0800100 00064953
	S_WAITCNT vmcnt(0)                                                              ; BF8C0770
	V_ADD_F32_e64 v73, v73, 0, 1, 0, 0, 0                                           ; D2060149 02010149
	V_CMP_GE_F32_e64 s[6:7], v73, s4, 0, 0, 0, 0                                    ; D00C0006 02000949
	V_CNDMASK_B32_e64 v73, 0, -1, s[6:7], 0, 0, 0, 0                                ; D2000049 00198280
	V_AND_B32_e32 v73, 1065353216, v73                                              ; 369292F2
	V_MUL_F32_e32 v78, v91, v73                                                     ; 109C935B
	V_MOV_B32_e32 v79, 4.401265e-01                                                 ; 7E9E02FF 3EE15844
	V_MAD_F32 v6, v78, v79, v6, 0, 0, 0, 0                                          ; D2820006 041A9F4E
	V_SUB_F32_e32 v94, v89, v1                                                      ; 08BC0359
	V_SUB_F32_e32 v93, v88, v0                                                      ; 08BA0158
	IMAGE_SAMPLE v[95:97], 7, 0, 0, 0, 0, 0, 0, 0, v[93:94], s[16:23], s[12:15]     ; F0800700 00645F5D
	V_SUB_F32_e32 v89, v84, v4                                                      ; 08B20954
	V_SUB_F32_e32 v88, v83, v3                                                      ; 08B00753
	IMAGE_SAMPLE v78, 1, 0, 0, 0, 0, 0, 0, 0, v[88:89], s[24:31], s[0:3]            ; F0800100 00064E58
	S_WAITCNT vmcnt(0)                                                              ; BF8C0770
	V_ADD_F32_e64 v78, v78, 0, 1, 0, 0, 0                                           ; D206014E 0201014E
	V_CMP_GE_F32_e64 s[6:7], v78, s4, 0, 0, 0, 0                                    ; D00C0006 0200094E
	V_CNDMASK_B32_e64 v78, 0, -1, s[6:7], 0, 0, 0, 0                                ; D200004E 00198280
	V_AND_B32_e32 v78, 1065353216, v78                                              ; 369C9CF2
	V_MUL_F32_e32 v83, v96, v78                                                     ; 10A69D60
	V_MOV_B32_e32 v84, 4.181202e-01                                                 ; 7EA802FF 3ED613DA
	V_MAD_F32 v6, v83, v84, v6, 0, 0, 0, 0                                          ; D2820006 041AA953
	V_SUB_F32_e32 v99, v94, v1                                                      ; 08C6035E
	V_SUB_F32_e32 v98, v93, v0                                                      ; 08C4015D
	IMAGE_SAMPLE v[100:102], 7, 0, 0, 0, 0, 0, 0, 0, v[98:99], s[16:23], s[12:15]   ; F0800700 00646462
	V_SUB_F32_e32 v94, v89, v4                                                      ; 08BC0959
	V_SUB_F32_e32 v93, v88, v3                                                      ; 08BA0758
	IMAGE_SAMPLE v83, 1, 0, 0, 0, 0, 0, 0, 0, v[93:94], s[24:31], s[0:3]            ; F0800100 0006535D
	S_WAITCNT vmcnt(0)                                                              ; BF8C0770
	V_ADD_F32_e64 v83, v83, 0, 1, 0, 0, 0                                           ; D2060153 02010153
	V_CMP_GE_F32_e64 s[6:7], v83, s4, 0, 0, 0, 0                                    ; D00C0006 02000953
	V_CNDMASK_B32_e64 v83, 0, -1, s[6:7], 0, 0, 0, 0                                ; D2000053 00198280
	V_AND_B32_e32 v83, 1065353216, v83                                              ; 36A6A6F2
	V_MUL_F32_e32 v88, v101, v83                                                    ; 10B0A765
	V_MOV_B32_e32 v89, 3.972142e-01                                                 ; 7EB202FF 3ECB5FA9
	V_MAD_F32 v6, v88, v89, v6, 0, 0, 0, 0                                          ; D2820006 041AB358
	V_SUB_F32_e32 v104, v99, v1                                                     ; 08D00363
	V_SUB_F32_e32 v103, v98, v0                                                     ; 08CE0162
	IMAGE_SAMPLE v[105:107], 7, 0, 0, 0, 0, 0, 0, 0, v[103:104], s[16:23], s[12:15] ; F0800700 00646967
	V_SUB_F32_e32 v99, v94, v4                                                      ; 08C6095E
	V_SUB_F32_e32 v98, v93, v3                                                      ; 08C4075D
	IMAGE_SAMPLE v88, 1, 0, 0, 0, 0, 0, 0, 0, v[98:99], s[24:31], s[0:3]            ; F0800100 00065862
	S_WAITCNT vmcnt(0)                                                              ; BF8C0770
	V_ADD_F32_e64 v88, v88, 0, 1, 0, 0, 0                                           ; D2060158 02010158
	V_CMP_GE_F32_e64 s[6:7], v88, s4, 0, 0, 0, 0                                    ; D00C0006 02000958
	V_CNDMASK_B32_e64 v88, 0, -1, s[6:7], 0, 0, 0, 0                                ; D2000058 00198280
	V_AND_B32_e32 v88, 1065353216, v88                                              ; 36B0B0F2
	V_MUL_F32_e32 v93, v106, v88                                                    ; 10BAB16A
	V_MOV_B32_e32 v94, 3.773535e-01                                                 ; 7EBC02FF 3EC1347A
	V_MAD_F32 v6, v93, v94, v6, 0, 0, 0, 0                                          ; D2820006 041ABD5D
	V_SUB_F32_e32 v109, v104, v1                                                    ; 08DA0368
	V_SUB_F32_e32 v108, v103, v0                                                    ; 08D80167
	IMAGE_SAMPLE v[110:112], 7, 0, 0, 0, 0, 0, 0, 0, v[108:109], s[16:23], s[12:15] ; F0800700 00646E6C
	V_SUB_F32_e32 v104, v99, v4                                                     ; 08D00963
	V_SUB_F32_e32 v103, v98, v3                                                     ; 08CE0762
	IMAGE_SAMPLE v93, 1, 0, 0, 0, 0, 0, 0, 0, v[103:104], s[24:31], s[0:3]          ; F0800100 00065D67
	S_WAITCNT vmcnt(0)                                                              ; BF8C0770
	V_ADD_F32_e64 v93, v93, 0, 1, 0, 0, 0                                           ; D206015D 0201015D
	V_CMP_GE_F32_e64 s[6:7], v93, s4, 0, 0, 0, 0                                    ; D00C0006 0200095D
	V_CNDMASK_B32_e64 v93, 0, -1, s[6:7], 0, 0, 0, 0                                ; D200005D 00198280
	V_AND_B32_e32 v93, 1065353216, v93                                              ; 36BABAF2
	V_MUL_F32_e32 v98, v111, v93                                                    ; 10C4BB6F
	V_MOV_B32_e32 v99, 3.584858e-01                                                 ; 7EC602FF 3EB78B74
	V_MAD_F32 v6, v98, v99, v6, 0, 0, 0, 0                                          ; D2820006 041AC762
	V_SUB_F32_e32 v114, v109, v1                                                    ; 08E4036D
	V_SUB_F32_e32 v113, v108, v0                                                    ; 08E2016C
	IMAGE_SAMPLE v[115:117], 7, 0, 0, 0, 0, 0, 0, 0, v[113:114], s[16:23], s[12:15] ; F0800700 00647371
	V_SUB_F32_e32 v109, v104, v4                                                    ; 08DA0968
	V_SUB_F32_e32 v108, v103, v3                                                    ; 08D80767
	IMAGE_SAMPLE v98, 1, 0, 0, 0, 0, 0, 0, 0, v[108:109], s[24:31], s[0:3]          ; F0800100 0006626C
	S_WAITCNT vmcnt(0)                                                              ; BF8C0770
	V_ADD_F32_e64 v98, v98, 0, 1, 0, 0, 0                                           ; D2060162 02010162
	V_CMP_GE_F32_e64 s[6:7], v98, s4, 0, 0, 0, 0                                    ; D00C0006 02000962
	V_CNDMASK_B32_e64 v98, 0, -1, s[6:7], 0, 0, 0, 0                                ; D2000062 00198280
	V_AND_B32_e32 v98, 1065353216, v98                                              ; 36C4C4F2
	V_MUL_F32_e32 v103, v116, v98                                                   ; 10CEC574
	V_MOV_B32_e32 v104, 3.405615e-01                                                ; 7ED002FF 3EAE5E14
	V_MAD_F32 v6, v103, v104, v6, 0, 0, 0, 0                                        ; D2820006 041AD167
	V_SUB_F32_e32 v119, v114, v1                                                    ; 08EE0372
	V_SUB_F32_e32 v118, v113, v0                                                    ; 08EC0171
	IMAGE_SAMPLE v[120:122], 7, 0, 0, 0, 0, 0, 0, 0, v[118:119], s[16:23], s[12:15] ; F0800700 00647876
	V_SUB_F32_e32 v114, v109, v4                                                    ; 08E4096D
	V_SUB_F32_e32 v113, v108, v3                                                    ; 08E2076C
	IMAGE_SAMPLE v103, 1, 0, 0, 0, 0, 0, 0, 0, v[113:114], s[24:31], s[0:3]         ; F0800100 00066771
	S_WAITCNT vmcnt(0)                                                              ; BF8C0770
	V_ADD_F32_e64 v103, v103, 0, 1, 0, 0, 0                                         ; D2060167 02010167
	V_CMP_GE_F32_e64 s[6:7], v103, s4, 0, 0, 0, 0                                   ; D00C0006 02000967
	V_CNDMASK_B32_e64 v103, 0, -1, s[6:7], 0, 0, 0, 0                               ; D2000067 00198280
	V_AND_B32_e32 v103, 1065353216, v103                                            ; 36CECEF2
	V_MUL_F32_e32 v108, v121, v103                                                  ; 10D8CF79
	V_MOV_B32_e32 v109, 3.235334e-01                                                ; 7EDA02FF 3EA5A62C
	V_MAD_F32 v6, v108, v109, v6, 0, 0, 0, 0                                        ; D2820006 041ADB6C
	V_SUB_F32_e32 v124, v119, v1                                                    ; 08F80377
	V_SUB_F32_e32 v123, v118, v0                                                    ; 08F60176
	IMAGE_SAMPLE v[125:127], 7, 0, 0, 0, 0, 0, 0, 0, v[123:124], s[16:23], s[12:15] ; F0800700 00647D7B
	V_SUB_F32_e32 v119, v114, v4                                                    ; 08EE0972
	V_SUB_F32_e32 v118, v113, v3                                                    ; 08EC0771
	IMAGE_SAMPLE v108, 1, 0, 0, 0, 0, 0, 0, 0, v[118:119], s[24:31], s[0:3]         ; F0800100 00066C76
	S_WAITCNT vmcnt(0)                                                              ; BF8C0770
	V_ADD_F32_e64 v108, v108, 0, 1, 0, 0, 0                                         ; D206016C 0201016C
	V_CMP_GE_F32_e64 s[6:7], v108, s4, 0, 0, 0, 0                                   ; D00C0006 0200096C
	V_CNDMASK_B32_e64 v108, 0, -1, s[6:7], 0, 0, 0, 0                               ; D200006C 00198280
	V_AND_B32_e32 v108, 1065353216, v108                                            ; 36D8D8F2
	V_MUL_F32_e32 v113, v126, v108                                                  ; 10E2D97E
	V_MOV_B32_e32 v114, 3.073567e-01                                                ; 7EE402FF 3E9D5DDD
	V_MAD_F32 v6, v113, v114, v6, 0, 0, 0, 0                                        ; D2820006 041AE571
	V_SUB_F32_e32 v129, v124, v1                                                    ; 0902037C
	V_SUB_F32_e32 v128, v123, v0                                                    ; 0900017B
	IMAGE_SAMPLE v[130:132], 7, 0, 0, 0, 0, 0, 0, 0, v[128:129], s[16:23], s[12:15] ; F0800700 00648280
	V_SUB_F32_e32 v124, v119, v4                                                    ; 08F80977
	V_SUB_F32_e32 v123, v118, v3                                                    ; 08F60776
	IMAGE_SAMPLE v113, 1, 0, 0, 0, 0, 0, 0, 0, v[123:124], s[24:31], s[0:3]         ; F0800100 0006717B
	S_WAITCNT vmcnt(0)                                                              ; BF8C0770
	V_ADD_F32_e64 v113, v113, 0, 1, 0, 0, 0                                         ; D2060171 02010171
	V_CMP_GE_F32_e64 s[6:7], v113, s4, 0, 0, 0, 0                                   ; D00C0006 02000971
	V_CNDMASK_B32_e64 v113, 0, -1, s[6:7], 0, 0, 0, 0                               ; D2000071 00198280
	V_AND_B32_e32 v113, 1065353216, v113                                            ; 36E2E2F2
	V_MUL_F32_e32 v118, v131, v113                                                  ; 10ECE383
	V_MOV_B32_e32 v119, 2.919889e-01                                                ; 7EEE02FF 3E957F92
	V_MAD_F32 v6, v118, v119, v6, 0, 0, 0, 0                                        ; D2820006 041AEF76
	V_SUB_F32_e32 v134, v129, v1                                                    ; 090C0381
	V_SUB_F32_e32 v133, v128, v0                                                    ; 090A0180
	IMAGE_SAMPLE v[135:137], 7, 0, 0, 0, 0, 0, 0, 0, v[133:134], s[16:23], s[12:15] ; F0800700 00648785
	V_SUB_F32_e32 v129, v124, v4                                                    ; 0902097C
	V_SUB_F32_e32 v128, v123, v3                                                    ; 0900077B
	IMAGE_SAMPLE v118, 1, 0, 0, 0, 0, 0, 0, 0, v[128:129], s[24:31], s[0:3]         ; F0800100 00067680
	S_WAITCNT vmcnt(0)                                                              ; BF8C0770
	V_ADD_F32_e64 v118, v118, 0, 1, 0, 0, 0                                         ; D2060176 02010176
	V_CMP_GE_F32_e64 s[6:7], v118, s4, 0, 0, 0, 0                                   ; D00C0006 02000976
	V_CNDMASK_B32_e64 v118, 0, -1, s[6:7], 0, 0, 0, 0                               ; D2000076 00198280
	V_AND_B32_e32 v118, 1065353216, v118                                            ; 36ECECF2
	V_MUL_F32_e32 v123, v136, v118                                                  ; 10F6ED88
	V_MOV_B32_e32 v124, 2.773895e-01                                                ; 7EF802FF 3E8E05FE
	V_MAD_F32 v6, v123, v124, v6, 0, 0, 0, 0                                        ; D2820006 041AF97B
	V_SUB_F32_e32 v139, v134, v1                                                    ; 09160386
	V_SUB_F32_e32 v138, v133, v0                                                    ; 09140185
	IMAGE_SAMPLE v[140:142], 7, 0, 0, 0, 0, 0, 0, 0, v[138:139], s[16:23], s[12:15] ; F0800700 00648C8A
	V_SUB_F32_e32 v134, v129, v4                                                    ; 090C0981
	V_SUB_F32_e32 v133, v128, v3                                                    ; 090A0780
	IMAGE_SAMPLE v123, 1, 0, 0, 0, 0, 0, 0, 0, v[133:134], s[24:31], s[0:3]         ; F0800100 00067B85
	S_WAITCNT vmcnt(0)                                                              ; BF8C0770
	V_ADD_F32_e64 v123, v123, 0, 1, 0, 0, 0                                         ; D206017B 0201017B
	V_CMP_GE_F32_e64 s[6:7], v123, s4, 0, 0, 0, 0                                   ; D00C0006 0200097B
	V_CNDMASK_B32_e64 v123, 0, -1, s[6:7], 0, 0, 0, 0                               ; D200007B 00198280
	V_AND_B32_e32 v123, 1065353216, v123                                            ; 36F6F6F2
	V_MUL_F32_e32 v128, v141, v123                                                  ; 1100F78D
	V_MOV_B32_e32 v129, 2.635200e-01                                                ; 7F0202FF 3E86EC18
	V_MAD_F32 v6, v128, v129, v6, 0, 0, 0, 0                                        ; D2820006 041B0380
	V_SUB_F32_e32 v144, v139, v1                                                    ; 0920038B
	V_SUB_F32_e32 v143, v138, v0                                                    ; 091E018A
	IMAGE_SAMPLE v[145:147], 7, 0, 0, 0, 0, 0, 0, 0, v[143:144], s[16:23], s[12:15] ; F0800700 0064918F
	V_SUB_F32_e32 v139, v134, v4                                                    ; 09160986
	V_SUB_F32_e32 v138, v133, v3                                                    ; 09140785
	IMAGE_SAMPLE v128, 1, 0, 0, 0, 0, 0, 0, 0, v[138:139], s[24:31], s[0:3]         ; F0800100 0006808A
	S_WAITCNT vmcnt(0)                                                              ; BF8C0770
	V_ADD_F32_e64 v128, v128, 0, 1, 0, 0, 0                                         ; D2060180 02010180
	V_CMP_GE_F32_e64 s[6:7], v128, s4, 0, 0, 0, 0                                   ; D00C0006 02000980
	V_CNDMASK_B32_e64 v128, 0, -1, s[6:7], 0, 0, 0, 0                               ; D2000080 00198280
	V_AND_B32_e32 v128, 1065353216, v128                                            ; 370100F2
	V_MUL_F32_e32 v133, v146, v128                                                  ; 110B0192
	V_MOV_B32_e32 v134, 2.503440e-01                                                ; 7F0C02FF 3E802D17
	V_MAD_F32 v6, v133, v134, v6, 0, 0, 0, 0                                        ; D2820006 041B0D85
	V_SUB_F32_e32 v149, v144, v1                                                    ; 092A0390
	V_SUB_F32_e32 v148, v143, v0                                                    ; 0928018F
	IMAGE_SAMPLE v[150:152], 7, 0, 0, 0, 0, 0, 0, 0, v[148:149], s[16:23], s[12:15] ; F0800700 00649694
	V_SUB_F32_e32 v144, v139, v4                                                    ; 0920098B
	V_SUB_F32_e32 v143, v138, v3                                                    ; 091E078A
	IMAGE_SAMPLE v133, 1, 0, 0, 0, 0, 0, 0, 0, v[143:144], s[24:31], s[0:3]         ; F0800100 0006858F
	S_WAITCNT vmcnt(0)                                                              ; BF8C0770
	V_ADD_F32_e64 v133, v133, 0, 1, 0, 0, 0                                         ; D2060185 02010185
	V_CMP_GE_F32_e64 s[6:7], v133, s4, 0, 0, 0, 0                                   ; D00C0006 02000985
	V_CNDMASK_B32_e64 v133, 0, -1, s[6:7], 0, 0, 0, 0                               ; D2000085 00198280
	V_AND_B32_e32 v133, 1065353216, v133                                            ; 370B0AF2
	V_MUL_F32_e32 v138, v151, v133                                                  ; 11150B97
	V_MOV_B32_e32 v139, 2.378268e-01                                                ; 7F1602FF 3E7388DF
	V_MAD_F32 v6, v138, v139, v6, 0, 0, 0, 0                                        ; D2820006 041B178A
	V_SUB_F32_e32 v154, v149, v1                                                    ; 09340395
	V_SUB_F32_e32 v153, v148, v0                                                    ; 09320194
	IMAGE_SAMPLE v[155:157], 7, 0, 0, 0, 0, 0, 0, 0, v[153:154], s[16:23], s[12:15] ; F0800700 00649B99
	V_SUB_F32_e32 v149, v144, v4                                                    ; 092A0990
	V_SUB_F32_e32 v148, v143, v3                                                    ; 0928078F
	IMAGE_SAMPLE v138, 1, 0, 0, 0, 0, 0, 0, 0, v[148:149], s[24:31], s[0:3]         ; F0800100 00068A94
	S_WAITCNT vmcnt(0)                                                              ; BF8C0770
	V_ADD_F32_e64 v138, v138, 0, 1, 0, 0, 0                                         ; D206018A 0201018A
	V_CMP_GE_F32_e64 s[6:7], v138, s4, 0, 0, 0, 0                                   ; D00C0006 0200098A
	V_CNDMASK_B32_e64 v138, 0, -1, s[6:7], 0, 0, 0, 0                               ; D200008A 00198280
	V_AND_B32_e32 v138, 1065353216, v138                                            ; 371514F2
	V_MUL_F32_e32 v143, v156, v138                                                  ; 111F159C
	V_MOV_B32_e32 v144, 2.259355e-01                                                ; 7F2002FF 3E675BA0
	V_MAD_F32 v6, v143, v144, v6, 0, 0, 0, 0                                        ; D2820006 041B218F
	V_SUB_F32_e32 v159, v154, v1                                                    ; 093E039A
	V_SUB_F32_e32 v158, v153, v0                                                    ; 093C0199
	IMAGE_SAMPLE v[160:162], 7, 0, 0, 0, 0, 0, 0, 0, v[158:159], s[16:23], s[12:15] ; F0800700 0064A09E
	V_SUB_F32_e32 v154, v149, v4                                                    ; 09340995
	V_SUB_F32_e32 v153, v148, v3                                                    ; 09320794
	IMAGE_SAMPLE v143, 1, 0, 0, 0, 0, 0, 0, 0, v[153:154], s[24:31], s[0:3]         ; F0800100 00068F99
	S_WAITCNT vmcnt(0)                                                              ; BF8C0770
	V_ADD_F32_e64 v143, v143, 0, 1, 0, 0, 0                                         ; D206018F 0201018F
	V_CMP_GE_F32_e64 s[6:7], v143, s4, 0, 0, 0, 0                                   ; D00C0006 0200098F
	V_CNDMASK_B32_e64 v143, 0, -1, s[6:7], 0, 0, 0, 0                               ; D200008F 00198280
	V_AND_B32_e32 v143, 1065353216, v143                                            ; 371F1EF2
	V_MUL_F32_e32 v148, v161, v143                                                  ; 11291FA1
	V_MOV_B32_e32 v149, 2.146387e-01                                                ; 7F2A02FF 3E5BCA3E
	V_MAD_F32 v6, v148, v149, v6, 0, 0, 0, 0                                        ; D2820006 041B2B94
	V_SUB_F32_e32 v164, v159, v1                                                    ; 0948039F
	V_SUB_F32_e32 v163, v158, v0                                                    ; 0946019E
	IMAGE_SAMPLE v[165:167], 7, 0, 0, 0, 0, 0, 0, 0, v[163:164], s[16:23], s[12:15] ; F0800700 0064A5A3
	V_SUB_F32_e32 v159, v154, v4                                                    ; 093E099A
	V_SUB_F32_e32 v158, v153, v3                                                    ; 093C0799
	IMAGE_SAMPLE v148, 1, 0, 0, 0, 0, 0, 0, 0, v[158:159], s[24:31], s[0:3]         ; F0800100 0006949E
	S_WAITCNT vmcnt(0)                                                              ; BF8C0770
	V_ADD_F32_e64 v148, v148, 0, 1, 0, 0, 0                                         ; D2060194 02010194
	V_CMP_GE_F32_e64 s[6:7], v148, s4, 0, 0, 0, 0                                   ; D00C0006 02000994
	V_CNDMASK_B32_e64 v148, 0, -1, s[6:7], 0, 0, 0, 0                               ; D2000094 00198280
	V_AND_B32_e32 v148, 1065353216, v148                                            ; 372928F2
	V_MUL_F32_e32 v153, v166, v148                                                  ; 113329A6
	V_MOV_B32_e32 v154, 2.039067e-01                                                ; 7F3402FF 3E50CCEE
	V_MAD_F32 v6, v153, v154, v6, 0, 0, 0, 0                                        ; D2820006 041B3599
	V_SUB_F32_e32 v169, v164, v1                                                    ; 095203A4
	V_SUB_F32_e32 v168, v163, v0                                                    ; 095001A3
	IMAGE_SAMPLE v[170:172], 7, 0, 0, 0, 0, 0, 0, 0, v[168:169], s[16:23], s[12:15] ; F0800700 0064AAA8
	V_SUB_F32_e32 v164, v159, v4                                                    ; 0948099F
	V_SUB_F32_e32 v163, v158, v3                                                    ; 0946079E
	IMAGE_SAMPLE v153, 1, 0, 0, 0, 0, 0, 0, 0, v[163:164], s[24:31], s[0:3]         ; F0800100 000699A3
	S_WAITCNT vmcnt(0)                                                              ; BF8C0770
	V_ADD_F32_e64 v153, v153, 0, 1, 0, 0, 0                                         ; D2060199 02010199
	V_CMP_GE_F32_e64 s[6:7], v153, s4, 0, 0, 0, 0                                   ; D00C0006 02000999
	V_CNDMASK_B32_e64 v153, 0, -1, s[6:7], 0, 0, 0, 0                               ; D2000099 00198280
	V_AND_B32_e32 v153, 1065353216, v153                                            ; 373332F2
	V_MUL_F32_e32 v158, v171, v153                                                  ; 113D33AB
	V_MOV_B32_e32 v159, 1.937114e-01                                                ; 7F3E02FF 3E465C48
	V_MAD_F32 v6, v158, v159, v6, 0, 0, 0, 0                                        ; D2820006 041B3F9E
	V_SUB_F32_e32 v174, v169, v1                                                    ; 095C03A9
	V_SUB_F32_e32 v173, v168, v0                                                    ; 095A01A8
	IMAGE_SAMPLE v[175:177], 7, 0, 0, 0, 0, 0, 0, 0, v[173:174], s[16:23], s[12:15] ; F0800700 0064AFAD
	V_SUB_F32_e32 v169, v164, v4                                                    ; 095209A4
	V_SUB_F32_e32 v168, v163, v3                                                    ; 095007A3
	IMAGE_SAMPLE v158, 1, 0, 0, 0, 0, 0, 0, 0, v[168:169], s[24:31], s[0:3]         ; F0800100 00069EA8
	S_WAITCNT vmcnt(0)                                                              ; BF8C0770
	V_ADD_F32_e64 v158, v158, 0, 1, 0, 0, 0                                         ; D206019E 0201019E
	V_CMP_GE_F32_e64 s[6:7], v158, s4, 0, 0, 0, 0                                   ; D00C0006 0200099E
	V_CNDMASK_B32_e64 v158, 0, -1, s[6:7], 0, 0, 0, 0                               ; D200009E 00198280
	V_AND_B32_e32 v158, 1065353216, v158                                            ; 373D3CF2
	V_MUL_F32_e32 v163, v176, v158                                                  ; 11473DB0
	V_MOV_B32_e32 v164, 1.840258e-01                                                ; 7F4802FF 3E3C7144
	V_MAD_F32 v6, v163, v164, v6, 0, 0, 0, 0                                        ; D2820006 041B49A3
	V_SUB_F32_e32 v179, v174, v1                                                    ; 096603AE
	V_SUB_F32_e32 v178, v173, v0                                                    ; 096401AD
	IMAGE_SAMPLE v[178:180], 7, 0, 0, 0, 0, 0, 0, 0, v[178:179], s[16:23], s[12:15] ; F0800700 0064B2B2
	V_SUB_F32_e32 v1, v169, v4                                                      ; 080209A9
	V_SUB_F32_e32 v0, v168, v3                                                      ; 080007A8
	IMAGE_SAMPLE v0, 1, 0, 0, 0, 0, 0, 0, 0, v[0:1], s[24:31], s[0:3]               ; F0800100 00060000
	S_WAITCNT vmcnt(0)                                                              ; BF8C0770
	V_ADD_F32_e64 v0, v0, 0, 1, 0, 0, 0                                             ; D2060100 02010100
	V_CMP_GE_F32_e64 s[0:1], v0, s4, 0, 0, 0, 0                                     ; D00C0000 02000900
	V_CNDMASK_B32_e64 v0, 0, -1, s[0:1], 0, 0, 0, 0                                 ; D2000000 00018280
	V_AND_B32_e32 v0, 1065353216, v0                                                ; 360000F2
	V_MUL_F32_e32 v1, v179, v0                                                      ; 100201B3
	V_MOV_B32_e32 v3, 1.748245e-01                                                  ; 7E0602FF 3E330534
	V_MAD_F32 v1, v1, v3, v6, 0, 0, 0, 0                                            ; D2820001 041A0701
	S_BUFFER_LOAD_DWORD s0, s[8:11], 9                                              ; C2000909
	S_WAITCNT lgkmcnt(0)                                                            ; BF8C007F
	V_MUL_F32_e32 v1, s0, v1                                                        ; 10020200
	V_MUL_F32_e32 v4, v9, v2                                                        ; 10080509
	V_MUL_F32_e32 v4, 9.500000e-01, v4                                              ; 100808FF 3F733333
	V_MAD_F32 v4, v17, v5, v4, 0, 0, 0, 0                                           ; D2820004 04120B11
	V_MUL_F32_e32 v6, v20, v14                                                      ; 100C1D14
	V_MAD_F32 v4, v6, v16, v4, 0, 0, 0, 0                                           ; D2820004 04122106
	V_MUL_F32_e32 v6, v25, v7                                                       ; 100C0F19
	V_MAD_F32 v4, v6, v15, v4, 0, 0, 0, 0                                           ; D2820004 04121F06
	V_MUL_F32_e32 v6, v30, v8                                                       ; 100C111E
	V_MAD_F32 v4, v6, v13, v4, 0, 0, 0, 0                                           ; D2820004 04121B06
	V_MUL_F32_e32 v6, v35, v12                                                      ; 100C1923
	V_MAD_F32 v4, v6, v24, v4, 0, 0, 0, 0                                           ; D2820004 04123106
	V_MUL_F32_e32 v6, v40, v23                                                      ; 100C2F28
	V_MAD_F32 v4, v6, v29, v4, 0, 0, 0, 0                                           ; D2820004 04123B06
	V_MUL_F32_e32 v6, v45, v28                                                      ; 100C392D
	V_MAD_F32 v4, v6, v34, v4, 0, 0, 0, 0                                           ; D2820004 04124506
	V_MUL_F32_e32 v6, v50, v33                                                      ; 100C4332
	V_MAD_F32 v4, v6, v39, v4, 0, 0, 0, 0                                           ; D2820004 04124F06
	V_MUL_F32_e32 v6, v55, v38                                                      ; 100C4D37
	V_MAD_F32 v4, v6, v44, v4, 0, 0, 0, 0                                           ; D2820004 04125906
	V_MUL_F32_e32 v6, v60, v43                                                      ; 100C573C
	V_MAD_F32 v4, v6, v49, v4, 0, 0, 0, 0                                           ; D2820004 04126306
	V_MUL_F32_e32 v6, v65, v48                                                      ; 100C6141
	V_MAD_F32 v4, v6, v54, v4, 0, 0, 0, 0                                           ; D2820004 04126D06
	V_MUL_F32_e32 v6, v70, v53                                                      ; 100C6B46
	V_MAD_F32 v4, v6, v59, v4, 0, 0, 0, 0                                           ; D2820004 04127706
	V_MUL_F32_e32 v6, v75, v58                                                      ; 100C754B
	V_MAD_F32 v4, v6, v64, v4, 0, 0, 0, 0                                           ; D2820004 04128106
	V_MUL_F32_e32 v6, v80, v63                                                      ; 100C7F50
	V_MAD_F32 v4, v6, v69, v4, 0, 0, 0, 0                                           ; D2820004 04128B06
	V_MUL_F32_e32 v6, v85, v68                                                      ; 100C8955
	V_MAD_F32 v4, v6, v74, v4, 0, 0, 0, 0                                           ; D2820004 04129506
	V_MUL_F32_e32 v6, v90, v73                                                      ; 100C935A
	V_MAD_F32 v4, v6, v79, v4, 0, 0, 0, 0                                           ; D2820004 04129F06
	V_MUL_F32_e32 v6, v95, v78                                                      ; 100C9D5F
	V_MAD_F32 v4, v6, v84, v4, 0, 0, 0, 0                                           ; D2820004 0412A906
	V_MUL_F32_e32 v6, v100, v83                                                     ; 100CA764
	V_MAD_F32 v4, v6, v89, v4, 0, 0, 0, 0                                           ; D2820004 0412B306
	V_MUL_F32_e32 v6, v105, v88                                                     ; 100CB169
	V_MAD_F32 v4, v6, v94, v4, 0, 0, 0, 0                                           ; D2820004 0412BD06
	V_MUL_F32_e32 v6, v110, v93                                                     ; 100CBB6E
	V_MAD_F32 v4, v6, v99, v4, 0, 0, 0, 0                                           ; D2820004 0412C706
	V_MUL_F32_e32 v6, v115, v98                                                     ; 100CC573
	V_MAD_F32 v4, v6, v104, v4, 0, 0, 0, 0                                          ; D2820004 0412D106
	V_MUL_F32_e32 v6, v120, v103                                                    ; 100CCF78
	V_MAD_F32 v4, v6, v109, v4, 0, 0, 0, 0                                          ; D2820004 0412DB06
	V_MUL_F32_e32 v6, v125, v108                                                    ; 100CD97D
	V_MAD_F32 v4, v6, v114, v4, 0, 0, 0, 0                                          ; D2820004 0412E506
	V_MUL_F32_e32 v6, v130, v113                                                    ; 100CE382
	V_MAD_F32 v4, v6, v119, v4, 0, 0, 0, 0                                          ; D2820004 0412EF06
	V_MUL_F32_e32 v6, v135, v118                                                    ; 100CED87
	V_MAD_F32 v4, v6, v124, v4, 0, 0, 0, 0                                          ; D2820004 0412F906
	V_MUL_F32_e32 v6, v140, v123                                                    ; 100CF78C
	V_MAD_F32 v4, v6, v129, v4, 0, 0, 0, 0                                          ; D2820004 04130306
	V_MUL_F32_e32 v6, v145, v128                                                    ; 100D0191
	V_MAD_F32 v4, v6, v134, v4, 0, 0, 0, 0                                          ; D2820004 04130D06
	V_MUL_F32_e32 v6, v150, v133                                                    ; 100D0B96
	V_MAD_F32 v4, v6, v139, v4, 0, 0, 0, 0                                          ; D2820004 04131706
	V_MUL_F32_e32 v6, v155, v138                                                    ; 100D159B
	V_MAD_F32 v4, v6, v144, v4, 0, 0, 0, 0                                          ; D2820004 04132106
	V_MUL_F32_e32 v6, v160, v143                                                    ; 100D1FA0
	V_MAD_F32 v4, v6, v149, v4, 0, 0, 0, 0                                          ; D2820004 04132B06
	V_MUL_F32_e32 v6, v165, v148                                                    ; 100D29A5
	V_MAD_F32 v4, v6, v154, v4, 0, 0, 0, 0                                          ; D2820004 04133506
	V_MUL_F32_e32 v6, v170, v153                                                    ; 100D33AA
	V_MAD_F32 v4, v6, v159, v4, 0, 0, 0, 0                                          ; D2820004 04133F06
	V_MUL_F32_e32 v6, v175, v158                                                    ; 100D3DAF
	V_MAD_F32 v4, v6, v164, v4, 0, 0, 0, 0                                          ; D2820004 04134906
	V_MUL_F32_e32 v6, v178, v0                                                      ; 100C01B2
	V_MAD_F32 v4, v6, v3, v4, 0, 0, 0, 0                                            ; D2820004 04120706
	S_BUFFER_LOAD_DWORD s0, s[8:11], 8                                              ; C2000908
	S_WAITCNT lgkmcnt(0)                                                            ; BF8C007F
	V_MUL_F32_e32 v4, s0, v4                                                        ; 10080800
	V_CVT_PKRTZ_F16_F32_e32 v1, v4, v1                                              ; 5E020304
	V_MUL_F32_e32 v2, v11, v2                                                       ; 1004050B
	V_MUL_F32_e32 v2, 9.500000e-01, v2                                              ; 100404FF 3F733333
	V_MAD_F32 v2, v19, v5, v2, 0, 0, 0, 0                                           ; D2820002 040A0B13
	V_MUL_F32_e32 v4, v22, v14                                                      ; 10081D16
	V_MAD_F32 v2, v4, v16, v2, 0, 0, 0, 0                                           ; D2820002 040A2104
	V_MUL_F32_e32 v4, v27, v7                                                       ; 10080F1B
	V_MAD_F32 v2, v4, v15, v2, 0, 0, 0, 0                                           ; D2820002 040A1F04
	V_MUL_F32_e32 v4, v32, v8                                                       ; 10081120
	V_MAD_F32 v2, v4, v13, v2, 0, 0, 0, 0                                           ; D2820002 040A1B04
	V_MUL_F32_e32 v4, v37, v12                                                      ; 10081925
	V_MAD_F32 v2, v4, v24, v2, 0, 0, 0, 0                                           ; D2820002 040A3104
	V_MUL_F32_e32 v4, v42, v23                                                      ; 10082F2A
	V_MAD_F32 v2, v4, v29, v2, 0, 0, 0, 0                                           ; D2820002 040A3B04
	V_MUL_F32_e32 v4, v47, v28                                                      ; 1008392F
	V_MAD_F32 v2, v4, v34, v2, 0, 0, 0, 0                                           ; D2820002 040A4504
	V_MUL_F32_e32 v4, v52, v33                                                      ; 10084334
	V_MAD_F32 v2, v4, v39, v2, 0, 0, 0, 0                                           ; D2820002 040A4F04
	V_MUL_F32_e32 v4, v57, v38                                                      ; 10084D39
	V_MAD_F32 v2, v4, v44, v2, 0, 0, 0, 0                                           ; D2820002 040A5904
	V_MUL_F32_e32 v4, v62, v43                                                      ; 1008573E
	V_MAD_F32 v2, v4, v49, v2, 0, 0, 0, 0                                           ; D2820002 040A6304
	V_MUL_F32_e32 v4, v67, v48                                                      ; 10086143
	V_MAD_F32 v2, v4, v54, v2, 0, 0, 0, 0                                           ; D2820002 040A6D04
	V_MUL_F32_e32 v4, v72, v53                                                      ; 10086B48
	V_MAD_F32 v2, v4, v59, v2, 0, 0, 0, 0                                           ; D2820002 040A7704
	V_MUL_F32_e32 v4, v77, v58                                                      ; 1008754D
	V_MAD_F32 v2, v4, v64, v2, 0, 0, 0, 0                                           ; D2820002 040A8104
	V_MUL_F32_e32 v4, v82, v63                                                      ; 10087F52
	V_MAD_F32 v2, v4, v69, v2, 0, 0, 0, 0                                           ; D2820002 040A8B04
	V_MUL_F32_e32 v4, v87, v68                                                      ; 10088957
	V_MAD_F32 v2, v4, v74, v2, 0, 0, 0, 0                                           ; D2820002 040A9504
	V_MUL_F32_e32 v4, v92, v73                                                      ; 1008935C
	V_MAD_F32 v2, v4, v79, v2, 0, 0, 0, 0                                           ; D2820002 040A9F04
	V_MUL_F32_e32 v4, v97, v78                                                      ; 10089D61
	V_MAD_F32 v2, v4, v84, v2, 0, 0, 0, 0                                           ; D2820002 040AA904
	V_MUL_F32_e32 v4, v102, v83                                                     ; 1008A766
	V_MAD_F32 v2, v4, v89, v2, 0, 0, 0, 0                                           ; D2820002 040AB304
	V_MUL_F32_e32 v4, v107, v88                                                     ; 1008B16B
	V_MAD_F32 v2, v4, v94, v2, 0, 0, 0, 0                                           ; D2820002 040ABD04
	V_MUL_F32_e32 v4, v112, v93                                                     ; 1008BB70
	V_MAD_F32 v2, v4, v99, v2, 0, 0, 0, 0                                           ; D2820002 040AC704
	V_MUL_F32_e32 v4, v117, v98                                                     ; 1008C575
	V_MAD_F32 v2, v4, v104, v2, 0, 0, 0, 0                                          ; D2820002 040AD104
	V_MUL_F32_e32 v4, v122, v103                                                    ; 1008CF7A
	V_MAD_F32 v2, v4, v109, v2, 0, 0, 0, 0                                          ; D2820002 040ADB04
	V_MUL_F32_e32 v4, v127, v108                                                    ; 1008D97F
	V_MAD_F32 v2, v4, v114, v2, 0, 0, 0, 0                                          ; D2820002 040AE504
	V_MUL_F32_e32 v4, v132, v113                                                    ; 1008E384
	V_MAD_F32 v2, v4, v119, v2, 0, 0, 0, 0                                          ; D2820002 040AEF04
	V_MUL_F32_e32 v4, v137, v118                                                    ; 1008ED89
	V_MAD_F32 v2, v4, v124, v2, 0, 0, 0, 0                                          ; D2820002 040AF904
	V_MUL_F32_e32 v4, v142, v123                                                    ; 1008F78E
	V_MAD_F32 v2, v4, v129, v2, 0, 0, 0, 0                                          ; D2820002 040B0304
	V_MUL_F32_e32 v4, v147, v128                                                    ; 10090193
	V_MAD_F32 v2, v4, v134, v2, 0, 0, 0, 0                                          ; D2820002 040B0D04
	V_MUL_F32_e32 v4, v152, v133                                                    ; 10090B98
	V_MAD_F32 v2, v4, v139, v2, 0, 0, 0, 0                                          ; D2820002 040B1704
	V_MUL_F32_e32 v4, v157, v138                                                    ; 1009159D
	V_MAD_F32 v2, v4, v144, v2, 0, 0, 0, 0                                          ; D2820002 040B2104
	V_MUL_F32_e32 v4, v162, v143                                                    ; 10091FA2
	V_MAD_F32 v2, v4, v149, v2, 0, 0, 0, 0                                          ; D2820002 040B2B04
	V_MUL_F32_e32 v4, v167, v148                                                    ; 100929A7
	V_MAD_F32 v2, v4, v154, v2, 0, 0, 0, 0                                          ; D2820002 040B3504
	V_MUL_F32_e32 v4, v172, v153                                                    ; 100933AC
	V_MAD_F32 v2, v4, v159, v2, 0, 0, 0, 0                                          ; D2820002 040B3F04
	V_MUL_F32_e32 v4, v177, v158                                                    ; 10093DB1
	V_MAD_F32 v2, v4, v164, v2, 0, 0, 0, 0                                          ; D2820002 040B4904
	V_MUL_F32_e32 v0, v180, v0                                                      ; 100001B4
	V_MAD_F32 v0, v0, v3, v2, 0, 0, 0, 0                                            ; D2820000 040A0700
	S_BUFFER_LOAD_DWORD s0, s[8:11], 10                                             ; C200090A
	S_WAITCNT lgkmcnt(0)                                                            ; BF8C007F
	V_MUL_F32_e32 v0, s0, v0                                                        ; 10000000
	V_CVT_PKRTZ_F16_F32_e64 v0, v0, 0.000000e+00, 0, 0, 0, 0                        ; D25E0000 02010100
	EXP 15, 0, 1, 1, 1, v1, v0, v1, v0                                              ; F8001C0F 00010001
	S_ENDPGM                                                                        ; BF810000

VERT
DCL IN[0]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[19]
DCL CONST[0..1]
DCL TEMP[0..2], LOCAL
IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
  0: MOV TEMP[0].zw, IMM[0].yyxy
  1: MOV TEMP[0].xy, IN[0].xyxx
  2: MAD TEMP[1].xy, IN[0].zwww, CONST[0].xyyy, CONST[0].zwww
  3: MAD TEMP[2].xy, IN[0].zwww, CONST[1].xyyy, CONST[1].zwww
  4: MOV TEMP[1].zw, TEMP[2].yyxy
  5: MOV OUT[1], TEMP[1]
  6: MOV OUT[0], TEMP[0]
  7: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0)
  %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4)
  %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8)
  %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12)
  %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16)
  %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20)
  %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24)
  %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28)
  %20 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %21, i32 0, i32 %6)
  %23 = extractelement <4 x float> %22, i32 0
  %24 = extractelement <4 x float> %22, i32 1
  %25 = extractelement <4 x float> %22, i32 2
  %26 = extractelement <4 x float> %22, i32 3
  %27 = fmul float %25, %12
  %28 = fadd float %27, %14
  %29 = fmul float %26, %13
  %30 = fadd float %29, %15
  %31 = fmul float %25, %16
  %32 = fadd float %31, %18
  %33 = fmul float %26, %17
  %34 = fadd float %33, %19
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %28, float %30, float %32, float %34)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %23, float %24, float 0.000000e+00, float 1.000000e+00)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg6

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%23](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%11](align=8)(tbaa=!"const")
	S_WAITCNT 112
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 7; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR4<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 5; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR3, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 6; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 4; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR2, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 3; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR3, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 0; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR8<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR2, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 32, 0, 0, 0, %VGPR7<kill>, %VGPR6<kill>, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>
	S_WAITCNT 1807
	%VGPR4<def> = V_MOV_B32_e32 1.000000e+00, %EXEC<imp-use>
	%VGPR5<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR1, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_LOAD_DWORDX4 s[4:7], s[6:7], 0               ; C0820700
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	BUFFER_LOAD_FORMAT_XYZW v[0:3], s[4:7][v0] + 0 ; E00C2000 80010000
	S_LOAD_DWORDX4 s[0:3], s[0:1], 0               ; C0800100
	S_WAITCNT vmcnt(0) lgkmcnt(0)                  ; BF8C0070
	S_BUFFER_LOAD_DWORD s4, s[0:3], 7              ; C2020107
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v4, s4                           ; 7E080204
	S_BUFFER_LOAD_DWORD s4, s[0:3], 5              ; C2020105
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v5, s4                           ; 7E0A0204
	V_MAD_F32 v4, v3, v5, v4, 0, 0, 0, 0           ; D2820004 04120B03
	S_BUFFER_LOAD_DWORD s4, s[0:3], 6              ; C2020106
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v5, s4                           ; 7E0A0204
	S_BUFFER_LOAD_DWORD s4, s[0:3], 4              ; C2020104
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v6, s4                           ; 7E0C0204
	V_MAD_F32 v5, v2, v6, v5, 0, 0, 0, 0           ; D2820005 04160D02
	S_BUFFER_LOAD_DWORD s4, s[0:3], 3              ; C2020103
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v6, s4                           ; 7E0C0204
	S_BUFFER_LOAD_DWORD s4, s[0:3], 1              ; C2020101
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v7, s4                           ; 7E0E0204
	V_MAD_F32 v6, v3, v7, v6, 0, 0, 0, 0           ; D2820006 041A0F03
	S_BUFFER_LOAD_DWORD s4, s[0:3], 2              ; C2020102
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v7, s4                           ; 7E0E0204
	S_BUFFER_LOAD_DWORD s0, s[0:3], 0              ; C2000100
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v8, s0                           ; 7E100200
	V_MAD_F32 v7, v2, v8, v7, 0, 0, 0, 0           ; D2820007 041E1102
	EXP 15, 32, 0, 0, 0, v7, v6, v5, v4            ; F800020F 04050607
	S_WAITCNT expcnt(0)                            ; BF8C070F
	V_MOV_B32_e32 v4, 1.000000e+00                 ; 7E0802F2
	V_MOV_B32_e32 v5, 0.000000e+00                 ; 7E0A0280
	EXP 15, 12, 0, 1, 0, v0, v1, v5, v4            ; F80008CF 04050100
	S_ENDPGM                                       ; BF810000

FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL CONST[0]
DCL TEMP[0], LOCAL
  0: MOV TEMP[0].xy, IN[0].xyyy
  1: TEX TEMP[0], TEMP[0], SAMP[0], 2D
  2: MUL TEMP[0], CONST[0], TEMP[0]
  3: MOV OUT[0], TEMP[0]
  4: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %21 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
  %22 = load <16 x i8> addrspace(2)* %21, !tbaa !0
  %23 = call float @llvm.SI.load.const(<16 x i8> %22, i32 0)
  %24 = call float @llvm.SI.load.const(<16 x i8> %22, i32 4)
  %25 = call float @llvm.SI.load.const(<16 x i8> %22, i32 8)
  %26 = call float @llvm.SI.load.const(<16 x i8> %22, i32 12)
  %27 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0
  %28 = load <32 x i8> addrspace(2)* %27, !tbaa !0
  %29 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0
  %30 = load <16 x i8> addrspace(2)* %29, !tbaa !0
  %31 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %4, <2 x i32> %6)
  %32 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %4, <2 x i32> %6)
  %33 = bitcast float %31 to i32
  %34 = bitcast float %32 to i32
  %35 = insertelement <2 x i32> undef, i32 %33, i32 0
  %36 = insertelement <2 x i32> %35, i32 %34, i32 1
  %37 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %36, <32 x i8> %28, <16 x i8> %30, i32 2)
  %38 = extractelement <4 x float> %37, i32 0
  %39 = extractelement <4 x float> %37, i32 1
  %40 = extractelement <4 x float> %37, i32 2
  %41 = extractelement <4 x float> %37, i32 3
  %42 = fmul float %23, %38
  %43 = fmul float %24, %39
  %44 = fmul float %25, %40
  %45 = fmul float %26, %41
  %46 = call i32 @llvm.SI.packf16(float %42, float %43)
  %47 = bitcast i32 %46 to float
  %48 = call i32 @llvm.SI.packf16(float %44, float %45)
  %49 = bitcast i32 %48 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %47, float %49, float %47, float %49)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR7 in %vreg4, %VGPR0 in %vreg5, %VGPR1 in %vreg6

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR7 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR7
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-def>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%32](align=8)(tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%29](tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = IMAGE_SAMPLE_V4_V2 15, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%22](align=8)(tbaa=!"const")
	S_WAITCNT 112
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 3; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR4<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR3, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>
	%VGPR4<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR1, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 0; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR0<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR0, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0<kill>, %VGPR5<kill>, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR0<kill>, %VGPR4<kill>, %VGPR0, %VGPR4, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_WQM_B64 exec, exec                                                    ; BEFE0A7E
	S_MOV_B32 m0, s7                                                        ; BEFC0307
	V_INTERP_P1_F32 v3, v0, 1, 0, [m0]                                      ; C80C0100
	V_INTERP_P2_F32 v3, [v3], v1, 1, 0, [m0]                                ; C80D0101
	V_INTERP_P1_F32 v2, v0, 0, 0, [m0]                                      ; C8080000
	V_INTERP_P2_F32 v2, [v2], v1, 0, 0, [m0]                                ; C8090001
	S_LOAD_DWORDX4 s[8:11], s[2:3], 0                                       ; C0840300
	S_LOAD_DWORDX8 s[12:19], s[4:5], 0                                      ; C0C60500
	S_WAITCNT lgkmcnt(0)                                                    ; BF8C007F
	IMAGE_SAMPLE v[0:3], 15, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[12:19], s[8:11] ; F0800F00 00430002
	S_LOAD_DWORDX4 s[0:3], s[0:1], 0                                        ; C0800100
	S_WAITCNT vmcnt(0) lgkmcnt(0)                                           ; BF8C0070
	S_BUFFER_LOAD_DWORD s4, s[0:3], 3                                       ; C2020103
	S_WAITCNT lgkmcnt(0)                                                    ; BF8C007F
	V_MUL_F32_e32 v4, s4, v3                                                ; 10080604
	S_BUFFER_LOAD_DWORD s4, s[0:3], 2                                       ; C2020102
	S_WAITCNT lgkmcnt(0)                                                    ; BF8C007F
	V_MUL_F32_e32 v5, s4, v2                                                ; 100A0404
	V_CVT_PKRTZ_F16_F32_e32 v4, v5, v4                                      ; 5E080905
	S_BUFFER_LOAD_DWORD s4, s[0:3], 1                                       ; C2020101
	S_WAITCNT lgkmcnt(0)                                                    ; BF8C007F
	V_MUL_F32_e32 v5, s4, v1                                                ; 100A0204
	S_BUFFER_LOAD_DWORD s0, s[0:3], 0                                       ; C2000100
	S_WAITCNT lgkmcnt(0)                                                    ; BF8C007F
	V_MUL_F32_e32 v0, s0, v0                                                ; 10000000
	V_CVT_PKRTZ_F16_F32_e32 v0, v0, v5                                      ; 5E000B00
	EXP 15, 0, 1, 1, 1, v0, v4, v0, v4                                      ; F8001C0F 04000400
	S_ENDPGM                                                                ; BF810000

VERT
DCL IN[0]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[19]
DCL CONST[0..1]
DCL TEMP[0..2], LOCAL
IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
  0: MOV TEMP[0].zw, IMM[0].yyxy
  1: MOV TEMP[0].xy, IN[0].xyxx
  2: MAD TEMP[1].xy, IN[0].zwww, CONST[0].xyyy, CONST[0].zwww
  3: MAD TEMP[2].xy, IN[0].zwww, CONST[1].xyyy, CONST[1].zwww
  4: MOV TEMP[1].zw, TEMP[2].yyxy
  5: MOV OUT[1], TEMP[1]
  6: MOV OUT[0], TEMP[0]
  7: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0)
  %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4)
  %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8)
  %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12)
  %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16)
  %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20)
  %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24)
  %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28)
  %20 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %21, i32 0, i32 %6)
  %23 = extractelement <4 x float> %22, i32 0
  %24 = extractelement <4 x float> %22, i32 1
  %25 = extractelement <4 x float> %22, i32 2
  %26 = extractelement <4 x float> %22, i32 3
  %27 = fmul float %25, %12
  %28 = fadd float %27, %14
  %29 = fmul float %26, %13
  %30 = fadd float %29, %15
  %31 = fmul float %25, %16
  %32 = fadd float %31, %18
  %33 = fmul float %26, %17
  %34 = fadd float %33, %19
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %28, float %30, float %32, float %34)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %23, float %24, float 0.000000e+00, float 1.000000e+00)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg6

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%23](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%11](align=8)(tbaa=!"const")
	S_WAITCNT 112
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 7; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR4<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 5; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR3, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 6; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 4; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR2, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 3; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR3, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 0; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR8<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR2, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 32, 0, 0, 0, %VGPR7<kill>, %VGPR6<kill>, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>
	S_WAITCNT 1807
	%VGPR4<def> = V_MOV_B32_e32 1.000000e+00, %EXEC<imp-use>
	%VGPR5<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR1, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_LOAD_DWORDX4 s[4:7], s[6:7], 0               ; C0820700
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	BUFFER_LOAD_FORMAT_XYZW v[0:3], s[4:7][v0] + 0 ; E00C2000 80010000
	S_LOAD_DWORDX4 s[0:3], s[0:1], 0               ; C0800100
	S_WAITCNT vmcnt(0) lgkmcnt(0)                  ; BF8C0070
	S_BUFFER_LOAD_DWORD s4, s[0:3], 7              ; C2020107
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v4, s4                           ; 7E080204
	S_BUFFER_LOAD_DWORD s4, s[0:3], 5              ; C2020105
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v5, s4                           ; 7E0A0204
	V_MAD_F32 v4, v3, v5, v4, 0, 0, 0, 0           ; D2820004 04120B03
	S_BUFFER_LOAD_DWORD s4, s[0:3], 6              ; C2020106
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v5, s4                           ; 7E0A0204
	S_BUFFER_LOAD_DWORD s4, s[0:3], 4              ; C2020104
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v6, s4                           ; 7E0C0204
	V_MAD_F32 v5, v2, v6, v5, 0, 0, 0, 0           ; D2820005 04160D02
	S_BUFFER_LOAD_DWORD s4, s[0:3], 3              ; C2020103
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v6, s4                           ; 7E0C0204
	S_BUFFER_LOAD_DWORD s4, s[0:3], 1              ; C2020101
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v7, s4                           ; 7E0E0204
	V_MAD_F32 v6, v3, v7, v6, 0, 0, 0, 0           ; D2820006 041A0F03
	S_BUFFER_LOAD_DWORD s4, s[0:3], 2              ; C2020102
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v7, s4                           ; 7E0E0204
	S_BUFFER_LOAD_DWORD s0, s[0:3], 0              ; C2000100
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v8, s0                           ; 7E100200
	V_MAD_F32 v7, v2, v8, v7, 0, 0, 0, 0           ; D2820007 041E1102
	EXP 15, 32, 0, 0, 0, v7, v6, v5, v4            ; F800020F 04050607
	S_WAITCNT expcnt(0)                            ; BF8C070F
	V_MOV_B32_e32 v4, 1.000000e+00                 ; 7E0802F2
	V_MOV_B32_e32 v5, 0.000000e+00                 ; 7E0A0280
	EXP 15, 12, 0, 1, 0, v0, v1, v5, v4            ; F80008CF 04050100
	S_ENDPGM                                       ; BF810000

FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL CONST[0..2]
DCL TEMP[0..21], LOCAL
IMM[0] FLT32 {    0.0000,     0.2990,     0.5870,     0.1140}
IMM[1] FLT32 {    0.0000,     1.0000,    -1.0000,     0.0833}
IMM[2] FLT32 {    0.1660,    -2.0000,     2.0000,     0.0833}
IMM[3] FLT32 {    0.5000,     3.0000,     0.2500,     1.5000}
IMM[4] FLT32 {    4.0000,     8.0000,     0.0000,     0.0000}
  0: MOV TEMP[0].xy, IN[0].xyxx
  1: MOV TEMP[1].xy, IN[0].xyyy
  2: MOV TEMP[1].w, IMM[0].xxxx
  3: TXL TEMP[1], TEMP[1], SAMP[0], 2D
  4: DP3 TEMP[2].x, TEMP[1].xyzz, IMM[0].yzww
  5: MAD TEMP[3].xy, IMM[1].xyyy, CONST[0].xyyy, IN[0].xyyy
  6: MOV TEMP[3].xy, TEMP[3].xyyy
  7: MOV TEMP[3].w, IMM[0].xxxx
  8: TXL TEMP[3].xyz, TEMP[3], SAMP[0], 2D
  9: DP3 TEMP[3].x, TEMP[3].xyzz, IMM[0].yzww
 10: MOV TEMP[4].x, TEMP[3].xxxx
 11: MAD TEMP[5].xy, IMM[1].yxxx, CONST[0].xyyy, IN[0].xyyy
 12: MOV TEMP[5].xy, TEMP[5].xyyy
 13: MOV TEMP[5].w, IMM[0].xxxx
 14: TXL TEMP[5].xyz, TEMP[5], SAMP[0], 2D
 15: DP3 TEMP[5].x, TEMP[5].xyzz, IMM[0].yzww
 16: MAD TEMP[6].xy, IMM[1].xzzz, CONST[0].xyyy, IN[0].xyyy
 17: MOV TEMP[6].xy, TEMP[6].xyyy
 18: MOV TEMP[6].w, IMM[0].xxxx
 19: TXL TEMP[6].xyz, TEMP[6], SAMP[0], 2D
 20: DP3 TEMP[6].x, TEMP[6].xyzz, IMM[0].yzww
 21: MOV TEMP[7].x, TEMP[6].xxxx
 22: MAD TEMP[8].xy, IMM[1].zxxx, CONST[0].xyyy, IN[0].xyyy
 23: MOV TEMP[8].xy, TEMP[8].xyyy
 24: MOV TEMP[8].w, IMM[0].xxxx
 25: TXL TEMP[8].xyz, TEMP[8], SAMP[0], 2D
 26: DP3 TEMP[8].x, TEMP[8].xyzz, IMM[0].yzww
 27: MAX TEMP[9].x, TEMP[6].xxxx, TEMP[8].xxxx
 28: MAX TEMP[10].x, TEMP[3].xxxx, TEMP[2].xxxx
 29: MAX TEMP[10].x, TEMP[5].xxxx, TEMP[10].xxxx
 30: MAX TEMP[9].x, TEMP[9].xxxx, TEMP[10].xxxx
 31: MIN TEMP[10].x, TEMP[6].xxxx, TEMP[8].xxxx
 32: MIN TEMP[11].x, TEMP[3].xxxx, TEMP[2].xxxx
 33: MIN TEMP[11].x, TEMP[5].xxxx, TEMP[11].xxxx
 34: MIN TEMP[10].x, TEMP[10].xxxx, TEMP[11].xxxx
 35: ADD TEMP[10].x, TEMP[9].xxxx, -TEMP[10].xxxx
 36: MUL TEMP[9].x, TEMP[9].xxxx, IMM[2].xxxx
 37: MAX TEMP[9].x, IMM[1].wwww, TEMP[9].xxxx
 38: FSLT TEMP[9].x, TEMP[10].xxxx, TEMP[9].xxxx
 39: UIF TEMP[9].xxxx :0
 40:   MOV TEMP[1], TEMP[1]
 41: ELSE :0
 42:   ADD TEMP[9].xy, IN[0].xyyy, -CONST[0].xyyy
 43:   MOV TEMP[9].xy, TEMP[9].xyyy
 44:   MOV TEMP[9].w, IMM[0].xxxx
 45:   TXL TEMP[9].xyz, TEMP[9], SAMP[0], 2D
 46:   DP3 TEMP[9].x, TEMP[9].xyzz, IMM[0].yzww
 47:   ADD TEMP[11].xy, IN[0].xyyy, CONST[0].xyyy
 48:   MOV TEMP[11].xy, TEMP[11].xyyy
 49:   MOV TEMP[11].w, IMM[0].xxxx
 50:   TXL TEMP[11].xyz, TEMP[11], SAMP[0], 2D
 51:   DP3 TEMP[11].x, TEMP[11].xyzz, IMM[0].yzww
 52:   MAD TEMP[12].xy, IMM[1].yzzz, CONST[0].xyyy, IN[0].xyyy
 53:   MOV TEMP[12].xy, TEMP[12].xyyy
 54:   MOV TEMP[12].w, IMM[0].xxxx
 55:   TXL TEMP[12].xyz, TEMP[12], SAMP[0], 2D
 56:   DP3 TEMP[12].x, TEMP[12].xyzz, IMM[0].yzww
 57:   MAD TEMP[13].xy, IMM[1].zyyy, CONST[0].xyyy, IN[0].xyyy
 58:   MOV TEMP[13].xy, TEMP[13].xyyy
 59:   MOV TEMP[13].w, IMM[0].xxxx
 60:   TXL TEMP[13].xyz, TEMP[13], SAMP[0], 2D
 61:   DP3 TEMP[13].x, TEMP[13].xyzz, IMM[0].yzww
 62:   ADD TEMP[14].x, TEMP[6].xxxx, TEMP[3].xxxx
 63:   ADD TEMP[15].x, TEMP[8].xxxx, TEMP[5].xxxx
 64:   RCP TEMP[10].x, TEMP[10].xxxx
 65:   ADD TEMP[16].x, TEMP[12].xxxx, TEMP[11].xxxx
 66:   ADD TEMP[17].x, TEMP[9].xxxx, TEMP[13].xxxx
 67:   MOV TEMP[18].x, CONST[0].xxxx
 68:   MAD TEMP[19].x, IMM[2].yyyy, TEMP[8].xxxx, TEMP[17].xxxx
 69:   ABS TEMP[19].x, TEMP[19].xxxx
 70:   MAD TEMP[20].x, IMM[2].yyyy, TEMP[2].xxxx, TEMP[14].xxxx
 71:   ABS TEMP[20].x, TEMP[20].xxxx
 72:   MAD TEMP[21].x, IMM[2].yyyy, TEMP[5].xxxx, TEMP[16].xxxx
 73:   ABS TEMP[21].x, TEMP[21].xxxx
 74:   MAD TEMP[20].x, TEMP[20].xxxx, IMM[2].zzzz, TEMP[21].xxxx
 75:   ADD TEMP[19].x, TEMP[19].xxxx, TEMP[20].xxxx
 76:   ADD TEMP[11].x, TEMP[13].xxxx, TEMP[11].xxxx
 77:   MAD TEMP[3].x, IMM[2].yyyy, TEMP[3].xxxx, TEMP[11].xxxx
 78:   ABS TEMP[3].x, TEMP[3].xxxx
 79:   MAD TEMP[11].x, IMM[2].yyyy, TEMP[2].xxxx, TEMP[15].xxxx
 80:   ABS TEMP[11].x, TEMP[11].xxxx
 81:   ADD TEMP[9].x, TEMP[9].xxxx, TEMP[12].xxxx
 82:   MAD TEMP[6].x, IMM[2].yyyy, TEMP[6].xxxx, TEMP[9].xxxx
 83:   ABS TEMP[6].x, TEMP[6].xxxx
 84:   MAD TEMP[6].x, TEMP[11].xxxx, IMM[2].zzzz, TEMP[6].xxxx
 85:   ADD TEMP[3].x, TEMP[3].xxxx, TEMP[6].xxxx
 86:   FSGE TEMP[3].x, TEMP[19].xxxx, TEMP[3].xxxx
 87:   ADD TEMP[6].x, TEMP[14].xxxx, TEMP[15].xxxx
 88:   ADD TEMP[9].x, TEMP[17].xxxx, TEMP[16].xxxx
 89:   MAD TEMP[6].x, TEMP[6].xxxx, IMM[2].zzzz, TEMP[9].xxxx
 90:   NOT TEMP[9].x, TEMP[3].xxxx
 91:   UIF TEMP[9].xxxx :0
 92:     MOV TEMP[7].x, TEMP[8].xxxx
 93:   ENDIF
 94:   NOT TEMP[8].x, TEMP[3].xxxx
 95:   UIF TEMP[8].xxxx :0
 96:     MOV TEMP[4].x, TEMP[5].xxxx
 97:   ENDIF
 98:   UIF TEMP[3].xxxx :0
 99:     MOV TEMP[18].x, CONST[0].yyyy
100:   ENDIF
101:   MAD TEMP[5].x, TEMP[6].xxxx, IMM[2].wwww, -TEMP[2].xxxx
102:   ADD TEMP[6].x, TEMP[7].xxxx, -TEMP[2].xxxx
103:   ADD TEMP[8].x, TEMP[4].xxxx, -TEMP[2].xxxx
104:   ADD TEMP[7].x, TEMP[7].xxxx, TEMP[2].xxxx
105:   ADD TEMP[4].x, TEMP[4].xxxx, TEMP[2].xxxx
106:   ABS TEMP[9].x, TEMP[6].xxxx
107:   ABS TEMP[11].x, TEMP[8].xxxx
108:   FSGE TEMP[9].x, TEMP[9].xxxx, TEMP[11].xxxx
109:   ABS TEMP[6].x, TEMP[6].xxxx
110:   ABS TEMP[8].x, TEMP[8].xxxx
111:   MAX TEMP[6].x, TEMP[6].xxxx, TEMP[8].xxxx
112:   UIF TEMP[9].xxxx :0
113:     MOV TEMP[18].x, -TEMP[18].xxxx
114:   ENDIF
115:   ABS TEMP[5].x, TEMP[5].xxxx
116:   MUL_SAT TEMP[5].x, TEMP[5].xxxx, TEMP[10].xxxx
117:   MOV TEMP[8].xy, IN[0].xyxx
118:   NOT TEMP[10].x, TEMP[3].xxxx
119:   UIF TEMP[10].xxxx :0
120:     MOV TEMP[10].x, IMM[0].xxxx
121:   ELSE :0
122:     MOV TEMP[10].x, CONST[0].xxxx
123:   ENDIF
124:   MOV TEMP[10].x, TEMP[10].xxxx
125:   UIF TEMP[3].xxxx :0
126:     MOV TEMP[11].x, IMM[0].xxxx
127:   ELSE :0
128:     MOV TEMP[11].x, CONST[0].yyyy
129:   ENDIF
130:   MOV TEMP[10].y, TEMP[11].xxxx
131:   NOT TEMP[11].x, TEMP[3].xxxx
132:   UIF TEMP[11].xxxx :0
133:     MAD TEMP[8].x, TEMP[18].xxxx, IMM[3].xxxx, IN[0].xxxx
134:   ENDIF
135:   UIF TEMP[3].xxxx :0
136:     MAD TEMP[11].x, TEMP[18].xxxx, IMM[3].xxxx, IN[0].yyyy
137:     MOV TEMP[8].y, TEMP[11].xxxx
138:   ENDIF
139:   ADD TEMP[11].xy, TEMP[8].xyyy, -TEMP[10].xyyy
140:   MOV TEMP[12].xy, TEMP[11].xyxx
141:   ADD TEMP[8].xy, TEMP[8].xyyy, TEMP[10].xyyy
142:   MAD TEMP[13].x, IMM[2].yyyy, TEMP[5].xxxx, IMM[3].yyyy
143:   MOV TEMP[14].xy, TEMP[11].xyyy
144:   MOV TEMP[14].w, IMM[0].xxxx
145:   TXL TEMP[14].xyz, TEMP[14], SAMP[0], 2D
146:   DP3 TEMP[14].x, TEMP[14].xyzz, IMM[0].yzww
147:   MUL TEMP[5].x, TEMP[5].xxxx, TEMP[5].xxxx
148:   MOV TEMP[15].xy, TEMP[8].xyyy
149:   MOV TEMP[15].w, IMM[0].xxxx
150:   TXL TEMP[15].xyz, TEMP[15], SAMP[0], 2D
151:   DP3 TEMP[15].x, TEMP[15].xyzz, IMM[0].yzww
152:   NOT TEMP[9].x, TEMP[9].xxxx
153:   UIF TEMP[9].xxxx :0
154:     MOV TEMP[7].x, TEMP[4].xxxx
155:   ENDIF
156:   MUL TEMP[6].x, TEMP[6].xxxx, IMM[3].zzzz
157:   MUL TEMP[5].x, TEMP[13].xxxx, TEMP[5].xxxx
158:   MUL TEMP[9].x, TEMP[7].xxxx, IMM[3].xxxx
159:   ADD TEMP[9].x, TEMP[2].xxxx, -TEMP[9].xxxx
160:   FSLT TEMP[9].x, TEMP[9].xxxx, IMM[0].xxxx
161:   MUL TEMP[13].x, TEMP[7].xxxx, IMM[3].xxxx
162:   ADD TEMP[13].x, TEMP[14].xxxx, -TEMP[13].xxxx
163:   MOV TEMP[2].x, TEMP[13].xxxx
164:   MUL TEMP[14].x, TEMP[7].xxxx, IMM[3].xxxx
165:   ADD TEMP[4].x, TEMP[15].xxxx, -TEMP[14].xxxx
166:   ABS TEMP[13].x, TEMP[13].xxxx
167:   FSGE TEMP[13].x, TEMP[13].xxxx, TEMP[6].xxxx
168:   ABS TEMP[14].x, TEMP[4].xxxx
169:   FSGE TEMP[14].x, TEMP[14].xxxx, TEMP[6].xxxx
170:   NOT TEMP[15].x, TEMP[13].xxxx
171:   UIF TEMP[15].xxxx :0
172:     MUL TEMP[15].xy, TEMP[10].xyyy, IMM[3].wwww
173:     ADD TEMP[12].xy, TEMP[11].xyyy, -TEMP[15].xyyy
174:   ENDIF
175:   AND TEMP[11].x, TEMP[13].xxxx, TEMP[14].xxxx
176:   NOT TEMP[11].x, TEMP[11].xxxx
177:   NOT TEMP[15].x, TEMP[14].xxxx
178:   UIF TEMP[15].xxxx :0
179:     MAD TEMP[8].xy, TEMP[10].xyyy, IMM[3].wwww, TEMP[8].xyyy
180:   ENDIF
181:   UIF TEMP[11].xxxx :0
182:     NOT TEMP[11].x, TEMP[13].xxxx
183:     UIF TEMP[11].xxxx :0
184:       MOV TEMP[11].xy, TEMP[12].xyyy
185:       MOV TEMP[11].w, IMM[0].xxxx
186:       TXL TEMP[11].xyz, TEMP[11], SAMP[0], 2D
187:       DP3 TEMP[2].x, TEMP[11].xyzz, IMM[0].yzww
188:     ENDIF
189:     NOT TEMP[11].x, TEMP[14].xxxx
190:     UIF TEMP[11].xxxx :0
191:       MOV TEMP[11].xy, TEMP[8].xyyy
192:       MOV TEMP[11].w, IMM[0].xxxx
193:       TXL TEMP[11].xyz, TEMP[11], SAMP[0], 2D
194:       DP3 TEMP[4].x, TEMP[11].xyzz, IMM[0].yzww
195:     ENDIF
196:     NOT TEMP[11].x, TEMP[13].xxxx
197:     UIF TEMP[11].xxxx :0
198:       MUL TEMP[11].x, TEMP[7].xxxx, IMM[3].xxxx
199:       ADD TEMP[2].x, TEMP[2].xxxx, -TEMP[11].xxxx
200:     ENDIF
201:     NOT TEMP[11].x, TEMP[14].xxxx
202:     UIF TEMP[11].xxxx :0
203:       MUL TEMP[11].x, TEMP[7].xxxx, IMM[3].xxxx
204:       ADD TEMP[4].x, TEMP[4].xxxx, -TEMP[11].xxxx
205:     ENDIF
206:     ABS TEMP[11].x, TEMP[2].xxxx
207:     FSGE TEMP[13].x, TEMP[11].xxxx, TEMP[6].xxxx
208:     ABS TEMP[11].x, TEMP[4].xxxx
209:     FSGE TEMP[11].x, TEMP[11].xxxx, TEMP[6].xxxx
210:     NOT TEMP[14].x, TEMP[13].xxxx
211:     UIF TEMP[14].xxxx :0
212:       MUL TEMP[14].xy, TEMP[10].xyyy, IMM[2].zzzz
213:       ADD TEMP[12].xy, TEMP[12].xyyy, -TEMP[14].xyyy
214:     ENDIF
215:     AND TEMP[14].x, TEMP[13].xxxx, TEMP[11].xxxx
216:     NOT TEMP[14].x, TEMP[14].xxxx
217:     NOT TEMP[15].x, TEMP[11].xxxx
218:     UIF TEMP[15].xxxx :0
219:       MAD TEMP[8].xy, TEMP[10].xyyy, IMM[2].zzzz, TEMP[8].xyyy
220:     ENDIF
221:     UIF TEMP[14].xxxx :0
222:       NOT TEMP[14].x, TEMP[13].xxxx
223:       UIF TEMP[14].xxxx :0
224:         MOV TEMP[14].xy, TEMP[12].xyyy
225:         MOV TEMP[14].w, IMM[0].xxxx
226:         TXL TEMP[14].xyz, TEMP[14], SAMP[0], 2D
227:         DP3 TEMP[2].x, TEMP[14].xyzz, IMM[0].yzww
228:       ENDIF
229:       NOT TEMP[14].x, TEMP[11].xxxx
230:       UIF TEMP[14].xxxx :0
231:         MOV TEMP[14].xy, TEMP[8].xyyy
232:         MOV TEMP[14].w, IMM[0].xxxx
233:         TXL TEMP[14].xyz, TEMP[14], SAMP[0], 2D
234:         DP3 TEMP[4].x, TEMP[14].xyzz, IMM[0].yzww
235:       ENDIF
236:       NOT TEMP[14].x, TEMP[13].xxxx
237:       UIF TEMP[14].xxxx :0
238:         MUL TEMP[14].x, TEMP[7].xxxx, IMM[3].xxxx
239:         ADD TEMP[2].x, TEMP[2].xxxx, -TEMP[14].xxxx
240:       ENDIF
241:       NOT TEMP[11].x, TEMP[11].xxxx
242:       UIF TEMP[11].xxxx :0
243:         MUL TEMP[11].x, TEMP[7].xxxx, IMM[3].xxxx
244:         ADD TEMP[4].x, TEMP[4].xxxx, -TEMP[11].xxxx
245:       ENDIF
246:       ABS TEMP[11].x, TEMP[2].xxxx
247:       FSGE TEMP[13].x, TEMP[11].xxxx, TEMP[6].xxxx
248:       ABS TEMP[11].x, TEMP[4].xxxx
249:       FSGE TEMP[11].x, TEMP[11].xxxx, TEMP[6].xxxx
250:       NOT TEMP[14].x, TEMP[13].xxxx
251:       UIF TEMP[14].xxxx :0
252:         MUL TEMP[14].xy, TEMP[10].xyyy, IMM[2].zzzz
253:         ADD TEMP[12].xy, TEMP[12].xyyy, -TEMP[14].xyyy
254:       ENDIF
255:       AND TEMP[14].x, TEMP[13].xxxx, TEMP[11].xxxx
256:       NOT TEMP[14].x, TEMP[14].xxxx
257:       NOT TEMP[15].x, TEMP[11].xxxx
258:       UIF TEMP[15].xxxx :0
259:         MAD TEMP[8].xy, TEMP[10].xyyy, IMM[2].zzzz, TEMP[8].xyyy
260:       ENDIF
261:       UIF TEMP[14].xxxx :0
262:         NOT TEMP[14].x, TEMP[13].xxxx
263:         UIF TEMP[14].xxxx :0
264:           MOV TEMP[14].xy, TEMP[12].xyyy
265:           MOV TEMP[14].w, IMM[0].xxxx
266:           TXL TEMP[14].xyz, TEMP[14], SAMP[0], 2D
267:           DP3 TEMP[2].x, TEMP[14].xyzz, IMM[0].yzww
268:         ENDIF
269:         NOT TEMP[14].x, TEMP[11].xxxx
270:         UIF TEMP[14].xxxx :0
271:           MOV TEMP[14].xy, TEMP[8].xyyy
272:           MOV TEMP[14].w, IMM[0].xxxx
273:           TXL TEMP[14].xyz, TEMP[14], SAMP[0], 2D
274:           DP3 TEMP[4].x, TEMP[14].xyzz, IMM[0].yzww
275:         ENDIF
276:         NOT TEMP[14].x, TEMP[13].xxxx
277:         UIF TEMP[14].xxxx :0
278:           MUL TEMP[14].x, TEMP[7].xxxx, IMM[3].xxxx
279:           ADD TEMP[2].x, TEMP[2].xxxx, -TEMP[14].xxxx
280:         ENDIF
281:         NOT TEMP[11].x, TEMP[11].xxxx
282:         UIF TEMP[11].xxxx :0
283:           MUL TEMP[11].x, TEMP[7].xxxx, IMM[3].xxxx
284:           ADD TEMP[4].x, TEMP[4].xxxx, -TEMP[11].xxxx
285:         ENDIF
286:         ABS TEMP[11].x, TEMP[2].xxxx
287:         FSGE TEMP[13].x, TEMP[11].xxxx, TEMP[6].xxxx
288:         ABS TEMP[11].x, TEMP[4].xxxx
289:         FSGE TEMP[11].x, TEMP[11].xxxx, TEMP[6].xxxx
290:         NOT TEMP[14].x, TEMP[13].xxxx
291:         UIF TEMP[14].xxxx :0
292:           MUL TEMP[14].xy, TEMP[10].xyyy, IMM[2].zzzz
293:           ADD TEMP[12].xy, TEMP[12].xyyy, -TEMP[14].xyyy
294:         ENDIF
295:         AND TEMP[14].x, TEMP[13].xxxx, TEMP[11].xxxx
296:         NOT TEMP[14].x, TEMP[14].xxxx
297:         NOT TEMP[15].x, TEMP[11].xxxx
298:         UIF TEMP[15].xxxx :0
299:           MAD TEMP[8].xy, TEMP[10].xyyy, IMM[2].zzzz, TEMP[8].xyyy
300:         ENDIF
301:         UIF TEMP[14].xxxx :0
302:           NOT TEMP[14].x, TEMP[13].xxxx
303:           UIF TEMP[14].xxxx :0
304:             MOV TEMP[14].xy, TEMP[12].xyyy
305:             MOV TEMP[14].w, IMM[0].xxxx
306:             TXL TEMP[14].xyz, TEMP[14], SAMP[0], 2D
307:             DP3 TEMP[2].x, TEMP[14].xyzz, IMM[0].yzww
308:           ENDIF
309:           NOT TEMP[14].x, TEMP[11].xxxx
310:           UIF TEMP[14].xxxx :0
311:             MOV TEMP[14].xy, TEMP[8].xyyy
312:             MOV TEMP[14].w, IMM[0].xxxx
313:             TXL TEMP[14].xyz, TEMP[14], SAMP[0], 2D
314:             DP3 TEMP[4].x, TEMP[14].xyzz, IMM[0].yzww
315:           ENDIF
316:           NOT TEMP[14].x, TEMP[13].xxxx
317:           UIF TEMP[14].xxxx :0
318:             MUL TEMP[14].x, TEMP[7].xxxx, IMM[3].xxxx
319:             ADD TEMP[2].x, TEMP[2].xxxx, -TEMP[14].xxxx
320:           ENDIF
321:           NOT TEMP[11].x, TEMP[11].xxxx
322:           UIF TEMP[11].xxxx :0
323:             MUL TEMP[11].x, TEMP[7].xxxx, IMM[3].xxxx
324:             ADD TEMP[4].x, TEMP[4].xxxx, -TEMP[11].xxxx
325:           ENDIF
326:           ABS TEMP[11].x, TEMP[2].xxxx
327:           FSGE TEMP[13].x, TEMP[11].xxxx, TEMP[6].xxxx
328:           ABS TEMP[11].x, TEMP[4].xxxx
329:           FSGE TEMP[11].x, TEMP[11].xxxx, TEMP[6].xxxx
330:           NOT TEMP[14].x, TEMP[13].xxxx
331:           UIF TEMP[14].xxxx :0
332:             MUL TEMP[14].xy, TEMP[10].xyyy, IMM[2].zzzz
333:             ADD TEMP[12].xy, TEMP[12].xyyy, -TEMP[14].xyyy
334:           ENDIF
335:           AND TEMP[14].x, TEMP[13].xxxx, TEMP[11].xxxx
336:           NOT TEMP[14].x, TEMP[14].xxxx
337:           NOT TEMP[15].x, TEMP[11].xxxx
338:           UIF TEMP[15].xxxx :0
339:             MAD TEMP[8].xy, TEMP[10].xyyy, IMM[2].zzzz, TEMP[8].xyyy
340:           ENDIF
341:           UIF TEMP[14].xxxx :0
342:             NOT TEMP[14].x, TEMP[13].xxxx
343:             UIF TEMP[14].xxxx :0
344:               MOV TEMP[14].xy, TEMP[12].xyyy
345:               MOV TEMP[14].w, IMM[0].xxxx
346:               TXL TEMP[14].xyz, TEMP[14], SAMP[0], 2D
347:               DP3 TEMP[2].x, TEMP[14].xyzz, IMM[0].yzww
348:             ENDIF
349:             NOT TEMP[14].x, TEMP[11].xxxx
350:             UIF TEMP[14].xxxx :0
351:               MOV TEMP[14].xy, TEMP[8].xyyy
352:               MOV TEMP[14].w, IMM[0].xxxx
353:               TXL TEMP[14].xyz, TEMP[14], SAMP[0], 2D
354:               DP3 TEMP[4].x, TEMP[14].xyzz, IMM[0].yzww
355:             ENDIF
356:             NOT TEMP[14].x, TEMP[13].xxxx
357:             UIF TEMP[14].xxxx :0
358:               MUL TEMP[14].x, TEMP[7].xxxx, IMM[3].xxxx
359:               ADD TEMP[2].x, TEMP[2].xxxx, -TEMP[14].xxxx
360:             ENDIF
361:             NOT TEMP[11].x, TEMP[11].xxxx
362:             UIF TEMP[11].xxxx :0
363:               MUL TEMP[11].x, TEMP[7].xxxx, IMM[3].xxxx
364:               ADD TEMP[4].x, TEMP[4].xxxx, -TEMP[11].xxxx
365:             ENDIF
366:             ABS TEMP[11].x, TEMP[2].xxxx
367:             FSGE TEMP[13].x, TEMP[11].xxxx, TEMP[6].xxxx
368:             ABS TEMP[11].x, TEMP[4].xxxx
369:             FSGE TEMP[11].x, TEMP[11].xxxx, TEMP[6].xxxx
370:             NOT TEMP[14].x, TEMP[13].xxxx
371:             UIF TEMP[14].xxxx :0
372:               MUL TEMP[14].xy, TEMP[10].xyyy, IMM[4].xxxx
373:               ADD TEMP[12].xy, TEMP[12].xyyy, -TEMP[14].xyyy
374:             ENDIF
375:             AND TEMP[14].x, TEMP[13].xxxx, TEMP[11].xxxx
376:             NOT TEMP[14].x, TEMP[14].xxxx
377:             NOT TEMP[15].x, TEMP[11].xxxx
378:             UIF TEMP[15].xxxx :0
379:               MAD TEMP[8].xy, TEMP[10].xyyy, IMM[4].xxxx, TEMP[8].xyyy
380:             ENDIF
381:             UIF TEMP[14].xxxx :0
382:               NOT TEMP[14].x, TEMP[13].xxxx
383:               UIF TEMP[14].xxxx :0
384:                 MOV TEMP[14].xy, TEMP[12].xyyy
385:                 MOV TEMP[14].w, IMM[0].xxxx
386:                 TXL TEMP[14].xyz, TEMP[14], SAMP[0], 2D
387:                 DP3 TEMP[2].x, TEMP[14].xyzz, IMM[0].yzww
388:               ENDIF
389:               NOT TEMP[14].x, TEMP[11].xxxx
390:               UIF TEMP[14].xxxx :0
391:                 MOV TEMP[14].xy, TEMP[8].xyyy
392:                 MOV TEMP[14].w, IMM[0].xxxx
393:                 TXL TEMP[14].xyz, TEMP[14], SAMP[0], 2D
394:                 DP3 TEMP[4].x, TEMP[14].xyzz, IMM[0].yzww
395:               ENDIF
396:               NOT TEMP[14].x, TEMP[13].xxxx
397:               UIF TEMP[14].xxxx :0
398:                 MUL TEMP[14].x, TEMP[7].xxxx, IMM[3].xxxx
399:                 ADD TEMP[2].x, TEMP[2].xxxx, -TEMP[14].xxxx
400:               ENDIF
401:               NOT TEMP[11].x, TEMP[11].xxxx
402:               UIF TEMP[11].xxxx :0
403:                 MUL TEMP[7].x, TEMP[7].xxxx, IMM[3].xxxx
404:                 ADD TEMP[4].x, TEMP[4].xxxx, -TEMP[7].xxxx
405:               ENDIF
406:               ABS TEMP[7].x, TEMP[2].xxxx
407:               FSGE TEMP[13].x, TEMP[7].xxxx, TEMP[6].xxxx
408:               ABS TEMP[7].x, TEMP[4].xxxx
409:               FSGE TEMP[6].x, TEMP[7].xxxx, TEMP[6].xxxx
410:               NOT TEMP[7].x, TEMP[13].xxxx
411:               UIF TEMP[7].xxxx :0
412:                 MUL TEMP[7].xy, TEMP[10].xyyy, IMM[4].yyyy
413:                 ADD TEMP[12].xy, TEMP[12].xyyy, -TEMP[7].xyyy
414:               ENDIF
415:               NOT TEMP[6].x, TEMP[6].xxxx
416:               UIF TEMP[6].xxxx :0
417:                 MAD TEMP[8].xy, TEMP[10].xyyy, IMM[4].yyyy, TEMP[8].xyyy
418:               ENDIF
419:             ENDIF
420:           ENDIF
421:         ENDIF
422:       ENDIF
423:     ENDIF
424:   ENDIF
425:   ADD TEMP[6].x, IN[0].xxxx, -TEMP[12].xxxx
426:   ADD TEMP[7].x, TEMP[8].xxxx, -IN[0].xxxx
427:   NOT TEMP[10].x, TEMP[3].xxxx
428:   UIF TEMP[10].xxxx :0
429:     ADD TEMP[6].x, IN[0].yyyy, -TEMP[12].yyyy
430:   ENDIF
431:   NOT TEMP[10].x, TEMP[3].xxxx
432:   UIF TEMP[10].xxxx :0
433:     ADD TEMP[7].x, TEMP[8].yyyy, -IN[0].yyyy
434:   ENDIF
435:   FSLT TEMP[2].x, TEMP[2].xxxx, IMM[0].xxxx
436:   USNE TEMP[2].x, TEMP[2].xxxx, TEMP[9].xxxx
437:   FSLT TEMP[4].x, TEMP[4].xxxx, IMM[0].xxxx
438:   USNE TEMP[4].x, TEMP[4].xxxx, TEMP[9].xxxx
439:   ADD TEMP[8].x, TEMP[7].xxxx, TEMP[6].xxxx
440:   RCP TEMP[8].x, TEMP[8].xxxx
441:   MIN TEMP[9].x, TEMP[6].xxxx, TEMP[7].xxxx
442:   FSLT TEMP[6].x, TEMP[6].xxxx, TEMP[7].xxxx
443:   UIF TEMP[6].xxxx :0
444:     MOV TEMP[2].x, TEMP[2].xxxx
445:   ELSE :0
446:     MOV TEMP[2].x, TEMP[4].xxxx
447:   ENDIF
448:   MAD TEMP[4].x, TEMP[9].xxxx, -TEMP[8].xxxx, IMM[3].xxxx
449:   MUL TEMP[5].x, TEMP[5].xxxx, TEMP[5].xxxx
450:   MUL TEMP[5].x, TEMP[5].xxxx, IMM[3].zzzz
451:   UIF TEMP[2].xxxx :0
452:     MOV TEMP[2].x, TEMP[4].xxxx
453:   ELSE :0
454:     MOV TEMP[2].x, IMM[0].xxxx
455:   ENDIF
456:   MAX TEMP[2].x, TEMP[2].xxxx, TEMP[5].xxxx
457:   NOT TEMP[4].x, TEMP[3].xxxx
458:   UIF TEMP[4].xxxx :0
459:     MAD TEMP[0].x, TEMP[2].xxxx, TEMP[18].xxxx, IN[0].xxxx
460:   ENDIF
461:   UIF TEMP[3].xxxx :0
462:     MAD TEMP[2].x, TEMP[2].xxxx, TEMP[18].xxxx, IN[0].yyyy
463:     MOV TEMP[0].y, TEMP[2].xxxx
464:   ENDIF
465:   MOV TEMP[0].xy, TEMP[0].xyyy
466:   MOV TEMP[0].w, IMM[0].xxxx
467:   TXL TEMP[0], TEMP[0], SAMP[0], 2D
468:   MOV TEMP[1], TEMP[0]
469: ENDIF
470: MOV OUT[0], TEMP[1]
471: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %21 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
  %22 = load <16 x i8> addrspace(2)* %21, !tbaa !0
  %23 = call float @llvm.SI.load.const(<16 x i8> %22, i32 0)
  %24 = call float @llvm.SI.load.const(<16 x i8> %22, i32 4)
  %25 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0
  %26 = load <32 x i8> addrspace(2)* %25, !tbaa !0
  %27 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0
  %28 = load <16 x i8> addrspace(2)* %27, !tbaa !0
  %29 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %4, <2 x i32> %6)
  %30 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %4, <2 x i32> %6)
  %31 = bitcast float %29 to i32
  %32 = bitcast float %30 to i32
  %33 = bitcast float 0.000000e+00 to i32
  %34 = insertelement <4 x i32> undef, i32 %31, i32 0
  %35 = insertelement <4 x i32> %34, i32 %32, i32 1
  %36 = insertelement <4 x i32> %35, i32 %33, i32 2
  %37 = insertelement <4 x i32> %36, i32 undef, i32 3
  %38 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %37, <32 x i8> %26, <16 x i8> %28, i32 2)
  %39 = extractelement <4 x float> %38, i32 0
  %40 = extractelement <4 x float> %38, i32 1
  %41 = extractelement <4 x float> %38, i32 2
  %42 = extractelement <4 x float> %38, i32 3
  %43 = fmul float %39, 0x3FD322D0E0000000
  %44 = fmul float %40, 0x3FE2C8B440000000
  %45 = fadd float %44, %43
  %46 = fmul float %41, 0x3FBD2F1AA0000000
  %47 = fadd float %45, %46
  %48 = fmul float 0.000000e+00, %23
  %49 = fadd float %48, %29
  %50 = fmul float 1.000000e+00, %24
  %51 = fadd float %50, %30
  %52 = bitcast float %49 to i32
  %53 = bitcast float %51 to i32
  %54 = bitcast float 0.000000e+00 to i32
  %55 = insertelement <4 x i32> undef, i32 %52, i32 0
  %56 = insertelement <4 x i32> %55, i32 %53, i32 1
  %57 = insertelement <4 x i32> %56, i32 %54, i32 2
  %58 = insertelement <4 x i32> %57, i32 undef, i32 3
  %59 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %58, <32 x i8> %26, <16 x i8> %28, i32 2)
  %60 = extractelement <4 x float> %59, i32 0
  %61 = extractelement <4 x float> %59, i32 1
  %62 = extractelement <4 x float> %59, i32 2
  %63 = fmul float %60, 0x3FD322D0E0000000
  %64 = fmul float %61, 0x3FE2C8B440000000
  %65 = fadd float %64, %63
  %66 = fmul float %62, 0x3FBD2F1AA0000000
  %67 = fadd float %65, %66
  %68 = fmul float 1.000000e+00, %23
  %69 = fadd float %68, %29
  %70 = fmul float 0.000000e+00, %24
  %71 = fadd float %70, %30
  %72 = bitcast float %69 to i32
  %73 = bitcast float %71 to i32
  %74 = bitcast float 0.000000e+00 to i32
  %75 = insertelement <4 x i32> undef, i32 %72, i32 0
  %76 = insertelement <4 x i32> %75, i32 %73, i32 1
  %77 = insertelement <4 x i32> %76, i32 %74, i32 2
  %78 = insertelement <4 x i32> %77, i32 undef, i32 3
  %79 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %78, <32 x i8> %26, <16 x i8> %28, i32 2)
  %80 = extractelement <4 x float> %79, i32 0
  %81 = extractelement <4 x float> %79, i32 1
  %82 = extractelement <4 x float> %79, i32 2
  %83 = fmul float %80, 0x3FD322D0E0000000
  %84 = fmul float %81, 0x3FE2C8B440000000
  %85 = fadd float %84, %83
  %86 = fmul float %82, 0x3FBD2F1AA0000000
  %87 = fadd float %85, %86
  %88 = fmul float 0.000000e+00, %23
  %89 = fadd float %88, %29
  %90 = fmul float -1.000000e+00, %24
  %91 = fadd float %90, %30
  %92 = bitcast float %89 to i32
  %93 = bitcast float %91 to i32
  %94 = bitcast float 0.000000e+00 to i32
  %95 = insertelement <4 x i32> undef, i32 %92, i32 0
  %96 = insertelement <4 x i32> %95, i32 %93, i32 1
  %97 = insertelement <4 x i32> %96, i32 %94, i32 2
  %98 = insertelement <4 x i32> %97, i32 undef, i32 3
  %99 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %98, <32 x i8> %26, <16 x i8> %28, i32 2)
  %100 = extractelement <4 x float> %99, i32 0
  %101 = extractelement <4 x float> %99, i32 1
  %102 = extractelement <4 x float> %99, i32 2
  %103 = fmul float %100, 0x3FD322D0E0000000
  %104 = fmul float %101, 0x3FE2C8B440000000
  %105 = fadd float %104, %103
  %106 = fmul float %102, 0x3FBD2F1AA0000000
  %107 = fadd float %105, %106
  %108 = fmul float -1.000000e+00, %23
  %109 = fadd float %108, %29
  %110 = fmul float 0.000000e+00, %24
  %111 = fadd float %110, %30
  %112 = bitcast float %109 to i32
  %113 = bitcast float %111 to i32
  %114 = bitcast float 0.000000e+00 to i32
  %115 = insertelement <4 x i32> undef, i32 %112, i32 0
  %116 = insertelement <4 x i32> %115, i32 %113, i32 1
  %117 = insertelement <4 x i32> %116, i32 %114, i32 2
  %118 = insertelement <4 x i32> %117, i32 undef, i32 3
  %119 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %118, <32 x i8> %26, <16 x i8> %28, i32 2)
  %120 = extractelement <4 x float> %119, i32 0
  %121 = extractelement <4 x float> %119, i32 1
  %122 = extractelement <4 x float> %119, i32 2
  %123 = fmul float %120, 0x3FD322D0E0000000
  %124 = fmul float %121, 0x3FE2C8B440000000
  %125 = fadd float %124, %123
  %126 = fmul float %122, 0x3FBD2F1AA0000000
  %127 = fadd float %125, %126
  %128 = fcmp uge float %107, %127
  %129 = select i1 %128, float %107, float %127
  %130 = fcmp uge float %67, %47
  %131 = select i1 %130, float %67, float %47
  %132 = fcmp uge float %87, %131
  %133 = select i1 %132, float %87, float %131
  %134 = fcmp uge float %129, %133
  %135 = select i1 %134, float %129, float %133
  %136 = fcmp uge float %107, %127
  %137 = select i1 %136, float %127, float %107
  %138 = fcmp uge float %67, %47
  %139 = select i1 %138, float %47, float %67
  %140 = fcmp uge float %87, %139
  %141 = select i1 %140, float %139, float %87
  %142 = fcmp uge float %137, %141
  %143 = select i1 %142, float %141, float %137
  %144 = fsub float -0.000000e+00, %143
  %145 = fadd float %135, %144
  %146 = fmul float %135, 0x3FC53F7CE0000000
  %147 = fcmp uge float 0x3FB5532620000000, %146
  %148 = select i1 %147, float 0x3FB5532620000000, float %146
  %149 = fcmp olt float %145, %148
  %150 = sext i1 %149 to i32
  %151 = bitcast i32 %150 to float
  %152 = bitcast float %151 to i32
  %153 = icmp ne i32 %152, 0
  br i1 %153, label %ENDIF, label %ELSE

ELSE:                                             ; preds = %main_body
  %154 = fsub float -0.000000e+00, %23
  %155 = fadd float %29, %154
  %156 = fsub float -0.000000e+00, %24
  %157 = fadd float %30, %156
  %158 = bitcast float %155 to i32
  %159 = bitcast float %157 to i32
  %160 = bitcast float 0.000000e+00 to i32
  %161 = insertelement <4 x i32> undef, i32 %158, i32 0
  %162 = insertelement <4 x i32> %161, i32 %159, i32 1
  %163 = insertelement <4 x i32> %162, i32 %160, i32 2
  %164 = insertelement <4 x i32> %163, i32 undef, i32 3
  %165 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %164, <32 x i8> %26, <16 x i8> %28, i32 2)
  %166 = extractelement <4 x float> %165, i32 0
  %167 = extractelement <4 x float> %165, i32 1
  %168 = extractelement <4 x float> %165, i32 2
  %169 = fmul float %166, 0x3FD322D0E0000000
  %170 = fmul float %167, 0x3FE2C8B440000000
  %171 = fadd float %170, %169
  %172 = fmul float %168, 0x3FBD2F1AA0000000
  %173 = fadd float %171, %172
  %174 = fadd float %29, %23
  %175 = fadd float %30, %24
  %176 = bitcast float %174 to i32
  %177 = bitcast float %175 to i32
  %178 = bitcast float 0.000000e+00 to i32
  %179 = insertelement <4 x i32> undef, i32 %176, i32 0
  %180 = insertelement <4 x i32> %179, i32 %177, i32 1
  %181 = insertelement <4 x i32> %180, i32 %178, i32 2
  %182 = insertelement <4 x i32> %181, i32 undef, i32 3
  %183 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %182, <32 x i8> %26, <16 x i8> %28, i32 2)
  %184 = extractelement <4 x float> %183, i32 0
  %185 = extractelement <4 x float> %183, i32 1
  %186 = extractelement <4 x float> %183, i32 2
  %187 = fmul float %184, 0x3FD322D0E0000000
  %188 = fmul float %185, 0x3FE2C8B440000000
  %189 = fadd float %188, %187
  %190 = fmul float %186, 0x3FBD2F1AA0000000
  %191 = fadd float %189, %190
  %192 = fmul float 1.000000e+00, %23
  %193 = fadd float %192, %29
  %194 = fmul float -1.000000e+00, %24
  %195 = fadd float %194, %30
  %196 = bitcast float %193 to i32
  %197 = bitcast float %195 to i32
  %198 = bitcast float 0.000000e+00 to i32
  %199 = insertelement <4 x i32> undef, i32 %196, i32 0
  %200 = insertelement <4 x i32> %199, i32 %197, i32 1
  %201 = insertelement <4 x i32> %200, i32 %198, i32 2
  %202 = insertelement <4 x i32> %201, i32 undef, i32 3
  %203 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %202, <32 x i8> %26, <16 x i8> %28, i32 2)
  %204 = extractelement <4 x float> %203, i32 0
  %205 = extractelement <4 x float> %203, i32 1
  %206 = extractelement <4 x float> %203, i32 2
  %207 = fmul float %204, 0x3FD322D0E0000000
  %208 = fmul float %205, 0x3FE2C8B440000000
  %209 = fadd float %208, %207
  %210 = fmul float %206, 0x3FBD2F1AA0000000
  %211 = fadd float %209, %210
  %212 = fmul float -1.000000e+00, %23
  %213 = fadd float %212, %29
  %214 = fmul float 1.000000e+00, %24
  %215 = fadd float %214, %30
  %216 = bitcast float %213 to i32
  %217 = bitcast float %215 to i32
  %218 = bitcast float 0.000000e+00 to i32
  %219 = insertelement <4 x i32> undef, i32 %216, i32 0
  %220 = insertelement <4 x i32> %219, i32 %217, i32 1
  %221 = insertelement <4 x i32> %220, i32 %218, i32 2
  %222 = insertelement <4 x i32> %221, i32 undef, i32 3
  %223 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %222, <32 x i8> %26, <16 x i8> %28, i32 2)
  %224 = extractelement <4 x float> %223, i32 0
  %225 = extractelement <4 x float> %223, i32 1
  %226 = extractelement <4 x float> %223, i32 2
  %227 = fmul float %224, 0x3FD322D0E0000000
  %228 = fmul float %225, 0x3FE2C8B440000000
  %229 = fadd float %228, %227
  %230 = fmul float %226, 0x3FBD2F1AA0000000
  %231 = fadd float %229, %230
  %232 = fadd float %107, %67
  %233 = fadd float %127, %87
  %234 = fdiv float 1.000000e+00, %145
  %235 = fadd float %211, %191
  %236 = fadd float %173, %231
  %237 = fmul float -2.000000e+00, %127
  %238 = fadd float %237, %236
  %239 = call float @fabs(float %238)
  %240 = fmul float -2.000000e+00, %47
  %241 = fadd float %240, %232
  %242 = call float @fabs(float %241)
  %243 = fmul float -2.000000e+00, %87
  %244 = fadd float %243, %235
  %245 = call float @fabs(float %244)
  %246 = fmul float %242, 2.000000e+00
  %247 = fadd float %246, %245
  %248 = fadd float %239, %247
  %249 = fadd float %231, %191
  %250 = fmul float -2.000000e+00, %67
  %251 = fadd float %250, %249
  %252 = call float @fabs(float %251)
  %253 = fmul float -2.000000e+00, %47
  %254 = fadd float %253, %233
  %255 = call float @fabs(float %254)
  %256 = fadd float %173, %211
  %257 = fmul float -2.000000e+00, %107
  %258 = fadd float %257, %256
  %259 = call float @fabs(float %258)
  %260 = fmul float %255, 2.000000e+00
  %261 = fadd float %260, %259
  %262 = fadd float %252, %261
  %263 = fcmp oge float %248, %262
  %264 = sext i1 %263 to i32
  %265 = bitcast i32 %264 to float
  %266 = fadd float %232, %233
  %267 = fadd float %236, %235
  %268 = fmul float %266, 2.000000e+00
  %269 = fadd float %268, %267
  %270 = bitcast float %265 to i32
  %271 = xor i32 %270, -1
  %272 = bitcast i32 %271 to float
  %273 = bitcast float %272 to i32
  %274 = icmp ne i32 %273, 0
  %. = select i1 %274, float %127, float %107
  %275 = bitcast float %265 to i32
  %276 = xor i32 %275, -1
  %277 = bitcast i32 %276 to float
  %278 = bitcast float %277 to i32
  %279 = icmp ne i32 %278, 0
  %temp16.0 = select i1 %279, float %87, float %67
  %280 = bitcast float %265 to i32
  %281 = icmp ne i32 %280, 0
  %.265 = select i1 %281, float %24, float %23
  %282 = fsub float -0.000000e+00, %47
  %283 = fmul float %269, 0x3FB5555560000000
  %284 = fadd float %283, %282
  %285 = fsub float -0.000000e+00, %47
  %286 = fadd float %., %285
  %287 = fsub float -0.000000e+00, %47
  %288 = fadd float %temp16.0, %287
  %289 = fadd float %., %47
  %290 = fadd float %temp16.0, %47
  %291 = call float @fabs(float %286)
  %292 = call float @fabs(float %288)
  %293 = fcmp oge float %291, %292
  %294 = sext i1 %293 to i32
  %295 = bitcast i32 %294 to float
  %296 = call float @fabs(float %286)
  %297 = call float @fabs(float %288)
  %298 = fcmp uge float %296, %297
  %299 = select i1 %298, float %296, float %297
  %300 = bitcast float %295 to i32
  %301 = icmp ne i32 %300, 0
  br i1 %301, label %IF98, label %ENDIF97

ENDIF:                                            ; preds = %main_body, %ENDIF262
  %temp7.0 = phi float [ %1060, %ENDIF262 ], [ %42, %main_body ]
  %temp6.0 = phi float [ %1059, %ENDIF262 ], [ %41, %main_body ]
  %temp5.0 = phi float [ %1058, %ENDIF262 ], [ %40, %main_body ]
  %temp4.0 = phi float [ %1057, %ENDIF262 ], [ %39, %main_body ]
  %302 = call i32 @llvm.SI.packf16(float %temp4.0, float %temp5.0)
  %303 = bitcast i32 %302 to float
  %304 = call i32 @llvm.SI.packf16(float %temp6.0, float %temp7.0)
  %305 = bitcast i32 %304 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %303, float %305, float %303, float %305)
  ret void

IF98:                                             ; preds = %ELSE
  %306 = fsub float -0.000000e+00, %.265
  br label %ENDIF97

ENDIF97:                                          ; preds = %ELSE, %IF98
  %temp72.1 = phi float [ %306, %IF98 ], [ %.265, %ELSE ]
  %307 = call float @fabs(float %284)
  %308 = fmul float %307, %234
  %309 = call float @llvm.AMDIL.clamp.(float %308, float 0.000000e+00, float 1.000000e+00)
  %310 = bitcast float %265 to i32
  %311 = xor i32 %310, -1
  %312 = bitcast i32 %311 to float
  %313 = bitcast float %312 to i32
  %314 = icmp ne i32 %313, 0
  %.266 = select i1 %314, float 0.000000e+00, float %23
  %315 = bitcast float %265 to i32
  %316 = icmp ne i32 %315, 0
  %temp44.0 = select i1 %316, float 0.000000e+00, float %24
  %317 = bitcast float %265 to i32
  %318 = xor i32 %317, -1
  %319 = bitcast i32 %318 to float
  %320 = bitcast float %319 to i32
  %321 = icmp ne i32 %320, 0
  br i1 %321, label %IF107, label %ENDIF106

IF107:                                            ; preds = %ENDIF97
  %322 = fmul float %temp72.1, 5.000000e-01
  %323 = fadd float %322, %29
  br label %ENDIF106

ENDIF106:                                         ; preds = %ENDIF97, %IF107
  %temp32.0 = phi float [ %323, %IF107 ], [ %29, %ENDIF97 ]
  %324 = bitcast float %265 to i32
  %325 = icmp ne i32 %324, 0
  br i1 %325, label %IF110, label %ENDIF109

IF110:                                            ; preds = %ENDIF106
  %326 = fmul float %temp72.1, 5.000000e-01
  %327 = fadd float %326, %30
  br label %ENDIF109

ENDIF109:                                         ; preds = %ENDIF106, %IF110
  %temp33.0 = phi float [ %327, %IF110 ], [ %30, %ENDIF106 ]
  %328 = fsub float -0.000000e+00, %.266
  %329 = fadd float %temp32.0, %328
  %330 = fsub float -0.000000e+00, %temp44.0
  %331 = fadd float %temp33.0, %330
  %332 = fadd float %temp32.0, %.266
  %333 = fadd float %temp33.0, %temp44.0
  %334 = fmul float -2.000000e+00, %309
  %335 = fadd float %334, 3.000000e+00
  %336 = bitcast float %329 to i32
  %337 = bitcast float %331 to i32
  %338 = bitcast float 0.000000e+00 to i32
  %339 = insertelement <4 x i32> undef, i32 %336, i32 0
  %340 = insertelement <4 x i32> %339, i32 %337, i32 1
  %341 = insertelement <4 x i32> %340, i32 %338, i32 2
  %342 = insertelement <4 x i32> %341, i32 undef, i32 3
  %343 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %342, <32 x i8> %26, <16 x i8> %28, i32 2)
  %344 = extractelement <4 x float> %343, i32 0
  %345 = extractelement <4 x float> %343, i32 1
  %346 = extractelement <4 x float> %343, i32 2
  %347 = fmul float %344, 0x3FD322D0E0000000
  %348 = fmul float %345, 0x3FE2C8B440000000
  %349 = fadd float %348, %347
  %350 = fmul float %346, 0x3FBD2F1AA0000000
  %351 = fadd float %349, %350
  %352 = fmul float %309, %309
  %353 = bitcast float %332 to i32
  %354 = bitcast float %333 to i32
  %355 = bitcast float 0.000000e+00 to i32
  %356 = insertelement <4 x i32> undef, i32 %353, i32 0
  %357 = insertelement <4 x i32> %356, i32 %354, i32 1
  %358 = insertelement <4 x i32> %357, i32 %355, i32 2
  %359 = insertelement <4 x i32> %358, i32 undef, i32 3
  %360 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %359, <32 x i8> %26, <16 x i8> %28, i32 2)
  %361 = extractelement <4 x float> %360, i32 0
  %362 = extractelement <4 x float> %360, i32 1
  %363 = extractelement <4 x float> %360, i32 2
  %364 = fmul float %361, 0x3FD322D0E0000000
  %365 = fmul float %362, 0x3FE2C8B440000000
  %366 = fadd float %365, %364
  %367 = fmul float %363, 0x3FBD2F1AA0000000
  %368 = fadd float %366, %367
  %369 = bitcast float %295 to i32
  %370 = xor i32 %369, -1
  %371 = bitcast i32 %370 to float
  %372 = bitcast float %371 to i32
  %373 = icmp ne i32 %372, 0
  %.267 = select i1 %373, float %290, float %289
  %374 = fmul float %299, 2.500000e-01
  %375 = fmul float %335, %352
  %376 = fmul float %.267, 5.000000e-01
  %377 = fsub float -0.000000e+00, %376
  %378 = fadd float %47, %377
  %379 = fcmp olt float %378, 0.000000e+00
  %380 = sext i1 %379 to i32
  %381 = bitcast i32 %380 to float
  %382 = fmul float %.267, 5.000000e-01
  %383 = fsub float -0.000000e+00, %382
  %384 = fadd float %351, %383
  %385 = fmul float %.267, 5.000000e-01
  %386 = fsub float -0.000000e+00, %385
  %387 = fadd float %368, %386
  %388 = call float @fabs(float %384)
  %389 = fcmp oge float %388, %374
  %390 = sext i1 %389 to i32
  %391 = bitcast i32 %390 to float
  %392 = call float @fabs(float %387)
  %393 = fcmp oge float %392, %374
  %394 = sext i1 %393 to i32
  %395 = bitcast i32 %394 to float
  %396 = bitcast float %391 to i32
  %397 = xor i32 %396, -1
  %398 = bitcast i32 %397 to float
  %399 = bitcast float %398 to i32
  %400 = icmp ne i32 %399, 0
  br i1 %400, label %IF116, label %ENDIF115

IF116:                                            ; preds = %ENDIF109
  %401 = fmul float %.266, 1.500000e+00
  %402 = fmul float %temp44.0, 1.500000e+00
  %403 = fsub float -0.000000e+00, %401
  %404 = fadd float %329, %403
  %405 = fsub float -0.000000e+00, %402
  %406 = fadd float %331, %405
  br label %ENDIF115

ENDIF115:                                         ; preds = %ENDIF109, %IF116
  %temp48.0 = phi float [ %404, %IF116 ], [ %329, %ENDIF109 ]
  %temp49.0 = phi float [ %406, %IF116 ], [ %331, %ENDIF109 ]
  %407 = bitcast float %391 to i32
  %408 = bitcast float %395 to i32
  %409 = and i32 %407, %408
  %410 = bitcast i32 %409 to float
  %411 = bitcast float %410 to i32
  %412 = xor i32 %411, -1
  %413 = bitcast i32 %412 to float
  %414 = bitcast float %395 to i32
  %415 = xor i32 %414, -1
  %416 = bitcast i32 %415 to float
  %417 = bitcast float %416 to i32
  %418 = icmp ne i32 %417, 0
  br i1 %418, label %IF119, label %ENDIF118

IF119:                                            ; preds = %ENDIF115
  %419 = fmul float %.266, 1.500000e+00
  %420 = fadd float %419, %332
  %421 = fmul float %temp44.0, 1.500000e+00
  %422 = fadd float %421, %333
  br label %ENDIF118

ENDIF118:                                         ; preds = %ENDIF115, %IF119
  %temp33.1 = phi float [ %422, %IF119 ], [ %333, %ENDIF115 ]
  %temp32.1 = phi float [ %420, %IF119 ], [ %332, %ENDIF115 ]
  %423 = bitcast float %413 to i32
  %424 = icmp ne i32 %423, 0
  br i1 %424, label %IF122, label %ENDIF121

IF122:                                            ; preds = %ENDIF118
  %425 = bitcast float %391 to i32
  %426 = xor i32 %425, -1
  %427 = bitcast i32 %426 to float
  %428 = bitcast float %427 to i32
  %429 = icmp ne i32 %428, 0
  br i1 %429, label %IF125, label %ENDIF124

ENDIF121:                                         ; preds = %IF245, %ENDIF241, %ENDIF223, %ENDIF202, %ENDIF181, %ENDIF160, %ENDIF139, %ENDIF118
  %temp33.2 = phi float [ %temp33.1, %ENDIF118 ], [ %temp33.3, %ENDIF139 ], [ %temp33.5, %ENDIF160 ], [ %temp33.7, %ENDIF181 ], [ %temp33.9, %ENDIF202 ], [ %temp33.11, %ENDIF223 ], [ %994, %IF245 ], [ %temp33.11, %ENDIF241 ]
  %temp32.2 = phi float [ %temp32.1, %ENDIF118 ], [ %temp32.3, %ENDIF139 ], [ %temp32.5, %ENDIF160 ], [ %temp32.7, %ENDIF181 ], [ %temp32.9, %ENDIF202 ], [ %temp32.11, %ENDIF223 ], [ %992, %IF245 ], [ %temp32.11, %ENDIF241 ]
  %temp48.1 = phi float [ %temp48.0, %ENDIF118 ], [ %temp48.2, %ENDIF139 ], [ %temp48.4, %ENDIF160 ], [ %temp48.6, %ENDIF181 ], [ %temp48.8, %ENDIF202 ], [ %temp48.10, %ENDIF223 ], [ %temp48.12, %ENDIF241 ], [ %temp48.12, %IF245 ]
  %temp49.1 = phi float [ %temp49.0, %ENDIF118 ], [ %temp49.2, %ENDIF139 ], [ %temp49.4, %ENDIF160 ], [ %temp49.6, %ENDIF181 ], [ %temp49.8, %ENDIF202 ], [ %temp49.10, %ENDIF223 ], [ %temp49.12, %ENDIF241 ], [ %temp49.12, %IF245 ]
  %temp16.1 = phi float [ %387, %ENDIF118 ], [ %temp16.3, %ENDIF139 ], [ %temp16.6, %ENDIF160 ], [ %temp16.9, %ENDIF181 ], [ %temp16.12, %ENDIF202 ], [ %temp16.15, %ENDIF223 ], [ %temp16.18, %ENDIF241 ], [ %temp16.18, %IF245 ]
  %temp8.0 = phi float [ %384, %ENDIF118 ], [ %temp8.2, %ENDIF139 ], [ %temp8.5, %ENDIF160 ], [ %temp8.8, %ENDIF181 ], [ %temp8.11, %ENDIF202 ], [ %temp8.14, %ENDIF223 ], [ %temp8.17, %ENDIF241 ], [ %temp8.17, %IF245 ]
  %430 = fsub float -0.000000e+00, %temp48.1
  %431 = fadd float %29, %430
  %432 = fsub float -0.000000e+00, %29
  %433 = fadd float %temp32.2, %432
  %434 = bitcast float %265 to i32
  %435 = xor i32 %434, -1
  %436 = bitcast i32 %435 to float
  %437 = bitcast float %436 to i32
  %438 = icmp ne i32 %437, 0
  br i1 %438, label %IF248, label %ENDIF247

IF125:                                            ; preds = %IF122
  %439 = bitcast float %temp48.0 to i32
  %440 = bitcast float %temp49.0 to i32
  %441 = bitcast float 0.000000e+00 to i32
  %442 = insertelement <4 x i32> undef, i32 %439, i32 0
  %443 = insertelement <4 x i32> %442, i32 %440, i32 1
  %444 = insertelement <4 x i32> %443, i32 %441, i32 2
  %445 = insertelement <4 x i32> %444, i32 undef, i32 3
  %446 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %445, <32 x i8> %26, <16 x i8> %28, i32 2)
  %447 = extractelement <4 x float> %446, i32 0
  %448 = extractelement <4 x float> %446, i32 1
  %449 = extractelement <4 x float> %446, i32 2
  %450 = fmul float %447, 0x3FD322D0E0000000
  %451 = fmul float %448, 0x3FE2C8B440000000
  %452 = fadd float %451, %450
  %453 = fmul float %449, 0x3FBD2F1AA0000000
  %454 = fadd float %452, %453
  br label %ENDIF124

ENDIF124:                                         ; preds = %IF122, %IF125
  %temp8.1 = phi float [ %454, %IF125 ], [ %384, %IF122 ]
  %455 = bitcast float %395 to i32
  %456 = xor i32 %455, -1
  %457 = bitcast i32 %456 to float
  %458 = bitcast float %457 to i32
  %459 = icmp ne i32 %458, 0
  br i1 %459, label %IF128, label %ENDIF127

IF128:                                            ; preds = %ENDIF124
  %460 = bitcast float %temp32.1 to i32
  %461 = bitcast float %temp33.1 to i32
  %462 = bitcast float 0.000000e+00 to i32
  %463 = insertelement <4 x i32> undef, i32 %460, i32 0
  %464 = insertelement <4 x i32> %463, i32 %461, i32 1
  %465 = insertelement <4 x i32> %464, i32 %462, i32 2
  %466 = insertelement <4 x i32> %465, i32 undef, i32 3
  %467 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %466, <32 x i8> %26, <16 x i8> %28, i32 2)
  %468 = extractelement <4 x float> %467, i32 0
  %469 = extractelement <4 x float> %467, i32 1
  %470 = extractelement <4 x float> %467, i32 2
  %471 = fmul float %468, 0x3FD322D0E0000000
  %472 = fmul float %469, 0x3FE2C8B440000000
  %473 = fadd float %472, %471
  %474 = fmul float %470, 0x3FBD2F1AA0000000
  %475 = fadd float %473, %474
  br label %ENDIF127

ENDIF127:                                         ; preds = %ENDIF124, %IF128
  %temp16.2 = phi float [ %475, %IF128 ], [ %387, %ENDIF124 ]
  %476 = bitcast float %391 to i32
  %477 = xor i32 %476, -1
  %478 = bitcast i32 %477 to float
  %479 = bitcast float %478 to i32
  %480 = icmp ne i32 %479, 0
  br i1 %480, label %IF131, label %ENDIF130

IF131:                                            ; preds = %ENDIF127
  %481 = fmul float %.267, 5.000000e-01
  %482 = fsub float -0.000000e+00, %481
  %483 = fadd float %temp8.1, %482
  br label %ENDIF130

ENDIF130:                                         ; preds = %ENDIF127, %IF131
  %temp8.2 = phi float [ %483, %IF131 ], [ %temp8.1, %ENDIF127 ]
  %484 = bitcast float %395 to i32
  %485 = xor i32 %484, -1
  %486 = bitcast i32 %485 to float
  %487 = bitcast float %486 to i32
  %488 = icmp ne i32 %487, 0
  br i1 %488, label %IF134, label %ENDIF133

IF134:                                            ; preds = %ENDIF130
  %489 = fmul float %.267, 5.000000e-01
  %490 = fsub float -0.000000e+00, %489
  %491 = fadd float %temp16.2, %490
  br label %ENDIF133

ENDIF133:                                         ; preds = %ENDIF130, %IF134
  %temp16.3 = phi float [ %491, %IF134 ], [ %temp16.2, %ENDIF130 ]
  %492 = call float @fabs(float %temp8.2)
  %493 = fcmp oge float %492, %374
  %494 = sext i1 %493 to i32
  %495 = bitcast i32 %494 to float
  %496 = call float @fabs(float %temp16.3)
  %497 = fcmp oge float %496, %374
  %498 = sext i1 %497 to i32
  %499 = bitcast i32 %498 to float
  %500 = bitcast float %495 to i32
  %501 = xor i32 %500, -1
  %502 = bitcast i32 %501 to float
  %503 = bitcast float %502 to i32
  %504 = icmp ne i32 %503, 0
  br i1 %504, label %IF137, label %ENDIF136

IF137:                                            ; preds = %ENDIF133
  %505 = fmul float %.266, 2.000000e+00
  %506 = fmul float %temp44.0, 2.000000e+00
  %507 = fsub float -0.000000e+00, %505
  %508 = fadd float %temp48.0, %507
  %509 = fsub float -0.000000e+00, %506
  %510 = fadd float %temp49.0, %509
  br label %ENDIF136

ENDIF136:                                         ; preds = %ENDIF133, %IF137
  %temp48.2 = phi float [ %508, %IF137 ], [ %temp48.0, %ENDIF133 ]
  %temp49.2 = phi float [ %510, %IF137 ], [ %temp49.0, %ENDIF133 ]
  %511 = bitcast float %495 to i32
  %512 = bitcast float %499 to i32
  %513 = and i32 %511, %512
  %514 = bitcast i32 %513 to float
  %515 = bitcast float %514 to i32
  %516 = xor i32 %515, -1
  %517 = bitcast i32 %516 to float
  %518 = bitcast float %499 to i32
  %519 = xor i32 %518, -1
  %520 = bitcast i32 %519 to float
  %521 = bitcast float %520 to i32
  %522 = icmp ne i32 %521, 0
  br i1 %522, label %IF140, label %ENDIF139

IF140:                                            ; preds = %ENDIF136
  %523 = fmul float %.266, 2.000000e+00
  %524 = fadd float %523, %temp32.1
  %525 = fmul float %temp44.0, 2.000000e+00
  %526 = fadd float %525, %temp33.1
  br label %ENDIF139

ENDIF139:                                         ; preds = %ENDIF136, %IF140
  %temp33.3 = phi float [ %526, %IF140 ], [ %temp33.1, %ENDIF136 ]
  %temp32.3 = phi float [ %524, %IF140 ], [ %temp32.1, %ENDIF136 ]
  %527 = bitcast float %517 to i32
  %528 = icmp ne i32 %527, 0
  br i1 %528, label %IF143, label %ENDIF121

IF143:                                            ; preds = %ENDIF139
  %529 = bitcast float %495 to i32
  %530 = xor i32 %529, -1
  %531 = bitcast i32 %530 to float
  %532 = bitcast float %531 to i32
  %533 = icmp ne i32 %532, 0
  br i1 %533, label %IF146, label %ENDIF145

IF146:                                            ; preds = %IF143
  %534 = bitcast float %temp48.2 to i32
  %535 = bitcast float %temp49.2 to i32
  %536 = bitcast float 0.000000e+00 to i32
  %537 = insertelement <4 x i32> undef, i32 %534, i32 0
  %538 = insertelement <4 x i32> %537, i32 %535, i32 1
  %539 = insertelement <4 x i32> %538, i32 %536, i32 2
  %540 = insertelement <4 x i32> %539, i32 undef, i32 3
  %541 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %540, <32 x i8> %26, <16 x i8> %28, i32 2)
  %542 = extractelement <4 x float> %541, i32 0
  %543 = extractelement <4 x float> %541, i32 1
  %544 = extractelement <4 x float> %541, i32 2
  %545 = fmul float %542, 0x3FD322D0E0000000
  %546 = fmul float %543, 0x3FE2C8B440000000
  %547 = fadd float %546, %545
  %548 = fmul float %544, 0x3FBD2F1AA0000000
  %549 = fadd float %547, %548
  br label %ENDIF145

ENDIF145:                                         ; preds = %IF143, %IF146
  %temp8.4 = phi float [ %549, %IF146 ], [ %temp8.2, %IF143 ]
  %550 = bitcast float %499 to i32
  %551 = xor i32 %550, -1
  %552 = bitcast i32 %551 to float
  %553 = bitcast float %552 to i32
  %554 = icmp ne i32 %553, 0
  br i1 %554, label %IF149, label %ENDIF148

IF149:                                            ; preds = %ENDIF145
  %555 = bitcast float %temp32.3 to i32
  %556 = bitcast float %temp33.3 to i32
  %557 = bitcast float 0.000000e+00 to i32
  %558 = insertelement <4 x i32> undef, i32 %555, i32 0
  %559 = insertelement <4 x i32> %558, i32 %556, i32 1
  %560 = insertelement <4 x i32> %559, i32 %557, i32 2
  %561 = insertelement <4 x i32> %560, i32 undef, i32 3
  %562 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %561, <32 x i8> %26, <16 x i8> %28, i32 2)
  %563 = extractelement <4 x float> %562, i32 0
  %564 = extractelement <4 x float> %562, i32 1
  %565 = extractelement <4 x float> %562, i32 2
  %566 = fmul float %563, 0x3FD322D0E0000000
  %567 = fmul float %564, 0x3FE2C8B440000000
  %568 = fadd float %567, %566
  %569 = fmul float %565, 0x3FBD2F1AA0000000
  %570 = fadd float %568, %569
  br label %ENDIF148

ENDIF148:                                         ; preds = %ENDIF145, %IF149
  %temp16.5 = phi float [ %570, %IF149 ], [ %temp16.3, %ENDIF145 ]
  %571 = bitcast float %495 to i32
  %572 = xor i32 %571, -1
  %573 = bitcast i32 %572 to float
  %574 = bitcast float %573 to i32
  %575 = icmp ne i32 %574, 0
  br i1 %575, label %IF152, label %ENDIF151

IF152:                                            ; preds = %ENDIF148
  %576 = fmul float %.267, 5.000000e-01
  %577 = fsub float -0.000000e+00, %576
  %578 = fadd float %temp8.4, %577
  br label %ENDIF151

ENDIF151:                                         ; preds = %ENDIF148, %IF152
  %temp8.5 = phi float [ %578, %IF152 ], [ %temp8.4, %ENDIF148 ]
  %579 = bitcast float %499 to i32
  %580 = xor i32 %579, -1
  %581 = bitcast i32 %580 to float
  %582 = bitcast float %581 to i32
  %583 = icmp ne i32 %582, 0
  br i1 %583, label %IF155, label %ENDIF154

IF155:                                            ; preds = %ENDIF151
  %584 = fmul float %.267, 5.000000e-01
  %585 = fsub float -0.000000e+00, %584
  %586 = fadd float %temp16.5, %585
  br label %ENDIF154

ENDIF154:                                         ; preds = %ENDIF151, %IF155
  %temp16.6 = phi float [ %586, %IF155 ], [ %temp16.5, %ENDIF151 ]
  %587 = call float @fabs(float %temp8.5)
  %588 = fcmp oge float %587, %374
  %589 = sext i1 %588 to i32
  %590 = bitcast i32 %589 to float
  %591 = call float @fabs(float %temp16.6)
  %592 = fcmp oge float %591, %374
  %593 = sext i1 %592 to i32
  %594 = bitcast i32 %593 to float
  %595 = bitcast float %590 to i32
  %596 = xor i32 %595, -1
  %597 = bitcast i32 %596 to float
  %598 = bitcast float %597 to i32
  %599 = icmp ne i32 %598, 0
  br i1 %599, label %IF158, label %ENDIF157

IF158:                                            ; preds = %ENDIF154
  %600 = fmul float %.266, 2.000000e+00
  %601 = fmul float %temp44.0, 2.000000e+00
  %602 = fsub float -0.000000e+00, %600
  %603 = fadd float %temp48.2, %602
  %604 = fsub float -0.000000e+00, %601
  %605 = fadd float %temp49.2, %604
  br label %ENDIF157

ENDIF157:                                         ; preds = %ENDIF154, %IF158
  %temp48.4 = phi float [ %603, %IF158 ], [ %temp48.2, %ENDIF154 ]
  %temp49.4 = phi float [ %605, %IF158 ], [ %temp49.2, %ENDIF154 ]
  %606 = bitcast float %590 to i32
  %607 = bitcast float %594 to i32
  %608 = and i32 %606, %607
  %609 = bitcast i32 %608 to float
  %610 = bitcast float %609 to i32
  %611 = xor i32 %610, -1
  %612 = bitcast i32 %611 to float
  %613 = bitcast float %594 to i32
  %614 = xor i32 %613, -1
  %615 = bitcast i32 %614 to float
  %616 = bitcast float %615 to i32
  %617 = icmp ne i32 %616, 0
  br i1 %617, label %IF161, label %ENDIF160

IF161:                                            ; preds = %ENDIF157
  %618 = fmul float %.266, 2.000000e+00
  %619 = fadd float %618, %temp32.3
  %620 = fmul float %temp44.0, 2.000000e+00
  %621 = fadd float %620, %temp33.3
  br label %ENDIF160

ENDIF160:                                         ; preds = %ENDIF157, %IF161
  %temp33.5 = phi float [ %621, %IF161 ], [ %temp33.3, %ENDIF157 ]
  %temp32.5 = phi float [ %619, %IF161 ], [ %temp32.3, %ENDIF157 ]
  %622 = bitcast float %612 to i32
  %623 = icmp ne i32 %622, 0
  br i1 %623, label %IF164, label %ENDIF121

IF164:                                            ; preds = %ENDIF160
  %624 = bitcast float %590 to i32
  %625 = xor i32 %624, -1
  %626 = bitcast i32 %625 to float
  %627 = bitcast float %626 to i32
  %628 = icmp ne i32 %627, 0
  br i1 %628, label %IF167, label %ENDIF166

IF167:                                            ; preds = %IF164
  %629 = bitcast float %temp48.4 to i32
  %630 = bitcast float %temp49.4 to i32
  %631 = bitcast float 0.000000e+00 to i32
  %632 = insertelement <4 x i32> undef, i32 %629, i32 0
  %633 = insertelement <4 x i32> %632, i32 %630, i32 1
  %634 = insertelement <4 x i32> %633, i32 %631, i32 2
  %635 = insertelement <4 x i32> %634, i32 undef, i32 3
  %636 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %635, <32 x i8> %26, <16 x i8> %28, i32 2)
  %637 = extractelement <4 x float> %636, i32 0
  %638 = extractelement <4 x float> %636, i32 1
  %639 = extractelement <4 x float> %636, i32 2
  %640 = fmul float %637, 0x3FD322D0E0000000
  %641 = fmul float %638, 0x3FE2C8B440000000
  %642 = fadd float %641, %640
  %643 = fmul float %639, 0x3FBD2F1AA0000000
  %644 = fadd float %642, %643
  br label %ENDIF166

ENDIF166:                                         ; preds = %IF164, %IF167
  %temp8.7 = phi float [ %644, %IF167 ], [ %temp8.5, %IF164 ]
  %645 = bitcast float %594 to i32
  %646 = xor i32 %645, -1
  %647 = bitcast i32 %646 to float
  %648 = bitcast float %647 to i32
  %649 = icmp ne i32 %648, 0
  br i1 %649, label %IF170, label %ENDIF169

IF170:                                            ; preds = %ENDIF166
  %650 = bitcast float %temp32.5 to i32
  %651 = bitcast float %temp33.5 to i32
  %652 = bitcast float 0.000000e+00 to i32
  %653 = insertelement <4 x i32> undef, i32 %650, i32 0
  %654 = insertelement <4 x i32> %653, i32 %651, i32 1
  %655 = insertelement <4 x i32> %654, i32 %652, i32 2
  %656 = insertelement <4 x i32> %655, i32 undef, i32 3
  %657 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %656, <32 x i8> %26, <16 x i8> %28, i32 2)
  %658 = extractelement <4 x float> %657, i32 0
  %659 = extractelement <4 x float> %657, i32 1
  %660 = extractelement <4 x float> %657, i32 2
  %661 = fmul float %658, 0x3FD322D0E0000000
  %662 = fmul float %659, 0x3FE2C8B440000000
  %663 = fadd float %662, %661
  %664 = fmul float %660, 0x3FBD2F1AA0000000
  %665 = fadd float %663, %664
  br label %ENDIF169

ENDIF169:                                         ; preds = %ENDIF166, %IF170
  %temp16.8 = phi float [ %665, %IF170 ], [ %temp16.6, %ENDIF166 ]
  %666 = bitcast float %590 to i32
  %667 = xor i32 %666, -1
  %668 = bitcast i32 %667 to float
  %669 = bitcast float %668 to i32
  %670 = icmp ne i32 %669, 0
  br i1 %670, label %IF173, label %ENDIF172

IF173:                                            ; preds = %ENDIF169
  %671 = fmul float %.267, 5.000000e-01
  %672 = fsub float -0.000000e+00, %671
  %673 = fadd float %temp8.7, %672
  br label %ENDIF172

ENDIF172:                                         ; preds = %ENDIF169, %IF173
  %temp8.8 = phi float [ %673, %IF173 ], [ %temp8.7, %ENDIF169 ]
  %674 = bitcast float %594 to i32
  %675 = xor i32 %674, -1
  %676 = bitcast i32 %675 to float
  %677 = bitcast float %676 to i32
  %678 = icmp ne i32 %677, 0
  br i1 %678, label %IF176, label %ENDIF175

IF176:                                            ; preds = %ENDIF172
  %679 = fmul float %.267, 5.000000e-01
  %680 = fsub float -0.000000e+00, %679
  %681 = fadd float %temp16.8, %680
  br label %ENDIF175

ENDIF175:                                         ; preds = %ENDIF172, %IF176
  %temp16.9 = phi float [ %681, %IF176 ], [ %temp16.8, %ENDIF172 ]
  %682 = call float @fabs(float %temp8.8)
  %683 = fcmp oge float %682, %374
  %684 = sext i1 %683 to i32
  %685 = bitcast i32 %684 to float
  %686 = call float @fabs(float %temp16.9)
  %687 = fcmp oge float %686, %374
  %688 = sext i1 %687 to i32
  %689 = bitcast i32 %688 to float
  %690 = bitcast float %685 to i32
  %691 = xor i32 %690, -1
  %692 = bitcast i32 %691 to float
  %693 = bitcast float %692 to i32
  %694 = icmp ne i32 %693, 0
  br i1 %694, label %IF179, label %ENDIF178

IF179:                                            ; preds = %ENDIF175
  %695 = fmul float %.266, 2.000000e+00
  %696 = fmul float %temp44.0, 2.000000e+00
  %697 = fsub float -0.000000e+00, %695
  %698 = fadd float %temp48.4, %697
  %699 = fsub float -0.000000e+00, %696
  %700 = fadd float %temp49.4, %699
  br label %ENDIF178

ENDIF178:                                         ; preds = %ENDIF175, %IF179
  %temp48.6 = phi float [ %698, %IF179 ], [ %temp48.4, %ENDIF175 ]
  %temp49.6 = phi float [ %700, %IF179 ], [ %temp49.4, %ENDIF175 ]
  %701 = bitcast float %685 to i32
  %702 = bitcast float %689 to i32
  %703 = and i32 %701, %702
  %704 = bitcast i32 %703 to float
  %705 = bitcast float %704 to i32
  %706 = xor i32 %705, -1
  %707 = bitcast i32 %706 to float
  %708 = bitcast float %689 to i32
  %709 = xor i32 %708, -1
  %710 = bitcast i32 %709 to float
  %711 = bitcast float %710 to i32
  %712 = icmp ne i32 %711, 0
  br i1 %712, label %IF182, label %ENDIF181

IF182:                                            ; preds = %ENDIF178
  %713 = fmul float %.266, 2.000000e+00
  %714 = fadd float %713, %temp32.5
  %715 = fmul float %temp44.0, 2.000000e+00
  %716 = fadd float %715, %temp33.5
  br label %ENDIF181

ENDIF181:                                         ; preds = %ENDIF178, %IF182
  %temp33.7 = phi float [ %716, %IF182 ], [ %temp33.5, %ENDIF178 ]
  %temp32.7 = phi float [ %714, %IF182 ], [ %temp32.5, %ENDIF178 ]
  %717 = bitcast float %707 to i32
  %718 = icmp ne i32 %717, 0
  br i1 %718, label %IF185, label %ENDIF121

IF185:                                            ; preds = %ENDIF181
  %719 = bitcast float %685 to i32
  %720 = xor i32 %719, -1
  %721 = bitcast i32 %720 to float
  %722 = bitcast float %721 to i32
  %723 = icmp ne i32 %722, 0
  br i1 %723, label %IF188, label %ENDIF187

IF188:                                            ; preds = %IF185
  %724 = bitcast float %temp48.6 to i32
  %725 = bitcast float %temp49.6 to i32
  %726 = bitcast float 0.000000e+00 to i32
  %727 = insertelement <4 x i32> undef, i32 %724, i32 0
  %728 = insertelement <4 x i32> %727, i32 %725, i32 1
  %729 = insertelement <4 x i32> %728, i32 %726, i32 2
  %730 = insertelement <4 x i32> %729, i32 undef, i32 3
  %731 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %730, <32 x i8> %26, <16 x i8> %28, i32 2)
  %732 = extractelement <4 x float> %731, i32 0
  %733 = extractelement <4 x float> %731, i32 1
  %734 = extractelement <4 x float> %731, i32 2
  %735 = fmul float %732, 0x3FD322D0E0000000
  %736 = fmul float %733, 0x3FE2C8B440000000
  %737 = fadd float %736, %735
  %738 = fmul float %734, 0x3FBD2F1AA0000000
  %739 = fadd float %737, %738
  br label %ENDIF187

ENDIF187:                                         ; preds = %IF185, %IF188
  %temp8.10 = phi float [ %739, %IF188 ], [ %temp8.8, %IF185 ]
  %740 = bitcast float %689 to i32
  %741 = xor i32 %740, -1
  %742 = bitcast i32 %741 to float
  %743 = bitcast float %742 to i32
  %744 = icmp ne i32 %743, 0
  br i1 %744, label %IF191, label %ENDIF190

IF191:                                            ; preds = %ENDIF187
  %745 = bitcast float %temp32.7 to i32
  %746 = bitcast float %temp33.7 to i32
  %747 = bitcast float 0.000000e+00 to i32
  %748 = insertelement <4 x i32> undef, i32 %745, i32 0
  %749 = insertelement <4 x i32> %748, i32 %746, i32 1
  %750 = insertelement <4 x i32> %749, i32 %747, i32 2
  %751 = insertelement <4 x i32> %750, i32 undef, i32 3
  %752 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %751, <32 x i8> %26, <16 x i8> %28, i32 2)
  %753 = extractelement <4 x float> %752, i32 0
  %754 = extractelement <4 x float> %752, i32 1
  %755 = extractelement <4 x float> %752, i32 2
  %756 = fmul float %753, 0x3FD322D0E0000000
  %757 = fmul float %754, 0x3FE2C8B440000000
  %758 = fadd float %757, %756
  %759 = fmul float %755, 0x3FBD2F1AA0000000
  %760 = fadd float %758, %759
  br label %ENDIF190

ENDIF190:                                         ; preds = %ENDIF187, %IF191
  %temp16.11 = phi float [ %760, %IF191 ], [ %temp16.9, %ENDIF187 ]
  %761 = bitcast float %685 to i32
  %762 = xor i32 %761, -1
  %763 = bitcast i32 %762 to float
  %764 = bitcast float %763 to i32
  %765 = icmp ne i32 %764, 0
  br i1 %765, label %IF194, label %ENDIF193

IF194:                                            ; preds = %ENDIF190
  %766 = fmul float %.267, 5.000000e-01
  %767 = fsub float -0.000000e+00, %766
  %768 = fadd float %temp8.10, %767
  br label %ENDIF193

ENDIF193:                                         ; preds = %ENDIF190, %IF194
  %temp8.11 = phi float [ %768, %IF194 ], [ %temp8.10, %ENDIF190 ]
  %769 = bitcast float %689 to i32
  %770 = xor i32 %769, -1
  %771 = bitcast i32 %770 to float
  %772 = bitcast float %771 to i32
  %773 = icmp ne i32 %772, 0
  br i1 %773, label %IF197, label %ENDIF196

IF197:                                            ; preds = %ENDIF193
  %774 = fmul float %.267, 5.000000e-01
  %775 = fsub float -0.000000e+00, %774
  %776 = fadd float %temp16.11, %775
  br label %ENDIF196

ENDIF196:                                         ; preds = %ENDIF193, %IF197
  %temp16.12 = phi float [ %776, %IF197 ], [ %temp16.11, %ENDIF193 ]
  %777 = call float @fabs(float %temp8.11)
  %778 = fcmp oge float %777, %374
  %779 = sext i1 %778 to i32
  %780 = bitcast i32 %779 to float
  %781 = call float @fabs(float %temp16.12)
  %782 = fcmp oge float %781, %374
  %783 = sext i1 %782 to i32
  %784 = bitcast i32 %783 to float
  %785 = bitcast float %780 to i32
  %786 = xor i32 %785, -1
  %787 = bitcast i32 %786 to float
  %788 = bitcast float %787 to i32
  %789 = icmp ne i32 %788, 0
  br i1 %789, label %IF200, label %ENDIF199

IF200:                                            ; preds = %ENDIF196
  %790 = fmul float %.266, 2.000000e+00
  %791 = fmul float %temp44.0, 2.000000e+00
  %792 = fsub float -0.000000e+00, %790
  %793 = fadd float %temp48.6, %792
  %794 = fsub float -0.000000e+00, %791
  %795 = fadd float %temp49.6, %794
  br label %ENDIF199

ENDIF199:                                         ; preds = %ENDIF196, %IF200
  %temp48.8 = phi float [ %793, %IF200 ], [ %temp48.6, %ENDIF196 ]
  %temp49.8 = phi float [ %795, %IF200 ], [ %temp49.6, %ENDIF196 ]
  %796 = bitcast float %780 to i32
  %797 = bitcast float %784 to i32
  %798 = and i32 %796, %797
  %799 = bitcast i32 %798 to float
  %800 = bitcast float %799 to i32
  %801 = xor i32 %800, -1
  %802 = bitcast i32 %801 to float
  %803 = bitcast float %784 to i32
  %804 = xor i32 %803, -1
  %805 = bitcast i32 %804 to float
  %806 = bitcast float %805 to i32
  %807 = icmp ne i32 %806, 0
  br i1 %807, label %IF203, label %ENDIF202

IF203:                                            ; preds = %ENDIF199
  %808 = fmul float %.266, 2.000000e+00
  %809 = fadd float %808, %temp32.7
  %810 = fmul float %temp44.0, 2.000000e+00
  %811 = fadd float %810, %temp33.7
  br label %ENDIF202

ENDIF202:                                         ; preds = %ENDIF199, %IF203
  %temp33.9 = phi float [ %811, %IF203 ], [ %temp33.7, %ENDIF199 ]
  %temp32.9 = phi float [ %809, %IF203 ], [ %temp32.7, %ENDIF199 ]
  %812 = bitcast float %802 to i32
  %813 = icmp ne i32 %812, 0
  br i1 %813, label %IF206, label %ENDIF121

IF206:                                            ; preds = %ENDIF202
  %814 = bitcast float %780 to i32
  %815 = xor i32 %814, -1
  %816 = bitcast i32 %815 to float
  %817 = bitcast float %816 to i32
  %818 = icmp ne i32 %817, 0
  br i1 %818, label %IF209, label %ENDIF208

IF209:                                            ; preds = %IF206
  %819 = bitcast float %temp48.8 to i32
  %820 = bitcast float %temp49.8 to i32
  %821 = bitcast float 0.000000e+00 to i32
  %822 = insertelement <4 x i32> undef, i32 %819, i32 0
  %823 = insertelement <4 x i32> %822, i32 %820, i32 1
  %824 = insertelement <4 x i32> %823, i32 %821, i32 2
  %825 = insertelement <4 x i32> %824, i32 undef, i32 3
  %826 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %825, <32 x i8> %26, <16 x i8> %28, i32 2)
  %827 = extractelement <4 x float> %826, i32 0
  %828 = extractelement <4 x float> %826, i32 1
  %829 = extractelement <4 x float> %826, i32 2
  %830 = fmul float %827, 0x3FD322D0E0000000
  %831 = fmul float %828, 0x3FE2C8B440000000
  %832 = fadd float %831, %830
  %833 = fmul float %829, 0x3FBD2F1AA0000000
  %834 = fadd float %832, %833
  br label %ENDIF208

ENDIF208:                                         ; preds = %IF206, %IF209
  %temp8.13 = phi float [ %834, %IF209 ], [ %temp8.11, %IF206 ]
  %835 = bitcast float %784 to i32
  %836 = xor i32 %835, -1
  %837 = bitcast i32 %836 to float
  %838 = bitcast float %837 to i32
  %839 = icmp ne i32 %838, 0
  br i1 %839, label %IF212, label %ENDIF211

IF212:                                            ; preds = %ENDIF208
  %840 = bitcast float %temp32.9 to i32
  %841 = bitcast float %temp33.9 to i32
  %842 = bitcast float 0.000000e+00 to i32
  %843 = insertelement <4 x i32> undef, i32 %840, i32 0
  %844 = insertelement <4 x i32> %843, i32 %841, i32 1
  %845 = insertelement <4 x i32> %844, i32 %842, i32 2
  %846 = insertelement <4 x i32> %845, i32 undef, i32 3
  %847 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %846, <32 x i8> %26, <16 x i8> %28, i32 2)
  %848 = extractelement <4 x float> %847, i32 0
  %849 = extractelement <4 x float> %847, i32 1
  %850 = extractelement <4 x float> %847, i32 2
  %851 = fmul float %848, 0x3FD322D0E0000000
  %852 = fmul float %849, 0x3FE2C8B440000000
  %853 = fadd float %852, %851
  %854 = fmul float %850, 0x3FBD2F1AA0000000
  %855 = fadd float %853, %854
  br label %ENDIF211

ENDIF211:                                         ; preds = %ENDIF208, %IF212
  %temp16.14 = phi float [ %855, %IF212 ], [ %temp16.12, %ENDIF208 ]
  %856 = bitcast float %780 to i32
  %857 = xor i32 %856, -1
  %858 = bitcast i32 %857 to float
  %859 = bitcast float %858 to i32
  %860 = icmp ne i32 %859, 0
  br i1 %860, label %IF215, label %ENDIF214

IF215:                                            ; preds = %ENDIF211
  %861 = fmul float %.267, 5.000000e-01
  %862 = fsub float -0.000000e+00, %861
  %863 = fadd float %temp8.13, %862
  br label %ENDIF214

ENDIF214:                                         ; preds = %ENDIF211, %IF215
  %temp8.14 = phi float [ %863, %IF215 ], [ %temp8.13, %ENDIF211 ]
  %864 = bitcast float %784 to i32
  %865 = xor i32 %864, -1
  %866 = bitcast i32 %865 to float
  %867 = bitcast float %866 to i32
  %868 = icmp ne i32 %867, 0
  br i1 %868, label %IF218, label %ENDIF217

IF218:                                            ; preds = %ENDIF214
  %869 = fmul float %.267, 5.000000e-01
  %870 = fsub float -0.000000e+00, %869
  %871 = fadd float %temp16.14, %870
  br label %ENDIF217

ENDIF217:                                         ; preds = %ENDIF214, %IF218
  %temp16.15 = phi float [ %871, %IF218 ], [ %temp16.14, %ENDIF214 ]
  %872 = call float @fabs(float %temp8.14)
  %873 = fcmp oge float %872, %374
  %874 = sext i1 %873 to i32
  %875 = bitcast i32 %874 to float
  %876 = call float @fabs(float %temp16.15)
  %877 = fcmp oge float %876, %374
  %878 = sext i1 %877 to i32
  %879 = bitcast i32 %878 to float
  %880 = bitcast float %875 to i32
  %881 = xor i32 %880, -1
  %882 = bitcast i32 %881 to float
  %883 = bitcast float %882 to i32
  %884 = icmp ne i32 %883, 0
  br i1 %884, label %IF221, label %ENDIF220

IF221:                                            ; preds = %ENDIF217
  %885 = fmul float %.266, 4.000000e+00
  %886 = fmul float %temp44.0, 4.000000e+00
  %887 = fsub float -0.000000e+00, %885
  %888 = fadd float %temp48.8, %887
  %889 = fsub float -0.000000e+00, %886
  %890 = fadd float %temp49.8, %889
  br label %ENDIF220

ENDIF220:                                         ; preds = %ENDIF217, %IF221
  %temp48.10 = phi float [ %888, %IF221 ], [ %temp48.8, %ENDIF217 ]
  %temp49.10 = phi float [ %890, %IF221 ], [ %temp49.8, %ENDIF217 ]
  %891 = bitcast float %875 to i32
  %892 = bitcast float %879 to i32
  %893 = and i32 %891, %892
  %894 = bitcast i32 %893 to float
  %895 = bitcast float %894 to i32
  %896 = xor i32 %895, -1
  %897 = bitcast i32 %896 to float
  %898 = bitcast float %879 to i32
  %899 = xor i32 %898, -1
  %900 = bitcast i32 %899 to float
  %901 = bitcast float %900 to i32
  %902 = icmp ne i32 %901, 0
  br i1 %902, label %IF224, label %ENDIF223

IF224:                                            ; preds = %ENDIF220
  %903 = fmul float %.266, 4.000000e+00
  %904 = fadd float %903, %temp32.9
  %905 = fmul float %temp44.0, 4.000000e+00
  %906 = fadd float %905, %temp33.9
  br label %ENDIF223

ENDIF223:                                         ; preds = %ENDIF220, %IF224
  %temp33.11 = phi float [ %906, %IF224 ], [ %temp33.9, %ENDIF220 ]
  %temp32.11 = phi float [ %904, %IF224 ], [ %temp32.9, %ENDIF220 ]
  %907 = bitcast float %897 to i32
  %908 = icmp ne i32 %907, 0
  br i1 %908, label %IF227, label %ENDIF121

IF227:                                            ; preds = %ENDIF223
  %909 = bitcast float %875 to i32
  %910 = xor i32 %909, -1
  %911 = bitcast i32 %910 to float
  %912 = bitcast float %911 to i32
  %913 = icmp ne i32 %912, 0
  br i1 %913, label %IF230, label %ENDIF229

IF230:                                            ; preds = %IF227
  %914 = bitcast float %temp48.10 to i32
  %915 = bitcast float %temp49.10 to i32
  %916 = bitcast float 0.000000e+00 to i32
  %917 = insertelement <4 x i32> undef, i32 %914, i32 0
  %918 = insertelement <4 x i32> %917, i32 %915, i32 1
  %919 = insertelement <4 x i32> %918, i32 %916, i32 2
  %920 = insertelement <4 x i32> %919, i32 undef, i32 3
  %921 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %920, <32 x i8> %26, <16 x i8> %28, i32 2)
  %922 = extractelement <4 x float> %921, i32 0
  %923 = extractelement <4 x float> %921, i32 1
  %924 = extractelement <4 x float> %921, i32 2
  %925 = fmul float %922, 0x3FD322D0E0000000
  %926 = fmul float %923, 0x3FE2C8B440000000
  %927 = fadd float %926, %925
  %928 = fmul float %924, 0x3FBD2F1AA0000000
  %929 = fadd float %927, %928
  br label %ENDIF229

ENDIF229:                                         ; preds = %IF227, %IF230
  %temp8.16 = phi float [ %929, %IF230 ], [ %temp8.14, %IF227 ]
  %930 = bitcast float %879 to i32
  %931 = xor i32 %930, -1
  %932 = bitcast i32 %931 to float
  %933 = bitcast float %932 to i32
  %934 = icmp ne i32 %933, 0
  br i1 %934, label %IF233, label %ENDIF232

IF233:                                            ; preds = %ENDIF229
  %935 = bitcast float %temp32.11 to i32
  %936 = bitcast float %temp33.11 to i32
  %937 = bitcast float 0.000000e+00 to i32
  %938 = insertelement <4 x i32> undef, i32 %935, i32 0
  %939 = insertelement <4 x i32> %938, i32 %936, i32 1
  %940 = insertelement <4 x i32> %939, i32 %937, i32 2
  %941 = insertelement <4 x i32> %940, i32 undef, i32 3
  %942 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %941, <32 x i8> %26, <16 x i8> %28, i32 2)
  %943 = extractelement <4 x float> %942, i32 0
  %944 = extractelement <4 x float> %942, i32 1
  %945 = extractelement <4 x float> %942, i32 2
  %946 = fmul float %943, 0x3FD322D0E0000000
  %947 = fmul float %944, 0x3FE2C8B440000000
  %948 = fadd float %947, %946
  %949 = fmul float %945, 0x3FBD2F1AA0000000
  %950 = fadd float %948, %949
  br label %ENDIF232

ENDIF232:                                         ; preds = %ENDIF229, %IF233
  %temp16.17 = phi float [ %950, %IF233 ], [ %temp16.15, %ENDIF229 ]
  %951 = bitcast float %875 to i32
  %952 = xor i32 %951, -1
  %953 = bitcast i32 %952 to float
  %954 = bitcast float %953 to i32
  %955 = icmp ne i32 %954, 0
  br i1 %955, label %IF236, label %ENDIF235

IF236:                                            ; preds = %ENDIF232
  %956 = fmul float %.267, 5.000000e-01
  %957 = fsub float -0.000000e+00, %956
  %958 = fadd float %temp8.16, %957
  br label %ENDIF235

ENDIF235:                                         ; preds = %ENDIF232, %IF236
  %temp8.17 = phi float [ %958, %IF236 ], [ %temp8.16, %ENDIF232 ]
  %959 = bitcast float %879 to i32
  %960 = xor i32 %959, -1
  %961 = bitcast i32 %960 to float
  %962 = bitcast float %961 to i32
  %963 = icmp ne i32 %962, 0
  br i1 %963, label %IF239, label %ENDIF238

IF239:                                            ; preds = %ENDIF235
  %964 = fmul float %.267, 5.000000e-01
  %965 = fsub float -0.000000e+00, %964
  %966 = fadd float %temp16.17, %965
  br label %ENDIF238

ENDIF238:                                         ; preds = %ENDIF235, %IF239
  %temp16.18 = phi float [ %966, %IF239 ], [ %temp16.17, %ENDIF235 ]
  %967 = call float @fabs(float %temp8.17)
  %968 = fcmp oge float %967, %374
  %969 = sext i1 %968 to i32
  %970 = bitcast i32 %969 to float
  %971 = call float @fabs(float %temp16.18)
  %972 = fcmp oge float %971, %374
  %973 = sext i1 %972 to i32
  %974 = bitcast i32 %973 to float
  %975 = bitcast float %970 to i32
  %976 = xor i32 %975, -1
  %977 = bitcast i32 %976 to float
  %978 = bitcast float %977 to i32
  %979 = icmp ne i32 %978, 0
  br i1 %979, label %IF242, label %ENDIF241

IF242:                                            ; preds = %ENDIF238
  %980 = fmul float %.266, 8.000000e+00
  %981 = fmul float %temp44.0, 8.000000e+00
  %982 = fsub float -0.000000e+00, %980
  %983 = fadd float %temp48.10, %982
  %984 = fsub float -0.000000e+00, %981
  %985 = fadd float %temp49.10, %984
  br label %ENDIF241

ENDIF241:                                         ; preds = %ENDIF238, %IF242
  %temp48.12 = phi float [ %983, %IF242 ], [ %temp48.10, %ENDIF238 ]
  %temp49.12 = phi float [ %985, %IF242 ], [ %temp49.10, %ENDIF238 ]
  %986 = bitcast float %974 to i32
  %987 = xor i32 %986, -1
  %988 = bitcast i32 %987 to float
  %989 = bitcast float %988 to i32
  %990 = icmp ne i32 %989, 0
  br i1 %990, label %IF245, label %ENDIF121

IF245:                                            ; preds = %ENDIF241
  %991 = fmul float %.266, 8.000000e+00
  %992 = fadd float %991, %temp32.11
  %993 = fmul float %temp44.0, 8.000000e+00
  %994 = fadd float %993, %temp33.11
  br label %ENDIF121

IF248:                                            ; preds = %ENDIF121
  %995 = fsub float -0.000000e+00, %temp49.1
  %996 = fadd float %30, %995
  br label %ENDIF247

ENDIF247:                                         ; preds = %ENDIF121, %IF248
  %temp24.0 = phi float [ %996, %IF248 ], [ %431, %ENDIF121 ]
  %997 = bitcast float %265 to i32
  %998 = xor i32 %997, -1
  %999 = bitcast i32 %998 to float
  %1000 = bitcast float %999 to i32
  %1001 = icmp ne i32 %1000, 0
  br i1 %1001, label %IF251, label %ENDIF250

IF251:                                            ; preds = %ENDIF247
  %1002 = fsub float -0.000000e+00, %30
  %1003 = fadd float %temp33.2, %1002
  br label %ENDIF250

ENDIF250:                                         ; preds = %ENDIF247, %IF251
  %temp28.2 = phi float [ %1003, %IF251 ], [ %433, %ENDIF247 ]
  %1004 = fcmp olt float %temp8.0, 0.000000e+00
  %1005 = sext i1 %1004 to i32
  %1006 = bitcast i32 %1005 to float
  %1007 = bitcast float %1006 to i32
  %1008 = bitcast float %381 to i32
  %1009 = icmp ne i32 %1007, %1008
  %1010 = sext i1 %1009 to i32
  %1011 = bitcast i32 %1010 to float
  %1012 = fcmp olt float %temp16.1, 0.000000e+00
  %1013 = sext i1 %1012 to i32
  %1014 = bitcast i32 %1013 to float
  %1015 = bitcast float %1014 to i32
  %1016 = bitcast float %381 to i32
  %1017 = icmp ne i32 %1015, %1016
  %1018 = sext i1 %1017 to i32
  %1019 = bitcast i32 %1018 to float
  %1020 = fadd float %temp28.2, %temp24.0
  %1021 = fdiv float 1.000000e+00, %1020
  %1022 = fcmp uge float %temp24.0, %temp28.2
  %1023 = select i1 %1022, float %temp28.2, float %temp24.0
  %1024 = fcmp olt float %temp24.0, %temp28.2
  %1025 = sext i1 %1024 to i32
  %1026 = bitcast i32 %1025 to float
  %1027 = bitcast float %1026 to i32
  %1028 = icmp ne i32 %1027, 0
  %.268 = select i1 %1028, float %1011, float %1019
  %1029 = fsub float -0.000000e+00, %1021
  %1030 = fmul float %1023, %1029
  %1031 = fadd float %1030, 5.000000e-01
  %1032 = fmul float %375, %375
  %1033 = fmul float %1032, 2.500000e-01
  %1034 = bitcast float %.268 to i32
  %1035 = icmp ne i32 %1034, 0
  %temp8.19 = select i1 %1035, float %1031, float 0.000000e+00
  %1036 = fcmp uge float %temp8.19, %1033
  %1037 = select i1 %1036, float %temp8.19, float %1033
  %1038 = bitcast float %265 to i32
  %1039 = xor i32 %1038, -1
  %1040 = bitcast i32 %1039 to float
  %1041 = bitcast float %1040 to i32
  %1042 = icmp ne i32 %1041, 0
  br i1 %1042, label %IF260, label %ENDIF259

IF260:                                            ; preds = %ENDIF250
  %1043 = fmul float %1037, %temp72.1
  %1044 = fadd float %1043, %29
  br label %ENDIF259

ENDIF259:                                         ; preds = %ENDIF250, %IF260
  %temp.0 = phi float [ %1044, %IF260 ], [ %29, %ENDIF250 ]
  %1045 = bitcast float %265 to i32
  %1046 = icmp ne i32 %1045, 0
  br i1 %1046, label %IF263, label %ENDIF262

IF263:                                            ; preds = %ENDIF259
  %1047 = fmul float %1037, %temp72.1
  %1048 = fadd float %1047, %30
  br label %ENDIF262

ENDIF262:                                         ; preds = %ENDIF259, %IF263
  %temp1.0 = phi float [ %1048, %IF263 ], [ %30, %ENDIF259 ]
  %1049 = bitcast float %temp.0 to i32
  %1050 = bitcast float %temp1.0 to i32
  %1051 = bitcast float 0.000000e+00 to i32
  %1052 = insertelement <4 x i32> undef, i32 %1049, i32 0
  %1053 = insertelement <4 x i32> %1052, i32 %1050, i32 1
  %1054 = insertelement <4 x i32> %1053, i32 %1051, i32 2
  %1055 = insertelement <4 x i32> %1054, i32 undef, i32 3
  %1056 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %1055, <32 x i8> %26, <16 x i8> %28, i32 2)
  %1057 = extractelement <4 x float> %1056, i32 0
  %1058 = extractelement <4 x float> %1056, i32 1
  %1059 = extractelement <4 x float> %1056, i32 2
  %1060 = extractelement <4 x float> %1056, i32 3
  br label %ENDIF
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.samplel.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readonly
declare float @fabs(float) #2

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #3

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readonly }
attributes #3 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg290, %SGPR2_SGPR3 in %vreg291, %SGPR4_SGPR5 in %vreg292, %SGPR7 in %vreg294, %VGPR0 in %vreg295, %VGPR1 in %vreg296

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR7 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR7
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<kill,tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR3_VGPR4_VGPR5_VGPR6<imp-def>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR3_VGPR4_VGPR5_VGPR6<imp-use,kill>, %VGPR3_VGPR4_VGPR5_VGPR6<imp-def>
	%VGPR5<def> = V_MOV_B32_e32 0, %EXEC<imp-use>, %VGPR3_VGPR4_VGPR5_VGPR6<imp-use,kill>, %VGPR3_VGPR4_VGPR5_VGPR6<imp-def>
	%VGPR4<def> = V_MOV_B32_e32 %VGPR2, %EXEC<imp-use>, %VGPR3_VGPR4_VGPR5_VGPR6<imp-def>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%30](align=8)(tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%27](tbaa=!"const")
	S_WAITCNT 127
	%VGPR13_VGPR14_VGPR15_VGPR16<def> = IMAGE_SAMPLE_L_V4_V4 15, 0, 0, 0, 0, 0, 0, 0, %VGPR3_VGPR4_VGPR5_VGPR6, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	%VGPR1<def> = V_MOV_B32_e32 2.990000e-01, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR0<def> = V_MUL_F32_e32 %VGPR13, %VGPR1, %EXEC<imp-use>
	%VGPR9<def> = V_MOV_B32_e32 5.870000e-01, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR14, %VGPR9, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR11<def> = V_MOV_B32_e32 1.140000e-01, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR15, %VGPR11, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%22](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR4_SGPR5_SGPR6_SGPR7, 1; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR18<def> = V_ADD_F32_e32 %SGPR2, %VGPR2, %EXEC<imp-use>, %VGPR17_VGPR18_VGPR19_VGPR20<imp-def>
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR4_SGPR5_SGPR6_SGPR7<kill>, 0; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR17<def> = V_MAD_F32 %SGPR3, 0.000000e+00, %VGPR3, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR17_VGPR18_VGPR19_VGPR20<imp-use,kill>, %VGPR17_VGPR18_VGPR19_VGPR20<imp-def>
	%VGPR19<def> = V_MOV_B32_e32 %VGPR5, %EXEC<imp-use>, %VGPR17_VGPR18_VGPR19_VGPR20<imp-def>
	%VGPR21_VGPR22_VGPR23<def> = IMAGE_SAMPLE_L_V3_V4 7, 0, 0, 0, 0, 0, 0, 0, %VGPR17_VGPR18_VGPR19_VGPR20, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR7<def> = V_MUL_F32_e32 %VGPR21, %VGPR1, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR22, %VGPR9, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR23, %VGPR11, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR21_VGPR22_VGPR23<imp-use,kill>
	%SGPR0_SGPR1<def> = V_CMP_U_F32_e64 %VGPR7, %VGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_GE_F32_e64 %VGPR7, %VGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_OR_B64 %SGPR4_SGPR5<kill>, %SGPR0_SGPR1<kill>
	%VGPR10<def> = V_CNDMASK_B32_e64 %VGPR0, %VGPR7, %SGPR0_SGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR22<def> = V_MAD_F32 %SGPR2, 0.000000e+00, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR21_VGPR22_VGPR23_VGPR24<imp-def>
	%VGPR21<def> = V_ADD_F32_e32 %SGPR3, %VGPR3, %EXEC<imp-use>, %VGPR21_VGPR22_VGPR23_VGPR24<imp-use,kill>, %VGPR21_VGPR22_VGPR23_VGPR24<imp-def>
	%VGPR23<def> = V_MOV_B32_e32 %VGPR5, %EXEC<imp-use>, %VGPR21_VGPR22_VGPR23_VGPR24<imp-def>
	%VGPR25_VGPR26_VGPR27<def> = IMAGE_SAMPLE_L_V3_V4 7, 0, 0, 0, 0, 0, 0, 0, %VGPR21_VGPR22_VGPR23_VGPR24, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR8<def> = V_MUL_F32_e32 %VGPR25, %VGPR1, %EXEC<imp-use>
	%VGPR8<def> = V_MAD_F32 %VGPR26, %VGPR9, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_MAD_F32 %VGPR27, %VGPR11, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR25_VGPR26_VGPR27<imp-use,kill>
	%SGPR4_SGPR5<def> = V_CMP_U_F32_e64 %VGPR8, %VGPR10, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %VGPR8, %VGPR10, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = S_OR_B64 %SGPR6_SGPR7<kill>, %SGPR4_SGPR5<kill>
	%VGPR25<def> = V_CNDMASK_B32_e64 %VGPR10<kill>, %VGPR8, %SGPR4_SGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR21<def> = V_SUBREV_F32_e32 %SGPR3, %VGPR3, %EXEC<imp-use>, %VGPR21_VGPR22_VGPR23_VGPR24<imp-use,kill>, %VGPR21_VGPR22_VGPR23_VGPR24<imp-def>
	%VGPR23<def> = V_MOV_B32_e32 %VGPR5, %EXEC<imp-use>, %VGPR21_VGPR22_VGPR23_VGPR24<imp-def>
	%VGPR21_VGPR22_VGPR23<def> = IMAGE_SAMPLE_L_V3_V4 7, 0, 0, 0, 0, 0, 0, 0, %VGPR21_VGPR22_VGPR23_VGPR24<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR10<def> = V_MUL_F32_e32 %VGPR21, %VGPR1, %EXEC<imp-use>
	%VGPR10<def> = V_MAD_F32 %VGPR22, %VGPR9, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR10<def> = V_MAD_F32 %VGPR23, %VGPR11, %VGPR10<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR21_VGPR22_VGPR23<imp-use,kill>
	%VGPR18<def> = V_SUBREV_F32_e32 %SGPR2, %VGPR2, %EXEC<imp-use>, %VGPR17_VGPR18_VGPR19_VGPR20<imp-use,kill>, %VGPR17_VGPR18_VGPR19_VGPR20<imp-def>
	%VGPR19<def> = V_MOV_B32_e32 %VGPR5, %EXEC<imp-use>, %VGPR17_VGPR18_VGPR19_VGPR20<imp-def>
	%VGPR17_VGPR18_VGPR19<def> = IMAGE_SAMPLE_L_V3_V4 7, 0, 0, 0, 0, 0, 0, 0, %VGPR17_VGPR18_VGPR19_VGPR20<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR1<def> = V_MUL_F32_e32 %VGPR17, %VGPR1<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_MAD_F32 %VGPR18, %VGPR9<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_MAD_F32 %VGPR19, %VGPR11<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR17_VGPR18_VGPR19<imp-use,kill>
	%SGPR4_SGPR5<def> = V_CMP_U_F32_e64 %VGPR12, %VGPR10, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %VGPR12, %VGPR10, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = S_OR_B64 %SGPR6_SGPR7<kill>, %SGPR4_SGPR5<kill>
	%VGPR1<def> = V_CNDMASK_B32_e64 %VGPR10, %VGPR12, %SGPR4_SGPR5, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_U_F32_e64 %VGPR1, %VGPR25, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR20_SGPR21<def> = V_CMP_GE_F32_e64 %VGPR1, %VGPR25, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = S_OR_B64 %SGPR20_SGPR21<kill>, %SGPR6_SGPR7<kill>
	%VGPR1<def> = V_CNDMASK_B32_e64 %VGPR25<kill>, %VGPR1<kill>, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_MUL_F32_e32 1.660000e-01, %VGPR1, %EXEC<imp-use>
	%VGPR11<def> = V_MOV_B32_e32 8.330000e-02, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_LE_F32_e64 %VGPR9, %VGPR11, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR20_SGPR21<def> = V_CMP_U_F32_e64 %VGPR9, %VGPR9, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = S_OR_B64 %SGPR6_SGPR7<kill>, %SGPR20_SGPR21<kill>
	%VGPR9<def> = V_CNDMASK_B32_e64 %VGPR9<kill>, %VGPR11<kill>, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR11<def> = V_CNDMASK_B32_e64 %VGPR7, %VGPR0, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = V_CMP_U_F32_e64 %VGPR8, %VGPR11, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %VGPR8, %VGPR11, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_OR_B64 %SGPR6_SGPR7<kill>, %SGPR0_SGPR1<kill>
	%VGPR11<def> = V_CNDMASK_B32_e64 %VGPR8, %VGPR11<kill>, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR17<def> = V_CNDMASK_B32_e64 %VGPR12, %VGPR10, %SGPR4_SGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = V_CMP_U_F32_e64 %VGPR17, %VGPR11, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_GE_F32_e64 %VGPR17, %VGPR11, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_OR_B64 %SGPR4_SGPR5<kill>, %SGPR0_SGPR1<kill>
	%VGPR11<def> = V_CNDMASK_B32_e64 %VGPR17<kill>, %VGPR11<kill>, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR11<def> = V_SUB_F32_e32 %VGPR1<kill>, %VGPR11<kill>, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = V_CMP_LT_F32_e64 %VGPR11, %VGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_CNDMASK_B32_e64 0, -1, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = V_CMP_EQ_I32_e64 %VGPR1<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_AND_SAVEEXEC_B64 %SGPR0_SGPR1, %EXEC<imp-def>, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_XOR_B64 %EXEC, %SGPR0_SGPR1
	S_CBRANCH_EXECZ <BB#4>, %EXEC
    Successors according to CFG: BB#1(16) BB#4(16)

BB#1: derived from LLVM BB %ELSE
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR12 %VGPR10 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR2 %SGPR3 %VGPR11 %SGPR0_SGPR1 %VGPR8 %VGPR7 %VGPR2
    Predecessors according to CFG: BB#0
	%VGPR9<def> = V_MOV_B32_e32 %SGPR2<kill>, %EXEC<imp-use>
	%VGPR13<def> = V_MOV_B32_e32 %SGPR3<kill>, %EXEC<imp-use>
	%VGPR19<def> = V_SUB_F32_e64 %VGPR2, %VGPR9, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR18_VGPR19_VGPR20_VGPR21<imp-def>
	%VGPR18<def> = V_ADD_F32_e64 %VGPR13, %VGPR3, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR18_VGPR19_VGPR20_VGPR21<imp-use,kill>, %VGPR18_VGPR19_VGPR20_VGPR21<imp-def>
	%VGPR20<def> = V_MOV_B32_e32 0, %EXEC<imp-use>, %VGPR18_VGPR19_VGPR20_VGPR21<imp-use,kill>, %VGPR18_VGPR19_VGPR20_VGPR21<imp-def>
	%VGPR14_VGPR15_VGPR16<def> = IMAGE_SAMPLE_L_V3_V4 7, 0, 0, 0, 0, 0, 0, 0, %VGPR18_VGPR19_VGPR20_VGPR21, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	%VGPR1<def> = V_MOV_B32_e32 2.990000e-01, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR17<def> = V_MUL_F32_e32 %VGPR14, %VGPR1, %EXEC<imp-use>
	%VGPR22<def> = V_MOV_B32_e32 5.870000e-01, %EXEC<imp-use>
	%VGPR17<def> = V_MAD_F32 %VGPR15, %VGPR22, %VGPR17<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR23<def> = V_MOV_B32_e32 1.140000e-01, %EXEC<imp-use>
	%VGPR14<def> = V_MAD_F32 %VGPR16, %VGPR23, %VGPR17<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16<imp-use,kill>
	%VGPR24<def> = V_SUB_F32_e64 %VGPR3, %VGPR13, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR24_VGPR25_VGPR26_VGPR27<imp-def>
	%VGPR25<def> = V_MOV_B32_e32 %VGPR19, %EXEC<imp-use>, %VGPR24_VGPR25_VGPR26_VGPR27<imp-def>
	%VGPR26<def> = V_MOV_B32_e32 %VGPR20, %EXEC<imp-use>, %VGPR24_VGPR25_VGPR26_VGPR27<imp-def>
	%VGPR15_VGPR16_VGPR17<def> = IMAGE_SAMPLE_L_V3_V4 7, 0, 0, 0, 0, 0, 0, 0, %VGPR24_VGPR25_VGPR26_VGPR27, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR28<def> = V_MUL_F32_e32 %VGPR15, %VGPR1, %EXEC<imp-use>
	%VGPR28<def> = V_MAD_F32 %VGPR16, %VGPR22, %VGPR28<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR15<def> = V_MAD_F32 %VGPR17, %VGPR23, %VGPR28<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR15_VGPR16_VGPR17<imp-use,kill>
	%VGPR16<def> = V_ADD_F32_e32 %VGPR15, %VGPR14, %EXEC<imp-use>
	%VGPR16<def> = V_MAD_F32 %VGPR12, -2.000000e+00, %VGPR16<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR16<def> = V_ADD_F32_e64 %VGPR16<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%VGPR17<def> = V_ADD_F32_e64 %VGPR10, %VGPR8, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR28<def> = V_MAD_F32 %VGPR0, -2.000000e+00, %VGPR17, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR28<def> = V_ADD_F32_e64 %VGPR28<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%VGPR28<def> = V_ADD_F32_e32 %VGPR28<kill>, %VGPR28, %EXEC<imp-use>
	%VGPR16<def> = V_ADD_F32_e32 %VGPR28<kill>, %VGPR16<kill>, %EXEC<imp-use>
	%VGPR19<def> = V_ADD_F32_e64 %VGPR9, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR18_VGPR19_VGPR20_VGPR21<imp-use,kill>, %VGPR18_VGPR19_VGPR20_VGPR21<imp-def>
	%VGPR28_VGPR29_VGPR30<def> = IMAGE_SAMPLE_L_V3_V4 7, 0, 0, 0, 0, 0, 0, 0, %VGPR18_VGPR19_VGPR20_VGPR21, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR31<def> = V_MUL_F32_e32 %VGPR28, %VGPR1, %EXEC<imp-use>
	%VGPR31<def> = V_MAD_F32 %VGPR29, %VGPR22, %VGPR31<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR28<def> = V_MAD_F32 %VGPR30, %VGPR23, %VGPR31<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR28_VGPR29_VGPR30<imp-use,kill>
	%VGPR25<def> = V_MOV_B32_e32 %VGPR19, %EXEC<imp-use>, %VGPR24_VGPR25_VGPR26_VGPR27<imp-def>
	%VGPR26<def> = V_MOV_B32_e32 %VGPR20, %EXEC<imp-use>, %VGPR24_VGPR25_VGPR26_VGPR27<imp-def>
	%VGPR18_VGPR19_VGPR20<def> = IMAGE_SAMPLE_L_V3_V4 7, 0, 0, 0, 0, 0, 0, 0, %VGPR24_VGPR25_VGPR26_VGPR27<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR1<def> = V_MUL_F32_e32 %VGPR18, %VGPR1<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_MAD_F32 %VGPR19, %VGPR22<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_MAD_F32 %VGPR20, %VGPR23<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR18_VGPR19_VGPR20<imp-use,kill>
	%VGPR18<def> = V_ADD_F32_e32 %VGPR1, %VGPR28, %EXEC<imp-use>
	%VGPR18<def> = V_MAD_F32 %VGPR7, -2.000000e+00, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR18<def> = V_ADD_F32_e64 %VGPR18<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%VGPR16<def> = V_ADD_F32_e32 %VGPR18<kill>, %VGPR16<kill>, %EXEC<imp-use>
	%VGPR18<def> = V_ADD_F32_e32 %VGPR14<kill>, %VGPR28<kill>, %EXEC<imp-use>
	%VGPR14<def> = V_MAD_F32 %VGPR8, -2.000000e+00, %VGPR18, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR14<def> = V_ADD_F32_e64 %VGPR14<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%VGPR19<def> = V_ADD_F32_e64 %VGPR12, %VGPR7, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR20<def> = V_MAD_F32 %VGPR0, -2.000000e+00, %VGPR19, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR20<def> = V_ADD_F32_e64 %VGPR20<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%VGPR20<def> = V_ADD_F32_e32 %VGPR20<kill>, %VGPR20, %EXEC<imp-use>
	%VGPR14<def> = V_ADD_F32_e32 %VGPR20<kill>, %VGPR14<kill>, %EXEC<imp-use>
	%VGPR20<def> = V_ADD_F32_e32 %VGPR15<kill>, %VGPR1<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_MAD_F32 %VGPR10, -2.000000e+00, %VGPR20, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_ADD_F32_e64 %VGPR1<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_ADD_F32_e32 %VGPR1<kill>, %VGPR14<kill>, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR1<kill>, %VGPR16<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_CNDMASK_B32_e64 0, -1, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_NE_I32_e64 %VGPR1, -1, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR14<def> = V_CNDMASK_B32_e64 %VGPR7<kill>, %VGPR8<kill>, %SGPR2_SGPR3, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_SUBREV_F32_e32 %VGPR0, %VGPR14, %EXEC<imp-use>
	%VGPR22<def> = V_ADD_F32_e64 %VGPR7<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%VGPR15<def> = V_CNDMASK_B32_e64 %VGPR12<kill>, %VGPR10<kill>, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_SUBREV_F32_e32 %VGPR0, %VGPR15, %EXEC<imp-use>
	%VGPR23<def> = V_ADD_F32_e64 %VGPR7<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR23, %VGPR22, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR16<def> = V_CNDMASK_B32_e64 0, -1, %SGPR2_SGPR3, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_NE_I32_e64 %VGPR1, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_CNDMASK_B32_e64 %VGPR13, %VGPR9, %SGPR4_SGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_AND_SAVEEXEC_B64 %SGPR2_SGPR3, %EXEC<imp-def>, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_XOR_B64 %EXEC, %SGPR2_SGPR3
    Successors according to CFG: BB#3(16) BB#5(16)

BB#3: derived from LLVM BB %IF98
    Live Ins: %VGPR13 %VGPR9 %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR17 %VGPR18 %VGPR1 %VGPR3_VGPR4_VGPR5_VGPR6 %VGPR11 %SGPR0_SGPR1 %VGPR19 %VGPR20 %VGPR14 %VGPR22 %VGPR15 %VGPR23 %VGPR16 %SGPR2_SGPR3 %VGPR7 %VGPR2
    Predecessors according to CFG: BB#1
	%VGPR7<def> = V_ADD_F32_e64 %VGPR7<kill>, 0, 0, 0, 0, 1, %EXEC<imp-use>
	S_WAITCNT 1807
    Successors according to CFG: BB#5

BB#5: derived from LLVM BB %ENDIF97
    Live Ins: %VGPR13 %VGPR9 %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR17 %VGPR18 %VGPR1 %VGPR3_VGPR4_VGPR5_VGPR6 %VGPR11 %SGPR0_SGPR1 %VGPR19 %VGPR20 %VGPR14 %VGPR22 %VGPR15 %VGPR23 %VGPR16 %SGPR2_SGPR3 %VGPR7 %VGPR2
    Predecessors according to CFG: BB#1 BB#3
	%EXEC<def> = S_OR_B64 %EXEC, %SGPR2_SGPR3
	%VGPR8<def> = V_ADD_F32_e64 %VGPR20<kill>, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR10<def> = V_ADD_F32_e64 %VGPR19<kill>, %VGPR17<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR10<def> = V_ADD_F32_e32 %VGPR10<kill>, %VGPR10, %EXEC<imp-use>
	%VGPR8<def> = V_ADD_F32_e32 %VGPR10<kill>, %VGPR8<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_F32_e32 8.333334e-02, %VGPR8<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_SUBREV_F32_e32 %VGPR0, %VGPR8<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_ADD_F32_e64 %VGPR8<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%VGPR10<def> = V_RCP_F32_e32 %VGPR11<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_F32_e32 %VGPR8<kill>, %VGPR10<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_ADD_F32_e64 0, %VGPR8<kill>, 0, 1, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_NE_I32_e64 %VGPR1, -1, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR19<def> = V_MOV_B32_e32 %VGPR3, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_AND_SAVEEXEC_B64 %SGPR2_SGPR3, %EXEC<imp-def>, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_XOR_B64 %EXEC, %SGPR2_SGPR3
    Successors according to CFG: BB#6(16) BB#7(16)

BB#6: derived from LLVM BB %IF107
    Live Ins: %VGPR13 %VGPR9 %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR14 %VGPR22 %VGPR15 %VGPR23 %VGPR16 %VGPR12 %SGPR2_SGPR3 %VGPR7 %VGPR2
    Predecessors according to CFG: BB#5
	%VGPR19<def> = V_MAD_F32 %VGPR7, 5.000000e-01, %VGPR3, 0, 0, 0, 0, %EXEC<imp-use>
    Successors according to CFG: BB#7

BB#7: derived from LLVM BB %ENDIF106
    Live Ins: %VGPR13 %VGPR9 %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR14 %VGPR22 %VGPR15 %VGPR23 %VGPR16 %VGPR12 %SGPR2_SGPR3 %VGPR7 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#5 BB#6
	%EXEC<def> = S_OR_B64 %EXEC, %SGPR2_SGPR3
	%SGPR2_SGPR3<def> = V_CMP_NE_I32_e64 %VGPR1, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR25<def> = V_MOV_B32_e32 %VGPR2, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_AND_SAVEEXEC_B64 %SGPR2_SGPR3, %EXEC<imp-def>, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_XOR_B64 %EXEC, %SGPR2_SGPR3
    Successors according to CFG: BB#8(16) BB#9(16)

BB#8: derived from LLVM BB %IF110
    Live Ins: %VGPR13 %VGPR9 %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR14 %VGPR22 %VGPR15 %VGPR23 %VGPR16 %VGPR12 %SGPR2_SGPR3 %VGPR7 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#7
	%VGPR25<def> = V_MAD_F32 %VGPR7, 5.000000e-01, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>
    Successors according to CFG: BB#9

BB#9: derived from LLVM BB %ENDIF109
    Live Ins: %VGPR13 %VGPR9 %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR14 %VGPR22 %VGPR15 %VGPR23 %VGPR16 %VGPR12 %SGPR2_SGPR3 %VGPR7 %VGPR19 %VGPR25 %VGPR2
    Predecessors according to CFG: BB#7 BB#8
	%EXEC<def> = S_OR_B64 %EXEC, %SGPR2_SGPR3
	%SGPR2_SGPR3<def> = V_CMP_NE_I32_e64 %VGPR1, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR20<def> = V_CNDMASK_B32_e64 %VGPR9<kill>, 0.000000e+00, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_ADD_F32_e32 %VGPR25, %VGPR20, %EXEC<imp-use>, %VGPR8_VGPR9_VGPR10_VGPR11<imp-def>
	%SGPR2_SGPR3<def> = V_CMP_NE_I32_e64 %VGPR1, -1, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR21<def> = V_CNDMASK_B32_e64 %VGPR13<kill>, 0.000000e+00, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_ADD_F32_e32 %VGPR19, %VGPR21, %EXEC<imp-use>, %VGPR8_VGPR9_VGPR10_VGPR11<imp-use,kill>, %VGPR8_VGPR9_VGPR10_VGPR11<imp-def>
	%VGPR10<def> = V_MOV_B32_e32 0, %EXEC<imp-use>, %VGPR8_VGPR9_VGPR10_VGPR11<imp-use,kill>, %VGPR8_VGPR9_VGPR10_VGPR11<imp-def>
	%VGPR26_VGPR27_VGPR28<def> = IMAGE_SAMPLE_L_V3_V4 7, 0, 0, 0, 0, 0, 0, 0, %VGPR8_VGPR9_VGPR10_VGPR11, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	%VGPR29<def> = V_MOV_B32_e32 2.990000e-01, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR13<def> = V_MUL_F32_e32 %VGPR26, %VGPR29, %EXEC<imp-use>
	%VGPR30<def> = V_MOV_B32_e32 5.870000e-01, %EXEC<imp-use>
	%VGPR13<def> = V_MAD_F32 %VGPR27, %VGPR30, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR31<def> = V_MOV_B32_e32 1.140000e-01, %EXEC<imp-use>
	%VGPR13<def> = V_MAD_F32 %VGPR28, %VGPR31, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR26_VGPR27_VGPR28<imp-use,kill>
	%VGPR14<def> = V_ADD_F32_e64 %VGPR14<kill>, %VGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR15<def> = V_ADD_F32_e64 %VGPR15<kill>, %VGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_NE_I32_e64 %VGPR16<kill>, -1, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR17<def> = V_CNDMASK_B32_e64 %VGPR15<kill>, %VGPR14<kill>, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR18<def> = V_MAD_F32 %VGPR17, -5.000000e-01, %VGPR13<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_ADD_F32_e64 %VGPR18, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%VGPR14<def> = V_SUB_F32_e32 %VGPR25<kill>, %VGPR20, %EXEC<imp-use>, %VGPR13_VGPR14_VGPR15_VGPR16<imp-def>
	%VGPR13<def> = V_SUB_F32_e32 %VGPR19<kill>, %VGPR21, %EXEC<imp-use>, %VGPR13_VGPR14_VGPR15_VGPR16<imp-use,kill>, %VGPR13_VGPR14_VGPR15_VGPR16<imp-def>
	%VGPR15<def> = V_MOV_B32_e32 %VGPR10, %EXEC<imp-use>, %VGPR13_VGPR14_VGPR15_VGPR16<imp-def>
	%VGPR25_VGPR26_VGPR27<def> = IMAGE_SAMPLE_L_V3_V4 7, 0, 0, 0, 0, 0, 0, 0, %VGPR13_VGPR14_VGPR15_VGPR16, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR19<def> = V_MUL_F32_e32 %VGPR25, %VGPR29<kill>, %EXEC<imp-use>
	%VGPR19<def> = V_MAD_F32 %VGPR26, %VGPR30<kill>, %VGPR19<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR19<def> = V_MAD_F32 %VGPR27, %VGPR31<kill>, %VGPR19<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR25_VGPR26_VGPR27<imp-use,kill>
	%VGPR19<def> = V_MAD_F32 %VGPR17, -5.000000e-01, %VGPR19<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR25<def> = V_ADD_F32_e64 %VGPR19, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_U_F32_e64 %VGPR23, %VGPR22, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_GE_F32_e64 %VGPR23, %VGPR22, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_OR_B64 %SGPR4_SGPR5<kill>, %SGPR2_SGPR3<kill>
	%VGPR22<def> = V_CNDMASK_B32_e64 %VGPR22<kill>, %VGPR23<kill>, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR22<def> = V_MUL_F32_e32 2.500000e-01, %VGPR22<kill>, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR25<kill>, %VGPR22, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR23<def> = V_CNDMASK_B32_e64 0, -1, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_NE_I32_e64 %VGPR23, -1, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_AND_SAVEEXEC_B64 %SGPR2_SGPR3, %EXEC<imp-def>, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_XOR_B64 %EXEC, %SGPR2_SGPR3
    Successors according to CFG: BB#10(16) BB#11(16)

BB#10: derived from LLVM BB %IF116
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR23 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR24 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#9
	%VGPR25<def> = V_MOV_B32_e32 1.500000e+00, %EXEC<imp-use>
	%VGPR26<def> = V_MUL_F32_e32 %VGPR20, %VGPR25, %EXEC<imp-use>
	%VGPR14<def> = V_SUB_F32_e32 %VGPR14, %VGPR26<kill>, %EXEC<imp-use>, %VGPR13_VGPR14_VGPR15_VGPR16<imp-use,kill>, %VGPR13_VGPR14_VGPR15_VGPR16<imp-def>
	%VGPR25<def> = V_MUL_F32_e32 %VGPR21, %VGPR25<kill>, %EXEC<imp-use>
	%VGPR13<def> = V_SUB_F32_e32 %VGPR13, %VGPR25<kill>, %EXEC<imp-use>, %VGPR13_VGPR14_VGPR15_VGPR16<imp-use,kill>, %VGPR13_VGPR14_VGPR15_VGPR16<imp-def>
    Successors according to CFG: BB#11

BB#11: derived from LLVM BB %ENDIF115
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR23 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR24 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#9 BB#10
	%EXEC<def> = S_OR_B64 %EXEC, %SGPR2_SGPR3
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR24<kill>, %VGPR22, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_CNDMASK_B32_e64 0, -1, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_NE_I32_e64 %VGPR24, -1, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_AND_SAVEEXEC_B64 %SGPR2_SGPR3, %EXEC<imp-def>, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_XOR_B64 %EXEC, %SGPR2_SGPR3
    Successors according to CFG: BB#12(16) BB#13(16)

BB#12: derived from LLVM BB %IF119
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR23 %VGPR24 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#11
	%VGPR25<def> = V_MOV_B32_e32 1.500000e+00, %EXEC<imp-use>
	%VGPR9<def> = V_MAD_F32 %VGPR20, %VGPR25, %VGPR9, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR8_VGPR9_VGPR10_VGPR11<imp-use,kill>, %VGPR8_VGPR9_VGPR10_VGPR11<imp-def>
	%VGPR8<def> = V_MAD_F32 %VGPR21, %VGPR25<kill>, %VGPR8, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR8_VGPR9_VGPR10_VGPR11<imp-use,kill>, %VGPR8_VGPR9_VGPR10_VGPR11<imp-def>
    Successors according to CFG: BB#13

BB#13: derived from LLVM BB %ENDIF118
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR23 %VGPR24 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#11 BB#12
	%EXEC<def> = S_OR_B64 %EXEC, %SGPR2_SGPR3
	%VGPR25<def> = V_AND_B32_e64 %VGPR23, %VGPR24, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_NE_I32_e64 %VGPR25<kill>, -1, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_AND_SAVEEXEC_B64 %SGPR2_SGPR3, %EXEC<imp-def>, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_XOR_B64 %EXEC, %SGPR2_SGPR3
	S_CBRANCH_EXECZ <BB#18>, %EXEC
    Successors according to CFG: BB#14(16) BB#18(16)

BB#14: derived from LLVM BB %IF122
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR23 %VGPR24 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#13
	%SGPR4_SGPR5<def> = V_CMP_NE_I32_e64 %VGPR23, -1, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = S_AND_SAVEEXEC_B64 %SGPR4_SGPR5, %EXEC<imp-def>, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = S_XOR_B64 %EXEC, %SGPR4_SGPR5
	S_CBRANCH_EXECZ <BB#19>, %EXEC
    Successors according to CFG: BB#17(16) BB#19(16)

BB#17: derived from LLVM BB %IF125
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR23 %VGPR24 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %VGPR7 %VGPR18 %VGPR2
    Predecessors according to CFG: BB#14
	%VGPR27<def> = V_MOV_B32_e32 0, %EXEC<imp-use>, %VGPR25_VGPR26_VGPR27_VGPR28<imp-def>
	%VGPR25<def> = V_MOV_B32_e32 %VGPR13, %EXEC<imp-use>, %VGPR25_VGPR26_VGPR27_VGPR28<imp-def>
	%VGPR26<def> = V_MOV_B32_e32 %VGPR14, %EXEC<imp-use>, %VGPR25_VGPR26_VGPR27_VGPR28<imp-def>
	%VGPR25_VGPR26_VGPR27<def> = IMAGE_SAMPLE_L_V3_V4 7, 0, 0, 0, 0, 0, 0, 0, %VGPR25_VGPR26_VGPR27_VGPR28<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	%VGPR19<def> = V_MOV_B32_e32 2.990000e-01, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR19<def> = V_MUL_F32_e32 %VGPR25, %VGPR19<kill>, %EXEC<imp-use>
	%VGPR28<def> = V_MOV_B32_e32 5.870000e-01, %EXEC<imp-use>
	%VGPR19<def> = V_MAD_F32 %VGPR26, %VGPR28<kill>, %VGPR19<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR28<def> = V_MOV_B32_e32 1.140000e-01, %EXEC<imp-use>
	%VGPR19<def> = V_MAD_F32 %VGPR27, %VGPR28<kill>, %VGPR19<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR25_VGPR26_VGPR27<imp-use,kill>
    Successors according to CFG: BB#19

BB#19: derived from LLVM BB %ENDIF124
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR23 %VGPR24 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#14 BB#17
	%EXEC<def> = S_OR_B64 %EXEC, %SGPR4_SGPR5
	%SGPR4_SGPR5<def> = V_CMP_NE_I32_e64 %VGPR24, -1, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = S_AND_SAVEEXEC_B64 %SGPR4_SGPR5, %EXEC<imp-def>, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = S_XOR_B64 %EXEC, %SGPR4_SGPR5
    Successors according to CFG: BB#20(16) BB#21(16)

BB#20: derived from LLVM BB %IF128
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR23 %VGPR24 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %VGPR7 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#19
	%VGPR27<def> = V_MOV_B32_e32 0, %EXEC<imp-use>, %VGPR25_VGPR26_VGPR27_VGPR28<imp-def>
	%VGPR25<def> = V_MOV_B32_e32 %VGPR8, %EXEC<imp-use>, %VGPR25_VGPR26_VGPR27_VGPR28<imp-def>
	%VGPR26<def> = V_MOV_B32_e32 %VGPR9, %EXEC<imp-use>, %VGPR25_VGPR26_VGPR27_VGPR28<imp-def>
	%VGPR25_VGPR26_VGPR27<def> = IMAGE_SAMPLE_L_V3_V4 7, 0, 0, 0, 0, 0, 0, 0, %VGPR25_VGPR26_VGPR27_VGPR28<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	%VGPR18<def> = V_MOV_B32_e32 2.990000e-01, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR18<def> = V_MUL_F32_e32 %VGPR25, %VGPR18<kill>, %EXEC<imp-use>
	%VGPR28<def> = V_MOV_B32_e32 5.870000e-01, %EXEC<imp-use>
	%VGPR18<def> = V_MAD_F32 %VGPR26, %VGPR28<kill>, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR28<def> = V_MOV_B32_e32 1.140000e-01, %EXEC<imp-use>
	%VGPR18<def> = V_MAD_F32 %VGPR27, %VGPR28<kill>, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR25_VGPR26_VGPR27<imp-use,kill>
    Successors according to CFG: BB#21

BB#21: derived from LLVM BB %ENDIF127
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR23 %VGPR24 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#19 BB#20
	%EXEC<def> = S_OR_B64 %EXEC, %SGPR4_SGPR5
	%SGPR4_SGPR5<def> = V_CMP_NE_I32_e64 %VGPR23<kill>, -1, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = S_AND_SAVEEXEC_B64 %SGPR4_SGPR5, %EXEC<imp-def>, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = S_XOR_B64 %EXEC, %SGPR4_SGPR5
    Successors according to CFG: BB#22(16) BB#23(16)

BB#22: derived from LLVM BB %IF131
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR24 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#21
	%VGPR19<def> = V_MAD_F32 %VGPR17, -5.000000e-01, %VGPR19<kill>, 0, 0, 0, 0, %EXEC<imp-use>
    Successors according to CFG: BB#23

BB#23: derived from LLVM BB %ENDIF130
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR24 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#21 BB#22
	%EXEC<def> = S_OR_B64 %EXEC, %SGPR4_SGPR5
	%SGPR4_SGPR5<def> = V_CMP_NE_I32_e64 %VGPR24<kill>, -1, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = S_AND_SAVEEXEC_B64 %SGPR4_SGPR5, %EXEC<imp-def>, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = S_XOR_B64 %EXEC, %SGPR4_SGPR5
    Successors according to CFG: BB#24(16) BB#25(16)

BB#24: derived from LLVM BB %IF134
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#23
	%VGPR18<def> = V_MAD_F32 %VGPR17, -5.000000e-01, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>
    Successors according to CFG: BB#25

BB#25: derived from LLVM BB %ENDIF133
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#23 BB#24
	%EXEC<def> = S_OR_B64 %EXEC, %SGPR4_SGPR5
	%VGPR23<def> = V_ADD_F32_e64 %VGPR19, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_GE_F32_e64 %VGPR23<kill>, %VGPR22, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR23<def> = V_CNDMASK_B32_e64 0, -1, %SGPR4_SGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_NE_I32_e64 %VGPR23, -1, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_ADD_F32_e64 %VGPR18, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = S_AND_SAVEEXEC_B64 %SGPR4_SGPR5, %EXEC<imp-def>, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = S_XOR_B64 %EXEC, %SGPR4_SGPR5
    Successors according to CFG: BB#26(16) BB#27(16)

BB#26: derived from LLVM BB %IF137
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR23 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %VGPR24 %SGPR4_SGPR5 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#25
	%VGPR25<def> = V_ADD_F32_e64 %VGPR20, %VGPR20, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR14<def> = V_SUB_F32_e32 %VGPR14, %VGPR25<kill>, %EXEC<imp-use>, %VGPR13_VGPR14_VGPR15_VGPR16<imp-use,kill>, %VGPR13_VGPR14_VGPR15_VGPR16<imp-def>
	%VGPR25<def> = V_ADD_F32_e64 %VGPR21, %VGPR21, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_SUB_F32_e32 %VGPR13, %VGPR25<kill>, %EXEC<imp-use>, %VGPR13_VGPR14_VGPR15_VGPR16<imp-use,kill>, %VGPR13_VGPR14_VGPR15_VGPR16<imp-def>
    Successors according to CFG: BB#27

BB#27: derived from LLVM BB %ENDIF136
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR23 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %VGPR24 %SGPR4_SGPR5 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#25 BB#26
	%EXEC<def> = S_OR_B64 %EXEC, %SGPR4_SGPR5
	%SGPR4_SGPR5<def> = V_CMP_GE_F32_e64 %VGPR24<kill>, %VGPR22, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_CNDMASK_B32_e64 0, -1, %SGPR4_SGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_NE_I32_e64 %VGPR24, -1, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = S_AND_SAVEEXEC_B64 %SGPR4_SGPR5, %EXEC<imp-def>, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = S_XOR_B64 %EXEC, %SGPR4_SGPR5
    Successors according to CFG: BB#28(16) BB#29(16)

BB#28: derived from LLVM BB %IF140
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR23 %VGPR24 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#27
	%VGPR25<def> = V_ADD_F32_e64 %VGPR20, %VGPR20, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_ADD_F32_e32 %VGPR9, %VGPR25<kill>, %EXEC<imp-use>, %VGPR8_VGPR9_VGPR10_VGPR11<imp-use,kill>, %VGPR8_VGPR9_VGPR10_VGPR11<imp-def>
	%VGPR25<def> = V_ADD_F32_e64 %VGPR21, %VGPR21, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_ADD_F32_e32 %VGPR8, %VGPR25<kill>, %EXEC<imp-use>, %VGPR8_VGPR9_VGPR10_VGPR11<imp-use,kill>, %VGPR8_VGPR9_VGPR10_VGPR11<imp-def>
    Successors according to CFG: BB#29

BB#29: derived from LLVM BB %ENDIF139
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR23 %VGPR24 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#27 BB#28
	%EXEC<def> = S_OR_B64 %EXEC, %SGPR4_SGPR5
	%VGPR25<def> = V_AND_B32_e64 %VGPR23, %VGPR24, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_NE_I32_e64 %VGPR25<kill>, -1, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = S_AND_SAVEEXEC_B64 %SGPR4_SGPR5, %EXEC<imp-def>, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = S_XOR_B64 %EXEC, %SGPR4_SGPR5
	S_CBRANCH_EXECZ <BB#32>, %EXEC
    Successors according to CFG: BB#30(16) BB#32(16)

BB#30: derived from LLVM BB %IF143
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR23 %VGPR24 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#29
	%SGPR6_SGPR7<def> = V_CMP_NE_I32_e64 %VGPR23, -1, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = S_AND_SAVEEXEC_B64 %SGPR6_SGPR7, %EXEC<imp-def>, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = S_XOR_B64 %EXEC, %SGPR6_SGPR7
	S_CBRANCH_EXECZ <BB#33>, %EXEC
    Successors according to CFG: BB#31(16) BB#33(16)

BB#31: derived from LLVM BB %IF146
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR23 %VGPR24 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6_SGPR7 %VGPR7 %VGPR18 %VGPR2
    Predecessors according to CFG: BB#30
	%VGPR27<def> = V_MOV_B32_e32 0, %EXEC<imp-use>, %VGPR25_VGPR26_VGPR27_VGPR28<imp-def>
	%VGPR25<def> = V_MOV_B32_e32 %VGPR13, %EXEC<imp-use>, %VGPR25_VGPR26_VGPR27_VGPR28<imp-def>
	%VGPR26<def> = V_MOV_B32_e32 %VGPR14, %EXEC<imp-use>, %VGPR25_VGPR26_VGPR27_VGPR28<imp-def>
	%VGPR25_VGPR26_VGPR27<def> = IMAGE_SAMPLE_L_V3_V4 7, 0, 0, 0, 0, 0, 0, 0, %VGPR25_VGPR26_VGPR27_VGPR28<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	%VGPR19<def> = V_MOV_B32_e32 2.990000e-01, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR19<def> = V_MUL_F32_e32 %VGPR25, %VGPR19<kill>, %EXEC<imp-use>
	%VGPR28<def> = V_MOV_B32_e32 5.870000e-01, %EXEC<imp-use>
	%VGPR19<def> = V_MAD_F32 %VGPR26, %VGPR28<kill>, %VGPR19<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR28<def> = V_MOV_B32_e32 1.140000e-01, %EXEC<imp-use>
	%VGPR19<def> = V_MAD_F32 %VGPR27, %VGPR28<kill>, %VGPR19<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR25_VGPR26_VGPR27<imp-use,kill>
    Successors according to CFG: BB#33

BB#33: derived from LLVM BB %ENDIF145
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR23 %VGPR24 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6_SGPR7 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#30 BB#31
	%EXEC<def> = S_OR_B64 %EXEC, %SGPR6_SGPR7
	%SGPR6_SGPR7<def> = V_CMP_NE_I32_e64 %VGPR24, -1, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = S_AND_SAVEEXEC_B64 %SGPR6_SGPR7, %EXEC<imp-def>, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = S_XOR_B64 %EXEC, %SGPR6_SGPR7
    Successors according to CFG: BB#34(16) BB#35(16)

BB#34: derived from LLVM BB %IF149
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR23 %VGPR24 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6_SGPR7 %VGPR7 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#33
	%VGPR27<def> = V_MOV_B32_e32 0, %EXEC<imp-use>, %VGPR25_VGPR26_VGPR27_VGPR28<imp-def>
	%VGPR25<def> = V_MOV_B32_e32 %VGPR8, %EXEC<imp-use>, %VGPR25_VGPR26_VGPR27_VGPR28<imp-def>
	%VGPR26<def> = V_MOV_B32_e32 %VGPR9, %EXEC<imp-use>, %VGPR25_VGPR26_VGPR27_VGPR28<imp-def>
	%VGPR25_VGPR26_VGPR27<def> = IMAGE_SAMPLE_L_V3_V4 7, 0, 0, 0, 0, 0, 0, 0, %VGPR25_VGPR26_VGPR27_VGPR28<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	%VGPR18<def> = V_MOV_B32_e32 2.990000e-01, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR18<def> = V_MUL_F32_e32 %VGPR25, %VGPR18<kill>, %EXEC<imp-use>
	%VGPR28<def> = V_MOV_B32_e32 5.870000e-01, %EXEC<imp-use>
	%VGPR18<def> = V_MAD_F32 %VGPR26, %VGPR28<kill>, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR28<def> = V_MOV_B32_e32 1.140000e-01, %EXEC<imp-use>
	%VGPR18<def> = V_MAD_F32 %VGPR27, %VGPR28<kill>, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR25_VGPR26_VGPR27<imp-use,kill>
    Successors according to CFG: BB#35

BB#35: derived from LLVM BB %ENDIF148
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR23 %VGPR24 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6_SGPR7 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#33 BB#34
	%EXEC<def> = S_OR_B64 %EXEC, %SGPR6_SGPR7
	%SGPR6_SGPR7<def> = V_CMP_NE_I32_e64 %VGPR23<kill>, -1, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = S_AND_SAVEEXEC_B64 %SGPR6_SGPR7, %EXEC<imp-def>, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = S_XOR_B64 %EXEC, %SGPR6_SGPR7
    Successors according to CFG: BB#36(16) BB#37(16)

BB#36: derived from LLVM BB %IF152
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR24 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6_SGPR7 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#35
	%VGPR19<def> = V_MAD_F32 %VGPR17, -5.000000e-01, %VGPR19<kill>, 0, 0, 0, 0, %EXEC<imp-use>
    Successors according to CFG: BB#37

BB#37: derived from LLVM BB %ENDIF151
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR24 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6_SGPR7 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#35 BB#36
	%EXEC<def> = S_OR_B64 %EXEC, %SGPR6_SGPR7
	%SGPR6_SGPR7<def> = V_CMP_NE_I32_e64 %VGPR24<kill>, -1, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = S_AND_SAVEEXEC_B64 %SGPR6_SGPR7, %EXEC<imp-def>, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = S_XOR_B64 %EXEC, %SGPR6_SGPR7
    Successors according to CFG: BB#38(16) BB#39(16)

BB#38: derived from LLVM BB %IF155
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6_SGPR7 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#37
	%VGPR18<def> = V_MAD_F32 %VGPR17, -5.000000e-01, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>
    Successors according to CFG: BB#39

BB#39: derived from LLVM BB %ENDIF154
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6_SGPR7 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#37 BB#38
	%EXEC<def> = S_OR_B64 %EXEC, %SGPR6_SGPR7
	%VGPR23<def> = V_ADD_F32_e64 %VGPR19, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %VGPR23<kill>, %VGPR22, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR23<def> = V_CNDMASK_B32_e64 0, -1, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_NE_I32_e64 %VGPR23, -1, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_ADD_F32_e64 %VGPR18, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = S_AND_SAVEEXEC_B64 %SGPR6_SGPR7, %EXEC<imp-def>, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = S_XOR_B64 %EXEC, %SGPR6_SGPR7
    Successors according to CFG: BB#40(16) BB#41(16)

BB#40: derived from LLVM BB %IF158
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR23 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %VGPR24 %SGPR6_SGPR7 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#39
	%VGPR25<def> = V_ADD_F32_e64 %VGPR20, %VGPR20, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR14<def> = V_SUB_F32_e32 %VGPR14, %VGPR25<kill>, %EXEC<imp-use>, %VGPR13_VGPR14_VGPR15_VGPR16<imp-use,kill>, %VGPR13_VGPR14_VGPR15_VGPR16<imp-def>
	%VGPR25<def> = V_ADD_F32_e64 %VGPR21, %VGPR21, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_SUB_F32_e32 %VGPR13, %VGPR25<kill>, %EXEC<imp-use>, %VGPR13_VGPR14_VGPR15_VGPR16<imp-use,kill>, %VGPR13_VGPR14_VGPR15_VGPR16<imp-def>
    Successors according to CFG: BB#41

BB#41: derived from LLVM BB %ENDIF157
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR23 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %VGPR24 %SGPR6_SGPR7 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#39 BB#40
	%EXEC<def> = S_OR_B64 %EXEC, %SGPR6_SGPR7
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %VGPR24<kill>, %VGPR22, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_CNDMASK_B32_e64 0, -1, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_NE_I32_e64 %VGPR24, -1, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = S_AND_SAVEEXEC_B64 %SGPR6_SGPR7, %EXEC<imp-def>, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = S_XOR_B64 %EXEC, %SGPR6_SGPR7
    Successors according to CFG: BB#42(16) BB#43(16)

BB#42: derived from LLVM BB %IF161
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR23 %VGPR24 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6_SGPR7 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#41
	%VGPR25<def> = V_ADD_F32_e64 %VGPR20, %VGPR20, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_ADD_F32_e32 %VGPR9, %VGPR25<kill>, %EXEC<imp-use>, %VGPR8_VGPR9_VGPR10_VGPR11<imp-use,kill>, %VGPR8_VGPR9_VGPR10_VGPR11<imp-def>
	%VGPR25<def> = V_ADD_F32_e64 %VGPR21, %VGPR21, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_ADD_F32_e32 %VGPR8, %VGPR25<kill>, %EXEC<imp-use>, %VGPR8_VGPR9_VGPR10_VGPR11<imp-use,kill>, %VGPR8_VGPR9_VGPR10_VGPR11<imp-def>
    Successors according to CFG: BB#43

BB#43: derived from LLVM BB %ENDIF160
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR23 %VGPR24 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6_SGPR7 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#41 BB#42
	%EXEC<def> = S_OR_B64 %EXEC, %SGPR6_SGPR7
	%VGPR25<def> = V_AND_B32_e64 %VGPR23, %VGPR24, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_NE_I32_e64 %VGPR25<kill>, -1, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = S_AND_SAVEEXEC_B64 %SGPR6_SGPR7, %EXEC<imp-def>, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = S_XOR_B64 %EXEC, %SGPR6_SGPR7
	S_CBRANCH_EXECZ <BB#46>, %EXEC
    Successors according to CFG: BB#44(16) BB#46(16)

BB#44: derived from LLVM BB %IF164
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR23 %VGPR24 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6_SGPR7 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#43
	%SGPR20_SGPR21<def> = V_CMP_NE_I32_e64 %VGPR23, -1, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR20_SGPR21<def> = S_AND_SAVEEXEC_B64 %SGPR20_SGPR21, %EXEC<imp-def>, %EXEC<imp-use>
	%SGPR20_SGPR21<def> = S_XOR_B64 %EXEC, %SGPR20_SGPR21
	S_CBRANCH_EXECZ <BB#47>, %EXEC
    Successors according to CFG: BB#45(16) BB#47(16)

BB#45: derived from LLVM BB %IF167
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR23 %VGPR24 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6_SGPR7 %SGPR20_SGPR21 %VGPR7 %VGPR18 %VGPR2
    Predecessors according to CFG: BB#44
	%VGPR27<def> = V_MOV_B32_e32 0, %EXEC<imp-use>, %VGPR25_VGPR26_VGPR27_VGPR28<imp-def>
	%VGPR25<def> = V_MOV_B32_e32 %VGPR13, %EXEC<imp-use>, %VGPR25_VGPR26_VGPR27_VGPR28<imp-def>
	%VGPR26<def> = V_MOV_B32_e32 %VGPR14, %EXEC<imp-use>, %VGPR25_VGPR26_VGPR27_VGPR28<imp-def>
	%VGPR25_VGPR26_VGPR27<def> = IMAGE_SAMPLE_L_V3_V4 7, 0, 0, 0, 0, 0, 0, 0, %VGPR25_VGPR26_VGPR27_VGPR28<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	%VGPR19<def> = V_MOV_B32_e32 2.990000e-01, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR19<def> = V_MUL_F32_e32 %VGPR25, %VGPR19<kill>, %EXEC<imp-use>
	%VGPR28<def> = V_MOV_B32_e32 5.870000e-01, %EXEC<imp-use>
	%VGPR19<def> = V_MAD_F32 %VGPR26, %VGPR28<kill>, %VGPR19<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR28<def> = V_MOV_B32_e32 1.140000e-01, %EXEC<imp-use>
	%VGPR19<def> = V_MAD_F32 %VGPR27, %VGPR28<kill>, %VGPR19<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR25_VGPR26_VGPR27<imp-use,kill>
    Successors according to CFG: BB#47

BB#47: derived from LLVM BB %ENDIF166
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR23 %VGPR24 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6_SGPR7 %SGPR20_SGPR21 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#44 BB#45
	%EXEC<def> = S_OR_B64 %EXEC, %SGPR20_SGPR21
	%SGPR20_SGPR21<def> = V_CMP_NE_I32_e64 %VGPR24, -1, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR20_SGPR21<def> = S_AND_SAVEEXEC_B64 %SGPR20_SGPR21, %EXEC<imp-def>, %EXEC<imp-use>
	%SGPR20_SGPR21<def> = S_XOR_B64 %EXEC, %SGPR20_SGPR21
    Successors according to CFG: BB#48(16) BB#49(16)

BB#48: derived from LLVM BB %IF170
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR23 %VGPR24 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6_SGPR7 %SGPR20_SGPR21 %VGPR7 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#47
	%VGPR27<def> = V_MOV_B32_e32 0, %EXEC<imp-use>, %VGPR25_VGPR26_VGPR27_VGPR28<imp-def>
	%VGPR25<def> = V_MOV_B32_e32 %VGPR8, %EXEC<imp-use>, %VGPR25_VGPR26_VGPR27_VGPR28<imp-def>
	%VGPR26<def> = V_MOV_B32_e32 %VGPR9, %EXEC<imp-use>, %VGPR25_VGPR26_VGPR27_VGPR28<imp-def>
	%VGPR25_VGPR26_VGPR27<def> = IMAGE_SAMPLE_L_V3_V4 7, 0, 0, 0, 0, 0, 0, 0, %VGPR25_VGPR26_VGPR27_VGPR28<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	%VGPR18<def> = V_MOV_B32_e32 2.990000e-01, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR18<def> = V_MUL_F32_e32 %VGPR25, %VGPR18<kill>, %EXEC<imp-use>
	%VGPR28<def> = V_MOV_B32_e32 5.870000e-01, %EXEC<imp-use>
	%VGPR18<def> = V_MAD_F32 %VGPR26, %VGPR28<kill>, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR28<def> = V_MOV_B32_e32 1.140000e-01, %EXEC<imp-use>
	%VGPR18<def> = V_MAD_F32 %VGPR27, %VGPR28<kill>, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR25_VGPR26_VGPR27<imp-use,kill>
    Successors according to CFG: BB#49

BB#49: derived from LLVM BB %ENDIF169
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR23 %VGPR24 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6_SGPR7 %SGPR20_SGPR21 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#47 BB#48
	%EXEC<def> = S_OR_B64 %EXEC, %SGPR20_SGPR21
	%SGPR20_SGPR21<def> = V_CMP_NE_I32_e64 %VGPR23<kill>, -1, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR20_SGPR21<def> = S_AND_SAVEEXEC_B64 %SGPR20_SGPR21, %EXEC<imp-def>, %EXEC<imp-use>
	%SGPR20_SGPR21<def> = S_XOR_B64 %EXEC, %SGPR20_SGPR21
    Successors according to CFG: BB#50(16) BB#51(16)

BB#50: derived from LLVM BB %IF173
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR24 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6_SGPR7 %SGPR20_SGPR21 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#49
	%VGPR19<def> = V_MAD_F32 %VGPR17, -5.000000e-01, %VGPR19<kill>, 0, 0, 0, 0, %EXEC<imp-use>
    Successors according to CFG: BB#51

BB#51: derived from LLVM BB %ENDIF172
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR24 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6_SGPR7 %SGPR20_SGPR21 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#49 BB#50
	%EXEC<def> = S_OR_B64 %EXEC, %SGPR20_SGPR21
	%SGPR20_SGPR21<def> = V_CMP_NE_I32_e64 %VGPR24<kill>, -1, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR20_SGPR21<def> = S_AND_SAVEEXEC_B64 %SGPR20_SGPR21, %EXEC<imp-def>, %EXEC<imp-use>
	%SGPR20_SGPR21<def> = S_XOR_B64 %EXEC, %SGPR20_SGPR21
    Successors according to CFG: BB#52(16) BB#53(16)

BB#52: derived from LLVM BB %IF176
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6_SGPR7 %SGPR20_SGPR21 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#51
	%VGPR18<def> = V_MAD_F32 %VGPR17, -5.000000e-01, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>
    Successors according to CFG: BB#53

BB#53: derived from LLVM BB %ENDIF175
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6_SGPR7 %SGPR20_SGPR21 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#51 BB#52
	%EXEC<def> = S_OR_B64 %EXEC, %SGPR20_SGPR21
	%VGPR23<def> = V_ADD_F32_e64 %VGPR19, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR20_SGPR21<def> = V_CMP_GE_F32_e64 %VGPR23<kill>, %VGPR22, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR23<def> = V_CNDMASK_B32_e64 0, -1, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR20_SGPR21<def> = V_CMP_NE_I32_e64 %VGPR23, -1, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_ADD_F32_e64 %VGPR18, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR20_SGPR21<def> = S_AND_SAVEEXEC_B64 %SGPR20_SGPR21, %EXEC<imp-def>, %EXEC<imp-use>
	%SGPR20_SGPR21<def> = S_XOR_B64 %EXEC, %SGPR20_SGPR21
    Successors according to CFG: BB#54(16) BB#55(16)

BB#54: derived from LLVM BB %IF179
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR23 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6_SGPR7 %VGPR24 %SGPR20_SGPR21 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#53
	%VGPR25<def> = V_ADD_F32_e64 %VGPR20, %VGPR20, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR14<def> = V_SUB_F32_e32 %VGPR14, %VGPR25<kill>, %EXEC<imp-use>, %VGPR13_VGPR14_VGPR15_VGPR16<imp-use,kill>, %VGPR13_VGPR14_VGPR15_VGPR16<imp-def>
	%VGPR25<def> = V_ADD_F32_e64 %VGPR21, %VGPR21, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_SUB_F32_e32 %VGPR13, %VGPR25<kill>, %EXEC<imp-use>, %VGPR13_VGPR14_VGPR15_VGPR16<imp-use,kill>, %VGPR13_VGPR14_VGPR15_VGPR16<imp-def>
    Successors according to CFG: BB#55

BB#55: derived from LLVM BB %ENDIF178
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR23 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6_SGPR7 %VGPR24 %SGPR20_SGPR21 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#53 BB#54
	%EXEC<def> = S_OR_B64 %EXEC, %SGPR20_SGPR21
	%SGPR20_SGPR21<def> = V_CMP_GE_F32_e64 %VGPR24<kill>, %VGPR22, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_CNDMASK_B32_e64 0, -1, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR20_SGPR21<def> = V_CMP_NE_I32_e64 %VGPR24, -1, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR20_SGPR21<def> = S_AND_SAVEEXEC_B64 %SGPR20_SGPR21, %EXEC<imp-def>, %EXEC<imp-use>
	%SGPR20_SGPR21<def> = S_XOR_B64 %EXEC, %SGPR20_SGPR21
    Successors according to CFG: BB#56(16) BB#57(16)

BB#56: derived from LLVM BB %IF182
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR23 %VGPR24 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6_SGPR7 %SGPR20_SGPR21 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#55
	%VGPR25<def> = V_ADD_F32_e64 %VGPR20, %VGPR20, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_ADD_F32_e32 %VGPR9, %VGPR25<kill>, %EXEC<imp-use>, %VGPR8_VGPR9_VGPR10_VGPR11<imp-use,kill>, %VGPR8_VGPR9_VGPR10_VGPR11<imp-def>
	%VGPR25<def> = V_ADD_F32_e64 %VGPR21, %VGPR21, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_ADD_F32_e32 %VGPR8, %VGPR25<kill>, %EXEC<imp-use>, %VGPR8_VGPR9_VGPR10_VGPR11<imp-use,kill>, %VGPR8_VGPR9_VGPR10_VGPR11<imp-def>
    Successors according to CFG: BB#57

BB#57: derived from LLVM BB %ENDIF181
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR23 %VGPR24 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6_SGPR7 %SGPR20_SGPR21 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#55 BB#56
	%EXEC<def> = S_OR_B64 %EXEC, %SGPR20_SGPR21
	%VGPR25<def> = V_AND_B32_e64 %VGPR23, %VGPR24, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR20_SGPR21<def> = V_CMP_NE_I32_e64 %VGPR25<kill>, -1, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR20_SGPR21<def> = S_AND_SAVEEXEC_B64 %SGPR20_SGPR21, %EXEC<imp-def>, %EXEC<imp-use>
	%SGPR20_SGPR21<def> = S_XOR_B64 %EXEC, %SGPR20_SGPR21
	S_CBRANCH_EXECZ <BB#60>, %EXEC
    Successors according to CFG: BB#58(16) BB#60(16)

BB#58: derived from LLVM BB %IF185
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR23 %VGPR24 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6_SGPR7 %SGPR20_SGPR21 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#57
	%SGPR22_SGPR23<def> = V_CMP_NE_I32_e64 %VGPR23, -1, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR22_SGPR23<def> = S_AND_SAVEEXEC_B64 %SGPR22_SGPR23, %EXEC<imp-def>, %EXEC<imp-use>
	%SGPR22_SGPR23<def> = S_XOR_B64 %EXEC, %SGPR22_SGPR23
	S_CBRANCH_EXECZ <BB#61>, %EXEC
    Successors according to CFG: BB#59(16) BB#61(16)

BB#59: derived from LLVM BB %IF188
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR23 %VGPR24 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6_SGPR7 %SGPR20_SGPR21 %SGPR22_SGPR23 %VGPR7 %VGPR18 %VGPR2
    Predecessors according to CFG: BB#58
	%VGPR27<def> = V_MOV_B32_e32 0, %EXEC<imp-use>, %VGPR25_VGPR26_VGPR27_VGPR28<imp-def>
	%VGPR25<def> = V_MOV_B32_e32 %VGPR13, %EXEC<imp-use>, %VGPR25_VGPR26_VGPR27_VGPR28<imp-def>
	%VGPR26<def> = V_MOV_B32_e32 %VGPR14, %EXEC<imp-use>, %VGPR25_VGPR26_VGPR27_VGPR28<imp-def>
	%VGPR25_VGPR26_VGPR27<def> = IMAGE_SAMPLE_L_V3_V4 7, 0, 0, 0, 0, 0, 0, 0, %VGPR25_VGPR26_VGPR27_VGPR28<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	%VGPR19<def> = V_MOV_B32_e32 2.990000e-01, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR19<def> = V_MUL_F32_e32 %VGPR25, %VGPR19<kill>, %EXEC<imp-use>
	%VGPR28<def> = V_MOV_B32_e32 5.870000e-01, %EXEC<imp-use>
	%VGPR19<def> = V_MAD_F32 %VGPR26, %VGPR28<kill>, %VGPR19<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR28<def> = V_MOV_B32_e32 1.140000e-01, %EXEC<imp-use>
	%VGPR19<def> = V_MAD_F32 %VGPR27, %VGPR28<kill>, %VGPR19<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR25_VGPR26_VGPR27<imp-use,kill>
    Successors according to CFG: BB#61

BB#61: derived from LLVM BB %ENDIF187
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR23 %VGPR24 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6_SGPR7 %SGPR20_SGPR21 %SGPR22_SGPR23 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#58 BB#59
	%EXEC<def> = S_OR_B64 %EXEC, %SGPR22_SGPR23
	%SGPR22_SGPR23<def> = V_CMP_NE_I32_e64 %VGPR24, -1, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR22_SGPR23<def> = S_AND_SAVEEXEC_B64 %SGPR22_SGPR23, %EXEC<imp-def>, %EXEC<imp-use>
	%SGPR22_SGPR23<def> = S_XOR_B64 %EXEC, %SGPR22_SGPR23
    Successors according to CFG: BB#62(16) BB#63(16)

BB#62: derived from LLVM BB %IF191
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR23 %VGPR24 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6_SGPR7 %SGPR20_SGPR21 %SGPR22_SGPR23 %VGPR7 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#61
	%VGPR27<def> = V_MOV_B32_e32 0, %EXEC<imp-use>, %VGPR25_VGPR26_VGPR27_VGPR28<imp-def>
	%VGPR25<def> = V_MOV_B32_e32 %VGPR8, %EXEC<imp-use>, %VGPR25_VGPR26_VGPR27_VGPR28<imp-def>
	%VGPR26<def> = V_MOV_B32_e32 %VGPR9, %EXEC<imp-use>, %VGPR25_VGPR26_VGPR27_VGPR28<imp-def>
	%VGPR25_VGPR26_VGPR27<def> = IMAGE_SAMPLE_L_V3_V4 7, 0, 0, 0, 0, 0, 0, 0, %VGPR25_VGPR26_VGPR27_VGPR28<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	%VGPR18<def> = V_MOV_B32_e32 2.990000e-01, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR18<def> = V_MUL_F32_e32 %VGPR25, %VGPR18<kill>, %EXEC<imp-use>
	%VGPR28<def> = V_MOV_B32_e32 5.870000e-01, %EXEC<imp-use>
	%VGPR18<def> = V_MAD_F32 %VGPR26, %VGPR28<kill>, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR28<def> = V_MOV_B32_e32 1.140000e-01, %EXEC<imp-use>
	%VGPR18<def> = V_MAD_F32 %VGPR27, %VGPR28<kill>, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR25_VGPR26_VGPR27<imp-use,kill>
    Successors according to CFG: BB#63

BB#63: derived from LLVM BB %ENDIF190
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR23 %VGPR24 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6_SGPR7 %SGPR20_SGPR21 %SGPR22_SGPR23 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#61 BB#62
	%EXEC<def> = S_OR_B64 %EXEC, %SGPR22_SGPR23
	%SGPR22_SGPR23<def> = V_CMP_NE_I32_e64 %VGPR23<kill>, -1, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR22_SGPR23<def> = S_AND_SAVEEXEC_B64 %SGPR22_SGPR23, %EXEC<imp-def>, %EXEC<imp-use>
	%SGPR22_SGPR23<def> = S_XOR_B64 %EXEC, %SGPR22_SGPR23
    Successors according to CFG: BB#64(16) BB#65(16)

BB#64: derived from LLVM BB %IF194
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR24 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6_SGPR7 %SGPR20_SGPR21 %SGPR22_SGPR23 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#63
	%VGPR19<def> = V_MAD_F32 %VGPR17, -5.000000e-01, %VGPR19<kill>, 0, 0, 0, 0, %EXEC<imp-use>
    Successors according to CFG: BB#65

BB#65: derived from LLVM BB %ENDIF193
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR24 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6_SGPR7 %SGPR20_SGPR21 %SGPR22_SGPR23 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#63 BB#64
	%EXEC<def> = S_OR_B64 %EXEC, %SGPR22_SGPR23
	%SGPR22_SGPR23<def> = V_CMP_NE_I32_e64 %VGPR24<kill>, -1, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR22_SGPR23<def> = S_AND_SAVEEXEC_B64 %SGPR22_SGPR23, %EXEC<imp-def>, %EXEC<imp-use>
	%SGPR22_SGPR23<def> = S_XOR_B64 %EXEC, %SGPR22_SGPR23
    Successors according to CFG: BB#66(16) BB#67(16)

BB#66: derived from LLVM BB %IF197
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6_SGPR7 %SGPR20_SGPR21 %SGPR22_SGPR23 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#65
	%VGPR18<def> = V_MAD_F32 %VGPR17, -5.000000e-01, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>
    Successors according to CFG: BB#67

BB#67: derived from LLVM BB %ENDIF196
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6_SGPR7 %SGPR20_SGPR21 %SGPR22_SGPR23 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#65 BB#66
	%EXEC<def> = S_OR_B64 %EXEC, %SGPR22_SGPR23
	%VGPR23<def> = V_ADD_F32_e64 %VGPR19, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR22_SGPR23<def> = V_CMP_GE_F32_e64 %VGPR23<kill>, %VGPR22, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR23<def> = V_CNDMASK_B32_e64 0, -1, %SGPR22_SGPR23<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR22_SGPR23<def> = V_CMP_NE_I32_e64 %VGPR23, -1, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_ADD_F32_e64 %VGPR18, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR22_SGPR23<def> = S_AND_SAVEEXEC_B64 %SGPR22_SGPR23, %EXEC<imp-def>, %EXEC<imp-use>
	%SGPR22_SGPR23<def> = S_XOR_B64 %EXEC, %SGPR22_SGPR23
    Successors according to CFG: BB#68(16) BB#69(16)

BB#68: derived from LLVM BB %IF200
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR23 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6_SGPR7 %SGPR20_SGPR21 %VGPR24 %SGPR22_SGPR23 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#67
	%VGPR25<def> = V_ADD_F32_e64 %VGPR20, %VGPR20, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR14<def> = V_SUB_F32_e32 %VGPR14, %VGPR25<kill>, %EXEC<imp-use>, %VGPR13_VGPR14_VGPR15_VGPR16<imp-use,kill>, %VGPR13_VGPR14_VGPR15_VGPR16<imp-def>
	%VGPR25<def> = V_ADD_F32_e64 %VGPR21, %VGPR21, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_SUB_F32_e32 %VGPR13, %VGPR25<kill>, %EXEC<imp-use>, %VGPR13_VGPR14_VGPR15_VGPR16<imp-use,kill>, %VGPR13_VGPR14_VGPR15_VGPR16<imp-def>
    Successors according to CFG: BB#69

BB#69: derived from LLVM BB %ENDIF199
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR23 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6_SGPR7 %SGPR20_SGPR21 %VGPR24 %SGPR22_SGPR23 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#67 BB#68
	%EXEC<def> = S_OR_B64 %EXEC, %SGPR22_SGPR23
	%SGPR22_SGPR23<def> = V_CMP_GE_F32_e64 %VGPR24<kill>, %VGPR22, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_CNDMASK_B32_e64 0, -1, %SGPR22_SGPR23<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR22_SGPR23<def> = V_CMP_NE_I32_e64 %VGPR24, -1, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR22_SGPR23<def> = S_AND_SAVEEXEC_B64 %SGPR22_SGPR23, %EXEC<imp-def>, %EXEC<imp-use>
	%SGPR22_SGPR23<def> = S_XOR_B64 %EXEC, %SGPR22_SGPR23
    Successors according to CFG: BB#70(16) BB#71(16)

BB#70: derived from LLVM BB %IF203
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR23 %VGPR24 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6_SGPR7 %SGPR20_SGPR21 %SGPR22_SGPR23 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#69
	%VGPR25<def> = V_ADD_F32_e64 %VGPR20, %VGPR20, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_ADD_F32_e32 %VGPR9, %VGPR25<kill>, %EXEC<imp-use>, %VGPR8_VGPR9_VGPR10_VGPR11<imp-use,kill>, %VGPR8_VGPR9_VGPR10_VGPR11<imp-def>
	%VGPR25<def> = V_ADD_F32_e64 %VGPR21, %VGPR21, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_ADD_F32_e32 %VGPR8, %VGPR25<kill>, %EXEC<imp-use>, %VGPR8_VGPR9_VGPR10_VGPR11<imp-use,kill>, %VGPR8_VGPR9_VGPR10_VGPR11<imp-def>
    Successors according to CFG: BB#71

BB#71: derived from LLVM BB %ENDIF202
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR23 %VGPR24 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6_SGPR7 %SGPR20_SGPR21 %SGPR22_SGPR23 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#69 BB#70
	%EXEC<def> = S_OR_B64 %EXEC, %SGPR22_SGPR23
	%VGPR25<def> = V_AND_B32_e64 %VGPR23, %VGPR24, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR22_SGPR23<def> = V_CMP_NE_I32_e64 %VGPR25<kill>, -1, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR22_SGPR23<def> = S_AND_SAVEEXEC_B64 %SGPR22_SGPR23, %EXEC<imp-def>, %EXEC<imp-use>
	%SGPR22_SGPR23<def> = S_XOR_B64 %EXEC, %SGPR22_SGPR23
	S_CBRANCH_EXECZ <BB#74>, %EXEC
    Successors according to CFG: BB#72(16) BB#74(16)

BB#72: derived from LLVM BB %IF206
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR23 %VGPR24 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6_SGPR7 %SGPR20_SGPR21 %SGPR22_SGPR23 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#71
	%SGPR24_SGPR25<def> = V_CMP_NE_I32_e64 %VGPR23, -1, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR24_SGPR25<def> = S_AND_SAVEEXEC_B64 %SGPR24_SGPR25, %EXEC<imp-def>, %EXEC<imp-use>
	%SGPR24_SGPR25<def> = S_XOR_B64 %EXEC, %SGPR24_SGPR25
	S_CBRANCH_EXECZ <BB#75>, %EXEC
    Successors according to CFG: BB#73(16) BB#75(16)

BB#73: derived from LLVM BB %IF209
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR23 %VGPR24 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6_SGPR7 %SGPR20_SGPR21 %SGPR22_SGPR23 %SGPR24_SGPR25 %VGPR7 %VGPR18 %VGPR2
    Predecessors according to CFG: BB#72
	%VGPR27<def> = V_MOV_B32_e32 0, %EXEC<imp-use>, %VGPR25_VGPR26_VGPR27_VGPR28<imp-def>
	%VGPR25<def> = V_MOV_B32_e32 %VGPR13, %EXEC<imp-use>, %VGPR25_VGPR26_VGPR27_VGPR28<imp-def>
	%VGPR26<def> = V_MOV_B32_e32 %VGPR14, %EXEC<imp-use>, %VGPR25_VGPR26_VGPR27_VGPR28<imp-def>
	%VGPR25_VGPR26_VGPR27<def> = IMAGE_SAMPLE_L_V3_V4 7, 0, 0, 0, 0, 0, 0, 0, %VGPR25_VGPR26_VGPR27_VGPR28<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	%VGPR19<def> = V_MOV_B32_e32 2.990000e-01, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR19<def> = V_MUL_F32_e32 %VGPR25, %VGPR19<kill>, %EXEC<imp-use>
	%VGPR28<def> = V_MOV_B32_e32 5.870000e-01, %EXEC<imp-use>
	%VGPR19<def> = V_MAD_F32 %VGPR26, %VGPR28<kill>, %VGPR19<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR28<def> = V_MOV_B32_e32 1.140000e-01, %EXEC<imp-use>
	%VGPR19<def> = V_MAD_F32 %VGPR27, %VGPR28<kill>, %VGPR19<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR25_VGPR26_VGPR27<imp-use,kill>
    Successors according to CFG: BB#75

BB#75: derived from LLVM BB %ENDIF208
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR23 %VGPR24 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6_SGPR7 %SGPR20_SGPR21 %SGPR22_SGPR23 %SGPR24_SGPR25 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#72 BB#73
	%EXEC<def> = S_OR_B64 %EXEC, %SGPR24_SGPR25
	%SGPR24_SGPR25<def> = V_CMP_NE_I32_e64 %VGPR24, -1, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR24_SGPR25<def> = S_AND_SAVEEXEC_B64 %SGPR24_SGPR25, %EXEC<imp-def>, %EXEC<imp-use>
	%SGPR24_SGPR25<def> = S_XOR_B64 %EXEC, %SGPR24_SGPR25
    Successors according to CFG: BB#76(16) BB#77(16)

BB#76: derived from LLVM BB %IF212
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR23 %VGPR24 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6_SGPR7 %SGPR20_SGPR21 %SGPR22_SGPR23 %SGPR24_SGPR25 %VGPR7 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#75
	%VGPR27<def> = V_MOV_B32_e32 0, %EXEC<imp-use>, %VGPR25_VGPR26_VGPR27_VGPR28<imp-def>
	%VGPR25<def> = V_MOV_B32_e32 %VGPR8, %EXEC<imp-use>, %VGPR25_VGPR26_VGPR27_VGPR28<imp-def>
	%VGPR26<def> = V_MOV_B32_e32 %VGPR9, %EXEC<imp-use>, %VGPR25_VGPR26_VGPR27_VGPR28<imp-def>
	%VGPR25_VGPR26_VGPR27<def> = IMAGE_SAMPLE_L_V3_V4 7, 0, 0, 0, 0, 0, 0, 0, %VGPR25_VGPR26_VGPR27_VGPR28<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	%VGPR18<def> = V_MOV_B32_e32 2.990000e-01, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR18<def> = V_MUL_F32_e32 %VGPR25, %VGPR18<kill>, %EXEC<imp-use>
	%VGPR28<def> = V_MOV_B32_e32 5.870000e-01, %EXEC<imp-use>
	%VGPR18<def> = V_MAD_F32 %VGPR26, %VGPR28<kill>, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR28<def> = V_MOV_B32_e32 1.140000e-01, %EXEC<imp-use>
	%VGPR18<def> = V_MAD_F32 %VGPR27, %VGPR28<kill>, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR25_VGPR26_VGPR27<imp-use,kill>
    Successors according to CFG: BB#77

BB#77: derived from LLVM BB %ENDIF211
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR23 %VGPR24 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6_SGPR7 %SGPR20_SGPR21 %SGPR22_SGPR23 %SGPR24_SGPR25 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#75 BB#76
	%EXEC<def> = S_OR_B64 %EXEC, %SGPR24_SGPR25
	%SGPR24_SGPR25<def> = V_CMP_NE_I32_e64 %VGPR23<kill>, -1, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR24_SGPR25<def> = S_AND_SAVEEXEC_B64 %SGPR24_SGPR25, %EXEC<imp-def>, %EXEC<imp-use>
	%SGPR24_SGPR25<def> = S_XOR_B64 %EXEC, %SGPR24_SGPR25
    Successors according to CFG: BB#78(16) BB#79(16)

BB#78: derived from LLVM BB %IF215
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR24 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6_SGPR7 %SGPR20_SGPR21 %SGPR22_SGPR23 %SGPR24_SGPR25 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#77
	%VGPR19<def> = V_MAD_F32 %VGPR17, -5.000000e-01, %VGPR19<kill>, 0, 0, 0, 0, %EXEC<imp-use>
    Successors according to CFG: BB#79

BB#79: derived from LLVM BB %ENDIF214
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR24 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6_SGPR7 %SGPR20_SGPR21 %SGPR22_SGPR23 %SGPR24_SGPR25 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#77 BB#78
	%EXEC<def> = S_OR_B64 %EXEC, %SGPR24_SGPR25
	%SGPR24_SGPR25<def> = V_CMP_NE_I32_e64 %VGPR24<kill>, -1, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR24_SGPR25<def> = S_AND_SAVEEXEC_B64 %SGPR24_SGPR25, %EXEC<imp-def>, %EXEC<imp-use>
	%SGPR24_SGPR25<def> = S_XOR_B64 %EXEC, %SGPR24_SGPR25
    Successors according to CFG: BB#80(16) BB#81(16)

BB#80: derived from LLVM BB %IF218
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6_SGPR7 %SGPR20_SGPR21 %SGPR22_SGPR23 %SGPR24_SGPR25 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#79
	%VGPR18<def> = V_MAD_F32 %VGPR17, -5.000000e-01, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>
    Successors according to CFG: BB#81

BB#81: derived from LLVM BB %ENDIF217
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6_SGPR7 %SGPR20_SGPR21 %SGPR22_SGPR23 %SGPR24_SGPR25 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#79 BB#80
	%EXEC<def> = S_OR_B64 %EXEC, %SGPR24_SGPR25
	%VGPR23<def> = V_ADD_F32_e64 %VGPR19, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR24_SGPR25<def> = V_CMP_GE_F32_e64 %VGPR23<kill>, %VGPR22, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR23<def> = V_CNDMASK_B32_e64 0, -1, %SGPR24_SGPR25<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR24_SGPR25<def> = V_CMP_NE_I32_e64 %VGPR23, -1, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_ADD_F32_e64 %VGPR18, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR24_SGPR25<def> = S_AND_SAVEEXEC_B64 %SGPR24_SGPR25, %EXEC<imp-def>, %EXEC<imp-use>
	%SGPR24_SGPR25<def> = S_XOR_B64 %EXEC, %SGPR24_SGPR25
    Successors according to CFG: BB#82(16) BB#83(16)

BB#82: derived from LLVM BB %IF221
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR23 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6_SGPR7 %SGPR20_SGPR21 %SGPR22_SGPR23 %VGPR24 %SGPR24_SGPR25 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#81
	%VGPR25<def> = V_MUL_F32_e64 %VGPR20, 4.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR14<def> = V_SUB_F32_e32 %VGPR14, %VGPR25<kill>, %EXEC<imp-use>, %VGPR13_VGPR14_VGPR15_VGPR16<imp-use,kill>, %VGPR13_VGPR14_VGPR15_VGPR16<imp-def>
	%VGPR25<def> = V_MUL_F32_e64 %VGPR21, 4.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR13<def> = V_SUB_F32_e32 %VGPR13, %VGPR25<kill>, %EXEC<imp-use>, %VGPR13_VGPR14_VGPR15_VGPR16<imp-use,kill>, %VGPR13_VGPR14_VGPR15_VGPR16<imp-def>
    Successors according to CFG: BB#83

BB#83: derived from LLVM BB %ENDIF220
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR23 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6_SGPR7 %SGPR20_SGPR21 %SGPR22_SGPR23 %VGPR24 %SGPR24_SGPR25 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#81 BB#82
	%EXEC<def> = S_OR_B64 %EXEC, %SGPR24_SGPR25
	%SGPR24_SGPR25<def> = V_CMP_GE_F32_e64 %VGPR24<kill>, %VGPR22, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_CNDMASK_B32_e64 0, -1, %SGPR24_SGPR25<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR24_SGPR25<def> = V_CMP_NE_I32_e64 %VGPR24, -1, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR24_SGPR25<def> = S_AND_SAVEEXEC_B64 %SGPR24_SGPR25, %EXEC<imp-def>, %EXEC<imp-use>
	%SGPR24_SGPR25<def> = S_XOR_B64 %EXEC, %SGPR24_SGPR25
    Successors according to CFG: BB#84(16) BB#85(16)

BB#84: derived from LLVM BB %IF224
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR23 %VGPR24 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6_SGPR7 %SGPR20_SGPR21 %SGPR22_SGPR23 %SGPR24_SGPR25 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#83
	%VGPR9<def> = V_MAD_F32 %VGPR20, 4.000000e+00, %VGPR9, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR8_VGPR9_VGPR10_VGPR11<imp-use,kill>, %VGPR8_VGPR9_VGPR10_VGPR11<imp-def>
	%VGPR8<def> = V_MAD_F32 %VGPR21, 4.000000e+00, %VGPR8, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR8_VGPR9_VGPR10_VGPR11<imp-use,kill>, %VGPR8_VGPR9_VGPR10_VGPR11<imp-def>
    Successors according to CFG: BB#85

BB#85: derived from LLVM BB %ENDIF223
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR23 %VGPR24 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6_SGPR7 %SGPR20_SGPR21 %SGPR22_SGPR23 %SGPR24_SGPR25 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#83 BB#84
	%EXEC<def> = S_OR_B64 %EXEC, %SGPR24_SGPR25
	%VGPR25<def> = V_AND_B32_e64 %VGPR23, %VGPR24, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR24_SGPR25<def> = V_CMP_NE_I32_e64 %VGPR25<kill>, -1, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR24_SGPR25<def> = S_AND_SAVEEXEC_B64 %SGPR24_SGPR25, %EXEC<imp-def>, %EXEC<imp-use>
	%SGPR24_SGPR25<def> = S_XOR_B64 %EXEC, %SGPR24_SGPR25
	S_CBRANCH_EXECZ <BB#88>, %EXEC
    Successors according to CFG: BB#86(16) BB#88(16)

BB#86: derived from LLVM BB %IF227
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR23 %VGPR24 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6_SGPR7 %SGPR20_SGPR21 %SGPR22_SGPR23 %SGPR24_SGPR25 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#85
	%SGPR26_SGPR27<def> = V_CMP_NE_I32_e64 %VGPR23, -1, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR26_SGPR27<def> = S_AND_SAVEEXEC_B64 %SGPR26_SGPR27, %EXEC<imp-def>, %EXEC<imp-use>
	%SGPR26_SGPR27<def> = S_XOR_B64 %EXEC, %SGPR26_SGPR27
	S_CBRANCH_EXECZ <BB#89>, %EXEC
    Successors according to CFG: BB#87(16) BB#89(16)

BB#87: derived from LLVM BB %IF230
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR23 %VGPR24 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6_SGPR7 %SGPR20_SGPR21 %SGPR22_SGPR23 %SGPR24_SGPR25 %SGPR26_SGPR27 %VGPR7 %VGPR18 %VGPR2
    Predecessors according to CFG: BB#86
	%VGPR27<def> = V_MOV_B32_e32 0, %EXEC<imp-use>, %VGPR25_VGPR26_VGPR27_VGPR28<imp-def>
	%VGPR25<def> = V_MOV_B32_e32 %VGPR13, %EXEC<imp-use>, %VGPR25_VGPR26_VGPR27_VGPR28<imp-def>
	%VGPR26<def> = V_MOV_B32_e32 %VGPR14, %EXEC<imp-use>, %VGPR25_VGPR26_VGPR27_VGPR28<imp-def>
	%VGPR25_VGPR26_VGPR27<def> = IMAGE_SAMPLE_L_V3_V4 7, 0, 0, 0, 0, 0, 0, 0, %VGPR25_VGPR26_VGPR27_VGPR28<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	%VGPR19<def> = V_MOV_B32_e32 2.990000e-01, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR19<def> = V_MUL_F32_e32 %VGPR25, %VGPR19<kill>, %EXEC<imp-use>
	%VGPR28<def> = V_MOV_B32_e32 5.870000e-01, %EXEC<imp-use>
	%VGPR19<def> = V_MAD_F32 %VGPR26, %VGPR28<kill>, %VGPR19<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR28<def> = V_MOV_B32_e32 1.140000e-01, %EXEC<imp-use>
	%VGPR19<def> = V_MAD_F32 %VGPR27, %VGPR28<kill>, %VGPR19<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR25_VGPR26_VGPR27<imp-use,kill>
    Successors according to CFG: BB#89

BB#89: derived from LLVM BB %ENDIF229
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR23 %VGPR24 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6_SGPR7 %SGPR20_SGPR21 %SGPR22_SGPR23 %SGPR24_SGPR25 %SGPR26_SGPR27 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#86 BB#87
	%EXEC<def> = S_OR_B64 %EXEC, %SGPR26_SGPR27
	%SGPR26_SGPR27<def> = V_CMP_NE_I32_e64 %VGPR24, -1, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR26_SGPR27<def> = S_AND_SAVEEXEC_B64 %SGPR26_SGPR27, %EXEC<imp-def>, %EXEC<imp-use>
	%SGPR26_SGPR27<def> = S_XOR_B64 %EXEC, %SGPR26_SGPR27
    Successors according to CFG: BB#90(16) BB#91(16)

BB#90: derived from LLVM BB %IF233
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR23 %VGPR24 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6_SGPR7 %SGPR20_SGPR21 %SGPR22_SGPR23 %SGPR24_SGPR25 %SGPR26_SGPR27 %VGPR7 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#89
	%VGPR27<def> = V_MOV_B32_e32 0, %EXEC<imp-use>, %VGPR25_VGPR26_VGPR27_VGPR28<imp-def>
	%VGPR25<def> = V_MOV_B32_e32 %VGPR8, %EXEC<imp-use>, %VGPR25_VGPR26_VGPR27_VGPR28<imp-def>
	%VGPR26<def> = V_MOV_B32_e32 %VGPR9, %EXEC<imp-use>, %VGPR25_VGPR26_VGPR27_VGPR28<imp-def>
	%VGPR25_VGPR26_VGPR27<def> = IMAGE_SAMPLE_L_V3_V4 7, 0, 0, 0, 0, 0, 0, 0, %VGPR25_VGPR26_VGPR27_VGPR28<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	%VGPR18<def> = V_MOV_B32_e32 2.990000e-01, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR18<def> = V_MUL_F32_e32 %VGPR25, %VGPR18<kill>, %EXEC<imp-use>
	%VGPR28<def> = V_MOV_B32_e32 5.870000e-01, %EXEC<imp-use>
	%VGPR18<def> = V_MAD_F32 %VGPR26, %VGPR28<kill>, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR28<def> = V_MOV_B32_e32 1.140000e-01, %EXEC<imp-use>
	%VGPR18<def> = V_MAD_F32 %VGPR27, %VGPR28<kill>, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR25_VGPR26_VGPR27<imp-use,kill>
    Successors according to CFG: BB#91

BB#91: derived from LLVM BB %ENDIF232
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR23 %VGPR24 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6_SGPR7 %SGPR20_SGPR21 %SGPR22_SGPR23 %SGPR24_SGPR25 %SGPR26_SGPR27 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#89 BB#90
	%EXEC<def> = S_OR_B64 %EXEC, %SGPR26_SGPR27
	%SGPR26_SGPR27<def> = V_CMP_NE_I32_e64 %VGPR23<kill>, -1, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR26_SGPR27<def> = S_AND_SAVEEXEC_B64 %SGPR26_SGPR27, %EXEC<imp-def>, %EXEC<imp-use>
	%SGPR26_SGPR27<def> = S_XOR_B64 %EXEC, %SGPR26_SGPR27
    Successors according to CFG: BB#92(16) BB#93(16)

BB#92: derived from LLVM BB %IF236
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR24 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6_SGPR7 %SGPR20_SGPR21 %SGPR22_SGPR23 %SGPR24_SGPR25 %SGPR26_SGPR27 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#91
	%VGPR19<def> = V_MAD_F32 %VGPR17, -5.000000e-01, %VGPR19<kill>, 0, 0, 0, 0, %EXEC<imp-use>
    Successors according to CFG: BB#93

BB#93: derived from LLVM BB %ENDIF235
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR24 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6_SGPR7 %SGPR20_SGPR21 %SGPR22_SGPR23 %SGPR24_SGPR25 %SGPR26_SGPR27 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#91 BB#92
	%EXEC<def> = S_OR_B64 %EXEC, %SGPR26_SGPR27
	%SGPR26_SGPR27<def> = V_CMP_NE_I32_e64 %VGPR24<kill>, -1, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR26_SGPR27<def> = S_AND_SAVEEXEC_B64 %SGPR26_SGPR27, %EXEC<imp-def>, %EXEC<imp-use>
	%SGPR26_SGPR27<def> = S_XOR_B64 %EXEC, %SGPR26_SGPR27
    Successors according to CFG: BB#94(16) BB#95(16)

BB#94: derived from LLVM BB %IF239
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6_SGPR7 %SGPR20_SGPR21 %SGPR22_SGPR23 %SGPR24_SGPR25 %SGPR26_SGPR27 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#93
	%VGPR18<def> = V_MAD_F32 %VGPR17, -5.000000e-01, %VGPR18<kill>, 0, 0, 0, 0, %EXEC<imp-use>
    Successors according to CFG: BB#95

BB#95: derived from LLVM BB %ENDIF238
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6_SGPR7 %SGPR20_SGPR21 %SGPR22_SGPR23 %SGPR24_SGPR25 %SGPR26_SGPR27 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#93 BB#94
	%EXEC<def> = S_OR_B64 %EXEC, %SGPR26_SGPR27
	%VGPR23<def> = V_ADD_F32_e64 %VGPR19, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR26_SGPR27<def> = V_CMP_GE_F32_e64 %VGPR23<kill>, %VGPR22, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR23<def> = V_CNDMASK_B32_e64 0, -1, %SGPR26_SGPR27<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR26_SGPR27<def> = V_CMP_NE_I32_e64 %VGPR23<kill>, -1, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR23<def> = V_ADD_F32_e64 %VGPR18, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR26_SGPR27<def> = S_AND_SAVEEXEC_B64 %SGPR26_SGPR27, %EXEC<imp-def>, %EXEC<imp-use>
	%SGPR26_SGPR27<def> = S_XOR_B64 %EXEC, %SGPR26_SGPR27
    Successors according to CFG: BB#96(16) BB#97(16)

BB#96: derived from LLVM BB %IF242
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6_SGPR7 %SGPR20_SGPR21 %SGPR22_SGPR23 %SGPR24_SGPR25 %VGPR23 %SGPR26_SGPR27 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#95
	%VGPR24<def> = V_MOV_B32_e32 8.000000e+00, %EXEC<imp-use>
	%VGPR25<def> = V_MUL_F32_e32 %VGPR20, %VGPR24, %EXEC<imp-use>
	%VGPR14<def> = V_SUB_F32_e32 %VGPR14, %VGPR25<kill>, %EXEC<imp-use>, %VGPR13_VGPR14_VGPR15_VGPR16<imp-use,kill>, %VGPR13_VGPR14_VGPR15_VGPR16<imp-def>
	%VGPR24<def> = V_MUL_F32_e32 %VGPR21, %VGPR24<kill>, %EXEC<imp-use>
	%VGPR13<def> = V_SUB_F32_e32 %VGPR13, %VGPR24<kill>, %EXEC<imp-use>, %VGPR13_VGPR14_VGPR15_VGPR16<imp-use,kill>, %VGPR13_VGPR14_VGPR15_VGPR16<imp-def>
    Successors according to CFG: BB#97

BB#97: derived from LLVM BB %ENDIF241
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR22 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6_SGPR7 %SGPR20_SGPR21 %SGPR22_SGPR23 %SGPR24_SGPR25 %VGPR23 %SGPR26_SGPR27 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#95 BB#96
	%EXEC<def> = S_OR_B64 %EXEC, %SGPR26_SGPR27
	%SGPR26_SGPR27<def> = V_CMP_GE_F32_e64 %VGPR23<kill>, %VGPR22<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR22<def> = V_CNDMASK_B32_e64 0, -1, %SGPR26_SGPR27<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR26_SGPR27<def> = V_CMP_NE_I32_e64 %VGPR22<kill>, -1, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR26_SGPR27<def> = S_AND_SAVEEXEC_B64 %SGPR26_SGPR27, %EXEC<imp-def>, %EXEC<imp-use>
	%SGPR26_SGPR27<def> = S_XOR_B64 %EXEC, %SGPR26_SGPR27
    Successors according to CFG: BB#98(16) BB#15(16)

BB#98: derived from LLVM BB %IF245
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR21 %VGPR20 %VGPR17 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6_SGPR7 %SGPR20_SGPR21 %SGPR22_SGPR23 %SGPR24_SGPR25 %SGPR26_SGPR27 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#97
	%VGPR22<def> = V_MOV_B32_e32 8.000000e+00, %EXEC<imp-use>
	%VGPR9<def> = V_MAD_F32 %VGPR20<kill>, %VGPR22, %VGPR9, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR8_VGPR9_VGPR10_VGPR11<imp-use,kill>, %VGPR8_VGPR9_VGPR10_VGPR11<imp-def>
	%VGPR8<def> = V_MAD_F32 %VGPR21<kill>, %VGPR22<kill>, %VGPR8, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR8_VGPR9_VGPR10_VGPR11<imp-use,kill>, %VGPR8_VGPR9_VGPR10_VGPR11<imp-def>
    Successors according to CFG: BB#15

BB#15: derived from LLVM BB %Flow
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR17 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6_SGPR7 %SGPR20_SGPR21 %SGPR22_SGPR23 %SGPR24_SGPR25 %SGPR26_SGPR27 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#97 BB#98
	%EXEC<def> = S_OR_B64 %EXEC, %SGPR26_SGPR27
    Successors according to CFG: BB#88

BB#88: derived from LLVM BB %Flow269
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR17 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6_SGPR7 %SGPR20_SGPR21 %SGPR22_SGPR23 %SGPR24_SGPR25 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#85 BB#15
	%EXEC<def> = S_OR_B64 %EXEC, %SGPR24_SGPR25
    Successors according to CFG: BB#74

BB#74: derived from LLVM BB %Flow270
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR17 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6_SGPR7 %SGPR20_SGPR21 %SGPR22_SGPR23 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#71 BB#88
	%EXEC<def> = S_OR_B64 %EXEC, %SGPR22_SGPR23
    Successors according to CFG: BB#60

BB#60: derived from LLVM BB %Flow271
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR17 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6_SGPR7 %SGPR20_SGPR21 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#57 BB#74
	%EXEC<def> = S_OR_B64 %EXEC, %SGPR20_SGPR21
    Successors according to CFG: BB#46

BB#46: derived from LLVM BB %Flow272
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR17 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR6_SGPR7 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#43 BB#60
	%EXEC<def> = S_OR_B64 %EXEC, %SGPR6_SGPR7
    Successors according to CFG: BB#32

BB#32: derived from LLVM BB %Flow273
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR17 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %SGPR4_SGPR5 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#29 BB#46
	%EXEC<def> = S_OR_B64 %EXEC, %SGPR4_SGPR5
    Successors according to CFG: BB#18

BB#18: derived from LLVM BB %Flow274
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR1 %VGPR17 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR12 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#13 BB#32
	%EXEC<def> = S_OR_B64 %EXEC, %SGPR2_SGPR3
	%VGPR20<def> = V_MOV_B32_e32 3.000000e+00, %EXEC<imp-use>
	%VGPR20<def> = V_MAD_F32 %VGPR12, -2.000000e+00, %VGPR20<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_MUL_F32_e64 %VGPR12<kill>, %VGPR12, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_MUL_F32_e32 %VGPR20<kill>, %VGPR12<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR17<kill>, -5.000000e-01, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_LT_F32_e64 %VGPR0<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR17<def> = V_CNDMASK_B32_e64 0, -1, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
    Successors according to CFG: BB#16

BB#16: derived from LLVM BB %ENDIF121
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR1 %VGPR12 %VGPR17 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#18
	%VGPR0<def> = V_SUB_F32_e64 %VGPR3, %VGPR13, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_NE_I32_e64 %VGPR1, -1, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_AND_SAVEEXEC_B64 %SGPR2_SGPR3, %EXEC<imp-def>, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_XOR_B64 %EXEC, %SGPR2_SGPR3
    Successors according to CFG: BB#99(16) BB#100(16)

BB#99: derived from LLVM BB %IF248
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR1 %VGPR12 %VGPR17 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR8_VGPR9_VGPR10_VGPR11 %VGPR13_VGPR14_VGPR15_VGPR16 %SGPR2_SGPR3 %VGPR7 %VGPR18 %VGPR19 %VGPR2
    Predecessors according to CFG: BB#16
	%VGPR0<def> = V_SUB_F32_e64 %VGPR2, %VGPR14, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR13_VGPR14_VGPR15_VGPR16<imp-use,kill>
    Successors according to CFG: BB#100

BB#100: derived from LLVM BB %ENDIF247
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR1 %VGPR12 %VGPR17 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR8_VGPR9_VGPR10_VGPR11 %SGPR2_SGPR3 %VGPR7 %VGPR18 %VGPR19 %VGPR0 %VGPR2
    Predecessors according to CFG: BB#16 BB#99
	%EXEC<def> = S_OR_B64 %EXEC, %SGPR2_SGPR3
	%VGPR13<def> = V_SUB_F32_e64 %VGPR8, %VGPR3, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_NE_I32_e64 %VGPR1, -1, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_AND_SAVEEXEC_B64 %SGPR2_SGPR3, %EXEC<imp-def>, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_XOR_B64 %EXEC, %SGPR2_SGPR3
    Successors according to CFG: BB#101(16) BB#102(16)

BB#101: derived from LLVM BB %IF251
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR1 %VGPR12 %VGPR17 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %VGPR8_VGPR9_VGPR10_VGPR11 %SGPR2_SGPR3 %VGPR7 %VGPR18 %VGPR19 %VGPR0 %VGPR2
    Predecessors according to CFG: BB#100
	%VGPR13<def> = V_SUB_F32_e64 %VGPR9, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR8_VGPR9_VGPR10_VGPR11<imp-use,kill>
    Successors according to CFG: BB#102

BB#102: derived from LLVM BB %ENDIF250
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR1 %VGPR12 %VGPR17 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %SGPR2_SGPR3 %VGPR7 %VGPR18 %VGPR19 %VGPR0 %VGPR13 %VGPR2
    Predecessors according to CFG: BB#100 BB#101
	%EXEC<def> = S_OR_B64 %EXEC, %SGPR2_SGPR3
	%SGPR2_SGPR3<def> = V_CMP_LT_F32_e64 %VGPR0, %VGPR13, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_LT_F32_e64 %VGPR19<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_CNDMASK_B32_e64 0, -1, %SGPR4_SGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_NE_I32_e64 %VGPR8<kill>, %VGPR17, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_CNDMASK_B32_e64 0, -1, %SGPR4_SGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_LT_F32_e64 %VGPR18<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_CNDMASK_B32_e64 0, -1, %SGPR4_SGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_NE_I32_e64 %VGPR9<kill>, %VGPR17<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_CNDMASK_B32_e64 0, -1, %SGPR4_SGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_CNDMASK_B32_e64 %VGPR9<kill>, %VGPR8<kill>, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_NE_I32_e64 %VGPR8<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_U_F32_e64 %VGPR0, %VGPR13, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %VGPR0, %VGPR13, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = S_OR_B64 %SGPR6_SGPR7<kill>, %SGPR4_SGPR5<kill>
	%VGPR8<def> = V_CNDMASK_B32_e64 %VGPR0, %VGPR13, %SGPR4_SGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_F32_e64 %VGPR13<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_RCP_F32_e32 %VGPR0<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_F32_e32 -1.000000e+00, %VGPR0<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR8<kill>, %VGPR0<kill>, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_CNDMASK_B32_e64 0.000000e+00, %VGPR0<kill>, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_F32_e64 %VGPR12<kill>, %VGPR12, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_F32_e32 2.500000e-01, %VGPR8<kill>, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_U_F32_e64 %VGPR0, %VGPR8, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_GE_F32_e64 %VGPR0, %VGPR8, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_OR_B64 %SGPR4_SGPR5<kill>, %SGPR2_SGPR3<kill>
	%VGPR0<def> = V_CNDMASK_B32_e64 %VGPR8<kill>, %VGPR0<kill>, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_NE_I32_e64 %VGPR1, -1, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_AND_SAVEEXEC_B64 %SGPR2_SGPR3, %EXEC<imp-def>, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_XOR_B64 %EXEC, %SGPR2_SGPR3
    Successors according to CFG: BB#103(16) BB#104(16)

BB#103: derived from LLVM BB %IF260
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR1 %VGPR0 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %SGPR2_SGPR3 %VGPR7 %VGPR2
    Predecessors according to CFG: BB#102
	%VGPR3<def> = V_MAD_F32 %VGPR0, %VGPR7, %VGPR3, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR3_VGPR4_VGPR5_VGPR6<imp-use,kill>, %VGPR3_VGPR4_VGPR5_VGPR6<imp-def>
    Successors according to CFG: BB#104

BB#104: derived from LLVM BB %ENDIF259
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR1 %VGPR0 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %SGPR2_SGPR3 %VGPR7 %VGPR2
    Predecessors according to CFG: BB#102 BB#103
	%EXEC<def> = S_OR_B64 %EXEC, %SGPR2_SGPR3
	%SGPR2_SGPR3<def> = V_CMP_NE_I32_e64 %VGPR1<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_AND_SAVEEXEC_B64 %SGPR2_SGPR3, %EXEC<imp-def>, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_XOR_B64 %EXEC, %SGPR2_SGPR3
    Successors according to CFG: BB#105(16) BB#106(16)

BB#105: derived from LLVM BB %IF263
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %SGPR2_SGPR3 %VGPR7 %VGPR2
    Predecessors according to CFG: BB#104
	%VGPR2<def> = V_MAD_F32 %VGPR0<kill>, %VGPR7<kill>, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
    Successors according to CFG: BB#106

BB#106: derived from LLVM BB %ENDIF262
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR3_VGPR4_VGPR5_VGPR6 %SGPR0_SGPR1 %SGPR2_SGPR3 %VGPR2
    Predecessors according to CFG: BB#104 BB#105
	%EXEC<def> = S_OR_B64 %EXEC, %SGPR2_SGPR3
	%VGPR5<def> = V_MOV_B32_e32 0, %EXEC<imp-use>, %VGPR3_VGPR4_VGPR5_VGPR6<imp-use,kill>, %VGPR3_VGPR4_VGPR5_VGPR6<imp-def>
	%VGPR4<def> = V_MOV_B32_e32 %VGPR2<kill>, %EXEC<imp-use>, %VGPR3_VGPR4_VGPR5_VGPR6<imp-def>
	%VGPR13_VGPR14_VGPR15_VGPR16<def> = IMAGE_SAMPLE_L_V4_V4 15, 0, 0, 0, 0, 0, 0, 0, %VGPR3_VGPR4_VGPR5_VGPR6<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
    Successors according to CFG: BB#4

BB#4: derived from LLVM BB %Flow275
    Live Ins: %SGPR0_SGPR1 %VGPR13_VGPR14_VGPR15_VGPR16
    Predecessors according to CFG: BB#0 BB#106
	%EXEC<def> = S_OR_B64 %EXEC, %SGPR0_SGPR1
    Successors according to CFG: BB#2

BB#2: derived from LLVM BB %ENDIF
    Live Ins: %VGPR13_VGPR14_VGPR15_VGPR16
    Predecessors according to CFG: BB#4
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e64 %VGPR15, %VGPR16, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_CVT_PKRTZ_F16_F32_e64 %VGPR13, %VGPR14, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR13_VGPR14_VGPR15_VGPR16<imp-use,kill>
	EXP 15, 0, 1, 1, 1, %VGPR1<kill>, %VGPR0<kill>, %VGPR1, %VGPR0, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_WQM_B64 exec, exec                                                         ; BEFE0A7E
	S_MOV_B32 m0, s7                                                             ; BEFC0307
	V_INTERP_P1_F32 v2, v0, 1, 0, [m0]                                           ; C8080100
	V_INTERP_P2_F32 v2, [v2], v1, 1, 0, [m0]                                     ; C8090101
	V_INTERP_P1_F32 v3, v0, 0, 0, [m0]                                           ; C80C0000
	V_INTERP_P2_F32 v3, [v3], v1, 0, 0, [m0]                                     ; C80D0001
	V_MOV_B32_e32 v5, 0                                                          ; 7E0A0280
	V_MOV_B32_e32 v4, v2                                                         ; 7E080302
	S_LOAD_DWORDX4 s[8:11], s[2:3], 0                                            ; C0840300
	S_LOAD_DWORDX8 s[12:19], s[4:5], 0                                           ; C0C60500
	S_WAITCNT lgkmcnt(0)                                                         ; BF8C007F
	IMAGE_SAMPLE_L v[13:16], 15, 0, 0, 0, 0, 0, 0, 0, v[3:6], s[12:19], s[8:11]  ; F0900F00 00430D03
	V_MOV_B32_e32 v1, 2.990000e-01                                               ; 7E0202FF 3E991687
	S_WAITCNT vmcnt(0)                                                           ; BF8C0770
	V_MUL_F32_e32 v0, v13, v1                                                    ; 1000030D
	V_MOV_B32_e32 v9, 5.870000e-01                                               ; 7E1202FF 3F1645A2
	V_MAD_F32 v0, v14, v9, v0, 0, 0, 0, 0                                        ; D2820000 0402130E
	V_MOV_B32_e32 v11, 1.140000e-01                                              ; 7E1602FF 3DE978D5
	V_MAD_F32 v0, v15, v11, v0, 0, 0, 0, 0                                       ; D2820000 0402170F
	S_LOAD_DWORDX4 s[4:7], s[0:1], 0                                             ; C0820100
	S_WAITCNT lgkmcnt(0)                                                         ; BF8C007F
	S_BUFFER_LOAD_DWORD s2, s[4:7], 1                                            ; C2010501
	S_WAITCNT lgkmcnt(0)                                                         ; BF8C007F
	V_ADD_F32_e32 v18, s2, v2                                                    ; 06240402
	S_BUFFER_LOAD_DWORD s3, s[4:7], 0                                            ; C2018500
	S_WAITCNT lgkmcnt(0)                                                         ; BF8C007F
	V_MAD_F32 v17, s3, 0.000000e+00, v3, 0, 0, 0, 0                              ; D2820011 040D0003
	V_MOV_B32_e32 v19, v5                                                        ; 7E260305
	IMAGE_SAMPLE_L v[21:23], 7, 0, 0, 0, 0, 0, 0, 0, v[17:20], s[12:19], s[8:11] ; F0900700 00431511
	S_WAITCNT vmcnt(0)                                                           ; BF8C0770
	V_MUL_F32_e32 v7, v21, v1                                                    ; 100E0315
	V_MAD_F32 v7, v22, v9, v7, 0, 0, 0, 0                                        ; D2820007 041E1316
	V_MAD_F32 v7, v23, v11, v7, 0, 0, 0, 0                                       ; D2820007 041E1717
	V_CMP_U_F32_e64 s[0:1], v7, v0, 0, 0, 0, 0                                   ; D0100000 02020107
	V_CMP_GE_F32_e64 s[4:5], v7, v0, 0, 0, 0, 0                                  ; D00C0004 02020107
	S_OR_B64 s[0:1], s[4:5], s[0:1]                                              ; 88800004
	V_CNDMASK_B32_e64 v10, v0, v7, s[0:1], 0, 0, 0, 0                            ; D200000A 00020F00
	V_MAD_F32 v22, s2, 0.000000e+00, v2, 0, 0, 0, 0                              ; D2820016 04090002
	V_ADD_F32_e32 v21, s3, v3                                                    ; 062A0603
	V_MOV_B32_e32 v23, v5                                                        ; 7E2E0305
	IMAGE_SAMPLE_L v[25:27], 7, 0, 0, 0, 0, 0, 0, 0, v[21:24], s[12:19], s[8:11] ; F0900700 00431915
	S_WAITCNT vmcnt(0)                                                           ; BF8C0770
	V_MUL_F32_e32 v8, v25, v1                                                    ; 10100319
	V_MAD_F32 v8, v26, v9, v8, 0, 0, 0, 0                                        ; D2820008 0422131A
	V_MAD_F32 v8, v27, v11, v8, 0, 0, 0, 0                                       ; D2820008 0422171B
	V_CMP_U_F32_e64 s[4:5], v8, v10, 0, 0, 0, 0                                  ; D0100004 02021508
	V_CMP_GE_F32_e64 s[6:7], v8, v10, 0, 0, 0, 0                                 ; D00C0006 02021508
	S_OR_B64 s[4:5], s[6:7], s[4:5]                                              ; 88840406
	V_CNDMASK_B32_e64 v25, v10, v8, s[4:5], 0, 0, 0, 0                           ; D2000019 0012110A
	V_SUBREV_F32_e32 v21, s3, v3                                                 ; 0A2A0603
	V_MOV_B32_e32 v23, v5                                                        ; 7E2E0305
	IMAGE_SAMPLE_L v[21:23], 7, 0, 0, 0, 0, 0, 0, 0, v[21:24], s[12:19], s[8:11] ; F0900700 00431515
	S_WAITCNT vmcnt(0)                                                           ; BF8C0770
	V_MUL_F32_e32 v10, v21, v1                                                   ; 10140315
	V_MAD_F32 v10, v22, v9, v10, 0, 0, 0, 0                                      ; D282000A 042A1316
	V_MAD_F32 v10, v23, v11, v10, 0, 0, 0, 0                                     ; D282000A 042A1717
	V_SUBREV_F32_e32 v18, s2, v2                                                 ; 0A240402
	V_MOV_B32_e32 v19, v5                                                        ; 7E260305
	IMAGE_SAMPLE_L v[17:19], 7, 0, 0, 0, 0, 0, 0, 0, v[17:20], s[12:19], s[8:11] ; F0900700 00431111
	S_WAITCNT vmcnt(0)                                                           ; BF8C0770
	V_MUL_F32_e32 v1, v17, v1                                                    ; 10020311
	V_MAD_F32 v1, v18, v9, v1, 0, 0, 0, 0                                        ; D2820001 04061312
	V_MAD_F32 v12, v19, v11, v1, 0, 0, 0, 0                                      ; D282000C 04061713
	V_CMP_U_F32_e64 s[4:5], v12, v10, 0, 0, 0, 0                                 ; D0100004 0202150C
	V_CMP_GE_F32_e64 s[6:7], v12, v10, 0, 0, 0, 0                                ; D00C0006 0202150C
	S_OR_B64 s[4:5], s[6:7], s[4:5]                                              ; 88840406
	V_CNDMASK_B32_e64 v1, v10, v12, s[4:5], 0, 0, 0, 0                           ; D2000001 0012190A
	V_CMP_U_F32_e64 s[6:7], v1, v25, 0, 0, 0, 0                                  ; D0100006 02023301
	V_CMP_GE_F32_e64 s[20:21], v1, v25, 0, 0, 0, 0                               ; D00C0014 02023301
	S_OR_B64 s[6:7], s[20:21], s[6:7]                                            ; 88860614
	V_CNDMASK_B32_e64 v1, v25, v1, s[6:7], 0, 0, 0, 0                            ; D2000001 001A0319
	V_MUL_F32_e32 v9, 1.660000e-01, v1                                           ; 101202FF 3E29FBE7
	V_MOV_B32_e32 v11, 8.330000e-02                                              ; 7E1602FF 3DAA9931
	V_CMP_LE_F32_e64 s[6:7], v9, v11, 0, 0, 0, 0                                 ; D0060006 02021709
	V_CMP_U_F32_e64 s[20:21], v9, v9, 0, 0, 0, 0                                 ; D0100014 02021309
	S_OR_B64 s[6:7], s[6:7], s[20:21]                                            ; 88861406
	V_CNDMASK_B32_e64 v9, v9, v11, s[6:7], 0, 0, 0, 0                            ; D2000009 001A1709
	V_CNDMASK_B32_e64 v11, v7, v0, s[0:1], 0, 0, 0, 0                            ; D200000B 00020107
	V_CMP_U_F32_e64 s[0:1], v8, v11, 0, 0, 0, 0                                  ; D0100000 02021708
	V_CMP_GE_F32_e64 s[6:7], v8, v11, 0, 0, 0, 0                                 ; D00C0006 02021708
	S_OR_B64 s[0:1], s[6:7], s[0:1]                                              ; 88800006
	V_CNDMASK_B32_e64 v11, v8, v11, s[0:1], 0, 0, 0, 0                           ; D200000B 00021708
	V_CNDMASK_B32_e64 v17, v12, v10, s[4:5], 0, 0, 0, 0                          ; D2000011 0012150C
	V_CMP_U_F32_e64 s[0:1], v17, v11, 0, 0, 0, 0                                 ; D0100000 02021711
	V_CMP_GE_F32_e64 s[4:5], v17, v11, 0, 0, 0, 0                                ; D00C0004 02021711
	S_OR_B64 s[0:1], s[4:5], s[0:1]                                              ; 88800004
	V_CNDMASK_B32_e64 v11, v17, v11, s[0:1], 0, 0, 0, 0                          ; D200000B 00021711
	V_SUB_F32_e32 v11, v1, v11                                                   ; 08161701
	V_CMP_LT_F32_e64 s[0:1], v11, v9, 0, 0, 0, 0                                 ; D0020000 0202130B
	V_CNDMASK_B32_e64 v1, 0, -1, s[0:1], 0, 0, 0, 0                              ; D2000001 00018280
	V_CMP_EQ_I32_e64 s[0:1], v1, 0, 0, 0, 0, 0                                   ; D1040000 02010101
	S_AND_SAVEEXEC_B64 s[0:1], s[0:1]                                            ; BE802400
	S_XOR_B64 s[0:1], exec, s[0:1]                                               ; 8980007E
	S_CBRANCH_EXECZ ";.BB0_4"                                                    ; BF880000
	V_MOV_B32_e32 v9, s2                                                         ; 7E120202
	V_MOV_B32_e32 v13, s3                                                        ; 7E1A0203
	V_SUB_F32_e64 v19, v2, v9, 0, 0, 0, 0                                        ; D2080013 02021302
	V_ADD_F32_e64 v18, v13, v3, 0, 0, 0, 0                                       ; D2060012 0202070D
	V_MOV_B32_e32 v20, 0                                                         ; 7E280280
	IMAGE_SAMPLE_L v[14:16], 7, 0, 0, 0, 0, 0, 0, 0, v[18:21], s[12:19], s[8:11] ; F0900700 00430E12
	V_MOV_B32_e32 v1, 2.990000e-01                                               ; 7E0202FF 3E991687
	S_WAITCNT vmcnt(0)                                                           ; BF8C0770
	V_MUL_F32_e32 v17, v14, v1                                                   ; 1022030E
	V_MOV_B32_e32 v22, 5.870000e-01                                              ; 7E2C02FF 3F1645A2
	V_MAD_F32 v17, v15, v22, v17, 0, 0, 0, 0                                     ; D2820011 04462D0F
	V_MOV_B32_e32 v23, 1.140000e-01                                              ; 7E2E02FF 3DE978D5
	V_MAD_F32 v14, v16, v23, v17, 0, 0, 0, 0                                     ; D282000E 04462F10
	V_SUB_F32_e64 v24, v3, v13, 0, 0, 0, 0                                       ; D2080018 02021B03
	V_MOV_B32_e32 v25, v19                                                       ; 7E320313
	V_MOV_B32_e32 v26, v20                                                       ; 7E340314
	IMAGE_SAMPLE_L v[15:17], 7, 0, 0, 0, 0, 0, 0, 0, v[24:27], s[12:19], s[8:11] ; F0900700 00430F18
	S_WAITCNT vmcnt(0)                                                           ; BF8C0770
	V_MUL_F32_e32 v28, v15, v1                                                   ; 1038030F
	V_MAD_F32 v28, v16, v22, v28, 0, 0, 0, 0                                     ; D282001C 04722D10
	V_MAD_F32 v15, v17, v23, v28, 0, 0, 0, 0                                     ; D282000F 04722F11
	V_ADD_F32_e32 v16, v15, v14                                                  ; 06201D0F
	V_MAD_F32 v16, v12, -2.000000e+00, v16, 0, 0, 0, 0                           ; D2820010 0441EB0C
	V_ADD_F32_e64 v16, v16, 0, 1, 0, 0, 0                                        ; D2060110 02010110
	V_ADD_F32_e64 v17, v10, v8, 0, 0, 0, 0                                       ; D2060011 0202110A
	V_MAD_F32 v28, v0, -2.000000e+00, v17, 0, 0, 0, 0                            ; D282001C 0445EB00
	V_ADD_F32_e64 v28, v28, 0, 1, 0, 0, 0                                        ; D206011C 0201011C
	V_ADD_F32_e32 v28, v28, v28                                                  ; 0638391C
	V_ADD_F32_e32 v16, v28, v16                                                  ; 0620211C
	V_ADD_F32_e64 v19, v9, v2, 0, 0, 0, 0                                        ; D2060013 02020509
	IMAGE_SAMPLE_L v[28:30], 7, 0, 0, 0, 0, 0, 0, 0, v[18:21], s[12:19], s[8:11] ; F0900700 00431C12
	S_WAITCNT vmcnt(0)                                                           ; BF8C0770
	V_MUL_F32_e32 v31, v28, v1                                                   ; 103E031C
	V_MAD_F32 v31, v29, v22, v31, 0, 0, 0, 0                                     ; D282001F 047E2D1D
	V_MAD_F32 v28, v30, v23, v31, 0, 0, 0, 0                                     ; D282001C 047E2F1E
	V_MOV_B32_e32 v25, v19                                                       ; 7E320313
	V_MOV_B32_e32 v26, v20                                                       ; 7E340314
	IMAGE_SAMPLE_L v[18:20], 7, 0, 0, 0, 0, 0, 0, 0, v[24:27], s[12:19], s[8:11] ; F0900700 00431218
	S_WAITCNT vmcnt(0)                                                           ; BF8C0770
	V_MUL_F32_e32 v1, v18, v1                                                    ; 10020312
	V_MAD_F32 v1, v19, v22, v1, 0, 0, 0, 0                                       ; D2820001 04062D13
	V_MAD_F32 v1, v20, v23, v1, 0, 0, 0, 0                                       ; D2820001 04062F14
	V_ADD_F32_e32 v18, v1, v28                                                   ; 06243901
	V_MAD_F32 v18, v7, -2.000000e+00, v18, 0, 0, 0, 0                            ; D2820012 0449EB07
	V_ADD_F32_e64 v18, v18, 0, 1, 0, 0, 0                                        ; D2060112 02010112
	V_ADD_F32_e32 v16, v18, v16                                                  ; 06202112
	V_ADD_F32_e32 v18, v14, v28                                                  ; 0624390E
	V_MAD_F32 v14, v8, -2.000000e+00, v18, 0, 0, 0, 0                            ; D282000E 0449EB08
	V_ADD_F32_e64 v14, v14, 0, 1, 0, 0, 0                                        ; D206010E 0201010E
	V_ADD_F32_e64 v19, v12, v7, 0, 0, 0, 0                                       ; D2060013 02020F0C
	V_MAD_F32 v20, v0, -2.000000e+00, v19, 0, 0, 0, 0                            ; D2820014 044DEB00
	V_ADD_F32_e64 v20, v20, 0, 1, 0, 0, 0                                        ; D2060114 02010114
	V_ADD_F32_e32 v20, v20, v20                                                  ; 06282914
	V_ADD_F32_e32 v14, v20, v14                                                  ; 061C1D14
	V_ADD_F32_e32 v20, v15, v1                                                   ; 0628030F
	V_MAD_F32 v1, v10, -2.000000e+00, v20, 0, 0, 0, 0                            ; D2820001 0451EB0A
	V_ADD_F32_e64 v1, v1, 0, 1, 0, 0, 0                                          ; D2060101 02010101
	V_ADD_F32_e32 v1, v1, v14                                                    ; 06021D01
	V_CMP_GE_F32_e64 s[2:3], v1, v16, 0, 0, 0, 0                                 ; D00C0002 02022101
	V_CNDMASK_B32_e64 v1, 0, -1, s[2:3], 0, 0, 0, 0                              ; D2000001 00098280
	V_CMP_NE_I32_e64 s[2:3], v1, -1, 0, 0, 0, 0                                  ; D10A0002 02018301
	V_CNDMASK_B32_e64 v14, v7, v8, s[2:3], 0, 0, 0, 0                            ; D200000E 000A1107
	V_SUBREV_F32_e32 v7, v0, v14                                                 ; 0A0E1D00
	V_ADD_F32_e64 v22, v7, 0, 1, 0, 0, 0                                         ; D2060116 02010107
	V_CNDMASK_B32_e64 v15, v12, v10, s[2:3], 0, 0, 0, 0                          ; D200000F 000A150C
	V_SUBREV_F32_e32 v7, v0, v15                                                 ; 0A0E1F00
	V_ADD_F32_e64 v23, v7, 0, 1, 0, 0, 0                                         ; D2060117 02010107
	V_CMP_GE_F32_e64 s[2:3], v23, v22, 0, 0, 0, 0                                ; D00C0002 02022D17
	V_CNDMASK_B32_e64 v16, 0, -1, s[2:3], 0, 0, 0, 0                             ; D2000010 00098280
	V_CMP_NE_I32_e64 s[4:5], v1, 0, 0, 0, 0, 0                                   ; D10A0004 02010101
	V_CNDMASK_B32_e64 v7, v13, v9, s[4:5], 0, 0, 0, 0                            ; D2000007 0012130D
	S_AND_SAVEEXEC_B64 s[2:3], s[2:3]                                            ; BE822402
	S_XOR_B64 s[2:3], exec, s[2:3]                                               ; 8982027E
	V_ADD_F32_e64 v7, v7, 0, 0, 0, 0, 1                                          ; D2060007 22010107
	S_WAITCNT expcnt(0)                                                          ; BF8C070F
	S_OR_B64 exec, exec, s[2:3]                                                  ; 88FE027E
	V_ADD_F32_e64 v8, v20, v18, 0, 0, 0, 0                                       ; D2060008 02022514
	V_ADD_F32_e64 v10, v19, v17, 0, 0, 0, 0                                      ; D206000A 02022313
	V_ADD_F32_e32 v10, v10, v10                                                  ; 0614150A
	V_ADD_F32_e32 v8, v10, v8                                                    ; 0610110A
	V_MUL_F32_e32 v8, 8.333334e-02, v8                                           ; 101010FF 3DAAAAAB
	V_SUBREV_F32_e32 v8, v0, v8                                                  ; 0A101100
	V_ADD_F32_e64 v8, v8, 0, 1, 0, 0, 0                                          ; D2060108 02010108
	V_RCP_F32_e32 v10, v11                                                       ; 7E14550B
	V_MUL_F32_e32 v8, v8, v10                                                    ; 10101508
	V_ADD_F32_e64 v12, 0, v8, 0, 1, 0, 0                                         ; D206080C 02021080
	V_CMP_NE_I32_e64 s[2:3], v1, -1, 0, 0, 0, 0                                  ; D10A0002 02018301
	V_MOV_B32_e32 v19, v3                                                        ; 7E260303
	S_AND_SAVEEXEC_B64 s[2:3], s[2:3]                                            ; BE822402
	S_XOR_B64 s[2:3], exec, s[2:3]                                               ; 8982027E
	V_MAD_F32 v19, v7, 5.000000e-01, v3, 0, 0, 0, 0                              ; D2820013 040DE107
	S_OR_B64 exec, exec, s[2:3]                                                  ; 88FE027E
	V_CMP_NE_I32_e64 s[2:3], v1, 0, 0, 0, 0, 0                                   ; D10A0002 02010101
	V_MOV_B32_e32 v25, v2                                                        ; 7E320302
	S_AND_SAVEEXEC_B64 s[2:3], s[2:3]                                            ; BE822402
	S_XOR_B64 s[2:3], exec, s[2:3]                                               ; 8982027E
	V_MAD_F32 v25, v7, 5.000000e-01, v2, 0, 0, 0, 0                              ; D2820019 0409E107
	S_OR_B64 exec, exec, s[2:3]                                                  ; 88FE027E
	V_CMP_NE_I32_e64 s[2:3], v1, 0, 0, 0, 0, 0                                   ; D10A0002 02010101
	V_CNDMASK_B32_e64 v20, v9, 0.000000e+00, s[2:3], 0, 0, 0, 0                  ; D2000014 00090109
	V_ADD_F32_e32 v9, v25, v20                                                   ; 06122919
	V_CMP_NE_I32_e64 s[2:3], v1, -1, 0, 0, 0, 0                                  ; D10A0002 02018301
	V_CNDMASK_B32_e64 v21, v13, 0.000000e+00, s[2:3], 0, 0, 0, 0                 ; D2000015 0009010D
	V_ADD_F32_e32 v8, v19, v21                                                   ; 06102B13
	V_MOV_B32_e32 v10, 0                                                         ; 7E140280
	IMAGE_SAMPLE_L v[26:28], 7, 0, 0, 0, 0, 0, 0, 0, v[8:11], s[12:19], s[8:11]  ; F0900700 00431A08
	V_MOV_B32_e32 v29, 2.990000e-01                                              ; 7E3A02FF 3E991687
	S_WAITCNT vmcnt(0)                                                           ; BF8C0770
	V_MUL_F32_e32 v13, v26, v29                                                  ; 101A3B1A
	V_MOV_B32_e32 v30, 5.870000e-01                                              ; 7E3C02FF 3F1645A2
	V_MAD_F32 v13, v27, v30, v13, 0, 0, 0, 0                                     ; D282000D 04363D1B
	V_MOV_B32_e32 v31, 1.140000e-01                                              ; 7E3E02FF 3DE978D5
	V_MAD_F32 v13, v28, v31, v13, 0, 0, 0, 0                                     ; D282000D 04363F1C
	V_ADD_F32_e64 v14, v14, v0, 0, 0, 0, 0                                       ; D206000E 0202010E
	V_ADD_F32_e64 v15, v15, v0, 0, 0, 0, 0                                       ; D206000F 0202010F
	V_CMP_NE_I32_e64 s[2:3], v16, -1, 0, 0, 0, 0                                 ; D10A0002 02018310
	V_CNDMASK_B32_e64 v17, v15, v14, s[2:3], 0, 0, 0, 0                          ; D2000011 000A1D0F
	V_MAD_F32 v18, v17, -5.000000e-01, v13, 0, 0, 0, 0                           ; D2820012 0435E311
	V_ADD_F32_e64 v24, v18, 0, 1, 0, 0, 0                                        ; D2060118 02010112
	V_SUB_F32_e32 v14, v25, v20                                                  ; 081C2919
	V_SUB_F32_e32 v13, v19, v21                                                  ; 081A2B13
	V_MOV_B32_e32 v15, v10                                                       ; 7E1E030A
	IMAGE_SAMPLE_L v[25:27], 7, 0, 0, 0, 0, 0, 0, 0, v[13:16], s[12:19], s[8:11] ; F0900700 0043190D
	S_WAITCNT vmcnt(0)                                                           ; BF8C0770
	V_MUL_F32_e32 v19, v25, v29                                                  ; 10263B19
	V_MAD_F32 v19, v26, v30, v19, 0, 0, 0, 0                                     ; D2820013 044E3D1A
	V_MAD_F32 v19, v27, v31, v19, 0, 0, 0, 0                                     ; D2820013 044E3F1B
	V_MAD_F32 v19, v17, -5.000000e-01, v19, 0, 0, 0, 0                           ; D2820013 044DE311
	V_ADD_F32_e64 v25, v19, 0, 1, 0, 0, 0                                        ; D2060119 02010113
	V_CMP_U_F32_e64 s[2:3], v23, v22, 0, 0, 0, 0                                 ; D0100002 02022D17
	V_CMP_GE_F32_e64 s[4:5], v23, v22, 0, 0, 0, 0                                ; D00C0004 02022D17
	S_OR_B64 s[2:3], s[4:5], s[2:3]                                              ; 88820204
	V_CNDMASK_B32_e64 v22, v22, v23, s[2:3], 0, 0, 0, 0                          ; D2000016 000A2F16
	V_MUL_F32_e32 v22, 2.500000e-01, v22                                         ; 102C2CFF 3E800000
	V_CMP_GE_F32_e64 s[2:3], v25, v22, 0, 0, 0, 0                                ; D00C0002 02022D19
	V_CNDMASK_B32_e64 v23, 0, -1, s[2:3], 0, 0, 0, 0                             ; D2000017 00098280
	V_CMP_NE_I32_e64 s[2:3], v23, -1, 0, 0, 0, 0                                 ; D10A0002 02018317
	S_AND_SAVEEXEC_B64 s[2:3], s[2:3]                                            ; BE822402
	S_XOR_B64 s[2:3], exec, s[2:3]                                               ; 8982027E
	V_MOV_B32_e32 v25, 1.500000e+00                                              ; 7E3202FF 3FC00000
	V_MUL_F32_e32 v26, v20, v25                                                  ; 10343314
	V_SUB_F32_e32 v14, v14, v26                                                  ; 081C350E
	V_MUL_F32_e32 v25, v21, v25                                                  ; 10323315
	V_SUB_F32_e32 v13, v13, v25                                                  ; 081A330D
	S_OR_B64 exec, exec, s[2:3]                                                  ; 88FE027E
	V_CMP_GE_F32_e64 s[2:3], v24, v22, 0, 0, 0, 0                                ; D00C0002 02022D18
	V_CNDMASK_B32_e64 v24, 0, -1, s[2:3], 0, 0, 0, 0                             ; D2000018 00098280
	V_CMP_NE_I32_e64 s[2:3], v24, -1, 0, 0, 0, 0                                 ; D10A0002 02018318
	S_AND_SAVEEXEC_B64 s[2:3], s[2:3]                                            ; BE822402
	S_XOR_B64 s[2:3], exec, s[2:3]                                               ; 8982027E
	V_MOV_B32_e32 v25, 1.500000e+00                                              ; 7E3202FF 3FC00000
	V_MAD_F32 v9, v20, v25, v9, 0, 0, 0, 0                                       ; D2820009 04263314
	V_MAD_F32 v8, v21, v25, v8, 0, 0, 0, 0                                       ; D2820008 04223315
	S_OR_B64 exec, exec, s[2:3]                                                  ; 88FE027E
	V_AND_B32_e64 v25, v23, v24, 0, 0, 0, 0                                      ; D2360019 02023117
	V_CMP_NE_I32_e64 s[2:3], v25, -1, 0, 0, 0, 0                                 ; D10A0002 02018319
	S_AND_SAVEEXEC_B64 s[2:3], s[2:3]                                            ; BE822402
	S_XOR_B64 s[2:3], exec, s[2:3]                                               ; 8982027E
	S_CBRANCH_EXECZ ";.BB0_18"                                                   ; BF880000
	V_CMP_NE_I32_e64 s[4:5], v23, -1, 0, 0, 0, 0                                 ; D10A0004 02018317
	S_AND_SAVEEXEC_B64 s[4:5], s[4:5]                                            ; BE842404
	S_XOR_B64 s[4:5], exec, s[4:5]                                               ; 8984047E
	S_CBRANCH_EXECZ ";.BB0_19"                                                   ; BF880000
	V_MOV_B32_e32 v27, 0                                                         ; 7E360280
	V_MOV_B32_e32 v25, v13                                                       ; 7E32030D
	V_MOV_B32_e32 v26, v14                                                       ; 7E34030E
	IMAGE_SAMPLE_L v[25:27], 7, 0, 0, 0, 0, 0, 0, 0, v[25:28], s[12:19], s[8:11] ; F0900700 00431919
	V_MOV_B32_e32 v19, 2.990000e-01                                              ; 7E2602FF 3E991687
	S_WAITCNT vmcnt(0)                                                           ; BF8C0770
	V_MUL_F32_e32 v19, v25, v19                                                  ; 10262719
	V_MOV_B32_e32 v28, 5.870000e-01                                              ; 7E3802FF 3F1645A2
	V_MAD_F32 v19, v26, v28, v19, 0, 0, 0, 0                                     ; D2820013 044E391A
	V_MOV_B32_e32 v28, 1.140000e-01                                              ; 7E3802FF 3DE978D5
	V_MAD_F32 v19, v27, v28, v19, 0, 0, 0, 0                                     ; D2820013 044E391B
	S_OR_B64 exec, exec, s[4:5]                                                  ; 88FE047E
	V_CMP_NE_I32_e64 s[4:5], v24, -1, 0, 0, 0, 0                                 ; D10A0004 02018318
	S_AND_SAVEEXEC_B64 s[4:5], s[4:5]                                            ; BE842404
	S_XOR_B64 s[4:5], exec, s[4:5]                                               ; 8984047E
	V_MOV_B32_e32 v27, 0                                                         ; 7E360280
	V_MOV_B32_e32 v25, v8                                                        ; 7E320308
	V_MOV_B32_e32 v26, v9                                                        ; 7E340309
	IMAGE_SAMPLE_L v[25:27], 7, 0, 0, 0, 0, 0, 0, 0, v[25:28], s[12:19], s[8:11] ; F0900700 00431919
	V_MOV_B32_e32 v18, 2.990000e-01                                              ; 7E2402FF 3E991687
	S_WAITCNT vmcnt(0)                                                           ; BF8C0770
	V_MUL_F32_e32 v18, v25, v18                                                  ; 10242519
	V_MOV_B32_e32 v28, 5.870000e-01                                              ; 7E3802FF 3F1645A2
	V_MAD_F32 v18, v26, v28, v18, 0, 0, 0, 0                                     ; D2820012 044A391A
	V_MOV_B32_e32 v28, 1.140000e-01                                              ; 7E3802FF 3DE978D5
	V_MAD_F32 v18, v27, v28, v18, 0, 0, 0, 0                                     ; D2820012 044A391B
	S_OR_B64 exec, exec, s[4:5]                                                  ; 88FE047E
	V_CMP_NE_I32_e64 s[4:5], v23, -1, 0, 0, 0, 0                                 ; D10A0004 02018317
	S_AND_SAVEEXEC_B64 s[4:5], s[4:5]                                            ; BE842404
	S_XOR_B64 s[4:5], exec, s[4:5]                                               ; 8984047E
	V_MAD_F32 v19, v17, -5.000000e-01, v19, 0, 0, 0, 0                           ; D2820013 044DE311
	S_OR_B64 exec, exec, s[4:5]                                                  ; 88FE047E
	V_CMP_NE_I32_e64 s[4:5], v24, -1, 0, 0, 0, 0                                 ; D10A0004 02018318
	S_AND_SAVEEXEC_B64 s[4:5], s[4:5]                                            ; BE842404
	S_XOR_B64 s[4:5], exec, s[4:5]                                               ; 8984047E
	V_MAD_F32 v18, v17, -5.000000e-01, v18, 0, 0, 0, 0                           ; D2820012 0449E311
	S_OR_B64 exec, exec, s[4:5]                                                  ; 88FE047E
	V_ADD_F32_e64 v23, v19, 0, 1, 0, 0, 0                                        ; D2060117 02010113
	V_CMP_GE_F32_e64 s[4:5], v23, v22, 0, 0, 0, 0                                ; D00C0004 02022D17
	V_CNDMASK_B32_e64 v23, 0, -1, s[4:5], 0, 0, 0, 0                             ; D2000017 00118280
	V_CMP_NE_I32_e64 s[4:5], v23, -1, 0, 0, 0, 0                                 ; D10A0004 02018317
	V_ADD_F32_e64 v24, v18, 0, 1, 0, 0, 0                                        ; D2060118 02010112
	S_AND_SAVEEXEC_B64 s[4:5], s[4:5]                                            ; BE842404
	S_XOR_B64 s[4:5], exec, s[4:5]                                               ; 8984047E
	V_ADD_F32_e64 v25, v20, v20, 0, 0, 0, 0                                      ; D2060019 02022914
	V_SUB_F32_e32 v14, v14, v25                                                  ; 081C330E
	V_ADD_F32_e64 v25, v21, v21, 0, 0, 0, 0                                      ; D2060019 02022B15
	V_SUB_F32_e32 v13, v13, v25                                                  ; 081A330D
	S_OR_B64 exec, exec, s[4:5]                                                  ; 88FE047E
	V_CMP_GE_F32_e64 s[4:5], v24, v22, 0, 0, 0, 0                                ; D00C0004 02022D18
	V_CNDMASK_B32_e64 v24, 0, -1, s[4:5], 0, 0, 0, 0                             ; D2000018 00118280
	V_CMP_NE_I32_e64 s[4:5], v24, -1, 0, 0, 0, 0                                 ; D10A0004 02018318
	S_AND_SAVEEXEC_B64 s[4:5], s[4:5]                                            ; BE842404
	S_XOR_B64 s[4:5], exec, s[4:5]                                               ; 8984047E
	V_ADD_F32_e64 v25, v20, v20, 0, 0, 0, 0                                      ; D2060019 02022914
	V_ADD_F32_e32 v9, v9, v25                                                    ; 06123309
	V_ADD_F32_e64 v25, v21, v21, 0, 0, 0, 0                                      ; D2060019 02022B15
	V_ADD_F32_e32 v8, v8, v25                                                    ; 06103308
	S_OR_B64 exec, exec, s[4:5]                                                  ; 88FE047E
	V_AND_B32_e64 v25, v23, v24, 0, 0, 0, 0                                      ; D2360019 02023117
	V_CMP_NE_I32_e64 s[4:5], v25, -1, 0, 0, 0, 0                                 ; D10A0004 02018319
	S_AND_SAVEEXEC_B64 s[4:5], s[4:5]                                            ; BE842404
	S_XOR_B64 s[4:5], exec, s[4:5]                                               ; 8984047E
	S_CBRANCH_EXECZ ";.BB0_32"                                                   ; BF880000
	V_CMP_NE_I32_e64 s[6:7], v23, -1, 0, 0, 0, 0                                 ; D10A0006 02018317
	S_AND_SAVEEXEC_B64 s[6:7], s[6:7]                                            ; BE862406
	S_XOR_B64 s[6:7], exec, s[6:7]                                               ; 8986067E
	S_CBRANCH_EXECZ ";.BB0_33"                                                   ; BF880000
	V_MOV_B32_e32 v27, 0                                                         ; 7E360280
	V_MOV_B32_e32 v25, v13                                                       ; 7E32030D
	V_MOV_B32_e32 v26, v14                                                       ; 7E34030E
	IMAGE_SAMPLE_L v[25:27], 7, 0, 0, 0, 0, 0, 0, 0, v[25:28], s[12:19], s[8:11] ; F0900700 00431919
	V_MOV_B32_e32 v19, 2.990000e-01                                              ; 7E2602FF 3E991687
	S_WAITCNT vmcnt(0)                                                           ; BF8C0770
	V_MUL_F32_e32 v19, v25, v19                                                  ; 10262719
	V_MOV_B32_e32 v28, 5.870000e-01                                              ; 7E3802FF 3F1645A2
	V_MAD_F32 v19, v26, v28, v19, 0, 0, 0, 0                                     ; D2820013 044E391A
	V_MOV_B32_e32 v28, 1.140000e-01                                              ; 7E3802FF 3DE978D5
	V_MAD_F32 v19, v27, v28, v19, 0, 0, 0, 0                                     ; D2820013 044E391B
	S_OR_B64 exec, exec, s[6:7]                                                  ; 88FE067E
	V_CMP_NE_I32_e64 s[6:7], v24, -1, 0, 0, 0, 0                                 ; D10A0006 02018318
	S_AND_SAVEEXEC_B64 s[6:7], s[6:7]                                            ; BE862406
	S_XOR_B64 s[6:7], exec, s[6:7]                                               ; 8986067E
	V_MOV_B32_e32 v27, 0                                                         ; 7E360280
	V_MOV_B32_e32 v25, v8                                                        ; 7E320308
	V_MOV_B32_e32 v26, v9                                                        ; 7E340309
	IMAGE_SAMPLE_L v[25:27], 7, 0, 0, 0, 0, 0, 0, 0, v[25:28], s[12:19], s[8:11] ; F0900700 00431919
	V_MOV_B32_e32 v18, 2.990000e-01                                              ; 7E2402FF 3E991687
	S_WAITCNT vmcnt(0)                                                           ; BF8C0770
	V_MUL_F32_e32 v18, v25, v18                                                  ; 10242519
	V_MOV_B32_e32 v28, 5.870000e-01                                              ; 7E3802FF 3F1645A2
	V_MAD_F32 v18, v26, v28, v18, 0, 0, 0, 0                                     ; D2820012 044A391A
	V_MOV_B32_e32 v28, 1.140000e-01                                              ; 7E3802FF 3DE978D5
	V_MAD_F32 v18, v27, v28, v18, 0, 0, 0, 0                                     ; D2820012 044A391B
	S_OR_B64 exec, exec, s[6:7]                                                  ; 88FE067E
	V_CMP_NE_I32_e64 s[6:7], v23, -1, 0, 0, 0, 0                                 ; D10A0006 02018317
	S_AND_SAVEEXEC_B64 s[6:7], s[6:7]                                            ; BE862406
	S_XOR_B64 s[6:7], exec, s[6:7]                                               ; 8986067E
	V_MAD_F32 v19, v17, -5.000000e-01, v19, 0, 0, 0, 0                           ; D2820013 044DE311
	S_OR_B64 exec, exec, s[6:7]                                                  ; 88FE067E
	V_CMP_NE_I32_e64 s[6:7], v24, -1, 0, 0, 0, 0                                 ; D10A0006 02018318
	S_AND_SAVEEXEC_B64 s[6:7], s[6:7]                                            ; BE862406
	S_XOR_B64 s[6:7], exec, s[6:7]                                               ; 8986067E
	V_MAD_F32 v18, v17, -5.000000e-01, v18, 0, 0, 0, 0                           ; D2820012 0449E311
	S_OR_B64 exec, exec, s[6:7]                                                  ; 88FE067E
	V_ADD_F32_e64 v23, v19, 0, 1, 0, 0, 0                                        ; D2060117 02010113
	V_CMP_GE_F32_e64 s[6:7], v23, v22, 0, 0, 0, 0                                ; D00C0006 02022D17
	V_CNDMASK_B32_e64 v23, 0, -1, s[6:7], 0, 0, 0, 0                             ; D2000017 00198280
	V_CMP_NE_I32_e64 s[6:7], v23, -1, 0, 0, 0, 0                                 ; D10A0006 02018317
	V_ADD_F32_e64 v24, v18, 0, 1, 0, 0, 0                                        ; D2060118 02010112
	S_AND_SAVEEXEC_B64 s[6:7], s[6:7]                                            ; BE862406
	S_XOR_B64 s[6:7], exec, s[6:7]                                               ; 8986067E
	V_ADD_F32_e64 v25, v20, v20, 0, 0, 0, 0                                      ; D2060019 02022914
	V_SUB_F32_e32 v14, v14, v25                                                  ; 081C330E
	V_ADD_F32_e64 v25, v21, v21, 0, 0, 0, 0                                      ; D2060019 02022B15
	V_SUB_F32_e32 v13, v13, v25                                                  ; 081A330D
	S_OR_B64 exec, exec, s[6:7]                                                  ; 88FE067E
	V_CMP_GE_F32_e64 s[6:7], v24, v22, 0, 0, 0, 0                                ; D00C0006 02022D18
	V_CNDMASK_B32_e64 v24, 0, -1, s[6:7], 0, 0, 0, 0                             ; D2000018 00198280
	V_CMP_NE_I32_e64 s[6:7], v24, -1, 0, 0, 0, 0                                 ; D10A0006 02018318
	S_AND_SAVEEXEC_B64 s[6:7], s[6:7]                                            ; BE862406
	S_XOR_B64 s[6:7], exec, s[6:7]                                               ; 8986067E
	V_ADD_F32_e64 v25, v20, v20, 0, 0, 0, 0                                      ; D2060019 02022914
	V_ADD_F32_e32 v9, v9, v25                                                    ; 06123309
	V_ADD_F32_e64 v25, v21, v21, 0, 0, 0, 0                                      ; D2060019 02022B15
	V_ADD_F32_e32 v8, v8, v25                                                    ; 06103308
	S_OR_B64 exec, exec, s[6:7]                                                  ; 88FE067E
	V_AND_B32_e64 v25, v23, v24, 0, 0, 0, 0                                      ; D2360019 02023117
	V_CMP_NE_I32_e64 s[6:7], v25, -1, 0, 0, 0, 0                                 ; D10A0006 02018319
	S_AND_SAVEEXEC_B64 s[6:7], s[6:7]                                            ; BE862406
	S_XOR_B64 s[6:7], exec, s[6:7]                                               ; 8986067E
	S_CBRANCH_EXECZ ";.BB0_46"                                                   ; BF880000
	V_CMP_NE_I32_e64 s[20:21], v23, -1, 0, 0, 0, 0                               ; D10A0014 02018317
	S_AND_SAVEEXEC_B64 s[20:21], s[20:21]                                        ; BE942414
	S_XOR_B64 s[20:21], exec, s[20:21]                                           ; 8994147E
	S_CBRANCH_EXECZ ";.BB0_47"                                                   ; BF880000
	V_MOV_B32_e32 v27, 0                                                         ; 7E360280
	V_MOV_B32_e32 v25, v13                                                       ; 7E32030D
	V_MOV_B32_e32 v26, v14                                                       ; 7E34030E
	IMAGE_SAMPLE_L v[25:27], 7, 0, 0, 0, 0, 0, 0, 0, v[25:28], s[12:19], s[8:11] ; F0900700 00431919
	V_MOV_B32_e32 v19, 2.990000e-01                                              ; 7E2602FF 3E991687
	S_WAITCNT vmcnt(0)                                                           ; BF8C0770
	V_MUL_F32_e32 v19, v25, v19                                                  ; 10262719
	V_MOV_B32_e32 v28, 5.870000e-01                                              ; 7E3802FF 3F1645A2
	V_MAD_F32 v19, v26, v28, v19, 0, 0, 0, 0                                     ; D2820013 044E391A
	V_MOV_B32_e32 v28, 1.140000e-01                                              ; 7E3802FF 3DE978D5
	V_MAD_F32 v19, v27, v28, v19, 0, 0, 0, 0                                     ; D2820013 044E391B
	S_OR_B64 exec, exec, s[20:21]                                                ; 88FE147E
	V_CMP_NE_I32_e64 s[20:21], v24, -1, 0, 0, 0, 0                               ; D10A0014 02018318
	S_AND_SAVEEXEC_B64 s[20:21], s[20:21]                                        ; BE942414
	S_XOR_B64 s[20:21], exec, s[20:21]                                           ; 8994147E
	V_MOV_B32_e32 v27, 0                                                         ; 7E360280
	V_MOV_B32_e32 v25, v8                                                        ; 7E320308
	V_MOV_B32_e32 v26, v9                                                        ; 7E340309
	IMAGE_SAMPLE_L v[25:27], 7, 0, 0, 0, 0, 0, 0, 0, v[25:28], s[12:19], s[8:11] ; F0900700 00431919
	V_MOV_B32_e32 v18, 2.990000e-01                                              ; 7E2402FF 3E991687
	S_WAITCNT vmcnt(0)                                                           ; BF8C0770
	V_MUL_F32_e32 v18, v25, v18                                                  ; 10242519
	V_MOV_B32_e32 v28, 5.870000e-01                                              ; 7E3802FF 3F1645A2
	V_MAD_F32 v18, v26, v28, v18, 0, 0, 0, 0                                     ; D2820012 044A391A
	V_MOV_B32_e32 v28, 1.140000e-01                                              ; 7E3802FF 3DE978D5
	V_MAD_F32 v18, v27, v28, v18, 0, 0, 0, 0                                     ; D2820012 044A391B
	S_OR_B64 exec, exec, s[20:21]                                                ; 88FE147E
	V_CMP_NE_I32_e64 s[20:21], v23, -1, 0, 0, 0, 0                               ; D10A0014 02018317
	S_AND_SAVEEXEC_B64 s[20:21], s[20:21]                                        ; BE942414
	S_XOR_B64 s[20:21], exec, s[20:21]                                           ; 8994147E
	V_MAD_F32 v19, v17, -5.000000e-01, v19, 0, 0, 0, 0                           ; D2820013 044DE311
	S_OR_B64 exec, exec, s[20:21]                                                ; 88FE147E
	V_CMP_NE_I32_e64 s[20:21], v24, -1, 0, 0, 0, 0                               ; D10A0014 02018318
	S_AND_SAVEEXEC_B64 s[20:21], s[20:21]                                        ; BE942414
	S_XOR_B64 s[20:21], exec, s[20:21]                                           ; 8994147E
	V_MAD_F32 v18, v17, -5.000000e-01, v18, 0, 0, 0, 0                           ; D2820012 0449E311
	S_OR_B64 exec, exec, s[20:21]                                                ; 88FE147E
	V_ADD_F32_e64 v23, v19, 0, 1, 0, 0, 0                                        ; D2060117 02010113
	V_CMP_GE_F32_e64 s[20:21], v23, v22, 0, 0, 0, 0                              ; D00C0014 02022D17
	V_CNDMASK_B32_e64 v23, 0, -1, s[20:21], 0, 0, 0, 0                           ; D2000017 00518280
	V_CMP_NE_I32_e64 s[20:21], v23, -1, 0, 0, 0, 0                               ; D10A0014 02018317
	V_ADD_F32_e64 v24, v18, 0, 1, 0, 0, 0                                        ; D2060118 02010112
	S_AND_SAVEEXEC_B64 s[20:21], s[20:21]                                        ; BE942414
	S_XOR_B64 s[20:21], exec, s[20:21]                                           ; 8994147E
	V_ADD_F32_e64 v25, v20, v20, 0, 0, 0, 0                                      ; D2060019 02022914
	V_SUB_F32_e32 v14, v14, v25                                                  ; 081C330E
	V_ADD_F32_e64 v25, v21, v21, 0, 0, 0, 0                                      ; D2060019 02022B15
	V_SUB_F32_e32 v13, v13, v25                                                  ; 081A330D
	S_OR_B64 exec, exec, s[20:21]                                                ; 88FE147E
	V_CMP_GE_F32_e64 s[20:21], v24, v22, 0, 0, 0, 0                              ; D00C0014 02022D18
	V_CNDMASK_B32_e64 v24, 0, -1, s[20:21], 0, 0, 0, 0                           ; D2000018 00518280
	V_CMP_NE_I32_e64 s[20:21], v24, -1, 0, 0, 0, 0                               ; D10A0014 02018318
	S_AND_SAVEEXEC_B64 s[20:21], s[20:21]                                        ; BE942414
	S_XOR_B64 s[20:21], exec, s[20:21]                                           ; 8994147E
	V_ADD_F32_e64 v25, v20, v20, 0, 0, 0, 0                                      ; D2060019 02022914
	V_ADD_F32_e32 v9, v9, v25                                                    ; 06123309
	V_ADD_F32_e64 v25, v21, v21, 0, 0, 0, 0                                      ; D2060019 02022B15
	V_ADD_F32_e32 v8, v8, v25                                                    ; 06103308
	S_OR_B64 exec, exec, s[20:21]                                                ; 88FE147E
	V_AND_B32_e64 v25, v23, v24, 0, 0, 0, 0                                      ; D2360019 02023117
	V_CMP_NE_I32_e64 s[20:21], v25, -1, 0, 0, 0, 0                               ; D10A0014 02018319
	S_AND_SAVEEXEC_B64 s[20:21], s[20:21]                                        ; BE942414
	S_XOR_B64 s[20:21], exec, s[20:21]                                           ; 8994147E
	S_CBRANCH_EXECZ ";.BB0_60"                                                   ; BF880000
	V_CMP_NE_I32_e64 s[22:23], v23, -1, 0, 0, 0, 0                               ; D10A0016 02018317
	S_AND_SAVEEXEC_B64 s[22:23], s[22:23]                                        ; BE962416
	S_XOR_B64 s[22:23], exec, s[22:23]                                           ; 8996167E
	S_CBRANCH_EXECZ ";.BB0_61"                                                   ; BF880000
	V_MOV_B32_e32 v27, 0                                                         ; 7E360280
	V_MOV_B32_e32 v25, v13                                                       ; 7E32030D
	V_MOV_B32_e32 v26, v14                                                       ; 7E34030E
	IMAGE_SAMPLE_L v[25:27], 7, 0, 0, 0, 0, 0, 0, 0, v[25:28], s[12:19], s[8:11] ; F0900700 00431919
	V_MOV_B32_e32 v19, 2.990000e-01                                              ; 7E2602FF 3E991687
	S_WAITCNT vmcnt(0)                                                           ; BF8C0770
	V_MUL_F32_e32 v19, v25, v19                                                  ; 10262719
	V_MOV_B32_e32 v28, 5.870000e-01                                              ; 7E3802FF 3F1645A2
	V_MAD_F32 v19, v26, v28, v19, 0, 0, 0, 0                                     ; D2820013 044E391A
	V_MOV_B32_e32 v28, 1.140000e-01                                              ; 7E3802FF 3DE978D5
	V_MAD_F32 v19, v27, v28, v19, 0, 0, 0, 0                                     ; D2820013 044E391B
	S_OR_B64 exec, exec, s[22:23]                                                ; 88FE167E
	V_CMP_NE_I32_e64 s[22:23], v24, -1, 0, 0, 0, 0                               ; D10A0016 02018318
	S_AND_SAVEEXEC_B64 s[22:23], s[22:23]                                        ; BE962416
	S_XOR_B64 s[22:23], exec, s[22:23]                                           ; 8996167E
	V_MOV_B32_e32 v27, 0                                                         ; 7E360280
	V_MOV_B32_e32 v25, v8                                                        ; 7E320308
	V_MOV_B32_e32 v26, v9                                                        ; 7E340309
	IMAGE_SAMPLE_L v[25:27], 7, 0, 0, 0, 0, 0, 0, 0, v[25:28], s[12:19], s[8:11] ; F0900700 00431919
	V_MOV_B32_e32 v18, 2.990000e-01                                              ; 7E2402FF 3E991687
	S_WAITCNT vmcnt(0)                                                           ; BF8C0770
	V_MUL_F32_e32 v18, v25, v18                                                  ; 10242519
	V_MOV_B32_e32 v28, 5.870000e-01                                              ; 7E3802FF 3F1645A2
	V_MAD_F32 v18, v26, v28, v18, 0, 0, 0, 0                                     ; D2820012 044A391A
	V_MOV_B32_e32 v28, 1.140000e-01                                              ; 7E3802FF 3DE978D5
	V_MAD_F32 v18, v27, v28, v18, 0, 0, 0, 0                                     ; D2820012 044A391B
	S_OR_B64 exec, exec, s[22:23]                                                ; 88FE167E
	V_CMP_NE_I32_e64 s[22:23], v23, -1, 0, 0, 0, 0                               ; D10A0016 02018317
	S_AND_SAVEEXEC_B64 s[22:23], s[22:23]                                        ; BE962416
	S_XOR_B64 s[22:23], exec, s[22:23]                                           ; 8996167E
	V_MAD_F32 v19, v17, -5.000000e-01, v19, 0, 0, 0, 0                           ; D2820013 044DE311
	S_OR_B64 exec, exec, s[22:23]                                                ; 88FE167E
	V_CMP_NE_I32_e64 s[22:23], v24, -1, 0, 0, 0, 0                               ; D10A0016 02018318
	S_AND_SAVEEXEC_B64 s[22:23], s[22:23]                                        ; BE962416
	S_XOR_B64 s[22:23], exec, s[22:23]                                           ; 8996167E
	V_MAD_F32 v18, v17, -5.000000e-01, v18, 0, 0, 0, 0                           ; D2820012 0449E311
	S_OR_B64 exec, exec, s[22:23]                                                ; 88FE167E
	V_ADD_F32_e64 v23, v19, 0, 1, 0, 0, 0                                        ; D2060117 02010113
	V_CMP_GE_F32_e64 s[22:23], v23, v22, 0, 0, 0, 0                              ; D00C0016 02022D17
	V_CNDMASK_B32_e64 v23, 0, -1, s[22:23], 0, 0, 0, 0                           ; D2000017 00598280
	V_CMP_NE_I32_e64 s[22:23], v23, -1, 0, 0, 0, 0                               ; D10A0016 02018317
	V_ADD_F32_e64 v24, v18, 0, 1, 0, 0, 0                                        ; D2060118 02010112
	S_AND_SAVEEXEC_B64 s[22:23], s[22:23]                                        ; BE962416
	S_XOR_B64 s[22:23], exec, s[22:23]                                           ; 8996167E
	V_ADD_F32_e64 v25, v20, v20, 0, 0, 0, 0                                      ; D2060019 02022914
	V_SUB_F32_e32 v14, v14, v25                                                  ; 081C330E
	V_ADD_F32_e64 v25, v21, v21, 0, 0, 0, 0                                      ; D2060019 02022B15
	V_SUB_F32_e32 v13, v13, v25                                                  ; 081A330D
	S_OR_B64 exec, exec, s[22:23]                                                ; 88FE167E
	V_CMP_GE_F32_e64 s[22:23], v24, v22, 0, 0, 0, 0                              ; D00C0016 02022D18
	V_CNDMASK_B32_e64 v24, 0, -1, s[22:23], 0, 0, 0, 0                           ; D2000018 00598280
	V_CMP_NE_I32_e64 s[22:23], v24, -1, 0, 0, 0, 0                               ; D10A0016 02018318
	S_AND_SAVEEXEC_B64 s[22:23], s[22:23]                                        ; BE962416
	S_XOR_B64 s[22:23], exec, s[22:23]                                           ; 8996167E
	V_ADD_F32_e64 v25, v20, v20, 0, 0, 0, 0                                      ; D2060019 02022914
	V_ADD_F32_e32 v9, v9, v25                                                    ; 06123309
	V_ADD_F32_e64 v25, v21, v21, 0, 0, 0, 0                                      ; D2060019 02022B15
	V_ADD_F32_e32 v8, v8, v25                                                    ; 06103308
	S_OR_B64 exec, exec, s[22:23]                                                ; 88FE167E
	V_AND_B32_e64 v25, v23, v24, 0, 0, 0, 0                                      ; D2360019 02023117
	V_CMP_NE_I32_e64 s[22:23], v25, -1, 0, 0, 0, 0                               ; D10A0016 02018319
	S_AND_SAVEEXEC_B64 s[22:23], s[22:23]                                        ; BE962416
	S_XOR_B64 s[22:23], exec, s[22:23]                                           ; 8996167E
	S_CBRANCH_EXECZ ";.BB0_74"                                                   ; BF880000
	V_CMP_NE_I32_e64 s[24:25], v23, -1, 0, 0, 0, 0                               ; D10A0018 02018317
	S_AND_SAVEEXEC_B64 s[24:25], s[24:25]                                        ; BE982418
	S_XOR_B64 s[24:25], exec, s[24:25]                                           ; 8998187E
	S_CBRANCH_EXECZ ";.BB0_75"                                                   ; BF880000
	V_MOV_B32_e32 v27, 0                                                         ; 7E360280
	V_MOV_B32_e32 v25, v13                                                       ; 7E32030D
	V_MOV_B32_e32 v26, v14                                                       ; 7E34030E
	IMAGE_SAMPLE_L v[25:27], 7, 0, 0, 0, 0, 0, 0, 0, v[25:28], s[12:19], s[8:11] ; F0900700 00431919
	V_MOV_B32_e32 v19, 2.990000e-01                                              ; 7E2602FF 3E991687
	S_WAITCNT vmcnt(0)                                                           ; BF8C0770
	V_MUL_F32_e32 v19, v25, v19                                                  ; 10262719
	V_MOV_B32_e32 v28, 5.870000e-01                                              ; 7E3802FF 3F1645A2
	V_MAD_F32 v19, v26, v28, v19, 0, 0, 0, 0                                     ; D2820013 044E391A
	V_MOV_B32_e32 v28, 1.140000e-01                                              ; 7E3802FF 3DE978D5
	V_MAD_F32 v19, v27, v28, v19, 0, 0, 0, 0                                     ; D2820013 044E391B
	S_OR_B64 exec, exec, s[24:25]                                                ; 88FE187E
	V_CMP_NE_I32_e64 s[24:25], v24, -1, 0, 0, 0, 0                               ; D10A0018 02018318
	S_AND_SAVEEXEC_B64 s[24:25], s[24:25]                                        ; BE982418
	S_XOR_B64 s[24:25], exec, s[24:25]                                           ; 8998187E
	V_MOV_B32_e32 v27, 0                                                         ; 7E360280
	V_MOV_B32_e32 v25, v8                                                        ; 7E320308
	V_MOV_B32_e32 v26, v9                                                        ; 7E340309
	IMAGE_SAMPLE_L v[25:27], 7, 0, 0, 0, 0, 0, 0, 0, v[25:28], s[12:19], s[8:11] ; F0900700 00431919
	V_MOV_B32_e32 v18, 2.990000e-01                                              ; 7E2402FF 3E991687
	S_WAITCNT vmcnt(0)                                                           ; BF8C0770
	V_MUL_F32_e32 v18, v25, v18                                                  ; 10242519
	V_MOV_B32_e32 v28, 5.870000e-01                                              ; 7E3802FF 3F1645A2
	V_MAD_F32 v18, v26, v28, v18, 0, 0, 0, 0                                     ; D2820012 044A391A
	V_MOV_B32_e32 v28, 1.140000e-01                                              ; 7E3802FF 3DE978D5
	V_MAD_F32 v18, v27, v28, v18, 0, 0, 0, 0                                     ; D2820012 044A391B
	S_OR_B64 exec, exec, s[24:25]                                                ; 88FE187E
	V_CMP_NE_I32_e64 s[24:25], v23, -1, 0, 0, 0, 0                               ; D10A0018 02018317
	S_AND_SAVEEXEC_B64 s[24:25], s[24:25]                                        ; BE982418
	S_XOR_B64 s[24:25], exec, s[24:25]                                           ; 8998187E
	V_MAD_F32 v19, v17, -5.000000e-01, v19, 0, 0, 0, 0                           ; D2820013 044DE311
	S_OR_B64 exec, exec, s[24:25]                                                ; 88FE187E
	V_CMP_NE_I32_e64 s[24:25], v24, -1, 0, 0, 0, 0                               ; D10A0018 02018318
	S_AND_SAVEEXEC_B64 s[24:25], s[24:25]                                        ; BE982418
	S_XOR_B64 s[24:25], exec, s[24:25]                                           ; 8998187E
	V_MAD_F32 v18, v17, -5.000000e-01, v18, 0, 0, 0, 0                           ; D2820012 0449E311
	S_OR_B64 exec, exec, s[24:25]                                                ; 88FE187E
	V_ADD_F32_e64 v23, v19, 0, 1, 0, 0, 0                                        ; D2060117 02010113
	V_CMP_GE_F32_e64 s[24:25], v23, v22, 0, 0, 0, 0                              ; D00C0018 02022D17
	V_CNDMASK_B32_e64 v23, 0, -1, s[24:25], 0, 0, 0, 0                           ; D2000017 00618280
	V_CMP_NE_I32_e64 s[24:25], v23, -1, 0, 0, 0, 0                               ; D10A0018 02018317
	V_ADD_F32_e64 v24, v18, 0, 1, 0, 0, 0                                        ; D2060118 02010112
	S_AND_SAVEEXEC_B64 s[24:25], s[24:25]                                        ; BE982418
	S_XOR_B64 s[24:25], exec, s[24:25]                                           ; 8998187E
	V_MUL_F32_e64 v25, v20, 4.000000e+00, 0, 0, 0, 0                             ; D2100019 0201ED14
	V_SUB_F32_e32 v14, v14, v25                                                  ; 081C330E
	V_MUL_F32_e64 v25, v21, 4.000000e+00, 0, 0, 0, 0                             ; D2100019 0201ED15
	V_SUB_F32_e32 v13, v13, v25                                                  ; 081A330D
	S_OR_B64 exec, exec, s[24:25]                                                ; 88FE187E
	V_CMP_GE_F32_e64 s[24:25], v24, v22, 0, 0, 0, 0                              ; D00C0018 02022D18
	V_CNDMASK_B32_e64 v24, 0, -1, s[24:25], 0, 0, 0, 0                           ; D2000018 00618280
	V_CMP_NE_I32_e64 s[24:25], v24, -1, 0, 0, 0, 0                               ; D10A0018 02018318
	S_AND_SAVEEXEC_B64 s[24:25], s[24:25]                                        ; BE982418
	S_XOR_B64 s[24:25], exec, s[24:25]                                           ; 8998187E
	V_MAD_F32 v9, v20, 4.000000e+00, v9, 0, 0, 0, 0                              ; D2820009 0425ED14
	V_MAD_F32 v8, v21, 4.000000e+00, v8, 0, 0, 0, 0                              ; D2820008 0421ED15
	S_OR_B64 exec, exec, s[24:25]                                                ; 88FE187E
	V_AND_B32_e64 v25, v23, v24, 0, 0, 0, 0                                      ; D2360019 02023117
	V_CMP_NE_I32_e64 s[24:25], v25, -1, 0, 0, 0, 0                               ; D10A0018 02018319
	S_AND_SAVEEXEC_B64 s[24:25], s[24:25]                                        ; BE982418
	S_XOR_B64 s[24:25], exec, s[24:25]                                           ; 8998187E
	S_CBRANCH_EXECZ ";.BB0_88"                                                   ; BF880000
	V_CMP_NE_I32_e64 s[26:27], v23, -1, 0, 0, 0, 0                               ; D10A001A 02018317
	S_AND_SAVEEXEC_B64 s[26:27], s[26:27]                                        ; BE9A241A
	S_XOR_B64 s[26:27], exec, s[26:27]                                           ; 899A1A7E
	S_CBRANCH_EXECZ ";.BB0_89"                                                   ; BF880000
	V_MOV_B32_e32 v27, 0                                                         ; 7E360280
	V_MOV_B32_e32 v25, v13                                                       ; 7E32030D
	V_MOV_B32_e32 v26, v14                                                       ; 7E34030E
	IMAGE_SAMPLE_L v[25:27], 7, 0, 0, 0, 0, 0, 0, 0, v[25:28], s[12:19], s[8:11] ; F0900700 00431919
	V_MOV_B32_e32 v19, 2.990000e-01                                              ; 7E2602FF 3E991687
	S_WAITCNT vmcnt(0)                                                           ; BF8C0770
	V_MUL_F32_e32 v19, v25, v19                                                  ; 10262719
	V_MOV_B32_e32 v28, 5.870000e-01                                              ; 7E3802FF 3F1645A2
	V_MAD_F32 v19, v26, v28, v19, 0, 0, 0, 0                                     ; D2820013 044E391A
	V_MOV_B32_e32 v28, 1.140000e-01                                              ; 7E3802FF 3DE978D5
	V_MAD_F32 v19, v27, v28, v19, 0, 0, 0, 0                                     ; D2820013 044E391B
	S_OR_B64 exec, exec, s[26:27]                                                ; 88FE1A7E
	V_CMP_NE_I32_e64 s[26:27], v24, -1, 0, 0, 0, 0                               ; D10A001A 02018318
	S_AND_SAVEEXEC_B64 s[26:27], s[26:27]                                        ; BE9A241A
	S_XOR_B64 s[26:27], exec, s[26:27]                                           ; 899A1A7E
	V_MOV_B32_e32 v27, 0                                                         ; 7E360280
	V_MOV_B32_e32 v25, v8                                                        ; 7E320308
	V_MOV_B32_e32 v26, v9                                                        ; 7E340309
	IMAGE_SAMPLE_L v[25:27], 7, 0, 0, 0, 0, 0, 0, 0, v[25:28], s[12:19], s[8:11] ; F0900700 00431919
	V_MOV_B32_e32 v18, 2.990000e-01                                              ; 7E2402FF 3E991687
	S_WAITCNT vmcnt(0)                                                           ; BF8C0770
	V_MUL_F32_e32 v18, v25, v18                                                  ; 10242519
	V_MOV_B32_e32 v28, 5.870000e-01                                              ; 7E3802FF 3F1645A2
	V_MAD_F32 v18, v26, v28, v18, 0, 0, 0, 0                                     ; D2820012 044A391A
	V_MOV_B32_e32 v28, 1.140000e-01                                              ; 7E3802FF 3DE978D5
	V_MAD_F32 v18, v27, v28, v18, 0, 0, 0, 0                                     ; D2820012 044A391B
	S_OR_B64 exec, exec, s[26:27]                                                ; 88FE1A7E
	V_CMP_NE_I32_e64 s[26:27], v23, -1, 0, 0, 0, 0                               ; D10A001A 02018317
	S_AND_SAVEEXEC_B64 s[26:27], s[26:27]                                        ; BE9A241A
	S_XOR_B64 s[26:27], exec, s[26:27]                                           ; 899A1A7E
	V_MAD_F32 v19, v17, -5.000000e-01, v19, 0, 0, 0, 0                           ; D2820013 044DE311
	S_OR_B64 exec, exec, s[26:27]                                                ; 88FE1A7E
	V_CMP_NE_I32_e64 s[26:27], v24, -1, 0, 0, 0, 0                               ; D10A001A 02018318
	S_AND_SAVEEXEC_B64 s[26:27], s[26:27]                                        ; BE9A241A
	S_XOR_B64 s[26:27], exec, s[26:27]                                           ; 899A1A7E
	V_MAD_F32 v18, v17, -5.000000e-01, v18, 0, 0, 0, 0                           ; D2820012 0449E311
	S_OR_B64 exec, exec, s[26:27]                                                ; 88FE1A7E
	V_ADD_F32_e64 v23, v19, 0, 1, 0, 0, 0                                        ; D2060117 02010113
	V_CMP_GE_F32_e64 s[26:27], v23, v22, 0, 0, 0, 0                              ; D00C001A 02022D17
	V_CNDMASK_B32_e64 v23, 0, -1, s[26:27], 0, 0, 0, 0                           ; D2000017 00698280
	V_CMP_NE_I32_e64 s[26:27], v23, -1, 0, 0, 0, 0                               ; D10A001A 02018317
	V_ADD_F32_e64 v23, v18, 0, 1, 0, 0, 0                                        ; D2060117 02010112
	S_AND_SAVEEXEC_B64 s[26:27], s[26:27]                                        ; BE9A241A
	S_XOR_B64 s[26:27], exec, s[26:27]                                           ; 899A1A7E
	V_MOV_B32_e32 v24, 8.000000e+00                                              ; 7E3002FF 41000000
	V_MUL_F32_e32 v25, v20, v24                                                  ; 10323114
	V_SUB_F32_e32 v14, v14, v25                                                  ; 081C330E
	V_MUL_F32_e32 v24, v21, v24                                                  ; 10303115
	V_SUB_F32_e32 v13, v13, v24                                                  ; 081A310D
	S_OR_B64 exec, exec, s[26:27]                                                ; 88FE1A7E
	V_CMP_GE_F32_e64 s[26:27], v23, v22, 0, 0, 0, 0                              ; D00C001A 02022D17
	V_CNDMASK_B32_e64 v22, 0, -1, s[26:27], 0, 0, 0, 0                           ; D2000016 00698280
	V_CMP_NE_I32_e64 s[26:27], v22, -1, 0, 0, 0, 0                               ; D10A001A 02018316
	S_AND_SAVEEXEC_B64 s[26:27], s[26:27]                                        ; BE9A241A
	S_XOR_B64 s[26:27], exec, s[26:27]                                           ; 899A1A7E
	V_MOV_B32_e32 v22, 8.000000e+00                                              ; 7E2C02FF 41000000
	V_MAD_F32 v9, v20, v22, v9, 0, 0, 0, 0                                       ; D2820009 04262D14
	V_MAD_F32 v8, v21, v22, v8, 0, 0, 0, 0                                       ; D2820008 04222D15
	S_OR_B64 exec, exec, s[26:27]                                                ; 88FE1A7E
	S_OR_B64 exec, exec, s[24:25]                                                ; 88FE187E
	S_OR_B64 exec, exec, s[22:23]                                                ; 88FE167E
	S_OR_B64 exec, exec, s[20:21]                                                ; 88FE147E
	S_OR_B64 exec, exec, s[6:7]                                                  ; 88FE067E
	S_OR_B64 exec, exec, s[4:5]                                                  ; 88FE047E
	S_OR_B64 exec, exec, s[2:3]                                                  ; 88FE027E
	V_MOV_B32_e32 v20, 3.000000e+00                                              ; 7E2802FF 40400000
	V_MAD_F32 v20, v12, -2.000000e+00, v20, 0, 0, 0, 0                           ; D2820014 0451EB0C
	V_MUL_F32_e64 v12, v12, v12, 0, 0, 0, 0                                      ; D210000C 0202190C
	V_MUL_F32_e32 v12, v20, v12                                                  ; 10181914
	V_MAD_F32 v0, v17, -5.000000e-01, v0, 0, 0, 0, 0                             ; D2820000 0401E311
	V_CMP_LT_F32_e64 s[2:3], v0, 0.000000e+00, 0, 0, 0, 0                        ; D0020002 02010100
	V_CNDMASK_B32_e64 v17, 0, -1, s[2:3], 0, 0, 0, 0                             ; D2000011 00098280
	V_SUB_F32_e64 v0, v3, v13, 0, 0, 0, 0                                        ; D2080000 02021B03
	V_CMP_NE_I32_e64 s[2:3], v1, -1, 0, 0, 0, 0                                  ; D10A0002 02018301
	S_AND_SAVEEXEC_B64 s[2:3], s[2:3]                                            ; BE822402
	S_XOR_B64 s[2:3], exec, s[2:3]                                               ; 8982027E
	V_SUB_F32_e64 v0, v2, v14, 0, 0, 0, 0                                        ; D2080000 02021D02
	S_OR_B64 exec, exec, s[2:3]                                                  ; 88FE027E
	V_SUB_F32_e64 v13, v8, v3, 0, 0, 0, 0                                        ; D208000D 02020708
	V_CMP_NE_I32_e64 s[2:3], v1, -1, 0, 0, 0, 0                                  ; D10A0002 02018301
	S_AND_SAVEEXEC_B64 s[2:3], s[2:3]                                            ; BE822402
	S_XOR_B64 s[2:3], exec, s[2:3]                                               ; 8982027E
	V_SUB_F32_e64 v13, v9, v2, 0, 0, 0, 0                                        ; D208000D 02020509
	S_OR_B64 exec, exec, s[2:3]                                                  ; 88FE027E
	V_CMP_LT_F32_e64 s[2:3], v0, v13, 0, 0, 0, 0                                 ; D0020002 02021B00
	V_CMP_LT_F32_e64 s[4:5], v19, 0.000000e+00, 0, 0, 0, 0                       ; D0020004 02010113
	V_CNDMASK_B32_e64 v8, 0, -1, s[4:5], 0, 0, 0, 0                              ; D2000008 00118280
	V_CMP_NE_I32_e64 s[4:5], v8, v17, 0, 0, 0, 0                                 ; D10A0004 02022308
	V_CNDMASK_B32_e64 v8, 0, -1, s[4:5], 0, 0, 0, 0                              ; D2000008 00118280
	V_CMP_LT_F32_e64 s[4:5], v18, 0.000000e+00, 0, 0, 0, 0                       ; D0020004 02010112
	V_CNDMASK_B32_e64 v9, 0, -1, s[4:5], 0, 0, 0, 0                              ; D2000009 00118280
	V_CMP_NE_I32_e64 s[4:5], v9, v17, 0, 0, 0, 0                                 ; D10A0004 02022309
	V_CNDMASK_B32_e64 v9, 0, -1, s[4:5], 0, 0, 0, 0                              ; D2000009 00118280
	V_CNDMASK_B32_e64 v8, v9, v8, s[2:3], 0, 0, 0, 0                             ; D2000008 000A1109
	V_CMP_NE_I32_e64 s[2:3], v8, 0, 0, 0, 0, 0                                   ; D10A0002 02010108
	V_CMP_U_F32_e64 s[4:5], v0, v13, 0, 0, 0, 0                                  ; D0100004 02021B00
	V_CMP_GE_F32_e64 s[6:7], v0, v13, 0, 0, 0, 0                                 ; D00C0006 02021B00
	S_OR_B64 s[4:5], s[6:7], s[4:5]                                              ; 88840406
	V_CNDMASK_B32_e64 v8, v0, v13, s[4:5], 0, 0, 0, 0                            ; D2000008 00121B00
	V_ADD_F32_e64 v0, v13, v0, 0, 0, 0, 0                                        ; D2060000 0202010D
	V_RCP_F32_e32 v0, v0                                                         ; 7E005500
	V_MUL_F32_e32 v0, -1.000000e+00, v0                                          ; 100000F3
	V_MAD_F32 v0, v8, v0, 5.000000e-01, 0, 0, 0, 0                               ; D2820000 03C20108
	V_CNDMASK_B32_e64 v0, 0.000000e+00, v0, s[2:3], 0, 0, 0, 0                   ; D2000000 000A0080
	V_MUL_F32_e64 v8, v12, v12, 0, 0, 0, 0                                       ; D2100008 0202190C
	V_MUL_F32_e32 v8, 2.500000e-01, v8                                           ; 101010FF 3E800000
	V_CMP_U_F32_e64 s[2:3], v0, v8, 0, 0, 0, 0                                   ; D0100002 02021100
	V_CMP_GE_F32_e64 s[4:5], v0, v8, 0, 0, 0, 0                                  ; D00C0004 02021100
	S_OR_B64 s[2:3], s[4:5], s[2:3]                                              ; 88820204
	V_CNDMASK_B32_e64 v0, v8, v0, s[2:3], 0, 0, 0, 0                             ; D2000000 000A0108
	V_CMP_NE_I32_e64 s[2:3], v1, -1, 0, 0, 0, 0                                  ; D10A0002 02018301
	S_AND_SAVEEXEC_B64 s[2:3], s[2:3]                                            ; BE822402
	S_XOR_B64 s[2:3], exec, s[2:3]                                               ; 8982027E
	V_MAD_F32 v3, v0, v7, v3, 0, 0, 0, 0                                         ; D2820003 040E0F00
	S_OR_B64 exec, exec, s[2:3]                                                  ; 88FE027E
	V_CMP_NE_I32_e64 s[2:3], v1, 0, 0, 0, 0, 0                                   ; D10A0002 02010101
	S_AND_SAVEEXEC_B64 s[2:3], s[2:3]                                            ; BE822402
	S_XOR_B64 s[2:3], exec, s[2:3]                                               ; 8982027E
	V_MAD_F32 v2, v0, v7, v2, 0, 0, 0, 0                                         ; D2820002 040A0F00
	S_OR_B64 exec, exec, s[2:3]                                                  ; 88FE027E
	V_MOV_B32_e32 v5, 0                                                          ; 7E0A0280
	V_MOV_B32_e32 v4, v2                                                         ; 7E080302
	IMAGE_SAMPLE_L v[13:16], 15, 0, 0, 0, 0, 0, 0, 0, v[3:6], s[12:19], s[8:11]  ; F0900F00 00430D03
	S_WAITCNT vmcnt(0)                                                           ; BF8C0770
	S_OR_B64 exec, exec, s[0:1]                                                  ; 88FE007E
	V_CVT_PKRTZ_F16_F32_e64 v0, v15, v16, 0, 0, 0, 0                             ; D25E0000 0202210F
	V_CVT_PKRTZ_F16_F32_e64 v1, v13, v14, 0, 0, 0, 0                             ; D25E0001 02021D0D
	EXP 15, 0, 1, 1, 1, v1, v0, v1, v0                                           ; F8001C0F 00010001
	S_ENDPGM                                                                     ; BF810000

VERT
DCL IN[0]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[19]
DCL CONST[0..1]
DCL TEMP[0..2], LOCAL
IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
  0: MOV TEMP[0].zw, IMM[0].yyxy
  1: MOV TEMP[0].xy, IN[0].xyxx
  2: MAD TEMP[1].xy, IN[0].zwww, CONST[0].xyyy, CONST[0].zwww
  3: MAD TEMP[2].xy, IN[0].zwww, CONST[1].xyyy, CONST[1].zwww
  4: MOV TEMP[1].zw, TEMP[2].yyxy
  5: MOV OUT[1], TEMP[1]
  6: MOV OUT[0], TEMP[0]
  7: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0)
  %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4)
  %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8)
  %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12)
  %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16)
  %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20)
  %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24)
  %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28)
  %20 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %21, i32 0, i32 %6)
  %23 = extractelement <4 x float> %22, i32 0
  %24 = extractelement <4 x float> %22, i32 1
  %25 = extractelement <4 x float> %22, i32 2
  %26 = extractelement <4 x float> %22, i32 3
  %27 = fmul float %25, %12
  %28 = fadd float %27, %14
  %29 = fmul float %26, %13
  %30 = fadd float %29, %15
  %31 = fmul float %25, %16
  %32 = fadd float %31, %18
  %33 = fmul float %26, %17
  %34 = fadd float %33, %19
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %28, float %30, float %32, float %34)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %23, float %24, float 0.000000e+00, float 1.000000e+00)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg6

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%23](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%11](align=8)(tbaa=!"const")
	S_WAITCNT 112
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 7; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR4<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 5; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR3, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 6; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 4; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR2, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 3; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR3, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 0; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR8<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR2, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 32, 0, 0, 0, %VGPR7<kill>, %VGPR6<kill>, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>
	S_WAITCNT 1807
	%VGPR4<def> = V_MOV_B32_e32 1.000000e+00, %EXEC<imp-use>
	%VGPR5<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR1, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_LOAD_DWORDX4 s[4:7], s[6:7], 0               ; C0820700
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	BUFFER_LOAD_FORMAT_XYZW v[0:3], s[4:7][v0] + 0 ; E00C2000 80010000
	S_LOAD_DWORDX4 s[0:3], s[0:1], 0               ; C0800100
	S_WAITCNT vmcnt(0) lgkmcnt(0)                  ; BF8C0070
	S_BUFFER_LOAD_DWORD s4, s[0:3], 7              ; C2020107
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v4, s4                           ; 7E080204
	S_BUFFER_LOAD_DWORD s4, s[0:3], 5              ; C2020105
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v5, s4                           ; 7E0A0204
	V_MAD_F32 v4, v3, v5, v4, 0, 0, 0, 0           ; D2820004 04120B03
	S_BUFFER_LOAD_DWORD s4, s[0:3], 6              ; C2020106
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v5, s4                           ; 7E0A0204
	S_BUFFER_LOAD_DWORD s4, s[0:3], 4              ; C2020104
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v6, s4                           ; 7E0C0204
	V_MAD_F32 v5, v2, v6, v5, 0, 0, 0, 0           ; D2820005 04160D02
	S_BUFFER_LOAD_DWORD s4, s[0:3], 3              ; C2020103
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v6, s4                           ; 7E0C0204
	S_BUFFER_LOAD_DWORD s4, s[0:3], 1              ; C2020101
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v7, s4                           ; 7E0E0204
	V_MAD_F32 v6, v3, v7, v6, 0, 0, 0, 0           ; D2820006 041A0F03
	S_BUFFER_LOAD_DWORD s4, s[0:3], 2              ; C2020102
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v7, s4                           ; 7E0E0204
	S_BUFFER_LOAD_DWORD s0, s[0:3], 0              ; C2000100
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v8, s0                           ; 7E100200
	V_MAD_F32 v7, v2, v8, v7, 0, 0, 0, 0           ; D2820007 041E1102
	EXP 15, 32, 0, 0, 0, v7, v6, v5, v4            ; F800020F 04050607
	S_WAITCNT expcnt(0)                            ; BF8C070F
	V_MOV_B32_e32 v4, 1.000000e+00                 ; 7E0802F2
	V_MOV_B32_e32 v5, 0.000000e+00                 ; 7E0A0280
	EXP 15, 12, 0, 1, 0, v0, v1, v5, v4            ; F80008CF 04050100
	S_ENDPGM                                       ; BF810000

FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL SAMP[1]
DCL CONST[0..223]
DCL TEMP[0..1], LOCAL
IMM[0] FLT32 {    0.0000,     1.0000, 65504.0000,     0.0000}
  0: ADD TEMP[0].xy, IN[0].xyyy, CONST[0].xyyy
  1: MOV TEMP[0].xy, TEMP[0].xyyy
  2: TEX TEMP[0], TEMP[0], SAMP[0], 2D
  3: MOV TEMP[0].xyz, TEMP[0]
  4: MOV TEMP[1].xy, IN[0].zwww
  5: TEX TEMP[1].x, TEMP[1], SAMP[1], 2D
  6: FSGE TEMP[1].x, TEMP[1].xxxx, IMM[0].xxxx
  7: UIF TEMP[1].xxxx :0
  8:   MOV TEMP[1].x, IMM[0].yyyy
  9: ELSE :0
 10:   MOV TEMP[1].x, IMM[0].xxxx
 11: ENDIF
 12: MOV TEMP[0].w, TEMP[1].xxxx
 13: MIN TEMP[0], TEMP[0], IMM[0].zzzz
 14: MOV OUT[0], TEMP[0]
 15: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %21 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
  %22 = load <16 x i8> addrspace(2)* %21, !tbaa !0
  %23 = call float @llvm.SI.load.const(<16 x i8> %22, i32 0)
  %24 = call float @llvm.SI.load.const(<16 x i8> %22, i32 4)
  %25 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0
  %26 = load <32 x i8> addrspace(2)* %25, !tbaa !0
  %27 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0
  %28 = load <16 x i8> addrspace(2)* %27, !tbaa !0
  %29 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 1
  %30 = load <32 x i8> addrspace(2)* %29, !tbaa !0
  %31 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 1
  %32 = load <16 x i8> addrspace(2)* %31, !tbaa !0
  %33 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %4, <2 x i32> %6)
  %34 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %4, <2 x i32> %6)
  %35 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %4, <2 x i32> %6)
  %36 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %4, <2 x i32> %6)
  %37 = fadd float %33, %23
  %38 = fadd float %34, %24
  %39 = bitcast float %37 to i32
  %40 = bitcast float %38 to i32
  %41 = insertelement <2 x i32> undef, i32 %39, i32 0
  %42 = insertelement <2 x i32> %41, i32 %40, i32 1
  %43 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %42, <32 x i8> %26, <16 x i8> %28, i32 2)
  %44 = extractelement <4 x float> %43, i32 0
  %45 = extractelement <4 x float> %43, i32 1
  %46 = extractelement <4 x float> %43, i32 2
  %47 = bitcast float %35 to i32
  %48 = bitcast float %36 to i32
  %49 = insertelement <2 x i32> undef, i32 %47, i32 0
  %50 = insertelement <2 x i32> %49, i32 %48, i32 1
  %51 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %50, <32 x i8> %30, <16 x i8> %32, i32 2)
  %52 = extractelement <4 x float> %51, i32 0
  %53 = fcmp oge float %52, 0.000000e+00
  %54 = sext i1 %53 to i32
  %55 = bitcast i32 %54 to float
  %56 = bitcast float %55 to i32
  %57 = icmp ne i32 %56, 0
  %. = select i1 %57, float 1.000000e+00, float 0.000000e+00
  %58 = fcmp uge float %44, 6.550400e+04
  %59 = select i1 %58, float 6.550400e+04, float %44
  %60 = fcmp uge float %45, 6.550400e+04
  %61 = select i1 %60, float 6.550400e+04, float %45
  %62 = fcmp uge float %46, 6.550400e+04
  %63 = select i1 %62, float 6.550400e+04, float %46
  %64 = fcmp uge float %., 6.550400e+04
  %65 = select i1 %64, float 6.550400e+04, float %.
  %66 = call i32 @llvm.SI.packf16(float %59, float %61)
  %67 = bitcast i32 %66 to float
  %68 = call i32 @llvm.SI.packf16(float %63, float %65)
  %69 = bitcast i32 %68 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %67, float %69, float %67, float %69)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR7 in %vreg4, %VGPR0 in %vreg5, %VGPR1 in %vreg6

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR7 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR7
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 3, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-def>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 3, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 2, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<tied0>, %VGPR1, 2, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 4; mem:LD16[%36](align=8)(tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 8; mem:LD32[%33](tbaa=!"const")
	S_WAITCNT 127
	%VGPR2<def> = IMAGE_SAMPLE_V1_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%SGPR8_SGPR9<def> = V_CMP_GE_F32_e64 %VGPR2<kill>, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR2<def> = V_CNDMASK_B32_e64 0.000000e+00, 1.000000e+00, %SGPR8_SGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_MOV_B32_e32 6.550400e+04, %EXEC<imp-use>
	%SGPR8_SGPR9<def> = V_CMP_GE_F32_e64 %VGPR2, %VGPR3, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR10_SGPR11<def> = V_CMP_U_F32_e64 %VGPR2, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8_SGPR9<def> = S_OR_B64 %SGPR8_SGPR9<kill>, %SGPR10_SGPR11<kill>
	%VGPR2<def> = V_CNDMASK_B32_e64 %VGPR2<kill>, %VGPR3, %SGPR8_SGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR4<def,tied1> = V_INTERP_P2_F32 %VGPR4<kill,tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%22](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 1; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_ADD_F32_e32 %SGPR0<kill>, %VGPR4<kill>, %EXEC<imp-use>, %VGPR4_VGPR5<imp-def>
	%VGPR6<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR6<def,tied1> = V_INTERP_P2_F32 %VGPR6<kill,tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11<kill>, 0; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR4<def> = V_ADD_F32_e32 %SGPR0<kill>, %VGPR6<kill>, %EXEC<imp-use>, %VGPR4_VGPR5<imp-use,kill>, %VGPR4_VGPR5<imp-def>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%30](align=8)(tbaa=!"const")
	%SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%27](tbaa=!"const")
	S_WAITCNT 127
	%VGPR4_VGPR5_VGPR6<def> = IMAGE_SAMPLE_V3_V2 7, 0, 0, 0, 0, 0, 0, 0, %VGPR4_VGPR5<kill>, %SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<kill>, %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%SGPR0_SGPR1<def> = V_CMP_U_F32_e64 %VGPR6, %VGPR6, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR6, %VGPR3, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_OR_B64 %SGPR2_SGPR3<kill>, %SGPR0_SGPR1<kill>
	%VGPR0<def> = V_CNDMASK_B32_e64 %VGPR6, %VGPR3, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = V_CMP_U_F32_e64 %VGPR5, %VGPR5, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR5, %VGPR3, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_OR_B64 %SGPR2_SGPR3<kill>, %SGPR0_SGPR1<kill>
	%VGPR1<def> = V_CNDMASK_B32_e64 %VGPR5, %VGPR3, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = V_CMP_U_F32_e64 %VGPR4, %VGPR4, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR4, %VGPR3, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_OR_B64 %SGPR2_SGPR3<kill>, %SGPR0_SGPR1<kill>
	%VGPR2<def> = V_CNDMASK_B32_e64 %VGPR4, %VGPR3<kill>, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR4_VGPR5_VGPR6<imp-use,kill>
	%VGPR1<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR2<kill>, %VGPR1<kill>, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR1<kill>, %VGPR0<kill>, %VGPR1, %VGPR0, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_WQM_B64 exec, exec                                                 ; BEFE0A7E
	S_MOV_B32 m0, s7                                                     ; BEFC0307
	V_INTERP_P1_F32 v3, v0, 3, 0, [m0]                                   ; C80C0300
	V_INTERP_P2_F32 v3, [v3], v1, 3, 0, [m0]                             ; C80D0301
	V_INTERP_P1_F32 v2, v0, 2, 0, [m0]                                   ; C8080200
	V_INTERP_P2_F32 v2, [v2], v1, 2, 0, [m0]                             ; C8090201
	S_LOAD_DWORDX4 s[8:11], s[2:3], 4                                    ; C0840304
	S_LOAD_DWORDX8 s[12:19], s[4:5], 8                                   ; C0C60508
	S_WAITCNT lgkmcnt(0)                                                 ; BF8C007F
	IMAGE_SAMPLE v2, 1, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[12:19], s[8:11]   ; F0800100 00430202
	S_WAITCNT vmcnt(0)                                                   ; BF8C0770
	V_CMP_GE_F32_e64 s[8:9], v2, 0.000000e+00, 0, 0, 0, 0                ; D00C0008 02010102
	V_CNDMASK_B32_e64 v2, 0.000000e+00, 1.000000e+00, s[8:9], 0, 0, 0, 0 ; D2000002 0021E480
	V_MOV_B32_e32 v3, 6.550400e+04                                       ; 7E0602FF 477FE000
	V_CMP_GE_F32_e64 s[8:9], v2, v3, 0, 0, 0, 0                          ; D00C0008 02020702
	V_CMP_U_F32_e64 s[10:11], v2, v2, 0, 0, 0, 0                         ; D010000A 02020502
	S_OR_B64 s[8:9], s[8:9], s[10:11]                                    ; 88880A08
	V_CNDMASK_B32_e64 v2, v2, v3, s[8:9], 0, 0, 0, 0                     ; D2000002 00220702
	V_INTERP_P1_F32 v4, v0, 1, 0, [m0]                                   ; C8100100
	V_INTERP_P2_F32 v4, [v4], v1, 1, 0, [m0]                             ; C8110101
	S_LOAD_DWORDX4 s[8:11], s[0:1], 0                                    ; C0840100
	S_WAITCNT lgkmcnt(0)                                                 ; BF8C007F
	S_BUFFER_LOAD_DWORD s0, s[8:11], 1                                   ; C2000901
	S_WAITCNT lgkmcnt(0)                                                 ; BF8C007F
	V_ADD_F32_e32 v5, s0, v4                                             ; 060A0800
	V_INTERP_P1_F32 v6, v0, 0, 0, [m0]                                   ; C8180000
	V_INTERP_P2_F32 v6, [v6], v1, 0, 0, [m0]                             ; C8190001
	S_BUFFER_LOAD_DWORD s0, s[8:11], 0                                   ; C2000900
	S_WAITCNT lgkmcnt(0)                                                 ; BF8C007F
	V_ADD_F32_e32 v4, s0, v6                                             ; 06080C00
	S_LOAD_DWORDX4 s[0:3], s[2:3], 0                                     ; C0800300
	S_LOAD_DWORDX8 s[4:11], s[4:5], 0                                    ; C0C20500
	S_WAITCNT lgkmcnt(0)                                                 ; BF8C007F
	IMAGE_SAMPLE v[4:6], 7, 0, 0, 0, 0, 0, 0, 0, v[4:5], s[4:11], s[0:3] ; F0800700 00010404
	S_WAITCNT vmcnt(0)                                                   ; BF8C0770
	V_CMP_U_F32_e64 s[0:1], v6, v6, 0, 0, 0, 0                           ; D0100000 02020D06
	V_CMP_GE_F32_e64 s[2:3], v6, v3, 0, 0, 0, 0                          ; D00C0002 02020706
	S_OR_B64 s[0:1], s[2:3], s[0:1]                                      ; 88800002
	V_CNDMASK_B32_e64 v0, v6, v3, s[0:1], 0, 0, 0, 0                     ; D2000000 00020706
	V_CVT_PKRTZ_F16_F32_e32 v0, v0, v2                                   ; 5E000500
	V_CMP_U_F32_e64 s[0:1], v5, v5, 0, 0, 0, 0                           ; D0100000 02020B05
	V_CMP_GE_F32_e64 s[2:3], v5, v3, 0, 0, 0, 0                          ; D00C0002 02020705
	S_OR_B64 s[0:1], s[2:3], s[0:1]                                      ; 88800002
	V_CNDMASK_B32_e64 v1, v5, v3, s[0:1], 0, 0, 0, 0                     ; D2000001 00020705
	V_CMP_U_F32_e64 s[0:1], v4, v4, 0, 0, 0, 0                           ; D0100000 02020904
	V_CMP_GE_F32_e64 s[2:3], v4, v3, 0, 0, 0, 0                          ; D00C0002 02020704
	S_OR_B64 s[0:1], s[2:3], s[0:1]                                      ; 88800002
	V_CNDMASK_B32_e64 v2, v4, v3, s[0:1], 0, 0, 0, 0                     ; D2000002 00020704
	V_CVT_PKRTZ_F16_F32_e32 v1, v2, v1                                   ; 5E020302
	EXP 15, 0, 1, 1, 1, v1, v0, v1, v0                                   ; F8001C0F 00010001
	S_ENDPGM                                                             ; BF810000

VERT
DCL IN[0]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[19]
DCL CONST[0..1]
DCL TEMP[0..2], LOCAL
IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
  0: MOV TEMP[0].zw, IMM[0].yyxy
  1: MOV TEMP[0].xy, IN[0].xyxx
  2: MAD TEMP[1].xy, IN[0].zwww, CONST[0].xyyy, CONST[0].zwww
  3: MAD TEMP[2].xy, IN[0].zwww, CONST[1].xyyy, CONST[1].zwww
  4: MOV TEMP[1].zw, TEMP[2].yyxy
  5: MOV OUT[1], TEMP[1]
  6: MOV OUT[0], TEMP[0]
  7: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0)
  %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4)
  %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8)
  %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12)
  %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16)
  %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20)
  %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24)
  %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28)
  %20 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %21, i32 0, i32 %6)
  %23 = extractelement <4 x float> %22, i32 0
  %24 = extractelement <4 x float> %22, i32 1
  %25 = extractelement <4 x float> %22, i32 2
  %26 = extractelement <4 x float> %22, i32 3
  %27 = fmul float %25, %12
  %28 = fadd float %27, %14
  %29 = fmul float %26, %13
  %30 = fadd float %29, %15
  %31 = fmul float %25, %16
  %32 = fadd float %31, %18
  %33 = fmul float %26, %17
  %34 = fadd float %33, %19
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %28, float %30, float %32, float %34)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %23, float %24, float 0.000000e+00, float 1.000000e+00)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg6

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%23](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%11](align=8)(tbaa=!"const")
	S_WAITCNT 112
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 7; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR4<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 5; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR3, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 6; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 4; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR2, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 3; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR3, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 0; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR8<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR2, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 32, 0, 0, 0, %VGPR7<kill>, %VGPR6<kill>, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>
	S_WAITCNT 1807
	%VGPR4<def> = V_MOV_B32_e32 1.000000e+00, %EXEC<imp-use>
	%VGPR5<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR1, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_LOAD_DWORDX4 s[4:7], s[6:7], 0               ; C0820700
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	BUFFER_LOAD_FORMAT_XYZW v[0:3], s[4:7][v0] + 0 ; E00C2000 80010000
	S_LOAD_DWORDX4 s[0:3], s[0:1], 0               ; C0800100
	S_WAITCNT vmcnt(0) lgkmcnt(0)                  ; BF8C0070
	S_BUFFER_LOAD_DWORD s4, s[0:3], 7              ; C2020107
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v4, s4                           ; 7E080204
	S_BUFFER_LOAD_DWORD s4, s[0:3], 5              ; C2020105
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v5, s4                           ; 7E0A0204
	V_MAD_F32 v4, v3, v5, v4, 0, 0, 0, 0           ; D2820004 04120B03
	S_BUFFER_LOAD_DWORD s4, s[0:3], 6              ; C2020106
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v5, s4                           ; 7E0A0204
	S_BUFFER_LOAD_DWORD s4, s[0:3], 4              ; C2020104
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v6, s4                           ; 7E0C0204
	V_MAD_F32 v5, v2, v6, v5, 0, 0, 0, 0           ; D2820005 04160D02
	S_BUFFER_LOAD_DWORD s4, s[0:3], 3              ; C2020103
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v6, s4                           ; 7E0C0204
	S_BUFFER_LOAD_DWORD s4, s[0:3], 1              ; C2020101
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v7, s4                           ; 7E0E0204
	V_MAD_F32 v6, v3, v7, v6, 0, 0, 0, 0           ; D2820006 041A0F03
	S_BUFFER_LOAD_DWORD s4, s[0:3], 2              ; C2020102
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v7, s4                           ; 7E0E0204
	S_BUFFER_LOAD_DWORD s0, s[0:3], 0              ; C2000100
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v8, s0                           ; 7E100200
	V_MAD_F32 v7, v2, v8, v7, 0, 0, 0, 0           ; D2820007 041E1102
	EXP 15, 32, 0, 0, 0, v7, v6, v5, v4            ; F800020F 04050607
	S_WAITCNT expcnt(0)                            ; BF8C070F
	V_MOV_B32_e32 v4, 1.000000e+00                 ; 7E0802F2
	V_MOV_B32_e32 v5, 0.000000e+00                 ; 7E0A0280
	EXP 15, 12, 0, 1, 0, v0, v1, v5, v4            ; F80008CF 04050100
	S_ENDPGM                                       ; BF810000

FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL CONST[0..223]
DCL TEMP[0..1], LOCAL
IMM[0] FLT32 {    0.2500, 65504.0000,     0.0000,     0.0000}
  0: ADD TEMP[0].xy, IN[0].xyyy, CONST[0].xyyy
  1: MOV TEMP[0].xy, TEMP[0].xyyy
  2: TEX TEMP[0], TEMP[0], SAMP[0], 2D
  3: ADD TEMP[1].xy, IN[0].xyyy, CONST[1].xyyy
  4: MOV TEMP[1].xy, TEMP[1].xyyy
  5: TEX TEMP[1], TEMP[1], SAMP[0], 2D
  6: ADD TEMP[0], TEMP[0], TEMP[1]
  7: ADD TEMP[1].xy, IN[0].xyyy, CONST[2].xyyy
  8: MOV TEMP[1].xy, TEMP[1].xyyy
  9: TEX TEMP[1], TEMP[1], SAMP[0], 2D
 10: ADD TEMP[0], TEMP[0], TEMP[1]
 11: ADD TEMP[1].xy, IN[0].xyyy, CONST[3].xyyy
 12: MOV TEMP[1].xy, TEMP[1].xyyy
 13: TEX TEMP[1], TEMP[1], SAMP[0], 2D
 14: ADD TEMP[0], TEMP[0], TEMP[1]
 15: MUL TEMP[0], TEMP[0], IMM[0].xxxx
 16: MIN TEMP[0], TEMP[0], IMM[0].yyyy
 17: MOV OUT[0], TEMP[0]
 18: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %21 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
  %22 = load <16 x i8> addrspace(2)* %21, !tbaa !0
  %23 = call float @llvm.SI.load.const(<16 x i8> %22, i32 0)
  %24 = call float @llvm.SI.load.const(<16 x i8> %22, i32 4)
  %25 = call float @llvm.SI.load.const(<16 x i8> %22, i32 16)
  %26 = call float @llvm.SI.load.const(<16 x i8> %22, i32 20)
  %27 = call float @llvm.SI.load.const(<16 x i8> %22, i32 32)
  %28 = call float @llvm.SI.load.const(<16 x i8> %22, i32 36)
  %29 = call float @llvm.SI.load.const(<16 x i8> %22, i32 48)
  %30 = call float @llvm.SI.load.const(<16 x i8> %22, i32 52)
  %31 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0
  %32 = load <32 x i8> addrspace(2)* %31, !tbaa !0
  %33 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0
  %34 = load <16 x i8> addrspace(2)* %33, !tbaa !0
  %35 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %4, <2 x i32> %6)
  %36 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %4, <2 x i32> %6)
  %37 = fadd float %35, %23
  %38 = fadd float %36, %24
  %39 = bitcast float %37 to i32
  %40 = bitcast float %38 to i32
  %41 = insertelement <2 x i32> undef, i32 %39, i32 0
  %42 = insertelement <2 x i32> %41, i32 %40, i32 1
  %43 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %42, <32 x i8> %32, <16 x i8> %34, i32 2)
  %44 = extractelement <4 x float> %43, i32 0
  %45 = extractelement <4 x float> %43, i32 1
  %46 = extractelement <4 x float> %43, i32 2
  %47 = extractelement <4 x float> %43, i32 3
  %48 = fadd float %35, %25
  %49 = fadd float %36, %26
  %50 = bitcast float %48 to i32
  %51 = bitcast float %49 to i32
  %52 = insertelement <2 x i32> undef, i32 %50, i32 0
  %53 = insertelement <2 x i32> %52, i32 %51, i32 1
  %54 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %53, <32 x i8> %32, <16 x i8> %34, i32 2)
  %55 = extractelement <4 x float> %54, i32 0
  %56 = extractelement <4 x float> %54, i32 1
  %57 = extractelement <4 x float> %54, i32 2
  %58 = extractelement <4 x float> %54, i32 3
  %59 = fadd float %44, %55
  %60 = fadd float %45, %56
  %61 = fadd float %46, %57
  %62 = fadd float %47, %58
  %63 = fadd float %35, %27
  %64 = fadd float %36, %28
  %65 = bitcast float %63 to i32
  %66 = bitcast float %64 to i32
  %67 = insertelement <2 x i32> undef, i32 %65, i32 0
  %68 = insertelement <2 x i32> %67, i32 %66, i32 1
  %69 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %68, <32 x i8> %32, <16 x i8> %34, i32 2)
  %70 = extractelement <4 x float> %69, i32 0
  %71 = extractelement <4 x float> %69, i32 1
  %72 = extractelement <4 x float> %69, i32 2
  %73 = extractelement <4 x float> %69, i32 3
  %74 = fadd float %59, %70
  %75 = fadd float %60, %71
  %76 = fadd float %61, %72
  %77 = fadd float %62, %73
  %78 = fadd float %35, %29
  %79 = fadd float %36, %30
  %80 = bitcast float %78 to i32
  %81 = bitcast float %79 to i32
  %82 = insertelement <2 x i32> undef, i32 %80, i32 0
  %83 = insertelement <2 x i32> %82, i32 %81, i32 1
  %84 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %83, <32 x i8> %32, <16 x i8> %34, i32 2)
  %85 = extractelement <4 x float> %84, i32 0
  %86 = extractelement <4 x float> %84, i32 1
  %87 = extractelement <4 x float> %84, i32 2
  %88 = extractelement <4 x float> %84, i32 3
  %89 = fadd float %74, %85
  %90 = fadd float %75, %86
  %91 = fadd float %76, %87
  %92 = fadd float %77, %88
  %93 = fmul float %89, 2.500000e-01
  %94 = fmul float %90, 2.500000e-01
  %95 = fmul float %91, 2.500000e-01
  %96 = fmul float %92, 2.500000e-01
  %97 = fcmp uge float %93, 6.550400e+04
  %98 = select i1 %97, float 6.550400e+04, float %93
  %99 = fcmp uge float %94, 6.550400e+04
  %100 = select i1 %99, float 6.550400e+04, float %94
  %101 = fcmp uge float %95, 6.550400e+04
  %102 = select i1 %101, float 6.550400e+04, float %95
  %103 = fcmp uge float %96, 6.550400e+04
  %104 = select i1 %103, float 6.550400e+04, float %96
  %105 = call i32 @llvm.SI.packf16(float %98, float %100)
  %106 = bitcast i32 %105 to float
  %107 = call i32 @llvm.SI.packf16(float %102, float %104)
  %108 = bitcast i32 %107 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %106, float %108, float %106, float %108)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR7 in %vreg4, %VGPR0 in %vreg5, %VGPR1 in %vreg6

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR7 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR7
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<kill,tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%22](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 5; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR4<def> = V_ADD_F32_e32 %SGPR0<kill>, %VGPR2, %EXEC<imp-use>, %VGPR3_VGPR4<imp-def>
	%VGPR5<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR5<def,tied1> = V_INTERP_P2_F32 %VGPR5<kill,tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 4; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR3<def> = V_ADD_F32_e32 %SGPR0<kill>, %VGPR5, %EXEC<imp-use>, %VGPR3_VGPR4<imp-use,kill>, %VGPR3_VGPR4<imp-def>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%36](align=8)(tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%33](tbaa=!"const")
	S_WAITCNT 127
	%VGPR6_VGPR7_VGPR8_VGPR9<def> = IMAGE_SAMPLE_V4_V2 15, 0, 0, 0, 0, 0, 0, 0, %VGPR3_VGPR4<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR0_SGPR1_SGPR2_SGPR3, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 1; mem:LD4[<unknown>]
	S_WAITCNT 112
	%VGPR1<def> = V_ADD_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>, %VGPR0_VGPR1<imp-def>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 0; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR0<def> = V_ADD_F32_e32 %SGPR4<kill>, %VGPR5, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%VGPR10_VGPR11_VGPR12_VGPR13<def> = IMAGE_SAMPLE_V4_V2 15, 0, 0, 0, 0, 0, 0, 0, %VGPR0_VGPR1<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR0_SGPR1_SGPR2_SGPR3, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR0<def> = V_ADD_F32_e32 %VGPR13, %VGPR9, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 9; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR4<def> = V_ADD_F32_e32 %SGPR4<kill>, %VGPR2, %EXEC<imp-use>, %VGPR3_VGPR4<imp-def>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 8; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR3<def> = V_ADD_F32_e32 %SGPR4<kill>, %VGPR5, %EXEC<imp-use>, %VGPR3_VGPR4<imp-use,kill>, %VGPR3_VGPR4<imp-def>
	%VGPR14_VGPR15_VGPR16_VGPR17<def> = IMAGE_SAMPLE_V4_V2 15, 0, 0, 0, 0, 0, 0, 0, %VGPR3_VGPR4<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR0_SGPR1_SGPR2_SGPR3, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR0<def> = V_ADD_F32_e32 %VGPR0<kill>, %VGPR17, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 13; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR2<def> = V_ADD_F32_e32 %SGPR4<kill>, %VGPR2<kill>, %EXEC<imp-use>, %VGPR1_VGPR2<imp-def>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11<kill>, 12; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR1<def> = V_ADD_F32_e32 %SGPR4<kill>, %VGPR5<kill>, %EXEC<imp-use>, %VGPR1_VGPR2<imp-use,kill>, %VGPR1_VGPR2<imp-def>
	%VGPR1_VGPR2_VGPR3_VGPR4<def> = IMAGE_SAMPLE_V4_V2 15, 0, 0, 0, 0, 0, 0, 0, %VGPR1_VGPR2<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR0<def> = V_ADD_F32_e32 %VGPR0<kill>, %VGPR4, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_F32_e32 2.500000e-01, %VGPR0<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MOV_B32_e32 6.550400e+04, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = V_CMP_GE_F32_e64 %VGPR0, %VGPR5, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_U_F32_e64 %VGPR0, %VGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_OR_B64 %SGPR0_SGPR1<kill>, %SGPR2_SGPR3<kill>
	%VGPR0<def> = V_CNDMASK_B32_e64 %VGPR0<kill>, %VGPR5, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR18<def> = V_ADD_F32_e32 %VGPR12, %VGPR8, %EXEC<imp-use>
	%VGPR18<def> = V_ADD_F32_e32 %VGPR18<kill>, %VGPR16, %EXEC<imp-use>
	%VGPR18<def> = V_ADD_F32_e32 %VGPR18<kill>, %VGPR3, %EXEC<imp-use>
	%VGPR18<def> = V_MUL_F32_e32 2.500000e-01, %VGPR18<kill>, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = V_CMP_GE_F32_e64 %VGPR18, %VGPR5, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_U_F32_e64 %VGPR18, %VGPR18, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_OR_B64 %SGPR0_SGPR1<kill>, %SGPR2_SGPR3<kill>
	%VGPR18<def> = V_CNDMASK_B32_e64 %VGPR18<kill>, %VGPR5, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR18<kill>, %VGPR0<kill>, %EXEC<imp-use>
	%VGPR18<def> = V_ADD_F32_e32 %VGPR11, %VGPR7, %EXEC<imp-use>
	%VGPR18<def> = V_ADD_F32_e32 %VGPR18<kill>, %VGPR15, %EXEC<imp-use>
	%VGPR18<def> = V_ADD_F32_e32 %VGPR18<kill>, %VGPR2, %EXEC<imp-use>
	%VGPR18<def> = V_MUL_F32_e32 2.500000e-01, %VGPR18<kill>, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = V_CMP_GE_F32_e64 %VGPR18, %VGPR5, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_U_F32_e64 %VGPR18, %VGPR18, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_OR_B64 %SGPR0_SGPR1<kill>, %SGPR2_SGPR3<kill>
	%VGPR18<def> = V_CNDMASK_B32_e64 %VGPR18<kill>, %VGPR5, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_ADD_F32_e32 %VGPR10, %VGPR6, %EXEC<imp-use>, %VGPR6_VGPR7_VGPR8_VGPR9<imp-use,kill>, %VGPR10_VGPR11_VGPR12_VGPR13<imp-use,kill>
	%VGPR6<def> = V_ADD_F32_e32 %VGPR6<kill>, %VGPR14, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17<imp-use,kill>
	%VGPR1<def> = V_ADD_F32_e32 %VGPR6<kill>, %VGPR1, %EXEC<imp-use>, %VGPR1_VGPR2_VGPR3_VGPR4<imp-use,kill>
	%VGPR1<def> = V_MUL_F32_e32 2.500000e-01, %VGPR1<kill>, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = V_CMP_GE_F32_e64 %VGPR1, %VGPR5, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_U_F32_e64 %VGPR1, %VGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_OR_B64 %SGPR0_SGPR1<kill>, %SGPR2_SGPR3<kill>
	%VGPR1<def> = V_CNDMASK_B32_e64 %VGPR1<kill>, %VGPR5<kill>, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR1<kill>, %VGPR18<kill>, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR1<kill>, %VGPR0<kill>, %VGPR1, %VGPR0, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_WQM_B64 exec, exec                                                     ; BEFE0A7E
	S_MOV_B32 m0, s7                                                         ; BEFC0307
	V_INTERP_P1_F32 v2, v0, 1, 0, [m0]                                       ; C8080100
	V_INTERP_P2_F32 v2, [v2], v1, 1, 0, [m0]                                 ; C8090101
	S_LOAD_DWORDX4 s[8:11], s[0:1], 0                                        ; C0840100
	S_WAITCNT lgkmcnt(0)                                                     ; BF8C007F
	S_BUFFER_LOAD_DWORD s0, s[8:11], 5                                       ; C2000905
	S_WAITCNT lgkmcnt(0)                                                     ; BF8C007F
	V_ADD_F32_e32 v4, s0, v2                                                 ; 06080400
	V_INTERP_P1_F32 v5, v0, 0, 0, [m0]                                       ; C8140000
	V_INTERP_P2_F32 v5, [v5], v1, 0, 0, [m0]                                 ; C8150001
	S_BUFFER_LOAD_DWORD s0, s[8:11], 4                                       ; C2000904
	S_WAITCNT lgkmcnt(0)                                                     ; BF8C007F
	V_ADD_F32_e32 v3, s0, v5                                                 ; 06060A00
	S_LOAD_DWORDX4 s[0:3], s[2:3], 0                                         ; C0800300
	S_LOAD_DWORDX8 s[12:19], s[4:5], 0                                       ; C0C60500
	S_WAITCNT lgkmcnt(0)                                                     ; BF8C007F
	IMAGE_SAMPLE v[6:9], 15, 0, 0, 0, 0, 0, 0, 0, v[3:4], s[12:19], s[0:3]   ; F0800F00 00030603
	S_BUFFER_LOAD_DWORD s4, s[8:11], 1                                       ; C2020901
	S_WAITCNT vmcnt(0) lgkmcnt(0)                                            ; BF8C0070
	V_ADD_F32_e32 v1, s4, v2                                                 ; 06020404
	S_BUFFER_LOAD_DWORD s4, s[8:11], 0                                       ; C2020900
	S_WAITCNT lgkmcnt(0)                                                     ; BF8C007F
	V_ADD_F32_e32 v0, s4, v5                                                 ; 06000A04
	IMAGE_SAMPLE v[10:13], 15, 0, 0, 0, 0, 0, 0, 0, v[0:1], s[12:19], s[0:3] ; F0800F00 00030A00
	S_WAITCNT vmcnt(0)                                                       ; BF8C0770
	V_ADD_F32_e32 v0, v13, v9                                                ; 0600130D
	S_BUFFER_LOAD_DWORD s4, s[8:11], 9                                       ; C2020909
	S_WAITCNT lgkmcnt(0)                                                     ; BF8C007F
	V_ADD_F32_e32 v4, s4, v2                                                 ; 06080404
	S_BUFFER_LOAD_DWORD s4, s[8:11], 8                                       ; C2020908
	S_WAITCNT lgkmcnt(0)                                                     ; BF8C007F
	V_ADD_F32_e32 v3, s4, v5                                                 ; 06060A04
	IMAGE_SAMPLE v[14:17], 15, 0, 0, 0, 0, 0, 0, 0, v[3:4], s[12:19], s[0:3] ; F0800F00 00030E03
	S_WAITCNT vmcnt(0)                                                       ; BF8C0770
	V_ADD_F32_e32 v0, v0, v17                                                ; 06002300
	S_BUFFER_LOAD_DWORD s4, s[8:11], 13                                      ; C202090D
	S_WAITCNT lgkmcnt(0)                                                     ; BF8C007F
	V_ADD_F32_e32 v2, s4, v2                                                 ; 06040404
	S_BUFFER_LOAD_DWORD s4, s[8:11], 12                                      ; C202090C
	S_WAITCNT lgkmcnt(0)                                                     ; BF8C007F
	V_ADD_F32_e32 v1, s4, v5                                                 ; 06020A04
	IMAGE_SAMPLE v[1:4], 15, 0, 0, 0, 0, 0, 0, 0, v[1:2], s[12:19], s[0:3]   ; F0800F00 00030101
	S_WAITCNT vmcnt(0)                                                       ; BF8C0770
	V_ADD_F32_e32 v0, v0, v4                                                 ; 06000900
	V_MUL_F32_e32 v0, 2.500000e-01, v0                                       ; 100000FF 3E800000
	V_MOV_B32_e32 v5, 6.550400e+04                                           ; 7E0A02FF 477FE000
	V_CMP_GE_F32_e64 s[0:1], v0, v5, 0, 0, 0, 0                              ; D00C0000 02020B00
	V_CMP_U_F32_e64 s[2:3], v0, v0, 0, 0, 0, 0                               ; D0100002 02020100
	S_OR_B64 s[0:1], s[0:1], s[2:3]                                          ; 88800200
	V_CNDMASK_B32_e64 v0, v0, v5, s[0:1], 0, 0, 0, 0                         ; D2000000 00020B00
	V_ADD_F32_e32 v18, v12, v8                                               ; 0624110C
	V_ADD_F32_e32 v18, v18, v16                                              ; 06242112
	V_ADD_F32_e32 v18, v18, v3                                               ; 06240712
	V_MUL_F32_e32 v18, 2.500000e-01, v18                                     ; 102424FF 3E800000
	V_CMP_GE_F32_e64 s[0:1], v18, v5, 0, 0, 0, 0                             ; D00C0000 02020B12
	V_CMP_U_F32_e64 s[2:3], v18, v18, 0, 0, 0, 0                             ; D0100002 02022512
	S_OR_B64 s[0:1], s[0:1], s[2:3]                                          ; 88800200
	V_CNDMASK_B32_e64 v18, v18, v5, s[0:1], 0, 0, 0, 0                       ; D2000012 00020B12
	V_CVT_PKRTZ_F16_F32_e32 v0, v18, v0                                      ; 5E000112
	V_ADD_F32_e32 v18, v11, v7                                               ; 06240F0B
	V_ADD_F32_e32 v18, v18, v15                                              ; 06241F12
	V_ADD_F32_e32 v18, v18, v2                                               ; 06240512
	V_MUL_F32_e32 v18, 2.500000e-01, v18                                     ; 102424FF 3E800000
	V_CMP_GE_F32_e64 s[0:1], v18, v5, 0, 0, 0, 0                             ; D00C0000 02020B12
	V_CMP_U_F32_e64 s[2:3], v18, v18, 0, 0, 0, 0                             ; D0100002 02022512
	S_OR_B64 s[0:1], s[0:1], s[2:3]                                          ; 88800200
	V_CNDMASK_B32_e64 v18, v18, v5, s[0:1], 0, 0, 0, 0                       ; D2000012 00020B12
	V_ADD_F32_e32 v6, v10, v6                                                ; 060C0D0A
	V_ADD_F32_e32 v6, v6, v14                                                ; 060C1D06
	V_ADD_F32_e32 v1, v6, v1                                                 ; 06020306
	V_MUL_F32_e32 v1, 2.500000e-01, v1                                       ; 100202FF 3E800000
	V_CMP_GE_F32_e64 s[0:1], v1, v5, 0, 0, 0, 0                              ; D00C0000 02020B01
	V_CMP_U_F32_e64 s[2:3], v1, v1, 0, 0, 0, 0                               ; D0100002 02020301
	S_OR_B64 s[0:1], s[0:1], s[2:3]                                          ; 88800200
	V_CNDMASK_B32_e64 v1, v1, v5, s[0:1], 0, 0, 0, 0                         ; D2000001 00020B01
	V_CVT_PKRTZ_F16_F32_e32 v1, v1, v18                                      ; 5E022501
	EXP 15, 0, 1, 1, 1, v1, v0, v1, v0                                       ; F8001C0F 00010001
	S_ENDPGM                                                                 ; BF810000

VERT
DCL IN[0]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[19]
DCL CONST[0..1]
DCL TEMP[0..2], LOCAL
IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
  0: MOV TEMP[0].zw, IMM[0].yyxy
  1: MOV TEMP[0].xy, IN[0].xyxx
  2: MAD TEMP[1].xy, IN[0].zwww, CONST[0].xyyy, CONST[0].zwww
  3: MAD TEMP[2].xy, IN[0].zwww, CONST[1].xyyy, CONST[1].zwww
  4: MOV TEMP[1].zw, TEMP[2].yyxy
  5: MOV OUT[1], TEMP[1]
  6: MOV OUT[0], TEMP[0]
  7: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0)
  %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4)
  %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8)
  %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12)
  %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16)
  %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20)
  %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24)
  %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28)
  %20 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %21, i32 0, i32 %6)
  %23 = extractelement <4 x float> %22, i32 0
  %24 = extractelement <4 x float> %22, i32 1
  %25 = extractelement <4 x float> %22, i32 2
  %26 = extractelement <4 x float> %22, i32 3
  %27 = fmul float %25, %12
  %28 = fadd float %27, %14
  %29 = fmul float %26, %13
  %30 = fadd float %29, %15
  %31 = fmul float %25, %16
  %32 = fadd float %31, %18
  %33 = fmul float %26, %17
  %34 = fadd float %33, %19
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %28, float %30, float %32, float %34)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %23, float %24, float 0.000000e+00, float 1.000000e+00)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg6

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%23](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%11](align=8)(tbaa=!"const")
	S_WAITCNT 112
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 7; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR4<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 5; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR3, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 6; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 4; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR2, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 3; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR3, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 0; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR8<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR2, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 32, 0, 0, 0, %VGPR7<kill>, %VGPR6<kill>, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>
	S_WAITCNT 1807
	%VGPR4<def> = V_MOV_B32_e32 1.000000e+00, %EXEC<imp-use>
	%VGPR5<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR1, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_LOAD_DWORDX4 s[4:7], s[6:7], 0               ; C0820700
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	BUFFER_LOAD_FORMAT_XYZW v[0:3], s[4:7][v0] + 0 ; E00C2000 80010000
	S_LOAD_DWORDX4 s[0:3], s[0:1], 0               ; C0800100
	S_WAITCNT vmcnt(0) lgkmcnt(0)                  ; BF8C0070
	S_BUFFER_LOAD_DWORD s4, s[0:3], 7              ; C2020107
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v4, s4                           ; 7E080204
	S_BUFFER_LOAD_DWORD s4, s[0:3], 5              ; C2020105
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v5, s4                           ; 7E0A0204
	V_MAD_F32 v4, v3, v5, v4, 0, 0, 0, 0           ; D2820004 04120B03
	S_BUFFER_LOAD_DWORD s4, s[0:3], 6              ; C2020106
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v5, s4                           ; 7E0A0204
	S_BUFFER_LOAD_DWORD s4, s[0:3], 4              ; C2020104
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v6, s4                           ; 7E0C0204
	V_MAD_F32 v5, v2, v6, v5, 0, 0, 0, 0           ; D2820005 04160D02
	S_BUFFER_LOAD_DWORD s4, s[0:3], 3              ; C2020103
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v6, s4                           ; 7E0C0204
	S_BUFFER_LOAD_DWORD s4, s[0:3], 1              ; C2020101
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v7, s4                           ; 7E0E0204
	V_MAD_F32 v6, v3, v7, v6, 0, 0, 0, 0           ; D2820006 041A0F03
	S_BUFFER_LOAD_DWORD s4, s[0:3], 2              ; C2020102
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v7, s4                           ; 7E0E0204
	S_BUFFER_LOAD_DWORD s0, s[0:3], 0              ; C2000100
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v8, s0                           ; 7E100200
	V_MAD_F32 v7, v2, v8, v7, 0, 0, 0, 0           ; D2820007 041E1102
	EXP 15, 32, 0, 0, 0, v7, v6, v5, v4            ; F800020F 04050607
	S_WAITCNT expcnt(0)                            ; BF8C070F
	V_MOV_B32_e32 v4, 1.000000e+00                 ; 7E0802F2
	V_MOV_B32_e32 v5, 0.000000e+00                 ; 7E0A0280
	EXP 15, 12, 0, 1, 0, v0, v1, v5, v4            ; F80008CF 04050100
	S_ENDPGM                                       ; BF810000

FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL SAMP[1]
DCL CONST[0]
DCL TEMP[0..2], LOCAL
IMM[0] FLT32 {    1.0000,     0.0000, 65504.0000,     0.5000}
  0: MOV TEMP[0].w, IMM[0].xxxx
  1: MOV TEMP[1].xy, IN[0].xyyy
  2: TEX TEMP[1].xyz, TEMP[1], SAMP[0], 2D
  3: MAX TEMP[1].xyz, TEMP[1].xyzz, IMM[0].yyyy
  4: MIN TEMP[1].xyz, TEMP[1].xyzz, IMM[0].zzzz
  5: MOV TEMP[2].xy, IMM[0].wwww
  6: TEX TEMP[2].x, TEMP[2], SAMP[1], 2D
  7: MUL TEMP[0].xyz, TEMP[1].xyzz, TEMP[2].xxxx
  8: MUL TEMP[0].xyz, TEMP[0].xyzz, CONST[0].xxxx
  9: ADD TEMP[0].xyz, TEMP[0].xyzz, -CONST[0].yyyy
 10: MAX TEMP[0].xyz, TEMP[0].xyzz, IMM[0].yyyy
 11: MOV OUT[0], TEMP[0]
 12: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %21 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
  %22 = load <16 x i8> addrspace(2)* %21, !tbaa !0
  %23 = call float @llvm.SI.load.const(<16 x i8> %22, i32 0)
  %24 = call float @llvm.SI.load.const(<16 x i8> %22, i32 4)
  %25 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0
  %26 = load <32 x i8> addrspace(2)* %25, !tbaa !0
  %27 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0
  %28 = load <16 x i8> addrspace(2)* %27, !tbaa !0
  %29 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 1
  %30 = load <32 x i8> addrspace(2)* %29, !tbaa !0
  %31 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 1
  %32 = load <16 x i8> addrspace(2)* %31, !tbaa !0
  %33 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %4, <2 x i32> %6)
  %34 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %4, <2 x i32> %6)
  %35 = bitcast float %33 to i32
  %36 = bitcast float %34 to i32
  %37 = insertelement <2 x i32> undef, i32 %35, i32 0
  %38 = insertelement <2 x i32> %37, i32 %36, i32 1
  %39 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %38, <32 x i8> %26, <16 x i8> %28, i32 2)
  %40 = extractelement <4 x float> %39, i32 0
  %41 = extractelement <4 x float> %39, i32 1
  %42 = extractelement <4 x float> %39, i32 2
  %43 = fcmp uge float %40, 0.000000e+00
  %44 = select i1 %43, float %40, float 0.000000e+00
  %45 = fcmp uge float %41, 0.000000e+00
  %46 = select i1 %45, float %41, float 0.000000e+00
  %47 = fcmp uge float %42, 0.000000e+00
  %48 = select i1 %47, float %42, float 0.000000e+00
  %49 = fcmp uge float %44, 6.550400e+04
  %50 = select i1 %49, float 6.550400e+04, float %44
  %51 = fcmp uge float %46, 6.550400e+04
  %52 = select i1 %51, float 6.550400e+04, float %46
  %53 = fcmp uge float %48, 6.550400e+04
  %54 = select i1 %53, float 6.550400e+04, float %48
  %55 = bitcast float 5.000000e-01 to i32
  %56 = bitcast float 5.000000e-01 to i32
  %57 = insertelement <2 x i32> undef, i32 %55, i32 0
  %58 = insertelement <2 x i32> %57, i32 %56, i32 1
  %59 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %58, <32 x i8> %30, <16 x i8> %32, i32 2)
  %60 = extractelement <4 x float> %59, i32 0
  %61 = fmul float %50, %60
  %62 = fmul float %52, %60
  %63 = fmul float %54, %60
  %64 = fmul float %61, %23
  %65 = fmul float %62, %23
  %66 = fmul float %63, %23
  %67 = fsub float -0.000000e+00, %24
  %68 = fadd float %64, %67
  %69 = fsub float -0.000000e+00, %24
  %70 = fadd float %65, %69
  %71 = fsub float -0.000000e+00, %24
  %72 = fadd float %66, %71
  %73 = fcmp uge float %68, 0.000000e+00
  %74 = select i1 %73, float %68, float 0.000000e+00
  %75 = fcmp uge float %70, 0.000000e+00
  %76 = select i1 %75, float %70, float 0.000000e+00
  %77 = fcmp uge float %72, 0.000000e+00
  %78 = select i1 %77, float %72, float 0.000000e+00
  %79 = call i32 @llvm.SI.packf16(float %74, float %76)
  %80 = bitcast i32 %79 to float
  %81 = call i32 @llvm.SI.packf16(float %78, float 1.000000e+00)
  %82 = bitcast i32 %81 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %80, float %82, float %80, float %82)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR7 in %vreg4, %VGPR0 in %vreg5, %VGPR1 in %vreg6

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR7 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR7
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-def>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 0; mem:LD16[%30](align=8)(tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 0; mem:LD32[%27](tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2<def> = IMAGE_SAMPLE_V3_V2 7, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%SGPR6_SGPR7<def> = V_CMP_U_F32_e64 %VGPR1, %VGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8_SGPR9<def> = V_CMP_GE_F32_e64 %VGPR1, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = S_OR_B64 %SGPR8_SGPR9<kill>, %SGPR6_SGPR7<kill>
	%VGPR3<def> = V_CNDMASK_B32_e64 0.000000e+00, %VGPR1, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MOV_B32_e32 6.550400e+04, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %VGPR3, %VGPR4, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8_SGPR9<def> = V_CMP_U_F32_e64 %VGPR3, %VGPR3, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = S_OR_B64 %SGPR6_SGPR7<kill>, %SGPR8_SGPR9<kill>
	%VGPR3<def> = V_CNDMASK_B32_e64 %VGPR3<kill>, %VGPR4, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 4; mem:LD16[%36](align=8)(tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 8; mem:LD32[%33](tbaa=!"const")
	%VGPR5<def> = V_MOV_B32_e32 1056964608, %EXEC<imp-use>, %VGPR5_VGPR6<imp-def>
	%VGPR6<def> = V_MOV_B32_e32 %VGPR5, %EXEC<imp-use>, %VGPR5_VGPR6<imp-def>
	S_WAITCNT 127
	%VGPR5<def> = IMAGE_SAMPLE_V1_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR5_VGPR6<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR3<def> = V_MUL_F32_e32 %VGPR3<kill>, %VGPR5, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%22](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 0; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR4, %VGPR3<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 1; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR3<def> = V_SUBREV_F32_e32 %SGPR0, %VGPR3<kill>, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_U_F32_e64 %VGPR3, %VGPR3, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %VGPR3, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_OR_B64 %SGPR6_SGPR7<kill>, %SGPR2_SGPR3<kill>
	%VGPR3<def> = V_CNDMASK_B32_e64 0.000000e+00, %VGPR3<kill>, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_U_F32_e64 %VGPR0, %VGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %VGPR0, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_OR_B64 %SGPR6_SGPR7<kill>, %SGPR2_SGPR3<kill>
	%VGPR6<def> = V_CNDMASK_B32_e64 0.000000e+00, %VGPR0, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR6, %VGPR4, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_U_F32_e64 %VGPR6, %VGPR6, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_OR_B64 %SGPR2_SGPR3<kill>, %SGPR6_SGPR7<kill>
	%VGPR6<def> = V_CNDMASK_B32_e64 %VGPR6<kill>, %VGPR4, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %VGPR6<kill>, %VGPR5, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %SGPR4, %VGPR6<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_SUBREV_F32_e32 %SGPR0, %VGPR6<kill>, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_U_F32_e64 %VGPR6, %VGPR6, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %VGPR6, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_OR_B64 %SGPR6_SGPR7<kill>, %SGPR2_SGPR3<kill>
	%VGPR6<def> = V_CNDMASK_B32_e64 0.000000e+00, %VGPR6<kill>, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR6<kill>, %VGPR3<kill>, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_U_F32_e64 %VGPR2, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %VGPR2, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_OR_B64 %SGPR6_SGPR7<kill>, %SGPR2_SGPR3<kill>
	%VGPR0<def> = V_CNDMASK_B32_e64 0.000000e+00, %VGPR2, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2<imp-use,kill>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR0, %VGPR4, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_U_F32_e64 %VGPR0, %VGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_OR_B64 %SGPR2_SGPR3<kill>, %SGPR6_SGPR7<kill>
	%VGPR0<def> = V_CNDMASK_B32_e64 %VGPR0<kill>, %VGPR4<kill>, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR0<kill>, %VGPR5<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR0<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_SUBREV_F32_e32 %SGPR0<kill>, %VGPR0<kill>, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = V_CMP_U_F32_e64 %VGPR0, %VGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR0, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_OR_B64 %SGPR2_SGPR3<kill>, %SGPR0_SGPR1<kill>
	%VGPR0<def> = V_CNDMASK_B32_e64 0.000000e+00, %VGPR0<kill>, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e64 %VGPR0<kill>, 1.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR3<kill>, %VGPR0<kill>, %VGPR3, %VGPR0, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_WQM_B64 exec, exec                                                   ; BEFE0A7E
	S_MOV_B32 m0, s7                                                       ; BEFC0307
	V_INTERP_P1_F32 v3, v0, 1, 0, [m0]                                     ; C80C0100
	V_INTERP_P2_F32 v3, [v3], v1, 1, 0, [m0]                               ; C80D0101
	V_INTERP_P1_F32 v2, v0, 0, 0, [m0]                                     ; C8080000
	V_INTERP_P2_F32 v2, [v2], v1, 0, 0, [m0]                               ; C8090001
	S_LOAD_DWORDX4 s[8:11], s[2:3], 0                                      ; C0840300
	S_LOAD_DWORDX8 s[12:19], s[4:5], 0                                     ; C0C60500
	S_WAITCNT lgkmcnt(0)                                                   ; BF8C007F
	IMAGE_SAMPLE v[0:2], 7, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[12:19], s[8:11] ; F0800700 00430002
	S_WAITCNT vmcnt(0)                                                     ; BF8C0770
	V_CMP_U_F32_e64 s[6:7], v1, v1, 0, 0, 0, 0                             ; D0100006 02020301
	V_CMP_GE_F32_e64 s[8:9], v1, 0.000000e+00, 0, 0, 0, 0                  ; D00C0008 02010101
	S_OR_B64 s[6:7], s[8:9], s[6:7]                                        ; 88860608
	V_CNDMASK_B32_e64 v3, 0.000000e+00, v1, s[6:7], 0, 0, 0, 0             ; D2000003 001A0280
	V_MOV_B32_e32 v4, 6.550400e+04                                         ; 7E0802FF 477FE000
	V_CMP_GE_F32_e64 s[6:7], v3, v4, 0, 0, 0, 0                            ; D00C0006 02020903
	V_CMP_U_F32_e64 s[8:9], v3, v3, 0, 0, 0, 0                             ; D0100008 02020703
	S_OR_B64 s[6:7], s[6:7], s[8:9]                                        ; 88860806
	V_CNDMASK_B32_e64 v3, v3, v4, s[6:7], 0, 0, 0, 0                       ; D2000003 001A0903
	S_LOAD_DWORDX4 s[8:11], s[2:3], 4                                      ; C0840304
	S_LOAD_DWORDX8 s[12:19], s[4:5], 8                                     ; C0C60508
	V_MOV_B32_e32 v5, 1056964608                                           ; 7E0A02F0
	V_MOV_B32_e32 v6, v5                                                   ; 7E0C0305
	S_WAITCNT lgkmcnt(0)                                                   ; BF8C007F
	IMAGE_SAMPLE v5, 1, 0, 0, 0, 0, 0, 0, 0, v[5:6], s[12:19], s[8:11]     ; F0800100 00430505
	S_WAITCNT vmcnt(0)                                                     ; BF8C0770
	V_MUL_F32_e32 v3, v3, v5                                               ; 10060B03
	S_LOAD_DWORDX4 s[0:3], s[0:1], 0                                       ; C0800100
	S_WAITCNT lgkmcnt(0)                                                   ; BF8C007F
	S_BUFFER_LOAD_DWORD s4, s[0:3], 0                                      ; C2020100
	S_WAITCNT lgkmcnt(0)                                                   ; BF8C007F
	V_MUL_F32_e32 v3, s4, v3                                               ; 10060604
	S_BUFFER_LOAD_DWORD s0, s[0:3], 1                                      ; C2000101
	S_WAITCNT lgkmcnt(0)                                                   ; BF8C007F
	V_SUBREV_F32_e32 v3, s0, v3                                            ; 0A060600
	V_CMP_U_F32_e64 s[2:3], v3, v3, 0, 0, 0, 0                             ; D0100002 02020703
	V_CMP_GE_F32_e64 s[6:7], v3, 0.000000e+00, 0, 0, 0, 0                  ; D00C0006 02010103
	S_OR_B64 s[2:3], s[6:7], s[2:3]                                        ; 88820206
	V_CNDMASK_B32_e64 v3, 0.000000e+00, v3, s[2:3], 0, 0, 0, 0             ; D2000003 000A0680
	V_CMP_U_F32_e64 s[2:3], v0, v0, 0, 0, 0, 0                             ; D0100002 02020100
	V_CMP_GE_F32_e64 s[6:7], v0, 0.000000e+00, 0, 0, 0, 0                  ; D00C0006 02010100
	S_OR_B64 s[2:3], s[6:7], s[2:3]                                        ; 88820206
	V_CNDMASK_B32_e64 v6, 0.000000e+00, v0, s[2:3], 0, 0, 0, 0             ; D2000006 000A0080
	V_CMP_GE_F32_e64 s[2:3], v6, v4, 0, 0, 0, 0                            ; D00C0002 02020906
	V_CMP_U_F32_e64 s[6:7], v6, v6, 0, 0, 0, 0                             ; D0100006 02020D06
	S_OR_B64 s[2:3], s[2:3], s[6:7]                                        ; 88820602
	V_CNDMASK_B32_e64 v6, v6, v4, s[2:3], 0, 0, 0, 0                       ; D2000006 000A0906
	V_MUL_F32_e32 v6, v6, v5                                               ; 100C0B06
	V_MUL_F32_e32 v6, s4, v6                                               ; 100C0C04
	V_SUBREV_F32_e32 v6, s0, v6                                            ; 0A0C0C00
	V_CMP_U_F32_e64 s[2:3], v6, v6, 0, 0, 0, 0                             ; D0100002 02020D06
	V_CMP_GE_F32_e64 s[6:7], v6, 0.000000e+00, 0, 0, 0, 0                  ; D00C0006 02010106
	S_OR_B64 s[2:3], s[6:7], s[2:3]                                        ; 88820206
	V_CNDMASK_B32_e64 v6, 0.000000e+00, v6, s[2:3], 0, 0, 0, 0             ; D2000006 000A0C80
	V_CVT_PKRTZ_F16_F32_e32 v3, v6, v3                                     ; 5E060706
	V_CMP_U_F32_e64 s[2:3], v2, v2, 0, 0, 0, 0                             ; D0100002 02020502
	V_CMP_GE_F32_e64 s[6:7], v2, 0.000000e+00, 0, 0, 0, 0                  ; D00C0006 02010102
	S_OR_B64 s[2:3], s[6:7], s[2:3]                                        ; 88820206
	V_CNDMASK_B32_e64 v0, 0.000000e+00, v2, s[2:3], 0, 0, 0, 0             ; D2000000 000A0480
	V_CMP_GE_F32_e64 s[2:3], v0, v4, 0, 0, 0, 0                            ; D00C0002 02020900
	V_CMP_U_F32_e64 s[6:7], v0, v0, 0, 0, 0, 0                             ; D0100006 02020100
	S_OR_B64 s[2:3], s[2:3], s[6:7]                                        ; 88820602
	V_CNDMASK_B32_e64 v0, v0, v4, s[2:3], 0, 0, 0, 0                       ; D2000000 000A0900
	V_MUL_F32_e32 v0, v0, v5                                               ; 10000B00
	V_MUL_F32_e32 v0, s4, v0                                               ; 10000004
	V_SUBREV_F32_e32 v0, s0, v0                                            ; 0A000000
	V_CMP_U_F32_e64 s[0:1], v0, v0, 0, 0, 0, 0                             ; D0100000 02020100
	V_CMP_GE_F32_e64 s[2:3], v0, 0.000000e+00, 0, 0, 0, 0                  ; D00C0002 02010100
	S_OR_B64 s[0:1], s[2:3], s[0:1]                                        ; 88800002
	V_CNDMASK_B32_e64 v0, 0.000000e+00, v0, s[0:1], 0, 0, 0, 0             ; D2000000 00020080
	V_CVT_PKRTZ_F16_F32_e64 v0, v0, 1.000000e+00, 0, 0, 0, 0               ; D25E0000 0201E500
	EXP 15, 0, 1, 1, 1, v3, v0, v3, v0                                     ; F8001C0F 00030003
	S_ENDPGM                                                               ; BF810000

VERT
DCL IN[0]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[19]
DCL CONST[0..1]
DCL TEMP[0..2], LOCAL
IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
  0: MOV TEMP[0].zw, IMM[0].yyxy
  1: MOV TEMP[0].xy, IN[0].xyxx
  2: MAD TEMP[1].xy, IN[0].zwww, CONST[0].xyyy, CONST[0].zwww
  3: MAD TEMP[2].xy, IN[0].zwww, CONST[1].xyyy, CONST[1].zwww
  4: MOV TEMP[1].zw, TEMP[2].yyxy
  5: MOV OUT[1], TEMP[1]
  6: MOV OUT[0], TEMP[0]
  7: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0)
  %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4)
  %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8)
  %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12)
  %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16)
  %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20)
  %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24)
  %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28)
  %20 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %21, i32 0, i32 %6)
  %23 = extractelement <4 x float> %22, i32 0
  %24 = extractelement <4 x float> %22, i32 1
  %25 = extractelement <4 x float> %22, i32 2
  %26 = extractelement <4 x float> %22, i32 3
  %27 = fmul float %25, %12
  %28 = fadd float %27, %14
  %29 = fmul float %26, %13
  %30 = fadd float %29, %15
  %31 = fmul float %25, %16
  %32 = fadd float %31, %18
  %33 = fmul float %26, %17
  %34 = fadd float %33, %19
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %28, float %30, float %32, float %34)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %23, float %24, float 0.000000e+00, float 1.000000e+00)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg6

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%23](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%11](align=8)(tbaa=!"const")
	S_WAITCNT 112
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 7; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR4<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 5; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR3, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 6; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 4; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR2, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 3; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR3, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 0; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR8<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR2, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 32, 0, 0, 0, %VGPR7<kill>, %VGPR6<kill>, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>
	S_WAITCNT 1807
	%VGPR4<def> = V_MOV_B32_e32 1.000000e+00, %EXEC<imp-use>
	%VGPR5<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR1, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_LOAD_DWORDX4 s[4:7], s[6:7], 0               ; C0820700
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	BUFFER_LOAD_FORMAT_XYZW v[0:3], s[4:7][v0] + 0 ; E00C2000 80010000
	S_LOAD_DWORDX4 s[0:3], s[0:1], 0               ; C0800100
	S_WAITCNT vmcnt(0) lgkmcnt(0)                  ; BF8C0070
	S_BUFFER_LOAD_DWORD s4, s[0:3], 7              ; C2020107
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v4, s4                           ; 7E080204
	S_BUFFER_LOAD_DWORD s4, s[0:3], 5              ; C2020105
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v5, s4                           ; 7E0A0204
	V_MAD_F32 v4, v3, v5, v4, 0, 0, 0, 0           ; D2820004 04120B03
	S_BUFFER_LOAD_DWORD s4, s[0:3], 6              ; C2020106
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v5, s4                           ; 7E0A0204
	S_BUFFER_LOAD_DWORD s4, s[0:3], 4              ; C2020104
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v6, s4                           ; 7E0C0204
	V_MAD_F32 v5, v2, v6, v5, 0, 0, 0, 0           ; D2820005 04160D02
	S_BUFFER_LOAD_DWORD s4, s[0:3], 3              ; C2020103
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v6, s4                           ; 7E0C0204
	S_BUFFER_LOAD_DWORD s4, s[0:3], 1              ; C2020101
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v7, s4                           ; 7E0E0204
	V_MAD_F32 v6, v3, v7, v6, 0, 0, 0, 0           ; D2820006 041A0F03
	S_BUFFER_LOAD_DWORD s4, s[0:3], 2              ; C2020102
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v7, s4                           ; 7E0E0204
	S_BUFFER_LOAD_DWORD s0, s[0:3], 0              ; C2000100
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v8, s0                           ; 7E100200
	V_MAD_F32 v7, v2, v8, v7, 0, 0, 0, 0           ; D2820007 041E1102
	EXP 15, 32, 0, 0, 0, v7, v6, v5, v4            ; F800020F 04050607
	S_WAITCNT expcnt(0)                            ; BF8C070F
	V_MOV_B32_e32 v4, 1.000000e+00                 ; 7E0802F2
	V_MOV_B32_e32 v5, 0.000000e+00                 ; 7E0A0280
	EXP 15, 12, 0, 1, 0, v0, v1, v5, v4            ; F80008CF 04050100
	S_ENDPGM                                       ; BF810000

FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL CONST[0..3]
DCL TEMP[0..22], LOCAL
IMM[0] FLT32 {65504.0000,     1.0000,     2.0000,     7.0000}
IMM[1] FLT32 {    1.4427,     0.0000,     0.0000,     0.0000}
  0: MOV TEMP[0], CONST[0]
  1: MOV TEMP[1], CONST[1]
  2: MOV TEMP[2].x, CONST[1].xxxx
  3: MOV TEMP[3].xy, IN[0].xyyy
  4: TEX TEMP[3], TEMP[3], SAMP[0], 2D
  5: MIN TEMP[3], TEMP[3], IMM[0].xxxx
  6: MOV TEMP[4].xy, IMM[0].yzyy
  7: MOV TEMP[5].xy, IN[0].xyxx
  8: BGNLOOP :0
  9:   FSGE TEMP[6].x, TEMP[4].xxxx, IMM[0].wwww
 10:   UIF TEMP[6].xxxx :0
 11:     BRK
 12:   ENDIF
 13:   MUL TEMP[7].xy, TEMP[4].xyyy, TEMP[4].xyyy
 14:   MUL TEMP[8].xy, TEMP[7].xyyy, TEMP[2].xxxx
 15:   MUL TEMP[9].xy, TEMP[8].xyyy, IMM[1].xxxx
 16:   EX2 TEMP[10].x, TEMP[9].xxxx
 17:   EX2 TEMP[10].y, TEMP[9].yyyy
 18:   ADD TEMP[11].x, TEMP[10].xxxx, TEMP[10].yyyy
 19:   RCP TEMP[12].x, TEMP[11].xxxx
 20:   MUL TEMP[13].x, TEMP[10].yyyy, TEMP[12].xxxx
 21:   ADD TEMP[14].x, TEMP[13].xxxx, TEMP[4].xxxx
 22:   MOV TEMP[15].xy, TEMP[14].xxxx
 23:   MOV TEMP[15].zw, -TEMP[14].xxxx
 24:   MAD TEMP[16], TEMP[0].xyxy, TEMP[15], TEMP[5].xyxy
 25:   MOV TEMP[17].xy, TEMP[16].xyyy
 26:   TEX TEMP[18], TEMP[17], SAMP[0], 2D
 27:   MOV TEMP[19].xy, TEMP[16].zwww
 28:   TEX TEMP[20], TEMP[19], SAMP[0], 2D
 29:   ADD TEMP[21], TEMP[18], TEMP[20]
 30:   MIN TEMP[22], TEMP[21], IMM[0].xxxx
 31:   MAD TEMP[3], TEMP[22], TEMP[11].xxxx, TEMP[3]
 32:   ADD TEMP[4].xy, TEMP[4].xyyy, IMM[0].zzzz
 33: ENDLOOP :0
 34: MUL TEMP[0], TEMP[3], TEMP[1].yyyy
 35: MOV OUT[0], TEMP[0]
 36: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %21 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
  %22 = load <16 x i8> addrspace(2)* %21, !tbaa !0
  %23 = call float @llvm.SI.load.const(<16 x i8> %22, i32 0)
  %24 = call float @llvm.SI.load.const(<16 x i8> %22, i32 4)
  %25 = call float @llvm.SI.load.const(<16 x i8> %22, i32 16)
  %26 = call float @llvm.SI.load.const(<16 x i8> %22, i32 20)
  %27 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0
  %28 = load <32 x i8> addrspace(2)* %27, !tbaa !0
  %29 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0
  %30 = load <16 x i8> addrspace(2)* %29, !tbaa !0
  %31 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %4, <2 x i32> %6)
  %32 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %4, <2 x i32> %6)
  %33 = bitcast float %31 to i32
  %34 = bitcast float %32 to i32
  %35 = insertelement <2 x i32> undef, i32 %33, i32 0
  %36 = insertelement <2 x i32> %35, i32 %34, i32 1
  %37 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %36, <32 x i8> %28, <16 x i8> %30, i32 2)
  %38 = extractelement <4 x float> %37, i32 0
  %39 = extractelement <4 x float> %37, i32 1
  %40 = extractelement <4 x float> %37, i32 2
  %41 = extractelement <4 x float> %37, i32 3
  %42 = fcmp uge float %38, 6.550400e+04
  %43 = select i1 %42, float 6.550400e+04, float %38
  %44 = fcmp uge float %39, 6.550400e+04
  %45 = select i1 %44, float 6.550400e+04, float %39
  %46 = fcmp uge float %40, 6.550400e+04
  %47 = select i1 %46, float 6.550400e+04, float %40
  %48 = fcmp uge float %41, 6.550400e+04
  %49 = select i1 %48, float 6.550400e+04, float %41
  br label %LOOP

LOOP:                                             ; preds = %ENDIF, %main_body
  %temp17.0 = phi float [ 2.000000e+00, %main_body ], [ %124, %ENDIF ]
  %temp16.0 = phi float [ 1.000000e+00, %main_body ], [ %123, %ENDIF ]
  %temp15.0 = phi float [ %49, %main_body ], [ %122, %ENDIF ]
  %temp14.0 = phi float [ %47, %main_body ], [ %120, %ENDIF ]
  %temp13.0 = phi float [ %45, %main_body ], [ %118, %ENDIF ]
  %temp12.0 = phi float [ %43, %main_body ], [ %116, %ENDIF ]
  %50 = fcmp oge float %temp16.0, 7.000000e+00
  %51 = sext i1 %50 to i32
  %52 = bitcast i32 %51 to float
  %53 = bitcast float %52 to i32
  %54 = icmp ne i32 %53, 0
  br i1 %54, label %IF, label %ENDIF

IF:                                               ; preds = %LOOP
  %55 = fmul float %temp12.0, %26
  %56 = fmul float %temp13.0, %26
  %57 = fmul float %temp14.0, %26
  %58 = fmul float %temp15.0, %26
  %59 = call i32 @llvm.SI.packf16(float %55, float %56)
  %60 = bitcast i32 %59 to float
  %61 = call i32 @llvm.SI.packf16(float %57, float %58)
  %62 = bitcast i32 %61 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %60, float %62, float %60, float %62)
  ret void

ENDIF:                                            ; preds = %LOOP
  %63 = fmul float %temp16.0, %temp16.0
  %64 = fmul float %temp17.0, %temp17.0
  %65 = fmul float %63, %25
  %66 = fmul float %64, %25
  %67 = fmul float %65, 0x3FF7154760000000
  %68 = fmul float %66, 0x3FF7154760000000
  %69 = call float @llvm.AMDIL.exp.(float %67)
  %70 = call float @llvm.AMDIL.exp.(float %68)
  %71 = fadd float %69, %70
  %72 = fdiv float 1.000000e+00, %71
  %73 = fmul float %70, %72
  %74 = fadd float %73, %temp16.0
  %75 = fsub float -0.000000e+00, %74
  %76 = fsub float -0.000000e+00, %74
  %77 = fmul float %23, %74
  %78 = fadd float %77, %31
  %79 = fmul float %24, %74
  %80 = fadd float %79, %32
  %81 = fmul float %23, %75
  %82 = fadd float %81, %31
  %83 = fmul float %24, %76
  %84 = fadd float %83, %32
  %85 = bitcast float %78 to i32
  %86 = bitcast float %80 to i32
  %87 = insertelement <2 x i32> undef, i32 %85, i32 0
  %88 = insertelement <2 x i32> %87, i32 %86, i32 1
  %89 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %88, <32 x i8> %28, <16 x i8> %30, i32 2)
  %90 = extractelement <4 x float> %89, i32 0
  %91 = extractelement <4 x float> %89, i32 1
  %92 = extractelement <4 x float> %89, i32 2
  %93 = extractelement <4 x float> %89, i32 3
  %94 = bitcast float %82 to i32
  %95 = bitcast float %84 to i32
  %96 = insertelement <2 x i32> undef, i32 %94, i32 0
  %97 = insertelement <2 x i32> %96, i32 %95, i32 1
  %98 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %97, <32 x i8> %28, <16 x i8> %30, i32 2)
  %99 = extractelement <4 x float> %98, i32 0
  %100 = extractelement <4 x float> %98, i32 1
  %101 = extractelement <4 x float> %98, i32 2
  %102 = extractelement <4 x float> %98, i32 3
  %103 = fadd float %90, %99
  %104 = fadd float %91, %100
  %105 = fadd float %92, %101
  %106 = fadd float %93, %102
  %107 = fcmp uge float %103, 6.550400e+04
  %108 = select i1 %107, float 6.550400e+04, float %103
  %109 = fcmp uge float %104, 6.550400e+04
  %110 = select i1 %109, float 6.550400e+04, float %104
  %111 = fcmp uge float %105, 6.550400e+04
  %112 = select i1 %111, float 6.550400e+04, float %105
  %113 = fcmp uge float %106, 6.550400e+04
  %114 = select i1 %113, float 6.550400e+04, float %106
  %115 = fmul float %108, %71
  %116 = fadd float %115, %temp12.0
  %117 = fmul float %110, %71
  %118 = fadd float %117, %temp13.0
  %119 = fmul float %112, %71
  %120 = fadd float %119, %temp14.0
  %121 = fmul float %114, %71
  %122 = fadd float %121, %temp15.0
  %123 = fadd float %temp16.0, 2.000000e+00
  %124 = fadd float %temp17.0, 2.000000e+00
  br label %LOOP
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.exp.(float) #2

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg33, %SGPR2_SGPR3 in %vreg34, %SGPR4_SGPR5 in %vreg35, %SGPR7 in %vreg37, %VGPR0 in %vreg38, %VGPR1 in %vreg39

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR7 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR7
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-def>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%32](align=8)(tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%29](tbaa=!"const")
	S_WAITCNT 127
	%VGPR11_VGPR12_VGPR13_VGPR14<def> = IMAGE_SAMPLE_V4_V2 15, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	S_WAITCNT 1904
	%SGPR2_SGPR3<def> = V_CMP_U_F32_e64 %VGPR14, %VGPR14, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MOV_B32_e32 6.550400e+04, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_GE_F32_e64 %VGPR14, %VGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_OR_B64 %SGPR4_SGPR5<kill>, %SGPR2_SGPR3<kill>
	%VGPR6<def> = V_CNDMASK_B32_e64 %VGPR14, %VGPR0, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_U_F32_e64 %VGPR13, %VGPR13, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_GE_F32_e64 %VGPR13, %VGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_OR_B64 %SGPR4_SGPR5<kill>, %SGPR2_SGPR3<kill>
	%VGPR9<def> = V_CNDMASK_B32_e64 %VGPR13, %VGPR0, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_U_F32_e64 %VGPR12, %VGPR12, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_GE_F32_e64 %VGPR12, %VGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_OR_B64 %SGPR4_SGPR5<kill>, %SGPR2_SGPR3<kill>
	%VGPR10<def> = V_CNDMASK_B32_e64 %VGPR12, %VGPR0, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_U_F32_e64 %VGPR11, %VGPR11, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_GE_F32_e64 %VGPR11, %VGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_OR_B64 %SGPR4_SGPR5<kill>, %SGPR2_SGPR3<kill>
	%VGPR11<def> = V_CNDMASK_B32_e64 %VGPR11, %VGPR0<kill>, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR11_VGPR12_VGPR13_VGPR14<imp-use,kill>
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%22](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR4_SGPR5_SGPR6_SGPR7, 5; mem:LD4[<unknown>]
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR4_SGPR5_SGPR6_SGPR7, 4; mem:LD4[<unknown>]
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR4_SGPR5_SGPR6_SGPR7, 1; mem:LD4[<unknown>]
	%SGPR3<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR4_SGPR5_SGPR6_SGPR7<kill>, 0; mem:LD4[<unknown>]
	%VGPR0<def> = V_MOV_B32_e32 1.000000e+00, %EXEC<imp-use>
	%VGPR1<def> = V_MOV_B32_e32 2.000000e+00, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = S_MOV_B64 0
	S_WAITCNT 127
    Successors according to CFG: BB#1

BB#1: derived from LLVM BB %LOOP
    Live Ins: %SGPR3 %SGPR2 %SGPR1 %SGPR0 %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR2_VGPR3 %SGPR4_SGPR5 %VGPR1 %VGPR0 %VGPR6 %VGPR9 %VGPR10 %VGPR11
    Predecessors according to CFG: BB#0 BB#2
	%VGPR4<def> = V_MOV_B32_e32 %VGPR11<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MOV_B32_e32 %VGPR10<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MOV_B32_e32 %VGPR9<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_MOV_B32_e32 %VGPR6<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MOV_B32_e32 7.000000e+00, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %VGPR0, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_CNDMASK_B32_e64 0, -1, %SGPR6_SGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_EQ_I32_e64 %VGPR6<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR11<def> = IMPLICIT_DEF
	%VGPR10<def> = IMPLICIT_DEF
	%VGPR9<def> = IMPLICIT_DEF
	%VGPR6<def> = IMPLICIT_DEF
	%SGPR6_SGPR7<def> = S_AND_SAVEEXEC_B64 %SGPR6_SGPR7, %EXEC<imp-def>, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = S_XOR_B64 %EXEC, %SGPR6_SGPR7
	S_CBRANCH_EXECZ <BB#2>, %EXEC
    Successors according to CFG: BB#4(62) BB#2(62)

BB#4: derived from LLVM BB %ENDIF
    Live Ins: %SGPR3 %SGPR2 %SGPR1 %SGPR0 %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR8 %VGPR7 %VGPR5 %VGPR4 %VGPR2_VGPR3 %SGPR6_SGPR7 %SGPR4_SGPR5 %VGPR1 %VGPR0
    Predecessors according to CFG: BB#1
	%VGPR6<def> = V_MUL_F32_e64 %VGPR1, %VGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %SGPR1, %VGPR6<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 1.442695e+00, %VGPR6<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_EXP_F32_e32 %VGPR6<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_MUL_F32_e64 %VGPR0, %VGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_MUL_F32_e32 %SGPR1, %VGPR9<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_MUL_F32_e32 1.442695e+00, %VGPR9<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_EXP_F32_e32 %VGPR9<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_ADD_F32_e32 %VGPR9<kill>, %VGPR6, %EXEC<imp-use>
	%VGPR9<def> = V_RCP_F32_e32 %VGPR11, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR6<kill>, %VGPR9<kill>, %VGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR10<def> = V_MAD_F32 %SGPR2, %VGPR6, %VGPR3, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR9_VGPR10<imp-def>
	%VGPR9<def> = V_MAD_F32 %SGPR3, %VGPR6, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR9_VGPR10<imp-use,kill>, %VGPR9_VGPR10<imp-def>
	%VGPR12_VGPR13_VGPR14_VGPR15<def> = IMAGE_SAMPLE_V4_V2 15, 0, 0, 0, 0, 0, 0, 0, %VGPR9_VGPR10<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	%VGPR9<def> = V_MUL_F32_e32 %SGPR2, %VGPR6, %EXEC<imp-use>
	%VGPR10<def> = V_SUB_F32_e32 %VGPR3, %VGPR9<kill>, %EXEC<imp-use>, %VGPR9_VGPR10<imp-def>
	%VGPR6<def> = V_MUL_F32_e32 %SGPR3, %VGPR6<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_SUB_F32_e32 %VGPR2, %VGPR6<kill>, %EXEC<imp-use>, %VGPR9_VGPR10<imp-use,kill>, %VGPR9_VGPR10<imp-def>
	%VGPR16_VGPR17_VGPR18_VGPR19<def> = IMAGE_SAMPLE_V4_V2 15, 0, 0, 0, 0, 0, 0, 0, %VGPR9_VGPR10<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	S_WAITCNT 1792
	%VGPR6<def> = V_ADD_F32_e32 %VGPR15, %VGPR19, %EXEC<imp-use>
	%VGPR20<def> = V_MOV_B32_e32 6.550400e+04, %EXEC<imp-use>
	%SGPR20_SGPR21<def> = V_CMP_GE_F32_e64 %VGPR6, %VGPR20, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR22_SGPR23<def> = V_CMP_U_F32_e64 %VGPR6, %VGPR6, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR20_SGPR21<def> = S_OR_B64 %SGPR20_SGPR21<kill>, %SGPR22_SGPR23<kill>
	%VGPR6<def> = V_CNDMASK_B32_e64 %VGPR6<kill>, %VGPR20, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR6<kill>, %VGPR11, %VGPR8, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_ADD_F32_e32 %VGPR14, %VGPR18, %EXEC<imp-use>
	%SGPR20_SGPR21<def> = V_CMP_GE_F32_e64 %VGPR9, %VGPR20, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR22_SGPR23<def> = V_CMP_U_F32_e64 %VGPR9, %VGPR9, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR20_SGPR21<def> = S_OR_B64 %SGPR20_SGPR21<kill>, %SGPR22_SGPR23<kill>
	%VGPR9<def> = V_CNDMASK_B32_e64 %VGPR9<kill>, %VGPR20, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_MAD_F32 %VGPR9<kill>, %VGPR11, %VGPR7, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR10<def> = V_ADD_F32_e32 %VGPR13, %VGPR17, %EXEC<imp-use>
	%SGPR20_SGPR21<def> = V_CMP_GE_F32_e64 %VGPR10, %VGPR20, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR22_SGPR23<def> = V_CMP_U_F32_e64 %VGPR10, %VGPR10, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR20_SGPR21<def> = S_OR_B64 %SGPR20_SGPR21<kill>, %SGPR22_SGPR23<kill>
	%VGPR10<def> = V_CNDMASK_B32_e64 %VGPR10<kill>, %VGPR20, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR10<def> = V_MAD_F32 %VGPR10<kill>, %VGPR11, %VGPR5, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR12<def> = V_ADD_F32_e32 %VGPR12, %VGPR16, %EXEC<imp-use>, %VGPR16_VGPR17_VGPR18_VGPR19<imp-use,kill>, %VGPR12_VGPR13_VGPR14_VGPR15<imp-use,kill>
	%SGPR20_SGPR21<def> = V_CMP_GE_F32_e64 %VGPR12, %VGPR20, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR22_SGPR23<def> = V_CMP_U_F32_e64 %VGPR12, %VGPR12, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR20_SGPR21<def> = S_OR_B64 %SGPR20_SGPR21<kill>, %SGPR22_SGPR23<kill>
	%VGPR12<def> = V_CNDMASK_B32_e64 %VGPR12<kill>, %VGPR20<kill>, %SGPR20_SGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR11<def> = V_MAD_F32 %VGPR12<kill>, %VGPR11<kill>, %VGPR4, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_ADD_F32_e64 %VGPR1<kill>, 2.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_F32_e64 %VGPR0<kill>, 2.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
    Successors according to CFG: BB#2

BB#2: derived from LLVM BB %Flow
    Live Ins: %SGPR3 %SGPR2 %SGPR1 %SGPR0 %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR8 %VGPR7 %VGPR5 %VGPR4 %VGPR2_VGPR3 %SGPR6_SGPR7 %SGPR4_SGPR5 %VGPR1 %VGPR0 %VGPR6 %VGPR9 %VGPR10 %VGPR11
    Predecessors according to CFG: BB#1 BB#4
	%EXEC<def> = S_OR_B64 %EXEC, %SGPR6_SGPR7
	%SGPR4_SGPR5<def> = S_OR_B64 %SGPR6_SGPR7, %SGPR4_SGPR5
	%EXEC<def> = S_ANDN2_B64 %EXEC, %SGPR4_SGPR5
	S_CBRANCH_EXECNZ <BB#1>, %EXEC
    Successors according to CFG: BB#3(4) BB#1(124)

BB#3: derived from LLVM BB %IF
    Live Ins: %SGPR0 %VGPR8 %VGPR7 %VGPR5 %VGPR4 %SGPR4_SGPR5
    Predecessors according to CFG: BB#2
	%EXEC<def> = S_OR_B64 %EXEC, %SGPR4_SGPR5
	%VGPR0<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_MUL_F32_e64 %VGPR8<kill>, %VGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR2<def> = V_MUL_F32_e64 %VGPR7<kill>, %VGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR2<kill>, %VGPR1<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_MUL_F32_e64 %VGPR5<kill>, %VGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_F32_e64 %VGPR4<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0<kill>, %VGPR2<kill>, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR0<kill>, %VGPR1<kill>, %VGPR0, %VGPR1, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_WQM_B64 exec, exec                                                       ; BEFE0A7E
	S_MOV_B32 m0, s7                                                           ; BEFC0307
	V_INTERP_P1_F32 v3, v0, 1, 0, [m0]                                         ; C80C0100
	V_INTERP_P2_F32 v3, [v3], v1, 1, 0, [m0]                                   ; C80D0101
	V_INTERP_P1_F32 v2, v0, 0, 0, [m0]                                         ; C8080000
	V_INTERP_P2_F32 v2, [v2], v1, 0, 0, [m0]                                   ; C8090001
	S_LOAD_DWORDX4 s[8:11], s[2:3], 0                                          ; C0840300
	S_LOAD_DWORDX8 s[12:19], s[4:5], 0                                         ; C0C60500
	S_WAITCNT lgkmcnt(0)                                                       ; BF8C007F
	IMAGE_SAMPLE v[11:14], 15, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[12:19], s[8:11]  ; F0800F00 00430B02
	S_WAITCNT vmcnt(0)                                                         ; BF8C0770
	V_CMP_U_F32_e64 s[2:3], v14, v14, 0, 0, 0, 0                               ; D0100002 02021D0E
	V_MOV_B32_e32 v0, 6.550400e+04                                             ; 7E0002FF 477FE000
	V_CMP_GE_F32_e64 s[4:5], v14, v0, 0, 0, 0, 0                               ; D00C0004 0202010E
	S_OR_B64 s[2:3], s[4:5], s[2:3]                                            ; 88820204
	V_CNDMASK_B32_e64 v6, v14, v0, s[2:3], 0, 0, 0, 0                          ; D2000006 000A010E
	V_CMP_U_F32_e64 s[2:3], v13, v13, 0, 0, 0, 0                               ; D0100002 02021B0D
	V_CMP_GE_F32_e64 s[4:5], v13, v0, 0, 0, 0, 0                               ; D00C0004 0202010D
	S_OR_B64 s[2:3], s[4:5], s[2:3]                                            ; 88820204
	V_CNDMASK_B32_e64 v9, v13, v0, s[2:3], 0, 0, 0, 0                          ; D2000009 000A010D
	V_CMP_U_F32_e64 s[2:3], v12, v12, 0, 0, 0, 0                               ; D0100002 0202190C
	V_CMP_GE_F32_e64 s[4:5], v12, v0, 0, 0, 0, 0                               ; D00C0004 0202010C
	S_OR_B64 s[2:3], s[4:5], s[2:3]                                            ; 88820204
	V_CNDMASK_B32_e64 v10, v12, v0, s[2:3], 0, 0, 0, 0                         ; D200000A 000A010C
	V_CMP_U_F32_e64 s[2:3], v11, v11, 0, 0, 0, 0                               ; D0100002 0202170B
	V_CMP_GE_F32_e64 s[4:5], v11, v0, 0, 0, 0, 0                               ; D00C0004 0202010B
	S_OR_B64 s[2:3], s[4:5], s[2:3]                                            ; 88820204
	V_CNDMASK_B32_e64 v11, v11, v0, s[2:3], 0, 0, 0, 0                         ; D200000B 000A010B
	S_LOAD_DWORDX4 s[4:7], s[0:1], 0                                           ; C0820100
	S_WAITCNT lgkmcnt(0)                                                       ; BF8C007F
	S_BUFFER_LOAD_DWORD s0, s[4:7], 5                                          ; C2000505
	S_BUFFER_LOAD_DWORD s1, s[4:7], 4                                          ; C2008504
	S_BUFFER_LOAD_DWORD s2, s[4:7], 1                                          ; C2010501
	S_BUFFER_LOAD_DWORD s3, s[4:7], 0                                          ; C2018500
	V_MOV_B32_e32 v0, 1.000000e+00                                             ; 7E0002F2
	V_MOV_B32_e32 v1, 2.000000e+00                                             ; 7E0202F4
	S_MOV_B64 s[4:5], 0                                                        ; BE840480
	S_WAITCNT lgkmcnt(0)                                                       ; BF8C007F
	V_MOV_B32_e32 v4, v11                                                      ; 7E08030B
	V_MOV_B32_e32 v5, v10                                                      ; 7E0A030A
	V_MOV_B32_e32 v7, v9                                                       ; 7E0E0309
	V_MOV_B32_e32 v8, v6                                                       ; 7E100306
	V_MOV_B32_e32 v6, 7.000000e+00                                             ; 7E0C02FF 40E00000
	V_CMP_GE_F32_e64 s[6:7], v0, v6, 0, 0, 0, 0                                ; D00C0006 02020D00
	V_CNDMASK_B32_e64 v6, 0, -1, s[6:7], 0, 0, 0, 0                            ; D2000006 00198280
	V_CMP_EQ_I32_e64 s[6:7], v6, 0, 0, 0, 0, 0                                 ; D1040006 02010106
	S_AND_SAVEEXEC_B64 s[6:7], s[6:7]                                          ; BE862406
	S_XOR_B64 s[6:7], exec, s[6:7]                                             ; 8986067E
	S_CBRANCH_EXECZ ";.BB0_2"                                                  ; BF880000
	V_MUL_F32_e64 v6, v1, v1, 0, 0, 0, 0                                       ; D2100006 02020301
	V_MUL_F32_e32 v6, s1, v6                                                   ; 100C0C01
	V_MUL_F32_e32 v6, 1.442695e+00, v6                                         ; 100C0CFF 3FB8AA3B
	V_EXP_F32_e32 v6, v6                                                       ; 7E0C4B06
	V_MUL_F32_e64 v9, v0, v0, 0, 0, 0, 0                                       ; D2100009 02020100
	V_MUL_F32_e32 v9, s1, v9                                                   ; 10121201
	V_MUL_F32_e32 v9, 1.442695e+00, v9                                         ; 101212FF 3FB8AA3B
	V_EXP_F32_e32 v9, v9                                                       ; 7E124B09
	V_ADD_F32_e32 v11, v9, v6                                                  ; 06160D09
	V_RCP_F32_e32 v9, v11                                                      ; 7E12550B
	V_MAD_F32 v6, v6, v9, v0, 0, 0, 0, 0                                       ; D2820006 04021306
	V_MAD_F32 v10, s2, v6, v3, 0, 0, 0, 0                                      ; D282000A 040E0C02
	V_MAD_F32 v9, s3, v6, v2, 0, 0, 0, 0                                       ; D2820009 040A0C03
	IMAGE_SAMPLE v[12:15], 15, 0, 0, 0, 0, 0, 0, 0, v[9:10], s[12:19], s[8:11] ; F0800F00 00430C09
	V_MUL_F32_e32 v9, s2, v6                                                   ; 10120C02
	V_SUB_F32_e32 v10, v3, v9                                                  ; 08141303
	V_MUL_F32_e32 v6, s3, v6                                                   ; 100C0C03
	V_SUB_F32_e32 v9, v2, v6                                                   ; 08120D02
	IMAGE_SAMPLE v[16:19], 15, 0, 0, 0, 0, 0, 0, 0, v[9:10], s[12:19], s[8:11] ; F0800F00 00431009
	S_WAITCNT vmcnt(0) expcnt(0)                                               ; BF8C0700
	V_ADD_F32_e32 v6, v15, v19                                                 ; 060C270F
	V_MOV_B32_e32 v20, 6.550400e+04                                            ; 7E2802FF 477FE000
	V_CMP_GE_F32_e64 s[20:21], v6, v20, 0, 0, 0, 0                             ; D00C0014 02022906
	V_CMP_U_F32_e64 s[22:23], v6, v6, 0, 0, 0, 0                               ; D0100016 02020D06
	S_OR_B64 s[20:21], s[20:21], s[22:23]                                      ; 88941614
	V_CNDMASK_B32_e64 v6, v6, v20, s[20:21], 0, 0, 0, 0                        ; D2000006 00522906
	V_MAD_F32 v6, v6, v11, v8, 0, 0, 0, 0                                      ; D2820006 04221706
	V_ADD_F32_e32 v9, v14, v18                                                 ; 0612250E
	V_CMP_GE_F32_e64 s[20:21], v9, v20, 0, 0, 0, 0                             ; D00C0014 02022909
	V_CMP_U_F32_e64 s[22:23], v9, v9, 0, 0, 0, 0                               ; D0100016 02021309
	S_OR_B64 s[20:21], s[20:21], s[22:23]                                      ; 88941614
	V_CNDMASK_B32_e64 v9, v9, v20, s[20:21], 0, 0, 0, 0                        ; D2000009 00522909
	V_MAD_F32 v9, v9, v11, v7, 0, 0, 0, 0                                      ; D2820009 041E1709
	V_ADD_F32_e32 v10, v13, v17                                                ; 0614230D
	V_CMP_GE_F32_e64 s[20:21], v10, v20, 0, 0, 0, 0                            ; D00C0014 0202290A
	V_CMP_U_F32_e64 s[22:23], v10, v10, 0, 0, 0, 0                             ; D0100016 0202150A
	S_OR_B64 s[20:21], s[20:21], s[22:23]                                      ; 88941614
	V_CNDMASK_B32_e64 v10, v10, v20, s[20:21], 0, 0, 0, 0                      ; D200000A 0052290A
	V_MAD_F32 v10, v10, v11, v5, 0, 0, 0, 0                                    ; D282000A 0416170A
	V_ADD_F32_e32 v12, v12, v16                                                ; 0618210C
	V_CMP_GE_F32_e64 s[20:21], v12, v20, 0, 0, 0, 0                            ; D00C0014 0202290C
	V_CMP_U_F32_e64 s[22:23], v12, v12, 0, 0, 0, 0                             ; D0100016 0202190C
	S_OR_B64 s[20:21], s[20:21], s[22:23]                                      ; 88941614
	V_CNDMASK_B32_e64 v12, v12, v20, s[20:21], 0, 0, 0, 0                      ; D200000C 0052290C
	V_MAD_F32 v11, v12, v11, v4, 0, 0, 0, 0                                    ; D282000B 0412170C
	V_ADD_F32_e64 v1, v1, 2.000000e+00, 0, 0, 0, 0                             ; D2060001 0201E901
	V_ADD_F32_e64 v0, v0, 2.000000e+00, 0, 0, 0, 0                             ; D2060000 0201E900
	S_OR_B64 exec, exec, s[6:7]                                                ; 88FE067E
	S_OR_B64 s[4:5], s[6:7], s[4:5]                                            ; 88840406
	S_ANDN2_B64 exec, exec, s[4:5]                                             ; 8AFE047E
	S_CBRANCH_EXECNZ ";.BB0_1"                                                 ; BF890000
	S_OR_B64 exec, exec, s[4:5]                                                ; 88FE047E
	V_MOV_B32_e32 v0, s0                                                       ; 7E000200
	V_MUL_F32_e64 v1, v8, v0, 0, 0, 0, 0                                       ; D2100001 02020108
	V_MUL_F32_e64 v2, v7, v0, 0, 0, 0, 0                                       ; D2100002 02020107
	V_CVT_PKRTZ_F16_F32_e32 v1, v2, v1                                         ; 5E020302
	V_MUL_F32_e64 v2, v5, v0, 0, 0, 0, 0                                       ; D2100002 02020105
	V_MUL_F32_e64 v0, v4, v0, 0, 0, 0, 0                                       ; D2100000 02020104
	V_CVT_PKRTZ_F16_F32_e32 v0, v0, v2                                         ; 5E000500
	EXP 15, 0, 1, 1, 1, v0, v1, v0, v1                                         ; F8001C0F 01000100
	S_ENDPGM                                                                   ; BF810000

VERT
DCL IN[0]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[19]
DCL CONST[0..1]
DCL TEMP[0..2], LOCAL
IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
  0: MOV TEMP[0].zw, IMM[0].yyxy
  1: MOV TEMP[0].xy, IN[0].xyxx
  2: MAD TEMP[1].xy, IN[0].zwww, CONST[0].xyyy, CONST[0].zwww
  3: MAD TEMP[2].xy, IN[0].zwww, CONST[1].xyyy, CONST[1].zwww
  4: MOV TEMP[1].zw, TEMP[2].yyxy
  5: MOV OUT[1], TEMP[1]
  6: MOV OUT[0], TEMP[0]
  7: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0)
  %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4)
  %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8)
  %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12)
  %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16)
  %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20)
  %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24)
  %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28)
  %20 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %21, i32 0, i32 %6)
  %23 = extractelement <4 x float> %22, i32 0
  %24 = extractelement <4 x float> %22, i32 1
  %25 = extractelement <4 x float> %22, i32 2
  %26 = extractelement <4 x float> %22, i32 3
  %27 = fmul float %25, %12
  %28 = fadd float %27, %14
  %29 = fmul float %26, %13
  %30 = fadd float %29, %15
  %31 = fmul float %25, %16
  %32 = fadd float %31, %18
  %33 = fmul float %26, %17
  %34 = fadd float %33, %19
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %28, float %30, float %32, float %34)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %23, float %24, float 0.000000e+00, float 1.000000e+00)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg6

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%23](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%11](align=8)(tbaa=!"const")
	S_WAITCNT 112
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 7; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR4<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 5; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR3, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 6; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 4; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR2, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 3; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR3, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 0; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR8<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR2, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 32, 0, 0, 0, %VGPR7<kill>, %VGPR6<kill>, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>
	S_WAITCNT 1807
	%VGPR4<def> = V_MOV_B32_e32 1.000000e+00, %EXEC<imp-use>
	%VGPR5<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR1, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_LOAD_DWORDX4 s[4:7], s[6:7], 0               ; C0820700
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	BUFFER_LOAD_FORMAT_XYZW v[0:3], s[4:7][v0] + 0 ; E00C2000 80010000
	S_LOAD_DWORDX4 s[0:3], s[0:1], 0               ; C0800100
	S_WAITCNT vmcnt(0) lgkmcnt(0)                  ; BF8C0070
	S_BUFFER_LOAD_DWORD s4, s[0:3], 7              ; C2020107
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v4, s4                           ; 7E080204
	S_BUFFER_LOAD_DWORD s4, s[0:3], 5              ; C2020105
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v5, s4                           ; 7E0A0204
	V_MAD_F32 v4, v3, v5, v4, 0, 0, 0, 0           ; D2820004 04120B03
	S_BUFFER_LOAD_DWORD s4, s[0:3], 6              ; C2020106
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v5, s4                           ; 7E0A0204
	S_BUFFER_LOAD_DWORD s4, s[0:3], 4              ; C2020104
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v6, s4                           ; 7E0C0204
	V_MAD_F32 v5, v2, v6, v5, 0, 0, 0, 0           ; D2820005 04160D02
	S_BUFFER_LOAD_DWORD s4, s[0:3], 3              ; C2020103
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v6, s4                           ; 7E0C0204
	S_BUFFER_LOAD_DWORD s4, s[0:3], 1              ; C2020101
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v7, s4                           ; 7E0E0204
	V_MAD_F32 v6, v3, v7, v6, 0, 0, 0, 0           ; D2820006 041A0F03
	S_BUFFER_LOAD_DWORD s4, s[0:3], 2              ; C2020102
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v7, s4                           ; 7E0E0204
	S_BUFFER_LOAD_DWORD s0, s[0:3], 0              ; C2000100
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v8, s0                           ; 7E100200
	V_MAD_F32 v7, v2, v8, v7, 0, 0, 0, 0           ; D2820007 041E1102
	EXP 15, 32, 0, 0, 0, v7, v6, v5, v4            ; F800020F 04050607
	S_WAITCNT expcnt(0)                            ; BF8C070F
	V_MOV_B32_e32 v4, 1.000000e+00                 ; 7E0802F2
	V_MOV_B32_e32 v5, 0.000000e+00                 ; 7E0A0280
	EXP 15, 12, 0, 1, 0, v0, v1, v5, v4            ; F80008CF 04050100
	S_ENDPGM                                       ; BF810000

FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL SAMP[1]
DCL SAMP[2]
DCL CONST[0..1]
DCL TEMP[0..4], LOCAL
IMM[0] FLT32 {    0.0000, 65504.0000,     0.5000,    12.9200}
IMM[1] FLT32 {    0.4167,     1.0550,    -0.0550,     0.0031}
IMM[2] FLT32 {    0.2125,     0.7154,     0.0721,     0.0000}
  0: MOV TEMP[0].xy, IN[0].xyyy
  1: TEX TEMP[0], TEMP[0], SAMP[0], 2D
  2: MAX TEMP[0], TEMP[0], IMM[0].xxxx
  3: MIN TEMP[0], TEMP[0], IMM[0].yyyy
  4: MOV TEMP[1].w, TEMP[0].wwww
  5: MUL TEMP[1].xyz, TEMP[0].xyzz, CONST[0].xxxx
  6: MOV TEMP[0].xy, IMM[0].zzzz
  7: TEX TEMP[0].x, TEMP[0], SAMP[1], 2D
  8: MUL TEMP[1].xyz, TEMP[1].xyzz, TEMP[0].xxxx
  9: MOV TEMP[0].xy, IN[0].zwww
 10: TEX TEMP[0].xyz, TEMP[0], SAMP[2], 2D
 11: MAD TEMP[1].xyz, TEMP[0].xyzz, CONST[0].yyyy, TEMP[1].xyzz
 12: MUL TEMP[2].xyz, TEMP[1].xyzz, IMM[0].wwww
 13: POW TEMP[3].x, TEMP[1].xxxx, IMM[1].xxxx
 14: POW TEMP[3].y, TEMP[1].yyyy, IMM[1].xxxx
 15: POW TEMP[3].z, TEMP[1].zzzz, IMM[1].xxxx
 16: MAD TEMP[3].xyz, TEMP[3].xyzz, IMM[1].yyyy, IMM[1].zzzz
 17: FSLT TEMP[4].x, TEMP[1].xxxx, IMM[1].wwww
 18: UIF TEMP[4].xxxx :0
 19:   MOV TEMP[4].x, TEMP[2].xxxx
 20: ELSE :0
 21:   MOV TEMP[4].x, TEMP[3].xxxx
 22: ENDIF
 23: MOV TEMP[0].x, TEMP[4].xxxx
 24: FSLT TEMP[4].x, TEMP[1].yyyy, IMM[1].wwww
 25: UIF TEMP[4].xxxx :0
 26:   MOV TEMP[4].x, TEMP[2].yyyy
 27: ELSE :0
 28:   MOV TEMP[4].x, TEMP[3].yyyy
 29: ENDIF
 30: MOV TEMP[0].y, TEMP[4].xxxx
 31: FSLT TEMP[4].x, TEMP[1].zzzz, IMM[1].wwww
 32: UIF TEMP[4].xxxx :0
 33:   MOV TEMP[2].x, TEMP[2].zzzz
 34: ELSE :0
 35:   MOV TEMP[2].x, TEMP[3].zzzz
 36: ENDIF
 37: MOV TEMP[0].z, TEMP[2].xxxx
 38: MOV_SAT TEMP[1].xyz, TEMP[0].xyzz
 39: DP3 TEMP[0].x, TEMP[1].xyzz, IMM[2].xyzz
 40: LRP TEMP[0].xyz, CONST[1].yyyy, TEMP[1].xyzz, TEMP[0].xxxx
 41: LRP TEMP[1].xyz, CONST[1].zzzz, CONST[1].wwww, TEMP[0].xyzz
 42: MOV_SAT TEMP[1].xyz, TEMP[1].xyzz
 43: MOV OUT[0], TEMP[1]
 44: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %21 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
  %22 = load <16 x i8> addrspace(2)* %21, !tbaa !0
  %23 = call float @llvm.SI.load.const(<16 x i8> %22, i32 0)
  %24 = call float @llvm.SI.load.const(<16 x i8> %22, i32 4)
  %25 = call float @llvm.SI.load.const(<16 x i8> %22, i32 20)
  %26 = call float @llvm.SI.load.const(<16 x i8> %22, i32 24)
  %27 = call float @llvm.SI.load.const(<16 x i8> %22, i32 28)
  %28 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0
  %29 = load <32 x i8> addrspace(2)* %28, !tbaa !0
  %30 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0
  %31 = load <16 x i8> addrspace(2)* %30, !tbaa !0
  %32 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 1
  %33 = load <32 x i8> addrspace(2)* %32, !tbaa !0
  %34 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 1
  %35 = load <16 x i8> addrspace(2)* %34, !tbaa !0
  %36 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 2
  %37 = load <32 x i8> addrspace(2)* %36, !tbaa !0
  %38 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 2
  %39 = load <16 x i8> addrspace(2)* %38, !tbaa !0
  %40 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %4, <2 x i32> %6)
  %41 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %4, <2 x i32> %6)
  %42 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %4, <2 x i32> %6)
  %43 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %4, <2 x i32> %6)
  %44 = bitcast float %40 to i32
  %45 = bitcast float %41 to i32
  %46 = insertelement <2 x i32> undef, i32 %44, i32 0
  %47 = insertelement <2 x i32> %46, i32 %45, i32 1
  %48 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %47, <32 x i8> %29, <16 x i8> %31, i32 2)
  %49 = extractelement <4 x float> %48, i32 0
  %50 = extractelement <4 x float> %48, i32 1
  %51 = extractelement <4 x float> %48, i32 2
  %52 = extractelement <4 x float> %48, i32 3
  %53 = fcmp uge float %49, 0.000000e+00
  %54 = select i1 %53, float %49, float 0.000000e+00
  %55 = fcmp uge float %50, 0.000000e+00
  %56 = select i1 %55, float %50, float 0.000000e+00
  %57 = fcmp uge float %51, 0.000000e+00
  %58 = select i1 %57, float %51, float 0.000000e+00
  %59 = fcmp uge float %52, 0.000000e+00
  %60 = select i1 %59, float %52, float 0.000000e+00
  %61 = fcmp uge float %54, 6.550400e+04
  %62 = select i1 %61, float 6.550400e+04, float %54
  %63 = fcmp uge float %56, 6.550400e+04
  %64 = select i1 %63, float 6.550400e+04, float %56
  %65 = fcmp uge float %58, 6.550400e+04
  %66 = select i1 %65, float 6.550400e+04, float %58
  %67 = fcmp uge float %60, 6.550400e+04
  %68 = select i1 %67, float 6.550400e+04, float %60
  %69 = fmul float %62, %23
  %70 = fmul float %64, %23
  %71 = fmul float %66, %23
  %72 = bitcast float 5.000000e-01 to i32
  %73 = bitcast float 5.000000e-01 to i32
  %74 = insertelement <2 x i32> undef, i32 %72, i32 0
  %75 = insertelement <2 x i32> %74, i32 %73, i32 1
  %76 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %75, <32 x i8> %33, <16 x i8> %35, i32 2)
  %77 = extractelement <4 x float> %76, i32 0
  %78 = fmul float %69, %77
  %79 = fmul float %70, %77
  %80 = fmul float %71, %77
  %81 = bitcast float %42 to i32
  %82 = bitcast float %43 to i32
  %83 = insertelement <2 x i32> undef, i32 %81, i32 0
  %84 = insertelement <2 x i32> %83, i32 %82, i32 1
  %85 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %84, <32 x i8> %37, <16 x i8> %39, i32 2)
  %86 = extractelement <4 x float> %85, i32 0
  %87 = extractelement <4 x float> %85, i32 1
  %88 = extractelement <4 x float> %85, i32 2
  %89 = fmul float %86, %24
  %90 = fadd float %89, %78
  %91 = fmul float %87, %24
  %92 = fadd float %91, %79
  %93 = fmul float %88, %24
  %94 = fadd float %93, %80
  %95 = fmul float %90, 0x4029D70A40000000
  %96 = fmul float %92, 0x4029D70A40000000
  %97 = fmul float %94, 0x4029D70A40000000
  %98 = call float @llvm.pow.f32(float %90, float 0x3FDAAAAAA0000000)
  %99 = call float @llvm.pow.f32(float %92, float 0x3FDAAAAAA0000000)
  %100 = call float @llvm.pow.f32(float %94, float 0x3FDAAAAAA0000000)
  %101 = fmul float %98, 0x3FF0E147A0000000
  %102 = fadd float %101, 0xBFAC28F5C0000000
  %103 = fmul float %99, 0x3FF0E147A0000000
  %104 = fadd float %103, 0xBFAC28F5C0000000
  %105 = fmul float %100, 0x3FF0E147A0000000
  %106 = fadd float %105, 0xBFAC28F5C0000000
  %107 = fcmp olt float %90, 0x3F69A5C380000000
  %108 = sext i1 %107 to i32
  %109 = bitcast i32 %108 to float
  %110 = bitcast float %109 to i32
  %111 = icmp ne i32 %110, 0
  %. = select i1 %111, float %95, float %102
  %112 = fcmp olt float %92, 0x3F69A5C380000000
  %113 = sext i1 %112 to i32
  %114 = bitcast i32 %113 to float
  %115 = bitcast float %114 to i32
  %116 = icmp ne i32 %115, 0
  %temp16.1 = select i1 %116, float %96, float %104
  %117 = fcmp olt float %94, 0x3F69A5C380000000
  %118 = sext i1 %117 to i32
  %119 = bitcast i32 %118 to float
  %120 = bitcast float %119 to i32
  %121 = icmp ne i32 %120, 0
  %.26 = select i1 %121, float %97, float %106
  %122 = call float @llvm.AMDIL.clamp.(float %., float 0.000000e+00, float 1.000000e+00)
  %123 = call float @llvm.AMDIL.clamp.(float %temp16.1, float 0.000000e+00, float 1.000000e+00)
  %124 = call float @llvm.AMDIL.clamp.(float %.26, float 0.000000e+00, float 1.000000e+00)
  %125 = fmul float %122, 0x3FCB333340000000
  %126 = fmul float %123, 0x3FE6E48E80000000
  %127 = fadd float %126, %125
  %128 = fmul float %124, 0x3FB2752540000000
  %129 = fadd float %127, %128
  %130 = call float @llvm.AMDGPU.lrp(float %25, float %122, float %129)
  %131 = call float @llvm.AMDGPU.lrp(float %25, float %123, float %129)
  %132 = call float @llvm.AMDGPU.lrp(float %25, float %124, float %129)
  %133 = call float @llvm.AMDGPU.lrp(float %26, float %27, float %130)
  %134 = call float @llvm.AMDGPU.lrp(float %26, float %27, float %131)
  %135 = call float @llvm.AMDGPU.lrp(float %26, float %27, float %132)
  %136 = call float @llvm.AMDIL.clamp.(float %133, float 0.000000e+00, float 1.000000e+00)
  %137 = call float @llvm.AMDIL.clamp.(float %134, float 0.000000e+00, float 1.000000e+00)
  %138 = call float @llvm.AMDIL.clamp.(float %135, float 0.000000e+00, float 1.000000e+00)
  %139 = call i32 @llvm.SI.packf16(float %136, float %137)
  %140 = bitcast i32 %139 to float
  %141 = call i32 @llvm.SI.packf16(float %138, float %68)
  %142 = bitcast i32 %141 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %140, float %142, float %140, float %142)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: nounwind readonly
declare float @llvm.pow.f32(float, float) #2

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #3

; Function Attrs: readnone
declare float @llvm.AMDGPU.lrp(float, float, float) #3

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { nounwind readonly }
attributes #3 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR7 in %vreg4, %VGPR0 in %vreg5, %VGPR1 in %vreg6

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR7 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR7
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-def>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 0; mem:LD16[%33](align=8)(tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 0; mem:LD32[%30](tbaa=!"const")
	S_WAITCNT 127
	%VGPR2_VGPR3_VGPR4_VGPR5<def> = IMAGE_SAMPLE_V4_V2 15, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%SGPR8_SGPR9<def> = V_CMP_U_F32_e64 %VGPR3, %VGPR3, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR10_SGPR11<def> = V_CMP_GE_F32_e64 %VGPR3, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8_SGPR9<def> = S_OR_B64 %SGPR10_SGPR11<kill>, %SGPR8_SGPR9<kill>
	%VGPR6<def> = V_CNDMASK_B32_e64 0.000000e+00, %VGPR3, %SGPR8_SGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_MOV_B32_e32 6.550400e+04, %EXEC<imp-use>
	%SGPR8_SGPR9<def> = V_CMP_GE_F32_e64 %VGPR6, %VGPR7, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR10_SGPR11<def> = V_CMP_U_F32_e64 %VGPR6, %VGPR6, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8_SGPR9<def> = S_OR_B64 %SGPR8_SGPR9<kill>, %SGPR10_SGPR11<kill>
	%VGPR6<def> = V_CNDMASK_B32_e64 %VGPR6<kill>, %VGPR7, %SGPR8_SGPR9<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%22](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 0; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR0, %VGPR6<kill>, %EXEC<imp-use>
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 4; mem:LD16[%39](align=8)(tbaa=!"const")
	%SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 8; mem:LD32[%36](tbaa=!"const")
	%VGPR8<def> = V_MOV_B32_e32 1056964608, %EXEC<imp-use>, %VGPR8_VGPR9<imp-def>
	%VGPR9<def> = V_MOV_B32_e32 %VGPR8, %EXEC<imp-use>, %VGPR8_VGPR9<imp-def>
	S_WAITCNT 127
	%VGPR8<def> = IMAGE_SAMPLE_V1_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR8_VGPR9<kill>, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23<kill>, %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR6<def> = V_MUL_F32_e32 %VGPR6<kill>, %VGPR8, %EXEC<imp-use>
	%VGPR10<def> = V_INTERP_P1_F32 %VGPR0, 3, 0, %M0<kill>, %EXEC<imp-use>, %VGPR9_VGPR10<imp-def>
	%VGPR10<def,tied1> = V_INTERP_P2_F32 %VGPR10<tied0>, %VGPR1, 3, 0, %M0<kill>, %EXEC<imp-use>, %VGPR9_VGPR10<imp-use,kill>, %VGPR9_VGPR10<imp-def>
	%VGPR9<def> = V_INTERP_P1_F32 %VGPR0, 2, 0, %M0<kill>, %EXEC<imp-use>, %VGPR9_VGPR10<imp-use,kill>, %VGPR9_VGPR10<imp-def>
	%VGPR9<def,tied1> = V_INTERP_P2_F32 %VGPR9<tied0>, %VGPR1, 2, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR9_VGPR10<imp-use,kill>, %VGPR9_VGPR10<imp-def>
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 8; mem:LD16[%45](align=8)(tbaa=!"const")
	%SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 16; mem:LD32[%42](tbaa=!"const")
	S_WAITCNT 127
	%VGPR9_VGPR10_VGPR11<def> = IMAGE_SAMPLE_V3_V2 7, 0, 0, 0, 0, 0, 0, 0, %VGPR9_VGPR10<kill>, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23<kill>, %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 1; mem:LD4[<unknown>]
	S_WAITCNT 112
	%VGPR0<def> = V_MOV_B32_e32 %SGPR1<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_MAD_F32 %VGPR10, %VGPR0, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_LOG_F32_e32 %VGPR1, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_LEGACY_F32_e32 4.166667e-01, %VGPR6<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_EXP_F32_e32 %VGPR6<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_MOV_B32_e32 -5.500000e-02, %EXEC<imp-use>
	%VGPR13<def> = V_MOV_B32_e32 1.055000e+00, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR6<kill>, %VGPR13, %VGPR12, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR14<def> = V_MOV_B32_e32 3.130800e-03, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_LT_F32_e64 %VGPR1, %VGPR14, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_MUL_F32_e32 1.292000e+01, %VGPR1<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_CNDMASK_B32_e64 %VGPR6<kill>, %VGPR1<kill>, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_ADD_F32_e64 0, %VGPR1<kill>, 0, 1, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_U_F32_e64 %VGPR2, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_GE_F32_e64 %VGPR2, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_OR_B64 %SGPR4_SGPR5<kill>, %SGPR2_SGPR3<kill>
	%VGPR6<def> = V_CNDMASK_B32_e64 0.000000e+00, %VGPR2, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR6, %VGPR7, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_U_F32_e64 %VGPR6, %VGPR6, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_OR_B64 %SGPR2_SGPR3<kill>, %SGPR4_SGPR5<kill>
	%VGPR6<def> = V_CNDMASK_B32_e64 %VGPR6<kill>, %VGPR7, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %SGPR0, %VGPR6<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %VGPR6<kill>, %VGPR8, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR9, %VGPR0, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR15<def> = V_LOG_F32_e32 %VGPR6, %EXEC<imp-use>
	%VGPR15<def> = V_MUL_LEGACY_F32_e32 4.166667e-01, %VGPR15<kill>, %EXEC<imp-use>
	%VGPR15<def> = V_EXP_F32_e32 %VGPR15<kill>, %EXEC<imp-use>
	%VGPR15<def> = V_MAD_F32 %VGPR15<kill>, %VGPR13, %VGPR12, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_LT_F32_e64 %VGPR6, %VGPR14, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 1.292000e+01, %VGPR6<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_CNDMASK_B32_e64 %VGPR15<kill>, %VGPR6<kill>, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_ADD_F32_e64 0, %VGPR6<kill>, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR15<def> = V_MUL_F32_e32 2.125000e-01, %VGPR6, %EXEC<imp-use>
	%VGPR16<def> = V_MOV_B32_e32 7.154000e-01, %EXEC<imp-use>
	%VGPR15<def> = V_MAD_F32 %VGPR1, %VGPR16<kill>, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_U_F32_e64 %VGPR4, %VGPR4, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_GE_F32_e64 %VGPR4, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_OR_B64 %SGPR4_SGPR5<kill>, %SGPR2_SGPR3<kill>
	%VGPR16<def> = V_CNDMASK_B32_e64 0.000000e+00, %VGPR4, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR16, %VGPR7, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_U_F32_e64 %VGPR16, %VGPR16, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_OR_B64 %SGPR2_SGPR3<kill>, %SGPR4_SGPR5<kill>
	%VGPR16<def> = V_CNDMASK_B32_e64 %VGPR16<kill>, %VGPR7, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR16<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR16<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_F32_e32 %VGPR16<kill>, %VGPR8<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR11, %VGPR0<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR9_VGPR10_VGPR11<imp-use,kill>
	%VGPR8<def> = V_LOG_F32_e32 %VGPR0, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_LEGACY_F32_e32 4.166667e-01, %VGPR8<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_EXP_F32_e32 %VGPR8<kill>, %EXEC<imp-use>
	%VGPR8<def> = V_MAD_F32 %VGPR8<kill>, %VGPR13<kill>, %VGPR12<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = V_CMP_LT_F32_e64 %VGPR0, %VGPR14<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_F32_e32 1.292000e+01, %VGPR0<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_CNDMASK_B32_e64 %VGPR8<kill>, %VGPR0<kill>, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_F32_e64 0, %VGPR0<kill>, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_MOV_B32_e32 7.210000e-02, %EXEC<imp-use>
	%VGPR8<def> = V_MAD_F32 %VGPR0, %VGPR8<kill>, %VGPR15<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 5; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR9<def> = V_SUB_F32_e64 1.000000e+00, %SGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_MUL_F32_e32 %VGPR9<kill>, %VGPR8<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_MAD_F32 %SGPR0, %VGPR1<kill>, %VGPR8, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 6; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR9<def> = V_SUB_F32_e64 1.000000e+00, %SGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_MUL_F32_e32 %VGPR9, %VGPR1<kill>, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11<kill>, 7; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR10<def> = V_MOV_B32_e32 %SGPR2<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_MAD_F32 %SGPR1, %VGPR10, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_ADD_F32_e64 0, %VGPR1<kill>, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %SGPR0, %VGPR6<kill>, %VGPR8, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e32 %VGPR9, %VGPR6<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %SGPR1, %VGPR10, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_ADD_F32_e64 0, %VGPR6<kill>, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR6<kill>, %VGPR1<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %SGPR0<kill>, %VGPR0<kill>, %VGPR8<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR9<kill>, %VGPR0<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %SGPR1<kill>, %VGPR10<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_F32_e64 0, %VGPR0<kill>, 0, 1, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = V_CMP_U_F32_e64 %VGPR5, %VGPR5, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR5, 0.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_OR_B64 %SGPR2_SGPR3<kill>, %SGPR0_SGPR1<kill>
	%VGPR2<def> = V_CNDMASK_B32_e64 0.000000e+00, %VGPR5, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>
	%SGPR0_SGPR1<def> = V_CMP_GE_F32_e64 %VGPR2, %VGPR7, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_U_F32_e64 %VGPR2, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_OR_B64 %SGPR0_SGPR1<kill>, %SGPR2_SGPR3<kill>
	%VGPR2<def> = V_CNDMASK_B32_e64 %VGPR2<kill>, %VGPR7<kill>, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0<kill>, %VGPR2<kill>, %EXEC<imp-use>
	EXP 15, 0, 1, 1, 1, %VGPR1<kill>, %VGPR0<kill>, %VGPR1, %VGPR0, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_WQM_B64 exec, exec                                                      ; BEFE0A7E
	S_MOV_B32 m0, s7                                                          ; BEFC0307
	V_INTERP_P1_F32 v3, v0, 1, 0, [m0]                                        ; C80C0100
	V_INTERP_P2_F32 v3, [v3], v1, 1, 0, [m0]                                  ; C80D0101
	V_INTERP_P1_F32 v2, v0, 0, 0, [m0]                                        ; C8080000
	V_INTERP_P2_F32 v2, [v2], v1, 0, 0, [m0]                                  ; C8090001
	S_LOAD_DWORDX4 s[8:11], s[2:3], 0                                         ; C0840300
	S_LOAD_DWORDX8 s[12:19], s[4:5], 0                                        ; C0C60500
	S_WAITCNT lgkmcnt(0)                                                      ; BF8C007F
	IMAGE_SAMPLE v[2:5], 15, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[12:19], s[8:11]   ; F0800F00 00430202
	S_WAITCNT vmcnt(0)                                                        ; BF8C0770
	V_CMP_U_F32_e64 s[8:9], v3, v3, 0, 0, 0, 0                                ; D0100008 02020703
	V_CMP_GE_F32_e64 s[10:11], v3, 0.000000e+00, 0, 0, 0, 0                   ; D00C000A 02010103
	S_OR_B64 s[8:9], s[10:11], s[8:9]                                         ; 8888080A
	V_CNDMASK_B32_e64 v6, 0.000000e+00, v3, s[8:9], 0, 0, 0, 0                ; D2000006 00220680
	V_MOV_B32_e32 v7, 6.550400e+04                                            ; 7E0E02FF 477FE000
	V_CMP_GE_F32_e64 s[8:9], v6, v7, 0, 0, 0, 0                               ; D00C0008 02020F06
	V_CMP_U_F32_e64 s[10:11], v6, v6, 0, 0, 0, 0                              ; D010000A 02020D06
	S_OR_B64 s[8:9], s[8:9], s[10:11]                                         ; 88880A08
	V_CNDMASK_B32_e64 v6, v6, v7, s[8:9], 0, 0, 0, 0                          ; D2000006 00220F06
	S_LOAD_DWORDX4 s[8:11], s[0:1], 0                                         ; C0840100
	S_WAITCNT lgkmcnt(0)                                                      ; BF8C007F
	S_BUFFER_LOAD_DWORD s0, s[8:11], 0                                        ; C2000900
	S_WAITCNT lgkmcnt(0)                                                      ; BF8C007F
	V_MUL_F32_e32 v6, s0, v6                                                  ; 100C0C00
	S_LOAD_DWORDX4 s[12:15], s[2:3], 4                                        ; C0860304
	S_LOAD_DWORDX8 s[16:23], s[4:5], 8                                        ; C0C80508
	V_MOV_B32_e32 v8, 1056964608                                              ; 7E1002F0
	V_MOV_B32_e32 v9, v8                                                      ; 7E120308
	S_WAITCNT lgkmcnt(0)                                                      ; BF8C007F
	IMAGE_SAMPLE v8, 1, 0, 0, 0, 0, 0, 0, 0, v[8:9], s[16:23], s[12:15]       ; F0800100 00640808
	S_WAITCNT vmcnt(0)                                                        ; BF8C0770
	V_MUL_F32_e32 v6, v6, v8                                                  ; 100C1106
	V_INTERP_P1_F32 v10, v0, 3, 0, [m0]                                       ; C8280300
	V_INTERP_P2_F32 v10, [v10], v1, 3, 0, [m0]                                ; C8290301
	V_INTERP_P1_F32 v9, v0, 2, 0, [m0]                                        ; C8240200
	V_INTERP_P2_F32 v9, [v9], v1, 2, 0, [m0]                                  ; C8250201
	S_LOAD_DWORDX4 s[12:15], s[2:3], 8                                        ; C0860308
	S_LOAD_DWORDX8 s[16:23], s[4:5], 16                                       ; C0C80510
	S_WAITCNT lgkmcnt(0)                                                      ; BF8C007F
	IMAGE_SAMPLE v[9:11], 7, 0, 0, 0, 0, 0, 0, 0, v[9:10], s[16:23], s[12:15] ; F0800700 00640909
	S_BUFFER_LOAD_DWORD s1, s[8:11], 1                                        ; C2008901
	S_WAITCNT vmcnt(0) lgkmcnt(0)                                             ; BF8C0070
	V_MOV_B32_e32 v0, s1                                                      ; 7E000201
	V_MAD_F32 v1, v10, v0, v6, 0, 0, 0, 0                                     ; D2820001 041A010A
	V_LOG_F32_e32 v6, v1                                                      ; 7E0C4F01
	V_MUL_LEGACY_F32_e32 v6, 4.166667e-01, v6                                 ; 0E0C0CFF 3ED55555
	V_EXP_F32_e32 v6, v6                                                      ; 7E0C4B06
	V_MOV_B32_e32 v12, -5.500000e-02                                          ; 7E1802FF BD6147AE
	V_MOV_B32_e32 v13, 1.055000e+00                                           ; 7E1A02FF 3F870A3D
	V_MAD_F32 v6, v6, v13, v12, 0, 0, 0, 0                                    ; D2820006 04321B06
	V_MOV_B32_e32 v14, 3.130800e-03                                           ; 7E1C02FF 3B4D2E1C
	V_CMP_LT_F32_e64 s[2:3], v1, v14, 0, 0, 0, 0                              ; D0020002 02021D01
	V_MUL_F32_e32 v1, 1.292000e+01, v1                                        ; 100202FF 414EB852
	V_CNDMASK_B32_e64 v1, v6, v1, s[2:3], 0, 0, 0, 0                          ; D2000001 000A0306
	V_ADD_F32_e64 v1, 0, v1, 0, 1, 0, 0                                       ; D2060801 02020280
	V_CMP_U_F32_e64 s[2:3], v2, v2, 0, 0, 0, 0                                ; D0100002 02020502
	V_CMP_GE_F32_e64 s[4:5], v2, 0.000000e+00, 0, 0, 0, 0                     ; D00C0004 02010102
	S_OR_B64 s[2:3], s[4:5], s[2:3]                                           ; 88820204
	V_CNDMASK_B32_e64 v6, 0.000000e+00, v2, s[2:3], 0, 0, 0, 0                ; D2000006 000A0480
	V_CMP_GE_F32_e64 s[2:3], v6, v7, 0, 0, 0, 0                               ; D00C0002 02020F06
	V_CMP_U_F32_e64 s[4:5], v6, v6, 0, 0, 0, 0                                ; D0100004 02020D06
	S_OR_B64 s[2:3], s[2:3], s[4:5]                                           ; 88820402
	V_CNDMASK_B32_e64 v6, v6, v7, s[2:3], 0, 0, 0, 0                          ; D2000006 000A0F06
	V_MUL_F32_e32 v6, s0, v6                                                  ; 100C0C00
	V_MUL_F32_e32 v6, v6, v8                                                  ; 100C1106
	V_MAD_F32 v6, v9, v0, v6, 0, 0, 0, 0                                      ; D2820006 041A0109
	V_LOG_F32_e32 v15, v6                                                     ; 7E1E4F06
	V_MUL_LEGACY_F32_e32 v15, 4.166667e-01, v15                               ; 0E1E1EFF 3ED55555
	V_EXP_F32_e32 v15, v15                                                    ; 7E1E4B0F
	V_MAD_F32 v15, v15, v13, v12, 0, 0, 0, 0                                  ; D282000F 04321B0F
	V_CMP_LT_F32_e64 s[2:3], v6, v14, 0, 0, 0, 0                              ; D0020002 02021D06
	V_MUL_F32_e32 v6, 1.292000e+01, v6                                        ; 100C0CFF 414EB852
	V_CNDMASK_B32_e64 v6, v15, v6, s[2:3], 0, 0, 0, 0                         ; D2000006 000A0D0F
	V_ADD_F32_e64 v6, 0, v6, 0, 1, 0, 0                                       ; D2060806 02020C80
	V_MUL_F32_e32 v15, 2.125000e-01, v6                                       ; 101E0CFF 3E59999A
	V_MOV_B32_e32 v16, 7.154000e-01                                           ; 7E2002FF 3F372474
	V_MAD_F32 v15, v1, v16, v15, 0, 0, 0, 0                                   ; D282000F 043E2101
	V_CMP_U_F32_e64 s[2:3], v4, v4, 0, 0, 0, 0                                ; D0100002 02020904
	V_CMP_GE_F32_e64 s[4:5], v4, 0.000000e+00, 0, 0, 0, 0                     ; D00C0004 02010104
	S_OR_B64 s[2:3], s[4:5], s[2:3]                                           ; 88820204
	V_CNDMASK_B32_e64 v16, 0.000000e+00, v4, s[2:3], 0, 0, 0, 0               ; D2000010 000A0880
	V_CMP_GE_F32_e64 s[2:3], v16, v7, 0, 0, 0, 0                              ; D00C0002 02020F10
	V_CMP_U_F32_e64 s[4:5], v16, v16, 0, 0, 0, 0                              ; D0100004 02022110
	S_OR_B64 s[2:3], s[2:3], s[4:5]                                           ; 88820402
	V_CNDMASK_B32_e64 v16, v16, v7, s[2:3], 0, 0, 0, 0                        ; D2000010 000A0F10
	V_MUL_F32_e32 v16, s0, v16                                                ; 10202000
	V_MUL_F32_e32 v8, v16, v8                                                 ; 10101110
	V_MAD_F32 v0, v11, v0, v8, 0, 0, 0, 0                                     ; D2820000 0422010B
	V_LOG_F32_e32 v8, v0                                                      ; 7E104F00
	V_MUL_LEGACY_F32_e32 v8, 4.166667e-01, v8                                 ; 0E1010FF 3ED55555
	V_EXP_F32_e32 v8, v8                                                      ; 7E104B08
	V_MAD_F32 v8, v8, v13, v12, 0, 0, 0, 0                                    ; D2820008 04321B08
	V_CMP_LT_F32_e64 s[0:1], v0, v14, 0, 0, 0, 0                              ; D0020000 02021D00
	V_MUL_F32_e32 v0, 1.292000e+01, v0                                        ; 100000FF 414EB852
	V_CNDMASK_B32_e64 v0, v8, v0, s[0:1], 0, 0, 0, 0                          ; D2000000 00020108
	V_ADD_F32_e64 v0, 0, v0, 0, 1, 0, 0                                       ; D2060800 02020080
	V_MOV_B32_e32 v8, 7.210000e-02                                            ; 7E1002FF 3D93A92A
	V_MAD_F32 v8, v0, v8, v15, 0, 0, 0, 0                                     ; D2820008 043E1100
	S_BUFFER_LOAD_DWORD s0, s[8:11], 5                                        ; C2000905
	S_WAITCNT lgkmcnt(0)                                                      ; BF8C007F
	V_SUB_F32_e64 v9, 1.000000e+00, s0, 0, 0, 0, 0                            ; D2080009 020000F2
	V_MUL_F32_e32 v8, v9, v8                                                  ; 10101109
	V_MAD_F32 v1, s0, v1, v8, 0, 0, 0, 0                                      ; D2820001 04220200
	S_BUFFER_LOAD_DWORD s1, s[8:11], 6                                        ; C2008906
	S_WAITCNT lgkmcnt(0)                                                      ; BF8C007F
	V_SUB_F32_e64 v9, 1.000000e+00, s1, 0, 0, 0, 0                            ; D2080009 020002F2
	V_MUL_F32_e32 v1, v9, v1                                                  ; 10020309
	S_BUFFER_LOAD_DWORD s2, s[8:11], 7                                        ; C2010907
	S_WAITCNT lgkmcnt(0)                                                      ; BF8C007F
	V_MOV_B32_e32 v10, s2                                                     ; 7E140202
	V_MAD_F32 v1, s1, v10, v1, 0, 0, 0, 0                                     ; D2820001 04061401
	V_ADD_F32_e64 v1, 0, v1, 0, 1, 0, 0                                       ; D2060801 02020280
	V_MAD_F32 v6, s0, v6, v8, 0, 0, 0, 0                                      ; D2820006 04220C00
	V_MUL_F32_e32 v6, v9, v6                                                  ; 100C0D09
	V_MAD_F32 v6, s1, v10, v6, 0, 0, 0, 0                                     ; D2820006 041A1401
	V_ADD_F32_e64 v6, 0, v6, 0, 1, 0, 0                                       ; D2060806 02020C80
	V_CVT_PKRTZ_F16_F32_e32 v1, v6, v1                                        ; 5E020306
	V_MAD_F32 v0, s0, v0, v8, 0, 0, 0, 0                                      ; D2820000 04220000
	V_MUL_F32_e32 v0, v9, v0                                                  ; 10000109
	V_MAD_F32 v0, s1, v10, v0, 0, 0, 0, 0                                     ; D2820000 04021401
	V_ADD_F32_e64 v0, 0, v0, 0, 1, 0, 0                                       ; D2060800 02020080
	V_CMP_U_F32_e64 s[0:1], v5, v5, 0, 0, 0, 0                                ; D0100000 02020B05
	V_CMP_GE_F32_e64 s[2:3], v5, 0.000000e+00, 0, 0, 0, 0                     ; D00C0002 02010105
	S_OR_B64 s[0:1], s[2:3], s[0:1]                                           ; 88800002
	V_CNDMASK_B32_e64 v2, 0.000000e+00, v5, s[0:1], 0, 0, 0, 0                ; D2000002 00020A80
	V_CMP_GE_F32_e64 s[0:1], v2, v7, 0, 0, 0, 0                               ; D00C0000 02020F02
	V_CMP_U_F32_e64 s[2:3], v2, v2, 0, 0, 0, 0                                ; D0100002 02020502
	S_OR_B64 s[0:1], s[0:1], s[2:3]                                           ; 88800200
	V_CNDMASK_B32_e64 v2, v2, v7, s[0:1], 0, 0, 0, 0                          ; D2000002 00020F02
	V_CVT_PKRTZ_F16_F32_e32 v0, v0, v2                                        ; 5E000500
	EXP 15, 0, 1, 1, 1, v1, v0, v1, v0                                        ; F8001C0F 00010001
	S_ENDPGM                                                                  ; BF810000

VERT
DCL IN[0]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[19]
DCL CONST[0..1]
DCL TEMP[0..2], LOCAL
IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
  0: MOV TEMP[0].zw, IMM[0].yyxy
  1: MOV TEMP[0].xy, IN[0].xyxx
  2: MAD TEMP[1].xy, IN[0].zwww, CONST[0].xyyy, CONST[0].zwww
  3: MAD TEMP[2].xy, IN[0].zwww, CONST[1].xyyy, CONST[1].zwww
  4: MOV TEMP[1].zw, TEMP[2].yyxy
  5: MOV OUT[1], TEMP[1]
  6: MOV OUT[0], TEMP[0]
  7: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0)
  %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4)
  %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8)
  %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12)
  %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16)
  %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20)
  %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24)
  %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28)
  %20 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %21, i32 0, i32 %6)
  %23 = extractelement <4 x float> %22, i32 0
  %24 = extractelement <4 x float> %22, i32 1
  %25 = extractelement <4 x float> %22, i32 2
  %26 = extractelement <4 x float> %22, i32 3
  %27 = fmul float %25, %12
  %28 = fadd float %27, %14
  %29 = fmul float %26, %13
  %30 = fadd float %29, %15
  %31 = fmul float %25, %16
  %32 = fadd float %31, %18
  %33 = fmul float %26, %17
  %34 = fadd float %33, %19
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %28, float %30, float %32, float %34)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %23, float %24, float 0.000000e+00, float 1.000000e+00)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg6

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%23](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%11](align=8)(tbaa=!"const")
	S_WAITCNT 112
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 7; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR4<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 5; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR3, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 6; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 4; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR2, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 3; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR3, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 0; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR8<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR2, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 32, 0, 0, 0, %VGPR7<kill>, %VGPR6<kill>, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>
	S_WAITCNT 1807
	%VGPR4<def> = V_MOV_B32_e32 1.000000e+00, %EXEC<imp-use>
	%VGPR5<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR1, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_LOAD_DWORDX4 s[4:7], s[6:7], 0               ; C0820700
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	BUFFER_LOAD_FORMAT_XYZW v[0:3], s[4:7][v0] + 0 ; E00C2000 80010000
	S_LOAD_DWORDX4 s[0:3], s[0:1], 0               ; C0800100
	S_WAITCNT vmcnt(0) lgkmcnt(0)                  ; BF8C0070
	S_BUFFER_LOAD_DWORD s4, s[0:3], 7              ; C2020107
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v4, s4                           ; 7E080204
	S_BUFFER_LOAD_DWORD s4, s[0:3], 5              ; C2020105
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v5, s4                           ; 7E0A0204
	V_MAD_F32 v4, v3, v5, v4, 0, 0, 0, 0           ; D2820004 04120B03
	S_BUFFER_LOAD_DWORD s4, s[0:3], 6              ; C2020106
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v5, s4                           ; 7E0A0204
	S_BUFFER_LOAD_DWORD s4, s[0:3], 4              ; C2020104
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v6, s4                           ; 7E0C0204
	V_MAD_F32 v5, v2, v6, v5, 0, 0, 0, 0           ; D2820005 04160D02
	S_BUFFER_LOAD_DWORD s4, s[0:3], 3              ; C2020103
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v6, s4                           ; 7E0C0204
	S_BUFFER_LOAD_DWORD s4, s[0:3], 1              ; C2020101
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v7, s4                           ; 7E0E0204
	V_MAD_F32 v6, v3, v7, v6, 0, 0, 0, 0           ; D2820006 041A0F03
	S_BUFFER_LOAD_DWORD s4, s[0:3], 2              ; C2020102
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v7, s4                           ; 7E0E0204
	S_BUFFER_LOAD_DWORD s0, s[0:3], 0              ; C2000100
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v8, s0                           ; 7E100200
	V_MAD_F32 v7, v2, v8, v7, 0, 0, 0, 0           ; D2820007 041E1102
	EXP 15, 32, 0, 0, 0, v7, v6, v5, v4            ; F800020F 04050607
	S_WAITCNT expcnt(0)                            ; BF8C070F
	V_MOV_B32_e32 v4, 1.000000e+00                 ; 7E0802F2
	V_MOV_B32_e32 v5, 0.000000e+00                 ; 7E0A0280
	EXP 15, 12, 0, 1, 0, v0, v1, v5, v4            ; F80008CF 04050100
	S_ENDPGM                                       ; BF810000

FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL OUT[0], COLOR
DCL CONST[0..13]
DCL TEMP[0..2], LOCAL
IMM[0] FLT32 {    1.0000,     0.0000,     4.0000,     0.0000}
  0: MOV TEMP[0].w, IMM[0].xxxx
  1: MAD TEMP[0].x, IN[0].zzzz, CONST[0].zzzz, CONST[0].yyyy
  2: MOV_SAT TEMP[1].x, TEMP[0].xxxx
  3: MOV TEMP[0].x, TEMP[1].xxxx
  4: MUL TEMP[2].x, TEMP[1].xxxx, TEMP[1].xxxx
  5: ADD TEMP[1].x, TEMP[1].xxxx, -TEMP[2].xxxx
  6: MUL TEMP[1].x, IMM[0].zzzz, TEMP[1].xxxx
  7: ADD TEMP[1].x, IMM[0].xxxx, -TEMP[1].xxxx
  8: MOV TEMP[0].y, TEMP[1].xxxx
  9: MOV TEMP[0].z, IMM[0].yyyy
 10: MOV OUT[0], TEMP[0]
 11: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %21 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
  %22 = load <16 x i8> addrspace(2)* %21, !tbaa !0
  %23 = call float @llvm.SI.load.const(<16 x i8> %22, i32 4)
  %24 = call float @llvm.SI.load.const(<16 x i8> %22, i32 8)
  %25 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %4, <2 x i32> %6)
  %26 = fmul float %25, %24
  %27 = fadd float %26, %23
  %28 = call float @llvm.AMDIL.clamp.(float %27, float 0.000000e+00, float 1.000000e+00)
  %29 = fmul float %28, %28
  %30 = fsub float -0.000000e+00, %29
  %31 = fadd float %28, %30
  %32 = fmul float 4.000000e+00, %31
  %33 = fsub float -0.000000e+00, %32
  %34 = fadd float 1.000000e+00, %33
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %28, float %34, float 0.000000e+00, float 1.000000e+00)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR7 in %vreg4, %VGPR0 in %vreg5, %VGPR1 in %vreg6

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR7 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR7
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<kill,tied0>, %VGPR1, 2, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%22](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2; mem:LD4[<unknown>]
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 1; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR0<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR2<kill>, %SGPR4<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_F32_e64 0, %VGPR0<kill>, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_MUL_F32_e32 %VGPR0, %VGPR0, %EXEC<imp-use>
	%VGPR1<def> = V_SUB_F32_e32 %VGPR0, %VGPR1<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_MAD_F32 %VGPR1<kill>, -4.000000e+00, 1.000000e+00, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR2<def> = V_MOV_B32_e32 1.000000e+00, %EXEC<imp-use>
	%VGPR3<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	EXP 15, 0, 0, 1, 1, %VGPR0<kill>, %VGPR1<kill>, %VGPR3<kill>, %VGPR2<kill>, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_WQM_B64 exec, exec                                      ; BEFE0A7E
	S_MOV_B32 m0, s7                                          ; BEFC0307
	V_INTERP_P1_F32 v2, v0, 2, 0, [m0]                        ; C8080200
	V_INTERP_P2_F32 v2, [v2], v1, 2, 0, [m0]                  ; C8090201
	S_LOAD_DWORDX4 s[0:3], s[0:1], 0                          ; C0800100
	S_WAITCNT lgkmcnt(0)                                      ; BF8C007F
	S_BUFFER_LOAD_DWORD s4, s[0:3], 2                         ; C2020102
	S_BUFFER_LOAD_DWORD s0, s[0:3], 1                         ; C2000101
	S_WAITCNT lgkmcnt(0)                                      ; BF8C007F
	V_MOV_B32_e32 v0, s0                                      ; 7E000200
	V_MAD_F32 v0, v2, s4, v0, 0, 0, 0, 0                      ; D2820000 04000902
	V_ADD_F32_e64 v0, 0, v0, 0, 1, 0, 0                       ; D2060800 02020080
	V_MUL_F32_e32 v1, v0, v0                                  ; 10020100
	V_SUB_F32_e32 v1, v0, v1                                  ; 08020300
	V_MAD_F32 v1, v1, -4.000000e+00, 1.000000e+00, 0, 0, 0, 0 ; D2820001 03C9EF01
	V_MOV_B32_e32 v2, 1.000000e+00                            ; 7E0402F2
	V_MOV_B32_e32 v3, 0.000000e+00                            ; 7E060280
	EXP 15, 0, 0, 1, 1, v0, v1, v3, v2                        ; F800180F 02030100
	S_ENDPGM                                                  ; BF810000

VERT
DCL IN[0]
DCL IN[1]
DCL IN[2]
DCL IN[3]
DCL OUT[0], POSITION
DCL OUT[1], CLIPVERTEX
DCL OUT[2], GENERIC[19]
DCL CONST[0..240]
DCL TEMP[0..7], LOCAL
DCL ADDR[0]
IMM[0] FLT32 {    1.0000,   255.0100,     0.0000,     0.0000}
IMM[1] INT32 {3, 41, 42, 43}
  0: MOV TEMP[0], IN[0]
  1: UIF CONST[240].xxxx :0
  2:   DP3 TEMP[1].x, IN[3].xyzz, IMM[0].xxxx
  3:   ADD TEMP[1].x, IMM[0].xxxx, -TEMP[1].xxxx
  4:   MUL TEMP[2], IN[2], IMM[0].yyyy
  5:   F2I TEMP[2], TEMP[2]
  6:   UMAD TEMP[3].x, TEMP[2].wwww, IMM[1].xxxx, IMM[1].yyyy
  7:   UMAD TEMP[4].x, TEMP[2].zzzz, IMM[1].xxxx, IMM[1].yyyy
  8:   UMAD TEMP[5].x, TEMP[2].yyyy, IMM[1].xxxx, IMM[1].yyyy
  9:   UMAD TEMP[6].x, TEMP[2].xxxx, IMM[1].xxxx, IMM[1].yyyy
 10:   UARL ADDR[0].x, TEMP[6].xxxx
 11:   MUL TEMP[6], CONST[ADDR[0].x], IN[3].xxxx
 12:   UARL ADDR[0].x, TEMP[5].xxxx
 13:   MAD TEMP[5], CONST[ADDR[0].x], IN[3].yyyy, TEMP[6]
 14:   UARL ADDR[0].x, TEMP[4].xxxx
 15:   MAD TEMP[4], CONST[ADDR[0].x], IN[3].zzzz, TEMP[5]
 16:   UARL ADDR[0].x, TEMP[3].xxxx
 17:   MAD TEMP[3], CONST[ADDR[0].x], TEMP[1].xxxx, TEMP[4]
 18:   DP4 TEMP[3].x, IN[0], TEMP[3]
 19:   UMAD TEMP[4].x, TEMP[2].wwww, IMM[1].xxxx, IMM[1].zzzz
 20:   UMAD TEMP[5].x, TEMP[2].zzzz, IMM[1].xxxx, IMM[1].zzzz
 21:   UMAD TEMP[6].x, TEMP[2].yyyy, IMM[1].xxxx, IMM[1].zzzz
 22:   UMAD TEMP[7].x, TEMP[2].xxxx, IMM[1].xxxx, IMM[1].zzzz
 23:   UARL ADDR[0].x, TEMP[7].xxxx
 24:   MUL TEMP[7], CONST[ADDR[0].x], IN[3].xxxx
 25:   UARL ADDR[0].x, TEMP[6].xxxx
 26:   MAD TEMP[6], CONST[ADDR[0].x], IN[3].yyyy, TEMP[7]
 27:   UARL ADDR[0].x, TEMP[5].xxxx
 28:   MAD TEMP[5], CONST[ADDR[0].x], IN[3].zzzz, TEMP[6]
 29:   UARL ADDR[0].x, TEMP[4].xxxx
 30:   MAD TEMP[4], CONST[ADDR[0].x], TEMP[1].xxxx, TEMP[5]
 31:   DP4 TEMP[4].x, IN[0], TEMP[4]
 32:   MOV TEMP[3].y, TEMP[4].xxxx
 33:   UMAD TEMP[4].x, TEMP[2].wwww, IMM[1].xxxx, IMM[1].wwww
 34:   UMAD TEMP[5].x, TEMP[2].zzzz, IMM[1].xxxx, IMM[1].wwww
 35:   UMAD TEMP[6].x, TEMP[2].yyyy, IMM[1].xxxx, IMM[1].wwww
 36:   UMAD TEMP[2].x, TEMP[2].xxxx, IMM[1].xxxx, IMM[1].wwww
 37:   UARL ADDR[0].x, TEMP[2].xxxx
 38:   MUL TEMP[2], CONST[ADDR[0].x], IN[3].xxxx
 39:   UARL ADDR[0].x, TEMP[6].xxxx
 40:   MAD TEMP[2], CONST[ADDR[0].x], IN[3].yyyy, TEMP[2]
 41:   UARL ADDR[0].x, TEMP[5].xxxx
 42:   MAD TEMP[2], CONST[ADDR[0].x], IN[3].zzzz, TEMP[2]
 43:   UARL ADDR[0].x, TEMP[4].xxxx
 44:   MAD TEMP[1], CONST[ADDR[0].x], TEMP[1].xxxx, TEMP[2]
 45:   DP4 TEMP[1].x, IN[0], TEMP[1]
 46:   MOV TEMP[3].z, TEMP[1].xxxx
 47:   MOV TEMP[0].xyz, TEMP[3].xyzx
 48: ENDIF
 49: DP4 TEMP[1].x, TEMP[0], CONST[0]
 50: DP4 TEMP[2].x, TEMP[0], CONST[1]
 51: MOV TEMP[1].y, TEMP[2].xxxx
 52: DP4 TEMP[2].x, TEMP[0], CONST[2]
 53: MOV TEMP[1].z, TEMP[2].xxxx
 54: DP4 TEMP[2].x, TEMP[0], CONST[3]
 55: MOV TEMP[1].w, TEMP[2].xxxx
 56: DP4 TEMP[0].x, TEMP[0], CONST[9]
 57: MOV TEMP[0].z, TEMP[0].xxxx
 58: DP4 TEMP[2].x, IN[1], CONST[7]
 59: DP4 TEMP[3].x, IN[1], CONST[8]
 60: MOV TEMP[2].y, TEMP[3].xxxx
 61: MOV TEMP[0].xy, TEMP[2].xyxx
 62: MOV TEMP[0].w, IMM[0].xxxx
 63: MOV OUT[0], TEMP[1]
 64: MOV OUT[2], TEMP[0]
 65: MOV OUT[1], TEMP[1]
 66: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0)
  %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4)
  %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8)
  %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12)
  %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16)
  %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20)
  %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24)
  %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28)
  %20 = call float @llvm.SI.load.const(<16 x i8> %11, i32 32)
  %21 = call float @llvm.SI.load.const(<16 x i8> %11, i32 36)
  %22 = call float @llvm.SI.load.const(<16 x i8> %11, i32 40)
  %23 = call float @llvm.SI.load.const(<16 x i8> %11, i32 44)
  %24 = call float @llvm.SI.load.const(<16 x i8> %11, i32 48)
  %25 = call float @llvm.SI.load.const(<16 x i8> %11, i32 52)
  %26 = call float @llvm.SI.load.const(<16 x i8> %11, i32 56)
  %27 = call float @llvm.SI.load.const(<16 x i8> %11, i32 60)
  %28 = call float @llvm.SI.load.const(<16 x i8> %11, i32 112)
  %29 = call float @llvm.SI.load.const(<16 x i8> %11, i32 116)
  %30 = call float @llvm.SI.load.const(<16 x i8> %11, i32 120)
  %31 = call float @llvm.SI.load.const(<16 x i8> %11, i32 124)
  %32 = call float @llvm.SI.load.const(<16 x i8> %11, i32 128)
  %33 = call float @llvm.SI.load.const(<16 x i8> %11, i32 132)
  %34 = call float @llvm.SI.load.const(<16 x i8> %11, i32 136)
  %35 = call float @llvm.SI.load.const(<16 x i8> %11, i32 140)
  %36 = call float @llvm.SI.load.const(<16 x i8> %11, i32 144)
  %37 = call float @llvm.SI.load.const(<16 x i8> %11, i32 148)
  %38 = call float @llvm.SI.load.const(<16 x i8> %11, i32 152)
  %39 = call float @llvm.SI.load.const(<16 x i8> %11, i32 156)
  %40 = call float @llvm.SI.load.const(<16 x i8> %11, i32 3840)
  %41 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0
  %42 = load <16 x i8> addrspace(2)* %41, !tbaa !0
  %43 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %42, i32 0, i32 %6)
  %44 = extractelement <4 x float> %43, i32 0
  %45 = extractelement <4 x float> %43, i32 1
  %46 = extractelement <4 x float> %43, i32 2
  %47 = extractelement <4 x float> %43, i32 3
  %48 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 1
  %49 = load <16 x i8> addrspace(2)* %48, !tbaa !0
  %50 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %49, i32 0, i32 %6)
  %51 = extractelement <4 x float> %50, i32 0
  %52 = extractelement <4 x float> %50, i32 1
  %53 = extractelement <4 x float> %50, i32 2
  %54 = extractelement <4 x float> %50, i32 3
  %55 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 2
  %56 = load <16 x i8> addrspace(2)* %55, !tbaa !0
  %57 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %56, i32 0, i32 %6)
  %58 = extractelement <4 x float> %57, i32 0
  %59 = extractelement <4 x float> %57, i32 1
  %60 = extractelement <4 x float> %57, i32 2
  %61 = extractelement <4 x float> %57, i32 3
  %62 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 3
  %63 = load <16 x i8> addrspace(2)* %62, !tbaa !0
  %64 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %63, i32 0, i32 %6)
  %65 = extractelement <4 x float> %64, i32 0
  %66 = extractelement <4 x float> %64, i32 1
  %67 = extractelement <4 x float> %64, i32 2
  %68 = bitcast float %40 to i32
  %69 = icmp ne i32 %68, 0
  br i1 %69, label %IF, label %ENDIF

IF:                                               ; preds = %main_body
  %70 = fmul float %65, 1.000000e+00
  %71 = fmul float %66, 1.000000e+00
  %72 = fadd float %71, %70
  %73 = fmul float %67, 1.000000e+00
  %74 = fadd float %72, %73
  %75 = fsub float -0.000000e+00, %74
  %76 = fadd float 1.000000e+00, %75
  %77 = fmul float %58, 0x406FE051E0000000
  %78 = fmul float %59, 0x406FE051E0000000
  %79 = fmul float %60, 0x406FE051E0000000
  %80 = fmul float %61, 0x406FE051E0000000
  %81 = fptosi float %77 to i32
  %82 = fptosi float %78 to i32
  %83 = fptosi float %79 to i32
  %84 = fptosi float %80 to i32
  %85 = bitcast i32 %81 to float
  %86 = bitcast i32 %82 to float
  %87 = bitcast i32 %83 to float
  %88 = bitcast i32 %84 to float
  %89 = bitcast float %88 to i32
  %90 = mul i32 %89, 3
  %91 = add i32 %90, 41
  %92 = bitcast i32 %91 to float
  %93 = bitcast float %87 to i32
  %94 = mul i32 %93, 3
  %95 = add i32 %94, 41
  %96 = bitcast i32 %95 to float
  %97 = bitcast float %86 to i32
  %98 = mul i32 %97, 3
  %99 = add i32 %98, 41
  %100 = bitcast i32 %99 to float
  %101 = bitcast float %85 to i32
  %102 = mul i32 %101, 3
  %103 = add i32 %102, 41
  %104 = bitcast i32 %103 to float
  %105 = bitcast float %104 to i32
  %106 = shl i32 %105, 4
  %107 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %106)
  %108 = fmul float %107, %65
  %109 = shl i32 %105, 4
  %110 = add i32 %109, 4
  %111 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %110)
  %112 = fmul float %111, %65
  %113 = shl i32 %105, 4
  %114 = add i32 %113, 8
  %115 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %114)
  %116 = fmul float %115, %65
  %117 = shl i32 %105, 4
  %118 = add i32 %117, 12
  %119 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %118)
  %120 = fmul float %119, %65
  %121 = bitcast float %100 to i32
  %122 = shl i32 %121, 4
  %123 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %122)
  %124 = fmul float %123, %66
  %125 = fadd float %124, %108
  %126 = shl i32 %121, 4
  %127 = add i32 %126, 4
  %128 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %127)
  %129 = fmul float %128, %66
  %130 = fadd float %129, %112
  %131 = shl i32 %121, 4
  %132 = add i32 %131, 8
  %133 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %132)
  %134 = fmul float %133, %66
  %135 = fadd float %134, %116
  %136 = shl i32 %121, 4
  %137 = add i32 %136, 12
  %138 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %137)
  %139 = fmul float %138, %66
  %140 = fadd float %139, %120
  %141 = bitcast float %96 to i32
  %142 = shl i32 %141, 4
  %143 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %142)
  %144 = fmul float %143, %67
  %145 = fadd float %144, %125
  %146 = shl i32 %141, 4
  %147 = add i32 %146, 4
  %148 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %147)
  %149 = fmul float %148, %67
  %150 = fadd float %149, %130
  %151 = shl i32 %141, 4
  %152 = add i32 %151, 8
  %153 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %152)
  %154 = fmul float %153, %67
  %155 = fadd float %154, %135
  %156 = shl i32 %141, 4
  %157 = add i32 %156, 12
  %158 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %157)
  %159 = fmul float %158, %67
  %160 = fadd float %159, %140
  %161 = bitcast float %92 to i32
  %162 = shl i32 %161, 4
  %163 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %162)
  %164 = fmul float %163, %76
  %165 = fadd float %164, %145
  %166 = shl i32 %161, 4
  %167 = add i32 %166, 4
  %168 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %167)
  %169 = fmul float %168, %76
  %170 = fadd float %169, %150
  %171 = shl i32 %161, 4
  %172 = add i32 %171, 8
  %173 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %172)
  %174 = fmul float %173, %76
  %175 = fadd float %174, %155
  %176 = shl i32 %161, 4
  %177 = add i32 %176, 12
  %178 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %177)
  %179 = fmul float %178, %76
  %180 = fadd float %179, %160
  %181 = fmul float %44, %165
  %182 = fmul float %45, %170
  %183 = fadd float %181, %182
  %184 = fmul float %46, %175
  %185 = fadd float %183, %184
  %186 = fmul float %47, %180
  %187 = fadd float %185, %186
  %188 = bitcast float %88 to i32
  %189 = mul i32 %188, 3
  %190 = add i32 %189, 42
  %191 = bitcast i32 %190 to float
  %192 = bitcast float %87 to i32
  %193 = mul i32 %192, 3
  %194 = add i32 %193, 42
  %195 = bitcast i32 %194 to float
  %196 = bitcast float %86 to i32
  %197 = mul i32 %196, 3
  %198 = add i32 %197, 42
  %199 = bitcast i32 %198 to float
  %200 = bitcast float %85 to i32
  %201 = mul i32 %200, 3
  %202 = add i32 %201, 42
  %203 = bitcast i32 %202 to float
  %204 = bitcast float %203 to i32
  %205 = shl i32 %204, 4
  %206 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %205)
  %207 = fmul float %206, %65
  %208 = shl i32 %204, 4
  %209 = add i32 %208, 4
  %210 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %209)
  %211 = fmul float %210, %65
  %212 = shl i32 %204, 4
  %213 = add i32 %212, 8
  %214 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %213)
  %215 = fmul float %214, %65
  %216 = shl i32 %204, 4
  %217 = add i32 %216, 12
  %218 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %217)
  %219 = fmul float %218, %65
  %220 = bitcast float %199 to i32
  %221 = shl i32 %220, 4
  %222 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %221)
  %223 = fmul float %222, %66
  %224 = fadd float %223, %207
  %225 = shl i32 %220, 4
  %226 = add i32 %225, 4
  %227 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %226)
  %228 = fmul float %227, %66
  %229 = fadd float %228, %211
  %230 = shl i32 %220, 4
  %231 = add i32 %230, 8
  %232 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %231)
  %233 = fmul float %232, %66
  %234 = fadd float %233, %215
  %235 = shl i32 %220, 4
  %236 = add i32 %235, 12
  %237 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %236)
  %238 = fmul float %237, %66
  %239 = fadd float %238, %219
  %240 = bitcast float %195 to i32
  %241 = shl i32 %240, 4
  %242 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %241)
  %243 = fmul float %242, %67
  %244 = fadd float %243, %224
  %245 = shl i32 %240, 4
  %246 = add i32 %245, 4
  %247 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %246)
  %248 = fmul float %247, %67
  %249 = fadd float %248, %229
  %250 = shl i32 %240, 4
  %251 = add i32 %250, 8
  %252 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %251)
  %253 = fmul float %252, %67
  %254 = fadd float %253, %234
  %255 = shl i32 %240, 4
  %256 = add i32 %255, 12
  %257 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %256)
  %258 = fmul float %257, %67
  %259 = fadd float %258, %239
  %260 = bitcast float %191 to i32
  %261 = shl i32 %260, 4
  %262 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %261)
  %263 = fmul float %262, %76
  %264 = fadd float %263, %244
  %265 = shl i32 %260, 4
  %266 = add i32 %265, 4
  %267 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %266)
  %268 = fmul float %267, %76
  %269 = fadd float %268, %249
  %270 = shl i32 %260, 4
  %271 = add i32 %270, 8
  %272 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %271)
  %273 = fmul float %272, %76
  %274 = fadd float %273, %254
  %275 = shl i32 %260, 4
  %276 = add i32 %275, 12
  %277 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %276)
  %278 = fmul float %277, %76
  %279 = fadd float %278, %259
  %280 = fmul float %44, %264
  %281 = fmul float %45, %269
  %282 = fadd float %280, %281
  %283 = fmul float %46, %274
  %284 = fadd float %282, %283
  %285 = fmul float %47, %279
  %286 = fadd float %284, %285
  %287 = bitcast float %88 to i32
  %288 = mul i32 %287, 3
  %289 = add i32 %288, 43
  %290 = bitcast i32 %289 to float
  %291 = bitcast float %87 to i32
  %292 = mul i32 %291, 3
  %293 = add i32 %292, 43
  %294 = bitcast i32 %293 to float
  %295 = bitcast float %86 to i32
  %296 = mul i32 %295, 3
  %297 = add i32 %296, 43
  %298 = bitcast i32 %297 to float
  %299 = bitcast float %85 to i32
  %300 = mul i32 %299, 3
  %301 = add i32 %300, 43
  %302 = bitcast i32 %301 to float
  %303 = bitcast float %302 to i32
  %304 = shl i32 %303, 4
  %305 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %304)
  %306 = fmul float %305, %65
  %307 = shl i32 %303, 4
  %308 = add i32 %307, 4
  %309 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %308)
  %310 = fmul float %309, %65
  %311 = shl i32 %303, 4
  %312 = add i32 %311, 8
  %313 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %312)
  %314 = fmul float %313, %65
  %315 = shl i32 %303, 4
  %316 = add i32 %315, 12
  %317 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %316)
  %318 = fmul float %317, %65
  %319 = bitcast float %298 to i32
  %320 = shl i32 %319, 4
  %321 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %320)
  %322 = fmul float %321, %66
  %323 = fadd float %322, %306
  %324 = shl i32 %319, 4
  %325 = add i32 %324, 4
  %326 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %325)
  %327 = fmul float %326, %66
  %328 = fadd float %327, %310
  %329 = shl i32 %319, 4
  %330 = add i32 %329, 8
  %331 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %330)
  %332 = fmul float %331, %66
  %333 = fadd float %332, %314
  %334 = shl i32 %319, 4
  %335 = add i32 %334, 12
  %336 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %335)
  %337 = fmul float %336, %66
  %338 = fadd float %337, %318
  %339 = bitcast float %294 to i32
  %340 = shl i32 %339, 4
  %341 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %340)
  %342 = fmul float %341, %67
  %343 = fadd float %342, %323
  %344 = shl i32 %339, 4
  %345 = add i32 %344, 4
  %346 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %345)
  %347 = fmul float %346, %67
  %348 = fadd float %347, %328
  %349 = shl i32 %339, 4
  %350 = add i32 %349, 8
  %351 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %350)
  %352 = fmul float %351, %67
  %353 = fadd float %352, %333
  %354 = shl i32 %339, 4
  %355 = add i32 %354, 12
  %356 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %355)
  %357 = fmul float %356, %67
  %358 = fadd float %357, %338
  %359 = bitcast float %290 to i32
  %360 = shl i32 %359, 4
  %361 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %360)
  %362 = fmul float %361, %76
  %363 = fadd float %362, %343
  %364 = shl i32 %359, 4
  %365 = add i32 %364, 4
  %366 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %365)
  %367 = fmul float %366, %76
  %368 = fadd float %367, %348
  %369 = shl i32 %359, 4
  %370 = add i32 %369, 8
  %371 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %370)
  %372 = fmul float %371, %76
  %373 = fadd float %372, %353
  %374 = shl i32 %359, 4
  %375 = add i32 %374, 12
  %376 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %375)
  %377 = fmul float %376, %76
  %378 = fadd float %377, %358
  %379 = fmul float %44, %363
  %380 = fmul float %45, %368
  %381 = fadd float %379, %380
  %382 = fmul float %46, %373
  %383 = fadd float %381, %382
  %384 = fmul float %47, %378
  %385 = fadd float %383, %384
  br label %ENDIF

ENDIF:                                            ; preds = %main_body, %IF
  %temp.0 = phi float [ %187, %IF ], [ %44, %main_body ]
  %temp1.0 = phi float [ %286, %IF ], [ %45, %main_body ]
  %temp2.0 = phi float [ %385, %IF ], [ %46, %main_body ]
  %386 = fmul float %temp.0, %12
  %387 = fmul float %temp1.0, %13
  %388 = fadd float %386, %387
  %389 = fmul float %temp2.0, %14
  %390 = fadd float %388, %389
  %391 = fmul float %47, %15
  %392 = fadd float %390, %391
  %393 = fmul float %temp.0, %16
  %394 = fmul float %temp1.0, %17
  %395 = fadd float %393, %394
  %396 = fmul float %temp2.0, %18
  %397 = fadd float %395, %396
  %398 = fmul float %47, %19
  %399 = fadd float %397, %398
  %400 = fmul float %temp.0, %20
  %401 = fmul float %temp1.0, %21
  %402 = fadd float %400, %401
  %403 = fmul float %temp2.0, %22
  %404 = fadd float %402, %403
  %405 = fmul float %47, %23
  %406 = fadd float %404, %405
  %407 = fmul float %temp.0, %24
  %408 = fmul float %temp1.0, %25
  %409 = fadd float %407, %408
  %410 = fmul float %temp2.0, %26
  %411 = fadd float %409, %410
  %412 = fmul float %47, %27
  %413 = fadd float %411, %412
  %414 = fmul float %temp.0, %36
  %415 = fmul float %temp1.0, %37
  %416 = fadd float %414, %415
  %417 = fmul float %temp2.0, %38
  %418 = fadd float %416, %417
  %419 = fmul float %47, %39
  %420 = fadd float %418, %419
  %421 = fmul float %51, %28
  %422 = fmul float %52, %29
  %423 = fadd float %421, %422
  %424 = fmul float %53, %30
  %425 = fadd float %423, %424
  %426 = fmul float %54, %31
  %427 = fadd float %425, %426
  %428 = fmul float %51, %32
  %429 = fmul float %52, %33
  %430 = fadd float %428, %429
  %431 = fmul float %53, %34
  %432 = fadd float %430, %431
  %433 = fmul float %54, %35
  %434 = fadd float %432, %433
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %427, float %434, float %420, float 1.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %392, float %399, float %406, float %413)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg41, %SGPR6_SGPR7 in %vreg44, %VGPR0 in %vreg47

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%53](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%VGPR5_VGPR6_VGPR7_VGPR8<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 0; mem:LD16[%44](align=8)(tbaa=!"const")
	S_WAITCNT 112
	%VGPR1_VGPR2_VGPR3_VGPR4<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%11](align=8)(tbaa=!"const")
	%SGPR4<def> = S_MOV_B32 3840
	S_WAITCNT 112
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_SGPR %SGPR0_SGPR1_SGPR2_SGPR3, %SGPR4<kill>; mem:LD4[<unknown>]
	S_WAITCNT 127
	%SGPR4_SGPR5<def> = V_CMP_NE_I32_e64 %SGPR4<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 39; mem:LD4[<unknown>]
	%SGPR9<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 38; mem:LD4[<unknown>]
	%SGPR10<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 37; mem:LD4[<unknown>]
	%SGPR11<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 36; mem:LD4[<unknown>]
	%SGPR12<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 35; mem:LD4[<unknown>]
	%SGPR13<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 34; mem:LD4[<unknown>]
	%SGPR14<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 33; mem:LD4[<unknown>]
	%SGPR15<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 32; mem:LD4[<unknown>]
	%SGPR16<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 31; mem:LD4[<unknown>]
	%SGPR17<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 30; mem:LD4[<unknown>]
	%SGPR18<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 29; mem:LD4[<unknown>]
	%SGPR19<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 28; mem:LD4[<unknown>]
	%SGPR20<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 15; mem:LD4[<unknown>]
	%SGPR21<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 14; mem:LD4[<unknown>]
	%SGPR22<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 13; mem:LD4[<unknown>]
	%SGPR23<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 12; mem:LD4[<unknown>]
	%SGPR24<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 11; mem:LD4[<unknown>]
	%SGPR25<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 10; mem:LD4[<unknown>]
	%SGPR26<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 9; mem:LD4[<unknown>]
	%SGPR27<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 8; mem:LD4[<unknown>]
	%SGPR28<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 7; mem:LD4[<unknown>]
	%SGPR29<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 6; mem:LD4[<unknown>]
	%SGPR30<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 5; mem:LD4[<unknown>]
	%SGPR31<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 4; mem:LD4[<unknown>]
	%SGPR32<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 3; mem:LD4[<unknown>]
	%SGPR33<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2; mem:LD4[<unknown>]
	%SGPR34<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1; mem:LD4[<unknown>]
	%SGPR35<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 0; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR29<def> = V_MOV_B32_e32 %SGPR8<kill>, %EXEC<imp-use>
	%VGPR32<def> = V_MOV_B32_e32 %SGPR9<kill>, %EXEC<imp-use>
	%VGPR36<def> = V_MOV_B32_e32 %SGPR10<kill>, %EXEC<imp-use>
	%VGPR35<def> = V_MOV_B32_e32 %SGPR11<kill>, %EXEC<imp-use>
	%VGPR18<def> = V_MOV_B32_e32 %SGPR12<kill>, %EXEC<imp-use>
	%VGPR28<def> = V_MOV_B32_e32 %SGPR13<kill>, %EXEC<imp-use>
	%VGPR34<def> = V_MOV_B32_e32 %SGPR14<kill>, %EXEC<imp-use>
	%VGPR33<def> = V_MOV_B32_e32 %SGPR15<kill>, %EXEC<imp-use>
	%VGPR17<def> = V_MOV_B32_e32 %SGPR16<kill>, %EXEC<imp-use>
	%VGPR19<def> = V_MOV_B32_e32 %SGPR17<kill>, %EXEC<imp-use>
	%VGPR31<def> = V_MOV_B32_e32 %SGPR18<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_MOV_B32_e32 %SGPR19<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_MOV_B32_e32 %SGPR20<kill>, %EXEC<imp-use>
	%VGPR16<def> = V_MOV_B32_e32 %SGPR21<kill>, %EXEC<imp-use>
	%VGPR27<def> = V_MOV_B32_e32 %SGPR22<kill>, %EXEC<imp-use>
	%VGPR26<def> = V_MOV_B32_e32 %SGPR23<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_MOV_B32_e32 %SGPR24<kill>, %EXEC<imp-use>
	%VGPR15<def> = V_MOV_B32_e32 %SGPR25<kill>, %EXEC<imp-use>
	%VGPR25<def> = V_MOV_B32_e32 %SGPR26<kill>, %EXEC<imp-use>
	%VGPR24<def> = V_MOV_B32_e32 %SGPR27<kill>, %EXEC<imp-use>
	%VGPR10<def> = V_MOV_B32_e32 %SGPR28<kill>, %EXEC<imp-use>
	%VGPR14<def> = V_MOV_B32_e32 %SGPR29<kill>, %EXEC<imp-use>
	%VGPR23<def> = V_MOV_B32_e32 %SGPR30<kill>, %EXEC<imp-use>
	%VGPR22<def> = V_MOV_B32_e32 %SGPR31<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_MOV_B32_e32 %SGPR32<kill>, %EXEC<imp-use>
	%VGPR13<def> = V_MOV_B32_e32 %SGPR33<kill>, %EXEC<imp-use>
	%VGPR21<def> = V_MOV_B32_e32 %SGPR34<kill>, %EXEC<imp-use>
	%VGPR20<def> = V_MOV_B32_e32 %SGPR35<kill>, %EXEC<imp-use>
	%VGPR39<def> = V_MOV_B32_e32 %VGPR1, %EXEC<imp-use>
	%VGPR38<def> = V_MOV_B32_e32 %VGPR2, %EXEC<imp-use>
	%VGPR37<def> = V_MOV_B32_e32 %VGPR3, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = S_AND_SAVEEXEC_B64 %SGPR4_SGPR5, %EXEC<imp-def>, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = S_XOR_B64 %EXEC, %SGPR4_SGPR5
	S_CBRANCH_EXECZ <BB#2>, %EXEC
    Successors according to CFG: BB#1(16) BB#2(16)

BB#1: derived from LLVM BB %IF
    Live Ins: %SGPR0_SGPR1_SGPR2_SGPR3 %VGPR20 %VGPR21 %VGPR13 %VGPR9 %VGPR22 %VGPR23 %VGPR14 %VGPR10 %VGPR24 %VGPR25 %VGPR15 %VGPR11 %VGPR26 %VGPR27 %VGPR16 %VGPR12 %VGPR30 %VGPR31 %VGPR19 %VGPR17 %VGPR33 %VGPR34 %VGPR28 %VGPR18 %VGPR35 %VGPR36 %VGPR32 %VGPR29 %VGPR5_VGPR6_VGPR7_VGPR8 %SGPR6_SGPR7 %VGPR0 %VGPR1_VGPR2_VGPR3_VGPR4 %SGPR4_SGPR5
    Predecessors according to CFG: BB#0
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 8; mem:LD16[%63](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%VGPR37_VGPR38_VGPR39_VGPR40<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	%VGPR41<def> = V_MOV_B32_e32 2.550100e+02, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR42<def> = V_MUL_F32_e32 %VGPR37, %VGPR41, %EXEC<imp-use>
	%VGPR42<def> = V_CVT_I32_F32_e32 %VGPR42<kill>, %EXEC<imp-use>
	%VGPR42<def> = V_MUL_LO_I32 3, %VGPR42<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR43<def> = V_ADD_I32_e32 43, %VGPR42, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR43<def> = V_LSHLREV_B32_e32 4, %VGPR43<kill>, %EXEC<imp-use>
	%VGPR44<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR43, %EXEC<imp-use>; mem:LD4[<unknown>]
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 12; mem:LD16[%72](align=8)(tbaa=!"const")
	S_WAITCNT 112
	%VGPR45_VGPR46_VGPR47_VGPR48<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR0<def> = V_MUL_F32_e32 %VGPR44<kill>, %VGPR45, %EXEC<imp-use>
	%VGPR44<def> = V_MUL_F32_e32 %VGPR38, %VGPR41, %EXEC<imp-use>
	%VGPR44<def> = V_CVT_I32_F32_e32 %VGPR44<kill>, %EXEC<imp-use>
	%VGPR44<def> = V_MUL_LO_I32 3, %VGPR44<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR49<def> = V_ADD_I32_e32 43, %VGPR44, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR49<def> = V_LSHLREV_B32_e32 4, %VGPR49<kill>, %EXEC<imp-use>
	%VGPR50<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR49, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR0<def> = V_MAD_F32 %VGPR50<kill>, %VGPR46, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR50<def> = V_MUL_F32_e32 %VGPR39, %VGPR41, %EXEC<imp-use>
	%VGPR50<def> = V_CVT_I32_F32_e32 %VGPR50<kill>, %EXEC<imp-use>
	%VGPR50<def> = V_MUL_LO_I32 3, %VGPR50<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR51<def> = V_ADD_I32_e32 43, %VGPR50, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR51<def> = V_LSHLREV_B32_e32 4, %VGPR51<kill>, %EXEC<imp-use>
	%VGPR52<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR51, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR0<def> = V_MAD_F32 %VGPR52<kill>, %VGPR47, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR52<def> = V_ADD_F32_e32 %VGPR46, %VGPR45, %EXEC<imp-use>
	%VGPR52<def> = V_ADD_F32_e32 %VGPR52<kill>, %VGPR47, %EXEC<imp-use>
	%VGPR52<def> = V_SUB_F32_e32 1.000000e+00, %VGPR52<kill>, %EXEC<imp-use>
	%VGPR37<def> = V_MUL_F32_e32 %VGPR40, %VGPR41<kill>, %EXEC<imp-use>, %VGPR37_VGPR38_VGPR39_VGPR40<imp-use,kill>
	%VGPR37<def> = V_CVT_I32_F32_e32 %VGPR37<kill>, %EXEC<imp-use>
	%VGPR39<def> = V_MUL_LO_I32 3, %VGPR37<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR37<def> = V_ADD_I32_e32 43, %VGPR39, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR37<def> = V_LSHLREV_B32_e32 4, %VGPR37<kill>, %EXEC<imp-use>
	%VGPR38<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR37, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR0<def> = V_MAD_F32 %VGPR38<kill>, %VGPR52, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR38<def> = V_OR_B32_e64 4, %VGPR43, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR38<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR38<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR38<def> = V_MUL_F32_e32 %VGPR38<kill>, %VGPR45, %EXEC<imp-use>
	%VGPR40<def> = V_OR_B32_e64 4, %VGPR49, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR40<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR40<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR38<def> = V_MAD_F32 %VGPR40<kill>, %VGPR46, %VGPR38<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR40<def> = V_OR_B32_e64 4, %VGPR51, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR40<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR40<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR38<def> = V_MAD_F32 %VGPR40<kill>, %VGPR47, %VGPR38<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR40<def> = V_OR_B32_e64 4, %VGPR37, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR40<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR40<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR38<def> = V_MAD_F32 %VGPR40<kill>, %VGPR52, %VGPR38<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR38<def> = V_MUL_F32_e32 %VGPR2, %VGPR38<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR1, %VGPR0<kill>, %VGPR38<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR38<def> = V_OR_B32_e64 8, %VGPR43, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR38<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR38<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR38<def> = V_MUL_F32_e32 %VGPR38<kill>, %VGPR45, %EXEC<imp-use>
	%VGPR40<def> = V_OR_B32_e64 8, %VGPR49, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR40<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR40<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR38<def> = V_MAD_F32 %VGPR40<kill>, %VGPR46, %VGPR38<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR40<def> = V_OR_B32_e64 8, %VGPR51, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR40<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR40<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR38<def> = V_MAD_F32 %VGPR40<kill>, %VGPR47, %VGPR38<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR40<def> = V_OR_B32_e64 8, %VGPR37, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR40<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR40<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR38<def> = V_MAD_F32 %VGPR40<kill>, %VGPR52, %VGPR38<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR3, %VGPR38<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR38<def> = V_OR_B32_e64 12, %VGPR43<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR38<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR38<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR38<def> = V_MUL_F32_e32 %VGPR38<kill>, %VGPR45, %EXEC<imp-use>
	%VGPR40<def> = V_OR_B32_e64 12, %VGPR49<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR40<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR40<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR38<def> = V_MAD_F32 %VGPR40<kill>, %VGPR46, %VGPR38<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR40<def> = V_OR_B32_e64 12, %VGPR51<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR40<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR40<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR38<def> = V_MAD_F32 %VGPR40<kill>, %VGPR47, %VGPR38<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR37<def> = V_OR_B32_e64 12, %VGPR37<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR37<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR37<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR37<def> = V_MAD_F32 %VGPR37<kill>, %VGPR52, %VGPR38<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR37<def> = V_MAD_F32 %VGPR4, %VGPR37<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_I32_e32 42, %VGPR42, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR0<def> = V_LSHLREV_B32_e32 4, %VGPR0<kill>, %EXEC<imp-use>
	%VGPR38<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR0, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR38<def> = V_MUL_F32_e32 %VGPR38<kill>, %VGPR45, %EXEC<imp-use>
	%VGPR40<def> = V_ADD_I32_e32 42, %VGPR44, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR40<def> = V_LSHLREV_B32_e32 4, %VGPR40<kill>, %EXEC<imp-use>
	%VGPR41<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR40, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR38<def> = V_MAD_F32 %VGPR41<kill>, %VGPR46, %VGPR38<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR41<def> = V_ADD_I32_e32 42, %VGPR50, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR41<def> = V_LSHLREV_B32_e32 4, %VGPR41<kill>, %EXEC<imp-use>
	%VGPR43<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR41, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR38<def> = V_MAD_F32 %VGPR43<kill>, %VGPR47, %VGPR38<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR43<def> = V_ADD_I32_e32 42, %VGPR39, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR43<def> = V_LSHLREV_B32_e32 4, %VGPR43<kill>, %EXEC<imp-use>
	%VGPR49<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR43, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR38<def> = V_MAD_F32 %VGPR49<kill>, %VGPR52, %VGPR38<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR49<def> = V_OR_B32_e64 4, %VGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR49<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR49<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR49<def> = V_MUL_F32_e32 %VGPR49<kill>, %VGPR45, %EXEC<imp-use>
	%VGPR51<def> = V_OR_B32_e64 4, %VGPR40, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR51<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR51<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR49<def> = V_MAD_F32 %VGPR51<kill>, %VGPR46, %VGPR49<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR51<def> = V_OR_B32_e64 4, %VGPR41, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR51<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR51<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR49<def> = V_MAD_F32 %VGPR51<kill>, %VGPR47, %VGPR49<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR51<def> = V_OR_B32_e64 4, %VGPR43, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR51<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR51<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR49<def> = V_MAD_F32 %VGPR51<kill>, %VGPR52, %VGPR49<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR49<def> = V_MUL_F32_e32 %VGPR2, %VGPR49<kill>, %EXEC<imp-use>
	%VGPR38<def> = V_MAD_F32 %VGPR1, %VGPR38<kill>, %VGPR49<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR49<def> = V_OR_B32_e64 8, %VGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR49<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR49<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR49<def> = V_MUL_F32_e32 %VGPR49<kill>, %VGPR45, %EXEC<imp-use>
	%VGPR51<def> = V_OR_B32_e64 8, %VGPR40, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR51<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR51<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR49<def> = V_MAD_F32 %VGPR51<kill>, %VGPR46, %VGPR49<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR51<def> = V_OR_B32_e64 8, %VGPR41, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR51<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR51<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR49<def> = V_MAD_F32 %VGPR51<kill>, %VGPR47, %VGPR49<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR51<def> = V_OR_B32_e64 8, %VGPR43, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR51<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR51<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR49<def> = V_MAD_F32 %VGPR51<kill>, %VGPR52, %VGPR49<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR38<def> = V_MAD_F32 %VGPR3, %VGPR49<kill>, %VGPR38<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_OR_B32_e64 12, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR0<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR0<def> = V_MUL_F32_e32 %VGPR0<kill>, %VGPR45, %EXEC<imp-use>
	%VGPR40<def> = V_OR_B32_e64 12, %VGPR40<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR40<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR40<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR0<def> = V_MAD_F32 %VGPR40<kill>, %VGPR46, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR40<def> = V_OR_B32_e64 12, %VGPR41<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR40<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR40<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR0<def> = V_MAD_F32 %VGPR40<kill>, %VGPR47, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR40<def> = V_OR_B32_e64 12, %VGPR43<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR40<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR40<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR0<def> = V_MAD_F32 %VGPR40<kill>, %VGPR52, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR38<def> = V_MAD_F32 %VGPR4, %VGPR0<kill>, %VGPR38<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_I32_e32 41, %VGPR42<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR0<def> = V_LSHLREV_B32_e32 4, %VGPR0<kill>, %EXEC<imp-use>
	%VGPR40<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR0, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR40<def> = V_MUL_F32_e32 %VGPR40<kill>, %VGPR45, %EXEC<imp-use>
	%VGPR41<def> = V_ADD_I32_e32 41, %VGPR44<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR41<def> = V_LSHLREV_B32_e32 4, %VGPR41<kill>, %EXEC<imp-use>
	%VGPR42<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR41, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR40<def> = V_MAD_F32 %VGPR42<kill>, %VGPR46, %VGPR40<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR42<def> = V_ADD_I32_e32 41, %VGPR50<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR42<def> = V_LSHLREV_B32_e32 4, %VGPR42<kill>, %EXEC<imp-use>
	%VGPR43<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR42, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR40<def> = V_MAD_F32 %VGPR43<kill>, %VGPR47, %VGPR40<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR39<def> = V_ADD_I32_e32 41, %VGPR39<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR39<def> = V_LSHLREV_B32_e32 4, %VGPR39<kill>, %EXEC<imp-use>
	%VGPR43<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR39, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR40<def> = V_MAD_F32 %VGPR43<kill>, %VGPR52, %VGPR40<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR43<def> = V_OR_B32_e64 4, %VGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR43<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR43<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR43<def> = V_MUL_F32_e32 %VGPR43<kill>, %VGPR45, %EXEC<imp-use>
	%VGPR44<def> = V_OR_B32_e64 4, %VGPR41, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR44<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR44<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR43<def> = V_MAD_F32 %VGPR44<kill>, %VGPR46, %VGPR43<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR44<def> = V_OR_B32_e64 4, %VGPR42, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR44<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR44<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR43<def> = V_MAD_F32 %VGPR44<kill>, %VGPR47, %VGPR43<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR44<def> = V_OR_B32_e64 4, %VGPR39, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR44<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR44<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR43<def> = V_MAD_F32 %VGPR44<kill>, %VGPR52, %VGPR43<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR43<def> = V_MUL_F32_e32 %VGPR2, %VGPR43<kill>, %EXEC<imp-use>
	%VGPR40<def> = V_MAD_F32 %VGPR1, %VGPR40<kill>, %VGPR43<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR43<def> = V_OR_B32_e64 8, %VGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR43<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR43<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR43<def> = V_MUL_F32_e32 %VGPR43<kill>, %VGPR45, %EXEC<imp-use>
	%VGPR44<def> = V_OR_B32_e64 8, %VGPR41, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR44<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR44<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR43<def> = V_MAD_F32 %VGPR44<kill>, %VGPR46, %VGPR43<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR44<def> = V_OR_B32_e64 8, %VGPR42, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR44<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR44<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR43<def> = V_MAD_F32 %VGPR44<kill>, %VGPR47, %VGPR43<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR44<def> = V_OR_B32_e64 8, %VGPR39, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR44<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR44<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR43<def> = V_MAD_F32 %VGPR44<kill>, %VGPR52, %VGPR43<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR40<def> = V_MAD_F32 %VGPR3, %VGPR43<kill>, %VGPR40<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_OR_B32_e64 12, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR0<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR0<def> = V_MUL_F32_e32 %VGPR0<kill>, %VGPR45, %EXEC<imp-use>
	%VGPR41<def> = V_OR_B32_e64 12, %VGPR41<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR41<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR41<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR0<def> = V_MAD_F32 %VGPR41<kill>, %VGPR46, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR41<def> = V_OR_B32_e64 12, %VGPR42<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR41<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3, %VGPR41<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR0<def> = V_MAD_F32 %VGPR41<kill>, %VGPR47, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR45_VGPR46_VGPR47_VGPR48<imp-use,kill>
	%VGPR39<def> = V_OR_B32_e64 12, %VGPR39<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR39<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %VGPR39<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR0<def> = V_MAD_F32 %VGPR39<kill>, %VGPR52<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR39<def> = V_MAD_F32 %VGPR4, %VGPR0<kill>, %VGPR40<kill>, 0, 0, 0, 0, %EXEC<imp-use>
    Successors according to CFG: BB#2

BB#2: derived from LLVM BB %ENDIF
    Live Ins: %VGPR20 %VGPR21 %VGPR13 %VGPR9 %VGPR22 %VGPR23 %VGPR14 %VGPR10 %VGPR24 %VGPR25 %VGPR15 %VGPR11 %VGPR26 %VGPR27 %VGPR16 %VGPR12 %VGPR30 %VGPR31 %VGPR19 %VGPR17 %VGPR33 %VGPR34 %VGPR28 %VGPR18 %VGPR35 %VGPR36 %VGPR32 %VGPR29 %VGPR5_VGPR6_VGPR7_VGPR8 %VGPR1_VGPR2_VGPR3_VGPR4 %SGPR4_SGPR5 %VGPR39 %VGPR38 %VGPR37
    Predecessors according to CFG: BB#0 BB#1
	%EXEC<def> = S_OR_B64 %EXEC, %SGPR4_SGPR5
	%VGPR0<def> = V_MUL_F32_e64 %VGPR38, %VGPR36<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR39, %VGPR35<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR37, %VGPR32<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR4, %VGPR29<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR29<def> = V_MUL_F32_e64 %VGPR6, %VGPR34<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR29<def> = V_MAD_F32 %VGPR5, %VGPR33<kill>, %VGPR29<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR28<def> = V_MAD_F32 %VGPR7, %VGPR28<kill>, %VGPR29<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR18<def> = V_MAD_F32 %VGPR8, %VGPR18<kill>, %VGPR28<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR28<def> = V_MUL_F32_e64 %VGPR6, %VGPR31<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR28<def> = V_MAD_F32 %VGPR5, %VGPR30<kill>, %VGPR28<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR19<def> = V_MAD_F32 %VGPR7, %VGPR19<kill>, %VGPR28<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR8, %VGPR17<kill>, %VGPR19<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-use,kill>
	%VGPR6<def> = V_MOV_B32_e32 1.000000e+00, %EXEC<imp-use>
	EXP 15, 32, 0, 0, 0, %VGPR5<kill>, %VGPR18<kill>, %VGPR0<kill>, %VGPR6<kill>, %EXEC<imp-use>
	S_WAITCNT 1807
	%VGPR0<def> = V_MUL_F32_e64 %VGPR38, %VGPR27<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR39, %VGPR26<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR37, %VGPR16<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR4, %VGPR12<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_MUL_F32_e64 %VGPR38, %VGPR25<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR39, %VGPR24<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR37, %VGPR15<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR4, %VGPR11<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e64 %VGPR38, %VGPR23<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR39, %VGPR22<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR37, %VGPR14<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR4, %VGPR10<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_MUL_F32_e64 %VGPR38<kill>, %VGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR39<kill>, %VGPR20<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR37<kill>, %VGPR13<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_MAD_F32 %VGPR4, %VGPR9<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR1_VGPR2_VGPR3_VGPR4<imp-use,kill>
	EXP 15, 12, 0, 1, 0, %VGPR1<kill>, %VGPR6<kill>, %VGPR5<kill>, %VGPR0<kill>, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_LOAD_DWORDX4 s[8:11], s[6:7], 4                 ; C0840704
	S_WAITCNT lgkmcnt(0)                              ; BF8C007F
	BUFFER_LOAD_FORMAT_XYZW v[5:8], s[8:11][v0] + 0   ; E00C2000 80020500
	S_LOAD_DWORDX4 s[8:11], s[6:7], 0                 ; C0840700
	S_WAITCNT vmcnt(0) lgkmcnt(0)                     ; BF8C0070
	BUFFER_LOAD_FORMAT_XYZW v[1:4], s[8:11][v0] + 0   ; E00C2000 80020100
	S_LOAD_DWORDX4 s[0:3], s[0:1], 0                  ; C0800100
	S_MOV_B32 s4, 3840                                ; BE8403FF 00000F00
	S_WAITCNT vmcnt(0) lgkmcnt(0)                     ; BF8C0070
	S_BUFFER_LOAD_DWORD s4, s[0:3], s4                ; C2020004
	S_WAITCNT lgkmcnt(0)                              ; BF8C007F
	V_CMP_NE_I32_e64 s[4:5], s4, 0, 0, 0, 0, 0        ; D10A0004 02010004
	S_BUFFER_LOAD_DWORD s8, s[0:3], 39                ; C2040127
	S_BUFFER_LOAD_DWORD s9, s[0:3], 38                ; C2048126
	S_BUFFER_LOAD_DWORD s10, s[0:3], 37               ; C2050125
	S_BUFFER_LOAD_DWORD s11, s[0:3], 36               ; C2058124
	S_BUFFER_LOAD_DWORD s12, s[0:3], 35               ; C2060123
	S_BUFFER_LOAD_DWORD s13, s[0:3], 34               ; C2068122
	S_BUFFER_LOAD_DWORD s14, s[0:3], 33               ; C2070121
	S_BUFFER_LOAD_DWORD s15, s[0:3], 32               ; C2078120
	S_BUFFER_LOAD_DWORD s16, s[0:3], 31               ; C208011F
	S_BUFFER_LOAD_DWORD s17, s[0:3], 30               ; C208811E
	S_BUFFER_LOAD_DWORD s18, s[0:3], 29               ; C209011D
	S_BUFFER_LOAD_DWORD s19, s[0:3], 28               ; C209811C
	S_BUFFER_LOAD_DWORD s20, s[0:3], 15               ; C20A010F
	S_BUFFER_LOAD_DWORD s21, s[0:3], 14               ; C20A810E
	S_BUFFER_LOAD_DWORD s22, s[0:3], 13               ; C20B010D
	S_BUFFER_LOAD_DWORD s23, s[0:3], 12               ; C20B810C
	S_BUFFER_LOAD_DWORD s24, s[0:3], 11               ; C20C010B
	S_BUFFER_LOAD_DWORD s25, s[0:3], 10               ; C20C810A
	S_BUFFER_LOAD_DWORD s26, s[0:3], 9                ; C20D0109
	S_BUFFER_LOAD_DWORD s27, s[0:3], 8                ; C20D8108
	S_BUFFER_LOAD_DWORD s28, s[0:3], 7                ; C20E0107
	S_BUFFER_LOAD_DWORD s29, s[0:3], 6                ; C20E8106
	S_BUFFER_LOAD_DWORD s30, s[0:3], 5                ; C20F0105
	S_BUFFER_LOAD_DWORD s31, s[0:3], 4                ; C20F8104
	S_BUFFER_LOAD_DWORD s32, s[0:3], 3                ; C2100103
	S_BUFFER_LOAD_DWORD s33, s[0:3], 2                ; C2108102
	S_BUFFER_LOAD_DWORD s34, s[0:3], 1                ; C2110101
	S_BUFFER_LOAD_DWORD s35, s[0:3], 0                ; C2118100
	S_WAITCNT lgkmcnt(0)                              ; BF8C007F
	V_MOV_B32_e32 v29, s8                             ; 7E3A0208
	V_MOV_B32_e32 v32, s9                             ; 7E400209
	V_MOV_B32_e32 v36, s10                            ; 7E48020A
	V_MOV_B32_e32 v35, s11                            ; 7E46020B
	V_MOV_B32_e32 v18, s12                            ; 7E24020C
	V_MOV_B32_e32 v28, s13                            ; 7E38020D
	V_MOV_B32_e32 v34, s14                            ; 7E44020E
	V_MOV_B32_e32 v33, s15                            ; 7E42020F
	V_MOV_B32_e32 v17, s16                            ; 7E220210
	V_MOV_B32_e32 v19, s17                            ; 7E260211
	V_MOV_B32_e32 v31, s18                            ; 7E3E0212
	V_MOV_B32_e32 v30, s19                            ; 7E3C0213
	V_MOV_B32_e32 v12, s20                            ; 7E180214
	V_MOV_B32_e32 v16, s21                            ; 7E200215
	V_MOV_B32_e32 v27, s22                            ; 7E360216
	V_MOV_B32_e32 v26, s23                            ; 7E340217
	V_MOV_B32_e32 v11, s24                            ; 7E160218
	V_MOV_B32_e32 v15, s25                            ; 7E1E0219
	V_MOV_B32_e32 v25, s26                            ; 7E32021A
	V_MOV_B32_e32 v24, s27                            ; 7E30021B
	V_MOV_B32_e32 v10, s28                            ; 7E14021C
	V_MOV_B32_e32 v14, s29                            ; 7E1C021D
	V_MOV_B32_e32 v23, s30                            ; 7E2E021E
	V_MOV_B32_e32 v22, s31                            ; 7E2C021F
	V_MOV_B32_e32 v9, s32                             ; 7E120220
	V_MOV_B32_e32 v13, s33                            ; 7E1A0221
	V_MOV_B32_e32 v21, s34                            ; 7E2A0222
	V_MOV_B32_e32 v20, s35                            ; 7E280223
	V_MOV_B32_e32 v39, v1                             ; 7E4E0301
	V_MOV_B32_e32 v38, v2                             ; 7E4C0302
	V_MOV_B32_e32 v37, v3                             ; 7E4A0303
	S_AND_SAVEEXEC_B64 s[4:5], s[4:5]                 ; BE842404
	S_XOR_B64 s[4:5], exec, s[4:5]                    ; 8984047E
	S_CBRANCH_EXECZ ";.BB0_2"                         ; BF880000
	S_LOAD_DWORDX4 s[8:11], s[6:7], 8                 ; C0840708
	S_WAITCNT lgkmcnt(0)                              ; BF8C007F
	BUFFER_LOAD_FORMAT_XYZW v[37:40], s[8:11][v0] + 0 ; E00C2000 80022500
	V_MOV_B32_e32 v41, 2.550100e+02                   ; 7E5202FF 437F028F
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MUL_F32_e32 v42, v37, v41                       ; 10545325
	V_CVT_I32_F32_e32 v42, v42                        ; 7E54112A
	V_MUL_LO_I32 v42, 3, v42, 0, 0, 0, 0, 0           ; D2D6002A 02025483
	V_ADD_I32_e32 v43, 43, v42                        ; 4A5654AB
	V_LSHLREV_B32_e32 v43, 4, v43                     ; 34565684
	BUFFER_LOAD_DWORD v44, s[0:3] + v43               ; E0301000 80002C2B
	S_LOAD_DWORDX4 s[8:11], s[6:7], 12                ; C084070C
	S_WAITCNT vmcnt(0) lgkmcnt(0)                     ; BF8C0070
	BUFFER_LOAD_FORMAT_XYZW v[45:48], s[8:11][v0] + 0 ; E00C2000 80022D00
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MUL_F32_e32 v0, v44, v45                        ; 10005B2C
	V_MUL_F32_e32 v44, v38, v41                       ; 10585326
	V_CVT_I32_F32_e32 v44, v44                        ; 7E58112C
	V_MUL_LO_I32 v44, 3, v44, 0, 0, 0, 0, 0           ; D2D6002C 02025883
	V_ADD_I32_e32 v49, 43, v44                        ; 4A6258AB
	V_LSHLREV_B32_e32 v49, 4, v49                     ; 34626284
	BUFFER_LOAD_DWORD v50, s[0:3] + v49               ; E0301000 80003231
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MAD_F32 v0, v50, v46, v0, 0, 0, 0, 0            ; D2820000 04025D32
	V_MUL_F32_e32 v50, v39, v41                       ; 10645327
	V_CVT_I32_F32_e32 v50, v50                        ; 7E641132
	V_MUL_LO_I32 v50, 3, v50, 0, 0, 0, 0, 0           ; D2D60032 02026483
	V_ADD_I32_e32 v51, 43, v50                        ; 4A6664AB
	V_LSHLREV_B32_e32 v51, 4, v51                     ; 34666684
	BUFFER_LOAD_DWORD v52, s[0:3] + v51               ; E0301000 80003433
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MAD_F32 v0, v52, v47, v0, 0, 0, 0, 0            ; D2820000 04025F34
	V_ADD_F32_e32 v52, v46, v45                       ; 06685B2E
	V_ADD_F32_e32 v52, v52, v47                       ; 06685F34
	V_SUB_F32_e32 v52, 1.000000e+00, v52              ; 086868F2
	V_MUL_F32_e32 v37, v40, v41                       ; 104A5328
	V_CVT_I32_F32_e32 v37, v37                        ; 7E4A1125
	V_MUL_LO_I32 v39, 3, v37, 0, 0, 0, 0, 0           ; D2D60027 02024A83
	V_ADD_I32_e32 v37, 43, v39                        ; 4A4A4EAB
	V_LSHLREV_B32_e32 v37, 4, v37                     ; 344A4A84
	BUFFER_LOAD_DWORD v38, s[0:3] + v37               ; E0301000 80002625
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MAD_F32 v0, v38, v52, v0, 0, 0, 0, 0            ; D2820000 04026926
	V_OR_B32_e64 v38, 4, v43, 0, 0, 0, 0              ; D2380026 02025684
	BUFFER_LOAD_DWORD v38, s[0:3] + v38               ; E0301000 80002626
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MUL_F32_e32 v38, v38, v45                       ; 104C5B26
	V_OR_B32_e64 v40, 4, v49, 0, 0, 0, 0              ; D2380028 02026284
	BUFFER_LOAD_DWORD v40, s[0:3] + v40               ; E0301000 80002828
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MAD_F32 v38, v40, v46, v38, 0, 0, 0, 0          ; D2820026 049A5D28
	V_OR_B32_e64 v40, 4, v51, 0, 0, 0, 0              ; D2380028 02026684
	BUFFER_LOAD_DWORD v40, s[0:3] + v40               ; E0301000 80002828
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MAD_F32 v38, v40, v47, v38, 0, 0, 0, 0          ; D2820026 049A5F28
	V_OR_B32_e64 v40, 4, v37, 0, 0, 0, 0              ; D2380028 02024A84
	BUFFER_LOAD_DWORD v40, s[0:3] + v40               ; E0301000 80002828
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MAD_F32 v38, v40, v52, v38, 0, 0, 0, 0          ; D2820026 049A6928
	V_MUL_F32_e32 v38, v2, v38                        ; 104C4D02
	V_MAD_F32 v0, v1, v0, v38, 0, 0, 0, 0             ; D2820000 049A0101
	V_OR_B32_e64 v38, 8, v43, 0, 0, 0, 0              ; D2380026 02025688
	BUFFER_LOAD_DWORD v38, s[0:3] + v38               ; E0301000 80002626
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MUL_F32_e32 v38, v38, v45                       ; 104C5B26
	V_OR_B32_e64 v40, 8, v49, 0, 0, 0, 0              ; D2380028 02026288
	BUFFER_LOAD_DWORD v40, s[0:3] + v40               ; E0301000 80002828
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MAD_F32 v38, v40, v46, v38, 0, 0, 0, 0          ; D2820026 049A5D28
	V_OR_B32_e64 v40, 8, v51, 0, 0, 0, 0              ; D2380028 02026688
	BUFFER_LOAD_DWORD v40, s[0:3] + v40               ; E0301000 80002828
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MAD_F32 v38, v40, v47, v38, 0, 0, 0, 0          ; D2820026 049A5F28
	V_OR_B32_e64 v40, 8, v37, 0, 0, 0, 0              ; D2380028 02024A88
	BUFFER_LOAD_DWORD v40, s[0:3] + v40               ; E0301000 80002828
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MAD_F32 v38, v40, v52, v38, 0, 0, 0, 0          ; D2820026 049A6928
	V_MAD_F32 v0, v3, v38, v0, 0, 0, 0, 0             ; D2820000 04024D03
	V_OR_B32_e64 v38, 12, v43, 0, 0, 0, 0             ; D2380026 0202568C
	BUFFER_LOAD_DWORD v38, s[0:3] + v38               ; E0301000 80002626
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MUL_F32_e32 v38, v38, v45                       ; 104C5B26
	V_OR_B32_e64 v40, 12, v49, 0, 0, 0, 0             ; D2380028 0202628C
	BUFFER_LOAD_DWORD v40, s[0:3] + v40               ; E0301000 80002828
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MAD_F32 v38, v40, v46, v38, 0, 0, 0, 0          ; D2820026 049A5D28
	V_OR_B32_e64 v40, 12, v51, 0, 0, 0, 0             ; D2380028 0202668C
	BUFFER_LOAD_DWORD v40, s[0:3] + v40               ; E0301000 80002828
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MAD_F32 v38, v40, v47, v38, 0, 0, 0, 0          ; D2820026 049A5F28
	V_OR_B32_e64 v37, 12, v37, 0, 0, 0, 0             ; D2380025 02024A8C
	BUFFER_LOAD_DWORD v37, s[0:3] + v37               ; E0301000 80002525
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MAD_F32 v37, v37, v52, v38, 0, 0, 0, 0          ; D2820025 049A6925
	V_MAD_F32 v37, v4, v37, v0, 0, 0, 0, 0            ; D2820025 04024B04
	V_ADD_I32_e32 v0, 42, v42                         ; 4A0054AA
	V_LSHLREV_B32_e32 v0, 4, v0                       ; 34000084
	BUFFER_LOAD_DWORD v38, s[0:3] + v0                ; E0301000 80002600
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MUL_F32_e32 v38, v38, v45                       ; 104C5B26
	V_ADD_I32_e32 v40, 42, v44                        ; 4A5058AA
	V_LSHLREV_B32_e32 v40, 4, v40                     ; 34505084
	BUFFER_LOAD_DWORD v41, s[0:3] + v40               ; E0301000 80002928
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MAD_F32 v38, v41, v46, v38, 0, 0, 0, 0          ; D2820026 049A5D29
	V_ADD_I32_e32 v41, 42, v50                        ; 4A5264AA
	V_LSHLREV_B32_e32 v41, 4, v41                     ; 34525284
	BUFFER_LOAD_DWORD v43, s[0:3] + v41               ; E0301000 80002B29
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MAD_F32 v38, v43, v47, v38, 0, 0, 0, 0          ; D2820026 049A5F2B
	V_ADD_I32_e32 v43, 42, v39                        ; 4A564EAA
	V_LSHLREV_B32_e32 v43, 4, v43                     ; 34565684
	BUFFER_LOAD_DWORD v49, s[0:3] + v43               ; E0301000 8000312B
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MAD_F32 v38, v49, v52, v38, 0, 0, 0, 0          ; D2820026 049A6931
	V_OR_B32_e64 v49, 4, v0, 0, 0, 0, 0               ; D2380031 02020084
	BUFFER_LOAD_DWORD v49, s[0:3] + v49               ; E0301000 80003131
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MUL_F32_e32 v49, v49, v45                       ; 10625B31
	V_OR_B32_e64 v51, 4, v40, 0, 0, 0, 0              ; D2380033 02025084
	BUFFER_LOAD_DWORD v51, s[0:3] + v51               ; E0301000 80003333
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MAD_F32 v49, v51, v46, v49, 0, 0, 0, 0          ; D2820031 04C65D33
	V_OR_B32_e64 v51, 4, v41, 0, 0, 0, 0              ; D2380033 02025284
	BUFFER_LOAD_DWORD v51, s[0:3] + v51               ; E0301000 80003333
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MAD_F32 v49, v51, v47, v49, 0, 0, 0, 0          ; D2820031 04C65F33
	V_OR_B32_e64 v51, 4, v43, 0, 0, 0, 0              ; D2380033 02025684
	BUFFER_LOAD_DWORD v51, s[0:3] + v51               ; E0301000 80003333
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MAD_F32 v49, v51, v52, v49, 0, 0, 0, 0          ; D2820031 04C66933
	V_MUL_F32_e32 v49, v2, v49                        ; 10626302
	V_MAD_F32 v38, v1, v38, v49, 0, 0, 0, 0           ; D2820026 04C64D01
	V_OR_B32_e64 v49, 8, v0, 0, 0, 0, 0               ; D2380031 02020088
	BUFFER_LOAD_DWORD v49, s[0:3] + v49               ; E0301000 80003131
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MUL_F32_e32 v49, v49, v45                       ; 10625B31
	V_OR_B32_e64 v51, 8, v40, 0, 0, 0, 0              ; D2380033 02025088
	BUFFER_LOAD_DWORD v51, s[0:3] + v51               ; E0301000 80003333
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MAD_F32 v49, v51, v46, v49, 0, 0, 0, 0          ; D2820031 04C65D33
	V_OR_B32_e64 v51, 8, v41, 0, 0, 0, 0              ; D2380033 02025288
	BUFFER_LOAD_DWORD v51, s[0:3] + v51               ; E0301000 80003333
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MAD_F32 v49, v51, v47, v49, 0, 0, 0, 0          ; D2820031 04C65F33
	V_OR_B32_e64 v51, 8, v43, 0, 0, 0, 0              ; D2380033 02025688
	BUFFER_LOAD_DWORD v51, s[0:3] + v51               ; E0301000 80003333
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MAD_F32 v49, v51, v52, v49, 0, 0, 0, 0          ; D2820031 04C66933
	V_MAD_F32 v38, v3, v49, v38, 0, 0, 0, 0           ; D2820026 049A6303
	V_OR_B32_e64 v0, 12, v0, 0, 0, 0, 0               ; D2380000 0202008C
	BUFFER_LOAD_DWORD v0, s[0:3] + v0                 ; E0301000 80000000
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MUL_F32_e32 v0, v0, v45                         ; 10005B00
	V_OR_B32_e64 v40, 12, v40, 0, 0, 0, 0             ; D2380028 0202508C
	BUFFER_LOAD_DWORD v40, s[0:3] + v40               ; E0301000 80002828
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MAD_F32 v0, v40, v46, v0, 0, 0, 0, 0            ; D2820000 04025D28
	V_OR_B32_e64 v40, 12, v41, 0, 0, 0, 0             ; D2380028 0202528C
	BUFFER_LOAD_DWORD v40, s[0:3] + v40               ; E0301000 80002828
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MAD_F32 v0, v40, v47, v0, 0, 0, 0, 0            ; D2820000 04025F28
	V_OR_B32_e64 v40, 12, v43, 0, 0, 0, 0             ; D2380028 0202568C
	BUFFER_LOAD_DWORD v40, s[0:3] + v40               ; E0301000 80002828
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MAD_F32 v0, v40, v52, v0, 0, 0, 0, 0            ; D2820000 04026928
	V_MAD_F32 v38, v4, v0, v38, 0, 0, 0, 0            ; D2820026 049A0104
	V_ADD_I32_e32 v0, 41, v42                         ; 4A0054A9
	V_LSHLREV_B32_e32 v0, 4, v0                       ; 34000084
	BUFFER_LOAD_DWORD v40, s[0:3] + v0                ; E0301000 80002800
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MUL_F32_e32 v40, v40, v45                       ; 10505B28
	V_ADD_I32_e32 v41, 41, v44                        ; 4A5258A9
	V_LSHLREV_B32_e32 v41, 4, v41                     ; 34525284
	BUFFER_LOAD_DWORD v42, s[0:3] + v41               ; E0301000 80002A29
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MAD_F32 v40, v42, v46, v40, 0, 0, 0, 0          ; D2820028 04A25D2A
	V_ADD_I32_e32 v42, 41, v50                        ; 4A5464A9
	V_LSHLREV_B32_e32 v42, 4, v42                     ; 34545484
	BUFFER_LOAD_DWORD v43, s[0:3] + v42               ; E0301000 80002B2A
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MAD_F32 v40, v43, v47, v40, 0, 0, 0, 0          ; D2820028 04A25F2B
	V_ADD_I32_e32 v39, 41, v39                        ; 4A4E4EA9
	V_LSHLREV_B32_e32 v39, 4, v39                     ; 344E4E84
	BUFFER_LOAD_DWORD v43, s[0:3] + v39               ; E0301000 80002B27
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MAD_F32 v40, v43, v52, v40, 0, 0, 0, 0          ; D2820028 04A2692B
	V_OR_B32_e64 v43, 4, v0, 0, 0, 0, 0               ; D238002B 02020084
	BUFFER_LOAD_DWORD v43, s[0:3] + v43               ; E0301000 80002B2B
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MUL_F32_e32 v43, v43, v45                       ; 10565B2B
	V_OR_B32_e64 v44, 4, v41, 0, 0, 0, 0              ; D238002C 02025284
	BUFFER_LOAD_DWORD v44, s[0:3] + v44               ; E0301000 80002C2C
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MAD_F32 v43, v44, v46, v43, 0, 0, 0, 0          ; D282002B 04AE5D2C
	V_OR_B32_e64 v44, 4, v42, 0, 0, 0, 0              ; D238002C 02025484
	BUFFER_LOAD_DWORD v44, s[0:3] + v44               ; E0301000 80002C2C
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MAD_F32 v43, v44, v47, v43, 0, 0, 0, 0          ; D282002B 04AE5F2C
	V_OR_B32_e64 v44, 4, v39, 0, 0, 0, 0              ; D238002C 02024E84
	BUFFER_LOAD_DWORD v44, s[0:3] + v44               ; E0301000 80002C2C
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MAD_F32 v43, v44, v52, v43, 0, 0, 0, 0          ; D282002B 04AE692C
	V_MUL_F32_e32 v43, v2, v43                        ; 10565702
	V_MAD_F32 v40, v1, v40, v43, 0, 0, 0, 0           ; D2820028 04AE5101
	V_OR_B32_e64 v43, 8, v0, 0, 0, 0, 0               ; D238002B 02020088
	BUFFER_LOAD_DWORD v43, s[0:3] + v43               ; E0301000 80002B2B
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MUL_F32_e32 v43, v43, v45                       ; 10565B2B
	V_OR_B32_e64 v44, 8, v41, 0, 0, 0, 0              ; D238002C 02025288
	BUFFER_LOAD_DWORD v44, s[0:3] + v44               ; E0301000 80002C2C
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MAD_F32 v43, v44, v46, v43, 0, 0, 0, 0          ; D282002B 04AE5D2C
	V_OR_B32_e64 v44, 8, v42, 0, 0, 0, 0              ; D238002C 02025488
	BUFFER_LOAD_DWORD v44, s[0:3] + v44               ; E0301000 80002C2C
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MAD_F32 v43, v44, v47, v43, 0, 0, 0, 0          ; D282002B 04AE5F2C
	V_OR_B32_e64 v44, 8, v39, 0, 0, 0, 0              ; D238002C 02024E88
	BUFFER_LOAD_DWORD v44, s[0:3] + v44               ; E0301000 80002C2C
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MAD_F32 v43, v44, v52, v43, 0, 0, 0, 0          ; D282002B 04AE692C
	V_MAD_F32 v40, v3, v43, v40, 0, 0, 0, 0           ; D2820028 04A25703
	V_OR_B32_e64 v0, 12, v0, 0, 0, 0, 0               ; D2380000 0202008C
	BUFFER_LOAD_DWORD v0, s[0:3] + v0                 ; E0301000 80000000
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MUL_F32_e32 v0, v0, v45                         ; 10005B00
	V_OR_B32_e64 v41, 12, v41, 0, 0, 0, 0             ; D2380029 0202528C
	BUFFER_LOAD_DWORD v41, s[0:3] + v41               ; E0301000 80002929
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MAD_F32 v0, v41, v46, v0, 0, 0, 0, 0            ; D2820000 04025D29
	V_OR_B32_e64 v41, 12, v42, 0, 0, 0, 0             ; D2380029 0202548C
	BUFFER_LOAD_DWORD v41, s[0:3] + v41               ; E0301000 80002929
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MAD_F32 v0, v41, v47, v0, 0, 0, 0, 0            ; D2820000 04025F29
	V_OR_B32_e64 v39, 12, v39, 0, 0, 0, 0             ; D2380027 02024E8C
	BUFFER_LOAD_DWORD v39, s[0:3] + v39               ; E0301000 80002727
	S_WAITCNT vmcnt(0)                                ; BF8C0770
	V_MAD_F32 v0, v39, v52, v0, 0, 0, 0, 0            ; D2820000 04026927
	V_MAD_F32 v39, v4, v0, v40, 0, 0, 0, 0            ; D2820027 04A20104
	S_OR_B64 exec, exec, s[4:5]                       ; 88FE047E
	V_MUL_F32_e64 v0, v38, v36, 0, 0, 0, 0            ; D2100000 02024926
	V_MAD_F32 v0, v39, v35, v0, 0, 0, 0, 0            ; D2820000 04024727
	V_MAD_F32 v0, v37, v32, v0, 0, 0, 0, 0            ; D2820000 04024125
	V_MAD_F32 v0, v4, v29, v0, 0, 0, 0, 0             ; D2820000 04023B04
	V_MUL_F32_e64 v29, v6, v34, 0, 0, 0, 0            ; D210001D 02024506
	V_MAD_F32 v29, v5, v33, v29, 0, 0, 0, 0           ; D282001D 04764305
	V_MAD_F32 v28, v7, v28, v29, 0, 0, 0, 0           ; D282001C 04763907
	V_MAD_F32 v18, v8, v18, v28, 0, 0, 0, 0           ; D2820012 04722508
	V_MUL_F32_e64 v28, v6, v31, 0, 0, 0, 0            ; D210001C 02023F06
	V_MAD_F32 v28, v5, v30, v28, 0, 0, 0, 0           ; D282001C 04723D05
	V_MAD_F32 v19, v7, v19, v28, 0, 0, 0, 0           ; D2820013 04722707
	V_MAD_F32 v5, v8, v17, v19, 0, 0, 0, 0            ; D2820005 044E2308
	V_MOV_B32_e32 v6, 1.000000e+00                    ; 7E0C02F2
	EXP 15, 32, 0, 0, 0, v5, v18, v0, v6              ; F800020F 06001205
	S_WAITCNT expcnt(0)                               ; BF8C070F
	V_MUL_F32_e64 v0, v38, v27, 0, 0, 0, 0            ; D2100000 02023726
	V_MAD_F32 v0, v39, v26, v0, 0, 0, 0, 0            ; D2820000 04023527
	V_MAD_F32 v0, v37, v16, v0, 0, 0, 0, 0            ; D2820000 04022125
	V_MAD_F32 v0, v4, v12, v0, 0, 0, 0, 0             ; D2820000 04021904
	V_MUL_F32_e64 v5, v38, v25, 0, 0, 0, 0            ; D2100005 02023326
	V_MAD_F32 v5, v39, v24, v5, 0, 0, 0, 0            ; D2820005 04163127
	V_MAD_F32 v5, v37, v15, v5, 0, 0, 0, 0            ; D2820005 04161F25
	V_MAD_F32 v5, v4, v11, v5, 0, 0, 0, 0             ; D2820005 04161704
	V_MUL_F32_e64 v6, v38, v23, 0, 0, 0, 0            ; D2100006 02022F26
	V_MAD_F32 v6, v39, v22, v6, 0, 0, 0, 0            ; D2820006 041A2D27
	V_MAD_F32 v6, v37, v14, v6, 0, 0, 0, 0            ; D2820006 041A1D25
	V_MAD_F32 v6, v4, v10, v6, 0, 0, 0, 0             ; D2820006 041A1504
	V_MUL_F32_e64 v7, v38, v21, 0, 0, 0, 0            ; D2100007 02022B26
	V_MAD_F32 v7, v39, v20, v7, 0, 0, 0, 0            ; D2820007 041E2927
	V_MAD_F32 v7, v37, v13, v7, 0, 0, 0, 0            ; D2820007 041E1B25
	V_MAD_F32 v1, v4, v9, v7, 0, 0, 0, 0              ; D2820001 041E1304
	EXP 15, 12, 0, 1, 0, v1, v6, v5, v0               ; F80008CF 00050601
	S_ENDPGM                                          ; BF810000

FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL OUT[0], COLOR
DCL CONST[0..13]
DCL TEMP[0], LOCAL
IMM[0] FLT32 {    1.0000,     0.0000,     0.0000,     0.0000}
  0: MOV TEMP[0].w, IMM[0].xxxx
  1: MOV TEMP[0].z, IMM[0].yyyy
  2: MAD TEMP[0].x, IN[0].zzzz, CONST[0].zzzz, CONST[0].yyyy
  3: MOV_SAT TEMP[0].x, TEMP[0].xxxx
  4: MOV TEMP[0].x, TEMP[0].xxxx
  5: MUL TEMP[0].x, TEMP[0].xxxx, CONST[0].wwww
  6: MOV TEMP[0].y, IMM[0].yyyy
  7: MOV OUT[0], TEMP[0]
  8: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %21 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
  %22 = load <16 x i8> addrspace(2)* %21, !tbaa !0
  %23 = call float @llvm.SI.load.const(<16 x i8> %22, i32 4)
  %24 = call float @llvm.SI.load.const(<16 x i8> %22, i32 8)
  %25 = call float @llvm.SI.load.const(<16 x i8> %22, i32 12)
  %26 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %4, <2 x i32> %6)
  %27 = fmul float %26, %24
  %28 = fadd float %27, %23
  %29 = call float @llvm.AMDIL.clamp.(float %28, float 0.000000e+00, float 1.000000e+00)
  %30 = fmul float %29, %25
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %30, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR7 in %vreg4, %VGPR0 in %vreg5, %VGPR1 in %vreg6

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR7 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR7
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<kill,tied0>, %VGPR1, 2, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%22](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2; mem:LD4[<unknown>]
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR0<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR2<kill>, %SGPR4<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_F32_e64 0, %VGPR0<kill>, 0, 1, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 3; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR0<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_MOV_B32_e32 1.000000e+00, %EXEC<imp-use>
	%VGPR2<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	EXP 15, 0, 0, 1, 1, %VGPR0<kill>, %VGPR2<kill>, %VGPR2, %VGPR1<kill>, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_WQM_B64 exec, exec                     ; BEFE0A7E
	S_MOV_B32 m0, s7                         ; BEFC0307
	V_INTERP_P1_F32 v2, v0, 2, 0, [m0]       ; C8080200
	V_INTERP_P2_F32 v2, [v2], v1, 2, 0, [m0] ; C8090201
	S_LOAD_DWORDX4 s[0:3], s[0:1], 0         ; C0800100
	S_WAITCNT lgkmcnt(0)                     ; BF8C007F
	S_BUFFER_LOAD_DWORD s4, s[0:3], 2        ; C2020102
	S_BUFFER_LOAD_DWORD s5, s[0:3], 1        ; C2028101
	S_WAITCNT lgkmcnt(0)                     ; BF8C007F
	V_MOV_B32_e32 v0, s5                     ; 7E000205
	V_MAD_F32 v0, v2, s4, v0, 0, 0, 0, 0     ; D2820000 04000902
	V_ADD_F32_e64 v0, 0, v0, 0, 1, 0, 0      ; D2060800 02020080
	S_BUFFER_LOAD_DWORD s0, s[0:3], 3        ; C2000103
	S_WAITCNT lgkmcnt(0)                     ; BF8C007F
	V_MUL_F32_e32 v0, s0, v0                 ; 10000000
	V_MOV_B32_e32 v1, 1.000000e+00           ; 7E0202F2
	V_MOV_B32_e32 v2, 0.000000e+00           ; 7E040280
	EXP 15, 0, 0, 1, 1, v0, v2, v2, v1       ; F800180F 01020200
	S_ENDPGM                                 ; BF810000

VERT
DCL IN[0]
DCL IN[1]
DCL IN[2]
DCL IN[3]
DCL OUT[0], POSITION
DCL OUT[1], CLIPVERTEX
DCL OUT[2], GENERIC[19]
DCL CONST[0..240]
DCL TEMP[0..7], LOCAL
DCL ADDR[0]
IMM[0] FLT32 {    1.0000,   255.0100,     0.0000,     0.0000}
IMM[1] INT32 {3, 41, 42, 43}
  0: MOV TEMP[0], IN[0]
  1: UIF CONST[240].xxxx :0
  2:   DP3 TEMP[1].x, IN[3].xyzz, IMM[0].xxxx
  3:   ADD TEMP[1].x, IMM[0].xxxx, -TEMP[1].xxxx
  4:   MUL TEMP[2], IN[2], IMM[0].yyyy
  5:   F2I TEMP[2], TEMP[2]
  6:   UMAD TEMP[3].x, TEMP[2].wwww, IMM[1].xxxx, IMM[1].yyyy
  7:   UMAD TEMP[4].x, TEMP[2].zzzz, IMM[1].xxxx, IMM[1].yyyy
  8:   UMAD TEMP[5].x, TEMP[2].yyyy, IMM[1].xxxx, IMM[1].yyyy
  9:   UMAD TEMP[6].x, TEMP[2].xxxx, IMM[1].xxxx, IMM[1].yyyy
 10:   UARL ADDR[0].x, TEMP[6].xxxx
 11:   MUL TEMP[6], CONST[ADDR[0].x], IN[3].xxxx
 12:   UARL ADDR[0].x, TEMP[5].xxxx
 13:   MAD TEMP[5], CONST[ADDR[0].x], IN[3].yyyy, TEMP[6]
 14:   UARL ADDR[0].x, TEMP[4].xxxx
 15:   MAD TEMP[4], CONST[ADDR[0].x], IN[3].zzzz, TEMP[5]
 16:   UARL ADDR[0].x, TEMP[3].xxxx
 17:   MAD TEMP[3], CONST[ADDR[0].x], TEMP[1].xxxx, TEMP[4]
 18:   DP4 TEMP[3].x, IN[0], TEMP[3]
 19:   UMAD TEMP[4].x, TEMP[2].wwww, IMM[1].xxxx, IMM[1].zzzz
 20:   UMAD TEMP[5].x, TEMP[2].zzzz, IMM[1].xxxx, IMM[1].zzzz
 21:   UMAD TEMP[6].x, TEMP[2].yyyy, IMM[1].xxxx, IMM[1].zzzz
 22:   UMAD TEMP[7].x, TEMP[2].xxxx, IMM[1].xxxx, IMM[1].zzzz
 23:   UARL ADDR[0].x, TEMP[7].xxxx
 24:   MUL TEMP[7], CONST[ADDR[0].x], IN[3].xxxx
 25:   UARL ADDR[0].x, TEMP[6].xxxx
 26:   MAD TEMP[6], CONST[ADDR[0].x], IN[3].yyyy, TEMP[7]
 27:   UARL ADDR[0].x, TEMP[5].xxxx
 28:   MAD TEMP[5], CONST[ADDR[0].x], IN[3].zzzz, TEMP[6]
 29:   UARL ADDR[0].x, TEMP[4].xxxx
 30:   MAD TEMP[4], CONST[ADDR[0].x], TEMP[1].xxxx, TEMP[5]
 31:   DP4 TEMP[4].x, IN[0], TEMP[4]
 32:   MOV TEMP[3].y, TEMP[4].xxxx
 33:   UMAD TEMP[4].x, TEMP[2].wwww, IMM[1].xxxx, IMM[1].wwww
 34:   UMAD TEMP[5].x, TEMP[2].zzzz, IMM[1].xxxx, IMM[1].wwww
 35:   UMAD TEMP[6].x, TEMP[2].yyyy, IMM[1].xxxx, IMM[1].wwww
 36:   UMAD TEMP[2].x, TEMP[2].xxxx, IMM[1].xxxx, IMM[1].wwww
 37:   UARL ADDR[0].x, TEMP[2].xxxx
 38:   MUL TEMP[2], CONST[ADDR[0].x], IN[3].xxxx
 39:   UARL ADDR[0].x, TEMP[6].xxxx
 40:   MAD TEMP[2], CONST[ADDR[0].x], IN[3].yyyy, TEMP[2]
 41:   UARL ADDR[0].x, TEMP[5].xxxx
 42:   MAD TEMP[2], CONST[ADDR[0].x], IN[3].zzzz, TEMP[2]
 43:   UARL ADDR[0].x, TEMP[4].xxxx
 44:   MAD TEMP[1], CONST[ADDR[0].x], TEMP[1].xxxx, TEMP[2]
 45:   DP4 TEMP[1].x, IN[0], TEMP[1]
 46:   MOV TEMP[3].z, TEMP[1].xxxx
 47:   MOV TEMP[0].xyz, TEMP[3].xyzx
 48: ENDIF
 49: DP4 TEMP[1].x, TEMP[0], CONST[0]
 50: DP4 TEMP[2].x, TEMP[0], CONST[1]
 51: MOV TEMP[1].y, TEMP[2].xxxx
 52: DP4 TEMP[2].x, TEMP[0], CONST[2]
 53: MOV TEMP[1].z, TEMP[2].xxxx
 54: DP4 TEMP[2].x, TEMP[0], CONST[3]
 55: MOV TEMP[1].w, TEMP[2].xxxx
 56: DP4 TEMP[0].x, TEMP[0], CONST[9]
 57: MOV TEMP[0].z, TEMP[0].xxxx
 58: DP4 TEMP[2].x, IN[1], CONST[7]
 59: DP4 TEMP[3].x, IN[1], CONST[8]
 60: MOV TEMP[2].y, TEMP[3].xxxx
 61: MOV TEMP[0].xy, TEMP[2].xyxx
 62: MOV TEMP[0].w, IMM[0].xxxx
 63: MOV OUT[0], TEMP[1]
 64: MOV OUT[2], TEMP[0]
 65: MOV OUT[1], TEMP[1]
 66: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0)
  %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4)
  %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8)
  %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12)
  %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16)
  %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20)
  %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24)
  %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28)
  %20 = call float @llvm.SI.load.const(<16 x i8> %11, i32 32)
  %21 = call float @llvm.SI.load.const(<16 x i8> %11, i32 36)
  %22 = call float @llvm.SI.load.const(<16 x i8> %11, i32 40)
  %23 = call float @llvm.SI.load.const(<16 x i8> %11, i32 44)
  %24 = call float @llvm.SI.load.const(<16 x i8> %11, i32 48)
  %25 = call float @llvm.SI.load.const(<16 x i8> %11, i32 52)
  %26 = call float @llvm.SI.load.const(<16 x i8> %11, i32 56)
  %27 = call float @llvm.SI.load.const(<16 x i8> %11, i32 60)
  %28 = call float @llvm.SI.load.const(<16 x i8> %11, i32 112)
  %29 = call float @llvm.SI.load.const(<16 x i8> %11, i32 116)
  %30 = call float @llvm.SI.load.const(<16 x i8> %11, i32 120)
  %31 = call float @llvm.SI.load.const(<16 x i8> %11, i32 124)
  %32 = call float @llvm.SI.load.const(<16 x i8> %11, i32 128)
  %33 = call float @llvm.SI.load.const(<16 x i8> %11, i32 132)
  %34 = call float @llvm.SI.load.const(<16 x i8> %11, i32 136)
  %35 = call float @llvm.SI.load.const(<16 x i8> %11, i32 140)
  %36 = call float @llvm.SI.load.const(<16 x i8> %11, i32 144)
  %37 = call float @llvm.SI.load.const(<16 x i8> %11, i32 148)
  %38 = call float @llvm.SI.load.const(<16 x i8> %11, i32 152)
  %39 = call float @llvm.SI.load.const(<16 x i8> %11, i32 156)
  %40 = call float @llvm.SI.load.const(<16 x i8> %11, i32 3840)
  %41 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0
  %42 = load <16 x i8> addrspace(2)* %41, !tbaa !0
  %43 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %42, i32 0, i32 %6)
  %44 = extractelement <4 x float> %43, i32 0
  %45 = extractelement <4 x float> %43, i32 1
  %46 = extractelement <4 x float> %43, i32 2
  %47 = extractelement <4 x float> %43, i32 3
  %48 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 1
  %49 = load <16 x i8> addrspace(2)* %48, !tbaa !0
  %50 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %49, i32 0, i32 %6)
  %51 = extractelement <4 x float> %50, i32 0
  %52 = extractelement <4 x float> %50, i32 1
  %53 = extractelement <4 x float> %50, i32 2
  %54 = extractelement <4 x float> %50, i32 3
  %55 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 2
  %56 = load <16 x i8> addrspace(2)* %55, !tbaa !0
  %57 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %56, i32 0, i32 %6)
  %58 = extractelement <4 x float> %57, i32 0
  %59 = extractelement <4 x float> %57, i32 1
  %60 = extractelement <4 x float> %57, i32 2
  %61 = extractelement <4 x float> %57, i32 3
  %62 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 3
  %63 = load <16 x i8> addrspace(2)* %62, !tbaa !0
  %64 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %63, i32 0, i32 %6)
  %65 = extractelement <4 x float> %64, i32 0
  %66 = extractelement <4 x float> %64, i32 1
  %67 = extractelement <4 x float> %64, i32 2
  %68 = bitcast float %40 to i32
  %69 = icmp ne i32 %68, 0
  br i1 %69, label %IF, label %ENDIF

IF:                                               ; preds = %main_body
  %70 = fmul float %65, 1.000000e+00
  %71 = fmul float %66, 1.000000e+00
  %72 = fadd float %71, %70
  %73 = fmul float %67, 1.000000e+00
  %74 = fadd float %72, %73
  %75 = fsub float -0.000000e+00, %74
  %76 = fadd float 1.000000e+00, %75
  %77 = fmul float %58, 0x406FE051E0000000
  %78 = fmul float %59, 0x406FE051E0000000
  %79 = fmul float %60, 0x406FE051E0000000
  %80 = fmul float %61, 0x406FE051E0000000
  %81 = fptosi float %77 to i32
  %82 = fptosi float %78 to i32
  %83 = fptosi float %79 to i32
  %84 = fptosi float %80 to i32
  %85 = bitcast i32 %81 to float
  %86 = bitcast i32 %82 to float
  %87 = bitcast i32 %83 to float
  %88 = bitcast i32 %84 to float
  %89 = bitcast float %88 to i32
  %90 = mul i32 %89, 3
  %91 = add i32 %90, 41
  %92 = bitcast i32 %91 to float
  %93 = bitcast float %87 to i32
  %94 = mul i32 %93, 3
  %95 = add i32 %94, 41
  %96 = bitcast i32 %95 to float
  %97 = bitcast float %86 to i32
  %98 = mul i32 %97, 3
  %99 = add i32 %98, 41
  %100 = bitcast i32 %99 to float
  %101 = bitcast float %85 to i32
  %102 = mul i32 %101, 3
  %103 = add i32 %102, 41
  %104 = bitcast i32 %103 to float
  %105 = bitcast float %104 to i32
  %106 = shl i32 %105, 4
  %107 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %106)
  %108 = fmul float %107, %65
  %109 = shl i32 %105, 4
  %110 = add i32 %109, 4
  %111 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %110)
  %112 = fmul float %111, %65
  %113 = shl i32 %105, 4
  %114 = add i32 %113, 8
  %115 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %114)
  %116 = fmul float %115, %65
  %117 = shl i32 %105, 4
  %118 = add i32 %117, 12
  %119 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %118)
  %120 = fmul float %119, %65
  %121 = bitcast float %100 to i32
  %122 = shl i32 %121, 4
  %123 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %122)
  %124 = fmul float %123, %66
  %125 = fadd float %124, %108
  %126 = shl i32 %121, 4
  %127 = add i32 %126, 4
  %128 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %127)
  %129 = fmul float %128, %66
  %130 = fadd float %129, %112
  %131 = shl i32 %121, 4
  %132 = add i32 %131, 8
  %133 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %132)
  %134 = fmul float %133, %66
  %135 = fadd float %134, %116
  %136 = shl i32 %121, 4
  %137 = add i32 %136, 12
  %138 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %137)
  %139 = fmul float %138, %66
  %140 = fadd float %139, %120
  %141 = bitcast float %96 to i32
  %142 = shl i32 %141, 4
  %143 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %142)
  %144 = fmul float %143, %67
  %145 = fadd float %144, %125
  %146 = shl i32 %141, 4
  %147 = add i32 %146, 4
  %148 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %147)
  %149 = fmul float %148, %67
  %150 = fadd float %149, %130
  %151 = shl i32 %141, 4
  %152 = add i32 %151, 8
  %153 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %152)
  %154 = fmul float %153, %67
  %155 = fadd float %154, %135
  %156 = shl i32 %141, 4
  %157 = add i32 %156, 12
  %158 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %157)
  %159 = fmul float %158, %67
  %160 = fadd float %159, %140
  %161 = bitcast float %92 to i32
  %162 = shl i32 %161, 4
  %163 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %162)
  %164 = fmul float %163, %76
  %165 = fadd float %164, %145
  %166 = shl i32 %161, 4
  %167 = add i32 %166, 4
  %168 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %167)
  %169 = fmul float %168, %76
  %170 = fadd float %169, %150
  %171 = shl i32 %161, 4
  %172 = add i32 %171, 8
  %173 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %172)
  %174 = fmul float %173, %76
  %175 = fadd float %174, %155
  %176 = shl i32 %161, 4
  %177 = add i32 %176, 12
  %178 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %177)
  %179 = fmul float %178, %76
  %180 = fadd float %179, %160
  %181 = fmul float %44, %165
  %182 = fmul float %45, %170
  %183 = fadd float %181, %182
  %184 = fmul float %46, %175
  %185 = fadd float %183, %184
  %186 = fmul float %47, %180
  %187 = fadd float %185, %186
  %188 = bitcast float %88 to i32
  %189 = mul i32 %188, 3
  %190 = add i32 %189, 42
  %191 = bitcast i32 %190 to float
  %192 = bitcast float %87 to i32
  %193 = mul i32 %192, 3
  %194 = add i32 %193, 42
  %195 = bitcast i32 %194 to float
  %196 = bitcast float %86 to i32
  %197 = mul i32 %196, 3
  %198 = add i32 %197, 42
  %199 = bitcast i32 %198 to float
  %200 = bitcast float %85 to i32
  %201 = mul i32 %200, 3
  %202 = add i32 %201, 42
  %203 = bitcast i32 %202 to float
  %204 = bitcast float %203 to i32
  %205 = shl i32 %204, 4
  %206 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %205)
  %207 = fmul float %206, %65
  %208 = shl i32 %204, 4
  %209 = add i32 %208, 4
  %210 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %209)
  %211 = fmul float %210, %65
  %212 = shl i32 %204, 4
  %213 = add i32 %212, 8
  %214 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %213)
  %215 = fmul float %214, %65
  %216 = shl i32 %204, 4
  %217 = add i32 %216, 12
  %218 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %217)
  %219 = fmul float %218, %65
  %220 = bitcast float %199 to i32
  %221 = shl i32 %220, 4
  %222 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %221)
  %223 = fmul float %222, %66
  %224 = fadd float %223, %207
  %225 = shl i32 %220, 4
  %226 = add i32 %225, 4
  %227 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %226)
  %228 = fmul float %227, %66
  %229 = fadd float %228, %211
  %230 = shl i32 %220, 4
  %231 = add i32 %230, 8
  %232 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %231)
  %233 = fmul float %232, %66
  %234 = fadd float %233, %215
  %235 = shl i32 %220, 4
  %236 = add i32 %235, 12
  %237 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %236)
  %238 = fmul float %237, %66
  %239 = fadd float %238, %219
  %240 = bitcast float %195 to i32
  %241 = shl i32 %240, 4
  %242 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %241)
  %243 = fmul float %242, %67
  %244 = fadd float %243, %224
  %245 = shl i32 %240, 4
  %246 = add i32 %245, 4
  %247 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %246)
  %248 = fmul float %247, %67
  %249 = fadd float %248, %229
  %250 = shl i32 %240, 4
  %251 = add i32 %250, 8
  %252 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %251)
  %253 = fmul float %252, %67
  %254 = fadd float %253, %234
  %255 = shl i32 %240, 4
  %256 = add i32 %255, 12
  %257 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %256)
  %258 = fmul float %257, %67
  %259 = fadd float %258, %239
  %260 = bitcast float %191 to i32
  %261 = shl i32 %260, 4
  %262 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %261)
  %263 = fmul float %262, %76
  %264 = fadd float %263, %244
  %265 = shl i32 %260, 4
  %266 = add i32 %265, 4
  %267 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %266)
  %268 = fmul float %267, %76
  %269 = fadd float %268, %249
  %270 = shl i32 %260, 4
  %271 = add i32 %270, 8
  %272 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %271)
  %273 = fmul float %272, %76
  %274 = fadd float %273, %254
  %275 = shl i32 %260, 4
  %276 = add i32 %275, 12
  %277 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %276)
  %278 = fmul float %277, %76
  %279 = fadd float %278, %259
  %280 = fmul float %44, %264
  %281 = fmul float %45, %269
  %282 = fadd float %280, %281
  %283 = fmul float %46, %274
  %284 = fadd float %282, %283
  %285 = fmul float %47, %279
  %286 = fadd float %284, %285
  %287 = bitcast float %88 to i32
  %288 = mul i32 %287, 3
  %289 = add i32 %288, 43
  %290 = bitcast i32 %289 to float
  %291 = bitcast float %87 to i32
  %292 = mul i32 %291, 3
  %293 = add i32 %292, 43
  %294 = bitcast i32 %293 to float
  %295 = bitcast float %86 to i32
  %296 = mul i32 %295, 3
  %297 = add i32 %296, 43
  %298 = bitcast i32 %297 to float
  %299 = bitcast float %85 to i32
  %300 = mul i32 %299, 3
  %301 = add i32 %300, 43
  %302 = bitcast i32 %301 to float
  %303 = bitcast float %302 to i32
  %304 = shl i32 %303, 4
  %305 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %304)
  %306 = fmul float %305, %65
  %307 = shl i32 %303, 4
  %308 = add i32 %307, 4
  %309 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %308)
  %310 = fmul float %309, %65
  %311 = shl i32 %303, 4
  %312 = add i32 %311, 8
  %313 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %312)
  %314 = fmul float %313, %65
  %315 = shl i32 %303, 4
  %316 = add i32 %315, 12
  %317 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %316)
  %318 = fmul float %317, %65
  %319 = bitcast float %298 to i32
  %320 = shl i32 %319, 4
  %321 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %320)
  %322 = fmul float %321, %66
  %323 = fadd float %322, %306
  %324 = shl i32 %319, 4
  %325 = add i32 %324, 4
  %326 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %325)
  %327 = fmul float %326, %66
  %328 = fadd float %327, %310
  %329 = shl i32 %319, 4
  %330 = add i32 %329, 8
  %331 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %330)
  %332 = fmul float %331, %66
  %333 = fadd float %332, %314
  %334 = shl i32 %319, 4
  %335 = add i32 %334, 12
  %336 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %335)
  %337 = fmul float %336, %66
  %338 = fadd float %337, %318
  %339 = bitcast float %294 to i32
  %340 = shl i32 %339, 4
  %341 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %340)
  %342 = fmul float %341, %67
  %343 = fadd float %342, %323
  %344 = shl i32 %339, 4
  %345 = add i32 %344, 4
  %346 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %345)
  %347 = fmul float %346, %67
  %348 = fadd float %347, %328
  %349 = shl i32 %339, 4
  %350 = add i32 %349, 8
  %351 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %350)
  %352 = fmul float %351, %67
  %353 = fadd float %352, %333
  %354 = shl i32 %339, 4
  %355 = add i32 %354, 12
  %356 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %355)
  %357 = fmul float %356, %67
  %358 = fadd float %357, %338
  %359 = bitcast float %290 to i32
  %360 = shl i32 %359, 4
  %361 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %360)
  %362 = fmul float %361, %76
  %363 = fadd float %362, %343
  %364 = shl i32 %359, 4
  %365 = add i32 %364, 4
  %366 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %365)
  %367 = fmul float %366, %76
  %368 = fadd float %367, %348
  %369 = shl i32 %359, 4
  %370 = add i32 %369, 8
  %371 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %370)
  %372 = fmul float %371, %76
  %373 = fadd float %372, %353
  %374 = shl i32 %359, 4
  %375 = add i32 %374, 12
  %376 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %375)
  %377 = fmul float %376, %76
  %378 = fadd float %377, %358
  %379 = fmul float %44, %363
  %380 = fmul float %45, %368
  %381 = fadd float %379, %380
  %382 = fmul float %46, %373
  %383 = fadd float %381, %382
  %384 = fmul float %47, %378
  %385 = fadd float %383, %384
  br label %ENDIF

ENDIF:                                            ; preds = %main_body, %IF
  %temp.0 = phi float [ %187, %IF ], [ %44, %main_body ]
  %temp1.0 = phi float [ %286, %IF ], [ %45, %main_body ]
  %temp2.0 = phi float [ %385, %IF ], [ %46, %main_body ]
  %386 = fmul float %temp.0, %12
  %387 = fmul float %temp1.0, %13
  %388 = fadd float %386, %387
  %389 = fmul float %temp2.0, %14
  %390 = fadd float %388, %389
  %391 = fmul float %47, %15
  %392 = fadd float %390, %391
  %393 = fmul float %temp.0, %16
  %394 = fmul float %temp1.0, %17
  %395 = fadd float %393, %394
  %396 = fmul float %temp2.0, %18
  %397 = fadd float %395, %396
  %398 = fmul float %47, %19
  %399 = fadd float %397, %398
  %400 = fmul float %temp.0, %20
  %401 = fmul float %temp1.0, %21
  %402 = fadd float %400, %401
  %403 = fmul float %temp2.0, %22
  %404 = fadd float %402, %403
  %405 = fmul float %47, %23
  %406 = fadd float %404, %405
  %407 = fmul float %temp.0, %24
  %408 = fmul float %temp1.0, %25
  %409 = fadd float %407, %408
  %410 = fmul float %temp2.0, %26
  %411 = fadd float %409, %410
  %412 = fmul float %47, %27
  %413 = fadd float %411, %412
  %414 = fmul float %temp.0, %36
  %415 = fmul float %temp1.0, %37
  %416 = fadd float %414, %415
  %417 = fmul float %temp2.0, %38
  %418 = fadd float %416, %417
  %419 = fmul float %47, %39
  %420 = fadd float %418, %419
  %421 = fmul float %51, %28
  %422 = fmul float %52, %29
  %423 = fadd float %421, %422
  %424 = fmul float %53, %30
  %425 = fadd float %423, %424
  %426 = fmul float %54, %31
  %427 = fadd float %425, %426
  %428 = fmul float %51, %32
  %429 = fmul float %52, %33
  %430 = fadd float %428, %429
  %431 = fmul float %53, %34
  %432 = fadd float %430, %431
  %433 = fmul float %54, %35
  %434 = fadd float %432, %433
  %435 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 16
  %436 = load <16 x i8> addrspace(2)* %435, !tbaa !0
  %437 = call float @llvm.SI.load.const(<16 x i8> %436, i32 0)
  %438 = fmul float %437, %392
  %439 = call float @llvm.SI.load.const(<16 x i8> %436, i32 4)
  %440 = fmul float %439, %399
  %441 = fadd float %438, %440
  %442 = call float @llvm.SI.load.const(<16 x i8> %436, i32 8)
  %443 = fmul float %442, %406
  %444 = fadd float %441, %443
  %445 = call float @llvm.SI.load.const(<16 x i8> %436, i32 12)
  %446 = fmul float %445, %413
  %447 = fadd float %444, %446
  %448 = call float @llvm.SI.load.const(<16 x i8> %436, i32 16)
  %449 = fmul float %448, %392
  %450 = call float @llvm.SI.load.const(<16 x i8> %436, i32 20)
  %451 = fmul float %450, %399
  %452 = fadd float %449, %451
  %453 = call float @llvm.SI.load.const(<16 x i8> %436, i32 24)
  %454 = fmul float %453, %406
  %455 = fadd float %452, %454
  %456 = call float @llvm.SI.load.const(<16 x i8> %436, i32 28)
  %457 = fmul float %456, %413
  %458 = fadd float %455, %457
  %459 = call float @llvm.SI.load.const(<16 x i8> %436, i32 32)
  %460 = fmul float %459, %392
  %461 = call float @llvm.SI.load.const(<16 x i8> %436, i32 36)
  %462 = fmul float %461, %399
  %463 = fadd float %460, %462
  %464 = call float @llvm.SI.load.const(<16 x i8> %436, i32 40)
  %465 = fmul float %464, %406
  %466 = fadd float %463, %465
  %467 = call float @llvm.SI.load.const(<16 x i8> %436, i32 44)
  %468 = fmul float %467, %413
  %469 = fadd float %466, %468
  %470 = call float @llvm.SI.load.const(<16 x i8> %436, i32 48)
  %471 = fmul float %470, %392
  %472 = call float @llvm.SI.load.const(<16 x i8> %436, i32 52)
  %473 = fmul float %472, %399
  %474 = fadd float %471, %473
  %475 = call float @llvm.SI.load.const(<16 x i8> %436, i32 56)
  %476 = fmul float %475, %406
  %477 = fadd float %474, %476
  %478 = call float @llvm.SI.load.const(<16 x i8> %436, i32 60)
  %479 = fmul float %478, %413
  %480 = fadd float %477, %479
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %427, float %434, float %420, float 1.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 12, i32 0, float %392, float %399, float %406, float %413)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 13, i32 0, float %447, float %458, float %469, float %480)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg41, %SGPR6_SGPR7 in %vreg44, %VGPR0 in %vreg47

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 4; mem:LD16[%53](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%VGPR5_VGPR6_VGPR7_VGPR8<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 0; mem:LD16[%44](align=8)(tbaa=!"const")
	S_WAITCNT 112
	%VGPR1_VGPR2_VGPR3_VGPR4<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR0, 0, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1, 0; mem:LD16[%11](align=8)(tbaa=!"const")
	%SGPR2<def> = S_MOV_B32 3840
	S_WAITCNT 112
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_SGPR %SGPR8_SGPR9_SGPR10_SGPR11, %SGPR2<kill>; mem:LD4[<unknown>]
	S_WAITCNT 127
	%SGPR2_SGPR3<def> = V_CMP_NE_I32_e64 %SGPR2<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 39; mem:LD4[<unknown>]
	%SGPR5<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 38; mem:LD4[<unknown>]
	%SGPR12<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 37; mem:LD4[<unknown>]
	%SGPR13<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 36; mem:LD4[<unknown>]
	%SGPR14<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 35; mem:LD4[<unknown>]
	%SGPR15<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 34; mem:LD4[<unknown>]
	%SGPR16<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 33; mem:LD4[<unknown>]
	%SGPR17<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 32; mem:LD4[<unknown>]
	%SGPR18<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 31; mem:LD4[<unknown>]
	%SGPR19<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 30; mem:LD4[<unknown>]
	%SGPR20<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 29; mem:LD4[<unknown>]
	%SGPR21<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 28; mem:LD4[<unknown>]
	%SGPR22<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 15; mem:LD4[<unknown>]
	%SGPR23<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 14; mem:LD4[<unknown>]
	%SGPR24<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 13; mem:LD4[<unknown>]
	%SGPR25<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 12; mem:LD4[<unknown>]
	%SGPR26<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 11; mem:LD4[<unknown>]
	%SGPR27<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 10; mem:LD4[<unknown>]
	%SGPR28<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 9; mem:LD4[<unknown>]
	%SGPR29<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 8; mem:LD4[<unknown>]
	%SGPR30<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 7; mem:LD4[<unknown>]
	%SGPR31<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 6; mem:LD4[<unknown>]
	%SGPR32<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 5; mem:LD4[<unknown>]
	%SGPR33<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 4; mem:LD4[<unknown>]
	%SGPR34<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 3; mem:LD4[<unknown>]
	%SGPR35<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 2; mem:LD4[<unknown>]
	%SGPR36<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 1; mem:LD4[<unknown>]
	%SGPR37<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 0; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR29<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR32<def> = V_MOV_B32_e32 %SGPR5<kill>, %EXEC<imp-use>
	%VGPR36<def> = V_MOV_B32_e32 %SGPR12<kill>, %EXEC<imp-use>
	%VGPR35<def> = V_MOV_B32_e32 %SGPR13<kill>, %EXEC<imp-use>
	%VGPR18<def> = V_MOV_B32_e32 %SGPR14<kill>, %EXEC<imp-use>
	%VGPR28<def> = V_MOV_B32_e32 %SGPR15<kill>, %EXEC<imp-use>
	%VGPR34<def> = V_MOV_B32_e32 %SGPR16<kill>, %EXEC<imp-use>
	%VGPR33<def> = V_MOV_B32_e32 %SGPR17<kill>, %EXEC<imp-use>
	%VGPR17<def> = V_MOV_B32_e32 %SGPR18<kill>, %EXEC<imp-use>
	%VGPR19<def> = V_MOV_B32_e32 %SGPR19<kill>, %EXEC<imp-use>
	%VGPR31<def> = V_MOV_B32_e32 %SGPR20<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_MOV_B32_e32 %SGPR21<kill>, %EXEC<imp-use>
	%VGPR12<def> = V_MOV_B32_e32 %SGPR22<kill>, %EXEC<imp-use>
	%VGPR16<def> = V_MOV_B32_e32 %SGPR23<kill>, %EXEC<imp-use>
	%VGPR27<def> = V_MOV_B32_e32 %SGPR24<kill>, %EXEC<imp-use>
	%VGPR26<def> = V_MOV_B32_e32 %SGPR25<kill>, %EXEC<imp-use>
	%VGPR11<def> = V_MOV_B32_e32 %SGPR26<kill>, %EXEC<imp-use>
	%VGPR15<def> = V_MOV_B32_e32 %SGPR27<kill>, %EXEC<imp-use>
	%VGPR25<def> = V_MOV_B32_e32 %SGPR28<kill>, %EXEC<imp-use>
	%VGPR24<def> = V_MOV_B32_e32 %SGPR29<kill>, %EXEC<imp-use>
	%VGPR10<def> = V_MOV_B32_e32 %SGPR30<kill>, %EXEC<imp-use>
	%VGPR14<def> = V_MOV_B32_e32 %SGPR31<kill>, %EXEC<imp-use>
	%VGPR23<def> = V_MOV_B32_e32 %SGPR32<kill>, %EXEC<imp-use>
	%VGPR22<def> = V_MOV_B32_e32 %SGPR33<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_MOV_B32_e32 %SGPR34<kill>, %EXEC<imp-use>
	%VGPR13<def> = V_MOV_B32_e32 %SGPR35<kill>, %EXEC<imp-use>
	%VGPR21<def> = V_MOV_B32_e32 %SGPR36<kill>, %EXEC<imp-use>
	%VGPR20<def> = V_MOV_B32_e32 %SGPR37<kill>, %EXEC<imp-use>
	%VGPR39<def> = V_MOV_B32_e32 %VGPR1, %EXEC<imp-use>
	%VGPR38<def> = V_MOV_B32_e32 %VGPR2, %EXEC<imp-use>
	%VGPR37<def> = V_MOV_B32_e32 %VGPR3, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_AND_SAVEEXEC_B64 %SGPR2_SGPR3, %EXEC<imp-def>, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_XOR_B64 %EXEC, %SGPR2_SGPR3
	S_CBRANCH_EXECZ <BB#2>, %EXEC
    Successors according to CFG: BB#1(16) BB#2(16)

BB#1: derived from LLVM BB %IF
    Live Ins: %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR20 %VGPR21 %VGPR13 %VGPR9 %VGPR22 %VGPR23 %VGPR14 %VGPR10 %VGPR24 %VGPR25 %VGPR15 %VGPR11 %VGPR26 %VGPR27 %VGPR16 %VGPR12 %VGPR30 %VGPR31 %VGPR19 %VGPR17 %VGPR33 %VGPR34 %VGPR28 %VGPR18 %VGPR35 %VGPR36 %VGPR32 %VGPR29 %VGPR5_VGPR6_VGPR7_VGPR8 %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0 %VGPR1_VGPR2_VGPR3_VGPR4 %SGPR2_SGPR3
    Predecessors according to CFG: BB#0
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7, 8; mem:LD16[%63](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%VGPR37_VGPR38_VGPR39_VGPR40<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %VGPR0, 0, %EXEC<imp-use>
	%VGPR41<def> = V_MOV_B32_e32 2.550100e+02, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR42<def> = V_MUL_F32_e32 %VGPR37, %VGPR41, %EXEC<imp-use>
	%VGPR42<def> = V_CVT_I32_F32_e32 %VGPR42<kill>, %EXEC<imp-use>
	%VGPR42<def> = V_MUL_LO_I32 3, %VGPR42<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR43<def> = V_ADD_I32_e32 43, %VGPR42, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR43<def> = V_LSHLREV_B32_e32 4, %VGPR43<kill>, %EXEC<imp-use>
	%VGPR44<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR43, %EXEC<imp-use>; mem:LD4[<unknown>]
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 12; mem:LD16[%72](align=8)(tbaa=!"const")
	S_WAITCNT 112
	%VGPR45_VGPR46_VGPR47_VGPR48<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR0<def> = V_MUL_F32_e32 %VGPR44<kill>, %VGPR45, %EXEC<imp-use>
	%VGPR44<def> = V_MUL_F32_e32 %VGPR38, %VGPR41, %EXEC<imp-use>
	%VGPR44<def> = V_CVT_I32_F32_e32 %VGPR44<kill>, %EXEC<imp-use>
	%VGPR44<def> = V_MUL_LO_I32 3, %VGPR44<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR49<def> = V_ADD_I32_e32 43, %VGPR44, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR49<def> = V_LSHLREV_B32_e32 4, %VGPR49<kill>, %EXEC<imp-use>
	%VGPR50<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR49, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR0<def> = V_MAD_F32 %VGPR50<kill>, %VGPR46, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR50<def> = V_MUL_F32_e32 %VGPR39, %VGPR41, %EXEC<imp-use>
	%VGPR50<def> = V_CVT_I32_F32_e32 %VGPR50<kill>, %EXEC<imp-use>
	%VGPR50<def> = V_MUL_LO_I32 3, %VGPR50<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR51<def> = V_ADD_I32_e32 43, %VGPR50, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR51<def> = V_LSHLREV_B32_e32 4, %VGPR51<kill>, %EXEC<imp-use>
	%VGPR52<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR51, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR0<def> = V_MAD_F32 %VGPR52<kill>, %VGPR47, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR52<def> = V_ADD_F32_e32 %VGPR46, %VGPR45, %EXEC<imp-use>
	%VGPR52<def> = V_ADD_F32_e32 %VGPR52<kill>, %VGPR47, %EXEC<imp-use>
	%VGPR52<def> = V_SUB_F32_e32 1.000000e+00, %VGPR52<kill>, %EXEC<imp-use>
	%VGPR37<def> = V_MUL_F32_e32 %VGPR40, %VGPR41<kill>, %EXEC<imp-use>, %VGPR37_VGPR38_VGPR39_VGPR40<imp-use,kill>
	%VGPR37<def> = V_CVT_I32_F32_e32 %VGPR37<kill>, %EXEC<imp-use>
	%VGPR39<def> = V_MUL_LO_I32 3, %VGPR37<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR37<def> = V_ADD_I32_e32 43, %VGPR39, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR37<def> = V_LSHLREV_B32_e32 4, %VGPR37<kill>, %EXEC<imp-use>
	%VGPR38<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR37, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR0<def> = V_MAD_F32 %VGPR38<kill>, %VGPR52, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR38<def> = V_OR_B32_e64 4, %VGPR43, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR38<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR38<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR38<def> = V_MUL_F32_e32 %VGPR38<kill>, %VGPR45, %EXEC<imp-use>
	%VGPR40<def> = V_OR_B32_e64 4, %VGPR49, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR40<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR40<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR38<def> = V_MAD_F32 %VGPR40<kill>, %VGPR46, %VGPR38<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR40<def> = V_OR_B32_e64 4, %VGPR51, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR40<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR40<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR38<def> = V_MAD_F32 %VGPR40<kill>, %VGPR47, %VGPR38<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR40<def> = V_OR_B32_e64 4, %VGPR37, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR40<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR40<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR38<def> = V_MAD_F32 %VGPR40<kill>, %VGPR52, %VGPR38<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR38<def> = V_MUL_F32_e32 %VGPR2, %VGPR38<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR1, %VGPR0<kill>, %VGPR38<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR38<def> = V_OR_B32_e64 8, %VGPR43, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR38<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR38<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR38<def> = V_MUL_F32_e32 %VGPR38<kill>, %VGPR45, %EXEC<imp-use>
	%VGPR40<def> = V_OR_B32_e64 8, %VGPR49, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR40<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR40<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR38<def> = V_MAD_F32 %VGPR40<kill>, %VGPR46, %VGPR38<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR40<def> = V_OR_B32_e64 8, %VGPR51, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR40<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR40<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR38<def> = V_MAD_F32 %VGPR40<kill>, %VGPR47, %VGPR38<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR40<def> = V_OR_B32_e64 8, %VGPR37, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR40<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR40<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR38<def> = V_MAD_F32 %VGPR40<kill>, %VGPR52, %VGPR38<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR3, %VGPR38<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR38<def> = V_OR_B32_e64 12, %VGPR43<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR38<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR38<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR38<def> = V_MUL_F32_e32 %VGPR38<kill>, %VGPR45, %EXEC<imp-use>
	%VGPR40<def> = V_OR_B32_e64 12, %VGPR49<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR40<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR40<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR38<def> = V_MAD_F32 %VGPR40<kill>, %VGPR46, %VGPR38<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR40<def> = V_OR_B32_e64 12, %VGPR51<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR40<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR40<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR38<def> = V_MAD_F32 %VGPR40<kill>, %VGPR47, %VGPR38<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR37<def> = V_OR_B32_e64 12, %VGPR37<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR37<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR37<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR37<def> = V_MAD_F32 %VGPR37<kill>, %VGPR52, %VGPR38<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR37<def> = V_MAD_F32 %VGPR4, %VGPR37<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_I32_e32 42, %VGPR42, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR0<def> = V_LSHLREV_B32_e32 4, %VGPR0<kill>, %EXEC<imp-use>
	%VGPR38<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR0, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR38<def> = V_MUL_F32_e32 %VGPR38<kill>, %VGPR45, %EXEC<imp-use>
	%VGPR40<def> = V_ADD_I32_e32 42, %VGPR44, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR40<def> = V_LSHLREV_B32_e32 4, %VGPR40<kill>, %EXEC<imp-use>
	%VGPR41<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR40, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR38<def> = V_MAD_F32 %VGPR41<kill>, %VGPR46, %VGPR38<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR41<def> = V_ADD_I32_e32 42, %VGPR50, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR41<def> = V_LSHLREV_B32_e32 4, %VGPR41<kill>, %EXEC<imp-use>
	%VGPR43<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR41, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR38<def> = V_MAD_F32 %VGPR43<kill>, %VGPR47, %VGPR38<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR43<def> = V_ADD_I32_e32 42, %VGPR39, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR43<def> = V_LSHLREV_B32_e32 4, %VGPR43<kill>, %EXEC<imp-use>
	%VGPR49<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR43, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR38<def> = V_MAD_F32 %VGPR49<kill>, %VGPR52, %VGPR38<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR49<def> = V_OR_B32_e64 4, %VGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR49<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR49<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR49<def> = V_MUL_F32_e32 %VGPR49<kill>, %VGPR45, %EXEC<imp-use>
	%VGPR51<def> = V_OR_B32_e64 4, %VGPR40, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR51<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR51<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR49<def> = V_MAD_F32 %VGPR51<kill>, %VGPR46, %VGPR49<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR51<def> = V_OR_B32_e64 4, %VGPR41, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR51<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR51<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR49<def> = V_MAD_F32 %VGPR51<kill>, %VGPR47, %VGPR49<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR51<def> = V_OR_B32_e64 4, %VGPR43, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR51<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR51<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR49<def> = V_MAD_F32 %VGPR51<kill>, %VGPR52, %VGPR49<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR49<def> = V_MUL_F32_e32 %VGPR2, %VGPR49<kill>, %EXEC<imp-use>
	%VGPR38<def> = V_MAD_F32 %VGPR1, %VGPR38<kill>, %VGPR49<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR49<def> = V_OR_B32_e64 8, %VGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR49<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR49<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR49<def> = V_MUL_F32_e32 %VGPR49<kill>, %VGPR45, %EXEC<imp-use>
	%VGPR51<def> = V_OR_B32_e64 8, %VGPR40, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR51<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR51<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR49<def> = V_MAD_F32 %VGPR51<kill>, %VGPR46, %VGPR49<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR51<def> = V_OR_B32_e64 8, %VGPR41, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR51<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR51<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR49<def> = V_MAD_F32 %VGPR51<kill>, %VGPR47, %VGPR49<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR51<def> = V_OR_B32_e64 8, %VGPR43, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR51<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR51<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR49<def> = V_MAD_F32 %VGPR51<kill>, %VGPR52, %VGPR49<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR38<def> = V_MAD_F32 %VGPR3, %VGPR49<kill>, %VGPR38<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_OR_B32_e64 12, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR0<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR0<def> = V_MUL_F32_e32 %VGPR0<kill>, %VGPR45, %EXEC<imp-use>
	%VGPR40<def> = V_OR_B32_e64 12, %VGPR40<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR40<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR40<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR0<def> = V_MAD_F32 %VGPR40<kill>, %VGPR46, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR40<def> = V_OR_B32_e64 12, %VGPR41<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR40<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR40<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR0<def> = V_MAD_F32 %VGPR40<kill>, %VGPR47, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR40<def> = V_OR_B32_e64 12, %VGPR43<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR40<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR40<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR0<def> = V_MAD_F32 %VGPR40<kill>, %VGPR52, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR38<def> = V_MAD_F32 %VGPR4, %VGPR0<kill>, %VGPR38<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_I32_e32 41, %VGPR42<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR0<def> = V_LSHLREV_B32_e32 4, %VGPR0<kill>, %EXEC<imp-use>
	%VGPR40<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR0, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR40<def> = V_MUL_F32_e32 %VGPR40<kill>, %VGPR45, %EXEC<imp-use>
	%VGPR41<def> = V_ADD_I32_e32 41, %VGPR44<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR41<def> = V_LSHLREV_B32_e32 4, %VGPR41<kill>, %EXEC<imp-use>
	%VGPR42<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR41, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR40<def> = V_MAD_F32 %VGPR42<kill>, %VGPR46, %VGPR40<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR42<def> = V_ADD_I32_e32 41, %VGPR50<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR42<def> = V_LSHLREV_B32_e32 4, %VGPR42<kill>, %EXEC<imp-use>
	%VGPR43<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR42, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR40<def> = V_MAD_F32 %VGPR43<kill>, %VGPR47, %VGPR40<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR39<def> = V_ADD_I32_e32 41, %VGPR39<kill>, %EXEC<imp-use>, %VCC<imp-def,dead>
	%VGPR39<def> = V_LSHLREV_B32_e32 4, %VGPR39<kill>, %EXEC<imp-use>
	%VGPR43<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR39, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR40<def> = V_MAD_F32 %VGPR43<kill>, %VGPR52, %VGPR40<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR43<def> = V_OR_B32_e64 4, %VGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR43<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR43<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR43<def> = V_MUL_F32_e32 %VGPR43<kill>, %VGPR45, %EXEC<imp-use>
	%VGPR44<def> = V_OR_B32_e64 4, %VGPR41, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR44<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR44<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR43<def> = V_MAD_F32 %VGPR44<kill>, %VGPR46, %VGPR43<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR44<def> = V_OR_B32_e64 4, %VGPR42, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR44<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR44<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR43<def> = V_MAD_F32 %VGPR44<kill>, %VGPR47, %VGPR43<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR44<def> = V_OR_B32_e64 4, %VGPR39, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR44<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR44<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR43<def> = V_MAD_F32 %VGPR44<kill>, %VGPR52, %VGPR43<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR43<def> = V_MUL_F32_e32 %VGPR2, %VGPR43<kill>, %EXEC<imp-use>
	%VGPR40<def> = V_MAD_F32 %VGPR1, %VGPR40<kill>, %VGPR43<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR43<def> = V_OR_B32_e64 8, %VGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR43<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR43<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR43<def> = V_MUL_F32_e32 %VGPR43<kill>, %VGPR45, %EXEC<imp-use>
	%VGPR44<def> = V_OR_B32_e64 8, %VGPR41, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR44<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR44<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR43<def> = V_MAD_F32 %VGPR44<kill>, %VGPR46, %VGPR43<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR44<def> = V_OR_B32_e64 8, %VGPR42, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR44<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR44<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR43<def> = V_MAD_F32 %VGPR44<kill>, %VGPR47, %VGPR43<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR44<def> = V_OR_B32_e64 8, %VGPR39, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR44<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR44<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR43<def> = V_MAD_F32 %VGPR44<kill>, %VGPR52, %VGPR43<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR40<def> = V_MAD_F32 %VGPR3, %VGPR43<kill>, %VGPR40<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_OR_B32_e64 12, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR0<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR0<def> = V_MUL_F32_e32 %VGPR0<kill>, %VGPR45, %EXEC<imp-use>
	%VGPR41<def> = V_OR_B32_e64 12, %VGPR41<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR41<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR41<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR0<def> = V_MAD_F32 %VGPR41<kill>, %VGPR46, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR41<def> = V_OR_B32_e64 12, %VGPR42<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR41<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR41<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR0<def> = V_MAD_F32 %VGPR41<kill>, %VGPR47, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR45_VGPR46_VGPR47_VGPR48<imp-use,kill>
	%VGPR39<def> = V_OR_B32_e64 12, %VGPR39<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR39<def> = BUFFER_LOAD_DWORD_OFFEN %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %VGPR39<kill>, %EXEC<imp-use>; mem:LD4[<unknown>]
	S_WAITCNT 1904
	%VGPR0<def> = V_MAD_F32 %VGPR39<kill>, %VGPR52<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR39<def> = V_MAD_F32 %VGPR4, %VGPR0<kill>, %VGPR40<kill>, 0, 0, 0, 0, %EXEC<imp-use>
    Successors according to CFG: BB#2

BB#2: derived from LLVM BB %ENDIF
    Live Ins: %VGPR20 %VGPR21 %VGPR13 %VGPR9 %VGPR22 %VGPR23 %VGPR14 %VGPR10 %VGPR24 %VGPR25 %VGPR15 %VGPR11 %VGPR26 %VGPR27 %VGPR16 %VGPR12 %VGPR30 %VGPR31 %VGPR19 %VGPR17 %VGPR33 %VGPR34 %VGPR28 %VGPR18 %VGPR35 %VGPR36 %VGPR32 %VGPR29 %VGPR5_VGPR6_VGPR7_VGPR8 %SGPR0_SGPR1 %VGPR1_VGPR2_VGPR3_VGPR4 %SGPR2_SGPR3 %VGPR39 %VGPR38 %VGPR37
    Predecessors according to CFG: BB#0 BB#1
	%EXEC<def> = S_OR_B64 %EXEC, %SGPR2_SGPR3
	%VGPR0<def> = V_MUL_F32_e64 %VGPR38, %VGPR36<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR39, %VGPR35<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR37, %VGPR32<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR4, %VGPR29<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR29<def> = V_MUL_F32_e64 %VGPR6, %VGPR34<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR29<def> = V_MAD_F32 %VGPR5, %VGPR33<kill>, %VGPR29<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR28<def> = V_MAD_F32 %VGPR7, %VGPR28<kill>, %VGPR29<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR18<def> = V_MAD_F32 %VGPR8, %VGPR18<kill>, %VGPR28<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR28<def> = V_MUL_F32_e64 %VGPR6, %VGPR31<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR28<def> = V_MAD_F32 %VGPR5, %VGPR30<kill>, %VGPR28<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR19<def> = V_MAD_F32 %VGPR7, %VGPR19<kill>, %VGPR28<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR8, %VGPR17<kill>, %VGPR19<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR5_VGPR6_VGPR7_VGPR8<imp-use,kill>
	%VGPR6<def> = V_MOV_B32_e32 1.000000e+00, %EXEC<imp-use>
	EXP 15, 32, 0, 0, 0, %VGPR5<kill>, %VGPR18<kill>, %VGPR0<kill>, %VGPR6<kill>, %EXEC<imp-use>
	S_WAITCNT 1807
	%VGPR0<def> = V_MUL_F32_e64 %VGPR38, %VGPR27<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR39, %VGPR26<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR37, %VGPR16<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR0<def> = V_MAD_F32 %VGPR4, %VGPR12<kill>, %VGPR0<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_MUL_F32_e64 %VGPR38, %VGPR25<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR39, %VGPR24<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR37, %VGPR15<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR4, %VGPR11<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MUL_F32_e64 %VGPR38, %VGPR23<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR39, %VGPR22<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR37, %VGPR14<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR4, %VGPR10<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_MUL_F32_e64 %VGPR38<kill>, %VGPR21<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR39<kill>, %VGPR20<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR37<kill>, %VGPR13<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_MAD_F32 %VGPR4, %VGPR9<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR1_VGPR2_VGPR3_VGPR4<imp-use,kill>
	EXP 15, 12, 0, 0, 0, %VGPR1, %VGPR6, %VGPR5, %VGPR0, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 64; mem:LD16[%449](align=8)(tbaa=!"const")
	S_WAITCNT 15
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 13; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 12; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 14; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %SGPR4<kill>, %VGPR5, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 15; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR2<def> = V_MAD_F32 %SGPR4<kill>, %VGPR0, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 9; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR3<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 8; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 10; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %SGPR4<kill>, %VGPR5, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 11; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %SGPR4<kill>, %VGPR0, %VGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 5; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR4<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR6, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 4; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 6; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %SGPR4<kill>, %VGPR5, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 7; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %SGPR4<kill>, %VGPR0, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR4<kill>, %VGPR6<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 0; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %SGPR4<kill>, %VGPR1<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR1<def> = V_MAD_F32 %SGPR4<kill>, %VGPR5<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 3; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR0<def> = V_MAD_F32 %SGPR0<kill>, %VGPR0<kill>, %VGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 13, 0, 1, 0, %VGPR0<kill>, %VGPR4<kill>, %VGPR3<kill>, %VGPR2<kill>, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_LOAD_DWORDX4 s[8:11], s[6:7], 4                  ; C0840704
	S_WAITCNT lgkmcnt(0)                               ; BF8C007F
	BUFFER_LOAD_FORMAT_XYZW v[5:8], s[8:11][v0] + 0    ; E00C2000 80020500
	S_LOAD_DWORDX4 s[8:11], s[6:7], 0                  ; C0840700
	S_WAITCNT vmcnt(0) lgkmcnt(0)                      ; BF8C0070
	BUFFER_LOAD_FORMAT_XYZW v[1:4], s[8:11][v0] + 0    ; E00C2000 80020100
	S_LOAD_DWORDX4 s[8:11], s[0:1], 0                  ; C0840100
	S_MOV_B32 s2, 3840                                 ; BE8203FF 00000F00
	S_WAITCNT vmcnt(0) lgkmcnt(0)                      ; BF8C0070
	S_BUFFER_LOAD_DWORD s2, s[8:11], s2                ; C2010802
	S_WAITCNT lgkmcnt(0)                               ; BF8C007F
	V_CMP_NE_I32_e64 s[2:3], s2, 0, 0, 0, 0, 0         ; D10A0002 02010002
	S_BUFFER_LOAD_DWORD s4, s[8:11], 39                ; C2020927
	S_BUFFER_LOAD_DWORD s5, s[8:11], 38                ; C2028926
	S_BUFFER_LOAD_DWORD s12, s[8:11], 37               ; C2060925
	S_BUFFER_LOAD_DWORD s13, s[8:11], 36               ; C2068924
	S_BUFFER_LOAD_DWORD s14, s[8:11], 35               ; C2070923
	S_BUFFER_LOAD_DWORD s15, s[8:11], 34               ; C2078922
	S_BUFFER_LOAD_DWORD s16, s[8:11], 33               ; C2080921
	S_BUFFER_LOAD_DWORD s17, s[8:11], 32               ; C2088920
	S_BUFFER_LOAD_DWORD s18, s[8:11], 31               ; C209091F
	S_BUFFER_LOAD_DWORD s19, s[8:11], 30               ; C209891E
	S_BUFFER_LOAD_DWORD s20, s[8:11], 29               ; C20A091D
	S_BUFFER_LOAD_DWORD s21, s[8:11], 28               ; C20A891C
	S_BUFFER_LOAD_DWORD s22, s[8:11], 15               ; C20B090F
	S_BUFFER_LOAD_DWORD s23, s[8:11], 14               ; C20B890E
	S_BUFFER_LOAD_DWORD s24, s[8:11], 13               ; C20C090D
	S_BUFFER_LOAD_DWORD s25, s[8:11], 12               ; C20C890C
	S_BUFFER_LOAD_DWORD s26, s[8:11], 11               ; C20D090B
	S_BUFFER_LOAD_DWORD s27, s[8:11], 10               ; C20D890A
	S_BUFFER_LOAD_DWORD s28, s[8:11], 9                ; C20E0909
	S_BUFFER_LOAD_DWORD s29, s[8:11], 8                ; C20E8908
	S_BUFFER_LOAD_DWORD s30, s[8:11], 7                ; C20F0907
	S_BUFFER_LOAD_DWORD s31, s[8:11], 6                ; C20F8906
	S_BUFFER_LOAD_DWORD s32, s[8:11], 5                ; C2100905
	S_BUFFER_LOAD_DWORD s33, s[8:11], 4                ; C2108904
	S_BUFFER_LOAD_DWORD s34, s[8:11], 3                ; C2110903
	S_BUFFER_LOAD_DWORD s35, s[8:11], 2                ; C2118902
	S_BUFFER_LOAD_DWORD s36, s[8:11], 1                ; C2120901
	S_BUFFER_LOAD_DWORD s37, s[8:11], 0                ; C2128900
	S_WAITCNT lgkmcnt(0)                               ; BF8C007F
	V_MOV_B32_e32 v29, s4                              ; 7E3A0204
	V_MOV_B32_e32 v32, s5                              ; 7E400205
	V_MOV_B32_e32 v36, s12                             ; 7E48020C
	V_MOV_B32_e32 v35, s13                             ; 7E46020D
	V_MOV_B32_e32 v18, s14                             ; 7E24020E
	V_MOV_B32_e32 v28, s15                             ; 7E38020F
	V_MOV_B32_e32 v34, s16                             ; 7E440210
	V_MOV_B32_e32 v33, s17                             ; 7E420211
	V_MOV_B32_e32 v17, s18                             ; 7E220212
	V_MOV_B32_e32 v19, s19                             ; 7E260213
	V_MOV_B32_e32 v31, s20                             ; 7E3E0214
	V_MOV_B32_e32 v30, s21                             ; 7E3C0215
	V_MOV_B32_e32 v12, s22                             ; 7E180216
	V_MOV_B32_e32 v16, s23                             ; 7E200217
	V_MOV_B32_e32 v27, s24                             ; 7E360218
	V_MOV_B32_e32 v26, s25                             ; 7E340219
	V_MOV_B32_e32 v11, s26                             ; 7E16021A
	V_MOV_B32_e32 v15, s27                             ; 7E1E021B
	V_MOV_B32_e32 v25, s28                             ; 7E32021C
	V_MOV_B32_e32 v24, s29                             ; 7E30021D
	V_MOV_B32_e32 v10, s30                             ; 7E14021E
	V_MOV_B32_e32 v14, s31                             ; 7E1C021F
	V_MOV_B32_e32 v23, s32                             ; 7E2E0220
	V_MOV_B32_e32 v22, s33                             ; 7E2C0221
	V_MOV_B32_e32 v9, s34                              ; 7E120222
	V_MOV_B32_e32 v13, s35                             ; 7E1A0223
	V_MOV_B32_e32 v21, s36                             ; 7E2A0224
	V_MOV_B32_e32 v20, s37                             ; 7E280225
	V_MOV_B32_e32 v39, v1                              ; 7E4E0301
	V_MOV_B32_e32 v38, v2                              ; 7E4C0302
	V_MOV_B32_e32 v37, v3                              ; 7E4A0303
	S_AND_SAVEEXEC_B64 s[2:3], s[2:3]                  ; BE822402
	S_XOR_B64 s[2:3], exec, s[2:3]                     ; 8982027E
	S_CBRANCH_EXECZ ";.BB0_2"                          ; BF880000
	S_LOAD_DWORDX4 s[12:15], s[6:7], 8                 ; C0860708
	S_WAITCNT lgkmcnt(0)                               ; BF8C007F
	BUFFER_LOAD_FORMAT_XYZW v[37:40], s[12:15][v0] + 0 ; E00C2000 80032500
	V_MOV_B32_e32 v41, 2.550100e+02                    ; 7E5202FF 437F028F
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MUL_F32_e32 v42, v37, v41                        ; 10545325
	V_CVT_I32_F32_e32 v42, v42                         ; 7E54112A
	V_MUL_LO_I32 v42, 3, v42, 0, 0, 0, 0, 0            ; D2D6002A 02025483
	V_ADD_I32_e32 v43, 43, v42                         ; 4A5654AB
	V_LSHLREV_B32_e32 v43, 4, v43                      ; 34565684
	BUFFER_LOAD_DWORD v44, s[8:11] + v43               ; E0301000 80022C2B
	S_LOAD_DWORDX4 s[4:7], s[6:7], 12                  ; C082070C
	S_WAITCNT vmcnt(0) lgkmcnt(0)                      ; BF8C0070
	BUFFER_LOAD_FORMAT_XYZW v[45:48], s[4:7][v0] + 0   ; E00C2000 80012D00
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MUL_F32_e32 v0, v44, v45                         ; 10005B2C
	V_MUL_F32_e32 v44, v38, v41                        ; 10585326
	V_CVT_I32_F32_e32 v44, v44                         ; 7E58112C
	V_MUL_LO_I32 v44, 3, v44, 0, 0, 0, 0, 0            ; D2D6002C 02025883
	V_ADD_I32_e32 v49, 43, v44                         ; 4A6258AB
	V_LSHLREV_B32_e32 v49, 4, v49                      ; 34626284
	BUFFER_LOAD_DWORD v50, s[8:11] + v49               ; E0301000 80023231
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v0, v50, v46, v0, 0, 0, 0, 0             ; D2820000 04025D32
	V_MUL_F32_e32 v50, v39, v41                        ; 10645327
	V_CVT_I32_F32_e32 v50, v50                         ; 7E641132
	V_MUL_LO_I32 v50, 3, v50, 0, 0, 0, 0, 0            ; D2D60032 02026483
	V_ADD_I32_e32 v51, 43, v50                         ; 4A6664AB
	V_LSHLREV_B32_e32 v51, 4, v51                      ; 34666684
	BUFFER_LOAD_DWORD v52, s[8:11] + v51               ; E0301000 80023433
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v0, v52, v47, v0, 0, 0, 0, 0             ; D2820000 04025F34
	V_ADD_F32_e32 v52, v46, v45                        ; 06685B2E
	V_ADD_F32_e32 v52, v52, v47                        ; 06685F34
	V_SUB_F32_e32 v52, 1.000000e+00, v52               ; 086868F2
	V_MUL_F32_e32 v37, v40, v41                        ; 104A5328
	V_CVT_I32_F32_e32 v37, v37                         ; 7E4A1125
	V_MUL_LO_I32 v39, 3, v37, 0, 0, 0, 0, 0            ; D2D60027 02024A83
	V_ADD_I32_e32 v37, 43, v39                         ; 4A4A4EAB
	V_LSHLREV_B32_e32 v37, 4, v37                      ; 344A4A84
	BUFFER_LOAD_DWORD v38, s[8:11] + v37               ; E0301000 80022625
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v0, v38, v52, v0, 0, 0, 0, 0             ; D2820000 04026926
	V_OR_B32_e64 v38, 4, v43, 0, 0, 0, 0               ; D2380026 02025684
	BUFFER_LOAD_DWORD v38, s[8:11] + v38               ; E0301000 80022626
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MUL_F32_e32 v38, v38, v45                        ; 104C5B26
	V_OR_B32_e64 v40, 4, v49, 0, 0, 0, 0               ; D2380028 02026284
	BUFFER_LOAD_DWORD v40, s[8:11] + v40               ; E0301000 80022828
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v38, v40, v46, v38, 0, 0, 0, 0           ; D2820026 049A5D28
	V_OR_B32_e64 v40, 4, v51, 0, 0, 0, 0               ; D2380028 02026684
	BUFFER_LOAD_DWORD v40, s[8:11] + v40               ; E0301000 80022828
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v38, v40, v47, v38, 0, 0, 0, 0           ; D2820026 049A5F28
	V_OR_B32_e64 v40, 4, v37, 0, 0, 0, 0               ; D2380028 02024A84
	BUFFER_LOAD_DWORD v40, s[8:11] + v40               ; E0301000 80022828
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v38, v40, v52, v38, 0, 0, 0, 0           ; D2820026 049A6928
	V_MUL_F32_e32 v38, v2, v38                         ; 104C4D02
	V_MAD_F32 v0, v1, v0, v38, 0, 0, 0, 0              ; D2820000 049A0101
	V_OR_B32_e64 v38, 8, v43, 0, 0, 0, 0               ; D2380026 02025688
	BUFFER_LOAD_DWORD v38, s[8:11] + v38               ; E0301000 80022626
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MUL_F32_e32 v38, v38, v45                        ; 104C5B26
	V_OR_B32_e64 v40, 8, v49, 0, 0, 0, 0               ; D2380028 02026288
	BUFFER_LOAD_DWORD v40, s[8:11] + v40               ; E0301000 80022828
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v38, v40, v46, v38, 0, 0, 0, 0           ; D2820026 049A5D28
	V_OR_B32_e64 v40, 8, v51, 0, 0, 0, 0               ; D2380028 02026688
	BUFFER_LOAD_DWORD v40, s[8:11] + v40               ; E0301000 80022828
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v38, v40, v47, v38, 0, 0, 0, 0           ; D2820026 049A5F28
	V_OR_B32_e64 v40, 8, v37, 0, 0, 0, 0               ; D2380028 02024A88
	BUFFER_LOAD_DWORD v40, s[8:11] + v40               ; E0301000 80022828
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v38, v40, v52, v38, 0, 0, 0, 0           ; D2820026 049A6928
	V_MAD_F32 v0, v3, v38, v0, 0, 0, 0, 0              ; D2820000 04024D03
	V_OR_B32_e64 v38, 12, v43, 0, 0, 0, 0              ; D2380026 0202568C
	BUFFER_LOAD_DWORD v38, s[8:11] + v38               ; E0301000 80022626
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MUL_F32_e32 v38, v38, v45                        ; 104C5B26
	V_OR_B32_e64 v40, 12, v49, 0, 0, 0, 0              ; D2380028 0202628C
	BUFFER_LOAD_DWORD v40, s[8:11] + v40               ; E0301000 80022828
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v38, v40, v46, v38, 0, 0, 0, 0           ; D2820026 049A5D28
	V_OR_B32_e64 v40, 12, v51, 0, 0, 0, 0              ; D2380028 0202668C
	BUFFER_LOAD_DWORD v40, s[8:11] + v40               ; E0301000 80022828
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v38, v40, v47, v38, 0, 0, 0, 0           ; D2820026 049A5F28
	V_OR_B32_e64 v37, 12, v37, 0, 0, 0, 0              ; D2380025 02024A8C
	BUFFER_LOAD_DWORD v37, s[8:11] + v37               ; E0301000 80022525
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v37, v37, v52, v38, 0, 0, 0, 0           ; D2820025 049A6925
	V_MAD_F32 v37, v4, v37, v0, 0, 0, 0, 0             ; D2820025 04024B04
	V_ADD_I32_e32 v0, 42, v42                          ; 4A0054AA
	V_LSHLREV_B32_e32 v0, 4, v0                        ; 34000084
	BUFFER_LOAD_DWORD v38, s[8:11] + v0                ; E0301000 80022600
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MUL_F32_e32 v38, v38, v45                        ; 104C5B26
	V_ADD_I32_e32 v40, 42, v44                         ; 4A5058AA
	V_LSHLREV_B32_e32 v40, 4, v40                      ; 34505084
	BUFFER_LOAD_DWORD v41, s[8:11] + v40               ; E0301000 80022928
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v38, v41, v46, v38, 0, 0, 0, 0           ; D2820026 049A5D29
	V_ADD_I32_e32 v41, 42, v50                         ; 4A5264AA
	V_LSHLREV_B32_e32 v41, 4, v41                      ; 34525284
	BUFFER_LOAD_DWORD v43, s[8:11] + v41               ; E0301000 80022B29
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v38, v43, v47, v38, 0, 0, 0, 0           ; D2820026 049A5F2B
	V_ADD_I32_e32 v43, 42, v39                         ; 4A564EAA
	V_LSHLREV_B32_e32 v43, 4, v43                      ; 34565684
	BUFFER_LOAD_DWORD v49, s[8:11] + v43               ; E0301000 8002312B
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v38, v49, v52, v38, 0, 0, 0, 0           ; D2820026 049A6931
	V_OR_B32_e64 v49, 4, v0, 0, 0, 0, 0                ; D2380031 02020084
	BUFFER_LOAD_DWORD v49, s[8:11] + v49               ; E0301000 80023131
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MUL_F32_e32 v49, v49, v45                        ; 10625B31
	V_OR_B32_e64 v51, 4, v40, 0, 0, 0, 0               ; D2380033 02025084
	BUFFER_LOAD_DWORD v51, s[8:11] + v51               ; E0301000 80023333
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v49, v51, v46, v49, 0, 0, 0, 0           ; D2820031 04C65D33
	V_OR_B32_e64 v51, 4, v41, 0, 0, 0, 0               ; D2380033 02025284
	BUFFER_LOAD_DWORD v51, s[8:11] + v51               ; E0301000 80023333
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v49, v51, v47, v49, 0, 0, 0, 0           ; D2820031 04C65F33
	V_OR_B32_e64 v51, 4, v43, 0, 0, 0, 0               ; D2380033 02025684
	BUFFER_LOAD_DWORD v51, s[8:11] + v51               ; E0301000 80023333
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v49, v51, v52, v49, 0, 0, 0, 0           ; D2820031 04C66933
	V_MUL_F32_e32 v49, v2, v49                         ; 10626302
	V_MAD_F32 v38, v1, v38, v49, 0, 0, 0, 0            ; D2820026 04C64D01
	V_OR_B32_e64 v49, 8, v0, 0, 0, 0, 0                ; D2380031 02020088
	BUFFER_LOAD_DWORD v49, s[8:11] + v49               ; E0301000 80023131
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MUL_F32_e32 v49, v49, v45                        ; 10625B31
	V_OR_B32_e64 v51, 8, v40, 0, 0, 0, 0               ; D2380033 02025088
	BUFFER_LOAD_DWORD v51, s[8:11] + v51               ; E0301000 80023333
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v49, v51, v46, v49, 0, 0, 0, 0           ; D2820031 04C65D33
	V_OR_B32_e64 v51, 8, v41, 0, 0, 0, 0               ; D2380033 02025288
	BUFFER_LOAD_DWORD v51, s[8:11] + v51               ; E0301000 80023333
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v49, v51, v47, v49, 0, 0, 0, 0           ; D2820031 04C65F33
	V_OR_B32_e64 v51, 8, v43, 0, 0, 0, 0               ; D2380033 02025688
	BUFFER_LOAD_DWORD v51, s[8:11] + v51               ; E0301000 80023333
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v49, v51, v52, v49, 0, 0, 0, 0           ; D2820031 04C66933
	V_MAD_F32 v38, v3, v49, v38, 0, 0, 0, 0            ; D2820026 049A6303
	V_OR_B32_e64 v0, 12, v0, 0, 0, 0, 0                ; D2380000 0202008C
	BUFFER_LOAD_DWORD v0, s[8:11] + v0                 ; E0301000 80020000
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MUL_F32_e32 v0, v0, v45                          ; 10005B00
	V_OR_B32_e64 v40, 12, v40, 0, 0, 0, 0              ; D2380028 0202508C
	BUFFER_LOAD_DWORD v40, s[8:11] + v40               ; E0301000 80022828
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v0, v40, v46, v0, 0, 0, 0, 0             ; D2820000 04025D28
	V_OR_B32_e64 v40, 12, v41, 0, 0, 0, 0              ; D2380028 0202528C
	BUFFER_LOAD_DWORD v40, s[8:11] + v40               ; E0301000 80022828
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v0, v40, v47, v0, 0, 0, 0, 0             ; D2820000 04025F28
	V_OR_B32_e64 v40, 12, v43, 0, 0, 0, 0              ; D2380028 0202568C
	BUFFER_LOAD_DWORD v40, s[8:11] + v40               ; E0301000 80022828
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v0, v40, v52, v0, 0, 0, 0, 0             ; D2820000 04026928
	V_MAD_F32 v38, v4, v0, v38, 0, 0, 0, 0             ; D2820026 049A0104
	V_ADD_I32_e32 v0, 41, v42                          ; 4A0054A9
	V_LSHLREV_B32_e32 v0, 4, v0                        ; 34000084
	BUFFER_LOAD_DWORD v40, s[8:11] + v0                ; E0301000 80022800
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MUL_F32_e32 v40, v40, v45                        ; 10505B28
	V_ADD_I32_e32 v41, 41, v44                         ; 4A5258A9
	V_LSHLREV_B32_e32 v41, 4, v41                      ; 34525284
	BUFFER_LOAD_DWORD v42, s[8:11] + v41               ; E0301000 80022A29
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v40, v42, v46, v40, 0, 0, 0, 0           ; D2820028 04A25D2A
	V_ADD_I32_e32 v42, 41, v50                         ; 4A5464A9
	V_LSHLREV_B32_e32 v42, 4, v42                      ; 34545484
	BUFFER_LOAD_DWORD v43, s[8:11] + v42               ; E0301000 80022B2A
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v40, v43, v47, v40, 0, 0, 0, 0           ; D2820028 04A25F2B
	V_ADD_I32_e32 v39, 41, v39                         ; 4A4E4EA9
	V_LSHLREV_B32_e32 v39, 4, v39                      ; 344E4E84
	BUFFER_LOAD_DWORD v43, s[8:11] + v39               ; E0301000 80022B27
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v40, v43, v52, v40, 0, 0, 0, 0           ; D2820028 04A2692B
	V_OR_B32_e64 v43, 4, v0, 0, 0, 0, 0                ; D238002B 02020084
	BUFFER_LOAD_DWORD v43, s[8:11] + v43               ; E0301000 80022B2B
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MUL_F32_e32 v43, v43, v45                        ; 10565B2B
	V_OR_B32_e64 v44, 4, v41, 0, 0, 0, 0               ; D238002C 02025284
	BUFFER_LOAD_DWORD v44, s[8:11] + v44               ; E0301000 80022C2C
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v43, v44, v46, v43, 0, 0, 0, 0           ; D282002B 04AE5D2C
	V_OR_B32_e64 v44, 4, v42, 0, 0, 0, 0               ; D238002C 02025484
	BUFFER_LOAD_DWORD v44, s[8:11] + v44               ; E0301000 80022C2C
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v43, v44, v47, v43, 0, 0, 0, 0           ; D282002B 04AE5F2C
	V_OR_B32_e64 v44, 4, v39, 0, 0, 0, 0               ; D238002C 02024E84
	BUFFER_LOAD_DWORD v44, s[8:11] + v44               ; E0301000 80022C2C
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v43, v44, v52, v43, 0, 0, 0, 0           ; D282002B 04AE692C
	V_MUL_F32_e32 v43, v2, v43                         ; 10565702
	V_MAD_F32 v40, v1, v40, v43, 0, 0, 0, 0            ; D2820028 04AE5101
	V_OR_B32_e64 v43, 8, v0, 0, 0, 0, 0                ; D238002B 02020088
	BUFFER_LOAD_DWORD v43, s[8:11] + v43               ; E0301000 80022B2B
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MUL_F32_e32 v43, v43, v45                        ; 10565B2B
	V_OR_B32_e64 v44, 8, v41, 0, 0, 0, 0               ; D238002C 02025288
	BUFFER_LOAD_DWORD v44, s[8:11] + v44               ; E0301000 80022C2C
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v43, v44, v46, v43, 0, 0, 0, 0           ; D282002B 04AE5D2C
	V_OR_B32_e64 v44, 8, v42, 0, 0, 0, 0               ; D238002C 02025488
	BUFFER_LOAD_DWORD v44, s[8:11] + v44               ; E0301000 80022C2C
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v43, v44, v47, v43, 0, 0, 0, 0           ; D282002B 04AE5F2C
	V_OR_B32_e64 v44, 8, v39, 0, 0, 0, 0               ; D238002C 02024E88
	BUFFER_LOAD_DWORD v44, s[8:11] + v44               ; E0301000 80022C2C
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v43, v44, v52, v43, 0, 0, 0, 0           ; D282002B 04AE692C
	V_MAD_F32 v40, v3, v43, v40, 0, 0, 0, 0            ; D2820028 04A25703
	V_OR_B32_e64 v0, 12, v0, 0, 0, 0, 0                ; D2380000 0202008C
	BUFFER_LOAD_DWORD v0, s[8:11] + v0                 ; E0301000 80020000
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MUL_F32_e32 v0, v0, v45                          ; 10005B00
	V_OR_B32_e64 v41, 12, v41, 0, 0, 0, 0              ; D2380029 0202528C
	BUFFER_LOAD_DWORD v41, s[8:11] + v41               ; E0301000 80022929
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v0, v41, v46, v0, 0, 0, 0, 0             ; D2820000 04025D29
	V_OR_B32_e64 v41, 12, v42, 0, 0, 0, 0              ; D2380029 0202548C
	BUFFER_LOAD_DWORD v41, s[8:11] + v41               ; E0301000 80022929
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v0, v41, v47, v0, 0, 0, 0, 0             ; D2820000 04025F29
	V_OR_B32_e64 v39, 12, v39, 0, 0, 0, 0              ; D2380027 02024E8C
	BUFFER_LOAD_DWORD v39, s[8:11] + v39               ; E0301000 80022727
	S_WAITCNT vmcnt(0)                                 ; BF8C0770
	V_MAD_F32 v0, v39, v52, v0, 0, 0, 0, 0             ; D2820000 04026927
	V_MAD_F32 v39, v4, v0, v40, 0, 0, 0, 0             ; D2820027 04A20104
	S_OR_B64 exec, exec, s[2:3]                        ; 88FE027E
	V_MUL_F32_e64 v0, v38, v36, 0, 0, 0, 0             ; D2100000 02024926
	V_MAD_F32 v0, v39, v35, v0, 0, 0, 0, 0             ; D2820000 04024727
	V_MAD_F32 v0, v37, v32, v0, 0, 0, 0, 0             ; D2820000 04024125
	V_MAD_F32 v0, v4, v29, v0, 0, 0, 0, 0              ; D2820000 04023B04
	V_MUL_F32_e64 v29, v6, v34, 0, 0, 0, 0             ; D210001D 02024506
	V_MAD_F32 v29, v5, v33, v29, 0, 0, 0, 0            ; D282001D 04764305
	V_MAD_F32 v28, v7, v28, v29, 0, 0, 0, 0            ; D282001C 04763907
	V_MAD_F32 v18, v8, v18, v28, 0, 0, 0, 0            ; D2820012 04722508
	V_MUL_F32_e64 v28, v6, v31, 0, 0, 0, 0             ; D210001C 02023F06
	V_MAD_F32 v28, v5, v30, v28, 0, 0, 0, 0            ; D282001C 04723D05
	V_MAD_F32 v19, v7, v19, v28, 0, 0, 0, 0            ; D2820013 04722707
	V_MAD_F32 v5, v8, v17, v19, 0, 0, 0, 0             ; D2820005 044E2308
	V_MOV_B32_e32 v6, 1.000000e+00                     ; 7E0C02F2
	EXP 15, 32, 0, 0, 0, v5, v18, v0, v6               ; F800020F 06001205
	S_WAITCNT expcnt(0)                                ; BF8C070F
	V_MUL_F32_e64 v0, v38, v27, 0, 0, 0, 0             ; D2100000 02023726
	V_MAD_F32 v0, v39, v26, v0, 0, 0, 0, 0             ; D2820000 04023527
	V_MAD_F32 v0, v37, v16, v0, 0, 0, 0, 0             ; D2820000 04022125
	V_MAD_F32 v0, v4, v12, v0, 0, 0, 0, 0              ; D2820000 04021904
	V_MUL_F32_e64 v5, v38, v25, 0, 0, 0, 0             ; D2100005 02023326
	V_MAD_F32 v5, v39, v24, v5, 0, 0, 0, 0             ; D2820005 04163127
	V_MAD_F32 v5, v37, v15, v5, 0, 0, 0, 0             ; D2820005 04161F25
	V_MAD_F32 v5, v4, v11, v5, 0, 0, 0, 0              ; D2820005 04161704
	V_MUL_F32_e64 v6, v38, v23, 0, 0, 0, 0             ; D2100006 02022F26
	V_MAD_F32 v6, v39, v22, v6, 0, 0, 0, 0             ; D2820006 041A2D27
	V_MAD_F32 v6, v37, v14, v6, 0, 0, 0, 0             ; D2820006 041A1D25
	V_MAD_F32 v6, v4, v10, v6, 0, 0, 0, 0              ; D2820006 041A1504
	V_MUL_F32_e64 v7, v38, v21, 0, 0, 0, 0             ; D2100007 02022B26
	V_MAD_F32 v7, v39, v20, v7, 0, 0, 0, 0             ; D2820007 041E2927
	V_MAD_F32 v7, v37, v13, v7, 0, 0, 0, 0             ; D2820007 041E1B25
	V_MAD_F32 v1, v4, v9, v7, 0, 0, 0, 0               ; D2820001 041E1304
	EXP 15, 12, 0, 0, 0, v1, v6, v5, v0                ; F80000CF 00050601
	S_LOAD_DWORDX4 s[0:3], s[0:1], 64                  ; C0800140
	S_WAITCNT expcnt(0) lgkmcnt(0)                     ; BF8C000F
	S_BUFFER_LOAD_DWORD s4, s[0:3], 13                 ; C202010D
	S_WAITCNT lgkmcnt(0)                               ; BF8C007F
	V_MUL_F32_e32 v2, s4, v6                           ; 10040C04
	S_BUFFER_LOAD_DWORD s4, s[0:3], 12                 ; C202010C
	S_WAITCNT lgkmcnt(0)                               ; BF8C007F
	V_MAD_F32 v2, s4, v1, v2, 0, 0, 0, 0               ; D2820002 040A0204
	S_BUFFER_LOAD_DWORD s4, s[0:3], 14                 ; C202010E
	S_WAITCNT lgkmcnt(0)                               ; BF8C007F
	V_MAD_F32 v2, s4, v5, v2, 0, 0, 0, 0               ; D2820002 040A0A04
	S_BUFFER_LOAD_DWORD s4, s[0:3], 15                 ; C202010F
	S_WAITCNT lgkmcnt(0)                               ; BF8C007F
	V_MAD_F32 v2, s4, v0, v2, 0, 0, 0, 0               ; D2820002 040A0004
	S_BUFFER_LOAD_DWORD s4, s[0:3], 9                  ; C2020109
	S_WAITCNT lgkmcnt(0)                               ; BF8C007F
	V_MUL_F32_e32 v3, s4, v6                           ; 10060C04
	S_BUFFER_LOAD_DWORD s4, s[0:3], 8                  ; C2020108
	S_WAITCNT lgkmcnt(0)                               ; BF8C007F
	V_MAD_F32 v3, s4, v1, v3, 0, 0, 0, 0               ; D2820003 040E0204
	S_BUFFER_LOAD_DWORD s4, s[0:3], 10                 ; C202010A
	S_WAITCNT lgkmcnt(0)                               ; BF8C007F
	V_MAD_F32 v3, s4, v5, v3, 0, 0, 0, 0               ; D2820003 040E0A04
	S_BUFFER_LOAD_DWORD s4, s[0:3], 11                 ; C202010B
	S_WAITCNT lgkmcnt(0)                               ; BF8C007F
	V_MAD_F32 v3, s4, v0, v3, 0, 0, 0, 0               ; D2820003 040E0004
	S_BUFFER_LOAD_DWORD s4, s[0:3], 5                  ; C2020105
	S_WAITCNT lgkmcnt(0)                               ; BF8C007F
	V_MUL_F32_e32 v4, s4, v6                           ; 10080C04
	S_BUFFER_LOAD_DWORD s4, s[0:3], 4                  ; C2020104
	S_WAITCNT lgkmcnt(0)                               ; BF8C007F
	V_MAD_F32 v4, s4, v1, v4, 0, 0, 0, 0               ; D2820004 04120204
	S_BUFFER_LOAD_DWORD s4, s[0:3], 6                  ; C2020106
	S_WAITCNT lgkmcnt(0)                               ; BF8C007F
	V_MAD_F32 v4, s4, v5, v4, 0, 0, 0, 0               ; D2820004 04120A04
	S_BUFFER_LOAD_DWORD s4, s[0:3], 7                  ; C2020107
	S_WAITCNT lgkmcnt(0)                               ; BF8C007F
	V_MAD_F32 v4, s4, v0, v4, 0, 0, 0, 0               ; D2820004 04120004
	S_BUFFER_LOAD_DWORD s4, s[0:3], 1                  ; C2020101
	S_WAITCNT lgkmcnt(0)                               ; BF8C007F
	V_MUL_F32_e32 v6, s4, v6                           ; 100C0C04
	S_BUFFER_LOAD_DWORD s4, s[0:3], 0                  ; C2020100
	S_WAITCNT lgkmcnt(0)                               ; BF8C007F
	V_MAD_F32 v1, s4, v1, v6, 0, 0, 0, 0               ; D2820001 041A0204
	S_BUFFER_LOAD_DWORD s4, s[0:3], 2                  ; C2020102
	S_WAITCNT lgkmcnt(0)                               ; BF8C007F
	V_MAD_F32 v1, s4, v5, v1, 0, 0, 0, 0               ; D2820001 04060A04
	S_BUFFER_LOAD_DWORD s0, s[0:3], 3                  ; C2000103
	S_WAITCNT lgkmcnt(0)                               ; BF8C007F
	V_MAD_F32 v0, s0, v0, v1, 0, 0, 0, 0               ; D2820000 04060000
	EXP 15, 13, 0, 1, 0, v0, v4, v3, v2                ; F80008DF 02030400
	S_ENDPGM                                           ; BF810000

FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], POSITION, LINEAR
DCL IN[1], FACE, CONSTANT
DCL IN[2], GENERIC[19], PERSPECTIVE
DCL IN[3], GENERIC[20], PERSPECTIVE
DCL IN[4], GENERIC[21], PERSPECTIVE
DCL IN[5], GENERIC[22], PERSPECTIVE
DCL IN[6], GENERIC[23], PERSPECTIVE
DCL IN[7], GENERIC[24], PERSPECTIVE
DCL IN[8], GENERIC[25], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL SAMP[1]
DCL SAMP[2]
DCL SAMP[3]
DCL SAMP[4]
DCL SAMP[5]
DCL SAMP[6]
DCL SAMP[7]
DCL SAMP[8]
DCL CONST[54]
DCL CONST[0..44]
DCL TEMP[0..1]
DCL TEMP[2..22], LOCAL
IMM[0] FLT32 {    0.0000,     1.0000,    -1.0000,     4.5948}
IMM[1] FLT32 {   32.0000,   -16.0000,     0.5000,     4.0000}
IMM[2] FLT32 {    2.0000,    -0.0010,     0.0000,     0.0000}
IMM[3] FLT32 {    0.0000,     0.0100,     0.2500,     3.0000}
IMM[4] FLT32 {    0.0000, 65504.0000,     0.0000,     0.0000}
  0: MOV TEMP[0], IN[0]
  1: MAD TEMP[0].y, IN[0], CONST[54].xxxx, CONST[54].yyyy
  2: MOV_SAT TEMP[1], IN[1]
  3: MOV TEMP[2].x, IN[7].wwww
  4: MOV TEMP[2].yz, IN[8].yxyy
  5: UIF TEMP[1].xxxx :3
  6:   MOV TEMP[3].x, IMM[0].zzzz
  7: ELSE :3
  8:   MOV TEMP[3].x, IMM[0].yyyy
  9: ENDIF
 10: ADD TEMP[4].xyz, CONST[11].xyzz, -IN[2].xyzz
 11: DP3 TEMP[5].x, TEMP[4].xyzz, TEMP[4].xyzz
 12: RSQ TEMP[5].x, TEMP[5].xxxx
 13: MUL TEMP[4].xyz, TEMP[4].xyzz, TEMP[5].xxxx
 14: MUL TEMP[5].x, TEMP[3].xxxx, CONST[14].wwww
 15: MUL TEMP[6].xy, TEMP[0].xyyy, CONST[12].xyyy
 16: MOV TEMP[7].xy, IN[4].zwww
 17: TEX TEMP[7], TEMP[7], SAMP[2], 2D
 18: MOV TEMP[8].w, TEMP[7].wwww
 19: MUL TEMP[8].xyz, TEMP[7].xyzz, IMM[0].wwww
 20: LRP TEMP[8].xyz, CONST[1].wwww, TEMP[8].xyzz, IMM[0].yyyy
 21: MOV TEMP[9].xy, IN[5].xyyy
 22: TEX TEMP[9], TEMP[9], SAMP[4], 2D
 23: MOV TEMP[10].xyz, TEMP[9]
 24: MOV TEMP[11].xy, IN[3].xyyy
 25: TEX TEMP[11], TEMP[11], SAMP[3], 2D
 26: MUL TEMP[12], TEMP[11], CONST[0]
 27: MUL TEMP[12], TEMP[12], IN[6]
 28: MOV TEMP[13].w, TEMP[12].wwww
 29: ADD TEMP[14].x, IMM[0].yyyy, -TEMP[11].wwww
 30: MUL TEMP[14].x, TEMP[14].xxxx, CONST[12].zzzz
 31: LRP TEMP[13].xyz, TEMP[14].xxxx, TEMP[11].xyzz, TEMP[12].xyzz
 32: MOV TEMP[11].xy, IN[3].zwww
 33: TEX TEMP[11].xyw, TEMP[11], SAMP[5], 2D
 34: MUL TEMP[12].xy, CONST[14].xyyy, TEMP[11].wxxx
 35: ADD TEMP[12].xy, IMM[0].yyyy, -TEMP[12].xyyy
 36: MUL TEMP[13], TEMP[13], TEMP[8]
 37: DP3 TEMP[8].x, IN[7].xyzz, IN[7].xyzz
 38: RSQ TEMP[8].x, TEMP[8].xxxx
 39: MUL TEMP[8].xyz, IN[7].xyzz, TEMP[8].xxxx
 40: FSLT TEMP[5].x, IMM[0].xxxx, TEMP[5].xxxx
 41: UIF TEMP[5].xxxx :3
 42:   MOV TEMP[5].xyz, -TEMP[8].xyzx
 43: ELSE :3
 44:   MOV TEMP[5].xyz, TEMP[8].xyzx
 45: ENDIF
 46: MOV TEMP[8].w, TEMP[13].wwww
 47: MOV TEMP[6].xy, TEMP[6].xyyy
 48: TEX TEMP[6], TEMP[6], SAMP[8], 2D
 49: MAD TEMP[3], TEMP[6], CONST[10].xxxz, CONST[10].yyyw
 50: MOV TEMP[6].xy, IN[4].xyyy
 51: TEX TEMP[6], TEMP[6], SAMP[6], 2D
 52: MAD TEMP[14].x, TEMP[6].wwww, IMM[1].xxxx, IMM[1].yyyy
 53: EX2 TEMP[14].x, TEMP[14].xxxx
 54: MUL TEMP[6].xyz, TEMP[6].xyzz, TEMP[14].xxxx
 55: MAD TEMP[2].xyz, CONST[3].xyzz, TEMP[6].xyzz, TEMP[2].xyzz
 56: MUL TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].wwww
 57: MAD TEMP[6].x, TEMP[3].wwww, IMM[1].zzzz, IMM[1].zzzz
 58: DP3_SAT TEMP[14].x, TEMP[5].xyzz, TEMP[4].xyzz
 59: ADD TEMP[14].x, IMM[0].yyyy, -TEMP[14].xxxx
 60: POW TEMP[14].x, TEMP[14].xxxx, IMM[1].wwww
 61: MUL TEMP[14].x, TEMP[14].xxxx, CONST[3].wwww
 62: MUL TEMP[15].xy, TEMP[12].xyyy, TEMP[14].xxxx
 63: ADD TEMP[15].y, TEMP[12].xyyy, -TEMP[15].xyyy
 64: DP3 TEMP[16].x, TEMP[5].xyzz, TEMP[4].xyzz
 65: MUL TEMP[16].xyz, TEMP[16].xxxx, TEMP[5].xyzz
 66: MUL TEMP[16].xyz, IMM[2].xxxx, TEMP[16].xyzz
 67: ADD TEMP[16].xyz, TEMP[4].xyzz, -TEMP[16].xyzz
 68: LRP TEMP[17].xyz, TEMP[15].yyyy, -TEMP[5].xyzz, TEMP[16].xyzz
 69: ABS TEMP[18].xyz, TEMP[17].xyzz
 70: MAX TEMP[19].x, TEMP[18].yyyy, TEMP[18].zzzz
 71: MAX TEMP[19].x, TEMP[18].xxxx, TEMP[19].xxxx
 72: ADD TEMP[20].x, TEMP[19].xxxx, IMM[2].yyyy
 73: FSGE TEMP[21].x, TEMP[20].xxxx, TEMP[18].xxxx
 74: AND TEMP[21].x, TEMP[21].xxxx, IMM[0].yyyy
 75: FSGE TEMP[22].x, TEMP[20].xxxx, TEMP[18].yyyy
 76: AND TEMP[22].x, TEMP[22].xxxx, IMM[0].yyyy
 77: MOV TEMP[21].y, TEMP[22].xxxx
 78: FSGE TEMP[18].x, TEMP[20].xxxx, TEMP[18].zzzz
 79: AND TEMP[18].x, TEMP[18].xxxx, IMM[0].yyyy
 80: MOV TEMP[21].z, TEMP[18].xxxx
 81: RCP TEMP[18].x, TEMP[19].xxxx
 82: MUL TEMP[18].xyz, IMM[0].zzyy, TEMP[18].xxxx
 83: MUL TEMP[16].xyz, TEMP[17].xyzz, TEMP[18].xyzz
 84: ADD TEMP[17].x, CONST[14].zzzz, IMM[0].zzzz
 85: MUL TEMP[17].x, TEMP[15].yyyy, TEMP[17].xxxx
 86: MUL TEMP[18].xyz, TEMP[16].xyzz, TEMP[21].xyzz
 87: FLR TEMP[19].x, TEMP[17].xxxx
 88: ADD TEMP[19].x, CONST[14].zzzz, -TEMP[19].xxxx
 89: EX2 TEMP[19].x, TEMP[19].xxxx
 90: RCP TEMP[19].x, TEMP[19].xxxx
 91: MUL TEMP[18].xyz, TEMP[18].xyzz, TEMP[19].xxxx
 92: ADD TEMP[16].xyz, TEMP[16].xyzz, -TEMP[18].xyzz
 93: MOV TEMP[16].xyz, TEMP[16].xyzz
 94: MOV TEMP[16].w, TEMP[17].xxxx
 95: TXL TEMP[16], TEMP[16], SAMP[7], CUBE
 96: MAD TEMP[17].x, TEMP[16].wwww, IMM[1].xxxx, IMM[1].yyyy
 97: EX2 TEMP[17].x, TEMP[17].xxxx
 98: MUL TEMP[16].xyz, TEMP[16].xyzz, TEMP[17].xxxx
 99: MUL TEMP[17].xyz, CONST[1].xyzz, TEMP[11].yyyy
100: MUL TEMP[17].xyz, TEMP[17].xyzz, TEMP[11].yyyy
101: MAD_SAT TEMP[15].x, TEMP[15].yyyy, IMM[2].xxxx, IMM[0].zzzz
102: MUL TEMP[3].xyz, TEMP[3].xyzz, TEMP[6].xxxx
103: MUL TEMP[16].xyz, TEMP[16].xyzz, CONST[2].xyzz
104: MUL TEMP[16].xyz, TEMP[17].xyzz, TEMP[16].xyzz
105: LRP TEMP[15].xyz, TEMP[15].xxxx, TEMP[17].xyzz, TEMP[16].xyzz
106: LRP TEMP[14].xyz, TEMP[14].xxxx, IMM[0].yyyy, TEMP[17].xyzz
107: LRP TEMP[14].xyz, TEMP[14].xyzz, TEMP[15].xyzz, TEMP[13].xyzz
108: MUL TEMP[2].xyz, TEMP[2].xyzz, TEMP[14].xyzz
109: MAD TEMP[2].xyz, TEMP[3].xyzz, TEMP[13].xyzz, TEMP[2].xyzz
110: ADD TEMP[3].xyz, IN[2].xyzz, -CONST[30].xyzz
111: DP3 TEMP[14].x, TEMP[3].xyzz, TEMP[3].xyzz
112: RSQ TEMP[14].x, TEMP[14].xxxx
113: MUL TEMP[15].x, CONST[31].wwww, TEMP[14].xxxx
114: RCP TEMP[15].x, TEMP[15].xxxx
115: MOV_SAT TEMP[15].x, TEMP[15].xxxx
116: ADD TEMP[15].x, IMM[0].yyyy, -TEMP[15].xxxx
117: MUL TEMP[15].x, TEMP[15].xxxx, TEMP[14].xxxx
118: MUL TEMP[3].xyz, -TEMP[3].xyzz, TEMP[14].xxxx
119: DP3 TEMP[14].x, TEMP[3].xyzz, -CONST[31].xyzz
120: MUL TEMP[14].x, TEMP[14].xxxx, CONST[29].wwww
121: ADD_SAT TEMP[14].x, CONST[30].wwww, -TEMP[14].xxxx
122: MUL TEMP[15].x, TEMP[15].xxxx, TEMP[14].xxxx
123: DP3_SAT TEMP[14].x, TEMP[5].xyzz, TEMP[3].xyzz
124: ADD TEMP[3].xyz, TEMP[4].xyzz, TEMP[3].xyzz
125: DP3 TEMP[16].x, TEMP[3].xyzz, TEMP[3].xyzz
126: RSQ TEMP[16].x, TEMP[16].xxxx
127: MUL TEMP[3].xyz, TEMP[3].xyzz, TEMP[16].xxxx
128: DP3 TEMP[16].x, TEMP[3].xyzz, TEMP[5].xyzz
129: DDX TEMP[17].x, TEMP[16].xxxx
130: ABS TEMP[17].x, TEMP[17].xxxx
131: MUL TEMP[19], CONST[54].xxxx, TEMP[16].xxxx
132: DDY TEMP[18].x, TEMP[19]
133: ABS TEMP[18].x, TEMP[18].xxxx
134: ADD TEMP[17].x, TEMP[17].xxxx, TEMP[18].xxxx
135: MAD TEMP[17].x, TEMP[17].xxxx, IMM[1].zzzz, IMM[2].zzzz
136: MAD_SAT TEMP[16].xy, TEMP[17].xxxx, IMM[0].zyyy, TEMP[16].xxxx
137: DP3_SAT TEMP[3].x, TEMP[3].xyzz, TEMP[4].xyzz
138: ADD TEMP[3].x, IMM[0].yyyy, -TEMP[3].xxxx
139: POW TEMP[3].x, TEMP[3].xxxx, IMM[1].wwww
140: MUL TEMP[3].x, TEMP[3].xxxx, CONST[3].wwww
141: MUL TEMP[3].xy, TEMP[12].xyyy, TEMP[3].xxxx
142: ADD TEMP[3].xy, TEMP[12].xyyy, -TEMP[3].xyyy
143: POW TEMP[12].x, TEMP[3].xxxx, IMM[1].wwww
144: POW TEMP[12].y, TEMP[3].yyyy, IMM[1].wwww
145: ADD_SAT TEMP[3].xy, TEMP[12].xyyy, IMM[2].wwww
146: MUL TEMP[12], TEMP[16].xyxy, TEMP[3].xxyy
147: ADD TEMP[17], TEMP[3].xxyy, IMM[0].zzzz
148: MAD TEMP[17], TEMP[16].xyxy, TEMP[17], IMM[0].yyyy
149: RCP TEMP[18].x, TEMP[17].xxxx
150: RCP TEMP[18].y, TEMP[17].yyyy
151: RCP TEMP[18].z, TEMP[17].zzzz
152: RCP TEMP[18].w, TEMP[17].wwww
153: MUL_SAT TEMP[12], TEMP[12], TEMP[18]
154: ADD TEMP[12].xy, TEMP[12].ywww, -TEMP[12].xzzz
155: ADD TEMP[16].x, TEMP[16].yyyy, -TEMP[16].xxxx
156: ADD TEMP[16].x, TEMP[16].xxxx, IMM[3].xxxx
157: DP3_SAT TEMP[17].x, TEMP[5].xyzz, TEMP[4].xyzz
158: MUL TEMP[17].x, TEMP[17].xxxx, TEMP[14].xxxx
159: MAX TEMP[17].x, TEMP[17].xxxx, IMM[3].yyyy
160: RSQ TEMP[18].x, TEMP[17].xxxx
161: MUL TEMP[18].x, TEMP[18].xxxx, TEMP[17].xxxx
162: CMP TEMP[18].x, -TEMP[17].xxxx, TEMP[18].xxxx, IMM[0].xxxx
163: LRP TEMP[3].xy, TEMP[3].xyyy, IMM[0].yyyy, TEMP[18].xxxx
164: MUL TEMP[3].xy, TEMP[16].xxxx, TEMP[3].xyyy
165: RCP TEMP[16].x, TEMP[3].xxxx
166: RCP TEMP[16].y, TEMP[3].yyyy
167: MUL TEMP[3].y, TEMP[12].xyyy, TEMP[16].xyyy
168: MUL TEMP[12].xyz, CONST[1].xyzz, TEMP[11].yyyy
169: MUL TEMP[11].xyz, TEMP[12].xyzz, TEMP[11].yyyy
170: LRP TEMP[3].xyz, TEMP[11].xyzz, TEMP[3].yyyy, TEMP[13].xyzz
171: MUL TEMP[3].xyz, TEMP[3].xyzz, TEMP[14].xxxx
172: MUL TEMP[3].xyz, TEMP[3].xyzz, CONST[29].xyzz
173: MUL TEMP[3].xyz, TEMP[3].xyzz, TEMP[15].xxxx
174: DP4 TEMP[11].x, IN[2], CONST[35]
175: DP4 TEMP[12].x, IN[2], CONST[36]
176: MOV TEMP[11].y, TEMP[12].xxxx
177: DP4 TEMP[12].x, IN[2], CONST[37]
178: DP4 TEMP[13].x, IN[2], CONST[38]
179: RCP TEMP[13].x, TEMP[13].xxxx
180: MUL TEMP[11].xy, TEMP[11].xyyy, TEMP[13].xxxx
181: MAD TEMP[11].xy, TEMP[11].xyyy, IMM[1].zzzz, IMM[1].zzzz
182: MAD TEMP[13].xy, TEMP[11].xyyy, CONST[34].xyyy, CONST[34].zwww
183: MOV TEMP[13].xy, TEMP[13].xyyy
184: TEX TEMP[13].xyz, TEMP[13], SAMP[1], 2D
185: MOV TEMP[11].xy, TEMP[11].xyyy
186: MOV TEMP[11].w, IMM[0].xxxx
187: TXL TEMP[11].xy, TEMP[11], SAMP[0], 2D
188: ADD TEMP[14].x, IMM[0].yyyy, -TEMP[11].yyyy
189: MUL TEMP[14].x, TEMP[14].xxxx, IMM[3].zzzz
190: ADD TEMP[14].x, TEMP[11].xxxx, -TEMP[14].xxxx
191: ADD TEMP[12].x, TEMP[11].xxxx, -TEMP[12].xxxx
192: MUL TEMP[11].x, TEMP[11].xxxx, TEMP[11].xxxx
193: ADD TEMP[11].x, TEMP[14].xxxx, -TEMP[11].xxxx
194: MAX TEMP[11].x, TEMP[11].xxxx, CONST[32].xxxx
195: MAD TEMP[14].x, TEMP[12].xxxx, TEMP[12].xxxx, TEMP[11].xxxx
196: RCP TEMP[14].x, TEMP[14].xxxx
197: MUL TEMP[11].x, TEMP[11].xxxx, TEMP[14].xxxx
198: POW TEMP[11].x, TEMP[11].xxxx, CONST[32].yyyy
199: MAD_SAT TEMP[11].x, TEMP[11].xxxx, CONST[33].zzzz, CONST[33].wwww
200: MUL TEMP[14].x, TEMP[11].xxxx, TEMP[11].xxxx
201: MUL TEMP[11].x, IMM[2].xxxx, TEMP[11].xxxx
202: ADD TEMP[11].x, IMM[3].wwww, -TEMP[11].xxxx
203: MUL TEMP[11].x, TEMP[14].xxxx, TEMP[11].xxxx
204: FSGE TEMP[12].x, TEMP[12].xxxx, IMM[0].xxxx
205: UIF TEMP[12].xxxx :3
206:   MOV TEMP[12].x, IMM[0].yyyy
207: ELSE :3
208:   MOV TEMP[12].x, TEMP[11].xxxx
209: ENDIF
210: MUL TEMP[11].xyz, TEMP[13].xyzz, TEMP[12].xxxx
211: MUL TEMP[3].xyz, TEMP[3].xyzz, TEMP[11].xyzz
212: MAD TEMP[8].xyz, TEMP[3].xyzz, TEMP[6].xxxx, TEMP[2].xyzz
213: LRP TEMP[2].x, TEMP[7].wwww, TEMP[9].wwww, IMM[0].yyyy
214: MOV TEMP[10].w, TEMP[2].xxxx
215: LRP TEMP[2], CONST[9].xxxy, TEMP[10], IMM[0].yyyy
216: MUL TEMP[2].xyz, TEMP[2].xyzz, TEMP[2].wwww
217: MUL TEMP[8].xyz, TEMP[8].xyzz, TEMP[2].xyzz
218: DP3 TEMP[2].x, TEMP[5].xyzz, TEMP[4].xyzz
219: ABS TEMP[2].x, TEMP[2].xxxx
220: MUL TEMP[2].x, TEMP[2].xxxx, TEMP[2].xxxx
221: MAD_SAT TEMP[2].x, TEMP[2].xxxx, CONST[13].xxxx, CONST[13].yyyy
222: ADD TEMP[2].x, IMM[0].yyyy, -TEMP[2].xxxx
223: MUL TEMP[2], CONST[4].zzzw, TEMP[2].xxxx
224: LRP TEMP[2], TEMP[2], CONST[4].xxxy, TEMP[8]
225: MAX TEMP[3].xyz, TEMP[2].xyzz, IMM[4].xxxx
226: MIN TEMP[8].xyz, TEMP[3].xyzz, IMM[4].yyyy
227: MAD_SAT TEMP[2].x, TEMP[2].wwww, CONST[13].zzzz, CONST[13].wwww
228: MOV TEMP[8].w, TEMP[2].xxxx
229: MOV OUT[0], TEMP[8]
230: END
; ModuleID = 'tgsi'

@ddxy_lds = external addrspace(3) global [64 x i32]

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %21 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
  %22 = load <16 x i8> addrspace(2)* %21, !tbaa !0
  %23 = call float @llvm.SI.load.const(<16 x i8> %22, i32 0)
  %24 = call float @llvm.SI.load.const(<16 x i8> %22, i32 4)
  %25 = call float @llvm.SI.load.const(<16 x i8> %22, i32 8)
  %26 = call float @llvm.SI.load.const(<16 x i8> %22, i32 12)
  %27 = call float @llvm.SI.load.const(<16 x i8> %22, i32 16)
  %28 = call float @llvm.SI.load.const(<16 x i8> %22, i32 20)
  %29 = call float @llvm.SI.load.const(<16 x i8> %22, i32 24)
  %30 = call float @llvm.SI.load.const(<16 x i8> %22, i32 28)
  %31 = call float @llvm.SI.load.const(<16 x i8> %22, i32 32)
  %32 = call float @llvm.SI.load.const(<16 x i8> %22, i32 36)
  %33 = call float @llvm.SI.load.const(<16 x i8> %22, i32 40)
  %34 = call float @llvm.SI.load.const(<16 x i8> %22, i32 48)
  %35 = call float @llvm.SI.load.const(<16 x i8> %22, i32 52)
  %36 = call float @llvm.SI.load.const(<16 x i8> %22, i32 56)
  %37 = call float @llvm.SI.load.const(<16 x i8> %22, i32 60)
  %38 = call float @llvm.SI.load.const(<16 x i8> %22, i32 64)
  %39 = call float @llvm.SI.load.const(<16 x i8> %22, i32 68)
  %40 = call float @llvm.SI.load.const(<16 x i8> %22, i32 72)
  %41 = call float @llvm.SI.load.const(<16 x i8> %22, i32 76)
  %42 = call float @llvm.SI.load.const(<16 x i8> %22, i32 144)
  %43 = call float @llvm.SI.load.const(<16 x i8> %22, i32 148)
  %44 = call float @llvm.SI.load.const(<16 x i8> %22, i32 160)
  %45 = call float @llvm.SI.load.const(<16 x i8> %22, i32 164)
  %46 = call float @llvm.SI.load.const(<16 x i8> %22, i32 168)
  %47 = call float @llvm.SI.load.const(<16 x i8> %22, i32 172)
  %48 = call float @llvm.SI.load.const(<16 x i8> %22, i32 176)
  %49 = call float @llvm.SI.load.const(<16 x i8> %22, i32 180)
  %50 = call float @llvm.SI.load.const(<16 x i8> %22, i32 184)
  %51 = call float @llvm.SI.load.const(<16 x i8> %22, i32 192)
  %52 = call float @llvm.SI.load.const(<16 x i8> %22, i32 196)
  %53 = call float @llvm.SI.load.const(<16 x i8> %22, i32 200)
  %54 = call float @llvm.SI.load.const(<16 x i8> %22, i32 208)
  %55 = call float @llvm.SI.load.const(<16 x i8> %22, i32 212)
  %56 = call float @llvm.SI.load.const(<16 x i8> %22, i32 216)
  %57 = call float @llvm.SI.load.const(<16 x i8> %22, i32 220)
  %58 = call float @llvm.SI.load.const(<16 x i8> %22, i32 224)
  %59 = call float @llvm.SI.load.const(<16 x i8> %22, i32 228)
  %60 = call float @llvm.SI.load.const(<16 x i8> %22, i32 232)
  %61 = call float @llvm.SI.load.const(<16 x i8> %22, i32 236)
  %62 = call float @llvm.SI.load.const(<16 x i8> %22, i32 464)
  %63 = call float @llvm.SI.load.const(<16 x i8> %22, i32 468)
  %64 = call float @llvm.SI.load.const(<16 x i8> %22, i32 472)
  %65 = call float @llvm.SI.load.const(<16 x i8> %22, i32 476)
  %66 = call float @llvm.SI.load.const(<16 x i8> %22, i32 480)
  %67 = call float @llvm.SI.load.const(<16 x i8> %22, i32 484)
  %68 = call float @llvm.SI.load.const(<16 x i8> %22, i32 488)
  %69 = call float @llvm.SI.load.const(<16 x i8> %22, i32 492)
  %70 = call float @llvm.SI.load.const(<16 x i8> %22, i32 496)
  %71 = call float @llvm.SI.load.const(<16 x i8> %22, i32 500)
  %72 = call float @llvm.SI.load.const(<16 x i8> %22, i32 504)
  %73 = call float @llvm.SI.load.const(<16 x i8> %22, i32 508)
  %74 = call float @llvm.SI.load.const(<16 x i8> %22, i32 512)
  %75 = call float @llvm.SI.load.const(<16 x i8> %22, i32 516)
  %76 = call float @llvm.SI.load.const(<16 x i8> %22, i32 536)
  %77 = call float @llvm.SI.load.const(<16 x i8> %22, i32 540)
  %78 = call float @llvm.SI.load.const(<16 x i8> %22, i32 544)
  %79 = call float @llvm.SI.load.const(<16 x i8> %22, i32 548)
  %80 = call float @llvm.SI.load.const(<16 x i8> %22, i32 552)
  %81 = call float @llvm.SI.load.const(<16 x i8> %22, i32 556)
  %82 = call float @llvm.SI.load.const(<16 x i8> %22, i32 560)
  %83 = call float @llvm.SI.load.const(<16 x i8> %22, i32 564)
  %84 = call float @llvm.SI.load.const(<16 x i8> %22, i32 568)
  %85 = call float @llvm.SI.load.const(<16 x i8> %22, i32 572)
  %86 = call float @llvm.SI.load.const(<16 x i8> %22, i32 576)
  %87 = call float @llvm.SI.load.const(<16 x i8> %22, i32 580)
  %88 = call float @llvm.SI.load.const(<16 x i8> %22, i32 584)
  %89 = call float @llvm.SI.load.const(<16 x i8> %22, i32 588)
  %90 = call float @llvm.SI.load.const(<16 x i8> %22, i32 592)
  %91 = call float @llvm.SI.load.const(<16 x i8> %22, i32 596)
  %92 = call float @llvm.SI.load.const(<16 x i8> %22, i32 600)
  %93 = call float @llvm.SI.load.const(<16 x i8> %22, i32 604)
  %94 = call float @llvm.SI.load.const(<16 x i8> %22, i32 608)
  %95 = call float @llvm.SI.load.const(<16 x i8> %22, i32 612)
  %96 = call float @llvm.SI.load.const(<16 x i8> %22, i32 616)
  %97 = call float @llvm.SI.load.const(<16 x i8> %22, i32 620)
  %98 = call float @llvm.SI.load.const(<16 x i8> %22, i32 864)
  %99 = call float @llvm.SI.load.const(<16 x i8> %22, i32 868)
  %100 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0
  %101 = load <32 x i8> addrspace(2)* %100, !tbaa !0
  %102 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0
  %103 = load <16 x i8> addrspace(2)* %102, !tbaa !0
  %104 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 1
  %105 = load <32 x i8> addrspace(2)* %104, !tbaa !0
  %106 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 1
  %107 = load <16 x i8> addrspace(2)* %106, !tbaa !0
  %108 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 2
  %109 = load <32 x i8> addrspace(2)* %108, !tbaa !0
  %110 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 2
  %111 = load <16 x i8> addrspace(2)* %110, !tbaa !0
  %112 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 3
  %113 = load <32 x i8> addrspace(2)* %112, !tbaa !0
  %114 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 3
  %115 = load <16 x i8> addrspace(2)* %114, !tbaa !0
  %116 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 4
  %117 = load <32 x i8> addrspace(2)* %116, !tbaa !0
  %118 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 4
  %119 = load <16 x i8> addrspace(2)* %118, !tbaa !0
  %120 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 5
  %121 = load <32 x i8> addrspace(2)* %120, !tbaa !0
  %122 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 5
  %123 = load <16 x i8> addrspace(2)* %122, !tbaa !0
  %124 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 6
  %125 = load <32 x i8> addrspace(2)* %124, !tbaa !0
  %126 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 6
  %127 = load <16 x i8> addrspace(2)* %126, !tbaa !0
  %128 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 7
  %129 = load <32 x i8> addrspace(2)* %128, !tbaa !0
  %130 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 7
  %131 = load <16 x i8> addrspace(2)* %130, !tbaa !0
  %132 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 8
  %133 = load <32 x i8> addrspace(2)* %132, !tbaa !0
  %134 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 8
  %135 = load <16 x i8> addrspace(2)* %134, !tbaa !0
  %136 = fcmp ugt float %17, 0.000000e+00
  %137 = select i1 %136, float 1.000000e+00, float 0.000000e+00
  %138 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %4, <2 x i32> %6)
  %139 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %4, <2 x i32> %6)
  %140 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %4, <2 x i32> %6)
  %141 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %4, <2 x i32> %6)
  %142 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %4, <2 x i32> %6)
  %143 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %4, <2 x i32> %6)
  %144 = call float @llvm.SI.fs.interp(i32 2, i32 1, i32 %4, <2 x i32> %6)
  %145 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %4, <2 x i32> %6)
  %146 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %4, <2 x i32> %6)
  %147 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %4, <2 x i32> %6)
  %148 = call float @llvm.SI.fs.interp(i32 2, i32 2, i32 %4, <2 x i32> %6)
  %149 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %4, <2 x i32> %6)
  %150 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %4, <2 x i32> %6)
  %151 = call float @llvm.SI.fs.interp(i32 1, i32 3, i32 %4, <2 x i32> %6)
  %152 = call float @llvm.SI.fs.interp(i32 0, i32 4, i32 %4, <2 x i32> %6)
  %153 = call float @llvm.SI.fs.interp(i32 1, i32 4, i32 %4, <2 x i32> %6)
  %154 = call float @llvm.SI.fs.interp(i32 2, i32 4, i32 %4, <2 x i32> %6)
  %155 = call float @llvm.SI.fs.interp(i32 3, i32 4, i32 %4, <2 x i32> %6)
  %156 = call float @llvm.SI.fs.interp(i32 0, i32 5, i32 %4, <2 x i32> %6)
  %157 = call float @llvm.SI.fs.interp(i32 1, i32 5, i32 %4, <2 x i32> %6)
  %158 = call float @llvm.SI.fs.interp(i32 2, i32 5, i32 %4, <2 x i32> %6)
  %159 = call float @llvm.SI.fs.interp(i32 3, i32 5, i32 %4, <2 x i32> %6)
  %160 = call float @llvm.SI.fs.interp(i32 0, i32 6, i32 %4, <2 x i32> %6)
  %161 = call float @llvm.SI.fs.interp(i32 1, i32 6, i32 %4, <2 x i32> %6)
  %162 = fmul float %14, %98
  %163 = fadd float %162, %99
  %164 = call float @llvm.AMDIL.clamp.(float %137, float 0.000000e+00, float 1.000000e+00)
  %165 = call float @llvm.AMDIL.clamp.(float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
  %166 = call float @llvm.AMDIL.clamp.(float 0.000000e+00, float 0.000000e+00, float 1.000000e+00)
  %167 = call float @llvm.AMDIL.clamp.(float 1.000000e+00, float 0.000000e+00, float 1.000000e+00)
  %168 = bitcast float %164 to i32
  %169 = icmp ne i32 %168, 0
  %. = select i1 %169, float -1.000000e+00, float 1.000000e+00
  %170 = fsub float -0.000000e+00, %138
  %171 = fadd float %48, %170
  %172 = fsub float -0.000000e+00, %139
  %173 = fadd float %49, %172
  %174 = fsub float -0.000000e+00, %140
  %175 = fadd float %50, %174
  %176 = fmul float %171, %171
  %177 = fmul float %173, %173
  %178 = fadd float %177, %176
  %179 = fmul float %175, %175
  %180 = fadd float %178, %179
  %181 = call float @llvm.AMDGPU.rsq(float %180)
  %182 = fmul float %171, %181
  %183 = fmul float %173, %181
  %184 = fmul float %175, %181
  %185 = fmul float %., %61
  %186 = fmul float %13, %51
  %187 = fmul float %163, %52
  %188 = bitcast float %148 to i32
  %189 = bitcast float %149 to i32
  %190 = insertelement <2 x i32> undef, i32 %188, i32 0
  %191 = insertelement <2 x i32> %190, i32 %189, i32 1
  %192 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %191, <32 x i8> %109, <16 x i8> %111, i32 2)
  %193 = extractelement <4 x float> %192, i32 0
  %194 = extractelement <4 x float> %192, i32 1
  %195 = extractelement <4 x float> %192, i32 2
  %196 = extractelement <4 x float> %192, i32 3
  %197 = fmul float %193, 0x4012611180000000
  %198 = fmul float %194, 0x4012611180000000
  %199 = fmul float %195, 0x4012611180000000
  %200 = call float @llvm.AMDGPU.lrp(float %30, float %197, float 1.000000e+00)
  %201 = call float @llvm.AMDGPU.lrp(float %30, float %198, float 1.000000e+00)
  %202 = call float @llvm.AMDGPU.lrp(float %30, float %199, float 1.000000e+00)
  %203 = bitcast float %150 to i32
  %204 = bitcast float %151 to i32
  %205 = insertelement <2 x i32> undef, i32 %203, i32 0
  %206 = insertelement <2 x i32> %205, i32 %204, i32 1
  %207 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %206, <32 x i8> %117, <16 x i8> %119, i32 2)
  %208 = extractelement <4 x float> %207, i32 0
  %209 = extractelement <4 x float> %207, i32 1
  %210 = extractelement <4 x float> %207, i32 2
  %211 = extractelement <4 x float> %207, i32 3
  %212 = bitcast float %142 to i32
  %213 = bitcast float %143 to i32
  %214 = insertelement <2 x i32> undef, i32 %212, i32 0
  %215 = insertelement <2 x i32> %214, i32 %213, i32 1
  %216 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %215, <32 x i8> %113, <16 x i8> %115, i32 2)
  %217 = extractelement <4 x float> %216, i32 0
  %218 = extractelement <4 x float> %216, i32 1
  %219 = extractelement <4 x float> %216, i32 2
  %220 = extractelement <4 x float> %216, i32 3
  %221 = fmul float %217, %23
  %222 = fmul float %218, %24
  %223 = fmul float %219, %25
  %224 = fmul float %220, %26
  %225 = fmul float %221, %152
  %226 = fmul float %222, %153
  %227 = fmul float %223, %154
  %228 = fmul float %224, %155
  %229 = fsub float -0.000000e+00, %220
  %230 = fadd float 1.000000e+00, %229
  %231 = fmul float %230, %53
  %232 = call float @llvm.AMDGPU.lrp(float %231, float %217, float %225)
  %233 = call float @llvm.AMDGPU.lrp(float %231, float %218, float %226)
  %234 = call float @llvm.AMDGPU.lrp(float %231, float %219, float %227)
  %235 = bitcast float %144 to i32
  %236 = bitcast float %145 to i32
  %237 = insertelement <2 x i32> undef, i32 %235, i32 0
  %238 = insertelement <2 x i32> %237, i32 %236, i32 1
  %239 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %238, <32 x i8> %121, <16 x i8> %123, i32 2)
  %240 = extractelement <4 x float> %239, i32 0
  %241 = extractelement <4 x float> %239, i32 1
  %242 = extractelement <4 x float> %239, i32 3
  %243 = fmul float %58, %242
  %244 = fmul float %59, %240
  %245 = fsub float -0.000000e+00, %243
  %246 = fadd float 1.000000e+00, %245
  %247 = fsub float -0.000000e+00, %244
  %248 = fadd float 1.000000e+00, %247
  %249 = fmul float %232, %200
  %250 = fmul float %233, %201
  %251 = fmul float %234, %202
  %252 = fmul float %228, %196
  %253 = fmul float %156, %156
  %254 = fmul float %157, %157
  %255 = fadd float %254, %253
  %256 = fmul float %158, %158
  %257 = fadd float %255, %256
  %258 = call float @llvm.AMDGPU.rsq(float %257)
  %259 = fmul float %156, %258
  %260 = fmul float %157, %258
  %261 = fmul float %158, %258
  %262 = fcmp olt float 0.000000e+00, %185
  %263 = sext i1 %262 to i32
  %264 = bitcast i32 %263 to float
  %265 = bitcast float %264 to i32
  %266 = icmp ne i32 %265, 0
  br i1 %266, label %IF93, label %ENDIF92

IF93:                                             ; preds = %main_body
  %267 = fsub float -0.000000e+00, %259
  %268 = fsub float -0.000000e+00, %260
  %269 = fsub float -0.000000e+00, %261
  br label %ENDIF92

ENDIF92:                                          ; preds = %main_body, %IF93
  %temp20.0 = phi float [ %267, %IF93 ], [ %259, %main_body ]
  %temp21.0 = phi float [ %268, %IF93 ], [ %260, %main_body ]
  %temp22.0 = phi float [ %269, %IF93 ], [ %261, %main_body ]
  %270 = bitcast float %186 to i32
  %271 = bitcast float %187 to i32
  %272 = insertelement <2 x i32> undef, i32 %270, i32 0
  %273 = insertelement <2 x i32> %272, i32 %271, i32 1
  %274 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %273, <32 x i8> %133, <16 x i8> %135, i32 2)
  %275 = extractelement <4 x float> %274, i32 0
  %276 = extractelement <4 x float> %274, i32 1
  %277 = extractelement <4 x float> %274, i32 2
  %278 = extractelement <4 x float> %274, i32 3
  %279 = fmul float %275, %44
  %280 = fadd float %279, %45
  %281 = fmul float %276, %44
  %282 = fadd float %281, %45
  %283 = fmul float %277, %44
  %284 = fadd float %283, %45
  %285 = fmul float %278, %46
  %286 = fadd float %285, %47
  %287 = bitcast float %146 to i32
  %288 = bitcast float %147 to i32
  %289 = insertelement <2 x i32> undef, i32 %287, i32 0
  %290 = insertelement <2 x i32> %289, i32 %288, i32 1
  %291 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %290, <32 x i8> %125, <16 x i8> %127, i32 2)
  %292 = extractelement <4 x float> %291, i32 0
  %293 = extractelement <4 x float> %291, i32 1
  %294 = extractelement <4 x float> %291, i32 2
  %295 = extractelement <4 x float> %291, i32 3
  %296 = fmul float %295, 3.200000e+01
  %297 = fadd float %296, -1.600000e+01
  %298 = call float @llvm.AMDIL.exp.(float %297)
  %299 = fmul float %292, %298
  %300 = fmul float %293, %298
  %301 = fmul float %294, %298
  %302 = fmul float %34, %299
  %303 = fadd float %302, %159
  %304 = fmul float %35, %300
  %305 = fadd float %304, %160
  %306 = fmul float %36, %301
  %307 = fadd float %306, %161
  %308 = fmul float %303, %286
  %309 = fmul float %305, %286
  %310 = fmul float %307, %286
  %311 = fmul float %286, 5.000000e-01
  %312 = fadd float %311, 5.000000e-01
  %313 = fmul float %temp20.0, %182
  %314 = fmul float %temp21.0, %183
  %315 = fadd float %314, %313
  %316 = fmul float %temp22.0, %184
  %317 = fadd float %315, %316
  %318 = call float @llvm.AMDIL.clamp.(float %317, float 0.000000e+00, float 1.000000e+00)
  %319 = fsub float -0.000000e+00, %318
  %320 = fadd float 1.000000e+00, %319
  %321 = call float @llvm.pow.f32(float %320, float 4.000000e+00)
  %322 = fmul float %321, %37
  %323 = fmul float %248, %322
  %324 = fsub float -0.000000e+00, %323
  %325 = fadd float %248, %324
  %326 = fmul float %temp20.0, %182
  %327 = fmul float %temp21.0, %183
  %328 = fadd float %327, %326
  %329 = fmul float %temp22.0, %184
  %330 = fadd float %328, %329
  %331 = fmul float %330, %temp20.0
  %332 = fmul float %330, %temp21.0
  %333 = fmul float %330, %temp22.0
  %334 = fmul float 2.000000e+00, %331
  %335 = fmul float 2.000000e+00, %332
  %336 = fmul float 2.000000e+00, %333
  %337 = fsub float -0.000000e+00, %334
  %338 = fadd float %182, %337
  %339 = fsub float -0.000000e+00, %335
  %340 = fadd float %183, %339
  %341 = fsub float -0.000000e+00, %336
  %342 = fadd float %184, %341
  %343 = fsub float -0.000000e+00, %temp20.0
  %344 = call float @llvm.AMDGPU.lrp(float %325, float %343, float %338)
  %345 = fsub float -0.000000e+00, %temp21.0
  %346 = call float @llvm.AMDGPU.lrp(float %325, float %345, float %340)
  %347 = fsub float -0.000000e+00, %temp22.0
  %348 = call float @llvm.AMDGPU.lrp(float %325, float %347, float %342)
  %349 = call float @fabs(float %344)
  %350 = call float @fabs(float %346)
  %351 = call float @fabs(float %348)
  %352 = fcmp uge float %350, %351
  %353 = select i1 %352, float %350, float %351
  %354 = fcmp uge float %349, %353
  %355 = select i1 %354, float %349, float %353
  %356 = fadd float %355, 0xBF50624DE0000000
  %357 = fcmp oge float %356, %349
  %358 = sext i1 %357 to i32
  %359 = bitcast i32 %358 to float
  %360 = bitcast float %359 to i32
  %361 = and i32 %360, 1065353216
  %362 = bitcast i32 %361 to float
  %363 = fcmp oge float %356, %350
  %364 = sext i1 %363 to i32
  %365 = bitcast i32 %364 to float
  %366 = bitcast float %365 to i32
  %367 = and i32 %366, 1065353216
  %368 = bitcast i32 %367 to float
  %369 = fcmp oge float %356, %351
  %370 = sext i1 %369 to i32
  %371 = bitcast i32 %370 to float
  %372 = bitcast float %371 to i32
  %373 = and i32 %372, 1065353216
  %374 = bitcast i32 %373 to float
  %375 = fdiv float 1.000000e+00, %355
  %376 = fmul float -1.000000e+00, %375
  %377 = fmul float -1.000000e+00, %375
  %378 = fmul float 1.000000e+00, %375
  %379 = fmul float %344, %376
  %380 = fmul float %346, %377
  %381 = fmul float %348, %378
  %382 = fadd float %60, -1.000000e+00
  %383 = fmul float %325, %382
  %384 = fmul float %379, %362
  %385 = fmul float %380, %368
  %386 = fmul float %381, %374
  %387 = call float @floor(float %383)
  %388 = fsub float -0.000000e+00, %387
  %389 = fadd float %60, %388
  %390 = call float @llvm.AMDIL.exp.(float %389)
  %391 = fdiv float 1.000000e+00, %390
  %392 = fmul float %384, %391
  %393 = fmul float %385, %391
  %394 = fmul float %386, %391
  %395 = fsub float -0.000000e+00, %392
  %396 = fadd float %379, %395
  %397 = fsub float -0.000000e+00, %393
  %398 = fadd float %380, %397
  %399 = fsub float -0.000000e+00, %394
  %400 = fadd float %381, %399
  %401 = insertelement <4 x float> undef, float %396, i32 0
  %402 = insertelement <4 x float> %401, float %398, i32 1
  %403 = insertelement <4 x float> %402, float %400, i32 2
  %404 = insertelement <4 x float> %403, float %383, i32 3
  %405 = call <4 x float> @llvm.AMDGPU.cube(<4 x float> %404)
  %406 = extractelement <4 x float> %405, i32 0
  %407 = extractelement <4 x float> %405, i32 1
  %408 = extractelement <4 x float> %405, i32 2
  %409 = extractelement <4 x float> %405, i32 3
  %410 = call float @fabs(float %408)
  %411 = fdiv float 1.000000e+00, %410
  %412 = fmul float %406, %411
  %413 = fadd float %412, 1.500000e+00
  %414 = fmul float %407, %411
  %415 = fadd float %414, 1.500000e+00
  %416 = bitcast float %415 to i32
  %417 = bitcast float %413 to i32
  %418 = bitcast float %409 to i32
  %419 = bitcast float %383 to i32
  %420 = insertelement <4 x i32> undef, i32 %416, i32 0
  %421 = insertelement <4 x i32> %420, i32 %417, i32 1
  %422 = insertelement <4 x i32> %421, i32 %418, i32 2
  %423 = insertelement <4 x i32> %422, i32 %419, i32 3
  %424 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %423, <32 x i8> %129, <16 x i8> %131, i32 4)
  %425 = extractelement <4 x float> %424, i32 0
  %426 = extractelement <4 x float> %424, i32 1
  %427 = extractelement <4 x float> %424, i32 2
  %428 = extractelement <4 x float> %424, i32 3
  %429 = fmul float %428, 3.200000e+01
  %430 = fadd float %429, -1.600000e+01
  %431 = call float @llvm.AMDIL.exp.(float %430)
  %432 = fmul float %425, %431
  %433 = fmul float %426, %431
  %434 = fmul float %427, %431
  %435 = fmul float %27, %241
  %436 = fmul float %28, %241
  %437 = fmul float %29, %241
  %438 = fmul float %435, %241
  %439 = fmul float %436, %241
  %440 = fmul float %437, %241
  %441 = fmul float %325, 2.000000e+00
  %442 = fadd float %441, -1.000000e+00
  %443 = call float @llvm.AMDIL.clamp.(float %442, float 0.000000e+00, float 1.000000e+00)
  %444 = fmul float %280, %312
  %445 = fmul float %282, %312
  %446 = fmul float %284, %312
  %447 = fmul float %432, %31
  %448 = fmul float %433, %32
  %449 = fmul float %434, %33
  %450 = fmul float %438, %447
  %451 = fmul float %439, %448
  %452 = fmul float %440, %449
  %453 = call float @llvm.AMDGPU.lrp(float %443, float %438, float %450)
  %454 = call float @llvm.AMDGPU.lrp(float %443, float %439, float %451)
  %455 = call float @llvm.AMDGPU.lrp(float %443, float %440, float %452)
  %456 = call float @llvm.AMDGPU.lrp(float %322, float 1.000000e+00, float %438)
  %457 = call float @llvm.AMDGPU.lrp(float %322, float 1.000000e+00, float %439)
  %458 = call float @llvm.AMDGPU.lrp(float %322, float 1.000000e+00, float %440)
  %459 = call float @llvm.AMDGPU.lrp(float %456, float %453, float %249)
  %460 = call float @llvm.AMDGPU.lrp(float %457, float %454, float %250)
  %461 = call float @llvm.AMDGPU.lrp(float %458, float %455, float %251)
  %462 = fmul float %308, %459
  %463 = fmul float %309, %460
  %464 = fmul float %310, %461
  %465 = fmul float %444, %249
  %466 = fadd float %465, %462
  %467 = fmul float %445, %250
  %468 = fadd float %467, %463
  %469 = fmul float %446, %251
  %470 = fadd float %469, %464
  %471 = fsub float -0.000000e+00, %66
  %472 = fadd float %138, %471
  %473 = fsub float -0.000000e+00, %67
  %474 = fadd float %139, %473
  %475 = fsub float -0.000000e+00, %68
  %476 = fadd float %140, %475
  %477 = fmul float %472, %472
  %478 = fmul float %474, %474
  %479 = fadd float %478, %477
  %480 = fmul float %476, %476
  %481 = fadd float %479, %480
  %482 = call float @llvm.AMDGPU.rsq(float %481)
  %483 = fmul float %73, %482
  %484 = fdiv float 1.000000e+00, %483
  %485 = call float @llvm.AMDIL.clamp.(float %484, float 0.000000e+00, float 1.000000e+00)
  %486 = fsub float -0.000000e+00, %485
  %487 = fadd float 1.000000e+00, %486
  %488 = fmul float %487, %482
  %489 = fsub float -0.000000e+00, %472
  %490 = fmul float %489, %482
  %491 = fsub float -0.000000e+00, %474
  %492 = fmul float %491, %482
  %493 = fsub float -0.000000e+00, %476
  %494 = fmul float %493, %482
  %495 = fsub float -0.000000e+00, %70
  %496 = fsub float -0.000000e+00, %71
  %497 = fsub float -0.000000e+00, %72
  %498 = fmul float %490, %495
  %499 = fmul float %492, %496
  %500 = fadd float %499, %498
  %501 = fmul float %494, %497
  %502 = fadd float %500, %501
  %503 = fmul float %502, %65
  %504 = fsub float -0.000000e+00, %503
  %505 = fadd float %69, %504
  %506 = call float @llvm.AMDIL.clamp.(float %505, float 0.000000e+00, float 1.000000e+00)
  %507 = fmul float %488, %506
  %508 = fmul float %temp20.0, %490
  %509 = fmul float %temp21.0, %492
  %510 = fadd float %509, %508
  %511 = fmul float %temp22.0, %494
  %512 = fadd float %510, %511
  %513 = call float @llvm.AMDIL.clamp.(float %512, float 0.000000e+00, float 1.000000e+00)
  %514 = fadd float %182, %490
  %515 = fadd float %183, %492
  %516 = fadd float %184, %494
  %517 = fmul float %514, %514
  %518 = fmul float %515, %515
  %519 = fadd float %518, %517
  %520 = fmul float %516, %516
  %521 = fadd float %519, %520
  %522 = call float @llvm.AMDGPU.rsq(float %521)
  %523 = fmul float %514, %522
  %524 = fmul float %515, %522
  %525 = fmul float %516, %522
  %526 = fmul float %523, %temp20.0
  %527 = fmul float %524, %temp21.0
  %528 = fadd float %527, %526
  %529 = fmul float %525, %temp22.0
  %530 = fadd float %528, %529
  %531 = call i32 @llvm.SI.tid()
  %532 = getelementptr [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %531
  %533 = and i32 %531, -4
  %534 = getelementptr [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %533
  %535 = add i32 %533, 1
  %536 = getelementptr [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %535
  %537 = bitcast float %530 to i32
  store i32 %537, i32 addrspace(3)* %532
  %538 = load i32 addrspace(3)* %534
  %539 = bitcast i32 %538 to float
  %540 = load i32 addrspace(3)* %536
  %541 = bitcast i32 %540 to float
  %542 = fsub float %541, %539
  %543 = insertelement <4 x float> undef, float %542, i32 0
  %544 = insertelement <4 x float> %543, float %542, i32 1
  %545 = insertelement <4 x float> %544, float %542, i32 2
  %546 = insertelement <4 x float> %545, float %542, i32 3
  %547 = extractelement <4 x float> %546, i32 0
  %548 = call float @fabs(float %547)
  %549 = fmul float %98, %530
  %550 = fmul float %98, %530
  %551 = fmul float %98, %530
  %552 = fmul float %98, %530
  %553 = call i32 @llvm.SI.tid()
  %554 = getelementptr [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %553
  %555 = and i32 %553, -4
  %556 = getelementptr [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %555
  %557 = add i32 %555, 2
  %558 = getelementptr [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %557
  %559 = bitcast float %549 to i32
  store i32 %559, i32 addrspace(3)* %554
  %560 = load i32 addrspace(3)* %556
  %561 = bitcast i32 %560 to float
  %562 = load i32 addrspace(3)* %558
  %563 = bitcast i32 %562 to float
  %564 = fsub float %563, %561
  %565 = bitcast float %550 to i32
  store i32 %565, i32 addrspace(3)* %554
  %566 = load i32 addrspace(3)* %556
  %567 = bitcast i32 %566 to float
  %568 = load i32 addrspace(3)* %558
  %569 = bitcast i32 %568 to float
  %570 = fsub float %569, %567
  %571 = bitcast float %551 to i32
  store i32 %571, i32 addrspace(3)* %554
  %572 = load i32 addrspace(3)* %556
  %573 = bitcast i32 %572 to float
  %574 = load i32 addrspace(3)* %558
  %575 = bitcast i32 %574 to float
  %576 = fsub float %575, %573
  %577 = bitcast float %552 to i32
  store i32 %577, i32 addrspace(3)* %554
  %578 = load i32 addrspace(3)* %556
  %579 = bitcast i32 %578 to float
  %580 = load i32 addrspace(3)* %558
  %581 = bitcast i32 %580 to float
  %582 = fsub float %581, %579
  %583 = insertelement <4 x float> undef, float %564, i32 0
  %584 = insertelement <4 x float> %583, float %570, i32 1
  %585 = insertelement <4 x float> %584, float %576, i32 2
  %586 = insertelement <4 x float> %585, float %582, i32 3
  %587 = extractelement <4 x float> %586, i32 0
  %588 = call float @fabs(float %587)
  %589 = fadd float %548, %588
  %590 = fmul float %589, 5.000000e-01
  %591 = fadd float %590, 0x3EE4F8B580000000
  %592 = fmul float %591, -1.000000e+00
  %593 = fadd float %592, %530
  %594 = fmul float %591, 1.000000e+00
  %595 = fadd float %594, %530
  %596 = call float @llvm.AMDIL.clamp.(float %593, float 0.000000e+00, float 1.000000e+00)
  %597 = call float @llvm.AMDIL.clamp.(float %595, float 0.000000e+00, float 1.000000e+00)
  %598 = fmul float %523, %182
  %599 = fmul float %524, %183
  %600 = fadd float %599, %598
  %601 = fmul float %525, %184
  %602 = fadd float %600, %601
  %603 = call float @llvm.AMDIL.clamp.(float %602, float 0.000000e+00, float 1.000000e+00)
  %604 = fsub float -0.000000e+00, %603
  %605 = fadd float 1.000000e+00, %604
  %606 = call float @llvm.pow.f32(float %605, float 4.000000e+00)
  %607 = fmul float %606, %37
  %608 = fmul float %246, %607
  %609 = fmul float %248, %607
  %610 = fsub float -0.000000e+00, %608
  %611 = fadd float %246, %610
  %612 = fsub float -0.000000e+00, %609
  %613 = fadd float %248, %612
  %614 = call float @llvm.pow.f32(float %611, float 4.000000e+00)
  %615 = call float @llvm.pow.f32(float %613, float 4.000000e+00)
  %616 = fadd float %614, 0x3E7AD7F2A0000000
  %617 = fadd float %615, 0x3E7AD7F2A0000000
  %618 = call float @llvm.AMDIL.clamp.(float %616, float 0.000000e+00, float 1.000000e+00)
  %619 = call float @llvm.AMDIL.clamp.(float %617, float 0.000000e+00, float 1.000000e+00)
  %620 = fmul float %596, %618
  %621 = fmul float %597, %618
  %622 = fmul float %596, %619
  %623 = fmul float %597, %619
  %624 = fadd float %618, -1.000000e+00
  %625 = fadd float %618, -1.000000e+00
  %626 = fadd float %619, -1.000000e+00
  %627 = fadd float %619, -1.000000e+00
  %628 = fmul float %596, %624
  %629 = fadd float %628, 1.000000e+00
  %630 = fmul float %597, %625
  %631 = fadd float %630, 1.000000e+00
  %632 = fmul float %596, %626
  %633 = fadd float %632, 1.000000e+00
  %634 = fmul float %597, %627
  %635 = fadd float %634, 1.000000e+00
  %636 = fdiv float 1.000000e+00, %629
  %637 = fdiv float 1.000000e+00, %631
  %638 = fdiv float 1.000000e+00, %633
  %639 = fdiv float 1.000000e+00, %635
  %640 = fmul float %620, %636
  %641 = fmul float %621, %637
  %642 = fmul float %622, %638
  %643 = fmul float %623, %639
  %644 = call float @llvm.AMDIL.clamp.(float %640, float 0.000000e+00, float 1.000000e+00)
  %645 = call float @llvm.AMDIL.clamp.(float %641, float 0.000000e+00, float 1.000000e+00)
  %646 = call float @llvm.AMDIL.clamp.(float %642, float 0.000000e+00, float 1.000000e+00)
  %647 = call float @llvm.AMDIL.clamp.(float %643, float 0.000000e+00, float 1.000000e+00)
  %648 = fsub float -0.000000e+00, %646
  %649 = fadd float %647, %648
  %650 = fsub float -0.000000e+00, %596
  %651 = fadd float %597, %650
  %652 = fadd float %651, 0x3EB0C6F7A0000000
  %653 = fmul float %temp20.0, %182
  %654 = fmul float %temp21.0, %183
  %655 = fadd float %654, %653
  %656 = fmul float %temp22.0, %184
  %657 = fadd float %655, %656
  %658 = call float @llvm.AMDIL.clamp.(float %657, float 0.000000e+00, float 1.000000e+00)
  %659 = fmul float %658, %513
  %660 = fcmp uge float %659, 0x3F847AE140000000
  %661 = select i1 %660, float %659, float 0x3F847AE140000000
  %662 = call float @llvm.AMDGPU.rsq(float %661)
  %663 = fmul float %662, %661
  %664 = fsub float -0.000000e+00, %661
  %665 = call float @llvm.AMDGPU.cndlt(float %664, float %663, float 0.000000e+00)
  %666 = call float @llvm.AMDGPU.lrp(float %618, float 1.000000e+00, float %665)
  %667 = call float @llvm.AMDGPU.lrp(float %619, float 1.000000e+00, float %665)
  %668 = fmul float %652, %667
  %669 = fdiv float 1.000000e+00, %668
  %670 = fmul float %649, %669
  %671 = fmul float %27, %241
  %672 = fmul float %28, %241
  %673 = fmul float %29, %241
  %674 = fmul float %671, %241
  %675 = fmul float %672, %241
  %676 = fmul float %673, %241
  %677 = call float @llvm.AMDGPU.lrp(float %674, float %670, float %249)
  %678 = call float @llvm.AMDGPU.lrp(float %675, float %670, float %250)
  %679 = call float @llvm.AMDGPU.lrp(float %676, float %670, float %251)
  %680 = fmul float %677, %513
  %681 = fmul float %678, %513
  %682 = fmul float %679, %513
  %683 = fmul float %680, %62
  %684 = fmul float %681, %63
  %685 = fmul float %682, %64
  %686 = fmul float %683, %507
  %687 = fmul float %684, %507
  %688 = fmul float %685, %507
  %689 = fmul float %138, %82
  %690 = fmul float %139, %83
  %691 = fadd float %689, %690
  %692 = fmul float %140, %84
  %693 = fadd float %691, %692
  %694 = fmul float %141, %85
  %695 = fadd float %693, %694
  %696 = fmul float %138, %86
  %697 = fmul float %139, %87
  %698 = fadd float %696, %697
  %699 = fmul float %140, %88
  %700 = fadd float %698, %699
  %701 = fmul float %141, %89
  %702 = fadd float %700, %701
  %703 = fmul float %138, %90
  %704 = fmul float %139, %91
  %705 = fadd float %703, %704
  %706 = fmul float %140, %92
  %707 = fadd float %705, %706
  %708 = fmul float %141, %93
  %709 = fadd float %707, %708
  %710 = fmul float %138, %94
  %711 = fmul float %139, %95
  %712 = fadd float %710, %711
  %713 = fmul float %140, %96
  %714 = fadd float %712, %713
  %715 = fmul float %141, %97
  %716 = fadd float %714, %715
  %717 = fdiv float 1.000000e+00, %716
  %718 = fmul float %695, %717
  %719 = fmul float %702, %717
  %720 = fmul float %718, 5.000000e-01
  %721 = fadd float %720, 5.000000e-01
  %722 = fmul float %719, 5.000000e-01
  %723 = fadd float %722, 5.000000e-01
  %724 = fmul float %721, %78
  %725 = fadd float %724, %80
  %726 = fmul float %723, %79
  %727 = fadd float %726, %81
  %728 = bitcast float %725 to i32
  %729 = bitcast float %727 to i32
  %730 = insertelement <2 x i32> undef, i32 %728, i32 0
  %731 = insertelement <2 x i32> %730, i32 %729, i32 1
  %732 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %731, <32 x i8> %105, <16 x i8> %107, i32 2)
  %733 = extractelement <4 x float> %732, i32 0
  %734 = extractelement <4 x float> %732, i32 1
  %735 = extractelement <4 x float> %732, i32 2
  %736 = bitcast float %721 to i32
  %737 = bitcast float %723 to i32
  %738 = bitcast float 0.000000e+00 to i32
  %739 = insertelement <4 x i32> undef, i32 %736, i32 0
  %740 = insertelement <4 x i32> %739, i32 %737, i32 1
  %741 = insertelement <4 x i32> %740, i32 %738, i32 2
  %742 = insertelement <4 x i32> %741, i32 undef, i32 3
  %743 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %742, <32 x i8> %101, <16 x i8> %103, i32 2)
  %744 = extractelement <4 x float> %743, i32 0
  %745 = extractelement <4 x float> %743, i32 1
  %746 = fsub float -0.000000e+00, %745
  %747 = fadd float 1.000000e+00, %746
  %748 = fmul float %747, 2.500000e-01
  %749 = fsub float -0.000000e+00, %748
  %750 = fadd float %744, %749
  %751 = fsub float -0.000000e+00, %709
  %752 = fadd float %744, %751
  %753 = fmul float %744, %744
  %754 = fsub float -0.000000e+00, %753
  %755 = fadd float %750, %754
  %756 = fcmp uge float %755, %74
  %757 = select i1 %756, float %755, float %74
  %758 = fmul float %752, %752
  %759 = fadd float %758, %757
  %760 = fdiv float 1.000000e+00, %759
  %761 = fmul float %757, %760
  %762 = call float @llvm.pow.f32(float %761, float %75)
  %763 = fmul float %762, %76
  %764 = fadd float %763, %77
  %765 = call float @llvm.AMDIL.clamp.(float %764, float 0.000000e+00, float 1.000000e+00)
  %766 = fmul float %765, %765
  %767 = fmul float 2.000000e+00, %765
  %768 = fsub float -0.000000e+00, %767
  %769 = fadd float 3.000000e+00, %768
  %770 = fmul float %766, %769
  %771 = fcmp oge float %752, 0.000000e+00
  %772 = sext i1 %771 to i32
  %773 = bitcast i32 %772 to float
  %774 = bitcast float %773 to i32
  %775 = icmp ne i32 %774, 0
  %.98 = select i1 %775, float 1.000000e+00, float %770
  %776 = fmul float %733, %.98
  %777 = fmul float %734, %.98
  %778 = fmul float %735, %.98
  %779 = fmul float %686, %776
  %780 = fmul float %687, %777
  %781 = fmul float %688, %778
  %782 = fmul float %779, %312
  %783 = fadd float %782, %466
  %784 = fmul float %780, %312
  %785 = fadd float %784, %468
  %786 = fmul float %781, %312
  %787 = fadd float %786, %470
  %788 = call float @llvm.AMDGPU.lrp(float %196, float %211, float 1.000000e+00)
  %789 = call float @llvm.AMDGPU.lrp(float %42, float %208, float 1.000000e+00)
  %790 = call float @llvm.AMDGPU.lrp(float %42, float %209, float 1.000000e+00)
  %791 = call float @llvm.AMDGPU.lrp(float %42, float %210, float 1.000000e+00)
  %792 = call float @llvm.AMDGPU.lrp(float %43, float %788, float 1.000000e+00)
  %793 = fmul float %789, %792
  %794 = fmul float %790, %792
  %795 = fmul float %791, %792
  %796 = fmul float %783, %793
  %797 = fmul float %785, %794
  %798 = fmul float %787, %795
  %799 = fmul float %temp20.0, %182
  %800 = fmul float %temp21.0, %183
  %801 = fadd float %800, %799
  %802 = fmul float %temp22.0, %184
  %803 = fadd float %801, %802
  %804 = call float @fabs(float %803)
  %805 = fmul float %804, %804
  %806 = fmul float %805, %54
  %807 = fadd float %806, %55
  %808 = call float @llvm.AMDIL.clamp.(float %807, float 0.000000e+00, float 1.000000e+00)
  %809 = fsub float -0.000000e+00, %808
  %810 = fadd float 1.000000e+00, %809
  %811 = fmul float %40, %810
  %812 = fmul float %40, %810
  %813 = fmul float %40, %810
  %814 = fmul float %41, %810
  %815 = call float @llvm.AMDGPU.lrp(float %811, float %38, float %796)
  %816 = call float @llvm.AMDGPU.lrp(float %812, float %38, float %797)
  %817 = call float @llvm.AMDGPU.lrp(float %813, float %38, float %798)
  %818 = call float @llvm.AMDGPU.lrp(float %814, float %39, float %252)
  %819 = fcmp uge float %815, 0x3E6FFFFE60000000
  %820 = select i1 %819, float %815, float 0x3E6FFFFE60000000
  %821 = fcmp uge float %816, 0x3E6FFFFE60000000
  %822 = select i1 %821, float %816, float 0x3E6FFFFE60000000
  %823 = fcmp uge float %817, 0x3E6FFFFE60000000
  %824 = select i1 %823, float %817, float 0x3E6FFFFE60000000
  %825 = fcmp uge float %820, 6.550400e+04
  %826 = select i1 %825, float 6.550400e+04, float %820
  %827 = fcmp uge float %822, 6.550400e+04
  %828 = select i1 %827, float 6.550400e+04, float %822
  %829 = fcmp uge float %824, 6.550400e+04
  %830 = select i1 %829, float 6.550400e+04, float %824
  %831 = fmul float %818, %56
  %832 = fadd float %831, %57
  %833 = call float @llvm.AMDIL.clamp.(float %832, float 0.000000e+00, float 1.000000e+00)
  %834 = call i32 @llvm.SI.packf16(float %826, float %828)
  %835 = bitcast i32 %834 to float
  %836 = call i32 @llvm.SI.packf16(float %830, float %833)
  %837 = bitcast i32 %836 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %835, float %837, float %835, float %837)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #2

; Function Attrs: readnone
declare float @llvm.AMDGPU.rsq(float) #2

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDGPU.lrp(float, float, float) #2

; Function Attrs: readnone
declare float @llvm.AMDIL.exp.(float) #2

; Function Attrs: nounwind readonly
declare float @llvm.pow.f32(float, float) #3

; Function Attrs: readonly
declare float @fabs(float) #4

; Function Attrs: readonly
declare float @floor(float) #4

; Function Attrs: readnone
declare <4 x float> @llvm.AMDGPU.cube(<4 x float>) #2

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.samplel.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readnone
declare i32 @llvm.SI.tid() #2

; Function Attrs: readnone
declare float @llvm.AMDGPU.cndlt(float, float, float) #2

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }
attributes #3 = { nounwind readonly }
attributes #4 = { readonly }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg104, %SGPR2_SGPR3 in %vreg105, %SGPR4_SGPR5 in %vreg106, %SGPR7 in %vreg108, %VGPR0 in %vreg109, %VGPR1 in %vreg110, %VGPR2 in %vreg111, %VGPR3 in %vreg112, %VGPR4 in %vreg113

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR7 %VGPR0 %VGPR1 %VGPR2 %VGPR3 %VGPR4
    Successors according to CFG: BB#1(16) BB#2(16)

BB#1: derived from LLVM BB %IF93
    Live Ins: %SGPR12 %SGPR8 %SGPR9 %SGPR25 %SGPR46 %SGPR47 %VGPR65 %VGPR63 %VGPR1 %VGPR0 %SGPR53 %VGPR67 %VGPR68 %VGPR66 %VGPR46 %VGPR45 %VGPR4 %VGPR40 %VGPR53 %VGPR54 %VGPR52 %VGPR49 %VGPR57 %VGPR58 %VGPR56 %VGPR55 %VGPR43 %VGPR44 %VGPR42 %VGPR41 %VGPR50 %VGPR51 %VGPR48 %VGPR47 %SGPR45 %VGPR59 %SGPR36_SGPR37_SGPR38_SGPR39_SGPR40_SGPR41_SGPR42_SGPR43 %SGPR32_SGPR33_SGPR34_SGPR35 %VGPR61 %VGPR60 %VGPR62 %VGPR10_VGPR11_VGPR12_VGPR13 %VGPR26 %VGPR35 %VGPR23 %VGPR14_VGPR15_VGPR16_VGPR17 %VGPR18_VGPR19_VGPR20_VGPR21 %SGPR2_SGPR3 %SGPR4_SGPR5 %VGPR2 %VGPR3 %VGPR5_VGPR6_VGPR7_VGPR8 %VGPR9 %VGPR31 %VGPR22 %VGPR32 %VGPR33 %VGPR34 %VGPR25 %VGPR37 %VGPR27 %VGPR24 %VGPR36 %SGPR29 %SGPR30 %SGPR31 %SGPR44 %SGPR27 %SGPR20 %SGPR23 %SGPR26 %SGPR21 %SGPR24 %SGPR7 %SGPR28 %SGPR13 %SGPR54 %SGPR0 %SGPR17 %SGPR49 %SGPR50 %SGPR6 %SGPR22 %SGPR1 %SGPR11 %SGPR48 %SGPR16 %SGPR14 %SGPR51 %SGPR18 %SGPR15 %SGPR52 %SGPR19 %SGPR10 %SGPR56_SGPR57 %VGPR64 %VGPR38_VGPR39 %VGPR30 %VGPR29 %VGPR28
    Predecessors according to CFG: BB#0
    Successors according to CFG: BB#2

BB#2: derived from LLVM BB %ENDIF92
    Live Ins: %SGPR12 %SGPR8 %SGPR9 %SGPR25 %SGPR46 %SGPR47 %VGPR65 %VGPR63 %VGPR1 %VGPR0 %SGPR53 %VGPR67 %VGPR68 %VGPR66 %VGPR46 %VGPR45 %VGPR4 %VGPR40 %VGPR53 %VGPR54 %VGPR52 %VGPR49 %VGPR57 %VGPR58 %VGPR56 %VGPR55 %VGPR43 %VGPR44 %VGPR42 %VGPR41 %VGPR50 %VGPR51 %VGPR48 %VGPR47 %SGPR45 %VGPR59 %SGPR36_SGPR37_SGPR38_SGPR39_SGPR40_SGPR41_SGPR42_SGPR43 %SGPR32_SGPR33_SGPR34_SGPR35 %VGPR61 %VGPR60 %VGPR62 %VGPR10_VGPR11_VGPR12_VGPR13 %VGPR26 %VGPR35 %VGPR23 %VGPR14_VGPR15_VGPR16_VGPR17 %VGPR18_VGPR19_VGPR20_VGPR21 %SGPR2_SGPR3 %SGPR4_SGPR5 %VGPR2 %VGPR3 %VGPR5_VGPR6_VGPR7_VGPR8 %VGPR9 %VGPR31 %VGPR22 %VGPR32 %VGPR33 %VGPR34 %VGPR25 %VGPR37 %VGPR27 %VGPR24 %VGPR36 %SGPR29 %SGPR30 %SGPR31 %SGPR44 %SGPR27 %SGPR20 %SGPR23 %SGPR26 %SGPR21 %SGPR24 %SGPR7 %SGPR28 %SGPR13 %SGPR54 %SGPR0 %SGPR17 %SGPR49 %SGPR50 %SGPR6 %SGPR22 %SGPR1 %SGPR11 %SGPR48 %SGPR16 %SGPR14 %SGPR51 %SGPR18 %SGPR15 %SGPR52 %SGPR19 %SGPR10 %SGPR56_SGPR57 %VGPR64 %VGPR38_VGPR39 %VGPR30 %VGPR29 %VGPR28
    Predecessors according to CFG: BB#0 BB#1
	EXP 0, 9, 0, 1, 1, %VGPR0, %VGPR0, %VGPR0, %VGPR0, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	EXP 0, 9, 0, 1, 1, v0, v0, v0, v0 ; F8001890 00000000
	S_ENDPGM                          ; BF810000

VERT
DCL IN[0]
DCL IN[1]
DCL IN[2]
DCL IN[3]
DCL IN[4]
DCL IN[5]
DCL IN[6]
DCL IN[7]
DCL IN[8]
DCL IN[9]
DCL OUT[0], POSITION
DCL OUT[1], CLIPVERTEX
DCL OUT[2], GENERIC[19]
DCL OUT[3], GENERIC[20]
DCL OUT[4], GENERIC[21]
DCL OUT[5], GENERIC[22]
DCL OUT[6], GENERIC[23]
DCL OUT[7], GENERIC[24]
DCL OUT[8], GENERIC[25]
DCL CONST[0..240]
DCL TEMP[0..11], LOCAL
DCL ADDR[0]
IMM[0] FLT32 {    0.0010,     1.0000,   255.0100,     3.0000}
IMM[1] INT32 {3, 41, 42, 43}
IMM[2] FLT32 {   -1.0000,     0.0000,     1.0000,     0.0000}
  0: MAD TEMP[0].xyz, IN[1].xyzz, CONST[36].zzzz, CONST[36].xyxx
  1: MOV TEMP[1].xz, TEMP[0].xxzx
  2: ADD TEMP[0].x, TEMP[0].yyyy, IMM[0].xxxx
  3: MOV TEMP[1].y, TEMP[0].xxxx
  4: MOV TEMP[0], IN[0]
  5: MOV TEMP[2].xyz, TEMP[1].xyzx
  6: UIF CONST[240].xxxx :0
  7:   DP3 TEMP[3].x, IN[9].xyzz, IMM[0].yyyy
  8:   ADD TEMP[3].x, IMM[0].yyyy, -TEMP[3].xxxx
  9:   MUL TEMP[4], IN[8], IMM[0].zzzz
 10:   F2I TEMP[4], TEMP[4]
 11:   UMAD TEMP[5].x, TEMP[4].wwww, IMM[1].xxxx, IMM[1].yyyy
 12:   UMAD TEMP[6].x, TEMP[4].zzzz, IMM[1].xxxx, IMM[1].yyyy
 13:   UMAD TEMP[7].x, TEMP[4].yyyy, IMM[1].xxxx, IMM[1].yyyy
 14:   UMAD TEMP[8].x, TEMP[4].xxxx, IMM[1].xxxx, IMM[1].yyyy
 15:   UARL ADDR[0].x, TEMP[8].xxxx
 16:   MUL TEMP[8], CONST[ADDR[0].x], IN[9].xxxx
 17:   UARL ADDR[0].x, TEMP[7].xxxx
 18:   MAD TEMP[7], CONST[ADDR[0].x], IN[9].yyyy, TEMP[8]
 19:   UARL ADDR[0].x, TEMP[6].xxxx
 20:   MAD TEMP[6], CONST[ADDR[0].x], IN[9].zzzz, TEMP[7]
 21:   UARL ADDR[0].x, TEMP[5].xxxx
 22:   UARL ADDR[0].x, TEMP[5].xxxx
 23:   MAD TEMP[5], CONST[ADDR[0].x], TEMP[3].xxxx, TEMP[6]
 24:   UMAD TEMP[6].x, TEMP[4].wwww, IMM[1].xxxx, IMM[1].zzzz
 25:   UMAD TEMP[7].x, TEMP[4].zzzz, IMM[1].xxxx, IMM[1].zzzz
 26:   UMAD TEMP[8].x, TEMP[4].yyyy, IMM[1].xxxx, IMM[1].zzzz
 27:   UMAD TEMP[9].x, TEMP[4].xxxx, IMM[1].xxxx, IMM[1].zzzz
 28:   UARL ADDR[0].x, TEMP[9].xxxx
 29:   MUL TEMP[9], CONST[ADDR[0].x], IN[9].xxxx
 30:   UARL ADDR[0].x, TEMP[8].xxxx
 31:   MAD TEMP[8], CONST[ADDR[0].x], IN[9].yyyy, TEMP[9]
 32:   UARL ADDR[0].x, TEMP[7].xxxx
 33:   MAD TEMP[7], CONST[ADDR[0].x], IN[9].zzzz, TEMP[8]
 34:   UARL ADDR[0].x, TEMP[6].xxxx
 35:   UARL ADDR[0].x, TEMP[6].xxxx
 36:   MAD TEMP[6], CONST[ADDR[0].x], TEMP[3].xxxx, TEMP[7]
 37:   UMAD TEMP[7].x, TEMP[4].wwww, IMM[1].xxxx, IMM[1].wwww
 38:   UMAD TEMP[8].x, TEMP[4].zzzz, IMM[1].xxxx, IMM[1].wwww
 39:   UMAD TEMP[9].x, TEMP[4].yyyy, IMM[1].xxxx, IMM[1].wwww
 40:   UMAD TEMP[4].x, TEMP[4].xxxx, IMM[1].xxxx, IMM[1].wwww
 41:   UARL ADDR[0].x, TEMP[4].xxxx
 42:   MUL TEMP[4], CONST[ADDR[0].x], IN[9].xxxx
 43:   UARL ADDR[0].x, TEMP[9].xxxx
 44:   MAD TEMP[4], CONST[ADDR[0].x], IN[9].yyyy, TEMP[4]
 45:   UARL ADDR[0].x, TEMP[8].xxxx
 46:   MAD TEMP[4], CONST[ADDR[0].x], IN[9].zzzz, TEMP[4]
 47:   UARL ADDR[0].x, TEMP[7].xxxx
 48:   UARL ADDR[0].x, TEMP[7].xxxx
 49:   MAD TEMP[3], CONST[ADDR[0].x], TEMP[3].xxxx, TEMP[4]
 50:   DP4 TEMP[4].x, IN[0], TEMP[5]
 51:   DP4 TEMP[7].x, IN[0], TEMP[6]
 52:   MOV TEMP[4].y, TEMP[7].xxxx
 53:   DP4 TEMP[7].x, IN[0], TEMP[3]
 54:   MOV TEMP[4].z, TEMP[7].xxxx
 55:   MOV TEMP[0].xyz, TEMP[4].xyzx
 56:   DP3 TEMP[4].x, TEMP[1].xyzz, TEMP[5].xyzz
 57:   DP3 TEMP[5].x, TEMP[1].xyzz, TEMP[6].xyzz
 58:   MOV TEMP[4].y, TEMP[5].xxxx
 59:   DP3 TEMP[1].x, TEMP[1].xyzz, TEMP[3].xyzz
 60:   MOV TEMP[4].z, TEMP[1].xxxx
 61:   MOV TEMP[2].xyz, TEMP[4].xyzx
 62: ENDIF
 63: DP4 TEMP[1].x, TEMP[0], CONST[0]
 64: DP4 TEMP[3].x, TEMP[0], CONST[1]
 65: MOV TEMP[1].y, TEMP[3].xxxx
 66: DP4 TEMP[3].x, TEMP[0], CONST[2]
 67: MOV TEMP[1].z, TEMP[3].xxxx
 68: DP4 TEMP[3].x, TEMP[0], CONST[3]
 69: MOV TEMP[1].w, TEMP[3].xxxx
 70: DP4 TEMP[3].x, TEMP[0], CONST[4]
 71: DP4 TEMP[4].x, TEMP[0], CONST[5]
 72: MOV TEMP[3].y, TEMP[4].xxxx
 73: DP4 TEMP[0].x, TEMP[0], CONST[6]
 74: MOV TEMP[3].z, TEMP[0].xxxx
 75: MOV TEMP[0].xyz, TEMP[3].xyzx
 76: MOV TEMP[0].w, IMM[0].yyyy
 77: DP3 TEMP[4].x, CONST[4].xyzz, CONST[4].xyzz
 78: RCP TEMP[4].x, TEMP[4].xxxx
 79: MUL TEMP[4].xyz, CONST[4].xyzz, TEMP[4].xxxx
 80: DP3 TEMP[4].x, TEMP[2].xyzz, TEMP[4].xyzz
 81: DP3 TEMP[5].x, CONST[5].xyzz, CONST[5].xyzz
 82: RCP TEMP[5].x, TEMP[5].xxxx
 83: MUL TEMP[5].xyz, CONST[5].xyzz, TEMP[5].xxxx
 84: DP3 TEMP[5].x, TEMP[2].xyzz, TEMP[5].xyzz
 85: MOV TEMP[4].y, TEMP[5].xxxx
 86: DP3 TEMP[5].x, CONST[6].xyzz, CONST[6].xyzz
 87: RCP TEMP[5].x, TEMP[5].xxxx
 88: MUL TEMP[5].xyz, CONST[6].xyzz, TEMP[5].xxxx
 89: DP3 TEMP[2].x, TEMP[2].xyzz, TEMP[5].xyzz
 90: MOV TEMP[4].z, TEMP[2].xxxx
 91: DP3 TEMP[2].x, TEMP[4].xyzz, TEMP[4].xyzz
 92: RSQ TEMP[2].x, TEMP[2].xxxx
 93: MUL TEMP[2].xyz, TEMP[4].xyzz, TEMP[2].xxxx
 94: MUL TEMP[4].xyz, TEMP[2].xyzz, TEMP[2].xyzz
 95: MUL TEMP[5].xyz, TEMP[2].xzyy, TEMP[2].zyxx
 96: MAD TEMP[6].xyz, CONST[15].xyzz, TEMP[2].xxxx, CONST[14].xyzz
 97: MAD TEMP[6].xyz, CONST[16].xyzz, TEMP[2].yyyy, TEMP[6].xyzz
 98: MAD TEMP[6].xyz, CONST[17].xyzz, TEMP[2].zzzz, TEMP[6].xyzz
 99: MAD TEMP[6].xyz, CONST[18].xyzz, TEMP[5].xxxx, TEMP[6].xyzz
100: MAD TEMP[6].xyz, CONST[19].xyzz, TEMP[5].yyyy, TEMP[6].xyzz
101: MAD TEMP[6].xyz, CONST[20].xyzz, TEMP[5].zzzz, TEMP[6].xyzz
102: MAD TEMP[5].x, TEMP[4].zzzz, IMM[0].wwww, IMM[2].xxxx
103: MAD TEMP[6].xyz, CONST[21].xyzz, TEMP[5].xxxx, TEMP[6].xyzz
104: ADD TEMP[4].x, TEMP[4].xxxx, -TEMP[4].yyyy
105: MAD TEMP[4].xyz, CONST[22].xyzz, TEMP[4].xxxx, TEMP[6].xyzz
106: MAX TEMP[4].xyz, TEMP[4].xyzz, IMM[2].yyyy
107: FSGE TEMP[6].x, CONST[31].zzzz, IMM[2].yyyy
108: UIF TEMP[6].xxxx :0
109:   MOV TEMP[6].x, TEMP[3].xxxx
110: ELSE :0
111:   MOV TEMP[6].x, IN[5].xxxx
112: ENDIF
113: FSGE TEMP[7].x, CONST[31].zzzz, IMM[2].yyyy
114: UIF TEMP[7].xxxx :0
115:   MOV TEMP[7].x, TEMP[3].yyyy
116: ELSE :0
117:   MOV TEMP[7].x, IN[5].yyyy
118: ENDIF
119: FSGE TEMP[8].x, CONST[31].xxxx, IMM[2].yyyy
120: UIF TEMP[8].xxxx :0
121:   MOV TEMP[8].x, TEMP[3].zzzz
122: ELSE :0
123:   MOV TEMP[8].x, TEMP[6].xxxx
124: ENDIF
125: MOV TEMP[5].x, TEMP[8].xxxx
126: FSGE TEMP[6].x, CONST[31].yyyy, IMM[2].yyyy
127: UIF TEMP[6].xxxx :0
128:   MOV TEMP[6].x, TEMP[3].zzzz
129: ELSE :0
130:   MOV TEMP[6].x, TEMP[7].xxxx
131: ENDIF
132: MOV TEMP[5].y, TEMP[6].xxxx
133: MOV TEMP[6].zw, IMM[2].zzyz
134: MOV TEMP[6].xy, TEMP[5].xyxx
135: FSGE TEMP[7].x, CONST[32].zzzz, IMM[2].yyyy
136: UIF TEMP[7].xxxx :0
137:   MOV TEMP[7].x, TEMP[3].xxxx
138: ELSE :0
139:   MOV TEMP[7].x, IN[2].xxxx
140: ENDIF
141: FSGE TEMP[8].x, CONST[32].zzzz, IMM[2].yyyy
142: UIF TEMP[8].xxxx :0
143:   MOV TEMP[8].x, TEMP[3].yyyy
144: ELSE :0
145:   MOV TEMP[8].x, IN[2].yyyy
146: ENDIF
147: FSGE TEMP[9].x, CONST[32].xxxx, IMM[2].yyyy
148: UIF TEMP[9].xxxx :0
149:   MOV TEMP[9].x, TEMP[3].zzzz
150: ELSE :0
151:   MOV TEMP[9].x, TEMP[7].xxxx
152: ENDIF
153: MOV TEMP[5].x, TEMP[9].xxxx
154: FSGE TEMP[7].x, CONST[32].yyyy, IMM[2].yyyy
155: UIF TEMP[7].xxxx :0
156:   MOV TEMP[7].x, TEMP[3].zzzz
157: ELSE :0
158:   MOV TEMP[7].x, TEMP[8].xxxx
159: ENDIF
160: MOV TEMP[5].y, TEMP[7].xxxx
161: MOV TEMP[7].zw, IMM[2].zzyz
162: MOV TEMP[7].xy, TEMP[5].xyxx
163: FSGE TEMP[8].x, CONST[33].zzzz, IMM[2].yyyy
164: UIF TEMP[8].xxxx :0
165:   MOV TEMP[8].x, TEMP[3].xxxx
166: ELSE :0
167:   MOV TEMP[8].x, IN[6].xxxx
168: ENDIF
169: FSGE TEMP[9].x, CONST[33].zzzz, IMM[2].yyyy
170: UIF TEMP[9].xxxx :0
171:   MOV TEMP[9].x, TEMP[3].yyyy
172: ELSE :0
173:   MOV TEMP[9].x, IN[6].yyyy
174: ENDIF
175: FSGE TEMP[10].x, CONST[33].xxxx, IMM[2].yyyy
176: UIF TEMP[10].xxxx :0
177:   MOV TEMP[10].x, TEMP[3].zzzz
178: ELSE :0
179:   MOV TEMP[10].x, TEMP[8].xxxx
180: ENDIF
181: MOV TEMP[5].x, TEMP[10].xxxx
182: FSGE TEMP[8].x, CONST[33].yyyy, IMM[2].yyyy
183: UIF TEMP[8].xxxx :0
184:   MOV TEMP[8].x, TEMP[3].zzzz
185: ELSE :0
186:   MOV TEMP[8].x, TEMP[9].xxxx
187: ENDIF
188: MOV TEMP[5].y, TEMP[8].xxxx
189: MOV TEMP[8].zw, IMM[2].zzyz
190: MOV TEMP[8].xy, TEMP[5].xyxx
191: FSGE TEMP[9].x, CONST[34].zzzz, IMM[2].yyyy
192: UIF TEMP[9].xxxx :0
193:   MOV TEMP[9].x, TEMP[3].xxxx
194: ELSE :0
195:   MOV TEMP[9].x, IN[3].xxxx
196: ENDIF
197: FSGE TEMP[10].x, CONST[34].zzzz, IMM[2].yyyy
198: UIF TEMP[10].xxxx :0
199:   MOV TEMP[10].x, TEMP[3].yyyy
200: ELSE :0
201:   MOV TEMP[10].x, IN[3].yyyy
202: ENDIF
203: FSGE TEMP[11].x, CONST[34].xxxx, IMM[2].yyyy
204: UIF TEMP[11].xxxx :0
205:   MOV TEMP[11].x, TEMP[3].zzzz
206: ELSE :0
207:   MOV TEMP[11].x, TEMP[9].xxxx
208: ENDIF
209: MOV TEMP[5].x, TEMP[11].xxxx
210: FSGE TEMP[9].x, CONST[34].yyyy, IMM[2].yyyy
211: UIF TEMP[9].xxxx :0
212:   MOV TEMP[3].x, TEMP[3].zzzz
213: ELSE :0
214:   MOV TEMP[3].x, TEMP[10].xxxx
215: ENDIF
216: MOV TEMP[5].y, TEMP[3].xxxx
217: MOV TEMP[3].zw, IMM[2].zzyz
218: MOV TEMP[3].xy, TEMP[5].xyxx
219: MAD TEMP[5].xy, IN[4].xyyy, CONST[29].xyyy, CONST[29].zwww
220: DP4 TEMP[9].x, TEMP[6], CONST[27]
221: DP4 TEMP[6].x, TEMP[6], CONST[28]
222: MOV TEMP[9].y, TEMP[6].xxxx
223: MOV TEMP[5].zw, TEMP[9].yyxy
224: DP4 TEMP[6].x, TEMP[7], CONST[7]
225: DP4 TEMP[7].x, TEMP[7], CONST[8]
226: MOV TEMP[6].y, TEMP[7].xxxx
227: MOV TEMP[6].xy, TEMP[6].xyxx
228: DP4 TEMP[7].x, TEMP[8], CONST[25]
229: DP4 TEMP[8].x, TEMP[8], CONST[26]
230: MOV TEMP[7].y, TEMP[8].xxxx
231: MOV TEMP[6].zw, TEMP[7].yyxy
232: DP4 TEMP[7].x, TEMP[3], CONST[23]
233: DP4 TEMP[3].x, TEMP[3], CONST[24]
234: MOV TEMP[7].y, TEMP[3].xxxx
235: MOV TEMP[3].xy, TEMP[7].xyxx
236: MOV TEMP[3].zw, IMM[2].yyyy
237: MAD TEMP[7], IN[7].zyxw, CONST[30].xxxy, CONST[30].zzzz
238: MOV TEMP[8].w, TEMP[7].wwww
239: MUL TEMP[8].xyz, TEMP[7].xyzz, TEMP[7].xyzz
240: MOV TEMP[2].xyz, TEMP[2].xyzx
241: MOV TEMP[2].w, TEMP[4].xxxx
242: MOV TEMP[4].xy, TEMP[4].yzyy
243: MOV OUT[3], TEMP[6]
244: MOV OUT[7], TEMP[2]
245: MOV OUT[2], TEMP[0]
246: MOV OUT[4], TEMP[5]
247: MOV OUT[0], TEMP[1]
248: MOV OUT[8], TEMP[4]
249: MOV OUT[6], TEMP[8]
250: MOV OUT[1], TEMP[1]
251: MOV OUT[5], TEMP[3]
252: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0)
  %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4)
  %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8)
  %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12)
  %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16)
  %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20)
  %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24)
  %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28)
  %20 = call float @llvm.SI.load.const(<16 x i8> %11, i32 32)
  %21 = call float @llvm.SI.load.const(<16 x i8> %11, i32 36)
  %22 = call float @llvm.SI.load.const(<16 x i8> %11, i32 40)
  %23 = call float @llvm.SI.load.const(<16 x i8> %11, i32 44)
  %24 = call float @llvm.SI.load.const(<16 x i8> %11, i32 48)
  %25 = call float @llvm.SI.load.const(<16 x i8> %11, i32 52)
  %26 = call float @llvm.SI.load.const(<16 x i8> %11, i32 56)
  %27 = call float @llvm.SI.load.const(<16 x i8> %11, i32 60)
  %28 = call float @llvm.SI.load.const(<16 x i8> %11, i32 64)
  %29 = call float @llvm.SI.load.const(<16 x i8> %11, i32 68)
  %30 = call float @llvm.SI.load.const(<16 x i8> %11, i32 72)
  %31 = call float @llvm.SI.load.const(<16 x i8> %11, i32 76)
  %32 = call float @llvm.SI.load.const(<16 x i8> %11, i32 80)
  %33 = call float @llvm.SI.load.const(<16 x i8> %11, i32 84)
  %34 = call float @llvm.SI.load.const(<16 x i8> %11, i32 88)
  %35 = call float @llvm.SI.load.const(<16 x i8> %11, i32 92)
  %36 = call float @llvm.SI.load.const(<16 x i8> %11, i32 96)
  %37 = call float @llvm.SI.load.const(<16 x i8> %11, i32 100)
  %38 = call float @llvm.SI.load.const(<16 x i8> %11, i32 104)
  %39 = call float @llvm.SI.load.const(<16 x i8> %11, i32 108)
  %40 = call float @llvm.SI.load.const(<16 x i8> %11, i32 112)
  %41 = call float @llvm.SI.load.const(<16 x i8> %11, i32 116)
  %42 = call float @llvm.SI.load.const(<16 x i8> %11, i32 120)
  %43 = call float @llvm.SI.load.const(<16 x i8> %11, i32 124)
  %44 = call float @llvm.SI.load.const(<16 x i8> %11, i32 128)
  %45 = call float @llvm.SI.load.const(<16 x i8> %11, i32 132)
  %46 = call float @llvm.SI.load.const(<16 x i8> %11, i32 136)
  %47 = call float @llvm.SI.load.const(<16 x i8> %11, i32 140)
  %48 = call float @llvm.SI.load.const(<16 x i8> %11, i32 224)
  %49 = call float @llvm.SI.load.const(<16 x i8> %11, i32 228)
  %50 = call float @llvm.SI.load.const(<16 x i8> %11, i32 232)
  %51 = call float @llvm.SI.load.const(<16 x i8> %11, i32 240)
  %52 = call float @llvm.SI.load.const(<16 x i8> %11, i32 244)
  %53 = call float @llvm.SI.load.const(<16 x i8> %11, i32 248)
  %54 = call float @llvm.SI.load.const(<16 x i8> %11, i32 256)
  %55 = call float @llvm.SI.load.const(<16 x i8> %11, i32 260)
  %56 = call float @llvm.SI.load.const(<16 x i8> %11, i32 264)
  %57 = call float @llvm.SI.load.const(<16 x i8> %11, i32 272)
  %58 = call float @llvm.SI.load.const(<16 x i8> %11, i32 276)
  %59 = call float @llvm.SI.load.const(<16 x i8> %11, i32 280)
  %60 = call float @llvm.SI.load.const(<16 x i8> %11, i32 288)
  %61 = call float @llvm.SI.load.const(<16 x i8> %11, i32 292)
  %62 = call float @llvm.SI.load.const(<16 x i8> %11, i32 296)
  %63 = call float @llvm.SI.load.const(<16 x i8> %11, i32 304)
  %64 = call float @llvm.SI.load.const(<16 x i8> %11, i32 308)
  %65 = call float @llvm.SI.load.const(<16 x i8> %11, i32 312)
  %66 = call float @llvm.SI.load.const(<16 x i8> %11, i32 320)
  %67 = call float @llvm.SI.load.const(<16 x i8> %11, i32 324)
  %68 = call float @llvm.SI.load.const(<16 x i8> %11, i32 328)
  %69 = call float @llvm.SI.load.const(<16 x i8> %11, i32 336)
  %70 = call float @llvm.SI.load.const(<16 x i8> %11, i32 340)
  %71 = call float @llvm.SI.load.const(<16 x i8> %11, i32 344)
  %72 = call float @llvm.SI.load.const(<16 x i8> %11, i32 352)
  %73 = call float @llvm.SI.load.const(<16 x i8> %11, i32 356)
  %74 = call float @llvm.SI.load.const(<16 x i8> %11, i32 360)
  %75 = call float @llvm.SI.load.const(<16 x i8> %11, i32 368)
  %76 = call float @llvm.SI.load.const(<16 x i8> %11, i32 372)
  %77 = call float @llvm.SI.load.const(<16 x i8> %11, i32 376)
  %78 = call float @llvm.SI.load.const(<16 x i8> %11, i32 380)
  %79 = call float @llvm.SI.load.const(<16 x i8> %11, i32 384)
  %80 = call float @llvm.SI.load.const(<16 x i8> %11, i32 388)
  %81 = call float @llvm.SI.load.const(<16 x i8> %11, i32 392)
  %82 = call float @llvm.SI.load.const(<16 x i8> %11, i32 396)
  %83 = call float @llvm.SI.load.const(<16 x i8> %11, i32 400)
  %84 = call float @llvm.SI.load.const(<16 x i8> %11, i32 404)
  %85 = call float @llvm.SI.load.const(<16 x i8> %11, i32 408)
  %86 = call float @llvm.SI.load.const(<16 x i8> %11, i32 412)
  %87 = call float @llvm.SI.load.const(<16 x i8> %11, i32 416)
  %88 = call float @llvm.SI.load.const(<16 x i8> %11, i32 420)
  %89 = call float @llvm.SI.load.const(<16 x i8> %11, i32 424)
  %90 = call float @llvm.SI.load.const(<16 x i8> %11, i32 428)
  %91 = call float @llvm.SI.load.const(<16 x i8> %11, i32 432)
  %92 = call float @llvm.SI.load.const(<16 x i8> %11, i32 436)
  %93 = call float @llvm.SI.load.const(<16 x i8> %11, i32 440)
  %94 = call float @llvm.SI.load.const(<16 x i8> %11, i32 444)
  %95 = call float @llvm.SI.load.const(<16 x i8> %11, i32 448)
  %96 = call float @llvm.SI.load.const(<16 x i8> %11, i32 452)
  %97 = call float @llvm.SI.load.const(<16 x i8> %11, i32 456)
  %98 = call float @llvm.SI.load.const(<16 x i8> %11, i32 460)
  %99 = call float @llvm.SI.load.const(<16 x i8> %11, i32 464)
  %100 = call float @llvm.SI.load.const(<16 x i8> %11, i32 468)
  %101 = call float @llvm.SI.load.const(<16 x i8> %11, i32 472)
  %102 = call float @llvm.SI.load.const(<16 x i8> %11, i32 476)
  %103 = call float @llvm.SI.load.const(<16 x i8> %11, i32 480)
  %104 = call float @llvm.SI.load.const(<16 x i8> %11, i32 484)
  %105 = call float @llvm.SI.load.const(<16 x i8> %11, i32 488)
  %106 = call float @llvm.SI.load.const(<16 x i8> %11, i32 496)
  %107 = call float @llvm.SI.load.const(<16 x i8> %11, i32 500)
  %108 = call float @llvm.SI.load.const(<16 x i8> %11, i32 504)
  %109 = call float @llvm.SI.load.const(<16 x i8> %11, i32 512)
  %110 = call float @llvm.SI.load.const(<16 x i8> %11, i32 516)
  %111 = call float @llvm.SI.load.const(<16 x i8> %11, i32 520)
  %112 = call float @llvm.SI.load.const(<16 x i8> %11, i32 528)
  %113 = call float @llvm.SI.load.const(<16 x i8> %11, i32 532)
  %114 = call float @llvm.SI.load.const(<16 x i8> %11, i32 536)
  %115 = call float @llvm.SI.load.const(<16 x i8> %11, i32 544)
  %116 = call float @llvm.SI.load.const(<16 x i8> %11, i32 548)
  %117 = call float @llvm.SI.load.const(<16 x i8> %11, i32 552)
  %118 = call float @llvm.SI.load.const(<16 x i8> %11, i32 576)
  %119 = call float @llvm.SI.load.const(<16 x i8> %11, i32 580)
  %120 = call float @llvm.SI.load.const(<16 x i8> %11, i32 584)
  %121 = call float @llvm.SI.load.const(<16 x i8> %11, i32 3840)
  %122 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0
  %123 = load <16 x i8> addrspace(2)* %122, !tbaa !0
  %124 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %123, i32 0, i32 %6)
  %125 = extractelement <4 x float> %124, i32 0
  %126 = extractelement <4 x float> %124, i32 1
  %127 = extractelement <4 x float> %124, i32 2
  %128 = extractelement <4 x float> %124, i32 3
  %129 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 1
  %130 = load <16 x i8> addrspace(2)* %129, !tbaa !0
  %131 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %130, i32 0, i32 %6)
  %132 = extractelement <4 x float> %131, i32 0
  %133 = extractelement <4 x float> %131, i32 1
  %134 = extractelement <4 x float> %131, i32 2
  %135 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 2
  %136 = load <16 x i8> addrspace(2)* %135, !tbaa !0
  %137 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %136, i32 0, i32 %6)
  %138 = extractelement <4 x float> %137, i32 0
  %139 = extractelement <4 x float> %137, i32 1
  %140 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 3
  %141 = load <16 x i8> addrspace(2)* %140, !tbaa !0
  %142 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %141, i32 0, i32 %6)
  %143 = extractelement <4 x float> %142, i32 0
  %144 = extractelement <4 x float> %142, i32 1
  %145 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 4
  %146 = load <16 x i8> addrspace(2)* %145, !tbaa !0
  %147 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %146, i32 0, i32 %6)
  %148 = extractelement <4 x float> %147, i32 0
  %149 = extractelement <4 x float> %147, i32 1
  %150 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 5
  %151 = load <16 x i8> addrspace(2)* %150, !tbaa !0
  %152 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %151, i32 0, i32 %6)
  %153 = extractelement <4 x float> %152, i32 0
  %154 = extractelement <4 x float> %152, i32 1
  %155 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 6
  %156 = load <16 x i8> addrspace(2)* %155, !tbaa !0
  %157 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %156, i32 0, i32 %6)
  %158 = extractelement <4 x float> %157, i32 0
  %159 = extractelement <4 x float> %157, i32 1
  %160 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 7
  %161 = load <16 x i8> addrspace(2)* %160, !tbaa !0
  %162 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %161, i32 0, i32 %6)
  %163 = extractelement <4 x float> %162, i32 0
  %164 = extractelement <4 x float> %162, i32 1
  %165 = extractelement <4 x float> %162, i32 2
  %166 = extractelement <4 x float> %162, i32 3
  %167 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 8
  %168 = load <16 x i8> addrspace(2)* %167, !tbaa !0
  %169 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %168, i32 0, i32 %6)
  %170 = extractelement <4 x float> %169, i32 0
  %171 = extractelement <4 x float> %169, i32 1
  %172 = extractelement <4 x float> %169, i32 2
  %173 = extractelement <4 x float> %169, i32 3
  %174 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 9
  %175 = load <16 x i8> addrspace(2)* %174, !tbaa !0
  %176 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %175, i32 0, i32 %6)
  %177 = extractelement <4 x float> %176, i32 0
  %178 = extractelement <4 x float> %176, i32 1
  %179 = extractelement <4 x float> %176, i32 2
  %180 = fmul float %132, %120
  %181 = fadd float %180, %118
  %182 = fmul float %133, %120
  %183 = fadd float %182, %119
  %184 = fmul float %134, %120
  %185 = fadd float %184, %118
  %186 = fadd float %183, 0x3F50624DE0000000
  %187 = bitcast float %121 to i32
  %188 = icmp ne i32 %187, 0
  br i1 %188, label %IF, label %ENDIF

IF:                                               ; preds = %main_body
  %189 = fmul float %177, 1.000000e+00
  %190 = fmul float %178, 1.000000e+00
  %191 = fadd float %190, %189
  %192 = fmul float %179, 1.000000e+00
  %193 = fadd float %191, %192
  %194 = fsub float -0.000000e+00, %193
  %195 = fadd float 1.000000e+00, %194
  %196 = fmul float %170, 0x406FE051E0000000
  %197 = fmul float %171, 0x406FE051E0000000
  %198 = fmul float %172, 0x406FE051E0000000
  %199 = fmul float %173, 0x406FE051E0000000
  %200 = fptosi float %196 to i32
  %201 = fptosi float %197 to i32
  %202 = fptosi float %198 to i32
  %203 = fptosi float %199 to i32
  %204 = bitcast i32 %200 to float
  %205 = bitcast i32 %201 to float
  %206 = bitcast i32 %202 to float
  %207 = bitcast i32 %203 to float
  %208 = bitcast float %207 to i32
  %209 = mul i32 %208, 3
  %210 = add i32 %209, 41
  %211 = bitcast i32 %210 to float
  %212 = bitcast float %206 to i32
  %213 = mul i32 %212, 3
  %214 = add i32 %213, 41
  %215 = bitcast i32 %214 to float
  %216 = bitcast float %205 to i32
  %217 = mul i32 %216, 3
  %218 = add i32 %217, 41
  %219 = bitcast i32 %218 to float
  %220 = bitcast float %204 to i32
  %221 = mul i32 %220, 3
  %222 = add i32 %221, 41
  %223 = bitcast i32 %222 to float
  %224 = bitcast float %223 to i32
  %225 = shl i32 %224, 4
  %226 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %225)
  %227 = fmul float %226, %177
  %228 = shl i32 %224, 4
  %229 = add i32 %228, 4
  %230 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %229)
  %231 = fmul float %230, %177
  %232 = shl i32 %224, 4
  %233 = add i32 %232, 8
  %234 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %233)
  %235 = fmul float %234, %177
  %236 = shl i32 %224, 4
  %237 = add i32 %236, 12
  %238 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %237)
  %239 = fmul float %238, %177
  %240 = bitcast float %219 to i32
  %241 = shl i32 %240, 4
  %242 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %241)
  %243 = fmul float %242, %178
  %244 = fadd float %243, %227
  %245 = shl i32 %240, 4
  %246 = add i32 %245, 4
  %247 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %246)
  %248 = fmul float %247, %178
  %249 = fadd float %248, %231
  %250 = shl i32 %240, 4
  %251 = add i32 %250, 8
  %252 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %251)
  %253 = fmul float %252, %178
  %254 = fadd float %253, %235
  %255 = shl i32 %240, 4
  %256 = add i32 %255, 12
  %257 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %256)
  %258 = fmul float %257, %178
  %259 = fadd float %258, %239
  %260 = bitcast float %215 to i32
  %261 = shl i32 %260, 4
  %262 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %261)
  %263 = fmul float %262, %179
  %264 = fadd float %263, %244
  %265 = shl i32 %260, 4
  %266 = add i32 %265, 4
  %267 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %266)
  %268 = fmul float %267, %179
  %269 = fadd float %268, %249
  %270 = shl i32 %260, 4
  %271 = add i32 %270, 8
  %272 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %271)
  %273 = fmul float %272, %179
  %274 = fadd float %273, %254
  %275 = shl i32 %260, 4
  %276 = add i32 %275, 12
  %277 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %276)
  %278 = fmul float %277, %179
  %279 = fadd float %278, %259
  %280 = bitcast float %211 to i32
  %281 = shl i32 %280, 4
  %282 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %281)
  %283 = fmul float %282, %195
  %284 = fadd float %283, %264
  %285 = shl i32 %280, 4
  %286 = add i32 %285, 4
  %287 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %286)
  %288 = fmul float %287, %195
  %289 = fadd float %288, %269
  %290 = shl i32 %280, 4
  %291 = add i32 %290, 8
  %292 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %291)
  %293 = fmul float %292, %195
  %294 = fadd float %293, %274
  %295 = shl i32 %280, 4
  %296 = add i32 %295, 12
  %297 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %296)
  %298 = fmul float %297, %195
  %299 = fadd float %298, %279
  %300 = bitcast float %207 to i32
  %301 = mul i32 %300, 3
  %302 = add i32 %301, 42
  %303 = bitcast i32 %302 to float
  %304 = bitcast float %206 to i32
  %305 = mul i32 %304, 3
  %306 = add i32 %305, 42
  %307 = bitcast i32 %306 to float
  %308 = bitcast float %205 to i32
  %309 = mul i32 %308, 3
  %310 = add i32 %309, 42
  %311 = bitcast i32 %310 to float
  %312 = bitcast float %204 to i32
  %313 = mul i32 %312, 3
  %314 = add i32 %313, 42
  %315 = bitcast i32 %314 to float
  %316 = bitcast float %315 to i32
  %317 = shl i32 %316, 4
  %318 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %317)
  %319 = fmul float %318, %177
  %320 = shl i32 %316, 4
  %321 = add i32 %320, 4
  %322 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %321)
  %323 = fmul float %322, %177
  %324 = shl i32 %316, 4
  %325 = add i32 %324, 8
  %326 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %325)
  %327 = fmul float %326, %177
  %328 = shl i32 %316, 4
  %329 = add i32 %328, 12
  %330 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %329)
  %331 = fmul float %330, %177
  %332 = bitcast float %311 to i32
  %333 = shl i32 %332, 4
  %334 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %333)
  %335 = fmul float %334, %178
  %336 = fadd float %335, %319
  %337 = shl i32 %332, 4
  %338 = add i32 %337, 4
  %339 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %338)
  %340 = fmul float %339, %178
  %341 = fadd float %340, %323
  %342 = shl i32 %332, 4
  %343 = add i32 %342, 8
  %344 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %343)
  %345 = fmul float %344, %178
  %346 = fadd float %345, %327
  %347 = shl i32 %332, 4
  %348 = add i32 %347, 12
  %349 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %348)
  %350 = fmul float %349, %178
  %351 = fadd float %350, %331
  %352 = bitcast float %307 to i32
  %353 = shl i32 %352, 4
  %354 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %353)
  %355 = fmul float %354, %179
  %356 = fadd float %355, %336
  %357 = shl i32 %352, 4
  %358 = add i32 %357, 4
  %359 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %358)
  %360 = fmul float %359, %179
  %361 = fadd float %360, %341
  %362 = shl i32 %352, 4
  %363 = add i32 %362, 8
  %364 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %363)
  %365 = fmul float %364, %179
  %366 = fadd float %365, %346
  %367 = shl i32 %352, 4
  %368 = add i32 %367, 12
  %369 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %368)
  %370 = fmul float %369, %179
  %371 = fadd float %370, %351
  %372 = bitcast float %303 to i32
  %373 = shl i32 %372, 4
  %374 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %373)
  %375 = fmul float %374, %195
  %376 = fadd float %375, %356
  %377 = shl i32 %372, 4
  %378 = add i32 %377, 4
  %379 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %378)
  %380 = fmul float %379, %195
  %381 = fadd float %380, %361
  %382 = shl i32 %372, 4
  %383 = add i32 %382, 8
  %384 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %383)
  %385 = fmul float %384, %195
  %386 = fadd float %385, %366
  %387 = shl i32 %372, 4
  %388 = add i32 %387, 12
  %389 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %388)
  %390 = fmul float %389, %195
  %391 = fadd float %390, %371
  %392 = bitcast float %207 to i32
  %393 = mul i32 %392, 3
  %394 = add i32 %393, 43
  %395 = bitcast i32 %394 to float
  %396 = bitcast float %206 to i32
  %397 = mul i32 %396, 3
  %398 = add i32 %397, 43
  %399 = bitcast i32 %398 to float
  %400 = bitcast float %205 to i32
  %401 = mul i32 %400, 3
  %402 = add i32 %401, 43
  %403 = bitcast i32 %402 to float
  %404 = bitcast float %204 to i32
  %405 = mul i32 %404, 3
  %406 = add i32 %405, 43
  %407 = bitcast i32 %406 to float
  %408 = bitcast float %407 to i32
  %409 = shl i32 %408, 4
  %410 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %409)
  %411 = fmul float %410, %177
  %412 = shl i32 %408, 4
  %413 = add i32 %412, 4
  %414 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %413)
  %415 = fmul float %414, %177
  %416 = shl i32 %408, 4
  %417 = add i32 %416, 8
  %418 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %417)
  %419 = fmul float %418, %177
  %420 = shl i32 %408, 4
  %421 = add i32 %420, 12
  %422 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %421)
  %423 = fmul float %422, %177
  %424 = bitcast float %403 to i32
  %425 = shl i32 %424, 4
  %426 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %425)
  %427 = fmul float %426, %178
  %428 = fadd float %427, %411
  %429 = shl i32 %424, 4
  %430 = add i32 %429, 4
  %431 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %430)
  %432 = fmul float %431, %178
  %433 = fadd float %432, %415
  %434 = shl i32 %424, 4
  %435 = add i32 %434, 8
  %436 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %435)
  %437 = fmul float %436, %178
  %438 = fadd float %437, %419
  %439 = shl i32 %424, 4
  %440 = add i32 %439, 12
  %441 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %440)
  %442 = fmul float %441, %178
  %443 = fadd float %442, %423
  %444 = bitcast float %399 to i32
  %445 = shl i32 %444, 4
  %446 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %445)
  %447 = fmul float %446, %179
  %448 = fadd float %447, %428
  %449 = shl i32 %444, 4
  %450 = add i32 %449, 4
  %451 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %450)
  %452 = fmul float %451, %179
  %453 = fadd float %452, %433
  %454 = shl i32 %444, 4
  %455 = add i32 %454, 8
  %456 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %455)
  %457 = fmul float %456, %179
  %458 = fadd float %457, %438
  %459 = shl i32 %444, 4
  %460 = add i32 %459, 12
  %461 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %460)
  %462 = fmul float %461, %179
  %463 = fadd float %462, %443
  %464 = bitcast float %395 to i32
  %465 = shl i32 %464, 4
  %466 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %465)
  %467 = fmul float %466, %195
  %468 = fadd float %467, %448
  %469 = shl i32 %464, 4
  %470 = add i32 %469, 4
  %471 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %470)
  %472 = fmul float %471, %195
  %473 = fadd float %472, %453
  %474 = shl i32 %464, 4
  %475 = add i32 %474, 8
  %476 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %475)
  %477 = fmul float %476, %195
  %478 = fadd float %477, %458
  %479 = shl i32 %464, 4
  %480 = add i32 %479, 12
  %481 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %480)
  %482 = fmul float %481, %195
  %483 = fadd float %482, %463
  %484 = fmul float %125, %284
  %485 = fmul float %126, %289
  %486 = fadd float %484, %485
  %487 = fmul float %127, %294
  %488 = fadd float %486, %487
  %489 = fmul float %128, %299
  %490 = fadd float %488, %489
  %491 = fmul float %125, %376
  %492 = fmul float %126, %381
  %493 = fadd float %491, %492
  %494 = fmul float %127, %386
  %495 = fadd float %493, %494
  %496 = fmul float %128, %391
  %497 = fadd float %495, %496
  %498 = fmul float %125, %468
  %499 = fmul float %126, %473
  %500 = fadd float %498, %499
  %501 = fmul float %127, %478
  %502 = fadd float %500, %501
  %503 = fmul float %128, %483
  %504 = fadd float %502, %503
  %505 = fmul float %181, %284
  %506 = fmul float %186, %289
  %507 = fadd float %506, %505
  %508 = fmul float %185, %294
  %509 = fadd float %507, %508
  %510 = fmul float %181, %376
  %511 = fmul float %186, %381
  %512 = fadd float %511, %510
  %513 = fmul float %185, %386
  %514 = fadd float %512, %513
  %515 = fmul float %181, %468
  %516 = fmul float %186, %473
  %517 = fadd float %516, %515
  %518 = fmul float %185, %478
  %519 = fadd float %517, %518
  br label %ENDIF

ENDIF:                                            ; preds = %main_body, %IF
  %temp.0 = phi float [ %490, %IF ], [ %125, %main_body ]
  %temp1.0 = phi float [ %497, %IF ], [ %126, %main_body ]
  %temp2.0 = phi float [ %504, %IF ], [ %127, %main_body ]
  %temp8.0 = phi float [ %509, %IF ], [ %181, %main_body ]
  %temp9.0 = phi float [ %514, %IF ], [ %186, %main_body ]
  %temp10.0 = phi float [ %519, %IF ], [ %185, %main_body ]
  %temp19.0 = phi float [ %463, %IF ], [ 0.000000e+00, %main_body ]
  %520 = fmul float %temp.0, %12
  %521 = fmul float %temp1.0, %13
  %522 = fadd float %520, %521
  %523 = fmul float %temp2.0, %14
  %524 = fadd float %522, %523
  %525 = fmul float %128, %15
  %526 = fadd float %524, %525
  %527 = fmul float %temp.0, %16
  %528 = fmul float %temp1.0, %17
  %529 = fadd float %527, %528
  %530 = fmul float %temp2.0, %18
  %531 = fadd float %529, %530
  %532 = fmul float %128, %19
  %533 = fadd float %531, %532
  %534 = fmul float %temp.0, %20
  %535 = fmul float %temp1.0, %21
  %536 = fadd float %534, %535
  %537 = fmul float %temp2.0, %22
  %538 = fadd float %536, %537
  %539 = fmul float %128, %23
  %540 = fadd float %538, %539
  %541 = fmul float %temp.0, %24
  %542 = fmul float %temp1.0, %25
  %543 = fadd float %541, %542
  %544 = fmul float %temp2.0, %26
  %545 = fadd float %543, %544
  %546 = fmul float %128, %27
  %547 = fadd float %545, %546
  %548 = fmul float %temp.0, %28
  %549 = fmul float %temp1.0, %29
  %550 = fadd float %548, %549
  %551 = fmul float %temp2.0, %30
  %552 = fadd float %550, %551
  %553 = fmul float %128, %31
  %554 = fadd float %552, %553
  %555 = fmul float %temp.0, %32
  %556 = fmul float %temp1.0, %33
  %557 = fadd float %555, %556
  %558 = fmul float %temp2.0, %34
  %559 = fadd float %557, %558
  %560 = fmul float %128, %35
  %561 = fadd float %559, %560
  %562 = fmul float %temp.0, %36
  %563 = fmul float %temp1.0, %37
  %564 = fadd float %562, %563
  %565 = fmul float %temp2.0, %38
  %566 = fadd float %564, %565
  %567 = fmul float %128, %39
  %568 = fadd float %566, %567
  %569 = fmul float %28, %28
  %570 = fmul float %29, %29
  %571 = fadd float %570, %569
  %572 = fmul float %30, %30
  %573 = fadd float %571, %572
  %574 = fdiv float 1.000000e+00, %573
  %575 = fmul float %28, %574
  %576 = fmul float %29, %574
  %577 = fmul float %30, %574
  %578 = fmul float %temp8.0, %575
  %579 = fmul float %temp9.0, %576
  %580 = fadd float %579, %578
  %581 = fmul float %temp10.0, %577
  %582 = fadd float %580, %581
  %583 = fmul float %32, %32
  %584 = fmul float %33, %33
  %585 = fadd float %584, %583
  %586 = fmul float %34, %34
  %587 = fadd float %585, %586
  %588 = fdiv float 1.000000e+00, %587
  %589 = fmul float %32, %588
  %590 = fmul float %33, %588
  %591 = fmul float %34, %588
  %592 = fmul float %temp8.0, %589
  %593 = fmul float %temp9.0, %590
  %594 = fadd float %593, %592
  %595 = fmul float %temp10.0, %591
  %596 = fadd float %594, %595
  %597 = fmul float %36, %36
  %598 = fmul float %37, %37
  %599 = fadd float %598, %597
  %600 = fmul float %38, %38
  %601 = fadd float %599, %600
  %602 = fdiv float 1.000000e+00, %601
  %603 = fmul float %36, %602
  %604 = fmul float %37, %602
  %605 = fmul float %38, %602
  %606 = fmul float %temp8.0, %603
  %607 = fmul float %temp9.0, %604
  %608 = fadd float %607, %606
  %609 = fmul float %temp10.0, %605
  %610 = fadd float %608, %609
  %611 = fmul float %582, %582
  %612 = fmul float %596, %596
  %613 = fadd float %612, %611
  %614 = fmul float %610, %610
  %615 = fadd float %613, %614
  %616 = call float @llvm.AMDGPU.rsq(float %615)
  %617 = fmul float %582, %616
  %618 = fmul float %596, %616
  %619 = fmul float %610, %616
  %620 = fmul float %617, %617
  %621 = fmul float %618, %618
  %622 = fmul float %619, %619
  %623 = fmul float %617, %619
  %624 = fmul float %619, %618
  %625 = fmul float %618, %617
  %626 = fmul float %51, %617
  %627 = fadd float %626, %48
  %628 = fmul float %52, %617
  %629 = fadd float %628, %49
  %630 = fmul float %53, %617
  %631 = fadd float %630, %50
  %632 = fmul float %54, %618
  %633 = fadd float %632, %627
  %634 = fmul float %55, %618
  %635 = fadd float %634, %629
  %636 = fmul float %56, %618
  %637 = fadd float %636, %631
  %638 = fmul float %57, %619
  %639 = fadd float %638, %633
  %640 = fmul float %58, %619
  %641 = fadd float %640, %635
  %642 = fmul float %59, %619
  %643 = fadd float %642, %637
  %644 = fmul float %60, %623
  %645 = fadd float %644, %639
  %646 = fmul float %61, %623
  %647 = fadd float %646, %641
  %648 = fmul float %62, %623
  %649 = fadd float %648, %643
  %650 = fmul float %63, %624
  %651 = fadd float %650, %645
  %652 = fmul float %64, %624
  %653 = fadd float %652, %647
  %654 = fmul float %65, %624
  %655 = fadd float %654, %649
  %656 = fmul float %66, %625
  %657 = fadd float %656, %651
  %658 = fmul float %67, %625
  %659 = fadd float %658, %653
  %660 = fmul float %68, %625
  %661 = fadd float %660, %655
  %662 = fmul float %622, 3.000000e+00
  %663 = fadd float %662, -1.000000e+00
  %664 = fmul float %69, %663
  %665 = fadd float %664, %657
  %666 = fmul float %70, %663
  %667 = fadd float %666, %659
  %668 = fmul float %71, %663
  %669 = fadd float %668, %661
  %670 = fsub float -0.000000e+00, %621
  %671 = fadd float %620, %670
  %672 = fmul float %72, %671
  %673 = fadd float %672, %665
  %674 = fmul float %73, %671
  %675 = fadd float %674, %667
  %676 = fmul float %74, %671
  %677 = fadd float %676, %669
  %678 = fcmp uge float %673, 0.000000e+00
  %679 = select i1 %678, float %673, float 0.000000e+00
  %680 = fcmp uge float %675, 0.000000e+00
  %681 = select i1 %680, float %675, float 0.000000e+00
  %682 = fcmp uge float %677, 0.000000e+00
  %683 = select i1 %682, float %677, float 0.000000e+00
  %684 = fcmp oge float %108, 0.000000e+00
  %685 = sext i1 %684 to i32
  %686 = bitcast i32 %685 to float
  %687 = bitcast float %686 to i32
  %688 = icmp ne i32 %687, 0
  %. = select i1 %688, float %554, float %153
  %689 = fcmp oge float %108, 0.000000e+00
  %690 = sext i1 %689 to i32
  %691 = bitcast i32 %690 to float
  %692 = bitcast float %691 to i32
  %693 = icmp ne i32 %692, 0
  %temp28.0 = select i1 %693, float %561, float %154
  %694 = fcmp oge float %106, 0.000000e+00
  %695 = sext i1 %694 to i32
  %696 = bitcast i32 %695 to float
  %697 = bitcast float %696 to i32
  %698 = icmp ne i32 %697, 0
  %.. = select i1 %698, float %568, float %.
  %699 = fcmp oge float %107, 0.000000e+00
  %700 = sext i1 %699 to i32
  %701 = bitcast i32 %700 to float
  %702 = bitcast float %701 to i32
  %703 = icmp ne i32 %702, 0
  %temp24.1 = select i1 %703, float %568, float %temp28.0
  %704 = fcmp oge float %111, 0.000000e+00
  %705 = sext i1 %704 to i32
  %706 = bitcast i32 %705 to float
  %707 = bitcast float %706 to i32
  %708 = icmp ne i32 %707, 0
  %.143 = select i1 %708, float %554, float %138
  %709 = fcmp oge float %111, 0.000000e+00
  %710 = sext i1 %709 to i32
  %711 = bitcast i32 %710 to float
  %712 = bitcast float %711 to i32
  %713 = icmp ne i32 %712, 0
  %temp32.1 = select i1 %713, float %561, float %139
  %714 = fcmp oge float %109, 0.000000e+00
  %715 = sext i1 %714 to i32
  %716 = bitcast i32 %715 to float
  %717 = bitcast float %716 to i32
  %718 = icmp ne i32 %717, 0
  %..143 = select i1 %718, float %568, float %.143
  %719 = fcmp oge float %110, 0.000000e+00
  %720 = sext i1 %719 to i32
  %721 = bitcast i32 %720 to float
  %722 = bitcast float %721 to i32
  %723 = icmp ne i32 %722, 0
  %temp28.2 = select i1 %723, float %568, float %temp32.1
  %724 = fcmp oge float %114, 0.000000e+00
  %725 = sext i1 %724 to i32
  %726 = bitcast i32 %725 to float
  %727 = bitcast float %726 to i32
  %728 = icmp ne i32 %727, 0
  %.144 = select i1 %728, float %554, float %158
  %729 = fcmp oge float %114, 0.000000e+00
  %730 = sext i1 %729 to i32
  %731 = bitcast i32 %730 to float
  %732 = bitcast float %731 to i32
  %733 = icmp ne i32 %732, 0
  %temp36.1 = select i1 %733, float %561, float %159
  %734 = fcmp oge float %112, 0.000000e+00
  %735 = sext i1 %734 to i32
  %736 = bitcast i32 %735 to float
  %737 = bitcast float %736 to i32
  %738 = icmp ne i32 %737, 0
  %..144 = select i1 %738, float %568, float %.144
  %739 = fcmp oge float %113, 0.000000e+00
  %740 = sext i1 %739 to i32
  %741 = bitcast i32 %740 to float
  %742 = bitcast float %741 to i32
  %743 = icmp ne i32 %742, 0
  %temp32.3 = select i1 %743, float %568, float %temp36.1
  %744 = fcmp oge float %117, 0.000000e+00
  %745 = sext i1 %744 to i32
  %746 = bitcast i32 %745 to float
  %747 = bitcast float %746 to i32
  %748 = icmp ne i32 %747, 0
  %.145 = select i1 %748, float %554, float %143
  %749 = fcmp oge float %117, 0.000000e+00
  %750 = sext i1 %749 to i32
  %751 = bitcast i32 %750 to float
  %752 = bitcast float %751 to i32
  %753 = icmp ne i32 %752, 0
  %temp40.1 = select i1 %753, float %561, float %144
  %754 = fcmp oge float %115, 0.000000e+00
  %755 = sext i1 %754 to i32
  %756 = bitcast i32 %755 to float
  %757 = bitcast float %756 to i32
  %758 = icmp ne i32 %757, 0
  %..145 = select i1 %758, float %568, float %.145
  %759 = fcmp oge float %116, 0.000000e+00
  %760 = sext i1 %759 to i32
  %761 = bitcast i32 %760 to float
  %762 = bitcast float %761 to i32
  %763 = icmp ne i32 %762, 0
  %temp12.0 = select i1 %763, float %568, float %temp40.1
  %764 = fmul float %148, %99
  %765 = fadd float %764, %101
  %766 = fmul float %149, %100
  %767 = fadd float %766, %102
  %768 = fmul float %.., %91
  %769 = fmul float %temp24.1, %92
  %770 = fadd float %768, %769
  %771 = fmul float 0.000000e+00, %93
  %772 = fadd float %770, %771
  %773 = fmul float 1.000000e+00, %94
  %774 = fadd float %772, %773
  %775 = fmul float %.., %95
  %776 = fmul float %temp24.1, %96
  %777 = fadd float %775, %776
  %778 = fmul float 0.000000e+00, %97
  %779 = fadd float %777, %778
  %780 = fmul float 1.000000e+00, %98
  %781 = fadd float %779, %780
  %782 = fmul float %..143, %40
  %783 = fmul float %temp28.2, %41
  %784 = fadd float %782, %783
  %785 = fmul float 0.000000e+00, %42
  %786 = fadd float %784, %785
  %787 = fmul float 1.000000e+00, %43
  %788 = fadd float %786, %787
  %789 = fmul float %..143, %44
  %790 = fmul float %temp28.2, %45
  %791 = fadd float %789, %790
  %792 = fmul float 0.000000e+00, %46
  %793 = fadd float %791, %792
  %794 = fmul float 1.000000e+00, %47
  %795 = fadd float %793, %794
  %796 = fmul float %..144, %83
  %797 = fmul float %temp32.3, %84
  %798 = fadd float %796, %797
  %799 = fmul float 0.000000e+00, %85
  %800 = fadd float %798, %799
  %801 = fmul float 1.000000e+00, %86
  %802 = fadd float %800, %801
  %803 = fmul float %..144, %87
  %804 = fmul float %temp32.3, %88
  %805 = fadd float %803, %804
  %806 = fmul float 0.000000e+00, %89
  %807 = fadd float %805, %806
  %808 = fmul float 1.000000e+00, %90
  %809 = fadd float %807, %808
  %810 = fmul float %..145, %75
  %811 = fmul float %temp12.0, %76
  %812 = fadd float %810, %811
  %813 = fmul float 0.000000e+00, %77
  %814 = fadd float %812, %813
  %815 = fmul float 1.000000e+00, %78
  %816 = fadd float %814, %815
  %817 = fmul float %..145, %79
  %818 = fmul float %temp12.0, %80
  %819 = fadd float %817, %818
  %820 = fmul float 0.000000e+00, %81
  %821 = fadd float %819, %820
  %822 = fmul float 1.000000e+00, %82
  %823 = fadd float %821, %822
  %824 = fmul float %165, %103
  %825 = fadd float %824, %105
  %826 = fmul float %164, %103
  %827 = fadd float %826, %105
  %828 = fmul float %163, %103
  %829 = fadd float %828, %105
  %830 = fmul float %166, %104
  %831 = fadd float %830, %105
  %832 = fmul float %825, %825
  %833 = fmul float %827, %827
  %834 = fmul float %829, %829
  %835 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 16
  %836 = load <16 x i8> addrspace(2)* %835, !tbaa !0
  %837 = call float @llvm.SI.load.const(<16 x i8> %836, i32 0)
  %838 = fmul float %837, %526
  %839 = call float @llvm.SI.load.const(<16 x i8> %836, i32 4)
  %840 = fmul float %839, %533
  %841 = fadd float %838, %840
  %842 = call float @llvm.SI.load.const(<16 x i8> %836, i32 8)
  %843 = fmul float %842, %540
  %844 = fadd float %841, %843
  %845 = call float @llvm.SI.load.const(<16 x i8> %836, i32 12)
  %846 = fmul float %845, %547
  %847 = fadd float %844, %846
  %848 = call float @llvm.SI.load.const(<16 x i8> %836, i32 16)
  %849 = fmul float %848, %526
  %850 = call float @llvm.SI.load.const(<16 x i8> %836, i32 20)
  %851 = fmul float %850, %533
  %852 = fadd float %849, %851
  %853 = call float @llvm.SI.load.const(<16 x i8> %836, i32 24)
  %854 = fmul float %853, %540
  %855 = fadd float %852, %854
  %856 = call float @llvm.SI.load.const(<16 x i8> %836, i32 28)
  %857 = fmul float %856, %547
  %858 = fadd float %855, %857
  %859 = call float @llvm.SI.load.const(<16 x i8> %836, i32 32)
  %860 = fmul float %859, %526
  %861 = call float @llvm.SI.load.const(<16 x i8> %836, i32 36)
  %862 = fmul float %861, %533
  %863 = fadd float %860, %862
  %864 = call float @llvm.SI.load.const(<16 x i8> %836, i32 40)
  %865 = fmul float %864, %540
  %866 = fadd float %863, %865
  %867 = call float @llvm.SI.load.const(<16 x i8> %836, i32 44)
  %868 = fmul float %867, %547
  %869 = fadd float %866, %868
  %870 = call float @llvm.SI.load.const(<16 x i8> %836, i32 48)
  %871 = fmul float %870, %526
  %872 = call float @llvm.SI.load.const(<16 x i8> %836, i32 52)
  %873 = fmul float %872, %533
  %874 = fadd float %871, %873
  %875 = call float @llvm.SI.load.const(<16 x i8> %836, i32 56)
  %876 = fmul float %875, %540
  %877 = fadd float %874, %876
  %878 = call float @llvm.SI.load.const(<16 x i8> %836, i32 60)
  %879 = fmul float %878, %547
  %880 = fadd float %877, %879
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %554, float %561, float %568, float 1.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %788, float %795, float %802, float %809)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %765, float %767, float %774, float %781)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %816, float %823, float 0.000000e+00, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 36, i32 0, float %832, float %833, float %834, float %831)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 37, i32 0, float %617, float %618, float %619, float %679)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 38, i32 0, float %681, float %683, float %683, float %temp19.0)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 12, i32 0, float %526, float %533, float %540, float %547)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 13, i32 0, float %847, float %858, float %869, float %880)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDGPU.rsq(float) #2

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Frame Objects:
  fi#0: size=4, align=4, at location [SP]
  fi#1: size=4, align=4, at location [SP+4]
  fi#2: size=4, align=4, at location [SP+8]
  fi#3: size=4, align=4, at location [SP+12]
  fi#4: size=4, align=4, at location [SP+16]
  fi#5: size=4, align=4, at location [SP+20]
  fi#6: size=4, align=4, at location [SP+24]
  fi#7: size=4, align=4, at location [SP+28]
  fi#8: size=4, align=4, at location [SP+32]
  fi#9: size=4, align=4, at location [SP+36]
  fi#10: size=4, align=4, at location [SP+40]
  fi#11: size=4, align=4, at location [SP+44]
  fi#12: size=4, align=4, at location [SP+48]
Function Live Ins: %SGPR0_SGPR1 in %vreg135, %SGPR6_SGPR7 in %vreg138, %VGPR0 in %vreg141

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
    Successors according to CFG: BB#1(16) BB#2(16)

BB#1: derived from LLVM BB %IF
    Live Ins: %SGPR68_SGPR69_SGPR70_SGPR71 %VGPR33 %VGPR34 %VGPR28 %VGPR24 %VGPR35 %VGPR36 %VGPR29 %VGPR25 %VGPR37 %VGPR38 %VGPR30 %VGPR26 %VGPR39 %VGPR40 %VGPR31 %VGPR27 %SGPR57 %SGPR58 %SGPR55 %VGPR57 %SGPR62 %SGPR63 %SGPR59 %VGPR58 %SGPR34 %SGPR35 %SGPR33 %VGPR59 %VGPR50 %VGPR32 %VGPR45 %VGPR54 %VGPR55 %VGPR52 %VGPR53 %SGPR26 %VGPR51 %SGPR27 %VGPR41_VGPR42_VGPR43_VGPR44 %VGPR11_VGPR12_VGPR13_VGPR14 %VGPR15_VGPR16_VGPR17_VGPR18 %VGPR19_VGPR20_VGPR21_VGPR22 %VGPR46_VGPR47_VGPR48_VGPR49 %VGPR6_VGPR7_VGPR8_VGPR9 %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0 %VGPR1_VGPR2_VGPR3_VGPR4 %SGPR32 %SGPR29 %SGPR31 %SGPR66 %SGPR64 %SGPR65 %SGPR61 %SGPR56 %SGPR60 %SGPR48 %SGPR38 %SGPR47 %SGPR45 %SGPR49 %SGPR51 %SGPR52 %SGPR46 %SGPR50 %SGPR53 %SGPR54 %SGPR67 %SGPR73 %SGPR75 %SGPR76 %SGPR72 %SGPR74 %SGPR77 %SGPR78 %SGPR36 %SGPR39 %SGPR41 %SGPR42 %SGPR37 %SGPR40 %SGPR43 %SGPR44 %SGPR19 %SGPR22 %SGPR23 %SGPR24 %SGPR18 %SGPR25 %SGPR20 %SGPR28 %SGPR21 %SGPR17 %SGPR30 %SGPR79 %SGPR81 %SGPR83 %SGPR84 %SGPR80 %SGPR82 %SGPR85 %SGPR86 %SGPR88_SGPR89 %VGPR5 %VGPR23 %VGPR10 %VGPR86 %VGPR87 %VGPR88 %VGPR89 %VGPR90 %VGPR91 %VGPR92 %VGPR93 %VGPR94 %VGPR95 %VGPR96 %VGPR97 %VGPR98
    Predecessors according to CFG: BB#0
    Successors according to CFG: BB#2

BB#2: derived from LLVM BB %ENDIF
    Live Ins: %VGPR33 %VGPR34 %VGPR28 %VGPR24 %VGPR35 %VGPR36 %VGPR29 %VGPR25 %VGPR37 %VGPR38 %VGPR30 %VGPR26 %VGPR39 %VGPR40 %VGPR31 %VGPR27 %SGPR57 %SGPR58 %SGPR55 %VGPR57 %SGPR62 %SGPR63 %SGPR59 %VGPR58 %SGPR34 %SGPR35 %SGPR33 %VGPR59 %VGPR50 %VGPR32 %VGPR45 %VGPR54 %VGPR55 %VGPR52 %VGPR53 %SGPR26 %VGPR51 %SGPR27 %VGPR41_VGPR42_VGPR43_VGPR44 %VGPR11_VGPR12_VGPR13_VGPR14 %VGPR15_VGPR16_VGPR17_VGPR18 %VGPR19_VGPR20_VGPR21_VGPR22 %VGPR46_VGPR47_VGPR48_VGPR49 %VGPR6_VGPR7_VGPR8_VGPR9 %SGPR0_SGPR1 %VGPR1_VGPR2_VGPR3_VGPR4 %SGPR32 %SGPR29 %SGPR31 %SGPR66 %SGPR64 %SGPR65 %SGPR61 %SGPR56 %SGPR60 %SGPR48 %SGPR38 %SGPR47 %SGPR45 %SGPR49 %SGPR51 %SGPR52 %SGPR46 %SGPR50 %SGPR53 %SGPR54 %SGPR67 %SGPR73 %SGPR75 %SGPR76 %SGPR72 %SGPR74 %SGPR77 %SGPR78 %SGPR36 %SGPR39 %SGPR41 %SGPR42 %SGPR37 %SGPR40 %SGPR43 %SGPR44 %SGPR19 %SGPR22 %SGPR23 %SGPR24 %SGPR18 %SGPR25 %SGPR20 %SGPR28 %SGPR21 %SGPR17 %SGPR30 %SGPR79 %SGPR81 %SGPR83 %SGPR84 %SGPR80 %SGPR82 %SGPR85 %SGPR86 %SGPR88_SGPR89 %VGPR62 %VGPR61 %VGPR60 %VGPR5 %VGPR23 %VGPR10 %VGPR56 %VGPR86 %VGPR87 %VGPR88 %VGPR89 %VGPR90 %VGPR91 %VGPR92 %VGPR93 %VGPR94 %VGPR95 %VGPR96 %VGPR97 %VGPR98
    Predecessors according to CFG: BB#0 BB#1
	EXP 0, 9, 0, 1, 1, %VGPR0, %VGPR0, %VGPR0, %VGPR0, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	EXP 0, 9, 0, 1, 1, v0, v0, v0, v0 ; F8001890 00000000
	S_ENDPGM                          ; BF810000

VERT
DCL IN[0]
DCL IN[1]
DCL IN[2]
DCL IN[3]
DCL IN[4]
DCL IN[5]
DCL IN[6]
DCL IN[7]
DCL IN[8]
DCL IN[9]
DCL OUT[0], POSITION
DCL OUT[1], CLIPVERTEX
DCL OUT[2], GENERIC[19]
DCL OUT[3], GENERIC[20]
DCL OUT[4], GENERIC[21]
DCL OUT[5], GENERIC[22]
DCL OUT[6], GENERIC[23]
DCL OUT[7], GENERIC[24]
DCL OUT[8], GENERIC[25]
DCL CONST[0..240]
DCL TEMP[0..11], LOCAL
DCL ADDR[0]
IMM[0] FLT32 {    0.0010,     1.0000,   255.0100,     3.0000}
IMM[1] INT32 {3, 41, 42, 43}
IMM[2] FLT32 {   -1.0000,     0.0000,     1.0000,     0.0000}
  0: MAD TEMP[0].xyz, IN[1].xyzz, CONST[36].zzzz, CONST[36].xyxx
  1: MOV TEMP[1].xz, TEMP[0].xxzx
  2: ADD TEMP[0].x, TEMP[0].yyyy, IMM[0].xxxx
  3: MOV TEMP[1].y, TEMP[0].xxxx
  4: MOV TEMP[0], IN[0]
  5: MOV TEMP[2].xyz, TEMP[1].xyzx
  6: UIF CONST[240].xxxx :0
  7:   DP3 TEMP[3].x, IN[9].xyzz, IMM[0].yyyy
  8:   ADD TEMP[3].x, IMM[0].yyyy, -TEMP[3].xxxx
  9:   MUL TEMP[4], IN[8], IMM[0].zzzz
 10:   F2I TEMP[4], TEMP[4]
 11:   UMAD TEMP[5].x, TEMP[4].wwww, IMM[1].xxxx, IMM[1].yyyy
 12:   UMAD TEMP[6].x, TEMP[4].zzzz, IMM[1].xxxx, IMM[1].yyyy
 13:   UMAD TEMP[7].x, TEMP[4].yyyy, IMM[1].xxxx, IMM[1].yyyy
 14:   UMAD TEMP[8].x, TEMP[4].xxxx, IMM[1].xxxx, IMM[1].yyyy
 15:   UARL ADDR[0].x, TEMP[8].xxxx
 16:   MUL TEMP[8], CONST[ADDR[0].x], IN[9].xxxx
 17:   UARL ADDR[0].x, TEMP[7].xxxx
 18:   MAD TEMP[7], CONST[ADDR[0].x], IN[9].yyyy, TEMP[8]
 19:   UARL ADDR[0].x, TEMP[6].xxxx
 20:   MAD TEMP[6], CONST[ADDR[0].x], IN[9].zzzz, TEMP[7]
 21:   UARL ADDR[0].x, TEMP[5].xxxx
 22:   UARL ADDR[0].x, TEMP[5].xxxx
 23:   MAD TEMP[5], CONST[ADDR[0].x], TEMP[3].xxxx, TEMP[6]
 24:   UMAD TEMP[6].x, TEMP[4].wwww, IMM[1].xxxx, IMM[1].zzzz
 25:   UMAD TEMP[7].x, TEMP[4].zzzz, IMM[1].xxxx, IMM[1].zzzz
 26:   UMAD TEMP[8].x, TEMP[4].yyyy, IMM[1].xxxx, IMM[1].zzzz
 27:   UMAD TEMP[9].x, TEMP[4].xxxx, IMM[1].xxxx, IMM[1].zzzz
 28:   UARL ADDR[0].x, TEMP[9].xxxx
 29:   MUL TEMP[9], CONST[ADDR[0].x], IN[9].xxxx
 30:   UARL ADDR[0].x, TEMP[8].xxxx
 31:   MAD TEMP[8], CONST[ADDR[0].x], IN[9].yyyy, TEMP[9]
 32:   UARL ADDR[0].x, TEMP[7].xxxx
 33:   MAD TEMP[7], CONST[ADDR[0].x], IN[9].zzzz, TEMP[8]
 34:   UARL ADDR[0].x, TEMP[6].xxxx
 35:   UARL ADDR[0].x, TEMP[6].xxxx
 36:   MAD TEMP[6], CONST[ADDR[0].x], TEMP[3].xxxx, TEMP[7]
 37:   UMAD TEMP[7].x, TEMP[4].wwww, IMM[1].xxxx, IMM[1].wwww
 38:   UMAD TEMP[8].x, TEMP[4].zzzz, IMM[1].xxxx, IMM[1].wwww
 39:   UMAD TEMP[9].x, TEMP[4].yyyy, IMM[1].xxxx, IMM[1].wwww
 40:   UMAD TEMP[4].x, TEMP[4].xxxx, IMM[1].xxxx, IMM[1].wwww
 41:   UARL ADDR[0].x, TEMP[4].xxxx
 42:   MUL TEMP[4], CONST[ADDR[0].x], IN[9].xxxx
 43:   UARL ADDR[0].x, TEMP[9].xxxx
 44:   MAD TEMP[4], CONST[ADDR[0].x], IN[9].yyyy, TEMP[4]
 45:   UARL ADDR[0].x, TEMP[8].xxxx
 46:   MAD TEMP[4], CONST[ADDR[0].x], IN[9].zzzz, TEMP[4]
 47:   UARL ADDR[0].x, TEMP[7].xxxx
 48:   UARL ADDR[0].x, TEMP[7].xxxx
 49:   MAD TEMP[3], CONST[ADDR[0].x], TEMP[3].xxxx, TEMP[4]
 50:   DP4 TEMP[4].x, IN[0], TEMP[5]
 51:   DP4 TEMP[7].x, IN[0], TEMP[6]
 52:   MOV TEMP[4].y, TEMP[7].xxxx
 53:   DP4 TEMP[7].x, IN[0], TEMP[3]
 54:   MOV TEMP[4].z, TEMP[7].xxxx
 55:   MOV TEMP[0].xyz, TEMP[4].xyzx
 56:   DP3 TEMP[4].x, TEMP[1].xyzz, TEMP[5].xyzz
 57:   DP3 TEMP[5].x, TEMP[1].xyzz, TEMP[6].xyzz
 58:   MOV TEMP[4].y, TEMP[5].xxxx
 59:   DP3 TEMP[1].x, TEMP[1].xyzz, TEMP[3].xyzz
 60:   MOV TEMP[4].z, TEMP[1].xxxx
 61:   MOV TEMP[2].xyz, TEMP[4].xyzx
 62: ENDIF
 63: DP4 TEMP[1].x, TEMP[0], CONST[0]
 64: DP4 TEMP[3].x, TEMP[0], CONST[1]
 65: MOV TEMP[1].y, TEMP[3].xxxx
 66: DP4 TEMP[3].x, TEMP[0], CONST[2]
 67: MOV TEMP[1].z, TEMP[3].xxxx
 68: DP4 TEMP[3].x, TEMP[0], CONST[3]
 69: MOV TEMP[1].w, TEMP[3].xxxx
 70: DP4 TEMP[3].x, TEMP[0], CONST[4]
 71: DP4 TEMP[4].x, TEMP[0], CONST[5]
 72: MOV TEMP[3].y, TEMP[4].xxxx
 73: DP4 TEMP[0].x, TEMP[0], CONST[6]
 74: MOV TEMP[3].z, TEMP[0].xxxx
 75: MOV TEMP[0].xyz, TEMP[3].xyzx
 76: MOV TEMP[0].w, IMM[0].yyyy
 77: DP3 TEMP[4].x, CONST[4].xyzz, CONST[4].xyzz
 78: RCP TEMP[4].x, TEMP[4].xxxx
 79: MUL TEMP[4].xyz, CONST[4].xyzz, TEMP[4].xxxx
 80: DP3 TEMP[4].x, TEMP[2].xyzz, TEMP[4].xyzz
 81: DP3 TEMP[5].x, CONST[5].xyzz, CONST[5].xyzz
 82: RCP TEMP[5].x, TEMP[5].xxxx
 83: MUL TEMP[5].xyz, CONST[5].xyzz, TEMP[5].xxxx
 84: DP3 TEMP[5].x, TEMP[2].xyzz, TEMP[5].xyzz
 85: MOV TEMP[4].y, TEMP[5].xxxx
 86: DP3 TEMP[5].x, CONST[6].xyzz, CONST[6].xyzz
 87: RCP TEMP[5].x, TEMP[5].xxxx
 88: MUL TEMP[5].xyz, CONST[6].xyzz, TEMP[5].xxxx
 89: DP3 TEMP[2].x, TEMP[2].xyzz, TEMP[5].xyzz
 90: MOV TEMP[4].z, TEMP[2].xxxx
 91: DP3 TEMP[2].x, TEMP[4].xyzz, TEMP[4].xyzz
 92: RSQ TEMP[2].x, TEMP[2].xxxx
 93: MUL TEMP[2].xyz, TEMP[4].xyzz, TEMP[2].xxxx
 94: MUL TEMP[4].xyz, TEMP[2].xyzz, TEMP[2].xyzz
 95: MUL TEMP[5].xyz, TEMP[2].xzyy, TEMP[2].zyxx
 96: MAD TEMP[6].xyz, CONST[15].xyzz, TEMP[2].xxxx, CONST[14].xyzz
 97: MAD TEMP[6].xyz, CONST[16].xyzz, TEMP[2].yyyy, TEMP[6].xyzz
 98: MAD TEMP[6].xyz, CONST[17].xyzz, TEMP[2].zzzz, TEMP[6].xyzz
 99: MAD TEMP[6].xyz, CONST[18].xyzz, TEMP[5].xxxx, TEMP[6].xyzz
100: MAD TEMP[6].xyz, CONST[19].xyzz, TEMP[5].yyyy, TEMP[6].xyzz
101: MAD TEMP[6].xyz, CONST[20].xyzz, TEMP[5].zzzz, TEMP[6].xyzz
102: MAD TEMP[5].x, TEMP[4].zzzz, IMM[0].wwww, IMM[2].xxxx
103: MAD TEMP[6].xyz, CONST[21].xyzz, TEMP[5].xxxx, TEMP[6].xyzz
104: ADD TEMP[4].x, TEMP[4].xxxx, -TEMP[4].yyyy
105: MAD TEMP[4].xyz, CONST[22].xyzz, TEMP[4].xxxx, TEMP[6].xyzz
106: MAX TEMP[4].xyz, TEMP[4].xyzz, IMM[2].yyyy
107: FSGE TEMP[6].x, CONST[31].zzzz, IMM[2].yyyy
108: UIF TEMP[6].xxxx :0
109:   MOV TEMP[6].x, TEMP[3].xxxx
110: ELSE :0
111:   MOV TEMP[6].x, IN[5].xxxx
112: ENDIF
113: FSGE TEMP[7].x, CONST[31].zzzz, IMM[2].yyyy
114: UIF TEMP[7].xxxx :0
115:   MOV TEMP[7].x, TEMP[3].yyyy
116: ELSE :0
117:   MOV TEMP[7].x, IN[5].yyyy
118: ENDIF
119: FSGE TEMP[8].x, CONST[31].xxxx, IMM[2].yyyy
120: UIF TEMP[8].xxxx :0
121:   MOV TEMP[8].x, TEMP[3].zzzz
122: ELSE :0
123:   MOV TEMP[8].x, TEMP[6].xxxx
124: ENDIF
125: MOV TEMP[5].x, TEMP[8].xxxx
126: FSGE TEMP[6].x, CONST[31].yyyy, IMM[2].yyyy
127: UIF TEMP[6].xxxx :0
128:   MOV TEMP[6].x, TEMP[3].zzzz
129: ELSE :0
130:   MOV TEMP[6].x, TEMP[7].xxxx
131: ENDIF
132: MOV TEMP[5].y, TEMP[6].xxxx
133: MOV TEMP[6].zw, IMM[2].zzyz
134: MOV TEMP[6].xy, TEMP[5].xyxx
135: FSGE TEMP[7].x, CONST[32].zzzz, IMM[2].yyyy
136: UIF TEMP[7].xxxx :0
137:   MOV TEMP[7].x, TEMP[3].xxxx
138: ELSE :0
139:   MOV TEMP[7].x, IN[2].xxxx
140: ENDIF
141: FSGE TEMP[8].x, CONST[32].zzzz, IMM[2].yyyy
142: UIF TEMP[8].xxxx :0
143:   MOV TEMP[8].x, TEMP[3].yyyy
144: ELSE :0
145:   MOV TEMP[8].x, IN[2].yyyy
146: ENDIF
147: FSGE TEMP[9].x, CONST[32].xxxx, IMM[2].yyyy
148: UIF TEMP[9].xxxx :0
149:   MOV TEMP[9].x, TEMP[3].zzzz
150: ELSE :0
151:   MOV TEMP[9].x, TEMP[7].xxxx
152: ENDIF
153: MOV TEMP[5].x, TEMP[9].xxxx
154: FSGE TEMP[7].x, CONST[32].yyyy, IMM[2].yyyy
155: UIF TEMP[7].xxxx :0
156:   MOV TEMP[7].x, TEMP[3].zzzz
157: ELSE :0
158:   MOV TEMP[7].x, TEMP[8].xxxx
159: ENDIF
160: MOV TEMP[5].y, TEMP[7].xxxx
161: MOV TEMP[7].zw, IMM[2].zzyz
162: MOV TEMP[7].xy, TEMP[5].xyxx
163: FSGE TEMP[8].x, CONST[33].zzzz, IMM[2].yyyy
164: UIF TEMP[8].xxxx :0
165:   MOV TEMP[8].x, TEMP[3].xxxx
166: ELSE :0
167:   MOV TEMP[8].x, IN[6].xxxx
168: ENDIF
169: FSGE TEMP[9].x, CONST[33].zzzz, IMM[2].yyyy
170: UIF TEMP[9].xxxx :0
171:   MOV TEMP[9].x, TEMP[3].yyyy
172: ELSE :0
173:   MOV TEMP[9].x, IN[6].yyyy
174: ENDIF
175: FSGE TEMP[10].x, CONST[33].xxxx, IMM[2].yyyy
176: UIF TEMP[10].xxxx :0
177:   MOV TEMP[10].x, TEMP[3].zzzz
178: ELSE :0
179:   MOV TEMP[10].x, TEMP[8].xxxx
180: ENDIF
181: MOV TEMP[5].x, TEMP[10].xxxx
182: FSGE TEMP[8].x, CONST[33].yyyy, IMM[2].yyyy
183: UIF TEMP[8].xxxx :0
184:   MOV TEMP[8].x, TEMP[3].zzzz
185: ELSE :0
186:   MOV TEMP[8].x, TEMP[9].xxxx
187: ENDIF
188: MOV TEMP[5].y, TEMP[8].xxxx
189: MOV TEMP[8].zw, IMM[2].zzyz
190: MOV TEMP[8].xy, TEMP[5].xyxx
191: FSGE TEMP[9].x, CONST[34].zzzz, IMM[2].yyyy
192: UIF TEMP[9].xxxx :0
193:   MOV TEMP[9].x, TEMP[3].xxxx
194: ELSE :0
195:   MOV TEMP[9].x, IN[3].xxxx
196: ENDIF
197: FSGE TEMP[10].x, CONST[34].zzzz, IMM[2].yyyy
198: UIF TEMP[10].xxxx :0
199:   MOV TEMP[10].x, TEMP[3].yyyy
200: ELSE :0
201:   MOV TEMP[10].x, IN[3].yyyy
202: ENDIF
203: FSGE TEMP[11].x, CONST[34].xxxx, IMM[2].yyyy
204: UIF TEMP[11].xxxx :0
205:   MOV TEMP[11].x, TEMP[3].zzzz
206: ELSE :0
207:   MOV TEMP[11].x, TEMP[9].xxxx
208: ENDIF
209: MOV TEMP[5].x, TEMP[11].xxxx
210: FSGE TEMP[9].x, CONST[34].yyyy, IMM[2].yyyy
211: UIF TEMP[9].xxxx :0
212:   MOV TEMP[3].x, TEMP[3].zzzz
213: ELSE :0
214:   MOV TEMP[3].x, TEMP[10].xxxx
215: ENDIF
216: MOV TEMP[5].y, TEMP[3].xxxx
217: MOV TEMP[3].zw, IMM[2].zzyz
218: MOV TEMP[3].xy, TEMP[5].xyxx
219: MAD TEMP[5].xy, IN[4].xyyy, CONST[29].xyyy, CONST[29].zwww
220: DP4 TEMP[9].x, TEMP[6], CONST[27]
221: DP4 TEMP[6].x, TEMP[6], CONST[28]
222: MOV TEMP[9].y, TEMP[6].xxxx
223: MOV TEMP[5].zw, TEMP[9].yyxy
224: DP4 TEMP[6].x, TEMP[7], CONST[7]
225: DP4 TEMP[7].x, TEMP[7], CONST[8]
226: MOV TEMP[6].y, TEMP[7].xxxx
227: MOV TEMP[6].xy, TEMP[6].xyxx
228: DP4 TEMP[7].x, TEMP[8], CONST[25]
229: DP4 TEMP[8].x, TEMP[8], CONST[26]
230: MOV TEMP[7].y, TEMP[8].xxxx
231: MOV TEMP[6].zw, TEMP[7].yyxy
232: DP4 TEMP[7].x, TEMP[3], CONST[23]
233: DP4 TEMP[3].x, TEMP[3], CONST[24]
234: MOV TEMP[7].y, TEMP[3].xxxx
235: MOV TEMP[3].xy, TEMP[7].xyxx
236: MOV TEMP[3].zw, IMM[2].yyyy
237: MAD TEMP[7], IN[7].zyxw, CONST[30].xxxy, CONST[30].zzzz
238: MOV TEMP[8].w, TEMP[7].wwww
239: MUL TEMP[8].xyz, TEMP[7].xyzz, TEMP[7].xyzz
240: MOV TEMP[2].xyz, TEMP[2].xyzx
241: MOV TEMP[2].w, TEMP[4].xxxx
242: MOV TEMP[4].xy, TEMP[4].yzyy
243: MOV OUT[3], TEMP[6]
244: MOV OUT[7], TEMP[2]
245: MOV OUT[2], TEMP[0]
246: MOV OUT[4], TEMP[5]
247: MOV OUT[0], TEMP[1]
248: MOV OUT[8], TEMP[4]
249: MOV OUT[6], TEMP[8]
250: MOV OUT[1], TEMP[1]
251: MOV OUT[5], TEMP[3]
252: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0)
  %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4)
  %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8)
  %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12)
  %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16)
  %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20)
  %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24)
  %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28)
  %20 = call float @llvm.SI.load.const(<16 x i8> %11, i32 32)
  %21 = call float @llvm.SI.load.const(<16 x i8> %11, i32 36)
  %22 = call float @llvm.SI.load.const(<16 x i8> %11, i32 40)
  %23 = call float @llvm.SI.load.const(<16 x i8> %11, i32 44)
  %24 = call float @llvm.SI.load.const(<16 x i8> %11, i32 48)
  %25 = call float @llvm.SI.load.const(<16 x i8> %11, i32 52)
  %26 = call float @llvm.SI.load.const(<16 x i8> %11, i32 56)
  %27 = call float @llvm.SI.load.const(<16 x i8> %11, i32 60)
  %28 = call float @llvm.SI.load.const(<16 x i8> %11, i32 64)
  %29 = call float @llvm.SI.load.const(<16 x i8> %11, i32 68)
  %30 = call float @llvm.SI.load.const(<16 x i8> %11, i32 72)
  %31 = call float @llvm.SI.load.const(<16 x i8> %11, i32 76)
  %32 = call float @llvm.SI.load.const(<16 x i8> %11, i32 80)
  %33 = call float @llvm.SI.load.const(<16 x i8> %11, i32 84)
  %34 = call float @llvm.SI.load.const(<16 x i8> %11, i32 88)
  %35 = call float @llvm.SI.load.const(<16 x i8> %11, i32 92)
  %36 = call float @llvm.SI.load.const(<16 x i8> %11, i32 96)
  %37 = call float @llvm.SI.load.const(<16 x i8> %11, i32 100)
  %38 = call float @llvm.SI.load.const(<16 x i8> %11, i32 104)
  %39 = call float @llvm.SI.load.const(<16 x i8> %11, i32 108)
  %40 = call float @llvm.SI.load.const(<16 x i8> %11, i32 112)
  %41 = call float @llvm.SI.load.const(<16 x i8> %11, i32 116)
  %42 = call float @llvm.SI.load.const(<16 x i8> %11, i32 120)
  %43 = call float @llvm.SI.load.const(<16 x i8> %11, i32 124)
  %44 = call float @llvm.SI.load.const(<16 x i8> %11, i32 128)
  %45 = call float @llvm.SI.load.const(<16 x i8> %11, i32 132)
  %46 = call float @llvm.SI.load.const(<16 x i8> %11, i32 136)
  %47 = call float @llvm.SI.load.const(<16 x i8> %11, i32 140)
  %48 = call float @llvm.SI.load.const(<16 x i8> %11, i32 224)
  %49 = call float @llvm.SI.load.const(<16 x i8> %11, i32 228)
  %50 = call float @llvm.SI.load.const(<16 x i8> %11, i32 232)
  %51 = call float @llvm.SI.load.const(<16 x i8> %11, i32 240)
  %52 = call float @llvm.SI.load.const(<16 x i8> %11, i32 244)
  %53 = call float @llvm.SI.load.const(<16 x i8> %11, i32 248)
  %54 = call float @llvm.SI.load.const(<16 x i8> %11, i32 256)
  %55 = call float @llvm.SI.load.const(<16 x i8> %11, i32 260)
  %56 = call float @llvm.SI.load.const(<16 x i8> %11, i32 264)
  %57 = call float @llvm.SI.load.const(<16 x i8> %11, i32 272)
  %58 = call float @llvm.SI.load.const(<16 x i8> %11, i32 276)
  %59 = call float @llvm.SI.load.const(<16 x i8> %11, i32 280)
  %60 = call float @llvm.SI.load.const(<16 x i8> %11, i32 288)
  %61 = call float @llvm.SI.load.const(<16 x i8> %11, i32 292)
  %62 = call float @llvm.SI.load.const(<16 x i8> %11, i32 296)
  %63 = call float @llvm.SI.load.const(<16 x i8> %11, i32 304)
  %64 = call float @llvm.SI.load.const(<16 x i8> %11, i32 308)
  %65 = call float @llvm.SI.load.const(<16 x i8> %11, i32 312)
  %66 = call float @llvm.SI.load.const(<16 x i8> %11, i32 320)
  %67 = call float @llvm.SI.load.const(<16 x i8> %11, i32 324)
  %68 = call float @llvm.SI.load.const(<16 x i8> %11, i32 328)
  %69 = call float @llvm.SI.load.const(<16 x i8> %11, i32 336)
  %70 = call float @llvm.SI.load.const(<16 x i8> %11, i32 340)
  %71 = call float @llvm.SI.load.const(<16 x i8> %11, i32 344)
  %72 = call float @llvm.SI.load.const(<16 x i8> %11, i32 352)
  %73 = call float @llvm.SI.load.const(<16 x i8> %11, i32 356)
  %74 = call float @llvm.SI.load.const(<16 x i8> %11, i32 360)
  %75 = call float @llvm.SI.load.const(<16 x i8> %11, i32 368)
  %76 = call float @llvm.SI.load.const(<16 x i8> %11, i32 372)
  %77 = call float @llvm.SI.load.const(<16 x i8> %11, i32 376)
  %78 = call float @llvm.SI.load.const(<16 x i8> %11, i32 380)
  %79 = call float @llvm.SI.load.const(<16 x i8> %11, i32 384)
  %80 = call float @llvm.SI.load.const(<16 x i8> %11, i32 388)
  %81 = call float @llvm.SI.load.const(<16 x i8> %11, i32 392)
  %82 = call float @llvm.SI.load.const(<16 x i8> %11, i32 396)
  %83 = call float @llvm.SI.load.const(<16 x i8> %11, i32 400)
  %84 = call float @llvm.SI.load.const(<16 x i8> %11, i32 404)
  %85 = call float @llvm.SI.load.const(<16 x i8> %11, i32 408)
  %86 = call float @llvm.SI.load.const(<16 x i8> %11, i32 412)
  %87 = call float @llvm.SI.load.const(<16 x i8> %11, i32 416)
  %88 = call float @llvm.SI.load.const(<16 x i8> %11, i32 420)
  %89 = call float @llvm.SI.load.const(<16 x i8> %11, i32 424)
  %90 = call float @llvm.SI.load.const(<16 x i8> %11, i32 428)
  %91 = call float @llvm.SI.load.const(<16 x i8> %11, i32 432)
  %92 = call float @llvm.SI.load.const(<16 x i8> %11, i32 436)
  %93 = call float @llvm.SI.load.const(<16 x i8> %11, i32 440)
  %94 = call float @llvm.SI.load.const(<16 x i8> %11, i32 444)
  %95 = call float @llvm.SI.load.const(<16 x i8> %11, i32 448)
  %96 = call float @llvm.SI.load.const(<16 x i8> %11, i32 452)
  %97 = call float @llvm.SI.load.const(<16 x i8> %11, i32 456)
  %98 = call float @llvm.SI.load.const(<16 x i8> %11, i32 460)
  %99 = call float @llvm.SI.load.const(<16 x i8> %11, i32 464)
  %100 = call float @llvm.SI.load.const(<16 x i8> %11, i32 468)
  %101 = call float @llvm.SI.load.const(<16 x i8> %11, i32 472)
  %102 = call float @llvm.SI.load.const(<16 x i8> %11, i32 476)
  %103 = call float @llvm.SI.load.const(<16 x i8> %11, i32 480)
  %104 = call float @llvm.SI.load.const(<16 x i8> %11, i32 484)
  %105 = call float @llvm.SI.load.const(<16 x i8> %11, i32 488)
  %106 = call float @llvm.SI.load.const(<16 x i8> %11, i32 496)
  %107 = call float @llvm.SI.load.const(<16 x i8> %11, i32 500)
  %108 = call float @llvm.SI.load.const(<16 x i8> %11, i32 504)
  %109 = call float @llvm.SI.load.const(<16 x i8> %11, i32 512)
  %110 = call float @llvm.SI.load.const(<16 x i8> %11, i32 516)
  %111 = call float @llvm.SI.load.const(<16 x i8> %11, i32 520)
  %112 = call float @llvm.SI.load.const(<16 x i8> %11, i32 528)
  %113 = call float @llvm.SI.load.const(<16 x i8> %11, i32 532)
  %114 = call float @llvm.SI.load.const(<16 x i8> %11, i32 536)
  %115 = call float @llvm.SI.load.const(<16 x i8> %11, i32 544)
  %116 = call float @llvm.SI.load.const(<16 x i8> %11, i32 548)
  %117 = call float @llvm.SI.load.const(<16 x i8> %11, i32 552)
  %118 = call float @llvm.SI.load.const(<16 x i8> %11, i32 576)
  %119 = call float @llvm.SI.load.const(<16 x i8> %11, i32 580)
  %120 = call float @llvm.SI.load.const(<16 x i8> %11, i32 584)
  %121 = call float @llvm.SI.load.const(<16 x i8> %11, i32 3840)
  %122 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0
  %123 = load <16 x i8> addrspace(2)* %122, !tbaa !0
  %124 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %123, i32 0, i32 %6)
  %125 = extractelement <4 x float> %124, i32 0
  %126 = extractelement <4 x float> %124, i32 1
  %127 = extractelement <4 x float> %124, i32 2
  %128 = extractelement <4 x float> %124, i32 3
  %129 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 1
  %130 = load <16 x i8> addrspace(2)* %129, !tbaa !0
  %131 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %130, i32 0, i32 %6)
  %132 = extractelement <4 x float> %131, i32 0
  %133 = extractelement <4 x float> %131, i32 1
  %134 = extractelement <4 x float> %131, i32 2
  %135 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 2
  %136 = load <16 x i8> addrspace(2)* %135, !tbaa !0
  %137 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %136, i32 0, i32 %6)
  %138 = extractelement <4 x float> %137, i32 0
  %139 = extractelement <4 x float> %137, i32 1
  %140 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 3
  %141 = load <16 x i8> addrspace(2)* %140, !tbaa !0
  %142 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %141, i32 0, i32 %6)
  %143 = extractelement <4 x float> %142, i32 0
  %144 = extractelement <4 x float> %142, i32 1
  %145 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 4
  %146 = load <16 x i8> addrspace(2)* %145, !tbaa !0
  %147 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %146, i32 0, i32 %6)
  %148 = extractelement <4 x float> %147, i32 0
  %149 = extractelement <4 x float> %147, i32 1
  %150 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 5
  %151 = load <16 x i8> addrspace(2)* %150, !tbaa !0
  %152 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %151, i32 0, i32 %6)
  %153 = extractelement <4 x float> %152, i32 0
  %154 = extractelement <4 x float> %152, i32 1
  %155 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 6
  %156 = load <16 x i8> addrspace(2)* %155, !tbaa !0
  %157 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %156, i32 0, i32 %6)
  %158 = extractelement <4 x float> %157, i32 0
  %159 = extractelement <4 x float> %157, i32 1
  %160 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 7
  %161 = load <16 x i8> addrspace(2)* %160, !tbaa !0
  %162 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %161, i32 0, i32 %6)
  %163 = extractelement <4 x float> %162, i32 0
  %164 = extractelement <4 x float> %162, i32 1
  %165 = extractelement <4 x float> %162, i32 2
  %166 = extractelement <4 x float> %162, i32 3
  %167 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 8
  %168 = load <16 x i8> addrspace(2)* %167, !tbaa !0
  %169 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %168, i32 0, i32 %6)
  %170 = extractelement <4 x float> %169, i32 0
  %171 = extractelement <4 x float> %169, i32 1
  %172 = extractelement <4 x float> %169, i32 2
  %173 = extractelement <4 x float> %169, i32 3
  %174 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 9
  %175 = load <16 x i8> addrspace(2)* %174, !tbaa !0
  %176 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %175, i32 0, i32 %6)
  %177 = extractelement <4 x float> %176, i32 0
  %178 = extractelement <4 x float> %176, i32 1
  %179 = extractelement <4 x float> %176, i32 2
  %180 = fmul float %132, %120
  %181 = fadd float %180, %118
  %182 = fmul float %133, %120
  %183 = fadd float %182, %119
  %184 = fmul float %134, %120
  %185 = fadd float %184, %118
  %186 = fadd float %183, 0x3F50624DE0000000
  %187 = bitcast float %121 to i32
  %188 = icmp ne i32 %187, 0
  br i1 %188, label %IF, label %ENDIF

IF:                                               ; preds = %main_body
  %189 = fmul float %177, 1.000000e+00
  %190 = fmul float %178, 1.000000e+00
  %191 = fadd float %190, %189
  %192 = fmul float %179, 1.000000e+00
  %193 = fadd float %191, %192
  %194 = fsub float -0.000000e+00, %193
  %195 = fadd float 1.000000e+00, %194
  %196 = fmul float %170, 0x406FE051E0000000
  %197 = fmul float %171, 0x406FE051E0000000
  %198 = fmul float %172, 0x406FE051E0000000
  %199 = fmul float %173, 0x406FE051E0000000
  %200 = fptosi float %196 to i32
  %201 = fptosi float %197 to i32
  %202 = fptosi float %198 to i32
  %203 = fptosi float %199 to i32
  %204 = bitcast i32 %200 to float
  %205 = bitcast i32 %201 to float
  %206 = bitcast i32 %202 to float
  %207 = bitcast i32 %203 to float
  %208 = bitcast float %207 to i32
  %209 = mul i32 %208, 3
  %210 = add i32 %209, 41
  %211 = bitcast i32 %210 to float
  %212 = bitcast float %206 to i32
  %213 = mul i32 %212, 3
  %214 = add i32 %213, 41
  %215 = bitcast i32 %214 to float
  %216 = bitcast float %205 to i32
  %217 = mul i32 %216, 3
  %218 = add i32 %217, 41
  %219 = bitcast i32 %218 to float
  %220 = bitcast float %204 to i32
  %221 = mul i32 %220, 3
  %222 = add i32 %221, 41
  %223 = bitcast i32 %222 to float
  %224 = bitcast float %223 to i32
  %225 = shl i32 %224, 4
  %226 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %225)
  %227 = fmul float %226, %177
  %228 = shl i32 %224, 4
  %229 = add i32 %228, 4
  %230 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %229)
  %231 = fmul float %230, %177
  %232 = shl i32 %224, 4
  %233 = add i32 %232, 8
  %234 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %233)
  %235 = fmul float %234, %177
  %236 = shl i32 %224, 4
  %237 = add i32 %236, 12
  %238 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %237)
  %239 = fmul float %238, %177
  %240 = bitcast float %219 to i32
  %241 = shl i32 %240, 4
  %242 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %241)
  %243 = fmul float %242, %178
  %244 = fadd float %243, %227
  %245 = shl i32 %240, 4
  %246 = add i32 %245, 4
  %247 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %246)
  %248 = fmul float %247, %178
  %249 = fadd float %248, %231
  %250 = shl i32 %240, 4
  %251 = add i32 %250, 8
  %252 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %251)
  %253 = fmul float %252, %178
  %254 = fadd float %253, %235
  %255 = shl i32 %240, 4
  %256 = add i32 %255, 12
  %257 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %256)
  %258 = fmul float %257, %178
  %259 = fadd float %258, %239
  %260 = bitcast float %215 to i32
  %261 = shl i32 %260, 4
  %262 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %261)
  %263 = fmul float %262, %179
  %264 = fadd float %263, %244
  %265 = shl i32 %260, 4
  %266 = add i32 %265, 4
  %267 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %266)
  %268 = fmul float %267, %179
  %269 = fadd float %268, %249
  %270 = shl i32 %260, 4
  %271 = add i32 %270, 8
  %272 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %271)
  %273 = fmul float %272, %179
  %274 = fadd float %273, %254
  %275 = shl i32 %260, 4
  %276 = add i32 %275, 12
  %277 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %276)
  %278 = fmul float %277, %179
  %279 = fadd float %278, %259
  %280 = bitcast float %211 to i32
  %281 = shl i32 %280, 4
  %282 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %281)
  %283 = fmul float %282, %195
  %284 = fadd float %283, %264
  %285 = shl i32 %280, 4
  %286 = add i32 %285, 4
  %287 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %286)
  %288 = fmul float %287, %195
  %289 = fadd float %288, %269
  %290 = shl i32 %280, 4
  %291 = add i32 %290, 8
  %292 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %291)
  %293 = fmul float %292, %195
  %294 = fadd float %293, %274
  %295 = shl i32 %280, 4
  %296 = add i32 %295, 12
  %297 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %296)
  %298 = fmul float %297, %195
  %299 = fadd float %298, %279
  %300 = bitcast float %207 to i32
  %301 = mul i32 %300, 3
  %302 = add i32 %301, 42
  %303 = bitcast i32 %302 to float
  %304 = bitcast float %206 to i32
  %305 = mul i32 %304, 3
  %306 = add i32 %305, 42
  %307 = bitcast i32 %306 to float
  %308 = bitcast float %205 to i32
  %309 = mul i32 %308, 3
  %310 = add i32 %309, 42
  %311 = bitcast i32 %310 to float
  %312 = bitcast float %204 to i32
  %313 = mul i32 %312, 3
  %314 = add i32 %313, 42
  %315 = bitcast i32 %314 to float
  %316 = bitcast float %315 to i32
  %317 = shl i32 %316, 4
  %318 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %317)
  %319 = fmul float %318, %177
  %320 = shl i32 %316, 4
  %321 = add i32 %320, 4
  %322 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %321)
  %323 = fmul float %322, %177
  %324 = shl i32 %316, 4
  %325 = add i32 %324, 8
  %326 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %325)
  %327 = fmul float %326, %177
  %328 = shl i32 %316, 4
  %329 = add i32 %328, 12
  %330 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %329)
  %331 = fmul float %330, %177
  %332 = bitcast float %311 to i32
  %333 = shl i32 %332, 4
  %334 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %333)
  %335 = fmul float %334, %178
  %336 = fadd float %335, %319
  %337 = shl i32 %332, 4
  %338 = add i32 %337, 4
  %339 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %338)
  %340 = fmul float %339, %178
  %341 = fadd float %340, %323
  %342 = shl i32 %332, 4
  %343 = add i32 %342, 8
  %344 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %343)
  %345 = fmul float %344, %178
  %346 = fadd float %345, %327
  %347 = shl i32 %332, 4
  %348 = add i32 %347, 12
  %349 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %348)
  %350 = fmul float %349, %178
  %351 = fadd float %350, %331
  %352 = bitcast float %307 to i32
  %353 = shl i32 %352, 4
  %354 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %353)
  %355 = fmul float %354, %179
  %356 = fadd float %355, %336
  %357 = shl i32 %352, 4
  %358 = add i32 %357, 4
  %359 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %358)
  %360 = fmul float %359, %179
  %361 = fadd float %360, %341
  %362 = shl i32 %352, 4
  %363 = add i32 %362, 8
  %364 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %363)
  %365 = fmul float %364, %179
  %366 = fadd float %365, %346
  %367 = shl i32 %352, 4
  %368 = add i32 %367, 12
  %369 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %368)
  %370 = fmul float %369, %179
  %371 = fadd float %370, %351
  %372 = bitcast float %303 to i32
  %373 = shl i32 %372, 4
  %374 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %373)
  %375 = fmul float %374, %195
  %376 = fadd float %375, %356
  %377 = shl i32 %372, 4
  %378 = add i32 %377, 4
  %379 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %378)
  %380 = fmul float %379, %195
  %381 = fadd float %380, %361
  %382 = shl i32 %372, 4
  %383 = add i32 %382, 8
  %384 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %383)
  %385 = fmul float %384, %195
  %386 = fadd float %385, %366
  %387 = shl i32 %372, 4
  %388 = add i32 %387, 12
  %389 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %388)
  %390 = fmul float %389, %195
  %391 = fadd float %390, %371
  %392 = bitcast float %207 to i32
  %393 = mul i32 %392, 3
  %394 = add i32 %393, 43
  %395 = bitcast i32 %394 to float
  %396 = bitcast float %206 to i32
  %397 = mul i32 %396, 3
  %398 = add i32 %397, 43
  %399 = bitcast i32 %398 to float
  %400 = bitcast float %205 to i32
  %401 = mul i32 %400, 3
  %402 = add i32 %401, 43
  %403 = bitcast i32 %402 to float
  %404 = bitcast float %204 to i32
  %405 = mul i32 %404, 3
  %406 = add i32 %405, 43
  %407 = bitcast i32 %406 to float
  %408 = bitcast float %407 to i32
  %409 = shl i32 %408, 4
  %410 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %409)
  %411 = fmul float %410, %177
  %412 = shl i32 %408, 4
  %413 = add i32 %412, 4
  %414 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %413)
  %415 = fmul float %414, %177
  %416 = shl i32 %408, 4
  %417 = add i32 %416, 8
  %418 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %417)
  %419 = fmul float %418, %177
  %420 = shl i32 %408, 4
  %421 = add i32 %420, 12
  %422 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %421)
  %423 = fmul float %422, %177
  %424 = bitcast float %403 to i32
  %425 = shl i32 %424, 4
  %426 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %425)
  %427 = fmul float %426, %178
  %428 = fadd float %427, %411
  %429 = shl i32 %424, 4
  %430 = add i32 %429, 4
  %431 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %430)
  %432 = fmul float %431, %178
  %433 = fadd float %432, %415
  %434 = shl i32 %424, 4
  %435 = add i32 %434, 8
  %436 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %435)
  %437 = fmul float %436, %178
  %438 = fadd float %437, %419
  %439 = shl i32 %424, 4
  %440 = add i32 %439, 12
  %441 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %440)
  %442 = fmul float %441, %178
  %443 = fadd float %442, %423
  %444 = bitcast float %399 to i32
  %445 = shl i32 %444, 4
  %446 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %445)
  %447 = fmul float %446, %179
  %448 = fadd float %447, %428
  %449 = shl i32 %444, 4
  %450 = add i32 %449, 4
  %451 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %450)
  %452 = fmul float %451, %179
  %453 = fadd float %452, %433
  %454 = shl i32 %444, 4
  %455 = add i32 %454, 8
  %456 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %455)
  %457 = fmul float %456, %179
  %458 = fadd float %457, %438
  %459 = shl i32 %444, 4
  %460 = add i32 %459, 12
  %461 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %460)
  %462 = fmul float %461, %179
  %463 = fadd float %462, %443
  %464 = bitcast float %395 to i32
  %465 = shl i32 %464, 4
  %466 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %465)
  %467 = fmul float %466, %195
  %468 = fadd float %467, %448
  %469 = shl i32 %464, 4
  %470 = add i32 %469, 4
  %471 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %470)
  %472 = fmul float %471, %195
  %473 = fadd float %472, %453
  %474 = shl i32 %464, 4
  %475 = add i32 %474, 8
  %476 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %475)
  %477 = fmul float %476, %195
  %478 = fadd float %477, %458
  %479 = shl i32 %464, 4
  %480 = add i32 %479, 12
  %481 = call float @llvm.SI.load.const(<16 x i8> %11, i32 %480)
  %482 = fmul float %481, %195
  %483 = fadd float %482, %463
  %484 = fmul float %125, %284
  %485 = fmul float %126, %289
  %486 = fadd float %484, %485
  %487 = fmul float %127, %294
  %488 = fadd float %486, %487
  %489 = fmul float %128, %299
  %490 = fadd float %488, %489
  %491 = fmul float %125, %376
  %492 = fmul float %126, %381
  %493 = fadd float %491, %492
  %494 = fmul float %127, %386
  %495 = fadd float %493, %494
  %496 = fmul float %128, %391
  %497 = fadd float %495, %496
  %498 = fmul float %125, %468
  %499 = fmul float %126, %473
  %500 = fadd float %498, %499
  %501 = fmul float %127, %478
  %502 = fadd float %500, %501
  %503 = fmul float %128, %483
  %504 = fadd float %502, %503
  %505 = fmul float %181, %284
  %506 = fmul float %186, %289
  %507 = fadd float %506, %505
  %508 = fmul float %185, %294
  %509 = fadd float %507, %508
  %510 = fmul float %181, %376
  %511 = fmul float %186, %381
  %512 = fadd float %511, %510
  %513 = fmul float %185, %386
  %514 = fadd float %512, %513
  %515 = fmul float %181, %468
  %516 = fmul float %186, %473
  %517 = fadd float %516, %515
  %518 = fmul float %185, %478
  %519 = fadd float %517, %518
  br label %ENDIF

ENDIF:                                            ; preds = %main_body, %IF
  %temp.0 = phi float [ %490, %IF ], [ %125, %main_body ]
  %temp1.0 = phi float [ %497, %IF ], [ %126, %main_body ]
  %temp2.0 = phi float [ %504, %IF ], [ %127, %main_body ]
  %temp8.0 = phi float [ %509, %IF ], [ %181, %main_body ]
  %temp9.0 = phi float [ %514, %IF ], [ %186, %main_body ]
  %temp10.0 = phi float [ %519, %IF ], [ %185, %main_body ]
  %temp19.0 = phi float [ %463, %IF ], [ 0.000000e+00, %main_body ]
  %520 = fmul float %temp.0, %12
  %521 = fmul float %temp1.0, %13
  %522 = fadd float %520, %521
  %523 = fmul float %temp2.0, %14
  %524 = fadd float %522, %523
  %525 = fmul float %128, %15
  %526 = fadd float %524, %525
  %527 = fmul float %temp.0, %16
  %528 = fmul float %temp1.0, %17
  %529 = fadd float %527, %528
  %530 = fmul float %temp2.0, %18
  %531 = fadd float %529, %530
  %532 = fmul float %128, %19
  %533 = fadd float %531, %532
  %534 = fmul float %temp.0, %20
  %535 = fmul float %temp1.0, %21
  %536 = fadd float %534, %535
  %537 = fmul float %temp2.0, %22
  %538 = fadd float %536, %537
  %539 = fmul float %128, %23
  %540 = fadd float %538, %539
  %541 = fmul float %temp.0, %24
  %542 = fmul float %temp1.0, %25
  %543 = fadd float %541, %542
  %544 = fmul float %temp2.0, %26
  %545 = fadd float %543, %544
  %546 = fmul float %128, %27
  %547 = fadd float %545, %546
  %548 = fmul float %temp.0, %28
  %549 = fmul float %temp1.0, %29
  %550 = fadd float %548, %549
  %551 = fmul float %temp2.0, %30
  %552 = fadd float %550, %551
  %553 = fmul float %128, %31
  %554 = fadd float %552, %553
  %555 = fmul float %temp.0, %32
  %556 = fmul float %temp1.0, %33
  %557 = fadd float %555, %556
  %558 = fmul float %temp2.0, %34
  %559 = fadd float %557, %558
  %560 = fmul float %128, %35
  %561 = fadd float %559, %560
  %562 = fmul float %temp.0, %36
  %563 = fmul float %temp1.0, %37
  %564 = fadd float %562, %563
  %565 = fmul float %temp2.0, %38
  %566 = fadd float %564, %565
  %567 = fmul float %128, %39
  %568 = fadd float %566, %567
  %569 = fmul float %28, %28
  %570 = fmul float %29, %29
  %571 = fadd float %570, %569
  %572 = fmul float %30, %30
  %573 = fadd float %571, %572
  %574 = fdiv float 1.000000e+00, %573
  %575 = fmul float %28, %574
  %576 = fmul float %29, %574
  %577 = fmul float %30, %574
  %578 = fmul float %temp8.0, %575
  %579 = fmul float %temp9.0, %576
  %580 = fadd float %579, %578
  %581 = fmul float %temp10.0, %577
  %582 = fadd float %580, %581
  %583 = fmul float %32, %32
  %584 = fmul float %33, %33
  %585 = fadd float %584, %583
  %586 = fmul float %34, %34
  %587 = fadd float %585, %586
  %588 = fdiv float 1.000000e+00, %587
  %589 = fmul float %32, %588
  %590 = fmul float %33, %588
  %591 = fmul float %34, %588
  %592 = fmul float %temp8.0, %589
  %593 = fmul float %temp9.0, %590
  %594 = fadd float %593, %592
  %595 = fmul float %temp10.0, %591
  %596 = fadd float %594, %595
  %597 = fmul float %36, %36
  %598 = fmul float %37, %37
  %599 = fadd float %598, %597
  %600 = fmul float %38, %38
  %601 = fadd float %599, %600
  %602 = fdiv float 1.000000e+00, %601
  %603 = fmul float %36, %602
  %604 = fmul float %37, %602
  %605 = fmul float %38, %602
  %606 = fmul float %temp8.0, %603
  %607 = fmul float %temp9.0, %604
  %608 = fadd float %607, %606
  %609 = fmul float %temp10.0, %605
  %610 = fadd float %608, %609
  %611 = fmul float %582, %582
  %612 = fmul float %596, %596
  %613 = fadd float %612, %611
  %614 = fmul float %610, %610
  %615 = fadd float %613, %614
  %616 = call float @llvm.AMDGPU.rsq(float %615)
  %617 = fmul float %582, %616
  %618 = fmul float %596, %616
  %619 = fmul float %610, %616
  %620 = fmul float %617, %617
  %621 = fmul float %618, %618
  %622 = fmul float %619, %619
  %623 = fmul float %617, %619
  %624 = fmul float %619, %618
  %625 = fmul float %618, %617
  %626 = fmul float %51, %617
  %627 = fadd float %626, %48
  %628 = fmul float %52, %617
  %629 = fadd float %628, %49
  %630 = fmul float %53, %617
  %631 = fadd float %630, %50
  %632 = fmul float %54, %618
  %633 = fadd float %632, %627
  %634 = fmul float %55, %618
  %635 = fadd float %634, %629
  %636 = fmul float %56, %618
  %637 = fadd float %636, %631
  %638 = fmul float %57, %619
  %639 = fadd float %638, %633
  %640 = fmul float %58, %619
  %641 = fadd float %640, %635
  %642 = fmul float %59, %619
  %643 = fadd float %642, %637
  %644 = fmul float %60, %623
  %645 = fadd float %644, %639
  %646 = fmul float %61, %623
  %647 = fadd float %646, %641
  %648 = fmul float %62, %623
  %649 = fadd float %648, %643
  %650 = fmul float %63, %624
  %651 = fadd float %650, %645
  %652 = fmul float %64, %624
  %653 = fadd float %652, %647
  %654 = fmul float %65, %624
  %655 = fadd float %654, %649
  %656 = fmul float %66, %625
  %657 = fadd float %656, %651
  %658 = fmul float %67, %625
  %659 = fadd float %658, %653
  %660 = fmul float %68, %625
  %661 = fadd float %660, %655
  %662 = fmul float %622, 3.000000e+00
  %663 = fadd float %662, -1.000000e+00
  %664 = fmul float %69, %663
  %665 = fadd float %664, %657
  %666 = fmul float %70, %663
  %667 = fadd float %666, %659
  %668 = fmul float %71, %663
  %669 = fadd float %668, %661
  %670 = fsub float -0.000000e+00, %621
  %671 = fadd float %620, %670
  %672 = fmul float %72, %671
  %673 = fadd float %672, %665
  %674 = fmul float %73, %671
  %675 = fadd float %674, %667
  %676 = fmul float %74, %671
  %677 = fadd float %676, %669
  %678 = fcmp uge float %673, 0.000000e+00
  %679 = select i1 %678, float %673, float 0.000000e+00
  %680 = fcmp uge float %675, 0.000000e+00
  %681 = select i1 %680, float %675, float 0.000000e+00
  %682 = fcmp uge float %677, 0.000000e+00
  %683 = select i1 %682, float %677, float 0.000000e+00
  %684 = fcmp oge float %108, 0.000000e+00
  %685 = sext i1 %684 to i32
  %686 = bitcast i32 %685 to float
  %687 = bitcast float %686 to i32
  %688 = icmp ne i32 %687, 0
  %. = select i1 %688, float %554, float %153
  %689 = fcmp oge float %108, 0.000000e+00
  %690 = sext i1 %689 to i32
  %691 = bitcast i32 %690 to float
  %692 = bitcast float %691 to i32
  %693 = icmp ne i32 %692, 0
  %temp28.0 = select i1 %693, float %561, float %154
  %694 = fcmp oge float %106, 0.000000e+00
  %695 = sext i1 %694 to i32
  %696 = bitcast i32 %695 to float
  %697 = bitcast float %696 to i32
  %698 = icmp ne i32 %697, 0
  %.. = select i1 %698, float %568, float %.
  %699 = fcmp oge float %107, 0.000000e+00
  %700 = sext i1 %699 to i32
  %701 = bitcast i32 %700 to float
  %702 = bitcast float %701 to i32
  %703 = icmp ne i32 %702, 0
  %temp24.1 = select i1 %703, float %568, float %temp28.0
  %704 = fcmp oge float %111, 0.000000e+00
  %705 = sext i1 %704 to i32
  %706 = bitcast i32 %705 to float
  %707 = bitcast float %706 to i32
  %708 = icmp ne i32 %707, 0
  %.143 = select i1 %708, float %554, float %138
  %709 = fcmp oge float %111, 0.000000e+00
  %710 = sext i1 %709 to i32
  %711 = bitcast i32 %710 to float
  %712 = bitcast float %711 to i32
  %713 = icmp ne i32 %712, 0
  %temp32.1 = select i1 %713, float %561, float %139
  %714 = fcmp oge float %109, 0.000000e+00
  %715 = sext i1 %714 to i32
  %716 = bitcast i32 %715 to float
  %717 = bitcast float %716 to i32
  %718 = icmp ne i32 %717, 0
  %..143 = select i1 %718, float %568, float %.143
  %719 = fcmp oge float %110, 0.000000e+00
  %720 = sext i1 %719 to i32
  %721 = bitcast i32 %720 to float
  %722 = bitcast float %721 to i32
  %723 = icmp ne i32 %722, 0
  %temp28.2 = select i1 %723, float %568, float %temp32.1
  %724 = fcmp oge float %114, 0.000000e+00
  %725 = sext i1 %724 to i32
  %726 = bitcast i32 %725 to float
  %727 = bitcast float %726 to i32
  %728 = icmp ne i32 %727, 0
  %.144 = select i1 %728, float %554, float %158
  %729 = fcmp oge float %114, 0.000000e+00
  %730 = sext i1 %729 to i32
  %731 = bitcast i32 %730 to float
  %732 = bitcast float %731 to i32
  %733 = icmp ne i32 %732, 0
  %temp36.1 = select i1 %733, float %561, float %159
  %734 = fcmp oge float %112, 0.000000e+00
  %735 = sext i1 %734 to i32
  %736 = bitcast i32 %735 to float
  %737 = bitcast float %736 to i32
  %738 = icmp ne i32 %737, 0
  %..144 = select i1 %738, float %568, float %.144
  %739 = fcmp oge float %113, 0.000000e+00
  %740 = sext i1 %739 to i32
  %741 = bitcast i32 %740 to float
  %742 = bitcast float %741 to i32
  %743 = icmp ne i32 %742, 0
  %temp32.3 = select i1 %743, float %568, float %temp36.1
  %744 = fcmp oge float %117, 0.000000e+00
  %745 = sext i1 %744 to i32
  %746 = bitcast i32 %745 to float
  %747 = bitcast float %746 to i32
  %748 = icmp ne i32 %747, 0
  %.145 = select i1 %748, float %554, float %143
  %749 = fcmp oge float %117, 0.000000e+00
  %750 = sext i1 %749 to i32
  %751 = bitcast i32 %750 to float
  %752 = bitcast float %751 to i32
  %753 = icmp ne i32 %752, 0
  %temp40.1 = select i1 %753, float %561, float %144
  %754 = fcmp oge float %115, 0.000000e+00
  %755 = sext i1 %754 to i32
  %756 = bitcast i32 %755 to float
  %757 = bitcast float %756 to i32
  %758 = icmp ne i32 %757, 0
  %..145 = select i1 %758, float %568, float %.145
  %759 = fcmp oge float %116, 0.000000e+00
  %760 = sext i1 %759 to i32
  %761 = bitcast i32 %760 to float
  %762 = bitcast float %761 to i32
  %763 = icmp ne i32 %762, 0
  %temp12.0 = select i1 %763, float %568, float %temp40.1
  %764 = fmul float %148, %99
  %765 = fadd float %764, %101
  %766 = fmul float %149, %100
  %767 = fadd float %766, %102
  %768 = fmul float %.., %91
  %769 = fmul float %temp24.1, %92
  %770 = fadd float %768, %769
  %771 = fmul float 0.000000e+00, %93
  %772 = fadd float %770, %771
  %773 = fmul float 1.000000e+00, %94
  %774 = fadd float %772, %773
  %775 = fmul float %.., %95
  %776 = fmul float %temp24.1, %96
  %777 = fadd float %775, %776
  %778 = fmul float 0.000000e+00, %97
  %779 = fadd float %777, %778
  %780 = fmul float 1.000000e+00, %98
  %781 = fadd float %779, %780
  %782 = fmul float %..143, %40
  %783 = fmul float %temp28.2, %41
  %784 = fadd float %782, %783
  %785 = fmul float 0.000000e+00, %42
  %786 = fadd float %784, %785
  %787 = fmul float 1.000000e+00, %43
  %788 = fadd float %786, %787
  %789 = fmul float %..143, %44
  %790 = fmul float %temp28.2, %45
  %791 = fadd float %789, %790
  %792 = fmul float 0.000000e+00, %46
  %793 = fadd float %791, %792
  %794 = fmul float 1.000000e+00, %47
  %795 = fadd float %793, %794
  %796 = fmul float %..144, %83
  %797 = fmul float %temp32.3, %84
  %798 = fadd float %796, %797
  %799 = fmul float 0.000000e+00, %85
  %800 = fadd float %798, %799
  %801 = fmul float 1.000000e+00, %86
  %802 = fadd float %800, %801
  %803 = fmul float %..144, %87
  %804 = fmul float %temp32.3, %88
  %805 = fadd float %803, %804
  %806 = fmul float 0.000000e+00, %89
  %807 = fadd float %805, %806
  %808 = fmul float 1.000000e+00, %90
  %809 = fadd float %807, %808
  %810 = fmul float %..145, %75
  %811 = fmul float %temp12.0, %76
  %812 = fadd float %810, %811
  %813 = fmul float 0.000000e+00, %77
  %814 = fadd float %812, %813
  %815 = fmul float 1.000000e+00, %78
  %816 = fadd float %814, %815
  %817 = fmul float %..145, %79
  %818 = fmul float %temp12.0, %80
  %819 = fadd float %817, %818
  %820 = fmul float 0.000000e+00, %81
  %821 = fadd float %819, %820
  %822 = fmul float 1.000000e+00, %82
  %823 = fadd float %821, %822
  %824 = fmul float %165, %103
  %825 = fadd float %824, %105
  %826 = fmul float %164, %103
  %827 = fadd float %826, %105
  %828 = fmul float %163, %103
  %829 = fadd float %828, %105
  %830 = fmul float %166, %104
  %831 = fadd float %830, %105
  %832 = fmul float %825, %825
  %833 = fmul float %827, %827
  %834 = fmul float %829, %829
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %554, float %561, float %568, float 1.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %788, float %795, float %802, float %809)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %765, float %767, float %774, float %781)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %816, float %823, float 0.000000e+00, float 0.000000e+00)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 36, i32 0, float %832, float %833, float %834, float %831)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 37, i32 0, float %617, float %618, float %619, float %679)
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 38, i32 0, float %681, float %683, float %683, float %temp19.0)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %526, float %533, float %540, float %547)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDGPU.rsq(float) #2

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }
attributes #2 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Frame Objects:
  fi#0: size=4, align=4, at location [SP]
  fi#1: size=4, align=4, at location [SP+4]
  fi#2: size=4, align=4, at location [SP+8]
  fi#3: size=4, align=4, at location [SP+12]
  fi#4: size=4, align=4, at location [SP+16]
  fi#5: size=4, align=4, at location [SP+20]
  fi#6: size=4, align=4, at location [SP+24]
  fi#7: size=4, align=4, at location [SP+28]
  fi#8: size=4, align=4, at location [SP+32]
  fi#9: size=4, align=4, at location [SP+36]
  fi#10: size=4, align=4, at location [SP+40]
Function Live Ins: %SGPR0_SGPR1 in %vreg135, %SGPR6_SGPR7 in %vreg138, %VGPR0 in %vreg141

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
    Successors according to CFG: BB#1(16) BB#2(16)

BB#1: derived from LLVM BB %IF
    Live Ins: %SGPR68_SGPR69_SGPR70_SGPR71 %VGPR33 %VGPR34 %VGPR28 %VGPR24 %VGPR35 %VGPR36 %VGPR29 %VGPR25 %VGPR37 %VGPR38 %VGPR30 %VGPR26 %VGPR39 %VGPR40 %VGPR31 %VGPR27 %SGPR55 %SGPR56 %SGPR53 %VGPR57 %SGPR60 %SGPR61 %SGPR57 %VGPR58 %SGPR32 %SGPR33 %SGPR31 %VGPR59 %VGPR50 %VGPR32 %VGPR45 %VGPR54 %VGPR55 %VGPR52 %VGPR53 %SGPR24 %VGPR51 %SGPR25 %VGPR41_VGPR42_VGPR43_VGPR44 %VGPR11_VGPR12_VGPR13_VGPR14 %VGPR15_VGPR16_VGPR17_VGPR18 %VGPR19_VGPR20_VGPR21_VGPR22 %VGPR46_VGPR47_VGPR48_VGPR49 %VGPR6_VGPR7_VGPR8_VGPR9 %SGPR6_SGPR7 %VGPR0 %VGPR1_VGPR2_VGPR3_VGPR4 %SGPR30 %SGPR27 %SGPR29 %SGPR64 %SGPR62 %SGPR63 %SGPR59 %SGPR54 %SGPR58 %SGPR46 %SGPR36 %SGPR45 %SGPR43 %SGPR47 %SGPR49 %SGPR50 %SGPR44 %SGPR48 %SGPR51 %SGPR52 %SGPR65 %SGPR67 %SGPR73 %SGPR74 %SGPR66 %SGPR72 %SGPR75 %SGPR76 %SGPR34 %SGPR37 %SGPR39 %SGPR40 %SGPR35 %SGPR38 %SGPR41 %SGPR42 %SGPR13 %SGPR17 %SGPR20 %SGPR21 %SGPR14 %SGPR22 %SGPR16 %SGPR23 %SGPR18 %SGPR26 %SGPR19 %SGPR15 %SGPR28 %SGPR77 %SGPR79 %SGPR81 %SGPR82 %SGPR78 %SGPR80 %SGPR83 %SGPR84 %SGPR86_SGPR87 %VGPR5 %VGPR23 %VGPR10 %VGPR86 %VGPR87 %VGPR88 %VGPR89 %VGPR90 %VGPR91 %VGPR92 %VGPR93 %VGPR94 %VGPR95 %VGPR96
    Predecessors according to CFG: BB#0
    Successors according to CFG: BB#2

BB#2: derived from LLVM BB %ENDIF
    Live Ins: %VGPR33 %VGPR34 %VGPR28 %VGPR24 %VGPR35 %VGPR36 %VGPR29 %VGPR25 %VGPR37 %VGPR38 %VGPR30 %VGPR26 %VGPR39 %VGPR40 %VGPR31 %VGPR27 %SGPR55 %SGPR56 %SGPR53 %VGPR57 %SGPR60 %SGPR61 %SGPR57 %VGPR58 %SGPR32 %SGPR33 %SGPR31 %VGPR59 %VGPR50 %VGPR32 %VGPR45 %VGPR54 %VGPR55 %VGPR52 %VGPR53 %SGPR24 %VGPR51 %SGPR25 %VGPR41_VGPR42_VGPR43_VGPR44 %VGPR11_VGPR12_VGPR13_VGPR14 %VGPR15_VGPR16_VGPR17_VGPR18 %VGPR19_VGPR20_VGPR21_VGPR22 %VGPR46_VGPR47_VGPR48_VGPR49 %VGPR6_VGPR7_VGPR8_VGPR9 %VGPR1_VGPR2_VGPR3_VGPR4 %SGPR30 %SGPR27 %SGPR29 %SGPR64 %SGPR62 %SGPR63 %SGPR59 %SGPR54 %SGPR58 %SGPR46 %SGPR36 %SGPR45 %SGPR43 %SGPR47 %SGPR49 %SGPR50 %SGPR44 %SGPR48 %SGPR51 %SGPR52 %SGPR65 %SGPR67 %SGPR73 %SGPR74 %SGPR66 %SGPR72 %SGPR75 %SGPR76 %SGPR34 %SGPR37 %SGPR39 %SGPR40 %SGPR35 %SGPR38 %SGPR41 %SGPR42 %SGPR13 %SGPR17 %SGPR20 %SGPR21 %SGPR14 %SGPR22 %SGPR16 %SGPR23 %SGPR18 %SGPR26 %SGPR19 %SGPR15 %SGPR28 %SGPR77 %SGPR79 %SGPR81 %SGPR82 %SGPR78 %SGPR80 %SGPR83 %SGPR84 %SGPR86_SGPR87 %VGPR62 %VGPR61 %VGPR60 %VGPR5 %VGPR23 %VGPR10 %VGPR56 %VGPR86 %VGPR87 %VGPR88 %VGPR89 %VGPR90 %VGPR91 %VGPR92 %VGPR93 %VGPR94 %VGPR95 %VGPR96
    Predecessors according to CFG: BB#0 BB#1
	EXP 0, 9, 0, 1, 1, %VGPR0, %VGPR0, %VGPR0, %VGPR0, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	EXP 0, 9, 0, 1, 1, v0, v0, v0, v0 ; F8001890 00000000
	S_ENDPGM                          ; BF810000

FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL SAMP[1]
DCL CONST[0..3]
DCL TEMP[0..2], LOCAL
IMM[0] FLT32 {   -0.5000,     0.5000,     1.0000,    -5.0000}
IMM[1] FLT32 {    5.0000,     0.1000,     0.0000,     0.0000}
  0: MAD TEMP[0], CONST[0].xyxy, IMM[0].xxyy, IN[0].zwzw
  1: MOV TEMP[1].xy, TEMP[0].xyyy
  2: TEX TEMP[1].x, TEMP[1], SAMP[1], 2D
  3: MOV TEMP[1].x, TEMP[1].xxxx
  4: MOV TEMP[2].xy, TEMP[0].zyyy
  5: TEX TEMP[2].x, TEMP[2], SAMP[1], 2D
  6: MOV TEMP[1].y, TEMP[2].xxxx
  7: MOV TEMP[2].xy, TEMP[0].xwww
  8: TEX TEMP[2].x, TEMP[2], SAMP[1], 2D
  9: MOV TEMP[1].z, TEMP[2].xxxx
 10: MOV TEMP[0].xy, TEMP[0].zwww
 11: TEX TEMP[0].x, TEMP[0], SAMP[1], 2D
 12: MOV TEMP[1].w, TEMP[0].xxxx
 13: ABS TEMP[0], TEMP[1]
 14: MAD TEMP[0], TEMP[0], CONST[3].yyyy, -CONST[3].xxxx
 15: RCP TEMP[1].x, TEMP[0].xxxx
 16: RCP TEMP[1].y, TEMP[0].yyyy
 17: RCP TEMP[1].z, TEMP[0].zzzz
 18: RCP TEMP[1].w, TEMP[0].wwww
 19: MUL TEMP[0], CONST[1].xxxx, TEMP[1]
 20: ADD TEMP[0], IMM[0].zzzz, -TEMP[0]
 21: MUL TEMP[0], CONST[1].yyyy, TEMP[0]
 22: MAX TEMP[0], TEMP[0], IMM[0].wwww
 23: MIN TEMP[0], TEMP[0], IMM[1].xxxx
 24: MAX TEMP[0].xy, TEMP[0].xyyy, TEMP[0].zwww
 25: MOV TEMP[1].xy, IN[0].xyyy
 26: TEX TEMP[1].xyz, TEMP[1], SAMP[0], 2D
 27: MOV TEMP[1].xyz, TEMP[1].xyzx
 28: MAX TEMP[0].x, TEMP[0].xxxx, TEMP[0].yyyy
 29: MAD_SAT TEMP[0].x, IMM[1].yyyy, TEMP[0].xxxx, IMM[0].yyyy
 30: MOV TEMP[1].w, TEMP[0].xxxx
 31: MOV OUT[0], TEMP[1]
 32: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %21 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
  %22 = load <16 x i8> addrspace(2)* %21, !tbaa !0
  %23 = call float @llvm.SI.load.const(<16 x i8> %22, i32 0)
  %24 = call float @llvm.SI.load.const(<16 x i8> %22, i32 4)
  %25 = call float @llvm.SI.load.const(<16 x i8> %22, i32 16)
  %26 = call float @llvm.SI.load.const(<16 x i8> %22, i32 20)
  %27 = call float @llvm.SI.load.const(<16 x i8> %22, i32 48)
  %28 = call float @llvm.SI.load.const(<16 x i8> %22, i32 52)
  %29 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0
  %30 = load <32 x i8> addrspace(2)* %29, !tbaa !0
  %31 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0
  %32 = load <16 x i8> addrspace(2)* %31, !tbaa !0
  %33 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 1
  %34 = load <32 x i8> addrspace(2)* %33, !tbaa !0
  %35 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 1
  %36 = load <16 x i8> addrspace(2)* %35, !tbaa !0
  %37 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %4, <2 x i32> %6)
  %38 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %4, <2 x i32> %6)
  %39 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %4, <2 x i32> %6)
  %40 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %4, <2 x i32> %6)
  %41 = fmul float %23, -5.000000e-01
  %42 = fadd float %41, %39
  %43 = fmul float %24, -5.000000e-01
  %44 = fadd float %43, %40
  %45 = fmul float %23, 5.000000e-01
  %46 = fadd float %45, %39
  %47 = fmul float %24, 5.000000e-01
  %48 = fadd float %47, %40
  %49 = bitcast float %42 to i32
  %50 = bitcast float %44 to i32
  %51 = insertelement <2 x i32> undef, i32 %49, i32 0
  %52 = insertelement <2 x i32> %51, i32 %50, i32 1
  %53 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %52, <32 x i8> %34, <16 x i8> %36, i32 2)
  %54 = extractelement <4 x float> %53, i32 0
  %55 = bitcast float %46 to i32
  %56 = bitcast float %44 to i32
  %57 = insertelement <2 x i32> undef, i32 %55, i32 0
  %58 = insertelement <2 x i32> %57, i32 %56, i32 1
  %59 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %58, <32 x i8> %34, <16 x i8> %36, i32 2)
  %60 = extractelement <4 x float> %59, i32 0
  %61 = bitcast float %42 to i32
  %62 = bitcast float %48 to i32
  %63 = insertelement <2 x i32> undef, i32 %61, i32 0
  %64 = insertelement <2 x i32> %63, i32 %62, i32 1
  %65 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %64, <32 x i8> %34, <16 x i8> %36, i32 2)
  %66 = extractelement <4 x float> %65, i32 0
  %67 = bitcast float %46 to i32
  %68 = bitcast float %48 to i32
  %69 = insertelement <2 x i32> undef, i32 %67, i32 0
  %70 = insertelement <2 x i32> %69, i32 %68, i32 1
  %71 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %70, <32 x i8> %34, <16 x i8> %36, i32 2)
  %72 = extractelement <4 x float> %71, i32 0
  %73 = call float @fabs(float %54)
  %74 = call float @fabs(float %60)
  %75 = call float @fabs(float %66)
  %76 = call float @fabs(float %72)
  %77 = fsub float -0.000000e+00, %27
  %78 = fmul float %73, %28
  %79 = fadd float %78, %77
  %80 = fsub float -0.000000e+00, %27
  %81 = fmul float %74, %28
  %82 = fadd float %81, %80
  %83 = fsub float -0.000000e+00, %27
  %84 = fmul float %75, %28
  %85 = fadd float %84, %83
  %86 = fsub float -0.000000e+00, %27
  %87 = fmul float %76, %28
  %88 = fadd float %87, %86
  %89 = fdiv float 1.000000e+00, %79
  %90 = fdiv float 1.000000e+00, %82
  %91 = fdiv float 1.000000e+00, %85
  %92 = fdiv float 1.000000e+00, %88
  %93 = fmul float %25, %89
  %94 = fmul float %25, %90
  %95 = fmul float %25, %91
  %96 = fmul float %25, %92
  %97 = fsub float -0.000000e+00, %93
  %98 = fadd float 1.000000e+00, %97
  %99 = fsub float -0.000000e+00, %94
  %100 = fadd float 1.000000e+00, %99
  %101 = fsub float -0.000000e+00, %95
  %102 = fadd float 1.000000e+00, %101
  %103 = fsub float -0.000000e+00, %96
  %104 = fadd float 1.000000e+00, %103
  %105 = fmul float %26, %98
  %106 = fmul float %26, %100
  %107 = fmul float %26, %102
  %108 = fmul float %26, %104
  %109 = fcmp uge float %105, -5.000000e+00
  %110 = select i1 %109, float %105, float -5.000000e+00
  %111 = fcmp uge float %106, -5.000000e+00
  %112 = select i1 %111, float %106, float -5.000000e+00
  %113 = fcmp uge float %107, -5.000000e+00
  %114 = select i1 %113, float %107, float -5.000000e+00
  %115 = fcmp uge float %108, -5.000000e+00
  %116 = select i1 %115, float %108, float -5.000000e+00
  %117 = fcmp uge float %110, 5.000000e+00
  %118 = select i1 %117, float 5.000000e+00, float %110
  %119 = fcmp uge float %112, 5.000000e+00
  %120 = select i1 %119, float 5.000000e+00, float %112
  %121 = fcmp uge float %114, 5.000000e+00
  %122 = select i1 %121, float 5.000000e+00, float %114
  %123 = fcmp uge float %116, 5.000000e+00
  %124 = select i1 %123, float 5.000000e+00, float %116
  %125 = fcmp uge float %118, %122
  %126 = select i1 %125, float %118, float %122
  %127 = fcmp uge float %120, %124
  %128 = select i1 %127, float %120, float %124
  %129 = bitcast float %37 to i32
  %130 = bitcast float %38 to i32
  %131 = insertelement <2 x i32> undef, i32 %129, i32 0
  %132 = insertelement <2 x i32> %131, i32 %130, i32 1
  %133 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %132, <32 x i8> %30, <16 x i8> %32, i32 2)
  %134 = extractelement <4 x float> %133, i32 0
  %135 = extractelement <4 x float> %133, i32 1
  %136 = extractelement <4 x float> %133, i32 2
  %137 = fcmp uge float %126, %128
  %138 = select i1 %137, float %126, float %128
  %139 = fmul float 0x3FB99999A0000000, %138
  %140 = fadd float %139, 5.000000e-01
  %141 = call float @llvm.AMDIL.clamp.(float %140, float 0.000000e+00, float 1.000000e+00)
  %142 = call i32 @llvm.SI.packf16(float %134, float %135)
  %143 = bitcast i32 %142 to float
  %144 = call i32 @llvm.SI.packf16(float %136, float %141)
  %145 = bitcast i32 %144 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %143, float %145, float %143, float %145)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readonly
declare float @fabs(float) #2

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #3

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readonly }
attributes #3 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR7 in %vreg4, %VGPR0 in %vreg5, %VGPR1 in %vreg6

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR7 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR7
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 3, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<kill,tied0>, %VGPR1, 3, 0, %M0<kill>, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%22](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 1; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR4<def> = V_MAD_F32 %SGPR0, 5.000000e-01, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR3_VGPR4<imp-def>
	%VGPR5<def> = V_INTERP_P1_F32 %VGPR0, 2, 0, %M0<kill>, %EXEC<imp-use>
	%VGPR5<def,tied1> = V_INTERP_P2_F32 %VGPR5<kill,tied0>, %VGPR1, 2, 0, %M0<kill>, %EXEC<imp-use>
	%SGPR1<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 0; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR3<def> = V_MAD_F32 %SGPR1, 5.000000e-01, %VGPR5, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR3_VGPR4<imp-use,kill>, %VGPR3_VGPR4<imp-def>
	%SGPR12_SGPR13_SGPR14_SGPR15<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 4; mem:LD16[%40](align=8)(tbaa=!"const")
	%SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 8; mem:LD32[%37](tbaa=!"const")
	S_WAITCNT 127
	%VGPR6<def> = IMAGE_SAMPLE_V1_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR3_VGPR4, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23, %SGPR12_SGPR13_SGPR14_SGPR15, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR6<def> = V_ADD_F32_e64 %VGPR6<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR6<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 13; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR6, %VGPR6<kill>, %EXEC<imp-use>
	%SGPR24<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 12; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_SUBREV_F32_e32 %SGPR24, %VGPR6<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_RCP_F32_e32 %VGPR6<kill>, %EXEC<imp-use>
	%SGPR25<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 4; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR25, %VGPR6<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_SUB_F32_e32 1.000000e+00, %VGPR6<kill>, %EXEC<imp-use>
	%SGPR8<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11<kill>, 5; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MUL_F32_e32 %SGPR8, %VGPR6<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MOV_B32_e32 -5.000000e+00, %EXEC<imp-use>
	%SGPR10_SGPR11<def> = V_CMP_GE_F32_e64 %VGPR6, %VGPR7, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR26_SGPR27<def> = V_CMP_U_F32_e64 %VGPR6, %VGPR6, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR10_SGPR11<def> = S_OR_B64 %SGPR10_SGPR11<kill>, %SGPR26_SGPR27<kill>
	%VGPR6<def> = V_CNDMASK_B32_e64 %VGPR7, %VGPR6<kill>, %SGPR10_SGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR8<def> = V_MOV_B32_e32 5.000000e+00, %EXEC<imp-use>
	%SGPR10_SGPR11<def> = V_CMP_GE_F32_e64 %VGPR6, %VGPR8, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR26_SGPR27<def> = V_CMP_U_F32_e64 %VGPR6, %VGPR6, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR10_SGPR11<def> = S_OR_B64 %SGPR10_SGPR11<kill>, %SGPR26_SGPR27<kill>
	%VGPR6<def> = V_CNDMASK_B32_e64 %VGPR6<kill>, %VGPR8, %SGPR10_SGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR2<def> = V_MAD_F32 %SGPR0<kill>, -5.000000e-01, %VGPR2<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_MOV_B32_e32 %VGPR3, %EXEC<imp-use>, %VGPR9_VGPR10<imp-def>
	%VGPR10<def> = V_MOV_B32_e32 %VGPR4, %EXEC<imp-use>
	%VGPR10<def> = V_MOV_B32_e32 %VGPR2, %EXEC<imp-use>, %VGPR9_VGPR10<imp-def>
	%VGPR9<def> = IMAGE_SAMPLE_V1_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR9_VGPR10<kill>, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23, %SGPR12_SGPR13_SGPR14_SGPR15, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR9<def> = V_ADD_F32_e64 %VGPR9<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%VGPR9<def> = V_MUL_F32_e32 %SGPR6, %VGPR9<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_SUBREV_F32_e32 %SGPR24, %VGPR9<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_RCP_F32_e32 %VGPR9<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_MUL_F32_e32 %SGPR25, %VGPR9<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_SUB_F32_e32 1.000000e+00, %VGPR9<kill>, %EXEC<imp-use>
	%VGPR9<def> = V_MUL_F32_e32 %SGPR8, %VGPR9<kill>, %EXEC<imp-use>
	%SGPR10_SGPR11<def> = V_CMP_GE_F32_e64 %VGPR9, %VGPR7, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR26_SGPR27<def> = V_CMP_U_F32_e64 %VGPR9, %VGPR9, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR10_SGPR11<def> = S_OR_B64 %SGPR10_SGPR11<kill>, %SGPR26_SGPR27<kill>
	%VGPR9<def> = V_CNDMASK_B32_e64 %VGPR7, %VGPR9<kill>, %SGPR10_SGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR10_SGPR11<def> = V_CMP_GE_F32_e64 %VGPR9, %VGPR8, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR26_SGPR27<def> = V_CMP_U_F32_e64 %VGPR9, %VGPR9, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR10_SGPR11<def> = S_OR_B64 %SGPR10_SGPR11<kill>, %SGPR26_SGPR27<kill>
	%VGPR9<def> = V_CNDMASK_B32_e64 %VGPR9<kill>, %VGPR8, %SGPR10_SGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR10_SGPR11<def> = V_CMP_U_F32_e64 %VGPR9, %VGPR6, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR26_SGPR27<def> = V_CMP_GE_F32_e64 %VGPR9, %VGPR6, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR10_SGPR11<def> = S_OR_B64 %SGPR26_SGPR27<kill>, %SGPR10_SGPR11<kill>
	%VGPR6<def> = V_CNDMASK_B32_e64 %VGPR6<kill>, %VGPR9<kill>, %SGPR10_SGPR11<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_MAD_F32 %SGPR1<kill>, -5.000000e-01, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR3_VGPR4<imp-use,kill>, %VGPR3_VGPR4<imp-def>
	%VGPR5<def> = IMAGE_SAMPLE_V1_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR3_VGPR4, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23, %SGPR12_SGPR13_SGPR14_SGPR15, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR5<def> = V_ADD_F32_e64 %VGPR5<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%VGPR5<def> = V_MUL_F32_e32 %SGPR6, %VGPR5<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_SUBREV_F32_e32 %SGPR24, %VGPR5<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_RCP_F32_e32 %VGPR5<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MUL_F32_e32 %SGPR25, %VGPR5<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_SUB_F32_e32 1.000000e+00, %VGPR5<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MUL_F32_e32 %SGPR8, %VGPR5<kill>, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = V_CMP_GE_F32_e64 %VGPR5, %VGPR7, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR10_SGPR11<def> = V_CMP_U_F32_e64 %VGPR5, %VGPR5, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_OR_B64 %SGPR0_SGPR1<kill>, %SGPR10_SGPR11<kill>
	%VGPR5<def> = V_CNDMASK_B32_e64 %VGPR7, %VGPR5<kill>, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = V_CMP_GE_F32_e64 %VGPR5, %VGPR8, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR10_SGPR11<def> = V_CMP_U_F32_e64 %VGPR5, %VGPR5, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_OR_B64 %SGPR0_SGPR1<kill>, %SGPR10_SGPR11<kill>
	%VGPR5<def> = V_CNDMASK_B32_e64 %VGPR5<kill>, %VGPR8, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_MOV_B32_e32 %VGPR2<kill>, %EXEC<imp-use>, %VGPR3_VGPR4<imp-def>
	%VGPR2<def> = IMAGE_SAMPLE_V1_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR3_VGPR4<kill>, %SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23<kill>, %SGPR12_SGPR13_SGPR14_SGPR15<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR2<def> = V_ADD_F32_e64 %VGPR2<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%VGPR2<def> = V_MUL_F32_e32 %SGPR6<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_SUBREV_F32_e32 %SGPR24<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_RCP_F32_e32 %VGPR2<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_MUL_F32_e32 %SGPR25<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_SUB_F32_e32 1.000000e+00, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_MUL_F32_e32 %SGPR8<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = V_CMP_GE_F32_e64 %VGPR2, %VGPR7, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8_SGPR9<def> = V_CMP_U_F32_e64 %VGPR2, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_OR_B64 %SGPR0_SGPR1<kill>, %SGPR8_SGPR9<kill>
	%VGPR2<def> = V_CNDMASK_B32_e64 %VGPR7<kill>, %VGPR2<kill>, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = V_CMP_GE_F32_e64 %VGPR2, %VGPR8, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8_SGPR9<def> = V_CMP_U_F32_e64 %VGPR2, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_OR_B64 %SGPR0_SGPR1<kill>, %SGPR8_SGPR9<kill>
	%VGPR2<def> = V_CNDMASK_B32_e64 %VGPR2<kill>, %VGPR8<kill>, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = V_CMP_U_F32_e64 %VGPR2, %VGPR5, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8_SGPR9<def> = V_CMP_GE_F32_e64 %VGPR2, %VGPR5, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_OR_B64 %SGPR8_SGPR9<kill>, %SGPR0_SGPR1<kill>
	%VGPR2<def> = V_CNDMASK_B32_e64 %VGPR5<kill>, %VGPR2<kill>, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = V_CMP_U_F32_e64 %VGPR2, %VGPR6, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8_SGPR9<def> = V_CMP_GE_F32_e64 %VGPR2, %VGPR6, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_OR_B64 %SGPR8_SGPR9<kill>, %SGPR0_SGPR1<kill>
	%VGPR2<def> = V_CNDMASK_B32_e64 %VGPR6<kill>, %VGPR2<kill>, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_MOV_B32_e32 1.000000e-01, %EXEC<imp-use>
	%VGPR2<def> = V_MAD_F32 %VGPR2<kill>, %VGPR3<kill>, 5.000000e-01, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR2<def> = V_ADD_F32_e64 0, %VGPR2<kill>, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR3_VGPR4<imp-def>
	%VGPR4<def,tied1> = V_INTERP_P2_F32 %VGPR4<tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR3_VGPR4<imp-use,kill>, %VGPR3_VGPR4<imp-def>
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR3_VGPR4<imp-use,kill>, %VGPR3_VGPR4<imp-def>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR3_VGPR4<imp-use,kill>, %VGPR3_VGPR4<imp-def>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%34](align=8)(tbaa=!"const")
	%SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%31](tbaa=!"const")
	S_WAITCNT 127
	%VGPR3_VGPR4_VGPR5<def> = IMAGE_SAMPLE_V3_V2 7, 0, 0, 0, 0, 0, 0, 0, %VGPR3_VGPR4<kill>, %SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<kill>, %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR5, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR3, %VGPR4, %EXEC<imp-use>, %VGPR3_VGPR4_VGPR5<imp-use,kill>
	EXP 15, 0, 1, 1, 1, %VGPR1<kill>, %VGPR0<kill>, %VGPR1, %VGPR0, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_WQM_B64 exec, exec                                                 ; BEFE0A7E
	S_MOV_B32 m0, s7                                                     ; BEFC0307
	V_INTERP_P1_F32 v2, v0, 3, 0, [m0]                                   ; C8080300
	V_INTERP_P2_F32 v2, [v2], v1, 3, 0, [m0]                             ; C8090301
	S_LOAD_DWORDX4 s[8:11], s[0:1], 0                                    ; C0840100
	S_WAITCNT lgkmcnt(0)                                                 ; BF8C007F
	S_BUFFER_LOAD_DWORD s0, s[8:11], 1                                   ; C2000901
	S_WAITCNT lgkmcnt(0)                                                 ; BF8C007F
	V_MAD_F32 v4, s0, 5.000000e-01, v2, 0, 0, 0, 0                       ; D2820004 0409E000
	V_INTERP_P1_F32 v5, v0, 2, 0, [m0]                                   ; C8140200
	V_INTERP_P2_F32 v5, [v5], v1, 2, 0, [m0]                             ; C8150201
	S_BUFFER_LOAD_DWORD s1, s[8:11], 0                                   ; C2008900
	S_WAITCNT lgkmcnt(0)                                                 ; BF8C007F
	V_MAD_F32 v3, s1, 5.000000e-01, v5, 0, 0, 0, 0                       ; D2820003 0415E001
	S_LOAD_DWORDX4 s[12:15], s[2:3], 4                                   ; C0860304
	S_LOAD_DWORDX8 s[16:23], s[4:5], 8                                   ; C0C80508
	S_WAITCNT lgkmcnt(0)                                                 ; BF8C007F
	IMAGE_SAMPLE v6, 1, 0, 0, 0, 0, 0, 0, 0, v[3:4], s[16:23], s[12:15]  ; F0800100 00640603
	S_WAITCNT vmcnt(0)                                                   ; BF8C0770
	V_ADD_F32_e64 v6, v6, 0, 1, 0, 0, 0                                  ; D2060106 02010106
	S_BUFFER_LOAD_DWORD s6, s[8:11], 13                                  ; C203090D
	S_WAITCNT lgkmcnt(0)                                                 ; BF8C007F
	V_MUL_F32_e32 v6, s6, v6                                             ; 100C0C06
	S_BUFFER_LOAD_DWORD s24, s[8:11], 12                                 ; C20C090C
	S_WAITCNT lgkmcnt(0)                                                 ; BF8C007F
	V_SUBREV_F32_e32 v6, s24, v6                                         ; 0A0C0C18
	V_RCP_F32_e32 v6, v6                                                 ; 7E0C5506
	S_BUFFER_LOAD_DWORD s25, s[8:11], 4                                  ; C20C8904
	S_WAITCNT lgkmcnt(0)                                                 ; BF8C007F
	V_MUL_F32_e32 v6, s25, v6                                            ; 100C0C19
	V_SUB_F32_e32 v6, 1.000000e+00, v6                                   ; 080C0CF2
	S_BUFFER_LOAD_DWORD s8, s[8:11], 5                                   ; C2040905
	S_WAITCNT lgkmcnt(0)                                                 ; BF8C007F
	V_MUL_F32_e32 v6, s8, v6                                             ; 100C0C08
	V_MOV_B32_e32 v7, -5.000000e+00                                      ; 7E0E02FF C0A00000
	V_CMP_GE_F32_e64 s[10:11], v6, v7, 0, 0, 0, 0                        ; D00C000A 02020F06
	V_CMP_U_F32_e64 s[26:27], v6, v6, 0, 0, 0, 0                         ; D010001A 02020D06
	S_OR_B64 s[10:11], s[10:11], s[26:27]                                ; 888A1A0A
	V_CNDMASK_B32_e64 v6, v7, v6, s[10:11], 0, 0, 0, 0                   ; D2000006 002A0D07
	V_MOV_B32_e32 v8, 5.000000e+00                                       ; 7E1002FF 40A00000
	V_CMP_GE_F32_e64 s[10:11], v6, v8, 0, 0, 0, 0                        ; D00C000A 02021106
	V_CMP_U_F32_e64 s[26:27], v6, v6, 0, 0, 0, 0                         ; D010001A 02020D06
	S_OR_B64 s[10:11], s[10:11], s[26:27]                                ; 888A1A0A
	V_CNDMASK_B32_e64 v6, v6, v8, s[10:11], 0, 0, 0, 0                   ; D2000006 002A1106
	V_MAD_F32 v2, s0, -5.000000e-01, v2, 0, 0, 0, 0                      ; D2820002 0409E200
	V_MOV_B32_e32 v9, v3                                                 ; 7E120303
	V_MOV_B32_e32 v10, v4                                                ; 7E140304
	V_MOV_B32_e32 v10, v2                                                ; 7E140302
	IMAGE_SAMPLE v9, 1, 0, 0, 0, 0, 0, 0, 0, v[9:10], s[16:23], s[12:15] ; F0800100 00640909
	S_WAITCNT vmcnt(0)                                                   ; BF8C0770
	V_ADD_F32_e64 v9, v9, 0, 1, 0, 0, 0                                  ; D2060109 02010109
	V_MUL_F32_e32 v9, s6, v9                                             ; 10121206
	V_SUBREV_F32_e32 v9, s24, v9                                         ; 0A121218
	V_RCP_F32_e32 v9, v9                                                 ; 7E125509
	V_MUL_F32_e32 v9, s25, v9                                            ; 10121219
	V_SUB_F32_e32 v9, 1.000000e+00, v9                                   ; 081212F2
	V_MUL_F32_e32 v9, s8, v9                                             ; 10121208
	V_CMP_GE_F32_e64 s[10:11], v9, v7, 0, 0, 0, 0                        ; D00C000A 02020F09
	V_CMP_U_F32_e64 s[26:27], v9, v9, 0, 0, 0, 0                         ; D010001A 02021309
	S_OR_B64 s[10:11], s[10:11], s[26:27]                                ; 888A1A0A
	V_CNDMASK_B32_e64 v9, v7, v9, s[10:11], 0, 0, 0, 0                   ; D2000009 002A1307
	V_CMP_GE_F32_e64 s[10:11], v9, v8, 0, 0, 0, 0                        ; D00C000A 02021109
	V_CMP_U_F32_e64 s[26:27], v9, v9, 0, 0, 0, 0                         ; D010001A 02021309
	S_OR_B64 s[10:11], s[10:11], s[26:27]                                ; 888A1A0A
	V_CNDMASK_B32_e64 v9, v9, v8, s[10:11], 0, 0, 0, 0                   ; D2000009 002A1109
	V_CMP_U_F32_e64 s[10:11], v9, v6, 0, 0, 0, 0                         ; D010000A 02020D09
	V_CMP_GE_F32_e64 s[26:27], v9, v6, 0, 0, 0, 0                        ; D00C001A 02020D09
	S_OR_B64 s[10:11], s[26:27], s[10:11]                                ; 888A0A1A
	V_CNDMASK_B32_e64 v6, v6, v9, s[10:11], 0, 0, 0, 0                   ; D2000006 002A1306
	V_MAD_F32 v3, s1, -5.000000e-01, v5, 0, 0, 0, 0                      ; D2820003 0415E201
	IMAGE_SAMPLE v5, 1, 0, 0, 0, 0, 0, 0, 0, v[3:4], s[16:23], s[12:15]  ; F0800100 00640503
	S_WAITCNT vmcnt(0)                                                   ; BF8C0770
	V_ADD_F32_e64 v5, v5, 0, 1, 0, 0, 0                                  ; D2060105 02010105
	V_MUL_F32_e32 v5, s6, v5                                             ; 100A0A06
	V_SUBREV_F32_e32 v5, s24, v5                                         ; 0A0A0A18
	V_RCP_F32_e32 v5, v5                                                 ; 7E0A5505
	V_MUL_F32_e32 v5, s25, v5                                            ; 100A0A19
	V_SUB_F32_e32 v5, 1.000000e+00, v5                                   ; 080A0AF2
	V_MUL_F32_e32 v5, s8, v5                                             ; 100A0A08
	V_CMP_GE_F32_e64 s[0:1], v5, v7, 0, 0, 0, 0                          ; D00C0000 02020F05
	V_CMP_U_F32_e64 s[10:11], v5, v5, 0, 0, 0, 0                         ; D010000A 02020B05
	S_OR_B64 s[0:1], s[0:1], s[10:11]                                    ; 88800A00
	V_CNDMASK_B32_e64 v5, v7, v5, s[0:1], 0, 0, 0, 0                     ; D2000005 00020B07
	V_CMP_GE_F32_e64 s[0:1], v5, v8, 0, 0, 0, 0                          ; D00C0000 02021105
	V_CMP_U_F32_e64 s[10:11], v5, v5, 0, 0, 0, 0                         ; D010000A 02020B05
	S_OR_B64 s[0:1], s[0:1], s[10:11]                                    ; 88800A00
	V_CNDMASK_B32_e64 v5, v5, v8, s[0:1], 0, 0, 0, 0                     ; D2000005 00021105
	V_MOV_B32_e32 v4, v2                                                 ; 7E080302
	IMAGE_SAMPLE v2, 1, 0, 0, 0, 0, 0, 0, 0, v[3:4], s[16:23], s[12:15]  ; F0800100 00640203
	S_WAITCNT vmcnt(0)                                                   ; BF8C0770
	V_ADD_F32_e64 v2, v2, 0, 1, 0, 0, 0                                  ; D2060102 02010102
	V_MUL_F32_e32 v2, s6, v2                                             ; 10040406
	V_SUBREV_F32_e32 v2, s24, v2                                         ; 0A040418
	V_RCP_F32_e32 v2, v2                                                 ; 7E045502
	V_MUL_F32_e32 v2, s25, v2                                            ; 10040419
	V_SUB_F32_e32 v2, 1.000000e+00, v2                                   ; 080404F2
	V_MUL_F32_e32 v2, s8, v2                                             ; 10040408
	V_CMP_GE_F32_e64 s[0:1], v2, v7, 0, 0, 0, 0                          ; D00C0000 02020F02
	V_CMP_U_F32_e64 s[8:9], v2, v2, 0, 0, 0, 0                           ; D0100008 02020502
	S_OR_B64 s[0:1], s[0:1], s[8:9]                                      ; 88800800
	V_CNDMASK_B32_e64 v2, v7, v2, s[0:1], 0, 0, 0, 0                     ; D2000002 00020507
	V_CMP_GE_F32_e64 s[0:1], v2, v8, 0, 0, 0, 0                          ; D00C0000 02021102
	V_CMP_U_F32_e64 s[8:9], v2, v2, 0, 0, 0, 0                           ; D0100008 02020502
	S_OR_B64 s[0:1], s[0:1], s[8:9]                                      ; 88800800
	V_CNDMASK_B32_e64 v2, v2, v8, s[0:1], 0, 0, 0, 0                     ; D2000002 00021102
	V_CMP_U_F32_e64 s[0:1], v2, v5, 0, 0, 0, 0                           ; D0100000 02020B02
	V_CMP_GE_F32_e64 s[8:9], v2, v5, 0, 0, 0, 0                          ; D00C0008 02020B02
	S_OR_B64 s[0:1], s[8:9], s[0:1]                                      ; 88800008
	V_CNDMASK_B32_e64 v2, v5, v2, s[0:1], 0, 0, 0, 0                     ; D2000002 00020505
	V_CMP_U_F32_e64 s[0:1], v2, v6, 0, 0, 0, 0                           ; D0100000 02020D02
	V_CMP_GE_F32_e64 s[8:9], v2, v6, 0, 0, 0, 0                          ; D00C0008 02020D02
	S_OR_B64 s[0:1], s[8:9], s[0:1]                                      ; 88800008
	V_CNDMASK_B32_e64 v2, v6, v2, s[0:1], 0, 0, 0, 0                     ; D2000002 00020506
	V_MOV_B32_e32 v3, 1.000000e-01                                       ; 7E0602FF 3DCCCCCD
	V_MAD_F32 v2, v2, v3, 5.000000e-01, 0, 0, 0, 0                       ; D2820002 03C20702
	V_ADD_F32_e64 v2, 0, v2, 0, 1, 0, 0                                  ; D2060802 02020480
	V_INTERP_P1_F32 v4, v0, 1, 0, [m0]                                   ; C8100100
	V_INTERP_P2_F32 v4, [v4], v1, 1, 0, [m0]                             ; C8110101
	V_INTERP_P1_F32 v3, v0, 0, 0, [m0]                                   ; C80C0000
	V_INTERP_P2_F32 v3, [v3], v1, 0, 0, [m0]                             ; C80D0001
	S_LOAD_DWORDX4 s[0:3], s[2:3], 0                                     ; C0800300
	S_LOAD_DWORDX8 s[4:11], s[4:5], 0                                    ; C0C20500
	S_WAITCNT lgkmcnt(0)                                                 ; BF8C007F
	IMAGE_SAMPLE v[3:5], 7, 0, 0, 0, 0, 0, 0, 0, v[3:4], s[4:11], s[0:3] ; F0800700 00010303
	S_WAITCNT vmcnt(0)                                                   ; BF8C0770
	V_CVT_PKRTZ_F16_F32_e32 v0, v5, v2                                   ; 5E000505
	V_CVT_PKRTZ_F16_F32_e32 v1, v3, v4                                   ; 5E020903
	EXP 15, 0, 1, 1, 1, v1, v0, v1, v0                                   ; F8001C0F 00010001
	S_ENDPGM                                                             ; BF810000

VERT
DCL IN[0]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[19]
DCL CONST[0..1]
DCL TEMP[0..2], LOCAL
IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
  0: MOV TEMP[0].zw, IMM[0].yyxy
  1: MOV TEMP[0].xy, IN[0].xyxx
  2: MAD TEMP[1].xy, IN[0].zwww, CONST[0].xyyy, CONST[0].zwww
  3: MAD TEMP[2].xy, IN[0].zwww, CONST[1].xyyy, CONST[1].zwww
  4: MOV TEMP[1].zw, TEMP[2].yyxy
  5: MOV OUT[1], TEMP[1]
  6: MOV OUT[0], TEMP[0]
  7: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0)
  %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4)
  %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8)
  %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12)
  %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16)
  %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20)
  %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24)
  %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28)
  %20 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %21, i32 0, i32 %6)
  %23 = extractelement <4 x float> %22, i32 0
  %24 = extractelement <4 x float> %22, i32 1
  %25 = extractelement <4 x float> %22, i32 2
  %26 = extractelement <4 x float> %22, i32 3
  %27 = fmul float %25, %12
  %28 = fadd float %27, %14
  %29 = fmul float %26, %13
  %30 = fadd float %29, %15
  %31 = fmul float %25, %16
  %32 = fadd float %31, %18
  %33 = fmul float %26, %17
  %34 = fadd float %33, %19
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %28, float %30, float %32, float %34)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %23, float %24, float 0.000000e+00, float 1.000000e+00)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg6

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%23](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%11](align=8)(tbaa=!"const")
	S_WAITCNT 112
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 7; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR4<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 5; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR3, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 6; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 4; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR2, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 3; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR3, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 0; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR8<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR2, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 32, 0, 0, 0, %VGPR7<kill>, %VGPR6<kill>, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>
	S_WAITCNT 1807
	%VGPR4<def> = V_MOV_B32_e32 1.000000e+00, %EXEC<imp-use>
	%VGPR5<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR1, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_LOAD_DWORDX4 s[4:7], s[6:7], 0               ; C0820700
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	BUFFER_LOAD_FORMAT_XYZW v[0:3], s[4:7][v0] + 0 ; E00C2000 80010000
	S_LOAD_DWORDX4 s[0:3], s[0:1], 0               ; C0800100
	S_WAITCNT vmcnt(0) lgkmcnt(0)                  ; BF8C0070
	S_BUFFER_LOAD_DWORD s4, s[0:3], 7              ; C2020107
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v4, s4                           ; 7E080204
	S_BUFFER_LOAD_DWORD s4, s[0:3], 5              ; C2020105
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v5, s4                           ; 7E0A0204
	V_MAD_F32 v4, v3, v5, v4, 0, 0, 0, 0           ; D2820004 04120B03
	S_BUFFER_LOAD_DWORD s4, s[0:3], 6              ; C2020106
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v5, s4                           ; 7E0A0204
	S_BUFFER_LOAD_DWORD s4, s[0:3], 4              ; C2020104
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v6, s4                           ; 7E0C0204
	V_MAD_F32 v5, v2, v6, v5, 0, 0, 0, 0           ; D2820005 04160D02
	S_BUFFER_LOAD_DWORD s4, s[0:3], 3              ; C2020103
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v6, s4                           ; 7E0C0204
	S_BUFFER_LOAD_DWORD s4, s[0:3], 1              ; C2020101
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v7, s4                           ; 7E0E0204
	V_MAD_F32 v6, v3, v7, v6, 0, 0, 0, 0           ; D2820006 041A0F03
	S_BUFFER_LOAD_DWORD s4, s[0:3], 2              ; C2020102
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v7, s4                           ; 7E0E0204
	S_BUFFER_LOAD_DWORD s0, s[0:3], 0              ; C2000100
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v8, s0                           ; 7E100200
	V_MAD_F32 v7, v2, v8, v7, 0, 0, 0, 0           ; D2820007 041E1102
	EXP 15, 32, 0, 0, 0, v7, v6, v5, v4            ; F800020F 04050607
	S_WAITCNT expcnt(0)                            ; BF8C070F
	V_MOV_B32_e32 v4, 1.000000e+00                 ; 7E0802F2
	V_MOV_B32_e32 v5, 0.000000e+00                 ; 7E0A0280
	EXP 15, 12, 0, 1, 0, v0, v1, v5, v4            ; F80008CF 04050100
	S_ENDPGM                                       ; BF810000

FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL CONST[0..3]
DCL TEMP[0..29], LOCAL
IMM[0] FLT32 {    2.0000,    -1.0000,     5.0000,     0.0010}
IMM[1] FLT32 {    3.5449,     1.0000,    -1.0000,    10.0000}
IMM[2] FLT32 {    0.0000,     1.4427,     0.0001,     0.0000}
  0: MOV TEMP[0].xy, IN[0].xyyy
  1: TEX TEMP[0], TEMP[0], SAMP[0], 2D
  2: MOV TEMP[1].w, TEMP[0].wwww
  3: MAD TEMP[2].x, TEMP[0].wwww, IMM[0].xxxx, IMM[0].yyyy
  4: MUL TEMP[2].x, TEMP[2].xxxx, IMM[0].zzzz
  5: MOV TEMP[3].z, TEMP[2].xxxx
  6: ABS TEMP[2].x, TEMP[2].xxxx
  7: MAX TEMP[2].x, TEMP[2].xxxx, IMM[0].wwww
  8: MOV TEMP[3].w, TEMP[2].xxxx
  9: MUL TEMP[2].x, TEMP[2].xxxx, IMM[1].xxxx
 10: RCP TEMP[2].x, TEMP[2].xxxx
 11: MOV TEMP[4].x, TEMP[2].xxxx
 12: MUL TEMP[5], CONST[0].xyxy, IMM[1].yyzz
 13: MOV TEMP[6], IN[0].xyxy
 14: MUL TEMP[1].xyz, TEMP[0].xyzz, TEMP[2].xxxx
 15: MOV TEMP[0].x, IMM[1].yyyy
 16: BGNLOOP :0
 17:   FSGE TEMP[2].x, TEMP[0].xxxx, IMM[1].wwww
 18:   UIF TEMP[2].xxxx :0
 19:     BRK
 20:   ENDIF
 21:   ADD TEMP[7], TEMP[6], TEMP[5]
 22:   MOV TEMP[6], TEMP[7]
 23:   MOV TEMP[8].xy, TEMP[7].xyyy
 24:   MOV TEMP[8].w, IMM[2].xxxx
 25:   TXL TEMP[9], TEMP[8], SAMP[0], 2D
 26:   MOV TEMP[10].xy, TEMP[7].zwww
 27:   MOV TEMP[10].w, IMM[2].xxxx
 28:   TXL TEMP[11], TEMP[10], SAMP[0], 2D
 29:   MOV TEMP[12].x, TEMP[9].wwww
 30:   MOV TEMP[12].y, TEMP[11].wwww
 31:   MAD TEMP[13].xy, TEMP[12].xyyy, IMM[0].xxxx, IMM[0].yyyy
 32:   MUL TEMP[3].xy, TEMP[13].xyyy, IMM[0].zzzz
 33:   MIN TEMP[3].xy, TEMP[3].xyyy, TEMP[3].zzzz
 34:   ABS TEMP[14].xy, TEMP[3].xyyy
 35:   MAX TEMP[3].xy, TEMP[14].xyyy, IMM[0].wwww
 36:   MUL TEMP[15].x, TEMP[0].xxxx, TEMP[0].xxxx
 37:   MUL TEMP[16].xy, IMM[0].xxxx, TEMP[3].xyyy
 38:   MUL TEMP[17].xy, TEMP[16].xyyy, TEMP[3].xyyy
 39:   RCP TEMP[18].x, TEMP[17].xxxx
 40:   RCP TEMP[18].y, TEMP[17].yyyy
 41:   MUL TEMP[19].xy, -TEMP[15].xxxx, TEMP[18].xyyy
 42:   MUL TEMP[20].xy, TEMP[19].xyyy, IMM[2].yyyy
 43:   EX2 TEMP[21].x, TEMP[20].xxxx
 44:   EX2 TEMP[21].y, TEMP[20].yyyy
 45:   MUL TEMP[22].xy, TEMP[3].xyyy, IMM[1].xxxx
 46:   RCP TEMP[23].x, TEMP[22].xxxx
 47:   RCP TEMP[23].y, TEMP[22].yyyy
 48:   MUL TEMP[24].xy, TEMP[21].xyyy, TEMP[23].xyyy
 49:   MUL TEMP[25].xyz, TEMP[9].xyzz, TEMP[24].xxxx
 50:   MAD TEMP[26].xyz, TEMP[11].xyzz, TEMP[24].yyyy, TEMP[25].xyzz
 51:   ADD TEMP[1].xyz, TEMP[1].xyzz, TEMP[26].xyzz
 52:   ADD TEMP[27].x, TEMP[24].xxxx, TEMP[24].yyyy
 53:   ADD TEMP[4].x, TEMP[4].xxxx, TEMP[27].xxxx
 54:   FSGE TEMP[28].x, TEMP[27].xxxx, IMM[2].zzzz
 55:   UIF TEMP[28].xxxx :0
 56:     MOV TEMP[29].x, IMM[1].yyyy
 57:   ELSE :0
 58:     MOV TEMP[29].x, IMM[1].wwww
 59:   ENDIF
 60:   ADD TEMP[0].x, TEMP[0].xxxx, TEMP[29].xxxx
 61: ENDLOOP :0
 62: RCP TEMP[0].x, TEMP[4].xxxx
 63: MUL TEMP[1].xyz, TEMP[1].xyzz, TEMP[0].xxxx
 64: MOV OUT[0], TEMP[1]
 65: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %21 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
  %22 = load <16 x i8> addrspace(2)* %21, !tbaa !0
  %23 = call float @llvm.SI.load.const(<16 x i8> %22, i32 0)
  %24 = call float @llvm.SI.load.const(<16 x i8> %22, i32 4)
  %25 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0
  %26 = load <32 x i8> addrspace(2)* %25, !tbaa !0
  %27 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0
  %28 = load <16 x i8> addrspace(2)* %27, !tbaa !0
  %29 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %4, <2 x i32> %6)
  %30 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %4, <2 x i32> %6)
  %31 = bitcast float %29 to i32
  %32 = bitcast float %30 to i32
  %33 = insertelement <2 x i32> undef, i32 %31, i32 0
  %34 = insertelement <2 x i32> %33, i32 %32, i32 1
  %35 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %34, <32 x i8> %26, <16 x i8> %28, i32 2)
  %36 = extractelement <4 x float> %35, i32 0
  %37 = extractelement <4 x float> %35, i32 1
  %38 = extractelement <4 x float> %35, i32 2
  %39 = extractelement <4 x float> %35, i32 3
  %40 = fmul float %39, 2.000000e+00
  %41 = fadd float %40, -1.000000e+00
  %42 = fmul float %41, 5.000000e+00
  %43 = call float @fabs(float %42)
  %44 = fcmp uge float %43, 0x3F50624DE0000000
  %45 = select i1 %44, float %43, float 0x3F50624DE0000000
  %46 = fmul float %45, 0x400C5BF480000000
  %47 = fdiv float 1.000000e+00, %46
  %48 = fmul float %23, 1.000000e+00
  %49 = fmul float %24, 1.000000e+00
  %50 = fmul float %23, -1.000000e+00
  %51 = fmul float %24, -1.000000e+00
  %52 = fmul float %36, %47
  %53 = fmul float %37, %47
  %54 = fmul float %38, %47
  br label %LOOP

LOOP:                                             ; preds = %ENDIF, %main_body
  %temp27.0 = phi float [ %30, %main_body ], [ %71, %ENDIF ]
  %temp26.0 = phi float [ %29, %main_body ], [ %70, %ENDIF ]
  %temp25.0 = phi float [ %30, %main_body ], [ %69, %ENDIF ]
  %temp24.0 = phi float [ %29, %main_body ], [ %68, %ENDIF ]
  %temp16.0 = phi float [ %47, %main_body ], [ %144, %ENDIF ]
  %temp6.0 = phi float [ %54, %main_body ], [ %142, %ENDIF ]
  %temp5.0 = phi float [ %53, %main_body ], [ %141, %ENDIF ]
  %temp4.0 = phi float [ %52, %main_body ], [ %140, %ENDIF ]
  %temp.0 = phi float [ 1.000000e+00, %main_body ], [ %150, %ENDIF ]
  %55 = fcmp oge float %temp.0, 1.000000e+01
  %56 = sext i1 %55 to i32
  %57 = bitcast i32 %56 to float
  %58 = bitcast float %57 to i32
  %59 = icmp ne i32 %58, 0
  br i1 %59, label %IF, label %ENDIF

IF:                                               ; preds = %LOOP
  %60 = fdiv float 1.000000e+00, %temp16.0
  %61 = fmul float %temp4.0, %60
  %62 = fmul float %temp5.0, %60
  %63 = fmul float %temp6.0, %60
  %64 = call i32 @llvm.SI.packf16(float %61, float %62)
  %65 = bitcast i32 %64 to float
  %66 = call i32 @llvm.SI.packf16(float %63, float %39)
  %67 = bitcast i32 %66 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %65, float %67, float %65, float %67)
  ret void

ENDIF:                                            ; preds = %LOOP
  %68 = fadd float %temp24.0, %48
  %69 = fadd float %temp25.0, %49
  %70 = fadd float %temp26.0, %50
  %71 = fadd float %temp27.0, %51
  %72 = bitcast float %68 to i32
  %73 = bitcast float %69 to i32
  %74 = insertelement <4 x i32> undef, i32 %72, i32 0
  %75 = insertelement <4 x i32> %74, i32 %73, i32 1
  %76 = insertelement <4 x i32> %75, i32 0, i32 2
  %77 = insertelement <4 x i32> %76, i32 undef, i32 3
  %78 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %77, <32 x i8> %26, <16 x i8> %28, i32 2)
  %79 = extractelement <4 x float> %78, i32 0
  %80 = extractelement <4 x float> %78, i32 1
  %81 = extractelement <4 x float> %78, i32 2
  %82 = extractelement <4 x float> %78, i32 3
  %83 = bitcast float %70 to i32
  %84 = bitcast float %71 to i32
  %85 = insertelement <4 x i32> undef, i32 %83, i32 0
  %86 = insertelement <4 x i32> %85, i32 %84, i32 1
  %87 = insertelement <4 x i32> %86, i32 0, i32 2
  %88 = insertelement <4 x i32> %87, i32 undef, i32 3
  %89 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %88, <32 x i8> %26, <16 x i8> %28, i32 2)
  %90 = extractelement <4 x float> %89, i32 0
  %91 = extractelement <4 x float> %89, i32 1
  %92 = extractelement <4 x float> %89, i32 2
  %93 = extractelement <4 x float> %89, i32 3
  %94 = fmul float %82, 2.000000e+00
  %95 = fadd float %94, -1.000000e+00
  %96 = fmul float %93, 2.000000e+00
  %97 = fadd float %96, -1.000000e+00
  %98 = fmul float %95, 5.000000e+00
  %99 = fmul float %97, 5.000000e+00
  %100 = fcmp uge float %98, %42
  %101 = select i1 %100, float %42, float %98
  %102 = fcmp uge float %99, %42
  %103 = select i1 %102, float %42, float %99
  %104 = call float @fabs(float %101)
  %105 = call float @fabs(float %103)
  %106 = fcmp uge float %104, 0x3F50624DE0000000
  %107 = select i1 %106, float %104, float 0x3F50624DE0000000
  %108 = fcmp uge float %105, 0x3F50624DE0000000
  %109 = select i1 %108, float %105, float 0x3F50624DE0000000
  %110 = fmul float %temp.0, %temp.0
  %111 = fmul float 2.000000e+00, %107
  %112 = fmul float 2.000000e+00, %109
  %113 = fmul float %111, %107
  %114 = fmul float %112, %109
  %115 = fdiv float 1.000000e+00, %113
  %116 = fdiv float 1.000000e+00, %114
  %117 = fsub float -0.000000e+00, %110
  %118 = fmul float %117, %115
  %119 = fsub float -0.000000e+00, %110
  %120 = fmul float %119, %116
  %121 = fmul float %118, 0x3FF7154760000000
  %122 = fmul float %120, 0x3FF7154760000000
  %123 = call float @llvm.AMDIL.exp.(float %121)
  %124 = call float @llvm.AMDIL.exp.(float %122)
  %125 = fmul float %107, 0x400C5BF480000000
  %126 = fmul float %109, 0x400C5BF480000000
  %127 = fdiv float 1.000000e+00, %125
  %128 = fdiv float 1.000000e+00, %126
  %129 = fmul float %123, %127
  %130 = fmul float %124, %128
  %131 = fmul float %79, %129
  %132 = fmul float %80, %129
  %133 = fmul float %81, %129
  %134 = fmul float %90, %130
  %135 = fadd float %134, %131
  %136 = fmul float %91, %130
  %137 = fadd float %136, %132
  %138 = fmul float %92, %130
  %139 = fadd float %138, %133
  %140 = fadd float %temp4.0, %135
  %141 = fadd float %temp5.0, %137
  %142 = fadd float %temp6.0, %139
  %143 = fadd float %129, %130
  %144 = fadd float %temp16.0, %143
  %145 = fcmp oge float %143, 0x3F1A36E2E0000000
  %146 = sext i1 %145 to i32
  %147 = bitcast i32 %146 to float
  %148 = bitcast float %147 to i32
  %149 = icmp ne i32 %148, 0
  %. = select i1 %149, float 1.000000e+00, float 1.000000e+01
  %150 = fadd float %temp.0, %.
  br label %LOOP
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readonly
declare float @fabs(float) #2

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.samplel.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readnone
declare float @llvm.AMDIL.exp.(float) #3

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readonly }
attributes #3 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg44, %SGPR2_SGPR3 in %vreg45, %SGPR4_SGPR5 in %vreg46, %SGPR7 in %vreg48, %VGPR0 in %vreg49, %VGPR1 in %vreg50

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR7 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR7
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%30](align=8)(tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%27](tbaa=!"const")
	S_WAITCNT 127
	%VGPR6_VGPR7_VGPR8_VGPR9<def> = IMAGE_SAMPLE_V4_V2 15, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR0<def> = V_ADD_F32_e32 %VGPR9, %VGPR9, %EXEC<imp-use>
	%VGPR0<def> = V_ADD_F32_e32 -1.000000e+00, %VGPR0<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_F32_e32 5.000000e+00, %VGPR0<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_ADD_F32_e64 %VGPR0, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%VGPR10<def> = V_MOV_B32_e32 1.000000e-03, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR1, %VGPR10, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_U_F32_e64 %VGPR1, %VGPR1, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_OR_B64 %SGPR2_SGPR3<kill>, %SGPR4_SGPR5<kill>
	%VGPR1<def> = V_CNDMASK_B32_e64 %VGPR10<kill>, %VGPR1<kill>, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR1<def> = V_MUL_F32_e32 3.544900e+00, %VGPR1<kill>, %EXEC<imp-use>
	%VGPR22<def> = V_RCP_F32_e32 %VGPR1<kill>, %EXEC<imp-use>
	%VGPR23<def> = V_MUL_F32_e32 %VGPR8, %VGPR22, %EXEC<imp-use>
	%VGPR24<def> = V_MUL_F32_e32 %VGPR7, %VGPR22, %EXEC<imp-use>
	%VGPR25<def> = V_MUL_F32_e32 %VGPR6, %VGPR22, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%22](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR1<def> = V_ADD_F32_e64 %SGPR4, 0, 0, 0, 0, 1, %EXEC<imp-use>
	%SGPR2<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 0; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR10<def> = V_ADD_F32_e64 %SGPR2, 0, 0, 0, 0, 1, %EXEC<imp-use>
	%VGPR11<def> = V_MOV_B32_e32 1.000000e+00, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_MOV_B64 0
	%VGPR12<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR13<def> = V_MOV_B32_e32 %SGPR2<kill>, %EXEC<imp-use>
	%VGPR15<def> = V_MOV_B32_e32 %VGPR3, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17<imp-def>
	%VGPR14<def> = V_MOV_B32_e32 %VGPR2, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17<imp-def>
    Successors according to CFG: BB#1

BB#1: derived from LLVM BB %LOOP
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR13 %VGPR12 %VGPR10 %VGPR1 %VGPR6_VGPR7_VGPR8_VGPR9 %VGPR2_VGPR3_VGPR4_VGPR5 %VGPR14_VGPR15_VGPR16_VGPR17 %SGPR0_SGPR1 %VGPR22 %VGPR23 %VGPR24 %VGPR25 %VGPR11
    Predecessors according to CFG: BB#0 BB#2
	%VGPR19<def> = V_MOV_B32_e32 %VGPR25<kill>, %EXEC<imp-use>
	%VGPR20<def> = V_MOV_B32_e32 %VGPR24<kill>, %EXEC<imp-use>
	%VGPR18<def> = V_MOV_B32_e32 %VGPR23<kill>, %EXEC<imp-use>
	%VGPR21<def> = V_MOV_B32_e32 %VGPR22<kill>, %EXEC<imp-use>
	%VGPR22<def> = V_MOV_B32_e32 1.000000e+01, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_GE_F32_e64 %VGPR11, %VGPR22<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR22<def> = V_CNDMASK_B32_e64 0, -1, %SGPR2_SGPR3<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = V_CMP_EQ_I32_e64 %VGPR22<kill>, 0, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR25<def> = IMPLICIT_DEF
	%VGPR24<def> = IMPLICIT_DEF
	%VGPR23<def> = IMPLICIT_DEF
	%VGPR22<def> = IMPLICIT_DEF
	%SGPR2_SGPR3<def> = S_AND_SAVEEXEC_B64 %SGPR2_SGPR3, %EXEC<imp-def>, %EXEC<imp-use>
	%SGPR2_SGPR3<def> = S_XOR_B64 %EXEC, %SGPR2_SGPR3
	S_CBRANCH_EXECZ <BB#2>, %EXEC
    Successors according to CFG: BB#4(62) BB#2(62)

BB#4: derived from LLVM BB %ENDIF
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR13 %VGPR12 %VGPR10 %VGPR1 %VGPR21 %VGPR18 %VGPR20 %VGPR19 %VGPR6_VGPR7_VGPR8_VGPR9 %SGPR2_SGPR3 %VGPR2_VGPR3_VGPR4_VGPR5 %VGPR14_VGPR15_VGPR16_VGPR17 %SGPR0_SGPR1 %VGPR11
    Predecessors according to CFG: BB#1
	%VGPR3<def> = V_ADD_F32_e64 %VGPR3, %VGPR1, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR2<def> = V_ADD_F32_e64 %VGPR2, %VGPR10, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR4<def> = V_MOV_B32_e32 0, %EXEC<imp-use>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-use,kill>, %VGPR2_VGPR3_VGPR4_VGPR5<imp-def>
	%VGPR25_VGPR26_VGPR27_VGPR28<def> = IMAGE_SAMPLE_L_V4_V4 15, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3_VGPR4_VGPR5, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	S_WAITCNT 1792
	%VGPR22<def> = V_ADD_F32_e32 %VGPR28, %VGPR28, %EXEC<imp-use>
	%VGPR22<def> = V_ADD_F32_e32 -1.000000e+00, %VGPR22<kill>, %EXEC<imp-use>
	%VGPR22<def> = V_MUL_F32_e32 5.000000e+00, %VGPR22<kill>, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_U_F32_e64 %VGPR22, %VGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %VGPR22, %VGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = S_OR_B64 %SGPR6_SGPR7<kill>, %SGPR4_SGPR5<kill>
	%VGPR22<def> = V_CNDMASK_B32_e64 %VGPR22<kill>, %VGPR0, %SGPR4_SGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR22<def> = V_ADD_F32_e64 %VGPR22<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%VGPR23<def> = V_MOV_B32_e32 1.000000e-03, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_GE_F32_e64 %VGPR22, %VGPR23, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_U_F32_e64 %VGPR22, %VGPR22, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = S_OR_B64 %SGPR4_SGPR5<kill>, %SGPR6_SGPR7<kill>
	%VGPR22<def> = V_CNDMASK_B32_e64 %VGPR23, %VGPR22<kill>, %SGPR4_SGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_ADD_F32_e32 %VGPR22, %VGPR22, %EXEC<imp-use>
	%VGPR24<def> = V_MUL_F32_e32 %VGPR24<kill>, %VGPR22, %EXEC<imp-use>
	%VGPR24<def> = V_RCP_F32_e32 %VGPR24<kill>, %EXEC<imp-use>
	%VGPR29<def> = V_MUL_F32_e64 %VGPR11, %VGPR11, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR29<def> = V_ADD_F32_e64 %VGPR29<kill>, 0, 0, 0, 0, 1, %EXEC<imp-use>
	%VGPR24<def> = V_MUL_F32_e32 %VGPR29, %VGPR24<kill>, %EXEC<imp-use>
	%VGPR24<def> = V_MUL_F32_e32 1.442695e+00, %VGPR24<kill>, %EXEC<imp-use>
	%VGPR24<def> = V_EXP_F32_e32 %VGPR24<kill>, %EXEC<imp-use>
	%VGPR22<def> = V_MUL_F32_e32 3.544900e+00, %VGPR22<kill>, %EXEC<imp-use>
	%VGPR22<def> = V_RCP_F32_e32 %VGPR22<kill>, %EXEC<imp-use>
	%VGPR30<def> = V_MUL_F32_e32 %VGPR24<kill>, %VGPR22<kill>, %EXEC<imp-use>
	%VGPR15<def> = V_ADD_F32_e64 %VGPR15, %VGPR12, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17<imp-def>
	%VGPR14<def> = V_ADD_F32_e64 %VGPR14, %VGPR13, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17<imp-use,kill>, %VGPR14_VGPR15_VGPR16_VGPR17<imp-def>
	%VGPR16<def> = V_MOV_B32_e32 %VGPR4, %EXEC<imp-use>, %VGPR14_VGPR15_VGPR16_VGPR17<imp-def>
	%VGPR31_VGPR32_VGPR33_VGPR34<def> = IMAGE_SAMPLE_L_V4_V4 15, 0, 0, 0, 0, 0, 0, 0, %VGPR14_VGPR15_VGPR16_VGPR17, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19, %SGPR8_SGPR9_SGPR10_SGPR11, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR22<def> = V_ADD_F32_e32 %VGPR34, %VGPR34, %EXEC<imp-use>
	%VGPR22<def> = V_ADD_F32_e32 -1.000000e+00, %VGPR22<kill>, %EXEC<imp-use>
	%VGPR22<def> = V_MUL_F32_e32 5.000000e+00, %VGPR22<kill>, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_U_F32_e64 %VGPR22, %VGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_GE_F32_e64 %VGPR22, %VGPR0, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = S_OR_B64 %SGPR6_SGPR7<kill>, %SGPR4_SGPR5<kill>
	%VGPR22<def> = V_CNDMASK_B32_e64 %VGPR22<kill>, %VGPR0, %SGPR4_SGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR22<def> = V_ADD_F32_e64 %VGPR22<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_GE_F32_e64 %VGPR22, %VGPR23, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR6_SGPR7<def> = V_CMP_U_F32_e64 %VGPR22, %VGPR22, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = S_OR_B64 %SGPR4_SGPR5<kill>, %SGPR6_SGPR7<kill>
	%VGPR22<def> = V_CNDMASK_B32_e64 %VGPR23<kill>, %VGPR22<kill>, %SGPR4_SGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR23<def> = V_ADD_F32_e32 %VGPR22, %VGPR22, %EXEC<imp-use>
	%VGPR23<def> = V_MUL_F32_e32 %VGPR23<kill>, %VGPR22, %EXEC<imp-use>
	%VGPR23<def> = V_RCP_F32_e32 %VGPR23<kill>, %EXEC<imp-use>
	%VGPR23<def> = V_MUL_F32_e32 %VGPR29<kill>, %VGPR23<kill>, %EXEC<imp-use>
	%VGPR23<def> = V_MUL_F32_e32 1.442695e+00, %VGPR23<kill>, %EXEC<imp-use>
	%VGPR23<def> = V_EXP_F32_e32 %VGPR23<kill>, %EXEC<imp-use>
	%VGPR22<def> = V_MUL_F32_e32 3.544900e+00, %VGPR22<kill>, %EXEC<imp-use>
	%VGPR24<def> = V_RCP_F32_e32 %VGPR22<kill>, %EXEC<imp-use>
	%VGPR29<def> = V_MAD_F32 %VGPR23, %VGPR24, %VGPR30, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR22<def> = V_ADD_F32_e32 %VGPR21, %VGPR29, %EXEC<imp-use>
	%VGPR35<def> = V_MUL_F32_e32 %VGPR23<kill>, %VGPR24<kill>, %EXEC<imp-use>
	%VGPR23<def> = V_MUL_F32_e32 %VGPR33, %VGPR35, %EXEC<imp-use>
	%VGPR23<def> = V_MAD_F32 %VGPR27, %VGPR30, %VGPR23<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR23<def> = V_ADD_F32_e32 %VGPR18, %VGPR23<kill>, %EXEC<imp-use>
	%VGPR24<def> = V_MUL_F32_e32 %VGPR32, %VGPR35, %EXEC<imp-use>
	%VGPR24<def> = V_MAD_F32 %VGPR26, %VGPR30, %VGPR24<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR24<def> = V_ADD_F32_e32 %VGPR20, %VGPR24<kill>, %EXEC<imp-use>
	%VGPR31<def> = V_MUL_F32_e32 %VGPR31, %VGPR35<kill>, %EXEC<imp-use>, %VGPR31_VGPR32_VGPR33_VGPR34<imp-use,kill>
	%VGPR25<def> = V_MAD_F32 %VGPR25, %VGPR30<kill>, %VGPR31<kill>, 0, 0, 0, 0, %EXEC<imp-use>, %VGPR25_VGPR26_VGPR27_VGPR28<imp-use,kill>
	%VGPR25<def> = V_ADD_F32_e32 %VGPR19, %VGPR25<kill>, %EXEC<imp-use>
	%VGPR26<def> = V_MOV_B32_e32 1.000000e-04, %EXEC<imp-use>
	%SGPR4_SGPR5<def> = V_CMP_GE_F32_e64 %VGPR29<kill>, %VGPR26<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR26<def> = V_MOV_B32_e32 1.000000e+01, %EXEC<imp-use>
	%VGPR26<def> = V_CNDMASK_B32_e64 %VGPR26<kill>, 1.000000e+00, %SGPR4_SGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR11<def> = V_ADD_F32_e32 %VGPR11<kill>, %VGPR26<kill>, %EXEC<imp-use>
    Successors according to CFG: BB#2

BB#2: derived from LLVM BB %Flow
    Live Ins: %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19 %SGPR8_SGPR9_SGPR10_SGPR11 %VGPR0 %VGPR13 %VGPR12 %VGPR10 %VGPR1 %VGPR21 %VGPR18 %VGPR20 %VGPR19 %VGPR6_VGPR7_VGPR8_VGPR9 %SGPR2_SGPR3 %VGPR2_VGPR3_VGPR4_VGPR5 %VGPR14_VGPR15_VGPR16_VGPR17 %SGPR0_SGPR1 %VGPR22 %VGPR23 %VGPR24 %VGPR25 %VGPR11
    Predecessors according to CFG: BB#1 BB#4
	%EXEC<def> = S_OR_B64 %EXEC, %SGPR2_SGPR3
	%SGPR0_SGPR1<def> = S_OR_B64 %SGPR2_SGPR3, %SGPR0_SGPR1
	%EXEC<def> = S_ANDN2_B64 %EXEC, %SGPR0_SGPR1
	S_CBRANCH_EXECNZ <BB#1>, %EXEC
    Successors according to CFG: BB#3(4) BB#1(124)

BB#3: derived from LLVM BB %IF
    Live Ins: %VGPR21 %VGPR18 %VGPR20 %VGPR19 %VGPR6_VGPR7_VGPR8_VGPR9 %SGPR0_SGPR1
    Predecessors according to CFG: BB#2
	%EXEC<def> = S_OR_B64 %EXEC, %SGPR0_SGPR1
	%VGPR0<def> = V_RCP_F32_e32 %VGPR21<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_MUL_F32_e32 %VGPR20<kill>, %VGPR0, %EXEC<imp-use>
	%VGPR2<def> = V_MUL_F32_e32 %VGPR19<kill>, %VGPR0, %EXEC<imp-use>
	%VGPR1<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR2<kill>, %VGPR1<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_MUL_F32_e32 %VGPR18<kill>, %VGPR0<kill>, %EXEC<imp-use>
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR0<kill>, %VGPR9, %EXEC<imp-use>, %VGPR6_VGPR7_VGPR8_VGPR9<imp-use,kill>
	EXP 15, 0, 1, 1, 1, %VGPR1<kill>, %VGPR0<kill>, %VGPR1, %VGPR0, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_WQM_B64 exec, exec                                                          ; BEFE0A7E
	S_MOV_B32 m0, s7                                                              ; BEFC0307
	V_INTERP_P1_F32 v3, v0, 1, 0, [m0]                                            ; C80C0100
	V_INTERP_P2_F32 v3, [v3], v1, 1, 0, [m0]                                      ; C80D0101
	V_INTERP_P1_F32 v2, v0, 0, 0, [m0]                                            ; C8080000
	V_INTERP_P2_F32 v2, [v2], v1, 0, 0, [m0]                                      ; C8090001
	S_LOAD_DWORDX4 s[8:11], s[2:3], 0                                             ; C0840300
	S_LOAD_DWORDX8 s[12:19], s[4:5], 0                                            ; C0C60500
	S_WAITCNT lgkmcnt(0)                                                          ; BF8C007F
	IMAGE_SAMPLE v[6:9], 15, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[12:19], s[8:11]       ; F0800F00 00430602
	S_WAITCNT vmcnt(0)                                                            ; BF8C0770
	V_ADD_F32_e32 v0, v9, v9                                                      ; 06001309
	V_ADD_F32_e32 v0, -1.000000e+00, v0                                           ; 060000F3
	V_MUL_F32_e32 v0, 5.000000e+00, v0                                            ; 100000FF 40A00000
	V_ADD_F32_e64 v1, v0, 0, 1, 0, 0, 0                                           ; D2060101 02010100
	V_MOV_B32_e32 v10, 1.000000e-03                                               ; 7E1402FF 3A83126F
	V_CMP_GE_F32_e64 s[2:3], v1, v10, 0, 0, 0, 0                                  ; D00C0002 02021501
	V_CMP_U_F32_e64 s[4:5], v1, v1, 0, 0, 0, 0                                    ; D0100004 02020301
	S_OR_B64 s[2:3], s[2:3], s[4:5]                                               ; 88820402
	V_CNDMASK_B32_e64 v1, v10, v1, s[2:3], 0, 0, 0, 0                             ; D2000001 000A030A
	V_MUL_F32_e32 v1, 3.544900e+00, v1                                            ; 100202FF 4062DFA4
	V_RCP_F32_e32 v22, v1                                                         ; 7E2C5501
	V_MUL_F32_e32 v23, v8, v22                                                    ; 102E2D08
	V_MUL_F32_e32 v24, v7, v22                                                    ; 10302D07
	V_MUL_F32_e32 v25, v6, v22                                                    ; 10322D06
	S_LOAD_DWORDX4 s[0:3], s[0:1], 0                                              ; C0800100
	S_WAITCNT lgkmcnt(0)                                                          ; BF8C007F
	S_BUFFER_LOAD_DWORD s4, s[0:3], 1                                             ; C2020101
	S_WAITCNT lgkmcnt(0)                                                          ; BF8C007F
	V_ADD_F32_e64 v1, s4, 0, 0, 0, 0, 1                                           ; D2060001 22010004
	S_BUFFER_LOAD_DWORD s2, s[0:3], 0                                             ; C2010100
	S_WAITCNT lgkmcnt(0)                                                          ; BF8C007F
	V_ADD_F32_e64 v10, s2, 0, 0, 0, 0, 1                                          ; D206000A 22010002
	V_MOV_B32_e32 v11, 1.000000e+00                                               ; 7E1602F2
	S_MOV_B64 s[0:1], 0                                                           ; BE800480
	V_MOV_B32_e32 v12, s4                                                         ; 7E180204
	V_MOV_B32_e32 v13, s2                                                         ; 7E1A0202
	V_MOV_B32_e32 v15, v3                                                         ; 7E1E0303
	V_MOV_B32_e32 v14, v2                                                         ; 7E1C0302
	V_MOV_B32_e32 v19, v25                                                        ; 7E260319
	V_MOV_B32_e32 v20, v24                                                        ; 7E280318
	V_MOV_B32_e32 v18, v23                                                        ; 7E240317
	V_MOV_B32_e32 v21, v22                                                        ; 7E2A0316
	V_MOV_B32_e32 v22, 1.000000e+01                                               ; 7E2C02FF 41200000
	V_CMP_GE_F32_e64 s[2:3], v11, v22, 0, 0, 0, 0                                 ; D00C0002 02022D0B
	V_CNDMASK_B32_e64 v22, 0, -1, s[2:3], 0, 0, 0, 0                              ; D2000016 00098280
	V_CMP_EQ_I32_e64 s[2:3], v22, 0, 0, 0, 0, 0                                   ; D1040002 02010116
	S_AND_SAVEEXEC_B64 s[2:3], s[2:3]                                             ; BE822402
	S_XOR_B64 s[2:3], exec, s[2:3]                                                ; 8982027E
	S_CBRANCH_EXECZ ";.BB0_2"                                                     ; BF880000
	V_ADD_F32_e64 v3, v3, v1, 0, 0, 0, 0                                          ; D2060003 02020303
	V_ADD_F32_e64 v2, v2, v10, 0, 0, 0, 0                                         ; D2060002 02021502
	V_MOV_B32_e32 v4, 0                                                           ; 7E080280
	IMAGE_SAMPLE_L v[25:28], 15, 0, 0, 0, 0, 0, 0, 0, v[2:5], s[12:19], s[8:11]   ; F0900F00 00431902
	S_WAITCNT vmcnt(0) expcnt(0)                                                  ; BF8C0700
	V_ADD_F32_e32 v22, v28, v28                                                   ; 062C391C
	V_ADD_F32_e32 v22, -1.000000e+00, v22                                         ; 062C2CF3
	V_MUL_F32_e32 v22, 5.000000e+00, v22                                          ; 102C2CFF 40A00000
	V_CMP_U_F32_e64 s[4:5], v22, v0, 0, 0, 0, 0                                   ; D0100004 02020116
	V_CMP_GE_F32_e64 s[6:7], v22, v0, 0, 0, 0, 0                                  ; D00C0006 02020116
	S_OR_B64 s[4:5], s[6:7], s[4:5]                                               ; 88840406
	V_CNDMASK_B32_e64 v22, v22, v0, s[4:5], 0, 0, 0, 0                            ; D2000016 00120116
	V_ADD_F32_e64 v22, v22, 0, 1, 0, 0, 0                                         ; D2060116 02010116
	V_MOV_B32_e32 v23, 1.000000e-03                                               ; 7E2E02FF 3A83126F
	V_CMP_GE_F32_e64 s[4:5], v22, v23, 0, 0, 0, 0                                 ; D00C0004 02022F16
	V_CMP_U_F32_e64 s[6:7], v22, v22, 0, 0, 0, 0                                  ; D0100006 02022D16
	S_OR_B64 s[4:5], s[4:5], s[6:7]                                               ; 88840604
	V_CNDMASK_B32_e64 v22, v23, v22, s[4:5], 0, 0, 0, 0                           ; D2000016 00122D17
	V_ADD_F32_e32 v24, v22, v22                                                   ; 06302D16
	V_MUL_F32_e32 v24, v24, v22                                                   ; 10302D18
	V_RCP_F32_e32 v24, v24                                                        ; 7E305518
	V_MUL_F32_e64 v29, v11, v11, 0, 0, 0, 0                                       ; D210001D 0202170B
	V_ADD_F32_e64 v29, v29, 0, 0, 0, 0, 1                                         ; D206001D 2201011D
	V_MUL_F32_e32 v24, v29, v24                                                   ; 1030311D
	V_MUL_F32_e32 v24, 1.442695e+00, v24                                          ; 103030FF 3FB8AA3B
	V_EXP_F32_e32 v24, v24                                                        ; 7E304B18
	V_MUL_F32_e32 v22, 3.544900e+00, v22                                          ; 102C2CFF 4062DFA4
	V_RCP_F32_e32 v22, v22                                                        ; 7E2C5516
	V_MUL_F32_e32 v30, v24, v22                                                   ; 103C2D18
	V_ADD_F32_e64 v15, v15, v12, 0, 0, 0, 0                                       ; D206000F 0202190F
	V_ADD_F32_e64 v14, v14, v13, 0, 0, 0, 0                                       ; D206000E 02021B0E
	V_MOV_B32_e32 v16, v4                                                         ; 7E200304
	IMAGE_SAMPLE_L v[31:34], 15, 0, 0, 0, 0, 0, 0, 0, v[14:17], s[12:19], s[8:11] ; F0900F00 00431F0E
	S_WAITCNT vmcnt(0)                                                            ; BF8C0770
	V_ADD_F32_e32 v22, v34, v34                                                   ; 062C4522
	V_ADD_F32_e32 v22, -1.000000e+00, v22                                         ; 062C2CF3
	V_MUL_F32_e32 v22, 5.000000e+00, v22                                          ; 102C2CFF 40A00000
	V_CMP_U_F32_e64 s[4:5], v22, v0, 0, 0, 0, 0                                   ; D0100004 02020116
	V_CMP_GE_F32_e64 s[6:7], v22, v0, 0, 0, 0, 0                                  ; D00C0006 02020116
	S_OR_B64 s[4:5], s[6:7], s[4:5]                                               ; 88840406
	V_CNDMASK_B32_e64 v22, v22, v0, s[4:5], 0, 0, 0, 0                            ; D2000016 00120116
	V_ADD_F32_e64 v22, v22, 0, 1, 0, 0, 0                                         ; D2060116 02010116
	V_CMP_GE_F32_e64 s[4:5], v22, v23, 0, 0, 0, 0                                 ; D00C0004 02022F16
	V_CMP_U_F32_e64 s[6:7], v22, v22, 0, 0, 0, 0                                  ; D0100006 02022D16
	S_OR_B64 s[4:5], s[4:5], s[6:7]                                               ; 88840604
	V_CNDMASK_B32_e64 v22, v23, v22, s[4:5], 0, 0, 0, 0                           ; D2000016 00122D17
	V_ADD_F32_e32 v23, v22, v22                                                   ; 062E2D16
	V_MUL_F32_e32 v23, v23, v22                                                   ; 102E2D17
	V_RCP_F32_e32 v23, v23                                                        ; 7E2E5517
	V_MUL_F32_e32 v23, v29, v23                                                   ; 102E2F1D
	V_MUL_F32_e32 v23, 1.442695e+00, v23                                          ; 102E2EFF 3FB8AA3B
	V_EXP_F32_e32 v23, v23                                                        ; 7E2E4B17
	V_MUL_F32_e32 v22, 3.544900e+00, v22                                          ; 102C2CFF 4062DFA4
	V_RCP_F32_e32 v24, v22                                                        ; 7E305516
	V_MAD_F32 v29, v23, v24, v30, 0, 0, 0, 0                                      ; D282001D 047A3117
	V_ADD_F32_e32 v22, v21, v29                                                   ; 062C3B15
	V_MUL_F32_e32 v35, v23, v24                                                   ; 10463117
	V_MUL_F32_e32 v23, v33, v35                                                   ; 102E4721
	V_MAD_F32 v23, v27, v30, v23, 0, 0, 0, 0                                      ; D2820017 045E3D1B
	V_ADD_F32_e32 v23, v18, v23                                                   ; 062E2F12
	V_MUL_F32_e32 v24, v32, v35                                                   ; 10304720
	V_MAD_F32 v24, v26, v30, v24, 0, 0, 0, 0                                      ; D2820018 04623D1A
	V_ADD_F32_e32 v24, v20, v24                                                   ; 06303114
	V_MUL_F32_e32 v31, v31, v35                                                   ; 103E471F
	V_MAD_F32 v25, v25, v30, v31, 0, 0, 0, 0                                      ; D2820019 047E3D19
	V_ADD_F32_e32 v25, v19, v25                                                   ; 06323313
	V_MOV_B32_e32 v26, 1.000000e-04                                               ; 7E3402FF 38D1B717
	V_CMP_GE_F32_e64 s[4:5], v29, v26, 0, 0, 0, 0                                 ; D00C0004 0202351D
	V_MOV_B32_e32 v26, 1.000000e+01                                               ; 7E3402FF 41200000
	V_CNDMASK_B32_e64 v26, v26, 1.000000e+00, s[4:5], 0, 0, 0, 0                  ; D200001A 0011E51A
	V_ADD_F32_e32 v11, v11, v26                                                   ; 0616350B
	S_OR_B64 exec, exec, s[2:3]                                                   ; 88FE027E
	S_OR_B64 s[0:1], s[2:3], s[0:1]                                               ; 88800002
	S_ANDN2_B64 exec, exec, s[0:1]                                                ; 8AFE007E
	S_CBRANCH_EXECNZ ";.BB0_1"                                                    ; BF890000
	S_OR_B64 exec, exec, s[0:1]                                                   ; 88FE007E
	V_RCP_F32_e32 v0, v21                                                         ; 7E005515
	V_MUL_F32_e32 v1, v20, v0                                                     ; 10020114
	V_MUL_F32_e32 v2, v19, v0                                                     ; 10040113
	V_CVT_PKRTZ_F16_F32_e32 v1, v2, v1                                            ; 5E020302
	V_MUL_F32_e32 v0, v18, v0                                                     ; 10000112
	V_CVT_PKRTZ_F16_F32_e32 v0, v0, v9                                            ; 5E001300
	EXP 15, 0, 1, 1, 1, v1, v0, v1, v0                                            ; F8001C0F 00010001
	S_ENDPGM                                                                      ; BF810000

VERT
DCL IN[0]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[19]
DCL CONST[0..1]
DCL TEMP[0..2], LOCAL
IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
  0: MOV TEMP[0].zw, IMM[0].yyxy
  1: MOV TEMP[0].xy, IN[0].xyxx
  2: MAD TEMP[1].xy, IN[0].zwww, CONST[0].xyyy, CONST[0].zwww
  3: MAD TEMP[2].xy, IN[0].zwww, CONST[1].xyyy, CONST[1].zwww
  4: MOV TEMP[1].zw, TEMP[2].yyxy
  5: MOV OUT[1], TEMP[1]
  6: MOV OUT[0], TEMP[0]
  7: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0)
  %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4)
  %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8)
  %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12)
  %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16)
  %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20)
  %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24)
  %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28)
  %20 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %21, i32 0, i32 %6)
  %23 = extractelement <4 x float> %22, i32 0
  %24 = extractelement <4 x float> %22, i32 1
  %25 = extractelement <4 x float> %22, i32 2
  %26 = extractelement <4 x float> %22, i32 3
  %27 = fmul float %25, %12
  %28 = fadd float %27, %14
  %29 = fmul float %26, %13
  %30 = fadd float %29, %15
  %31 = fmul float %25, %16
  %32 = fadd float %31, %18
  %33 = fmul float %26, %17
  %34 = fadd float %33, %19
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %28, float %30, float %32, float %34)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %23, float %24, float 0.000000e+00, float 1.000000e+00)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg6

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%23](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%11](align=8)(tbaa=!"const")
	S_WAITCNT 112
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 7; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR4<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 5; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR3, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 6; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 4; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR2, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 3; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR3, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 0; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR8<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR2, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 32, 0, 0, 0, %VGPR7<kill>, %VGPR6<kill>, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>
	S_WAITCNT 1807
	%VGPR4<def> = V_MOV_B32_e32 1.000000e+00, %EXEC<imp-use>
	%VGPR5<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR1, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_LOAD_DWORDX4 s[4:7], s[6:7], 0               ; C0820700
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	BUFFER_LOAD_FORMAT_XYZW v[0:3], s[4:7][v0] + 0 ; E00C2000 80010000
	S_LOAD_DWORDX4 s[0:3], s[0:1], 0               ; C0800100
	S_WAITCNT vmcnt(0) lgkmcnt(0)                  ; BF8C0070
	S_BUFFER_LOAD_DWORD s4, s[0:3], 7              ; C2020107
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v4, s4                           ; 7E080204
	S_BUFFER_LOAD_DWORD s4, s[0:3], 5              ; C2020105
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v5, s4                           ; 7E0A0204
	V_MAD_F32 v4, v3, v5, v4, 0, 0, 0, 0           ; D2820004 04120B03
	S_BUFFER_LOAD_DWORD s4, s[0:3], 6              ; C2020106
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v5, s4                           ; 7E0A0204
	S_BUFFER_LOAD_DWORD s4, s[0:3], 4              ; C2020104
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v6, s4                           ; 7E0C0204
	V_MAD_F32 v5, v2, v6, v5, 0, 0, 0, 0           ; D2820005 04160D02
	S_BUFFER_LOAD_DWORD s4, s[0:3], 3              ; C2020103
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v6, s4                           ; 7E0C0204
	S_BUFFER_LOAD_DWORD s4, s[0:3], 1              ; C2020101
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v7, s4                           ; 7E0E0204
	V_MAD_F32 v6, v3, v7, v6, 0, 0, 0, 0           ; D2820006 041A0F03
	S_BUFFER_LOAD_DWORD s4, s[0:3], 2              ; C2020102
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v7, s4                           ; 7E0E0204
	S_BUFFER_LOAD_DWORD s0, s[0:3], 0              ; C2000100
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v8, s0                           ; 7E100200
	V_MAD_F32 v7, v2, v8, v7, 0, 0, 0, 0           ; D2820007 041E1102
	EXP 15, 32, 0, 0, 0, v7, v6, v5, v4            ; F800020F 04050607
	S_WAITCNT expcnt(0)                            ; BF8C070F
	V_MOV_B32_e32 v4, 1.000000e+00                 ; 7E0802F2
	V_MOV_B32_e32 v5, 0.000000e+00                 ; 7E0A0280
	EXP 15, 12, 0, 1, 0, v0, v1, v5, v4            ; F80008CF 04050100
	S_ENDPGM                                       ; BF810000

FRAG
PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
DCL IN[0], GENERIC[19], PERSPECTIVE
DCL OUT[0], COLOR
DCL SAMP[0]
DCL SAMP[1]
DCL CONST[0..3]
DCL TEMP[0..1], LOCAL
IMM[0] FLT32 {    1.0000,    -5.0000,     5.0000,     0.0000}
  0: MOV TEMP[0].xy, IN[0].xyyy
  1: TEX TEMP[0].xyz, TEMP[0], SAMP[0], 2D
  2: MOV TEMP[0].xyz, TEMP[0].xyzx
  3: MOV TEMP[1].xy, IN[0].zwww
  4: TEX TEMP[1].x, TEMP[1], SAMP[1], 2D
  5: ABS TEMP[1].x, TEMP[1].xxxx
  6: MAD TEMP[1].x, TEMP[1].xxxx, CONST[3].yyyy, -CONST[3].xxxx
  7: RCP TEMP[1].x, TEMP[1].xxxx
  8: MUL TEMP[1].x, CONST[1].xxxx, TEMP[1].xxxx
  9: ADD TEMP[1].x, IMM[0].xxxx, -TEMP[1].xxxx
 10: MUL TEMP[1].x, CONST[1].yyyy, TEMP[1].xxxx
 11: MAX TEMP[1].x, TEMP[1].xxxx, IMM[0].yyyy
 12: MIN TEMP[1].x, TEMP[1].xxxx, IMM[0].zzzz
 13: ABS TEMP[1].x, TEMP[1].xxxx
 14: MOV_SAT TEMP[1].x, TEMP[1].xxxx
 15: MOV TEMP[0].w, TEMP[1].xxxx
 16: MOV OUT[0], TEMP[0]
 17: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
main_body:
  %21 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
  %22 = load <16 x i8> addrspace(2)* %21, !tbaa !0
  %23 = call float @llvm.SI.load.const(<16 x i8> %22, i32 16)
  %24 = call float @llvm.SI.load.const(<16 x i8> %22, i32 20)
  %25 = call float @llvm.SI.load.const(<16 x i8> %22, i32 48)
  %26 = call float @llvm.SI.load.const(<16 x i8> %22, i32 52)
  %27 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0
  %28 = load <32 x i8> addrspace(2)* %27, !tbaa !0
  %29 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0
  %30 = load <16 x i8> addrspace(2)* %29, !tbaa !0
  %31 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 1
  %32 = load <32 x i8> addrspace(2)* %31, !tbaa !0
  %33 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 1
  %34 = load <16 x i8> addrspace(2)* %33, !tbaa !0
  %35 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %4, <2 x i32> %6)
  %36 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %4, <2 x i32> %6)
  %37 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %4, <2 x i32> %6)
  %38 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %4, <2 x i32> %6)
  %39 = bitcast float %35 to i32
  %40 = bitcast float %36 to i32
  %41 = insertelement <2 x i32> undef, i32 %39, i32 0
  %42 = insertelement <2 x i32> %41, i32 %40, i32 1
  %43 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %42, <32 x i8> %28, <16 x i8> %30, i32 2)
  %44 = extractelement <4 x float> %43, i32 0
  %45 = extractelement <4 x float> %43, i32 1
  %46 = extractelement <4 x float> %43, i32 2
  %47 = bitcast float %37 to i32
  %48 = bitcast float %38 to i32
  %49 = insertelement <2 x i32> undef, i32 %47, i32 0
  %50 = insertelement <2 x i32> %49, i32 %48, i32 1
  %51 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %50, <32 x i8> %32, <16 x i8> %34, i32 2)
  %52 = extractelement <4 x float> %51, i32 0
  %53 = call float @fabs(float %52)
  %54 = fsub float -0.000000e+00, %25
  %55 = fmul float %53, %26
  %56 = fadd float %55, %54
  %57 = fdiv float 1.000000e+00, %56
  %58 = fmul float %23, %57
  %59 = fsub float -0.000000e+00, %58
  %60 = fadd float 1.000000e+00, %59
  %61 = fmul float %24, %60
  %62 = fcmp uge float %61, -5.000000e+00
  %63 = select i1 %62, float %61, float -5.000000e+00
  %64 = fcmp uge float %63, 5.000000e+00
  %65 = select i1 %64, float 5.000000e+00, float %63
  %66 = call float @fabs(float %65)
  %67 = call float @llvm.AMDIL.clamp.(float %66, float 0.000000e+00, float 1.000000e+00)
  %68 = call i32 @llvm.SI.packf16(float %44, float %45)
  %69 = bitcast i32 %68 to float
  %70 = call i32 @llvm.SI.packf16(float %46, float %67)
  %71 = bitcast i32 %70 to float
  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %69, float %71, float %69, float %71)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1

; Function Attrs: readonly
declare float @fabs(float) #2

; Function Attrs: readnone
declare float @llvm.AMDIL.clamp.(float, float, float) #3

; Function Attrs: nounwind readnone
declare i32 @llvm.SI.packf16(float, float) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="0" }
attributes #1 = { nounwind readnone }
attributes #2 = { readonly }
attributes #3 = { readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR2_SGPR3 in %vreg1, %SGPR4_SGPR5 in %vreg2, %SGPR7 in %vreg4, %VGPR0 in %vreg5, %VGPR1 in %vreg6

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR2_SGPR3 %SGPR4_SGPR5 %SGPR7 %VGPR0 %VGPR1
	%EXEC<def> = S_WQM_B64 %EXEC
	%VGPR1<def> = KILL %VGPR1, %VGPR0_VGPR1<imp-def>
	%VGPR0<def> = KILL %VGPR0, %VGPR0_VGPR1<imp-use,kill>, %VGPR0_VGPR1<imp-def>
	%M0<def> = S_MOV_B32 %SGPR7
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 3, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-def>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 3, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def> = V_INTERP_P1_F32 %VGPR0, 2, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%VGPR2<def,tied1> = V_INTERP_P2_F32 %VGPR2<tied0>, %VGPR1, 2, 0, %M0<kill>, %EXEC<imp-use>, %VGPR2_VGPR3<imp-use,kill>, %VGPR2_VGPR3<imp-def>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3, 4; mem:LD16[%38](align=8)(tbaa=!"const")
	%SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5, 8; mem:LD32[%35](tbaa=!"const")
	S_WAITCNT 127
	%VGPR2<def> = IMAGE_SAMPLE_V1_V2 1, 0, 0, 0, 0, 0, 0, 0, %VGPR2_VGPR3<kill>, %SGPR12_SGPR13_SGPR14_SGPR15_SGPR16_SGPR17_SGPR18_SGPR19<kill>, %SGPR8_SGPR9_SGPR10_SGPR11<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR2<def> = V_ADD_F32_e64 %VGPR2<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%22](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 13; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 12; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR2<def> = V_SUBREV_F32_e32 %SGPR0<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_RCP_F32_e32 %VGPR2<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11, 4; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR2<def> = V_SUB_F32_e32 1.000000e+00, %VGPR2<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR8_SGPR9_SGPR10_SGPR11<kill>, 5; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR2<def> = V_MUL_F32_e32 %SGPR0<kill>, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR3<def> = V_MOV_B32_e32 -5.000000e+00, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = V_CMP_GE_F32_e64 %VGPR2, %VGPR3, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8_SGPR9<def> = V_CMP_U_F32_e64 %VGPR2, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_OR_B64 %SGPR0_SGPR1<kill>, %SGPR8_SGPR9<kill>
	%VGPR2<def> = V_CNDMASK_B32_e64 %VGPR3<kill>, %VGPR2<kill>, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR3<def> = V_MOV_B32_e32 5.000000e+00, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = V_CMP_GE_F32_e64 %VGPR2, %VGPR3, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR8_SGPR9<def> = V_CMP_U_F32_e64 %VGPR2, %VGPR2, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR0_SGPR1<def> = S_OR_B64 %SGPR0_SGPR1<kill>, %SGPR8_SGPR9<kill>
	%VGPR2<def> = V_CNDMASK_B32_e64 %VGPR2<kill>, %VGPR3<kill>, %SGPR0_SGPR1<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%VGPR2<def> = V_ADD_F32_e64 %VGPR2<kill>, 0, 1, 0, 0, 0, %EXEC<imp-use>
	%VGPR2<def> = V_ADD_F32_e64 0, %VGPR2<kill>, 0, 1, 0, 0, %EXEC<imp-use>
	%VGPR4<def> = V_INTERP_P1_F32 %VGPR0, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR3_VGPR4<imp-def>
	%VGPR4<def,tied1> = V_INTERP_P2_F32 %VGPR4<tied0>, %VGPR1, 1, 0, %M0<kill>, %EXEC<imp-use>, %VGPR3_VGPR4<imp-use,kill>, %VGPR3_VGPR4<imp-def>
	%VGPR3<def> = V_INTERP_P1_F32 %VGPR0, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR3_VGPR4<imp-use,kill>, %VGPR3_VGPR4<imp-def>
	%VGPR3<def,tied1> = V_INTERP_P2_F32 %VGPR3<tied0>, %VGPR1, 0, 0, %M0<kill>, %EXEC<imp-use>, %VGPR0_VGPR1<imp-use,kill>, %VGPR3_VGPR4<imp-use,kill>, %VGPR3_VGPR4<imp-def>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR2_SGPR3<kill>, 0; mem:LD16[%32](align=8)(tbaa=!"const")
	%SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<def> = S_LOAD_DWORDX8_IMM %SGPR4_SGPR5<kill>, 0; mem:LD32[%29](tbaa=!"const")
	S_WAITCNT 127
	%VGPR3_VGPR4_VGPR5<def> = IMAGE_SAMPLE_V3_V2 7, 0, 0, 0, 0, 0, 0, 0, %VGPR3_VGPR4<kill>, %SGPR4_SGPR5_SGPR6_SGPR7_SGPR8_SGPR9_SGPR10_SGPR11<kill>, %SGPR0_SGPR1_SGPR2_SGPR3<kill>, %EXEC<imp-use>
	S_WAITCNT 1904
	%VGPR0<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR5, %VGPR2<kill>, %EXEC<imp-use>
	%VGPR1<def> = V_CVT_PKRTZ_F16_F32_e32 %VGPR3, %VGPR4, %EXEC<imp-use>, %VGPR3_VGPR4_VGPR5<imp-use,kill>
	EXP 15, 0, 1, 1, 1, %VGPR1<kill>, %VGPR0<kill>, %VGPR1, %VGPR0, %EXEC<imp-use>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_WQM_B64 exec, exec                                                 ; BEFE0A7E
	S_MOV_B32 m0, s7                                                     ; BEFC0307
	V_INTERP_P1_F32 v3, v0, 3, 0, [m0]                                   ; C80C0300
	V_INTERP_P2_F32 v3, [v3], v1, 3, 0, [m0]                             ; C80D0301
	V_INTERP_P1_F32 v2, v0, 2, 0, [m0]                                   ; C8080200
	V_INTERP_P2_F32 v2, [v2], v1, 2, 0, [m0]                             ; C8090201
	S_LOAD_DWORDX4 s[8:11], s[2:3], 4                                    ; C0840304
	S_LOAD_DWORDX8 s[12:19], s[4:5], 8                                   ; C0C60508
	S_WAITCNT lgkmcnt(0)                                                 ; BF8C007F
	IMAGE_SAMPLE v2, 1, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[12:19], s[8:11]   ; F0800100 00430202
	S_WAITCNT vmcnt(0)                                                   ; BF8C0770
	V_ADD_F32_e64 v2, v2, 0, 1, 0, 0, 0                                  ; D2060102 02010102
	S_LOAD_DWORDX4 s[8:11], s[0:1], 0                                    ; C0840100
	S_WAITCNT lgkmcnt(0)                                                 ; BF8C007F
	S_BUFFER_LOAD_DWORD s0, s[8:11], 13                                  ; C200090D
	S_WAITCNT lgkmcnt(0)                                                 ; BF8C007F
	V_MUL_F32_e32 v2, s0, v2                                             ; 10040400
	S_BUFFER_LOAD_DWORD s0, s[8:11], 12                                  ; C200090C
	S_WAITCNT lgkmcnt(0)                                                 ; BF8C007F
	V_SUBREV_F32_e32 v2, s0, v2                                          ; 0A040400
	V_RCP_F32_e32 v2, v2                                                 ; 7E045502
	S_BUFFER_LOAD_DWORD s0, s[8:11], 4                                   ; C2000904
	S_WAITCNT lgkmcnt(0)                                                 ; BF8C007F
	V_MUL_F32_e32 v2, s0, v2                                             ; 10040400
	V_SUB_F32_e32 v2, 1.000000e+00, v2                                   ; 080404F2
	S_BUFFER_LOAD_DWORD s0, s[8:11], 5                                   ; C2000905
	S_WAITCNT lgkmcnt(0)                                                 ; BF8C007F
	V_MUL_F32_e32 v2, s0, v2                                             ; 10040400
	V_MOV_B32_e32 v3, -5.000000e+00                                      ; 7E0602FF C0A00000
	V_CMP_GE_F32_e64 s[0:1], v2, v3, 0, 0, 0, 0                          ; D00C0000 02020702
	V_CMP_U_F32_e64 s[8:9], v2, v2, 0, 0, 0, 0                           ; D0100008 02020502
	S_OR_B64 s[0:1], s[0:1], s[8:9]                                      ; 88800800
	V_CNDMASK_B32_e64 v2, v3, v2, s[0:1], 0, 0, 0, 0                     ; D2000002 00020503
	V_MOV_B32_e32 v3, 5.000000e+00                                       ; 7E0602FF 40A00000
	V_CMP_GE_F32_e64 s[0:1], v2, v3, 0, 0, 0, 0                          ; D00C0000 02020702
	V_CMP_U_F32_e64 s[8:9], v2, v2, 0, 0, 0, 0                           ; D0100008 02020502
	S_OR_B64 s[0:1], s[0:1], s[8:9]                                      ; 88800800
	V_CNDMASK_B32_e64 v2, v2, v3, s[0:1], 0, 0, 0, 0                     ; D2000002 00020702
	V_ADD_F32_e64 v2, v2, 0, 1, 0, 0, 0                                  ; D2060102 02010102
	V_ADD_F32_e64 v2, 0, v2, 0, 1, 0, 0                                  ; D2060802 02020480
	V_INTERP_P1_F32 v4, v0, 1, 0, [m0]                                   ; C8100100
	V_INTERP_P2_F32 v4, [v4], v1, 1, 0, [m0]                             ; C8110101
	V_INTERP_P1_F32 v3, v0, 0, 0, [m0]                                   ; C80C0000
	V_INTERP_P2_F32 v3, [v3], v1, 0, 0, [m0]                             ; C80D0001
	S_LOAD_DWORDX4 s[0:3], s[2:3], 0                                     ; C0800300
	S_LOAD_DWORDX8 s[4:11], s[4:5], 0                                    ; C0C20500
	S_WAITCNT lgkmcnt(0)                                                 ; BF8C007F
	IMAGE_SAMPLE v[3:5], 7, 0, 0, 0, 0, 0, 0, 0, v[3:4], s[4:11], s[0:3] ; F0800700 00010303
	S_WAITCNT vmcnt(0)                                                   ; BF8C0770
	V_CVT_PKRTZ_F16_F32_e32 v0, v5, v2                                   ; 5E000505
	V_CVT_PKRTZ_F16_F32_e32 v1, v3, v4                                   ; 5E020903
	EXP 15, 0, 1, 1, 1, v1, v0, v1, v0                                   ; F8001C0F 00010001
	S_ENDPGM                                                             ; BF810000

VERT
DCL IN[0]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[19]
DCL CONST[0..1]
DCL TEMP[0..2], LOCAL
IMM[0] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
  0: MOV TEMP[0].zw, IMM[0].yyxy
  1: MOV TEMP[0].xy, IN[0].xyxx
  2: MAD TEMP[1].xy, IN[0].zwww, CONST[0].xyyy, CONST[0].zwww
  3: MAD TEMP[2].xy, IN[0].zwww, CONST[1].xyyy, CONST[1].zwww
  4: MOV TEMP[1].zw, TEMP[2].yyxy
  5: MOV OUT[1], TEMP[1]
  6: MOV OUT[0], TEMP[0]
  7: END
; ModuleID = 'tgsi'

define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 {
main_body:
  %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0
  %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0
  %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0)
  %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4)
  %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8)
  %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12)
  %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16)
  %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20)
  %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24)
  %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28)
  %20 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 0
  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
  %22 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %21, i32 0, i32 %6)
  %23 = extractelement <4 x float> %22, i32 0
  %24 = extractelement <4 x float> %22, i32 1
  %25 = extractelement <4 x float> %22, i32 2
  %26 = extractelement <4 x float> %22, i32 3
  %27 = fmul float %25, %12
  %28 = fadd float %27, %14
  %29 = fmul float %26, %13
  %30 = fadd float %29, %15
  %31 = fmul float %25, %16
  %32 = fadd float %31, %18
  %33 = fmul float %26, %17
  %34 = fadd float %33, %19
  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %28, float %30, float %32, float %34)
  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %23, float %24, float 0.000000e+00, float 1.000000e+00)
  ret void
}

; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1

; Function Attrs: nounwind readnone
declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1

declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)

attributes #0 = { "ShaderType"="1" }
attributes #1 = { nounwind readnone }

!0 = metadata !{metadata !"const", null, i32 1}
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %SGPR0_SGPR1 in %vreg0, %SGPR6_SGPR7 in %vreg3, %VGPR0 in %vreg6

BB#0: derived from LLVM BB %main_body
    Live Ins: %SGPR0_SGPR1 %SGPR6_SGPR7 %VGPR0
	%SGPR4_SGPR5_SGPR6_SGPR7<def> = S_LOAD_DWORDX4_IMM %SGPR6_SGPR7<kill>, 0; mem:LD16[%23](align=8)(tbaa=!"const")
	S_WAITCNT 127
	%VGPR0_VGPR1_VGPR2_VGPR3<def> = BUFFER_LOAD_FORMAT_XYZW_IDXEN %SGPR4_SGPR5_SGPR6_SGPR7<kill>, %VGPR0<kill>, 0, %EXEC<imp-use>
	%SGPR0_SGPR1_SGPR2_SGPR3<def> = S_LOAD_DWORDX4_IMM %SGPR0_SGPR1<kill>, 0; mem:LD16[%11](align=8)(tbaa=!"const")
	S_WAITCNT 112
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 7; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR4<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 5; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR4<def> = V_MAD_F32 %VGPR3, %VGPR5<kill>, %VGPR4<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 6; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR5<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 4; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR5<def> = V_MAD_F32 %VGPR2, %VGPR6<kill>, %VGPR5<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 3; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR6<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 1; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%VGPR6<def> = V_MAD_F32 %VGPR3, %VGPR7<kill>, %VGPR6<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	%SGPR4<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3, 2; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR7<def> = V_MOV_B32_e32 %SGPR4<kill>, %EXEC<imp-use>
	%SGPR0<def> = S_BUFFER_LOAD_DWORD_IMM %SGPR0_SGPR1_SGPR2_SGPR3<kill>, 0; mem:LD4[<unknown>]
	S_WAITCNT 127
	%VGPR8<def> = V_MOV_B32_e32 %SGPR0<kill>, %EXEC<imp-use>
	%VGPR7<def> = V_MAD_F32 %VGPR2, %VGPR8<kill>, %VGPR7<kill>, 0, 0, 0, 0, %EXEC<imp-use>
	EXP 15, 32, 0, 0, 0, %VGPR7<kill>, %VGPR6<kill>, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>
	S_WAITCNT 1807
	%VGPR4<def> = V_MOV_B32_e32 1.000000e+00, %EXEC<imp-use>
	%VGPR5<def> = V_MOV_B32_e32 0.000000e+00, %EXEC<imp-use>
	EXP 15, 12, 0, 1, 0, %VGPR0, %VGPR1, %VGPR5<kill>, %VGPR4<kill>, %EXEC<imp-use>, %VGPR0_VGPR1_VGPR2_VGPR3<imp-use,kill>
	S_ENDPGM

# End machine code for function main.


Shader Disassembly:

	S_LOAD_DWORDX4 s[4:7], s[6:7], 0               ; C0820700
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	BUFFER_LOAD_FORMAT_XYZW v[0:3], s[4:7][v0] + 0 ; E00C2000 80010000
	S_LOAD_DWORDX4 s[0:3], s[0:1], 0               ; C0800100
	S_WAITCNT vmcnt(0) lgkmcnt(0)                  ; BF8C0070
	S_BUFFER_LOAD_DWORD s4, s[0:3], 7              ; C2020107
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v4, s4                           ; 7E080204
	S_BUFFER_LOAD_DWORD s4, s[0:3], 5              ; C2020105
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v5, s4                           ; 7E0A0204
	V_MAD_F32 v4, v3, v5, v4, 0, 0, 0, 0           ; D2820004 04120B03
	S_BUFFER_LOAD_DWORD s4, s[0:3], 6              ; C2020106
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v5, s4                           ; 7E0A0204
	S_BUFFER_LOAD_DWORD s4, s[0:3], 4              ; C2020104
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v6, s4                           ; 7E0C0204
	V_MAD_F32 v5, v2, v6, v5, 0, 0, 0, 0           ; D2820005 04160D02
	S_BUFFER_LOAD_DWORD s4, s[0:3], 3              ; C2020103
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v6, s4                           ; 7E0C0204
	S_BUFFER_LOAD_DWORD s4, s[0:3], 1              ; C2020101
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v7, s4                           ; 7E0E0204
	V_MAD_F32 v6, v3, v7, v6, 0, 0, 0, 0           ; D2820006 041A0F03
	S_BUFFER_LOAD_DWORD s4, s[0:3], 2              ; C2020102
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v7, s4                           ; 7E0E0204
	S_BUFFER_LOAD_DWORD s0, s[0:3], 0              ; C2000100
	S_WAITCNT lgkmcnt(0)                           ; BF8C007F
	V_MOV_B32_e32 v8, s0                           ; 7E100200
	V_MAD_F32 v7, v2, v8, v7, 0, 0, 0, 0           ; D2820007 041E1102
	EXP 15, 32, 0, 0, 0, v7, v6, v5, v4            ; F800020F 04050607
	S_WAITCNT expcnt(0)                            ; BF8C070F
	V_MOV_B32_e32 v4, 1.000000e+00                 ; 7E0802F2
	V_MOV_B32_e32 v5, 0.000000e+00                 ; 7E0A0280
	EXP 15, 12, 0, 1, 0, v0, v1, v5, v4            ; F80008CF 04050100
	S_ENDPGM                                       ; BF810000