[  525.971101] [drm:i915_runtime_suspend], Suspending device
[  525.995135] [drm:i915_runtime_resume], Resuming device
[  525.997086] [drm:i915_runtime_suspend], Suspending device
[  526.021126] [drm:i915_runtime_resume], Resuming device
[  526.023084] [drm:i915_runtime_suspend], Suspending device
[  526.047116] [drm:i915_runtime_resume], Resuming device
[  526.049063] [drm:i915_runtime_suspend], Suspending device
[  526.073105] [drm:i915_runtime_resume], Resuming device
[  526.075063] [drm:i915_runtime_suspend], Suspending device
[  526.099096] [drm:i915_runtime_resume], Resuming device
[  526.101056] [drm:i915_runtime_suspend], Suspending device
[  526.125064] [drm:i915_runtime_resume], Resuming device
[  526.127046] [drm:i915_runtime_suspend], Suspending device
[  526.151078] [drm:i915_runtime_resume], Resuming device
[  526.153027] [drm:i915_runtime_suspend], Suspending device
[  526.177068] [drm:i915_runtime_resume], Resuming device
[  526.179028] [drm:i915_runtime_suspend], Suspending device
[  526.203071] [drm:i915_runtime_resume], Resuming device
[  526.205010] [drm:i915_runtime_suspend], Suspending device
[  526.229048] [drm:i915_runtime_resume], Resuming device
[  526.231004] [drm:i915_runtime_suspend], Suspending device
[  526.255042] [drm:i915_runtime_resume], Resuming device
[  526.256991] [drm:i915_runtime_suspend], Suspending device
[  526.281033] [drm:i915_runtime_resume], Resuming device
[  526.282986] [drm:i915_runtime_suspend], Suspending device
[  526.307022] [drm:i915_runtime_resume], Resuming device
[  526.308971] [drm:i915_runtime_suspend], Suspending device
[  526.333011] [drm:i915_runtime_resume], Resuming device
[  526.334966] [drm:i915_runtime_suspend], Suspending device
[  526.358979] [drm:i915_runtime_resume], Resuming device
[  526.360952] [drm:i915_runtime_suspend], Suspending device
[  526.384994] [drm:i915_runtime_resume], Resuming device
[  526.386950] [drm:i915_runtime_suspend], Suspending device
[  526.410964] [drm:i915_runtime_resume], Resuming device
[  526.412934] [drm:i915_runtime_suspend], Suspending device
[  526.436955] [drm:i915_runtime_resume], Resuming device
[  526.442858] [drm:i915_runtime_suspend], Suspending device
[  526.466947] [drm:i915_runtime_resume], Resuming device
[  526.468918] [drm:i915_runtime_suspend], Suspending device
[  526.492960] [drm:i915_runtime_resume], Resuming device
[  526.494905] [drm:i915_runtime_suspend], Suspending device
[  526.518939] [drm:i915_runtime_resume], Resuming device
[  526.524829] [drm:i915_runtime_suspend], Suspending device
[  526.548951] [drm:i915_runtime_resume], Resuming device
[  526.550885] [drm:i915_runtime_suspend], Suspending device
[  526.574901] [drm:i915_runtime_resume], Resuming device
[  526.580808] [drm:i915_runtime_suspend], Suspending device
[  526.604913] [drm:i915_runtime_resume], Resuming device
[  526.606870] [drm:i915_runtime_suspend], Suspending device
[  526.630901] [drm:i915_runtime_resume], Resuming device
[  526.632855] [drm:i915_runtime_suspend], Suspending device
[  526.656890] [drm:i915_runtime_resume], Resuming device
[  526.663782] [drm:i915_runtime_suspend], Suspending device
[  526.687857] [drm:i915_runtime_resume], Resuming device
[  526.689833] [drm:i915_runtime_suspend], Suspending device
[  526.713882] [drm:i915_runtime_resume], Resuming device
[  526.715824] [drm:i915_runtime_suspend], Suspending device
[  526.739867] [drm:i915_runtime_resume], Resuming device
[  526.745752] [drm:i915_runtime_suspend], Suspending device
[  526.769853] [drm:i915_runtime_resume], Resuming device
[  526.771810] [drm:i915_runtime_suspend], Suspending device
[  526.795821] [drm:i915_runtime_resume], Resuming device
[  526.797797] [drm:i915_runtime_suspend], Suspending device
[  526.821830] [drm:i915_runtime_resume], Resuming device
[  526.824664] [drm:drm_mode_setcrtc], [CRTC:3]
[  526.824690] [drm:drm_mode_setcrtc], [CONNECTOR:10:eDP-1]
[  526.824695] [drm:intel_crtc_set_config], [CRTC:3] [FB:21] #connectors=1 (x y) (0 0)
[  526.824699] [drm:intel_set_config_compute_mode_changes], inactive crtc, full mode set
[  526.824702] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:3], mode_changed=1, fb_changed=0
[  526.824705] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
[  526.824708] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
[  526.824717] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
[  526.824733] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
[  526.824741] [drm:connected_sink_compute_bpp], [CONNECTOR:10:eDP-1] checking for sink bpp constrains
[  526.824747] [drm:intel_dp_compute_config], DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
[  526.824756] [drm:intel_dp_compute_config], DP link bw 0a lane count 2 clock 270000 bpp 24
[  526.824759] [drm:intel_dp_compute_config], DP link bw required 333072 available 432000
[  526.824763] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 24, dithering: 0
[  526.824766] [drm:intel_dump_pipe_config], [CRTC:3][modeset] config for pipe A
[  526.824768] [drm:intel_dump_pipe_config], cpu_transcoder: P
[  526.824770] [drm:intel_dump_pipe_config], pipe bpp: 24, dithering: 0
[  526.824773] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
[  526.824777] [drm:intel_dump_pipe_config], dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
[  526.824779] [drm:intel_dump_pipe_config], requested mode:
[  526.824784] [drm:drm_mode_debug_printmodeline], Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
[  526.824786] [drm:intel_dump_pipe_config], adjusted mode:
[  526.824800] [drm:drm_mode_debug_printmodeline], Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
[  526.824815] [drm:intel_dump_crtc_timings], crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
[  526.824828] [drm:intel_dump_pipe_config], port clock: 270000
[  526.824833] [drm:intel_dump_pipe_config], pipe src size: 1920x1080
[  526.824836] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
[  526.824839] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000, disabled
[  526.824841] [drm:intel_dump_pipe_config], ips: 1
[  526.824843] [drm:intel_dump_pipe_config], double wide: 0
[  526.824849] [drm:__hsw_disable_package_c8], Disabling package C8+
[  526.869906] [drm:ironlake_update_plane], Writing base 00C91000 00000000 0 0 7680
[  526.869916] [drm:intel_edp_psr_match_conditions], crtc not active for PSR
[  526.869922] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:0:1920x1080]
[  526.869926] [drm:intel_ddi_mode_set], Preparing DDI mode on port A, pipe A
[  526.869929] [drm:ironlake_edp_panel_on], Turn eDP power on
[  526.869935] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
[  526.869940] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000
[  526.869943] [drm:ironlake_wait_panel_status], Wait complete
[  526.869948] [drm:ironlake_wait_panel_on], Wait for panel power on
[  526.869952] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0003
[  527.001708] [drm:ironlake_wait_panel_status], Wait complete
[  527.002864] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
[  527.003328] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
[  527.003780] [drm:intel_dp_start_link_train], clock recovery OK
[  527.004541] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful
[  527.056596] [drm:g4x_wait_for_vblank], vblank wait timed out
[  527.056774] [drm:ironlake_edp_backlight_on], 
[  527.058600] [drm:intel_panel_enable_backlight], pipe A
[  527.058608] [drm:intel_panel_actually_set_backlight], set backlight PWM = 765
[  527.058618] [drm:intel_edp_psr_match_conditions], PSR condition failed: fb not tiled or fenced
[  527.090585] [drm:intel_update_fbc], framebuffer not tiled or fenced, disabling compression
[  527.108581] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
[  527.108587] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
[  527.108592] [drm:check_encoder_state], [ENCODER:17:TMDS-17]
[  527.108596] [drm:check_crtc_state], [CRTC:3]
[  527.108606] [drm:check_crtc_state], [CRTC:5]
[  527.108610] [drm:check_crtc_state], [CRTC:7]
[  527.108675] [drm:drm_mode_setcrtc], [CRTC:3]
[  527.108682] [drm:drm_mode_setcrtc], [CONNECTOR:10:eDP-1]
[  527.108687] [drm:intel_crtc_set_config], [CRTC:3] [FB:21] #connectors=1 (x y) (0 0)
[  527.108692] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:3], mode_changed=0, fb_changed=0
[  527.108697] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
[  527.108706] [drm:drm_mode_getresources], CRTC[3] CONNECTORS[2] ENCODERS[2]
[  527.108714] [drm:drm_mode_getresources], CRTC[3] CONNECTORS[2] ENCODERS[2]
[  527.108722] [drm:drm_mode_getconnector], [CONNECTOR:10:?]
[  527.108726] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:10:eDP-1]
[  527.108731] [drm:intel_dp_detect], [CONNECTOR:10:eDP-1]
[  527.108738] [drm:ironlake_edp_panel_vdd_on], Turning eDP VDD on
[  527.108747] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f
[  527.108933] [drm:intel_dp_probe_oui], Sink OUI: 001cf8
[  527.109102] [drm:intel_dp_probe_oui], Branch OUI: 000000
[  527.109116] [drm:drm_edid_to_eld], ELD: no CEA Extension found
[  527.109122] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:10:eDP-1] probed modes :
[  527.109129] [drm:drm_mode_debug_printmodeline], Modeline 11:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
[  527.109135] [drm:drm_mode_getconnector], [CONNECTOR:10:?]
[  527.109177] [drm:drm_mode_getconnector], [CONNECTOR:18:?]
[  527.109181] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:18:HDMI-A-1]
[  527.109186] [drm:intel_hdmi_detect], [CONNECTOR:18:HDMI-A-1]
[  527.109357] [drm:gmbus_xfer], GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1)
[  527.109361] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpc
[  527.109365] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:18:HDMI-A-1] disconnected
[  527.109371] [drm:drm_mode_getconnector], [CONNECTOR:18:?]
[  527.109375] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:18:HDMI-A-1]
[  527.109379] [drm:intel_hdmi_detect], [CONNECTOR:18:HDMI-A-1]
[  527.109544] [drm:gmbus_xfer], GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1)
[  527.109548] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpc
[  527.109552] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:18:HDMI-A-1] disconnected
[  527.109603] [drm:drm_mode_setcrtc], [CRTC:3]
[  527.109616] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
[  527.109630] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:3], mode_changed=1, fb_changed=0
[  527.109645] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC]
[  527.109659] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
[  527.109673] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
[  527.109689] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 1
[  527.143571] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
[  527.143580] [drm:ironlake_edp_backlight_off], 
[  527.358772] [drm:ironlake_edp_panel_off], Turn eDP power off
[  527.358785] [drm:ironlake_wait_panel_off], Wait for panel power off time
[  527.358796] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0008
[  528.194286] [drm:ironlake_wait_panel_status], Wait complete
[  528.194304] [drm:intel_update_fbc], no output, disabling
[  528.194322] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
[  528.194326] [drm:check_encoder_state], [ENCODER:17:TMDS-17]
[  528.194330] [drm:check_crtc_state], [CRTC:3]
[  528.194335] [drm:check_crtc_state], [CRTC:5]
[  528.194338] [drm:check_crtc_state], [CRTC:7]
[  528.194352] [drm:drm_mode_setcrtc], [CRTC:5]
[  528.194356] [drm:intel_crtc_set_config], [CRTC:5] [NOFB]
[  528.194361] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:5], mode_changed=0, fb_changed=0
[  528.194365] [drm:drm_mode_setcrtc], [CRTC:7]
[  528.194369] [drm:intel_crtc_set_config], [CRTC:7] [NOFB]
[  528.194373] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:7], mode_changed=0, fb_changed=0
[  530.112588] [drm:ironlake_panel_vdd_off_sync], Turning eDP VDD off
[  530.112603] [drm:ironlake_panel_vdd_off_sync], PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0000
[  533.207466] [drm:hsw_enable_pc8_work], Enabling package C8+
[  533.215468] [drm:i915_runtime_suspend], Suspending device
[  533.300218] [drm:drm_mode_getresources], CRTC[3] CONNECTORS[2] ENCODERS[2]
[  533.300230] [drm:drm_mode_getresources], CRTC[3] CONNECTORS[2] ENCODERS[2]
[  533.300239] [drm:drm_mode_getconnector], [CONNECTOR:10:?]
[  533.300244] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:10:eDP-1]
[  533.310484] [drm:i915_runtime_resume], Resuming device
[  533.312423] [drm:intel_dp_detect], [CONNECTOR:10:eDP-1]
[  533.312433] [drm:ironlake_edp_panel_vdd_on], Turning eDP VDD on
[  533.312439] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
[  533.312446] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000
[  533.312451] [drm:ironlake_wait_panel_status], Wait complete
[  533.312460] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008
[  533.312466] [drm:ironlake_edp_panel_vdd_on], eDP was not running
[  533.433389] [drm:__hsw_disable_package_c8], Disabling package C8+
[  533.463451] [drm:intel_dp_probe_oui], Sink OUI: 001cf8
[  533.463624] [drm:intel_dp_probe_oui], Branch OUI: 000000
[  533.463641] [drm:drm_edid_to_eld], ELD: no CEA Extension found
[  533.463648] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:10:eDP-1] probed modes :
[  533.463656] [drm:drm_mode_debug_printmodeline], Modeline 11:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
[  533.463669] [drm:drm_mode_getconnector], [CONNECTOR:10:?]
[  533.463714] [drm:drm_mode_getconnector], [CONNECTOR:18:?]
[  533.463719] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:18:HDMI-A-1]
[  533.463723] [drm:intel_hdmi_detect], [CONNECTOR:18:HDMI-A-1]
[  533.463889] [drm:gmbus_xfer], GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1)
[  533.463894] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpc
[  533.463898] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:18:HDMI-A-1] disconnected
[  533.463904] [drm:drm_mode_getconnector], [CONNECTOR:18:?]
[  533.463908] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:18:HDMI-A-1]
[  533.463911] [drm:intel_hdmi_detect], [CONNECTOR:18:HDMI-A-1]
[  533.464077] [drm:gmbus_xfer], GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1)
[  533.464081] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpc
[  533.464085] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:18:HDMI-A-1] disconnected
[  536.470298] [drm:ironlake_panel_vdd_off_sync], Turning eDP VDD off
[  536.470313] [drm:ironlake_panel_vdd_off_sync], PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0000
[  538.469538] [drm:hsw_enable_pc8_work], Enabling package C8+
[  538.477527] [drm:i915_runtime_suspend], Suspending device
[  538.568935] [drm:drm_mode_setcrtc], [CRTC:3]
[  538.568945] [drm:drm_mode_setcrtc], [CONNECTOR:10:eDP-1]
[  538.568950] [drm:intel_crtc_set_config], [CRTC:3] [FB:21] #connectors=1 (x y) (0 0)
[  538.568954] [drm:intel_set_config_compute_mode_changes], inactive crtc, full mode set
[  538.568957] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:3], mode_changed=1, fb_changed=0
[  538.568959] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
[  538.568963] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
[  538.568965] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
[  538.568970] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
[  538.568973] [drm:connected_sink_compute_bpp], [CONNECTOR:10:eDP-1] checking for sink bpp constrains
[  538.568979] [drm:intel_dp_compute_config], DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
[  538.568988] [drm:intel_dp_compute_config], DP link bw 0a lane count 2 clock 270000 bpp 24
[  538.568991] [drm:intel_dp_compute_config], DP link bw required 333072 available 432000
[  538.568995] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 24, dithering: 0
[  538.568998] [drm:intel_dump_pipe_config], [CRTC:3][modeset] config for pipe A
[  538.569000] [drm:intel_dump_pipe_config], cpu_transcoder: P
[  538.569003] [drm:intel_dump_pipe_config], pipe bpp: 24, dithering: 0
[  538.569006] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
[  538.569010] [drm:intel_dump_pipe_config], dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
[  538.569012] [drm:intel_dump_pipe_config], requested mode:
[  538.569017] [drm:drm_mode_debug_printmodeline], Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
[  538.569019] [drm:intel_dump_pipe_config], adjusted mode:
[  538.569023] [drm:drm_mode_debug_printmodeline], Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
[  538.569027] [drm:intel_dump_crtc_timings], crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
[  538.569029] [drm:intel_dump_pipe_config], port clock: 270000
[  538.569032] [drm:intel_dump_pipe_config], pipe src size: 1920x1080
[  538.569035] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
[  538.569038] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000, disabled
[  538.569040] [drm:intel_dump_pipe_config], ips: 1
[  538.569042] [drm:intel_dump_pipe_config], double wide: 0
[  538.569048] [drm:__hsw_disable_package_c8], Disabling package C8+
[  538.579520] [drm:i915_runtime_resume], Resuming device
[  538.609499] [drm:ironlake_update_plane], Writing base 00C91000 00000000 0 0 7680
[  538.609508] [drm:intel_edp_psr_match_conditions], crtc not active for PSR
[  538.609513] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:0:1920x1080]
[  538.609517] [drm:intel_ddi_mode_set], Preparing DDI mode on port A, pipe A
[  538.609520] [drm:ironlake_edp_panel_on], Turn eDP power on
[  538.609525] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
[  538.609530] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000
[  538.609533] [drm:ironlake_wait_panel_status], Wait complete
[  538.609538] [drm:ironlake_wait_panel_on], Wait for panel power on
[  538.609543] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0003
[  538.741427] [drm:ironlake_wait_panel_status], Wait complete
[  538.742534] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
[  538.742996] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
[  538.743451] [drm:intel_dp_start_link_train], clock recovery OK
[  538.744212] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful
[  538.796433] [drm:g4x_wait_for_vblank], vblank wait timed out
[  538.796628] [drm:ironlake_edp_backlight_on], 
[  538.798388] [drm:intel_panel_enable_backlight], pipe A
[  538.798399] [drm:intel_panel_actually_set_backlight], set backlight PWM = 765
[  538.798409] [drm:intel_edp_psr_match_conditions], PSR condition failed: fb not tiled or fenced
[  538.830370] [drm:intel_update_fbc], framebuffer not tiled or fenced, disabling compression
[  538.848368] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
[  538.848375] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
[  538.848379] [drm:check_encoder_state], [ENCODER:17:TMDS-17]
[  538.848382] [drm:check_crtc_state], [CRTC:3]
[  538.848391] [drm:check_crtc_state], [CRTC:5]
[  538.848394] [drm:check_crtc_state], [CRTC:7]
[  538.848414] [drm:drm_mode_getresources], CRTC[3] CONNECTORS[2] ENCODERS[2]
[  538.848421] [drm:drm_mode_getresources], CRTC[3] CONNECTORS[2] ENCODERS[2]
[  538.848427] [drm:drm_mode_getconnector], [CONNECTOR:10:?]
[  538.848431] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:10:eDP-1]
[  538.848435] [drm:intel_dp_detect], [CONNECTOR:10:eDP-1]
[  538.848440] [drm:ironlake_edp_panel_vdd_on], Turning eDP VDD on
[  538.848449] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f
[  538.848628] [drm:intel_dp_probe_oui], Sink OUI: 001cf8
[  538.848797] [drm:intel_dp_probe_oui], Branch OUI: 000000
[  538.848813] [drm:drm_edid_to_eld], ELD: no CEA Extension found
[  538.848819] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:10:eDP-1] probed modes :
[  538.848827] [drm:drm_mode_debug_printmodeline], Modeline 11:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
[  538.848832] [drm:drm_mode_getconnector], [CONNECTOR:10:?]
[  538.848872] [drm:drm_mode_getconnector], [CONNECTOR:18:?]
[  538.848877] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:18:HDMI-A-1]
[  538.848881] [drm:intel_hdmi_detect], [CONNECTOR:18:HDMI-A-1]
[  538.849047] [drm:gmbus_xfer], GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1)
[  538.849050] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpc
[  538.849055] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:18:HDMI-A-1] disconnected
[  538.849060] [drm:drm_mode_getconnector], [CONNECTOR:18:?]
[  538.849064] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:18:HDMI-A-1]
[  538.849068] [drm:intel_hdmi_detect], [CONNECTOR:18:HDMI-A-1]
[  538.849233] [drm:gmbus_xfer], GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1)
[  538.849237] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpc
[  538.849241] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:18:HDMI-A-1] disconnected
[  538.849353] [drm:drm_mode_setcrtc], [CRTC:3]
[  538.849366] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
[  538.849379] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:3], mode_changed=1, fb_changed=0
[  538.849388] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC]
[  538.849401] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
[  538.849411] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
[  538.849427] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 1
[  538.883434] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
[  538.883446] [drm:ironlake_edp_backlight_off], 
[  539.098525] [drm:ironlake_edp_panel_off], Turn eDP power off
[  539.098537] [drm:ironlake_wait_panel_off], Wait for panel power off time
[  539.098548] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0008
[  539.890044] [drm:ironlake_wait_panel_status], Wait complete
[  539.890063] [drm:intel_update_fbc], no output, disabling
[  539.890082] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
[  539.890086] [drm:check_encoder_state], [ENCODER:17:TMDS-17]
[  539.890090] [drm:check_crtc_state], [CRTC:3]
[  539.890095] [drm:check_crtc_state], [CRTC:5]
[  539.890098] [drm:check_crtc_state], [CRTC:7]
[  539.890112] [drm:drm_mode_setcrtc], [CRTC:5]
[  539.890116] [drm:intel_crtc_set_config], [CRTC:5] [NOFB]
[  539.890121] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:5], mode_changed=0, fb_changed=0
[  539.890126] [drm:drm_mode_setcrtc], [CRTC:7]
[  539.890130] [drm:intel_crtc_set_config], [CRTC:7] [NOFB]
[  539.890134] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:7], mode_changed=0, fb_changed=0
[  541.852391] [drm:ironlake_panel_vdd_off_sync], Turning eDP VDD off
[  541.852406] [drm:ironlake_panel_vdd_off_sync], PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0000
[  544.899254] [drm:hsw_enable_pc8_work], Enabling package C8+
[  544.907251] [drm:i915_runtime_suspend], Suspending device
[  544.996249] [drm:drm_mode_setcrtc], [CRTC:3]
[  544.996261] [drm:drm_mode_setcrtc], [CONNECTOR:10:eDP-1]
[  544.996267] [drm:intel_crtc_set_config], [CRTC:3] [FB:21] #connectors=1 (x y) (0 0)
[  544.996272] [drm:intel_set_config_compute_mode_changes], inactive crtc, full mode set
[  544.996276] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:3], mode_changed=1, fb_changed=0
[  544.996279] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
[  544.996284] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
[  544.996287] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
[  544.996292] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
[  544.996297] [drm:connected_sink_compute_bpp], [CONNECTOR:10:eDP-1] checking for sink bpp constrains
[  544.996303] [drm:intel_dp_compute_config], DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
[  544.996314] [drm:intel_dp_compute_config], DP link bw 0a lane count 2 clock 270000 bpp 24
[  544.996317] [drm:intel_dp_compute_config], DP link bw required 333072 available 432000
[  544.996322] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 24, dithering: 0
[  544.996325] [drm:intel_dump_pipe_config], [CRTC:3][modeset] config for pipe A
[  544.996329] [drm:intel_dump_pipe_config], cpu_transcoder: P
[  544.996332] [drm:intel_dump_pipe_config], pipe bpp: 24, dithering: 0
[  544.996336] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
[  544.996340] [drm:intel_dump_pipe_config], dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
[  544.996343] [drm:intel_dump_pipe_config], requested mode:
[  544.996349] [drm:drm_mode_debug_printmodeline], Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
[  544.996352] [drm:intel_dump_pipe_config], adjusted mode:
[  544.996357] [drm:drm_mode_debug_printmodeline], Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
[  544.996362] [drm:intel_dump_crtc_timings], crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
[  544.996365] [drm:intel_dump_pipe_config], port clock: 270000
[  544.996368] [drm:intel_dump_pipe_config], pipe src size: 1920x1080
[  544.996372] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
[  544.996375] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000, disabled
[  544.996378] [drm:intel_dump_pipe_config], ips: 1
[  544.996381] [drm:intel_dump_pipe_config], double wide: 0
[  544.996389] [drm:__hsw_disable_package_c8], Disabling package C8+
[  545.007266] [drm:i915_runtime_resume], Resuming device
[  545.053202] [drm:ironlake_update_plane], Writing base 00C91000 00000000 0 0 7680
[  545.053212] [drm:intel_edp_psr_match_conditions], crtc not active for PSR
[  545.053220] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:0:1920x1080]
[  545.053224] [drm:intel_ddi_mode_set], Preparing DDI mode on port A, pipe A
[  545.053228] [drm:ironlake_edp_panel_on], Turn eDP power on
[  545.053235] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
[  545.053243] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000
[  545.053249] [drm:ironlake_wait_panel_status], Wait complete
[  545.053255] [drm:ironlake_wait_panel_on], Wait for panel power on
[  545.053261] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0003
[  545.185128] [drm:ironlake_wait_panel_status], Wait complete
[  545.186294] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
[  545.186759] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
[  545.187215] [drm:intel_dp_start_link_train], clock recovery OK
[  545.187985] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful
[  545.240104] [drm:g4x_wait_for_vblank], vblank wait timed out
[  545.240300] [drm:ironlake_edp_backlight_on], 
[  545.242059] [drm:intel_panel_enable_backlight], pipe A
[  545.242069] [drm:intel_panel_actually_set_backlight], set backlight PWM = 765
[  545.242079] [drm:intel_edp_psr_match_conditions], PSR condition failed: fb not tiled or fenced
[  545.274041] [drm:intel_update_fbc], framebuffer not tiled or fenced, disabling compression
[  545.292038] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
[  545.292046] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
[  545.292049] [drm:check_encoder_state], [ENCODER:17:TMDS-17]
[  545.292052] [drm:check_crtc_state], [CRTC:3]
[  545.292062] [drm:check_crtc_state], [CRTC:5]
[  545.292064] [drm:check_crtc_state], [CRTC:7]
[  545.292111] [drm:drm_mode_setcrtc], [CRTC:3]
[  545.292114] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
[  545.292118] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:3], mode_changed=1, fb_changed=0
[  545.292121] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC]
[  545.292123] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
[  545.292125] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
[  545.292129] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 1
[  545.326080] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
[  545.326091] [drm:ironlake_edp_backlight_off], 
[  545.541196] [drm:ironlake_edp_panel_off], Turn eDP power off
[  545.541209] [drm:ironlake_wait_panel_off], Wait for panel power off time
[  545.541220] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000
[  546.387643] [drm:ironlake_wait_panel_status], Wait complete
[  546.387660] [drm:intel_update_fbc], no output, disabling
[  546.387675] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
[  546.387679] [drm:check_encoder_state], [ENCODER:17:TMDS-17]
[  546.387682] [drm:check_crtc_state], [CRTC:3]
[  546.387685] [drm:check_crtc_state], [CRTC:5]
[  546.387688] [drm:check_crtc_state], [CRTC:7]
[  546.387699] [drm:drm_mode_setcrtc], [CRTC:5]
[  546.387702] [drm:intel_crtc_set_config], [CRTC:5] [NOFB]
[  546.387706] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:5], mode_changed=0, fb_changed=0
[  546.387709] [drm:drm_mode_setcrtc], [CRTC:7]
[  546.387711] [drm:intel_crtc_set_config], [CRTC:7] [NOFB]
[  546.387714] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:7], mode_changed=0, fb_changed=0
[  551.392899] [drm:hsw_enable_pc8_work], Enabling package C8+
[  551.400904] [drm:i915_runtime_suspend], Suspending device
[  551.493848] [drm:drm_mode_setcrtc], [CRTC:3]
[  551.493860] [drm:drm_mode_setcrtc], [CONNECTOR:10:eDP-1]
[  551.493865] [drm:intel_crtc_set_config], [CRTC:3] [FB:21] #connectors=1 (x y) (0 0)
[  551.493868] [drm:intel_set_config_compute_mode_changes], inactive crtc, full mode set
[  551.493872] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:3], mode_changed=1, fb_changed=0
[  551.493874] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
[  551.493878] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
[  551.493880] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
[  551.493884] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
[  551.493888] [drm:connected_sink_compute_bpp], [CONNECTOR:10:eDP-1] checking for sink bpp constrains
[  551.493893] [drm:intel_dp_compute_config], DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
[  551.493903] [drm:intel_dp_compute_config], DP link bw 0a lane count 2 clock 270000 bpp 24
[  551.493905] [drm:intel_dp_compute_config], DP link bw required 333072 available 432000
[  551.493909] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 24, dithering: 0
[  551.493912] [drm:intel_dump_pipe_config], [CRTC:3][modeset] config for pipe A
[  551.493914] [drm:intel_dump_pipe_config], cpu_transcoder: P
[  551.493917] [drm:intel_dump_pipe_config], pipe bpp: 24, dithering: 0
[  551.493920] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
[  551.493923] [drm:intel_dump_pipe_config], dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
[  551.493925] [drm:intel_dump_pipe_config], requested mode:
[  551.493930] [drm:drm_mode_debug_printmodeline], Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
[  551.493932] [drm:intel_dump_pipe_config], adjusted mode:
[  551.493953] [drm:drm_mode_debug_printmodeline], Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
[  551.493957] [drm:intel_dump_crtc_timings], crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
[  551.493960] [drm:intel_dump_pipe_config], port clock: 270000
[  551.493962] [drm:intel_dump_pipe_config], pipe src size: 1920x1080
[  551.493965] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
[  551.493968] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000, disabled
[  551.493970] [drm:intel_dump_pipe_config], ips: 1
[  551.493972] [drm:intel_dump_pipe_config], double wide: 0
[  551.493978] [drm:__hsw_disable_package_c8], Disabling package C8+
[  551.504908] [drm:i915_runtime_resume], Resuming device
[  551.550868] [drm:ironlake_update_plane], Writing base 00C91000 00000000 0 0 7680
[  551.550878] [drm:intel_edp_psr_match_conditions], crtc not active for PSR
[  551.550885] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:0:1920x1080]
[  551.550890] [drm:intel_ddi_mode_set], Preparing DDI mode on port A, pipe A
[  551.550894] [drm:ironlake_edp_panel_on], Turn eDP power on
[  551.550901] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
[  551.550907] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000
[  551.550912] [drm:ironlake_wait_panel_status], Wait complete
[  551.550918] [drm:ironlake_wait_panel_on], Wait for panel power on
[  551.550924] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 9000000a control abcd0003
[  551.682788] [drm:ironlake_wait_panel_status], Wait complete
[  551.683945] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
[  551.684409] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
[  551.684866] [drm:intel_dp_start_link_train], clock recovery OK
[  551.685629] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful
[  551.737755] [drm:g4x_wait_for_vblank], vblank wait timed out
[  551.737951] [drm:ironlake_edp_backlight_on], 
[  551.739763] [drm:intel_panel_enable_backlight], pipe A
[  551.739774] [drm:intel_panel_actually_set_backlight], set backlight PWM = 765
[  551.739785] [drm:intel_edp_psr_match_conditions], PSR condition failed: fb not tiled or fenced
[  551.771753] [drm:intel_update_fbc], framebuffer not tiled or fenced, disabling compression
[  551.789747] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
[  551.789756] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
[  551.789760] [drm:check_encoder_state], [ENCODER:17:TMDS-17]
[  551.789765] [drm:check_crtc_state], [CRTC:3]
[  551.789776] [drm:check_crtc_state], [CRTC:5]
[  551.789780] [drm:check_crtc_state], [CRTC:7]
[  551.789854] [drm:drm_mode_setcrtc], [CRTC:3]
[  551.789858] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
[  551.789863] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:3], mode_changed=1, fb_changed=0
[  551.789867] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC]
[  551.789870] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
[  551.789873] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
[  551.789879] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 1
[  551.823735] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
[  551.823746] [drm:ironlake_edp_backlight_off], 
[  552.038851] [drm:ironlake_edp_panel_off], Turn eDP power off
[  552.038864] [drm:ironlake_wait_panel_off], Wait for panel power off time
[  552.038874] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000
[  552.885350] [drm:ironlake_wait_panel_status], Wait complete
[  552.885369] [drm:intel_update_fbc], no output, disabling
[  552.885387] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
[  552.885391] [drm:check_encoder_state], [ENCODER:17:TMDS-17]
[  552.885395] [drm:check_crtc_state], [CRTC:3]
[  552.885399] [drm:check_crtc_state], [CRTC:5]
[  552.885403] [drm:check_crtc_state], [CRTC:7]
[  552.885417] [drm:drm_mode_setcrtc], [CRTC:5]
[  552.885421] [drm:intel_crtc_set_config], [CRTC:5] [NOFB]
[  552.885426] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:5], mode_changed=0, fb_changed=0
[  552.885430] [drm:drm_mode_setcrtc], [CRTC:7]
[  552.885433] [drm:intel_crtc_set_config], [CRTC:7] [NOFB]
[  552.885437] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:7], mode_changed=0, fb_changed=0
[  557.886561] [drm:hsw_enable_pc8_work], Enabling package C8+
[  557.894545] [drm:i915_runtime_suspend], Suspending device
[  557.991461] [drm:drm_mode_setcrtc], [CRTC:3]
[  557.991473] [drm:drm_mode_setcrtc], [CONNECTOR:10:eDP-1]
[  557.991478] [drm:intel_crtc_set_config], [CRTC:3] [FB:21] #connectors=1 (x y) (0 0)
[  557.991483] [drm:intel_set_config_compute_mode_changes], inactive crtc, full mode set
[  557.991487] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:3], mode_changed=1, fb_changed=0
[  557.991490] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
[  557.991494] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
[  557.991497] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
[  557.991503] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
[  557.991508] [drm:connected_sink_compute_bpp], [CONNECTOR:10:eDP-1] checking for sink bpp constrains
[  557.991514] [drm:intel_dp_compute_config], DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
[  557.991525] [drm:intel_dp_compute_config], DP link bw 0a lane count 2 clock 270000 bpp 24
[  557.991528] [drm:intel_dp_compute_config], DP link bw required 333072 available 432000
[  557.991533] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 24, dithering: 0
[  557.991537] [drm:intel_dump_pipe_config], [CRTC:3][modeset] config for pipe A
[  557.991540] [drm:intel_dump_pipe_config], cpu_transcoder: P
[  557.991544] [drm:intel_dump_pipe_config], pipe bpp: 24, dithering: 0
[  557.991548] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
[  557.991552] [drm:intel_dump_pipe_config], dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
[  557.991555] [drm:intel_dump_pipe_config], requested mode:
[  557.991561] [drm:drm_mode_debug_printmodeline], Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
[  557.991564] [drm:intel_dump_pipe_config], adjusted mode:
[  557.991568] [drm:drm_mode_debug_printmodeline], Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
[  557.991573] [drm:intel_dump_crtc_timings], crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
[  557.991576] [drm:intel_dump_pipe_config], port clock: 270000
[  557.991579] [drm:intel_dump_pipe_config], pipe src size: 1920x1080
[  557.991583] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
[  557.991587] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000, disabled
[  557.991590] [drm:intel_dump_pipe_config], ips: 1
[  557.991593] [drm:intel_dump_pipe_config], double wide: 0
[  557.991600] [drm:__hsw_disable_package_c8], Disabling package C8+
[  558.002558] [drm:i915_runtime_resume], Resuming device
[  558.048506] [drm:ironlake_update_plane], Writing base 00C91000 00000000 0 0 7680
[  558.048517] [drm:intel_edp_psr_match_conditions], crtc not active for PSR
[  558.048524] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:0:1920x1080]
[  558.048528] [drm:intel_ddi_mode_set], Preparing DDI mode on port A, pipe A
[  558.048532] [drm:ironlake_edp_panel_on], Turn eDP power on
[  558.048538] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
[  558.048545] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000
[  558.048550] [drm:ironlake_wait_panel_status], Wait complete
[  558.048556] [drm:ironlake_wait_panel_on], Wait for panel power on
[  558.048561] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0003
[  558.180438] [drm:ironlake_wait_panel_status], Wait complete
[  558.181598] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
[  558.182063] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
[  558.182518] [drm:intel_dp_start_link_train], clock recovery OK
[  558.183281] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful
[  558.235407] [drm:g4x_wait_for_vblank], vblank wait timed out
[  558.235604] [drm:ironlake_edp_backlight_on], 
[  558.237366] [drm:intel_panel_enable_backlight], pipe A
[  558.237376] [drm:intel_panel_actually_set_backlight], set backlight PWM = 765
[  558.237386] [drm:intel_edp_psr_match_conditions], PSR condition failed: fb not tiled or fenced
[  558.269348] [drm:intel_update_fbc], framebuffer not tiled or fenced, disabling compression
[  558.287341] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
[  558.287348] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
[  558.287352] [drm:check_encoder_state], [ENCODER:17:TMDS-17]
[  558.287355] [drm:check_crtc_state], [CRTC:3]
[  558.287365] [drm:check_crtc_state], [CRTC:5]
[  558.287367] [drm:check_crtc_state], [CRTC:7]
[  558.287419] [drm:drm_mode_setcrtc], [CRTC:3]
[  558.287422] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
[  558.287426] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:3], mode_changed=1, fb_changed=0
[  558.287429] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC]
[  558.287432] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
[  558.287434] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
[  558.287438] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 1
[  558.321329] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
[  558.321338] [drm:ironlake_edp_backlight_off], 
[  558.536500] [drm:ironlake_edp_panel_off], Turn eDP power off
[  558.536513] [drm:ironlake_wait_panel_off], Wait for panel power off time
[  558.536523] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000
[  559.383002] [drm:ironlake_wait_panel_status], Wait complete
[  559.383020] [drm:intel_update_fbc], no output, disabling
[  559.383038] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
[  559.383043] [drm:check_encoder_state], [ENCODER:17:TMDS-17]
[  559.383046] [drm:check_crtc_state], [CRTC:3]
[  559.383051] [drm:check_crtc_state], [CRTC:5]
[  559.383054] [drm:check_crtc_state], [CRTC:7]
[  559.383068] [drm:drm_mode_setcrtc], [CRTC:5]
[  559.383072] [drm:intel_crtc_set_config], [CRTC:5] [NOFB]
[  559.383077] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:5], mode_changed=0, fb_changed=0
[  559.383082] [drm:drm_mode_setcrtc], [CRTC:7]
[  559.383085] [drm:intel_crtc_set_config], [CRTC:7] [NOFB]
[  559.383088] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:7], mode_changed=0, fb_changed=0
[  564.396202] [drm:hsw_enable_pc8_work], Enabling package C8+
[  564.404191] [drm:i915_runtime_suspend], Suspending device
[  564.489014] [drm:drm_mode_setcrtc], [CRTC:3]
[  564.489026] [drm:drm_mode_setcrtc], [CONNECTOR:10:eDP-1]
[  564.489031] [drm:intel_crtc_set_config], [CRTC:3] [FB:21] #connectors=1 (x y) (0 0)
[  564.489036] [drm:intel_set_config_compute_mode_changes], inactive crtc, full mode set
[  564.489040] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:3], mode_changed=1, fb_changed=0
[  564.489044] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
[  564.489048] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
[  564.489051] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
[  564.489056] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
[  564.489082] [drm:connected_sink_compute_bpp], [CONNECTOR:10:eDP-1] checking for sink bpp constrains
[  564.489089] [drm:intel_dp_compute_config], DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
[  564.489101] [drm:intel_dp_compute_config], DP link bw 0a lane count 2 clock 270000 bpp 24
[  564.489121] [drm:intel_dp_compute_config], DP link bw required 333072 available 432000
[  564.489139] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 24, dithering: 0
[  564.489157] [drm:intel_dump_pipe_config], [CRTC:3][modeset] config for pipe A
[  564.489166] [drm:intel_dump_pipe_config], cpu_transcoder: P
[  564.489170] [drm:intel_dump_pipe_config], pipe bpp: 24, dithering: 0
[  564.489175] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
[  564.489180] [drm:intel_dump_pipe_config], dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
[  564.489184] [drm:intel_dump_pipe_config], requested mode:
[  564.489189] [drm:drm_mode_debug_printmodeline], Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
[  564.489191] [drm:intel_dump_pipe_config], adjusted mode:
[  564.489195] [drm:drm_mode_debug_printmodeline], Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
[  564.489199] [drm:intel_dump_crtc_timings], crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
[  564.489202] [drm:intel_dump_pipe_config], port clock: 270000
[  564.489206] [drm:intel_dump_pipe_config], pipe src size: 1920x1080
[  564.489210] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
[  564.489213] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000, disabled
[  564.489216] [drm:intel_dump_pipe_config], ips: 1
[  564.489219] [drm:intel_dump_pipe_config], double wide: 0
[  564.489228] [drm:__hsw_disable_package_c8], Disabling package C8+
[  564.500210] [drm:i915_runtime_resume], Resuming device
[  564.540159] [drm:ironlake_update_plane], Writing base 00C91000 00000000 0 0 7680
[  564.540170] [drm:intel_edp_psr_match_conditions], crtc not active for PSR
[  564.540177] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:0:1920x1080]
[  564.540182] [drm:intel_ddi_mode_set], Preparing DDI mode on port A, pipe A
[  564.540186] [drm:ironlake_edp_panel_on], Turn eDP power on
[  564.540193] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
[  564.540199] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000
[  564.540204] [drm:ironlake_wait_panel_status], Wait complete
[  564.540210] [drm:ironlake_wait_panel_on], Wait for panel power on
[  564.540215] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0003
[  564.672086] [drm:ironlake_wait_panel_status], Wait complete
[  564.673243] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
[  564.673707] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
[  564.674162] [drm:intel_dp_start_link_train], clock recovery OK
[  564.674924] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful
[  564.727060] [drm:g4x_wait_for_vblank], vblank wait timed out
[  564.727256] [drm:ironlake_edp_backlight_on], 
[  564.729020] [drm:intel_panel_enable_backlight], pipe A
[  564.729031] [drm:intel_panel_actually_set_backlight], set backlight PWM = 765
[  564.729041] [drm:intel_edp_psr_match_conditions], PSR condition failed: fb not tiled or fenced
[  564.761001] [drm:intel_update_fbc], framebuffer not tiled or fenced, disabling compression
[  564.778994] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
[  564.779002] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
[  564.779005] [drm:check_encoder_state], [ENCODER:17:TMDS-17]
[  564.779009] [drm:check_crtc_state], [CRTC:3]
[  564.779018] [drm:check_crtc_state], [CRTC:5]
[  564.779020] [drm:check_crtc_state], [CRTC:7]
[  564.779103] [drm:drm_mode_setcrtc], [CRTC:3]
[  564.779109] [drm:drm_mode_setcrtc], [CONNECTOR:10:eDP-1]
[  564.779113] [drm:intel_crtc_set_config], [CRTC:3] [FB:21] #connectors=1 (x y) (0 0)
[  564.779117] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:3], mode_changed=0, fb_changed=0
[  564.779120] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
[  564.781589] [drm:drm_mode_setcrtc], [CRTC:3]
[  564.781593] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
[  564.781597] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:3], mode_changed=1, fb_changed=0
[  564.781600] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC]
[  564.781603] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
[  564.781606] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
[  564.781610] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 1
[  564.813035] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
[  564.813047] [drm:ironlake_edp_backlight_off], 
[  565.028163] [drm:ironlake_edp_panel_off], Turn eDP power off
[  565.028176] [drm:ironlake_wait_panel_off], Wait for panel power off time
[  565.028187] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status a0000003 control abcd0000
[  565.885652] [drm:ironlake_wait_panel_status], Wait complete
[  565.885670] [drm:intel_update_fbc], no output, disabling
[  565.885688] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
[  565.885693] [drm:check_encoder_state], [ENCODER:17:TMDS-17]
[  565.885697] [drm:check_crtc_state], [CRTC:3]
[  565.885701] [drm:check_crtc_state], [CRTC:5]
[  565.885704] [drm:check_crtc_state], [CRTC:7]
[  565.885718] [drm:drm_mode_setcrtc], [CRTC:5]
[  565.885722] [drm:intel_crtc_set_config], [CRTC:5] [NOFB]
[  565.885727] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:5], mode_changed=0, fb_changed=0
[  565.885732] [drm:drm_mode_setcrtc], [CRTC:7]
[  565.885735] [drm:intel_crtc_set_config], [CRTC:7] [NOFB]
[  565.885738] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:7], mode_changed=0, fb_changed=0
[  570.889856] [drm:hsw_enable_pc8_work], Enabling package C8+
[  570.897848] [drm:i915_runtime_suspend], Suspending device
[  571.001868] [drm:i915_runtime_resume], Resuming device
[  571.003815] [drm:i915_runtime_suspend], Suspending device
[  571.027855] [drm:i915_runtime_resume], Resuming device
[  571.029802] [drm:i915_runtime_suspend], Suspending device
[  571.053848] [drm:i915_runtime_resume], Resuming device
[  571.055798] [drm:i915_runtime_suspend], Suspending device
[  571.079838] [drm:i915_runtime_resume], Resuming device
[  571.081784] [drm:i915_runtime_suspend], Suspending device
[  571.105830] [drm:i915_runtime_resume], Resuming device
[  571.107777] [drm:i915_runtime_suspend], Suspending device
[  571.131819] [drm:i915_runtime_resume], Resuming device
[  571.133770] [drm:i915_runtime_suspend], Suspending device
[  571.157812] [drm:i915_runtime_resume], Resuming device
[  571.159761] [drm:i915_runtime_suspend], Suspending device
[  571.183800] [drm:i915_runtime_resume], Resuming device
[  571.185749] [drm:i915_runtime_suspend], Suspending device
[  571.209792] [drm:i915_runtime_resume], Resuming device
[  571.211741] [drm:i915_runtime_suspend], Suspending device
[  571.235757] [drm:i915_runtime_resume], Resuming device
[  571.237743] [drm:i915_runtime_suspend], Suspending device
[  571.261772] [drm:i915_runtime_resume], Resuming device
[  571.263724] [drm:i915_runtime_suspend], Suspending device
[  571.287763] [drm:i915_runtime_resume], Resuming device
[  571.289713] [drm:i915_runtime_suspend], Suspending device
[  571.313754] [drm:i915_runtime_resume], Resuming device
[  571.315714] [drm:i915_runtime_suspend], Suspending device
[  571.339719] [drm:i915_runtime_resume], Resuming device
[  571.341705] [drm:i915_runtime_suspend], Suspending device
[  571.365734] [drm:i915_runtime_resume], Resuming device
[  571.367686] [drm:i915_runtime_suspend], Suspending device
[  571.391725] [drm:i915_runtime_resume], Resuming device
[  571.393676] [drm:i915_runtime_suspend], Suspending device
[  571.417717] [drm:i915_runtime_resume], Resuming device
[  571.419677] [drm:i915_runtime_suspend], Suspending device
[  571.443695] [drm:i915_runtime_resume], Resuming device
[  571.445661] [drm:i915_runtime_suspend], Suspending device
[  571.469688] [drm:i915_runtime_resume], Resuming device
[  571.474050] [drm:i915_runtime_suspend], Suspending device
[  571.584653] [drm:i915_runtime_resume], Resuming device
[  571.586605] [drm:i915_runtime_suspend], Suspending device
[  571.610647] [drm:i915_runtime_resume], Resuming device
[  571.612597] [drm:i915_runtime_suspend], Suspending device
[  571.636631] [drm:i915_runtime_resume], Resuming device
[  571.638587] [drm:i915_runtime_suspend], Suspending device
[  571.662629] [drm:i915_runtime_resume], Resuming device
[  571.664581] [drm:i915_runtime_suspend], Suspending device
[  571.688612] [drm:i915_runtime_resume], Resuming device
[  571.690580] [drm:i915_runtime_suspend], Suspending device
[  571.714598] [drm:i915_runtime_resume], Resuming device
[  571.716556] [drm:i915_runtime_suspend], Suspending device
[  571.740599] [drm:i915_runtime_resume], Resuming device
[  571.742549] [drm:i915_runtime_suspend], Suspending device
[  571.766589] [drm:i915_runtime_resume], Resuming device
[  571.768551] [drm:i915_runtime_suspend], Suspending device
[  571.792581] [drm:i915_runtime_resume], Resuming device
[  571.794559] [drm:i915_runtime_suspend], Suspending device
[  571.894672] [drm:drm_mode_setcrtc], [CRTC:3]
[  571.894684] [drm:drm_mode_setcrtc], [CONNECTOR:10:eDP-1]
[  571.894690] [drm:intel_crtc_set_config], [CRTC:3] [FB:21] #connectors=1 (x y) (0 0)
[  571.894695] [drm:intel_set_config_compute_mode_changes], inactive crtc, full mode set
[  571.894699] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:3], mode_changed=1, fb_changed=0
[  571.894702] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
[  571.894707] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
[  571.894710] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
[  571.894715] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
[  571.894720] [drm:connected_sink_compute_bpp], [CONNECTOR:10:eDP-1] checking for sink bpp constrains
[  571.894726] [drm:intel_dp_compute_config], DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
[  571.894737] [drm:intel_dp_compute_config], DP link bw 0a lane count 2 clock 270000 bpp 24
[  571.894740] [drm:intel_dp_compute_config], DP link bw required 333072 available 432000
[  571.894745] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 24, dithering: 0
[  571.894749] [drm:intel_dump_pipe_config], [CRTC:3][modeset] config for pipe A
[  571.894753] [drm:intel_dump_pipe_config], cpu_transcoder: P
[  571.894756] [drm:intel_dump_pipe_config], pipe bpp: 24, dithering: 0
[  571.894760] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
[  571.894765] [drm:intel_dump_pipe_config], dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
[  571.894768] [drm:intel_dump_pipe_config], requested mode:
[  571.894773] [drm:drm_mode_debug_printmodeline], Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
[  571.894776] [drm:intel_dump_pipe_config], adjusted mode:
[  571.894781] [drm:drm_mode_debug_printmodeline], Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
[  571.894786] [drm:intel_dump_crtc_timings], crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
[  571.894789] [drm:intel_dump_pipe_config], port clock: 270000
[  571.894792] [drm:intel_dump_pipe_config], pipe src size: 1920x1080
[  571.894796] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
[  571.894799] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000, disabled
[  571.894802] [drm:intel_dump_pipe_config], ips: 1
[  571.894805] [drm:intel_dump_pipe_config], double wide: 0
[  571.894813] [drm:__hsw_disable_package_c8], Disabling package C8+
[  571.905534] [drm:i915_runtime_resume], Resuming device
[  571.943494] [drm:ironlake_update_plane], Writing base 00C91000 00000000 0 0 7680
[  571.943504] [drm:intel_edp_psr_match_conditions], crtc not active for PSR
[  571.943512] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:0:1920x1080]
[  571.943516] [drm:intel_ddi_mode_set], Preparing DDI mode on port A, pipe A
[  571.943520] [drm:ironlake_edp_panel_on], Turn eDP power on
[  571.943526] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
[  571.943532] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000
[  571.943538] [drm:ironlake_wait_panel_status], Wait complete
[  571.943543] [drm:ironlake_wait_panel_on], Wait for panel power on
[  571.943549] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0003
[  572.075414] [drm:ironlake_wait_panel_status], Wait complete
[  572.076571] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
[  572.077036] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
[  572.077492] [drm:intel_dp_start_link_train], clock recovery OK
[  572.078255] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful
[  572.130383] [drm:g4x_wait_for_vblank], vblank wait timed out
[  572.130579] [drm:ironlake_edp_backlight_on], 
[  572.132343] [drm:intel_panel_enable_backlight], pipe A
[  572.132353] [drm:intel_panel_actually_set_backlight], set backlight PWM = 765
[  572.132363] [drm:intel_edp_psr_match_conditions], PSR condition failed: fb not tiled or fenced
[  572.164326] [drm:intel_update_fbc], framebuffer not tiled or fenced, disabling compression
[  572.182318] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
[  572.182325] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
[  572.182329] [drm:check_encoder_state], [ENCODER:17:TMDS-17]
[  572.182332] [drm:check_crtc_state], [CRTC:3]
[  572.182342] [drm:check_crtc_state], [CRTC:5]
[  572.182344] [drm:check_crtc_state], [CRTC:7]
[  572.184786] [drm:drm_mode_setcrtc], [CRTC:3]
[  572.184790] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
[  572.184793] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:3], mode_changed=1, fb_changed=0
[  572.184796] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC]
[  572.184799] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
[  572.184801] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
[  572.184805] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 1
[  572.216356] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
[  572.216368] [drm:ironlake_edp_backlight_off], 
[  572.431408] [drm:ironlake_edp_panel_off], Turn eDP power off
[  572.431419] [drm:ironlake_wait_panel_off], Wait for panel power off time
[  572.431429] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000
[  573.277983] [drm:ironlake_wait_panel_status], Wait complete
[  573.278001] [drm:intel_update_fbc], no output, disabling
[  573.278019] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
[  573.278024] [drm:check_encoder_state], [ENCODER:17:TMDS-17]
[  573.278028] [drm:check_crtc_state], [CRTC:3]
[  573.278032] [drm:check_crtc_state], [CRTC:5]
[  573.278035] [drm:check_crtc_state], [CRTC:7]
[  573.278049] [drm:drm_mode_setcrtc], [CRTC:5]
[  573.278053] [drm:intel_crtc_set_config], [CRTC:5] [NOFB]
[  573.278058] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:5], mode_changed=0, fb_changed=0
[  573.278063] [drm:drm_mode_setcrtc], [CRTC:7]
[  573.278066] [drm:intel_crtc_set_config], [CRTC:7] [NOFB]
[  573.278070] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:7], mode_changed=0, fb_changed=0
[  578.295173] [drm:hsw_enable_pc8_work], Enabling package C8+
[  578.303180] [drm:i915_runtime_suspend], Suspending device
[  578.395187] [drm:i915_runtime_resume], Resuming device
[  578.397145] [drm:i915_runtime_suspend], Suspending device
[  578.421208] [drm:i915_runtime_resume], Resuming device
[  578.423135] [drm:i915_runtime_suspend], Suspending device
[  578.447170] [drm:i915_runtime_resume], Resuming device
[  578.449124] [drm:i915_runtime_suspend], Suspending device
[  578.473165] [drm:i915_runtime_resume], Resuming device
[  578.475116] [drm:i915_runtime_suspend], Suspending device
[  578.499151] [drm:i915_runtime_resume], Resuming device
[  578.501106] [drm:i915_runtime_suspend], Suspending device
[  578.525167] [drm:i915_runtime_resume], Resuming device
[  578.527098] [drm:i915_runtime_suspend], Suspending device
[  578.551138] [drm:i915_runtime_resume], Resuming device
[  578.553086] [drm:i915_runtime_suspend], Suspending device
[  578.577128] [drm:i915_runtime_resume], Resuming device
[  578.579078] [drm:i915_runtime_suspend], Suspending device
[  578.603121] [drm:i915_runtime_resume], Resuming device
[  578.605080] [drm:i915_runtime_suspend], Suspending device
[  578.629108] [drm:i915_runtime_resume], Resuming device
[  578.631070] [drm:i915_runtime_suspend], Suspending device
[  578.655101] [drm:i915_runtime_resume], Resuming device
[  578.657050] [drm:i915_runtime_suspend], Suspending device
[  578.681092] [drm:i915_runtime_resume], Resuming device
[  578.683043] [drm:i915_runtime_suspend], Suspending device
[  578.707081] [drm:i915_runtime_resume], Resuming device
[  578.709027] [drm:i915_runtime_suspend], Suspending device
[  578.733085] [drm:i915_runtime_resume], Resuming device
[  578.735020] [drm:i915_runtime_suspend], Suspending device
[  578.759062] [drm:i915_runtime_resume], Resuming device
[  578.761024] [drm:i915_runtime_suspend], Suspending device
[  578.785031] [drm:i915_runtime_resume], Resuming device
[  578.787015] [drm:i915_runtime_suspend], Suspending device
[  578.811045] [drm:i915_runtime_resume], Resuming device
[  578.812992] [drm:i915_runtime_suspend], Suspending device
[  578.837039] [drm:i915_runtime_resume], Resuming device
[  578.838983] [drm:i915_runtime_suspend], Suspending device
[  578.863038] [drm:i915_runtime_resume], Resuming device
[  578.864976] [drm:i915_runtime_suspend], Suspending device
[  578.888991] [drm:i915_runtime_resume], Resuming device
[  578.893380] [drm:i915_runtime_suspend], Suspending device
[  578.993563] [drm:drm_mode_setcrtc], [CRTC:3]
[  578.993575] [drm:drm_mode_setcrtc], [CONNECTOR:10:eDP-1]
[  578.993581] [drm:intel_crtc_set_config], [CRTC:3] [FB:21] #connectors=1 (x y) (0 0)
[  578.993585] [drm:intel_set_config_compute_mode_changes], inactive crtc, full mode set
[  578.993590] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:3], mode_changed=1, fb_changed=0
[  578.993593] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
[  578.993598] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
[  578.993601] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
[  578.993606] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
[  578.993611] [drm:connected_sink_compute_bpp], [CONNECTOR:10:eDP-1] checking for sink bpp constrains
[  578.993617] [drm:intel_dp_compute_config], DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
[  578.993628] [drm:intel_dp_compute_config], DP link bw 0a lane count 2 clock 270000 bpp 24
[  578.993631] [drm:intel_dp_compute_config], DP link bw required 333072 available 432000
[  578.993636] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 24, dithering: 0
[  578.993640] [drm:intel_dump_pipe_config], [CRTC:3][modeset] config for pipe A
[  578.993643] [drm:intel_dump_pipe_config], cpu_transcoder: P
[  578.993646] [drm:intel_dump_pipe_config], pipe bpp: 24, dithering: 0
[  578.993650] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
[  578.993655] [drm:intel_dump_pipe_config], dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
[  578.993658] [drm:intel_dump_pipe_config], requested mode:
[  578.993663] [drm:drm_mode_debug_printmodeline], Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
[  578.993666] [drm:intel_dump_pipe_config], adjusted mode:
[  578.993671] [drm:drm_mode_debug_printmodeline], Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
[  578.993676] [drm:intel_dump_crtc_timings], crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
[  578.993679] [drm:intel_dump_pipe_config], port clock: 270000
[  578.993682] [drm:intel_dump_pipe_config], pipe src size: 1920x1080
[  578.993686] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
[  578.993690] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000, disabled
[  578.993693] [drm:intel_dump_pipe_config], ips: 1
[  578.993696] [drm:intel_dump_pipe_config], double wide: 0
[  578.993704] [drm:__hsw_disable_package_c8], Disabling package C8+
[  579.003968] [drm:i915_runtime_resume], Resuming device
[  579.039918] [drm:ironlake_update_plane], Writing base 00C91000 00000000 0 0 7680
[  579.039929] [drm:intel_edp_psr_match_conditions], crtc not active for PSR
[  579.039936] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:0:1920x1080]
[  579.039940] [drm:intel_ddi_mode_set], Preparing DDI mode on port A, pipe A
[  579.039945] [drm:ironlake_edp_panel_on], Turn eDP power on
[  579.039951] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
[  579.039958] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000
[  579.039964] [drm:ironlake_wait_panel_status], Wait complete
[  579.039969] [drm:ironlake_wait_panel_on], Wait for panel power on
[  579.039975] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0003
[  579.171850] [drm:ironlake_wait_panel_status], Wait complete
[  579.173013] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
[  579.173484] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
[  579.173950] [drm:intel_dp_start_link_train], clock recovery OK
[  579.174712] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful
[  579.226739] [drm:g4x_wait_for_vblank], vblank wait timed out
[  579.226927] [drm:ironlake_edp_backlight_on], 
[  579.228745] [drm:intel_panel_enable_backlight], pipe A
[  579.228754] [drm:intel_panel_actually_set_backlight], set backlight PWM = 765
[  579.228763] [drm:intel_edp_psr_match_conditions], PSR condition failed: fb not tiled or fenced
[  579.260730] [drm:intel_update_fbc], framebuffer not tiled or fenced, disabling compression
[  579.278725] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
[  579.278731] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
[  579.278735] [drm:check_encoder_state], [ENCODER:17:TMDS-17]
[  579.278739] [drm:check_crtc_state], [CRTC:3]
[  579.278750] [drm:check_crtc_state], [CRTC:5]
[  579.278754] [drm:check_crtc_state], [CRTC:7]
[  579.281328] [drm:drm_mode_setcrtc], [CRTC:3]
[  579.281336] [drm:drm_mode_setcrtc], [CONNECTOR:10:eDP-1]
[  579.281341] [drm:intel_crtc_set_config], [CRTC:3] [FB:21] #connectors=1 (x y) (0 0)
[  579.281346] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:3], mode_changed=0, fb_changed=0
[  579.281351] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
[  579.281409] [drm:drm_mode_setcrtc], [CRTC:3]
[  579.281412] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
[  579.281417] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:3], mode_changed=1, fb_changed=0
[  579.281421] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC]
[  579.281435] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
[  579.281438] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
[  579.281443] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 1
[  579.312712] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
[  579.312721] [drm:ironlake_edp_backlight_off], 
[  579.527916] [drm:ironlake_edp_panel_off], Turn eDP power off
[  579.527929] [drm:ironlake_wait_panel_off], Wait for panel power off time
[  579.527939] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000
[  580.374329] [drm:ironlake_wait_panel_status], Wait complete
[  580.374345] [drm:intel_update_fbc], no output, disabling
[  580.374361] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
[  580.374366] [drm:check_encoder_state], [ENCODER:17:TMDS-17]
[  580.374370] [drm:check_crtc_state], [CRTC:3]
[  580.374374] [drm:check_crtc_state], [CRTC:5]
[  580.374378] [drm:check_crtc_state], [CRTC:7]
[  580.374391] [drm:drm_mode_setcrtc], [CRTC:5]
[  580.374396] [drm:intel_crtc_set_config], [CRTC:5] [NOFB]
[  580.374400] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:5], mode_changed=0, fb_changed=0
[  580.374405] [drm:drm_mode_setcrtc], [CRTC:7]
[  580.374408] [drm:intel_crtc_set_config], [CRTC:7] [NOFB]
[  580.374412] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:7], mode_changed=0, fb_changed=0
[  585.380618] [drm:hsw_enable_pc8_work], Enabling package C8+
[  585.386625] [drm:i915_runtime_suspend], Suspending device
[  585.479968] [drm:drm_mode_setcrtc], [CRTC:3]
[  585.479980] [drm:drm_mode_setcrtc], [CONNECTOR:10:eDP-1]
[  585.479985] [drm:intel_crtc_set_config], [CRTC:3] [FB:21] #connectors=1 (x y) (0 0)
[  585.479990] [drm:intel_set_config_compute_mode_changes], inactive crtc, full mode set
[  585.479994] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:3], mode_changed=1, fb_changed=0
[  585.479997] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
[  585.480002] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
[  585.480005] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
[  585.480009] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
[  585.480015] [drm:connected_sink_compute_bpp], [CONNECTOR:10:eDP-1] checking for sink bpp constrains
[  585.480021] [drm:intel_dp_compute_config], DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
[  585.480031] [drm:intel_dp_compute_config], DP link bw 0a lane count 2 clock 270000 bpp 24
[  585.480035] [drm:intel_dp_compute_config], DP link bw required 333072 available 432000
[  585.480040] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 24, dithering: 0
[  585.480044] [drm:intel_dump_pipe_config], [CRTC:3][modeset] config for pipe A
[  585.480047] [drm:intel_dump_pipe_config], cpu_transcoder: P
[  585.480051] [drm:intel_dump_pipe_config], pipe bpp: 24, dithering: 0
[  585.480055] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
[  585.480060] [drm:intel_dump_pipe_config], dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
[  585.480063] [drm:intel_dump_pipe_config], requested mode:
[  585.480069] [drm:drm_mode_debug_printmodeline], Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
[  585.480072] [drm:intel_dump_pipe_config], adjusted mode:
[  585.480077] [drm:drm_mode_debug_printmodeline], Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
[  585.480082] [drm:intel_dump_crtc_timings], crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
[  585.480085] [drm:intel_dump_pipe_config], port clock: 270000
[  585.480088] [drm:intel_dump_pipe_config], pipe src size: 1920x1080
[  585.480092] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
[  585.480095] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000, disabled
[  585.480098] [drm:intel_dump_pipe_config], ips: 1
[  585.480101] [drm:intel_dump_pipe_config], double wide: 0
[  585.480109] [drm:__hsw_disable_package_c8], Disabling package C8+
[  585.490623] [drm:i915_runtime_resume], Resuming device
[  585.536568] [drm:ironlake_update_plane], Writing base 00C91000 00000000 0 0 7680
[  585.536578] [drm:intel_edp_psr_match_conditions], crtc not active for PSR
[  585.536585] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:0:1920x1080]
[  585.536589] [drm:intel_ddi_mode_set], Preparing DDI mode on port A, pipe A
[  585.536593] [drm:ironlake_edp_panel_on], Turn eDP power on
[  585.536600] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
[  585.536607] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000
[  585.536612] [drm:ironlake_wait_panel_status], Wait complete
[  585.536618] [drm:ironlake_wait_panel_on], Wait for panel power on
[  585.536623] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0003
[  585.668499] [drm:ironlake_wait_panel_status], Wait complete
[  585.669687] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
[  585.670154] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
[  585.670615] [drm:intel_dp_start_link_train], clock recovery OK
[  585.671377] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful
[  585.723391] [drm:g4x_wait_for_vblank], vblank wait timed out
[  585.723569] [drm:ironlake_edp_backlight_on], 
[  585.725395] [drm:intel_panel_enable_backlight], pipe A
[  585.725403] [drm:intel_panel_actually_set_backlight], set backlight PWM = 765
[  585.725413] [drm:intel_edp_psr_match_conditions], PSR condition failed: fb not tiled or fenced
[  585.757380] [drm:intel_update_fbc], framebuffer not tiled or fenced, disabling compression
[  585.775376] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
[  585.775382] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
[  585.775386] [drm:check_encoder_state], [ENCODER:17:TMDS-17]
[  585.775390] [drm:check_crtc_state], [CRTC:3]
[  585.775401] [drm:check_crtc_state], [CRTC:5]
[  585.775405] [drm:check_crtc_state], [CRTC:7]
[  585.775497] [drm:drm_mode_setcrtc], [CRTC:3]
[  585.775504] [drm:drm_mode_setcrtc], [CONNECTOR:10:eDP-1]
[  585.775509] [drm:intel_crtc_set_config], [CRTC:3] [FB:21] #connectors=1 (x y) (0 0)
[  585.775515] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:3], mode_changed=0, fb_changed=0
[  585.775520] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
[  585.775632] [drm:drm_mode_setcrtc], [CRTC:3]
[  585.775635] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
[  585.775640] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:3], mode_changed=1, fb_changed=0
[  585.775644] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC]
[  585.775647] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
[  585.775650] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
[  585.775655] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 1
[  585.809445] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
[  585.809457] [drm:ironlake_edp_backlight_off], 
[  586.024563] [drm:ironlake_edp_panel_off], Turn eDP power off
[  586.024576] [drm:ironlake_wait_panel_off], Wait for panel power off time
[  586.024586] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000
[  586.870981] [drm:ironlake_wait_panel_status], Wait complete
[  586.870997] [drm:intel_update_fbc], no output, disabling
[  586.871013] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
[  586.871017] [drm:check_encoder_state], [ENCODER:17:TMDS-17]
[  586.871021] [drm:check_crtc_state], [CRTC:3]
[  586.871026] [drm:check_crtc_state], [CRTC:5]
[  586.871029] [drm:check_crtc_state], [CRTC:7]
[  586.871042] [drm:drm_mode_setcrtc], [CRTC:5]
[  586.871046] [drm:intel_crtc_set_config], [CRTC:5] [NOFB]
[  586.871051] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:5], mode_changed=0, fb_changed=0
[  586.871056] [drm:drm_mode_setcrtc], [CRTC:7]
[  586.871059] [drm:intel_crtc_set_config], [CRTC:7] [NOFB]
[  586.871063] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:7], mode_changed=0, fb_changed=0
[  591.874280] [drm:hsw_enable_pc8_work], Enabling package C8+
[  591.882260] [drm:i915_runtime_suspend], Suspending device
[  591.987283] [drm:i915_runtime_resume], Resuming device
[  591.989247] [drm:__hsw_disable_package_c8], Disabling package C8+
[  598.607853] [drm:hsw_enable_pc8_work], Enabling package C8+
[  598.615828] [drm:i915_runtime_suspend], Suspending device
[  598.636711] [drm:drm_mode_setcrtc], [CRTC:3]
[  598.636747] [drm:drm_mode_setcrtc], [CONNECTOR:10:eDP-1]
[  598.636753] [drm:intel_crtc_set_config], [CRTC:3] [FB:21] #connectors=1 (x y) (0 0)
[  598.636759] [drm:intel_set_config_compute_mode_changes], inactive crtc, full mode set
[  598.636781] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:3], mode_changed=1, fb_changed=0
[  598.636789] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
[  598.636794] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
[  598.636797] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
[  598.636804] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
[  598.636810] [drm:connected_sink_compute_bpp], [CONNECTOR:10:eDP-1] checking for sink bpp constrains
[  598.636818] [drm:intel_dp_compute_config], DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
[  598.636831] [drm:intel_dp_compute_config], DP link bw 0a lane count 2 clock 270000 bpp 24
[  598.636836] [drm:intel_dp_compute_config], DP link bw required 333072 available 432000
[  598.636842] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 24, dithering: 0
[  598.636846] [drm:intel_dump_pipe_config], [CRTC:3][modeset] config for pipe A
[  598.636854] [drm:intel_dump_pipe_config], cpu_transcoder: P
[  598.636864] [drm:intel_dump_pipe_config], pipe bpp: 24, dithering: 0
[  598.636878] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
[  598.636884] [drm:intel_dump_pipe_config], dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
[  598.636886] [drm:intel_dump_pipe_config], requested mode:
[  598.636891] [drm:drm_mode_debug_printmodeline], Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
[  598.636893] [drm:intel_dump_pipe_config], adjusted mode:
[  598.636897] [drm:drm_mode_debug_printmodeline], Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
[  598.636901] [drm:intel_dump_crtc_timings], crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
[  598.636903] [drm:intel_dump_pipe_config], port clock: 270000
[  598.636906] [drm:intel_dump_pipe_config], pipe src size: 1920x1080
[  598.636919] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
[  598.636930] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000, disabled
[  598.636932] [drm:intel_dump_pipe_config], ips: 1
[  598.636934] [drm:intel_dump_pipe_config], double wide: 0
[  598.636942] [drm:__hsw_disable_package_c8], Disabling package C8+
[  598.647867] [drm:i915_runtime_resume], Resuming device
[  598.693812] [drm:ironlake_update_plane], Writing base 00C91000 00000000 0 0 7680
[  598.693822] [drm:intel_edp_psr_match_conditions], crtc not active for PSR
[  598.693830] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:0:1920x1080]
[  598.693835] [drm:intel_ddi_mode_set], Preparing DDI mode on port A, pipe A
[  598.693839] [drm:ironlake_edp_panel_on], Turn eDP power on
[  598.693846] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
[  598.693852] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000
[  598.693858] [drm:ironlake_wait_panel_status], Wait complete
[  598.693863] [drm:ironlake_wait_panel_on], Wait for panel power on
[  598.693869] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0003
[  598.825749] [drm:ironlake_wait_panel_status], Wait complete
[  598.826907] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
[  598.827372] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
[  598.827826] [drm:intel_dp_start_link_train], clock recovery OK
[  598.828588] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful
[  598.880635] [drm:g4x_wait_for_vblank], vblank wait timed out
[  598.880812] [drm:ironlake_edp_backlight_on], 
[  598.882641] [drm:intel_panel_enable_backlight], pipe A
[  598.882649] [drm:intel_panel_actually_set_backlight], set backlight PWM = 765
[  598.882659] [drm:intel_edp_psr_match_conditions], PSR condition failed: fb not tiled or fenced
[  598.914626] [drm:intel_update_fbc], framebuffer not tiled or fenced, disabling compression
[  598.932620] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
[  598.932626] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
[  598.932631] [drm:check_encoder_state], [ENCODER:17:TMDS-17]
[  598.932635] [drm:check_crtc_state], [CRTC:3]
[  598.932646] [drm:check_crtc_state], [CRTC:5]
[  598.932650] [drm:check_crtc_state], [CRTC:7]
[  598.932948] [drm:drm_mode_setcrtc], [CRTC:3]
[  598.932952] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
[  598.932957] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:3], mode_changed=1, fb_changed=0
[  598.932961] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC]
[  598.932964] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
[  598.932968] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
[  598.932973] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 1
[  598.966705] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
[  598.966717] [drm:ironlake_edp_backlight_off], 
[  599.181808] [drm:ironlake_edp_panel_off], Turn eDP power off
[  599.181821] [drm:ironlake_wait_panel_off], Wait for panel power off time
[  599.181831] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000
[  599.973342] [drm:ironlake_wait_panel_status], Wait complete
[  599.973360] [drm:intel_update_fbc], no output, disabling
[  599.973376] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
[  599.973381] [drm:check_encoder_state], [ENCODER:17:TMDS-17]
[  599.973385] [drm:check_crtc_state], [CRTC:3]
[  599.973389] [drm:check_crtc_state], [CRTC:5]
[  599.973393] [drm:check_crtc_state], [CRTC:7]
[  599.973406] [drm:drm_mode_setcrtc], [CRTC:5]
[  599.973410] [drm:intel_crtc_set_config], [CRTC:5] [NOFB]
[  599.973415] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:5], mode_changed=0, fb_changed=0
[  599.973420] [drm:drm_mode_setcrtc], [CRTC:7]
[  599.973423] [drm:intel_crtc_set_config], [CRTC:7] [NOFB]
[  599.973427] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:7], mode_changed=0, fb_changed=0
[  605.613303] [drm:hsw_enable_pc8_work], Enabling package C8+
[  605.621230] [drm:i915_runtime_suspend], Suspending device
[  605.691323] [drm:i915_runtime_resume], Resuming device
[  605.693280] [drm:i915_runtime_suspend], Suspending device
[  605.693698] [drm:drm_mode_setcrtc], [CRTC:3]
[  605.693706] [drm:drm_mode_setcrtc], [CONNECTOR:10:eDP-1]
[  605.693730] [drm:intel_crtc_set_config], [CRTC:3] [FB:21] #connectors=1 (x y) (0 0)
[  605.693734] [drm:intel_set_config_compute_mode_changes], inactive crtc, full mode set
[  605.693737] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:3], mode_changed=1, fb_changed=0
[  605.693740] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
[  605.693743] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
[  605.693746] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
[  605.693750] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
[  605.693754] [drm:connected_sink_compute_bpp], [CONNECTOR:10:eDP-1] checking for sink bpp constrains
[  605.693759] [drm:intel_dp_compute_config], DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
[  605.693769] [drm:intel_dp_compute_config], DP link bw 0a lane count 2 clock 270000 bpp 24
[  605.693771] [drm:intel_dp_compute_config], DP link bw required 333072 available 432000
[  605.693775] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 24, dithering: 0
[  605.693778] [drm:intel_dump_pipe_config], [CRTC:3][modeset] config for pipe A
[  605.693780] [drm:intel_dump_pipe_config], cpu_transcoder: P
[  605.693783] [drm:intel_dump_pipe_config], pipe bpp: 24, dithering: 0
[  605.693786] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
[  605.693790] [drm:intel_dump_pipe_config], dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
[  605.693792] [drm:intel_dump_pipe_config], requested mode:
[  605.693796] [drm:drm_mode_debug_printmodeline], Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
[  605.693798] [drm:intel_dump_pipe_config], adjusted mode:
[  605.693802] [drm:drm_mode_debug_printmodeline], Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
[  605.693806] [drm:intel_dump_crtc_timings], crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
[  605.693809] [drm:intel_dump_pipe_config], port clock: 270000
[  605.693811] [drm:intel_dump_pipe_config], pipe src size: 1920x1080
[  605.693814] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
[  605.693817] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000, disabled
[  605.693819] [drm:intel_dump_pipe_config], ips: 1
[  605.693821] [drm:intel_dump_pipe_config], double wide: 0
[  605.693827] [drm:__hsw_disable_package_c8], Disabling package C8+
[  605.717329] [drm:i915_runtime_resume], Resuming device
[  605.751264] [drm:ironlake_update_plane], Writing base 00C91000 00000000 0 0 7680
[  605.751275] [drm:intel_edp_psr_match_conditions], crtc not active for PSR
[  605.751282] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:0:1920x1080]
[  605.751287] [drm:intel_ddi_mode_set], Preparing DDI mode on port A, pipe A
[  605.751291] [drm:ironlake_edp_panel_on], Turn eDP power on
[  605.751298] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
[  605.751306] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000
[  605.751312] [drm:ironlake_wait_panel_status], Wait complete
[  605.751318] [drm:ironlake_wait_panel_on], Wait for panel power on
[  605.751323] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0003
[  605.883194] [drm:ironlake_wait_panel_status], Wait complete
[  605.884380] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
[  605.884845] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
[  605.885305] [drm:intel_dp_start_link_train], clock recovery OK
[  605.886066] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful
[  605.938086] [drm:g4x_wait_for_vblank], vblank wait timed out
[  605.938275] [drm:ironlake_edp_backlight_on], 
[  605.940088] [drm:intel_panel_enable_backlight], pipe A
[  605.940097] [drm:intel_panel_actually_set_backlight], set backlight PWM = 765
[  605.940107] [drm:intel_edp_psr_match_conditions], PSR condition failed: fb not tiled or fenced
[  605.972073] [drm:intel_update_fbc], framebuffer not tiled or fenced, disabling compression
[  605.990071] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
[  605.990077] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
[  605.990082] [drm:check_encoder_state], [ENCODER:17:TMDS-17]
[  605.990086] [drm:check_crtc_state], [CRTC:3]
[  605.990096] [drm:check_crtc_state], [CRTC:5]
[  605.990100] [drm:check_crtc_state], [CRTC:7]
[  605.990120] [drm:drm_mode_setcrtc], [CRTC:3]
[  605.990124] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
[  605.990128] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:3], mode_changed=1, fb_changed=0
[  605.990132] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC]
[  605.990136] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
[  605.990139] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
[  605.990144] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 1
[  606.024058] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
[  606.024066] [drm:ironlake_edp_backlight_off], 
[  606.239156] [drm:ironlake_edp_panel_off], Turn eDP power off
[  606.239164] [drm:ironlake_wait_panel_off], Wait for panel power off time
[  606.239171] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000
[  607.063768] [drm:ironlake_wait_panel_status], Wait complete
[  607.063787] [drm:intel_update_fbc], no output, disabling
[  607.063805] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
[  607.063809] [drm:check_encoder_state], [ENCODER:17:TMDS-17]
[  607.063813] [drm:check_crtc_state], [CRTC:3]
[  607.063817] [drm:check_crtc_state], [CRTC:5]
[  607.063820] [drm:check_crtc_state], [CRTC:7]
[  607.063834] [drm:drm_mode_setcrtc], [CRTC:5]
[  607.063838] [drm:intel_crtc_set_config], [CRTC:5] [NOFB]
[  607.063843] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:5], mode_changed=0, fb_changed=0
[  607.063848] [drm:drm_mode_setcrtc], [CRTC:7]
[  607.063852] [drm:intel_crtc_set_config], [CRTC:7] [NOFB]
[  607.063856] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:7], mode_changed=0, fb_changed=0
[  612.074959] [drm:hsw_enable_pc8_work], Enabling package C8+
[  612.082960] [drm:i915_runtime_suspend], Suspending device
[  612.169897] [drm:__hsw_disable_package_c8], Disabling package C8+
[  612.180870] [drm:i915_runtime_resume], Resuming device
[  612.207239] [drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x714500e1
[  612.207248] [drm:intel_dp_i2c_aux_ch], aux_ch failed -110
[  612.207255] [drm:ironlake_edp_panel_vdd_on], Turning eDP VDD on
[  612.207259] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
[  612.207266] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000
[  612.207272] [drm:ironlake_wait_panel_status], Wait complete
[  612.207280] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008
[  612.207284] [drm:ironlake_edp_panel_vdd_on], eDP was not running
[  612.327942] [drm:i2c_algo_dp_aux_xfer], dp_aux_xfer return -110
[  612.378840] [drm] GMBUS [i915 gmbus dpd] timed out, falling back to bit banging on pin 6
[  612.437820] [drm] GMBUS [i915 gmbus dpb] timed out, falling back to bit banging on pin 5
[  612.446008] [drm:gmbus_xfer], GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(128)
[  612.496799] [drm] GMBUS [i915 gmbus panel] timed out, falling back to bit banging on pin 3
[  612.555776] [drm] GMBUS [i915 gmbus vga] timed out, falling back to bit banging on pin 2
[  612.614756] [drm] GMBUS [i915 gmbus ssc] timed out, falling back to bit banging on pin 1
[  612.622831] [drm:drm_mode_setcrtc], [CRTC:3]
[  612.622836] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
[  612.622840] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:3], mode_changed=0, fb_changed=0
[  612.622844] [drm:drm_mode_setcrtc], [CRTC:5]
[  612.622847] [drm:intel_crtc_set_config], [CRTC:5] [NOFB]
[  612.622849] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:5], mode_changed=0, fb_changed=0
[  612.622852] [drm:drm_mode_setcrtc], [CRTC:7]
[  612.622854] [drm:intel_crtc_set_config], [CRTC:7] [NOFB]
[  612.622857] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:7], mode_changed=0, fb_changed=0
[  615.209859] [drm:ironlake_panel_vdd_off_sync], Turning eDP VDD off
[  615.209873] [drm:ironlake_panel_vdd_off_sync], PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0000
[  617.624960] [drm:hsw_enable_pc8_work], Enabling package C8+
[  617.632953] [drm:i915_runtime_suspend], Suspending device
[  617.730017] [drm:drm_mode_setcrtc], [CRTC:3]
[  617.730029] [drm:drm_mode_setcrtc], [CONNECTOR:10:eDP-1]
[  617.730035] [drm:intel_crtc_set_config], [CRTC:3] [FB:21] #connectors=1 (x y) (0 0)
[  617.730039] [drm:intel_set_config_compute_mode_changes], inactive crtc, full mode set
[  617.730043] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:3], mode_changed=1, fb_changed=0
[  617.730047] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
[  617.730051] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
[  617.730054] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
[  617.730059] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
[  617.730065] [drm:connected_sink_compute_bpp], [CONNECTOR:10:eDP-1] checking for sink bpp constrains
[  617.730071] [drm:intel_dp_compute_config], DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
[  617.730082] [drm:intel_dp_compute_config], DP link bw 0a lane count 2 clock 270000 bpp 24
[  617.730085] [drm:intel_dp_compute_config], DP link bw required 333072 available 432000
[  617.730090] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 24, dithering: 0
[  617.730094] [drm:intel_dump_pipe_config], [CRTC:3][modeset] config for pipe A
[  617.730097] [drm:intel_dump_pipe_config], cpu_transcoder: P
[  617.730100] [drm:intel_dump_pipe_config], pipe bpp: 24, dithering: 0
[  617.730105] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
[  617.730109] [drm:intel_dump_pipe_config], dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
[  617.730112] [drm:intel_dump_pipe_config], requested mode:
[  617.730118] [drm:drm_mode_debug_printmodeline], Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
[  617.730120] [drm:intel_dump_pipe_config], adjusted mode:
[  617.730125] [drm:drm_mode_debug_printmodeline], Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
[  617.730130] [drm:intel_dump_crtc_timings], crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
[  617.730133] [drm:intel_dump_pipe_config], port clock: 270000
[  617.730136] [drm:intel_dump_pipe_config], pipe src size: 1920x1080
[  617.730140] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
[  617.730144] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000, disabled
[  617.730147] [drm:intel_dump_pipe_config], ips: 1
[  617.730150] [drm:intel_dump_pipe_config], double wide: 0
[  617.730157] [drm:__hsw_disable_package_c8], Disabling package C8+
[  617.740942] [drm:i915_runtime_resume], Resuming device
[  617.778919] [drm:ironlake_update_plane], Writing base 00C91000 00000000 0 0 7680
[  617.778929] [drm:intel_edp_psr_match_conditions], crtc not active for PSR
[  617.778936] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:0:1920x1080]
[  617.778941] [drm:intel_ddi_mode_set], Preparing DDI mode on port A, pipe A
[  617.778945] [drm:ironlake_edp_panel_on], Turn eDP power on
[  617.778952] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
[  617.778960] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000
[  617.778965] [drm:ironlake_wait_panel_status], Wait complete
[  617.778972] [drm:ironlake_wait_panel_on], Wait for panel power on
[  617.778977] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0003
[  617.910846] [drm:ironlake_wait_panel_status], Wait complete
[  617.912024] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
[  617.912489] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
[  617.912998] [drm:intel_dp_start_link_train], clock recovery OK
[  617.913771] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful
[  617.965818] [drm:g4x_wait_for_vblank], vblank wait timed out
[  617.966030] [drm:ironlake_edp_backlight_on], 
[  617.967818] [drm:intel_panel_enable_backlight], pipe A
[  617.967830] [drm:intel_panel_actually_set_backlight], set backlight PWM = 765
[  617.967841] [drm:intel_edp_psr_match_conditions], PSR condition failed: fb not tiled or fenced
[  617.999814] [drm:intel_update_fbc], framebuffer not tiled or fenced, disabling compression
[  618.017807] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
[  618.017816] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
[  618.017821] [drm:check_encoder_state], [ENCODER:17:TMDS-17]
[  618.017825] [drm:check_crtc_state], [CRTC:3]
[  618.017836] [drm:check_crtc_state], [CRTC:5]
[  618.017840] [drm:check_crtc_state], [CRTC:7]
[  628.032345] [drm:drm_mode_setcrtc], [CRTC:3]
[  628.032353] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
[  628.032360] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:3], mode_changed=1, fb_changed=0
[  628.032365] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC]
[  628.032369] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
[  628.032373] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
[  628.032378] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 1
[  628.064173] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
[  628.064185] [drm:ironlake_edp_backlight_off], 
[  628.279304] [drm:ironlake_edp_panel_off], Turn eDP power off
[  628.279316] [drm:ironlake_wait_panel_off], Wait for panel power off time
[  628.279327] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000
[  629.059819] [drm:ironlake_wait_panel_status], Wait complete
[  629.059838] [drm:intel_update_fbc], no output, disabling
[  629.059857] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
[  629.059861] [drm:check_encoder_state], [ENCODER:17:TMDS-17]
[  629.059865] [drm:check_crtc_state], [CRTC:3]
[  629.059869] [drm:check_crtc_state], [CRTC:5]
[  629.059873] [drm:check_crtc_state], [CRTC:7]
[  629.059887] [drm:drm_mode_setcrtc], [CRTC:5]
[  629.059891] [drm:intel_crtc_set_config], [CRTC:5] [NOFB]
[  629.059896] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:5], mode_changed=0, fb_changed=0
[  629.059901] [drm:drm_mode_setcrtc], [CRTC:7]
[  629.059904] [drm:intel_crtc_set_config], [CRTC:7] [NOFB]
[  629.059908] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:7], mode_changed=0, fb_changed=0
[  634.067012] [drm:hsw_enable_pc8_work], Enabling package C8+
[  634.075010] [drm:i915_runtime_suspend], Suspending device
[  634.177030] [drm:i915_runtime_resume], Resuming device
[  634.178975] [drm:i915_runtime_suspend], Suspending device
[  634.289961] [drm:i915_runtime_resume], Resuming device
[  634.295118] [drm:i915_runtime_suspend], Suspending device
[  634.318991] [drm:i915_runtime_resume], Resuming device
[  634.324200] [drm:i915_runtime_suspend], Suspending device
[  634.347970] [drm:i915_runtime_resume], Resuming device
[  634.353319] [drm:i915_runtime_suspend], Suspending device
[  634.376957] [drm:i915_runtime_resume], Resuming device
[  634.382554] [drm:i915_runtime_suspend], Suspending device
[  634.405919] [drm:i915_runtime_resume], Resuming device
[  634.412238] [drm:i915_runtime_suspend], Suspending device
[  634.435927] [drm:i915_runtime_resume], Resuming device
[  634.442453] [drm:i915_runtime_suspend], Suspending device
[  634.553919] [drm:i915_runtime_resume], Resuming device
[  634.555929] [drm:i915_runtime_suspend], Suspending device
[  634.666835] [drm:i915_runtime_resume], Resuming device
[  634.668885] [drm:i915_runtime_suspend], Suspending device
[  634.779836] [drm:i915_runtime_resume], Resuming device
[  634.813763] [drm:i915_runtime_suspend], Suspending device
[  634.924734] [drm:i915_runtime_resume], Resuming device
[  634.926817] [drm:i915_runtime_suspend], Suspending device
[  635.037720] [drm:i915_runtime_resume], Resuming device
[  635.040033] [drm:i915_runtime_suspend], Suspending device
[  635.150680] [drm:i915_runtime_resume], Resuming device
[  635.152816] [drm:i915_runtime_suspend], Suspending device
[  635.263621] [drm:i915_runtime_resume], Resuming device
[  635.265683] [drm:i915_runtime_suspend], Suspending device
[  635.376578] [drm:i915_runtime_resume], Resuming device
[  635.378627] [drm:i915_runtime_suspend], Suspending device
[  635.489532] [drm:i915_runtime_resume], Resuming device
[  635.491645] [drm:i915_runtime_suspend], Suspending device
[  635.602491] [drm:i915_runtime_resume], Resuming device
[  635.604588] [drm:i915_runtime_suspend], Suspending device
[  635.715476] [drm:i915_runtime_resume], Resuming device
[  635.717504] [drm:i915_runtime_suspend], Suspending device
[  635.828436] [drm:i915_runtime_resume], Resuming device
[  635.830478] [drm:i915_runtime_suspend], Suspending device
[  635.930771] [drm:drm_mode_setcrtc], [CRTC:3]
[  635.930779] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
[  635.930785] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:3], mode_changed=0, fb_changed=0
[  635.930792] [drm:drm_mode_setcrtc], [CRTC:5]
[  635.930796] [drm:intel_crtc_set_config], [CRTC:5] [NOFB]
[  635.930801] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:5], mode_changed=0, fb_changed=0
[  635.930805] [drm:drm_mode_setcrtc], [CRTC:7]
[  635.930807] [drm:intel_crtc_set_config], [CRTC:7] [NOFB]
[  635.930810] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:7], mode_changed=0, fb_changed=0
[  635.941366] [drm:i915_runtime_resume], Resuming device
[  645.939973] [drm:i915_runtime_suspend], Suspending device
[  646.040174] [drm:drm_mode_setcrtc], [CRTC:3]
[  646.040183] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
[  646.040190] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:3], mode_changed=0, fb_changed=0
[  646.040197] [drm:drm_mode_setcrtc], [CRTC:5]
[  646.040200] [drm:intel_crtc_set_config], [CRTC:5] [NOFB]
[  646.040205] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:5], mode_changed=0, fb_changed=0
[  646.040211] [drm:drm_mode_setcrtc], [CRTC:7]
[  646.040213] [drm:intel_crtc_set_config], [CRTC:7] [NOFB]
[  646.040216] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:7], mode_changed=0, fb_changed=0
[  646.040467] [drm:intel_hdmi_detect], [CONNECTOR:18:HDMI-A-1]
[  646.040473] [drm:__hsw_disable_package_c8], Disabling package C8+
[  646.050706] [drm:i915_runtime_resume], Resuming device
[  646.076912] [drm:gmbus_xfer], GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1)
[  646.076923] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus dpc
[  651.084847] [drm:hsw_enable_pc8_work], Enabling package C8+
[  651.092854] [drm:i915_runtime_suspend], Suspending device
[  651.193875] [drm:i915_runtime_resume], Resuming device
[  651.195823] [drm:i915_runtime_suspend], Suspending device
[  651.306835] [drm:i915_runtime_resume], Resuming device
[  651.308795] [drm:i915_runtime_suspend], Suspending device
[  651.419797] [drm:i915_runtime_resume], Resuming device
[  651.421743] [drm:i915_runtime_suspend], Suspending device
[  651.532758] [drm:i915_runtime_resume], Resuming device
[  651.534703] [drm:i915_runtime_suspend], Suspending device
[  651.646690] [drm:i915_runtime_resume], Resuming device
[  651.648650] [drm:intel_panel_get_backlight], get backlight PWM = 0
[  651.648669] [drm:i915_runtime_suspend], Suspending device
[  651.759671] [drm:i915_runtime_resume], Resuming device
[  651.761606] [drm:intel_dp_detect], [CONNECTOR:10:eDP-1]
[  651.761616] [drm:ironlake_edp_panel_vdd_on], Turning eDP VDD on
[  651.761622] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
[  651.761629] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000
[  651.761635] [drm:ironlake_wait_panel_status], Wait complete
[  651.761644] [drm:ironlake_edp_panel_vdd_on], PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008
[  651.761650] [drm:ironlake_edp_panel_vdd_on], eDP was not running
[  651.882637] [drm:__hsw_disable_package_c8], Disabling package C8+
[  651.906648] [drm:intel_dp_probe_oui], Sink OUI: 001cf8
[  651.906821] [drm:intel_dp_probe_oui], Branch OUI: 000000
[  654.907486] [drm:ironlake_panel_vdd_off_sync], Turning eDP VDD off
[  654.907500] [drm:ironlake_panel_vdd_off_sync], PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0000
[  656.922750] [drm:hsw_enable_pc8_work], Enabling package C8+
[  656.930765] [drm:i915_runtime_suspend], Suspending device
[  657.023766] [drm:i915_runtime_resume], Resuming device
[  657.025717] [drm:i915_runtime_suspend], Suspending device
[  657.136727] [drm:i915_runtime_resume], Resuming device
[  657.138677] [drm:i915_runtime_suspend], Suspending device
[  657.241891] [drm:drm_mode_setcrtc], [CRTC:3]
[  657.241897] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
[  657.241901] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:3], mode_changed=0, fb_changed=0
[  657.241906] [drm:drm_mode_setcrtc], [CRTC:5]
[  657.241908] [drm:intel_crtc_set_config], [CRTC:5] [NOFB]
[  657.241911] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:5], mode_changed=0, fb_changed=0
[  657.241914] [drm:drm_mode_setcrtc], [CRTC:7]
[  657.241916] [drm:intel_crtc_set_config], [CRTC:7] [NOFB]
[  657.241918] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:7], mode_changed=0, fb_changed=0
[  657.241923] [drm:drm_mode_setcrtc], [CRTC:3]
[  657.241929] [drm:drm_mode_setcrtc], [CONNECTOR:10:eDP-1]
[  657.241932] [drm:intel_crtc_set_config], [CRTC:3] [FB:21] #connectors=1 (x y) (0 0)
[  657.241934] [drm:intel_set_config_compute_mode_changes], inactive crtc, full mode set
[  657.241937] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:3], mode_changed=1, fb_changed=0
[  657.241939] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
[  657.241943] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
[  657.241945] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
[  657.241949] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
[  657.241952] [drm:connected_sink_compute_bpp], [CONNECTOR:10:eDP-1] checking for sink bpp constrains
[  657.241957] [drm:intel_dp_compute_config], DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
[  657.241966] [drm:intel_dp_compute_config], DP link bw 0a lane count 2 clock 270000 bpp 24
[  657.241968] [drm:intel_dp_compute_config], DP link bw required 333072 available 432000
[  657.241972] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 24, dithering: 0
[  657.241975] [drm:intel_dump_pipe_config], [CRTC:3][modeset] config for pipe A
[  657.241977] [drm:intel_dump_pipe_config], cpu_transcoder: P
[  657.241980] [drm:intel_dump_pipe_config], pipe bpp: 24, dithering: 0
[  657.241983] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
[  657.241986] [drm:intel_dump_pipe_config], dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
[  657.242003] [drm:intel_dump_pipe_config], requested mode:
[  657.242008] [drm:drm_mode_debug_printmodeline], Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
[  657.242010] [drm:intel_dump_pipe_config], adjusted mode:
[  657.242014] [drm:drm_mode_debug_printmodeline], Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
[  657.242018] [drm:intel_dump_crtc_timings], crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
[  657.242020] [drm:intel_dump_pipe_config], port clock: 270000
[  657.242023] [drm:intel_dump_pipe_config], pipe src size: 1920x1080
[  657.242026] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
[  657.242028] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000, disabled
[  657.242030] [drm:intel_dump_pipe_config], ips: 1
[  657.242033] [drm:intel_dump_pipe_config], double wide: 0
[  657.242038] [drm:__hsw_disable_package_c8], Disabling package C8+
[  657.252685] [drm:i915_runtime_resume], Resuming device
[  657.296632] [drm:ironlake_update_plane], Writing base 00C91000 00000000 0 0 7680
[  657.296643] [drm:intel_edp_psr_match_conditions], crtc not active for PSR
[  657.296649] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:0:1920x1080]
[  657.296654] [drm:intel_ddi_mode_set], Preparing DDI mode on port A, pipe A
[  657.296658] [drm:ironlake_edp_panel_on], Turn eDP power on
[  657.296664] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
[  657.296671] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000
[  657.296676] [drm:ironlake_wait_panel_status], Wait complete
[  657.296682] [drm:ironlake_wait_panel_on], Wait for panel power on
[  657.296688] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0003
[  657.428560] [drm:ironlake_wait_panel_status], Wait complete
[  657.429713] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
[  657.430174] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
[  657.430627] [drm:intel_dp_start_link_train], clock recovery OK
[  657.431386] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful
[  657.483533] [drm:g4x_wait_for_vblank], vblank wait timed out
[  657.483729] [drm:ironlake_edp_backlight_on], 
[  657.485488] [drm:intel_panel_enable_backlight], pipe A
[  657.485499] [drm:intel_panel_actually_set_backlight], set backlight PWM = 765
[  657.485509] [drm:intel_edp_psr_match_conditions], PSR condition failed: fb not tiled or fenced
[  657.517474] [drm:intel_update_fbc], framebuffer not tiled or fenced, disabling compression
[  657.535472] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
[  657.535479] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
[  657.535483] [drm:check_encoder_state], [ENCODER:17:TMDS-17]
[  657.535486] [drm:check_crtc_state], [CRTC:3]
[  657.535496] [drm:check_crtc_state], [CRTC:5]
[  657.535499] [drm:check_crtc_state], [CRTC:7]
[  657.535517] [drm:drm_mode_setcrtc], [CRTC:3]
[  657.535520] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
[  657.535524] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:3], mode_changed=1, fb_changed=0
[  657.535528] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC]
[  657.535530] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
[  657.535532] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
[  657.535536] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 1
[  657.569455] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
[  657.569465] [drm:ironlake_edp_backlight_off], 
[  657.784542] [drm:ironlake_edp_panel_off], Turn eDP power off
[  657.784553] [drm:ironlake_wait_panel_off], Wait for panel power off time
[  657.784562] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000
[  658.543170] [drm:ironlake_wait_panel_status], Wait complete
[  658.543189] [drm:intel_update_fbc], no output, disabling
[  658.543208] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
[  658.543212] [drm:check_encoder_state], [ENCODER:17:TMDS-17]
[  658.543216] [drm:check_crtc_state], [CRTC:3]
[  658.543221] [drm:check_crtc_state], [CRTC:5]
[  658.543224] [drm:check_crtc_state], [CRTC:7]
[  658.543237] [drm:drm_mode_setcrtc], [CRTC:5]
[  658.543242] [drm:intel_crtc_set_config], [CRTC:5] [NOFB]
[  658.543246] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:5], mode_changed=0, fb_changed=0
[  658.543251] [drm:drm_mode_setcrtc], [CRTC:7]
[  658.543255] [drm:intel_crtc_set_config], [CRTC:7] [NOFB]
[  658.543259] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:7], mode_changed=0, fb_changed=0
[  663.544363] [drm:hsw_enable_pc8_work], Enabling package C8+
[  663.550376] [drm:i915_runtime_suspend], Suspending device
[  663.649243] [drm:drm_mode_setcrtc], [CRTC:3]
[  663.649255] [drm:drm_mode_setcrtc], [CONNECTOR:10:eDP-1]
[  663.649260] [drm:intel_crtc_set_config], [CRTC:3] [FB:21] #connectors=1 (x y) (0 0)
[  663.649265] [drm:intel_set_config_compute_mode_changes], inactive crtc, full mode set
[  663.649270] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:3], mode_changed=1, fb_changed=0
[  663.649273] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
[  663.649277] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
[  663.649281] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
[  663.649286] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
[  663.649292] [drm:connected_sink_compute_bpp], [CONNECTOR:10:eDP-1] checking for sink bpp constrains
[  663.649299] [drm:intel_dp_compute_config], DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
[  663.649309] [drm:intel_dp_compute_config], DP link bw 0a lane count 2 clock 270000 bpp 24
[  663.649313] [drm:intel_dp_compute_config], DP link bw required 333072 available 432000
[  663.649318] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 24, dithering: 0
[  663.649323] [drm:intel_dump_pipe_config], [CRTC:3][modeset] config for pipe A
[  663.649326] [drm:intel_dump_pipe_config], cpu_transcoder: P
[  663.649329] [drm:intel_dump_pipe_config], pipe bpp: 24, dithering: 0
[  663.649334] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
[  663.649338] [drm:intel_dump_pipe_config], dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
[  663.649341] [drm:intel_dump_pipe_config], requested mode:
[  663.649347] [drm:drm_mode_debug_printmodeline], Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
[  663.649350] [drm:intel_dump_pipe_config], adjusted mode:
[  663.649355] [drm:drm_mode_debug_printmodeline], Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
[  663.649360] [drm:intel_dump_crtc_timings], crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
[  663.649363] [drm:intel_dump_pipe_config], port clock: 270000
[  663.649366] [drm:intel_dump_pipe_config], pipe src size: 1920x1080
[  663.649369] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
[  663.649373] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000, disabled
[  663.649376] [drm:intel_dump_pipe_config], ips: 1
[  663.649379] [drm:intel_dump_pipe_config], double wide: 0
[  663.649387] [drm:__hsw_disable_package_c8], Disabling package C8+
[  663.660368] [drm:i915_runtime_resume], Resuming device
[  663.708314] [drm:ironlake_update_plane], Writing base 00C91000 00000000 0 0 7680
[  663.708325] [drm:intel_edp_psr_match_conditions], crtc not active for PSR
[  663.708332] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:0:1920x1080]
[  663.708336] [drm:intel_ddi_mode_set], Preparing DDI mode on port A, pipe A
[  663.708341] [drm:ironlake_edp_panel_on], Turn eDP power on
[  663.708348] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
[  663.708356] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000
[  663.708362] [drm:ironlake_wait_panel_status], Wait complete
[  663.708367] [drm:ironlake_wait_panel_on], Wait for panel power on
[  663.708373] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0003
[  663.840248] [drm:ironlake_wait_panel_status], Wait complete
[  663.841419] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
[  663.841886] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
[  663.842379] [drm:intel_dp_start_link_train], clock recovery OK
[  663.843141] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful
[  663.895136] [drm:g4x_wait_for_vblank], vblank wait timed out
[  663.895314] [drm:ironlake_edp_backlight_on], 
[  663.897140] [drm:intel_panel_enable_backlight], pipe A
[  663.897148] [drm:intel_panel_actually_set_backlight], set backlight PWM = 765
[  663.897158] [drm:intel_edp_psr_match_conditions], PSR condition failed: fb not tiled or fenced
[  663.929124] [drm:intel_update_fbc], framebuffer not tiled or fenced, disabling compression
[  663.947121] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
[  663.947127] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
[  663.947131] [drm:check_encoder_state], [ENCODER:17:TMDS-17]
[  663.947136] [drm:check_crtc_state], [CRTC:3]
[  663.947146] [drm:check_crtc_state], [CRTC:5]
[  663.947150] [drm:check_crtc_state], [CRTC:7]
[  663.947170] [drm:drm_mode_setcrtc], [CRTC:3]
[  663.947174] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
[  663.947179] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:3], mode_changed=1, fb_changed=0
[  663.947183] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [NOCRTC]
[  663.947186] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
[  663.947190] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
[  663.947195] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 1
[  663.981109] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0
[  663.981117] [drm:ironlake_edp_backlight_off], 
[  664.196208] [drm:ironlake_edp_panel_off], Turn eDP power off
[  664.196216] [drm:ironlake_wait_panel_off], Wait for panel power off time
[  664.196223] [drm:ironlake_wait_panel_status], mask b000000f value 00000000 status 80000008 control abcd0000
[  665.042811] [drm:ironlake_wait_panel_status], Wait complete
[  665.042830] [drm:intel_update_fbc], no output, disabling
[  665.042848] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
[  665.042852] [drm:check_encoder_state], [ENCODER:17:TMDS-17]
[  665.042856] [drm:check_crtc_state], [CRTC:3]
[  665.042860] [drm:check_crtc_state], [CRTC:5]
[  665.042864] [drm:check_crtc_state], [CRTC:7]
[  665.042877] [drm:drm_mode_setcrtc], [CRTC:5]
[  665.042881] [drm:intel_crtc_set_config], [CRTC:5] [NOFB]
[  665.042887] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:5], mode_changed=0, fb_changed=0
[  665.042892] [drm:drm_mode_setcrtc], [CRTC:7]
[  665.042895] [drm:intel_crtc_set_config], [CRTC:7] [NOFB]
[  665.042899] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:7], mode_changed=0, fb_changed=0
[  669.839354] [drm:intel_crtc_set_config], [CRTC:3] [FB:20] #connectors=1 (x y) (0 0)
[  669.839358] [drm:intel_set_config_compute_mode_changes], inactive crtc, full mode set
[  669.839360] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:3], mode_changed=1, fb_changed=0
[  669.839362] [drm:intel_modeset_stage_output_state], encoder changed, full mode switch
[  669.839364] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
[  669.839366] [drm:intel_modeset_stage_output_state], crtc changed, full mode switch
[  669.839369] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 1, prepare: 1, disable: 0
[  669.839373] [drm:connected_sink_compute_bpp], [CONNECTOR:10:eDP-1] checking for sink bpp constrains
[  669.839378] [drm:intel_dp_compute_config], DP link computation with max lane count 2 max bw 0a pixel clock 138780KHz
[  669.839386] [drm:intel_dp_compute_config], DP link bw 0a lane count 2 clock 270000 bpp 24
[  669.839388] [drm:intel_dp_compute_config], DP link bw required 333072 available 432000
[  669.839391] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 24, dithering: 0
[  669.839393] [drm:intel_dump_pipe_config], [CRTC:3][modeset] config for pipe A
[  669.839395] [drm:intel_dump_pipe_config], cpu_transcoder: P
[  669.839396] [drm:intel_dump_pipe_config], pipe bpp: 24, dithering: 0
[  669.839398] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
[  669.839401] [drm:intel_dump_pipe_config], dp: 1, gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
[  669.839402] [drm:intel_dump_pipe_config], requested mode:
[  669.839406] [drm:drm_mode_debug_printmodeline], Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
[  669.839407] [drm:intel_dump_pipe_config], adjusted mode:
[  669.839410] [drm:drm_mode_debug_printmodeline], Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
[  669.839413] [drm:intel_dump_crtc_timings], crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
[  669.839414] [drm:intel_dump_pipe_config], port clock: 270000
[  669.839415] [drm:intel_dump_pipe_config], pipe src size: 1920x1080
[  669.839417] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
[  669.839419] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000, disabled
[  669.839420] [drm:intel_dump_pipe_config], ips: 1
[  669.839421] [drm:intel_dump_pipe_config], double wide: 0
[  669.839451] [drm:ironlake_update_plane], Writing base 00296000 00000000 0 0 7680
[  669.839457] [drm:intel_edp_psr_match_conditions], crtc not active for PSR
[  669.839460] [drm:intel_crtc_mode_set], [ENCODER:9:TMDS-9] set [MODE:0:1920x1080]
[  669.839462] [drm:intel_ddi_mode_set], Preparing DDI mode on port A, pipe A
[  669.839464] [drm:ironlake_edp_panel_on], Turn eDP power on
[  669.839468] [drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle
[  669.839472] [drm:ironlake_wait_panel_status], mask b800000f value 00000000 status 00000000 control abcd0000
[  669.839474] [drm:ironlake_wait_panel_status], Wait complete
[  669.839478] [drm:ironlake_wait_panel_on], Wait for panel power on
[  669.839482] [drm:ironlake_wait_panel_status], mask b000000f value 80000008 status 0000000a control abcd0003
[  669.971027] [drm:ironlake_wait_panel_status], Wait complete
[  669.972166] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
[  669.972638] [drm:intel_dp_set_signal_levels], Using signal levels 00000000
[  669.973091] [drm:intel_dp_start_link_train], clock recovery OK
[  669.973853] [drm:intel_dp_complete_link_train], Channel EQ done. DP Training successful
[  670.025920] [drm:g4x_wait_for_vblank], vblank wait timed out
[  670.026076] [drm:ironlake_edp_backlight_on], 
[  670.027924] [drm:intel_panel_enable_backlight], pipe A
[  670.027930] [drm:intel_panel_actually_set_backlight], set backlight PWM = 765
[  670.027938] [drm:intel_edp_psr_match_conditions], PSR condition failed: fb not tiled or fenced
[  670.059908] [drm:intel_update_fbc], framebuffer not tiled or fenced, disabling compression
[  670.077906] [drm:intel_connector_check_state], [CONNECTOR:10:eDP-1]
[  670.077911] [drm:check_encoder_state], [ENCODER:9:TMDS-9]
[  670.077914] [drm:check_encoder_state], [ENCODER:17:TMDS-17]
[  670.077917] [drm:check_crtc_state], [CRTC:3]
[  670.077926] [drm:check_crtc_state], [CRTC:5]
[  670.077928] [drm:check_crtc_state], [CRTC:7]
[  670.077934] [drm:intel_crtc_set_config], [CRTC:5] [NOFB]
[  670.077937] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:5], mode_changed=0, fb_changed=0
[  670.077940] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
[  670.077942] [drm:intel_crtc_set_config], [CRTC:7] [NOFB]
[  670.077945] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:7], mode_changed=0, fb_changed=0
[  670.077948] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
[  670.095124] [drm:i915_gem_open], 
[  670.096035] [drm:gen6_ppgtt_init], Allocated pde space (2M) at GTT entry: 1480
[  670.096177] [drm:i915_gem_open], 
[  670.096775] [drm:gen6_ppgtt_init], Allocated pde space (2M) at GTT entry: 1480
[  670.097883] [drm:intel_crtc_cursor_set], cursor off
[  670.097911] [drm:intel_crtc_set_config], [CRTC:3] [FB:20] #connectors=1 (x y) (0 0)
[  670.097916] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:3], mode_changed=0, fb_changed=0
[  670.097921] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
[  670.097932] [drm:intel_crtc_cursor_set], cursor off
[  670.097936] [drm:intel_crtc_set_config], [CRTC:5] [NOFB]
[  670.097946] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:5], mode_changed=0, fb_changed=0
[  670.097955] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]
[  670.097959] [drm:intel_crtc_cursor_set], cursor off
[  670.097963] [drm:intel_crtc_set_config], [CRTC:7] [NOFB]
[  670.097967] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:7], mode_changed=0, fb_changed=0
[  670.097972] [drm:intel_modeset_stage_output_state], [CONNECTOR:10:eDP-1] to [CRTC:3]