-------------------------------------------------------------- FRAG 0: END ; ModuleID = 'tgsi' define void @main() #0 { main_body: call void @llvm.R600.store.dummy(i32 0) ret void } declare void @llvm.R600.store.dummy(i32) attributes #0 = { "ShaderType"="0" } Shader Disassembly: EXPORT T0.____ ; C0000000 94200FFF CF_END ; 00000000 80200000 ===== SHADER #6 ============================================ PS/RS780/R600 ===== ===== 4 dw ===== 1 gprs ===== 0 stack ========================================== 0000 c0000000 94200fff EXPORT_DONE PIXEL 0 R0.____ EOP ===== SHADER_END =============================================================== ===== SHADER #6 OPT ======================================== PS/RS780/R600 ===== ===== 2 dw ===== 0 gprs ===== 0 stack ========================================== 0000 c0000000 94200fff EXPORT_DONE PIXEL 0 R0.____ EOP ===== SHADER_END =============================================================== -------------------------------------------------------------- FRAG DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main() #0 { main_body: %0 = call float @llvm.R600.load.input(i32 0) %1 = call float @llvm.R600.load.input(i32 1) %2 = call float @llvm.R600.load.input(i32 2) %3 = call float @llvm.R600.load.input(i32 3) %4 = insertelement <4 x float> undef, float %0, i32 0 %5 = insertelement <4 x float> %4, float %1, i32 1 %6 = insertelement <4 x float> %5, float %2, i32 2 %7 = insertelement <4 x float> %6, float %3, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %7, i32 0, i32 0) ret void } ; Function Attrs: readnone declare float @llvm.R600.load.input(i32) #1 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } Shader Disassembly: EXPORT T0.XYZW ; C0000000 94200688 CF_END ; 00000000 80200000 ===== SHADER #7 ============================================ PS/RS780/R600 ===== ===== 4 dw ===== 1 gprs ===== 0 stack ========================================== 0000 c0000000 94200688 EXPORT_DONE PIXEL 0 R0.xyzw EOP ===== SHADER_END =============================================================== ===== SHADER #7 OPT ======================================== PS/RS780/R600 ===== ===== 2 dw ===== 1 gprs ===== 0 stack ========================================== 0000 c0000000 94200688 EXPORT_DONE PIXEL 0 R0.xyzw EOP ===== SHADER_END =============================================================== -------------------------------------------------------------- FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main() #0 { main_body: %0 = call float @llvm.R600.load.input(i32 0) %1 = call float @llvm.R600.load.input(i32 1) %2 = call float @llvm.R600.load.input(i32 2) %3 = call float @llvm.R600.load.input(i32 3) %4 = insertelement <4 x float> undef, float %0, i32 0 %5 = insertelement <4 x float> %4, float %1, i32 1 %6 = insertelement <4 x float> %5, float %2, i32 2 %7 = insertelement <4 x float> %6, float %3, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %7, i32 0, i32 0) ret void } ; Function Attrs: readnone declare float @llvm.R600.load.input(i32) #1 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } Shader Disassembly: EXPORT T0.XYZW ; C0000000 94200688 CF_END ; 00000000 80200000 ===== SHADER #8 ============================================ PS/RS780/R600 ===== ===== 4 dw ===== 1 gprs ===== 0 stack ========================================== 0000 c0000000 94200688 EXPORT_DONE PIXEL 0 R0.xyzw EOP ===== SHADER_END =============================================================== ===== SHADER #8 OPT ======================================== PS/RS780/R600 ===== ===== 2 dw ===== 1 gprs ===== 0 stack ========================================== 0000 c0000000 94200688 EXPORT_DONE PIXEL 0 R0.xyzw EOP ===== SHADER_END =============================================================== -------------------------------------------------------------- VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] 0: MOV OUT[0], IN[0] 1: MOV OUT[1], IN[1] 2: END ; ModuleID = 'tgsi' define void @main() #0 { main_body: %0 = call float @llvm.R600.load.input(i32 4) %1 = call float @llvm.R600.load.input(i32 5) %2 = call float @llvm.R600.load.input(i32 6) %3 = call float @llvm.R600.load.input(i32 7) %4 = call float @llvm.R600.load.input(i32 8) %5 = call float @llvm.R600.load.input(i32 9) %6 = call float @llvm.R600.load.input(i32 10) %7 = call float @llvm.R600.load.input(i32 11) %8 = insertelement <4 x float> undef, float %0, i32 0 %9 = insertelement <4 x float> %8, float %1, i32 1 %10 = insertelement <4 x float> %9, float %2, i32 2 %11 = insertelement <4 x float> %10, float %3, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %11, i32 60, i32 1) %12 = insertelement <4 x float> undef, float %4, i32 0 %13 = insertelement <4 x float> %12, float %5, i32 1 %14 = insertelement <4 x float> %13, float %6, i32 2 %15 = insertelement <4 x float> %14, float %7, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %15, i32 0, i32 2) ret void } ; Function Attrs: readnone declare float @llvm.R600.load.input(i32) #1 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="1" } attributes #1 = { readnone } Shader Disassembly: CALL_FS ; 00000000 89800000 EXPORT T1.XYZW ; C000A03C 94000688 EXPORT T2.XYZW ; C0014000 94200688 CF_END ; 00000000 80200000 ===== SHADER #9 ============================================ VS/RS780/R600 ===== ===== 8 dw ===== 3 gprs ===== 1 stack ========================================== 0000 00000000 89800000 CALL_FS @0 0002 c000a03c 94000688 EXPORT_DONE POS 60 R1.xyzw 0004 c0014000 94200688 EXPORT_DONE PARAM 0 R2.xyzw EOP ===== SHADER_END =============================================================== ===== SHADER #9 OPT ======================================== VS/RS780/R600 ===== ===== 12 dw ===== 3 gprs ===== 1 stack ========================================= 0000 00000000 89800000 CALL_FS @0 0002 c0014000 94000688 EXPORT_DONE PARAM 0 R2.xyzw 0004 c000a03c 94000688 EXPORT_DONE POS 60 R1.xyzw 0006 00000005 a0000000 ALU 1 @10 0010 80000000 00001a00 1 x: ALU_NOP __.x 0008 00000000 80200000 NOP @0 EOP ===== SHADER_END =============================================================== -------------------------------------------------------------- VERT DCL IN[0] DCL OUT[0], POSITION 0: MOV OUT[0], IN[0] 1: END STREAMOUT 0: MEM_STREAM0_BUF0[0..0] <- OUT[0].x ; ModuleID = 'tgsi' define void @main() #0 { main_body: %0 = call float @llvm.R600.load.input(i32 4) %1 = call float @llvm.R600.load.input(i32 5) %2 = call float @llvm.R600.load.input(i32 6) %3 = call float @llvm.R600.load.input(i32 7) %4 = insertelement <4 x float> undef, float %0, i32 0 %5 = insertelement <4 x float> %4, float %1, i32 1 %6 = insertelement <4 x float> %5, float %2, i32 2 %7 = insertelement <4 x float> %6, float %3, i32 3 call void @llvm.R600.store.stream.output(<4 x float> %7, i32 0, i32 0, i32 1) %8 = insertelement <4 x float> undef, float %0, i32 0 %9 = insertelement <4 x float> %8, float %1, i32 1 %10 = insertelement <4 x float> %9, float %2, i32 2 %11 = insertelement <4 x float> %10, float %3, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %11, i32 60, i32 1) call void @llvm.R600.store.dummy(i32 2) ret void } ; Function Attrs: readnone declare float @llvm.R600.load.input(i32) #1 declare void @llvm.R600.store.stream.output(<4 x float>, i32, i32, i32) declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) declare void @llvm.R600.store.dummy(i32) attributes #0 = { "ShaderType"="1" } attributes #1 = { readnone } Shader Disassembly: CALL_FS ; 00000000 89800000 EXPORT T1 ; 00008000 90001FFF EXPORT T1.XYZW ; C000A03C 94000688 EXPORT T0.____ ; C0004000 94200FFF CF_END ; 00000000 80200000 PAD ; 00000000 00000000 ===== SHADER #10 =========================================== VS/RS780/R600 ===== ===== 12 dw ===== 2 gprs ===== 1 stack ========================================= 0000 00000000 89800000 CALL_FS @0 0002 00008000 90001fff MEM_STREAM0 WRITE 0 R1.x___ ES:0 0004 c000a03c 94000688 EXPORT_DONE POS 60 R1.xyzw 0006 c0004000 94200fff EXPORT_DONE PARAM 0 R0.____ EOP ===== SHADER_END =============================================================== ===== SHADER #10 OPT ======================================= VS/RS780/R600 ===== ===== 14 dw ===== 2 gprs ===== 1 stack ========================================= 0000 00000000 89800000 CALL_FS @0 0002 c000a03c 94000688 EXPORT_DONE POS 60 R1.xyzw 0004 00008000 90001fff MEM_STREAM0 WRITE 0 R1.x___ ES:0 0006 c0004000 94000fff EXPORT_DONE PARAM 0 R0.____ 0008 00000006 a0000000 ALU 1 @12 0012 80000000 00001a00 1 x: ALU_NOP __.x 0010 00000000 80200000 NOP @0 EOP ===== SHADER_END =============================================================== -------------------------------------------------------------- FRAG DCL IN[0], GENERIC[0], CONSTANT 0: END ; ModuleID = 'tgsi' define void @main() #0 { main_body: %0 = call float @llvm.R600.load.input(i32 0) %1 = call float @llvm.R600.load.input(i32 1) %2 = call float @llvm.R600.load.input(i32 2) %3 = call float @llvm.R600.load.input(i32 3) call void @llvm.R600.store.dummy(i32 0) ret void } ; Function Attrs: readnone declare float @llvm.R600.load.input(i32) #1 declare void @llvm.R600.store.dummy(i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } Shader Disassembly: EXPORT T0.____ ; C0000000 94200FFF CF_END ; 00000000 80200000 ===== SHADER #11 =========================================== PS/RS780/R600 ===== ===== 4 dw ===== 1 gprs ===== 0 stack ========================================== 0000 c0000000 94200fff EXPORT_DONE PIXEL 0 R0.____ EOP ===== SHADER_END =============================================================== ===== SHADER #11 OPT ======================================= PS/RS780/R600 ===== ===== 2 dw ===== 0 gprs ===== 0 stack ========================================== 0000 c0000000 94200fff EXPORT_DONE PIXEL 0 R0.____ EOP ===== SHADER_END =============================================================== -------------------------------------------------------------- FRAG 0: END ; ModuleID = 'tgsi' define void @main() #0 { main_body: call void @llvm.R600.store.dummy(i32 0) ret void } declare void @llvm.R600.store.dummy(i32) attributes #0 = { "ShaderType"="0" } Shader Disassembly: EXPORT T0.____ ; C0000000 94200FFF CF_END ; 00000000 80200000 ===== SHADER #17 =========================================== PS/RS780/R600 ===== ===== 4 dw ===== 1 gprs ===== 0 stack ========================================== 0000 c0000000 94200fff EXPORT_DONE PIXEL 0 R0.____ EOP ===== SHADER_END =============================================================== ===== SHADER #17 OPT ======================================= PS/RS780/R600 ===== ===== 2 dw ===== 0 gprs ===== 0 stack ========================================== 0000 c0000000 94200fff EXPORT_DONE PIXEL 0 R0.____ EOP ===== SHADER_END =============================================================== -------------------------------------------------------------- FRAG DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main() #0 { main_body: %0 = call float @llvm.R600.load.input(i32 0) %1 = call float @llvm.R600.load.input(i32 1) %2 = call float @llvm.R600.load.input(i32 2) %3 = call float @llvm.R600.load.input(i32 3) %4 = insertelement <4 x float> undef, float %0, i32 0 %5 = insertelement <4 x float> %4, float %1, i32 1 %6 = insertelement <4 x float> %5, float %2, i32 2 %7 = insertelement <4 x float> %6, float %3, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %7, i32 0, i32 0) ret void } ; Function Attrs: readnone declare float @llvm.R600.load.input(i32) #1 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } Shader Disassembly: EXPORT T0.XYZW ; C0000000 94200688 CF_END ; 00000000 80200000 ===== SHADER #18 =========================================== PS/RS780/R600 ===== ===== 4 dw ===== 1 gprs ===== 0 stack ========================================== 0000 c0000000 94200688 EXPORT_DONE PIXEL 0 R0.xyzw EOP ===== SHADER_END =============================================================== ===== SHADER #18 OPT ======================================= PS/RS780/R600 ===== ===== 2 dw ===== 1 gprs ===== 0 stack ========================================== 0000 c0000000 94200688 EXPORT_DONE PIXEL 0 R0.xyzw EOP ===== SHADER_END =============================================================== -------------------------------------------------------------- FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main() #0 { main_body: %0 = call float @llvm.R600.load.input(i32 0) %1 = call float @llvm.R600.load.input(i32 1) %2 = call float @llvm.R600.load.input(i32 2) %3 = call float @llvm.R600.load.input(i32 3) %4 = insertelement <4 x float> undef, float %0, i32 0 %5 = insertelement <4 x float> %4, float %1, i32 1 %6 = insertelement <4 x float> %5, float %2, i32 2 %7 = insertelement <4 x float> %6, float %3, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %7, i32 0, i32 0) ret void } ; Function Attrs: readnone declare float @llvm.R600.load.input(i32) #1 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } Shader Disassembly: EXPORT T0.XYZW ; C0000000 94200688 CF_END ; 00000000 80200000 ===== SHADER #19 =========================================== PS/RS780/R600 ===== ===== 4 dw ===== 1 gprs ===== 0 stack ========================================== 0000 c0000000 94200688 EXPORT_DONE PIXEL 0 R0.xyzw EOP ===== SHADER_END =============================================================== ===== SHADER #19 OPT ======================================= PS/RS780/R600 ===== ===== 2 dw ===== 1 gprs ===== 0 stack ========================================== 0000 c0000000 94200688 EXPORT_DONE PIXEL 0 R0.xyzw EOP ===== SHADER_END =============================================================== -------------------------------------------------------------- VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] 0: MOV OUT[0], IN[0] 1: MOV OUT[1], IN[1] 2: END ; ModuleID = 'tgsi' define void @main() #0 { main_body: %0 = call float @llvm.R600.load.input(i32 4) %1 = call float @llvm.R600.load.input(i32 5) %2 = call float @llvm.R600.load.input(i32 6) %3 = call float @llvm.R600.load.input(i32 7) %4 = call float @llvm.R600.load.input(i32 8) %5 = call float @llvm.R600.load.input(i32 9) %6 = call float @llvm.R600.load.input(i32 10) %7 = call float @llvm.R600.load.input(i32 11) %8 = insertelement <4 x float> undef, float %0, i32 0 %9 = insertelement <4 x float> %8, float %1, i32 1 %10 = insertelement <4 x float> %9, float %2, i32 2 %11 = insertelement <4 x float> %10, float %3, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %11, i32 60, i32 1) %12 = insertelement <4 x float> undef, float %4, i32 0 %13 = insertelement <4 x float> %12, float %5, i32 1 %14 = insertelement <4 x float> %13, float %6, i32 2 %15 = insertelement <4 x float> %14, float %7, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %15, i32 0, i32 2) ret void } ; Function Attrs: readnone declare float @llvm.R600.load.input(i32) #1 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="1" } attributes #1 = { readnone } Shader Disassembly: CALL_FS ; 00000000 89800000 EXPORT T1.XYZW ; C000A03C 94000688 EXPORT T2.XYZW ; C0014000 94200688 CF_END ; 00000000 80200000 ===== SHADER #20 =========================================== VS/RS780/R600 ===== ===== 8 dw ===== 3 gprs ===== 1 stack ========================================== 0000 00000000 89800000 CALL_FS @0 0002 c000a03c 94000688 EXPORT_DONE POS 60 R1.xyzw 0004 c0014000 94200688 EXPORT_DONE PARAM 0 R2.xyzw EOP ===== SHADER_END =============================================================== ===== SHADER #20 OPT ======================================= VS/RS780/R600 ===== ===== 12 dw ===== 3 gprs ===== 1 stack ========================================= 0000 00000000 89800000 CALL_FS @0 0002 c0014000 94000688 EXPORT_DONE PARAM 0 R2.xyzw 0004 c000a03c 94000688 EXPORT_DONE POS 60 R1.xyzw 0006 00000005 a0000000 ALU 1 @10 0010 80000000 00001a00 1 x: ALU_NOP __.x 0008 00000000 80200000 NOP @0 EOP ===== SHADER_END =============================================================== -------------------------------------------------------------- VERT DCL IN[0] DCL OUT[0], POSITION 0: MOV OUT[0], IN[0] 1: END STREAMOUT 0: MEM_STREAM0_BUF0[0..0] <- OUT[0].x ; ModuleID = 'tgsi' define void @main() #0 { main_body: %0 = call float @llvm.R600.load.input(i32 4) %1 = call float @llvm.R600.load.input(i32 5) %2 = call float @llvm.R600.load.input(i32 6) %3 = call float @llvm.R600.load.input(i32 7) %4 = insertelement <4 x float> undef, float %0, i32 0 %5 = insertelement <4 x float> %4, float %1, i32 1 %6 = insertelement <4 x float> %5, float %2, i32 2 %7 = insertelement <4 x float> %6, float %3, i32 3 call void @llvm.R600.store.stream.output(<4 x float> %7, i32 0, i32 0, i32 1) %8 = insertelement <4 x float> undef, float %0, i32 0 %9 = insertelement <4 x float> %8, float %1, i32 1 %10 = insertelement <4 x float> %9, float %2, i32 2 %11 = insertelement <4 x float> %10, float %3, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %11, i32 60, i32 1) call void @llvm.R600.store.dummy(i32 2) ret void } ; Function Attrs: readnone declare float @llvm.R600.load.input(i32) #1 declare void @llvm.R600.store.stream.output(<4 x float>, i32, i32, i32) declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) declare void @llvm.R600.store.dummy(i32) attributes #0 = { "ShaderType"="1" } attributes #1 = { readnone } Shader Disassembly: CALL_FS ; 00000000 89800000 EXPORT T1 ; 00008000 90001FFF EXPORT T1.XYZW ; C000A03C 94000688 EXPORT T0.____ ; C0004000 94200FFF CF_END ; 00000000 80200000 PAD ; 00000000 00000000 ===== SHADER #21 =========================================== VS/RS780/R600 ===== ===== 12 dw ===== 2 gprs ===== 1 stack ========================================= 0000 00000000 89800000 CALL_FS @0 0002 00008000 90001fff MEM_STREAM0 WRITE 0 R1.x___ ES:0 0004 c000a03c 94000688 EXPORT_DONE POS 60 R1.xyzw 0006 c0004000 94200fff EXPORT_DONE PARAM 0 R0.____ EOP ===== SHADER_END =============================================================== ===== SHADER #21 OPT ======================================= VS/RS780/R600 ===== ===== 14 dw ===== 2 gprs ===== 1 stack ========================================= 0000 00000000 89800000 CALL_FS @0 0002 c000a03c 94000688 EXPORT_DONE POS 60 R1.xyzw 0004 00008000 90001fff MEM_STREAM0 WRITE 0 R1.x___ ES:0 0006 c0004000 94000fff EXPORT_DONE PARAM 0 R0.____ 0008 00000006 a0000000 ALU 1 @12 0012 80000000 00001a00 1 x: ALU_NOP __.x 0010 00000000 80200000 NOP @0 EOP ===== SHADER_END =============================================================== -------------------------------------------------------------- FRAG DCL IN[0], GENERIC[0], CONSTANT 0: END ; ModuleID = 'tgsi' define void @main() #0 { main_body: %0 = call float @llvm.R600.load.input(i32 0) %1 = call float @llvm.R600.load.input(i32 1) %2 = call float @llvm.R600.load.input(i32 2) %3 = call float @llvm.R600.load.input(i32 3) call void @llvm.R600.store.dummy(i32 0) ret void } ; Function Attrs: readnone declare float @llvm.R600.load.input(i32) #1 declare void @llvm.R600.store.dummy(i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } Shader Disassembly: EXPORT T0.____ ; C0000000 94200FFF CF_END ; 00000000 80200000 ===== SHADER #22 =========================================== PS/RS780/R600 ===== ===== 4 dw ===== 1 gprs ===== 0 stack ========================================== 0000 c0000000 94200fff EXPORT_DONE PIXEL 0 R0.____ EOP ===== SHADER_END =============================================================== ===== SHADER #22 OPT ======================================= PS/RS780/R600 ===== ===== 2 dw ===== 0 gprs ===== 0 stack ========================================== 0000 c0000000 94200fff EXPORT_DONE PIXEL 0 R0.____ EOP ===== SHADER_END =============================================================== -------------------------------------------------------------- Enter: demo_glstate_create Enter: demo_shader_create_program Enter: compile_shader Leave: compile_shader Enter: compile_shader Leave: compile_shader Enter: link_program Leave: link_program Leave: demo_shader_create_program Enter: demo_atlas_create Leave: demo_atlas_create Leave: demo_glstate_create Enter: demo_view_create Leave: demo_view_create Welcome to GLyphy demo FRAG DCL IN[0], GENERIC[0], LINEAR DCL OUT[0], COLOR DCL SAMP[0] 0: TEX OUT[0], IN[0], SAMP[0], 2D 1: END ; ModuleID = 'tgsi' define void @main() #0 { main_body: %0 = call float @llvm.R600.load.input(i32 0) %1 = call float @llvm.R600.load.input(i32 1) %2 = call float @llvm.R600.load.input(i32 2) %3 = call float @llvm.R600.load.input(i32 3) %4 = insertelement <4 x float> undef, float %0, i32 0 %5 = insertelement <4 x float> %4, float %1, i32 1 %6 = insertelement <4 x float> %5, float %2, i32 2 %7 = insertelement <4 x float> %6, float %3, i32 3 %8 = extractelement <4 x float> %7, i32 0 %9 = extractelement <4 x float> %7, i32 1 %10 = insertelement <4 x float> undef, float %8, i32 0 %11 = insertelement <4 x float> %10, float %9, i32 1 %12 = insertelement <4 x float> %11, float undef, i32 2 %13 = insertelement <4 x float> %12, float undef, i32 3 %14 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %13, i32 16, i32 0, i32 2) %15 = extractelement <4 x float> %14, i32 0 %16 = extractelement <4 x float> %14, i32 1 %17 = extractelement <4 x float> %14, i32 2 %18 = extractelement <4 x float> %14, i32 3 %19 = insertelement <4 x float> undef, float %15, i32 0 %20 = insertelement <4 x float> %19, float %16, i32 1 %21 = insertelement <4 x float> %20, float %17, i32 2 %22 = insertelement <4 x float> %21, float %18, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %22, i32 0, i32 0) ret void } ; Function Attrs: readnone declare float @llvm.R600.load.input(i32) #1 ; Function Attrs: readnone declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32, i32) #1 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } Shader Disassembly: TEX 0 @4 ; 00000004 80800000 EXPORT T0.XYZW ; C0000000 94200688 CF_END ; 00000000 80200000 PAD ; 00000000 00000000 Fetch clause starting at 4: ; TEX_SAMPLE T0.XYZW, T0.XY__ RID:16 SID:0 CT:NNNN ; 00001010 F00D1000 FC800000 00000000 ===== SHADER #23 =========================================== PS/RS780/R600 ===== ===== 12 dw ===== 1 gprs ===== 0 stack ========================================= 0000 00000004 80800000 TEX 1 @8 0008 00001010 f00d1000 fc800000 SAMPLE R0.xyzw, R0.xy__, RID:16, SID:0 CT:NNNN 0002 c0000000 94200688 EXPORT_DONE PIXEL 0 R0.xyzw EOP ===== SHADER_END =============================================================== ===== SHADER #23 OPT ======================================= PS/RS780/R600 ===== ===== 8 dw ===== 1 gprs ===== 0 stack ========================================== 0000 00000002 80800000 TEX 1 @4 0004 00001010 f00d1000 fc800000 SAMPLE R0.xyzw, R0.xy__, RID:16, SID:0 CT:NNNN 0002 c0000000 94200688 EXPORT_DONE PIXEL 0 R0.xyzw EOP ===== SHADER_END =============================================================== -------------------------------------------------------------- FRAG DCL IN[0], GENERIC[0], LINEAR DCL OUT[0], COLOR DCL SAMP[0] 0: TEX OUT[0], IN[0], SAMP[0], 2D 1: END ; ModuleID = 'tgsi' define void @main() #0 { main_body: %0 = call float @llvm.R600.load.input(i32 0) %1 = call float @llvm.R600.load.input(i32 1) %2 = call float @llvm.R600.load.input(i32 2) %3 = call float @llvm.R600.load.input(i32 3) %4 = insertelement <4 x float> undef, float %0, i32 0 %5 = insertelement <4 x float> %4, float %1, i32 1 %6 = insertelement <4 x float> %5, float %2, i32 2 %7 = insertelement <4 x float> %6, float %3, i32 3 %8 = extractelement <4 x float> %7, i32 0 %9 = extractelement <4 x float> %7, i32 1 %10 = insertelement <4 x float> undef, float %8, i32 0 %11 = insertelement <4 x float> %10, float %9, i32 1 %12 = insertelement <4 x float> %11, float undef, i32 2 %13 = insertelement <4 x float> %12, float undef, i32 3 %14 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %13, i32 16, i32 0, i32 2) %15 = extractelement <4 x float> %14, i32 0 %16 = extractelement <4 x float> %14, i32 1 %17 = extractelement <4 x float> %14, i32 2 %18 = extractelement <4 x float> %14, i32 3 %19 = insertelement <4 x float> undef, float %15, i32 0 %20 = insertelement <4 x float> %19, float %16, i32 1 %21 = insertelement <4 x float> %20, float %17, i32 2 %22 = insertelement <4 x float> %21, float %18, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %22, i32 0, i32 0) ret void } ; Function Attrs: readnone declare float @llvm.R600.load.input(i32) #1 ; Function Attrs: readnone declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32, i32) #1 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } Shader Disassembly: TEX 0 @4 ; 00000004 80800000 EXPORT T0.XYZW ; C0000000 94200688 CF_END ; 00000000 80200000 PAD ; 00000000 00000000 Fetch clause starting at 4: ; TEX_SAMPLE T0.XYZW, T0.XY__ RID:16 SID:0 CT:NNNN ; 00001010 F00D1000 FC800000 00000000 ===== SHADER #24 =========================================== PS/RS780/R600 ===== ===== 12 dw ===== 1 gprs ===== 0 stack ========================================= 0000 00000004 80800000 TEX 1 @8 0008 00001010 f00d1000 fc800000 SAMPLE R0.xyzw, R0.xy__, RID:16, SID:0 CT:NNNN 0002 c0000000 94200688 EXPORT_DONE PIXEL 0 R0.xyzw EOP ===== SHADER_END =============================================================== ===== SHADER #24 OPT ======================================= PS/RS780/R600 ===== ===== 8 dw ===== 1 gprs ===== 0 stack ========================================== 0000 00000002 80800000 TEX 1 @4 0004 00001010 f00d1000 fc800000 SAMPLE R0.xyzw, R0.xy__, RID:16, SID:0 CT:NNNN 0002 c0000000 94200688 EXPORT_DONE PIXEL 0 R0.xyzw EOP ===== SHADER_END =============================================================== No sRGB framebuffer extension found; failed to set sRGB framebuffer -------------------------------------------------------------- 45 glyphs; avg num endpoints 23.78; avg error 60.4%; avg tex fetch 2.96; avg 2.23kb per glyph Setting vsync on. Setting sRGB framebuffer on. Setting debug to 0 Setting contrast to 1 Setting gamma_adjust to 1 Setting outline to 0 Setting outline_thickness to 1 Setting boldness to 0 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[19], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL CONST[1..8] DCL TEMP[0..223], LOCAL IMM[0] FLT32 { 256.0000, 0.0039, 0.0000, 0.7071} IMM[1] INT32 {2, 4, 256, -1} IMM[2] FLT32 { 0.0000, 1.0000, 0.5000, 256.0000} IMM[3] INT32 {0, 255, 1, -128} IMM[4] INT32 {-16384, -32768, 16, 32} IMM[5] FLT32 { 0.0001, 0.0001, 1000000000.0000, 16.0000} IMM[6] FLT32 { 0.0625, 0.0039, 500000000.0000, 2.0000} IMM[7] UINT32 {0, 0, 0, 0} IMM[8] FLT32 { 0.1000, 4.0000, 1.0000, -1.0000} IMM[9] FLT32 { 10.0000, -0.7071, 2.4142, -0.5000} IMM[10] FLT32 { 3.0000, -2.0000, 0.0000, 0.4000} IMM[11] FLT32 { -0.0500, 100.0000, 0.0000, 0.1255} IMM[12] FLT32 { 0.0000, 0.1255, 0.0125, 0.0000} 0: MOV TEMP[0].xy, IN[0].xyxx 1: MUL TEMP[1].xy, IN[0].zwww, IMM[0].yyyy 2: FRC TEMP[1].xy, TEMP[1].xyyy 3: MUL TEMP[1].xy, IMM[0].xxxx, TEMP[1].xyyy 4: F2I TEMP[1].xy, TEMP[1].xyyy 5: UADD TEMP[1].xy, TEMP[1].xyyy, IMM[1].xxxx 6: IDIV TEMP[1].xy, TEMP[1].xyyy, IMM[1].yyyy 7: F2I TEMP[2].xy, IN[0].zwww 8: IDIV TEMP[2].xy, TEMP[2].xyyy, IMM[1].zzzz 9: DDX TEMP[3].xy, IN[0].xyyy 10: MUL TEMP[4], CONST[8].xxxx, IN[0].xyyy 11: DDY TEMP[4].xy, TEMP[4] 12: DP2 TEMP[5].x, TEMP[3].xyyy, TEMP[3].xyyy 13: RSQ TEMP[6].x, TEMP[5].xxxx 14: MUL TEMP[6].x, TEMP[6].xxxx, TEMP[5].xxxx 15: CMP TEMP[5].x, -TEMP[5].xxxx, TEMP[6].xxxx, IMM[0].zzzz 16: DP2 TEMP[6].x, TEMP[4].xyyy, TEMP[4].xyyy 17: RSQ TEMP[7].x, TEMP[6].xxxx 18: MUL TEMP[7].x, TEMP[7].xxxx, TEMP[6].xxxx 19: CMP TEMP[7].x, -TEMP[6].xxxx, TEMP[7].xxxx, IMM[0].zzzz 20: MOV TEMP[5].y, TEMP[7].xxxx 21: DP2 TEMP[5].x, TEMP[5].xyyy, TEMP[5].xyyy 22: RSQ TEMP[6].x, TEMP[5].xxxx 23: MUL TEMP[6].x, TEMP[6].xxxx, TEMP[5].xxxx 24: CMP TEMP[6].x, -TEMP[5].xxxx, TEMP[6].xxxx, IMM[0].zzzz 25: MUL TEMP[5].x, TEMP[6].xxxx, IMM[0].wwww 26: DP2 TEMP[6].x, TEMP[3].xyyy, TEMP[3].xyyy 27: RSQ TEMP[6].x, TEMP[6].xxxx 28: MUL TEMP[3].xy, TEMP[3].xyyy, TEMP[6].xxxx 29: ABS TEMP[3].x, TEMP[3].xxxx 30: DP2 TEMP[6].x, TEMP[4].xyyy, TEMP[4].xyyy 31: RSQ TEMP[6].x, TEMP[6].xxxx 32: MUL TEMP[4].xy, TEMP[4].xyyy, TEMP[6].xxxx 33: ABS TEMP[4].x, TEMP[4].xxxx 34: ADD TEMP[3].x, TEMP[3].xxxx, TEMP[4].xxxx 35: MOV TEMP[4], IMM[2].xxxy 36: MOV TEMP[6].xy, IN[0].xyxx 37: MOV TEMP[7].xy, TEMP[1].xyxx 38: MOV TEMP[8], CONST[1] 39: MOV TEMP[9].xy, TEMP[2].xyxx 40: FLR TEMP[10].xy, IN[0].xyyy 41: MAX TEMP[10].xy, TEMP[10].xyyy, IMM[0].zzzz 42: UADD TEMP[11].xy, TEMP[1].xyyy, IMM[1].wwww 43: I2F TEMP[11].xy, TEMP[11].xyyy 44: MIN TEMP[10].xy, TEMP[10].xyyy, TEMP[11].xyyy 45: F2I TEMP[10].xy, TEMP[10].xyyy 46: UMAD TEMP[10].x, TEMP[10].yyyy, TEMP[1].xxxx, TEMP[10].xxxx 47: I2F TEMP[11].x, CONST[1].zzzz 48: I2F TEMP[12].x, TEMP[10].xxxx 49: RCP TEMP[13].x, TEMP[11].xxxx 50: MUL TEMP[12].x, TEMP[12].xxxx, TEMP[13].xxxx 51: FRC TEMP[12].x, TEMP[12].xxxx 52: MUL TEMP[11].x, TEMP[11].xxxx, TEMP[12].xxxx 53: F2I TEMP[11].x, TEMP[11].xxxx 54: IDIV TEMP[10].x, TEMP[10].xxxx, CONST[1].zzzz 55: MOV TEMP[11].y, TEMP[10].xxxx 56: UMAD TEMP[10].xy, TEMP[2].xyyy, CONST[1].zwww, TEMP[11].xyyy 57: I2F TEMP[10].xy, TEMP[10].xyyy 58: ADD TEMP[10].xy, TEMP[10].xyyy, IMM[2].zzzz 59: I2F TEMP[11].xy, CONST[1].xyyy 60: RCP TEMP[12].x, TEMP[11].xxxx 61: RCP TEMP[12].y, TEMP[11].yyyy 62: MUL TEMP[10].xy, TEMP[10].xyyy, TEMP[12].xyyy 63: MOV TEMP[10].xy, TEMP[10].xyyy 64: TEX TEMP[10], TEMP[10], SAMP[0], 2D 65: MUL TEMP[10], TEMP[10], IMM[2].wwww 66: F2I TEMP[10], TEMP[10] 67: MOV TEMP[11].x, IMM[3].xxxx 68: USEQ TEMP[12].x, TEMP[10].xxxx, IMM[3].xxxx 69: UIF TEMP[12].xxxx :0 70: UMAD TEMP[12].x, TEMP[10].yyyy, IMM[1].zzzz, TEMP[10].zzzz 71: MOV TEMP[13].x, TEMP[10].wwww 72: USEQ TEMP[14].x, TEMP[10].wwww, IMM[3].yyyy 73: UIF TEMP[14].xxxx :0 74: MOV TEMP[13].x, IMM[3].xxxx 75: MOV TEMP[11].x, IMM[1].wwww 76: ELSE :0 77: USEQ TEMP[14].x, TEMP[13].xxxx, IMM[3].xxxx 78: UIF TEMP[14].xxxx :0 79: MOV TEMP[11].x, IMM[3].zzzz 80: ENDIF 81: ENDIF 82: ELSE :0 83: MOV TEMP[13].x, IMM[1].wwww 84: UADD TEMP[14].x, TEMP[10].xxxx, IMM[3].wwww 85: UMAD TEMP[14].x, TEMP[14].xxxx, IMM[1].zzzz, TEMP[10].yyyy 86: UADD TEMP[14].x, TEMP[14].xxxx, IMM[4].xxxx 87: I2F TEMP[14].x, TEMP[14].xxxx 88: MUL TEMP[14].x, TEMP[14].xxxx, IMM[5].xxxx 89: I2F TEMP[15].x, TEMP[1].xxxx 90: I2F TEMP[16].x, TEMP[1].yyyy 91: MAX TEMP[15].x, TEMP[15].xxxx, TEMP[16].xxxx 92: MUL TEMP[14].x, TEMP[14].xxxx, TEMP[15].xxxx 93: UMAD TEMP[10].x, TEMP[10].zzzz, IMM[1].zzzz, TEMP[10].wwww 94: UADD TEMP[10].x, TEMP[10].xxxx, IMM[4].yyyy 95: INEG TEMP[10].x, TEMP[10].xxxx 96: I2F TEMP[10].x, TEMP[10].xxxx 97: MUL TEMP[10].x, IMM[5].yyyy, TEMP[10].xxxx 98: ENDIF 99: MOV TEMP[15].x, TEMP[13].xxxx 100: MOV TEMP[16].x, TEMP[12].xxxx 101: USEQ TEMP[17].x, TEMP[13].xxxx, IMM[3].xxxx 102: UIF TEMP[17].xxxx :0 103: I2F TEMP[17].x, TEMP[11].xxxx 104: MUL TEMP[17].x, IMM[5].zzzz, TEMP[17].xxxx 105: ELSE :0 106: USEQ TEMP[13].x, TEMP[13].xxxx, IMM[1].wwww 107: UIF TEMP[13].xxxx :0 108: COS TEMP[13].x, TEMP[10].xxxx 109: SIN TEMP[10].x, TEMP[10].xxxx 110: MOV TEMP[13].y, TEMP[10].xxxx 111: I2F TEMP[10].xy, TEMP[1].xyyy 112: MUL TEMP[10].xy, TEMP[10].xyyy, IMM[2].zzzz 113: ADD TEMP[10].xy, IN[0].xyyy, -TEMP[10].xyyy 114: DP2 TEMP[10].x, TEMP[10].xyyy, TEMP[13].xyyy 115: ADD TEMP[17].x, TEMP[10].xxxx, -TEMP[14].xxxx 116: ELSE :0 117: I2F TEMP[10].x, TEMP[11].xxxx 118: MOV TEMP[11].x, IMM[5].zzzz 119: I2F TEMP[13].x, CONST[1].zzzz 120: I2F TEMP[14].x, TEMP[12].xxxx 121: RCP TEMP[18].x, TEMP[13].xxxx 122: MUL TEMP[14].x, TEMP[14].xxxx, TEMP[18].xxxx 123: FRC TEMP[14].x, TEMP[14].xxxx 124: MUL TEMP[13].x, TEMP[13].xxxx, TEMP[14].xxxx 125: F2I TEMP[13].x, TEMP[13].xxxx 126: IDIV TEMP[12].x, TEMP[12].xxxx, CONST[1].zzzz 127: MOV TEMP[13].y, TEMP[12].xxxx 128: UMAD TEMP[12].xy, TEMP[2].xyyy, CONST[1].zwww, TEMP[13].xyyy 129: I2F TEMP[12].xy, TEMP[12].xyyy 130: ADD TEMP[12].xy, TEMP[12].xyyy, IMM[2].zzzz 131: I2F TEMP[13].xy, CONST[1].xyyy 132: RCP TEMP[14].x, TEMP[13].xxxx 133: RCP TEMP[14].y, TEMP[13].yyyy 134: MUL TEMP[12].xy, TEMP[12].xyyy, TEMP[14].xyyy 135: MOV TEMP[12].xy, TEMP[12].xyyy 136: TEX TEMP[12], TEMP[12], SAMP[0], 2D 137: MUL TEMP[13].x, TEMP[12].wwww, IMM[2].wwww 138: F2I TEMP[13].x, TEMP[13].xxxx 139: IDIV TEMP[14].x, TEMP[13].xxxx, IMM[4].zzzz 140: I2F TEMP[13].x, TEMP[13].xxxx 141: MUL TEMP[13].x, TEMP[13].xxxx, IMM[6].xxxx 142: FRC TEMP[13].x, TEMP[13].xxxx 143: MUL TEMP[13].x, IMM[5].wwww, TEMP[13].xxxx 144: F2I TEMP[13].x, TEMP[13].xxxx 145: MOV TEMP[14].y, TEMP[13].xxxx 146: I2F TEMP[13].xy, TEMP[14].xyyy 147: ADD TEMP[13].xy, TEMP[13].xyyy, TEMP[12].yzzz 148: MUL TEMP[13].xy, TEMP[13].xyyy, IMM[6].xxxx 149: MOV TEMP[14].x, TEMP[12].xxxx 150: FSEQ TEMP[12].x, TEMP[12].xxxx, IMM[0].zzzz 151: UIF TEMP[12].xxxx :0 152: MOV TEMP[14].x, IMM[5].zzzz 153: ELSE :0 154: MUL TEMP[12].x, TEMP[14].xxxx, IMM[2].wwww 155: F2I TEMP[12].x, TEMP[12].xxxx 156: UADD TEMP[19].x, TEMP[12].xxxx, IMM[3].wwww 157: ENDIF 158: I2F TEMP[12].xy, TEMP[1].xyyy 159: MUL TEMP[12].xy, TEMP[13].xyyy, TEMP[12].xyyy 160: MOV TEMP[13].x, IMM[3].zzzz 161: BGNLOOP :0 162: ISGE TEMP[14].x, TEMP[13].xxxx, IMM[4].wwww 163: UIF TEMP[14].xxxx :0 164: BRK 165: ENDIF 166: ISGE TEMP[18].x, TEMP[13].xxxx, TEMP[15].xxxx 167: UIF TEMP[18].xxxx :0 168: BRK 169: ENDIF 170: UADD TEMP[20].x, TEMP[16].xxxx, TEMP[13].xxxx 171: I2F TEMP[21].x, TEMP[8].zzzz 172: I2F TEMP[22].x, TEMP[20].xxxx 173: RCP TEMP[23].x, TEMP[21].xxxx 174: MUL TEMP[24].x, TEMP[22].xxxx, TEMP[23].xxxx 175: FRC TEMP[25].x, TEMP[24].xxxx 176: MUL TEMP[26].x, TEMP[21].xxxx, TEMP[25].xxxx 177: F2I TEMP[27].x, TEMP[26].xxxx 178: IDIV TEMP[28].x, TEMP[20].xxxx, TEMP[8].zzzz 179: MOV TEMP[27].y, TEMP[28].xxxx 180: UMAD TEMP[29].xy, TEMP[9].xyyy, TEMP[8].zwww, TEMP[27].xyyy 181: I2F TEMP[30].xy, TEMP[29].xyyy 182: ADD TEMP[31].xy, TEMP[30].xyyy, IMM[2].zzzz 183: I2F TEMP[32].xy, TEMP[8].xyyy 184: RCP TEMP[33].x, TEMP[32].xxxx 185: RCP TEMP[33].y, TEMP[32].yyyy 186: MUL TEMP[34].xy, TEMP[31].xyyy, TEMP[33].xyyy 187: MOV TEMP[35].xy, TEMP[34].xyyy 188: TEX TEMP[36], TEMP[35], SAMP[0], 2D 189: MUL TEMP[37].x, TEMP[36].wwww, IMM[2].wwww 190: F2I TEMP[38].x, TEMP[37].xxxx 191: IDIV TEMP[39].x, TEMP[38].xxxx, IMM[4].zzzz 192: I2F TEMP[40].x, TEMP[38].xxxx 193: MUL TEMP[41].x, TEMP[40].xxxx, IMM[6].xxxx 194: FRC TEMP[42].x, TEMP[41].xxxx 195: MUL TEMP[43].x, IMM[5].wwww, TEMP[42].xxxx 196: F2I TEMP[44].x, TEMP[43].xxxx 197: MOV TEMP[39].y, TEMP[44].xxxx 198: I2F TEMP[45].xy, TEMP[39].xyyy 199: ADD TEMP[46].xy, TEMP[45].xyyy, TEMP[36].yzzz 200: MUL TEMP[47].xy, TEMP[46].xyyy, IMM[6].xxxx 201: MOV TEMP[48].x, TEMP[36].xxxx 202: FSEQ TEMP[49].x, TEMP[36].xxxx, IMM[0].zzzz 203: UIF TEMP[49].xxxx :0 204: MOV TEMP[48].x, IMM[5].zzzz 205: ELSE :0 206: MUL TEMP[50].x, TEMP[48].xxxx, IMM[2].wwww 207: F2I TEMP[51].x, TEMP[50].xxxx 208: UADD TEMP[52].x, TEMP[51].xxxx, IMM[3].wwww 209: I2F TEMP[53].x, TEMP[52].xxxx 210: MUL TEMP[48].x, IMM[6].yyyy, TEMP[53].xxxx 211: ENDIF 212: I2F TEMP[54].xy, TEMP[7].xyyy 213: MUL TEMP[55].xy, TEMP[47].xyyy, TEMP[54].xyyy 214: MOV TEMP[56].xy, TEMP[12].xyxx 215: MOV TEMP[12].xy, TEMP[55].xyxx 216: ABS TEMP[57].x, TEMP[48].xxxx 217: FSGE TEMP[58].x, TEMP[57].xxxx, IMM[6].zzzz 218: UIF TEMP[58].xxxx :0 219: UADD TEMP[13].x, TEMP[13].xxxx, IMM[3].zzzz 220: CONT 221: ENDIF 222: MUL TEMP[59].x, IMM[6].wwww, TEMP[48].xxxx 223: MUL TEMP[60].x, TEMP[48].xxxx, TEMP[48].xxxx 224: ADD TEMP[61].x, IMM[2].yyyy, -TEMP[60].xxxx 225: RCP TEMP[62].x, TEMP[61].xxxx 226: MUL TEMP[63].x, TEMP[59].xxxx, TEMP[62].xxxx 227: MOV TEMP[64].x, IMM[2].yyyy 228: MOV TEMP[64].y, TEMP[63].xxxx 229: MOV TEMP[65].x, -TEMP[63].xxxx 230: MOV TEMP[65].y, IMM[2].yyyy 231: ADD TEMP[66].xy, TEMP[55].xyyy, -TEMP[56].xyyy 232: DP2 TEMP[67].x, TEMP[66].xyyy, TEMP[64].xyyy 233: DP2 TEMP[68].x, TEMP[66].xyyy, TEMP[65].xyyy 234: MOV TEMP[67].y, TEMP[68].xxxx 235: ADD TEMP[69].xy, TEMP[6].xyyy, -TEMP[56].xyyy 236: DP2 TEMP[70].x, TEMP[69].xyyy, TEMP[67].xyyy 237: FSGE TEMP[71].x, TEMP[70].xxxx, IMM[0].zzzz 238: UIF TEMP[71].xxxx :0 239: MOV TEMP[72].x, IMM[2].yyyy 240: MOV TEMP[72].y, -TEMP[63].xxxx 241: MOV TEMP[73].x, TEMP[63].xxxx 242: MOV TEMP[73].y, IMM[2].yyyy 243: ADD TEMP[74].xy, TEMP[55].xyyy, -TEMP[56].xyyy 244: DP2 TEMP[75].x, TEMP[74].xyyy, TEMP[72].xyyy 245: DP2 TEMP[76].x, TEMP[74].xyyy, TEMP[73].xyyy 246: MOV TEMP[75].y, TEMP[76].xxxx 247: ADD TEMP[77].xy, TEMP[6].xyyy, -TEMP[55].xyyy 248: DP2 TEMP[78].x, TEMP[77].xyyy, TEMP[75].xyyy 249: FSGE TEMP[79].x, IMM[0].zzzz, TEMP[78].xxxx 250: ELSE :0 251: MOV TEMP[79].x, IMM[7].xxxx 252: ENDIF 253: UIF TEMP[79].xxxx :0 254: ABS TEMP[80].x, TEMP[48].xxxx 255: FSGE TEMP[81].x, IMM[8].xxxx, TEMP[80].xxxx 256: UIF TEMP[81].xxxx :0 257: ADD TEMP[82].xy, TEMP[55].xyyy, -TEMP[56].xyyy 258: DP2 TEMP[83].x, TEMP[82].xyyy, TEMP[82].xyyy 259: RSQ TEMP[84].x, TEMP[83].xxxx 260: MUL TEMP[85].xy, TEMP[82].xyyy, TEMP[84].xxxx 261: MOV TEMP[86].x, -TEMP[85].yyyy 262: MOV TEMP[86].y, TEMP[85].xxxx 263: ADD TEMP[87].xy, TEMP[6].xyyy, -TEMP[56].xyyy 264: DP2 TEMP[88].x, TEMP[87].xyyy, TEMP[86].xyyy 265: FSEQ TEMP[89].x, TEMP[48].xxxx, IMM[0].zzzz 266: UIF TEMP[89].xxxx :0 267: MOV TEMP[90].x, TEMP[88].xxxx 268: ELSE :0 269: ADD TEMP[91].xy, TEMP[6].xyyy, -TEMP[56].xyyy 270: DP2 TEMP[92].x, TEMP[91].xyyy, TEMP[85].xyyy 271: FSLT TEMP[93].x, TEMP[92].xxxx, IMM[0].zzzz 272: UIF TEMP[93].xxxx :0 273: ADD TEMP[94].xy, TEMP[6].xyyy, -TEMP[56].xyyy 274: SSG TEMP[95].x, TEMP[88].xxxx 275: DP2 TEMP[96].x, TEMP[94].xyyy, TEMP[94].xyyy 276: RSQ TEMP[97].x, TEMP[96].xxxx 277: MUL TEMP[97].x, TEMP[97].xxxx, TEMP[96].xxxx 278: CMP TEMP[97].x, -TEMP[96].xxxx, TEMP[97].xxxx, IMM[0].zzzz 279: MUL TEMP[90].x, TEMP[95].xxxx, TEMP[97].xxxx 280: ELSE :0 281: ADD TEMP[98].xy, TEMP[55].xyyy, -TEMP[6].xyyy 282: DP2 TEMP[99].x, TEMP[98].xyyy, TEMP[85].xyyy 283: FSLT TEMP[100].x, TEMP[99].xxxx, IMM[0].zzzz 284: UIF TEMP[100].xxxx :0 285: ADD TEMP[101].xy, TEMP[6].xyyy, -TEMP[55].xyyy 286: SSG TEMP[102].x, TEMP[88].xxxx 287: DP2 TEMP[103].x, TEMP[101].xyyy, TEMP[101].xyyy 288: RSQ TEMP[104].x, TEMP[103].xxxx 289: MUL TEMP[104].x, TEMP[104].xxxx, TEMP[103].xxxx 290: CMP TEMP[104].x, -TEMP[103].xxxx, TEMP[104].xxxx, IMM[0].zzzz 291: MUL TEMP[90].x, TEMP[102].xxxx, TEMP[104].xxxx 292: ELSE :0 293: MUL TEMP[105].x, IMM[6].wwww, TEMP[48].xxxx 294: MUL TEMP[106].x, TEMP[92].xxxx, TEMP[99].xxxx 295: MUL TEMP[107].x, TEMP[105].xxxx, TEMP[106].xxxx 296: ADD TEMP[108].x, TEMP[92].xxxx, TEMP[99].xxxx 297: RCP TEMP[109].x, TEMP[108].xxxx 298: MUL TEMP[110].x, TEMP[107].xxxx, TEMP[109].xxxx 299: MUL TEMP[111].x, TEMP[110].xxxx, TEMP[88].xxxx 300: FSLT TEMP[112].x, IMM[0].zzzz, TEMP[111].xxxx 301: UIF TEMP[112].xxxx :0 302: ADD TEMP[113].xy, TEMP[6].xyyy, -TEMP[56].xyyy 303: ADD TEMP[114].xy, TEMP[6].xyyy, -TEMP[55].xyyy 304: SSG TEMP[115].x, TEMP[88].xxxx 305: ADD TEMP[116].x, TEMP[88].xxxx, TEMP[110].xxxx 306: ABS TEMP[117].x, TEMP[116].xxxx 307: DP2 TEMP[118].x, TEMP[113].xyyy, TEMP[113].xyyy 308: RSQ TEMP[119].x, TEMP[118].xxxx 309: MUL TEMP[119].x, TEMP[119].xxxx, TEMP[118].xxxx 310: CMP TEMP[119].x, -TEMP[118].xxxx, TEMP[119].xxxx, IMM[0].zzzz 311: DP2 TEMP[120].x, TEMP[114].xyyy, TEMP[114].xyyy 312: RSQ TEMP[121].x, TEMP[120].xxxx 313: MUL TEMP[121].x, TEMP[121].xxxx, TEMP[120].xxxx 314: CMP TEMP[121].x, -TEMP[120].xxxx, TEMP[121].xxxx, IMM[0].zzzz 315: MIN TEMP[122].x, TEMP[119].xxxx, TEMP[121].xxxx 316: MIN TEMP[123].x, TEMP[117].xxxx, TEMP[122].xxxx 317: MUL TEMP[90].x, TEMP[115].xxxx, TEMP[123].xxxx 318: ELSE :0 319: ADD TEMP[90].x, TEMP[88].xxxx, TEMP[110].xxxx 320: ENDIF 321: ENDIF 322: ENDIF 323: ENDIF 324: MOV TEMP[124].x, TEMP[90].xxxx 325: ELSE :0 326: ADD TEMP[125].xy, TEMP[55].xyyy, -TEMP[56].xyyy 327: MOV TEMP[126].x, -TEMP[125].yyyy 328: MOV TEMP[126].y, TEMP[125].xxxx 329: MUL TEMP[127].x, TEMP[48].xxxx, TEMP[48].xxxx 330: ADD TEMP[128].x, IMM[2].yyyy, -TEMP[127].xxxx 331: RCP TEMP[129].x, TEMP[128].xxxx 332: MUL TEMP[130].x, IMM[8].yyyy, TEMP[129].xxxx 333: MUL TEMP[131].x, TEMP[48].xxxx, TEMP[130].xxxx 334: RCP TEMP[132].x, TEMP[131].xxxx 335: LRP TEMP[133].xy, IMM[2].zzzz, TEMP[55].xyyy, TEMP[56].xyyy 336: MAD TEMP[134].xy, TEMP[126].xyyy, TEMP[132].xxxx, TEMP[133].xyyy 337: ADD TEMP[135].xy, TEMP[56].xyyy, -TEMP[134].xyyy 338: ADD TEMP[136].xy, TEMP[6].xyyy, -TEMP[134].xyyy 339: SSG TEMP[137].x, TEMP[48].xxxx 340: DP2 TEMP[138].x, TEMP[135].xyyy, TEMP[135].xyyy 341: RSQ TEMP[139].x, TEMP[138].xxxx 342: MUL TEMP[139].x, TEMP[139].xxxx, TEMP[138].xxxx 343: CMP TEMP[139].x, -TEMP[138].xxxx, TEMP[139].xxxx, IMM[0].zzzz 344: DP2 TEMP[140].x, TEMP[136].xyyy, TEMP[136].xyyy 345: RSQ TEMP[141].x, TEMP[140].xxxx 346: MUL TEMP[141].x, TEMP[141].xxxx, TEMP[140].xxxx 347: CMP TEMP[141].x, -TEMP[140].xxxx, TEMP[141].xxxx, IMM[0].zzzz 348: ADD TEMP[142].x, TEMP[139].xxxx, -TEMP[141].xxxx 349: MUL TEMP[124].x, TEMP[137].xxxx, TEMP[142].xxxx 350: ENDIF 351: ABS TEMP[143].x, TEMP[124].xxxx 352: MUL TEMP[144].x, TEMP[143].xxxx, IMM[8].zzzz 353: FSGE TEMP[145].x, TEMP[11].xxxx, TEMP[144].xxxx 354: UIF TEMP[145].xxxx :0 355: MOV TEMP[11].x, TEMP[144].xxxx 356: FSGE TEMP[146].x, IMM[0].zzzz, TEMP[124].xxxx 357: UIF TEMP[146].xxxx :0 358: MOV TEMP[147].x, IMM[8].wwww 359: ELSE :0 360: MOV TEMP[147].x, IMM[2].yyyy 361: ENDIF 362: MOV TEMP[10].x, TEMP[147].xxxx 363: ENDIF 364: ELSE :0 365: ADD TEMP[148].xy, TEMP[6].xyyy, -TEMP[56].xyyy 366: ADD TEMP[149].xy, TEMP[6].xyyy, -TEMP[55].xyyy 367: DP2 TEMP[150].x, TEMP[148].xyyy, TEMP[148].xyyy 368: RSQ TEMP[151].x, TEMP[150].xxxx 369: MUL TEMP[151].x, TEMP[151].xxxx, TEMP[150].xxxx 370: CMP TEMP[151].x, -TEMP[150].xxxx, TEMP[151].xxxx, IMM[0].zzzz 371: DP2 TEMP[19].x, TEMP[149].xyyy, TEMP[149].xyyy 372: RSQ TEMP[152].x, TEMP[19].xxxx 373: MUL TEMP[152].x, TEMP[152].xxxx, TEMP[19].xxxx 374: CMP TEMP[152].x, -TEMP[19].xxxx, TEMP[152].xxxx, IMM[0].zzzz 375: MIN TEMP[153].x, TEMP[151].xxxx, TEMP[152].xxxx 376: FSLT TEMP[154].x, TEMP[153].xxxx, TEMP[11].xxxx 377: UIF TEMP[154].xxxx :0 378: MOV TEMP[11].x, TEMP[153].xxxx 379: MOV TEMP[10].x, IMM[0].zzzz 380: MOV TEMP[155].xy, TEMP[56].xyxx 381: MOV TEMP[156].xy, TEMP[55].xyxx 382: MOV TEMP[157].x, TEMP[48].xxxx 383: ELSE :0 384: FSEQ TEMP[158].x, TEMP[10].xxxx, IMM[0].zzzz 385: FSEQ TEMP[159].x, TEMP[153].xxxx, TEMP[11].xxxx 386: AND TEMP[160].x, TEMP[158].xxxx, TEMP[159].xxxx 387: UIF TEMP[160].xxxx :0 388: LRP TEMP[161].xy, IMM[2].zzzz, TEMP[156].xyyy, TEMP[155].xyyy 389: MUL TEMP[162].x, IMM[6].wwww, TEMP[157].xxxx 390: MUL TEMP[163].x, TEMP[157].xxxx, TEMP[157].xxxx 391: ADD TEMP[164].x, IMM[2].yyyy, -TEMP[163].xxxx 392: RCP TEMP[165].x, TEMP[164].xxxx 393: MUL TEMP[166].x, TEMP[162].xxxx, TEMP[165].xxxx 394: ADD TEMP[167].xy, TEMP[6].xyyy, -TEMP[161].xyyy 395: ADD TEMP[168].xy, TEMP[156].xyyy, -TEMP[161].xyyy 396: DP2 TEMP[169].x, TEMP[167].xyyy, TEMP[168].xyyy 397: FSLT TEMP[170].x, TEMP[169].xxxx, IMM[0].zzzz 398: UIF TEMP[170].xxxx :0 399: MOV TEMP[171].x, TEMP[166].xxxx 400: MOV TEMP[171].y, IMM[8].wwww 401: MOV TEMP[172].x, IMM[2].yyyy 402: MOV TEMP[172].y, TEMP[166].xxxx 403: ADD TEMP[173].xy, TEMP[156].xyyy, -TEMP[155].xyyy 404: DP2 TEMP[174].x, TEMP[173].xyyy, TEMP[171].xyyy 405: DP2 TEMP[175].x, TEMP[173].xyyy, TEMP[172].xyyy 406: MOV TEMP[174].y, TEMP[175].xxxx 407: ADD TEMP[176].xy, TEMP[6].xyyy, -TEMP[155].xyyy 408: DP2 TEMP[177].x, TEMP[174].xyyy, TEMP[174].xyyy 409: RSQ TEMP[178].x, TEMP[177].xxxx 410: MUL TEMP[179].xy, TEMP[174].xyyy, TEMP[178].xxxx 411: DP2 TEMP[180].x, TEMP[176].xyyy, TEMP[179].xyyy 412: ELSE :0 413: MOV TEMP[181].x, -TEMP[166].xxxx 414: MOV TEMP[181].y, IMM[8].wwww 415: MOV TEMP[182].x, IMM[2].yyyy 416: MOV TEMP[182].y, -TEMP[166].xxxx 417: ADD TEMP[183].xy, TEMP[156].xyyy, -TEMP[155].xyyy 418: DP2 TEMP[184].x, TEMP[183].xyyy, TEMP[181].xyyy 419: DP2 TEMP[185].x, TEMP[183].xyyy, TEMP[182].xyyy 420: MOV TEMP[184].y, TEMP[185].xxxx 421: ADD TEMP[186].xy, TEMP[6].xyyy, -TEMP[156].xyyy 422: DP2 TEMP[187].x, TEMP[184].xyyy, TEMP[184].xyyy 423: RSQ TEMP[188].x, TEMP[187].xxxx 424: MUL TEMP[189].xy, TEMP[184].xyyy, TEMP[188].xxxx 425: DP2 TEMP[180].x, TEMP[186].xyyy, TEMP[189].xyyy 426: ENDIF 427: LRP TEMP[190].xy, IMM[2].zzzz, TEMP[55].xyyy, TEMP[56].xyyy 428: MUL TEMP[191].x, IMM[6].wwww, TEMP[48].xxxx 429: MUL TEMP[192].x, TEMP[48].xxxx, TEMP[48].xxxx 430: ADD TEMP[193].x, IMM[2].yyyy, -TEMP[192].xxxx 431: RCP TEMP[194].x, TEMP[193].xxxx 432: MUL TEMP[195].x, TEMP[191].xxxx, TEMP[194].xxxx 433: ADD TEMP[196].xy, TEMP[6].xyyy, -TEMP[190].xyyy 434: ADD TEMP[197].xy, TEMP[55].xyyy, -TEMP[190].xyyy 435: DP2 TEMP[198].x, TEMP[196].xyyy, TEMP[197].xyyy 436: FSLT TEMP[199].x, TEMP[198].xxxx, IMM[0].zzzz 437: UIF TEMP[199].xxxx :0 438: MOV TEMP[200].x, TEMP[195].xxxx 439: MOV TEMP[200].y, IMM[8].wwww 440: MOV TEMP[201].x, IMM[2].yyyy 441: MOV TEMP[201].y, TEMP[195].xxxx 442: ADD TEMP[202].xy, TEMP[55].xyyy, -TEMP[56].xyyy 443: DP2 TEMP[203].x, TEMP[202].xyyy, TEMP[200].xyyy 444: DP2 TEMP[204].x, TEMP[202].xyyy, TEMP[201].xyyy 445: MOV TEMP[203].y, TEMP[204].xxxx 446: ADD TEMP[205].xy, TEMP[6].xyyy, -TEMP[56].xyyy 447: DP2 TEMP[206].x, TEMP[203].xyyy, TEMP[203].xyyy 448: RSQ TEMP[207].x, TEMP[206].xxxx 449: MUL TEMP[208].xy, TEMP[203].xyyy, TEMP[207].xxxx 450: DP2 TEMP[209].x, TEMP[205].xyyy, TEMP[208].xyyy 451: ELSE :0 452: MOV TEMP[210].x, -TEMP[195].xxxx 453: MOV TEMP[210].y, IMM[8].wwww 454: MOV TEMP[211].x, IMM[2].yyyy 455: MOV TEMP[211].y, -TEMP[195].xxxx 456: ADD TEMP[212].xy, TEMP[55].xyyy, -TEMP[56].xyyy 457: DP2 TEMP[213].x, TEMP[212].xyyy, TEMP[210].xyyy 458: DP2 TEMP[214].x, TEMP[212].xyyy, TEMP[211].xyyy 459: MOV TEMP[213].y, TEMP[214].xxxx 460: ADD TEMP[215].xy, TEMP[6].xyyy, -TEMP[55].xyyy 461: DP2 TEMP[216].x, TEMP[213].xyyy, TEMP[213].xyyy 462: RSQ TEMP[217].x, TEMP[216].xxxx 463: MUL TEMP[218].xy, TEMP[213].xyyy, TEMP[217].xxxx 464: DP2 TEMP[209].x, TEMP[215].xyyy, TEMP[218].xyyy 465: ENDIF 466: ABS TEMP[219].x, TEMP[209].xxxx 467: ABS TEMP[220].x, TEMP[180].xxxx 468: FSGE TEMP[221].x, TEMP[220].xxxx, TEMP[219].xxxx 469: UIF TEMP[221].xxxx :0 470: MOV TEMP[222].x, TEMP[180].xxxx 471: ELSE :0 472: MOV TEMP[222].x, TEMP[209].xxxx 473: ENDIF 474: ABS TEMP[11].x, TEMP[222].xxxx 475: SSG TEMP[10].x, TEMP[222].xxxx 476: ENDIF 477: ENDIF 478: ENDIF 479: UADD TEMP[13].x, TEMP[13].xxxx, IMM[3].zzzz 480: ENDLOOP :0 481: FSEQ TEMP[6].x, TEMP[10].xxxx, IMM[0].zzzz 482: UIF TEMP[6].xxxx :0 483: LRP TEMP[6].xy, IMM[2].zzzz, TEMP[156].xyyy, TEMP[155].xyyy 484: MUL TEMP[7].x, IMM[6].wwww, TEMP[157].xxxx 485: MUL TEMP[8].x, TEMP[157].xxxx, TEMP[157].xxxx 486: ADD TEMP[8].x, IMM[2].yyyy, -TEMP[8].xxxx 487: RCP TEMP[8].x, TEMP[8].xxxx 488: MUL TEMP[7].x, TEMP[7].xxxx, TEMP[8].xxxx 489: ADD TEMP[8].xy, IN[0].xyyy, -TEMP[6].xyyy 490: ADD TEMP[6].xy, TEMP[156].xyyy, -TEMP[6].xyyy 491: DP2 TEMP[6].x, TEMP[8].xyyy, TEMP[6].xyyy 492: FSLT TEMP[6].x, TEMP[6].xxxx, IMM[0].zzzz 493: UIF TEMP[6].xxxx :0 494: MOV TEMP[6].x, TEMP[7].xxxx 495: MOV TEMP[6].y, IMM[8].wwww 496: MOV TEMP[8].x, IMM[2].yyyy 497: MOV TEMP[8].y, TEMP[7].xxxx 498: ADD TEMP[9].xy, TEMP[156].xyyy, -TEMP[155].xyyy 499: DP2 TEMP[6].x, TEMP[9].xyyy, TEMP[6].xyyy 500: DP2 TEMP[8].x, TEMP[9].xyyy, TEMP[8].xyyy 501: MOV TEMP[6].y, TEMP[8].xxxx 502: ADD TEMP[8].xy, IN[0].xyyy, -TEMP[155].xyyy 503: DP2 TEMP[9].x, TEMP[6].xyyy, TEMP[6].xyyy 504: RSQ TEMP[9].x, TEMP[9].xxxx 505: MUL TEMP[6].xy, TEMP[6].xyyy, TEMP[9].xxxx 506: DP2 TEMP[6].x, TEMP[8].xyyy, TEMP[6].xyyy 507: ELSE :0 508: MOV TEMP[8].x, -TEMP[7].xxxx 509: MOV TEMP[8].y, IMM[8].wwww 510: MOV TEMP[9].x, IMM[2].yyyy 511: MOV TEMP[9].y, -TEMP[7].xxxx 512: ADD TEMP[7].xy, TEMP[156].xyyy, -TEMP[155].xyyy 513: DP2 TEMP[8].x, TEMP[7].xyyy, TEMP[8].xyyy 514: DP2 TEMP[7].x, TEMP[7].xyyy, TEMP[9].xyyy 515: MOV TEMP[8].y, TEMP[7].xxxx 516: ADD TEMP[7].xy, IN[0].xyyy, -TEMP[156].xyyy 517: DP2 TEMP[9].x, TEMP[8].xyyy, TEMP[8].xyyy 518: RSQ TEMP[9].x, TEMP[9].xxxx 519: MUL TEMP[8].xy, TEMP[8].xyyy, TEMP[9].xxxx 520: DP2 TEMP[6].x, TEMP[7].xyyy, TEMP[8].xyyy 521: ENDIF 522: SSG TEMP[10].x, TEMP[6].xxxx 523: ENDIF 524: MUL TEMP[17].x, TEMP[11].xxxx, TEMP[10].xxxx 525: ENDIF 526: ENDIF 527: RCP TEMP[5].x, TEMP[5].xxxx 528: MUL TEMP[5].x, TEMP[17].xxxx, TEMP[5].xxxx 529: MUL TEMP[5].x, TEMP[5].xxxx, CONST[2].xxxx 530: MOV TEMP[6].x, TEMP[5].xxxx 531: NOT TEMP[7].x, CONST[7].xxxx 532: UIF TEMP[7].xxxx :0 533: MUL TEMP[7].x, CONST[6].xxxx, IMM[9].xxxx 534: ADD TEMP[5].x, TEMP[5].xxxx, -TEMP[7].xxxx 535: MOV TEMP[6].x, TEMP[5].xxxx 536: UIF CONST[5].xxxx :0 537: ABS TEMP[5].x, TEMP[5].xxxx 538: MUL TEMP[7].x, CONST[4].xxxx, IMM[2].zzzz 539: ADD TEMP[6].x, TEMP[5].xxxx, -TEMP[7].xxxx 540: ENDIF 541: FSLT TEMP[5].x, IMM[2].yyyy, TEMP[6].xxxx 542: UIF TEMP[5].xxxx :0 543: KILL 544: ENDIF 545: MOV TEMP[5].x, -TEMP[6].xxxx 546: ADD_SAT TEMP[7].x, TEMP[5].xxxx, IMM[2].zzzz 547: FSGE TEMP[8].x, IMM[9].yyyy, TEMP[5].xxxx 548: UIF TEMP[8].xxxx :0 549: MOV TEMP[8].x, IMM[0].zzzz 550: ELSE :0 551: FSGE TEMP[9].x, TEMP[5].xxxx, IMM[0].wwww 552: UIF TEMP[9].xxxx :0 553: MOV TEMP[8].x, IMM[2].yyyy 554: ELSE :0 555: FSGE TEMP[9].x, IMM[0].zzzz, TEMP[5].xxxx 556: UIF TEMP[9].xxxx :0 557: ADD TEMP[9].x, TEMP[5].xxxx, IMM[0].wwww 558: POW TEMP[8].x, TEMP[9].xxxx, IMM[6].wwww 559: ELSE :0 560: ADD TEMP[5].x, IMM[0].wwww, -TEMP[5].xxxx 561: POW TEMP[5].x, TEMP[5].xxxx, IMM[6].wwww 562: ADD TEMP[8].x, IMM[2].yyyy, -TEMP[5].xxxx 563: ENDIF 564: ENDIF 565: ENDIF 566: ADD TEMP[3].x, TEMP[3].xxxx, IMM[8].wwww 567: MUL_SAT TEMP[3].x, TEMP[3].xxxx, IMM[9].zzzz 568: LRP TEMP[3].x, TEMP[3].xxxx, TEMP[8].xxxx, TEMP[7].xxxx 569: MOV TEMP[5].x, TEMP[3].xxxx 570: FSNE TEMP[7].x, CONST[3].xxxx, IMM[2].yyyy 571: UIF TEMP[7].xxxx :0 572: RCP TEMP[7].x, CONST[3].xxxx 573: POW TEMP[5].x, TEMP[3].xxxx, TEMP[7].xxxx 574: ENDIF 575: MOV TEMP[3].xyz, IMM[0].zzzz 576: MOV TEMP[3].w, TEMP[5].xxxx 577: MOV TEMP[4], TEMP[3] 578: ELSE :0 579: ADD TEMP[3].x, TEMP[6].xxxx, IMM[8].wwww 580: MUL_SAT TEMP[3].x, TEMP[3].xxxx, IMM[9].wwww 581: MUL TEMP[5].x, IMM[6].wwww, TEMP[3].xxxx 582: ADD TEMP[5].x, IMM[10].xxxx, -TEMP[5].xxxx 583: MUL TEMP[5].x, TEMP[3].xxxx, TEMP[5].xxxx 584: MUL TEMP[3].x, TEMP[3].xxxx, TEMP[5].xxxx 585: MUL TEMP[4], IMM[2].zxxz, TEMP[3].xxxx 586: ABS TEMP[3].x, TEMP[6].xxxx 587: ADD TEMP[5].x, TEMP[3].xxxx, IMM[10].yyyy 588: MOV_SAT TEMP[5].x, -TEMP[5].xxxx 589: MUL TEMP[6].x, IMM[6].wwww, TEMP[5].xxxx 590: ADD TEMP[6].x, IMM[10].xxxx, -TEMP[6].xxxx 591: MUL TEMP[6].x, TEMP[5].xxxx, TEMP[6].xxxx 592: MUL TEMP[5].x, TEMP[5].xxxx, TEMP[6].xxxx 593: MAD TEMP[4], IMM[2].yxxy, TEMP[5].xxxx, TEMP[4] 594: ABS TEMP[3].x, TEMP[3].xxxx 595: FSGE TEMP[3].x, TEMP[3].xxxx, IMM[6].zzzz 596: NOT TEMP[3].x, TEMP[3].xxxx 597: UIF TEMP[3].xxxx :0 598: MOV TEMP[3].xyz, IMM[10].zwzz 599: ABS TEMP[5].x, TEMP[17].xxxx 600: I2F TEMP[6].x, TEMP[1].xxxx 601: I2F TEMP[7].x, TEMP[1].yyyy 602: MAX TEMP[6].x, TEMP[6].xxxx, TEMP[7].xxxx 603: RCP TEMP[6].x, TEMP[6].xxxx 604: MUL TEMP[5].x, TEMP[5].xxxx, TEMP[6].xxxx 605: MUL TEMP[5].x, TEMP[5].xxxx, IMM[8].yyyy 606: ADD TEMP[5].x, IMM[10].wwww, -TEMP[5].xxxx 607: MOV TEMP[3].w, TEMP[5].xxxx 608: ADD TEMP[4], TEMP[4], TEMP[3] 609: ENDIF 610: MOV TEMP[0].xy, TEMP[0].xyxx 611: MOV TEMP[3].xy, TEMP[1].xyxx 612: MOV TEMP[5], CONST[1] 613: MOV TEMP[6].xy, TEMP[2].xyxx 614: FLR TEMP[7].xy, IN[0].xyyy 615: MAX TEMP[7].xy, TEMP[7].xyyy, IMM[0].zzzz 616: UADD TEMP[8].xy, TEMP[1].xyyy, IMM[1].wwww 617: I2F TEMP[8].xy, TEMP[8].xyyy 618: MIN TEMP[7].xy, TEMP[7].xyyy, TEMP[8].xyyy 619: F2I TEMP[7].xy, TEMP[7].xyyy 620: UMAD TEMP[7].x, TEMP[7].yyyy, TEMP[1].xxxx, TEMP[7].xxxx 621: I2F TEMP[8].x, CONST[1].zzzz 622: I2F TEMP[9].x, TEMP[7].xxxx 623: RCP TEMP[10].x, TEMP[8].xxxx 624: MUL TEMP[9].x, TEMP[9].xxxx, TEMP[10].xxxx 625: FRC TEMP[9].x, TEMP[9].xxxx 626: MUL TEMP[8].x, TEMP[8].xxxx, TEMP[9].xxxx 627: F2I TEMP[8].x, TEMP[8].xxxx 628: IDIV TEMP[7].x, TEMP[7].xxxx, CONST[1].zzzz 629: MOV TEMP[8].y, TEMP[7].xxxx 630: UMAD TEMP[7].xy, TEMP[2].xyyy, CONST[1].zwww, TEMP[8].xyyy 631: I2F TEMP[7].xy, TEMP[7].xyyy 632: ADD TEMP[7].xy, TEMP[7].xyyy, IMM[2].zzzz 633: I2F TEMP[8].xy, CONST[1].xyyy 634: RCP TEMP[9].x, TEMP[8].xxxx 635: RCP TEMP[9].y, TEMP[8].yyyy 636: MUL TEMP[7].xy, TEMP[7].xyyy, TEMP[9].xyyy 637: MOV TEMP[7].xy, TEMP[7].xyyy 638: TEX TEMP[7], TEMP[7], SAMP[0], 2D 639: MUL TEMP[7], TEMP[7], IMM[2].wwww 640: F2I TEMP[7], TEMP[7] 641: USEQ TEMP[8].x, TEMP[7].xxxx, IMM[3].xxxx 642: UIF TEMP[8].xxxx :0 643: UMAD TEMP[8].x, TEMP[7].yyyy, IMM[1].zzzz, TEMP[7].zzzz 644: MOV TEMP[9].x, TEMP[7].wwww 645: USEQ TEMP[7].x, TEMP[7].wwww, IMM[3].yyyy 646: UIF TEMP[7].xxxx :0 647: MOV TEMP[9].x, IMM[3].xxxx 648: ENDIF 649: ELSE :0 650: MOV TEMP[9].x, IMM[1].wwww 651: ENDIF 652: MOV TEMP[7].x, TEMP[9].xxxx 653: MOV TEMP[10].x, TEMP[8].xxxx 654: MOV TEMP[11].x, IMM[5].zzzz 655: USEQ TEMP[9].x, TEMP[9].xxxx, IMM[3].xxxx 656: UIF TEMP[9].xxxx :0 657: MOV TEMP[9].x, IMM[5].zzzz 658: ELSE :0 659: I2F TEMP[12].x, CONST[1].zzzz 660: I2F TEMP[13].x, TEMP[8].xxxx 661: RCP TEMP[14].x, TEMP[12].xxxx 662: MUL TEMP[13].x, TEMP[13].xxxx, TEMP[14].xxxx 663: FRC TEMP[13].x, TEMP[13].xxxx 664: MUL TEMP[12].x, TEMP[12].xxxx, TEMP[13].xxxx 665: F2I TEMP[12].x, TEMP[12].xxxx 666: IDIV TEMP[8].x, TEMP[8].xxxx, CONST[1].zzzz 667: MOV TEMP[12].y, TEMP[8].xxxx 668: UMAD TEMP[8].xy, TEMP[2].xyyy, CONST[1].zwww, TEMP[12].xyyy 669: I2F TEMP[8].xy, TEMP[8].xyyy 670: ADD TEMP[8].xy, TEMP[8].xyyy, IMM[2].zzzz 671: I2F TEMP[12].xy, CONST[1].xyyy 672: RCP TEMP[13].x, TEMP[12].xxxx 673: RCP TEMP[13].y, TEMP[12].yyyy 674: MUL TEMP[8].xy, TEMP[8].xyyy, TEMP[13].xyyy 675: MOV TEMP[8].xy, TEMP[8].xyyy 676: TEX TEMP[8], TEMP[8], SAMP[0], 2D 677: MOV TEMP[12].x, TEMP[8].xxxx 678: FSEQ TEMP[8].x, TEMP[8].xxxx, IMM[0].zzzz 679: UIF TEMP[8].xxxx :0 680: MOV TEMP[12].x, IMM[5].zzzz 681: ELSE :0 682: MUL TEMP[8].x, TEMP[12].xxxx, IMM[2].wwww 683: F2I TEMP[8].x, TEMP[8].xxxx 684: UADD TEMP[223].x, TEMP[8].xxxx, IMM[3].wwww 685: ENDIF 686: MOV TEMP[8].x, IMM[3].zzzz 687: BGNLOOP :0 688: ISGE TEMP[12].x, TEMP[8].xxxx, IMM[4].wwww 689: UIF TEMP[12].xxxx :0 690: BRK 691: ENDIF 692: ISGE TEMP[13].x, TEMP[8].xxxx, TEMP[7].xxxx 693: UIF TEMP[13].xxxx :0 694: BRK 695: ENDIF 696: UADD TEMP[14].x, TEMP[10].xxxx, TEMP[8].xxxx 697: I2F TEMP[15].x, TEMP[5].zzzz 698: I2F TEMP[16].x, TEMP[14].xxxx 699: RCP TEMP[17].x, TEMP[15].xxxx 700: MUL TEMP[18].x, TEMP[16].xxxx, TEMP[17].xxxx 701: FRC TEMP[20].x, TEMP[18].xxxx 702: MUL TEMP[21].x, TEMP[15].xxxx, TEMP[20].xxxx 703: F2I TEMP[22].x, TEMP[21].xxxx 704: IDIV TEMP[23].x, TEMP[14].xxxx, TEMP[5].zzzz 705: MOV TEMP[22].y, TEMP[23].xxxx 706: UMAD TEMP[24].xy, TEMP[6].xyyy, TEMP[5].zwww, TEMP[22].xyyy 707: I2F TEMP[25].xy, TEMP[24].xyyy 708: ADD TEMP[26].xy, TEMP[25].xyyy, IMM[2].zzzz 709: I2F TEMP[27].xy, TEMP[5].xyyy 710: RCP TEMP[28].x, TEMP[27].xxxx 711: RCP TEMP[28].y, TEMP[27].yyyy 712: MUL TEMP[29].xy, TEMP[26].xyyy, TEMP[28].xyyy 713: MOV TEMP[30].xy, TEMP[29].xyyy 714: TEX TEMP[31], TEMP[30], SAMP[0], 2D 715: MUL TEMP[32].x, TEMP[31].wwww, IMM[2].wwww 716: F2I TEMP[33].x, TEMP[32].xxxx 717: IDIV TEMP[34].x, TEMP[33].xxxx, IMM[4].zzzz 718: I2F TEMP[35].x, TEMP[33].xxxx 719: MUL TEMP[36].x, TEMP[35].xxxx, IMM[6].xxxx 720: FRC TEMP[37].x, TEMP[36].xxxx 721: MUL TEMP[38].x, IMM[5].wwww, TEMP[37].xxxx 722: F2I TEMP[39].x, TEMP[38].xxxx 723: MOV TEMP[34].y, TEMP[39].xxxx 724: I2F TEMP[40].xy, TEMP[34].xyyy 725: ADD TEMP[41].xy, TEMP[40].xyyy, TEMP[31].yzzz 726: MUL TEMP[42].xy, TEMP[41].xyyy, IMM[6].xxxx 727: MOV TEMP[43].x, TEMP[31].xxxx 728: FSEQ TEMP[44].x, TEMP[31].xxxx, IMM[0].zzzz 729: UIF TEMP[44].xxxx :0 730: MOV TEMP[43].x, IMM[5].zzzz 731: ELSE :0 732: MUL TEMP[45].x, TEMP[43].xxxx, IMM[2].wwww 733: F2I TEMP[46].x, TEMP[45].xxxx 734: UADD TEMP[47].x, TEMP[46].xxxx, IMM[3].wwww 735: I2F TEMP[48].x, TEMP[47].xxxx 736: MUL TEMP[43].x, IMM[6].yyyy, TEMP[48].xxxx 737: ENDIF 738: I2F TEMP[49].xy, TEMP[3].xyyy 739: MUL TEMP[50].xy, TEMP[42].xyyy, TEMP[49].xyyy 740: ABS TEMP[51].x, TEMP[43].xxxx 741: FSGE TEMP[52].x, TEMP[51].xxxx, IMM[6].zzzz 742: UIF TEMP[52].xxxx :0 743: UADD TEMP[8].x, TEMP[8].xxxx, IMM[3].zzzz 744: CONT 745: ENDIF 746: ADD TEMP[53].xy, TEMP[0].xyyy, -TEMP[50].xyyy 747: DP2 TEMP[54].x, TEMP[53].xyyy, TEMP[53].xyyy 748: RSQ TEMP[55].x, TEMP[54].xxxx 749: MUL TEMP[55].x, TEMP[55].xxxx, TEMP[54].xxxx 750: CMP TEMP[55].x, -TEMP[54].xxxx, TEMP[55].xxxx, IMM[0].zzzz 751: MIN TEMP[11].x, TEMP[11].xxxx, TEMP[55].xxxx 752: UADD TEMP[8].x, TEMP[8].xxxx, IMM[3].zzzz 753: ENDLOOP :0 754: MOV TEMP[9].x, TEMP[11].xxxx 755: ENDIF 756: ADD TEMP[0].x, TEMP[9].xxxx, IMM[11].xxxx 757: MUL_SAT TEMP[0].x, TEMP[0].xxxx, IMM[11].yyyy 758: MUL TEMP[3].x, IMM[6].wwww, TEMP[0].xxxx 759: ADD TEMP[3].x, IMM[10].xxxx, -TEMP[3].xxxx 760: MUL TEMP[3].x, TEMP[0].xxxx, TEMP[3].xxxx 761: MUL TEMP[0].x, TEMP[0].xxxx, TEMP[3].xxxx 762: LRP TEMP[0], TEMP[0].xxxx, TEMP[4], IMM[2].xyxz 763: FLR TEMP[3].xy, IN[0].xyyy 764: MAX TEMP[3].xy, TEMP[3].xyyy, IMM[0].zzzz 765: UADD TEMP[5].xy, TEMP[1].xyyy, IMM[1].wwww 766: I2F TEMP[5].xy, TEMP[5].xyyy 767: MIN TEMP[3].xy, TEMP[3].xyyy, TEMP[5].xyyy 768: F2I TEMP[3].xy, TEMP[3].xyyy 769: UMAD TEMP[1].x, TEMP[3].yyyy, TEMP[1].xxxx, TEMP[3].xxxx 770: I2F TEMP[3].x, CONST[1].zzzz 771: I2F TEMP[5].x, TEMP[1].xxxx 772: RCP TEMP[6].x, TEMP[3].xxxx 773: MUL TEMP[5].x, TEMP[5].xxxx, TEMP[6].xxxx 774: FRC TEMP[5].x, TEMP[5].xxxx 775: MUL TEMP[3].x, TEMP[3].xxxx, TEMP[5].xxxx 776: F2I TEMP[3].x, TEMP[3].xxxx 777: IDIV TEMP[1].x, TEMP[1].xxxx, CONST[1].zzzz 778: MOV TEMP[3].y, TEMP[1].xxxx 779: UMAD TEMP[1].xy, TEMP[2].xyyy, CONST[1].zwww, TEMP[3].xyyy 780: I2F TEMP[1].xy, TEMP[1].xyyy 781: ADD TEMP[1].xy, TEMP[1].xyyy, IMM[2].zzzz 782: I2F TEMP[2].xy, CONST[1].xyyy 783: RCP TEMP[3].x, TEMP[2].xxxx 784: RCP TEMP[3].y, TEMP[2].yyyy 785: MUL TEMP[1].xy, TEMP[1].xyyy, TEMP[3].xyyy 786: MOV TEMP[1].xy, TEMP[1].xyyy 787: TEX TEMP[1], TEMP[1], SAMP[0], 2D 788: MUL TEMP[1], TEMP[1], IMM[2].wwww 789: F2I TEMP[1].xw, TEMP[1] 790: USEQ TEMP[2].x, TEMP[1].xxxx, IMM[3].xxxx 791: UIF TEMP[2].xxxx :0 792: MOV TEMP[2].x, TEMP[1].wwww 793: USEQ TEMP[1].x, TEMP[1].wwww, IMM[3].yyyy 794: UIF TEMP[1].xxxx :0 795: MOV TEMP[2].x, IMM[3].xxxx 796: ENDIF 797: ELSE :0 798: MOV TEMP[2].x, IMM[1].wwww 799: ENDIF 800: I2F TEMP[1].x, TEMP[2].xxxx 801: MAD TEMP[4], IMM[12].xxyz, TEMP[1].xxxx, TEMP[0] 802: ENDIF 803: MOV OUT[0], TEMP[4] 804: END ; ModuleID = 'tgsi' define void @main() #0 { main_body: %0 = call float @llvm.R600.load.input(i32 0) %1 = call float @llvm.R600.load.input(i32 1) %2 = call float @llvm.R600.load.input(i32 2) %3 = call float @llvm.R600.load.input(i32 3) %4 = fmul float %2, 3.906250e-03 %5 = fmul float %3, 3.906250e-03 %6 = call float @llvm.AMDIL.fraction.(float %4) %7 = call float @llvm.AMDIL.fraction.(float %5) %8 = fmul float 2.560000e+02, %6 %9 = fmul float 2.560000e+02, %7 %10 = fptosi float %8 to i32 %11 = fptosi float %9 to i32 %12 = bitcast i32 %10 to float %13 = bitcast i32 %11 to float %14 = bitcast float %12 to i32 %15 = add i32 %14, 2 %16 = bitcast float %13 to i32 %17 = add i32 %16, 2 %18 = bitcast i32 %15 to float %19 = bitcast i32 %17 to float %20 = bitcast float %18 to i32 %21 = sdiv i32 %20, 4 %22 = bitcast float %19 to i32 %23 = sdiv i32 %22, 4 %24 = bitcast i32 %21 to float %25 = bitcast i32 %23 to float %26 = fptosi float %2 to i32 %27 = fptosi float %3 to i32 %28 = bitcast i32 %26 to float %29 = bitcast i32 %27 to float %30 = bitcast float %28 to i32 %31 = sdiv i32 %30, 256 %32 = bitcast float %29 to i32 %33 = sdiv i32 %32, 256 %34 = bitcast i32 %31 to float %35 = bitcast i32 %33 to float %36 = insertelement <4 x float> undef, float %0, i32 0 %37 = insertelement <4 x float> %36, float %1, i32 1 %38 = insertelement <4 x float> %37, float %1, i32 2 %39 = insertelement <4 x float> %38, float %1, i32 3 %40 = call <4 x float> @llvm.AMDGPU.ddx(<4 x float> %39, i32 16, i32 0, i32 0) %41 = insertelement <4 x float> undef, float %0, i32 0 %42 = insertelement <4 x float> %41, float %1, i32 1 %43 = insertelement <4 x float> %42, float %1, i32 2 %44 = insertelement <4 x float> %43, float %1, i32 3 %45 = call <4 x float> @llvm.AMDGPU.ddx(<4 x float> %44, i32 16, i32 0, i32 0) %46 = extractelement <4 x float> %45, i32 0 %47 = extractelement <4 x float> %45, i32 1 %48 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8) %49 = extractelement <4 x float> %48, i32 0 %50 = fmul float %49, %0 %51 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8) %52 = extractelement <4 x float> %51, i32 0 %53 = fmul float %52, %1 %54 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8) %55 = extractelement <4 x float> %54, i32 0 %56 = fmul float %55, %1 %57 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8) %58 = extractelement <4 x float> %57, i32 0 %59 = fmul float %58, %1 %60 = insertelement <4 x float> undef, float %50, i32 0 %61 = insertelement <4 x float> %60, float %53, i32 1 %62 = insertelement <4 x float> %61, float %56, i32 2 %63 = insertelement <4 x float> %62, float %59, i32 3 %64 = call <4 x float> @llvm.AMDGPU.ddy(<4 x float> %63, i32 20, i32 4, i32 0) %65 = insertelement <4 x float> undef, float %50, i32 0 %66 = insertelement <4 x float> %65, float %53, i32 1 %67 = insertelement <4 x float> %66, float %56, i32 2 %68 = insertelement <4 x float> %67, float %59, i32 3 %69 = call <4 x float> @llvm.AMDGPU.ddy(<4 x float> %68, i32 20, i32 4, i32 0) %70 = extractelement <4 x float> %69, i32 0 %71 = extractelement <4 x float> %69, i32 1 %72 = insertelement <4 x float> undef, float %46, i32 0 %73 = insertelement <4 x float> %72, float %47, i32 1 %74 = insertelement <4 x float> %73, float 0.000000e+00, i32 2 %75 = insertelement <4 x float> %74, float 0.000000e+00, i32 3 %76 = insertelement <4 x float> undef, float %46, i32 0 %77 = insertelement <4 x float> %76, float %47, i32 1 %78 = insertelement <4 x float> %77, float 0.000000e+00, i32 2 %79 = insertelement <4 x float> %78, float 0.000000e+00, i32 3 %80 = call float @llvm.AMDGPU.dp4(<4 x float> %75, <4 x float> %79) %81 = call float @llvm.AMDGPU.rsq(float %80) %82 = fmul float %81, %80 %83 = fsub float -0.000000e+00, %80 %84 = fcmp ult float %83, 0.000000e+00 %85 = select i1 %84, float %82, float 0.000000e+00 %86 = insertelement <4 x float> undef, float %70, i32 0 %87 = insertelement <4 x float> %86, float %71, i32 1 %88 = insertelement <4 x float> %87, float 0.000000e+00, i32 2 %89 = insertelement <4 x float> %88, float 0.000000e+00, i32 3 %90 = insertelement <4 x float> undef, float %70, i32 0 %91 = insertelement <4 x float> %90, float %71, i32 1 %92 = insertelement <4 x float> %91, float 0.000000e+00, i32 2 %93 = insertelement <4 x float> %92, float 0.000000e+00, i32 3 %94 = call float @llvm.AMDGPU.dp4(<4 x float> %89, <4 x float> %93) %95 = call float @llvm.AMDGPU.rsq(float %94) %96 = fmul float %95, %94 %97 = fsub float -0.000000e+00, %94 %98 = fcmp ult float %97, 0.000000e+00 %99 = select i1 %98, float %96, float 0.000000e+00 %100 = insertelement <4 x float> undef, float %85, i32 0 %101 = insertelement <4 x float> %100, float %99, i32 1 %102 = insertelement <4 x float> %101, float 0.000000e+00, i32 2 %103 = insertelement <4 x float> %102, float 0.000000e+00, i32 3 %104 = insertelement <4 x float> undef, float %85, i32 0 %105 = insertelement <4 x float> %104, float %99, i32 1 %106 = insertelement <4 x float> %105, float 0.000000e+00, i32 2 %107 = insertelement <4 x float> %106, float 0.000000e+00, i32 3 %108 = call float @llvm.AMDGPU.dp4(<4 x float> %103, <4 x float> %107) %109 = call float @llvm.AMDGPU.rsq(float %108) %110 = fmul float %109, %108 %111 = fsub float -0.000000e+00, %108 %112 = fcmp ult float %111, 0.000000e+00 %113 = select i1 %112, float %110, float 0.000000e+00 %114 = fmul float %113, 0x3FE6A09E60000000 %115 = insertelement <4 x float> undef, float %46, i32 0 %116 = insertelement <4 x float> %115, float %47, i32 1 %117 = insertelement <4 x float> %116, float 0.000000e+00, i32 2 %118 = insertelement <4 x float> %117, float 0.000000e+00, i32 3 %119 = insertelement <4 x float> undef, float %46, i32 0 %120 = insertelement <4 x float> %119, float %47, i32 1 %121 = insertelement <4 x float> %120, float 0.000000e+00, i32 2 %122 = insertelement <4 x float> %121, float 0.000000e+00, i32 3 %123 = call float @llvm.AMDGPU.dp4(<4 x float> %118, <4 x float> %122) %124 = call float @llvm.AMDGPU.rsq(float %123) %125 = fmul float %46, %124 %126 = call float @fabs(float %125) %127 = insertelement <4 x float> undef, float %70, i32 0 %128 = insertelement <4 x float> %127, float %71, i32 1 %129 = insertelement <4 x float> %128, float 0.000000e+00, i32 2 %130 = insertelement <4 x float> %129, float 0.000000e+00, i32 3 %131 = insertelement <4 x float> undef, float %70, i32 0 %132 = insertelement <4 x float> %131, float %71, i32 1 %133 = insertelement <4 x float> %132, float 0.000000e+00, i32 2 %134 = insertelement <4 x float> %133, float 0.000000e+00, i32 3 %135 = call float @llvm.AMDGPU.dp4(<4 x float> %130, <4 x float> %134) %136 = call float @llvm.AMDGPU.rsq(float %135) %137 = fmul float %70, %136 %138 = call float @fabs(float %137) %139 = fadd float %126, %138 %140 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %141 = extractelement <4 x float> %140, i32 0 %142 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %143 = extractelement <4 x float> %142, i32 1 %144 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %145 = extractelement <4 x float> %144, i32 2 %146 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %147 = extractelement <4 x float> %146, i32 3 %148 = call float @floor(float %0) %149 = call float @floor(float %1) %150 = fcmp uge float %148, 0.000000e+00 %151 = select i1 %150, float %148, float 0.000000e+00 %152 = fcmp uge float %149, 0.000000e+00 %153 = select i1 %152, float %149, float 0.000000e+00 %154 = bitcast float %24 to i32 %155 = add i32 %154, -1 %156 = bitcast float %25 to i32 %157 = add i32 %156, -1 %158 = bitcast i32 %155 to float %159 = bitcast i32 %157 to float %160 = bitcast float %158 to i32 %161 = sitofp i32 %160 to float %162 = bitcast float %159 to i32 %163 = sitofp i32 %162 to float %164 = fcmp uge float %151, %161 %165 = select i1 %164, float %161, float %151 %166 = fcmp uge float %153, %163 %167 = select i1 %166, float %163, float %153 %168 = fptosi float %165 to i32 %169 = fptosi float %167 to i32 %170 = bitcast i32 %168 to float %171 = bitcast i32 %169 to float %172 = bitcast float %171 to i32 %173 = bitcast float %24 to i32 %174 = bitcast float %170 to i32 %175 = mul i32 %172, %173 %176 = add i32 %175, %174 %177 = bitcast i32 %176 to float %178 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %179 = extractelement <4 x float> %178, i32 2 %180 = bitcast float %179 to i32 %181 = sitofp i32 %180 to float %182 = bitcast float %177 to i32 %183 = sitofp i32 %182 to float %184 = fdiv float 1.000000e+00, %181 %185 = fmul float %183, %184 %186 = call float @llvm.AMDIL.fraction.(float %185) %187 = fmul float %181, %186 %188 = fptosi float %187 to i32 %189 = bitcast i32 %188 to float %190 = bitcast float %177 to i32 %191 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %192 = extractelement <4 x float> %191, i32 2 %193 = bitcast float %192 to i32 %194 = sdiv i32 %190, %193 %195 = bitcast i32 %194 to float %196 = bitcast float %34 to i32 %197 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %198 = extractelement <4 x float> %197, i32 2 %199 = bitcast float %198 to i32 %200 = bitcast float %189 to i32 %201 = mul i32 %196, %199 %202 = add i32 %201, %200 %203 = bitcast float %35 to i32 %204 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %205 = extractelement <4 x float> %204, i32 3 %206 = bitcast float %205 to i32 %207 = bitcast float %195 to i32 %208 = mul i32 %203, %206 %209 = add i32 %208, %207 %210 = bitcast i32 %202 to float %211 = bitcast i32 %209 to float %212 = bitcast float %210 to i32 %213 = sitofp i32 %212 to float %214 = bitcast float %211 to i32 %215 = sitofp i32 %214 to float %216 = fadd float %213, 5.000000e-01 %217 = fadd float %215, 5.000000e-01 %218 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %219 = extractelement <4 x float> %218, i32 0 %220 = bitcast float %219 to i32 %221 = sitofp i32 %220 to float %222 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %223 = extractelement <4 x float> %222, i32 1 %224 = bitcast float %223 to i32 %225 = sitofp i32 %224 to float %226 = fdiv float 1.000000e+00, %221 %227 = fdiv float 1.000000e+00, %225 %228 = fmul float %216, %226 %229 = fmul float %217, %227 %230 = insertelement <4 x float> undef, float %228, i32 0 %231 = insertelement <4 x float> %230, float %229, i32 1 %232 = insertelement <4 x float> %231, float 0.000000e+00, i32 2 %233 = insertelement <4 x float> %232, float 0.000000e+00, i32 3 %234 = extractelement <4 x float> %233, i32 0 %235 = extractelement <4 x float> %233, i32 1 %236 = insertelement <4 x float> undef, float %234, i32 0 %237 = insertelement <4 x float> %236, float %235, i32 1 %238 = insertelement <4 x float> %237, float undef, i32 2 %239 = insertelement <4 x float> %238, float undef, i32 3 %240 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %239, i32 16, i32 0, i32 2) %241 = extractelement <4 x float> %240, i32 0 %242 = extractelement <4 x float> %240, i32 1 %243 = extractelement <4 x float> %240, i32 2 %244 = extractelement <4 x float> %240, i32 3 %245 = fmul float %241, 0x406FFFFFE0000000 %246 = fmul float %242, 0x406FFFFFE0000000 %247 = fmul float %243, 0x406FFFFFE0000000 %248 = fmul float %244, 0x406FFFFFE0000000 %249 = fptosi float %245 to i32 %250 = fptosi float %246 to i32 %251 = fptosi float %247 to i32 %252 = fptosi float %248 to i32 %253 = bitcast i32 %249 to float %254 = bitcast i32 %250 to float %255 = bitcast i32 %251 to float %256 = bitcast i32 %252 to float %257 = bitcast float %253 to i32 %258 = icmp eq i32 %257, 0 %259 = sext i1 %258 to i32 %260 = bitcast i32 %259 to float %261 = bitcast float %260 to i32 %262 = icmp ne i32 %261, 0 br i1 %262, label %IF, label %ELSE IF: ; preds = %main_body %263 = bitcast float %254 to i32 %264 = bitcast float %255 to i32 %265 = mul i32 %263, 256 %266 = add i32 %265, %264 %267 = bitcast i32 %266 to float %268 = bitcast float %256 to i32 %269 = icmp eq i32 %268, 255 %270 = sext i1 %269 to i32 %271 = bitcast i32 %270 to float %272 = bitcast float %271 to i32 %273 = icmp ne i32 %272, 0 br i1 %273, label %ENDIF, label %ELSE898 ELSE: ; preds = %main_body %274 = bitcast float %253 to i32 %275 = add i32 %274, -128 %276 = bitcast i32 %275 to float %277 = bitcast float %276 to i32 %278 = bitcast float %254 to i32 %279 = mul i32 %277, 256 %280 = add i32 %279, %278 %281 = bitcast i32 %280 to float %282 = bitcast float %281 to i32 %283 = add i32 %282, -16384 %284 = bitcast i32 %283 to float %285 = bitcast float %284 to i32 %286 = sitofp i32 %285 to float %287 = fmul float %286, 0x3F20008000000000 %288 = bitcast float %24 to i32 %289 = sitofp i32 %288 to float %290 = bitcast float %25 to i32 %291 = sitofp i32 %290 to float %292 = fcmp uge float %289, %291 %293 = select i1 %292, float %289, float %291 %294 = fmul float %287, %293 %295 = bitcast float %255 to i32 %296 = bitcast float %256 to i32 %297 = mul i32 %295, 256 %298 = add i32 %297, %296 %299 = bitcast i32 %298 to float %300 = bitcast float %299 to i32 %301 = add i32 %300, -32768 %302 = bitcast i32 %301 to float %303 = bitcast float %302 to i32 %304 = sub i32 0, %303 %305 = bitcast i32 %304 to float %306 = bitcast float %305 to i32 %307 = sitofp i32 %306 to float %308 = fmul float 0x3F19222DA0000000, %307 br label %ENDIF ENDIF: ; preds = %ELSE898, %IF, %ELSE %temp56.0 = phi float [ %294, %ELSE ], [ %318, %ELSE898 ], [ %271, %IF ] %temp52.0 = phi float [ 0xFFFFFFFFE0000000, %ELSE ], [ %256, %ELSE898 ], [ 0.000000e+00, %IF ] %temp48.0 = phi float [ %260, %ELSE ], [ %267, %IF ], [ %267, %ELSE898 ] %temp44.0 = phi float [ 0.000000e+00, %ELSE ], [ %., %ELSE898 ], [ 0xFFFFFFFFE0000000, %IF ] %temp40.0 = phi float [ %308, %ELSE ], [ %253, %IF ], [ %253, %ELSE898 ] %309 = bitcast float %temp52.0 to i32 %310 = icmp eq i32 %309, 0 %311 = sext i1 %310 to i32 %312 = bitcast i32 %311 to float %313 = bitcast float %312 to i32 %314 = icmp ne i32 %313, 0 br i1 %314, label %IF903, label %ELSE904 ELSE898: ; preds = %IF %315 = bitcast float %256 to i32 %316 = icmp eq i32 %315, 0 %317 = sext i1 %316 to i32 %318 = bitcast i32 %317 to float %319 = bitcast float %318 to i32 %320 = icmp ne i32 %319, 0 %. = select i1 %320, float 0x36A0000000000000, float 0.000000e+00 br label %ENDIF IF903: ; preds = %ENDIF %321 = bitcast float %temp44.0 to i32 %322 = sitofp i32 %321 to float %323 = fmul float 1.000000e+09, %322 br label %ENDIF902 ELSE904: ; preds = %ENDIF %324 = bitcast float %temp52.0 to i32 %325 = icmp eq i32 %324, -1 %326 = sext i1 %325 to i32 %327 = bitcast i32 %326 to float %328 = bitcast float %327 to i32 %329 = icmp ne i32 %328, 0 br i1 %329, label %IF906, label %ELSE907 ENDIF902: ; preds = %IF906, %ENDIF965, %IF903 %temp68.0 = phi float [ %323, %IF903 ], [ %364, %IF906 ], [ %1268, %ENDIF965 ] %330 = fdiv float 1.000000e+00, %114 %331 = fmul float %temp68.0, %330 %332 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %333 = extractelement <4 x float> %332, i32 0 %334 = fmul float %331, %333 %335 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) %336 = extractelement <4 x float> %335, i32 0 %337 = bitcast float %336 to i32 %338 = xor i32 %337, -1 %339 = bitcast i32 %338 to float %340 = bitcast float %339 to i32 %341 = icmp ne i32 %340, 0 br i1 %341, label %IF972, label %ELSE973 IF906: ; preds = %ELSE904 %342 = call float @llvm.cos.f32(float %temp40.0) %343 = call float @llvm.sin.f32(float %temp40.0) %344 = bitcast float %24 to i32 %345 = sitofp i32 %344 to float %346 = bitcast float %25 to i32 %347 = sitofp i32 %346 to float %348 = fmul float %345, 5.000000e-01 %349 = fmul float %347, 5.000000e-01 %350 = fsub float -0.000000e+00, %348 %351 = fadd float %0, %350 %352 = fsub float -0.000000e+00, %349 %353 = fadd float %1, %352 %354 = insertelement <4 x float> undef, float %351, i32 0 %355 = insertelement <4 x float> %354, float %353, i32 1 %356 = insertelement <4 x float> %355, float 0.000000e+00, i32 2 %357 = insertelement <4 x float> %356, float 0.000000e+00, i32 3 %358 = insertelement <4 x float> undef, float %342, i32 0 %359 = insertelement <4 x float> %358, float %343, i32 1 %360 = insertelement <4 x float> %359, float 0.000000e+00, i32 2 %361 = insertelement <4 x float> %360, float 0.000000e+00, i32 3 %362 = call float @llvm.AMDGPU.dp4(<4 x float> %357, <4 x float> %361) %363 = fsub float -0.000000e+00, %temp56.0 %364 = fadd float %362, %363 br label %ENDIF902 ELSE907: ; preds = %ELSE904 %365 = bitcast float %temp44.0 to i32 %366 = sitofp i32 %365 to float %367 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %368 = extractelement <4 x float> %367, i32 2 %369 = bitcast float %368 to i32 %370 = sitofp i32 %369 to float %371 = bitcast float %temp48.0 to i32 %372 = sitofp i32 %371 to float %373 = fdiv float 1.000000e+00, %370 %374 = fmul float %372, %373 %375 = call float @llvm.AMDIL.fraction.(float %374) %376 = fmul float %370, %375 %377 = fptosi float %376 to i32 %378 = bitcast i32 %377 to float %379 = bitcast float %temp48.0 to i32 %380 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %381 = extractelement <4 x float> %380, i32 2 %382 = bitcast float %381 to i32 %383 = sdiv i32 %379, %382 %384 = bitcast i32 %383 to float %385 = bitcast float %34 to i32 %386 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %387 = extractelement <4 x float> %386, i32 2 %388 = bitcast float %387 to i32 %389 = bitcast float %378 to i32 %390 = mul i32 %385, %388 %391 = add i32 %390, %389 %392 = bitcast float %35 to i32 %393 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %394 = extractelement <4 x float> %393, i32 3 %395 = bitcast float %394 to i32 %396 = bitcast float %384 to i32 %397 = mul i32 %392, %395 %398 = add i32 %397, %396 %399 = bitcast i32 %391 to float %400 = bitcast i32 %398 to float %401 = bitcast float %399 to i32 %402 = sitofp i32 %401 to float %403 = bitcast float %400 to i32 %404 = sitofp i32 %403 to float %405 = fadd float %402, 5.000000e-01 %406 = fadd float %404, 5.000000e-01 %407 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %408 = extractelement <4 x float> %407, i32 0 %409 = bitcast float %408 to i32 %410 = sitofp i32 %409 to float %411 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %412 = extractelement <4 x float> %411, i32 1 %413 = bitcast float %412 to i32 %414 = sitofp i32 %413 to float %415 = fdiv float 1.000000e+00, %410 %416 = fdiv float 1.000000e+00, %414 %417 = fmul float %405, %415 %418 = fmul float %406, %416 %419 = insertelement <4 x float> undef, float %417, i32 0 %420 = insertelement <4 x float> %419, float %418, i32 1 %421 = insertelement <4 x float> %420, float 0.000000e+00, i32 2 %422 = insertelement <4 x float> %421, float 0.000000e+00, i32 3 %423 = extractelement <4 x float> %422, i32 0 %424 = extractelement <4 x float> %422, i32 1 %425 = insertelement <4 x float> undef, float %423, i32 0 %426 = insertelement <4 x float> %425, float %424, i32 1 %427 = insertelement <4 x float> %426, float undef, i32 2 %428 = insertelement <4 x float> %427, float undef, i32 3 %429 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %428, i32 16, i32 0, i32 2) %430 = extractelement <4 x float> %429, i32 1 %431 = extractelement <4 x float> %429, i32 2 %432 = extractelement <4 x float> %429, i32 3 %433 = fmul float %432, 0x406FFFFFE0000000 %434 = fptosi float %433 to i32 %435 = bitcast i32 %434 to float %436 = bitcast float %435 to i32 %437 = sdiv i32 %436, 16 %438 = bitcast i32 %437 to float %439 = bitcast float %435 to i32 %440 = sitofp i32 %439 to float %441 = fmul float %440, 6.250000e-02 %442 = call float @llvm.AMDIL.fraction.(float %441) %443 = fmul float 1.600000e+01, %442 %444 = fptosi float %443 to i32 %445 = bitcast i32 %444 to float %446 = bitcast float %438 to i32 %447 = sitofp i32 %446 to float %448 = bitcast float %445 to i32 %449 = sitofp i32 %448 to float %450 = fadd float %447, %430 %451 = fadd float %449, %431 %452 = fmul float %450, 6.250000e-02 %453 = fmul float %451, 6.250000e-02 %454 = bitcast float %24 to i32 %455 = sitofp i32 %454 to float %456 = bitcast float %25 to i32 %457 = sitofp i32 %456 to float %458 = fmul float %452, %455 %459 = fmul float %453, %457 %460 = bitcast float %temp52.0 to i32 %461 = bitcast float %temp48.0 to i32 %462 = bitcast float %145 to i32 %463 = sitofp i32 %462 to float %464 = fdiv float 1.000000e+00, %463 %465 = bitcast float %145 to i32 %466 = bitcast float %34 to i32 %467 = bitcast float %145 to i32 %468 = mul i32 %466, %467 %469 = bitcast float %35 to i32 %470 = bitcast float %147 to i32 %471 = mul i32 %469, %470 %472 = bitcast float %141 to i32 %473 = sitofp i32 %472 to float %474 = bitcast float %143 to i32 %475 = sitofp i32 %474 to float %476 = fdiv float 1.000000e+00, %473 %477 = fdiv float 1.000000e+00, %475 %478 = bitcast float %24 to i32 %479 = sitofp i32 %478 to float %480 = bitcast float %25 to i32 %481 = sitofp i32 %480 to float %482 = fsub float -0.000000e+00, %0 %483 = fsub float -0.000000e+00, %1 br label %LOOP.outer LOOP.outer: ; preds = %ENDIF926, %ELSE907 %temp620.0.ph = phi float [ 0.000000e+00, %ELSE907 ], [ %temp620.1, %ENDIF926 ] %temp621.0.ph = phi float [ 0.000000e+00, %ELSE907 ], [ %temp621.1, %ENDIF926 ] %temp624.0.ph = phi float [ 0.000000e+00, %ELSE907 ], [ %temp624.1, %ENDIF926 ] %temp625.0.ph = phi float [ 0.000000e+00, %ELSE907 ], [ %temp625.1, %ENDIF926 ] %temp628.0.ph = phi float [ 0.000000e+00, %ELSE907 ], [ %temp628.1, %ENDIF926 ] %temp52.2.ph = phi float [ 0x36A0000000000000, %ELSE907 ], [ %725, %ENDIF926 ] %temp49.0.ph = phi float [ %459, %ELSE907 ], [ %579, %ENDIF926 ] %temp48.1.ph = phi float [ %458, %ELSE907 ], [ %578, %ENDIF926 ] %temp44.3.ph = phi float [ 1.000000e+09, %ELSE907 ], [ %temp44.4, %ENDIF926 ] %temp40.1.ph = phi float [ %366, %ELSE907 ], [ %temp40.2, %ENDIF926 ] br label %LOOP LOOP: ; preds = %LOOP.outer, %IF921 %temp52.2 = phi float [ %588, %IF921 ], [ %temp52.2.ph, %LOOP.outer ] %temp49.0 = phi float [ %579, %IF921 ], [ %temp49.0.ph, %LOOP.outer ] %temp48.1 = phi float [ %578, %IF921 ], [ %temp48.1.ph, %LOOP.outer ] %484 = bitcast float %temp52.2 to i32 %485 = icmp sge i32 %484, 32 %486 = sext i1 %485 to i32 %487 = bitcast i32 %486 to float %488 = bitcast float %487 to i32 %489 = icmp ne i32 %488, 0 br i1 %489, label %ENDLOOP, label %ENDIF911 ENDLOOP: ; preds = %ENDIF911, %LOOP %490 = fcmp oeq float %temp40.1.ph, 0.000000e+00 %491 = sext i1 %490 to i32 %492 = bitcast i32 %491 to float %493 = bitcast float %492 to i32 %494 = icmp ne i32 %493, 0 br i1 %494, label %IF966, label %ENDIF965 ENDIF911: ; preds = %LOOP %495 = bitcast float %temp52.2 to i32 %496 = icmp sge i32 %495, %460 %497 = sext i1 %496 to i32 %498 = bitcast i32 %497 to float %499 = bitcast float %498 to i32 %500 = icmp ne i32 %499, 0 br i1 %500, label %ENDLOOP, label %ENDIF914 ENDIF914: ; preds = %ENDIF911 %501 = bitcast float %temp52.2 to i32 %502 = add i32 %461, %501 %503 = bitcast i32 %502 to float %504 = bitcast float %503 to i32 %505 = sitofp i32 %504 to float %506 = fmul float %505, %464 %507 = call float @llvm.AMDIL.fraction.(float %506) %508 = fmul float %463, %507 %509 = fptosi float %508 to i32 %510 = bitcast i32 %509 to float %511 = bitcast float %503 to i32 %512 = sdiv i32 %511, %465 %513 = bitcast i32 %512 to float %514 = bitcast float %510 to i32 %515 = add i32 %468, %514 %516 = bitcast float %513 to i32 %517 = add i32 %471, %516 %518 = bitcast i32 %515 to float %519 = bitcast i32 %517 to float %520 = bitcast float %518 to i32 %521 = sitofp i32 %520 to float %522 = bitcast float %519 to i32 %523 = sitofp i32 %522 to float %524 = fadd float %521, 5.000000e-01 %525 = fadd float %523, 5.000000e-01 %526 = fmul float %524, %476 %527 = fmul float %525, %477 %528 = insertelement <4 x float> undef, float %526, i32 0 %529 = insertelement <4 x float> %528, float %527, i32 1 %530 = insertelement <4 x float> %529, float 0.000000e+00, i32 2 %531 = insertelement <4 x float> %530, float 0.000000e+00, i32 3 %532 = extractelement <4 x float> %531, i32 0 %533 = extractelement <4 x float> %531, i32 1 %534 = insertelement <4 x float> undef, float %532, i32 0 %535 = insertelement <4 x float> %534, float %533, i32 1 %536 = insertelement <4 x float> %535, float undef, i32 2 %537 = insertelement <4 x float> %536, float undef, i32 3 %538 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %537, i32 16, i32 0, i32 2) %539 = extractelement <4 x float> %538, i32 0 %540 = extractelement <4 x float> %538, i32 1 %541 = extractelement <4 x float> %538, i32 2 %542 = extractelement <4 x float> %538, i32 3 %543 = fmul float %542, 0x406FFFFFE0000000 %544 = fptosi float %543 to i32 %545 = bitcast i32 %544 to float %546 = bitcast float %545 to i32 %547 = sdiv i32 %546, 16 %548 = bitcast i32 %547 to float %549 = bitcast float %545 to i32 %550 = sitofp i32 %549 to float %551 = fmul float %550, 6.250000e-02 %552 = call float @llvm.AMDIL.fraction.(float %551) %553 = fmul float 1.600000e+01, %552 %554 = fptosi float %553 to i32 %555 = bitcast i32 %554 to float %556 = bitcast float %548 to i32 %557 = sitofp i32 %556 to float %558 = bitcast float %555 to i32 %559 = sitofp i32 %558 to float %560 = fadd float %557, %540 %561 = fadd float %559, %541 %562 = fmul float %560, 6.250000e-02 %563 = fmul float %561, 6.250000e-02 %564 = fcmp oeq float %539, 0.000000e+00 %565 = sext i1 %564 to i32 %566 = bitcast i32 %565 to float %567 = bitcast float %566 to i32 %568 = icmp ne i32 %567, 0 br i1 %568, label %ENDIF917, label %ELSE919 ELSE919: ; preds = %ENDIF914 %569 = fmul float %539, 0x406FFFFFE0000000 %570 = fptosi float %569 to i32 %571 = bitcast i32 %570 to float %572 = bitcast float %571 to i32 %573 = add i32 %572, -128 %574 = bitcast i32 %573 to float %575 = bitcast float %574 to i32 %576 = sitofp i32 %575 to float %577 = fmul float 0x3F70204080000000, %576 br label %ENDIF917 ENDIF917: ; preds = %ENDIF914, %ELSE919 %temp192.0 = phi float [ %577, %ELSE919 ], [ 1.000000e+09, %ENDIF914 ] %578 = fmul float %562, %479 %579 = fmul float %563, %481 %580 = call float @fabs(float %temp192.0) %581 = fcmp oge float %580, 5.000000e+08 %582 = sext i1 %581 to i32 %583 = bitcast i32 %582 to float %584 = bitcast float %583 to i32 %585 = icmp ne i32 %584, 0 br i1 %585, label %IF921, label %ENDIF920 IF921: ; preds = %ENDIF917 %586 = bitcast float %temp52.2 to i32 %587 = add i32 %586, 1 %588 = bitcast i32 %587 to float br label %LOOP ENDIF920: ; preds = %ENDIF917 %589 = fmul float 2.000000e+00, %temp192.0 %590 = fmul float %temp192.0, %temp192.0 %591 = fsub float -0.000000e+00, %590 %592 = fadd float 1.000000e+00, %591 %593 = fdiv float 1.000000e+00, %592 %594 = fmul float %589, %593 %595 = fsub float -0.000000e+00, %594 %596 = fsub float -0.000000e+00, %temp48.1 %597 = fadd float %578, %596 %598 = fsub float -0.000000e+00, %temp49.0 %599 = fadd float %579, %598 %600 = insertelement <4 x float> undef, float %597, i32 0 %601 = insertelement <4 x float> %600, float %599, i32 1 %602 = insertelement <4 x float> %601, float 0.000000e+00, i32 2 %603 = insertelement <4 x float> %602, float 0.000000e+00, i32 3 %604 = insertelement <4 x float> , float %594, i32 1 %605 = insertelement <4 x float> %604, float 0.000000e+00, i32 2 %606 = insertelement <4 x float> %605, float 0.000000e+00, i32 3 %607 = call float @llvm.AMDGPU.dp4(<4 x float> %603, <4 x float> %606) %608 = insertelement <4 x float> undef, float %597, i32 0 %609 = insertelement <4 x float> %608, float %599, i32 1 %610 = insertelement <4 x float> %609, float 0.000000e+00, i32 2 %611 = insertelement <4 x float> %610, float 0.000000e+00, i32 3 %612 = insertelement <4 x float> undef, float %595, i32 0 %613 = insertelement <4 x float> %612, float 1.000000e+00, i32 1 %614 = insertelement <4 x float> %613, float 0.000000e+00, i32 2 %615 = insertelement <4 x float> %614, float 0.000000e+00, i32 3 %616 = call float @llvm.AMDGPU.dp4(<4 x float> %611, <4 x float> %615) %617 = fsub float -0.000000e+00, %temp48.1 %618 = fadd float %0, %617 %619 = fsub float -0.000000e+00, %temp49.0 %620 = fadd float %1, %619 %621 = insertelement <4 x float> undef, float %618, i32 0 %622 = insertelement <4 x float> %621, float %620, i32 1 %623 = insertelement <4 x float> %622, float 0.000000e+00, i32 2 %624 = insertelement <4 x float> %623, float 0.000000e+00, i32 3 %625 = insertelement <4 x float> undef, float %607, i32 0 %626 = insertelement <4 x float> %625, float %616, i32 1 %627 = insertelement <4 x float> %626, float 0.000000e+00, i32 2 %628 = insertelement <4 x float> %627, float 0.000000e+00, i32 3 %629 = call float @llvm.AMDGPU.dp4(<4 x float> %624, <4 x float> %628) %630 = fcmp oge float %629, 0.000000e+00 %631 = sext i1 %630 to i32 %632 = bitcast i32 %631 to float %633 = bitcast float %632 to i32 %634 = icmp ne i32 %633, 0 br i1 %634, label %IF924, label %ENDIF923 IF924: ; preds = %ENDIF920 %635 = insertelement <4 x float> undef, float %597, i32 0 %636 = insertelement <4 x float> %635, float %599, i32 1 %637 = insertelement <4 x float> %636, float 0.000000e+00, i32 2 %638 = insertelement <4 x float> %637, float 0.000000e+00, i32 3 %639 = insertelement <4 x float> , float %595, i32 1 %640 = insertelement <4 x float> %639, float 0.000000e+00, i32 2 %641 = insertelement <4 x float> %640, float 0.000000e+00, i32 3 %642 = call float @llvm.AMDGPU.dp4(<4 x float> %638, <4 x float> %641) %643 = insertelement <4 x float> undef, float %597, i32 0 %644 = insertelement <4 x float> %643, float %599, i32 1 %645 = insertelement <4 x float> %644, float 0.000000e+00, i32 2 %646 = insertelement <4 x float> %645, float 0.000000e+00, i32 3 %647 = insertelement <4 x float> undef, float %594, i32 0 %648 = insertelement <4 x float> %647, float 1.000000e+00, i32 1 %649 = insertelement <4 x float> %648, float 0.000000e+00, i32 2 %650 = insertelement <4 x float> %649, float 0.000000e+00, i32 3 %651 = call float @llvm.AMDGPU.dp4(<4 x float> %646, <4 x float> %650) %652 = fsub float -0.000000e+00, %578 %653 = fadd float %0, %652 %654 = fsub float -0.000000e+00, %579 %655 = fadd float %1, %654 %656 = insertelement <4 x float> undef, float %653, i32 0 %657 = insertelement <4 x float> %656, float %655, i32 1 %658 = insertelement <4 x float> %657, float 0.000000e+00, i32 2 %659 = insertelement <4 x float> %658, float 0.000000e+00, i32 3 %660 = insertelement <4 x float> undef, float %642, i32 0 %661 = insertelement <4 x float> %660, float %651, i32 1 %662 = insertelement <4 x float> %661, float 0.000000e+00, i32 2 %663 = insertelement <4 x float> %662, float 0.000000e+00, i32 3 %664 = call float @llvm.AMDGPU.dp4(<4 x float> %659, <4 x float> %663) %665 = fcmp oge float 0.000000e+00, %664 %666 = sext i1 %665 to i32 %667 = bitcast i32 %666 to float br label %ENDIF923 ENDIF923: ; preds = %ENDIF920, %IF924 %temp316.0 = phi float [ %667, %IF924 ], [ 0.000000e+00, %ENDIF920 ] %668 = bitcast float %temp316.0 to i32 %669 = icmp ne i32 %668, 0 br i1 %669, label %IF927, label %ELSE928 IF927: ; preds = %ENDIF923 %670 = call float @fabs(float %temp192.0) %671 = fcmp oge float 0x3FB99999A0000000, %670 %672 = sext i1 %671 to i32 %673 = bitcast i32 %672 to float %674 = bitcast float %673 to i32 %675 = icmp ne i32 %674, 0 %676 = fsub float -0.000000e+00, %temp48.1 %677 = fadd float %578, %676 %678 = fsub float -0.000000e+00, %temp49.0 %679 = fadd float %579, %678 br i1 %675, label %IF930, label %ELSE931 ELSE928: ; preds = %ENDIF923 %680 = fsub float -0.000000e+00, %temp48.1 %681 = fadd float %0, %680 %682 = fsub float -0.000000e+00, %temp49.0 %683 = fadd float %1, %682 %684 = fsub float -0.000000e+00, %578 %685 = fadd float %0, %684 %686 = fsub float -0.000000e+00, %579 %687 = fadd float %1, %686 %688 = insertelement <4 x float> undef, float %681, i32 0 %689 = insertelement <4 x float> %688, float %683, i32 1 %690 = insertelement <4 x float> %689, float 0.000000e+00, i32 2 %691 = insertelement <4 x float> %690, float 0.000000e+00, i32 3 %692 = insertelement <4 x float> undef, float %681, i32 0 %693 = insertelement <4 x float> %692, float %683, i32 1 %694 = insertelement <4 x float> %693, float 0.000000e+00, i32 2 %695 = insertelement <4 x float> %694, float 0.000000e+00, i32 3 %696 = call float @llvm.AMDGPU.dp4(<4 x float> %691, <4 x float> %695) %697 = call float @llvm.AMDGPU.rsq(float %696) %698 = fmul float %697, %696 %699 = fsub float -0.000000e+00, %696 %700 = fcmp ult float %699, 0.000000e+00 %701 = select i1 %700, float %698, float 0.000000e+00 %702 = insertelement <4 x float> undef, float %685, i32 0 %703 = insertelement <4 x float> %702, float %687, i32 1 %704 = insertelement <4 x float> %703, float 0.000000e+00, i32 2 %705 = insertelement <4 x float> %704, float 0.000000e+00, i32 3 %706 = insertelement <4 x float> undef, float %685, i32 0 %707 = insertelement <4 x float> %706, float %687, i32 1 %708 = insertelement <4 x float> %707, float 0.000000e+00, i32 2 %709 = insertelement <4 x float> %708, float 0.000000e+00, i32 3 %710 = call float @llvm.AMDGPU.dp4(<4 x float> %705, <4 x float> %709) %711 = call float @llvm.AMDGPU.rsq(float %710) %712 = fmul float %711, %710 %713 = fsub float -0.000000e+00, %710 %714 = fcmp ult float %713, 0.000000e+00 %715 = select i1 %714, float %712, float 0.000000e+00 %716 = fcmp uge float %701, %715 %717 = select i1 %716, float %715, float %701 %718 = fcmp olt float %717, %temp44.3.ph %719 = sext i1 %718 to i32 %720 = bitcast i32 %719 to float %721 = bitcast float %720 to i32 %722 = icmp ne i32 %721, 0 br i1 %722, label %ENDIF926, label %ELSE952 ENDIF926: ; preds = %ENDIF959, %ELSE952, %ELSE928, %IF945, %ENDIF929 %temp620.1 = phi float [ %temp620.0.ph, %ENDIF929 ], [ %temp620.0.ph, %IF945 ], [ %temp48.1, %ELSE928 ], [ %temp620.0.ph, %ELSE952 ], [ %temp620.0.ph, %ENDIF959 ] %temp621.1 = phi float [ %temp621.0.ph, %ENDIF929 ], [ %temp621.0.ph, %IF945 ], [ %temp49.0, %ELSE928 ], [ %temp621.0.ph, %ELSE952 ], [ %temp621.0.ph, %ENDIF959 ] %temp624.1 = phi float [ %temp624.0.ph, %ENDIF929 ], [ %temp624.0.ph, %IF945 ], [ %578, %ELSE928 ], [ %temp624.0.ph, %ELSE952 ], [ %temp624.0.ph, %ENDIF959 ] %temp625.1 = phi float [ %temp625.0.ph, %ENDIF929 ], [ %temp625.0.ph, %IF945 ], [ %579, %ELSE928 ], [ %temp625.0.ph, %ELSE952 ], [ %temp625.0.ph, %ENDIF959 ] %temp628.1 = phi float [ %temp628.0.ph, %ENDIF929 ], [ %temp628.0.ph, %IF945 ], [ %temp192.0, %ELSE928 ], [ %temp628.0.ph, %ELSE952 ], [ %temp628.0.ph, %ENDIF959 ] %temp44.4 = phi float [ %815, %IF945 ], [ %temp44.3.ph, %ENDIF929 ], [ %717, %ELSE928 ], [ %1233, %ENDIF959 ], [ %temp44.3.ph, %ELSE952 ] %temp40.2 = phi float [ %.1027, %IF945 ], [ %temp40.1.ph, %ENDIF929 ], [ 0.000000e+00, %ELSE928 ], [ %1237, %ENDIF959 ], [ %temp40.1.ph, %ELSE952 ] %723 = bitcast float %temp52.2 to i32 %724 = add i32 %723, 1 %725 = bitcast i32 %724 to float br label %LOOP.outer IF930: ; preds = %IF927 %726 = insertelement <4 x float> undef, float %677, i32 0 %727 = insertelement <4 x float> %726, float %679, i32 1 %728 = insertelement <4 x float> %727, float 0.000000e+00, i32 2 %729 = insertelement <4 x float> %728, float 0.000000e+00, i32 3 %730 = insertelement <4 x float> undef, float %677, i32 0 %731 = insertelement <4 x float> %730, float %679, i32 1 %732 = insertelement <4 x float> %731, float 0.000000e+00, i32 2 %733 = insertelement <4 x float> %732, float 0.000000e+00, i32 3 %734 = call float @llvm.AMDGPU.dp4(<4 x float> %729, <4 x float> %733) %735 = call float @llvm.AMDGPU.rsq(float %734) %736 = fmul float %677, %735 %737 = fmul float %679, %735 %738 = fsub float -0.000000e+00, %737 %739 = fsub float -0.000000e+00, %temp48.1 %740 = fadd float %0, %739 %741 = fsub float -0.000000e+00, %temp49.0 %742 = fadd float %1, %741 %743 = insertelement <4 x float> undef, float %740, i32 0 %744 = insertelement <4 x float> %743, float %742, i32 1 %745 = insertelement <4 x float> %744, float 0.000000e+00, i32 2 %746 = insertelement <4 x float> %745, float 0.000000e+00, i32 3 %747 = insertelement <4 x float> undef, float %738, i32 0 %748 = insertelement <4 x float> %747, float %736, i32 1 %749 = insertelement <4 x float> %748, float 0.000000e+00, i32 2 %750 = insertelement <4 x float> %749, float 0.000000e+00, i32 3 %751 = call float @llvm.AMDGPU.dp4(<4 x float> %746, <4 x float> %750) %752 = fcmp oeq float %temp192.0, 0.000000e+00 %753 = sext i1 %752 to i32 %754 = bitcast i32 %753 to float %755 = bitcast float %754 to i32 %756 = icmp ne i32 %755, 0 br i1 %756, label %ENDIF929, label %ELSE934 ELSE931: ; preds = %IF927 %757 = fsub float -0.000000e+00, %679 %758 = fmul float %temp192.0, %temp192.0 %759 = fsub float -0.000000e+00, %758 %760 = fadd float 1.000000e+00, %759 %761 = fdiv float 1.000000e+00, %760 %762 = fmul float 4.000000e+00, %761 %763 = fmul float %temp192.0, %762 %764 = fdiv float 1.000000e+00, %763 %765 = call float @llvm.AMDGPU.lrp(float 5.000000e-01, float %578, float %temp48.1) %766 = call float @llvm.AMDGPU.lrp(float 5.000000e-01, float %579, float %temp49.0) %767 = fmul float %757, %764 %768 = fadd float %767, %765 %769 = fmul float %677, %764 %770 = fadd float %769, %766 %771 = fsub float -0.000000e+00, %768 %772 = fadd float %temp48.1, %771 %773 = fsub float -0.000000e+00, %770 %774 = fadd float %temp49.0, %773 %775 = fsub float -0.000000e+00, %768 %776 = fadd float %0, %775 %777 = fsub float -0.000000e+00, %770 %778 = fadd float %1, %777 %779 = fcmp ugt float %temp192.0, 0.000000e+00 %780 = select i1 %779, float 1.000000e+00, float %temp192.0 %781 = fcmp uge float %780, 0.000000e+00 %782 = select i1 %781, float %780, float -1.000000e+00 %783 = insertelement <4 x float> undef, float %772, i32 0 %784 = insertelement <4 x float> %783, float %774, i32 1 %785 = insertelement <4 x float> %784, float 0.000000e+00, i32 2 %786 = insertelement <4 x float> %785, float 0.000000e+00, i32 3 %787 = insertelement <4 x float> undef, float %772, i32 0 %788 = insertelement <4 x float> %787, float %774, i32 1 %789 = insertelement <4 x float> %788, float 0.000000e+00, i32 2 %790 = insertelement <4 x float> %789, float 0.000000e+00, i32 3 %791 = call float @llvm.AMDGPU.dp4(<4 x float> %786, <4 x float> %790) %792 = call float @llvm.AMDGPU.rsq(float %791) %793 = fmul float %792, %791 %794 = fsub float -0.000000e+00, %791 %795 = fcmp ult float %794, 0.000000e+00 %796 = select i1 %795, float %793, float 0.000000e+00 %797 = insertelement <4 x float> undef, float %776, i32 0 %798 = insertelement <4 x float> %797, float %778, i32 1 %799 = insertelement <4 x float> %798, float 0.000000e+00, i32 2 %800 = insertelement <4 x float> %799, float 0.000000e+00, i32 3 %801 = insertelement <4 x float> undef, float %776, i32 0 %802 = insertelement <4 x float> %801, float %778, i32 1 %803 = insertelement <4 x float> %802, float 0.000000e+00, i32 2 %804 = insertelement <4 x float> %803, float 0.000000e+00, i32 3 %805 = call float @llvm.AMDGPU.dp4(<4 x float> %800, <4 x float> %804) %806 = call float @llvm.AMDGPU.rsq(float %805) %807 = fmul float %806, %805 %808 = fsub float -0.000000e+00, %805 %809 = fcmp ult float %808, 0.000000e+00 %810 = select i1 %809, float %807, float 0.000000e+00 %811 = fsub float -0.000000e+00, %810 %812 = fadd float %796, %811 %813 = fmul float %782, %812 br label %ENDIF929 ENDIF929: ; preds = %IF942, %ELSE943, %IF939, %IF936, %IF930, %ELSE931 %temp496.0 = phi float [ %813, %ELSE931 ], [ %751, %IF930 ], [ %861, %IF936 ], [ %900, %IF939 ], [ %959, %IF942 ], [ %960, %ELSE943 ] %814 = call float @fabs(float %temp496.0) %815 = fmul float %814, 0x3FEFFFEB00000000 %816 = fcmp oge float %temp44.3.ph, %815 %817 = sext i1 %816 to i32 %818 = bitcast i32 %817 to float %819 = bitcast float %818 to i32 %820 = icmp ne i32 %819, 0 br i1 %820, label %IF945, label %ENDIF926 ELSE934: ; preds = %IF930 %821 = fsub float -0.000000e+00, %temp48.1 %822 = fadd float %0, %821 %823 = fsub float -0.000000e+00, %temp49.0 %824 = fadd float %1, %823 %825 = insertelement <4 x float> undef, float %822, i32 0 %826 = insertelement <4 x float> %825, float %824, i32 1 %827 = insertelement <4 x float> %826, float 0.000000e+00, i32 2 %828 = insertelement <4 x float> %827, float 0.000000e+00, i32 3 %829 = insertelement <4 x float> undef, float %736, i32 0 %830 = insertelement <4 x float> %829, float %737, i32 1 %831 = insertelement <4 x float> %830, float 0.000000e+00, i32 2 %832 = insertelement <4 x float> %831, float 0.000000e+00, i32 3 %833 = call float @llvm.AMDGPU.dp4(<4 x float> %828, <4 x float> %832) %834 = fcmp olt float %833, 0.000000e+00 %835 = sext i1 %834 to i32 %836 = bitcast i32 %835 to float %837 = bitcast float %836 to i32 %838 = icmp ne i32 %837, 0 br i1 %838, label %IF936, label %ELSE937 IF936: ; preds = %ELSE934 %839 = fsub float -0.000000e+00, %temp48.1 %840 = fadd float %0, %839 %841 = fsub float -0.000000e+00, %temp49.0 %842 = fadd float %1, %841 %843 = fcmp ugt float %751, 0.000000e+00 %844 = select i1 %843, float 1.000000e+00, float %751 %845 = fcmp uge float %844, 0.000000e+00 %846 = select i1 %845, float %844, float -1.000000e+00 %847 = insertelement <4 x float> undef, float %840, i32 0 %848 = insertelement <4 x float> %847, float %842, i32 1 %849 = insertelement <4 x float> %848, float 0.000000e+00, i32 2 %850 = insertelement <4 x float> %849, float 0.000000e+00, i32 3 %851 = insertelement <4 x float> undef, float %840, i32 0 %852 = insertelement <4 x float> %851, float %842, i32 1 %853 = insertelement <4 x float> %852, float 0.000000e+00, i32 2 %854 = insertelement <4 x float> %853, float 0.000000e+00, i32 3 %855 = call float @llvm.AMDGPU.dp4(<4 x float> %850, <4 x float> %854) %856 = call float @llvm.AMDGPU.rsq(float %855) %857 = fmul float %856, %855 %858 = fsub float -0.000000e+00, %855 %859 = fcmp ult float %858, 0.000000e+00 %860 = select i1 %859, float %857, float 0.000000e+00 %861 = fmul float %846, %860 br label %ENDIF929 ELSE937: ; preds = %ELSE934 %862 = fadd float %578, %482 %863 = fadd float %579, %483 %864 = insertelement <4 x float> undef, float %862, i32 0 %865 = insertelement <4 x float> %864, float %863, i32 1 %866 = insertelement <4 x float> %865, float 0.000000e+00, i32 2 %867 = insertelement <4 x float> %866, float 0.000000e+00, i32 3 %868 = insertelement <4 x float> undef, float %736, i32 0 %869 = insertelement <4 x float> %868, float %737, i32 1 %870 = insertelement <4 x float> %869, float 0.000000e+00, i32 2 %871 = insertelement <4 x float> %870, float 0.000000e+00, i32 3 %872 = call float @llvm.AMDGPU.dp4(<4 x float> %867, <4 x float> %871) %873 = fcmp olt float %872, 0.000000e+00 %874 = sext i1 %873 to i32 %875 = bitcast i32 %874 to float %876 = bitcast float %875 to i32 %877 = icmp ne i32 %876, 0 br i1 %877, label %IF939, label %ELSE940 IF939: ; preds = %ELSE937 %878 = fsub float -0.000000e+00, %578 %879 = fadd float %0, %878 %880 = fsub float -0.000000e+00, %579 %881 = fadd float %1, %880 %882 = fcmp ugt float %751, 0.000000e+00 %883 = select i1 %882, float 1.000000e+00, float %751 %884 = fcmp uge float %883, 0.000000e+00 %885 = select i1 %884, float %883, float -1.000000e+00 %886 = insertelement <4 x float> undef, float %879, i32 0 %887 = insertelement <4 x float> %886, float %881, i32 1 %888 = insertelement <4 x float> %887, float 0.000000e+00, i32 2 %889 = insertelement <4 x float> %888, float 0.000000e+00, i32 3 %890 = insertelement <4 x float> undef, float %879, i32 0 %891 = insertelement <4 x float> %890, float %881, i32 1 %892 = insertelement <4 x float> %891, float 0.000000e+00, i32 2 %893 = insertelement <4 x float> %892, float 0.000000e+00, i32 3 %894 = call float @llvm.AMDGPU.dp4(<4 x float> %889, <4 x float> %893) %895 = call float @llvm.AMDGPU.rsq(float %894) %896 = fmul float %895, %894 %897 = fsub float -0.000000e+00, %894 %898 = fcmp ult float %897, 0.000000e+00 %899 = select i1 %898, float %896, float 0.000000e+00 %900 = fmul float %885, %899 br label %ENDIF929 ELSE940: ; preds = %ELSE937 %901 = fmul float 2.000000e+00, %temp192.0 %902 = fmul float %833, %872 %903 = fmul float %901, %902 %904 = fadd float %833, %872 %905 = fdiv float 1.000000e+00, %904 %906 = fmul float %903, %905 %907 = fmul float %906, %751 %908 = fcmp olt float 0.000000e+00, %907 %909 = sext i1 %908 to i32 %910 = bitcast i32 %909 to float %911 = bitcast float %910 to i32 %912 = icmp ne i32 %911, 0 br i1 %912, label %IF942, label %ELSE943 IF942: ; preds = %ELSE940 %913 = fsub float -0.000000e+00, %temp48.1 %914 = fadd float %0, %913 %915 = fsub float -0.000000e+00, %temp49.0 %916 = fadd float %1, %915 %917 = fsub float -0.000000e+00, %578 %918 = fadd float %0, %917 %919 = fsub float -0.000000e+00, %579 %920 = fadd float %1, %919 %921 = fcmp ugt float %751, 0.000000e+00 %922 = select i1 %921, float 1.000000e+00, float %751 %923 = fcmp uge float %922, 0.000000e+00 %924 = select i1 %923, float %922, float -1.000000e+00 %925 = fadd float %751, %906 %926 = call float @fabs(float %925) %927 = insertelement <4 x float> undef, float %914, i32 0 %928 = insertelement <4 x float> %927, float %916, i32 1 %929 = insertelement <4 x float> %928, float 0.000000e+00, i32 2 %930 = insertelement <4 x float> %929, float 0.000000e+00, i32 3 %931 = insertelement <4 x float> undef, float %914, i32 0 %932 = insertelement <4 x float> %931, float %916, i32 1 %933 = insertelement <4 x float> %932, float 0.000000e+00, i32 2 %934 = insertelement <4 x float> %933, float 0.000000e+00, i32 3 %935 = call float @llvm.AMDGPU.dp4(<4 x float> %930, <4 x float> %934) %936 = call float @llvm.AMDGPU.rsq(float %935) %937 = fmul float %936, %935 %938 = fsub float -0.000000e+00, %935 %939 = fcmp ult float %938, 0.000000e+00 %940 = select i1 %939, float %937, float 0.000000e+00 %941 = insertelement <4 x float> undef, float %918, i32 0 %942 = insertelement <4 x float> %941, float %920, i32 1 %943 = insertelement <4 x float> %942, float 0.000000e+00, i32 2 %944 = insertelement <4 x float> %943, float 0.000000e+00, i32 3 %945 = insertelement <4 x float> undef, float %918, i32 0 %946 = insertelement <4 x float> %945, float %920, i32 1 %947 = insertelement <4 x float> %946, float 0.000000e+00, i32 2 %948 = insertelement <4 x float> %947, float 0.000000e+00, i32 3 %949 = call float @llvm.AMDGPU.dp4(<4 x float> %944, <4 x float> %948) %950 = call float @llvm.AMDGPU.rsq(float %949) %951 = fmul float %950, %949 %952 = fsub float -0.000000e+00, %949 %953 = fcmp ult float %952, 0.000000e+00 %954 = select i1 %953, float %951, float 0.000000e+00 %955 = fcmp uge float %940, %954 %956 = select i1 %955, float %954, float %940 %957 = fcmp uge float %926, %956 %958 = select i1 %957, float %956, float %926 %959 = fmul float %924, %958 br label %ENDIF929 ELSE943: ; preds = %ELSE940 %960 = fadd float %751, %906 br label %ENDIF929 IF945: ; preds = %ENDIF929 %961 = fcmp oge float 0.000000e+00, %temp496.0 %962 = sext i1 %961 to i32 %963 = bitcast i32 %962 to float %964 = bitcast float %963 to i32 %965 = icmp ne i32 %964, 0 %.1027 = select i1 %965, float -1.000000e+00, float 1.000000e+00 br label %ENDIF926 ELSE952: ; preds = %ELSE928 %966 = fcmp oeq float %temp40.1.ph, 0.000000e+00 %967 = sext i1 %966 to i32 %968 = bitcast i32 %967 to float %969 = fcmp oeq float %717, %temp44.3.ph %970 = sext i1 %969 to i32 %971 = bitcast i32 %970 to float %972 = bitcast float %968 to i32 %973 = bitcast float %971 to i32 %974 = and i32 %972, %973 %975 = bitcast i32 %974 to float %976 = bitcast float %975 to i32 %977 = icmp ne i32 %976, 0 br i1 %977, label %IF954, label %ENDIF926 IF954: ; preds = %ELSE952 %978 = call float @llvm.AMDGPU.lrp(float 5.000000e-01, float %temp624.0.ph, float %temp620.0.ph) %979 = call float @llvm.AMDGPU.lrp(float 5.000000e-01, float %temp625.0.ph, float %temp621.0.ph) %980 = fmul float 2.000000e+00, %temp628.0.ph %981 = fmul float %temp628.0.ph, %temp628.0.ph %982 = fsub float -0.000000e+00, %981 %983 = fadd float 1.000000e+00, %982 %984 = fdiv float 1.000000e+00, %983 %985 = fmul float %980, %984 %986 = fsub float -0.000000e+00, %978 %987 = fadd float %0, %986 %988 = fsub float -0.000000e+00, %979 %989 = fadd float %1, %988 %990 = fsub float -0.000000e+00, %978 %991 = fadd float %temp624.0.ph, %990 %992 = fsub float -0.000000e+00, %979 %993 = fadd float %temp625.0.ph, %992 %994 = insertelement <4 x float> undef, float %987, i32 0 %995 = insertelement <4 x float> %994, float %989, i32 1 %996 = insertelement <4 x float> %995, float 0.000000e+00, i32 2 %997 = insertelement <4 x float> %996, float 0.000000e+00, i32 3 %998 = insertelement <4 x float> undef, float %991, i32 0 %999 = insertelement <4 x float> %998, float %993, i32 1 %1000 = insertelement <4 x float> %999, float 0.000000e+00, i32 2 %1001 = insertelement <4 x float> %1000, float 0.000000e+00, i32 3 %1002 = call float @llvm.AMDGPU.dp4(<4 x float> %997, <4 x float> %1001) %1003 = fcmp olt float %1002, 0.000000e+00 %1004 = sext i1 %1003 to i32 %1005 = bitcast i32 %1004 to float %1006 = bitcast float %1005 to i32 %1007 = icmp ne i32 %1006, 0 br i1 %1007, label %IF957, label %ELSE958 IF957: ; preds = %IF954 %1008 = fsub float -0.000000e+00, %temp620.0.ph %1009 = fadd float %temp624.0.ph, %1008 %1010 = fsub float -0.000000e+00, %temp621.0.ph %1011 = fadd float %temp625.0.ph, %1010 %1012 = insertelement <4 x float> undef, float %1009, i32 0 %1013 = insertelement <4 x float> %1012, float %1011, i32 1 %1014 = insertelement <4 x float> %1013, float 0.000000e+00, i32 2 %1015 = insertelement <4 x float> %1014, float 0.000000e+00, i32 3 %1016 = insertelement <4 x float> undef, float %985, i32 0 %1017 = insertelement <4 x float> %1016, float -1.000000e+00, i32 1 %1018 = insertelement <4 x float> %1017, float 0.000000e+00, i32 2 %1019 = insertelement <4 x float> %1018, float 0.000000e+00, i32 3 %1020 = call float @llvm.AMDGPU.dp4(<4 x float> %1015, <4 x float> %1019) %1021 = insertelement <4 x float> undef, float %1009, i32 0 %1022 = insertelement <4 x float> %1021, float %1011, i32 1 %1023 = insertelement <4 x float> %1022, float 0.000000e+00, i32 2 %1024 = insertelement <4 x float> %1023, float 0.000000e+00, i32 3 %1025 = insertelement <4 x float> , float %985, i32 1 %1026 = insertelement <4 x float> %1025, float 0.000000e+00, i32 2 %1027 = insertelement <4 x float> %1026, float 0.000000e+00, i32 3 %1028 = call float @llvm.AMDGPU.dp4(<4 x float> %1024, <4 x float> %1027) %1029 = fsub float -0.000000e+00, %temp620.0.ph %1030 = fadd float %0, %1029 %1031 = fsub float -0.000000e+00, %temp621.0.ph %1032 = fadd float %1, %1031 %1033 = insertelement <4 x float> undef, float %1020, i32 0 %1034 = insertelement <4 x float> %1033, float %1028, i32 1 %1035 = insertelement <4 x float> %1034, float 0.000000e+00, i32 2 %1036 = insertelement <4 x float> %1035, float 0.000000e+00, i32 3 %1037 = insertelement <4 x float> undef, float %1020, i32 0 %1038 = insertelement <4 x float> %1037, float %1028, i32 1 %1039 = insertelement <4 x float> %1038, float 0.000000e+00, i32 2 %1040 = insertelement <4 x float> %1039, float 0.000000e+00, i32 3 %1041 = call float @llvm.AMDGPU.dp4(<4 x float> %1036, <4 x float> %1040) %1042 = call float @llvm.AMDGPU.rsq(float %1041) %1043 = fmul float %1020, %1042 %1044 = fmul float %1028, %1042 %1045 = insertelement <4 x float> undef, float %1030, i32 0 %1046 = insertelement <4 x float> %1045, float %1032, i32 1 %1047 = insertelement <4 x float> %1046, float 0.000000e+00, i32 2 %1048 = insertelement <4 x float> %1047, float 0.000000e+00, i32 3 %1049 = insertelement <4 x float> undef, float %1043, i32 0 %1050 = insertelement <4 x float> %1049, float %1044, i32 1 %1051 = insertelement <4 x float> %1050, float 0.000000e+00, i32 2 %1052 = insertelement <4 x float> %1051, float 0.000000e+00, i32 3 %1053 = call float @llvm.AMDGPU.dp4(<4 x float> %1048, <4 x float> %1052) br label %ENDIF956 ELSE958: ; preds = %IF954 %1054 = fsub float -0.000000e+00, %985 %1055 = fsub float -0.000000e+00, %985 %1056 = fsub float -0.000000e+00, %temp620.0.ph %1057 = fadd float %temp624.0.ph, %1056 %1058 = fsub float -0.000000e+00, %temp621.0.ph %1059 = fadd float %temp625.0.ph, %1058 %1060 = insertelement <4 x float> undef, float %1057, i32 0 %1061 = insertelement <4 x float> %1060, float %1059, i32 1 %1062 = insertelement <4 x float> %1061, float 0.000000e+00, i32 2 %1063 = insertelement <4 x float> %1062, float 0.000000e+00, i32 3 %1064 = insertelement <4 x float> undef, float %1054, i32 0 %1065 = insertelement <4 x float> %1064, float -1.000000e+00, i32 1 %1066 = insertelement <4 x float> %1065, float 0.000000e+00, i32 2 %1067 = insertelement <4 x float> %1066, float 0.000000e+00, i32 3 %1068 = call float @llvm.AMDGPU.dp4(<4 x float> %1063, <4 x float> %1067) %1069 = insertelement <4 x float> undef, float %1057, i32 0 %1070 = insertelement <4 x float> %1069, float %1059, i32 1 %1071 = insertelement <4 x float> %1070, float 0.000000e+00, i32 2 %1072 = insertelement <4 x float> %1071, float 0.000000e+00, i32 3 %1073 = insertelement <4 x float> , float %1055, i32 1 %1074 = insertelement <4 x float> %1073, float 0.000000e+00, i32 2 %1075 = insertelement <4 x float> %1074, float 0.000000e+00, i32 3 %1076 = call float @llvm.AMDGPU.dp4(<4 x float> %1072, <4 x float> %1075) %1077 = fsub float -0.000000e+00, %temp624.0.ph %1078 = fadd float %0, %1077 %1079 = fsub float -0.000000e+00, %temp625.0.ph %1080 = fadd float %1, %1079 %1081 = insertelement <4 x float> undef, float %1068, i32 0 %1082 = insertelement <4 x float> %1081, float %1076, i32 1 %1083 = insertelement <4 x float> %1082, float 0.000000e+00, i32 2 %1084 = insertelement <4 x float> %1083, float 0.000000e+00, i32 3 %1085 = insertelement <4 x float> undef, float %1068, i32 0 %1086 = insertelement <4 x float> %1085, float %1076, i32 1 %1087 = insertelement <4 x float> %1086, float 0.000000e+00, i32 2 %1088 = insertelement <4 x float> %1087, float 0.000000e+00, i32 3 %1089 = call float @llvm.AMDGPU.dp4(<4 x float> %1084, <4 x float> %1088) %1090 = call float @llvm.AMDGPU.rsq(float %1089) %1091 = fmul float %1068, %1090 %1092 = fmul float %1076, %1090 %1093 = insertelement <4 x float> undef, float %1078, i32 0 %1094 = insertelement <4 x float> %1093, float %1080, i32 1 %1095 = insertelement <4 x float> %1094, float 0.000000e+00, i32 2 %1096 = insertelement <4 x float> %1095, float 0.000000e+00, i32 3 %1097 = insertelement <4 x float> undef, float %1091, i32 0 %1098 = insertelement <4 x float> %1097, float %1092, i32 1 %1099 = insertelement <4 x float> %1098, float 0.000000e+00, i32 2 %1100 = insertelement <4 x float> %1099, float 0.000000e+00, i32 3 %1101 = call float @llvm.AMDGPU.dp4(<4 x float> %1096, <4 x float> %1100) br label %ENDIF956 ENDIF956: ; preds = %ELSE958, %IF957 %temp720.0 = phi float [ %1053, %IF957 ], [ %1101, %ELSE958 ] %1102 = call float @llvm.AMDGPU.lrp(float 5.000000e-01, float %578, float %temp48.1) %1103 = call float @llvm.AMDGPU.lrp(float 5.000000e-01, float %579, float %temp49.0) %1104 = fmul float 2.000000e+00, %temp192.0 %1105 = fmul float %temp192.0, %temp192.0 %1106 = fsub float -0.000000e+00, %1105 %1107 = fadd float 1.000000e+00, %1106 %1108 = fdiv float 1.000000e+00, %1107 %1109 = fmul float %1104, %1108 %1110 = fsub float -0.000000e+00, %1102 %1111 = fadd float %0, %1110 %1112 = fsub float -0.000000e+00, %1103 %1113 = fadd float %1, %1112 %1114 = fsub float -0.000000e+00, %1102 %1115 = fadd float %578, %1114 %1116 = fsub float -0.000000e+00, %1103 %1117 = fadd float %579, %1116 %1118 = insertelement <4 x float> undef, float %1111, i32 0 %1119 = insertelement <4 x float> %1118, float %1113, i32 1 %1120 = insertelement <4 x float> %1119, float 0.000000e+00, i32 2 %1121 = insertelement <4 x float> %1120, float 0.000000e+00, i32 3 %1122 = insertelement <4 x float> undef, float %1115, i32 0 %1123 = insertelement <4 x float> %1122, float %1117, i32 1 %1124 = insertelement <4 x float> %1123, float 0.000000e+00, i32 2 %1125 = insertelement <4 x float> %1124, float 0.000000e+00, i32 3 %1126 = call float @llvm.AMDGPU.dp4(<4 x float> %1121, <4 x float> %1125) %1127 = fcmp olt float %1126, 0.000000e+00 %1128 = sext i1 %1127 to i32 %1129 = bitcast i32 %1128 to float %1130 = bitcast float %1129 to i32 %1131 = icmp ne i32 %1130, 0 br i1 %1131, label %IF960, label %ELSE961 IF960: ; preds = %ENDIF956 %1132 = fsub float -0.000000e+00, %temp48.1 %1133 = fadd float %578, %1132 %1134 = fsub float -0.000000e+00, %temp49.0 %1135 = fadd float %579, %1134 %1136 = insertelement <4 x float> undef, float %1133, i32 0 %1137 = insertelement <4 x float> %1136, float %1135, i32 1 %1138 = insertelement <4 x float> %1137, float 0.000000e+00, i32 2 %1139 = insertelement <4 x float> %1138, float 0.000000e+00, i32 3 %1140 = insertelement <4 x float> undef, float %1109, i32 0 %1141 = insertelement <4 x float> %1140, float -1.000000e+00, i32 1 %1142 = insertelement <4 x float> %1141, float 0.000000e+00, i32 2 %1143 = insertelement <4 x float> %1142, float 0.000000e+00, i32 3 %1144 = call float @llvm.AMDGPU.dp4(<4 x float> %1139, <4 x float> %1143) %1145 = insertelement <4 x float> undef, float %1133, i32 0 %1146 = insertelement <4 x float> %1145, float %1135, i32 1 %1147 = insertelement <4 x float> %1146, float 0.000000e+00, i32 2 %1148 = insertelement <4 x float> %1147, float 0.000000e+00, i32 3 %1149 = insertelement <4 x float> , float %1109, i32 1 %1150 = insertelement <4 x float> %1149, float 0.000000e+00, i32 2 %1151 = insertelement <4 x float> %1150, float 0.000000e+00, i32 3 %1152 = call float @llvm.AMDGPU.dp4(<4 x float> %1148, <4 x float> %1151) %1153 = fsub float -0.000000e+00, %temp48.1 %1154 = fadd float %0, %1153 %1155 = fsub float -0.000000e+00, %temp49.0 %1156 = fadd float %1, %1155 %1157 = insertelement <4 x float> undef, float %1144, i32 0 %1158 = insertelement <4 x float> %1157, float %1152, i32 1 %1159 = insertelement <4 x float> %1158, float 0.000000e+00, i32 2 %1160 = insertelement <4 x float> %1159, float 0.000000e+00, i32 3 %1161 = insertelement <4 x float> undef, float %1144, i32 0 %1162 = insertelement <4 x float> %1161, float %1152, i32 1 %1163 = insertelement <4 x float> %1162, float 0.000000e+00, i32 2 %1164 = insertelement <4 x float> %1163, float 0.000000e+00, i32 3 %1165 = call float @llvm.AMDGPU.dp4(<4 x float> %1160, <4 x float> %1164) %1166 = call float @llvm.AMDGPU.rsq(float %1165) %1167 = fmul float %1144, %1166 %1168 = fmul float %1152, %1166 %1169 = insertelement <4 x float> undef, float %1154, i32 0 %1170 = insertelement <4 x float> %1169, float %1156, i32 1 %1171 = insertelement <4 x float> %1170, float 0.000000e+00, i32 2 %1172 = insertelement <4 x float> %1171, float 0.000000e+00, i32 3 %1173 = insertelement <4 x float> undef, float %1167, i32 0 %1174 = insertelement <4 x float> %1173, float %1168, i32 1 %1175 = insertelement <4 x float> %1174, float 0.000000e+00, i32 2 %1176 = insertelement <4 x float> %1175, float 0.000000e+00, i32 3 %1177 = call float @llvm.AMDGPU.dp4(<4 x float> %1172, <4 x float> %1176) br label %ENDIF959 ELSE961: ; preds = %ENDIF956 %1178 = fsub float -0.000000e+00, %1109 %1179 = fsub float -0.000000e+00, %1109 %1180 = fsub float -0.000000e+00, %temp48.1 %1181 = fadd float %578, %1180 %1182 = fsub float -0.000000e+00, %temp49.0 %1183 = fadd float %579, %1182 %1184 = insertelement <4 x float> undef, float %1181, i32 0 %1185 = insertelement <4 x float> %1184, float %1183, i32 1 %1186 = insertelement <4 x float> %1185, float 0.000000e+00, i32 2 %1187 = insertelement <4 x float> %1186, float 0.000000e+00, i32 3 %1188 = insertelement <4 x float> undef, float %1178, i32 0 %1189 = insertelement <4 x float> %1188, float -1.000000e+00, i32 1 %1190 = insertelement <4 x float> %1189, float 0.000000e+00, i32 2 %1191 = insertelement <4 x float> %1190, float 0.000000e+00, i32 3 %1192 = call float @llvm.AMDGPU.dp4(<4 x float> %1187, <4 x float> %1191) %1193 = insertelement <4 x float> undef, float %1181, i32 0 %1194 = insertelement <4 x float> %1193, float %1183, i32 1 %1195 = insertelement <4 x float> %1194, float 0.000000e+00, i32 2 %1196 = insertelement <4 x float> %1195, float 0.000000e+00, i32 3 %1197 = insertelement <4 x float> , float %1179, i32 1 %1198 = insertelement <4 x float> %1197, float 0.000000e+00, i32 2 %1199 = insertelement <4 x float> %1198, float 0.000000e+00, i32 3 %1200 = call float @llvm.AMDGPU.dp4(<4 x float> %1196, <4 x float> %1199) %1201 = fsub float -0.000000e+00, %578 %1202 = fadd float %0, %1201 %1203 = fsub float -0.000000e+00, %579 %1204 = fadd float %1, %1203 %1205 = insertelement <4 x float> undef, float %1192, i32 0 %1206 = insertelement <4 x float> %1205, float %1200, i32 1 %1207 = insertelement <4 x float> %1206, float 0.000000e+00, i32 2 %1208 = insertelement <4 x float> %1207, float 0.000000e+00, i32 3 %1209 = insertelement <4 x float> undef, float %1192, i32 0 %1210 = insertelement <4 x float> %1209, float %1200, i32 1 %1211 = insertelement <4 x float> %1210, float 0.000000e+00, i32 2 %1212 = insertelement <4 x float> %1211, float 0.000000e+00, i32 3 %1213 = call float @llvm.AMDGPU.dp4(<4 x float> %1208, <4 x float> %1212) %1214 = call float @llvm.AMDGPU.rsq(float %1213) %1215 = fmul float %1192, %1214 %1216 = fmul float %1200, %1214 %1217 = insertelement <4 x float> undef, float %1202, i32 0 %1218 = insertelement <4 x float> %1217, float %1204, i32 1 %1219 = insertelement <4 x float> %1218, float 0.000000e+00, i32 2 %1220 = insertelement <4 x float> %1219, float 0.000000e+00, i32 3 %1221 = insertelement <4 x float> undef, float %1215, i32 0 %1222 = insertelement <4 x float> %1221, float %1216, i32 1 %1223 = insertelement <4 x float> %1222, float 0.000000e+00, i32 2 %1224 = insertelement <4 x float> %1223, float 0.000000e+00, i32 3 %1225 = call float @llvm.AMDGPU.dp4(<4 x float> %1220, <4 x float> %1224) br label %ENDIF959 ENDIF959: ; preds = %ELSE961, %IF960 %temp836.0 = phi float [ %1177, %IF960 ], [ %1225, %ELSE961 ] %1226 = call float @fabs(float %temp836.0) %1227 = call float @fabs(float %temp720.0) %1228 = fcmp oge float %1227, %1226 %1229 = sext i1 %1228 to i32 %1230 = bitcast i32 %1229 to float %1231 = bitcast float %1230 to i32 %1232 = icmp ne i32 %1231, 0 %temp720.0.temp836.0 = select i1 %1232, float %temp720.0, float %temp836.0 %1233 = call float @fabs(float %temp720.0.temp836.0) %1234 = fcmp ugt float %temp720.0.temp836.0, 0.000000e+00 %1235 = select i1 %1234, float 1.000000e+00, float %temp720.0.temp836.0 %1236 = fcmp uge float %1235, 0.000000e+00 %1237 = select i1 %1236, float %1235, float -1.000000e+00 br label %ENDIF926 IF966: ; preds = %ENDLOOP %1238 = call float @llvm.AMDGPU.lrp(float 5.000000e-01, float %temp624.0.ph, float %temp620.0.ph) %1239 = call float @llvm.AMDGPU.lrp(float 5.000000e-01, float %temp625.0.ph, float %temp621.0.ph) %1240 = fmul float 2.000000e+00, %temp628.0.ph %1241 = fmul float %temp628.0.ph, %temp628.0.ph %1242 = fsub float -0.000000e+00, %1241 %1243 = fadd float 1.000000e+00, %1242 %1244 = fdiv float 1.000000e+00, %1243 %1245 = fmul float %1240, %1244 %1246 = fsub float -0.000000e+00, %1238 %1247 = fadd float %0, %1246 %1248 = fsub float -0.000000e+00, %1239 %1249 = fadd float %1, %1248 %1250 = fsub float -0.000000e+00, %1238 %1251 = fadd float %temp624.0.ph, %1250 %1252 = fsub float -0.000000e+00, %1239 %1253 = fadd float %temp625.0.ph, %1252 %1254 = insertelement <4 x float> undef, float %1247, i32 0 %1255 = insertelement <4 x float> %1254, float %1249, i32 1 %1256 = insertelement <4 x float> %1255, float 0.000000e+00, i32 2 %1257 = insertelement <4 x float> %1256, float 0.000000e+00, i32 3 %1258 = insertelement <4 x float> undef, float %1251, i32 0 %1259 = insertelement <4 x float> %1258, float %1253, i32 1 %1260 = insertelement <4 x float> %1259, float 0.000000e+00, i32 2 %1261 = insertelement <4 x float> %1260, float 0.000000e+00, i32 3 %1262 = call float @llvm.AMDGPU.dp4(<4 x float> %1257, <4 x float> %1261) %1263 = fcmp olt float %1262, 0.000000e+00 %1264 = sext i1 %1263 to i32 %1265 = bitcast i32 %1264 to float %1266 = bitcast float %1265 to i32 %1267 = icmp ne i32 %1266, 0 br i1 %1267, label %IF969, label %ELSE970 ENDIF965: ; preds = %ENDLOOP, %ENDIF968 %temp40.6 = phi float [ %1368, %ENDIF968 ], [ %temp40.1.ph, %ENDLOOP ] %1268 = fmul float %temp44.3.ph, %temp40.6 br label %ENDIF902 IF969: ; preds = %IF966 %1269 = fsub float -0.000000e+00, %temp620.0.ph %1270 = fadd float %temp624.0.ph, %1269 %1271 = fsub float -0.000000e+00, %temp621.0.ph %1272 = fadd float %temp625.0.ph, %1271 %1273 = insertelement <4 x float> undef, float %1270, i32 0 %1274 = insertelement <4 x float> %1273, float %1272, i32 1 %1275 = insertelement <4 x float> %1274, float 0.000000e+00, i32 2 %1276 = insertelement <4 x float> %1275, float 0.000000e+00, i32 3 %1277 = insertelement <4 x float> undef, float %1245, i32 0 %1278 = insertelement <4 x float> %1277, float -1.000000e+00, i32 1 %1279 = insertelement <4 x float> %1278, float 0.000000e+00, i32 2 %1280 = insertelement <4 x float> %1279, float 0.000000e+00, i32 3 %1281 = call float @llvm.AMDGPU.dp4(<4 x float> %1276, <4 x float> %1280) %1282 = insertelement <4 x float> undef, float %1270, i32 0 %1283 = insertelement <4 x float> %1282, float %1272, i32 1 %1284 = insertelement <4 x float> %1283, float 0.000000e+00, i32 2 %1285 = insertelement <4 x float> %1284, float 0.000000e+00, i32 3 %1286 = insertelement <4 x float> undef, float 1.000000e+00, i32 0 %1287 = insertelement <4 x float> %1286, float %1245, i32 1 %1288 = insertelement <4 x float> %1287, float 0.000000e+00, i32 2 %1289 = insertelement <4 x float> %1288, float 0.000000e+00, i32 3 %1290 = call float @llvm.AMDGPU.dp4(<4 x float> %1285, <4 x float> %1289) %1291 = fsub float -0.000000e+00, %temp620.0.ph %1292 = fadd float %0, %1291 %1293 = fsub float -0.000000e+00, %temp621.0.ph %1294 = fadd float %1, %1293 %1295 = insertelement <4 x float> undef, float %1281, i32 0 %1296 = insertelement <4 x float> %1295, float %1290, i32 1 %1297 = insertelement <4 x float> %1296, float 0.000000e+00, i32 2 %1298 = insertelement <4 x float> %1297, float 0.000000e+00, i32 3 %1299 = insertelement <4 x float> undef, float %1281, i32 0 %1300 = insertelement <4 x float> %1299, float %1290, i32 1 %1301 = insertelement <4 x float> %1300, float 0.000000e+00, i32 2 %1302 = insertelement <4 x float> %1301, float 0.000000e+00, i32 3 %1303 = call float @llvm.AMDGPU.dp4(<4 x float> %1298, <4 x float> %1302) %1304 = call float @llvm.AMDGPU.rsq(float %1303) %1305 = fmul float %1281, %1304 %1306 = fmul float %1290, %1304 %1307 = insertelement <4 x float> undef, float %1292, i32 0 %1308 = insertelement <4 x float> %1307, float %1294, i32 1 %1309 = insertelement <4 x float> %1308, float 0.000000e+00, i32 2 %1310 = insertelement <4 x float> %1309, float 0.000000e+00, i32 3 %1311 = insertelement <4 x float> undef, float %1305, i32 0 %1312 = insertelement <4 x float> %1311, float %1306, i32 1 %1313 = insertelement <4 x float> %1312, float 0.000000e+00, i32 2 %1314 = insertelement <4 x float> %1313, float 0.000000e+00, i32 3 %1315 = call float @llvm.AMDGPU.dp4(<4 x float> %1310, <4 x float> %1314) br label %ENDIF968 ELSE970: ; preds = %IF966 %1316 = fsub float -0.000000e+00, %1245 %1317 = fsub float -0.000000e+00, %1245 %1318 = fsub float -0.000000e+00, %temp620.0.ph %1319 = fadd float %temp624.0.ph, %1318 %1320 = fsub float -0.000000e+00, %temp621.0.ph %1321 = fadd float %temp625.0.ph, %1320 %1322 = insertelement <4 x float> undef, float %1319, i32 0 %1323 = insertelement <4 x float> %1322, float %1321, i32 1 %1324 = insertelement <4 x float> %1323, float 0.000000e+00, i32 2 %1325 = insertelement <4 x float> %1324, float 0.000000e+00, i32 3 %1326 = insertelement <4 x float> undef, float %1316, i32 0 %1327 = insertelement <4 x float> %1326, float -1.000000e+00, i32 1 %1328 = insertelement <4 x float> %1327, float 0.000000e+00, i32 2 %1329 = insertelement <4 x float> %1328, float 0.000000e+00, i32 3 %1330 = call float @llvm.AMDGPU.dp4(<4 x float> %1325, <4 x float> %1329) %1331 = insertelement <4 x float> undef, float %1319, i32 0 %1332 = insertelement <4 x float> %1331, float %1321, i32 1 %1333 = insertelement <4 x float> %1332, float 0.000000e+00, i32 2 %1334 = insertelement <4 x float> %1333, float 0.000000e+00, i32 3 %1335 = insertelement <4 x float> undef, float 1.000000e+00, i32 0 %1336 = insertelement <4 x float> %1335, float %1317, i32 1 %1337 = insertelement <4 x float> %1336, float 0.000000e+00, i32 2 %1338 = insertelement <4 x float> %1337, float 0.000000e+00, i32 3 %1339 = call float @llvm.AMDGPU.dp4(<4 x float> %1334, <4 x float> %1338) %1340 = fsub float -0.000000e+00, %temp624.0.ph %1341 = fadd float %0, %1340 %1342 = fsub float -0.000000e+00, %temp625.0.ph %1343 = fadd float %1, %1342 %1344 = insertelement <4 x float> undef, float %1330, i32 0 %1345 = insertelement <4 x float> %1344, float %1339, i32 1 %1346 = insertelement <4 x float> %1345, float 0.000000e+00, i32 2 %1347 = insertelement <4 x float> %1346, float 0.000000e+00, i32 3 %1348 = insertelement <4 x float> undef, float %1330, i32 0 %1349 = insertelement <4 x float> %1348, float %1339, i32 1 %1350 = insertelement <4 x float> %1349, float 0.000000e+00, i32 2 %1351 = insertelement <4 x float> %1350, float 0.000000e+00, i32 3 %1352 = call float @llvm.AMDGPU.dp4(<4 x float> %1347, <4 x float> %1351) %1353 = call float @llvm.AMDGPU.rsq(float %1352) %1354 = fmul float %1330, %1353 %1355 = fmul float %1339, %1353 %1356 = insertelement <4 x float> undef, float %1341, i32 0 %1357 = insertelement <4 x float> %1356, float %1343, i32 1 %1358 = insertelement <4 x float> %1357, float 0.000000e+00, i32 2 %1359 = insertelement <4 x float> %1358, float 0.000000e+00, i32 3 %1360 = insertelement <4 x float> undef, float %1354, i32 0 %1361 = insertelement <4 x float> %1360, float %1355, i32 1 %1362 = insertelement <4 x float> %1361, float 0.000000e+00, i32 2 %1363 = insertelement <4 x float> %1362, float 0.000000e+00, i32 3 %1364 = call float @llvm.AMDGPU.dp4(<4 x float> %1359, <4 x float> %1363) br label %ENDIF968 ENDIF968: ; preds = %ELSE970, %IF969 %temp24.0 = phi float [ %1315, %IF969 ], [ %1364, %ELSE970 ] %1365 = fcmp ugt float %temp24.0, 0.000000e+00 %1366 = select i1 %1365, float 1.000000e+00, float %temp24.0 %1367 = fcmp uge float %1366, 0.000000e+00 %1368 = select i1 %1367, float %1366, float -1.000000e+00 br label %ENDIF965 IF972: ; preds = %ENDIF902 %1369 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6) %1370 = extractelement <4 x float> %1369, i32 0 %1371 = fmul float %1370, 1.000000e+01 %1372 = fsub float -0.000000e+00, %1371 %1373 = fadd float %334, %1372 %1374 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5) %1375 = extractelement <4 x float> %1374, i32 0 %1376 = bitcast float %1375 to i32 %1377 = icmp ne i32 %1376, 0 br i1 %1377, label %IF975, label %ENDIF974 ELSE973: ; preds = %ENDIF902 %1378 = fadd float %334, -1.000000e+00 %1379 = fmul float %1378, -5.000000e-01 %1380 = call float @llvm.AMDIL.clamp.(float %1379, float 0.000000e+00, float 1.000000e+00) %1381 = fmul float 2.000000e+00, %1380 %1382 = fsub float -0.000000e+00, %1381 %1383 = fadd float 3.000000e+00, %1382 %1384 = fmul float %1380, %1383 %1385 = fmul float %1380, %1384 %1386 = fmul float 5.000000e-01, %1385 %1387 = fmul float 0.000000e+00, %1385 %1388 = fmul float 0.000000e+00, %1385 %1389 = fmul float 5.000000e-01, %1385 %1390 = call float @fabs(float %334) %1391 = fadd float %1390, -2.000000e+00 %1392 = fsub float -0.000000e+00, %1391 %1393 = call float @llvm.AMDIL.clamp.(float %1392, float 0.000000e+00, float 1.000000e+00) %1394 = fmul float 2.000000e+00, %1393 %1395 = fsub float -0.000000e+00, %1394 %1396 = fadd float 3.000000e+00, %1395 %1397 = fmul float %1393, %1396 %1398 = fmul float %1393, %1397 %1399 = fmul float 1.000000e+00, %1398 %1400 = fadd float %1399, %1386 %1401 = fmul float 0.000000e+00, %1398 %1402 = fadd float %1401, %1387 %1403 = fmul float 0.000000e+00, %1398 %1404 = fadd float %1403, %1388 %1405 = fmul float 1.000000e+00, %1398 %1406 = fadd float %1405, %1389 %1407 = call float @fabs(float %1390) %1408 = fcmp oge float %1407, 5.000000e+08 %1409 = sext i1 %1408 to i32 %1410 = bitcast i32 %1409 to float %1411 = bitcast float %1410 to i32 %1412 = xor i32 %1411, -1 %1413 = bitcast i32 %1412 to float %1414 = bitcast float %1413 to i32 %1415 = icmp ne i32 %1414, 0 br i1 %1415, label %IF993, label %ENDIF992 ENDIF971: ; preds = %IF990, %ENDIF980, %ENDIF1021 %temp19.0 = phi float [ %1969, %ENDIF1021 ], [ %1470, %IF990 ], [ %1447, %ENDIF980 ] %temp18.0 = phi float [ %1967, %ENDIF1021 ], [ 0.000000e+00, %ENDIF980 ], [ 0.000000e+00, %IF990 ] %temp17.0 = phi float [ %1965, %ENDIF1021 ], [ 0.000000e+00, %ENDIF980 ], [ 0.000000e+00, %IF990 ] %temp16.0 = phi float [ %1963, %ENDIF1021 ], [ 0.000000e+00, %ENDIF980 ], [ 0.000000e+00, %IF990 ] %1416 = insertelement <4 x float> undef, float %temp16.0, i32 0 %1417 = insertelement <4 x float> %1416, float %temp17.0, i32 1 %1418 = insertelement <4 x float> %1417, float %temp18.0, i32 2 %1419 = insertelement <4 x float> %1418, float %temp19.0, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %1419, i32 0, i32 0) ret void IF975: ; preds = %IF972 %1420 = call float @fabs(float %1373) %1421 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) %1422 = extractelement <4 x float> %1421, i32 0 %1423 = fmul float %1422, 5.000000e-01 %1424 = fsub float -0.000000e+00, %1423 %1425 = fadd float %1420, %1424 br label %ENDIF974 ENDIF974: ; preds = %IF972, %IF975 %temp24.1 = phi float [ %1425, %IF975 ], [ %1373, %IF972 ] %1426 = fcmp olt float 1.000000e+00, %temp24.1 %1427 = sext i1 %1426 to i32 %1428 = bitcast i32 %1427 to float %1429 = bitcast float %1428 to i32 %1430 = icmp ne i32 %1429, 0 br i1 %1430, label %IF978, label %ENDIF977 IF978: ; preds = %ENDIF974 call void @llvm.AMDGPU.kilp() br label %ENDIF977 ENDIF977: ; preds = %ENDIF974, %IF978 %1431 = fsub float -0.000000e+00, %temp24.1 %1432 = fadd float %1431, 5.000000e-01 %1433 = call float @llvm.AMDIL.clamp.(float %1432, float 0.000000e+00, float 1.000000e+00) %1434 = fcmp oge float 0xBFE6A09E60000000, %1431 %1435 = sext i1 %1434 to i32 %1436 = bitcast i32 %1435 to float %1437 = bitcast float %1436 to i32 %1438 = icmp ne i32 %1437, 0 br i1 %1438, label %ENDIF980, label %ELSE982 ELSE982: ; preds = %ENDIF977 %1439 = fcmp oge float %1431, 0x3FE6A09E60000000 %1440 = sext i1 %1439 to i32 %1441 = bitcast i32 %1440 to float %1442 = bitcast float %1441 to i32 %1443 = icmp ne i32 %1442, 0 br i1 %1443, label %ENDIF980, label %ELSE985 ENDIF980: ; preds = %IF987, %ELSE988, %ELSE982, %ENDIF977 %temp32.0 = phi float [ 0.000000e+00, %ENDIF977 ], [ 1.000000e+00, %ELSE982 ], [ %1461, %IF987 ], [ %1466, %ELSE988 ] %1444 = fadd float %139, -1.000000e+00 %1445 = fmul float %1444, 0x4003504F40000000 %1446 = call float @llvm.AMDIL.clamp.(float %1445, float 0.000000e+00, float 1.000000e+00) %1447 = call float @llvm.AMDGPU.lrp(float %1446, float %temp32.0, float %1433) %1448 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %1449 = extractelement <4 x float> %1448, i32 0 %1450 = fcmp une float %1449, 1.000000e+00 %1451 = sext i1 %1450 to i32 %1452 = bitcast i32 %1451 to float %1453 = bitcast float %1452 to i32 %1454 = icmp ne i32 %1453, 0 br i1 %1454, label %IF990, label %ENDIF971 ELSE985: ; preds = %ELSE982 %1455 = fcmp oge float 0.000000e+00, %1431 %1456 = sext i1 %1455 to i32 %1457 = bitcast i32 %1456 to float %1458 = bitcast float %1457 to i32 %1459 = icmp ne i32 %1458, 0 br i1 %1459, label %IF987, label %ELSE988 IF987: ; preds = %ELSE985 %1460 = fadd float %1431, 0x3FE6A09E60000000 %1461 = call float @llvm.pow.f32(float %1460, float 2.000000e+00) br label %ENDIF980 ELSE988: ; preds = %ELSE985 %1462 = fsub float -0.000000e+00, %1431 %1463 = fadd float 0x3FE6A09E60000000, %1462 %1464 = call float @llvm.pow.f32(float %1463, float 2.000000e+00) %1465 = fsub float -0.000000e+00, %1464 %1466 = fadd float 1.000000e+00, %1465 br label %ENDIF980 IF990: ; preds = %ENDIF980 %1467 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %1468 = extractelement <4 x float> %1467, i32 0 %1469 = fdiv float 1.000000e+00, %1468 %1470 = call float @llvm.pow.f32(float %1447, float %1469) br label %ENDIF971 IF993: ; preds = %ELSE973 %1471 = call float @fabs(float %temp68.0) %1472 = bitcast float %24 to i32 %1473 = sitofp i32 %1472 to float %1474 = bitcast float %25 to i32 %1475 = sitofp i32 %1474 to float %1476 = fcmp uge float %1473, %1475 %1477 = select i1 %1476, float %1473, float %1475 %1478 = fdiv float 1.000000e+00, %1477 %1479 = fmul float %1471, %1478 %1480 = fmul float %1479, 4.000000e+00 %1481 = fsub float -0.000000e+00, %1480 %1482 = fadd float 0x3FD99999A0000000, %1481 %1483 = fadd float %1400, 0.000000e+00 %1484 = fadd float %1402, 0x3FD99999A0000000 %1485 = fadd float %1404, 0.000000e+00 %1486 = fadd float %1406, %1482 br label %ENDIF992 ENDIF992: ; preds = %ELSE973, %IF993 %temp19.1 = phi float [ %1486, %IF993 ], [ %1406, %ELSE973 ] %temp18.1 = phi float [ %1485, %IF993 ], [ %1404, %ELSE973 ] %temp17.1 = phi float [ %1484, %IF993 ], [ %1402, %ELSE973 ] %temp16.1 = phi float [ %1483, %IF993 ], [ %1400, %ELSE973 ] %1487 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %1488 = extractelement <4 x float> %1487, i32 0 %1489 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %1490 = extractelement <4 x float> %1489, i32 1 %1491 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %1492 = extractelement <4 x float> %1491, i32 2 %1493 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %1494 = extractelement <4 x float> %1493, i32 3 %1495 = call float @floor(float %0) %1496 = call float @floor(float %1) %1497 = fcmp uge float %1495, 0.000000e+00 %1498 = select i1 %1497, float %1495, float 0.000000e+00 %1499 = fcmp uge float %1496, 0.000000e+00 %1500 = select i1 %1499, float %1496, float 0.000000e+00 %1501 = bitcast float %24 to i32 %1502 = add i32 %1501, -1 %1503 = bitcast float %25 to i32 %1504 = add i32 %1503, -1 %1505 = bitcast i32 %1502 to float %1506 = bitcast i32 %1504 to float %1507 = bitcast float %1505 to i32 %1508 = sitofp i32 %1507 to float %1509 = bitcast float %1506 to i32 %1510 = sitofp i32 %1509 to float %1511 = fcmp uge float %1498, %1508 %1512 = select i1 %1511, float %1508, float %1498 %1513 = fcmp uge float %1500, %1510 %1514 = select i1 %1513, float %1510, float %1500 %1515 = fptosi float %1512 to i32 %1516 = fptosi float %1514 to i32 %1517 = bitcast i32 %1515 to float %1518 = bitcast i32 %1516 to float %1519 = bitcast float %1518 to i32 %1520 = bitcast float %24 to i32 %1521 = bitcast float %1517 to i32 %1522 = mul i32 %1519, %1520 %1523 = add i32 %1522, %1521 %1524 = bitcast i32 %1523 to float %1525 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %1526 = extractelement <4 x float> %1525, i32 2 %1527 = bitcast float %1526 to i32 %1528 = sitofp i32 %1527 to float %1529 = bitcast float %1524 to i32 %1530 = sitofp i32 %1529 to float %1531 = fdiv float 1.000000e+00, %1528 %1532 = fmul float %1530, %1531 %1533 = call float @llvm.AMDIL.fraction.(float %1532) %1534 = fmul float %1528, %1533 %1535 = fptosi float %1534 to i32 %1536 = bitcast i32 %1535 to float %1537 = bitcast float %1524 to i32 %1538 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %1539 = extractelement <4 x float> %1538, i32 2 %1540 = bitcast float %1539 to i32 %1541 = sdiv i32 %1537, %1540 %1542 = bitcast i32 %1541 to float %1543 = bitcast float %34 to i32 %1544 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %1545 = extractelement <4 x float> %1544, i32 2 %1546 = bitcast float %1545 to i32 %1547 = bitcast float %1536 to i32 %1548 = mul i32 %1543, %1546 %1549 = add i32 %1548, %1547 %1550 = bitcast float %35 to i32 %1551 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %1552 = extractelement <4 x float> %1551, i32 3 %1553 = bitcast float %1552 to i32 %1554 = bitcast float %1542 to i32 %1555 = mul i32 %1550, %1553 %1556 = add i32 %1555, %1554 %1557 = bitcast i32 %1549 to float %1558 = bitcast i32 %1556 to float %1559 = bitcast float %1557 to i32 %1560 = sitofp i32 %1559 to float %1561 = bitcast float %1558 to i32 %1562 = sitofp i32 %1561 to float %1563 = fadd float %1560, 5.000000e-01 %1564 = fadd float %1562, 5.000000e-01 %1565 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %1566 = extractelement <4 x float> %1565, i32 0 %1567 = bitcast float %1566 to i32 %1568 = sitofp i32 %1567 to float %1569 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %1570 = extractelement <4 x float> %1569, i32 1 %1571 = bitcast float %1570 to i32 %1572 = sitofp i32 %1571 to float %1573 = fdiv float 1.000000e+00, %1568 %1574 = fdiv float 1.000000e+00, %1572 %1575 = fmul float %1563, %1573 %1576 = fmul float %1564, %1574 %1577 = insertelement <4 x float> undef, float %1575, i32 0 %1578 = insertelement <4 x float> %1577, float %1576, i32 1 %1579 = insertelement <4 x float> %1578, float 0.000000e+00, i32 2 %1580 = insertelement <4 x float> %1579, float 0.000000e+00, i32 3 %1581 = extractelement <4 x float> %1580, i32 0 %1582 = extractelement <4 x float> %1580, i32 1 %1583 = insertelement <4 x float> undef, float %1581, i32 0 %1584 = insertelement <4 x float> %1583, float %1582, i32 1 %1585 = insertelement <4 x float> %1584, float undef, i32 2 %1586 = insertelement <4 x float> %1585, float undef, i32 3 %1587 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %1586, i32 16, i32 0, i32 2) %1588 = extractelement <4 x float> %1587, i32 0 %1589 = extractelement <4 x float> %1587, i32 1 %1590 = extractelement <4 x float> %1587, i32 2 %1591 = extractelement <4 x float> %1587, i32 3 %1592 = fmul float %1588, 0x406FFFFFE0000000 %1593 = fmul float %1589, 0x406FFFFFE0000000 %1594 = fmul float %1590, 0x406FFFFFE0000000 %1595 = fmul float %1591, 0x406FFFFFE0000000 %1596 = fptosi float %1592 to i32 %1597 = fptosi float %1593 to i32 %1598 = fptosi float %1594 to i32 %1599 = fptosi float %1595 to i32 %1600 = bitcast i32 %1596 to float %1601 = bitcast i32 %1597 to float %1602 = bitcast i32 %1598 to float %1603 = bitcast i32 %1599 to float %1604 = bitcast float %1600 to i32 %1605 = icmp eq i32 %1604, 0 %1606 = sext i1 %1605 to i32 %1607 = bitcast i32 %1606 to float %1608 = bitcast float %1607 to i32 %1609 = icmp ne i32 %1608, 0 br i1 %1609, label %IF996, label %ENDIF995 IF996: ; preds = %ENDIF992 %1610 = bitcast float %1601 to i32 %1611 = bitcast float %1602 to i32 %1612 = mul i32 %1610, 256 %1613 = add i32 %1612, %1611 %1614 = bitcast i32 %1613 to float %1615 = bitcast float %1603 to i32 %1616 = icmp eq i32 %1615, 255 %1617 = sext i1 %1616 to i32 %1618 = bitcast i32 %1617 to float %1619 = bitcast float %1618 to i32 %1620 = icmp ne i32 %1619, 0 %.1028 = select i1 %1620, float 0.000000e+00, float %1603 br label %ENDIF995 ENDIF995: ; preds = %ENDIF992, %IF996 %temp36.0 = phi float [ %.1028, %IF996 ], [ 0xFFFFFFFFE0000000, %ENDIF992 ] %temp32.3 = phi float [ %1614, %IF996 ], [ %1607, %ENDIF992 ] %1621 = bitcast float %temp36.0 to i32 %1622 = icmp eq i32 %1621, 0 %1623 = sext i1 %1622 to i32 %1624 = bitcast i32 %1623 to float %1625 = bitcast float %1624 to i32 %1626 = icmp ne i32 %1625, 0 br i1 %1626, label %ENDIF1001, label %ELSE1003 ELSE1003: ; preds = %ENDIF995 %1627 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %1628 = extractelement <4 x float> %1627, i32 2 %1629 = bitcast float %1628 to i32 %1630 = sitofp i32 %1629 to float %1631 = bitcast float %temp32.3 to i32 %1632 = sitofp i32 %1631 to float %1633 = fdiv float 1.000000e+00, %1630 %1634 = fmul float %1632, %1633 %1635 = call float @llvm.AMDIL.fraction.(float %1634) %1636 = fmul float %1630, %1635 %1637 = fptosi float %1636 to i32 %1638 = bitcast i32 %1637 to float %1639 = bitcast float %temp32.3 to i32 %1640 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %1641 = extractelement <4 x float> %1640, i32 2 %1642 = bitcast float %1641 to i32 %1643 = sdiv i32 %1639, %1642 %1644 = bitcast i32 %1643 to float %1645 = bitcast float %34 to i32 %1646 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %1647 = extractelement <4 x float> %1646, i32 2 %1648 = bitcast float %1647 to i32 %1649 = bitcast float %1638 to i32 %1650 = mul i32 %1645, %1648 %1651 = add i32 %1650, %1649 %1652 = bitcast float %35 to i32 %1653 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %1654 = extractelement <4 x float> %1653, i32 3 %1655 = bitcast float %1654 to i32 %1656 = bitcast float %1644 to i32 %1657 = mul i32 %1652, %1655 %1658 = add i32 %1657, %1656 %1659 = bitcast i32 %1651 to float %1660 = bitcast i32 %1658 to float %1661 = bitcast float %1659 to i32 %1662 = sitofp i32 %1661 to float %1663 = bitcast float %1660 to i32 %1664 = sitofp i32 %1663 to float %1665 = fadd float %1662, 5.000000e-01 %1666 = fadd float %1664, 5.000000e-01 %1667 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %1668 = extractelement <4 x float> %1667, i32 0 %1669 = bitcast float %1668 to i32 %1670 = sitofp i32 %1669 to float %1671 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %1672 = extractelement <4 x float> %1671, i32 1 %1673 = bitcast float %1672 to i32 %1674 = sitofp i32 %1673 to float %1675 = fdiv float 1.000000e+00, %1670 %1676 = fdiv float 1.000000e+00, %1674 %1677 = fmul float %1665, %1675 %1678 = fmul float %1666, %1676 %1679 = insertelement <4 x float> undef, float %1677, i32 0 %1680 = insertelement <4 x float> %1679, float %1678, i32 1 %1681 = insertelement <4 x float> %1680, float %145, i32 2 %1682 = insertelement <4 x float> %1681, float %147, i32 3 %1683 = extractelement <4 x float> %1682, i32 0 %1684 = extractelement <4 x float> %1682, i32 1 %1685 = insertelement <4 x float> undef, float %1683, i32 0 %1686 = insertelement <4 x float> %1685, float %1684, i32 1 %1687 = insertelement <4 x float> %1686, float undef, i32 2 %1688 = insertelement <4 x float> %1687, float undef, i32 3 %1689 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %1688, i32 16, i32 0, i32 2) %1690 = bitcast float %temp36.0 to i32 %1691 = bitcast float %temp32.3 to i32 %1692 = bitcast float %1492 to i32 %1693 = sitofp i32 %1692 to float %1694 = fdiv float 1.000000e+00, %1693 %1695 = bitcast float %1492 to i32 %1696 = bitcast float %34 to i32 %1697 = bitcast float %1492 to i32 %1698 = mul i32 %1696, %1697 %1699 = bitcast float %35 to i32 %1700 = bitcast float %1494 to i32 %1701 = mul i32 %1699, %1700 %1702 = bitcast float %1488 to i32 %1703 = sitofp i32 %1702 to float %1704 = bitcast float %1490 to i32 %1705 = sitofp i32 %1704 to float %1706 = fdiv float 1.000000e+00, %1703 %1707 = fdiv float 1.000000e+00, %1705 %1708 = bitcast float %24 to i32 %1709 = sitofp i32 %1708 to float %1710 = bitcast float %25 to i32 %1711 = sitofp i32 %1710 to float br label %LOOP1008.outer ENDIF1001: ; preds = %ENDIF1009, %LOOP1008, %ENDIF995 %temp36.2 = phi float [ 1.000000e+09, %ENDIF995 ], [ %temp44.8.ph, %LOOP1008 ], [ %temp44.8.ph, %ENDIF1009 ] %1712 = fadd float %temp36.2, 0xBFA99999A0000000 %1713 = fmul float %1712, 0x4059000060000000 %1714 = call float @llvm.AMDIL.clamp.(float %1713, float 0.000000e+00, float 1.000000e+00) %1715 = fmul float 2.000000e+00, %1714 %1716 = fsub float -0.000000e+00, %1715 %1717 = fadd float 3.000000e+00, %1716 %1718 = fmul float %1714, %1717 %1719 = fmul float %1714, %1718 %1720 = call float @llvm.AMDGPU.lrp(float %1719, float %temp16.1, float 0.000000e+00) %1721 = call float @llvm.AMDGPU.lrp(float %1719, float %temp17.1, float 1.000000e+00) %1722 = call float @llvm.AMDGPU.lrp(float %1719, float %temp18.1, float 0.000000e+00) %1723 = call float @llvm.AMDGPU.lrp(float %1719, float %temp19.1, float 5.000000e-01) %1724 = call float @floor(float %0) %1725 = call float @floor(float %1) %1726 = fcmp uge float %1724, 0.000000e+00 %1727 = select i1 %1726, float %1724, float 0.000000e+00 %1728 = fcmp uge float %1725, 0.000000e+00 %1729 = select i1 %1728, float %1725, float 0.000000e+00 %1730 = bitcast float %24 to i32 %1731 = add i32 %1730, -1 %1732 = bitcast float %25 to i32 %1733 = add i32 %1732, -1 %1734 = bitcast i32 %1731 to float %1735 = bitcast i32 %1733 to float %1736 = bitcast float %1734 to i32 %1737 = sitofp i32 %1736 to float %1738 = bitcast float %1735 to i32 %1739 = sitofp i32 %1738 to float %1740 = fcmp uge float %1727, %1737 %1741 = select i1 %1740, float %1737, float %1727 %1742 = fcmp uge float %1729, %1739 %1743 = select i1 %1742, float %1739, float %1729 %1744 = fptosi float %1741 to i32 %1745 = fptosi float %1743 to i32 %1746 = bitcast i32 %1744 to float %1747 = bitcast i32 %1745 to float %1748 = bitcast float %1747 to i32 %1749 = bitcast float %24 to i32 %1750 = bitcast float %1746 to i32 %1751 = mul i32 %1748, %1749 %1752 = add i32 %1751, %1750 %1753 = bitcast i32 %1752 to float %1754 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %1755 = extractelement <4 x float> %1754, i32 2 %1756 = bitcast float %1755 to i32 %1757 = sitofp i32 %1756 to float %1758 = bitcast float %1753 to i32 %1759 = sitofp i32 %1758 to float %1760 = fdiv float 1.000000e+00, %1757 %1761 = fmul float %1759, %1760 %1762 = call float @llvm.AMDIL.fraction.(float %1761) %1763 = fmul float %1757, %1762 %1764 = fptosi float %1763 to i32 %1765 = bitcast i32 %1764 to float %1766 = bitcast float %1753 to i32 %1767 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %1768 = extractelement <4 x float> %1767, i32 2 %1769 = bitcast float %1768 to i32 %1770 = sdiv i32 %1766, %1769 %1771 = bitcast i32 %1770 to float %1772 = bitcast float %34 to i32 %1773 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %1774 = extractelement <4 x float> %1773, i32 2 %1775 = bitcast float %1774 to i32 %1776 = bitcast float %1765 to i32 %1777 = mul i32 %1772, %1775 %1778 = add i32 %1777, %1776 %1779 = bitcast float %35 to i32 %1780 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %1781 = extractelement <4 x float> %1780, i32 3 %1782 = bitcast float %1781 to i32 %1783 = bitcast float %1771 to i32 %1784 = mul i32 %1779, %1782 %1785 = add i32 %1784, %1783 %1786 = bitcast i32 %1778 to float %1787 = bitcast i32 %1785 to float %1788 = bitcast float %1786 to i32 %1789 = sitofp i32 %1788 to float %1790 = bitcast float %1787 to i32 %1791 = sitofp i32 %1790 to float %1792 = fadd float %1789, 5.000000e-01 %1793 = fadd float %1791, 5.000000e-01 %1794 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %1795 = extractelement <4 x float> %1794, i32 0 %1796 = bitcast float %1795 to i32 %1797 = sitofp i32 %1796 to float %1798 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %1799 = extractelement <4 x float> %1798, i32 1 %1800 = bitcast float %1799 to i32 %1801 = sitofp i32 %1800 to float %1802 = fdiv float 1.000000e+00, %1797 %1803 = fdiv float 1.000000e+00, %1801 %1804 = fmul float %1792, %1802 %1805 = fmul float %1793, %1803 %1806 = insertelement <4 x float> undef, float %1804, i32 0 %1807 = insertelement <4 x float> %1806, float %1805, i32 1 %1808 = insertelement <4 x float> %1807, float 0.000000e+00, i32 2 %1809 = insertelement <4 x float> %1808, float 0.000000e+00, i32 3 %1810 = extractelement <4 x float> %1809, i32 0 %1811 = extractelement <4 x float> %1809, i32 1 %1812 = insertelement <4 x float> undef, float %1810, i32 0 %1813 = insertelement <4 x float> %1812, float %1811, i32 1 %1814 = insertelement <4 x float> %1813, float undef, i32 2 %1815 = insertelement <4 x float> %1814, float undef, i32 3 %1816 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %1815, i32 16, i32 0, i32 2) %1817 = extractelement <4 x float> %1816, i32 0 %1818 = extractelement <4 x float> %1816, i32 3 %1819 = fmul float %1817, 0x406FFFFFE0000000 %1820 = fmul float %1818, 0x406FFFFFE0000000 %1821 = fptosi float %1819 to i32 %1822 = fptosi float %1820 to i32 %1823 = bitcast i32 %1821 to float %1824 = bitcast i32 %1822 to float %1825 = bitcast float %1823 to i32 %1826 = icmp eq i32 %1825, 0 %1827 = sext i1 %1826 to i32 %1828 = bitcast i32 %1827 to float %1829 = bitcast float %1828 to i32 %1830 = icmp ne i32 %1829, 0 br i1 %1830, label %IF1022, label %ENDIF1021 LOOP1008.outer: ; preds = %ELSE1020, %ELSE1003 %temp44.8.ph = phi float [ 1.000000e+09, %ELSE1003 ], [ %1950, %ELSE1020 ] %temp32.4.ph = phi float [ 0x36A0000000000000, %ELSE1003 ], [ %1953, %ELSE1020 ] br label %LOOP1008 LOOP1008: ; preds = %LOOP1008.outer, %IF1019 %temp32.4 = phi float [ %1912, %IF1019 ], [ %temp32.4.ph, %LOOP1008.outer ] %1831 = bitcast float %temp32.4 to i32 %1832 = icmp sge i32 %1831, 32 %1833 = sext i1 %1832 to i32 %1834 = bitcast i32 %1833 to float %1835 = bitcast float %1834 to i32 %1836 = icmp ne i32 %1835, 0 br i1 %1836, label %ENDIF1001, label %ENDIF1009 ENDIF1009: ; preds = %LOOP1008 %1837 = bitcast float %temp32.4 to i32 %1838 = icmp sge i32 %1837, %1690 %1839 = sext i1 %1838 to i32 %1840 = bitcast i32 %1839 to float %1841 = bitcast float %1840 to i32 %1842 = icmp ne i32 %1841, 0 br i1 %1842, label %ENDIF1001, label %ENDIF1012 ENDIF1012: ; preds = %ENDIF1009 %1843 = bitcast float %temp32.4 to i32 %1844 = add i32 %1691, %1843 %1845 = bitcast i32 %1844 to float %1846 = bitcast float %1845 to i32 %1847 = sitofp i32 %1846 to float %1848 = fmul float %1847, %1694 %1849 = call float @llvm.AMDIL.fraction.(float %1848) %1850 = fmul float %1693, %1849 %1851 = fptosi float %1850 to i32 %1852 = bitcast i32 %1851 to float %1853 = bitcast float %1845 to i32 %1854 = sdiv i32 %1853, %1695 %1855 = bitcast i32 %1854 to float %1856 = bitcast float %1852 to i32 %1857 = add i32 %1698, %1856 %1858 = bitcast float %1855 to i32 %1859 = add i32 %1701, %1858 %1860 = bitcast i32 %1857 to float %1861 = bitcast i32 %1859 to float %1862 = bitcast float %1860 to i32 %1863 = sitofp i32 %1862 to float %1864 = bitcast float %1861 to i32 %1865 = sitofp i32 %1864 to float %1866 = fadd float %1863, 5.000000e-01 %1867 = fadd float %1865, 5.000000e-01 %1868 = fmul float %1866, %1706 %1869 = fmul float %1867, %1707 %1870 = insertelement <4 x float> undef, float %1868, i32 0 %1871 = insertelement <4 x float> %1870, float %1869, i32 1 %1872 = insertelement <4 x float> %1871, float 0.000000e+00, i32 2 %1873 = insertelement <4 x float> %1872, float 0.000000e+00, i32 3 %1874 = extractelement <4 x float> %1873, i32 0 %1875 = extractelement <4 x float> %1873, i32 1 %1876 = insertelement <4 x float> undef, float %1874, i32 0 %1877 = insertelement <4 x float> %1876, float %1875, i32 1 %1878 = insertelement <4 x float> %1877, float undef, i32 2 %1879 = insertelement <4 x float> %1878, float undef, i32 3 %1880 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %1879, i32 16, i32 0, i32 2) %1881 = extractelement <4 x float> %1880, i32 0 %1882 = extractelement <4 x float> %1880, i32 3 %1883 = fmul float %1882, 0x406FFFFFE0000000 %1884 = fptosi float %1883 to i32 %1885 = bitcast i32 %1884 to float %1886 = bitcast float %1885 to i32 %1887 = sitofp i32 %1886 to float %1888 = fmul float %1887, 6.250000e-02 %1889 = call float @llvm.AMDIL.fraction.(float %1888) %1890 = fcmp oeq float %1881, 0.000000e+00 %1891 = sext i1 %1890 to i32 %1892 = bitcast i32 %1891 to float %1893 = bitcast float %1892 to i32 %1894 = icmp ne i32 %1893, 0 br i1 %1894, label %ENDIF1015, label %ELSE1017 ELSE1017: ; preds = %ENDIF1012 %1895 = fmul float %1881, 0x406FFFFFE0000000 %1896 = fptosi float %1895 to i32 %1897 = bitcast i32 %1896 to float %1898 = bitcast float %1897 to i32 %1899 = add i32 %1898, -128 %1900 = bitcast i32 %1899 to float %1901 = bitcast float %1900 to i32 %1902 = sitofp i32 %1901 to float %1903 = fmul float 0x3F70204080000000, %1902 br label %ENDIF1015 ENDIF1015: ; preds = %ENDIF1012, %ELSE1017 %temp172.0 = phi float [ %1903, %ELSE1017 ], [ 1.000000e+09, %ENDIF1012 ] %1904 = call float @fabs(float %temp172.0) %1905 = fcmp oge float %1904, 5.000000e+08 %1906 = sext i1 %1905 to i32 %1907 = bitcast i32 %1906 to float %1908 = bitcast float %1907 to i32 %1909 = icmp ne i32 %1908, 0 br i1 %1909, label %IF1019, label %ELSE1020 IF1019: ; preds = %ENDIF1015 %1910 = bitcast float %temp32.4 to i32 %1911 = add i32 %1910, 1 %1912 = bitcast i32 %1911 to float br label %LOOP1008 ELSE1020: ; preds = %ENDIF1015 %1913 = extractelement <4 x float> %1880, i32 1 %1914 = extractelement <4 x float> %1880, i32 2 %1915 = bitcast float %1885 to i32 %1916 = sdiv i32 %1915, 16 %1917 = bitcast i32 %1916 to float %1918 = fmul float 1.600000e+01, %1889 %1919 = fptosi float %1918 to i32 %1920 = bitcast i32 %1919 to float %1921 = bitcast float %1917 to i32 %1922 = sitofp i32 %1921 to float %1923 = bitcast float %1920 to i32 %1924 = sitofp i32 %1923 to float %1925 = fadd float %1922, %1913 %1926 = fadd float %1924, %1914 %1927 = fmul float %1925, 6.250000e-02 %1928 = fmul float %1926, 6.250000e-02 %1929 = fmul float %1927, %1709 %1930 = fmul float %1928, %1711 %1931 = fsub float -0.000000e+00, %1929 %1932 = fadd float %0, %1931 %1933 = fsub float -0.000000e+00, %1930 %1934 = fadd float %1, %1933 %1935 = insertelement <4 x float> undef, float %1932, i32 0 %1936 = insertelement <4 x float> %1935, float %1934, i32 1 %1937 = insertelement <4 x float> %1936, float 0.000000e+00, i32 2 %1938 = insertelement <4 x float> %1937, float 0.000000e+00, i32 3 %1939 = insertelement <4 x float> undef, float %1932, i32 0 %1940 = insertelement <4 x float> %1939, float %1934, i32 1 %1941 = insertelement <4 x float> %1940, float 0.000000e+00, i32 2 %1942 = insertelement <4 x float> %1941, float 0.000000e+00, i32 3 %1943 = call float @llvm.AMDGPU.dp4(<4 x float> %1938, <4 x float> %1942) %1944 = call float @llvm.AMDGPU.rsq(float %1943) %1945 = fmul float %1944, %1943 %1946 = fsub float -0.000000e+00, %1943 %1947 = fcmp ult float %1946, 0.000000e+00 %1948 = select i1 %1947, float %1945, float 0.000000e+00 %1949 = fcmp uge float %temp44.8.ph, %1948 %1950 = select i1 %1949, float %1948, float %temp44.8.ph %1951 = bitcast float %temp32.4 to i32 %1952 = add i32 %1951, 1 %1953 = bitcast i32 %1952 to float br label %LOOP1008.outer IF1022: ; preds = %ENDIF1001 %1954 = bitcast float %1824 to i32 %1955 = icmp eq i32 %1954, 255 %1956 = sext i1 %1955 to i32 %1957 = bitcast i32 %1956 to float %1958 = bitcast float %1957 to i32 %1959 = icmp ne i32 %1958, 0 %.1029 = select i1 %1959, float 0.000000e+00, float %1824 br label %ENDIF1021 ENDIF1021: ; preds = %ENDIF1001, %IF1022 %temp8.0 = phi float [ %.1029, %IF1022 ], [ 0xFFFFFFFFE0000000, %ENDIF1001 ] %1960 = bitcast float %temp8.0 to i32 %1961 = sitofp i32 %1960 to float %1962 = fmul float 0.000000e+00, %1961 %1963 = fadd float %1962, %1720 %1964 = fmul float 0.000000e+00, %1961 %1965 = fadd float %1964, %1721 %1966 = fmul float 0x3FC0101020000000, %1961 %1967 = fadd float %1966, %1722 %1968 = fmul float 0x3F89B34D00000000, %1961 %1969 = fadd float %1968, %1723 br label %ENDIF971 } ; Function Attrs: readnone declare float @llvm.R600.load.input(i32) #1 ; Function Attrs: readnone declare float @llvm.AMDIL.fraction.(float) #1 ; Function Attrs: readnone declare <4 x float> @llvm.AMDGPU.ddx(<4 x float>, i32, i32, i32) #1 ; Function Attrs: readnone declare <4 x float> @llvm.AMDGPU.ddy(<4 x float>, i32, i32, i32) #1 ; Function Attrs: readnone declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1 ; Function Attrs: readnone declare float @llvm.AMDGPU.rsq(float) #1 ; Function Attrs: readonly declare float @fabs(float) #2 ; Function Attrs: readonly declare float @floor(float) #2 ; Function Attrs: readnone declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32, i32) #1 ; Function Attrs: nounwind readonly declare float @llvm.cos.f32(float) #3 ; Function Attrs: nounwind readonly declare float @llvm.sin.f32(float) #3 ; Function Attrs: readnone declare float @llvm.AMDGPU.lrp(float, float, float) #1 declare void @llvm.AMDGPU.kilp() ; Function Attrs: readnone declare float @llvm.AMDIL.clamp.(float, float, float) #1 ; Function Attrs: nounwind readonly declare float @llvm.pow.f32(float, float) #3 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } attributes #2 = { readonly } attributes #3 = { nounwind readonly } Shader Disassembly: ALU 110, @144, KC0[CB0:0-32], KC1[] ; 80000090 A1B80000 TEX 0 @128 ; 00000080 80800000 ALU 39, @255, KC0[], KC1[] ; 000000FF A09C0000 ALU_PUSH_BEFORE 1, @295, KC0[], KC1[] ; 00000127 A4040000 JUMP @6 POP:1 ; 00000006 85000001 ALU_POP_AFTER 13, @297, KC0[], KC1[] ; 00000129 A8340000 ALU_PUSH_BEFORE 7, @311, KC0[CB0:0-32], KC1[] ; 80000137 A41C0000 JUMP @72 POP:1 ; 00000048 85000001 ALU_PUSH_BEFORE 3, @319, KC0[], KC1[] ; 0000013F A40C0000 JUMP @71 POP:1 ; 00000047 85000001 ALU 29, @323, KC0[], KC1[] ; 00000143 A0740000 TEX 0 @130 ; 00000082 80800000 ALU 47, @353, KC0[], KC1[] ; 00000161 A0BC0000 LOOP_START_DX10 @66 ; 00000042 83000000 ALU 6, @401, KC0[], KC1[] ; 00000191 A0180000 LOOP_START_DX10 @30 ; 0000001E 83000000 ALU_PUSH_BEFORE 9, @408, KC0[], KC1[] ; 00000198 A4240000 JUMP @25 POP:1 ; 00000019 85000001 ALU_PUSH_BEFORE 5, @418, KC0[], KC1[] ; 000001A2 A4140000 JUMP @24 POP:1 ; 00000018 85000001 ALU 42, @424, KC0[], KC1[] ; 000001A8 A0A80000 TEX 0 @132 ; 00000084 80800000 ALU 43, @467, KC0[], KC1[] ; 000001D3 A0AC0000 ALU_POP_AFTER 0, @511, KC0[], KC1[] ; 000001FF A8000000 POP @25 POP:1 ; 00000019 87000001 ALU_PUSH_BEFORE 4, @512, KC0[], KC1[] ; 00000200 A4100000 JUMP @29 POP:1 ; 0000001D 85000001 LOOP_BREAK @29 ; 0000001D 84800000 POP @29 POP:1 ; 0000001D 87000001 END_LOOP @16 ; 00000010 82800000 ALU_PUSH_BEFORE 3, @517, KC0[], KC1[] ; 00000205 A40C0000 JUMP @61 POP:1 ; 0000003D 85000001 ALU_PUSH_BEFORE 47, @521, KC0[], KC1[] ; 00000209 A4BC0000 JUMP @43 POP:1 ; 0000002B 85000001 ALU_PUSH_BEFORE 27, @569, KC0[], KC1[] ; 00000239 A46C0000 JUMP @42 POP:1 ; 0000002A 85000001 ALU_PUSH_BEFORE 7, @597, KC0[], KC1[] ; 00000255 A41C0000 JUMP @41 POP:1 ; 00000029 85000001 ALU 49, @605, KC0[], KC1[] ; 0000025D A0C40000 ALU 69, @655, KC0[], KC1[] ; 0000028F A1140000 ALU_POP_AFTER 31, @725, KC0[], KC1[] ; 000002D5 A87C0000 ALU_POP_AFTER 4, @757, KC0[], KC1[] ; 000002F5 A8100000 POP @43 POP:1 ; 0000002B 87000001 ALU_PUSH_BEFORE 1, @762, KC0[], KC1[] ; 000002FA A4040000 JUMP @60 POP:1 ; 0000003C 85000001 ALU 42, @764, KC0[], KC1[] ; 000002FC A0A80000 ALU_PUSH_BEFORE 1, @807, KC0[], KC1[] ; 00000327 A4040000 JUMP @59 POP:1 ; 0000003B 85000001 ALU_PUSH_BEFORE 12, @809, KC0[], KC1[] ; 00000329 A4300000 JUMP @58 POP:1 ; 0000003A 85000001 ALU_PUSH_BEFORE 10, @822, KC0[], KC1[] ; 00000336 A4280000 JUMP @57 POP:1 ; 00000039 85000001 ALU_PUSH_BEFORE 12, @833, KC0[], KC1[] ; 00000341 A4300000 JUMP @56 POP:1 ; 00000038 85000001 ALU 13, @846, KC0[], KC1[] ; 0000034E A0340000 ALU_POP_AFTER 28, @860, KC0[], KC1[] ; 0000035C A8700000 ALU_POP_AFTER 18, @889, KC0[], KC1[] ; 00000379 A8480000 ALU_POP_AFTER 15, @908, KC0[], KC1[] ; 0000038C A83C0000 POP @59 POP:1 ; 0000003B 87000001 ALU_POP_AFTER 16, @924, KC0[], KC1[] ; 0000039C A8400000 ALU_POP_AFTER 2, @941, KC0[], KC1[] ; 000003AD A8080000 ALU_PUSH_BEFORE 4, @944, KC0[], KC1[] ; 000003B0 A4100000 JUMP @65 POP:1 ; 00000041 85000001 LOOP_BREAK @65 ; 00000041 84800000 POP @65 POP:1 ; 00000041 87000001 END_LOOP @14 ; 0000000E 82800000 ALU_PUSH_BEFORE 1, @949, KC0[], KC1[] ; 000003B5 A4040000 JUMP @70 POP:1 ; 00000046 85000001 ALU 49, @951, KC0[], KC1[] ; 000003B7 A0C40000 ALU_POP_AFTER 32, @1001, KC0[], KC1[] ; 000003E9 A8800000 ALU_POP_AFTER 2, @1034, KC0[], KC1[] ; 0000040A A8080000 ALU_POP_AFTER 26, @1037, KC0[], KC1[] ; 0000040D A8680000 TEX 1 @134 ; 00000086 80800400 ALU_PUSH_BEFORE 34, @1064, KC0[CB0:0-32], KC1[] ; 80000428 A4880000 JUMP @106 POP:1 ; 0000006A 85000001 ALU 82, @1099, KC0[], KC1[] ; 0000044B A1480000 TEX 0 @138 ; 0000008A 80800000 ALU_PUSH_BEFORE 24, @1182, KC0[], KC1[] ; 0000049E A4600000 JUMP @104 POP:1 ; 00000068 85000001 ALU 12, @1207, KC0[], KC1[] ; 000004B7 A0300000 LOOP_START_DX10 @103 ; 00000067 83000000 ALU 0, @1220, KC0[], KC1[] ; 000004C4 A0000000 LOOP_START_DX10 @97 ; 00000061 83000000 ALU_PUSH_BEFORE 6, @1221, KC0[], KC1[] ; 000004C5 A4180000 JUMP @92 POP:1 ; 0000005C 85000001 ALU_PUSH_BEFORE 5, @1228, KC0[], KC1[] ; 000004CC A4140000 JUMP @91 POP:1 ; 0000005B 85000001 ALU 42, @1234, KC0[], KC1[] ; 000004D2 A0A80000 TEX 0 @140 ; 0000008C 80800000 ALU 25, @1277, KC0[], KC1[] ; 000004FD A0640000 ALU_POP_AFTER 1, @1303, KC0[], KC1[] ; 00000517 A8040000 POP @92 POP:1 ; 0000005C 87000001 ALU_PUSH_BEFORE 4, @1305, KC0[], KC1[] ; 00000519 A4100000 JUMP @96 POP:1 ; 00000060 85000001 LOOP_BREAK @96 ; 00000060 84800000 POP @96 POP:1 ; 00000060 87000001 END_LOOP @83 ; 00000053 82800000 ALU 34, @1310, KC0[], KC1[] ; 0000051E A0880000 ALU_PUSH_BEFORE 1, @1345, KC0[], KC1[] ; 00000541 A4040000 JUMP @102 POP:1 ; 00000066 85000001 LOOP_BREAK @102 ; 00000066 84800000 POP @102 POP:1 ; 00000066 87000001 END_LOOP @81 ; 00000051 82800000 POP @104 POP:1 ; 00000068 87000001 TEX 0 @142 ; 0000008E 80800000 ALU_POP_AFTER 36, @1347, KC0[], KC1[] ; 00000543 A8900000 ALU_PUSH_BEFORE 4, @1384, KC0[], KC1[] ; 00000568 A4100000 JUMP @125 POP:1 ; 0000007D 85000001 ALU_PUSH_BEFORE 3, @1389, KC0[CB0:0-32], KC1[] ; 8000056D A40C0000 JUMP @111 POP:1 ; 0000006F 85000001 ALU_POP_AFTER 2, @1393, KC0[CB0:0-32], KC1[] ; 80000571 A8080000 ALU_PUSH_BEFORE 2, @1396, KC0[], KC1[] ; 00000574 A4080000 JUMP @114 POP:1 ; 00000072 85000001 ALU_POP_AFTER 0, @1399, KC0[], KC1[] ; 00000577 A8000000 ALU_PUSH_BEFORE 5, @1400, KC0[], KC1[] ; 00000578 A4140000 JUMP @121 POP:1 ; 00000079 85000001 ALU_PUSH_BEFORE 5, @1406, KC0[], KC1[] ; 0000057E A4140000 JUMP @120 POP:1 ; 00000078 85000001 ALU 13, @1412, KC0[], KC1[] ; 00000584 A0340000 ALU_POP_AFTER 7, @1426, KC0[], KC1[] ; 00000592 A81C0000 POP @121 POP:1 ; 00000079 87000001 ALU_PUSH_BEFORE 12, @1434, KC0[CB0:0-32], KC1[] ; 8000059A A4300000 JUMP @124 POP:1 ; 0000007C 85000001 ALU_POP_AFTER 3, @1447, KC0[CB0:0-32], KC1[] ; 800005A7 A80C0000 ALU_POP_AFTER 1, @1451, KC0[], KC1[] ; 000005AB A8040000 ALU 1, @1453, KC0[], KC1[] ; 000005AD A0040000 EXPORT T10.XYZW ; C0050000 94200688 CF_END ; 00000000 80200000 Fetch clause starting at 128: ; TEX_SAMPLE T6.XYZW, T6.XY__ RID:16 SID:0 CT:NNNN ; 00061010 F00D1006 FC800000 00000000 Fetch clause starting at 130: ; TEX_SAMPLE T10.XYZW, T9.XY__ RID:16 SID:0 CT:NNNN ; 00091010 F00D100A FC800000 00000000 Fetch clause starting at 132: ; TEX_SAMPLE T13.XYZW, T13.XY__ RID:16 SID:0 CT:NNNN ; 000D1010 F00D100D FC800000 00000000 Fetch clause starting at 134: ; TEX_GET_GRADIENTS_V T7.XYZW, T0.ZWWW RID:20 SID:4 CT:NNNN ; 00001408 F00D1007 6DA20000 00000000 TEX_GET_GRADIENTS_H T8.XYZW, T0.XYYY RID:16 SID:0 CT:NNNN ; 00001007 F00D1008 24800000 00000000 Fetch clause starting at 138: ; TEX_SAMPLE T14.XYZW, T13.XY__ RID:16 SID:0 CT:NNNN ; 000D1010 F00D100E FC800000 00000000 Fetch clause starting at 140: ; TEX_SAMPLE T14.XYZW, T14.XY__ RID:16 SID:0 CT:NNNN ; 000E1010 F00D100E FC800000 00000000 Fetch clause starting at 142: ; TEX_SAMPLE T1.XYZW, T13.XY__ RID:16 SID:0 CT:NNNN ; 000D1010 F00D1001 FC800000 00000000 ALU clause starting at 144: ; MOV T1.X, T0.W, ; 00000C00 00201910 MOV * T1.Y, T0.Z, ; 80000800 20201910 MUL_IEEE * T1.W, PV.X, literal.x, ; 801FA0FE 60200210 998244352(3.906250e-03), 0(0.000000e+00) ; 3B800000 00000000 FRACT * T1.W, PV.W, ; 80000CFE 60201010 MUL_IEEE T1.W, PV.W, literal.x, ; 001FACFE 60200210 MUL_IEEE * T2.W, T1.Y, literal.y, ; 809FA401 60400210 1132462080(2.560000e+02), 998244352(3.906250e-03) ; 43800000 3B800000 FLT_TO_INT * T1.Z, PV.W, ; 80000CFE 40206B10 ADD_INT T1.W, PS, literal.x, ; 001FA0FF 60203410 FRACT * T2.W, T2.W, ; 80000C02 60401010 2(2.802597e-45), 0(0.000000e+00) ; 00000002 00000000 MUL_IEEE T2.W, PS, literal.x, ; 001FA0FF 60400210 ASHR * T3.W, PV.W, literal.y, ; 809FACFE 60607010 1132462080(2.560000e+02), 31(4.344025e-44) ; 43800000 0000001F LSHR T3.W, PS, literal.x, ; 001FA0FF 60607110 FLT_TO_INT * T1.Z, PV.W, ; 80000CFE 40206B10 30(4.203895e-44), 0(0.000000e+00) ; 0000001E 00000000 MUL_IEEE T0.Z, KC0[8].X, T0.X, ; 00000088 40000210 ADD_INT T1.W, T1.W, PV.W, ; 019FCC01 60203410 ADD_INT * T2.W, PS, literal.x, ; 801FA0FF 60403410 2(2.802597e-45), 0(0.000000e+00) ; 00000002 00000000 ASHR T1.Z, PS, literal.x, ; 001FA0FF 40207010 ASHR T1.W, PV.W, literal.y, ; 009FACFE 60207010 MUL_IEEE * T0.W, KC0[8].X, T0.Y, ; 80800088 60000210 31(4.344025e-44), 2(2.802597e-45) ; 0000001F 00000002 ADD_INT T2.Z, PV.W, literal.x, ; 001FACFE 40403410 FLOOR T3.W, T0.Y, ; 00000400 60601410 LSHR * T4.W, PV.Z, literal.y, ; 809FA8FE 60807110 -1(-nan), 30(4.203895e-44) ; FFFFFFFF 0000001E ADD_INT T1.Z, T2.W, PS, ; 001FEC02 40203410 MAX T2.W, 0.0, PV.W, ; 019FC0F8 60400310 INT_TO_FLT * T2.X, PV.Z, ; 800008FE 00406C10 MIN T3.W, PS, PV.W, ; 019FC0FF 60600410 ASHR * T2.W, PV.Z, literal.x, ; 801FA8FE 60407010 2(2.802597e-45), 0(0.000000e+00) ; 00000002 00000000 ADD_INT T1.Z, PS, literal.x, ; 001FA0FF 40203410 FLOOR T4.W, T0.X, ; 00000000 60801410 FLT_TO_INT * T3.X, PV.W, ; 80000CFE 00606B10 -1(-nan), 0(0.000000e+00) ; FFFFFFFF 00000000 SETGT_INT T2.Z, 0.0, KC0[1].Z, ; 011020F8 40403B10 MAX T3.W, 0.0, PV.W, ; 019FC0F8 60600310 INT_TO_FLT * T2.Y, PV.Z, ; 800008FE 20406C10 MIN T1.Z, PS, PV.W, ; 019FC0FF 40200410 ADD_INT T3.W, KC0[1].Z, PV.Z, ; 011FC881 60603410 MULLO_INT * T3.X, T3.X, T2.W, ; 81804003 00607310 XOR_INT T4.W, PV.W, T2.Z, ; 01004CFE 60803210 FLT_TO_INT * T1.Z, PV.Z, ; 800008FE 40206B10 RECIP_UINT * T3.Y, PV.W, ; 80000CFE 20607810 MULLO_INT * T3.Z, PS, T4.W, ; 818080FF 40607310 SUB_INT T3.W, 0.0, PS, ; 001FE0F8 60603510 MULHI * T4.X, T3.Y, T4.W, ; 81808403 00807610 CNDE_INT T3.W, PS, PV.W, T3.Z, ; 019FC0FF 60638803 ADD_INT * T6.W, T3.X, T1.Z, ; 81002003 60C03410 SETGT_INT T7.W, 0.0, PS, ; 001FE0F8 60E03B10 MULHI * T1.Z, PV.W, T3.Y, ; 80806CFE 40207610 SUB_INT T3.Z, T3.Y, PS, ; 001FE403 40603510 ADD_INT T3.W, T3.Y, PS, ; 001FE403 60603410 ADD_INT * T5.W, T6.W, PV.W, ; 819FCC06 60A03410 XOR_INT T8.W, PS, T7.W, ; 0180E0FF 61003210 CNDE_INT * T5.W, T4.X, PV.W, PV.Z, ; 819FC004 60A388FE MULHI * T1.Z, PS, PV.W, ; 819FC0FF 40207610 MULLO_INT * T3.X, PS, T4.W, ; 818080FF 00607310 SUB_INT * T3.W, T8.W, PS, ; 801FEC08 60603510 SETGE_UINT T3.Z, PV.W, T4.W, ; 01808CFE 40603F10 SETGE_UINT T3.W, T8.W, T3.X, ; 00006C08 60603F10 FLT_TO_INT * T1.X, T1.X, ; 80000001 00206B10 AND_INT T3.Y, PV.Z, PV.W, ; 019FC8FE 20603010 ADD_INT T3.Z, T1.Z, 1, ; 001F4801 40603410 ASHR T8.W, PS, literal.x, ; 001FA0FF 61007010 FLT_TO_INT * T1.Y, T1.Y, ; 80000401 20206B10 31(4.344025e-44), 0(0.000000e+00) ; 0000001F 00000000 LSHR T4.Y, PV.W, literal.x, ; 001FACFE 20807110 CNDE_INT T3.Z, PV.Y, T1.Z, PV.Z, ; 010024FE 406388FE ADD_INT T8.W, T1.Z, literal.y, ; 009FA801 61003410 INT_TO_FLT * T4.X, T6.W, ; 80000C06 00806C10 24(3.363116e-44), -1(-nan) ; 00000018 FFFFFFFF CNDE_INT T3.Y, T3.W, PV.W, PV.Z, ; 019FCC03 206388FE XOR_INT T3.Z, T7.W, T2.Z, BS:VEC_120/SCL_212 ; 01004C07 40683210 ADD_INT T3.W, T1.X, PV.Y, ; 009FC001 60603410 INT_TO_FLT * T3.X, KC0[1].Z, ; 80000881 00606C10 ASHR T1.Z, PV.W, literal.x, ; 001FACFE 40207010 ADD_INT T3.W, PV.Y, PV.Z, ; 011FC4FE 60603410 RECIP_IEEE * T3.Y, PS, ; 800000FF 20606610 8(1.121039e-44), 0(0.000000e+00) ; 00000008 00000000 MUL_IEEE T4.Y, T4.X, PS, ; 001FE004 20800210 ASHR T4.Z, T1.Y, literal.x, ; 001FA401 40807010 XOR_INT T3.W, PV.W, T3.Z, ; 01006CFE 60603210 MULLO_INT * T1.X, PV.Z, KC0[1].W, ; 819028FE 00207310 31(4.344025e-44), 0(0.000000e+00) ; 0000001F 00000000 ADD_INT T5.Y, PS, PV.W, ; 019FC0FF 20A03410 LSHR T3.Z, PV.Z, literal.x, ; 001FA8FE 40607110 FRACT T3.W, PV.Y, ; 000004FE 60601010 INT_TO_FLT * T4.X, KC0[1].Y, ; 80000481 00806C10 24(3.363116e-44), 0(0.000000e+00) ; 00000018 00000000 MUL_IEEE T4.Z, T3.X, PV.W, ; 019FC003 40800210 ADD_INT T3.W, T1.Y, PV.Z, ; 011FC401 60603410 INT_TO_FLT * T1.Y, PV.Y, ; 800004FE 20206C10 ASHR T3.W, PV.W, literal.x, ; 001FACFE 60607010 FLT_TO_INT * T3.Z, PV.Z, ; 800008FE 40606B10 8(1.121039e-44), 0(0.000000e+00) ; 00000008 00000000 MULLO_INT * T4.Y, PV.W, KC0[1].Z, ; 81102CFE 20807310 ADD_INT T6.W, PS, T3.Z, ; 010060FF 60C03410 INT_TO_FLT * T3.Z, KC0[1].X, ; 80000081 40606C10 INT_TO_FLT * T4.Z, PV.W, ; 80000CFE 40806C10 ADD T6.W, PS, 0.5, ; 001F80FF 60C00010 RECIP_IEEE * T3.Z, T3.Z, ; 80000803 40606610 MUL_IEEE T6.X, PV.W, PS, ; 001FECFE 00C00210 ADD T7.W, T1.Y, 0.5, ; 001F8401 60E00010 RECIP_IEEE * T4.X, T4.X, ; 80000004 00806610 MUL_IEEE * T6.Y, PV.W, PS, ; 801FECFE 20C00210 ALU clause starting at 255: ; MUL_IEEE T7.W, T6.W, literal.x, ; 001FAC06 60E00210 MUL_IEEE * T8.W, T6.Z, literal.x, ; 801FA806 61000210 1132462079(2.560000e+02), 0(0.000000e+00) ; 437FFFFF 00000000 FLT_TO_INT * T4.Z, PV.W, ; 80000CFE 40806B10 MUL_IEEE T7.W, T6.X, literal.x, ; 001FA006 60E00210 FLT_TO_INT * T5.X, T8.W, ; 80000C08 00A06B10 1132462079(2.560000e+02), 0(0.000000e+00) ; 437FFFFF 00000000 MUL_IEEE T6.W, T6.Y, literal.x, ; 001FA406 60C00210 FLT_TO_INT * T1.Y, PV.W, ; 80000CFE 20206B10 1132462079(2.560000e+02), 0(0.000000e+00) ; 437FFFFF 00000000 MOV T6.Z, literal.x, ; 000000FD 40C01910 SETNE_INT T7.W, PS, 0.0, ; 001F00FF 60E03D10 FLT_TO_INT * T6.Y, PV.W, ; 80000CFE 20C06B10 1(1.401298e-45), 0(0.000000e+00) ; 00000001 00000000 PRED_SETNE_INT * Pred,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00004508 LSHL * T6.W, T1.Y, literal.x, Pred_sel_one ; E01FA401 60C07210 8(1.121039e-44), 0(0.000000e+00) ; 00000008 00000000 LSHL T5.Z, T5.X, literal.x, Pred_sel_one ; 601FA005 40A07210 ADD_INT T6.W, T6.W, T6.Y, Pred_sel_one ; 6080CC06 60C03410 INT_TO_FLT * T5.Y, T1.W, Pred_sel_one ; E0000C01 20A06C10 8(1.121039e-44), 0(0.000000e+00) ; 00000008 00000000 ADD_INT T6.Z, T6.W, literal.x, Pred_sel_one ; 601FAC06 40C03410 ADD_INT T6.W, T5.Z, T4.Z, Pred_sel_one ; 61008805 60C03410 INT_TO_FLT * T5.Z, T2.W, Pred_sel_one ; E0000C02 40A06C10 -49152(-nan), 0(0.000000e+00) ; FFFF4000 00000000 SUB_INT T6.W, literal.x, T6.W, Pred_sel_one ; 6180C0FD 60C03510 INT_TO_FLT * T6.X, T6.Z, Pred_sel_one ; E0000806 00C06C10 32768(4.591775e-41), 0(0.000000e+00) ; 00008000 00000000 MUL_IEEE T7.Y, T6.X, literal.x, Pred_sel_one ; 601FA006 20E00210 MOV T6.Z, literal.y, Pred_sel_one ; 600004FD 40C01910 MAX T7.W, T5.Y, T5.Z, Pred_sel_one ; 6100A405 60E00310 INT_TO_FLT * T6.W, T6.W, Pred_sel_one ; E0000C06 60C06C10 956302336(1.220852e-04), 0(0.000000e+00) ; 39000400 00000000 MOV T6.X, literal.x, Pred_sel_one ; 600000FD 00C01910 MOV T5.Y, literal.y, Pred_sel_one ; 600004FD 20A01910 MUL_IEEE T5.Z, T7.Y, T7.W, Pred_sel_one ; 6180E407 40A00210 MUL_IEEE T7.W, T6.W, literal.z, Pred_sel_one ; 611FAC06 60E00210 SETE_INT * T8.W, T1.Y, 0.0, Pred_sel_one ; E01F0401 61003A10 0(0.000000e+00), -1(-nan) ; 00000000 FFFFFFFF 952701293(9.587673e-05), 0(0.000000e+00) ; 38C9116D 00000000 ALU clause starting at 295: ; SETNE_INT * T6.W, T6.Z, 1, ; 801F4806 60C03D10 PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00004204 ALU clause starting at 297: ; LSHL * T6.W, T6.Y, literal.x, ; 801FA406 60C07210 8(1.121039e-44), 0(0.000000e+00) ; 00000008 00000000 MOV T6.X, literal.x, ; 000000FD 00C01910 MOV T5.Y, literal.y, ; 000004FD 20A01910 SETE_INT T5.Z, T4.Z, literal.z, ; 011FA804 40A03A10 ADD_INT T8.W, PV.W, T5.X, ; 0000ACFE 61003410 SETNE_INT * T6.W, T4.Z, literal.z, ; 811FA804 60C03D10 -1(-nan), 0(0.000000e+00) ; FFFFFFFF 00000000 255(3.573311e-43), 0(0.000000e+00) ; 000000FF 00000000 PRED_SETNE_INT * Pred,PredicateBit (MASKED), PS, 0.0, ; 801F00FF 00004508 SETE_INT * T5.Z, T4.Z, 0.0, Pred_sel_one ; E01F0804 40A03A10 CNDE_INT T6.X, T5.Z, 0.0, 1, Pred_sel_one ; 601F0805 00C380FA MOV * T5.Y, T4.Z, Pred_sel_one BS:VEC_120/SCL_212 ; E0000804 20A81910 MOV * T7.W, T1.Y, ; 80000401 60E01910 ALU clause starting at 311: ; MOV * T9.W, literal.x, ; 800000FD 61201910 1(1.401298e-45), 0(0.000000e+00) ; 00000001 00000000 MOV T5.X, KC0[1].W, ; 00000C81 00A01910 MOV T1.Y, KC0[1].Z, ; 00000881 20201910 MOV T4.Z, KC0[1].Y, ; 00000481 40801910 MOV T6.W, KC0[1].X, ; 00000081 60C01910 SETNE_INT * T10.W, T5.Y, 0.0, ; 801F0405 61403D10 PRED_SETNE_INT * ExecMask,PredicateBit (MASKED), PS, 0.0, ; 801F00FF 00004504 ALU clause starting at 319: ; MOV T9.W, literal.x, ; 000000FD 61201910 SETNE_INT * T10.W, T5.Y, literal.y, ; 809FA405 61403D10 1(1.401298e-45), -1(-nan) ; 00000001 FFFFFFFF PRED_SETNE_INT * ExecMask,PredicateBit (MASKED), PS, 0.0, ; 801F00FF 00004504 ALU clause starting at 323: ; SETGT_INT * T9.W, 0.0, T8.W, ; 818100F8 61203B10 ADD_INT * T10.W, T8.W, PV.W, ; 819FCC08 61403410 XOR_INT * T10.W, PV.W, T9.W, ; 81812CFE 61403210 MULHI * T6.Y, T5.W, PV.W, ; 819FCC05 20C07610 MULLO_INT * T6.Z, PS, T4.W, ; 818080FF 40C07310 SUB_INT * T11.W, T10.W, PS, ; 801FEC0A 61603510 SETGE_UINT T7.Z, PV.W, T4.W, ; 01808CFE 40E03F10 SETGE_UINT T10.W, T10.W, T6.Z, ; 0100CC0A 61403F10 INT_TO_FLT * T6.Z, T8.W, ; 80000C08 40C06C10 MUL_IEEE T6.Z, PS, T3.Y, ; 008060FF 40C00210 AND_INT T11.W, PV.Z, PV.W, ; 019FC8FE 61603010 ADD_INT * T12.W, T6.Y, 1, ; 801F4406 61803410 CNDE_INT T7.Z, PV.W, T6.Y, PS, ; 0080CCFE 40E380FF ADD_INT T11.W, T6.Y, literal.x, ; 001FA406 61603410 FRACT * T12.W, PV.Z, ; 800008FE 61801010 -1(-nan), 0(0.000000e+00) ; FFFFFFFF 00000000 MUL_IEEE T6.Z, T3.X, PS, ; 001FE003 40C00210 CNDE_INT T10.W, T10.W, PV.W, PV.Z, ; 019FCC0A 614388FE XOR_INT * T9.W, T9.W, T2.Z, ; 81004C09 61203210 ADD_INT T10.W, PV.W, PS, ; 001FECFE 61403410 FLT_TO_INT * T6.Y, PV.Z, ; 800008FE 20C06B10 ADD_INT T11.W, T4.Y, PS, ; 001FE404 61603410 XOR_INT * T9.W, PV.W, T9.W, ; 81812CFE 61203210 ADD_INT T9.W, T1.X, PS, ; 001FE001 61203410 INT_TO_FLT * T6.Y, PV.W, ; 80000CFE 20C06C10 ADD T10.W, PS, 0.5, ; 001F80FF 61400010 INT_TO_FLT * T6.Y, PV.W, ; 80000CFE 20C06C10 MUL_IEEE T9.X, PV.W, T3.Z, ; 01006CFE 01200210 ADD * T10.W, PS, 0.5, ; 801F80FF 61400010 MUL_IEEE * T9.Y, PV.W, T4.X, ; 80008CFE 21200210 ALU clause starting at 353: ; INT_TO_FLT * T6.Y, T4.Z, ; 80000804 20C06C10 RECIP_IEEE * T8.X, PS, ; 800000FF 01006610 INT_TO_FLT * T6.Y, T6.W, ; 80000C06 20C06C10 RECIP_IEEE * T8.Y, PS, ; 800000FF 21006610 MUL_IEEE T9.W, T10.W, literal.x, ; 001FAC0A 61200210 MULLO_INT * T8.Z, T1.Z, T5.X, ; 8000A801 41007310 1132462079(2.560000e+02), 0(0.000000e+00) ; 437FFFFF 00000000 FLT_TO_INT * T6.Y, PV.W, ; 80000CFE 20C06B10 ASHR T9.W, PS, literal.x, ; 001FA0FF 61207010 MULLO_INT * T9.X, T3.W, T1.Y, ; 80802C03 01207310 31(4.344025e-44), 0(0.000000e+00) ; 0000001F 00000000 LSHR T9.W, PV.W, literal.x, ; 001FACFE 61207110 INT_TO_FLT * T6.Z, T6.Y, ; 80000406 40C06C10 28(3.923636e-44), 0(0.000000e+00) ; 0000001C 00000000 MUL_IEEE T6.Z, PS, literal.x, ; 001FA0FF 40C00210 ADD_INT T9.W, T6.Y, PV.W, ; 019FC406 61203410 INT_TO_FLT * T9.Y, T1.Y, ; 80000401 21206C10 1031798784(6.250000e-02), 0(0.000000e+00) ; 3D800000 00000000 ASHR T7.Z, PV.W, literal.x, ; 001FACFE 40E07010 FRACT T9.W, PV.Z, ; 000008FE 61201010 RECIP_IEEE * T9.Z, PS, ; 800000FF 41206610 4(5.605194e-45), 0(0.000000e+00) ; 00000004 00000000 MUL_IEEE T9.W, PV.W, literal.x, ; 001FACFE 61200210 INT_TO_FLT * T6.Y, PV.Z, ; 800008FE 20C06C10 1098907648(1.600000e+01), 0(0.000000e+00) ; 41800000 00000000 MOV T15.W, literal.x, ; 000000FD 61E01910 FLT_TO_INT * T6.Z, PV.W, ; 80000CFE 40C06B10 0(0.000000e+00), 0(0.000000e+00) ; 00000000 00000000 MOV * T16.Z, PV.W, ; 80000CFE 42001910 MOV T16.X, T15.W, ; 00000C0F 02001910 INT_TO_FLT * T6.Z, T6.Z, ; 80000806 40C06C10 MOV T15.Z, T15.W, ; 00000C0F 41E01910 MOV * T14.Z, T15.W, ; 80000C0F 41C01910 ADD T6.Z, T6.Z, T10.Z, ; 01014806 40C00010 ADD T9.W, T6.Y, T10.Y, ; 00814406 61200010 INT_TO_FLT * T10.X, T2.W, ; 80000C02 01406C10 MOV T13.X, literal.x, ; 000000FD 01A01910 MOV T15.Y, literal.y, ; 000004FD 21E01910 MUL_IEEE T7.Z, PV.W, literal.z, ; 011FACFE 40E00210 MUL_IEEE T9.W, PV.Z, literal.z, ; 011FA8FE 61200210 INT_TO_FLT * T10.Y, T1.W, ; 80000C01 21406C10 1(1.401298e-45), 1315859240(1.000000e+09) ; 00000001 4E6E6B28 1031798784(6.250000e-02), 0(0.000000e+00) ; 3D800000 00000000 MOV T11.X, -T0.Y, ; 00001400 01601910 MOV T11.Y, -T0.X, ; 00001000 21601910 MUL_IEEE T11.Z, PV.W, PS, ; 001FECFE 41600210 MUL_IEEE T11.W, PV.Z, T10.X, ; 000148FE 61600210 INT_TO_FLT * T14.W, T6.X, ; 80000006 61C06C10 ALU clause starting at 401: ; MOV T7.X, T15.W, ; 00000C0F 00E01910 MOV * T6.Z, T14.Z, ; 8000080E 40C01910 MOV T7.Y, T15.Z, ; 0000080F 20E01910 MOV T7.Z, T16.X, ; 00000010 40E01910 MOV T9.W, T16.Z, BS:VEC_120/SCL_212 ; 00000810 61281910 MOV * T6.Y, T15.Y, ; 8000040F 20C01910 MOV * T10.W, T14.W, ; 80000C0E 61401910 ALU clause starting at 408: ; MOV * T10.Z, T13.X, ; 8000000D 41401910 SETGT_INT * T12.W, PV.Z, literal.x, ; 801FA8FE 61803B10 31(4.344025e-44), 0(0.000000e+00) ; 0000001F 00000000 MOV T14.X, literal.x, ; 000000FD 01C01910 MOV T13.Y, literal.y, ; 000004FD 21A01910 MOV * T12.X, T11.Z, ; 8000080B 01801910 1(1.401298e-45), 0(0.000000e+00) ; 00000001 00000000 MOV T12.Z, T11.W, ; 00000C0B 41801910 SETE_INT * T12.W, T12.W, 0.0, BS:VEC_120/SCL_212 ; 801F0C0C 61883A10 PRED_SETNE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00004504 ALU clause starting at 418: ; SETGE_INT * T12.W, T10.Z, T5.Y, ; 8080A80A 61803C10 MOV T14.X, literal.x, ; 000000FD 01C01910 MOV T13.Y, literal.y, ; 000004FD 21A01910 SETE_INT * T12.W, PV.W, 0.0, ; 801F0CFE 61803A10 1(1.401298e-45), 0(0.000000e+00) ; 00000001 00000000 PRED_SETNE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00004504 ALU clause starting at 424: ; SETGT_INT * T11.W, 0.0, T1.Y, ; 808020F8 61603B10 ADD_INT * T12.W, T1.Y, PV.W, ; 819FC401 61803410 XOR_INT * T12.W, PV.W, T11.W, ; 81816CFE 61803210 RECIP_UINT * T11.Z, PV.W, ; 80000CFE 41607810 MULLO_INT * T12.Y, PS, T12.W, ; 818180FF 21807310 SUB_INT T13.W, 0.0, PS, ; 001FE0F8 61A03510 MULHI * T13.X, T11.Z, T12.W, ; 8181880B 01A07610 CNDE_INT T13.W, PS, PV.W, T12.Y, ; 019FC0FF 61A3840C ADD_INT * T14.W, T8.W, T10.Z, ; 81014C08 61C03410 SETGT_INT T15.W, 0.0, PS, ; 001FE0F8 61E03B10 MULHI * T12.Y, PV.W, T11.Z, ; 81016CFE 21807610 ADD_INT T13.Z, T14.W, PV.W, ; 019FCC0E 41A03410 SUB_INT T13.W, T11.Z, PS, ; 001FE80B 61A03510 ADD_INT * T16.W, T11.Z, PS, ; 801FE80B 62003410 CNDE_INT T13.W, T13.X, PS, PV.W, ; 001FE00D 61A38CFE XOR_INT * T16.W, PV.Z, T15.W, ; 8181E8FE 62003210 MULHI * T11.Z, PV.W, PS, ; 801FECFE 41607610 MULLO_INT * T12.Y, PS, T12.W, ; 818180FF 21807310 SUB_INT * T13.W, T16.W, PS, ; 801FEC10 61A03510 SETGE_UINT T13.Z, PV.W, T12.W, ; 01818CFE 41A03F10 SETGE_UINT T12.W, T16.W, T12.Y, ; 00818C10 61803F10 INT_TO_FLT * T12.Y, T14.W, ; 80000C0E 21806C10 MUL_IEEE T14.Z, PS, T9.Z, ; 010120FF 41C00210 AND_INT T13.W, PV.Z, PV.W, ; 019FC8FE 61A03010 ADD_INT * T14.W, T11.Z, 1, ; 801F480B 61C03410 CNDE_INT T13.Z, PV.W, T11.Z, PS, ; 01016CFE 41A380FF ADD_INT T13.W, T11.Z, literal.x, ; 001FA80B 61A03410 FRACT * T14.W, PV.Z, ; 800008FE 61C01010 -1(-nan), 0(0.000000e+00) ; FFFFFFFF 00000000 MUL_IEEE T11.Z, T9.Y, PS, ; 001FE409 41600210 CNDE_INT T12.W, T12.W, PV.W, PV.Z, ; 019FCC0C 618388FE XOR_INT * T11.W, T15.W, T11.W, ; 81816C0F 61603210 ADD_INT T12.W, PV.W, PS, ; 001FECFE 61803410 FLT_TO_INT * T11.Z, PV.Z, ; 800008FE 41606B10 ADD_INT T13.W, T9.X, PS, ; 001FE009 61A03410 XOR_INT * T11.W, PV.W, T11.W, ; 81816CFE 61603210 ADD_INT T11.W, T8.Z, PS, ; 001FE808 61603410 INT_TO_FLT * T11.Z, PV.W, ; 80000CFE 41606C10 ADD T12.W, PS, 0.5, ; 001F80FF 61800010 INT_TO_FLT * T11.Z, PV.W, ; 80000CFE 41606C10 MUL_IEEE T13.X, PV.W, T8.Y, ; 00810CFE 01A00210 ADD * T11.W, PS, 0.5, ; 801F80FF 61600010 MUL_IEEE * T13.Y, PV.W, T8.X, ; 80010CFE 21A00210 ALU clause starting at 467: ; MUL_IEEE * T11.W, T13.W, literal.x, ; 801FAC0D 61600210 1132462079(2.560000e+02), 0(0.000000e+00) ; 437FFFFF 00000000 FLT_TO_INT * T11.Z, PV.W, ; 80000CFE 41606B10 INT_TO_FLT * T11.W, PS, ; 800000FF 61606C10 MUL_IEEE T11.W, PS, literal.x, ; 001FA0FF 61600210 ASHR * T12.W, T11.Z, literal.y, ; 809FA80B 61807010 1031798784(6.250000e-02), 31(4.344025e-44) ; 3D800000 0000001F FRACT * T11.W, PV.W, ; 80000CFE 61601010 MUL_IEEE T11.W, PV.W, literal.x, ; 001FACFE 61600210 LSHR * T12.W, T12.W, literal.y, ; 809FAC0C 61807110 1098907648(1.600000e+01), 28(3.923636e-44) ; 41800000 0000001C ADD_INT T12.W, T11.Z, PS, ; 001FE80B 61803410 FLT_TO_INT * T11.Z, PV.W, ; 80000CFE 41606B10 ASHR T11.W, PV.W, literal.x, ; 001FACFE 61607010 INT_TO_FLT * T11.Z, PS, ; 800000FF 41606C10 4(5.605194e-45), 0(0.000000e+00) ; 00000004 00000000 INT_TO_FLT * T11.W, PV.W, ; 80000CFE 61606C10 ADD T11.W, PS, T13.Y, ; 0081A0FF 61600010 ADD * T12.W, T11.Z, T13.Z, ; 8101A80B 61800010 MOV T12.Y, literal.x, ; 000000FD 21801910 MUL_IEEE T11.Z, PS, literal.y, ; 009FA0FF 41600210 MUL_IEEE T11.W, PV.W, literal.y, ; 009FACFE 61600210 SETE_DX10 * T12.W, T13.X, 0.0, ; 801F000D 61800C10 1315859240(1.000000e+09), 1031798784(6.250000e-02) ; 4E6E6B28 3D800000 PRED_SETNE_INT * Pred,PredicateBit (MASKED), PS, 0.0, ; 801F00FF 00004508 MUL_IEEE * T12.W, T13.X, literal.x, Pred_sel_zero ; C01FA00D 61800210 1132462079(2.560000e+02), 0(0.000000e+00) ; 437FFFFF 00000000 FLT_TO_INT * T12.Y, T12.W, Pred_sel_zero ; C0000C0C 21806B10 ADD_INT * T12.W, T12.Y, literal.x, Pred_sel_zero ; C01FA40C 61803410 -128(-nan), 0(0.000000e+00) ; FFFFFF80 00000000 INT_TO_FLT * T12.Y, T12.W, Pred_sel_zero ; C0000C0C 21806C10 MUL_IEEE * T12.Y, T12.Y, literal.x, Pred_sel_zero ; C01FA40C 21800210 998310404(3.937008e-03), 0(0.000000e+00) ; 3B810204 00000000 SETGE_DX10 * T12.W, |T12.Y|, literal.x, ; 801FA40C 61800E11 1307470632(5.000000e+08), 0(0.000000e+00) ; 4DEE6B28 00000000 MOV T14.X, literal.x, ; 000000FD 01C01910 MUL_IEEE T11.Z, T11.Z, T10.Y, ; 0081480B 41600210 SETE_INT T12.W, PV.W, 0.0, ; 001F0CFE 61803A10 MUL_IEEE * T11.W, T11.W, T10.X, ; 80014C0B 61600210 1(1.401298e-45), 0(0.000000e+00) ; 00000001 00000000 PRED_SETNE_INT * Pred,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00004508 MOV T14.X, literal.x, Pred_sel_zero ; 400000FD 01C01910 ADD_INT * T13.X, T10.Z, 1, Pred_sel_zero ; C01F480A 01A03410 0(0.000000e+00), 0(0.000000e+00) ; 00000000 00000000 ALU clause starting at 511: ; MOV * T13.Y, T14.X, ; 8000000E 21A01910 ALU clause starting at 512: ; LSHL * T12.W, T14.X, literal.x, ; 801FA00E 61807210 31(4.344025e-44), 0(0.000000e+00) ; 0000001F 00000000 ASHR * T12.W, PV.W, literal.x, ; 801FACFE 61807010 31(4.344025e-44), 0(0.000000e+00) ; 0000001F 00000000 PRED_SETNE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00004504 ALU clause starting at 517: ; MOV T12.W, literal.x, ; 000000FD 61801910 SETNE_INT * T13.W, T13.Y, 1, ; 801F440D 61A03D10 1(1.401298e-45), 0(0.000000e+00) ; 00000001 00000000 PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PS, 0.0, ; 801F00FF 00004204 ALU clause starting at 521: ; MUL_IEEE * T12.W, T12.Y, T12.Y, ; 8081840C 61800210 ADD T13.W, -PV.W, 1.0, ; 001F3CFE 61A00010 ADD * T12.W, T12.Y, T12.Y, ; 8081840C 61800010 RECIP_IEEE * T13.Z, PV.W, ; 80000CFE 41A06610 ADD T13.X, T0.X, -T12.Z, ; 03018000 01A00010 MUL_IEEE * T15.Y, T12.W, PS, ; 801FEC0C 21E00210 MOV T15.X, PV.Y, ; 000004FE 01E01910 ADD T13.Y, T0.Y, -T12.X, ; 02018400 21A00010 ADD * T14.X, T11.W, -T12.Z, ; 83018C0B 01C00010 ADD * T14.Y, T11.Z, -T12.X, ; 8201880B 21C00010 DOT4 T16.X (MASKED), T14.X, -T15.X, ; 0201E00E 02005000 DOT4 T16.Y, T14.Y, 1.0, ; 001F240E 22005010 DOT4 T16.Z (MASKED), 0.0, 0.0, ; 001F00F8 42005000 DOT4 * T16.W (MASKED), 0.0, 0.0, ; 801F00F8 62005000 DOT4 T15.X, T14.X, 1.0, ; 001F200E 01E05010 DOT4 T15.Y (MASKED), T14.Y, T15.Y, ; 0081E40E 21E05000 DOT4 T15.Z (MASKED), 0.0, 0.0, ; 001F00F8 41E05000 DOT4 * T15.W (MASKED), 0.0, 0.0, ; 801F00F8 61E05000 DOT4 T13.X (MASKED), T13.X, T15.X, ; 0001E00D 01A05000 DOT4 T13.Y (MASKED), T13.Y, T16.Y, ; 0082040D 21A05000 DOT4 T13.Z (MASKED), 0.0, 0.0, ; 001F00F8 41A05000 DOT4 * T13.W, 0.0, 0.0, ; 801F00F8 61A05010 SETGE_DX10 T13.W, PV.X, 0.0, ; 001F00FE 61A00E10 MOV * T14.W, literal.x, ; 800000FD 61C01910 0(0.000000e+00), 0(0.000000e+00) ; 00000000 00000000 SETE_INT * T13.W, PV.W, 0.0, ; 801F0CFE 61A03A10 PRED_SETNE_INT * Pred,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00004508 ADD T15.X, T0.X, -T11.W, Pred_sel_zero ; 43816000 01E00010 ADD T16.Y, T0.Y, -T11.Z, Pred_sel_zero ; 43016400 22000010 MOV * T16.X, T15.Y, Pred_sel_zero ; C000040F 02001910 MOV * T15.Y, -T15.Y, Pred_sel_zero ; C000140F 21E01910 DOT4 T17.X (MASKED), T14.X, T16.X, Pred_sel_zero ; 4002000E 02205000 DOT4 T17.Y, T14.Y, 1.0, Pred_sel_zero ; 401F240E 22205010 DOT4 T17.Z (MASKED), 0.0, 0.0, Pred_sel_zero ; 401F00F8 42205000 DOT4 * T17.W (MASKED), 0.0, 0.0, Pred_sel_zero ; C01F00F8 62205000 DOT4 T16.X, T14.X, 1.0, Pred_sel_zero ; 401F200E 02005010 DOT4 T16.Y (MASKED), T14.Y, T15.Y, Pred_sel_zero ; 4081E40E 22005000 DOT4 T16.Z (MASKED), 0.0, 0.0, Pred_sel_zero ; 401F00F8 42005000 DOT4 * T16.W (MASKED), 0.0, 0.0, Pred_sel_zero ; C01F00F8 62005000 DOT4 T13.X (MASKED), T15.X, T16.X, Pred_sel_zero ; 4002000F 01A05000 DOT4 T13.Y (MASKED), T16.Y, T17.Y, Pred_sel_zero ; 40822410 21A05000 DOT4 T13.Z (MASKED), 0.0, 0.0, Pred_sel_zero ; 401F00F8 41A05000 DOT4 * T13.W, 0.0, 0.0, Pred_sel_zero ; C01F00F8 61A05010 SETGE_DX10 * T14.W, 0.0, T13.W, Pred_sel_zero ; C181A0F8 61C00E10 MOV T13.W, literal.x, ; 000000FD 61A01910 SETE_INT * T14.W, T14.W, 0.0, ; 801F0C0E 61C03A10 1(1.401298e-45), 0(0.000000e+00) ; 00000001 00000000 PRED_SETNE_INT * ExecMask,PredicateBit (MASKED), PS, 0.0, ; 801F00FF 00004504 ALU clause starting at 569: ; ADD T15.X, T0.X, -T11.W, ; 03816000 01E00010 ADD * T16.Y, T0.Y, -T11.Z, ; 83016400 22000010 DOT4 T13.X (MASKED), T15.X, T15.X, ; 0001E00F 01A05000 DOT4 T13.Y (MASKED), T16.Y, T16.Y, ; 00820410 21A05000 DOT4 T13.Z (MASKED), 0.0, 0.0, ; 001F00F8 41A05000 DOT4 * T13.W, 0.0, 0.0, ; 801F00F8 61A05010 RECIPSQRT_CLAMPED * T14.Z, PV.X, ; 800000FE 41C06710 DOT4 T14.X (MASKED), T13.X, T13.X, ; 0001A00D 01C05000 DOT4 T14.Y (MASKED), T13.Y, T13.Y, ; 0081A40D 21C05000 DOT4 T14.Z (MASKED), 0.0, 0.0, ; 001F00F8 41C05000 DOT4 * T14.W, 0.0, 0.0, ; 801F00F8 61C05010 RECIPSQRT_CLAMPED * T15.Y, PV.X, ; 800000FE 21E06710 MUL_IEEE T15.W, PS, T14.W, BS:VEC_021/SCL_122 ; 0181C0FF 61E40210 MUL_IEEE * T16.W, T14.Z, T13.W, ; 8181A80E 62000210 CNDGE T14.Z, -T13.W, 0.0, PS, ; 001F1C0D 41C340FF CNDGE * T13.W, -T14.W, 0.0, PV.W, BS:VEC_120/SCL_212 ; 801F1C0E 61AB4CFE MIN T15.Y, PV.Z, PV.W, ; 019FC8FE 21E00410 MOV T14.Z, T12.X, ; 0000000C 41C01910 MOV * T15.Z, T11.W, ; 80000C0B 41E01910 SETGT_DX10 T15.W, T6.Y, PV.Y, ; 009FC406 61E00D10 MOV * T13.W, literal.x, ; 800000FD 61A01910 0(0.000000e+00), 0(0.000000e+00) ; 00000000 00000000 MOV T16.X, T11.Z, ; 0000080B 02001910 MOV T16.Z, T12.Y, ; 0000040C 42001910 MOV T14.W, PS, ; 000000FF 61C01910 SETE_INT * T16.W, PV.W, 0.0, ; 801F0CFE 62003A10 MOV * T15.W, T12.Z, ; 8000080C 61E01910 PRED_SETNE_INT * ExecMask,PredicateBit (MASKED), T16.W, 0.0, ; 801F0C10 00004504 ALU clause starting at 597: ; SETE_DX10 T14.W, T10.W, 0.0, ; 001F0C0A 61C00C10 SETE_DX10 * T15.W, T15.Y, T6.Y, ; 8080C40F 61E00C10 AND_INT * T14.W, PV.W, PS, ; 801FECFE 61C03010 AND_INT * T14.W, PV.W, 1, ; 801F4CFE 61C03010 MOV T15.Y, T6.Y, ; 00000406 21E01910 SETE_INT T15.W, PV.W, 0.0, ; 001F0CFE 61E03A10 MOV * T14.W, T10.W, ; 80000C0A 61C01910 PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00004204 ALU clause starting at 605: ; MUL_IEEE T14.W, T7.X, 0.5, ; 001F8007 61C00210 MUL_IEEE * T15.W, T6.Z, 0.5, ; 801F8806 61E00210 MULADD_IEEE T15.W, T7.Z, 0.5, PS, ; 001F8807 61E280FF MULADD_IEEE * T14.W, T7.Y, 0.5, PV.W, BS:VEC_021/SCL_122 ; 801F8407 61C68CFE ADD T16.X, T0.X, -PS, ; 021FE000 02000010 ADD T15.Y, T0.Y, -PV.W, ; 039FC400 21E00010 ADD * T17.X, T7.Y, -PS, ; 821FE407 02200010 ADD T17.Y, T7.Z, -T15.W, ; 0381E807 22200010 MUL_IEEE * T14.W, T9.W, T9.W, ; 81812C09 61C00210 ADD * T14.W, -PV.W, 1.0, ; 801F3CFE 61C00010 DOT4 T14.X (MASKED), T16.X, T17.X, ; 00022010 01C05000 DOT4 T14.Y (MASKED), T15.Y, T17.Y, ; 0082240F 21C05000 DOT4 T14.Z, 0.0, 0.0, ; 001F00F8 41C05010 DOT4 * T14.W (MASKED), 0.0, 0.0, ; 801F00F8 61C05000 SETGT_DX10 T14.Z, 0.0, PV.X, ; 001FC0F8 41C00D10 ADD T15.W, T9.W, T9.W, ; 01812C09 61E00010 RECIP_IEEE * T14.W, T14.W, ; 80000C0E 61C06610 MUL_IEEE T16.X, PV.W, PS, ; 001FECFE 02000210 MOV T14.W, literal.x, ; 000000FD 61C01910 SETE_INT * T15.W, PV.Z, 0.0, ; 801F08FE 61E03A10 1(1.401298e-45), 0(0.000000e+00) ; 00000001 00000000 PRED_SETNE_INT * Pred,PredicateBit (MASKED), PS, 0.0, ; 801F00FF 00004508 MOV T15.Y, T16.X, Pred_sel_one ; 60000010 21E01910 ADD * T17.Y, T7.Z, -T6.Z, Pred_sel_one ; E300C807 22200010 ADD T17.X, T7.Y, -T7.X, Pred_sel_one ; 6200E407 02200010 MOV * T18.Y, literal.x, Pred_sel_one ; E00000FD 22401910 -1082130432(-1.000000e+00), 0(0.000000e+00) ; BF800000 00000000 DOT4 T18.X, T17.X, -T16.X, Pred_sel_one ; 62020011 02405010 DOT4 T18.Y (MASKED), T17.Y, T18.Y, Pred_sel_one ; 60824411 22405000 DOT4 T18.Z (MASKED), 0.0, 0.0, Pred_sel_one ; 601F00F8 42405000 DOT4 * T18.W (MASKED), 0.0, 0.0, Pred_sel_one ; E01F00F8 62405000 DOT4 T15.X (MASKED), T17.X, 1.0, Pred_sel_one ; 601F2011 01E05000 DOT4 T15.Y, T17.Y, -T15.Y, Pred_sel_one ; 6281E411 21E05010 DOT4 T15.Z (MASKED), 0.0, 0.0, Pred_sel_one ; 601F00F8 41E05000 DOT4 * T15.W (MASKED), 0.0, 0.0, Pred_sel_one ; E01F00F8 61E05000 DOT4 T14.X (MASKED), T18.X, T18.X, Pred_sel_one ; 60024012 01C05000 DOT4 T14.Y (MASKED), T15.Y, T15.Y, Pred_sel_one ; 6081E40F 21C05000 DOT4 T14.Z, 0.0, 0.0, Pred_sel_one ; 601F00F8 41C05010 DOT4 * T14.W (MASKED), 0.0, 0.0, Pred_sel_one ; E01F00F8 61C05000 RECIPSQRT_CLAMPED * T14.Z, T14.Z, Pred_sel_one ; E000080E 41C06710 MUL_IEEE T17.X, T18.X, T14.Z, Pred_sel_one ; 6101C012 02200210 MUL_IEEE T15.Y, T15.Y, T14.Z, Pred_sel_one ; 6101C40F 21E00210 ADD * T18.X, T0.X, -T7.Y, Pred_sel_one ; E280E000 02400010 ADD T17.Y, T0.Y, -T7.Z, Pred_sel_one ; 6300E400 22200010 MOV * T14.W, literal.x, Pred_sel_one ; E00000FD 61C01910 0(0.000000e+00), 0(0.000000e+00) ; 00000000 00000000 DOT4 T14.X (MASKED), T18.X, T17.X, Pred_sel_one ; 60022012 01C05000 DOT4 T14.Y (MASKED), T17.Y, T15.Y, Pred_sel_one ; 6081E411 21C05000 DOT4 T14.Z, 0.0, 0.0, Pred_sel_one ; 601F00F8 41C05010 DOT4 * T14.W (MASKED), 0.0, 0.0, Pred_sel_one ; E01F00F8 61C05000 ALU clause starting at 655: ; SETNE_INT * T14.W, T14.W, 1, ; 801F4C0E 61C03D10 PRED_SETNE_INT * Pred,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00004508 MOV T15.Y, T16.X, Pred_sel_zero ; 40000010 21E01910 ADD * T17.Y, T7.Z, -T6.Z, Pred_sel_zero ; C300C807 22200010 ADD T17.X, T7.Y, -T7.X, Pred_sel_zero ; 4200E407 02200010 MOV * T18.Y, literal.x, Pred_sel_zero ; C00000FD 22401910 -1082130432(-1.000000e+00), 0(0.000000e+00) ; BF800000 00000000 DOT4 T16.X, T17.X, T16.X, Pred_sel_zero ; 40020011 02005010 DOT4 T16.Y (MASKED), T17.Y, T18.Y, Pred_sel_zero ; 40824411 22005000 DOT4 T16.Z (MASKED), 0.0, 0.0, Pred_sel_zero ; 401F00F8 42005000 DOT4 * T16.W (MASKED), 0.0, 0.0, Pred_sel_zero ; C01F00F8 62005000 DOT4 T15.X (MASKED), T17.X, 1.0, Pred_sel_zero ; 401F2011 01E05000 DOT4 T15.Y, T17.Y, T15.Y, Pred_sel_zero ; 4081E411 21E05010 DOT4 T15.Z (MASKED), 0.0, 0.0, Pred_sel_zero ; 401F00F8 41E05000 DOT4 * T15.W (MASKED), 0.0, 0.0, Pred_sel_zero ; C01F00F8 61E05000 DOT4 T14.X (MASKED), T16.X, T16.X, Pred_sel_zero ; 40020010 01C05000 DOT4 T14.Y (MASKED), T15.Y, T15.Y, Pred_sel_zero ; 4081E40F 21C05000 DOT4 T14.Z, 0.0, 0.0, Pred_sel_zero ; 401F00F8 41C05010 DOT4 * T14.W (MASKED), 0.0, 0.0, Pred_sel_zero ; C01F00F8 61C05000 RECIPSQRT_CLAMPED * T14.Z, T14.Z, Pred_sel_zero ; C000080E 41C06710 MUL_IEEE T16.X, T16.X, T14.Z, Pred_sel_zero ; 4101C010 02000210 MUL_IEEE T15.Y, T15.Y, T14.Z, Pred_sel_zero ; 4101C40F 21E00210 ADD * T17.X, T0.X, -T7.X, Pred_sel_zero ; C200E000 02200010 ADD * T17.Y, T0.Y, -T6.Z, Pred_sel_zero ; C300C400 22200010 DOT4 T14.X (MASKED), T17.X, T16.X, Pred_sel_zero ; 40020011 01C05000 DOT4 T14.Y (MASKED), T17.Y, T15.Y, Pred_sel_zero ; 4081E411 21C05000 DOT4 T14.Z, 0.0, 0.0, Pred_sel_zero ; 401F00F8 41C05010 DOT4 * T14.W (MASKED), 0.0, 0.0, Pred_sel_zero ; C01F00F8 61C05000 MUL_IEEE T14.W, T12.Z, 0.5, ; 001F880C 61C00210 MUL_IEEE * T15.W, T12.X, 0.5, ; 801F800C 61E00210 MULADD_IEEE T15.W, T11.Z, 0.5, PS, ; 001F880B 61E280FF MULADD_IEEE * T14.W, T11.W, 0.5, PV.W, BS:VEC_021/SCL_122 ; 801F8C0B 61C68CFE ADD T16.X, T0.X, -PS, ; 021FE000 02000010 ADD T15.Y, T0.Y, -PV.W, ; 039FC400 21E00010 ADD * T17.X, T11.W, -PS, ; 821FEC0B 02200010 ADD * T17.Y, T11.Z, -T15.W, ; 8381E80B 22200010 DOT4 T14.X (MASKED), T16.X, T17.X, ; 00022010 01C05000 DOT4 T14.Y (MASKED), T15.Y, T17.Y, ; 0082240F 21C05000 DOT4 T14.Z (MASKED), 0.0, 0.0, ; 001F00F8 41C05000 DOT4 * T14.W, 0.0, 0.0, ; 801F00F8 61C05010 SETGT_DX10 * T14.W, 0.0, PV.X, ; 801FC0F8 61C00D10 MUL_IEEE T16.X, T12.W, T13.Z, ; 0101AC0C 02000210 MOV T15.W, literal.x, ; 000000FD 61E01910 SETE_INT * T14.W, PV.W, 0.0, ; 801F0CFE 61C03A10 1(1.401298e-45), 0(0.000000e+00) ; 00000001 00000000 PRED_SETNE_INT * Pred,PredicateBit (MASKED), PS, 0.0, ; 801F00FF 00004508 MOV T15.Y, T16.X, Pred_sel_one ; 60000010 21E01910 MOV * T17.Y, literal.x, Pred_sel_one ; E00000FD 22201910 -1082130432(-1.000000e+00), 0(0.000000e+00) ; BF800000 00000000 DOT4 T17.X, T14.X, -T16.X, Pred_sel_one ; 6202000E 02205010 DOT4 T17.Y (MASKED), T14.Y, T17.Y, Pred_sel_one ; 6082240E 22205000 DOT4 T17.Z (MASKED), 0.0, 0.0, Pred_sel_one ; 601F00F8 42205000 DOT4 * T17.W (MASKED), 0.0, 0.0, Pred_sel_one ; E01F00F8 62205000 DOT4 T15.X (MASKED), T14.X, 1.0, Pred_sel_one ; 601F200E 01E05000 DOT4 T15.Y, T14.Y, -T15.Y, Pred_sel_one ; 6281E40E 21E05010 DOT4 T15.Z (MASKED), 0.0, 0.0, Pred_sel_one ; 601F00F8 41E05000 DOT4 * T15.W (MASKED), 0.0, 0.0, Pred_sel_one ; E01F00F8 61E05000 DOT4 T14.X (MASKED), T17.X, T17.X, Pred_sel_one ; 60022011 01C05000 DOT4 T14.Y (MASKED), T15.Y, T15.Y, Pred_sel_one ; 6081E40F 21C05000 DOT4 T14.Z (MASKED), 0.0, 0.0, Pred_sel_one ; 601F00F8 41C05000 DOT4 * T14.W, 0.0, 0.0, Pred_sel_one ; E01F00F8 61C05010 RECIPSQRT_CLAMPED * T14.W, T14.W, Pred_sel_one ; E0000C0E 61C06710 MUL_IEEE T17.X, T17.X, T14.W, Pred_sel_one ; 6181C011 02200210 MUL_IEEE T15.Y, T15.Y, T14.W, Pred_sel_one ; 6181C40F 21E00210 MOV * T15.W, literal.x, Pred_sel_one ; E00000FD 61E01910 0(0.000000e+00), 0(0.000000e+00) ; 00000000 00000000 DOT4 T14.X (MASKED), T15.X, T17.X, Pred_sel_one ; 6002200F 01C05000 DOT4 T14.Y (MASKED), T16.Y, T15.Y, Pred_sel_one ; 6081E410 21C05000 DOT4 T14.Z (MASKED), 0.0, 0.0, Pred_sel_one ; 601F00F8 41C05000 DOT4 * T14.W, 0.0, 0.0, Pred_sel_one ; E01F00F8 61C05010 ALU clause starting at 725: ; SETNE_INT * T15.W, T15.W, 1, ; 801F4C0F 61E03D10 PRED_SETNE_INT * Pred,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00004508 MOV T15.Y, T16.X, Pred_sel_zero ; 40000010 21E01910 MOV * T16.Y, literal.x, Pred_sel_zero ; C00000FD 22001910 -1082130432(-1.000000e+00), 0(0.000000e+00) ; BF800000 00000000 DOT4 T15.X, T14.X, T16.X, Pred_sel_zero ; 4002000E 01E05010 DOT4 T15.Y (MASKED), T14.Y, T16.Y, Pred_sel_zero ; 4082040E 21E05000 DOT4 T15.Z (MASKED), 0.0, 0.0, Pred_sel_zero ; 401F00F8 41E05000 DOT4 * T15.W (MASKED), 0.0, 0.0, Pred_sel_zero ; C01F00F8 61E05000 DOT4 T15.X (MASKED), T14.X, 1.0, Pred_sel_zero ; 401F200E 01E05000 DOT4 T15.Y, T14.Y, T15.Y, Pred_sel_zero ; 4081E40E 21E05010 DOT4 T15.Z (MASKED), 0.0, 0.0, Pred_sel_zero ; 401F00F8 41E05000 DOT4 * T15.W (MASKED), 0.0, 0.0, Pred_sel_zero ; C01F00F8 61E05000 DOT4 T14.X (MASKED), T15.X, T15.X, Pred_sel_zero ; 4001E00F 01C05000 DOT4 T14.Y (MASKED), T15.Y, T15.Y, Pred_sel_zero ; 4081E40F 21C05000 DOT4 T14.Z (MASKED), 0.0, 0.0, Pred_sel_zero ; 401F00F8 41C05000 DOT4 * T14.W, 0.0, 0.0, Pred_sel_zero ; C01F00F8 61C05010 RECIPSQRT_CLAMPED * T14.W, T14.W, Pred_sel_zero ; C0000C0E 61C06710 MUL_IEEE T15.X, T15.X, T14.W, Pred_sel_zero ; 4181C00F 01E00210 MUL_IEEE * T15.Y, T15.Y, T14.W, Pred_sel_zero ; C181C40F 21E00210 DOT4 T14.X (MASKED), T13.X, T15.X, Pred_sel_zero ; 4001E00D 01C05000 DOT4 T14.Y (MASKED), T13.Y, T15.Y, Pred_sel_zero ; 4081E40D 21C05000 DOT4 T14.Z (MASKED), 0.0, 0.0, Pred_sel_zero ; 401F00F8 41C05000 DOT4 * T14.W, 0.0, 0.0, Pred_sel_zero ; C01F00F8 61C05010 SETGE_DX10 * T15.W, |T14.Z|, |T14.W|, ; 8181C80E 61E00E13 CNDE_INT * T14.W, PV.W, T14.W, T14.Z, ; 8181CCFE 61C3880E SETGE * T15.W, 0.0, PV.W, ; 819FC0F8 61E00A10 CNDE * T15.W, PV.W, 1.0, T14.W, ; 801F2CFE 61E30C0E SETGT * T16.W, 0.0, PV.W, ; 819FC0F8 62000910 MOV T15.Y, |T14.W|, ; 00000C0E 21E01911 CNDE * T14.W, PV.W, T15.W, literal.x, ; 8181ECFE 61C300FD -1082130432(-1.000000e+00), 0(0.000000e+00) ; BF800000 00000000 ALU clause starting at 757: ; MOV T14.Z, T6.Z, ; 00000806 41C01910 MOV * T15.Z, T7.Y, ; 80000407 41E01910 MOV T16.X, T7.Z, ; 00000807 02001910 MOV T16.Z, T9.W, ; 00000C09 42001910 MOV * T15.W, T7.X, ; 80000007 61E01910 ALU clause starting at 762: ; SETNE_INT * T13.W, T13.W, 1, ; 801F4C0D 61A03D10 PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00004204 ALU clause starting at 764: ; SETGE_DX10 T13.W, literal.x, |T12.Y|, ; 008180FD 61A00E12 MOV * T14.W, literal.y, ; 800004FD 61C01910 1036831949(1.000000e-01), 1(1.401298e-45) ; 3DCCCCCD 00000001 SETE_INT * T13.W, PV.W, 0.0, ; 801F0CFE 61A03A10 PRED_SETE_INT * Pred,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00004208 MUL_IEEE * T13.W, T13.Z, literal.x, Pred_sel_zero ; C01FA80D 61A00210 1082130432(4.000000e+00), 0(0.000000e+00) ; 40800000 00000000 MUL_IEEE * T13.W, T12.Y, T13.W, Pred_sel_zero ; C181A40C 61A00210 MUL_IEEE T13.Z, T12.X, 0.5, Pred_sel_zero ; 401F800C 41A00210 MUL_IEEE T14.W, T12.Z, 0.5, Pred_sel_zero ; 401F880C 61C00210 RECIP_IEEE * T13.W, T13.W, Pred_sel_zero ; C0000C0D 61A06610 MUL_IEEE T14.Z, T14.Y, T13.W, Pred_sel_zero ; 4181A40E 41C00210 MULADD_IEEE T14.W, T11.W, 0.5, T14.W, Pred_sel_zero ; 401F8C0B 61C28C0E MULADD_IEEE * T15.W, T11.Z, 0.5, T13.Z, Pred_sel_zeroBS:VEC_021/SCL_122 ; C01F880B 61E6880D MULADD_IEEE T13.W, T14.X, T13.W, T15.W, Pred_sel_zeroBS:VEC_201 ; 4181A00E 61B28C0F ADD * T14.W, T14.W, -T14.Z, Pred_sel_zero ; C301CC0E 61C00010 ADD T15.X, T0.X, -T14.W, Pred_sel_zero ; 4381C000 01E00010 ADD T15.Y, T0.Y, -T13.W, Pred_sel_zero BS:VEC_021/SCL_122 ; 4381A400 21E40010 ADD * T16.X, T12.Z, -T14.W, Pred_sel_zero ; C381C80C 02000010 ADD * T16.Y, T12.X, -T13.W, Pred_sel_zero ; C381A00C 22000010 DOT4 T12.X, T16.X, T16.X, Pred_sel_zero ; 40020010 01805010 DOT4 T12.Y (MASKED), T16.Y, T16.Y, Pred_sel_zero ; 40820410 21805000 DOT4 T12.Z (MASKED), 0.0, 0.0, Pred_sel_zero ; 401F00F8 41805000 DOT4 * T12.W (MASKED), 0.0, 0.0, Pred_sel_zero ; C01F00F8 61805000 RECIPSQRT_CLAMPED * T12.Z, T12.X, Pred_sel_zero ; C000000C 41806710 DOT4 T13.X (MASKED), T15.X, T15.X, Pred_sel_zero ; 4001E00F 01A05000 DOT4 T13.Y (MASKED), T15.Y, T15.Y, Pred_sel_zero ; 4081E40F 21A05000 DOT4 T13.Z, 0.0, 0.0, Pred_sel_zero ; 401F00F8 41A05010 DOT4 * T13.W (MASKED), 0.0, 0.0, Pred_sel_zero ; C01F00F8 61A05000 SETGE T13.W, 0.0, T12.Y, Pred_sel_zero ; 408180F8 61A00A10 RECIPSQRT_CLAMPED * T14.Z, T13.Z, Pred_sel_zero ; C000080D 41C06710 CNDE T15.Z, T13.W, 1.0, T12.Y, Pred_sel_zero ; 401F2C0D 41E3040C MUL_IEEE T13.W, T14.Z, T13.Z, Pred_sel_zero ; 4101A80E 61A00210 MUL_IEEE * T14.W, T12.Z, T12.X, Pred_sel_zero ; C001880C 61C00210 CNDGE T12.Z, -T12.X, 0.0, T14.W, Pred_sel_zero ; 401F100C 41834C0E CNDGE T13.W, -T13.Z, 0.0, T13.W, Pred_sel_zeroBS:VEC_021/SCL_122 ; 401F180D 61A74C0D SETGT * T14.W, 0.0, T15.Z, Pred_sel_zero ; C101E0F8 61C00910 ADD T13.W, T12.Z, -T13.W, Pred_sel_zero ; 4381A80C 61A00010 CNDE * T14.W, T14.W, T15.Z, literal.x, Pred_sel_zero ; C101EC0E 61C300FD -1082130432(-1.000000e+00), 0(0.000000e+00) ; BF800000 00000000 MUL_IEEE T13.W, T14.W, T13.W, Pred_sel_zero ; 4181AC0E 61A00210 MOV * T14.W, literal.x, Pred_sel_zero ; C00000FD 61C01910 0(0.000000e+00), 0(0.000000e+00) ; 00000000 00000000 ALU clause starting at 807: ; SETNE_INT * T14.W, T14.W, 1, ; 801F4C0E 61C03D10 PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00004204 ALU clause starting at 809: ; DOT4 T12.X, T14.X, T14.X, ; 0001C00E 01805010 DOT4 T12.Y (MASKED), T14.Y, T14.Y, ; 0081C40E 21805000 DOT4 T12.Z (MASKED), 0.0, 0.0, ; 001F00F8 41805000 DOT4 * T12.W (MASKED), 0.0, 0.0, ; 801F00F8 61805000 RECIPSQRT_CLAMPED * T12.X, PV.X, ; 800000FE 01806710 MUL_IEEE T15.X, T14.Y, PS, ; 001FE40E 01E00210 MUL_IEEE T14.Y, T14.X, PS, ; 001FE00E 21C00210 SETNE_DX10 * T14.W, T12.Y, 0.0, BS:VEC_120/SCL_212 ; 801F040C 61C80F10 DOT4 T13.X (MASKED), T13.X, -T15.X, ; 0201E00D 01A05000 DOT4 T13.Y (MASKED), T13.Y, T14.Y, ; 0081C40D 21A05000 DOT4 T13.Z (MASKED), 0.0, 0.0, ; 001F00F8 41A05000 DOT4 * T13.W, 0.0, 0.0, ; 801F00F8 61A05010 PRED_SETNE_INT * ExecMask,PredicateBit (MASKED), T14.W, 0.0, ; 801F0C0E 00004504 ALU clause starting at 822: ; MOV T12.X, T14.Y, ; 0000040E 01801910 MOV * T15.Y, T15.X, ; 8000000F 21E01910 DOT4 T12.X, T13.X, T12.X, ; 0001800D 01805010 DOT4 T12.Y (MASKED), T13.Y, T15.Y, ; 0081E40D 21805000 DOT4 T12.Z (MASKED), 0.0, 0.0, ; 001F00F8 41805000 DOT4 * T12.W (MASKED), 0.0, 0.0, ; 801F00F8 61805000 SETGT_DX10 T14.W, 0.0, PV.X, ; 001FC0F8 61C00D10 MOV * T15.W, literal.x, ; 800000FD 61E01910 1(1.401298e-45), 0(0.000000e+00) ; 00000001 00000000 SETE_INT * T14.W, PV.W, 0.0, ; 801F0CFE 61C03A10 PRED_SETNE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00004504 ALU clause starting at 833: ; ADD T14.X, T11.W, T11.Y, ; 00816C0B 01C00010 ADD T15.Y, T11.Z, T11.X, ; 0001680B 21E00010 MOV * T16.X, T14.Y, ; 8000040E 02001910 MOV * T14.Y, T15.X, ; 8000000F 21C01910 DOT4 T12.X (MASKED), T14.X, T16.X, ; 0002000E 01805000 DOT4 T12.Y (MASKED), T15.Y, T14.Y, ; 0081C40F 21805000 DOT4 T12.Z, 0.0, 0.0, ; 001F00F8 41805010 DOT4 * T12.W (MASKED), 0.0, 0.0, ; 801F00F8 61805000 SETGT_DX10 T14.W, 0.0, PV.X, ; 001FC0F8 61C00D10 MOV * T15.W, literal.x, ; 800000FD 61E01910 1(1.401298e-45), 0(0.000000e+00) ; 00000001 00000000 SETE_INT * T14.W, PV.W, 0.0, ; 801F0CFE 61C03A10 PRED_SETNE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00004504 ALU clause starting at 846: ; ADD T14.W, T12.X, T12.Z, ; 0101800C 61C00010 MUL_IEEE * T15.W, T12.X, T12.Z, ; 8101800C 61E00210 MUL_IEEE T12.W, T12.W, PS, ; 001FEC0C 61800210 RECIP_IEEE * T12.X, PV.W, ; 80000CFE 01806610 MUL_IEEE * T12.W, PV.W, PS, ; 801FECFE 61800210 MUL_IEEE * T14.W, PV.W, T13.W, ; 8181ACFE 61C00210 SETGT_DX10 T14.W, PV.W, 0.0, ; 001F0CFE 61C00D10 MOV * T15.W, literal.x, ; 800000FD 61E01910 1(1.401298e-45), 0(0.000000e+00) ; 00000001 00000000 SETE_INT * T14.W, PV.W, 0.0, ; 801F0CFE 61C03A10 PRED_SETNE_INT * Pred,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00004508 MOV T15.W, literal.x, Pred_sel_one ; 600000FD 61E01910 ADD * T14.W, T13.W, T12.W, Pred_sel_one ; E1818C0D 61C00010 0(0.000000e+00), 0(0.000000e+00) ; 00000000 00000000 ALU clause starting at 860: ; SETNE_INT * T15.W, T15.W, 1, ; 801F4C0F 61E03D10 PRED_SETNE_INT * Pred,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00004508 ADD T12.X, T0.X, -T11.W, Pred_sel_zero ; 43816000 01800010 ADD * T14.Y, T0.Y, -T11.Z, Pred_sel_zero ; C3016400 21C00010 DOT4 T12.X, T12.X, T12.X, Pred_sel_zero ; 4001800C 01805010 DOT4 T12.Y (MASKED), T14.Y, T14.Y, Pred_sel_zero ; 4081C40E 21805000 DOT4 T12.Z (MASKED), 0.0, 0.0, Pred_sel_zero ; 401F00F8 41805000 DOT4 * T12.W (MASKED), 0.0, 0.0, Pred_sel_zero ; C01F00F8 61805000 RECIPSQRT_CLAMPED * T12.Z, T12.X, Pred_sel_zero ; C000000C 41806710 DOT4 T13.X (MASKED), T13.X, T13.X, Pred_sel_zero ; 4001A00D 01A05000 DOT4 T13.Y (MASKED), T13.Y, T13.Y, Pred_sel_zero ; 4081A40D 21A05000 DOT4 T13.Z, 0.0, 0.0, Pred_sel_zero ; 401F00F8 41A05010 DOT4 * T13.W (MASKED), 0.0, 0.0, Pred_sel_zero ; C01F00F8 61A05000 RECIPSQRT_CLAMPED * T14.X, T13.Z, Pred_sel_zero ; C000080D 01C06710 SETGE T14.Z, 0.0, T13.W, Pred_sel_zero ; 4181A0F8 41C00A10 MUL_IEEE T14.W, T14.X, T13.Z, Pred_sel_zero ; 4101A00E 61C00210 MUL_IEEE * T15.W, T12.Z, T12.X, Pred_sel_zero ; C001880C 61E00210 CNDGE T12.Z, -T12.X, 0.0, T15.W, Pred_sel_zeroBS:VEC_021/SCL_122 ; 401F100C 41874C0F CNDGE T14.W, -T13.Z, 0.0, T14.W, Pred_sel_zeroBS:VEC_210 ; 401F180D 61D74C0E CNDE * T15.W, T14.Z, 1.0, T13.W, Pred_sel_zeroBS:VEC_021/SCL_122 ; C01F280E 61E70C0D SETGT T13.Z, 0.0, T15.W, Pred_sel_zero ; 4181E0F8 41A00910 MIN * T14.W, T12.Z, T14.W, Pred_sel_zero BS:VEC_021/SCL_122 ; C181C80C 61C40410 ADD * T12.W, T13.W, T12.W, Pred_sel_zero ; C1818C0D 61800010 MIN T12.W, T14.W, |T12.W|, Pred_sel_zero BS:VEC_021/SCL_122 ; 41818C0E 61840412 CNDE * T14.W, T13.Z, T15.W, literal.x, Pred_sel_zero ; C181E80D 61C300FD -1082130432(-1.000000e+00), 0(0.000000e+00) ; BF800000 00000000 MUL_IEEE * T14.W, T14.W, T12.W, Pred_sel_zero ; C1818C0E 61C00210 MOV * T15.W, literal.x, ; 800000FD 61E01910 0(0.000000e+00), 0(0.000000e+00) ; 00000000 00000000 ALU clause starting at 889: ; SETNE_INT * T12.W, T15.W, 1, ; 801F4C0F 61803D10 PRED_SETNE_INT * Pred,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00004508 ADD T12.X, T0.X, -T11.W, Pred_sel_zero ; 43816000 01800010 ADD T14.Y, T0.Y, -T11.Z, Pred_sel_zero ; 43016400 21C00010 SETGE * T12.W, 0.0, T13.W, Pred_sel_zero BS:VEC_021/SCL_122 ; C181A0F8 61840A10 DOT4 T12.X, T12.X, T12.X, Pred_sel_zero ; 4001800C 01805010 DOT4 T12.Y (MASKED), T14.Y, T14.Y, Pred_sel_zero ; 4081C40E 21805000 DOT4 T12.Z (MASKED), 0.0, 0.0, Pred_sel_zero ; 401F00F8 41805000 DOT4 * T12.W (MASKED), 0.0, 0.0, Pred_sel_zero ; C01F00F8 61805000 CNDE T12.W, T12.W, 1.0, T13.W, Pred_sel_zero ; 401F2C0C 61830C0D RECIPSQRT_CLAMPED * T12.Z, T12.X, Pred_sel_zero ; C000000C 41806710 SETGT T14.W, 0.0, T12.W, Pred_sel_zero ; 418180F8 61C00910 MUL_IEEE * T15.W, T12.Z, T12.X, Pred_sel_zero ; C001880C 61E00210 CNDGE T15.W, -T12.X, 0.0, T15.W, Pred_sel_zeroBS:VEC_120/SCL_212 ; 401F100C 61EB4C0F CNDE * T12.W, T14.W, T12.W, literal.x, Pred_sel_zero ; C1818C0E 618300FD -1082130432(-1.000000e+00), 0(0.000000e+00) ; BF800000 00000000 MUL_IEEE * T14.W, T12.W, T15.W, Pred_sel_zero ; C181EC0C 61C00210 MOV * T15.W, literal.x, ; 800000FD 61E01910 0(0.000000e+00), 0(0.000000e+00) ; 00000000 00000000 ALU clause starting at 908: ; SETNE_INT * T12.W, T15.W, 1, ; 801F4C0F 61803D10 PRED_SETNE_INT * Pred,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00004508 SETGE * T12.W, 0.0, T13.W, Pred_sel_zero ; C181A0F8 61800A10 DOT4 T12.X, T13.X, T13.X, Pred_sel_zero ; 4001A00D 01805010 DOT4 T12.Y (MASKED), T13.Y, T13.Y, Pred_sel_zero ; 4081A40D 21805000 DOT4 T12.Z (MASKED), 0.0, 0.0, Pred_sel_zero ; 401F00F8 41805000 DOT4 * T12.W (MASKED), 0.0, 0.0, Pred_sel_zero ; C01F00F8 61805000 CNDE T12.W, T12.W, 1.0, T13.W, Pred_sel_zero ; 401F2C0C 61830C0D RECIPSQRT_CLAMPED * T12.Z, T12.X, Pred_sel_zero ; C000000C 41806710 SETGT T13.W, 0.0, T12.W, Pred_sel_zero ; 418180F8 61A00910 MUL_IEEE * T14.W, T12.Z, T12.X, Pred_sel_zero ; C001880C 61C00210 CNDGE T14.W, -T12.X, 0.0, T14.W, Pred_sel_zeroBS:VEC_120/SCL_212 ; 401F100C 61CB4C0E CNDE * T12.W, T13.W, T12.W, literal.x, Pred_sel_zero ; C1818C0D 618300FD -1082130432(-1.000000e+00), 0(0.000000e+00) ; BF800000 00000000 MUL_IEEE * T14.W, T12.W, T14.W, Pred_sel_zero ; C181CC0C 61C00210 MOV * T13.W, T14.W, ; 80000C0E 61A01910 ALU clause starting at 924: ; MUL_IEEE * T12.W, |T13.W|, literal.x, ; 801FAC0D 61800211 1065353048(9.999900e-01), 0(0.000000e+00) ; 3F7FFF58 00000000 MOV T15.Y, T6.Y, ; 00000406 21E01910 MOV T14.W, T10.W, ; 00000C0A 61C01910 SETGE_DX10 * T15.W, T6.Y, PV.W, ; 819FC406 61E00E10 PRED_SETNE_INT * Pred,PredicateBit (MASKED), PS, 0.0, ; 801F00FF 00004508 SETGE_DX10 T13.W, 0.0, T13.W, Pred_sel_one ; 6181A0F8 61A00E10 MOV * T14.W, literal.x, Pred_sel_one ; E00000FD 61C01910 -1082130432(-1.000000e+00), 0(0.000000e+00) ; BF800000 00000000 MOV T15.Y, T12.W, Pred_sel_one ; 60000C0C 21E01910 CNDE_INT * T14.W, T13.W, literal.x, T14.W, Pred_sel_oneBS:VEC_102/SCL_221 ; E01FAC0D 61CF8C0E 1065353216(1.000000e+00), 0(0.000000e+00) ; 3F800000 00000000 MOV T14.Z, T6.Z, ; 00000806 41C01910 MOV * T15.Z, T7.Y, ; 80000407 41E01910 MOV T16.X, T7.Z, ; 00000807 02001910 MOV T16.Z, T9.W, ; 00000C09 42001910 MOV * T15.W, T7.X, ; 80000007 61E01910 ALU clause starting at 941: ; ADD_INT T13.X, T10.Z, 1, ; 001F480A 01A03410 MOV * T12.W, literal.x, ; 800000FD 61801910 0(0.000000e+00), 0(0.000000e+00) ; 00000000 00000000 ALU clause starting at 944: ; LSHL * T12.W, T12.W, literal.x, ; 801FAC0C 61807210 31(4.344025e-44), 0(0.000000e+00) ; 0000001F 00000000 ASHR * T12.W, PV.W, literal.x, ; 801FACFE 61807010 31(4.344025e-44), 0(0.000000e+00) ; 0000001F 00000000 PRED_SETNE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00004504 ALU clause starting at 949: ; SETE_DX10 * T8.W, T10.W, 0.0, ; 801F0C0A 61000C10 PRED_SETNE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00004504 ALU clause starting at 951: ; MUL_IEEE T8.W, T7.X, 0.5, ; 001F8007 61000210 MUL_IEEE * T10.W, T6.Z, 0.5, ; 801F8806 61400210 MULADD_IEEE T10.W, T7.Z, 0.5, PS, ; 001F8807 614280FF MULADD_IEEE * T8.W, T7.Y, 0.5, PV.W, BS:VEC_021/SCL_122 ; 801F8407 61068CFE ADD T8.X, T0.X, -PS, ; 021FE000 01000010 ADD T5.Y, T0.Y, -PV.W, ; 039FC400 20A00010 ADD * T9.X, T7.Y, -PS, ; 821FE407 01200010 ADD T8.Y, T7.Z, -T10.W, ; 03814807 21000010 MUL_IEEE * T8.W, T9.W, T9.W, ; 81812C09 61000210 ADD * T8.W, -PV.W, 1.0, ; 801F3CFE 61000010 DOT4 T5.X (MASKED), T8.X, T9.X, ; 00012008 00A05000 DOT4 T5.Y, T5.Y, T8.Y, ; 00810405 20A05010 DOT4 T5.Z (MASKED), 0.0, 0.0, ; 001F00F8 40A05000 DOT4 * T5.W (MASKED), 0.0, 0.0, ; 801F00F8 60A05000 SETGT_DX10 T8.Z, 0.0, PV.X, ; 001FC0F8 41000D10 ADD T9.W, T9.W, T9.W, ; 01812C09 61200010 RECIP_IEEE * T5.Y, T8.W, ; 80000C08 20A06610 MUL_IEEE T8.X, PV.W, PS, ; 001FECFE 01000210 MOV T8.W, literal.x, ; 000000FD 61001910 SETE_INT * T9.W, PV.Z, 0.0, ; 801F08FE 61203A10 1(1.401298e-45), 0(0.000000e+00) ; 00000001 00000000 PRED_SETE_INT * Pred,PredicateBit (MASKED), PS, 0.0, ; 801F00FF 00004208 MOV T5.Y, T8.X, Pred_sel_zero ; 40000008 20A01910 ADD * T8.Y, T7.Z, -T6.Z, Pred_sel_zero ; C300C807 21000010 ADD T9.X, T7.Y, -T7.X, Pred_sel_zero ; 4200E407 01200010 MOV * T9.Y, literal.x, Pred_sel_zero ; C00000FD 21201910 -1082130432(-1.000000e+00), 0(0.000000e+00) ; BF800000 00000000 DOT4 T10.X, T9.X, -T8.X, Pred_sel_zero ; 42010009 01405010 DOT4 T10.Y (MASKED), T8.Y, T9.Y, Pred_sel_zero ; 40812408 21405000 DOT4 T10.Z (MASKED), 0.0, 0.0, Pred_sel_zero ; 401F00F8 41405000 DOT4 * T10.W (MASKED), 0.0, 0.0, Pred_sel_zero ; C01F00F8 61405000 DOT4 T5.X (MASKED), T9.X, 1.0, Pred_sel_zero ; 401F2009 00A05000 DOT4 T5.Y, T8.Y, -T5.Y, Pred_sel_zero ; 4280A408 20A05010 DOT4 T5.Z (MASKED), 0.0, 0.0, Pred_sel_zero ; 401F00F8 40A05000 DOT4 * T5.W (MASKED), 0.0, 0.0, Pred_sel_zero ; C01F00F8 60A05000 DOT4 T8.X (MASKED), T10.X, T10.X, Pred_sel_zero ; 4001400A 01005000 DOT4 T8.Y, T5.Y, T5.Y, Pred_sel_zero ; 4080A405 21005010 DOT4 T8.Z (MASKED), 0.0, 0.0, Pred_sel_zero ; 401F00F8 41005000 DOT4 * T8.W (MASKED), 0.0, 0.0, Pred_sel_zero ; C01F00F8 61005000 RECIPSQRT_CLAMPED * T8.Y, T8.Y, Pred_sel_zero ; C0000408 21006710 MUL_IEEE T9.X, T10.X, T8.Y, Pred_sel_zero BS:VEC_021/SCL_122 ; 4081000A 01240210 MUL_IEEE T5.Y, T5.Y, T8.Y, Pred_sel_zero BS:VEC_021/SCL_122 ; 40810405 20A40210 ADD * T10.X, T0.X, -T7.Y, Pred_sel_zero ; C280E000 01400010 ADD T8.Y, T0.Y, -T7.Z, Pred_sel_zero ; 4300E400 21000010 MOV * T8.W, literal.x, Pred_sel_zero ; C00000FD 61001910 0(0.000000e+00), 0(0.000000e+00) ; 00000000 00000000 DOT4 T5.X (MASKED), T10.X, T9.X, Pred_sel_zero ; 4001200A 00A05000 DOT4 T5.Y, T8.Y, T5.Y, Pred_sel_zero ; 4080A408 20A05010 DOT4 T5.Z (MASKED), 0.0, 0.0, Pred_sel_zero ; 401F00F8 40A05000 DOT4 * T5.W (MASKED), 0.0, 0.0, Pred_sel_zero ; C01F00F8 60A05000 ALU clause starting at 1001: ; SETNE_INT * T8.W, T8.W, 1, ; 801F4C08 61003D10 PRED_SETNE_INT * Pred,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00004508 MOV T5.Y, T8.X, Pred_sel_zero ; 40000008 20A01910 ADD * T8.Y, T7.Z, -T6.Z, Pred_sel_zero ; C300C807 21000010 ADD T9.X, T7.Y, -T7.X, Pred_sel_zero ; 4200E407 01200010 MOV * T7.Y, literal.x, Pred_sel_zero ; C00000FD 20E01910 -1082130432(-1.000000e+00), 0(0.000000e+00) ; BF800000 00000000 DOT4 T8.X, T9.X, T8.X, Pred_sel_zero ; 40010009 01005010 DOT4 T8.Y (MASKED), T8.Y, T7.Y, Pred_sel_zero ; 4080E408 21005000 DOT4 T8.Z (MASKED), 0.0, 0.0, Pred_sel_zero ; 401F00F8 41005000 DOT4 * T8.W (MASKED), 0.0, 0.0, Pred_sel_zero ; C01F00F8 61005000 DOT4 T5.X (MASKED), T9.X, 1.0, Pred_sel_zero ; 401F2009 00A05000 DOT4 T5.Y, T8.Y, T5.Y, Pred_sel_zero ; 4080A408 20A05010 DOT4 T5.Z (MASKED), 0.0, 0.0, Pred_sel_zero ; 401F00F8 40A05000 DOT4 * T5.W (MASKED), 0.0, 0.0, Pred_sel_zero ; C01F00F8 60A05000 DOT4 T7.X (MASKED), T8.X, T8.X, Pred_sel_zero ; 40010008 00E05000 DOT4 T7.Y, T5.Y, T5.Y, Pred_sel_zero ; 4080A405 20E05010 DOT4 T7.Z (MASKED), 0.0, 0.0, Pred_sel_zero ; 401F00F8 40E05000 DOT4 * T7.W (MASKED), 0.0, 0.0, Pred_sel_zero ; C01F00F8 60E05000 RECIPSQRT_CLAMPED * T7.Y, T7.Y, Pred_sel_zero ; C0000407 20E06710 MUL_IEEE T8.X, T8.X, T7.Y, Pred_sel_zero ; 4080E008 01000210 MUL_IEEE T5.Y, T5.Y, T7.Y, Pred_sel_zero ; 4080E405 20A00210 ADD * T7.X, T0.X, -T7.X, Pred_sel_zero ; C200E000 00E00010 ADD * T7.Y, T0.Y, -T6.Z, Pred_sel_zero ; C300C400 20E00010 DOT4 T5.X (MASKED), T7.X, T8.X, Pred_sel_zero ; 40010007 00A05000 DOT4 T5.Y, T7.Y, T5.Y, Pred_sel_zero ; 4080A407 20A05010 DOT4 T5.Z (MASKED), 0.0, 0.0, Pred_sel_zero ; 401F00F8 40A05000 DOT4 * T5.W (MASKED), 0.0, 0.0, Pred_sel_zero ; C01F00F8 60A05000 SETGE * T8.W, 0.0, T5.Y, ; 8080A0F8 61000A10 CNDE * T8.W, PV.W, 1.0, T5.Y, ; 801F2CFE 61030405 SETGT * T9.W, 0.0, PV.W, ; 819FC0F8 61200910 CNDE * T10.W, PV.W, T8.W, literal.x, ; 81810CFE 614300FD -1082130432(-1.000000e+00), 0(0.000000e+00) ; BF800000 00000000 ALU clause starting at 1034: ; MOV T9.W, literal.x, ; 000000FD 61201910 MUL_IEEE * T13.W, T6.Y, T10.W, ; 81814406 61A00210 0(0.000000e+00), 0(0.000000e+00) ; 00000000 00000000 ALU clause starting at 1037: ; LSHL * T8.W, T9.W, literal.x, ; 801FAC09 61007210 31(4.344025e-44), 0(0.000000e+00) ; 0000001F 00000000 ASHR * T8.W, PV.W, literal.x, ; 801FACFE 61007010 31(4.344025e-44), 0(0.000000e+00) ; 0000001F 00000000 PRED_SETNE_INT * Pred,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00004508 MULADD_IEEE * T7.W, T7.W, literal.x, 0.5, Pred_sel_one ; E01FAC07 60E280FC 1042479491(1.591549e-01), 0(0.000000e+00) ; 3E22F983 00000000 FRACT * T7.W, T7.W, Pred_sel_one ; E0000C07 60E01010 ADD T7.W, T7.W, literal.x, Pred_sel_one ; 601FAC07 60E00010 INT_TO_FLT * T5.Y, T1.W, Pred_sel_one ; E0000C01 20A06C10 -1090519040(-5.000000e-01), 0(0.000000e+00) ; BF000000 00000000 SIN * T6.Y, T7.W, Pred_sel_one ; E0000C07 20C06E10 COS * T6.Z, T7.W, Pred_sel_one ; E0000C07 40C06F10 MUL_IEEE T7.X, T6.Z, literal.x, Pred_sel_one ; 601FA806 00E00210 MUL_IEEE T6.Y, T6.Y, literal.x, Pred_sel_one ; 601FA406 20C00210 INT_TO_FLT * T6.Z, T2.W, Pred_sel_one ; E0000C02 40C06C10 1078530011(3.141593e+00), 0(0.000000e+00) ; 40490FDB 00000000 MULADD_IEEE T8.X, T6.Z, literal.x, T0.X, Pred_sel_one ; 601FA806 01028000 MULADD_IEEE * T5.Y, T5.Y, literal.x, T0.Y, Pred_sel_one ; E01FA405 20A28400 -1090519040(-5.000000e-01), 0(0.000000e+00) ; BF000000 00000000 DOT4 T5.X (MASKED), T8.X, T7.X, Pred_sel_one ; 6000E008 00A05000 DOT4 T5.Y, T5.Y, T6.Y, Pred_sel_one ; 6080C405 20A05010 DOT4 T5.Z (MASKED), 0.0, 0.0, Pred_sel_one ; 601F00F8 40A05000 DOT4 * T5.W (MASKED), 0.0, 0.0, Pred_sel_one ; E01F00F8 60A05000 ADD * T13.W, T5.Y, -T5.Z, Pred_sel_one ; E300A405 61A00010 MOV * T9.W, literal.x, ; 800000FD 61201910 0(0.000000e+00), 0(0.000000e+00) ; 00000000 00000000 ALU clause starting at 1064: ; DOT4 T6.X (MASKED), T8.X, T8.X, ; 00010008 00C05000 DOT4 T6.Y, T8.Y, T8.Y, ; 00810408 20C05010 DOT4 T6.Z (MASKED), 0.0, 0.0, ; 001F00F8 40C05000 DOT4 * T6.W (MASKED), 0.0, 0.0, ; 801F00F8 60C05000 RECIPSQRT_CLAMPED * T5.Y, PV.X, ; 800000FE 20A06710 DOT4 T6.X (MASKED), T7.X, T7.X, ; 0000E007 00C05000 DOT4 T6.Y (MASKED), T7.Y, T7.Y, ; 0080E407 20C05000 DOT4 T6.Z, 0.0, 0.0, ; 001F00F8 40C05010 DOT4 * T6.W (MASKED), 0.0, 0.0, ; 801F00F8 60C05000 RECIPSQRT_CLAMPED * T5.Z, PV.X, ; 800000FE 40A06710 MUL_IEEE T10.W, PS, T6.Z, ; 0100C0FF 61400210 MUL_IEEE * T11.W, T5.Y, T6.Y, ; 8080C405 61600210 CNDGE T9.X, -T6.Y, 0.0, PS, ; 001F1406 012340FF CNDGE * T6.Y, -T6.Z, 0.0, PV.W, ; 801F1806 20C34CFE DOT4 T6.X (MASKED), T9.X, T9.X, ; 00012009 00C05000 DOT4 T6.Y, T6.Y, T6.Y, ; 0080C406 20C05010 DOT4 T6.Z (MASKED), 0.0, 0.0, ; 001F00F8 40C05000 DOT4 * T6.W (MASKED), 0.0, 0.0, ; 801F00F8 60C05000 RECIPSQRT_CLAMPED * T6.Z, PV.X, ; 800000FE 40C06710 MUL_IEEE * T10.W, PS, T6.Y, ; 8080C0FF 61400210 CNDGE * T10.W, -T6.Y, 0.0, PV.W, ; 801F1406 61434CFE MUL_IEEE T10.W, PV.W, literal.x, ; 001FACFE 61400210 SETNE_INT * T9.W, T9.W, 1, ; 801F4C09 61203D10 1060439283(7.071068e-01), 0(0.000000e+00) ; 3F3504F3 00000000 PRED_SETNE_INT * Pred,PredicateBit (MASKED), PS, 0.0, ; 801F00FF 00004508 INT_TO_FLT * T6.X, T6.X, Pred_sel_zero ; C0000006 00C06C10 MUL_IEEE * T13.W, T6.X, literal.x, Pred_sel_zero ; C01FA006 61A00210 1315859240(1.000000e+09), 0(0.000000e+00) ; 4E6E6B28 00000000 RECIP_IEEE * T6.X, T10.W, ; 80000C0A 00C06610 MUL_IEEE * T9.W, T13.W, PS, ; 801FEC0D 61200210 MOV T6.Z, literal.x, ; 000000FD 40C01910 MUL_IEEE T9.W, PV.W, KC0[2].X, ; 00104CFE 61200210 SETE_INT * T10.W, KC0[7].X, literal.y, ; 809FA087 61403A10 1(1.401298e-45), -1(-nan) ; 00000001 FFFFFFFF PRED_SETNE_INT * ExecMask,PredicateBit (MASKED), PS, 0.0, ; 801F00FF 00004504 ALU clause starting at 1099: ; ADD T10.W, T9.W, literal.x, ; 001FAC09 61400010 ADD * T11.W, |T9.W|, literal.y, ; 809FAC09 61600011 -1082130432(-1.000000e+00), -1073741824(-2.000000e+00) ; BF800000 C0000000 MOV T11.W, -PS, ; 000010FF 61601910 MUL_IEEE_SAT * T10.W, PV.W, literal.x, ; 801FACFE E1400210 -1090519040(-5.000000e-01), 0(0.000000e+00) ; BF000000 00000000 ADD T12.W, PS, PS, ; 001FE0FF 61800010 MOV_SAT * T11.W, PV.W, ; 80000CFE E1601910 ADD T14.W, PS, PS, ; 001FE0FF 61C00010 ADD * T12.W, -PV.W, literal.x, ; 801FBCFE 61800010 1077936128(3.000000e+00), 0(0.000000e+00) ; 40400000 00000000 MUL_IEEE T12.W, T10.W, PS, ; 001FEC0A 61800210 ADD * T14.W, -PV.W, literal.x, ; 801FBCFE 61C00010 1077936128(3.000000e+00), 0(0.000000e+00) ; 40400000 00000000 MUL_IEEE T14.W, T11.W, PS, ; 001FEC0B 61C00210 MUL_IEEE * T10.W, T10.W, PV.W, ; 819FCC0A 61400210 MUL_IEEE T6.Z, PS, 0.5, ; 001F80FF 40C00210 MUL_IEEE T12.W, T11.W, PV.W, ; 019FCC0B 61800210 MUL_IEEE * T10.W, PS, 0.0, ; 801F00FF 61400210 SETGE_DX10 T9.Z, |T9.W|, literal.x, ; 001FAC09 41200E11 MULADD_IEEE T10.W, PV.W, 0.0, PS, ; 001F0CFE 614280FF MULADD_IEEE * T11.W, T11.W, T14.W, PV.Z, ; 8181CC0B 616288FE 1307470632(5.000000e+08), 0(0.000000e+00) ; 4DEE6B28 00000000 MOV * T12.W, PS, ; 800000FF 61801910 MOV T6.Z, T10.W, ; 00000C0A 40C01910 SETNE_INT * T14.W, T9.Z, literal.x, ; 801FA809 61C03D10 -1(-nan), 0(0.000000e+00) ; FFFFFFFF 00000000 PRED_SETE_INT * Pred,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00004208 INT_TO_FLT * T6.X, T1.W, Pred_sel_zero ; C0000C01 00C06C10 INT_TO_FLT * T6.Y, T2.W, Pred_sel_zero ; C0000C02 20C06C10 MAX * T12.W, T6.X, T6.Y, Pred_sel_zero ; C080C006 61800310 RECIP_IEEE * T6.X, T12.W, Pred_sel_zero ; C0000C0C 00C06610 MUL_IEEE * T12.W, literal.x, T6.X, Pred_sel_zero ; C000C0FD 61800210 -1082130432(-1.000000e+00), 0(0.000000e+00) ; BF800000 00000000 MUL_IEEE T12.W, |T13.W|, T12.W, Pred_sel_zero ; 41818C0D 61800211 MOV * T13.W, literal.x, Pred_sel_zero ; C00000FD 61A01910 1053609165(4.000000e-01), 0(0.000000e+00) ; 3ECCCCCD 00000000 ADD T6.Z, T10.W, literal.x, Pred_sel_zero ; 401FAC0A 40C00010 MULADD_IEEE * T13.W, T12.W, literal.y, T13.W, Pred_sel_zeroBS:VEC_102/SCL_221 ; C09FAC0C 61AE8C0D 1053609165(4.000000e-01), 1082130432(4.000000e+00) ; 3ECCCCCD 40800000 ADD T12.W, T11.W, 0.0, Pred_sel_zero ; 401F0C0B 61800010 ADD * T11.W, T11.W, T13.W, Pred_sel_zero ; C181AC0B 61600010 ADD * T10.W, T10.W, 0.0, Pred_sel_zero ; C01F0C0A 61400010 FLOOR * T13.W, T0.Y, ; 80000400 61A01410 MAX * T13.W, 0.0, PV.W, ; 819FC0F8 61A00310 MIN T13.W, T2.X, PV.W, ; 019FC002 61A00410 FLOOR * T14.W, T0.X, ; 80000000 61C01410 MAX T14.W, 0.0, PS, ; 001FE0F8 61C00310 FLT_TO_INT * T2.X, PV.W, ; 80000CFE 00406B10 MIN T13.W, T2.Y, PV.W, ; 019FC402 61A00410 MULLO_INT * T2.X, PS, T2.W, ; 818040FF 00407310 FLT_TO_INT * T2.Y, PV.W, ; 80000CFE 20406B10 ADD_INT * T13.W, T2.X, PS, ; 801FE002 61A03410 SETGT_INT * T14.W, 0.0, PV.W, ; 819FC0F8 61C03B10 ADD_INT * T15.W, T13.W, PV.W, ; 819FCC0D 61E03410 XOR_INT * T15.W, PV.W, T14.W, ; 8181CCFE 61E03210 MULHI * T2.X, T5.W, PV.W, ; 819FCC05 00407610 MULLO_INT * T2.Y, PS, T4.W, ; 818080FF 20407310 SUB_INT * T5.W, T15.W, PS, ; 801FEC0F 60A03510 SETGE_UINT T9.Z, PV.W, T4.W, ; 01808CFE 41203F10 SETGE_UINT T4.W, T15.W, T2.Y, ; 00804C0F 60803F10 INT_TO_FLT * T2.Y, T13.W, ; 80000C0D 20406C10 MUL_IEEE T10.Z, PS, T3.Y, ; 008060FF 41400210 AND_INT T5.W, PV.Z, PV.W, ; 019FC8FE 60A03010 ADD_INT * T13.W, T2.X, 1, ; 801F4002 61A03410 CNDE_INT T9.Z, PV.W, T2.X, PS, ; 00004CFE 412380FF ADD_INT T5.W, T2.X, literal.x, ; 001FA002 60A03410 FRACT * T13.W, PV.Z, ; 800008FE 61A01010 -1(-nan), 0(0.000000e+00) ; FFFFFFFF 00000000 MUL_IEEE T10.Z, T3.X, PS, ; 001FE003 41400210 CNDE_INT T4.W, T4.W, PV.W, PV.Z, ; 019FCC04 608388FE XOR_INT * T5.W, T14.W, T2.Z, ; 81004C0E 60A03210 ADD_INT T4.W, PV.W, PS, ; 001FECFE 60803410 FLT_TO_INT * T2.X, PV.Z, ; 800008FE 00406B10 ADD_INT T13.W, T4.Y, PS, ; 001FE404 61A03410 XOR_INT * T4.W, PV.W, T5.W, ; 8180ACFE 60803210 ADD_INT T4.W, T1.X, PS, ; 001FE001 60803410 INT_TO_FLT * T1.X, PV.W, ; 80000CFE 00206C10 ADD T5.W, PS, 0.5, ; 001F80FF 60A00010 INT_TO_FLT * T1.X, PV.W, ; 80000CFE 00206C10 MUL_IEEE T13.X, PV.W, T3.Z, ; 01006CFE 01A00210 ADD * T4.W, PS, 0.5, ; 801F80FF 60800010 MUL_IEEE * T13.Y, PV.W, T4.X, ; 80008CFE 21A00210 ALU clause starting at 1182: ; MUL_IEEE * T4.W, T14.X, literal.x, ; 801FA00E 60800210 1132462079(2.560000e+02), 0(0.000000e+00) ; 437FFFFF 00000000 FLT_TO_INT * T1.X, PV.W, ; 80000CFE 00206B10 MOV T2.Z, literal.x, ; 000000FD 40401910 SETE_INT T4.W, PS, 0.0, ; 001F00FF 60803A10 SETNE_INT * T5.W, PS, 0.0, ; 801F00FF 60A03D10 -1(-nan), 0(0.000000e+00) ; FFFFFFFF 00000000 PRED_SETNE_INT * Pred,PredicateBit (MASKED), PS, 0.0, ; 801F00FF 00004508 MUL_IEEE T4.W, T14.W, literal.x, Pred_sel_zero ; 401FAC0E 60800210 MUL_IEEE * T5.W, T14.Y, literal.x, Pred_sel_zero ; C01FA40E 60A00210 1132462079(2.560000e+02), 0(0.000000e+00) ; 437FFFFF 00000000 FLT_TO_INT * T1.X, T4.W, Pred_sel_zero ; C0000C04 00206B10 MUL_IEEE T4.W, T14.Z, literal.x, Pred_sel_zero ; 401FA80E 60800210 FLT_TO_INT * T2.X, T5.W, Pred_sel_zero ; C0000C05 00406B10 1132462079(2.560000e+02), 0(0.000000e+00) ; 437FFFFF 00000000 LSHL T3.Z, T2.X, literal.x, Pred_sel_zero ; 401FA002 40607210 SETE_INT T5.W, T1.X, literal.y, Pred_sel_zero BS:VEC_120/SCL_212 ; 409FA001 60A83A10 FLT_TO_INT * T2.X, T4.W, Pred_sel_zero ; C0000C04 00406B10 8(1.121039e-44), 255(3.573311e-43) ; 00000008 000000FF CNDE_INT T2.Z, T5.W, T1.X, 0.0, Pred_sel_zero ; 40002C05 404380F8 ADD_INT * T4.W, T3.Z, T2.X, Pred_sel_zero BS:VEC_021/SCL_122 ; C0004803 60843410 MOV T5.W, literal.x, ; 000000FD 60A01910 SETE_INT * T14.W, T2.Z, 0.0, ; 801F0802 61C03A10 1315859240(1.000000e+09), 0(0.000000e+00) ; 4E6E6B28 00000000 PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PS, 0.0, ; 801F00FF 00004204 ALU clause starting at 1207: ; INT_TO_FLT * T1.X, T1.W, ; 80000C01 00206C10 INT_TO_FLT * T1.W, T2.W, ; 80000C02 60206C10 INT_TO_FLT * T2.X, T4.Z, ; 80000804 00406C10 RECIP_IEEE * T2.X, PS, ; 800000FF 00406610 INT_TO_FLT * T2.Y, T6.W, ; 80000C06 20406C10 RECIP_IEEE * T2.Y, PS, ; 800000FF 20406610 MULLO_INT * T1.Z, T1.Z, T5.X, ; 8000A801 40207310 MULLO_INT * T2.W, T3.W, T1.Y, ; 80802C03 60407310 INT_TO_FLT * T3.X, T1.Y, ; 80000401 00606C10 MOV T4.Z, literal.x, ; 000000FD 40801910 MOV T15.W, literal.y, ; 000004FD 61E01910 RECIP_IEEE * T3.Y, PS, ; 800000FF 20606610 1315859240(1.000000e+09), 1(1.401298e-45) ; 4E6E6B28 00000001 ALU clause starting at 1220: ; MOV * T5.W, T4.Z, ; 80000804 60A01910 ALU clause starting at 1221: ; MOV T3.Z, T15.W, ; 00000C0F 40601910 MOV * T4.Z, literal.x, ; 800000FD 40801910 1(1.401298e-45), 0(0.000000e+00) ; 00000001 00000000 MOV T16.W, literal.x, ; 000000FD 62001910 SETGT_INT * T15.W, PV.Z, literal.y, ; 809FA8FE 61E03B10 0(0.000000e+00), 31(4.344025e-44) ; 00000000 0000001F PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PS, 0.0, ; 801F00FF 00004204 ALU clause starting at 1228: ; SETGE_INT * T15.W, T3.Z, T2.Z, ; 81004803 61E03C10 MOV T4.Z, literal.x, ; 000000FD 40801910 SETE_INT T15.W, PV.W, 0.0, ; 001F0CFE 61E03A10 MOV * T16.W, literal.y, ; 800004FD 62001910 1(1.401298e-45), 0(0.000000e+00) ; 00000001 00000000 PRED_SETNE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00004504 ALU clause starting at 1234: ; SETGT_INT * T3.W, 0.0, T1.Y, ; 808020F8 60603B10 ADD_INT * T6.W, T1.Y, PV.W, ; 819FC401 60C03410 XOR_INT * T6.W, PV.W, T3.W, ; 81806CFE 60C03210 RECIP_UINT * T4.X, PV.W, ; 80000CFE 00807810 MULLO_INT * T4.Y, PS, T6.W, ; 8180C0FF 20807310 SUB_INT T14.W, 0.0, PS, ; 001FE0F8 61C03510 MULHI * T4.Z, T4.X, T6.W, ; 8180C004 40807610 CNDE_INT T14.W, PS, PV.W, T4.Y, ; 019FC0FF 61C38404 ADD_INT * T15.W, T4.W, T3.Z, ; 81006C04 61E03410 SETGT_INT T16.W, 0.0, PS, ; 001FE0F8 62003B10 MULHI * T4.Y, PV.W, T4.X, ; 80008CFE 20807610 ADD_INT T9.Z, T15.W, PV.W, ; 019FCC0F 41203410 SUB_INT T14.W, T4.X, PS, ; 001FE004 61C03510 ADD_INT * T17.W, T4.X, PS, ; 801FE004 62203410 CNDE_INT T14.W, T4.Z, PS, PV.W, ; 001FE804 61C38CFE XOR_INT * T17.W, PV.Z, T16.W, ; 818208FE 62203210 MULHI * T4.X, PV.W, PS, ; 801FECFE 00807610 MULLO_INT * T4.Y, PS, T6.W, ; 8180C0FF 20807310 SUB_INT * T14.W, T17.W, PS, ; 801FEC11 61C03510 SETGE_UINT T4.Z, PV.W, T6.W, ; 0180CCFE 40803F10 SETGE_UINT T6.W, T17.W, T4.Y, ; 00808C11 60C03F10 INT_TO_FLT * T4.Y, T15.W, ; 80000C0F 20806C10 MUL_IEEE T9.Z, PS, T3.Y, ; 008060FF 41200210 AND_INT T14.W, PV.Z, PV.W, ; 019FC8FE 61C03010 ADD_INT * T15.W, T4.X, 1, ; 801F4004 61E03410 CNDE_INT T4.Z, PV.W, T4.X, PS, ; 00008CFE 408380FF ADD_INT T14.W, T4.X, literal.x, ; 001FA004 61C03410 FRACT * T15.W, PV.Z, ; 800008FE 61E01010 -1(-nan), 0(0.000000e+00) ; FFFFFFFF 00000000 MUL_IEEE T9.Z, T3.X, PS, ; 001FE003 41200210 CNDE_INT T6.W, T6.W, PV.W, PV.Z, ; 019FCC06 60C388FE XOR_INT * T3.W, T16.W, T3.W, ; 81806C10 60603210 ADD_INT T6.W, PV.W, PS, ; 001FECFE 60C03410 FLT_TO_INT * T4.X, PV.Z, ; 800008FE 00806B10 ADD_INT T14.W, T2.W, PS, ; 001FEC02 61C03410 XOR_INT * T3.W, PV.W, T3.W, ; 81806CFE 60603210 ADD_INT T3.W, T1.Z, PS, ; 001FE801 60603410 INT_TO_FLT * T4.X, PV.W, ; 80000CFE 00806C10 ADD T6.W, PS, 0.5, ; 001F80FF 60C00010 INT_TO_FLT * T3.W, PV.W, ; 80000CFE 60606C10 MUL_IEEE T14.X, PV.W, T2.Y, ; 00804CFE 01C00210 ADD * T3.W, PS, 0.5, ; 801F80FF 60600010 MUL_IEEE * T14.Y, PV.W, T2.X, ; 80004CFE 21C00210 ALU clause starting at 1277: ; MUL_IEEE * T3.W, T14.W, literal.x, ; 801FAC0E 60600210 1132462079(2.560000e+02), 0(0.000000e+00) ; 437FFFFF 00000000 FLT_TO_INT * T3.W, PV.W, ; 80000CFE 60606B10 MOV T4.Z, literal.x, ; 000000FD 40801910 SETE_DX10 T6.W, T14.X, 0.0, ; 001F000E 60C00C10 INT_TO_FLT * T4.X, PS, ; 800000FF 00806C10 1315859240(1.000000e+09), 0(0.000000e+00) ; 4E6E6B28 00000000 PRED_SETNE_INT * Pred,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00004508 MUL_IEEE * T6.W, T14.X, literal.x, Pred_sel_zero ; C01FA00E 60C00210 1132462079(2.560000e+02), 0(0.000000e+00) ; 437FFFFF 00000000 FLT_TO_INT * T4.Y, T6.W, Pred_sel_zero ; C0000C06 20806B10 ADD_INT * T6.W, T4.Y, literal.x, Pred_sel_zero ; C01FA404 60C03410 -128(-nan), 0(0.000000e+00) ; FFFFFF80 00000000 INT_TO_FLT * T4.Y, T6.W, Pred_sel_zero ; C0000C06 20806C10 MUL_IEEE * T4.Z, T4.Y, literal.x, Pred_sel_zero ; C01FA404 40800210 998310404(3.937008e-03), 0(0.000000e+00) ; 3B810204 00000000 SETGE_DX10 * T15.W, |T4.Z|, literal.x, ; 801FA804 61E00E11 1307470632(5.000000e+08), 0(0.000000e+00) ; 4DEE6B28 00000000 MOV T4.Z, literal.x, ; 000000FD 40801910 MUL_IEEE T6.W, T4.X, literal.y, ; 009FA004 60C00210 SETE_INT * T15.W, PV.W, 0.0, ; 801F0CFE 61E03A10 1(1.401298e-45), 1031798784(6.250000e-02) ; 00000001 3D800000 PRED_SETNE_INT * Pred,PredicateBit (MASKED), PS, 0.0, ; 801F00FF 00004508 MOV T4.Z, literal.x, Pred_sel_zero ; 400000FD 40801910 ADD_INT * T15.W, T3.Z, 1, Pred_sel_zero ; C01F4803 61E03410 0(0.000000e+00), 0(0.000000e+00) ; 00000000 00000000 ALU clause starting at 1303: ; FRACT T6.W, T6.W, ; 00000C06 60C01010 MOV * T16.W, T4.Z, ; 80000804 62001910 ALU clause starting at 1305: ; LSHL * T17.W, T4.Z, literal.x, ; 801FA804 62207210 31(4.344025e-44), 0(0.000000e+00) ; 0000001F 00000000 ASHR * T17.W, PV.W, literal.x, ; 801FACFE 62207010 31(4.344025e-44), 0(0.000000e+00) ; 0000001F 00000000 PRED_SETNE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00004504 ALU clause starting at 1310: ; MOV T17.W, literal.x, ; 000000FD 62201910 SETNE_INT * T15.W, T16.W, 1, ; 801F4C10 61E03D10 1(1.401298e-45), 0(0.000000e+00) ; 00000001 00000000 PRED_SETNE_INT * Pred,PredicateBit (MASKED), PS, 0.0, ; 801F00FF 00004508 ASHR * T15.W, T3.W, literal.x, Pred_sel_zero ; C01FAC03 61E07010 31(4.344025e-44), 0(0.000000e+00) ; 0000001F 00000000 LSHR * T15.W, T15.W, literal.x, Pred_sel_zero ; C01FAC0F 61E07110 28(3.923636e-44), 0(0.000000e+00) ; 0000001C 00000000 ADD_INT * T15.W, T3.W, T15.W, Pred_sel_zero ; C181EC03 61E03410 ASHR T15.W, T15.W, literal.x, Pred_sel_zero ; 401FAC0F 61E07010 MUL_IEEE * T16.W, T6.W, literal.y, Pred_sel_zero ; C09FAC06 62000210 4(5.605194e-45), 1098907648(1.600000e+01) ; 00000004 41800000 INT_TO_FLT * T4.X, T15.W, Pred_sel_zero ; C0000C0F 00806C10 FLT_TO_INT * T4.Y, T16.W, Pred_sel_zero ; C0000C10 20806B10 INT_TO_FLT * T4.Y, T4.Y, Pred_sel_zero ; C0000404 20806C10 ADD T15.W, T4.Y, T14.Z, Pred_sel_zero ; 4101C404 61E00010 ADD * T16.W, T4.X, T14.Y, Pred_sel_zero ; C081C004 62000010 MUL_IEEE T16.W, T16.W, literal.x, Pred_sel_zero ; 401FAC10 62000210 MUL_IEEE * T15.W, T15.W, literal.x, Pred_sel_zero ; C01FAC0F 61E00210 1031798784(6.250000e-02), 0(0.000000e+00) ; 3D800000 00000000 MUL_IEEE T15.W, T15.W, T1.X, Pred_sel_zero ; 40002C0F 61E00210 MUL_IEEE * T16.W, T16.W, T1.W, Pred_sel_zero ; C1802C10 62000210 ADD T4.X, T0.X, -T16.W, Pred_sel_zero ; 43820000 00800010 ADD * T4.Y, T0.Y, -T15.W, Pred_sel_zero BS:VEC_021/SCL_122 ; C381E400 20840010 DOT4 T4.X, T4.X, T4.X, Pred_sel_zero ; 40008004 00805010 DOT4 T4.Y (MASKED), T4.Y, T4.Y, Pred_sel_zero ; 40808404 20805000 DOT4 T4.Z (MASKED), 0.0, 0.0, Pred_sel_zero ; 401F00F8 40805000 DOT4 * T4.W (MASKED), 0.0, 0.0, Pred_sel_zero ; C01F00F8 60805000 RECIPSQRT_CLAMPED * T4.Y, T4.X, Pred_sel_zero ; C0000004 20806710 MUL_IEEE * T15.W, T4.Y, T4.X, Pred_sel_zero ; C0008404 61E00210 CNDGE * T15.W, -T4.X, 0.0, T15.W, Pred_sel_zero ; C01F1004 61E34C0F MIN T4.Z, T15.W, T5.W, Pred_sel_zero ; 4180AC0F 40800410 MOV T17.W, literal.x, Pred_sel_zero ; 400000FD 62201910 ADD_INT * T15.W, T3.Z, 1, Pred_sel_zero ; C01F4803 61E03410 0(0.000000e+00), 0(0.000000e+00) ; 00000000 00000000 ALU clause starting at 1345: ; SETNE_INT * T16.W, T17.W, 1, ; 801F4C11 62003D10 PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00004204 ALU clause starting at 1347: ; ADD * T0.W, T5.W, literal.x, ; 801FAC05 60000010 -1119040307(-5.000000e-02), 0(0.000000e+00) ; BD4CCCCD 00000000 MUL_IEEE_SAT * T0.W, PV.W, literal.x, ; 801FACFE E0000210 1120403459(1.000000e+02), 0(0.000000e+00) ; 42C80003 00000000 ADD * T2.W, PV.W, PV.W, ; 819FCCFE 60400010 ADD * T2.W, -PV.W, literal.x, ; 801FBCFE 60400010 1077936128(3.000000e+00), 0(0.000000e+00) ; 40400000 00000000 MUL_IEEE * T2.W, T0.W, PV.W, ; 819FCC00 60400210 MUL_IEEE T0.W, T0.W, PV.W, ; 019FCC00 60000210 MUL_IEEE * T2.W, T1.X, literal.x, ; 801FA001 60400210 1132462079(2.560000e+02), 0(0.000000e+00) ; 437FFFFF 00000000 ADD * T3.W, -PV.W, 1.0, ; 801F3CFE 60600010 MOV T2.Y, literal.x, ; 000000FD 20401910 MUL_IEEE T2.Z, PV.W, 0.0, ; 001F0CFE 40400210 MUL_IEEE T4.W, PV.W, 0.5, ; 001F8CFE 60800210 FLT_TO_INT * T2.X, T2.W, ; 80000C02 00406B10 -1(-nan), 0(0.000000e+00) ; FFFFFFFF 00000000 MULADD_IEEE T0.X, T0.W, T11.W, PV.W, ; 01816C00 00028CFE MULADD_IEEE * T0.Y, T0.W, T10.W, PV.Z, BS:VEC_021/SCL_122 ; 81814C00 200688FE MULADD_IEEE T0.Z, T0.W, T6.Z, T3.W, ; 0100CC00 40028C03 MULADD_IEEE T0.W, T0.W, T12.W, T2.Z, ; 01818C00 60028802 SETE_INT * T2.W, T2.X, 0.0, ; 801F0002 60403A10 PRED_SETE_INT * Pred,PredicateBit (MASKED), PS, 0.0, ; 801F00FF 00004208 MUL_IEEE * T1.W, T1.W, literal.x, Pred_sel_zero ; C01FAC01 60200210 1132462079(2.560000e+02), 0(0.000000e+00) ; 437FFFFF 00000000 FLT_TO_INT * T1.X, T1.W, Pred_sel_zero ; C0000C01 00206B10 SETE_INT * T1.W, T1.X, literal.x, Pred_sel_zero ; C01FA001 60203A10 255(3.573311e-43), 0(0.000000e+00) ; 000000FF 00000000 CNDE_INT * T2.Y, T1.W, T1.X, 0.0, Pred_sel_zero ; C0002C01 204380F8 INT_TO_FLT * T1.X, T2.Y, ; 80000402 00206C10 MULADD_IEEE T10.X, PS, 0.0, T0.W, ; 001F00FF 01428C00 MULADD_IEEE T6.Y, PS, literal.x, T0.Y, ; 001FA0FF 20C28400 MOV T6.Z, literal.y, ; 000004FD 40C01910 MULADD_IEEE T11.W, PS, 0.0, T0.Z, ; 001F00FF 61628800 MULADD_IEEE * T10.W, PS, literal.z, T0.X, BS:VEC_021/SCL_122 ; 811FA0FF 61468000 1040220289(1.254902e-01), 0(0.000000e+00) ; 3E008081 00000000 1011718760(1.254902e-02), 0(0.000000e+00) ; 3C4D9A68 00000000 ALU clause starting at 1384: ; LSHL * T0.W, T6.Z, literal.x, ; 801FA806 60007210 31(4.344025e-44), 0(0.000000e+00) ; 0000001F 00000000 ASHR * T0.W, PV.W, literal.x, ; 801FACFE 60007010 31(4.344025e-44), 0(0.000000e+00) ; 0000001F 00000000 PRED_SETNE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00004504 ALU clause starting at 1389: ; MULADD_IEEE T0.W, KC0[6].X, literal.x, T9.W, ; 001FA086 60028C09 SETNE_INT * T1.W, KC0[5].X, 0.0, ; 801F0085 60203D10 -1054867456(-1.000000e+01), 0(0.000000e+00) ; C1200000 00000000 PRED_SETNE_INT * ExecMask,PredicateBit (MASKED), PS, 0.0, ; 801F00FF 00004504 ALU clause starting at 1393: ; MOV * T0.W, |T0.W|, ; 80000C00 60001911 MULADD_IEEE * T0.W, KC0[4].X, literal.x, PV.W, ; 801FA084 60028CFE -1090519040(-5.000000e-01), 0(0.000000e+00) ; BF000000 00000000 ALU clause starting at 1396: ; SETGT_DX10 * T1.W, T0.W, 1.0, ; 801F2C00 60200D10 SETE_INT * T1.W, PV.W, 0.0, ; 801F0CFE 60203A10 PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00004204 ALU clause starting at 1399: ; KILLGT * T0.X (MASKED), 1.0, 0.0, ; 801F00F9 00002D00 ALU clause starting at 1400: ; MOV * T10.X, literal.x, ; 800000FD 01401910 0(0.000000e+00), 0(0.000000e+00) ; 00000000 00000000 MOV T1.W, PV.X, ; 000000FE 60201910 SETGE_DX10 * T2.W, literal.x, -T0.W, ; 838000FD 60400E10 -1087044365(-7.071068e-01), 0(0.000000e+00) ; BF3504F3 00000000 PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PS, 0.0, ; 801F00FF 00004204 ALU clause starting at 1406: ; MOV * T2.W, -T0.W, ; 80001C00 60401910 SETGE_DX10 T3.W, PV.W, literal.x, ; 001FACFE 60600E10 MOV * T1.W, literal.y, ; 800004FD 60201910 1060439283(7.071068e-01), 1065353216(1.000000e+00) ; 3F3504F3 3F800000 SETE_INT * T3.W, PV.W, 0.0, ; 801F0CFE 60603A10 PRED_SETNE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00004504 ALU clause starting at 1412: ; SETGE_DX10 T1.W, 0.0, T2.W, ; 018040F8 60200E10 MOV * T3.W, literal.x, ; 800000FD 60601910 1(1.401298e-45), 0(0.000000e+00) ; 00000001 00000000 SETE_INT * T1.W, PV.W, 0.0, ; 801F0CFE 60203A10 PRED_SETNE_INT * Pred,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00004508 ADD * T1.W, -T2.W, literal.x, Pred_sel_one ; E01FBC02 60200010 1060439283(7.071068e-01), 0(0.000000e+00) ; 3F3504F3 00000000 LOG_IEEE * T0.X, T1.W, Pred_sel_one ; E0000C01 00006310 MUL NON-IEEE * T1.W, literal.x, T0.X, Pred_sel_one ; E00000FD 60200110 1073741824(2.000000e+00), 0(0.000000e+00) ; 40000000 00000000 EXP_IEEE * T0.X, T1.W, Pred_sel_one ; E0000C01 00006110 MOV T3.W, literal.x, Pred_sel_one ; 600000FD 60601910 ADD * T1.W, -T0.X, 1.0, Pred_sel_one ; E01F3000 60200010 0(0.000000e+00), 0(0.000000e+00) ; 00000000 00000000 ALU clause starting at 1426: ; SETNE_INT * T3.W, T3.W, 1, ; 801F4C03 60603D10 PRED_SETNE_INT * Pred,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00004508 ADD * T1.W, T2.W, literal.x, Pred_sel_zero ; C01FAC02 60200010 1060439283(7.071068e-01), 0(0.000000e+00) ; 3F3504F3 00000000 LOG_IEEE * T0.X, T1.W, Pred_sel_zero ; C0000C01 00006310 MUL NON-IEEE * T1.W, literal.x, T0.X, Pred_sel_zero ; C00000FD 60200110 1073741824(2.000000e+00), 0(0.000000e+00) ; 40000000 00000000 EXP_IEEE * T1.W, T1.W, Pred_sel_zero ; C0000C01 60206110 ALU clause starting at 1434: ; MUL_IEEE T2.W, T8.X, T5.Y, ; 0080A008 60400210 MUL_IEEE * T3.W, T7.X, T5.Z, ; 8100A007 60600210 ADD * T2.W, |PV.W|, |PS|, ; 801FECFE 60400013 ADD * T2.W, PV.W, literal.x, ; 801FACFE 60400010 -1082130432(-1.000000e+00), 0(0.000000e+00) ; BF800000 00000000 MUL_IEEE_SAT * T2.W, PV.W, literal.x, ; 801FACFE E0400210 1075479162(2.414214e+00), 0(0.000000e+00) ; 401A827A 00000000 ADD T3.W, -PV.W, 1.0, ; 001F3CFE 60600010 ADD_SAT * T0.W, -T0.W, 0.5, ; 801F9C00 E0000010 MUL_IEEE T0.W, PV.W, PS, ; 001FECFE 60000210 SETNE_DX10 * T3.W, KC0[3].X, 1.0, ; 801F2083 60600F10 MULADD_IEEE * T10.W, T2.W, T1.W, PV.W, ; 81802C02 61428CFE PRED_SETNE_INT * ExecMask,PredicateBit (MASKED), T3.W, 0.0, ; 801F0C03 00004504 ALU clause starting at 1447: ; RECIP_IEEE * T0.X, KC0[3].X, ; 80000083 00006610 LOG_IEEE * T0.Y, T10.W, ; 80000C0A 20006310 MUL NON-IEEE * T0.W, T0.X, PS, ; 801FE000 60000110 EXP_IEEE * T10.W, PV.W, ; 80000CFE 61406110 ALU clause starting at 1451: ; MOV T6.Y, T10.X, ; 0000000A 20C01910 MOV * T11.W, T10.X, ; 8000000A 61601910 ALU clause starting at 1453: ; MOV T10.Y, T11.W, ; 00000C0B 21401910 MOV * T10.Z, T6.Y, ; 80000406 41401910