diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 30c627c..0dd78fd 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -555,7 +555,7 @@ intel_dp_aux_native_write(struct intel_dp *intel_dp,
 		if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
 			break;
 		else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
-			udelay(100);
+			udelay(500);
 		else
 			return -EIO;
 	}
@@ -1935,10 +1935,17 @@ intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
 static bool
 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
 {
-	return intel_dp_aux_native_read_retry(intel_dp,
+	bool ret = intel_dp_aux_native_read_retry(intel_dp,
 					      DP_LANE0_1_STATUS,
 					      link_status,
 					      DP_LINK_STATUS_SIZE);
+	DRM_DEBUG_KMS("Read link_status 0: %02x\n", link_status[0]);
+	DRM_DEBUG_KMS("Read link_status 1: %02x\n", link_status[1]);
+	DRM_DEBUG_KMS("Read link_status 2: %02x\n", link_status[2]);
+	DRM_DEBUG_KMS("Read link_status 3: %02x\n", link_status[3]);
+	DRM_DEBUG_KMS("Read link_status 4: %02x\n", link_status[4]);
+	DRM_DEBUG_KMS("Read link_status 5: %02x\n", link_status[5]);
+	return ret;
 }
 
 #if 0
@@ -2153,7 +2160,8 @@ intel_get_adjust_train(struct intel_dp *intel_dp,
 	for (lane = 0; lane < intel_dp->lane_count; lane++) {
 		uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
 		uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
-
+		DRM_DEBUG_KMS("This v: %d\n", this_v);
+		DRM_DEBUG_KMS("This p: %d\n", this_p);
 		if (this_v > v)
 			v = this_v;
 		if (this_p > p)
@@ -2168,6 +2176,7 @@ intel_get_adjust_train(struct intel_dp *intel_dp,
 	if (p >= preemph_max)
 		p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
 
+	DRM_DEBUG_KMS("Trainset: %08x\n", v | p);
 	for (lane = 0; lane < 4; lane++)
 		intel_dp->train_set[lane] = v | p;
 }
@@ -2352,6 +2361,7 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
 		signal_levels = intel_bdw_signal_levels(train_set);
 		mask = DDI_BUF_EMP_MASK;
 	} else if (IS_HASWELL(dev)) {
+		DRM_DEBUG_KMS("Haswell...\n", train_set);
 		signal_levels = intel_hsw_signal_levels(train_set);
 		mask = DDI_BUF_EMP_MASK;
 	} else if (IS_VALLEYVIEW(dev)) {
@@ -2368,6 +2378,7 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
 		mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
 	}
 
+	DRM_DEBUG_KMS("Train set is: %02x\n", train_set);
 	DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
 
 	*DP = (*DP & ~mask) | signal_levels;