PGETBL_CTL: 0x00000000 GEN6_INSTDONE_1: 0xffdffffe GEN6_INSTDONE_2: 0x00000000 CPU_VGACNTRL: 0x80002900 (disabled) DIGITAL_PORT_HOTPLUG_CNTRL: 0x00000013 RR_HW_CTL: 0x00f50e98 (low 152, high 14) FDI_PLL_BIOS_0: 0x00000000 FDI_PLL_BIOS_1: 0x00000000 FDI_PLL_BIOS_2: 0x00000000 DISPLAY_PORT_PLL_BIOS_0: 0x00000000 DISPLAY_PORT_PLL_BIOS_1: 0x00000000 DISPLAY_PORT_PLL_BIOS_2: 0x00000000 FDI_PLL_FREQ_CTL: 0x00000000 PIPEACONF: 0x00000000 (disabled, inactive, pf-pd, rotate 0, 8bpc) HTOTAL_A: 0x00000000 (1 active, 1 total) HBLANK_A: 0x00000000 (1 start, 1 end) HSYNC_A: 0x00000000 (1 start, 1 end) VTOTAL_A: 0x00000000 (1 active, 1 total) VBLANK_A: 0x00000000 (1 start, 1 end) VSYNC_A: 0x00000000 (1 start, 1 end) VSYNCSHIFT_A: 0x00000000 PIPEASRC: 0x077f0437 (1920, 1080) PIPEA_DATA_M1: 0x00000000 (TU 1, val 0x0 0) PIPEA_DATA_N1: 0x00000000 (val 0x0 0) PIPEA_DATA_M2: 0x00000000 (TU 1, val 0x0 0) PIPEA_DATA_N2: 0x00000000 (val 0x0 0) PIPEA_LINK_M1: 0x00000000 (val 0x0 0) PIPEA_LINK_N1: 0x00000000 (val 0x0 0) PIPEA_LINK_M2: 0x00000000 (val 0x0 0) PIPEA_LINK_N2: 0x00000000 (val 0x0 0) DSPACNTR: 0xd9000400 (enabled) DSPABASE: 0x00000000 DSPASTRIDE: 0x00001e00 (120) DSPASURF: 0x01093000 DSPATILEOFF: 0x00000000 (0, 0) PIPEBCONF: 0x00000000 (disabled, inactive, pf-pd, rotate 0, 8bpc) HTOTAL_B: 0x00000000 (1 active, 1 total) HBLANK_B: 0x00000000 (1 start, 1 end) HSYNC_B: 0x00000000 (1 start, 1 end) VTOTAL_B: 0x00000000 (1 active, 1 total) VBLANK_B: 0x00000000 (1 start, 1 end) VSYNC_B: 0x00000000 (1 start, 1 end) VSYNCSHIFT_B: 0x00000000 PIPEBSRC: 0x00000000 (1, 1) PIPEB_DATA_M1: 0x00000000 (TU 1, val 0x0 0) PIPEB_DATA_N1: 0x00000000 (val 0x0 0) PIPEB_DATA_M2: 0x00000000 (TU 1, val 0x0 0) PIPEB_DATA_N2: 0x00000000 (val 0x0 0) PIPEB_LINK_M1: 0x00000000 (val 0x0 0) PIPEB_LINK_N1: 0x00000000 (val 0x0 0) PIPEB_LINK_M2: 0x00000000 (val 0x0 0) PIPEB_LINK_N2: 0x00000000 (val 0x0 0) DSPBCNTR: 0x00000000 (disabled) DSPBBASE: 0x00000000 DSPBSTRIDE: 0x00000000 (0) DSPBSURF: 0x00000000 DSPBTILEOFF: 0x00000000 (0, 0) PIPECCONF: 0x00000000 (disabled, inactive, pf-pd, rotate 0, 8bpc) HTOTAL_C: 0x00000000 (1 active, 1 total) HBLANK_C: 0x00000000 (1 start, 1 end) HSYNC_C: 0x00000000 (1 start, 1 end) VTOTAL_C: 0x00000000 (1 active, 1 total) VBLANK_C: 0x00000000 (1 start, 1 end) VSYNC_C: 0x00000000 (1 start, 1 end) VSYNCSHIFT_C: 0x00000000 PIPECSRC: 0x00000000 (1, 1) PIPEC_DATA_M1: 0x00000000 (TU 1, val 0x0 0) PIPEC_DATA_N1: 0x00000000 (val 0x0 0) PIPEC_DATA_M2: 0x00000000 (TU 1, val 0x0 0) PIPEC_DATA_N2: 0x00000000 (val 0x0 0) PIPEC_LINK_M1: 0x00000000 (val 0x0 0) PIPEC_LINK_N1: 0x00000000 (val 0x0 0) PIPEC_LINK_M2: 0x00000000 (val 0x0 0) PIPEC_LINK_N2: 0x00000000 (val 0x0 0) DSPCCNTR: 0x00000000 (disabled) DSPCBASE: 0x00000000 DSPCSTRIDE: 0x00000000 (0) DSPCSURF: 0x00000000 DSPCTILEOFF: 0x00000000 (0, 0) PFA_CTL_1: 0x00000000 (disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1) PFA_CTL_2: 0x00000000 (vscale 0.000000) PFA_CTL_3: 0x00000000 (vscale initial phase 0.000000) PFA_CTL_4: 0x00000000 (hscale 0.000000) PFA_WIN_POS: 0x00000000 (0, 0) PFA_WIN_SIZE: 0x00000000 (0, 0) PFB_CTL_1: 0x00000000 (disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1) PFB_CTL_2: 0x00000000 (vscale 0.000000) PFB_CTL_3: 0x00000000 (vscale initial phase 0.000000) PFB_CTL_4: 0x00000000 (hscale 0.000000) PFB_WIN_POS: 0x00000000 (0, 0) PFB_WIN_SIZE: 0x00000000 (0, 0) PFC_CTL_1: 0x00000000 (disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1) PFC_CTL_2: 0x00000000 (vscale 0.000000) PFC_CTL_3: 0x00000000 (vscale initial phase 0.000000) PFC_CTL_4: 0x00000000 (hscale 0.000000) PFC_WIN_POS: 0x00000000 (0, 0) PFC_WIN_SIZE: 0x00000000 (0, 0) PCH_DREF_CONTROL: 0xffffffff (cpu source nonspread, ssc_source enable, nonspread_source enable, superspread_source enable, ssc4_mode centerspread, ssc1 enable, ssc4 enable) PCH_RAWCLK_FREQ: 0x00000018 (FDL_TP1 timer 0.5us, FDL_TP2 timer 1.5us, freq 24) PCH_DPLL_TMR_CFG: 0x00000018 PCH_SSC4_PARMS: 0x00000018 PCH_SSC4_AUX_PARMS: 0x00000018 PCH_DPLL_SEL: 0x00000018 (FDL_TP1 timer 0.5us, FDL_TP2 timer 1.5us, freq 24) PCH_DPLL_ANALOG_CTL: 0x00000018 PCH_DPLL_A: 0x00000018 (disable, sdvo high speed no, mode (null), p2 (null), FPA0 P1 0, FPA1 P1 4, refclk default 120Mhz, sdvo/hdmi mul 1) PCH_DPLL_B: 0x00000018 (disable, sdvo high speed no, mode (null), p2 (null), FPA0 P1 0, FPA1 P1 4, refclk default 120Mhz, sdvo/hdmi mul 1) PCH_FPA0: 0x00000018 (n = 0, m1 = 0, m2 = 24) PCH_FPA1: 0x00000018 (n = 0, m1 = 0, m2 = 24) PCH_FPB0: 0x00000018 (n = 0, m1 = 0, m2 = 24) PCH_FPB1: 0x00000018 (n = 0, m1 = 0, m2 = 24) TRANS_HTOTAL_A: 0x00000018 (25 active, 1 total) TRANS_HBLANK_A: 0x00000018 (25 start, 1 end) TRANS_HSYNC_A: 0x00000018 (25 start, 1 end) TRANS_VTOTAL_A: 0x00000018 (25 active, 1 total) TRANS_VBLANK_A: 0x00000018 (25 start, 1 end) TRANS_VSYNC_A: 0x00000018 (25 start, 1 end) TRANS_VSYNCSHIFT_A: 0x00000018 TRANSA_DATA_M1: 0x00000018 (TU 1, val 0x18 24) TRANSA_DATA_N1: 0x00000018 (val 0x18 24) TRANSA_DATA_M2: 0x00000018 (TU 1, val 0x18 24) TRANSA_DATA_N2: 0x00000018 (val 0x18 24) TRANSA_DP_LINK_M1: 0x00000018 (val 0x18 24) TRANSA_DP_LINK_N1: 0x00000018 (val 0x18 24) TRANSA_DP_LINK_M2: 0x00000018 (val 0x18 24) TRANSA_DP_LINK_N2: 0x00000018 (val 0x18 24) TRANS_HTOTAL_B: 0x00000018 (25 active, 1 total) TRANS_HBLANK_B: 0x00000018 (25 start, 1 end) TRANS_HSYNC_B: 0x00000018 (25 start, 1 end) TRANS_VTOTAL_B: 0x00000018 (25 active, 1 total) TRANS_VBLANK_B: 0x00000018 (25 start, 1 end) TRANS_VSYNC_B: 0x00000018 (25 start, 1 end) TRANS_VSYNCSHIFT_B: 0x00000018 TRANSB_DATA_M1: 0x00000018 (TU 1, val 0x18 24) TRANSB_DATA_N1: 0x00000018 (val 0x18 24) TRANSB_DATA_M2: 0x00000018 (TU 1, val 0x18 24) TRANSB_DATA_N2: 0x00000018 (val 0x18 24) TRANSB_DP_LINK_M1: 0x00000018 (val 0x18 24) TRANSB_DP_LINK_N1: 0x00000018 (val 0x18 24) TRANSB_DP_LINK_M2: 0x00000018 (val 0x18 24) TRANSB_DP_LINK_N2: 0x00000018 (val 0x18 24) TRANS_HTOTAL_C: 0x00000000 (1 active, 1 total) TRANS_HBLANK_C: 0x00000000 (1 start, 1 end) TRANS_HSYNC_C: 0x00000000 (1 start, 1 end) TRANS_VTOTAL_C: 0x00000000 (1 active, 1 total) TRANS_VBLANK_C: 0x00000000 (1 start, 1 end) TRANS_VSYNC_C: 0x00000000 (1 start, 1 end) TRANS_VSYNCSHIFT_C: 0x00000000 TRANSC_DATA_M1: 0x00000000 (TU 1, val 0x0 0) TRANSC_DATA_N1: 0x00000000 (val 0x0 0) TRANSC_DATA_M2: 0x00000000 (TU 1, val 0x0 0) TRANSC_DATA_N2: 0x00000000 (val 0x0 0) TRANSC_DP_LINK_M1: 0x00000000 (val 0x0 0) TRANSC_DP_LINK_N1: 0x00000000 (val 0x0 0) TRANSC_DP_LINK_M2: 0x00000000 (val 0x0 0) TRANSC_DP_LINK_N2: 0x00000000 (val 0x0 0) TRANSACONF: 0x00000018 (disable, inactive, progressive) TRANSBCONF: 0x00000018 (disable, inactive, progressive) TRANSCCONF: 0x00000018 (disable, inactive, progressive) FDI_TXA_CTL: 0x00000000 (disable, train pattern pattern_1, voltage swing 0.4V,pre-emphasis none, port width X1, enhanced framing disable, FDI PLL disable, scrambing enable, master mode disable) FDI_TXB_CTL: 0x00000000 (disable, train pattern pattern_1, voltage swing 0.4V,pre-emphasis none, port width X1, enhanced framing disable, FDI PLL disable, scrambing enable, master mode disable) FDI_TXC_CTL: 0x00000000 (disable, train pattern pattern_1, voltage swing 0.4V,pre-emphasis none, port width X1, enhanced framing disable, FDI PLL disable, scrambing enable, master mode disable) FDI_RXA_CTL: 0xffffffff (enable, train pattern not train, port width (null), (null),link_reverse_strap_overwrite yes, dmi_link_reverse yes, FDI PLL enable,FS ecc enable, FE ecc enable, FS err report enable, FE err report enable,scrambing disable, enhanced framing enable, PCDClk) FDI_RXB_CTL: 0x00000000 (disable, train pattern pattern_1, port width X1, 8bpc,link_reverse_strap_overwrite no, dmi_link_reverse no, FDI PLL disable,FS ecc disable, FE ecc disable, FS err report disable, FE err report disable,scrambing enable, enhanced framing disable, RawClk) FDI_RXC_CTL: 0xffffffff (enable, train pattern not train, port width (null), (null),link_reverse_strap_overwrite yes, dmi_link_reverse yes, FDI PLL enable,FS ecc enable, FE ecc enable, FS err report enable, FE err report enable,scrambing disable, enhanced framing enable, PCDClk) FDI_RXA_MISC: 0xffffffff (FDI Delay 8191) FDI_RXB_MISC: 0xffffffff (FDI Delay 8191) FDI_RXC_MISC: 0xffffffff (FDI Delay 8191) FDI_RXA_TUSIZE1: 0x00000000 FDI_RXA_TUSIZE2: 0x00000000 FDI_RXB_TUSIZE1: 0x00000000 FDI_RXB_TUSIZE2: 0x00000000 FDI_RXC_TUSIZE1: 0x00000000 FDI_RXC_TUSIZE2: 0x00000000 FDI_PLL_CTL_1: 0x00000000 FDI_PLL_CTL_2: 0x00000000 FDI_RXA_IIR: 0xffffffff FDI_RXA_IMR: 0xffffffff FDI_RXB_IIR: 0xffffffff FDI_RXB_IMR: 0xffffffff PCH_ADPA: 0xffffffff (enabled, transcoder B, +hsync, +vsync) HDMIB: 0x00000000 (disabled pipe A 8bpc SDVO DVI audio disabled -vsync -hsync non-detected) HDMIC: 0x00000000 (disabled pipe A 8bpc SDVO DVI audio disabled -vsync -hsync non-detected) HDMID: 0x00000000 (disabled pipe A 8bpc SDVO DVI audio disabled -vsync -hsync non-detected) PCH_LVDS: 0x00000000 (disabled, pipe A, 18 bit, 1 channel) CPU_eDP_A: 0x80000003 PCH_DP_B: 0xffffffff PCH_DP_C: 0xffffffff PCH_DP_D: 0xffffffff TRANS_DP_CTL_A: 0x00000000 (disabled, pipe A, 18 bit, 1 channel) TRANS_DP_CTL_B: 0x00000000 (disabled, pipe A, 18 bit, 1 channel) TRANS_DP_CTL_C: 0x00000000 (disabled, pipe A, 18 bit, 1 channel) BLC_PWM_CPU_CTL2: 0xe0000000 BLC_PWM_CPU_CTL: 0x03a902fd BLC_PWM_PCH_CTL1: 0x80000000 BLC_PWM_PCH_CTL2: 0x03a903a9 PCH_PP_STATUS: 0x80000008 (on, not ready, sequencing idle) PCH_PP_CONTROL: 0xabcd0007 (blacklight enabled, power down on reset, panel on) PCH_PP_ON_DELAYS: 0x07d0000a PCH_PP_OFF_DELAYS: 0x01f407d0 PCH_PP_DIVISOR: 0x0004af06 PORT_DBG: 0x00000000 (HW DRRS off) RC6_RESIDENCY_TIME: 0x9832eb4d RC6p_RESIDENCY_TIME: 0x00000000 RC6pp_RESIDENCY_TIME: 0x00000000 GEN6_RP_CONTROL: 0x00000d92 (enabled) GEN6_RPNSWREQ: 0x04000000 GEN6_RP_DOWN_TIMEOUT: 0x0000c350 GEN6_RP_INTERRUPT_LIMITS: 0x16040000 GEN6_RP_UP_THRESHOLD: 0x00002e18 GEN6_RP_UP_EI: 0x000030d4 GEN6_RP_DOWN_EI: 0x000061a8 GEN6_RP_IDLE_HYSTERSIS: 0x0000000a GEN6_RC_STATE: 0x00000000 GEN6_RC_CONTROL: 0x88040000 GEN6_RC1_WAKE_RATE_LIMIT: 0x03e80000 GEN6_RC6_WAKE_RATE_LIMIT: 0x0028001e GEN6_RC_EVALUATION_INTERVAL: 0x0001e848 GEN6_RC_IDLE_HYSTERSIS: 0x00000019 GEN6_RC_SLEEP: 0x00000000 GEN6_RC1e_THRESHOLD: 0x000003e8 GEN6_RC6_THRESHOLD: 0x0000c350 GEN6_RC_VIDEO_FREQ: 0x08000000 GEN6_PMIER: 0x00000470 GEN6_PMIMR: 0xffffff8f GEN6_PMINTRMSK: 0x0000000e HSW_PWR_WELL_CTL1: 0x40000000 HSW_PWR_WELL_CTL2: 0xc0000000 HSW_PWR_WELL_CTL3: 0x40000000 HSW_PWR_WELL_CTL4: 0x40000000 HSW_PWR_WELL_CTL5: 0x0004050f HSW_PWR_WELL_CTL6: 0x00000000 PIPE_DDI_FUNC_CTL_A: 0x00030000 PIPE_DDI_FUNC_CTL_B: 0x00030000 PIPE_DDI_FUNC_CTL_C: 0x00030000 PIPE_DDI_FUNC_CTL_EDP: 0x82210002 DP_TP_CTL_A: 0x80040300 DP_TP_CTL_B: 0x00000000 DP_TP_CTL_C: 0x00000000 DP_TP_CTL_D: 0x00000000 DP_TP_CTL_E: 0x00000000 DP_TP_STATUS_A: 0x00000000 DP_TP_STATUS_B: 0x00000000 DP_TP_STATUS_C: 0x00000000 DP_TP_STATUS_D: 0x00000000 DP_TP_STATUS_E: 0x00000000 DDI_BUF_CTL_A: 0x80000003 DDI_BUF_CTL_B: 0x00000000 DDI_BUF_CTL_C: 0x00000000 DDI_BUF_CTL_D: 0x00000000 DDI_BUF_CTL_E: 0x00000000 PIXCLK_GATE: 0x00000000 SPLL_CTL: 0x00000000 LCPLL_CTL: 0x40000037 WRPLL_CTL1: 0x10280202 WRPLL_CTL2: 0x00202418 PORT_CLK_SEL_A: 0x40000000 PORT_CLK_SEL_B: 0xe0000000 PORT_CLK_SEL_C: 0xe0000000 PORT_CLK_SEL_D: 0xe0000000 PORT_CLK_SEL_E: 0xe0000000 PIPE_CLK_SEL_A: 0x00000000 PIPE_CLK_SEL_B: 0x00000000 PIPE_CLK_SEL_C: 0x00000000 PIPE_WM_LINETIME_A: 0x0025007a PIPE_WM_LINETIME_B: 0x00000000 PIPE_WM_LINETIME_C: 0x00000000 SFUSE_STRAP: 0x00000006