Launching steam Running Steam on arch rolling 64-bit STEAM_RUNTIME is disabled by the user Installing breakpad exception handler for appid(steam)/version(1390852599_client) -------------------------------------------------------------- [2014-01-31 18:51:03] Startup - updater built Jan 25 2014 13:44:41 [2014-01-31 18:51:03] Opted in to client beta 'publicbeta' via beta file FRAG 0: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg) #0 { main_body: call void @llvm.R600.store.dummy(i32 0) ret void } declare void @llvm.R600.store.dummy(i32) attributes #0 = { "ShaderType"="0" } Shader Disassembly: EXPORT T0.____ ; C0000000 95200FFF CF_END ; 00000000 88000000 ===== SHADER #6 ========================================= PS/CAYMAN/CAYMAN ===== ===== 4 dw ===== 1 gprs ===== 1 stack ========================================== 0000 c0000000 95200fff EXPORT_DONE PIXEL 0 R0.____ 0002 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #6 OPT ===================================== PS/CAYMAN/CAYMAN ===== ===== 4 dw ===== 0 gprs ===== 0 stack ========================================== 0000 c0000000 95000fff EXPORT_DONE PIXEL 0 R0.____ 0002 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- FRAG DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg) #0 { main_body: %2 = call <4 x float> @llvm.R600.interp.const(i32 0) %3 = extractelement <4 x float> %2, i32 0 %4 = extractelement <4 x float> %2, i32 1 %5 = extractelement <4 x float> %2, i32 2 %6 = extractelement <4 x float> %2, i32 3 %7 = insertelement <4 x float> undef, float %3, i32 0 %8 = insertelement <4 x float> %7, float %4, i32 1 %9 = insertelement <4 x float> %8, float %5, i32 2 %10 = insertelement <4 x float> %9, float %6, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %10, i32 0, i32 0) ret void } ; Function Attrs: readnone declare <4 x float> @llvm.R600.interp.const(i32) #1 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } Shader Disassembly: ALU 3, @4, KC0[], KC1[] ; 00000004 A00C0000 EXPORT T0.XYZW ; C0000000 95200688 CF_END ; 00000000 88000000 PAD ; 00000000 00000000 ALU clause starting at 4: ; INTERP_LOAD_P0 T0.X, ARRAY_BASE, ; 000001C0 00007010 INTERP_LOAD_P0 T0.Y, ARRAY_BASE, ; 000001C0 20007010 INTERP_LOAD_P0 T0.Z, ARRAY_BASE, ; 000001C0 40007010 INTERP_LOAD_P0 * T0.W, ARRAY_BASE, ; 800001C0 60007010 ===== SHADER #7 ========================================= PS/CAYMAN/CAYMAN ===== ===== 16 dw ===== 1 gprs ===== 1 stack ========================================= 0000 00000004 a00c0000 ALU 4 @8 0008 000001c0 00007010 1 x: INTERP_LOAD_P0 R0.x, Param0.x 0010 000001c0 20007010 y: INTERP_LOAD_P0 R0.y, Param0.x 0012 000001c0 40007010 z: INTERP_LOAD_P0 R0.z, Param0.x 0014 800001c0 60007010 w: INTERP_LOAD_P0 R0.w, Param0.x 0002 c0000000 95200688 EXPORT_DONE PIXEL 0 R0.xyzw 0004 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #7 OPT ===================================== PS/CAYMAN/CAYMAN ===== ===== 14 dw ===== 1 gprs ===== 0 stack ========================================= 0000 00000003 a00c0000 ALU 4 @6 0006 000001c0 00007010 1 x: INTERP_LOAD_P0 R0.x, Param0.x 0008 000005c0 20007010 y: INTERP_LOAD_P0 R0.y, Param0.y 0010 000009c0 40007010 z: INTERP_LOAD_P0 R0.z, Param0.z 0012 80000dc0 60007010 w: INTERP_LOAD_P0 R0.w, Param0.w 0002 c0000000 95000688 EXPORT_DONE PIXEL 0 R0.xyzw 0004 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg) #0 { main_body: %2 = call <4 x float> @llvm.R600.interp.const(i32 0) %3 = extractelement <4 x float> %2, i32 0 %4 = extractelement <4 x float> %2, i32 1 %5 = extractelement <4 x float> %2, i32 2 %6 = extractelement <4 x float> %2, i32 3 %7 = insertelement <4 x float> undef, float %3, i32 0 %8 = insertelement <4 x float> %7, float %4, i32 1 %9 = insertelement <4 x float> %8, float %5, i32 2 %10 = insertelement <4 x float> %9, float %6, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %10, i32 0, i32 0) ret void } ; Function Attrs: readnone declare <4 x float> @llvm.R600.interp.const(i32) #1 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } Shader Disassembly: ALU 3, @4, KC0[], KC1[] ; 00000004 A00C0000 EXPORT T0.XYZW ; C0000000 95200688 CF_END ; 00000000 88000000 PAD ; 00000000 00000000 ALU clause starting at 4: ; INTERP_LOAD_P0 T0.X, ARRAY_BASE, ; 000001C0 00007010 INTERP_LOAD_P0 T0.Y, ARRAY_BASE, ; 000001C0 20007010 INTERP_LOAD_P0 T0.Z, ARRAY_BASE, ; 000001C0 40007010 INTERP_LOAD_P0 * T0.W, ARRAY_BASE, ; 800001C0 60007010 ===== SHADER #8 ========================================= PS/CAYMAN/CAYMAN ===== ===== 16 dw ===== 1 gprs ===== 1 stack ========================================= 0000 00000004 a00c0000 ALU 4 @8 0008 000001c0 00007010 1 x: INTERP_LOAD_P0 R0.x, Param0.x 0010 000001c0 20007010 y: INTERP_LOAD_P0 R0.y, Param0.x 0012 000001c0 40007010 z: INTERP_LOAD_P0 R0.z, Param0.x 0014 800001c0 60007010 w: INTERP_LOAD_P0 R0.w, Param0.x 0002 c0000000 95200688 EXPORT_DONE PIXEL 0 R0.xyzw 0004 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #8 OPT ===================================== PS/CAYMAN/CAYMAN ===== ===== 14 dw ===== 1 gprs ===== 0 stack ========================================= 0000 00000003 a00c0000 ALU 4 @6 0006 000001c0 00007010 1 x: INTERP_LOAD_P0 R0.x, Param0.x 0008 000005c0 20007010 y: INTERP_LOAD_P0 R0.y, Param0.y 0010 000009c0 40007010 z: INTERP_LOAD_P0 R0.z, Param0.z 0012 80000dc0 60007010 w: INTERP_LOAD_P0 R0.w, Param0.w 0002 c0000000 95000688 EXPORT_DONE PIXEL 0 R0.xyzw 0004 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] 0: MOV OUT[0], IN[0] 1: MOV OUT[1], IN[1] 2: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg, <4 x float> inreg) #0 { main_body: %3 = extractelement <4 x float> %1, i32 0 %4 = extractelement <4 x float> %1, i32 1 %5 = extractelement <4 x float> %1, i32 2 %6 = extractelement <4 x float> %1, i32 3 %7 = extractelement <4 x float> %2, i32 0 %8 = extractelement <4 x float> %2, i32 1 %9 = extractelement <4 x float> %2, i32 2 %10 = extractelement <4 x float> %2, i32 3 %11 = insertelement <4 x float> undef, float %3, i32 0 %12 = insertelement <4 x float> %11, float %4, i32 1 %13 = insertelement <4 x float> %12, float %5, i32 2 %14 = insertelement <4 x float> %13, float %6, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %14, i32 60, i32 1) %15 = insertelement <4 x float> undef, float %7, i32 0 %16 = insertelement <4 x float> %15, float %8, i32 1 %17 = insertelement <4 x float> %16, float %9, i32 2 %18 = insertelement <4 x float> %17, float %10, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %18, i32 0, i32 2) ret void } declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="1" } Shader Disassembly: CALL_FS ; 00000000 84C00000 EXPORT T1.XYZW ; C000A03C 95000688 EXPORT T2.XYZW ; C0014000 95200688 CF_END ; 00000000 88000000 ===== SHADER #9 ========================================= VS/CAYMAN/CAYMAN ===== ===== 8 dw ===== 3 gprs ===== 1 stack ========================================== 0000 00000000 84c00000 CALL_FS @0 0002 c000a03c 95000688 EXPORT_DONE POS 60 R1.xyzw 0004 c0014000 95200688 EXPORT_DONE PARAM 0 R2.xyzw 0006 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #9 OPT ===================================== VS/CAYMAN/CAYMAN ===== ===== 8 dw ===== 3 gprs ===== 1 stack ========================================== 0000 00000000 84c00000 CALL_FS @0 0002 c0014000 95000688 EXPORT_DONE PARAM 0 R2.xyzw 0004 c000a03c 95000688 EXPORT_DONE POS 60 R1.xyzw 0006 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- VERT DCL IN[0] DCL OUT[0], POSITION 0: MOV OUT[0], IN[0] 1: END STREAMOUT 0: MEM_STREAM0_BUF0[0..0] <- OUT[0].x ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg) #0 { main_body: %2 = extractelement <4 x float> %1, i32 0 %3 = extractelement <4 x float> %1, i32 1 %4 = extractelement <4 x float> %1, i32 2 %5 = extractelement <4 x float> %1, i32 3 %6 = insertelement <4 x float> undef, float %2, i32 0 %7 = insertelement <4 x float> %6, float %3, i32 1 %8 = insertelement <4 x float> %7, float %4, i32 2 %9 = insertelement <4 x float> %8, float %5, i32 3 call void @llvm.R600.store.stream.output(<4 x float> %9, i32 0, i32 0, i32 1) %10 = insertelement <4 x float> undef, float %2, i32 0 %11 = insertelement <4 x float> %10, float %3, i32 1 %12 = insertelement <4 x float> %11, float %4, i32 2 %13 = insertelement <4 x float> %12, float %5, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %13, i32 60, i32 1) call void @llvm.R600.store.dummy(i32 2) ret void } declare void @llvm.R600.store.stream.output(<4 x float>, i32, i32, i32) declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) declare void @llvm.R600.store.dummy(i32) attributes #0 = { "ShaderType"="1" } Shader Disassembly: CALL_FS ; 00000000 84C00000 EXPORT T1 ; 00008000 90001FFF EXPORT T1.XYZW ; C000A03C 95000688 EXPORT T0.____ ; C0004000 95200FFF CF_END ; 00000000 88000000 PAD ; 00000000 00000000 ===== SHADER #10 ======================================== VS/CAYMAN/CAYMAN ===== ===== 12 dw ===== 2 gprs ===== 1 stack ========================================= 0000 00000000 84c00000 CALL_FS @0 0002 00008000 90001fff MEM_STREAM0_BUF0 WRITE 0 R1.x___ ES:0 0004 c000a03c 95000688 EXPORT_DONE POS 60 R1.xyzw 0006 c0004000 95200fff EXPORT_DONE PARAM 0 R0.____ 0008 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #10 OPT ==================================== VS/CAYMAN/CAYMAN ===== ===== 10 dw ===== 2 gprs ===== 1 stack ========================================= 0000 00000000 84c00000 CALL_FS @0 0002 c000a03c 95000688 EXPORT_DONE POS 60 R1.xyzw 0004 00008000 90001fff MEM_STREAM0_BUF0 WRITE 0 R1.x___ ES:0 0006 c0004000 95000fff EXPORT_DONE PARAM 0 R0.____ 0008 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- FRAG DCL IN[0], GENERIC[0], CONSTANT 0: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg) #0 { main_body: %2 = call <4 x float> @llvm.R600.interp.const(i32 0) call void @llvm.R600.store.dummy(i32 0) ret void } ; Function Attrs: readnone declare <4 x float> @llvm.R600.interp.const(i32) #1 declare void @llvm.R600.store.dummy(i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } Shader Disassembly: EXPORT T0.____ ; C0000000 95200FFF CF_END ; 00000000 88000000 ===== SHADER #11 ======================================== PS/CAYMAN/CAYMAN ===== ===== 4 dw ===== 1 gprs ===== 1 stack ========================================== 0000 c0000000 95200fff EXPORT_DONE PIXEL 0 R0.____ 0002 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #11 OPT ==================================== PS/CAYMAN/CAYMAN ===== ===== 4 dw ===== 0 gprs ===== 0 stack ========================================== 0000 c0000000 95000fff EXPORT_DONE PIXEL 0 R0.____ 0002 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- FRAG 0: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg) #0 { main_body: call void @llvm.R600.store.dummy(i32 0) ret void } declare void @llvm.R600.store.dummy(i32) attributes #0 = { "ShaderType"="0" } Shader Disassembly: EXPORT T0.____ ; C0000000 95200FFF CF_END ; 00000000 88000000 ===== SHADER #17 ======================================== PS/CAYMAN/CAYMAN ===== ===== 4 dw ===== 1 gprs ===== 1 stack ========================================== 0000 c0000000 95200fff EXPORT_DONE PIXEL 0 R0.____ 0002 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #17 OPT ==================================== PS/CAYMAN/CAYMAN ===== ===== 4 dw ===== 0 gprs ===== 0 stack ========================================== 0000 c0000000 95000fff EXPORT_DONE PIXEL 0 R0.____ 0002 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- FRAG DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg) #0 { main_body: %2 = call <4 x float> @llvm.R600.interp.const(i32 0) %3 = extractelement <4 x float> %2, i32 0 %4 = extractelement <4 x float> %2, i32 1 %5 = extractelement <4 x float> %2, i32 2 %6 = extractelement <4 x float> %2, i32 3 %7 = insertelement <4 x float> undef, float %3, i32 0 %8 = insertelement <4 x float> %7, float %4, i32 1 %9 = insertelement <4 x float> %8, float %5, i32 2 %10 = insertelement <4 x float> %9, float %6, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %10, i32 0, i32 0) ret void } ; Function Attrs: readnone declare <4 x float> @llvm.R600.interp.const(i32) #1 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } Shader Disassembly: ALU 3, @4, KC0[], KC1[] ; 00000004 A00C0000 EXPORT T0.XYZW ; C0000000 95200688 CF_END ; 00000000 88000000 PAD ; 00000000 00000000 ALU clause starting at 4: ; INTERP_LOAD_P0 T0.X, ARRAY_BASE, ; 000001C0 00007010 INTERP_LOAD_P0 T0.Y, ARRAY_BASE, ; 000001C0 20007010 INTERP_LOAD_P0 T0.Z, ARRAY_BASE, ; 000001C0 40007010 INTERP_LOAD_P0 * T0.W, ARRAY_BASE, ; 800001C0 60007010 ===== SHADER #18 ======================================== PS/CAYMAN/CAYMAN ===== ===== 16 dw ===== 1 gprs ===== 1 stack ========================================= 0000 00000004 a00c0000 ALU 4 @8 0008 000001c0 00007010 1 x: INTERP_LOAD_P0 R0.x, Param0.x 0010 000001c0 20007010 y: INTERP_LOAD_P0 R0.y, Param0.x 0012 000001c0 40007010 z: INTERP_LOAD_P0 R0.z, Param0.x 0014 800001c0 60007010 w: INTERP_LOAD_P0 R0.w, Param0.x 0002 c0000000 95200688 EXPORT_DONE PIXEL 0 R0.xyzw 0004 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #18 OPT ==================================== PS/CAYMAN/CAYMAN ===== ===== 14 dw ===== 1 gprs ===== 0 stack ========================================= 0000 00000003 a00c0000 ALU 4 @6 0006 000001c0 00007010 1 x: INTERP_LOAD_P0 R0.x, Param0.x 0008 000005c0 20007010 y: INTERP_LOAD_P0 R0.y, Param0.y 0010 000009c0 40007010 z: INTERP_LOAD_P0 R0.z, Param0.z 0012 80000dc0 60007010 w: INTERP_LOAD_P0 R0.w, Param0.w 0002 c0000000 95000688 EXPORT_DONE PIXEL 0 R0.xyzw 0004 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg) #0 { main_body: %2 = call <4 x float> @llvm.R600.interp.const(i32 0) %3 = extractelement <4 x float> %2, i32 0 %4 = extractelement <4 x float> %2, i32 1 %5 = extractelement <4 x float> %2, i32 2 %6 = extractelement <4 x float> %2, i32 3 %7 = insertelement <4 x float> undef, float %3, i32 0 %8 = insertelement <4 x float> %7, float %4, i32 1 %9 = insertelement <4 x float> %8, float %5, i32 2 %10 = insertelement <4 x float> %9, float %6, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %10, i32 0, i32 0) ret void } ; Function Attrs: readnone declare <4 x float> @llvm.R600.interp.const(i32) #1 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } Shader Disassembly: ALU 3, @4, KC0[], KC1[] ; 00000004 A00C0000 EXPORT T0.XYZW ; C0000000 95200688 CF_END ; 00000000 88000000 PAD ; 00000000 00000000 ALU clause starting at 4: ; INTERP_LOAD_P0 T0.X, ARRAY_BASE, ; 000001C0 00007010 INTERP_LOAD_P0 T0.Y, ARRAY_BASE, ; 000001C0 20007010 INTERP_LOAD_P0 T0.Z, ARRAY_BASE, ; 000001C0 40007010 INTERP_LOAD_P0 * T0.W, ARRAY_BASE, ; 800001C0 60007010 ===== SHADER #19 ======================================== PS/CAYMAN/CAYMAN ===== ===== 16 dw ===== 1 gprs ===== 1 stack ========================================= 0000 00000004 a00c0000 ALU 4 @8 0008 000001c0 00007010 1 x: INTERP_LOAD_P0 R0.x, Param0.x 0010 000001c0 20007010 y: INTERP_LOAD_P0 R0.y, Param0.x 0012 000001c0 40007010 z: INTERP_LOAD_P0 R0.z, Param0.x 0014 800001c0 60007010 w: INTERP_LOAD_P0 R0.w, Param0.x 0002 c0000000 95200688 EXPORT_DONE PIXEL 0 R0.xyzw 0004 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #19 OPT ==================================== PS/CAYMAN/CAYMAN ===== ===== 14 dw ===== 1 gprs ===== 0 stack ========================================= 0000 00000003 a00c0000 ALU 4 @6 0006 000001c0 00007010 1 x: INTERP_LOAD_P0 R0.x, Param0.x 0008 000005c0 20007010 y: INTERP_LOAD_P0 R0.y, Param0.y 0010 000009c0 40007010 z: INTERP_LOAD_P0 R0.z, Param0.z 0012 80000dc0 60007010 w: INTERP_LOAD_P0 R0.w, Param0.w 0002 c0000000 95000688 EXPORT_DONE PIXEL 0 R0.xyzw 0004 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] 0: MOV OUT[0], IN[0] 1: MOV OUT[1], IN[1] 2: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg, <4 x float> inreg) #0 { main_body: %3 = extractelement <4 x float> %1, i32 0 %4 = extractelement <4 x float> %1, i32 1 %5 = extractelement <4 x float> %1, i32 2 %6 = extractelement <4 x float> %1, i32 3 %7 = extractelement <4 x float> %2, i32 0 %8 = extractelement <4 x float> %2, i32 1 %9 = extractelement <4 x float> %2, i32 2 %10 = extractelement <4 x float> %2, i32 3 %11 = insertelement <4 x float> undef, float %3, i32 0 %12 = insertelement <4 x float> %11, float %4, i32 1 %13 = insertelement <4 x float> %12, float %5, i32 2 %14 = insertelement <4 x float> %13, float %6, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %14, i32 60, i32 1) %15 = insertelement <4 x float> undef, float %7, i32 0 %16 = insertelement <4 x float> %15, float %8, i32 1 %17 = insertelement <4 x float> %16, float %9, i32 2 %18 = insertelement <4 x float> %17, float %10, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %18, i32 0, i32 2) ret void } declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="1" } Shader Disassembly: CALL_FS ; 00000000 84C00000 EXPORT T1.XYZW ; C000A03C 95000688 EXPORT T2.XYZW ; C0014000 95200688 CF_END ; 00000000 88000000 ===== SHADER #20 ======================================== VS/CAYMAN/CAYMAN ===== ===== 8 dw ===== 3 gprs ===== 1 stack ========================================== 0000 00000000 84c00000 CALL_FS @0 0002 c000a03c 95000688 EXPORT_DONE POS 60 R1.xyzw 0004 c0014000 95200688 EXPORT_DONE PARAM 0 R2.xyzw 0006 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #20 OPT ==================================== VS/CAYMAN/CAYMAN ===== ===== 8 dw ===== 3 gprs ===== 1 stack ========================================== 0000 00000000 84c00000 CALL_FS @0 0002 c0014000 95000688 EXPORT_DONE PARAM 0 R2.xyzw 0004 c000a03c 95000688 EXPORT_DONE POS 60 R1.xyzw 0006 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- VERT DCL IN[0] DCL OUT[0], POSITION 0: MOV OUT[0], IN[0] 1: END STREAMOUT 0: MEM_STREAM0_BUF0[0..0] <- OUT[0].x ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg) #0 { main_body: %2 = extractelement <4 x float> %1, i32 0 %3 = extractelement <4 x float> %1, i32 1 %4 = extractelement <4 x float> %1, i32 2 %5 = extractelement <4 x float> %1, i32 3 %6 = insertelement <4 x float> undef, float %2, i32 0 %7 = insertelement <4 x float> %6, float %3, i32 1 %8 = insertelement <4 x float> %7, float %4, i32 2 %9 = insertelement <4 x float> %8, float %5, i32 3 call void @llvm.R600.store.stream.output(<4 x float> %9, i32 0, i32 0, i32 1) %10 = insertelement <4 x float> undef, float %2, i32 0 %11 = insertelement <4 x float> %10, float %3, i32 1 %12 = insertelement <4 x float> %11, float %4, i32 2 %13 = insertelement <4 x float> %12, float %5, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %13, i32 60, i32 1) call void @llvm.R600.store.dummy(i32 2) ret void } declare void @llvm.R600.store.stream.output(<4 x float>, i32, i32, i32) declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) declare void @llvm.R600.store.dummy(i32) attributes #0 = { "ShaderType"="1" } Shader Disassembly: CALL_FS ; 00000000 84C00000 EXPORT T1 ; 00008000 90001FFF EXPORT T1.XYZW ; C000A03C 95000688 EXPORT T0.____ ; C0004000 95200FFF CF_END ; 00000000 88000000 PAD ; 00000000 00000000 ===== SHADER #21 ======================================== VS/CAYMAN/CAYMAN ===== ===== 12 dw ===== 2 gprs ===== 1 stack ========================================= 0000 00000000 84c00000 CALL_FS @0 0002 00008000 90001fff MEM_STREAM0_BUF0 WRITE 0 R1.x___ ES:0 0004 c000a03c 95000688 EXPORT_DONE POS 60 R1.xyzw 0006 c0004000 95200fff EXPORT_DONE PARAM 0 R0.____ 0008 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #21 OPT ==================================== VS/CAYMAN/CAYMAN ===== ===== 10 dw ===== 2 gprs ===== 1 stack ========================================= 0000 00000000 84c00000 CALL_FS @0 0002 c000a03c 95000688 EXPORT_DONE POS 60 R1.xyzw 0004 00008000 90001fff MEM_STREAM0_BUF0 WRITE 0 R1.x___ ES:0 0006 c0004000 95000fff EXPORT_DONE PARAM 0 R0.____ 0008 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- FRAG DCL IN[0], GENERIC[0], CONSTANT 0: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg) #0 { main_body: %2 = call <4 x float> @llvm.R600.interp.const(i32 0) call void @llvm.R600.store.dummy(i32 0) ret void } ; Function Attrs: readnone declare <4 x float> @llvm.R600.interp.const(i32) #1 declare void @llvm.R600.store.dummy(i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } Shader Disassembly: EXPORT T0.____ ; C0000000 95200FFF CF_END ; 00000000 88000000 ===== SHADER #22 ======================================== PS/CAYMAN/CAYMAN ===== ===== 4 dw ===== 1 gprs ===== 1 stack ========================================== 0000 c0000000 95200fff EXPORT_DONE PIXEL 0 R0.____ 0002 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #22 OPT ==================================== PS/CAYMAN/CAYMAN ===== ===== 4 dw ===== 0 gprs ===== 0 stack ========================================== 0000 c0000000 95000fff EXPORT_DONE PIXEL 0 R0.____ 0002 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] 0: MOV OUT[0], IN[0] 1: MOV OUT[1], IN[1] 2: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg, <4 x float> inreg) #0 { main_body: %3 = extractelement <4 x float> %1, i32 0 %4 = extractelement <4 x float> %1, i32 1 %5 = extractelement <4 x float> %1, i32 2 %6 = extractelement <4 x float> %1, i32 3 %7 = extractelement <4 x float> %2, i32 0 %8 = extractelement <4 x float> %2, i32 1 %9 = extractelement <4 x float> %2, i32 2 %10 = extractelement <4 x float> %2, i32 3 %11 = insertelement <4 x float> undef, float %3, i32 0 %12 = insertelement <4 x float> %11, float %4, i32 1 %13 = insertelement <4 x float> %12, float %5, i32 2 %14 = insertelement <4 x float> %13, float %6, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %14, i32 60, i32 1) %15 = insertelement <4 x float> undef, float %7, i32 0 %16 = insertelement <4 x float> %15, float %8, i32 1 %17 = insertelement <4 x float> %16, float %9, i32 2 %18 = insertelement <4 x float> %17, float %10, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %18, i32 0, i32 2) ret void } declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="1" } Shader Disassembly: CALL_FS ; 00000000 84C00000 EXPORT T1.XYZW ; C000A03C 95000688 EXPORT T2.XYZW ; C0014000 95200688 CF_END ; 00000000 88000000 ===== SHADER #23 ======================================== VS/CAYMAN/CAYMAN ===== ===== 8 dw ===== 3 gprs ===== 1 stack ========================================== 0000 00000000 84c00000 CALL_FS @0 0002 c000a03c 95000688 EXPORT_DONE POS 60 R1.xyzw 0004 c0014000 95200688 EXPORT_DONE PARAM 0 R2.xyzw 0006 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #23 OPT ==================================== VS/CAYMAN/CAYMAN ===== ===== 8 dw ===== 3 gprs ===== 1 stack ========================================== 0000 00000000 84c00000 CALL_FS @0 0002 c0014000 95000688 EXPORT_DONE PARAM 0 R2.xyzw 0004 c000a03c 95000688 EXPORT_DONE POS 60 R1.xyzw 0006 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] DCL OUT[2], GENERIC[10] DCL OUT[3], GENERIC[11] DCL CONST[0] IMM[0] FLT32 { 1.0000, 0.0000, -1.0000, 0.0000} 0: MOV OUT[0], IN[0] 1: MOV OUT[1], IN[1] 2: MAD OUT[2], CONST[0].xyxy, IMM[0].zyyz, IN[1].xyxy 3: MAD OUT[3], CONST[0].xyxy, IMM[0].xyyx, IN[1].xyxy 4: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg, <4 x float> inreg) #0 { main_body: %3 = extractelement <4 x float> %1, i32 0 %4 = extractelement <4 x float> %1, i32 1 %5 = extractelement <4 x float> %1, i32 2 %6 = extractelement <4 x float> %1, i32 3 %7 = extractelement <4 x float> %2, i32 0 %8 = extractelement <4 x float> %2, i32 1 %9 = extractelement <4 x float> %2, i32 2 %10 = extractelement <4 x float> %2, i32 3 %11 = load <4 x float> addrspace(8)* null %12 = extractelement <4 x float> %11, i32 0 %13 = fmul float %12, -1.000000e+00 %14 = fadd float %13, %7 %15 = load <4 x float> addrspace(8)* null %16 = extractelement <4 x float> %15, i32 1 %17 = fmul float %16, 0.000000e+00 %18 = fadd float %17, %8 %19 = load <4 x float> addrspace(8)* null %20 = extractelement <4 x float> %19, i32 0 %21 = fmul float %20, 0.000000e+00 %22 = fadd float %21, %7 %23 = load <4 x float> addrspace(8)* null %24 = extractelement <4 x float> %23, i32 1 %25 = fmul float %24, -1.000000e+00 %26 = fadd float %25, %8 %27 = load <4 x float> addrspace(8)* null %28 = extractelement <4 x float> %27, i32 0 %29 = fmul float %28, 1.000000e+00 %30 = fadd float %29, %7 %31 = load <4 x float> addrspace(8)* null %32 = extractelement <4 x float> %31, i32 1 %33 = fmul float %32, 0.000000e+00 %34 = fadd float %33, %8 %35 = load <4 x float> addrspace(8)* null %36 = extractelement <4 x float> %35, i32 0 %37 = fmul float %36, 0.000000e+00 %38 = fadd float %37, %7 %39 = load <4 x float> addrspace(8)* null %40 = extractelement <4 x float> %39, i32 1 %41 = fmul float %40, 1.000000e+00 %42 = fadd float %41, %8 %43 = insertelement <4 x float> undef, float %3, i32 0 %44 = insertelement <4 x float> %43, float %4, i32 1 %45 = insertelement <4 x float> %44, float %5, i32 2 %46 = insertelement <4 x float> %45, float %6, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %46, i32 60, i32 1) %47 = insertelement <4 x float> undef, float %7, i32 0 %48 = insertelement <4 x float> %47, float %8, i32 1 %49 = insertelement <4 x float> %48, float %9, i32 2 %50 = insertelement <4 x float> %49, float %10, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %50, i32 0, i32 2) %51 = insertelement <4 x float> undef, float %14, i32 0 %52 = insertelement <4 x float> %51, float %18, i32 1 %53 = insertelement <4 x float> %52, float %22, i32 2 %54 = insertelement <4 x float> %53, float %26, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %54, i32 1, i32 2) %55 = insertelement <4 x float> undef, float %30, i32 0 %56 = insertelement <4 x float> %55, float %34, i32 1 %57 = insertelement <4 x float> %56, float %38, i32 2 %58 = insertelement <4 x float> %57, float %42, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %58, i32 2, i32 2) ret void } declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="1" } Shader Disassembly: CALL_FS ; 00000000 84C00000 ALU 7, @8, KC0[CB0:0-32], KC1[] ; 80000008 A01C0000 EXPORT T1.XYZW ; C000A03C 95000688 EXPORT T2.XYZW ; C0014000 94C00688 EXPORT T0.XYZW ; C0004001 94C00688 EXPORT T3.XYZW ; C001C002 95200688 CF_END ; 00000000 88000000 PAD ; 00000000 00000000 ALU clause starting at 8: ; ADD T0.X, T2.X, -KC0[0].X, ; 02100002 00000010 MULADD_IEEE T0.Y, KC0[0].Y, 0.0, T2.Y, ; 001F0480 20030402 MULADD_IEEE * T0.Z, KC0[0].X, 0.0, T2.X, ; 801F0080 40030002 ADD T3.X, KC0[0].X, T2.X, ; 00004080 00600010 ADD * T0.W, T2.Y, -KC0[0].Y, ; 82900402 60000010 ADD * T3.W, KC0[0].Y, T2.Y, ; 80804480 60600010 MOV T3.Y, T0.Y, ; 00000400 20600C90 MOV * T3.Z, T0.Z, ; 80000800 40600C90 ===== SHADER #24 ======================================== VS/CAYMAN/CAYMAN ===== ===== 32 dw ===== 4 gprs ===== 1 stack ========================================= 0000 00000000 84c00000 CALL_FS @0 0002 80000008 a01c0000 ALU 8 @16 KC0[CB0:0-31] 0016 02100002 00000010 1 x: ADD R0.x, R2.x, -KC0[0].x 0018 001f0480 20030402 y: MULADD_IEEE R0.y, KC0[0].y, 0, R2.y 0020 801f0080 40030002 z: MULADD_IEEE R0.z, KC0[0].x, 0, R2.x 0022 00004080 00600010 2 x: ADD R3.x, KC0[0].x, R2.x 0024 82900402 60000010 w: ADD R0.w, R2.y, -KC0[0].y 0026 80804480 60600010 3 w: ADD R3.w, KC0[0].y, R2.y 0028 00000400 20600c90 4 y: MOV R3.y, R0.y 0030 80000800 40600c90 z: MOV R3.z, R0.z 0004 c000a03c 95000688 EXPORT_DONE POS 60 R1.xyzw 0006 c0014000 94c00688 EXPORT PARAM 0 R2.xyzw 0008 c0004001 94c00688 EXPORT PARAM 1 R0.xyzw 0010 c001c002 95200688 EXPORT_DONE PARAM 2 R3.xyzw 0012 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #24 OPT ==================================== VS/CAYMAN/CAYMAN ===== ===== 30 dw ===== 4 gprs ===== 1 stack ========================================= 0000 00000000 84c00000 CALL_FS @0 0002 40000007 a01c0000 ALU 8 @14 KC0[CB0:0-15] 0014 00004080 00000010 1 x: ADD R0.x, KC0[0].x, R2.x 0016 001f0480 20030402 y: MULADD_IEEE R0.y, KC0[0].y, 0, R2.y 0018 001f0080 40030002 z: MULADD_IEEE R0.z, KC0[0].x, 0, R2.x 0020 80804480 60000010 w: ADD R0.w, KC0[0].y, R2.y 0022 02100002 00600010 2 x: ADD R3.x, R2.x, -KC0[0].x 0024 00000400 20600c90 y: MOV R3.y, R0.y 0026 00000800 40600c90 z: MOV R3.z, R0.z 0028 82900402 60680010 w: ADD R3.w, R2.y, -KC0[0].y VEC_120 0004 c001c001 94c00688 EXPORT PARAM 1 R3.xyzw 0006 c0004002 94c00688 EXPORT PARAM 2 R0.xyzw 0008 c0014000 95000688 EXPORT_DONE PARAM 0 R2.xyzw 0010 c000a03c 95000688 EXPORT_DONE POS 60 R1.xyzw 0012 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], PERSPECTIVE DCL IN[1], GENERIC[10], PERSPECTIVE DCL IN[2], GENERIC[11], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL TEMP[0..2] IMM[0] FLT32 { 0.0030, 0.0000, 1.0000, 0.0000} 0: TEX TEMP[0].x, IN[1].xyyy, SAMP[0], 2D 1: MOV TEMP[1].x, TEMP[0].xxxx 2: TEX TEMP[0].x, IN[1].zwww, SAMP[0], 2D 3: MOV TEMP[1].y, TEMP[0].xxxx 4: TEX TEMP[0].x, IN[2].xyyy, SAMP[0], 2D 5: MOV TEMP[1].z, TEMP[0].xxxx 6: TEX TEMP[0].x, IN[2].zwww, SAMP[0], 2D 7: MOV TEMP[1].w, TEMP[0].xxxx 8: TEX TEMP[0].x, IN[0].xyyy, SAMP[0], 2D 9: ADD TEMP[2], TEMP[0].xxxx, -TEMP[1] 10: ABS TEMP[0], TEMP[2] 11: SGE TEMP[2], TEMP[0], IMM[0].xxxx 12: DP4 TEMP[0].x, TEMP[2], IMM[0].zzzz 13: SEQ TEMP[1].x, TEMP[0].xxxx, IMM[0].yyyy 14: IF TEMP[1].xxxx :16 15: KILL 16: ENDIF 17: MOV OUT[0], TEMP[2] 18: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg, <4 x float> inreg, <4 x float> inreg) #0 { main_body: %4 = extractelement <4 x float> %0, i32 0 %5 = extractelement <4 x float> %0, i32 1 %6 = call <2 x float> @llvm.R600.interp.xy(i32 0, float %4, float %5) %7 = call <2 x float> @llvm.R600.interp.zw(i32 0, float %4, float %5) %8 = shufflevector <2 x float> %6, <2 x float> %7, <4 x i32> %9 = extractelement <4 x float> %8, i32 0 %10 = extractelement <4 x float> %8, i32 1 %11 = extractelement <4 x float> %0, i32 0 %12 = extractelement <4 x float> %0, i32 1 %13 = call <2 x float> @llvm.R600.interp.xy(i32 1, float %11, float %12) %14 = call <2 x float> @llvm.R600.interp.zw(i32 1, float %11, float %12) %15 = shufflevector <2 x float> %13, <2 x float> %14, <4 x i32> %16 = extractelement <4 x float> %15, i32 0 %17 = extractelement <4 x float> %15, i32 1 %18 = extractelement <4 x float> %15, i32 2 %19 = extractelement <4 x float> %15, i32 3 %20 = extractelement <4 x float> %0, i32 0 %21 = extractelement <4 x float> %0, i32 1 %22 = call <2 x float> @llvm.R600.interp.xy(i32 2, float %20, float %21) %23 = call <2 x float> @llvm.R600.interp.zw(i32 2, float %20, float %21) %24 = shufflevector <2 x float> %22, <2 x float> %23, <4 x i32> %25 = extractelement <4 x float> %24, i32 0 %26 = extractelement <4 x float> %24, i32 1 %27 = extractelement <4 x float> %24, i32 2 %28 = extractelement <4 x float> %24, i32 3 %29 = insertelement <4 x float> undef, float %16, i32 0 %30 = insertelement <4 x float> %29, float %17, i32 1 %31 = insertelement <4 x float> %30, float %17, i32 2 %32 = insertelement <4 x float> %31, float %17, i32 3 %33 = extractelement <4 x float> %32, i32 0 %34 = extractelement <4 x float> %32, i32 1 %35 = insertelement <4 x float> undef, float %33, i32 0 %36 = insertelement <4 x float> %35, float %34, i32 1 %37 = insertelement <4 x float> %36, float undef, i32 2 %38 = insertelement <4 x float> %37, float undef, i32 3 %39 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %38, i32 16, i32 0, i32 2) %40 = extractelement <4 x float> %39, i32 0 %41 = insertelement <4 x float> undef, float %18, i32 0 %42 = insertelement <4 x float> %41, float %19, i32 1 %43 = insertelement <4 x float> %42, float %19, i32 2 %44 = insertelement <4 x float> %43, float %19, i32 3 %45 = extractelement <4 x float> %44, i32 0 %46 = extractelement <4 x float> %44, i32 1 %47 = insertelement <4 x float> undef, float %45, i32 0 %48 = insertelement <4 x float> %47, float %46, i32 1 %49 = insertelement <4 x float> %48, float undef, i32 2 %50 = insertelement <4 x float> %49, float undef, i32 3 %51 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %50, i32 16, i32 0, i32 2) %52 = extractelement <4 x float> %51, i32 0 %53 = insertelement <4 x float> undef, float %25, i32 0 %54 = insertelement <4 x float> %53, float %26, i32 1 %55 = insertelement <4 x float> %54, float %26, i32 2 %56 = insertelement <4 x float> %55, float %26, i32 3 %57 = extractelement <4 x float> %56, i32 0 %58 = extractelement <4 x float> %56, i32 1 %59 = insertelement <4 x float> undef, float %57, i32 0 %60 = insertelement <4 x float> %59, float %58, i32 1 %61 = insertelement <4 x float> %60, float undef, i32 2 %62 = insertelement <4 x float> %61, float undef, i32 3 %63 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %62, i32 16, i32 0, i32 2) %64 = extractelement <4 x float> %63, i32 0 %65 = insertelement <4 x float> undef, float %27, i32 0 %66 = insertelement <4 x float> %65, float %28, i32 1 %67 = insertelement <4 x float> %66, float %28, i32 2 %68 = insertelement <4 x float> %67, float %28, i32 3 %69 = extractelement <4 x float> %68, i32 0 %70 = extractelement <4 x float> %68, i32 1 %71 = insertelement <4 x float> undef, float %69, i32 0 %72 = insertelement <4 x float> %71, float %70, i32 1 %73 = insertelement <4 x float> %72, float undef, i32 2 %74 = insertelement <4 x float> %73, float undef, i32 3 %75 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %74, i32 16, i32 0, i32 2) %76 = extractelement <4 x float> %75, i32 0 %77 = insertelement <4 x float> undef, float %9, i32 0 %78 = insertelement <4 x float> %77, float %10, i32 1 %79 = insertelement <4 x float> %78, float %10, i32 2 %80 = insertelement <4 x float> %79, float %10, i32 3 %81 = extractelement <4 x float> %80, i32 0 %82 = extractelement <4 x float> %80, i32 1 %83 = insertelement <4 x float> undef, float %81, i32 0 %84 = insertelement <4 x float> %83, float %82, i32 1 %85 = insertelement <4 x float> %84, float undef, i32 2 %86 = insertelement <4 x float> %85, float undef, i32 3 %87 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %86, i32 16, i32 0, i32 2) %88 = extractelement <4 x float> %87, i32 0 %89 = fsub float -0.000000e+00, %40 %90 = fadd float %88, %89 %91 = fsub float -0.000000e+00, %52 %92 = fadd float %88, %91 %93 = fsub float -0.000000e+00, %64 %94 = fadd float %88, %93 %95 = fsub float -0.000000e+00, %76 %96 = fadd float %88, %95 %97 = call float @fabs(float %90) %98 = call float @fabs(float %92) %99 = call float @fabs(float %94) %100 = call float @fabs(float %96) %101 = fcmp oge float %97, 0x3F689374C0000000 %102 = select i1 %101, float 1.000000e+00, float 0.000000e+00 %103 = fcmp oge float %98, 0x3F689374C0000000 %104 = select i1 %103, float 1.000000e+00, float 0.000000e+00 %105 = fcmp oge float %99, 0x3F689374C0000000 %106 = select i1 %105, float 1.000000e+00, float 0.000000e+00 %107 = fcmp oge float %100, 0x3F689374C0000000 %108 = select i1 %107, float 1.000000e+00, float 0.000000e+00 %109 = insertelement <4 x float> undef, float %102, i32 0 %110 = insertelement <4 x float> %109, float %104, i32 1 %111 = insertelement <4 x float> %110, float %106, i32 2 %112 = insertelement <4 x float> %111, float %108, i32 3 %113 = call float @llvm.AMDGPU.dp4(<4 x float> %112, <4 x float> ) %114 = fcmp oeq float %113, 0.000000e+00 %115 = select i1 %114, float 1.000000e+00, float 0.000000e+00 %116 = fcmp une float %115, 0.000000e+00 br i1 %116, label %IF, label %ENDIF IF: ; preds = %main_body call void @llvm.AMDGPU.kilp() br label %ENDIF ENDIF: ; preds = %main_body, %IF %117 = insertelement <4 x float> undef, float %102, i32 0 %118 = insertelement <4 x float> %117, float %104, i32 1 %119 = insertelement <4 x float> %118, float %106, i32 2 %120 = insertelement <4 x float> %119, float %108, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %120, i32 0, i32 0) ret void } ; Function Attrs: readnone declare <2 x float> @llvm.R600.interp.xy(i32, float, float) #1 ; Function Attrs: readnone declare <2 x float> @llvm.R600.interp.zw(i32, float, float) #1 ; Function Attrs: readnone declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32, i32) #1 ; Function Attrs: readonly declare float @fabs(float) #2 ; Function Attrs: readnone declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1 declare void @llvm.AMDGPU.kilp() declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } attributes #2 = { readonly } Shader Disassembly: ALU 23, @18, KC0[], KC1[] ; 00000012 A05C0000 TEX 4 @8 ; 00000008 80401000 ALU_PUSH_BEFORE 18, @42, KC0[], KC1[] ; 0000002A A4480000 JUMP @5 POP:1 ; 00000005 82800001 ALU_POP_AFTER 0, @61, KC0[], KC1[] ; 0000003D A8000000 EXPORT T0.XYZW ; C0000000 95200688 CF_END ; 00000000 88000000 PAD ; 00000000 00000000 Fetch clause starting at 8: ; TEX_SAMPLE T3.XYZW, T6.XY__ RID:16 SID:0 CT:NNNN ; 00061010 F00D1003 FC800000 00000000 TEX_SAMPLE T5.XYZW, T5.XY__ RID:16 SID:0 CT:NNNN ; 00051010 F00D1005 FC800000 00000000 TEX_SAMPLE T4.XYZW, T4.XY__ RID:16 SID:0 CT:NNNN ; 00041010 F00D1004 FC800000 00000000 TEX_SAMPLE T1.XYZW, T1.XY__ RID:16 SID:0 CT:NNNN ; 00011010 F00D1001 FC800000 00000000 TEX_SAMPLE T0.XYZW, T2.XY__ RID:16 SID:0 CT:NNNN ; 00021010 F00D1000 FC800000 00000000 ALU clause starting at 18: ; INTERP_XY T1.X, T0.Y, ARRAY_BASE, ; 00380400 00346B10 INTERP_XY T1.Y, T0.X, ARRAY_BASE, ; 00380000 20346B10 INTERP_XY T0.Z (MASKED), T0.Y, ARRAY_BASE, ; 00380400 40146B00 INTERP_XY * T0.W (MASKED), T0.X, ARRAY_BASE, ; 80380000 60146B00 INTERP_XY T2.X, T0.Y, ARRAY_BASE, ; 00382400 00546B10 INTERP_XY T2.Y, T0.X, ARRAY_BASE, ; 00382000 20546B10 INTERP_XY T0.Z (MASKED), T0.Y, ARRAY_BASE, ; 00382400 40146B00 INTERP_XY * T0.W (MASKED), T0.X, ARRAY_BASE, ; 80382000 60146B00 INTERP_ZW T0.X (MASKED), T0.Y, ARRAY_BASE, ; 00382400 00146B80 INTERP_ZW T0.Y (MASKED), T0.X, ARRAY_BASE, ; 00382000 20146B80 INTERP_ZW T3.Z, T0.Y, ARRAY_BASE, ; 00382400 40746B90 INTERP_ZW * T3.W, T0.X, ARRAY_BASE, ; 80382000 60746B90 MOV * T4.X, PV.Z, ; 800008FE 00800C90 INTERP_XY T5.X, T0.Y, ARRAY_BASE, ; 00384400 00B46B10 INTERP_XY T5.Y, T0.X, ARRAY_BASE, ; 00384000 20B46B10 INTERP_XY T0.Z (MASKED), T0.Y, ARRAY_BASE, ; 00384400 40146B00 INTERP_XY * T0.W (MASKED), T0.X, ARRAY_BASE, ; 80384000 60146B00 INTERP_ZW T0.X (MASKED), T0.Y, ARRAY_BASE, ; 00384400 00146B80 INTERP_ZW T0.Y (MASKED), T0.X, ARRAY_BASE, ; 00384000 20146B80 INTERP_ZW T0.Z, T0.Y, ARRAY_BASE, ; 00384400 40146B90 INTERP_ZW * T0.W, T0.X, ARRAY_BASE, ; 80384000 60146B90 MOV T6.X, PV.Z, ; 000008FE 00C00C90 MOV * T4.Y, T3.W, ; 80000C03 20800C90 MOV * T6.Y, T0.W, ; 80000C00 20C00C90 ALU clause starting at 42: ; ADD * T0.W, T1.X, -T0.X, ; 82000001 60000010 SETGE T0.X, |PV.W|, literal.x, ; 001FACFE 00000511 ADD * T2.W, T1.X, -T4.X, ; 82008001 60400010 994352038(3.000000e-03), 0(0.000000e+00) ; 3B449BA6 00000000 SETGE T0.Y, |PV.W|, literal.x, ; 001FACFE 20000511 ADD * T2.W, T1.X, -T5.X, ; 8200A001 60400010 994352038(3.000000e-03), 0(0.000000e+00) ; 3B449BA6 00000000 SETGE T0.Z, |PV.W|, literal.x, ; 001FACFE 40000511 ADD * T1.W, T1.X, -T3.X, ; 82006001 60200010 994352038(3.000000e-03), 0(0.000000e+00) ; 3B449BA6 00000000 SETGE * T0.W, |PV.W|, literal.x, ; 801FACFE 60000511 994352038(3.000000e-03), 0(0.000000e+00) ; 3B449BA6 00000000 DOT4 T1.X, T0.X, 1.0, ; 001F2000 00205F10 DOT4 T1.Y (MASKED), T0.Y, 1.0, ; 001F2400 20205F00 DOT4 T1.Z (MASKED), T0.Z, 1.0, ; 001F2800 40205F00 DOT4 * T1.W (MASKED), T0.W, 1.0, ; 801F2C00 60205F00 SETE * T1.W, PV.X, 0.0, ; 801F00FE 60200410 SETE_DX10 * T1.W, PV.W, 0.0, ; 801F0CFE 60200610 PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002104 ALU clause starting at 61: ; KILLGT * T1.X (MASKED), 1.0, 0.0, ; 801F00F9 00201680 ===== SHADER #25 ======================================== PS/CAYMAN/CAYMAN ===== ===== 124 dw ===== 7 gprs ===== 1 stack ======================================== 0000 00000012 a05c0000 ALU 24 @36 0036 00380400 00346b10 1 x: INTERP_XY R1.x, R0.y, Param0.x VEC_210 0038 00380000 20346b10 y: INTERP_XY R1.y, R0.x, Param0.x VEC_210 0040 00380400 40146b00 z: INTERP_XY __.z, R0.y, Param0.x VEC_210 0042 80380000 60146b00 w: INTERP_XY __.w, R0.x, Param0.x VEC_210 0044 00382400 00546b10 2 x: INTERP_XY R2.x, R0.y, Param1.x VEC_210 0046 00382000 20546b10 y: INTERP_XY R2.y, R0.x, Param1.x VEC_210 0048 00382400 40146b00 z: INTERP_XY __.z, R0.y, Param1.x VEC_210 0050 80382000 60146b00 w: INTERP_XY __.w, R0.x, Param1.x VEC_210 0052 00382400 00146b80 3 x: INTERP_ZW __.x, R0.y, Param1.x VEC_210 0054 00382000 20146b80 y: INTERP_ZW __.y, R0.x, Param1.x VEC_210 0056 00382400 40746b90 z: INTERP_ZW R3.z, R0.y, Param1.x VEC_210 0058 80382000 60746b90 w: INTERP_ZW R3.w, R0.x, Param1.x VEC_210 0060 800008fe 00800c90 4 x: MOV R4.x, PV.z 0062 00384400 00b46b10 5 x: INTERP_XY R5.x, R0.y, Param2.x VEC_210 0064 00384000 20b46b10 y: INTERP_XY R5.y, R0.x, Param2.x VEC_210 0066 00384400 40146b00 z: INTERP_XY __.z, R0.y, Param2.x VEC_210 0068 80384000 60146b00 w: INTERP_XY __.w, R0.x, Param2.x VEC_210 0070 00384400 00146b80 6 x: INTERP_ZW __.x, R0.y, Param2.x VEC_210 0072 00384000 20146b80 y: INTERP_ZW __.y, R0.x, Param2.x VEC_210 0074 00384400 40146b90 z: INTERP_ZW R0.z, R0.y, Param2.x VEC_210 0076 80384000 60146b90 w: INTERP_ZW R0.w, R0.x, Param2.x VEC_210 0078 000008fe 00c00c90 7 x: MOV R6.x, PV.z 0080 80000c03 20800c90 y: MOV R4.y, R3.w 0082 80000c00 20c00c90 8 y: MOV R6.y, R0.w 0002 00000008 80401000 TEX 5 @16 0016 00061010 f00d1003 fc800000 SAMPLE R3.xyzw, R6.xy__, RID:16, SID:0 CT:NNNN 0020 00051010 f00d1005 fc800000 SAMPLE R5.xyzw, R5.xy__, RID:16, SID:0 CT:NNNN 0024 00041010 f00d1004 fc800000 SAMPLE R4.xyzw, R4.xy__, RID:16, SID:0 CT:NNNN 0028 00011010 f00d1001 fc800000 SAMPLE R1.xyzw, R1.xy__, RID:16, SID:0 CT:NNNN 0032 00021010 f00d1000 fc800000 SAMPLE R0.xyzw, R2.xy__, RID:16, SID:0 CT:NNNN 0004 0000002a a4480000 ALU_PUSH_BEFORE 19 @84 0084 82000001 60000010 9 w: ADD R0.w, R1.x, -R0.x 0086 001facfe 00000511 10 x: SETGE R0.x, |PV.w|, [0x3b449ba6 0.003].x 0088 82008001 60400010 w: ADD R2.w, R1.x, -R4.x 0090 3b449ba6 0092 001facfe 20000511 11 y: SETGE R0.y, |PV.w|, [0x3b449ba6 0.003].x 0094 8200a001 60400010 w: ADD R2.w, R1.x, -R5.x 0096 3b449ba6 0098 001facfe 40000511 12 z: SETGE R0.z, |PV.w|, [0x3b449ba6 0.003].x 0100 82006001 60200010 w: ADD R1.w, R1.x, -R3.x 0102 3b449ba6 0104 801facfe 60000511 13 w: SETGE R0.w, |PV.w|, [0x3b449ba6 0.003].x 0106 3b449ba6 0108 001f2000 00205f10 14 x: DOT4 R1.x, R0.x, 1.0 0110 001f2400 20205f00 y: DOT4 __.y, R0.y, 1.0 0112 001f2800 40205f00 z: DOT4 __.z, R0.z, 1.0 0114 801f2c00 60205f00 w: DOT4 __.w, R0.w, 1.0 0116 801f00fe 60200410 15 w: SETE R1.w, PV.x, 0 0118 801f0cfe 60200610 16 w: SETE_DX10 R1.w, PV.w, 0 0120 801f0cfe 00002104 17 M x: PRED_SETE_INT __.x, PV.w, 0 0006 00000005 82800001 JUMP @10 POP:1 0008 0000003d a8000000 ALU_POP_AFTER 1 @122 0122 801f00f9 00201680 18 x: KILLGT __.x, 1.0, 0 0010 c0000000 95200688 EXPORT_DONE PIXEL 0 R0.xyzw 0012 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #25 OPT ==================================== PS/CAYMAN/CAYMAN ===== ===== 100 dw ===== 4 gprs ===== 0 stack ======================================== 0000 00000005 a04c0000 ALU 20 @10 0010 00382400 00346b10 1 x: INTERP_XY R1.x, R0.y, Param1.x VEC_210 0012 00b82000 20346b10 y: INTERP_XY R1.y, R0.x, Param1.y VEC_210 0014 01382400 40146b00 z: INTERP_XY __.z, R0.y, Param1.z VEC_210 0016 81b82000 60146b00 w: INTERP_XY __.w, R0.x, Param1.w VEC_210 0018 00382400 00146b80 2 x: INTERP_ZW __.x, R0.y, Param1.x VEC_210 0020 00b82000 20146b80 y: INTERP_ZW __.y, R0.x, Param1.y VEC_210 0022 01382400 40146b90 z: INTERP_ZW R0.z, R0.y, Param1.z VEC_210 0024 81b82000 60146b90 w: INTERP_ZW R0.w, R0.x, Param1.w VEC_210 0026 00384400 00746b10 3 x: INTERP_XY R3.x, R0.y, Param2.x VEC_210 0028 00b84000 20746b10 y: INTERP_XY R3.y, R0.x, Param2.y VEC_210 0030 01384400 40146b00 z: INTERP_XY __.z, R0.y, Param2.z VEC_210 0032 81b84000 60146b00 w: INTERP_XY __.w, R0.x, Param2.w VEC_210 0034 00380400 00546b10 4 x: INTERP_XY R2.x, R0.y, Param0.x VEC_210 0036 00b80000 20546b10 y: INTERP_XY R2.y, R0.x, Param0.y VEC_210 0038 01380400 40146b00 z: INTERP_XY __.z, R0.y, Param0.z VEC_210 0040 81b80000 60146b00 w: INTERP_XY __.w, R0.x, Param0.w VEC_210 0042 00384400 00146b80 5 x: INTERP_ZW __.x, R0.y, Param2.x VEC_210 0044 00b84000 20146b80 y: INTERP_ZW __.y, R0.x, Param2.y VEC_210 0046 01384400 40346b90 z: INTERP_ZW R1.z, R0.y, Param2.z VEC_210 0048 81b84000 60346b90 w: INTERP_ZW R1.w, R0.x, Param2.w VEC_210 0002 0000001a 80401000 TEX 5 @52 0052 00011010 f003fe01 fda00000 SAMPLE R1.___x, R1.zw__, RID:16, SID:0 CT:NNNN 0056 00021010 f01f8e00 fc800000 SAMPLE R0._x__, R2.xy__, RID:16, SID:0 CT:NNNN 0060 00031010 f01c7e01 fc800000 SAMPLE R1.__x_, R3.xy__, RID:16, SID:0 CT:NNNN 0064 00001010 f01c7e00 fda00000 SAMPLE R0.__x_, R0.zw__, RID:16, SID:0 CT:NNNN 0068 00011010 f01ff000 fc800000 SAMPLE R0.x___, R1.xy__, RID:16, SID:0 CT:NNNN 0004 00000024 a0340000 ALU 14 @72 0072 03002400 0f840010 6 x: ADD T0.x, R0.y, -R1.z VEC_021 0074 03000400 2f800010 y: ADD T0.y, R0.y, -R0.z 0076 02000400 4f800010 z: ADD T0.z, R0.y, -R0.x 0078 83802400 6f800010 w: ADD T0.w, R0.y, -R1.w 0080 001fa87c 00000511 7 x: SETGE R0.x, |T0.z|, [0x3b449ba6 0.003].x 0082 001fa47c 20000511 y: SETGE R0.y, |T0.y|, [0x3b449ba6 0.003].x 0084 001fa07c 40000511 z: SETGE R0.z, |T0.x|, [0x3b449ba6 0.003].x 0086 801fac7c 60000511 w: SETGE R0.w, |T0.w|, [0x3b449ba6 0.003].x 0088 3b449ba6 0090 001f2000 00005f00 8 x: DOT4 __.x, R0.x, 1.0 0092 001f2400 20005f00 y: DOT4 __.y, R0.y, 1.0 0094 001f2800 40005f00 z: DOT4 __.z, R0.z, 1.0 0096 801f2c00 6f805f10 w: DOT4 T0.w, R0.w, 1.0 0098 801f0c7c 00001600 9 x: KILLE __.x, T0.w, 0 0006 c0000000 95000688 EXPORT_DONE PIXEL 0 R0.xyzw 0008 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL SAMP[1] DCL SAMP[2] DCL CONST[0] DCL TEMP[0..6] IMM[0] FLT32 { 0.0000, -0.2500, 0.0061, 0.5000} IMM[1] FLT32 { -1.5000, -2.0000, 0.9000, 1.5000} IMM[2] FLT32 { 2.0000, 1.0000, 4.0000, 33.0000} IMM[3] FLT32 { 8.0000, 0.0000, 0.0000, 0.0000} 0: MOV TEMP[0], IMM[0].xxxx 1: TEX TEMP[1], IN[0].xyyy, SAMP[1], 2D 2: MOV TEMP[2].x, TEMP[1] 3: SNE TEMP[3].x, TEMP[1].yyyy, IMM[0].xxxx 4: IF TEMP[3].xxxx :76 5: MOV TEMP[1].xy, IN[0].xyxx 6: MOV TEMP[4].x, IMM[1].xxxx 7: BGNLOOP :24 8: MUL TEMP[5].x, IMM[1].yyyy, IMM[3].xxxx 9: SLE TEMP[6].x, TEMP[4].xxxx, TEMP[5].xxxx 10: IF TEMP[6].xxxx :12 11: BRK 12: ENDIF 13: MOV TEMP[4].y, IMM[0].xxxx 14: MAD TEMP[3].xyz, CONST[0].xyyy, TEMP[4].xyyy, TEMP[1].xyyy 15: MOV TEMP[3].w, IMM[0].xxxx 16: TXL TEMP[5], TEMP[3], SAMP[2], 2D 17: MOV TEMP[3].x, TEMP[5].yyyy 18: SLT TEMP[6].x, TEMP[5].yyyy, IMM[1].zzzz 19: IF TEMP[6].xxxx :21 20: BRK 21: ENDIF 22: ADD TEMP[6].x, TEMP[4].xxxx, IMM[1].yyyy 23: MOV TEMP[4].x, TEMP[6].xxxx 24: ENDLOOP :7 25: ADD TEMP[1].x, TEMP[4].xxxx, IMM[1].wwww 26: MAD TEMP[6].x, -IMM[2].xxxx, TEMP[3].xxxx, TEMP[1].xxxx 27: MUL TEMP[1].x, IMM[1].yyyy, IMM[3].xxxx 28: MAX TEMP[4].x, TEMP[6].xxxx, TEMP[1].xxxx 29: MOV TEMP[1].x, TEMP[4].xxxx 30: MOV TEMP[3].xy, IN[0].xyxx 31: MOV TEMP[5].x, IMM[1].wwww 32: BGNLOOP :49 33: MUL TEMP[6].x, IMM[2].xxxx, IMM[3].xxxx 34: SGE TEMP[4].x, TEMP[5].xxxx, TEMP[6].xxxx 35: IF TEMP[4].xxxx :37 36: BRK 37: ENDIF 38: MOV TEMP[5].y, IMM[0].xxxx 39: MAD TEMP[4].xyz, CONST[0].xyyy, TEMP[5].xyyy, TEMP[3].xyyy 40: MOV TEMP[4].w, IMM[0].xxxx 41: TXL TEMP[6].xy, TEMP[4], SAMP[2], 2D 42: MOV TEMP[4].x, TEMP[6].yyyy 43: SLT TEMP[0].x, TEMP[6].yyyy, IMM[1].zzzz 44: IF TEMP[0].xxxx :46 45: BRK 46: ENDIF 47: ADD TEMP[6].x, TEMP[5].xxxx, IMM[2].xxxx 48: MOV TEMP[5].x, TEMP[6].xxxx 49: ENDLOOP :32 50: ADD TEMP[3].x, TEMP[5].xxxx, IMM[1].xxxx 51: MAD TEMP[5].x, IMM[2].xxxx, TEMP[4].xxxx, TEMP[3].xxxx 52: MUL TEMP[3].x, IMM[2].xxxx, IMM[3].xxxx 53: MIN TEMP[4].x, TEMP[5].xxxx, TEMP[3].xxxx 54: MOV TEMP[3].x, TEMP[1].xxxx 55: MOV TEMP[3].y, TEMP[4].xxxx 56: MOV TEMP[5].yw, IMM[0].yyyy 57: MOV TEMP[5].x, TEMP[1].xxxx 58: ADD TEMP[1].x, TEMP[4].xxxx, IMM[2].yyyy 59: MOV TEMP[5].z, TEMP[1].xxxx 60: MAD TEMP[1], TEMP[5], CONST[0].xyxy, IN[0].xyxy 61: MOV TEMP[4], TEMP[1].xyyy 62: MOV TEMP[4].w, IMM[0].xxxx 63: TXL TEMP[5].x, TEMP[4], SAMP[2], 2D 64: MOV TEMP[4].x, TEMP[5].xxxx 65: MOV TEMP[5], TEMP[1].zwww 66: MOV TEMP[5].w, IMM[0].xxxx 67: TXL TEMP[1].x, TEMP[5], SAMP[2], 2D 68: MOV TEMP[4].y, TEMP[1].xxxx 69: MUL TEMP[5].xy, IMM[2].zzzz, TEMP[4].xyyy 70: ROUND TEMP[1].xy, TEMP[5].xyyy 71: ABS TEMP[4].xy, TEMP[3].xyyy 72: MAD TEMP[3].xy, IMM[2].wwww, TEMP[1].xyyy, TEMP[4].xyyy 73: MUL TEMP[5].xyz, TEMP[3].xyyy, IMM[0].zzzz 74: MOV TEMP[5].w, IMM[0].xxxx 75: TXL TEMP[0].xy, TEMP[5], SAMP[0], 2D 76: ENDIF 77: SNE TEMP[1].x, TEMP[2].xxxx, IMM[0].xxxx 78: IF TEMP[1].xxxx :151 79: MOV TEMP[1].xy, IN[0].xyxx 80: MOV TEMP[3].x, IMM[1].xxxx 81: BGNLOOP :98 82: MUL TEMP[4].x, IMM[1].yyyy, IMM[3].xxxx 83: SLE TEMP[5].x, TEMP[3].xxxx, TEMP[4].xxxx 84: IF TEMP[5].xxxx :86 85: BRK 86: ENDIF 87: MOV TEMP[3].y, IMM[0].xxxx 88: MAD TEMP[5].xyz, CONST[0].xyyy, TEMP[3].yxxx, TEMP[1].xyyy 89: MOV TEMP[5].w, IMM[0].xxxx 90: TXL TEMP[4], TEMP[5], SAMP[2], 2D 91: MOV TEMP[2].x, TEMP[4].xxxx 92: SLT TEMP[5].x, TEMP[4].xxxx, IMM[1].zzzz 93: IF TEMP[5].xxxx :95 94: BRK 95: ENDIF 96: ADD TEMP[4].x, TEMP[3].xxxx, IMM[1].yyyy 97: MOV TEMP[3].x, TEMP[4].xxxx 98: ENDLOOP :81 99: ADD TEMP[1].x, TEMP[3].xxxx, IMM[1].wwww 100: MAD TEMP[6].x, -IMM[2].xxxx, TEMP[2].xxxx, TEMP[1].xxxx 101: MUL TEMP[1].x, IMM[1].yyyy, IMM[3].xxxx 102: MAX TEMP[3].x, TEMP[6].xxxx, TEMP[1].xxxx 103: MOV TEMP[1].x, TEMP[3].xxxx 104: MOV TEMP[2].xy, IN[0].xyxx 105: MOV TEMP[4].x, IMM[1].wwww 106: BGNLOOP :123 107: MUL TEMP[5].x, IMM[2].xxxx, IMM[3].xxxx 108: SGE TEMP[6].x, TEMP[4].xxxx, TEMP[5].xxxx 109: IF TEMP[6].xxxx :111 110: BRK 111: ENDIF 112: MOV TEMP[4].y, IMM[0].xxxx 113: MAD TEMP[5].xyz, CONST[0].xyyy, TEMP[4].yxxx, TEMP[2].xyyy 114: MOV TEMP[5].w, IMM[0].xxxx 115: TXL TEMP[6], TEMP[5], SAMP[2], 2D 116: MOV TEMP[3].x, TEMP[6].xxxx 117: SLT TEMP[5].x, TEMP[6].xxxx, IMM[1].zzzz 118: IF TEMP[5].xxxx :120 119: BRK 120: ENDIF 121: ADD TEMP[6].x, TEMP[4].xxxx, IMM[2].xxxx 122: MOV TEMP[4].x, TEMP[6].xxxx 123: ENDLOOP :106 124: ADD TEMP[2].x, TEMP[4].xxxx, IMM[1].xxxx 125: MAD TEMP[4].x, IMM[2].xxxx, TEMP[3].xxxx, TEMP[2].xxxx 126: MUL TEMP[2].x, IMM[2].xxxx, IMM[3].xxxx 127: MIN TEMP[3].x, TEMP[4].xxxx, TEMP[2].xxxx 128: MOV TEMP[2].x, TEMP[1].xxxx 129: MOV TEMP[2].y, TEMP[3].xxxx 130: MOV TEMP[4].xz, IMM[0].yyyy 131: MOV TEMP[4].y, TEMP[1].xxxx 132: ADD TEMP[1].x, TEMP[3].xxxx, IMM[2].yyyy 133: MOV TEMP[4].w, TEMP[1].xxxx 134: MAD TEMP[1], TEMP[4], CONST[0].xyxy, IN[0].xyxy 135: MOV TEMP[3], TEMP[1].xyyy 136: MOV TEMP[3].w, IMM[0].xxxx 137: TXL TEMP[4].y, TEMP[3], SAMP[2], 2D 138: MOV TEMP[3].x, TEMP[4].yyyy 139: MOV TEMP[4], TEMP[1].zwww 140: MOV TEMP[4].w, IMM[0].xxxx 141: TXL TEMP[1].y, TEMP[4], SAMP[2], 2D 142: MOV TEMP[3].y, TEMP[1].yyyy 143: MUL TEMP[4].xy, IMM[2].zzzz, TEMP[3].xyyy 144: ROUND TEMP[1].xy, TEMP[4].xyyy 145: ABS TEMP[3].xy, TEMP[2].xyyy 146: MAD TEMP[2].xy, IMM[2].wwww, TEMP[1].xyyy, TEMP[3].xyyy 147: MUL TEMP[3].xyz, TEMP[2].xyyy, IMM[0].zzzz 148: MOV TEMP[3].w, IMM[0].xxxx 149: TXL TEMP[1].xy, TEMP[3], SAMP[0], 2D 150: MOV TEMP[0].zw, TEMP[1].yyxy 151: ENDIF 152: MOV OUT[0], TEMP[0] 153: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg) #0 { main_body: %2 = extractelement <4 x float> %0, i32 0 %3 = extractelement <4 x float> %0, i32 1 %4 = call <2 x float> @llvm.R600.interp.xy(i32 0, float %2, float %3) %5 = call <2 x float> @llvm.R600.interp.zw(i32 0, float %2, float %3) %6 = shufflevector <2 x float> %4, <2 x float> %5, <4 x i32> %7 = extractelement <4 x float> %6, i32 0 %8 = extractelement <4 x float> %6, i32 1 %9 = insertelement <4 x float> undef, float %7, i32 0 %10 = insertelement <4 x float> %9, float %8, i32 1 %11 = insertelement <4 x float> %10, float %8, i32 2 %12 = insertelement <4 x float> %11, float %8, i32 3 %13 = extractelement <4 x float> %12, i32 0 %14 = extractelement <4 x float> %12, i32 1 %15 = insertelement <4 x float> undef, float %13, i32 0 %16 = insertelement <4 x float> %15, float %14, i32 1 %17 = insertelement <4 x float> %16, float undef, i32 2 %18 = insertelement <4 x float> %17, float undef, i32 3 %19 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %18, i32 17, i32 1, i32 2) %20 = extractelement <4 x float> %19, i32 0 %21 = extractelement <4 x float> %19, i32 1 %22 = fcmp une float %21, 0.000000e+00 %23 = select i1 %22, float 1.000000e+00, float 0.000000e+00 %24 = fcmp une float %23, 0.000000e+00 br i1 %24, label %LOOP, label %ENDIF ENDIF: ; preds = %main_body, %ENDLOOP34 %temp.0 = phi float [ %113, %ENDLOOP34 ], [ 0.000000e+00, %main_body ] %temp1.0 = phi float [ %114, %ENDLOOP34 ], [ 0.000000e+00, %main_body ] %25 = fcmp une float %20, 0.000000e+00 %26 = select i1 %25, float 1.000000e+00, float 0.000000e+00 %27 = fcmp une float %26, 0.000000e+00 br i1 %27, label %LOOP46, label %ENDIF42 LOOP: ; preds = %main_body, %ENDIF31 %temp12.0 = phi float [ %53, %ENDIF31 ], [ %23, %main_body ] %temp16.0 = phi float [ %57, %ENDIF31 ], [ -1.500000e+00, %main_body ] %28 = fcmp ole float %temp16.0, -1.600000e+01 %29 = select i1 %28, float 1.000000e+00, float 0.000000e+00 %30 = fcmp une float %29, 0.000000e+00 br i1 %30, label %ENDLOOP, label %ENDIF28 ENDLOOP: ; preds = %ENDIF28, %LOOP %temp12.1 = phi float [ %temp12.0, %LOOP ], [ %53, %ENDIF28 ] %31 = fadd float %temp16.0, 1.500000e+00 %32 = fmul float -2.000000e+00, %temp12.1 %33 = fadd float %32, %31 %34 = fcmp uge float %33, -1.600000e+01 %35 = select i1 %34, float %33, float -1.600000e+01 br label %LOOP35 ENDIF28: ; preds = %LOOP %36 = load <4 x float> addrspace(8)* null %37 = extractelement <4 x float> %36, i32 0 %38 = fmul float %37, %temp16.0 %39 = fadd float %38, %7 %40 = load <4 x float> addrspace(8)* null %41 = extractelement <4 x float> %40, i32 1 %42 = fmul float %41, 0.000000e+00 %43 = fadd float %42, %8 %44 = load <4 x float> addrspace(8)* null %45 = extractelement <4 x float> %44, i32 1 %46 = fmul float %45, 0.000000e+00 %47 = fadd float %46, %8 %48 = insertelement <4 x float> undef, float %39, i32 0 %49 = insertelement <4 x float> %48, float %43, i32 1 %50 = insertelement <4 x float> %49, float %47, i32 2 %51 = insertelement <4 x float> %50, float 0.000000e+00, i32 3 %52 = call <4 x float> @llvm.AMDGPU.txl(<4 x float> %51, i32 18, i32 2, i32 2) %53 = extractelement <4 x float> %52, i32 1 %54 = fcmp olt float %53, 0x3FECCCCCC0000000 %55 = select i1 %54, float 1.000000e+00, float 0.000000e+00 %56 = fcmp une float %55, 0.000000e+00 br i1 %56, label %ENDLOOP, label %ENDIF31 ENDIF31: ; preds = %ENDIF28 %57 = fadd float %temp16.0, -2.000000e+00 br label %LOOP LOOP35: ; preds = %ENDIF39, %ENDLOOP %temp20.0 = phi float [ 1.500000e+00, %ENDLOOP ], [ %136, %ENDIF39 ] %58 = fcmp oge float %temp20.0, 1.600000e+01 %59 = select i1 %58, float 1.000000e+00, float 0.000000e+00 %60 = fcmp une float %59, 0.000000e+00 br i1 %60, label %ENDLOOP34, label %ENDIF36 ENDLOOP34: ; preds = %ENDIF36, %LOOP35 %temp16.1 = phi float [ %59, %LOOP35 ], [ %132, %ENDIF36 ] %61 = fadd float %temp20.0, -1.500000e+00 %62 = fmul float 2.000000e+00, %temp16.1 %63 = fadd float %62, %61 %64 = fcmp uge float %63, 1.600000e+01 %65 = select i1 %64, float 1.600000e+01, float %63 %66 = fadd float %65, 1.000000e+00 %67 = load <4 x float> addrspace(8)* null %68 = extractelement <4 x float> %67, i32 0 %69 = fmul float %35, %68 %70 = fadd float %69, %7 %71 = load <4 x float> addrspace(8)* null %72 = extractelement <4 x float> %71, i32 1 %73 = fmul float -2.500000e-01, %72 %74 = fadd float %73, %8 %75 = load <4 x float> addrspace(8)* null %76 = extractelement <4 x float> %75, i32 0 %77 = fmul float %66, %76 %78 = fadd float %77, %7 %79 = load <4 x float> addrspace(8)* null %80 = extractelement <4 x float> %79, i32 1 %81 = fmul float -2.500000e-01, %80 %82 = fadd float %81, %8 %83 = insertelement <4 x float> undef, float %70, i32 0 %84 = insertelement <4 x float> %83, float %74, i32 1 %85 = insertelement <4 x float> %84, float %74, i32 2 %86 = insertelement <4 x float> %85, float 0.000000e+00, i32 3 %87 = call <4 x float> @llvm.AMDGPU.txl(<4 x float> %86, i32 18, i32 2, i32 2) %88 = extractelement <4 x float> %87, i32 0 %89 = insertelement <4 x float> undef, float %78, i32 0 %90 = insertelement <4 x float> %89, float %82, i32 1 %91 = insertelement <4 x float> %90, float %82, i32 2 %92 = insertelement <4 x float> %91, float 0.000000e+00, i32 3 %93 = call <4 x float> @llvm.AMDGPU.txl(<4 x float> %92, i32 18, i32 2, i32 2) %94 = extractelement <4 x float> %93, i32 0 %95 = fmul float 4.000000e+00, %88 %96 = fmul float 4.000000e+00, %94 %97 = call float @llvm.AMDIL.round.nearest.(float %95) %98 = call float @llvm.AMDIL.round.nearest.(float %96) %99 = call float @fabs(float %35) %100 = call float @fabs(float %65) %101 = fmul float 3.300000e+01, %97 %102 = fadd float %101, %99 %103 = fmul float 3.300000e+01, %98 %104 = fadd float %103, %100 %105 = fmul float %102, 0x3F78F9C140000000 %106 = fmul float %104, 0x3F78F9C140000000 %107 = fmul float %104, 0x3F78F9C140000000 %108 = insertelement <4 x float> undef, float %105, i32 0 %109 = insertelement <4 x float> %108, float %106, i32 1 %110 = insertelement <4 x float> %109, float %107, i32 2 %111 = insertelement <4 x float> %110, float 0.000000e+00, i32 3 %112 = call <4 x float> @llvm.AMDGPU.txl(<4 x float> %111, i32 16, i32 0, i32 2) %113 = extractelement <4 x float> %112, i32 0 %114 = extractelement <4 x float> %112, i32 1 br label %ENDIF ENDIF36: ; preds = %LOOP35 %115 = load <4 x float> addrspace(8)* null %116 = extractelement <4 x float> %115, i32 0 %117 = fmul float %116, %temp20.0 %118 = fadd float %117, %7 %119 = load <4 x float> addrspace(8)* null %120 = extractelement <4 x float> %119, i32 1 %121 = fmul float %120, 0.000000e+00 %122 = fadd float %121, %8 %123 = load <4 x float> addrspace(8)* null %124 = extractelement <4 x float> %123, i32 1 %125 = fmul float %124, 0.000000e+00 %126 = fadd float %125, %8 %127 = insertelement <4 x float> undef, float %118, i32 0 %128 = insertelement <4 x float> %127, float %122, i32 1 %129 = insertelement <4 x float> %128, float %126, i32 2 %130 = insertelement <4 x float> %129, float 0.000000e+00, i32 3 %131 = call <4 x float> @llvm.AMDGPU.txl(<4 x float> %130, i32 18, i32 2, i32 2) %132 = extractelement <4 x float> %131, i32 1 %133 = fcmp olt float %132, 0x3FECCCCCC0000000 %134 = select i1 %133, float 1.000000e+00, float 0.000000e+00 %135 = fcmp une float %134, 0.000000e+00 br i1 %135, label %ENDLOOP34, label %ENDIF39 ENDIF39: ; preds = %ENDIF36 %136 = fadd float %temp20.0, 2.000000e+00 br label %LOOP35 ENDIF42: ; preds = %ENDIF, %ENDLOOP53 %temp2.0 = phi float [ %226, %ENDLOOP53 ], [ 0.000000e+00, %ENDIF ] %temp3.0 = phi float [ %227, %ENDLOOP53 ], [ 0.000000e+00, %ENDIF ] %137 = insertelement <4 x float> undef, float %temp.0, i32 0 %138 = insertelement <4 x float> %137, float %temp1.0, i32 1 %139 = insertelement <4 x float> %138, float %temp2.0, i32 2 %140 = insertelement <4 x float> %139, float %temp3.0, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %140, i32 0, i32 0) ret void LOOP46: ; preds = %ENDIF, %ENDIF50 %temp8.0 = phi float [ %166, %ENDIF50 ], [ %20, %ENDIF ] %temp12.2 = phi float [ %170, %ENDIF50 ], [ -1.500000e+00, %ENDIF ] %141 = fcmp ole float %temp12.2, -1.600000e+01 %142 = select i1 %141, float 1.000000e+00, float 0.000000e+00 %143 = fcmp une float %142, 0.000000e+00 br i1 %143, label %ENDLOOP45, label %ENDIF47 ENDLOOP45: ; preds = %ENDIF47, %LOOP46 %temp8.1 = phi float [ %temp8.0, %LOOP46 ], [ %166, %ENDIF47 ] %144 = fadd float %temp12.2, 1.500000e+00 %145 = fmul float -2.000000e+00, %temp8.1 %146 = fadd float %145, %144 %147 = fcmp uge float %146, -1.600000e+01 %148 = select i1 %147, float %146, float -1.600000e+01 br label %LOOP54 ENDIF47: ; preds = %LOOP46 %149 = load <4 x float> addrspace(8)* null %150 = extractelement <4 x float> %149, i32 0 %151 = fmul float %150, 0.000000e+00 %152 = fadd float %151, %7 %153 = load <4 x float> addrspace(8)* null %154 = extractelement <4 x float> %153, i32 1 %155 = fmul float %154, %temp12.2 %156 = fadd float %155, %8 %157 = load <4 x float> addrspace(8)* null %158 = extractelement <4 x float> %157, i32 1 %159 = fmul float %158, %temp12.2 %160 = fadd float %159, %8 %161 = insertelement <4 x float> undef, float %152, i32 0 %162 = insertelement <4 x float> %161, float %156, i32 1 %163 = insertelement <4 x float> %162, float %160, i32 2 %164 = insertelement <4 x float> %163, float 0.000000e+00, i32 3 %165 = call <4 x float> @llvm.AMDGPU.txl(<4 x float> %164, i32 18, i32 2, i32 2) %166 = extractelement <4 x float> %165, i32 0 %167 = fcmp olt float %166, 0x3FECCCCCC0000000 %168 = select i1 %167, float 1.000000e+00, float 0.000000e+00 %169 = fcmp une float %168, 0.000000e+00 br i1 %169, label %ENDLOOP45, label %ENDIF50 ENDIF50: ; preds = %ENDIF47 %170 = fadd float %temp12.2, -2.000000e+00 br label %LOOP46 LOOP54: ; preds = %ENDIF58, %ENDLOOP45 %temp12.3 = phi float [ %148, %ENDLOOP45 ], [ %245, %ENDIF58 ] %temp16.2 = phi float [ 1.500000e+00, %ENDLOOP45 ], [ %249, %ENDIF58 ] %171 = fcmp oge float %temp16.2, 1.600000e+01 %172 = select i1 %171, float 1.000000e+00, float 0.000000e+00 %173 = fcmp une float %172, 0.000000e+00 br i1 %173, label %ENDLOOP53, label %ENDIF55 ENDLOOP53: ; preds = %ENDIF55, %LOOP54 %temp12.4 = phi float [ %temp12.3, %LOOP54 ], [ %245, %ENDIF55 ] %174 = fadd float %temp16.2, -1.500000e+00 %175 = fmul float 2.000000e+00, %temp12.4 %176 = fadd float %175, %174 %177 = fcmp uge float %176, 1.600000e+01 %178 = select i1 %177, float 1.600000e+01, float %176 %179 = fadd float %178, 1.000000e+00 %180 = load <4 x float> addrspace(8)* null %181 = extractelement <4 x float> %180, i32 0 %182 = fmul float -2.500000e-01, %181 %183 = fadd float %182, %7 %184 = load <4 x float> addrspace(8)* null %185 = extractelement <4 x float> %184, i32 1 %186 = fmul float %148, %185 %187 = fadd float %186, %8 %188 = load <4 x float> addrspace(8)* null %189 = extractelement <4 x float> %188, i32 0 %190 = fmul float -2.500000e-01, %189 %191 = fadd float %190, %7 %192 = load <4 x float> addrspace(8)* null %193 = extractelement <4 x float> %192, i32 1 %194 = fmul float %179, %193 %195 = fadd float %194, %8 %196 = insertelement <4 x float> undef, float %183, i32 0 %197 = insertelement <4 x float> %196, float %187, i32 1 %198 = insertelement <4 x float> %197, float %187, i32 2 %199 = insertelement <4 x float> %198, float 0.000000e+00, i32 3 %200 = call <4 x float> @llvm.AMDGPU.txl(<4 x float> %199, i32 18, i32 2, i32 2) %201 = extractelement <4 x float> %200, i32 1 %202 = insertelement <4 x float> undef, float %191, i32 0 %203 = insertelement <4 x float> %202, float %195, i32 1 %204 = insertelement <4 x float> %203, float %195, i32 2 %205 = insertelement <4 x float> %204, float 0.000000e+00, i32 3 %206 = call <4 x float> @llvm.AMDGPU.txl(<4 x float> %205, i32 18, i32 2, i32 2) %207 = extractelement <4 x float> %206, i32 1 %208 = fmul float 4.000000e+00, %201 %209 = fmul float 4.000000e+00, %207 %210 = call float @llvm.AMDIL.round.nearest.(float %208) %211 = call float @llvm.AMDIL.round.nearest.(float %209) %212 = call float @fabs(float %148) %213 = call float @fabs(float %178) %214 = fmul float 3.300000e+01, %210 %215 = fadd float %214, %212 %216 = fmul float 3.300000e+01, %211 %217 = fadd float %216, %213 %218 = fmul float %215, 0x3F78F9C140000000 %219 = fmul float %217, 0x3F78F9C140000000 %220 = fmul float %217, 0x3F78F9C140000000 %221 = insertelement <4 x float> undef, float %218, i32 0 %222 = insertelement <4 x float> %221, float %219, i32 1 %223 = insertelement <4 x float> %222, float %220, i32 2 %224 = insertelement <4 x float> %223, float 0.000000e+00, i32 3 %225 = call <4 x float> @llvm.AMDGPU.txl(<4 x float> %224, i32 16, i32 0, i32 2) %226 = extractelement <4 x float> %225, i32 0 %227 = extractelement <4 x float> %225, i32 1 br label %ENDIF42 ENDIF55: ; preds = %LOOP54 %228 = load <4 x float> addrspace(8)* null %229 = extractelement <4 x float> %228, i32 0 %230 = fmul float %229, 0.000000e+00 %231 = fadd float %230, %7 %232 = load <4 x float> addrspace(8)* null %233 = extractelement <4 x float> %232, i32 1 %234 = fmul float %233, %temp16.2 %235 = fadd float %234, %8 %236 = load <4 x float> addrspace(8)* null %237 = extractelement <4 x float> %236, i32 1 %238 = fmul float %237, %temp16.2 %239 = fadd float %238, %8 %240 = insertelement <4 x float> undef, float %231, i32 0 %241 = insertelement <4 x float> %240, float %235, i32 1 %242 = insertelement <4 x float> %241, float %239, i32 2 %243 = insertelement <4 x float> %242, float 0.000000e+00, i32 3 %244 = call <4 x float> @llvm.AMDGPU.txl(<4 x float> %243, i32 18, i32 2, i32 2) %245 = extractelement <4 x float> %244, i32 0 %246 = fcmp olt float %245, 0x3FECCCCCC0000000 %247 = select i1 %246, float 1.000000e+00, float 0.000000e+00 %248 = fcmp une float %247, 0.000000e+00 br i1 %248, label %ENDLOOP53, label %ENDIF58 ENDIF58: ; preds = %ENDIF55 %249 = fadd float %temp16.2, 2.000000e+00 br label %LOOP54 } ; Function Attrs: readnone declare <2 x float> @llvm.R600.interp.xy(i32, float, float) #1 ; Function Attrs: readnone declare <2 x float> @llvm.R600.interp.zw(i32, float, float) #1 ; Function Attrs: readnone declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32, i32) #1 ; Function Attrs: readnone declare <4 x float> @llvm.AMDGPU.txl(<4 x float>, i32, i32, i32) #1 ; Function Attrs: readnone declare float @llvm.AMDIL.round.nearest.(float) #1 ; Function Attrs: readonly declare float @fabs(float) #2 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } attributes #2 = { readonly } Shader Disassembly: ALU 3, @122, KC0[], KC1[] ; 0000007A A00C0000 TEX 0 @100 ; 00000064 80400000 ALU_PUSH_BEFORE 2, @126, KC0[], KC1[] ; 0000007E A4080000 JUMP @5 POP:0 ; 00000005 82800000 ALU 2, @129, KC0[], KC1[] ; 00000081 A0080000 ELSE @48 POP:1 ; 00000030 83400001 ALU 1, @132, KC0[], KC1[] ; 00000084 A0040000 LOOP_START_DX10 @25 ; 00000019 81800000 ALU_PUSH_BEFORE 4, @134, KC0[], KC1[] ; 00000086 A4100000 JUMP @11 POP:0 ; 0000000B 82800000 ALU 1, @139, KC0[], KC1[] ; 0000008B A0040000 ELSE @20 POP:1 ; 00000014 83400001 ALU 1, @141, KC0[CB0:0-32], KC1[] ; 8000008D A0040000 TEX 0 @102 ; 00000066 80400000 ALU_PUSH_BEFORE 3, @143, KC0[], KC1[] ; 0000008F A40C0000 JUMP @17 POP:0 ; 00000011 82800000 ALU 1, @147, KC0[], KC1[] ; 00000093 A0040000 ELSE @19 POP:1 ; 00000013 83400001 ALU_POP_AFTER 2, @149, KC0[], KC1[] ; 00000095 A8080000 POP @20 POP:1 ; 00000014 83800001 ALU_PUSH_BEFORE 4, @152, KC0[], KC1[] ; 00000098 A4100000 JUMP @24 POP:1 ; 00000018 82800001 LOOP_BREAK @24 ; 00000018 82400000 POP @24 POP:1 ; 00000018 83800001 END_LOOP @8 ; 00000008 81400000 ALU 6, @157, KC0[], KC1[] ; 0000009D A0180000 LOOP_START_DX10 @44 ; 0000002C 81800000 ALU_PUSH_BEFORE 4, @164, KC0[], KC1[] ; 000000A4 A4100000 JUMP @30 POP:0 ; 0000001E 82800000 ALU 1, @169, KC0[], KC1[] ; 000000A9 A0040000 ELSE @39 POP:1 ; 00000027 83400001 ALU 1, @171, KC0[CB0:0-32], KC1[] ; 800000AB A0040000 TEX 0 @104 ; 00000068 80400000 ALU_PUSH_BEFORE 3, @173, KC0[], KC1[] ; 000000AD A40C0000 JUMP @36 POP:0 ; 00000024 82800000 ALU 1, @177, KC0[], KC1[] ; 000000B1 A0040000 ELSE @38 POP:1 ; 00000026 83400001 ALU_POP_AFTER 2, @179, KC0[], KC1[] ; 000000B3 A8080000 POP @39 POP:1 ; 00000027 83800001 ALU_PUSH_BEFORE 4, @182, KC0[], KC1[] ; 000000B6 A4100000 JUMP @43 POP:1 ; 0000002B 82800001 LOOP_BREAK @43 ; 0000002B 82400000 POP @43 POP:1 ; 0000002B 83800001 END_LOOP @27 ; 0000001B 81400000 ALU 11, @187, KC0[CB0:0-32], KC1[] ; 800000BB A02C0000 TEX 1 @106 ; 0000006A 80400400 ALU_POP_AFTER 14, @199, KC0[], KC1[] ; 000000C7 A8380000 TEX 0 @110 ; 0000006E 80400000 ALU_PUSH_BEFORE 2, @214, KC0[], KC1[] ; 000000D6 A4080000 JUMP @51 POP:0 ; 00000033 82800000 ALU 2, @217, KC0[], KC1[] ; 000000D9 A0080000 ELSE @96 POP:1 ; 00000060 83400001 ALU 1, @220, KC0[], KC1[] ; 000000DC A0040000 LOOP_START_DX10 @71 ; 00000047 81800000 ALU_PUSH_BEFORE 4, @222, KC0[], KC1[] ; 000000DE A4100000 JUMP @57 POP:0 ; 00000039 82800000 ALU 1, @227, KC0[], KC1[] ; 000000E3 A0040000 ELSE @66 POP:1 ; 00000042 83400001 ALU 1, @229, KC0[CB0:0-32], KC1[] ; 800000E5 A0040000 TEX 0 @112 ; 00000070 80400000 ALU_PUSH_BEFORE 3, @231, KC0[], KC1[] ; 000000E7 A40C0000 JUMP @63 POP:0 ; 0000003F 82800000 ALU 1, @235, KC0[], KC1[] ; 000000EB A0040000 ELSE @65 POP:1 ; 00000041 83400001 ALU_POP_AFTER 2, @237, KC0[], KC1[] ; 000000ED A8080000 POP @66 POP:1 ; 00000042 83800001 ALU_PUSH_BEFORE 4, @240, KC0[], KC1[] ; 000000F0 A4100000 JUMP @70 POP:1 ; 00000046 82800001 LOOP_BREAK @70 ; 00000046 82400000 POP @70 POP:1 ; 00000046 83800001 END_LOOP @54 ; 00000036 81400000 ALU 8, @245, KC0[], KC1[] ; 000000F5 A0200000 LOOP_START_DX10 @90 ; 0000005A 81800000 ALU_PUSH_BEFORE 4, @254, KC0[], KC1[] ; 000000FE A4100000 JUMP @76 POP:0 ; 0000004C 82800000 ALU 1, @259, KC0[], KC1[] ; 00000103 A0040000 ELSE @85 POP:1 ; 00000055 83400001 ALU 1, @261, KC0[CB0:0-32], KC1[] ; 80000105 A0040000 TEX 0 @114 ; 00000072 80400000 ALU_PUSH_BEFORE 3, @263, KC0[], KC1[] ; 00000107 A40C0000 JUMP @82 POP:0 ; 00000052 82800000 ALU 1, @267, KC0[], KC1[] ; 0000010B A0040000 ELSE @84 POP:1 ; 00000054 83400001 ALU_POP_AFTER 3, @269, KC0[], KC1[] ; 0000010D A80C0000 POP @85 POP:1 ; 00000055 83800001 ALU_PUSH_BEFORE 4, @273, KC0[], KC1[] ; 00000111 A4100000 JUMP @89 POP:1 ; 00000059 82800001 LOOP_BREAK @89 ; 00000059 82400000 POP @89 POP:1 ; 00000059 83800001 END_LOOP @73 ; 00000049 81400000 ALU 2, @278, KC0[CB0:0-32], KC1[] ; 80000116 A0080000 TEX 0 @116 ; 00000074 80400000 ALU 8, @281, KC0[CB0:0-32], KC1[] ; 80000119 A0200000 TEX 0 @118 ; 00000076 80400000 ALU_POP_AFTER 14, @290, KC0[], KC1[] ; 00000122 A8380000 TEX 0 @120 ; 00000078 80400000 ALU 1, @305, KC0[], KC1[] ; 00000131 A0040000 EXPORT T2.XYZW ; C0010000 95200688 CF_END ; 00000000 88000000 PAD ; 00000000 00000000 Fetch clause starting at 100: ; TEX_SAMPLE T1.XYZW, T0.XY__ RID:17 SID:1 CT:NNNN ; 00001110 F00D1001 FC808000 00000000 Fetch clause starting at 102: ; TEX_SAMPLE_L T2.XYZW, T2.XYY0 RID:18 SID:2 CT:NNNN ; 00021211 F00D1002 84810000 00000000 Fetch clause starting at 104: ; TEX_SAMPLE_L T3.XYZW, T3.XYY0 RID:18 SID:2 CT:NNNN ; 00031211 F00D1003 84810000 00000000 Fetch clause starting at 106: ; TEX_SAMPLE_L T5.XYZW, T5.XYY0 RID:18 SID:2 CT:NNNN ; 00051211 F00D1005 84810000 00000000 TEX_SAMPLE_L T4.XYZW, T4.XYY0 RID:18 SID:2 CT:NNNN ; 00041211 F00D1004 84810000 00000000 Fetch clause starting at 110: ; TEX_SAMPLE_L T2.XYZW, T2.XYY0 RID:16 SID:0 CT:NNNN ; 00021011 F00D1002 84800000 00000000 Fetch clause starting at 112: ; TEX_SAMPLE_L T1.XYZW, T1.XYY0 RID:18 SID:2 CT:NNNN ; 00011211 F00D1001 84810000 00000000 Fetch clause starting at 114: ; TEX_SAMPLE_L T3.XYZW, T3.XYY0 RID:18 SID:2 CT:NNNN ; 00031211 F00D1003 84810000 00000000 Fetch clause starting at 116: ; TEX_SAMPLE_L T5.XYZW, T4.XYY0 RID:18 SID:2 CT:NNNN ; 00041211 F00D1005 84810000 00000000 Fetch clause starting at 118: ; TEX_SAMPLE_L T0.XYZW, T4.XYY0 RID:18 SID:2 CT:NNNN ; 00041211 F00D1000 84810000 00000000 Fetch clause starting at 120: ; TEX_SAMPLE_L T0.XYZW, T1.XYY0 RID:16 SID:0 CT:NNNN ; 00011011 F00D1000 84800000 00000000 ALU clause starting at 122: ; INTERP_XY T0.X, T0.Y, ARRAY_BASE, ; 00380400 00146B10 INTERP_XY T0.Y, T0.X, ARRAY_BASE, ; 00380000 20146B10 INTERP_XY T0.Z (MASKED), T0.Y, ARRAY_BASE, ; 00380400 40146B00 INTERP_XY * T0.W (MASKED), T0.X, ARRAY_BASE, ; 80380000 60146B00 ALU clause starting at 126: ; SETNE * T2.Y, T1.Y, 0.0, ; 801F0401 20400590 SETNE_DX10 * T3.W, PV.Y, 0.0, ; 801F04FE 60600790 PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002104 ALU clause starting at 129: ; MOV * T2.Y, literal.x, ; 800000FD 20400C90 0(0.000000e+00), 0(0.000000e+00) ; 00000000 00000000 MOV * T2.X, PV.Y, ; 800004FE 00400C90 ALU clause starting at 132: ; MOV * T3.Z, literal.x, ; 800000FD 40600C90 -1077936128(-1.500000e+00), 0(0.000000e+00) ; BFC00000 00000000 ALU clause starting at 134: ; MOV * T3.X, T3.Z, ; 80000803 00600C90 SETGE * T3.W, literal.x, PV.X, ; 801FC0FD 60600510 -1048576000(-1.600000e+01), 0(0.000000e+00) ; C1800000 00000000 SETE_DX10 * T3.W, PV.W, 0.0, ; 801F0CFE 60600610 PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002104 ALU clause starting at 139: ; MOV * T3.W, literal.x, ; 800000FD 60600C90 1(1.401298e-45), 0(0.000000e+00) ; 00000001 00000000 ALU clause starting at 141: ; MULADD_IEEE T2.X, KC0[0].X, T3.X, T0.X, ; 00006080 00430000 MULADD_IEEE * T2.Y, KC0[0].Y, 0.0, T0.Y, ; 801F0480 20430400 ALU clause starting at 143: ; SETGT * T3.W, literal.x, T2.Y, ; 808040FD 60600490 1063675494(9.000000e-01), 0(0.000000e+00) ; 3F666666 00000000 SETE_DX10 * T3.W, PV.W, 0.0, ; 801F0CFE 60600610 PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002104 ALU clause starting at 147: ; MOV * T3.W, literal.x, ; 800000FD 60600C90 1(1.401298e-45), 0(0.000000e+00) ; 00000001 00000000 ALU clause starting at 149: ; ADD T3.Z, T3.X, literal.x, ; 001FA003 40600010 MOV * T3.W, literal.y, ; 800004FD 60600C90 -1073741824(-2.000000e+00), 0(0.000000e+00) ; C0000000 00000000 ALU clause starting at 152: ; LSHL * T3.W, T3.W, literal.x, ; 801FAC03 60600B90 31(4.344025e-44), 0(0.000000e+00) ; 0000001F 00000000 ASHR * T3.W, PV.W, literal.x, ; 801FACFE 60600A90 31(4.344025e-44), 0(0.000000e+00) ; 0000001F 00000000 PRED_SETNE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002284 ALU clause starting at 157: ; ADD * T3.W, T3.X, literal.x, ; 801FA003 60600010 1069547520(1.500000e+00), 0(0.000000e+00) ; 3FC00000 00000000 MULADD_IEEE * T2.W, T2.Y, literal.x, PV.W, ; 801FA402 60430CFE -1073741824(-2.000000e+00), 0(0.000000e+00) ; C0000000 00000000 MOV T2.Z, literal.x, ; 000000FD 40400C90 MAX * T2.W, literal.y, PV.W, ; 819FC4FD 60400190 1069547520(1.500000e+00), -1048576000(-1.600000e+01) ; 3FC00000 C1800000 ALU clause starting at 164: ; MOV * T2.X, T2.Z, ; 80000802 00400C90 SETGE * T3.Y, PV.X, literal.x, ; 801FA0FE 20600510 1098907648(1.600000e+01), 0(0.000000e+00) ; 41800000 00000000 SETE_DX10 * T4.W, PV.Y, 0.0, ; 801F04FE 60800610 PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002104 ALU clause starting at 169: ; MOV * T4.W, literal.x, ; 800000FD 60800C90 1(1.401298e-45), 0(0.000000e+00) ; 00000001 00000000 ALU clause starting at 171: ; MULADD_IEEE T3.X, KC0[0].X, T2.X, T0.X, ; 00004080 00630000 MULADD_IEEE * T3.Y, KC0[0].Y, 0.0, T0.Y, ; 801F0480 20630400 ALU clause starting at 173: ; SETGT * T4.W, literal.x, T3.Y, ; 808060FD 60800490 1063675494(9.000000e-01), 0(0.000000e+00) ; 3F666666 00000000 SETE_DX10 * T4.W, PV.W, 0.0, ; 801F0CFE 60800610 PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002104 ALU clause starting at 177: ; MOV * T4.W, literal.x, ; 800000FD 60800C90 1(1.401298e-45), 0(0.000000e+00) ; 00000001 00000000 ALU clause starting at 179: ; ADD T2.Z, T2.X, literal.x, ; 001FA002 40400010 MOV * T4.W, literal.y, ; 800004FD 60800C90 1073741824(2.000000e+00), 0(0.000000e+00) ; 40000000 00000000 ALU clause starting at 182: ; LSHL * T4.W, T4.W, literal.x, ; 801FAC04 60800B90 31(4.344025e-44), 0(0.000000e+00) ; 0000001F 00000000 ASHR * T4.W, PV.W, literal.x, ; 801FACFE 60800A90 31(4.344025e-44), 0(0.000000e+00) ; 0000001F 00000000 PRED_SETNE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002284 ALU clause starting at 187: ; ADD T2.Z, T3.Y, T3.Y, ; 00806403 40400010 ADD * T3.W, T2.X, literal.x, ; 801FA002 60600010 -1077936128(-1.500000e+00), 0(0.000000e+00) ; BFC00000 00000000 ADD * T3.W, PV.Z, PV.W, ; 819FC8FE 60600010 MIN * T3.W, literal.x, PV.W, ; 819FC0FD 60600210 1098907648(1.600000e+01), 0(0.000000e+00) ; 41800000 00000000 MULADD_IEEE T4.X, T2.W, KC0[0].X, T0.X, ; 00100C02 00830000 ADD * T5.W, PV.W, 1.0, ; 801F2CFE 60A00010 MULADD_IEEE T5.X, PV.W, KC0[0].X, T0.X, ; 00100CFE 00A30000 MULADD_IEEE * T4.Y, KC0[0].Y, literal.x, T0.Y, ; 801FA480 20830400 -1098907648(-2.500000e-01), 0(0.000000e+00) ; BE800000 00000000 MOV * T5.Y, PV.Y, ; 800004FE 20A00C90 ALU clause starting at 199: ; MUL_IEEE * T4.W, T4.X, literal.x, ; 801FA004 60800110 1082130432(4.000000e+00), 0(0.000000e+00) ; 40800000 00000000 RNDNE T2.Y, PV.W, ; 00000CFE 20400990 MOV T2.Z, |T2.W|, ; 00000C02 40400C91 MUL_IEEE * T2.W, T5.X, literal.x, ; 801FA005 60400110 1082130432(4.000000e+00), 0(0.000000e+00) ; 40800000 00000000 RNDNE T3.Y, PV.W, ; 00000CFE 20600990 MOV T3.Z, |T3.W|, ; 00000C03 40600C91 MULADD_IEEE * T2.W, PV.Y, literal.x, PV.Z, ; 801FA4FE 604308FE 1107558400(3.300000e+01), 0(0.000000e+00) ; 42040000 00000000 MUL_IEEE T2.X, PV.W, literal.x, ; 001FACFE 00400110 MULADD_IEEE * T3.W, PV.Y, literal.y, PV.Z, ; 809FA4FE 606308FE 1002950154(6.097560e-03), 1107558400(3.300000e+01) ; 3BC7CE0A 42040000 MUL_IEEE * T2.Y, PV.W, literal.x, ; 801FACFE 20400110 1002950154(6.097560e-03), 0(0.000000e+00) ; 3BC7CE0A 00000000 ALU clause starting at 214: ; SETNE * T3.W, T1.X, 0.0, ; 801F0001 60600590 SETNE_DX10 * T3.W, PV.W, 0.0, ; 801F0CFE 60600790 PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002104 ALU clause starting at 217: ; MOV * T0.Y, literal.x, ; 800000FD 20000C90 0(0.000000e+00), 0(0.000000e+00) ; 00000000 00000000 MOV * T0.X, PV.Y, ; 800004FE 00000C90 ALU clause starting at 220: ; MOV * T3.Z, literal.x, ; 800000FD 40600C90 -1077936128(-1.500000e+00), 0(0.000000e+00) ; BFC00000 00000000 ALU clause starting at 222: ; MOV * T3.X, T3.Z, ; 80000803 00600C90 SETGE * T3.W, literal.x, PV.X, ; 801FC0FD 60600510 -1048576000(-1.600000e+01), 0(0.000000e+00) ; C1800000 00000000 SETE_DX10 * T3.W, PV.W, 0.0, ; 801F0CFE 60600610 PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002104 ALU clause starting at 227: ; MOV * T3.W, literal.x, ; 800000FD 60600C90 1(1.401298e-45), 0(0.000000e+00) ; 00000001 00000000 ALU clause starting at 229: ; MULADD_IEEE T1.X, KC0[0].X, 0.0, T0.X, ; 001F0080 00230000 MULADD_IEEE * T1.Y, KC0[0].Y, T3.X, T0.Y, ; 80006480 20230400 ALU clause starting at 231: ; SETGT * T3.W, literal.x, T1.X, ; 800020FD 60600490 1063675494(9.000000e-01), 0(0.000000e+00) ; 3F666666 00000000 SETE_DX10 * T3.W, PV.W, 0.0, ; 801F0CFE 60600610 PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002104 ALU clause starting at 235: ; MOV * T3.W, literal.x, ; 800000FD 60600C90 1(1.401298e-45), 0(0.000000e+00) ; 00000001 00000000 ALU clause starting at 237: ; ADD T3.Z, T3.X, literal.x, ; 001FA003 40600010 MOV * T3.W, literal.y, ; 800004FD 60600C90 -1073741824(-2.000000e+00), 0(0.000000e+00) ; C0000000 00000000 ALU clause starting at 240: ; LSHL * T3.W, T3.W, literal.x, ; 801FAC03 60600B90 31(4.344025e-44), 0(0.000000e+00) ; 0000001F 00000000 ASHR * T3.W, PV.W, literal.x, ; 801FACFE 60600A90 31(4.344025e-44), 0(0.000000e+00) ; 0000001F 00000000 PRED_SETNE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002284 ALU clause starting at 245: ; ADD * T3.W, T3.X, literal.x, ; 801FA003 60600010 1069547520(1.500000e+00), 0(0.000000e+00) ; 3FC00000 00000000 MULADD_IEEE * T1.W, T1.X, literal.x, PV.W, ; 801FA001 60230CFE -1073741824(-2.000000e+00), 0(0.000000e+00) ; C0000000 00000000 MAX * T1.W, literal.x, PV.W, ; 819FC0FD 60200190 -1048576000(-1.600000e+01), 0(0.000000e+00) ; C1800000 00000000 MOV T3.X, PV.W, ; 00000CFE 00600C90 MOV * T4.W, literal.x, ; 800000FD 60800C90 1069547520(1.500000e+00), 0(0.000000e+00) ; 3FC00000 00000000 ALU clause starting at 254: ; MOV * T1.X, T4.W, ; 80000C04 00200C90 SETGE * T4.W, PV.X, literal.x, ; 801FA0FE 60800510 1098907648(1.600000e+01), 0(0.000000e+00) ; 41800000 00000000 SETE_DX10 * T4.W, PV.W, 0.0, ; 801F0CFE 60800610 PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002104 ALU clause starting at 259: ; MOV * T5.W, literal.x, ; 800000FD 60A00C90 1(1.401298e-45), 0(0.000000e+00) ; 00000001 00000000 ALU clause starting at 261: ; MULADD_IEEE T3.X, KC0[0].X, 0.0, T0.X, ; 001F0080 00630000 MULADD_IEEE * T3.Y, KC0[0].Y, T1.X, T0.Y, ; 80002480 20630400 ALU clause starting at 263: ; SETGT * T4.W, literal.x, T3.X, ; 800060FD 60800490 1063675494(9.000000e-01), 0(0.000000e+00) ; 3F666666 00000000 SETE_DX10 * T4.W, PV.W, 0.0, ; 801F0CFE 60800610 PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002104 ALU clause starting at 267: ; MOV * T5.W, literal.x, ; 800000FD 60A00C90 1(1.401298e-45), 0(0.000000e+00) ; 00000001 00000000 ALU clause starting at 269: ; MOV * T5.W, literal.x, ; 800000FD 60A00C90 0(0.000000e+00), 0(0.000000e+00) ; 00000000 00000000 ADD * T4.W, T1.X, literal.x, ; 801FA001 60800010 1073741824(2.000000e+00), 0(0.000000e+00) ; 40000000 00000000 ALU clause starting at 273: ; LSHL * T5.W, T5.W, literal.x, ; 801FAC05 60A00B90 31(4.344025e-44), 0(0.000000e+00) ; 0000001F 00000000 ASHR * T5.W, PV.W, literal.x, ; 801FACFE 60A00A90 31(4.344025e-44), 0(0.000000e+00) ; 0000001F 00000000 PRED_SETNE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002284 ALU clause starting at 278: ; MULADD_IEEE T4.X, KC0[0].X, literal.x, T0.X, ; 001FA080 00830000 MULADD_IEEE * T4.Y, T1.W, KC0[0].Y, T0.Y, ; 80900C01 20830400 -1098907648(-2.500000e-01), 0(0.000000e+00) ; BE800000 00000000 ALU clause starting at 281: ; ADD T1.Z, T3.X, T3.X, ; 00006003 40200010 ADD * T3.W, T1.X, literal.x, BS:VEC_120/SCL_212 ; 801FA001 60680010 -1077936128(-1.500000e+00), 0(0.000000e+00) ; BFC00000 00000000 ADD * T3.W, PV.Z, PV.W, ; 819FC8FE 60600010 MIN * T3.W, literal.x, PV.W, ; 819FC0FD 60600210 1098907648(1.600000e+01), 0(0.000000e+00) ; 41800000 00000000 ADD * T6.W, PV.W, 1.0, ; 801F2CFE 60C00010 MULADD_IEEE * T0.W, PV.W, KC0[0].Y, T0.Y, ; 80900CFE 60030400 MOV * T4.Y, PV.W, ; 80000CFE 20800C90 ALU clause starting at 290: ; MUL_IEEE * T4.W, T5.Y, literal.x, ; 801FA405 60800110 1082130432(4.000000e+00), 0(0.000000e+00) ; 40800000 00000000 RNDNE T1.Y, PV.W, ; 00000CFE 20200990 MOV T1.Z, |T1.W|, ; 00000C01 40200C91 MUL_IEEE * T0.W, T0.Y, literal.x, ; 801FA400 60000110 1082130432(4.000000e+00), 0(0.000000e+00) ; 40800000 00000000 RNDNE T0.Y, PV.W, ; 00000CFE 20000990 MOV T0.Z, |T3.W|, ; 00000C03 40000C91 MULADD_IEEE * T0.W, PV.Y, literal.x, PV.Z, ; 801FA4FE 600308FE 1107558400(3.300000e+01), 0(0.000000e+00) ; 42040000 00000000 MUL_IEEE T1.X, PV.W, literal.x, ; 001FACFE 00200110 MULADD_IEEE * T0.W, PV.Y, literal.y, PV.Z, ; 809FA4FE 600308FE 1002950154(6.097560e-03), 1107558400(3.300000e+01) ; 3BC7CE0A 42040000 MUL_IEEE * T1.Y, PV.W, literal.x, ; 801FACFE 20200110 1002950154(6.097560e-03), 0(0.000000e+00) ; 3BC7CE0A 00000000 ALU clause starting at 305: ; MOV T2.Z, T0.X, ; 00000000 40400C90 MOV * T2.W, T0.Y, ; 80000400 60400C90 ===== SHADER #26 ======================================== PS/CAYMAN/CAYMAN ===== ===== 614 dw ===== 7 gprs ===== 3 stack ======================================== 0000 0000007a a00c0000 ALU 4 @244 0244 00380400 00146b10 1 x: INTERP_XY R0.x, R0.y, Param0.x VEC_210 0246 00380000 20146b10 y: INTERP_XY R0.y, R0.x, Param0.x VEC_210 0248 00380400 40146b00 z: INTERP_XY __.z, R0.y, Param0.x VEC_210 0250 80380000 60146b00 w: INTERP_XY __.w, R0.x, Param0.x VEC_210 0002 00000064 80400000 TEX 1 @200 0200 00001110 f00d1001 fc808000 SAMPLE R1.xyzw, R0.xy__, RID:17, SID:1 CT:NNNN 0004 0000007e a4080000 ALU_PUSH_BEFORE 3 @252 0252 801f0401 20400590 2 y: SETNE R2.y, R1.y, 0 0254 801f04fe 60600790 3 w: SETNE_DX10 R3.w, PV.y, 0 0256 801f0cfe 00002104 4 M x: PRED_SETE_INT __.x, PV.w, 0 0006 00000005 82800000 JUMP @10 0008 00000081 a0080000 ALU 3 @258 0258 800000fd 20400c90 5 y: MOV R2.y, [0x00000000 0].x 0260 00000000 0262 800004fe 00400c90 6 x: MOV R2.x, PV.y 0010 00000030 83400001 ELSE @96 POP:1 0012 00000084 a0040000 ALU 2 @264 0264 800000fd 40600c90 7 z: MOV R3.z, [0xbfc00000 -1.5].x 0266 bfc00000 0014 00000019 81800000 LOOP_START_DX10 @50 0016 00000086 a4100000 ALU_PUSH_BEFORE 5 @268 0268 80000803 00600c90 8 x: MOV R3.x, R3.z 0270 801fc0fd 60600510 9 w: SETGE R3.w, [0xc1800000 -16].x, PV.x 0272 c1800000 0274 801f0cfe 60600610 10 w: SETE_DX10 R3.w, PV.w, 0 0276 801f0cfe 00002104 11 M x: PRED_SETE_INT __.x, PV.w, 0 0018 0000000b 82800000 JUMP @22 0020 0000008b a0040000 ALU 2 @278 0278 800000fd 60600c90 12 w: MOV R3.w, [0x00000001 1.4013e-45].x 0280 00000001 0022 00000014 83400001 ELSE @40 POP:1 0024 8000008d a0040000 ALU 2 @282 KC0[CB0:0-31] 0282 00006080 00430000 13 x: MULADD_IEEE R2.x, KC0[0].x, R3.x, R0.x 0284 801f0480 20430400 y: MULADD_IEEE R2.y, KC0[0].y, 0, R0.y 0026 00000066 80400000 TEX 1 @204 0204 00021211 f00d1002 84810000 SAMPLE_L R2.xyzw, R2.xyy0, RID:18, SID:2 CT:NNNN 0028 0000008f a40c0000 ALU_PUSH_BEFORE 4 @286 0286 808040fd 60600490 14 w: SETGT R3.w, [0x3f666666 0.9].x, R2.y 0288 3f666666 0290 801f0cfe 60600610 15 w: SETE_DX10 R3.w, PV.w, 0 0292 801f0cfe 00002104 16 M x: PRED_SETE_INT __.x, PV.w, 0 0030 00000011 82800000 JUMP @34 0032 00000093 a0040000 ALU 2 @294 0294 800000fd 60600c90 17 w: MOV R3.w, [0x00000001 1.4013e-45].x 0296 00000001 0034 00000013 83400001 ELSE @38 POP:1 0036 00000095 a8080000 ALU_POP_AFTER 3 @298 0298 001fa003 40600010 18 z: ADD R3.z, R3.x, [0xc0000000 -2].x 0300 800004fd 60600c90 w: MOV R3.w, [0x00000000 0].y 0302 c0000000 0303 00000000 0038 00000014 83800001 POP @40 POP:1 0040 00000098 a4100000 ALU_PUSH_BEFORE 5 @304 0304 801fac03 60600b90 19 w: LSHL_INT R3.w, R3.w, [0x0000001f 4.34403e-44].x 0306 0000001f 0308 801facfe 60600a90 20 w: ASHR_INT R3.w, PV.w, [0x0000001f 4.34403e-44].x 0310 0000001f 0312 801f0cfe 00002284 21 M x: PRED_SETNE_INT __.x, PV.w, 0 0042 00000018 82800001 JUMP @48 POP:1 0044 00000018 82400000 LOOP_BREAK @48 0046 00000018 83800001 POP @48 POP:1 0048 00000008 81400000 LOOP_END @16 0050 0000009d a0180000 ALU 7 @314 0314 801fa003 60600010 22 w: ADD R3.w, R3.x, [0x3fc00000 1.5].x 0316 3fc00000 0318 801fa402 60430cfe 23 w: MULADD_IEEE R2.w, R2.y, [0xc0000000 -2].x, PV.w 0320 c0000000 0322 000000fd 40400c90 24 z: MOV R2.z, [0x3fc00000 1.5].x 0324 819fc4fd 60400190 w: MAX R2.w, [0xc1800000 -16].y, PV.w 0326 3fc00000 0327 c1800000 0052 0000002c 81800000 LOOP_START_DX10 @88 0054 000000a4 a4100000 ALU_PUSH_BEFORE 5 @328 0328 80000802 00400c90 25 x: MOV R2.x, R2.z 0330 801fa0fe 20600510 26 y: SETGE R3.y, PV.x, [0x41800000 16].x 0332 41800000 0334 801f04fe 60800610 27 w: SETE_DX10 R4.w, PV.y, 0 0336 801f0cfe 00002104 28 M x: PRED_SETE_INT __.x, PV.w, 0 0056 0000001e 82800000 JUMP @60 0058 000000a9 a0040000 ALU 2 @338 0338 800000fd 60800c90 29 w: MOV R4.w, [0x00000001 1.4013e-45].x 0340 00000001 0060 00000027 83400001 ELSE @78 POP:1 0062 800000ab a0040000 ALU 2 @342 KC0[CB0:0-31] 0342 00004080 00630000 30 x: MULADD_IEEE R3.x, KC0[0].x, R2.x, R0.x 0344 801f0480 20630400 y: MULADD_IEEE R3.y, KC0[0].y, 0, R0.y 0064 00000068 80400000 TEX 1 @208 0208 00031211 f00d1003 84810000 SAMPLE_L R3.xyzw, R3.xyy0, RID:18, SID:2 CT:NNNN 0066 000000ad a40c0000 ALU_PUSH_BEFORE 4 @346 0346 808060fd 60800490 31 w: SETGT R4.w, [0x3f666666 0.9].x, R3.y 0348 3f666666 0350 801f0cfe 60800610 32 w: SETE_DX10 R4.w, PV.w, 0 0352 801f0cfe 00002104 33 M x: PRED_SETE_INT __.x, PV.w, 0 0068 00000024 82800000 JUMP @72 0070 000000b1 a0040000 ALU 2 @354 0354 800000fd 60800c90 34 w: MOV R4.w, [0x00000001 1.4013e-45].x 0356 00000001 0072 00000026 83400001 ELSE @76 POP:1 0074 000000b3 a8080000 ALU_POP_AFTER 3 @358 0358 001fa002 40400010 35 z: ADD R2.z, R2.x, [0x40000000 2].x 0360 800004fd 60800c90 w: MOV R4.w, [0x00000000 0].y 0362 40000000 0363 00000000 0076 00000027 83800001 POP @78 POP:1 0078 000000b6 a4100000 ALU_PUSH_BEFORE 5 @364 0364 801fac04 60800b90 36 w: LSHL_INT R4.w, R4.w, [0x0000001f 4.34403e-44].x 0366 0000001f 0368 801facfe 60800a90 37 w: ASHR_INT R4.w, PV.w, [0x0000001f 4.34403e-44].x 0370 0000001f 0372 801f0cfe 00002284 38 M x: PRED_SETNE_INT __.x, PV.w, 0 0080 0000002b 82800001 JUMP @86 POP:1 0082 0000002b 82400000 LOOP_BREAK @86 0084 0000002b 83800001 POP @86 POP:1 0086 0000001b 81400000 LOOP_END @54 0088 800000bb a02c0000 ALU 12 @374 KC0[CB0:0-31] 0374 00806403 40400010 39 z: ADD R2.z, R3.y, R3.y 0376 801fa002 60600010 w: ADD R3.w, R2.x, [0xbfc00000 -1.5].x 0378 bfc00000 0380 819fc8fe 60600010 40 w: ADD R3.w, PV.z, PV.w 0382 819fc0fd 60600210 41 w: MIN R3.w, [0x41800000 16].x, PV.w 0384 41800000 0386 00100c02 00830000 42 x: MULADD_IEEE R4.x, R2.w, KC0[0].x, R0.x 0388 801f2cfe 60a00010 w: ADD R5.w, PV.w, 1.0 0390 00100cfe 00a30000 43 x: MULADD_IEEE R5.x, PV.w, KC0[0].x, R0.x 0392 801fa480 20830400 y: MULADD_IEEE R4.y, KC0[0].y, [0xbe800000 -0.25].x, R0.y 0394 be800000 0396 800004fe 20a00c90 44 y: MOV R5.y, PV.y 0090 0000006a 80400400 TEX 2 @212 0212 00051211 f00d1005 84810000 SAMPLE_L R5.xyzw, R5.xyy0, RID:18, SID:2 CT:NNNN 0216 00041211 f00d1004 84810000 SAMPLE_L R4.xyzw, R4.xyy0, RID:18, SID:2 CT:NNNN 0092 000000c7 a8380000 ALU_POP_AFTER 15 @398 0398 801fa004 60800110 45 w: MUL_IEEE R4.w, R4.x, [0x40800000 4].x 0400 40800000 0402 00000cfe 20400990 46 y: RNDNE R2.y, PV.w 0404 00000c02 40400c91 z: MOV R2.z, |R2.w| 0406 801fa005 60400110 w: MUL_IEEE R2.w, R5.x, [0x40800000 4].x 0408 40800000 0410 00000cfe 20600990 47 y: RNDNE R3.y, PV.w 0412 00000c03 40600c91 z: MOV R3.z, |R3.w| 0414 801fa4fe 604308fe w: MULADD_IEEE R2.w, PV.y, [0x42040000 33].x, PV.z 0416 42040000 0418 001facfe 00400110 48 x: MUL_IEEE R2.x, PV.w, [0x3bc7ce0a 0.00609756].x 0420 809fa4fe 606308fe w: MULADD_IEEE R3.w, PV.y, [0x42040000 33].y, PV.z 0422 3bc7ce0a 0423 42040000 0424 801facfe 20400110 49 y: MUL_IEEE R2.y, PV.w, [0x3bc7ce0a 0.00609756].x 0426 3bc7ce0a 0094 0000006e 80400000 TEX 1 @220 0220 00021011 f00d1002 84800000 SAMPLE_L R2.xyzw, R2.xyy0, RID:16, SID:0 CT:NNNN 0096 000000d6 a4080000 ALU_PUSH_BEFORE 3 @428 0428 801f0001 60600590 50 w: SETNE R3.w, R1.x, 0 0430 801f0cfe 60600790 51 w: SETNE_DX10 R3.w, PV.w, 0 0432 801f0cfe 00002104 52 M x: PRED_SETE_INT __.x, PV.w, 0 0098 00000033 82800000 JUMP @102 0100 000000d9 a0080000 ALU 3 @434 0434 800000fd 20000c90 53 y: MOV R0.y, [0x00000000 0].x 0436 00000000 0438 800004fe 00000c90 54 x: MOV R0.x, PV.y 0102 00000060 83400001 ELSE @192 POP:1 0104 000000dc a0040000 ALU 2 @440 0440 800000fd 40600c90 55 z: MOV R3.z, [0xbfc00000 -1.5].x 0442 bfc00000 0106 00000047 81800000 LOOP_START_DX10 @142 0108 000000de a4100000 ALU_PUSH_BEFORE 5 @444 0444 80000803 00600c90 56 x: MOV R3.x, R3.z 0446 801fc0fd 60600510 57 w: SETGE R3.w, [0xc1800000 -16].x, PV.x 0448 c1800000 0450 801f0cfe 60600610 58 w: SETE_DX10 R3.w, PV.w, 0 0452 801f0cfe 00002104 59 M x: PRED_SETE_INT __.x, PV.w, 0 0110 00000039 82800000 JUMP @114 0112 000000e3 a0040000 ALU 2 @454 0454 800000fd 60600c90 60 w: MOV R3.w, [0x00000001 1.4013e-45].x 0456 00000001 0114 00000042 83400001 ELSE @132 POP:1 0116 800000e5 a0040000 ALU 2 @458 KC0[CB0:0-31] 0458 001f0080 00230000 61 x: MULADD_IEEE R1.x, KC0[0].x, 0, R0.x 0460 80006480 20230400 y: MULADD_IEEE R1.y, KC0[0].y, R3.x, R0.y 0118 00000070 80400000 TEX 1 @224 0224 00011211 f00d1001 84810000 SAMPLE_L R1.xyzw, R1.xyy0, RID:18, SID:2 CT:NNNN 0120 000000e7 a40c0000 ALU_PUSH_BEFORE 4 @462 0462 800020fd 60600490 62 w: SETGT R3.w, [0x3f666666 0.9].x, R1.x 0464 3f666666 0466 801f0cfe 60600610 63 w: SETE_DX10 R3.w, PV.w, 0 0468 801f0cfe 00002104 64 M x: PRED_SETE_INT __.x, PV.w, 0 0122 0000003f 82800000 JUMP @126 0124 000000eb a0040000 ALU 2 @470 0470 800000fd 60600c90 65 w: MOV R3.w, [0x00000001 1.4013e-45].x 0472 00000001 0126 00000041 83400001 ELSE @130 POP:1 0128 000000ed a8080000 ALU_POP_AFTER 3 @474 0474 001fa003 40600010 66 z: ADD R3.z, R3.x, [0xc0000000 -2].x 0476 800004fd 60600c90 w: MOV R3.w, [0x00000000 0].y 0478 c0000000 0479 00000000 0130 00000042 83800001 POP @132 POP:1 0132 000000f0 a4100000 ALU_PUSH_BEFORE 5 @480 0480 801fac03 60600b90 67 w: LSHL_INT R3.w, R3.w, [0x0000001f 4.34403e-44].x 0482 0000001f 0484 801facfe 60600a90 68 w: ASHR_INT R3.w, PV.w, [0x0000001f 4.34403e-44].x 0486 0000001f 0488 801f0cfe 00002284 69 M x: PRED_SETNE_INT __.x, PV.w, 0 0134 00000046 82800001 JUMP @140 POP:1 0136 00000046 82400000 LOOP_BREAK @140 0138 00000046 83800001 POP @140 POP:1 0140 00000036 81400000 LOOP_END @108 0142 000000f5 a0200000 ALU 9 @490 0490 801fa003 60600010 70 w: ADD R3.w, R3.x, [0x3fc00000 1.5].x 0492 3fc00000 0494 801fa001 60230cfe 71 w: MULADD_IEEE R1.w, R1.x, [0xc0000000 -2].x, PV.w 0496 c0000000 0498 819fc0fd 60200190 72 w: MAX R1.w, [0xc1800000 -16].x, PV.w 0500 c1800000 0502 00000cfe 00600c90 73 x: MOV R3.x, PV.w 0504 800000fd 60800c90 w: MOV R4.w, [0x3fc00000 1.5].x 0506 3fc00000 0144 0000005a 81800000 LOOP_START_DX10 @180 0146 000000fe a4100000 ALU_PUSH_BEFORE 5 @508 0508 80000c04 00200c90 74 x: MOV R1.x, R4.w 0510 801fa0fe 60800510 75 w: SETGE R4.w, PV.x, [0x41800000 16].x 0512 41800000 0514 801f0cfe 60800610 76 w: SETE_DX10 R4.w, PV.w, 0 0516 801f0cfe 00002104 77 M x: PRED_SETE_INT __.x, PV.w, 0 0148 0000004c 82800000 JUMP @152 0150 00000103 a0040000 ALU 2 @518 0518 800000fd 60a00c90 78 w: MOV R5.w, [0x00000001 1.4013e-45].x 0520 00000001 0152 00000055 83400001 ELSE @170 POP:1 0154 80000105 a0040000 ALU 2 @522 KC0[CB0:0-31] 0522 001f0080 00630000 79 x: MULADD_IEEE R3.x, KC0[0].x, 0, R0.x 0524 80002480 20630400 y: MULADD_IEEE R3.y, KC0[0].y, R1.x, R0.y 0156 00000072 80400000 TEX 1 @228 0228 00031211 f00d1003 84810000 SAMPLE_L R3.xyzw, R3.xyy0, RID:18, SID:2 CT:NNNN 0158 00000107 a40c0000 ALU_PUSH_BEFORE 4 @526 0526 800060fd 60800490 80 w: SETGT R4.w, [0x3f666666 0.9].x, R3.x 0528 3f666666 0530 801f0cfe 60800610 81 w: SETE_DX10 R4.w, PV.w, 0 0532 801f0cfe 00002104 82 M x: PRED_SETE_INT __.x, PV.w, 0 0160 00000052 82800000 JUMP @164 0162 0000010b a0040000 ALU 2 @534 0534 800000fd 60a00c90 83 w: MOV R5.w, [0x00000001 1.4013e-45].x 0536 00000001 0164 00000054 83400001 ELSE @168 POP:1 0166 0000010d a80c0000 ALU_POP_AFTER 4 @538 0538 800000fd 60a00c90 84 w: MOV R5.w, [0x00000000 0].x 0540 00000000 0542 801fa001 60800010 85 w: ADD R4.w, R1.x, [0x40000000 2].x 0544 40000000 0168 00000055 83800001 POP @170 POP:1 0170 00000111 a4100000 ALU_PUSH_BEFORE 5 @546 0546 801fac05 60a00b90 86 w: LSHL_INT R5.w, R5.w, [0x0000001f 4.34403e-44].x 0548 0000001f 0550 801facfe 60a00a90 87 w: ASHR_INT R5.w, PV.w, [0x0000001f 4.34403e-44].x 0552 0000001f 0554 801f0cfe 00002284 88 M x: PRED_SETNE_INT __.x, PV.w, 0 0172 00000059 82800001 JUMP @178 POP:1 0174 00000059 82400000 LOOP_BREAK @178 0176 00000059 83800001 POP @178 POP:1 0178 00000049 81400000 LOOP_END @146 0180 80000116 a0080000 ALU 3 @556 KC0[CB0:0-31] 0556 001fa080 00830000 89 x: MULADD_IEEE R4.x, KC0[0].x, [0xbe800000 -0.25].x, R0.x 0558 80900c01 20830400 y: MULADD_IEEE R4.y, R1.w, KC0[0].y, R0.y 0560 be800000 0182 00000074 80400000 TEX 1 @232 0232 00041211 f00d1005 84810000 SAMPLE_L R5.xyzw, R4.xyy0, RID:18, SID:2 CT:NNNN 0184 80000119 a0200000 ALU 9 @562 KC0[CB0:0-31] 0562 00006003 40200010 90 z: ADD R1.z, R3.x, R3.x 0564 801fa001 60680010 w: ADD R3.w, R1.x, [0xbfc00000 -1.5].x VEC_120 0566 bfc00000 0568 819fc8fe 60600010 91 w: ADD R3.w, PV.z, PV.w 0570 819fc0fd 60600210 92 w: MIN R3.w, [0x41800000 16].x, PV.w 0572 41800000 0574 801f2cfe 60c00010 93 w: ADD R6.w, PV.w, 1.0 0576 80900cfe 60030400 94 w: MULADD_IEEE R0.w, PV.w, KC0[0].y, R0.y 0578 80000cfe 20800c90 95 y: MOV R4.y, PV.w 0186 00000076 80400000 TEX 1 @236 0236 00041211 f00d1000 84810000 SAMPLE_L R0.xyzw, R4.xyy0, RID:18, SID:2 CT:NNNN 0188 00000122 a8380000 ALU_POP_AFTER 15 @580 0580 801fa405 60800110 96 w: MUL_IEEE R4.w, R5.y, [0x40800000 4].x 0582 40800000 0584 00000cfe 20200990 97 y: RNDNE R1.y, PV.w 0586 00000c01 40200c91 z: MOV R1.z, |R1.w| 0588 801fa400 60000110 w: MUL_IEEE R0.w, R0.y, [0x40800000 4].x 0590 40800000 0592 00000cfe 20000990 98 y: RNDNE R0.y, PV.w 0594 00000c03 40000c91 z: MOV R0.z, |R3.w| 0596 801fa4fe 600308fe w: MULADD_IEEE R0.w, PV.y, [0x42040000 33].x, PV.z 0598 42040000 0600 001facfe 00200110 99 x: MUL_IEEE R1.x, PV.w, [0x3bc7ce0a 0.00609756].x 0602 809fa4fe 600308fe w: MULADD_IEEE R0.w, PV.y, [0x42040000 33].y, PV.z 0604 3bc7ce0a 0605 42040000 0606 801facfe 20200110 100 y: MUL_IEEE R1.y, PV.w, [0x3bc7ce0a 0.00609756].x 0608 3bc7ce0a 0190 00000078 80400000 TEX 1 @240 0240 00011011 f00d1000 84800000 SAMPLE_L R0.xyzw, R1.xyy0, RID:16, SID:0 CT:NNNN 0192 00000131 a0040000 ALU 2 @610 0610 00000000 40400c90 101 z: MOV R2.z, R0.x 0612 80000400 60400c90 w: MOV R2.w, R0.y 0194 c0010000 95200688 EXPORT_DONE PIXEL 0 R2.xyzw 0196 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #26 OPT ==================================== PS/CAYMAN/CAYMAN ===== ===== 520 dw ===== 6 gprs ===== 2 stack ======================================== 0000 00000052 a00c0000 ALU 4 @164 0164 00380400 00946b10 1 x: INTERP_XY R4.x, R0.y, Param0.x VEC_210 0166 00b80000 20946b10 y: INTERP_XY R4.y, R0.x, Param0.y VEC_210 0168 01380400 40146b00 z: INTERP_XY __.z, R0.y, Param0.z VEC_210 0170 81b80000 60146b00 w: INTERP_XY __.w, R0.x, Param0.w VEC_210 0002 00000056 80400000 TEX 1 @172 0172 00041110 f00d1001 fc808000 SAMPLE R1.xyzw, R4.xy__, RID:17, SID:1 CT:NNNN 0004 00000058 a4000000 ALU_PUSH_BEFORE 1 @176 0176 801f0401 00001004 2 M x: PRED_SETE __.x, R1.y, 0 0006 00000005 82800000 JUMP @10 0008 00000059 a0040000 ALU 2 @178 0178 000000f8 00400c90 3 x: MOV R2.x, 0 0180 800000f8 20400c90 y: MOV R2.y, 0 0010 00000029 83400001 ELSE @82 POP:1 0012 4000005b a00c0000 ALU 4 @182 KC0[CB0:0-15] 0182 801f0401 20400590 4 y: SETNE R2.y, R1.y, 0 0184 000000fd 00000c90 5 x: MOV R0.x, [0xbfc00000 -1.5].x 0186 801f0480 20630404 y: MULADD_IEEE R3.y, KC0[0].y, 0, R4.y 0188 bfc00000 0014 00000015 81800000 LOOP_START_DX10 @42 0016 0000005f a4040000 ALU_PUSH_BEFORE 2 @190 0190 800000fd 00001104 6 M x: PRED_SETGE __.x, [0xc1800000 -16].x, R0.x 0192 c1800000 0018 0000000b 82800000 JUMP @22 0020 00000061 a0040000 ALU 2 @194 0194 000000fa 20000c90 7 y: MOV R0.y, 1 0196 80000000 40000c90 z: MOV R0.z, R0.x 0022 0000000f 83400001 ELSE @30 POP:1 0024 40000063 a0000000 ALU 1 @198 KC0[CB0:0-15] 0198 80000080 00630004 8 x: MULADD_IEEE R3.x, KC0[0].x, R0.x, R4.x 0026 00000064 80400000 TEX 1 @200 0200 00031211 f00d1002 84810000 SAMPLE_L R2.xyzw, R3.xyy0, RID:18, SID:2 CT:NNNN 0028 00000066 a8100000 ALU_POP_AFTER 5 @204 0204 001fa402 2f800710 9 y: SETGE_DX10 T0.y, R2.y, [0x3f666666 0.9].x 0206 809fa000 4f800010 z: ADD T0.z, R0.x, [0xc0000000 -2].y 0208 3f666666 0209 c0000000 0210 001f447c 200380f8 10 y: CNDE_INT R0.y, T0.y, 1, 0 0212 8000047c 4003887c z: CNDE_INT R0.z, T0.y, R0.x, T0.z 0030 0000006b a4100000 ALU_PUSH_BEFORE 5 @214 0214 801fa400 6f800b90 11 w: LSHL_INT T0.w, R0.y, [0x0000001f 4.34403e-44].x 0216 0000001f 0218 801fac7c 0f800a90 12 x: ASHR_INT T0.x, T0.w, [0x0000001f 4.34403e-44].x 0220 0000001f 0222 801f007c 00002284 13 M x: PRED_SETNE_INT __.x, T0.x, 0 0032 00000013 82800001 JUMP @38 POP:1 0034 00000014 82400000 LOOP_BREAK @40 0036 00000013 83800001 POP @38 POP:1 0038 00000070 a0000000 ALU 1 @224 0224 80000800 00000c90 14 x: MOV R0.x, R0.z 0040 00000008 81400000 LOOP_END @16 0042 00000071 a0100000 ALU 5 @226 0226 801fa000 20a00010 15 y: ADD R5.y, R0.x, [0x3fc00000 1.5].x 0228 3fc00000 0230 000000fd 00400c90 16 x: MOV R2.x, [0x3fc00000 1.5].x 0232 80000405 60000c90 w: MOV R0.w, R5.y 0234 3fc00000 0044 00000024 81800000 LOOP_START_DX10 @72 0046 00000076 a4040000 ALU_PUSH_BEFORE 2 @236 0236 801fa002 00001104 17 M x: PRED_SETGE __.x, R2.x, [0x41800000 16].x 0238 41800000 0048 0000001a 82800000 JUMP @52 0050 00000078 a00c0000 ALU 4 @240 0240 001fa002 20000510 18 y: SETGE R0.y, R2.x, [0x41800000 16].x 0242 000000fa 40400c90 z: MOV R2.z, 1 0244 80000002 60400c90 w: MOV R2.w, R2.x 0246 41800000 0052 0000001e 83400001 ELSE @60 POP:1 0054 4000007c a0000000 ALU 1 @248 KC0[CB0:0-15] 0248 80004080 00630004 19 x: MULADD_IEEE R3.x, KC0[0].x, R2.x, R4.x 0056 0000007e 80400000 TEX 1 @252 0252 00031211 f00d1000 84810000 SAMPLE_L R0.xyzw, R3.xyy0, RID:18, SID:2 CT:NNNN 0058 00000080 a8100000 ALU_POP_AFTER 5 @256 0256 001fa400 4f800710 20 z: SETGE_DX10 T0.z, R0.y, [0x3f666666 0.9].x 0258 809fa002 6f800010 w: ADD T0.w, R2.x, [0x40000000 2].y 0260 3f666666 0261 40000000 0262 001f487c 404380f8 21 z: CNDE_INT R2.z, T0.z, 1, 0 0264 8000487c 60438c7c w: CNDE_INT R2.w, T0.z, R2.x, T0.w 0060 00000085 a4100000 ALU_PUSH_BEFORE 5 @266 0266 801fa802 0f800b90 22 x: LSHL_INT T0.x, R2.z, [0x0000001f 4.34403e-44].x 0268 0000001f 0270 801fa07c 2f800a90 23 y: ASHR_INT T0.y, T0.x, [0x0000001f 4.34403e-44].x 0272 0000001f 0274 801f047c 00002284 24 M x: PRED_SETNE_INT __.x, T0.y, 0 0062 00000022 82800001 JUMP @68 POP:1 0064 00000023 82400000 LOOP_BREAK @70 0066 00000022 83800001 POP @68 POP:1 0068 0000008a a0000000 ALU 1 @276 0276 80000c02 00400c90 25 x: MOV R2.x, R2.w 0070 00000017 81400000 LOOP_END @46 0072 4000008b a0340000 ALU 14 @278 KC0[CB0:0-15] 0278 801fa002 4f800010 26 z: ADD T0.z, R2.x, [0xbfc00000 -1.5].x 0280 bfc00000 0282 801fa400 6f82887c 27 w: MULADD T0.w, R0.y, [0x40000000 2].x, T0.z 0284 40000000 0286 001fa402 0f830405 28 x: MULADD_IEEE T0.x, R2.y, [0xc0000000 -2].x, R5.y 0288 809fac7c 20400210 y: MIN R2.y, T0.w, [0x41800000 16].y 0290 c0000000 0291 41800000 0292 001fa07c 40400190 29 z: MAX R2.z, T0.x, [0xc1800000 -16].x 0294 801f2402 6f800010 w: ADD T0.w, R2.y, 1.0 0296 c1800000 0298 00100802 00030004 30 x: MULADD_IEEE R0.x, R2.z, KC0[0].x, R4.x 0300 001fa480 20030404 y: MULADD_IEEE R0.y, KC0[0].y, [0xbe800000 -0.25].x, R4.y 0302 80100c7c 40030004 z: MULADD_IEEE R0.z, T0.w, KC0[0].x, R4.x 0304 be800000 0074 0000009a 80400400 TEX 2 @308 0308 00001211 f01c7e00 84a10000 SAMPLE_L R0.__x_, R0.zyy0, RID:18, SID:2 CT:NNNN 0312 00001211 f01ff000 84810000 SAMPLE_L R0.x___, R0.xyy0, RID:18, SID:2 CT:NNNN 0076 0000009e a0300000 ALU 13 @316 0316 001fa800 0f800110 31 x: MUL_IEEE T0.x, R0.z, [0x40800000 4].x 0318 801fa000 2f800110 y: MUL_IEEE T0.y, R0.x, [0x40800000 4].x 0320 40800000 0322 00000802 0f800c91 32 x: MOV T0.x, |R2.z| 0324 0000007c 20000990 y: RNDNE R0.y, T0.x 0326 00000402 4f800c91 z: MOV T0.z, |R2.y| 0328 8000047c 6f880990 w: RNDNE T0.w, T0.y VEC_120 0330 001fa400 2f83087c 33 y: MULADD_IEEE T0.y, R0.y, [0x42040000 33].x, T0.z 0332 801fac7c 4f83007c z: MULADD_IEEE T0.z, T0.w, [0x42040000 33].x, T0.x 0334 42040000 0336 001fa87c 00000110 34 x: MUL_IEEE R0.x, T0.z, [0x3bc7ce0a 0.00609756].x 0338 801fa47c 40000110 z: MUL_IEEE R0.z, T0.y, [0x3bc7ce0a 0.00609756].x 0340 3bc7ce0a 0078 000000ac 80400000 TEX 1 @344 0344 00001011 f01f9002 89000000 SAMPLE_L R2.xy__, R0.xzz0, RID:16, SID:0 CT:NNNN 0080 00000029 83800001 POP @82 POP:1 0082 000000ae a4000000 ALU_PUSH_BEFORE 1 @348 0348 801f0001 00001004 35 M x: PRED_SETE __.x, R1.x, 0 0084 0000002c 82800000 JUMP @88 0086 000000af a0040000 ALU 2 @350 0350 000000f8 40400c90 36 z: MOV R2.z, 0 0352 800000f8 60400c90 w: MOV R2.w, 0 0088 00000050 83400001 ELSE @160 POP:1 0090 400000b1 a0080000 ALU 3 @354 KC0[CB0:0-15] 0354 000000fd 00000c90 37 x: MOV R0.x, [0xbfc00000 -1.5].x 0356 801f0080 40430004 z: MULADD_IEEE R2.z, KC0[0].x, 0, R4.x 0358 bfc00000 0092 0000003c 81800000 LOOP_START_DX10 @120 0094 000000b4 a4040000 ALU_PUSH_BEFORE 2 @360 0360 800000fd 00001104 38 M x: PRED_SETGE __.x, [0xc1800000 -16].x, R0.x 0362 c1800000 0096 00000032 82800000 JUMP @100 0098 000000b6 a0040000 ALU 2 @364 0364 00000000 40000c90 39 z: MOV R0.z, R0.x 0366 800000fa 60000c90 w: MOV R0.w, 1 0100 00000036 83400001 ELSE @108 POP:1 0102 400000b8 a0000000 ALU 1 @368 KC0[CB0:0-15] 0368 80000480 60430404 40 w: MULADD_IEEE R2.w, KC0[0].y, R0.x, R4.y 0104 000000ba 80400000 TEX 1 @372 0372 00021211 f00d1001 8da10000 SAMPLE_L R1.xyzw, R2.zww0, RID:18, SID:2 CT:NNNN 0106 000000bc a8100000 ALU_POP_AFTER 5 @376 0376 001fa000 0f800010 41 x: ADD T0.x, R0.x, [0xc0000000 -2].x 0378 809fa001 6f880710 w: SETGE_DX10 T0.w, R1.x, [0x3f666666 0.9].y VEC_120 0380 c0000000 0381 3f666666 0382 00000c7c 4003807c 42 z: CNDE_INT R0.z, T0.w, R0.x, T0.x 0384 801f4c7c 600380f8 w: CNDE_INT R0.w, T0.w, 1, 0 0108 000000c1 a4100000 ALU_PUSH_BEFORE 5 @386 0386 801fac00 2f800b90 43 y: LSHL_INT T0.y, R0.w, [0x0000001f 4.34403e-44].x 0388 0000001f 0390 801fa47c 4f800a90 44 z: ASHR_INT T0.z, T0.y, [0x0000001f 4.34403e-44].x 0392 0000001f 0394 801f087c 00002284 45 M x: PRED_SETNE_INT __.x, T0.z, 0 0110 0000003a 82800001 JUMP @116 POP:1 0112 0000003b 82400000 LOOP_BREAK @118 0114 0000003a 83800001 POP @116 POP:1 0116 000000c6 a0000000 ALU 1 @396 0396 80000800 00000c90 46 x: MOV R0.x, R0.z 0118 0000002f 81400000 LOOP_END @94 0120 000000c7 a0200000 ALU 9 @398 0398 801fa000 60000010 47 w: ADD R0.w, R0.x, [0x3fc00000 1.5].x 0400 3fc00000 0402 801fa001 6f830c00 48 w: MULADD_IEEE T0.w, R1.x, [0xc0000000 -2].x, R0.w 0404 c0000000 0406 801fac7c 00600190 49 x: MAX R3.x, T0.w, [0xc1800000 -16].x 0408 c1800000 0410 800000fd 00200c90 50 x: MOV R1.x, [0x3fc00000 1.5].x 0412 3fc00000 0414 80000003 00000c90 51 x: MOV R0.x, R3.x 0122 0000004b 81800000 LOOP_START_DX10 @150 0124 000000d0 a4040000 ALU_PUSH_BEFORE 2 @416 0416 801fa001 00001104 52 M x: PRED_SETGE __.x, R1.x, [0x41800000 16].x 0418 41800000 0126 00000041 82800000 JUMP @130 0128 000000d2 a0080000 ALU 3 @420 0420 000000fa 20200c90 53 y: MOV R1.y, 1 0422 800020fd 40200690 z: SETGT_DX10 R1.z, [0x41800000 16].x, R1.x 0424 41800000 0130 00000045 83400001 ELSE @138 POP:1 0132 400000d5 a0000000 ALU 1 @426 KC0[CB0:0-15] 0426 80002480 60430404 54 w: MULADD_IEEE R2.w, KC0[0].y, R1.x, R4.y 0134 000000d6 80400000 TEX 1 @428 0428 00021211 f00d1000 8da10000 SAMPLE_L R0.xyzw, R2.zww0, RID:18, SID:2 CT:NNNN 0136 000000d8 a8100000 ALU_POP_AFTER 5 @432 0432 001fa000 2f800710 55 y: SETGE_DX10 T0.y, R0.x, [0x3f666666 0.9].x 0434 809fa001 4f880010 z: ADD T0.z, R1.x, [0x40000000 2].y VEC_120 0436 3f666666 0437 40000000 0438 001f447c 202380f8 56 y: CNDE_INT R1.y, T0.y, 1, 0 0440 808f847c 4023887c z: CNDE_INT R1.z, T0.y, T0.y, T0.z 0138 000000dd a4100000 ALU_PUSH_BEFORE 5 @442 0442 801fa401 6f800b90 57 w: LSHL_INT T0.w, R1.y, [0x0000001f 4.34403e-44].x 0444 0000001f 0446 801fac7c 0f800a90 58 x: ASHR_INT T0.x, T0.w, [0x0000001f 4.34403e-44].x 0448 0000001f 0450 801f007c 00002284 59 M x: PRED_SETNE_INT __.x, T0.x, 0 0140 00000049 82800001 JUMP @146 POP:1 0142 0000004a 82400000 LOOP_BREAK @148 0144 00000049 83800001 POP @146 POP:1 0146 000000e2 a0000000 ALU 1 @452 0452 80000801 00200c90 60 x: MOV R1.x, R1.z 0148 0000003e 81400000 LOOP_END @124 0150 400000e3 a0280000 ALU 11 @454 KC0[CB0:0-15] 0454 801fa001 2f800010 61 y: ADD T0.y, R1.x, [0xbfc00000 -1.5].x 0456 bfc00000 0458 801fa000 4f82847c 62 z: MULADD T0.z, R0.x, [0x40000000 2].x, T0.y 0460 40000000 0462 801fa87c 60000210 63 w: MIN R0.w, T0.z, [0x41800000 16].x 0464 41800000 0466 801f2c00 0f800010 64 x: ADD T0.x, R0.w, 1.0 0468 001fa080 00030004 65 x: MULADD_IEEE R0.x, KC0[0].x, [0xbe800000 -0.25].x, R4.x 0470 0090007c 20030404 y: MULADD_IEEE R0.y, T0.x, KC0[0].y, R4.y 0472 80900003 400b0404 z: MULADD_IEEE R0.z, R3.x, KC0[0].y, R4.y VEC_120 0474 be800000 0152 000000ee 80400400 TEX 2 @476 0476 00001211 f01f9e00 84810000 SAMPLE_L R0._y__, R0.xyy0, RID:18, SID:2 CT:NNNN 0480 00001211 f01ff200 89010000 SAMPLE_L R0.y___, R0.xzz0, RID:18, SID:2 CT:NNNN 0154 000000f2 a0300000 ALU 13 @484 0484 001fa400 2f800110 66 y: MUL_IEEE T0.y, R0.y, [0x40800000 4].x 0486 801fa000 4f800110 z: MUL_IEEE T0.z, R0.x, [0x40800000 4].x 0488 40800000 0490 00000c00 0f800c91 67 x: MOV T0.x, |R0.w| 0492 0000087c 2f800990 y: RNDNE T0.y, T0.z 0494 00000003 4f800c91 z: MOV T0.z, |R3.x| 0496 8000047c 6f800990 w: RNDNE T0.w, T0.y 0498 001fa47c 0f83087c 68 x: MULADD_IEEE T0.x, T0.y, [0x42040000 33].x, T0.z 0500 801fac7c 6f83007c w: MULADD_IEEE T0.w, T0.w, [0x42040000 33].x, T0.x 0502 42040000 0504 001fa07c 00000110 69 x: MUL_IEEE R0.x, T0.x, [0x3bc7ce0a 0.00609756].x 0506 801fac7c 20000110 y: MUL_IEEE R0.y, T0.w, [0x3bc7ce0a 0.00609756].x 0508 3bc7ce0a 0156 00000100 80400000 TEX 1 @512 0512 00001011 f01f9000 84800000 SAMPLE_L R0.xy__, R0.xyy0, RID:16, SID:0 CT:NNNN 0158 00000102 a8040000 ALU_POP_AFTER 2 @516 0516 00000000 40400c90 70 z: MOV R2.z, R0.x 0518 80000400 60400c90 w: MOV R2.w, R0.y 0160 c0010000 95000688 EXPORT_DONE PIXEL 0 R2.xyzw 0162 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], PERSPECTIVE DCL IN[1], GENERIC[10], PERSPECTIVE DCL IN[2], GENERIC[11], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL SAMP[1] DCL TEMP[0..8] IMM[0] FLT32 { 1.0000, 0.0000, 0.0000, 0.0000} 0: TEX TEMP[0], IN[0].xyyy, SAMP[1], 2D 1: MOV TEMP[1].x, TEMP[0].xxxx 2: TEX TEMP[2].y, IN[2].zwww, SAMP[1], 2D 3: MOV TEMP[1].y, TEMP[2].yyyy 4: MOV TEMP[1].z, TEMP[0].zzzz 5: TEX TEMP[1].w, IN[2].xyyy, SAMP[1], 2D 6: MUL TEMP[4], TEMP[1], TEMP[1] 7: MUL TEMP[5], TEMP[4], TEMP[1] 8: DP4 TEMP[1].x, TEMP[5], IMM[0].xxxx 9: SLT TEMP[4].x, TEMP[1].xxxx, IMM[0].yyyy 10: IF TEMP[4].xxxx :12 11: KILL 12: ENDIF 13: TEX TEMP[4], IN[0].xyyy, SAMP[0], 2D 14: TEX TEMP[6], IN[1].zwww, SAMP[0], 2D 15: ADD TEMP[7].x, IMM[0].xxxx, -TEMP[0].xxxx 16: MUL TEMP[8], TEMP[4], TEMP[7].xxxx 17: MAD TEMP[7], TEMP[6], TEMP[0].xxxx, TEMP[8] 18: MUL TEMP[6], TEMP[7], TEMP[5].xxxx 19: TEX TEMP[7], IN[2].zwww, SAMP[0], 2D 20: ADD TEMP[8].x, IMM[0].xxxx, -TEMP[2].yyyy 21: MUL TEMP[3], TEMP[4], TEMP[8].xxxx 22: MAD TEMP[8], TEMP[7], TEMP[2].yyyy, TEMP[3] 23: MAD TEMP[2], TEMP[8], TEMP[5].yyyy, TEMP[6] 24: TEX TEMP[6], IN[1].xyyy, SAMP[0], 2D 25: ADD TEMP[7].x, IMM[0].xxxx, -TEMP[0].zzzz 26: MUL TEMP[8], TEMP[4], TEMP[7].xxxx 27: MAD TEMP[7], TEMP[6], TEMP[0].zzzz, TEMP[8] 28: MAD TEMP[0], TEMP[7], TEMP[5].zzzz, TEMP[2] 29: TEX TEMP[2], IN[2].xyyy, SAMP[0], 2D 30: ADD TEMP[6].x, IMM[0].xxxx, -TEMP[1].wwww 31: MUL TEMP[7], TEMP[4], TEMP[6].xxxx 32: MAD TEMP[4], TEMP[2], TEMP[1].wwww, TEMP[7] 33: MAD TEMP[2], TEMP[4], TEMP[5].wwww, TEMP[0] 34: RCP TEMP[0].x, TEMP[1].xxxx 35: MUL OUT[0], TEMP[2], TEMP[0].xxxx 36: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg, <4 x float> inreg, <4 x float> inreg) #0 { main_body: %4 = extractelement <4 x float> %0, i32 0 %5 = extractelement <4 x float> %0, i32 1 %6 = call <2 x float> @llvm.R600.interp.xy(i32 0, float %4, float %5) %7 = call <2 x float> @llvm.R600.interp.zw(i32 0, float %4, float %5) %8 = shufflevector <2 x float> %6, <2 x float> %7, <4 x i32> %9 = extractelement <4 x float> %8, i32 0 %10 = extractelement <4 x float> %8, i32 1 %11 = extractelement <4 x float> %0, i32 0 %12 = extractelement <4 x float> %0, i32 1 %13 = call <2 x float> @llvm.R600.interp.xy(i32 1, float %11, float %12) %14 = call <2 x float> @llvm.R600.interp.zw(i32 1, float %11, float %12) %15 = shufflevector <2 x float> %13, <2 x float> %14, <4 x i32> %16 = extractelement <4 x float> %15, i32 0 %17 = extractelement <4 x float> %15, i32 1 %18 = extractelement <4 x float> %15, i32 2 %19 = extractelement <4 x float> %15, i32 3 %20 = extractelement <4 x float> %0, i32 0 %21 = extractelement <4 x float> %0, i32 1 %22 = call <2 x float> @llvm.R600.interp.xy(i32 2, float %20, float %21) %23 = call <2 x float> @llvm.R600.interp.zw(i32 2, float %20, float %21) %24 = shufflevector <2 x float> %22, <2 x float> %23, <4 x i32> %25 = extractelement <4 x float> %24, i32 0 %26 = extractelement <4 x float> %24, i32 1 %27 = extractelement <4 x float> %24, i32 2 %28 = extractelement <4 x float> %24, i32 3 %29 = insertelement <4 x float> undef, float %9, i32 0 %30 = insertelement <4 x float> %29, float %10, i32 1 %31 = insertelement <4 x float> %30, float %10, i32 2 %32 = insertelement <4 x float> %31, float %10, i32 3 %33 = extractelement <4 x float> %32, i32 0 %34 = extractelement <4 x float> %32, i32 1 %35 = insertelement <4 x float> undef, float %33, i32 0 %36 = insertelement <4 x float> %35, float %34, i32 1 %37 = insertelement <4 x float> %36, float undef, i32 2 %38 = insertelement <4 x float> %37, float undef, i32 3 %39 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %38, i32 17, i32 1, i32 2) %40 = extractelement <4 x float> %39, i32 0 %41 = extractelement <4 x float> %39, i32 2 %42 = insertelement <4 x float> undef, float %27, i32 0 %43 = insertelement <4 x float> %42, float %28, i32 1 %44 = insertelement <4 x float> %43, float %28, i32 2 %45 = insertelement <4 x float> %44, float %28, i32 3 %46 = extractelement <4 x float> %45, i32 0 %47 = extractelement <4 x float> %45, i32 1 %48 = insertelement <4 x float> undef, float %46, i32 0 %49 = insertelement <4 x float> %48, float %47, i32 1 %50 = insertelement <4 x float> %49, float undef, i32 2 %51 = insertelement <4 x float> %50, float undef, i32 3 %52 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %51, i32 17, i32 1, i32 2) %53 = extractelement <4 x float> %52, i32 1 %54 = insertelement <4 x float> undef, float %25, i32 0 %55 = insertelement <4 x float> %54, float %26, i32 1 %56 = insertelement <4 x float> %55, float %26, i32 2 %57 = insertelement <4 x float> %56, float %26, i32 3 %58 = extractelement <4 x float> %57, i32 0 %59 = extractelement <4 x float> %57, i32 1 %60 = insertelement <4 x float> undef, float %58, i32 0 %61 = insertelement <4 x float> %60, float %59, i32 1 %62 = insertelement <4 x float> %61, float undef, i32 2 %63 = insertelement <4 x float> %62, float undef, i32 3 %64 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %63, i32 17, i32 1, i32 2) %65 = extractelement <4 x float> %64, i32 3 %66 = fmul float %40, %40 %67 = fmul float %53, %53 %68 = fmul float %41, %41 %69 = fmul float %65, %65 %70 = fmul float %66, %40 %71 = fmul float %67, %53 %72 = fmul float %68, %41 %73 = fmul float %69, %65 %74 = insertelement <4 x float> undef, float %70, i32 0 %75 = insertelement <4 x float> %74, float %71, i32 1 %76 = insertelement <4 x float> %75, float %72, i32 2 %77 = insertelement <4 x float> %76, float %73, i32 3 %78 = call float @llvm.AMDGPU.dp4(<4 x float> %77, <4 x float> ) %79 = fcmp olt float %78, 0x3EE4F8B580000000 %80 = select i1 %79, float 1.000000e+00, float 0.000000e+00 %81 = fcmp une float %80, 0.000000e+00 br i1 %81, label %IF, label %ENDIF IF: ; preds = %main_body call void @llvm.AMDGPU.kilp() br label %ENDIF ENDIF: ; preds = %main_body, %IF %82 = insertelement <4 x float> undef, float %9, i32 0 %83 = insertelement <4 x float> %82, float %10, i32 1 %84 = insertelement <4 x float> %83, float %10, i32 2 %85 = insertelement <4 x float> %84, float %10, i32 3 %86 = extractelement <4 x float> %85, i32 0 %87 = extractelement <4 x float> %85, i32 1 %88 = insertelement <4 x float> undef, float %86, i32 0 %89 = insertelement <4 x float> %88, float %87, i32 1 %90 = insertelement <4 x float> %89, float undef, i32 2 %91 = insertelement <4 x float> %90, float undef, i32 3 %92 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %91, i32 16, i32 0, i32 2) %93 = extractelement <4 x float> %92, i32 0 %94 = extractelement <4 x float> %92, i32 1 %95 = extractelement <4 x float> %92, i32 2 %96 = extractelement <4 x float> %92, i32 3 %97 = insertelement <4 x float> undef, float %18, i32 0 %98 = insertelement <4 x float> %97, float %19, i32 1 %99 = insertelement <4 x float> %98, float %19, i32 2 %100 = insertelement <4 x float> %99, float %19, i32 3 %101 = extractelement <4 x float> %100, i32 0 %102 = extractelement <4 x float> %100, i32 1 %103 = insertelement <4 x float> undef, float %101, i32 0 %104 = insertelement <4 x float> %103, float %102, i32 1 %105 = insertelement <4 x float> %104, float undef, i32 2 %106 = insertelement <4 x float> %105, float undef, i32 3 %107 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %106, i32 16, i32 0, i32 2) %108 = extractelement <4 x float> %107, i32 0 %109 = extractelement <4 x float> %107, i32 1 %110 = extractelement <4 x float> %107, i32 2 %111 = extractelement <4 x float> %107, i32 3 %112 = fsub float -0.000000e+00, %40 %113 = fadd float 1.000000e+00, %112 %114 = fmul float %93, %113 %115 = fmul float %94, %113 %116 = fmul float %95, %113 %117 = fmul float %96, %113 %118 = fmul float %108, %40 %119 = fadd float %118, %114 %120 = fmul float %109, %40 %121 = fadd float %120, %115 %122 = fmul float %110, %40 %123 = fadd float %122, %116 %124 = fmul float %111, %40 %125 = fadd float %124, %117 %126 = fmul float %119, %70 %127 = fmul float %121, %70 %128 = fmul float %123, %70 %129 = fmul float %125, %70 %130 = insertelement <4 x float> undef, float %27, i32 0 %131 = insertelement <4 x float> %130, float %28, i32 1 %132 = insertelement <4 x float> %131, float %28, i32 2 %133 = insertelement <4 x float> %132, float %28, i32 3 %134 = extractelement <4 x float> %133, i32 0 %135 = extractelement <4 x float> %133, i32 1 %136 = insertelement <4 x float> undef, float %134, i32 0 %137 = insertelement <4 x float> %136, float %135, i32 1 %138 = insertelement <4 x float> %137, float undef, i32 2 %139 = insertelement <4 x float> %138, float undef, i32 3 %140 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %139, i32 16, i32 0, i32 2) %141 = extractelement <4 x float> %140, i32 0 %142 = extractelement <4 x float> %140, i32 1 %143 = extractelement <4 x float> %140, i32 2 %144 = extractelement <4 x float> %140, i32 3 %145 = fsub float -0.000000e+00, %53 %146 = fadd float 1.000000e+00, %145 %147 = fmul float %93, %146 %148 = fmul float %94, %146 %149 = fmul float %95, %146 %150 = fmul float %96, %146 %151 = fmul float %141, %53 %152 = fadd float %151, %147 %153 = fmul float %142, %53 %154 = fadd float %153, %148 %155 = fmul float %143, %53 %156 = fadd float %155, %149 %157 = fmul float %144, %53 %158 = fadd float %157, %150 %159 = fmul float %152, %71 %160 = fadd float %159, %126 %161 = fmul float %154, %71 %162 = fadd float %161, %127 %163 = fmul float %156, %71 %164 = fadd float %163, %128 %165 = fmul float %158, %71 %166 = fadd float %165, %129 %167 = insertelement <4 x float> undef, float %16, i32 0 %168 = insertelement <4 x float> %167, float %17, i32 1 %169 = insertelement <4 x float> %168, float %17, i32 2 %170 = insertelement <4 x float> %169, float %17, i32 3 %171 = extractelement <4 x float> %170, i32 0 %172 = extractelement <4 x float> %170, i32 1 %173 = insertelement <4 x float> undef, float %171, i32 0 %174 = insertelement <4 x float> %173, float %172, i32 1 %175 = insertelement <4 x float> %174, float undef, i32 2 %176 = insertelement <4 x float> %175, float undef, i32 3 %177 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %176, i32 16, i32 0, i32 2) %178 = extractelement <4 x float> %177, i32 0 %179 = extractelement <4 x float> %177, i32 1 %180 = extractelement <4 x float> %177, i32 2 %181 = extractelement <4 x float> %177, i32 3 %182 = fsub float -0.000000e+00, %41 %183 = fadd float 1.000000e+00, %182 %184 = fmul float %93, %183 %185 = fmul float %94, %183 %186 = fmul float %95, %183 %187 = fmul float %96, %183 %188 = fmul float %178, %41 %189 = fadd float %188, %184 %190 = fmul float %179, %41 %191 = fadd float %190, %185 %192 = fmul float %180, %41 %193 = fadd float %192, %186 %194 = fmul float %181, %41 %195 = fadd float %194, %187 %196 = fmul float %189, %72 %197 = fadd float %196, %160 %198 = fmul float %191, %72 %199 = fadd float %198, %162 %200 = fmul float %193, %72 %201 = fadd float %200, %164 %202 = fmul float %195, %72 %203 = fadd float %202, %166 %204 = insertelement <4 x float> undef, float %25, i32 0 %205 = insertelement <4 x float> %204, float %26, i32 1 %206 = insertelement <4 x float> %205, float %26, i32 2 %207 = insertelement <4 x float> %206, float %26, i32 3 %208 = extractelement <4 x float> %207, i32 0 %209 = extractelement <4 x float> %207, i32 1 %210 = insertelement <4 x float> undef, float %208, i32 0 %211 = insertelement <4 x float> %210, float %209, i32 1 %212 = insertelement <4 x float> %211, float undef, i32 2 %213 = insertelement <4 x float> %212, float undef, i32 3 %214 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %213, i32 16, i32 0, i32 2) %215 = extractelement <4 x float> %214, i32 0 %216 = extractelement <4 x float> %214, i32 1 %217 = extractelement <4 x float> %214, i32 2 %218 = extractelement <4 x float> %214, i32 3 %219 = fsub float -0.000000e+00, %65 %220 = fadd float 1.000000e+00, %219 %221 = fmul float %93, %220 %222 = fmul float %94, %220 %223 = fmul float %95, %220 %224 = fmul float %96, %220 %225 = fmul float %215, %65 %226 = fadd float %225, %221 %227 = fmul float %216, %65 %228 = fadd float %227, %222 %229 = fmul float %217, %65 %230 = fadd float %229, %223 %231 = fmul float %218, %65 %232 = fadd float %231, %224 %233 = fmul float %226, %73 %234 = fadd float %233, %197 %235 = fmul float %228, %73 %236 = fadd float %235, %199 %237 = fmul float %230, %73 %238 = fadd float %237, %201 %239 = fmul float %232, %73 %240 = fadd float %239, %203 %241 = fdiv float 1.000000e+00, %78 %242 = fmul float %234, %241 %243 = fmul float %236, %241 %244 = fmul float %238, %241 %245 = fmul float %240, %241 %246 = insertelement <4 x float> undef, float %242, i32 0 %247 = insertelement <4 x float> %246, float %243, i32 1 %248 = insertelement <4 x float> %247, float %244, i32 2 %249 = insertelement <4 x float> %248, float %245, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %249, i32 0, i32 0) ret void } ; Function Attrs: readnone declare <2 x float> @llvm.R600.interp.xy(i32, float, float) #1 ; Function Attrs: readnone declare <2 x float> @llvm.R600.interp.zw(i32, float, float) #1 ; Function Attrs: readnone declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32, i32) #1 ; Function Attrs: readnone declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1 declare void @llvm.AMDGPU.kilp() declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } Shader Disassembly: ALU 21, @26, KC0[], KC1[] ; 0000001A A0540000 TEX 2 @10 ; 0000000A 80400800 ALU_PUSH_BEFORE 15, @48, KC0[], KC1[] ; 00000030 A43C0000 JUMP @5 POP:1 ; 00000005 82800001 ALU_POP_AFTER 0, @64, KC0[], KC1[] ; 00000040 A8000000 ALU 3, @65, KC0[], KC1[] ; 00000041 A00C0000 TEX 4 @16 ; 00000010 80401000 ALU 59, @69, KC0[], KC1[] ; 00000045 A0EC0000 EXPORT T4.XYZW ; C0020000 95200688 CF_END ; 00000000 88000000 Fetch clause starting at 10: ; TEX_SAMPLE T2.XYZW, T0.XY__ RID:17 SID:1 CT:NNNN ; 00001110 F00D1002 FC808000 00000000 TEX_SAMPLE T0.XYZW, T4.XY__ RID:17 SID:1 CT:NNNN ; 00041110 F00D1000 FC808000 00000000 TEX_SAMPLE T1.XYZW, T7.XY__ RID:17 SID:1 CT:NNNN ; 00071110 F00D1001 FC808000 00000000 Fetch clause starting at 16: ; TEX_SAMPLE T7.XYZW, T7.XY__ RID:16 SID:0 CT:NNNN ; 00071010 F00D1007 FC800000 00000000 TEX_SAMPLE T6.XYZW, T6.XY__ RID:16 SID:0 CT:NNNN ; 00061010 F00D1006 FC800000 00000000 TEX_SAMPLE T8.XYZW, T10.XY__ RID:16 SID:0 CT:NNNN ; 000A1010 F00D1008 FC800000 00000000 TEX_SAMPLE T9.XYZW, T9.XY__ RID:16 SID:0 CT:NNNN ; 00091010 F00D1009 FC800000 00000000 TEX_SAMPLE T4.XYZW, T4.XY__ RID:16 SID:0 CT:NNNN ; 00041010 F00D1004 FC800000 00000000 ALU clause starting at 26: ; INTERP_XY T4.X, T0.Y, ARRAY_BASE, ; 00380400 00946B10 INTERP_XY T4.Y, T0.X, ARRAY_BASE, ; 00380000 20946B10 INTERP_XY T0.Z (MASKED), T0.Y, ARRAY_BASE, ; 00380400 40146B00 INTERP_XY * T0.W (MASKED), T0.X, ARRAY_BASE, ; 80380000 60146B00 INTERP_XY T6.X, T0.Y, ARRAY_BASE, ; 00382400 00D46B10 INTERP_XY T6.Y, T0.X, ARRAY_BASE, ; 00382000 20D46B10 INTERP_XY T0.Z (MASKED), T0.Y, ARRAY_BASE, ; 00382400 40146B00 INTERP_XY * T0.W (MASKED), T0.X, ARRAY_BASE, ; 80382000 60146B00 INTERP_ZW T0.X (MASKED), T0.Y, ARRAY_BASE, ; 00382400 00146B80 INTERP_ZW T0.Y (MASKED), T0.X, ARRAY_BASE, ; 00382000 20146B80 INTERP_ZW T8.Z, T0.Y, ARRAY_BASE, ; 00382400 41146B90 INTERP_ZW * T5.W, T0.X, ARRAY_BASE, ; 80382000 60B46B90 INTERP_XY T7.X, T0.Y, ARRAY_BASE, ; 00384400 00F46B10 INTERP_XY T7.Y, T0.X, ARRAY_BASE, ; 00384000 20F46B10 INTERP_XY T0.Z (MASKED), T0.Y, ARRAY_BASE, ; 00384400 40146B00 INTERP_XY * T0.W (MASKED), T0.X, ARRAY_BASE, ; 80384000 60146B00 INTERP_ZW T0.X (MASKED), T0.Y, ARRAY_BASE, ; 00384400 00146B80 INTERP_ZW T0.Y (MASKED), T0.X, ARRAY_BASE, ; 00384000 20146B80 INTERP_ZW T5.Z, T0.Y, ARRAY_BASE, ; 00384400 40B46B90 INTERP_ZW * T8.W, T0.X, ARRAY_BASE, ; 80384000 61146B90 MOV T0.X, PV.Z, ; 000008FE 00000C90 MOV * T0.Y, PV.W, ; 80000CFE 20000C90 ALU clause starting at 48: ; MUL_IEEE T3.X, T1.W, T1.W, ; 01802C01 00600110 MUL_IEEE T5.Y, T0.Z, T0.Z, ; 01000800 20A00110 MUL_IEEE T3.Z, T2.Y, T2.Y, ; 00804402 40600110 MUL_IEEE * T3.W, T0.X, T0.X, ; 80000000 60600110 MUL_IEEE T5.X, PV.W, T0.X, ; 00000CFE 00A00110 MUL_IEEE T3.Y, PV.Z, T2.Y, ; 008048FE 20600110 MUL_IEEE T3.Z, PV.Y, T0.Z, ; 010004FE 40600110 MUL_IEEE * T3.W, PV.X, T1.W, ; 818020FE 60600110 DOT4 T3.X, T5.X, 1.0, ; 001F2005 00605F10 DOT4 T3.Y (MASKED), T3.Y, 1.0, ; 001F2403 20605F00 DOT4 T3.Z (MASKED), T3.Z, 1.0, ; 001F2803 40605F00 DOT4 * T3.W (MASKED), T3.W, 1.0, ; 801F2C03 60605F00 SETGT * T9.W, literal.x, PV.X, ; 801FC0FD 61200490 925353388(1.000000e-05), 0(0.000000e+00) ; 3727C5AC 00000000 SETE_DX10 * T9.W, PV.W, 0.0, ; 801F0CFE 61200610 PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002104 ALU clause starting at 64: ; KILLGT * T5.Y (MASKED), 1.0, 0.0, ; 801F00F9 20A01680 ALU clause starting at 65: ; MOV * T9.X, T8.Z, ; 80000808 01200C90 MOV T10.X, T5.Z, ; 00000805 01400C90 MOV * T9.Y, T5.W, ; 80000C05 21200C90 MOV * T10.Y, T8.W, ; 80000C08 21400C90 ALU clause starting at 69: ; ADD * T5.W, -T0.X, 1.0, ; 801F3000 60A00010 MUL_IEEE T5.Z, T4.Z, PV.W, ; 019FC804 40A00110 ADD * T10.W, -T2.Y, 1.0, ; 801F3402 61400010 MUL_IEEE T5.Y, T4.Z, PV.W, ; 019FC804 20A00110 MULADD_IEEE T5.Z, T9.Z, T0.X, PV.Z, BS:VEC_120/SCL_212 ; 00000809 40AB08FE ADD * T11.W, -T0.Z, 1.0, BS:VEC_201 ; 801F3800 61700010 MUL_IEEE T10.X, T4.Z, PV.W, ; 019FC804 01400110 MUL_IEEE T10.Y, PV.Z, T5.X, ; 0000A8FE 21400110 MULADD_IEEE T5.Z, T8.Z, T2.Y, PV.Y, BS:VEC_120/SCL_212 ; 00804808 40AB04FE ADD * T12.W, -T1.W, 1.0, ; 801F3C01 61800010 MUL_IEEE T5.Y, T4.Z, PV.W, ; 019FC804 20A00110 MULADD_IEEE T5.Z, PV.Z, T3.Y, PV.Y, ; 008068FE 40A304FE MULADD_IEEE * T13.W, T6.Z, T0.Z, PV.X, BS:VEC_120/SCL_212 ; 81000806 61AB00FE MULADD_IEEE T10.X, PV.W, T3.Z, PV.Z, ; 01006CFE 014308FE MULADD_IEEE T5.Y, T7.Z, T1.W, PV.Y, ; 01802807 20A304FE MUL_IEEE * T5.Z, T4.W, T12.W, BS:VEC_021/SCL_122 ; 81818C04 40A40110 MUL_IEEE * T13.W, T4.X, T5.W, ; 8180A004 61A00110 MUL_IEEE T11.X, T4.W, T11.W, ; 01816C04 01600110 MUL_IEEE * T10.Y, T4.W, T5.W, BS:VEC_021/SCL_122 ; 8180AC04 21440110 MUL_IEEE T10.Z, T4.X, T10.W, ; 01814004 41400110 MULADD_IEEE * T13.W, T9.X, T0.X, T13.W, BS:VEC_120/SCL_212 ; 80000009 61AB0C0D MUL_IEEE T12.X, T4.X, T11.W, ; 01816004 01800110 MUL_IEEE T11.Y, PV.W, T5.X, ; 0000ACFE 21600110 MULADD_IEEE * T10.Z, T8.X, T2.Y, PV.Z, BS:VEC_201 ; 80804008 415308FE MULADD_IEEE * T13.W, T9.W, T0.X, T10.Y, ; 80000C09 61A3040A MUL_IEEE T13.X, PV.W, T5.X, ; 0000ACFE 01A00110 MUL_IEEE T10.Y, T4.Y, T5.W, ; 0180A404 21400110 MULADD_IEEE T10.Z, T10.Z, T3.Y, T11.Y, ; 0080680A 4143040B MULADD_IEEE * T5.W, T6.X, T0.Z, T12.X, ; 81000006 60A3000C MULADD_IEEE T12.X, PV.W, T3.Z, PV.Z, ; 01006CFE 018308FE MUL_IEEE T11.Y, T4.Y, T10.W, ; 01814404 21600110 MULADD_IEEE T9.Z, T9.Y, T0.X, PV.Y, BS:VEC_120/SCL_212 ; 00000409 412B04FE MUL_IEEE * T5.W, T4.X, T12.W, BS:VEC_021/SCL_122 ; 81818004 60A40110 MULADD_IEEE T9.X, T7.X, T1.W, PV.W, ; 01802007 01230CFE MUL_IEEE T9.Y, T4.Y, T11.W, BS:VEC_021/SCL_122 ; 01816404 21240110 MUL_IEEE T9.Z, PV.Z, T5.X, ; 0000A8FE 41200110 MULADD_IEEE * T5.W, T8.Y, T2.Y, PV.Y, BS:VEC_120/SCL_212 ; 80804408 60AB04FE MUL_IEEE T5.X, T4.Y, T12.W, ; 01818404 00A00110 MULADD_IEEE T10.Y, PV.W, T3.Y, PV.Z, ; 00806CFE 214308FE MULADD_IEEE T9.Z, T6.Y, T0.Z, PV.Y, BS:VEC_201 ; 01000406 413304FE MUL_IEEE * T4.W, T4.W, T10.W, BS:VEC_021/SCL_122 ; 81814C04 60840110 MULADD_IEEE T2.X, T8.W, T2.Y, PV.W, ; 00804C08 00430CFE MULADD_IEEE T2.Y, PV.Z, T3.Z, PV.Y, ; 010068FE 204304FE MULADD_IEEE T2.Z, T7.Y, T1.W, PV.X, ; 01802407 404300FE MULADD_IEEE * T2.W, T9.X, T3.W, T12.X, BS:VEC_021/SCL_122 ; 81806009 6047000C RECIP_IEEE T3.X, T3.X, ; 00000003 00604310 RECIP_IEEE T3.Y (MASKED), T3.X, ; 00000003 20604300 RECIP_IEEE T3.Z (MASKED), T3.X, ; 00000003 40604300 RECIP_IEEE * T3.W (MASKED), T3.X, ; 80000003 60604300 MUL_IEEE T4.X, T2.W, PV.X, ; 001FCC02 00800110 MULADD_IEEE T2.Y, T2.Z, T3.W, T2.Y, ; 01806802 20430402 MULADD_IEEE T2.Z, T2.X, T3.Y, T13.X, BS:VEC_102/SCL_221 ; 00806002 404F000D MULADD_IEEE * T0.W, T6.W, T0.Z, T11.X, BS:VEC_210 ; 81000C06 6017000B MULADD_IEEE T0.X, PV.W, T3.Z, PV.Z, ; 01006CFE 000308FE MUL_IEEE T4.Y, PV.Y, T3.X, ; 000064FE 20800110 MULADD_IEEE T0.Z, T7.W, T1.W, T5.Z, ; 01802C07 40030805 MULADD_IEEE * T0.W, T5.Y, T3.W, T10.X, BS:VEC_120/SCL_212 ; 81806405 600B000A MUL_IEEE T4.Z, PV.W, T3.X, ; 00006CFE 40800110 MULADD_IEEE * T0.W, PV.Z, T3.W, PV.X, ; 818068FE 600300FE MUL_IEEE * T4.W, PV.W, T3.X, ; 80006CFE 60800110 ===== SHADER #27 ======================================== PS/CAYMAN/CAYMAN ===== ===== 258 dw ===== 14 gprs ===== 1 stack ======================================= 0000 0000001a a0540000 ALU 22 @52 0052 00380400 00946b10 1 x: INTERP_XY R4.x, R0.y, Param0.x VEC_210 0054 00380000 20946b10 y: INTERP_XY R4.y, R0.x, Param0.x VEC_210 0056 00380400 40146b00 z: INTERP_XY __.z, R0.y, Param0.x VEC_210 0058 80380000 60146b00 w: INTERP_XY __.w, R0.x, Param0.x VEC_210 0060 00382400 00d46b10 2 x: INTERP_XY R6.x, R0.y, Param1.x VEC_210 0062 00382000 20d46b10 y: INTERP_XY R6.y, R0.x, Param1.x VEC_210 0064 00382400 40146b00 z: INTERP_XY __.z, R0.y, Param1.x VEC_210 0066 80382000 60146b00 w: INTERP_XY __.w, R0.x, Param1.x VEC_210 0068 00382400 00146b80 3 x: INTERP_ZW __.x, R0.y, Param1.x VEC_210 0070 00382000 20146b80 y: INTERP_ZW __.y, R0.x, Param1.x VEC_210 0072 00382400 41146b90 z: INTERP_ZW R8.z, R0.y, Param1.x VEC_210 0074 80382000 60b46b90 w: INTERP_ZW R5.w, R0.x, Param1.x VEC_210 0076 00384400 00f46b10 4 x: INTERP_XY R7.x, R0.y, Param2.x VEC_210 0078 00384000 20f46b10 y: INTERP_XY R7.y, R0.x, Param2.x VEC_210 0080 00384400 40146b00 z: INTERP_XY __.z, R0.y, Param2.x VEC_210 0082 80384000 60146b00 w: INTERP_XY __.w, R0.x, Param2.x VEC_210 0084 00384400 00146b80 5 x: INTERP_ZW __.x, R0.y, Param2.x VEC_210 0086 00384000 20146b80 y: INTERP_ZW __.y, R0.x, Param2.x VEC_210 0088 00384400 40b46b90 z: INTERP_ZW R5.z, R0.y, Param2.x VEC_210 0090 80384000 61146b90 w: INTERP_ZW R8.w, R0.x, Param2.x VEC_210 0092 000008fe 00000c90 6 x: MOV R0.x, PV.z 0094 80000cfe 20000c90 y: MOV R0.y, PV.w 0002 0000000a 80400800 TEX 3 @20 0020 00001110 f00d1002 fc808000 SAMPLE R2.xyzw, R0.xy__, RID:17, SID:1 CT:NNNN 0024 00041110 f00d1000 fc808000 SAMPLE R0.xyzw, R4.xy__, RID:17, SID:1 CT:NNNN 0028 00071110 f00d1001 fc808000 SAMPLE R1.xyzw, R7.xy__, RID:17, SID:1 CT:NNNN 0004 00000030 a43c0000 ALU_PUSH_BEFORE 16 @96 0096 01802c01 00600110 7 x: MUL_IEEE R3.x, R1.w, R1.w 0098 01000800 20a00110 y: MUL_IEEE R5.y, R0.z, R0.z 0100 00804402 40600110 z: MUL_IEEE R3.z, R2.y, R2.y 0102 80000000 60600110 w: MUL_IEEE R3.w, R0.x, R0.x 0104 00000cfe 00a00110 8 x: MUL_IEEE R5.x, PV.w, R0.x 0106 008048fe 20600110 y: MUL_IEEE R3.y, PV.z, R2.y 0108 010004fe 40600110 z: MUL_IEEE R3.z, PV.y, R0.z 0110 818020fe 60600110 w: MUL_IEEE R3.w, PV.x, R1.w 0112 001f2005 00605f10 9 x: DOT4 R3.x, R5.x, 1.0 0114 001f2403 20605f00 y: DOT4 __.y, R3.y, 1.0 0116 001f2803 40605f00 z: DOT4 __.z, R3.z, 1.0 0118 801f2c03 60605f00 w: DOT4 __.w, R3.w, 1.0 0120 801fc0fd 61200490 10 w: SETGT R9.w, [0x3727c5ac 1e-05].x, PV.x 0122 3727c5ac 0124 801f0cfe 61200610 11 w: SETE_DX10 R9.w, PV.w, 0 0126 801f0cfe 00002104 12 M x: PRED_SETE_INT __.x, PV.w, 0 0006 00000005 82800001 JUMP @10 POP:1 0008 00000040 a8000000 ALU_POP_AFTER 1 @128 0128 801f00f9 20a01680 13 y: KILLGT __.y, 1.0, 0 0010 00000041 a00c0000 ALU 4 @130 0130 80000808 01200c90 14 x: MOV R9.x, R8.z 0132 00000805 01400c90 15 x: MOV R10.x, R5.z 0134 80000c05 21200c90 y: MOV R9.y, R5.w 0136 80000c08 21400c90 16 y: MOV R10.y, R8.w 0012 00000010 80401000 TEX 5 @32 0032 00071010 f00d1007 fc800000 SAMPLE R7.xyzw, R7.xy__, RID:16, SID:0 CT:NNNN 0036 00061010 f00d1006 fc800000 SAMPLE R6.xyzw, R6.xy__, RID:16, SID:0 CT:NNNN 0040 000a1010 f00d1008 fc800000 SAMPLE R8.xyzw, R10.xy__, RID:16, SID:0 CT:NNNN 0044 00091010 f00d1009 fc800000 SAMPLE R9.xyzw, R9.xy__, RID:16, SID:0 CT:NNNN 0048 00041010 f00d1004 fc800000 SAMPLE R4.xyzw, R4.xy__, RID:16, SID:0 CT:NNNN 0014 00000045 a0ec0000 ALU 60 @138 0138 801f3000 60a00010 17 w: ADD R5.w, -R0.x, 1.0 0140 019fc804 40a00110 18 z: MUL_IEEE R5.z, R4.z, PV.w 0142 801f3402 61400010 w: ADD R10.w, -R2.y, 1.0 0144 019fc804 20a00110 19 y: MUL_IEEE R5.y, R4.z, PV.w 0146 00000809 40ab08fe z: MULADD_IEEE R5.z, R9.z, R0.x, PV.z VEC_120 0148 801f3800 61700010 w: ADD R11.w, -R0.z, 1.0 VEC_201 0150 019fc804 01400110 20 x: MUL_IEEE R10.x, R4.z, PV.w 0152 0000a8fe 21400110 y: MUL_IEEE R10.y, PV.z, R5.x 0154 00804808 40ab04fe z: MULADD_IEEE R5.z, R8.z, R2.y, PV.y VEC_120 0156 801f3c01 61800010 w: ADD R12.w, -R1.w, 1.0 0158 019fc804 20a00110 21 y: MUL_IEEE R5.y, R4.z, PV.w 0160 008068fe 40a304fe z: MULADD_IEEE R5.z, PV.z, R3.y, PV.y 0162 81000806 61ab00fe w: MULADD_IEEE R13.w, R6.z, R0.z, PV.x VEC_120 0164 01006cfe 014308fe 22 x: MULADD_IEEE R10.x, PV.w, R3.z, PV.z 0166 01802807 20a304fe y: MULADD_IEEE R5.y, R7.z, R1.w, PV.y 0168 81818c04 40a40110 z: MUL_IEEE R5.z, R4.w, R12.w VEC_021 0170 8180a004 61a00110 23 w: MUL_IEEE R13.w, R4.x, R5.w 0172 01816c04 01600110 24 x: MUL_IEEE R11.x, R4.w, R11.w 0174 8180ac04 21440110 y: MUL_IEEE R10.y, R4.w, R5.w VEC_021 0176 01814004 41400110 25 z: MUL_IEEE R10.z, R4.x, R10.w 0178 80000009 61ab0c0d w: MULADD_IEEE R13.w, R9.x, R0.x, R13.w VEC_120 0180 01816004 01800110 26 x: MUL_IEEE R12.x, R4.x, R11.w 0182 0000acfe 21600110 y: MUL_IEEE R11.y, PV.w, R5.x 0184 80804008 415308fe z: MULADD_IEEE R10.z, R8.x, R2.y, PV.z VEC_201 0186 80000c09 61a3040a 27 w: MULADD_IEEE R13.w, R9.w, R0.x, R10.y 0188 0000acfe 01a00110 28 x: MUL_IEEE R13.x, PV.w, R5.x 0190 0180a404 21400110 y: MUL_IEEE R10.y, R4.y, R5.w 0192 0080680a 4143040b z: MULADD_IEEE R10.z, R10.z, R3.y, R11.y 0194 81000006 60a3000c w: MULADD_IEEE R5.w, R6.x, R0.z, R12.x 0196 01006cfe 018308fe 29 x: MULADD_IEEE R12.x, PV.w, R3.z, PV.z 0198 01814404 21600110 y: MUL_IEEE R11.y, R4.y, R10.w 0200 00000409 412b04fe z: MULADD_IEEE R9.z, R9.y, R0.x, PV.y VEC_120 0202 81818004 60a40110 w: MUL_IEEE R5.w, R4.x, R12.w VEC_021 0204 01802007 01230cfe 30 x: MULADD_IEEE R9.x, R7.x, R1.w, PV.w 0206 01816404 21240110 y: MUL_IEEE R9.y, R4.y, R11.w VEC_021 0208 0000a8fe 41200110 z: MUL_IEEE R9.z, PV.z, R5.x 0210 80804408 60ab04fe w: MULADD_IEEE R5.w, R8.y, R2.y, PV.y VEC_120 0212 01818404 00a00110 31 x: MUL_IEEE R5.x, R4.y, R12.w 0214 00806cfe 214308fe y: MULADD_IEEE R10.y, PV.w, R3.y, PV.z 0216 01000406 413304fe z: MULADD_IEEE R9.z, R6.y, R0.z, PV.y VEC_201 0218 81814c04 60840110 w: MUL_IEEE R4.w, R4.w, R10.w VEC_021 0220 00804c08 00430cfe 32 x: MULADD_IEEE R2.x, R8.w, R2.y, PV.w 0222 010068fe 204304fe y: MULADD_IEEE R2.y, PV.z, R3.z, PV.y 0224 01802407 404300fe z: MULADD_IEEE R2.z, R7.y, R1.w, PV.x 0226 81806009 6047000c w: MULADD_IEEE R2.w, R9.x, R3.w, R12.x VEC_021 0228 00000003 00604310 33 x: RECIP_IEEE R3.x, R3.x 0230 00000003 20604300 y: RECIP_IEEE __.y, R3.x 0232 00000003 40604300 z: RECIP_IEEE __.z, R3.x 0234 80000003 60604300 w: RECIP_IEEE __.w, R3.x 0236 001fcc02 00800110 34 x: MUL_IEEE R4.x, R2.w, PV.x 0238 01806802 20430402 y: MULADD_IEEE R2.y, R2.z, R3.w, R2.y 0240 00806002 404f000d z: MULADD_IEEE R2.z, R2.x, R3.y, R13.x VEC_102 0242 81000c06 6017000b w: MULADD_IEEE R0.w, R6.w, R0.z, R11.x VEC_210 0244 01006cfe 000308fe 35 x: MULADD_IEEE R0.x, PV.w, R3.z, PV.z 0246 000064fe 20800110 y: MUL_IEEE R4.y, PV.y, R3.x 0248 01802c07 40030805 z: MULADD_IEEE R0.z, R7.w, R1.w, R5.z 0250 81806405 600b000a w: MULADD_IEEE R0.w, R5.y, R3.w, R10.x VEC_120 0252 00006cfe 40800110 36 z: MUL_IEEE R4.z, PV.w, R3.x 0254 818068fe 600300fe w: MULADD_IEEE R0.w, PV.z, R3.w, PV.x 0256 80006cfe 60800110 37 w: MUL_IEEE R4.w, PV.w, R3.x 0016 c0020000 95200688 EXPORT_DONE PIXEL 0 R4.xyzw 0018 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #27 OPT ==================================== PS/CAYMAN/CAYMAN ===== ===== 236 dw ===== 8 gprs ===== 0 stack ======================================== 0000 00000007 a02c0000 ALU 12 @14 0014 00384400 00146b80 1 x: INTERP_ZW __.x, R0.y, Param2.x VEC_210 0016 00b84000 20146b80 y: INTERP_ZW __.y, R0.x, Param2.y VEC_210 0018 01384400 40546b90 z: INTERP_ZW R2.z, R0.y, Param2.z VEC_210 0020 81b84000 60546b90 w: INTERP_ZW R2.w, R0.x, Param2.w VEC_210 0022 00380400 00346b10 2 x: INTERP_XY R1.x, R0.y, Param0.x VEC_210 0024 00b80000 20346b10 y: INTERP_XY R1.y, R0.x, Param0.y VEC_210 0026 01380400 40146b00 z: INTERP_XY __.z, R0.y, Param0.z VEC_210 0028 81b80000 60146b00 w: INTERP_XY __.w, R0.x, Param0.w VEC_210 0030 00384400 00946b10 3 x: INTERP_XY R4.x, R0.y, Param2.x VEC_210 0032 00b84000 20946b10 y: INTERP_XY R4.y, R0.x, Param2.y VEC_210 0034 01384400 40146b00 z: INTERP_XY __.z, R0.y, Param2.z VEC_210 0036 81b84000 60146b00 w: INTERP_XY __.w, R0.x, Param2.w VEC_210 0002 00000014 80400800 TEX 3 @40 0040 00041110 f01dfe05 fc808000 SAMPLE R5.__w_, R4.xy__, RID:17, SID:1 CT:NNNN 0044 00011110 f01fa005 fc808000 SAMPLE R5.xz__, R1.xy__, RID:17, SID:1 CT:NNNN 0048 00021110 f007fe05 fda08000 SAMPLE R5.___y, R2.zw__, RID:17, SID:1 CT:NNNN 0004 0000001a a0540000 ALU 22 @52 0052 0180ac05 0f800110 4 x: MUL_IEEE T0.x, R5.w, R5.w 0054 0000a005 2f800110 y: MUL_IEEE T0.y, R5.x, R5.x 0056 0100a805 4f800110 z: MUL_IEEE T0.z, R5.z, R5.z 0058 8080a405 6f800110 w: MUL_IEEE T0.w, R5.y, R5.y 0060 0000a47c 00c00110 5 x: MUL_IEEE R6.x, T0.y, R5.x 0062 0180a07c 20c00110 y: MUL_IEEE R6.y, T0.x, R5.w 0064 0080ac7c 40e00110 z: MUL_IEEE R7.z, T0.w, R5.y 0066 8100a87c 60c00110 w: MUL_IEEE R6.w, T0.z, R5.z 0068 001f2006 00005f00 6 x: DOT4 __.x, R6.x, 1.0 0070 001f2406 20005f00 y: DOT4 __.y, R6.y, 1.0 0072 001f2807 40c05f10 z: DOT4 R6.z, R7.z, 1.0 0074 801f2c06 60005f00 w: DOT4 __.w, R6.w, 1.0 0076 00382400 00746b10 7 x: INTERP_XY R3.x, R0.y, Param1.x VEC_210 0078 00b82000 20746b10 y: INTERP_XY R3.y, R0.x, Param1.y VEC_210 0080 01382400 40146b00 z: INTERP_XY __.z, R0.y, Param1.z VEC_210 0082 81b82000 60146b00 w: INTERP_XY __.w, R0.x, Param1.w VEC_210 0084 00382400 00146b80 8 x: INTERP_ZW __.x, R0.y, Param1.x VEC_210 0086 00b82000 20146b80 y: INTERP_ZW __.y, R0.x, Param1.y VEC_210 0088 01382400 40346b90 z: INTERP_ZW R1.z, R0.y, Param1.z VEC_210 0090 81b82000 60346b90 w: INTERP_ZW R1.w, R0.x, Param1.w VEC_210 0092 8100c0fd 00001680 9 x: KILLGT __.x, [0x3727c5ac 1e-05].x, R6.z 0094 3727c5ac 0006 00000030 80401000 TEX 5 @96 0096 00011010 f00d1000 fc800000 SAMPLE R0.xyzw, R1.xy__, RID:16, SID:0 CT:NNNN 0100 00011010 f00d1001 fda00000 SAMPLE R1.xyzw, R1.zw__, RID:16, SID:0 CT:NNNN 0104 00021010 f00d1002 fda00000 SAMPLE R2.xyzw, R2.zw__, RID:16, SID:0 CT:NNNN 0108 00031010 f00d1003 fc800000 SAMPLE R3.xyzw, R3.xy__, RID:16, SID:0 CT:NNNN 0112 00041010 f00d1004 fc800000 SAMPLE R4.xyzw, R4.xy__, RID:16, SID:0 CT:NNNN 0008 0000003a a0ec0000 ALU 60 @116 0116 801f3005 6f800010 10 w: ADD T0.w, -R5.x, 1.0 0118 818f8000 0f800110 11 x: MUL_IEEE T0.x, R0.x, T0.w 0120 001f3c05 0f800010 12 x: ADD T0.x, -R5.w, 1.0 0122 0000a001 2fa3007c y: MULADD_IEEE T1.y, R1.x, R5.x, T0.x 0124 818f8800 4fa00110 z: MUL_IEEE T1.z, R0.z, T0.w 0126 018f8c00 2f800110 13 y: MUL_IEEE T0.y, R0.w, T0.w 0128 000f8c00 4f800110 z: MUL_IEEE T0.z, R0.w, T0.x 0130 818f8400 6f800110 w: MUL_IEEE T0.w, R0.y, T0.w 0132 000f8000 0fa00110 14 x: MUL_IEEE T1.x, R0.x, T0.x 0134 001f3405 2ff00010 y: ADD T3.y, -R5.y, 1.0 VEC_201 0136 000f8400 4fc00110 z: MUL_IEEE T2.z, R0.y, T0.x 0138 8000ac01 6fc7047c w: MULADD_IEEE T2.w, R1.w, R5.x, T0.y VEC_021 0140 000f8800 0f900110 15 x: MUL_IEEE T0.x, R0.z, T0.x VEC_201 0142 0000a801 2f87087d y: MULADD_IEEE T0.y, R1.z, R5.x, T1.z VEC_021 0144 0000c47d 4fa00110 z: MUL_IEEE T1.z, T1.y, R6.x 0146 8000a401 6f8b0c7c w: MULADD_IEEE T0.w, R1.y, R5.x, T0.w VEC_120 0148 0180ac02 0fc3087c 16 x: MULADD_IEEE T2.x, R2.w, R5.w, T0.z 0150 0180a002 2fc7007d y: MULADD_IEEE T2.y, R2.x, R5.w, T1.x VEC_021 0152 001f3805 4fe80010 z: ADD T3.z, -R5.z, 1.0 VEC_120 0154 8180a802 6fa3007c w: MULADD_IEEE T1.w, R2.z, R5.w, T0.x 0156 0000c47c 0fa00110 17 x: MUL_IEEE T1.x, T0.y, R6.x 0158 0000cc7e 2fa80110 y: MUL_IEEE T1.y, T2.w, R6.x VEC_120 0160 008fe800 4f800110 z: MUL_IEEE T0.z, R0.z, T3.y 0162 808fec00 6fc00110 w: MUL_IEEE T2.w, R0.w, T3.y 0164 008fe000 0f800110 18 x: MUL_IEEE T0.x, R0.x, T3.y 0166 008fe400 2f940110 y: MUL_IEEE T0.y, R0.y, T3.y VEC_210 0168 0180a402 4fc3087e z: MULADD_IEEE T2.z, R2.y, R5.w, T2.z 0170 8000cc7c 6f800110 w: MUL_IEEE T0.w, T0.w, R6.x 0172 0080cc7d 0fe3007d 19 x: MULADD_IEEE T3.x, T1.w, R6.y, T1.x 0174 0080c07e 2fc3047d y: MULADD_IEEE T2.y, T2.x, R6.y, T1.y 0176 0080c47e 4fa3087d z: MULADD_IEEE T1.z, T2.y, R6.y, T1.z 0178 810fec00 6fac0110 w: MUL_IEEE T1.w, R0.w, T3.z VEC_102 0180 0080ac03 0fa30c7e 20 x: MULADD_IEEE T1.x, R3.w, R5.y, T2.w 0182 0080a003 2fa3007c y: MULADD_IEEE T1.y, R3.x, R5.y, T0.x 0184 0080a403 4f83047c z: MULADD_IEEE T0.z, R3.y, R5.y, T0.y 0186 8080a803 6fc3087c w: MULADD_IEEE T2.w, R3.z, R5.y, T0.z 0188 010fe000 0f800110 21 x: MUL_IEEE T0.x, R0.x, T3.z 0190 010fe400 2f940110 y: MUL_IEEE T0.y, R0.y, T3.z VEC_210 0192 010fe800 4fc00110 z: MUL_IEEE T2.z, R0.z, T3.z 0194 8080c87e 6f930c7c w: MULADD_IEEE T0.w, T2.z, R6.y, T0.w VEC_201 0196 0100e07d 0fc3047e 22 x: MULADD_IEEE T2.x, T1.x, R7.z, T2.y 0198 0100e47d 4fa3087d z: MULADD_IEEE T1.z, T1.y, R7.z, T1.z 0200 8100ac04 6faf0c7d w: MULADD_IEEE T1.w, R4.w, R5.z, T1.w VEC_102 0202 0100e87c 0fa30c7c 23 x: MULADD_IEEE T1.x, T0.z, R7.z, T0.w 0204 0100a004 2fa7007c y: MULADD_IEEE T1.y, R4.x, R5.z, T0.x VEC_021 0206 0100ec7e 4f83007f z: MULADD_IEEE T0.z, T2.w, R7.z, T3.x 0208 8100a404 6f87047c w: MULADD_IEEE T0.w, R4.y, R5.z, T0.y VEC_021 0210 00000806 0f804310 24 x: RECIP_IEEE T0.x, R6.z 0212 00000806 20004300 y: RECIP_IEEE __.y, R6.z 0214 00000806 40004300 z: RECIP_IEEE __.z, R6.z 0216 80000806 60004300 w: RECIP_IEEE __.w, R6.z 0218 0100a804 2f83087e 25 y: MULADD_IEEE T0.y, R4.z, R5.z, T2.z 0220 8180cc7d 6fa3007e w: MULADD_IEEE T1.w, T1.w, R6.w, T2.x 0222 0180c47c 2f8b087c 26 y: MULADD_IEEE T0.y, T0.y, R6.w, T0.z VEC_120 0224 0180cc7c 4f83007d z: MULADD_IEEE T0.z, T0.w, R6.w, T1.x 0226 8180c47d 6f83087d w: MULADD_IEEE T0.w, T1.y, R6.w, T1.z 0228 000f8c7c 00000110 27 x: MUL_IEEE R0.x, T0.w, T0.x 0230 000f887c 20000110 y: MUL_IEEE R0.y, T0.z, T0.x 0232 000f847c 40000110 z: MUL_IEEE R0.z, T0.y, T0.x 0234 800f8c7d 60080110 w: MUL_IEEE R0.w, T1.w, T0.x VEC_120 0010 c0000000 95000688 EXPORT_DONE PIXEL 0 R0.xyzw 0012 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== Installing breakpad exception handler for appid(steam)/version(1390852599_client) unlinked 0 orphaned pipes (steam:15114): Gtk-WARNING **: Unable to locate theme engine in module_path: "xfce", (steam:15114): Gtk-WARNING **: Unable to locate theme engine in module_path: "xfce", (steam:15114): Gtk-WARNING **: Unable to locate theme engine in module_path: "xfce", (steam:15114): Gtk-WARNING **: Unable to locate theme engine in module_path: "xfce", (steam:15114): Gtk-WARNING **: Unable to locate theme engine in module_path: "xfce", (steam:15114): Gtk-WARNING **: Unable to locate theme engine in module_path: "xfce", (steam:15114): Gtk-WARNING **: Unable to locate theme engine in module_path: "xfce", (steam:15114): Gtk-WARNING **: Unable to locate theme engine in module_path: "xfce", (steam:15114): Gtk-WARNING **: Unable to locate theme engine in module_path: "xfce", (steam:15114): Gtk-WARNING **: Unable to locate theme engine in module_path: "xfce", (steam:15114): Gtk-WARNING **: Unable to locate theme engine in module_path: "xfce", Installing breakpad exception handler for appid(steam)/version(1390852599_client) [0131/185103:WARNING:proxy_service.cc(958)] PAC support disabled because there is no system implementation -------------------------------------------------------------- [2014-01-31 18:51:03] Verifying installation... [2014-01-31 18:51:03] Verification complete FRAG 0: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg) #0 { main_body: call void @llvm.R600.store.dummy(i32 0) ret void } declare void @llvm.R600.store.dummy(i32) attributes #0 = { "ShaderType"="0" } Shader Disassembly: EXPORT T0.____ ; C0000000 95200FFF CF_END ; 00000000 88000000 ===== SHADER #33 ======================================== PS/CAYMAN/CAYMAN ===== ===== 4 dw ===== 1 gprs ===== 1 stack ========================================== 0000 c0000000 95200fff EXPORT_DONE PIXEL 0 R0.____ 0002 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #33 OPT ==================================== PS/CAYMAN/CAYMAN ===== ===== 4 dw ===== 0 gprs ===== 0 stack ========================================== 0000 c0000000 95000fff EXPORT_DONE PIXEL 0 R0.____ 0002 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- FRAG DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg) #0 { main_body: %2 = call <4 x float> @llvm.R600.interp.const(i32 0) %3 = extractelement <4 x float> %2, i32 0 %4 = extractelement <4 x float> %2, i32 1 %5 = extractelement <4 x float> %2, i32 2 %6 = extractelement <4 x float> %2, i32 3 %7 = insertelement <4 x float> undef, float %3, i32 0 %8 = insertelement <4 x float> %7, float %4, i32 1 %9 = insertelement <4 x float> %8, float %5, i32 2 %10 = insertelement <4 x float> %9, float %6, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %10, i32 0, i32 0) ret void } ; Function Attrs: readnone declare <4 x float> @llvm.R600.interp.const(i32) #1 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } Shader Disassembly: ALU 3, @4, KC0[], KC1[] ; 00000004 A00C0000 EXPORT T0.XYZW ; C0000000 95200688 CF_END ; 00000000 88000000 PAD ; 00000000 00000000 ALU clause starting at 4: ; INTERP_LOAD_P0 T0.X, ARRAY_BASE, ; 000001C0 00007010 INTERP_LOAD_P0 T0.Y, ARRAY_BASE, ; 000001C0 20007010 INTERP_LOAD_P0 T0.Z, ARRAY_BASE, ; 000001C0 40007010 INTERP_LOAD_P0 * T0.W, ARRAY_BASE, ; 800001C0 60007010 ===== SHADER #34 ======================================== PS/CAYMAN/CAYMAN ===== ===== 16 dw ===== 1 gprs ===== 1 stack ========================================= 0000 00000004 a00c0000 ALU 4 @8 0008 000001c0 00007010 1 x: INTERP_LOAD_P0 R0.x, Param0.x 0010 000001c0 20007010 y: INTERP_LOAD_P0 R0.y, Param0.x 0012 000001c0 40007010 z: INTERP_LOAD_P0 R0.z, Param0.x 0014 800001c0 60007010 w: INTERP_LOAD_P0 R0.w, Param0.x 0002 c0000000 95200688 EXPORT_DONE PIXEL 0 R0.xyzw 0004 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #34 OPT ==================================== PS/CAYMAN/CAYMAN ===== ===== 14 dw ===== 1 gprs ===== 0 stack ========================================= 0000 00000003 a00c0000 ALU 4 @6 0006 000001c0 00007010 1 x: INTERP_LOAD_P0 R0.x, Param0.x 0008 000005c0 20007010 y: INTERP_LOAD_P0 R0.y, Param0.y 0010 000009c0 40007010 z: INTERP_LOAD_P0 R0.z, Param0.z 0012 80000dc0 60007010 w: INTERP_LOAD_P0 R0.w, Param0.w 0002 c0000000 95000688 EXPORT_DONE PIXEL 0 R0.xyzw 0004 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg) #0 { main_body: %2 = call <4 x float> @llvm.R600.interp.const(i32 0) %3 = extractelement <4 x float> %2, i32 0 %4 = extractelement <4 x float> %2, i32 1 %5 = extractelement <4 x float> %2, i32 2 %6 = extractelement <4 x float> %2, i32 3 %7 = insertelement <4 x float> undef, float %3, i32 0 %8 = insertelement <4 x float> %7, float %4, i32 1 %9 = insertelement <4 x float> %8, float %5, i32 2 %10 = insertelement <4 x float> %9, float %6, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %10, i32 0, i32 0) ret void } ; Function Attrs: readnone declare <4 x float> @llvm.R600.interp.const(i32) #1 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } Shader Disassembly: ALU 3, @4, KC0[], KC1[] ; 00000004 A00C0000 EXPORT T0.XYZW ; C0000000 95200688 CF_END ; 00000000 88000000 PAD ; 00000000 00000000 ALU clause starting at 4: ; INTERP_LOAD_P0 T0.X, ARRAY_BASE, ; 000001C0 00007010 INTERP_LOAD_P0 T0.Y, ARRAY_BASE, ; 000001C0 20007010 INTERP_LOAD_P0 T0.Z, ARRAY_BASE, ; 000001C0 40007010 INTERP_LOAD_P0 * T0.W, ARRAY_BASE, ; 800001C0 60007010 ===== SHADER #35 ======================================== PS/CAYMAN/CAYMAN ===== ===== 16 dw ===== 1 gprs ===== 1 stack ========================================= 0000 00000004 a00c0000 ALU 4 @8 0008 000001c0 00007010 1 x: INTERP_LOAD_P0 R0.x, Param0.x 0010 000001c0 20007010 y: INTERP_LOAD_P0 R0.y, Param0.x 0012 000001c0 40007010 z: INTERP_LOAD_P0 R0.z, Param0.x 0014 800001c0 60007010 w: INTERP_LOAD_P0 R0.w, Param0.x 0002 c0000000 95200688 EXPORT_DONE PIXEL 0 R0.xyzw 0004 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #35 OPT ==================================== PS/CAYMAN/CAYMAN ===== ===== 14 dw ===== 1 gprs ===== 0 stack ========================================= 0000 00000003 a00c0000 ALU 4 @6 0006 000001c0 00007010 1 x: INTERP_LOAD_P0 R0.x, Param0.x 0008 000005c0 20007010 y: INTERP_LOAD_P0 R0.y, Param0.y 0010 000009c0 40007010 z: INTERP_LOAD_P0 R0.z, Param0.z 0012 80000dc0 60007010 w: INTERP_LOAD_P0 R0.w, Param0.w 0002 c0000000 95000688 EXPORT_DONE PIXEL 0 R0.xyzw 0004 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] 0: MOV OUT[0], IN[0] 1: MOV OUT[1], IN[1] 2: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg, <4 x float> inreg) #0 { main_body: %3 = extractelement <4 x float> %1, i32 0 %4 = extractelement <4 x float> %1, i32 1 %5 = extractelement <4 x float> %1, i32 2 %6 = extractelement <4 x float> %1, i32 3 %7 = extractelement <4 x float> %2, i32 0 %8 = extractelement <4 x float> %2, i32 1 %9 = extractelement <4 x float> %2, i32 2 %10 = extractelement <4 x float> %2, i32 3 %11 = insertelement <4 x float> undef, float %3, i32 0 %12 = insertelement <4 x float> %11, float %4, i32 1 %13 = insertelement <4 x float> %12, float %5, i32 2 %14 = insertelement <4 x float> %13, float %6, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %14, i32 60, i32 1) %15 = insertelement <4 x float> undef, float %7, i32 0 %16 = insertelement <4 x float> %15, float %8, i32 1 %17 = insertelement <4 x float> %16, float %9, i32 2 %18 = insertelement <4 x float> %17, float %10, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %18, i32 0, i32 2) ret void } declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="1" } Shader Disassembly: CALL_FS ; 00000000 84C00000 EXPORT T1.XYZW ; C000A03C 95000688 EXPORT T2.XYZW ; C0014000 95200688 CF_END ; 00000000 88000000 ===== SHADER #36 ======================================== VS/CAYMAN/CAYMAN ===== ===== 8 dw ===== 3 gprs ===== 1 stack ========================================== 0000 00000000 84c00000 CALL_FS @0 0002 c000a03c 95000688 EXPORT_DONE POS 60 R1.xyzw 0004 c0014000 95200688 EXPORT_DONE PARAM 0 R2.xyzw 0006 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #36 OPT ==================================== VS/CAYMAN/CAYMAN ===== ===== 8 dw ===== 3 gprs ===== 1 stack ========================================== 0000 00000000 84c00000 CALL_FS @0 0002 c0014000 95000688 EXPORT_DONE PARAM 0 R2.xyzw 0004 c000a03c 95000688 EXPORT_DONE POS 60 R1.xyzw 0006 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- VERT DCL IN[0] DCL OUT[0], POSITION 0: MOV OUT[0], IN[0] 1: END STREAMOUT 0: MEM_STREAM0_BUF0[0..0] <- OUT[0].x ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg) #0 { main_body: %2 = extractelement <4 x float> %1, i32 0 %3 = extractelement <4 x float> %1, i32 1 %4 = extractelement <4 x float> %1, i32 2 %5 = extractelement <4 x float> %1, i32 3 %6 = insertelement <4 x float> undef, float %2, i32 0 %7 = insertelement <4 x float> %6, float %3, i32 1 %8 = insertelement <4 x float> %7, float %4, i32 2 %9 = insertelement <4 x float> %8, float %5, i32 3 call void @llvm.R600.store.stream.output(<4 x float> %9, i32 0, i32 0, i32 1) %10 = insertelement <4 x float> undef, float %2, i32 0 %11 = insertelement <4 x float> %10, float %3, i32 1 %12 = insertelement <4 x float> %11, float %4, i32 2 %13 = insertelement <4 x float> %12, float %5, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %13, i32 60, i32 1) call void @llvm.R600.store.dummy(i32 2) ret void } declare void @llvm.R600.store.stream.output(<4 x float>, i32, i32, i32) declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) declare void @llvm.R600.store.dummy(i32) attributes #0 = { "ShaderType"="1" } Shader Disassembly: CALL_FS ; 00000000 84C00000 EXPORT T1 ; 00008000 90001FFF EXPORT T1.XYZW ; C000A03C 95000688 EXPORT T0.____ ; C0004000 95200FFF CF_END ; 00000000 88000000 PAD ; 00000000 00000000 ===== SHADER #37 ======================================== VS/CAYMAN/CAYMAN ===== ===== 12 dw ===== 2 gprs ===== 1 stack ========================================= 0000 00000000 84c00000 CALL_FS @0 0002 00008000 90001fff MEM_STREAM0_BUF0 WRITE 0 R1.x___ ES:0 0004 c000a03c 95000688 EXPORT_DONE POS 60 R1.xyzw 0006 c0004000 95200fff EXPORT_DONE PARAM 0 R0.____ 0008 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #37 OPT ==================================== VS/CAYMAN/CAYMAN ===== ===== 10 dw ===== 2 gprs ===== 1 stack ========================================= 0000 00000000 84c00000 CALL_FS @0 0002 c000a03c 95000688 EXPORT_DONE POS 60 R1.xyzw 0004 00008000 90001fff MEM_STREAM0_BUF0 WRITE 0 R1.x___ ES:0 0006 c0004000 95000fff EXPORT_DONE PARAM 0 R0.____ 0008 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- FRAG DCL IN[0], GENERIC[0], CONSTANT 0: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg) #0 { main_body: %2 = call <4 x float> @llvm.R600.interp.const(i32 0) call void @llvm.R600.store.dummy(i32 0) ret void } ; Function Attrs: readnone declare <4 x float> @llvm.R600.interp.const(i32) #1 declare void @llvm.R600.store.dummy(i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } Shader Disassembly: EXPORT T0.____ ; C0000000 95200FFF CF_END ; 00000000 88000000 ===== SHADER #38 ======================================== PS/CAYMAN/CAYMAN ===== ===== 4 dw ===== 1 gprs ===== 1 stack ========================================== 0000 c0000000 95200fff EXPORT_DONE PIXEL 0 R0.____ 0002 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #38 OPT ==================================== PS/CAYMAN/CAYMAN ===== ===== 4 dw ===== 0 gprs ===== 0 stack ========================================== 0000 c0000000 95000fff EXPORT_DONE PIXEL 0 R0.____ 0002 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- FRAG 0: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg) #0 { main_body: call void @llvm.R600.store.dummy(i32 0) ret void } declare void @llvm.R600.store.dummy(i32) attributes #0 = { "ShaderType"="0" } Shader Disassembly: EXPORT T0.____ ; C0000000 95200FFF CF_END ; 00000000 88000000 ===== SHADER #44 ======================================== PS/CAYMAN/CAYMAN ===== ===== 4 dw ===== 1 gprs ===== 1 stack ========================================== 0000 c0000000 95200fff EXPORT_DONE PIXEL 0 R0.____ 0002 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #44 OPT ==================================== PS/CAYMAN/CAYMAN ===== ===== 4 dw ===== 0 gprs ===== 0 stack ========================================== 0000 c0000000 95000fff EXPORT_DONE PIXEL 0 R0.____ 0002 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- FRAG DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg) #0 { main_body: %2 = call <4 x float> @llvm.R600.interp.const(i32 0) %3 = extractelement <4 x float> %2, i32 0 %4 = extractelement <4 x float> %2, i32 1 %5 = extractelement <4 x float> %2, i32 2 %6 = extractelement <4 x float> %2, i32 3 %7 = insertelement <4 x float> undef, float %3, i32 0 %8 = insertelement <4 x float> %7, float %4, i32 1 %9 = insertelement <4 x float> %8, float %5, i32 2 %10 = insertelement <4 x float> %9, float %6, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %10, i32 0, i32 0) ret void } ; Function Attrs: readnone declare <4 x float> @llvm.R600.interp.const(i32) #1 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } Shader Disassembly: ALU 3, @4, KC0[], KC1[] ; 00000004 A00C0000 EXPORT T0.XYZW ; C0000000 95200688 CF_END ; 00000000 88000000 PAD ; 00000000 00000000 ALU clause starting at 4: ; INTERP_LOAD_P0 T0.X, ARRAY_BASE, ; 000001C0 00007010 INTERP_LOAD_P0 T0.Y, ARRAY_BASE, ; 000001C0 20007010 INTERP_LOAD_P0 T0.Z, ARRAY_BASE, ; 000001C0 40007010 INTERP_LOAD_P0 * T0.W, ARRAY_BASE, ; 800001C0 60007010 ===== SHADER #45 ======================================== PS/CAYMAN/CAYMAN ===== ===== 16 dw ===== 1 gprs ===== 1 stack ========================================= 0000 00000004 a00c0000 ALU 4 @8 0008 000001c0 00007010 1 x: INTERP_LOAD_P0 R0.x, Param0.x 0010 000001c0 20007010 y: INTERP_LOAD_P0 R0.y, Param0.x 0012 000001c0 40007010 z: INTERP_LOAD_P0 R0.z, Param0.x 0014 800001c0 60007010 w: INTERP_LOAD_P0 R0.w, Param0.x 0002 c0000000 95200688 EXPORT_DONE PIXEL 0 R0.xyzw 0004 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #45 OPT ==================================== PS/CAYMAN/CAYMAN ===== ===== 14 dw ===== 1 gprs ===== 0 stack ========================================= 0000 00000003 a00c0000 ALU 4 @6 0006 000001c0 00007010 1 x: INTERP_LOAD_P0 R0.x, Param0.x 0008 000005c0 20007010 y: INTERP_LOAD_P0 R0.y, Param0.y 0010 000009c0 40007010 z: INTERP_LOAD_P0 R0.z, Param0.z 0012 80000dc0 60007010 w: INTERP_LOAD_P0 R0.w, Param0.w 0002 c0000000 95000688 EXPORT_DONE PIXEL 0 R0.xyzw 0004 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg) #0 { main_body: %2 = call <4 x float> @llvm.R600.interp.const(i32 0) %3 = extractelement <4 x float> %2, i32 0 %4 = extractelement <4 x float> %2, i32 1 %5 = extractelement <4 x float> %2, i32 2 %6 = extractelement <4 x float> %2, i32 3 %7 = insertelement <4 x float> undef, float %3, i32 0 %8 = insertelement <4 x float> %7, float %4, i32 1 %9 = insertelement <4 x float> %8, float %5, i32 2 %10 = insertelement <4 x float> %9, float %6, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %10, i32 0, i32 0) ret void } ; Function Attrs: readnone declare <4 x float> @llvm.R600.interp.const(i32) #1 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } Shader Disassembly: ALU 3, @4, KC0[], KC1[] ; 00000004 A00C0000 EXPORT T0.XYZW ; C0000000 95200688 CF_END ; 00000000 88000000 PAD ; 00000000 00000000 ALU clause starting at 4: ; INTERP_LOAD_P0 T0.X, ARRAY_BASE, ; 000001C0 00007010 INTERP_LOAD_P0 T0.Y, ARRAY_BASE, ; 000001C0 20007010 INTERP_LOAD_P0 T0.Z, ARRAY_BASE, ; 000001C0 40007010 INTERP_LOAD_P0 * T0.W, ARRAY_BASE, ; 800001C0 60007010 ===== SHADER #46 ======================================== PS/CAYMAN/CAYMAN ===== ===== 16 dw ===== 1 gprs ===== 1 stack ========================================= 0000 00000004 a00c0000 ALU 4 @8 0008 000001c0 00007010 1 x: INTERP_LOAD_P0 R0.x, Param0.x 0010 000001c0 20007010 y: INTERP_LOAD_P0 R0.y, Param0.x 0012 000001c0 40007010 z: INTERP_LOAD_P0 R0.z, Param0.x 0014 800001c0 60007010 w: INTERP_LOAD_P0 R0.w, Param0.x 0002 c0000000 95200688 EXPORT_DONE PIXEL 0 R0.xyzw 0004 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #46 OPT ==================================== PS/CAYMAN/CAYMAN ===== ===== 14 dw ===== 1 gprs ===== 0 stack ========================================= 0000 00000003 a00c0000 ALU 4 @6 0006 000001c0 00007010 1 x: INTERP_LOAD_P0 R0.x, Param0.x 0008 000005c0 20007010 y: INTERP_LOAD_P0 R0.y, Param0.y 0010 000009c0 40007010 z: INTERP_LOAD_P0 R0.z, Param0.z 0012 80000dc0 60007010 w: INTERP_LOAD_P0 R0.w, Param0.w 0002 c0000000 95000688 EXPORT_DONE PIXEL 0 R0.xyzw 0004 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] 0: MOV OUT[0], IN[0] 1: MOV OUT[1], IN[1] 2: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg, <4 x float> inreg) #0 { main_body: %3 = extractelement <4 x float> %1, i32 0 %4 = extractelement <4 x float> %1, i32 1 %5 = extractelement <4 x float> %1, i32 2 %6 = extractelement <4 x float> %1, i32 3 %7 = extractelement <4 x float> %2, i32 0 %8 = extractelement <4 x float> %2, i32 1 %9 = extractelement <4 x float> %2, i32 2 %10 = extractelement <4 x float> %2, i32 3 %11 = insertelement <4 x float> undef, float %3, i32 0 %12 = insertelement <4 x float> %11, float %4, i32 1 %13 = insertelement <4 x float> %12, float %5, i32 2 %14 = insertelement <4 x float> %13, float %6, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %14, i32 60, i32 1) %15 = insertelement <4 x float> undef, float %7, i32 0 %16 = insertelement <4 x float> %15, float %8, i32 1 %17 = insertelement <4 x float> %16, float %9, i32 2 %18 = insertelement <4 x float> %17, float %10, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %18, i32 0, i32 2) ret void } declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="1" } Shader Disassembly: CALL_FS ; 00000000 84C00000 EXPORT T1.XYZW ; C000A03C 95000688 EXPORT T2.XYZW ; C0014000 95200688 CF_END ; 00000000 88000000 ===== SHADER #47 ======================================== VS/CAYMAN/CAYMAN ===== ===== 8 dw ===== 3 gprs ===== 1 stack ========================================== 0000 00000000 84c00000 CALL_FS @0 0002 c000a03c 95000688 EXPORT_DONE POS 60 R1.xyzw 0004 c0014000 95200688 EXPORT_DONE PARAM 0 R2.xyzw 0006 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #47 OPT ==================================== VS/CAYMAN/CAYMAN ===== ===== 8 dw ===== 3 gprs ===== 1 stack ========================================== 0000 00000000 84c00000 CALL_FS @0 0002 c0014000 95000688 EXPORT_DONE PARAM 0 R2.xyzw 0004 c000a03c 95000688 EXPORT_DONE POS 60 R1.xyzw 0006 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- VERT DCL IN[0] DCL OUT[0], POSITION 0: MOV OUT[0], IN[0] 1: END STREAMOUT 0: MEM_STREAM0_BUF0[0..0] <- OUT[0].x ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg) #0 { main_body: %2 = extractelement <4 x float> %1, i32 0 %3 = extractelement <4 x float> %1, i32 1 %4 = extractelement <4 x float> %1, i32 2 %5 = extractelement <4 x float> %1, i32 3 %6 = insertelement <4 x float> undef, float %2, i32 0 %7 = insertelement <4 x float> %6, float %3, i32 1 %8 = insertelement <4 x float> %7, float %4, i32 2 %9 = insertelement <4 x float> %8, float %5, i32 3 call void @llvm.R600.store.stream.output(<4 x float> %9, i32 0, i32 0, i32 1) %10 = insertelement <4 x float> undef, float %2, i32 0 %11 = insertelement <4 x float> %10, float %3, i32 1 %12 = insertelement <4 x float> %11, float %4, i32 2 %13 = insertelement <4 x float> %12, float %5, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %13, i32 60, i32 1) call void @llvm.R600.store.dummy(i32 2) ret void } declare void @llvm.R600.store.stream.output(<4 x float>, i32, i32, i32) declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) declare void @llvm.R600.store.dummy(i32) attributes #0 = { "ShaderType"="1" } Shader Disassembly: CALL_FS ; 00000000 84C00000 EXPORT T1 ; 00008000 90001FFF EXPORT T1.XYZW ; C000A03C 95000688 EXPORT T0.____ ; C0004000 95200FFF CF_END ; 00000000 88000000 PAD ; 00000000 00000000 ===== SHADER #48 ======================================== VS/CAYMAN/CAYMAN ===== ===== 12 dw ===== 2 gprs ===== 1 stack ========================================= 0000 00000000 84c00000 CALL_FS @0 0002 00008000 90001fff MEM_STREAM0_BUF0 WRITE 0 R1.x___ ES:0 0004 c000a03c 95000688 EXPORT_DONE POS 60 R1.xyzw 0006 c0004000 95200fff EXPORT_DONE PARAM 0 R0.____ 0008 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #48 OPT ==================================== VS/CAYMAN/CAYMAN ===== ===== 10 dw ===== 2 gprs ===== 1 stack ========================================= 0000 00000000 84c00000 CALL_FS @0 0002 c000a03c 95000688 EXPORT_DONE POS 60 R1.xyzw 0004 00008000 90001fff MEM_STREAM0_BUF0 WRITE 0 R1.x___ ES:0 0006 c0004000 95000fff EXPORT_DONE PARAM 0 R0.____ 0008 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- FRAG DCL IN[0], GENERIC[0], CONSTANT 0: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg) #0 { main_body: %2 = call <4 x float> @llvm.R600.interp.const(i32 0) call void @llvm.R600.store.dummy(i32 0) ret void } ; Function Attrs: readnone declare <4 x float> @llvm.R600.interp.const(i32) #1 declare void @llvm.R600.store.dummy(i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } Shader Disassembly: EXPORT T0.____ ; C0000000 95200FFF CF_END ; 00000000 88000000 ===== SHADER #49 ======================================== PS/CAYMAN/CAYMAN ===== ===== 4 dw ===== 1 gprs ===== 1 stack ========================================== 0000 c0000000 95200fff EXPORT_DONE PIXEL 0 R0.____ 0002 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #49 OPT ==================================== PS/CAYMAN/CAYMAN ===== ===== 4 dw ===== 0 gprs ===== 0 stack ========================================== 0000 c0000000 95000fff EXPORT_DONE PIXEL 0 R0.____ 0002 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] 0: MOV OUT[0], IN[0] 1: MOV OUT[1], IN[1] 2: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg, <4 x float> inreg) #0 { main_body: %3 = extractelement <4 x float> %1, i32 0 %4 = extractelement <4 x float> %1, i32 1 %5 = extractelement <4 x float> %1, i32 2 %6 = extractelement <4 x float> %1, i32 3 %7 = extractelement <4 x float> %2, i32 0 %8 = extractelement <4 x float> %2, i32 1 %9 = extractelement <4 x float> %2, i32 2 %10 = extractelement <4 x float> %2, i32 3 %11 = insertelement <4 x float> undef, float %3, i32 0 %12 = insertelement <4 x float> %11, float %4, i32 1 %13 = insertelement <4 x float> %12, float %5, i32 2 %14 = insertelement <4 x float> %13, float %6, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %14, i32 60, i32 1) %15 = insertelement <4 x float> undef, float %7, i32 0 %16 = insertelement <4 x float> %15, float %8, i32 1 %17 = insertelement <4 x float> %16, float %9, i32 2 %18 = insertelement <4 x float> %17, float %10, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %18, i32 0, i32 2) ret void } declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="1" } Shader Disassembly: CALL_FS ; 00000000 84C00000 EXPORT T1.XYZW ; C000A03C 95000688 EXPORT T2.XYZW ; C0014000 95200688 CF_END ; 00000000 88000000 ===== SHADER #50 ======================================== VS/CAYMAN/CAYMAN ===== ===== 8 dw ===== 3 gprs ===== 1 stack ========================================== 0000 00000000 84c00000 CALL_FS @0 0002 c000a03c 95000688 EXPORT_DONE POS 60 R1.xyzw 0004 c0014000 95200688 EXPORT_DONE PARAM 0 R2.xyzw 0006 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #50 OPT ==================================== VS/CAYMAN/CAYMAN ===== ===== 8 dw ===== 3 gprs ===== 1 stack ========================================== 0000 00000000 84c00000 CALL_FS @0 0002 c0014000 95000688 EXPORT_DONE PARAM 0 R2.xyzw 0004 c000a03c 95000688 EXPORT_DONE POS 60 R1.xyzw 0006 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] DCL OUT[2], GENERIC[10] DCL OUT[3], GENERIC[11] DCL CONST[0] IMM[0] FLT32 { 1.0000, 0.0000, -1.0000, 0.0000} 0: MOV OUT[0], IN[0] 1: MOV OUT[1], IN[1] 2: MAD OUT[2], CONST[0].xyxy, IMM[0].zyyz, IN[1].xyxy 3: MAD OUT[3], CONST[0].xyxy, IMM[0].xyyx, IN[1].xyxy 4: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg, <4 x float> inreg) #0 { main_body: %3 = extractelement <4 x float> %1, i32 0 %4 = extractelement <4 x float> %1, i32 1 %5 = extractelement <4 x float> %1, i32 2 %6 = extractelement <4 x float> %1, i32 3 %7 = extractelement <4 x float> %2, i32 0 %8 = extractelement <4 x float> %2, i32 1 %9 = extractelement <4 x float> %2, i32 2 %10 = extractelement <4 x float> %2, i32 3 %11 = load <4 x float> addrspace(8)* null %12 = extractelement <4 x float> %11, i32 0 %13 = fmul float %12, -1.000000e+00 %14 = fadd float %13, %7 %15 = load <4 x float> addrspace(8)* null %16 = extractelement <4 x float> %15, i32 1 %17 = fmul float %16, 0.000000e+00 %18 = fadd float %17, %8 %19 = load <4 x float> addrspace(8)* null %20 = extractelement <4 x float> %19, i32 0 %21 = fmul float %20, 0.000000e+00 %22 = fadd float %21, %7 %23 = load <4 x float> addrspace(8)* null %24 = extractelement <4 x float> %23, i32 1 %25 = fmul float %24, -1.000000e+00 %26 = fadd float %25, %8 %27 = load <4 x float> addrspace(8)* null %28 = extractelement <4 x float> %27, i32 0 %29 = fmul float %28, 1.000000e+00 %30 = fadd float %29, %7 %31 = load <4 x float> addrspace(8)* null %32 = extractelement <4 x float> %31, i32 1 %33 = fmul float %32, 0.000000e+00 %34 = fadd float %33, %8 %35 = load <4 x float> addrspace(8)* null %36 = extractelement <4 x float> %35, i32 0 %37 = fmul float %36, 0.000000e+00 %38 = fadd float %37, %7 %39 = load <4 x float> addrspace(8)* null %40 = extractelement <4 x float> %39, i32 1 %41 = fmul float %40, 1.000000e+00 %42 = fadd float %41, %8 %43 = insertelement <4 x float> undef, float %3, i32 0 %44 = insertelement <4 x float> %43, float %4, i32 1 %45 = insertelement <4 x float> %44, float %5, i32 2 %46 = insertelement <4 x float> %45, float %6, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %46, i32 60, i32 1) %47 = insertelement <4 x float> undef, float %7, i32 0 %48 = insertelement <4 x float> %47, float %8, i32 1 %49 = insertelement <4 x float> %48, float %9, i32 2 %50 = insertelement <4 x float> %49, float %10, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %50, i32 0, i32 2) %51 = insertelement <4 x float> undef, float %14, i32 0 %52 = insertelement <4 x float> %51, float %18, i32 1 %53 = insertelement <4 x float> %52, float %22, i32 2 %54 = insertelement <4 x float> %53, float %26, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %54, i32 1, i32 2) %55 = insertelement <4 x float> undef, float %30, i32 0 %56 = insertelement <4 x float> %55, float %34, i32 1 %57 = insertelement <4 x float> %56, float %38, i32 2 %58 = insertelement <4 x float> %57, float %42, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %58, i32 2, i32 2) ret void } declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="1" } Shader Disassembly: CALL_FS ; 00000000 84C00000 ALU 7, @8, KC0[CB0:0-32], KC1[] ; 80000008 A01C0000 EXPORT T1.XYZW ; C000A03C 95000688 EXPORT T2.XYZW ; C0014000 94C00688 EXPORT T0.XYZW ; C0004001 94C00688 EXPORT T3.XYZW ; C001C002 95200688 CF_END ; 00000000 88000000 PAD ; 00000000 00000000 ALU clause starting at 8: ; ADD T0.X, T2.X, -KC0[0].X, ; 02100002 00000010 MULADD_IEEE T0.Y, KC0[0].Y, 0.0, T2.Y, ; 001F0480 20030402 MULADD_IEEE * T0.Z, KC0[0].X, 0.0, T2.X, ; 801F0080 40030002 ADD T3.X, KC0[0].X, T2.X, ; 00004080 00600010 ADD * T0.W, T2.Y, -KC0[0].Y, ; 82900402 60000010 ADD * T3.W, KC0[0].Y, T2.Y, ; 80804480 60600010 MOV T3.Y, T0.Y, ; 00000400 20600C90 MOV * T3.Z, T0.Z, ; 80000800 40600C90 ===== SHADER #51 ======================================== VS/CAYMAN/CAYMAN ===== ===== 32 dw ===== 4 gprs ===== 1 stack ========================================= 0000 00000000 84c00000 CALL_FS @0 0002 80000008 a01c0000 ALU 8 @16 KC0[CB0:0-31] 0016 02100002 00000010 1 x: ADD R0.x, R2.x, -KC0[0].x 0018 001f0480 20030402 y: MULADD_IEEE R0.y, KC0[0].y, 0, R2.y 0020 801f0080 40030002 z: MULADD_IEEE R0.z, KC0[0].x, 0, R2.x 0022 00004080 00600010 2 x: ADD R3.x, KC0[0].x, R2.x 0024 82900402 60000010 w: ADD R0.w, R2.y, -KC0[0].y 0026 80804480 60600010 3 w: ADD R3.w, KC0[0].y, R2.y 0028 00000400 20600c90 4 y: MOV R3.y, R0.y 0030 80000800 40600c90 z: MOV R3.z, R0.z 0004 c000a03c 95000688 EXPORT_DONE POS 60 R1.xyzw 0006 c0014000 94c00688 EXPORT PARAM 0 R2.xyzw 0008 c0004001 94c00688 EXPORT PARAM 1 R0.xyzw 0010 c001c002 95200688 EXPORT_DONE PARAM 2 R3.xyzw 0012 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #51 OPT ==================================== VS/CAYMAN/CAYMAN ===== ===== 30 dw ===== 4 gprs ===== 1 stack ========================================= 0000 00000000 84c00000 CALL_FS @0 0002 40000007 a01c0000 ALU 8 @14 KC0[CB0:0-15] 0014 00004080 00000010 1 x: ADD R0.x, KC0[0].x, R2.x 0016 001f0480 20030402 y: MULADD_IEEE R0.y, KC0[0].y, 0, R2.y 0018 001f0080 40030002 z: MULADD_IEEE R0.z, KC0[0].x, 0, R2.x 0020 80804480 60000010 w: ADD R0.w, KC0[0].y, R2.y 0022 02100002 00600010 2 x: ADD R3.x, R2.x, -KC0[0].x 0024 00000400 20600c90 y: MOV R3.y, R0.y 0026 00000800 40600c90 z: MOV R3.z, R0.z 0028 82900402 60680010 w: ADD R3.w, R2.y, -KC0[0].y VEC_120 0004 c001c001 94c00688 EXPORT PARAM 1 R3.xyzw 0006 c0004002 94c00688 EXPORT PARAM 2 R0.xyzw 0008 c0014000 95000688 EXPORT_DONE PARAM 0 R2.xyzw 0010 c000a03c 95000688 EXPORT_DONE POS 60 R1.xyzw 0012 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], PERSPECTIVE DCL IN[1], GENERIC[10], PERSPECTIVE DCL IN[2], GENERIC[11], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL TEMP[0..2] IMM[0] FLT32 { 0.0030, 0.0000, 1.0000, 0.0000} 0: TEX TEMP[0].x, IN[1].xyyy, SAMP[0], 2D 1: MOV TEMP[1].x, TEMP[0].xxxx 2: TEX TEMP[0].x, IN[1].zwww, SAMP[0], 2D 3: MOV TEMP[1].y, TEMP[0].xxxx 4: TEX TEMP[0].x, IN[2].xyyy, SAMP[0], 2D 5: MOV TEMP[1].z, TEMP[0].xxxx 6: TEX TEMP[0].x, IN[2].zwww, SAMP[0], 2D 7: MOV TEMP[1].w, TEMP[0].xxxx 8: TEX TEMP[0].x, IN[0].xyyy, SAMP[0], 2D 9: ADD TEMP[2], TEMP[0].xxxx, -TEMP[1] 10: ABS TEMP[0], TEMP[2] 11: SGE TEMP[2], TEMP[0], IMM[0].xxxx 12: DP4 TEMP[0].x, TEMP[2], IMM[0].zzzz 13: SEQ TEMP[1].x, TEMP[0].xxxx, IMM[0].yyyy 14: IF TEMP[1].xxxx :16 15: KILL 16: ENDIF 17: MOV OUT[0], TEMP[2] 18: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg, <4 x float> inreg, <4 x float> inreg) #0 { main_body: %4 = extractelement <4 x float> %0, i32 0 %5 = extractelement <4 x float> %0, i32 1 %6 = call <2 x float> @llvm.R600.interp.xy(i32 0, float %4, float %5) %7 = call <2 x float> @llvm.R600.interp.zw(i32 0, float %4, float %5) %8 = shufflevector <2 x float> %6, <2 x float> %7, <4 x i32> %9 = extractelement <4 x float> %8, i32 0 %10 = extractelement <4 x float> %8, i32 1 %11 = extractelement <4 x float> %0, i32 0 %12 = extractelement <4 x float> %0, i32 1 %13 = call <2 x float> @llvm.R600.interp.xy(i32 1, float %11, float %12) %14 = call <2 x float> @llvm.R600.interp.zw(i32 1, float %11, float %12) %15 = shufflevector <2 x float> %13, <2 x float> %14, <4 x i32> %16 = extractelement <4 x float> %15, i32 0 %17 = extractelement <4 x float> %15, i32 1 %18 = extractelement <4 x float> %15, i32 2 %19 = extractelement <4 x float> %15, i32 3 %20 = extractelement <4 x float> %0, i32 0 %21 = extractelement <4 x float> %0, i32 1 %22 = call <2 x float> @llvm.R600.interp.xy(i32 2, float %20, float %21) %23 = call <2 x float> @llvm.R600.interp.zw(i32 2, float %20, float %21) %24 = shufflevector <2 x float> %22, <2 x float> %23, <4 x i32> %25 = extractelement <4 x float> %24, i32 0 %26 = extractelement <4 x float> %24, i32 1 %27 = extractelement <4 x float> %24, i32 2 %28 = extractelement <4 x float> %24, i32 3 %29 = insertelement <4 x float> undef, float %16, i32 0 %30 = insertelement <4 x float> %29, float %17, i32 1 %31 = insertelement <4 x float> %30, float %17, i32 2 %32 = insertelement <4 x float> %31, float %17, i32 3 %33 = extractelement <4 x float> %32, i32 0 %34 = extractelement <4 x float> %32, i32 1 %35 = insertelement <4 x float> undef, float %33, i32 0 %36 = insertelement <4 x float> %35, float %34, i32 1 %37 = insertelement <4 x float> %36, float undef, i32 2 %38 = insertelement <4 x float> %37, float undef, i32 3 %39 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %38, i32 16, i32 0, i32 2) %40 = extractelement <4 x float> %39, i32 0 %41 = insertelement <4 x float> undef, float %18, i32 0 %42 = insertelement <4 x float> %41, float %19, i32 1 %43 = insertelement <4 x float> %42, float %19, i32 2 %44 = insertelement <4 x float> %43, float %19, i32 3 %45 = extractelement <4 x float> %44, i32 0 %46 = extractelement <4 x float> %44, i32 1 %47 = insertelement <4 x float> undef, float %45, i32 0 %48 = insertelement <4 x float> %47, float %46, i32 1 %49 = insertelement <4 x float> %48, float undef, i32 2 %50 = insertelement <4 x float> %49, float undef, i32 3 %51 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %50, i32 16, i32 0, i32 2) %52 = extractelement <4 x float> %51, i32 0 %53 = insertelement <4 x float> undef, float %25, i32 0 %54 = insertelement <4 x float> %53, float %26, i32 1 %55 = insertelement <4 x float> %54, float %26, i32 2 %56 = insertelement <4 x float> %55, float %26, i32 3 %57 = extractelement <4 x float> %56, i32 0 %58 = extractelement <4 x float> %56, i32 1 %59 = insertelement <4 x float> undef, float %57, i32 0 %60 = insertelement <4 x float> %59, float %58, i32 1 %61 = insertelement <4 x float> %60, float undef, i32 2 %62 = insertelement <4 x float> %61, float undef, i32 3 %63 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %62, i32 16, i32 0, i32 2) %64 = extractelement <4 x float> %63, i32 0 %65 = insertelement <4 x float> undef, float %27, i32 0 %66 = insertelement <4 x float> %65, float %28, i32 1 %67 = insertelement <4 x float> %66, float %28, i32 2 %68 = insertelement <4 x float> %67, float %28, i32 3 %69 = extractelement <4 x float> %68, i32 0 %70 = extractelement <4 x float> %68, i32 1 %71 = insertelement <4 x float> undef, float %69, i32 0 %72 = insertelement <4 x float> %71, float %70, i32 1 %73 = insertelement <4 x float> %72, float undef, i32 2 %74 = insertelement <4 x float> %73, float undef, i32 3 %75 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %74, i32 16, i32 0, i32 2) %76 = extractelement <4 x float> %75, i32 0 %77 = insertelement <4 x float> undef, float %9, i32 0 %78 = insertelement <4 x float> %77, float %10, i32 1 %79 = insertelement <4 x float> %78, float %10, i32 2 %80 = insertelement <4 x float> %79, float %10, i32 3 %81 = extractelement <4 x float> %80, i32 0 %82 = extractelement <4 x float> %80, i32 1 %83 = insertelement <4 x float> undef, float %81, i32 0 %84 = insertelement <4 x float> %83, float %82, i32 1 %85 = insertelement <4 x float> %84, float undef, i32 2 %86 = insertelement <4 x float> %85, float undef, i32 3 %87 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %86, i32 16, i32 0, i32 2) %88 = extractelement <4 x float> %87, i32 0 %89 = fsub float -0.000000e+00, %40 %90 = fadd float %88, %89 %91 = fsub float -0.000000e+00, %52 %92 = fadd float %88, %91 %93 = fsub float -0.000000e+00, %64 %94 = fadd float %88, %93 %95 = fsub float -0.000000e+00, %76 %96 = fadd float %88, %95 %97 = call float @fabs(float %90) %98 = call float @fabs(float %92) %99 = call float @fabs(float %94) %100 = call float @fabs(float %96) %101 = fcmp oge float %97, 0x3F689374C0000000 %102 = select i1 %101, float 1.000000e+00, float 0.000000e+00 %103 = fcmp oge float %98, 0x3F689374C0000000 %104 = select i1 %103, float 1.000000e+00, float 0.000000e+00 %105 = fcmp oge float %99, 0x3F689374C0000000 %106 = select i1 %105, float 1.000000e+00, float 0.000000e+00 %107 = fcmp oge float %100, 0x3F689374C0000000 %108 = select i1 %107, float 1.000000e+00, float 0.000000e+00 %109 = insertelement <4 x float> undef, float %102, i32 0 %110 = insertelement <4 x float> %109, float %104, i32 1 %111 = insertelement <4 x float> %110, float %106, i32 2 %112 = insertelement <4 x float> %111, float %108, i32 3 %113 = call float @llvm.AMDGPU.dp4(<4 x float> %112, <4 x float> ) %114 = fcmp oeq float %113, 0.000000e+00 %115 = select i1 %114, float 1.000000e+00, float 0.000000e+00 %116 = fcmp une float %115, 0.000000e+00 br i1 %116, label %IF, label %ENDIF IF: ; preds = %main_body call void @llvm.AMDGPU.kilp() br label %ENDIF ENDIF: ; preds = %main_body, %IF %117 = insertelement <4 x float> undef, float %102, i32 0 %118 = insertelement <4 x float> %117, float %104, i32 1 %119 = insertelement <4 x float> %118, float %106, i32 2 %120 = insertelement <4 x float> %119, float %108, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %120, i32 0, i32 0) ret void } ; Function Attrs: readnone declare <2 x float> @llvm.R600.interp.xy(i32, float, float) #1 ; Function Attrs: readnone declare <2 x float> @llvm.R600.interp.zw(i32, float, float) #1 ; Function Attrs: readnone declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32, i32) #1 ; Function Attrs: readonly declare float @fabs(float) #2 ; Function Attrs: readnone declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1 declare void @llvm.AMDGPU.kilp() declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } attributes #2 = { readonly } Shader Disassembly: ALU 23, @18, KC0[], KC1[] ; 00000012 A05C0000 TEX 4 @8 ; 00000008 80401000 ALU_PUSH_BEFORE 18, @42, KC0[], KC1[] ; 0000002A A4480000 JUMP @5 POP:1 ; 00000005 82800001 ALU_POP_AFTER 0, @61, KC0[], KC1[] ; 0000003D A8000000 EXPORT T0.XYZW ; C0000000 95200688 CF_END ; 00000000 88000000 PAD ; 00000000 00000000 Fetch clause starting at 8: ; TEX_SAMPLE T3.XYZW, T6.XY__ RID:16 SID:0 CT:NNNN ; 00061010 F00D1003 FC800000 00000000 TEX_SAMPLE T5.XYZW, T5.XY__ RID:16 SID:0 CT:NNNN ; 00051010 F00D1005 FC800000 00000000 TEX_SAMPLE T4.XYZW, T4.XY__ RID:16 SID:0 CT:NNNN ; 00041010 F00D1004 FC800000 00000000 TEX_SAMPLE T1.XYZW, T1.XY__ RID:16 SID:0 CT:NNNN ; 00011010 F00D1001 FC800000 00000000 TEX_SAMPLE T0.XYZW, T2.XY__ RID:16 SID:0 CT:NNNN ; 00021010 F00D1000 FC800000 00000000 ALU clause starting at 18: ; INTERP_XY T1.X, T0.Y, ARRAY_BASE, ; 00380400 00346B10 INTERP_XY T1.Y, T0.X, ARRAY_BASE, ; 00380000 20346B10 INTERP_XY T0.Z (MASKED), T0.Y, ARRAY_BASE, ; 00380400 40146B00 INTERP_XY * T0.W (MASKED), T0.X, ARRAY_BASE, ; 80380000 60146B00 INTERP_XY T2.X, T0.Y, ARRAY_BASE, ; 00382400 00546B10 INTERP_XY T2.Y, T0.X, ARRAY_BASE, ; 00382000 20546B10 INTERP_XY T0.Z (MASKED), T0.Y, ARRAY_BASE, ; 00382400 40146B00 INTERP_XY * T0.W (MASKED), T0.X, ARRAY_BASE, ; 80382000 60146B00 INTERP_ZW T0.X (MASKED), T0.Y, ARRAY_BASE, ; 00382400 00146B80 INTERP_ZW T0.Y (MASKED), T0.X, ARRAY_BASE, ; 00382000 20146B80 INTERP_ZW T3.Z, T0.Y, ARRAY_BASE, ; 00382400 40746B90 INTERP_ZW * T3.W, T0.X, ARRAY_BASE, ; 80382000 60746B90 MOV * T4.X, PV.Z, ; 800008FE 00800C90 INTERP_XY T5.X, T0.Y, ARRAY_BASE, ; 00384400 00B46B10 INTERP_XY T5.Y, T0.X, ARRAY_BASE, ; 00384000 20B46B10 INTERP_XY T0.Z (MASKED), T0.Y, ARRAY_BASE, ; 00384400 40146B00 INTERP_XY * T0.W (MASKED), T0.X, ARRAY_BASE, ; 80384000 60146B00 INTERP_ZW T0.X (MASKED), T0.Y, ARRAY_BASE, ; 00384400 00146B80 INTERP_ZW T0.Y (MASKED), T0.X, ARRAY_BASE, ; 00384000 20146B80 INTERP_ZW T0.Z, T0.Y, ARRAY_BASE, ; 00384400 40146B90 INTERP_ZW * T0.W, T0.X, ARRAY_BASE, ; 80384000 60146B90 MOV T6.X, PV.Z, ; 000008FE 00C00C90 MOV * T4.Y, T3.W, ; 80000C03 20800C90 MOV * T6.Y, T0.W, ; 80000C00 20C00C90 ALU clause starting at 42: ; ADD * T0.W, T1.X, -T0.X, ; 82000001 60000010 SETGE T0.X, |PV.W|, literal.x, ; 001FACFE 00000511 ADD * T2.W, T1.X, -T4.X, ; 82008001 60400010 994352038(3.000000e-03), 0(0.000000e+00) ; 3B449BA6 00000000 SETGE T0.Y, |PV.W|, literal.x, ; 001FACFE 20000511 ADD * T2.W, T1.X, -T5.X, ; 8200A001 60400010 994352038(3.000000e-03), 0(0.000000e+00) ; 3B449BA6 00000000 SETGE T0.Z, |PV.W|, literal.x, ; 001FACFE 40000511 ADD * T1.W, T1.X, -T3.X, ; 82006001 60200010 994352038(3.000000e-03), 0(0.000000e+00) ; 3B449BA6 00000000 SETGE * T0.W, |PV.W|, literal.x, ; 801FACFE 60000511 994352038(3.000000e-03), 0(0.000000e+00) ; 3B449BA6 00000000 DOT4 T1.X, T0.X, 1.0, ; 001F2000 00205F10 DOT4 T1.Y (MASKED), T0.Y, 1.0, ; 001F2400 20205F00 DOT4 T1.Z (MASKED), T0.Z, 1.0, ; 001F2800 40205F00 DOT4 * T1.W (MASKED), T0.W, 1.0, ; 801F2C00 60205F00 SETE * T1.W, PV.X, 0.0, ; 801F00FE 60200410 SETE_DX10 * T1.W, PV.W, 0.0, ; 801F0CFE 60200610 PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002104 ALU clause starting at 61: ; KILLGT * T1.X (MASKED), 1.0, 0.0, ; 801F00F9 00201680 ===== SHADER #52 ======================================== PS/CAYMAN/CAYMAN ===== ===== 124 dw ===== 7 gprs ===== 1 stack ======================================== 0000 00000012 a05c0000 ALU 24 @36 0036 00380400 00346b10 1 x: INTERP_XY R1.x, R0.y, Param0.x VEC_210 0038 00380000 20346b10 y: INTERP_XY R1.y, R0.x, Param0.x VEC_210 0040 00380400 40146b00 z: INTERP_XY __.z, R0.y, Param0.x VEC_210 0042 80380000 60146b00 w: INTERP_XY __.w, R0.x, Param0.x VEC_210 0044 00382400 00546b10 2 x: INTERP_XY R2.x, R0.y, Param1.x VEC_210 0046 00382000 20546b10 y: INTERP_XY R2.y, R0.x, Param1.x VEC_210 0048 00382400 40146b00 z: INTERP_XY __.z, R0.y, Param1.x VEC_210 0050 80382000 60146b00 w: INTERP_XY __.w, R0.x, Param1.x VEC_210 0052 00382400 00146b80 3 x: INTERP_ZW __.x, R0.y, Param1.x VEC_210 0054 00382000 20146b80 y: INTERP_ZW __.y, R0.x, Param1.x VEC_210 0056 00382400 40746b90 z: INTERP_ZW R3.z, R0.y, Param1.x VEC_210 0058 80382000 60746b90 w: INTERP_ZW R3.w, R0.x, Param1.x VEC_210 0060 800008fe 00800c90 4 x: MOV R4.x, PV.z 0062 00384400 00b46b10 5 x: INTERP_XY R5.x, R0.y, Param2.x VEC_210 0064 00384000 20b46b10 y: INTERP_XY R5.y, R0.x, Param2.x VEC_210 0066 00384400 40146b00 z: INTERP_XY __.z, R0.y, Param2.x VEC_210 0068 80384000 60146b00 w: INTERP_XY __.w, R0.x, Param2.x VEC_210 0070 00384400 00146b80 6 x: INTERP_ZW __.x, R0.y, Param2.x VEC_210 0072 00384000 20146b80 y: INTERP_ZW __.y, R0.x, Param2.x VEC_210 0074 00384400 40146b90 z: INTERP_ZW R0.z, R0.y, Param2.x VEC_210 0076 80384000 60146b90 w: INTERP_ZW R0.w, R0.x, Param2.x VEC_210 0078 000008fe 00c00c90 7 x: MOV R6.x, PV.z 0080 80000c03 20800c90 y: MOV R4.y, R3.w 0082 80000c00 20c00c90 8 y: MOV R6.y, R0.w 0002 00000008 80401000 TEX 5 @16 0016 00061010 f00d1003 fc800000 SAMPLE R3.xyzw, R6.xy__, RID:16, SID:0 CT:NNNN 0020 00051010 f00d1005 fc800000 SAMPLE R5.xyzw, R5.xy__, RID:16, SID:0 CT:NNNN 0024 00041010 f00d1004 fc800000 SAMPLE R4.xyzw, R4.xy__, RID:16, SID:0 CT:NNNN 0028 00011010 f00d1001 fc800000 SAMPLE R1.xyzw, R1.xy__, RID:16, SID:0 CT:NNNN 0032 00021010 f00d1000 fc800000 SAMPLE R0.xyzw, R2.xy__, RID:16, SID:0 CT:NNNN 0004 0000002a a4480000 ALU_PUSH_BEFORE 19 @84 0084 82000001 60000010 9 w: ADD R0.w, R1.x, -R0.x 0086 001facfe 00000511 10 x: SETGE R0.x, |PV.w|, [0x3b449ba6 0.003].x 0088 82008001 60400010 w: ADD R2.w, R1.x, -R4.x 0090 3b449ba6 0092 001facfe 20000511 11 y: SETGE R0.y, |PV.w|, [0x3b449ba6 0.003].x 0094 8200a001 60400010 w: ADD R2.w, R1.x, -R5.x 0096 3b449ba6 0098 001facfe 40000511 12 z: SETGE R0.z, |PV.w|, [0x3b449ba6 0.003].x 0100 82006001 60200010 w: ADD R1.w, R1.x, -R3.x 0102 3b449ba6 0104 801facfe 60000511 13 w: SETGE R0.w, |PV.w|, [0x3b449ba6 0.003].x 0106 3b449ba6 0108 001f2000 00205f10 14 x: DOT4 R1.x, R0.x, 1.0 0110 001f2400 20205f00 y: DOT4 __.y, R0.y, 1.0 0112 001f2800 40205f00 z: DOT4 __.z, R0.z, 1.0 0114 801f2c00 60205f00 w: DOT4 __.w, R0.w, 1.0 0116 801f00fe 60200410 15 w: SETE R1.w, PV.x, 0 0118 801f0cfe 60200610 16 w: SETE_DX10 R1.w, PV.w, 0 0120 801f0cfe 00002104 17 M x: PRED_SETE_INT __.x, PV.w, 0 0006 00000005 82800001 JUMP @10 POP:1 0008 0000003d a8000000 ALU_POP_AFTER 1 @122 0122 801f00f9 00201680 18 x: KILLGT __.x, 1.0, 0 0010 c0000000 95200688 EXPORT_DONE PIXEL 0 R0.xyzw 0012 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #52 OPT ==================================== PS/CAYMAN/CAYMAN ===== ===== 100 dw ===== 4 gprs ===== 0 stack ======================================== 0000 00000005 a04c0000 ALU 20 @10 0010 00382400 00346b10 1 x: INTERP_XY R1.x, R0.y, Param1.x VEC_210 0012 00b82000 20346b10 y: INTERP_XY R1.y, R0.x, Param1.y VEC_210 0014 01382400 40146b00 z: INTERP_XY __.z, R0.y, Param1.z VEC_210 0016 81b82000 60146b00 w: INTERP_XY __.w, R0.x, Param1.w VEC_210 0018 00382400 00146b80 2 x: INTERP_ZW __.x, R0.y, Param1.x VEC_210 0020 00b82000 20146b80 y: INTERP_ZW __.y, R0.x, Param1.y VEC_210 0022 01382400 40146b90 z: INTERP_ZW R0.z, R0.y, Param1.z VEC_210 0024 81b82000 60146b90 w: INTERP_ZW R0.w, R0.x, Param1.w VEC_210 0026 00384400 00746b10 3 x: INTERP_XY R3.x, R0.y, Param2.x VEC_210 0028 00b84000 20746b10 y: INTERP_XY R3.y, R0.x, Param2.y VEC_210 0030 01384400 40146b00 z: INTERP_XY __.z, R0.y, Param2.z VEC_210 0032 81b84000 60146b00 w: INTERP_XY __.w, R0.x, Param2.w VEC_210 0034 00380400 00546b10 4 x: INTERP_XY R2.x, R0.y, Param0.x VEC_210 0036 00b80000 20546b10 y: INTERP_XY R2.y, R0.x, Param0.y VEC_210 0038 01380400 40146b00 z: INTERP_XY __.z, R0.y, Param0.z VEC_210 0040 81b80000 60146b00 w: INTERP_XY __.w, R0.x, Param0.w VEC_210 0042 00384400 00146b80 5 x: INTERP_ZW __.x, R0.y, Param2.x VEC_210 0044 00b84000 20146b80 y: INTERP_ZW __.y, R0.x, Param2.y VEC_210 0046 01384400 40346b90 z: INTERP_ZW R1.z, R0.y, Param2.z VEC_210 0048 81b84000 60346b90 w: INTERP_ZW R1.w, R0.x, Param2.w VEC_210 0002 0000001a 80401000 TEX 5 @52 0052 00011010 f003fe01 fda00000 SAMPLE R1.___x, R1.zw__, RID:16, SID:0 CT:NNNN 0056 00021010 f01f8e00 fc800000 SAMPLE R0._x__, R2.xy__, RID:16, SID:0 CT:NNNN 0060 00031010 f01c7e01 fc800000 SAMPLE R1.__x_, R3.xy__, RID:16, SID:0 CT:NNNN 0064 00001010 f01c7e00 fda00000 SAMPLE R0.__x_, R0.zw__, RID:16, SID:0 CT:NNNN 0068 00011010 f01ff000 fc800000 SAMPLE R0.x___, R1.xy__, RID:16, SID:0 CT:NNNN 0004 00000024 a0340000 ALU 14 @72 0072 03002400 0f840010 6 x: ADD T0.x, R0.y, -R1.z VEC_021 0074 03000400 2f800010 y: ADD T0.y, R0.y, -R0.z 0076 02000400 4f800010 z: ADD T0.z, R0.y, -R0.x 0078 83802400 6f800010 w: ADD T0.w, R0.y, -R1.w 0080 001fa87c 00000511 7 x: SETGE R0.x, |T0.z|, [0x3b449ba6 0.003].x 0082 001fa47c 20000511 y: SETGE R0.y, |T0.y|, [0x3b449ba6 0.003].x 0084 001fa07c 40000511 z: SETGE R0.z, |T0.x|, [0x3b449ba6 0.003].x 0086 801fac7c 60000511 w: SETGE R0.w, |T0.w|, [0x3b449ba6 0.003].x 0088 3b449ba6 0090 001f2000 00005f00 8 x: DOT4 __.x, R0.x, 1.0 0092 001f2400 20005f00 y: DOT4 __.y, R0.y, 1.0 0094 001f2800 40005f00 z: DOT4 __.z, R0.z, 1.0 0096 801f2c00 6f805f10 w: DOT4 T0.w, R0.w, 1.0 0098 801f0c7c 00001600 9 x: KILLE __.x, T0.w, 0 0006 c0000000 95000688 EXPORT_DONE PIXEL 0 R0.xyzw 0008 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL SAMP[1] DCL SAMP[2] DCL CONST[0] DCL TEMP[0..6] IMM[0] FLT32 { 0.0000, -0.2500, 0.0061, 0.5000} IMM[1] FLT32 { -1.5000, -2.0000, 0.9000, 1.5000} IMM[2] FLT32 { 2.0000, 1.0000, 4.0000, 33.0000} IMM[3] FLT32 { 8.0000, 0.0000, 0.0000, 0.0000} 0: MOV TEMP[0], IMM[0].xxxx 1: TEX TEMP[1], IN[0].xyyy, SAMP[1], 2D 2: MOV TEMP[2].x, TEMP[1] 3: SNE TEMP[3].x, TEMP[1].yyyy, IMM[0].xxxx 4: IF TEMP[3].xxxx :76 5: MOV TEMP[1].xy, IN[0].xyxx 6: MOV TEMP[4].x, IMM[1].xxxx 7: BGNLOOP :24 8: MUL TEMP[5].x, IMM[1].yyyy, IMM[3].xxxx 9: SLE TEMP[6].x, TEMP[4].xxxx, TEMP[5].xxxx 10: IF TEMP[6].xxxx :12 11: BRK 12: ENDIF 13: MOV TEMP[4].y, IMM[0].xxxx 14: MAD TEMP[3].xyz, CONST[0].xyyy, TEMP[4].xyyy, TEMP[1].xyyy 15: MOV TEMP[3].w, IMM[0].xxxx 16: TXL TEMP[5], TEMP[3], SAMP[2], 2D 17: MOV TEMP[3].x, TEMP[5].yyyy 18: SLT TEMP[6].x, TEMP[5].yyyy, IMM[1].zzzz 19: IF TEMP[6].xxxx :21 20: BRK 21: ENDIF 22: ADD TEMP[6].x, TEMP[4].xxxx, IMM[1].yyyy 23: MOV TEMP[4].x, TEMP[6].xxxx 24: ENDLOOP :7 25: ADD TEMP[1].x, TEMP[4].xxxx, IMM[1].wwww 26: MAD TEMP[6].x, -IMM[2].xxxx, TEMP[3].xxxx, TEMP[1].xxxx 27: MUL TEMP[1].x, IMM[1].yyyy, IMM[3].xxxx 28: MAX TEMP[4].x, TEMP[6].xxxx, TEMP[1].xxxx 29: MOV TEMP[1].x, TEMP[4].xxxx 30: MOV TEMP[3].xy, IN[0].xyxx 31: MOV TEMP[5].x, IMM[1].wwww 32: BGNLOOP :49 33: MUL TEMP[6].x, IMM[2].xxxx, IMM[3].xxxx 34: SGE TEMP[4].x, TEMP[5].xxxx, TEMP[6].xxxx 35: IF TEMP[4].xxxx :37 36: BRK 37: ENDIF 38: MOV TEMP[5].y, IMM[0].xxxx 39: MAD TEMP[4].xyz, CONST[0].xyyy, TEMP[5].xyyy, TEMP[3].xyyy 40: MOV TEMP[4].w, IMM[0].xxxx 41: TXL TEMP[6].xy, TEMP[4], SAMP[2], 2D 42: MOV TEMP[4].x, TEMP[6].yyyy 43: SLT TEMP[0].x, TEMP[6].yyyy, IMM[1].zzzz 44: IF TEMP[0].xxxx :46 45: BRK 46: ENDIF 47: ADD TEMP[6].x, TEMP[5].xxxx, IMM[2].xxxx 48: MOV TEMP[5].x, TEMP[6].xxxx 49: ENDLOOP :32 50: ADD TEMP[3].x, TEMP[5].xxxx, IMM[1].xxxx 51: MAD TEMP[5].x, IMM[2].xxxx, TEMP[4].xxxx, TEMP[3].xxxx 52: MUL TEMP[3].x, IMM[2].xxxx, IMM[3].xxxx 53: MIN TEMP[4].x, TEMP[5].xxxx, TEMP[3].xxxx 54: MOV TEMP[3].x, TEMP[1].xxxx 55: MOV TEMP[3].y, TEMP[4].xxxx 56: MOV TEMP[5].yw, IMM[0].yyyy 57: MOV TEMP[5].x, TEMP[1].xxxx 58: ADD TEMP[1].x, TEMP[4].xxxx, IMM[2].yyyy 59: MOV TEMP[5].z, TEMP[1].xxxx 60: MAD TEMP[1], TEMP[5], CONST[0].xyxy, IN[0].xyxy 61: MOV TEMP[4], TEMP[1].xyyy 62: MOV TEMP[4].w, IMM[0].xxxx 63: TXL TEMP[5].x, TEMP[4], SAMP[2], 2D 64: MOV TEMP[4].x, TEMP[5].xxxx 65: MOV TEMP[5], TEMP[1].zwww 66: MOV TEMP[5].w, IMM[0].xxxx 67: TXL TEMP[1].x, TEMP[5], SAMP[2], 2D 68: MOV TEMP[4].y, TEMP[1].xxxx 69: MUL TEMP[5].xy, IMM[2].zzzz, TEMP[4].xyyy 70: ROUND TEMP[1].xy, TEMP[5].xyyy 71: ABS TEMP[4].xy, TEMP[3].xyyy 72: MAD TEMP[3].xy, IMM[2].wwww, TEMP[1].xyyy, TEMP[4].xyyy 73: MUL TEMP[5].xyz, TEMP[3].xyyy, IMM[0].zzzz 74: MOV TEMP[5].w, IMM[0].xxxx 75: TXL TEMP[0].xy, TEMP[5], SAMP[0], 2D 76: ENDIF 77: SNE TEMP[1].x, TEMP[2].xxxx, IMM[0].xxxx 78: IF TEMP[1].xxxx :151 79: MOV TEMP[1].xy, IN[0].xyxx 80: MOV TEMP[3].x, IMM[1].xxxx 81: BGNLOOP :98 82: MUL TEMP[4].x, IMM[1].yyyy, IMM[3].xxxx 83: SLE TEMP[5].x, TEMP[3].xxxx, TEMP[4].xxxx 84: IF TEMP[5].xxxx :86 85: BRK 86: ENDIF 87: MOV TEMP[3].y, IMM[0].xxxx 88: MAD TEMP[5].xyz, CONST[0].xyyy, TEMP[3].yxxx, TEMP[1].xyyy 89: MOV TEMP[5].w, IMM[0].xxxx 90: TXL TEMP[4], TEMP[5], SAMP[2], 2D 91: MOV TEMP[2].x, TEMP[4].xxxx 92: SLT TEMP[5].x, TEMP[4].xxxx, IMM[1].zzzz 93: IF TEMP[5].xxxx :95 94: BRK 95: ENDIF 96: ADD TEMP[4].x, TEMP[3].xxxx, IMM[1].yyyy 97: MOV TEMP[3].x, TEMP[4].xxxx 98: ENDLOOP :81 99: ADD TEMP[1].x, TEMP[3].xxxx, IMM[1].wwww 100: MAD TEMP[6].x, -IMM[2].xxxx, TEMP[2].xxxx, TEMP[1].xxxx 101: MUL TEMP[1].x, IMM[1].yyyy, IMM[3].xxxx 102: MAX TEMP[3].x, TEMP[6].xxxx, TEMP[1].xxxx 103: MOV TEMP[1].x, TEMP[3].xxxx 104: MOV TEMP[2].xy, IN[0].xyxx 105: MOV TEMP[4].x, IMM[1].wwww 106: BGNLOOP :123 107: MUL TEMP[5].x, IMM[2].xxxx, IMM[3].xxxx 108: SGE TEMP[6].x, TEMP[4].xxxx, TEMP[5].xxxx 109: IF TEMP[6].xxxx :111 110: BRK 111: ENDIF 112: MOV TEMP[4].y, IMM[0].xxxx 113: MAD TEMP[5].xyz, CONST[0].xyyy, TEMP[4].yxxx, TEMP[2].xyyy 114: MOV TEMP[5].w, IMM[0].xxxx 115: TXL TEMP[6], TEMP[5], SAMP[2], 2D 116: MOV TEMP[3].x, TEMP[6].xxxx 117: SLT TEMP[5].x, TEMP[6].xxxx, IMM[1].zzzz 118: IF TEMP[5].xxxx :120 119: BRK 120: ENDIF 121: ADD TEMP[6].x, TEMP[4].xxxx, IMM[2].xxxx 122: MOV TEMP[4].x, TEMP[6].xxxx 123: ENDLOOP :106 124: ADD TEMP[2].x, TEMP[4].xxxx, IMM[1].xxxx 125: MAD TEMP[4].x, IMM[2].xxxx, TEMP[3].xxxx, TEMP[2].xxxx 126: MUL TEMP[2].x, IMM[2].xxxx, IMM[3].xxxx 127: MIN TEMP[3].x, TEMP[4].xxxx, TEMP[2].xxxx 128: MOV TEMP[2].x, TEMP[1].xxxx 129: MOV TEMP[2].y, TEMP[3].xxxx 130: MOV TEMP[4].xz, IMM[0].yyyy 131: MOV TEMP[4].y, TEMP[1].xxxx 132: ADD TEMP[1].x, TEMP[3].xxxx, IMM[2].yyyy 133: MOV TEMP[4].w, TEMP[1].xxxx 134: MAD TEMP[1], TEMP[4], CONST[0].xyxy, IN[0].xyxy 135: MOV TEMP[3], TEMP[1].xyyy 136: MOV TEMP[3].w, IMM[0].xxxx 137: TXL TEMP[4].y, TEMP[3], SAMP[2], 2D 138: MOV TEMP[3].x, TEMP[4].yyyy 139: MOV TEMP[4], TEMP[1].zwww 140: MOV TEMP[4].w, IMM[0].xxxx 141: TXL TEMP[1].y, TEMP[4], SAMP[2], 2D 142: MOV TEMP[3].y, TEMP[1].yyyy 143: MUL TEMP[4].xy, IMM[2].zzzz, TEMP[3].xyyy 144: ROUND TEMP[1].xy, TEMP[4].xyyy 145: ABS TEMP[3].xy, TEMP[2].xyyy 146: MAD TEMP[2].xy, IMM[2].wwww, TEMP[1].xyyy, TEMP[3].xyyy 147: MUL TEMP[3].xyz, TEMP[2].xyyy, IMM[0].zzzz 148: MOV TEMP[3].w, IMM[0].xxxx 149: TXL TEMP[1].xy, TEMP[3], SAMP[0], 2D 150: MOV TEMP[0].zw, TEMP[1].yyxy 151: ENDIF 152: MOV OUT[0], TEMP[0] 153: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg) #0 { main_body: %2 = extractelement <4 x float> %0, i32 0 %3 = extractelement <4 x float> %0, i32 1 %4 = call <2 x float> @llvm.R600.interp.xy(i32 0, float %2, float %3) %5 = call <2 x float> @llvm.R600.interp.zw(i32 0, float %2, float %3) %6 = shufflevector <2 x float> %4, <2 x float> %5, <4 x i32> %7 = extractelement <4 x float> %6, i32 0 %8 = extractelement <4 x float> %6, i32 1 %9 = insertelement <4 x float> undef, float %7, i32 0 %10 = insertelement <4 x float> %9, float %8, i32 1 %11 = insertelement <4 x float> %10, float %8, i32 2 %12 = insertelement <4 x float> %11, float %8, i32 3 %13 = extractelement <4 x float> %12, i32 0 %14 = extractelement <4 x float> %12, i32 1 %15 = insertelement <4 x float> undef, float %13, i32 0 %16 = insertelement <4 x float> %15, float %14, i32 1 %17 = insertelement <4 x float> %16, float undef, i32 2 %18 = insertelement <4 x float> %17, float undef, i32 3 %19 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %18, i32 17, i32 1, i32 2) %20 = extractelement <4 x float> %19, i32 0 %21 = extractelement <4 x float> %19, i32 1 %22 = fcmp une float %21, 0.000000e+00 %23 = select i1 %22, float 1.000000e+00, float 0.000000e+00 %24 = fcmp une float %23, 0.000000e+00 br i1 %24, label %LOOP, label %ENDIF ENDIF: ; preds = %main_body, %ENDLOOP34 %temp.0 = phi float [ %113, %ENDLOOP34 ], [ 0.000000e+00, %main_body ] %temp1.0 = phi float [ %114, %ENDLOOP34 ], [ 0.000000e+00, %main_body ] %25 = fcmp une float %20, 0.000000e+00 %26 = select i1 %25, float 1.000000e+00, float 0.000000e+00 %27 = fcmp une float %26, 0.000000e+00 br i1 %27, label %LOOP46, label %ENDIF42 LOOP: ; preds = %main_body, %ENDIF31 %temp12.0 = phi float [ %53, %ENDIF31 ], [ %23, %main_body ] %temp16.0 = phi float [ %57, %ENDIF31 ], [ -1.500000e+00, %main_body ] %28 = fcmp ole float %temp16.0, -1.600000e+01 %29 = select i1 %28, float 1.000000e+00, float 0.000000e+00 %30 = fcmp une float %29, 0.000000e+00 br i1 %30, label %ENDLOOP, label %ENDIF28 ENDLOOP: ; preds = %ENDIF28, %LOOP %temp12.1 = phi float [ %temp12.0, %LOOP ], [ %53, %ENDIF28 ] %31 = fadd float %temp16.0, 1.500000e+00 %32 = fmul float -2.000000e+00, %temp12.1 %33 = fadd float %32, %31 %34 = fcmp uge float %33, -1.600000e+01 %35 = select i1 %34, float %33, float -1.600000e+01 br label %LOOP35 ENDIF28: ; preds = %LOOP %36 = load <4 x float> addrspace(8)* null %37 = extractelement <4 x float> %36, i32 0 %38 = fmul float %37, %temp16.0 %39 = fadd float %38, %7 %40 = load <4 x float> addrspace(8)* null %41 = extractelement <4 x float> %40, i32 1 %42 = fmul float %41, 0.000000e+00 %43 = fadd float %42, %8 %44 = load <4 x float> addrspace(8)* null %45 = extractelement <4 x float> %44, i32 1 %46 = fmul float %45, 0.000000e+00 %47 = fadd float %46, %8 %48 = insertelement <4 x float> undef, float %39, i32 0 %49 = insertelement <4 x float> %48, float %43, i32 1 %50 = insertelement <4 x float> %49, float %47, i32 2 %51 = insertelement <4 x float> %50, float 0.000000e+00, i32 3 %52 = call <4 x float> @llvm.AMDGPU.txl(<4 x float> %51, i32 18, i32 2, i32 2) %53 = extractelement <4 x float> %52, i32 1 %54 = fcmp olt float %53, 0x3FECCCCCC0000000 %55 = select i1 %54, float 1.000000e+00, float 0.000000e+00 %56 = fcmp une float %55, 0.000000e+00 br i1 %56, label %ENDLOOP, label %ENDIF31 ENDIF31: ; preds = %ENDIF28 %57 = fadd float %temp16.0, -2.000000e+00 br label %LOOP LOOP35: ; preds = %ENDIF39, %ENDLOOP %temp20.0 = phi float [ 1.500000e+00, %ENDLOOP ], [ %136, %ENDIF39 ] %58 = fcmp oge float %temp20.0, 1.600000e+01 %59 = select i1 %58, float 1.000000e+00, float 0.000000e+00 %60 = fcmp une float %59, 0.000000e+00 br i1 %60, label %ENDLOOP34, label %ENDIF36 ENDLOOP34: ; preds = %ENDIF36, %LOOP35 %temp16.1 = phi float [ %59, %LOOP35 ], [ %132, %ENDIF36 ] %61 = fadd float %temp20.0, -1.500000e+00 %62 = fmul float 2.000000e+00, %temp16.1 %63 = fadd float %62, %61 %64 = fcmp uge float %63, 1.600000e+01 %65 = select i1 %64, float 1.600000e+01, float %63 %66 = fadd float %65, 1.000000e+00 %67 = load <4 x float> addrspace(8)* null %68 = extractelement <4 x float> %67, i32 0 %69 = fmul float %35, %68 %70 = fadd float %69, %7 %71 = load <4 x float> addrspace(8)* null %72 = extractelement <4 x float> %71, i32 1 %73 = fmul float -2.500000e-01, %72 %74 = fadd float %73, %8 %75 = load <4 x float> addrspace(8)* null %76 = extractelement <4 x float> %75, i32 0 %77 = fmul float %66, %76 %78 = fadd float %77, %7 %79 = load <4 x float> addrspace(8)* null %80 = extractelement <4 x float> %79, i32 1 %81 = fmul float -2.500000e-01, %80 %82 = fadd float %81, %8 %83 = insertelement <4 x float> undef, float %70, i32 0 %84 = insertelement <4 x float> %83, float %74, i32 1 %85 = insertelement <4 x float> %84, float %74, i32 2 %86 = insertelement <4 x float> %85, float 0.000000e+00, i32 3 %87 = call <4 x float> @llvm.AMDGPU.txl(<4 x float> %86, i32 18, i32 2, i32 2) %88 = extractelement <4 x float> %87, i32 0 %89 = insertelement <4 x float> undef, float %78, i32 0 %90 = insertelement <4 x float> %89, float %82, i32 1 %91 = insertelement <4 x float> %90, float %82, i32 2 %92 = insertelement <4 x float> %91, float 0.000000e+00, i32 3 %93 = call <4 x float> @llvm.AMDGPU.txl(<4 x float> %92, i32 18, i32 2, i32 2) %94 = extractelement <4 x float> %93, i32 0 %95 = fmul float 4.000000e+00, %88 %96 = fmul float 4.000000e+00, %94 %97 = call float @llvm.AMDIL.round.nearest.(float %95) %98 = call float @llvm.AMDIL.round.nearest.(float %96) %99 = call float @fabs(float %35) %100 = call float @fabs(float %65) %101 = fmul float 3.300000e+01, %97 %102 = fadd float %101, %99 %103 = fmul float 3.300000e+01, %98 %104 = fadd float %103, %100 %105 = fmul float %102, 0x3F78F9C140000000 %106 = fmul float %104, 0x3F78F9C140000000 %107 = fmul float %104, 0x3F78F9C140000000 %108 = insertelement <4 x float> undef, float %105, i32 0 %109 = insertelement <4 x float> %108, float %106, i32 1 %110 = insertelement <4 x float> %109, float %107, i32 2 %111 = insertelement <4 x float> %110, float 0.000000e+00, i32 3 %112 = call <4 x float> @llvm.AMDGPU.txl(<4 x float> %111, i32 16, i32 0, i32 2) %113 = extractelement <4 x float> %112, i32 0 %114 = extractelement <4 x float> %112, i32 1 br label %ENDIF ENDIF36: ; preds = %LOOP35 %115 = load <4 x float> addrspace(8)* null %116 = extractelement <4 x float> %115, i32 0 %117 = fmul float %116, %temp20.0 %118 = fadd float %117, %7 %119 = load <4 x float> addrspace(8)* null %120 = extractelement <4 x float> %119, i32 1 %121 = fmul float %120, 0.000000e+00 %122 = fadd float %121, %8 %123 = load <4 x float> addrspace(8)* null %124 = extractelement <4 x float> %123, i32 1 %125 = fmul float %124, 0.000000e+00 %126 = fadd float %125, %8 %127 = insertelement <4 x float> undef, float %118, i32 0 %128 = insertelement <4 x float> %127, float %122, i32 1 %129 = insertelement <4 x float> %128, float %126, i32 2 %130 = insertelement <4 x float> %129, float 0.000000e+00, i32 3 %131 = call <4 x float> @llvm.AMDGPU.txl(<4 x float> %130, i32 18, i32 2, i32 2) %132 = extractelement <4 x float> %131, i32 1 %133 = fcmp olt float %132, 0x3FECCCCCC0000000 %134 = select i1 %133, float 1.000000e+00, float 0.000000e+00 %135 = fcmp une float %134, 0.000000e+00 br i1 %135, label %ENDLOOP34, label %ENDIF39 ENDIF39: ; preds = %ENDIF36 %136 = fadd float %temp20.0, 2.000000e+00 br label %LOOP35 ENDIF42: ; preds = %ENDIF, %ENDLOOP53 %temp2.0 = phi float [ %226, %ENDLOOP53 ], [ 0.000000e+00, %ENDIF ] %temp3.0 = phi float [ %227, %ENDLOOP53 ], [ 0.000000e+00, %ENDIF ] %137 = insertelement <4 x float> undef, float %temp.0, i32 0 %138 = insertelement <4 x float> %137, float %temp1.0, i32 1 %139 = insertelement <4 x float> %138, float %temp2.0, i32 2 %140 = insertelement <4 x float> %139, float %temp3.0, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %140, i32 0, i32 0) ret void LOOP46: ; preds = %ENDIF, %ENDIF50 %temp8.0 = phi float [ %166, %ENDIF50 ], [ %20, %ENDIF ] %temp12.2 = phi float [ %170, %ENDIF50 ], [ -1.500000e+00, %ENDIF ] %141 = fcmp ole float %temp12.2, -1.600000e+01 %142 = select i1 %141, float 1.000000e+00, float 0.000000e+00 %143 = fcmp une float %142, 0.000000e+00 br i1 %143, label %ENDLOOP45, label %ENDIF47 ENDLOOP45: ; preds = %ENDIF47, %LOOP46 %temp8.1 = phi float [ %temp8.0, %LOOP46 ], [ %166, %ENDIF47 ] %144 = fadd float %temp12.2, 1.500000e+00 %145 = fmul float -2.000000e+00, %temp8.1 %146 = fadd float %145, %144 %147 = fcmp uge float %146, -1.600000e+01 %148 = select i1 %147, float %146, float -1.600000e+01 br label %LOOP54 ENDIF47: ; preds = %LOOP46 %149 = load <4 x float> addrspace(8)* null %150 = extractelement <4 x float> %149, i32 0 %151 = fmul float %150, 0.000000e+00 %152 = fadd float %151, %7 %153 = load <4 x float> addrspace(8)* null %154 = extractelement <4 x float> %153, i32 1 %155 = fmul float %154, %temp12.2 %156 = fadd float %155, %8 %157 = load <4 x float> addrspace(8)* null %158 = extractelement <4 x float> %157, i32 1 %159 = fmul float %158, %temp12.2 %160 = fadd float %159, %8 %161 = insertelement <4 x float> undef, float %152, i32 0 %162 = insertelement <4 x float> %161, float %156, i32 1 %163 = insertelement <4 x float> %162, float %160, i32 2 %164 = insertelement <4 x float> %163, float 0.000000e+00, i32 3 %165 = call <4 x float> @llvm.AMDGPU.txl(<4 x float> %164, i32 18, i32 2, i32 2) %166 = extractelement <4 x float> %165, i32 0 %167 = fcmp olt float %166, 0x3FECCCCCC0000000 %168 = select i1 %167, float 1.000000e+00, float 0.000000e+00 %169 = fcmp une float %168, 0.000000e+00 br i1 %169, label %ENDLOOP45, label %ENDIF50 ENDIF50: ; preds = %ENDIF47 %170 = fadd float %temp12.2, -2.000000e+00 br label %LOOP46 LOOP54: ; preds = %ENDIF58, %ENDLOOP45 %temp12.3 = phi float [ %148, %ENDLOOP45 ], [ %245, %ENDIF58 ] %temp16.2 = phi float [ 1.500000e+00, %ENDLOOP45 ], [ %249, %ENDIF58 ] %171 = fcmp oge float %temp16.2, 1.600000e+01 %172 = select i1 %171, float 1.000000e+00, float 0.000000e+00 %173 = fcmp une float %172, 0.000000e+00 br i1 %173, label %ENDLOOP53, label %ENDIF55 ENDLOOP53: ; preds = %ENDIF55, %LOOP54 %temp12.4 = phi float [ %temp12.3, %LOOP54 ], [ %245, %ENDIF55 ] %174 = fadd float %temp16.2, -1.500000e+00 %175 = fmul float 2.000000e+00, %temp12.4 %176 = fadd float %175, %174 %177 = fcmp uge float %176, 1.600000e+01 %178 = select i1 %177, float 1.600000e+01, float %176 %179 = fadd float %178, 1.000000e+00 %180 = load <4 x float> addrspace(8)* null %181 = extractelement <4 x float> %180, i32 0 %182 = fmul float -2.500000e-01, %181 %183 = fadd float %182, %7 %184 = load <4 x float> addrspace(8)* null %185 = extractelement <4 x float> %184, i32 1 %186 = fmul float %148, %185 %187 = fadd float %186, %8 %188 = load <4 x float> addrspace(8)* null %189 = extractelement <4 x float> %188, i32 0 %190 = fmul float -2.500000e-01, %189 %191 = fadd float %190, %7 %192 = load <4 x float> addrspace(8)* null %193 = extractelement <4 x float> %192, i32 1 %194 = fmul float %179, %193 %195 = fadd float %194, %8 %196 = insertelement <4 x float> undef, float %183, i32 0 %197 = insertelement <4 x float> %196, float %187, i32 1 %198 = insertelement <4 x float> %197, float %187, i32 2 %199 = insertelement <4 x float> %198, float 0.000000e+00, i32 3 %200 = call <4 x float> @llvm.AMDGPU.txl(<4 x float> %199, i32 18, i32 2, i32 2) %201 = extractelement <4 x float> %200, i32 1 %202 = insertelement <4 x float> undef, float %191, i32 0 %203 = insertelement <4 x float> %202, float %195, i32 1 %204 = insertelement <4 x float> %203, float %195, i32 2 %205 = insertelement <4 x float> %204, float 0.000000e+00, i32 3 %206 = call <4 x float> @llvm.AMDGPU.txl(<4 x float> %205, i32 18, i32 2, i32 2) %207 = extractelement <4 x float> %206, i32 1 %208 = fmul float 4.000000e+00, %201 %209 = fmul float 4.000000e+00, %207 %210 = call float @llvm.AMDIL.round.nearest.(float %208) %211 = call float @llvm.AMDIL.round.nearest.(float %209) %212 = call float @fabs(float %148) %213 = call float @fabs(float %178) %214 = fmul float 3.300000e+01, %210 %215 = fadd float %214, %212 %216 = fmul float 3.300000e+01, %211 %217 = fadd float %216, %213 %218 = fmul float %215, 0x3F78F9C140000000 %219 = fmul float %217, 0x3F78F9C140000000 %220 = fmul float %217, 0x3F78F9C140000000 %221 = insertelement <4 x float> undef, float %218, i32 0 %222 = insertelement <4 x float> %221, float %219, i32 1 %223 = insertelement <4 x float> %222, float %220, i32 2 %224 = insertelement <4 x float> %223, float 0.000000e+00, i32 3 %225 = call <4 x float> @llvm.AMDGPU.txl(<4 x float> %224, i32 16, i32 0, i32 2) %226 = extractelement <4 x float> %225, i32 0 %227 = extractelement <4 x float> %225, i32 1 br label %ENDIF42 ENDIF55: ; preds = %LOOP54 %228 = load <4 x float> addrspace(8)* null %229 = extractelement <4 x float> %228, i32 0 %230 = fmul float %229, 0.000000e+00 %231 = fadd float %230, %7 %232 = load <4 x float> addrspace(8)* null %233 = extractelement <4 x float> %232, i32 1 %234 = fmul float %233, %temp16.2 %235 = fadd float %234, %8 %236 = load <4 x float> addrspace(8)* null %237 = extractelement <4 x float> %236, i32 1 %238 = fmul float %237, %temp16.2 %239 = fadd float %238, %8 %240 = insertelement <4 x float> undef, float %231, i32 0 %241 = insertelement <4 x float> %240, float %235, i32 1 %242 = insertelement <4 x float> %241, float %239, i32 2 %243 = insertelement <4 x float> %242, float 0.000000e+00, i32 3 %244 = call <4 x float> @llvm.AMDGPU.txl(<4 x float> %243, i32 18, i32 2, i32 2) %245 = extractelement <4 x float> %244, i32 0 %246 = fcmp olt float %245, 0x3FECCCCCC0000000 %247 = select i1 %246, float 1.000000e+00, float 0.000000e+00 %248 = fcmp une float %247, 0.000000e+00 br i1 %248, label %ENDLOOP53, label %ENDIF58 ENDIF58: ; preds = %ENDIF55 %249 = fadd float %temp16.2, 2.000000e+00 br label %LOOP54 } ; Function Attrs: readnone declare <2 x float> @llvm.R600.interp.xy(i32, float, float) #1 ; Function Attrs: readnone declare <2 x float> @llvm.R600.interp.zw(i32, float, float) #1 ; Function Attrs: readnone declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32, i32) #1 ; Function Attrs: readnone declare <4 x float> @llvm.AMDGPU.txl(<4 x float>, i32, i32, i32) #1 ; Function Attrs: readnone declare float @llvm.AMDIL.round.nearest.(float) #1 ; Function Attrs: readonly declare float @fabs(float) #2 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } attributes #2 = { readonly } Shader Disassembly: ALU 3, @122, KC0[], KC1[] ; 0000007A A00C0000 TEX 0 @100 ; 00000064 80400000 ALU_PUSH_BEFORE 2, @126, KC0[], KC1[] ; 0000007E A4080000 JUMP @5 POP:0 ; 00000005 82800000 ALU 2, @129, KC0[], KC1[] ; 00000081 A0080000 ELSE @48 POP:1 ; 00000030 83400001 ALU 1, @132, KC0[], KC1[] ; 00000084 A0040000 LOOP_START_DX10 @25 ; 00000019 81800000 ALU_PUSH_BEFORE 4, @134, KC0[], KC1[] ; 00000086 A4100000 JUMP @11 POP:0 ; 0000000B 82800000 ALU 1, @139, KC0[], KC1[] ; 0000008B A0040000 ELSE @20 POP:1 ; 00000014 83400001 ALU 1, @141, KC0[CB0:0-32], KC1[] ; 8000008D A0040000 TEX 0 @102 ; 00000066 80400000 ALU_PUSH_BEFORE 3, @143, KC0[], KC1[] ; 0000008F A40C0000 JUMP @17 POP:0 ; 00000011 82800000 ALU 1, @147, KC0[], KC1[] ; 00000093 A0040000 ELSE @19 POP:1 ; 00000013 83400001 ALU_POP_AFTER 2, @149, KC0[], KC1[] ; 00000095 A8080000 POP @20 POP:1 ; 00000014 83800001 ALU_PUSH_BEFORE 4, @152, KC0[], KC1[] ; 00000098 A4100000 JUMP @24 POP:1 ; 00000018 82800001 LOOP_BREAK @24 ; 00000018 82400000 POP @24 POP:1 ; 00000018 83800001 END_LOOP @8 ; 00000008 81400000 ALU 6, @157, KC0[], KC1[] ; 0000009D A0180000 LOOP_START_DX10 @44 ; 0000002C 81800000 ALU_PUSH_BEFORE 4, @164, KC0[], KC1[] ; 000000A4 A4100000 JUMP @30 POP:0 ; 0000001E 82800000 ALU 1, @169, KC0[], KC1[] ; 000000A9 A0040000 ELSE @39 POP:1 ; 00000027 83400001 ALU 1, @171, KC0[CB0:0-32], KC1[] ; 800000AB A0040000 TEX 0 @104 ; 00000068 80400000 ALU_PUSH_BEFORE 3, @173, KC0[], KC1[] ; 000000AD A40C0000 JUMP @36 POP:0 ; 00000024 82800000 ALU 1, @177, KC0[], KC1[] ; 000000B1 A0040000 ELSE @38 POP:1 ; 00000026 83400001 ALU_POP_AFTER 2, @179, KC0[], KC1[] ; 000000B3 A8080000 POP @39 POP:1 ; 00000027 83800001 ALU_PUSH_BEFORE 4, @182, KC0[], KC1[] ; 000000B6 A4100000 JUMP @43 POP:1 ; 0000002B 82800001 LOOP_BREAK @43 ; 0000002B 82400000 POP @43 POP:1 ; 0000002B 83800001 END_LOOP @27 ; 0000001B 81400000 ALU 11, @187, KC0[CB0:0-32], KC1[] ; 800000BB A02C0000 TEX 1 @106 ; 0000006A 80400400 ALU_POP_AFTER 14, @199, KC0[], KC1[] ; 000000C7 A8380000 TEX 0 @110 ; 0000006E 80400000 ALU_PUSH_BEFORE 2, @214, KC0[], KC1[] ; 000000D6 A4080000 JUMP @51 POP:0 ; 00000033 82800000 ALU 2, @217, KC0[], KC1[] ; 000000D9 A0080000 ELSE @96 POP:1 ; 00000060 83400001 ALU 1, @220, KC0[], KC1[] ; 000000DC A0040000 LOOP_START_DX10 @71 ; 00000047 81800000 ALU_PUSH_BEFORE 4, @222, KC0[], KC1[] ; 000000DE A4100000 JUMP @57 POP:0 ; 00000039 82800000 ALU 1, @227, KC0[], KC1[] ; 000000E3 A0040000 ELSE @66 POP:1 ; 00000042 83400001 ALU 1, @229, KC0[CB0:0-32], KC1[] ; 800000E5 A0040000 TEX 0 @112 ; 00000070 80400000 ALU_PUSH_BEFORE 3, @231, KC0[], KC1[] ; 000000E7 A40C0000 JUMP @63 POP:0 ; 0000003F 82800000 ALU 1, @235, KC0[], KC1[] ; 000000EB A0040000 ELSE @65 POP:1 ; 00000041 83400001 ALU_POP_AFTER 2, @237, KC0[], KC1[] ; 000000ED A8080000 POP @66 POP:1 ; 00000042 83800001 ALU_PUSH_BEFORE 4, @240, KC0[], KC1[] ; 000000F0 A4100000 JUMP @70 POP:1 ; 00000046 82800001 LOOP_BREAK @70 ; 00000046 82400000 POP @70 POP:1 ; 00000046 83800001 END_LOOP @54 ; 00000036 81400000 ALU 8, @245, KC0[], KC1[] ; 000000F5 A0200000 LOOP_START_DX10 @90 ; 0000005A 81800000 ALU_PUSH_BEFORE 4, @254, KC0[], KC1[] ; 000000FE A4100000 JUMP @76 POP:0 ; 0000004C 82800000 ALU 1, @259, KC0[], KC1[] ; 00000103 A0040000 ELSE @85 POP:1 ; 00000055 83400001 ALU 1, @261, KC0[CB0:0-32], KC1[] ; 80000105 A0040000 TEX 0 @114 ; 00000072 80400000 ALU_PUSH_BEFORE 3, @263, KC0[], KC1[] ; 00000107 A40C0000 JUMP @82 POP:0 ; 00000052 82800000 ALU 1, @267, KC0[], KC1[] ; 0000010B A0040000 ELSE @84 POP:1 ; 00000054 83400001 ALU_POP_AFTER 3, @269, KC0[], KC1[] ; 0000010D A80C0000 POP @85 POP:1 ; 00000055 83800001 ALU_PUSH_BEFORE 4, @273, KC0[], KC1[] ; 00000111 A4100000 JUMP @89 POP:1 ; 00000059 82800001 LOOP_BREAK @89 ; 00000059 82400000 POP @89 POP:1 ; 00000059 83800001 END_LOOP @73 ; 00000049 81400000 ALU 2, @278, KC0[CB0:0-32], KC1[] ; 80000116 A0080000 TEX 0 @116 ; 00000074 80400000 ALU 8, @281, KC0[CB0:0-32], KC1[] ; 80000119 A0200000 TEX 0 @118 ; 00000076 80400000 ALU_POP_AFTER 14, @290, KC0[], KC1[] ; 00000122 A8380000 TEX 0 @120 ; 00000078 80400000 ALU 1, @305, KC0[], KC1[] ; 00000131 A0040000 EXPORT T2.XYZW ; C0010000 95200688 CF_END ; 00000000 88000000 PAD ; 00000000 00000000 Fetch clause starting at 100: ; TEX_SAMPLE T1.XYZW, T0.XY__ RID:17 SID:1 CT:NNNN ; 00001110 F00D1001 FC808000 00000000 Fetch clause starting at 102: ; TEX_SAMPLE_L T2.XYZW, T2.XYY0 RID:18 SID:2 CT:NNNN ; 00021211 F00D1002 84810000 00000000 Fetch clause starting at 104: ; TEX_SAMPLE_L T3.XYZW, T3.XYY0 RID:18 SID:2 CT:NNNN ; 00031211 F00D1003 84810000 00000000 Fetch clause starting at 106: ; TEX_SAMPLE_L T5.XYZW, T5.XYY0 RID:18 SID:2 CT:NNNN ; 00051211 F00D1005 84810000 00000000 TEX_SAMPLE_L T4.XYZW, T4.XYY0 RID:18 SID:2 CT:NNNN ; 00041211 F00D1004 84810000 00000000 Fetch clause starting at 110: ; TEX_SAMPLE_L T2.XYZW, T2.XYY0 RID:16 SID:0 CT:NNNN ; 00021011 F00D1002 84800000 00000000 Fetch clause starting at 112: ; TEX_SAMPLE_L T1.XYZW, T1.XYY0 RID:18 SID:2 CT:NNNN ; 00011211 F00D1001 84810000 00000000 Fetch clause starting at 114: ; TEX_SAMPLE_L T3.XYZW, T3.XYY0 RID:18 SID:2 CT:NNNN ; 00031211 F00D1003 84810000 00000000 Fetch clause starting at 116: ; TEX_SAMPLE_L T5.XYZW, T4.XYY0 RID:18 SID:2 CT:NNNN ; 00041211 F00D1005 84810000 00000000 Fetch clause starting at 118: ; TEX_SAMPLE_L T0.XYZW, T4.XYY0 RID:18 SID:2 CT:NNNN ; 00041211 F00D1000 84810000 00000000 Fetch clause starting at 120: ; TEX_SAMPLE_L T0.XYZW, T1.XYY0 RID:16 SID:0 CT:NNNN ; 00011011 F00D1000 84800000 00000000 ALU clause starting at 122: ; INTERP_XY T0.X, T0.Y, ARRAY_BASE, ; 00380400 00146B10 INTERP_XY T0.Y, T0.X, ARRAY_BASE, ; 00380000 20146B10 INTERP_XY T0.Z (MASKED), T0.Y, ARRAY_BASE, ; 00380400 40146B00 INTERP_XY * T0.W (MASKED), T0.X, ARRAY_BASE, ; 80380000 60146B00 ALU clause starting at 126: ; SETNE * T2.Y, T1.Y, 0.0, ; 801F0401 20400590 SETNE_DX10 * T3.W, PV.Y, 0.0, ; 801F04FE 60600790 PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002104 ALU clause starting at 129: ; MOV * T2.Y, literal.x, ; 800000FD 20400C90 0(0.000000e+00), 0(0.000000e+00) ; 00000000 00000000 MOV * T2.X, PV.Y, ; 800004FE 00400C90 ALU clause starting at 132: ; MOV * T3.Z, literal.x, ; 800000FD 40600C90 -1077936128(-1.500000e+00), 0(0.000000e+00) ; BFC00000 00000000 ALU clause starting at 134: ; MOV * T3.X, T3.Z, ; 80000803 00600C90 SETGE * T3.W, literal.x, PV.X, ; 801FC0FD 60600510 -1048576000(-1.600000e+01), 0(0.000000e+00) ; C1800000 00000000 SETE_DX10 * T3.W, PV.W, 0.0, ; 801F0CFE 60600610 PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002104 ALU clause starting at 139: ; MOV * T3.W, literal.x, ; 800000FD 60600C90 1(1.401298e-45), 0(0.000000e+00) ; 00000001 00000000 ALU clause starting at 141: ; MULADD_IEEE T2.X, KC0[0].X, T3.X, T0.X, ; 00006080 00430000 MULADD_IEEE * T2.Y, KC0[0].Y, 0.0, T0.Y, ; 801F0480 20430400 ALU clause starting at 143: ; SETGT * T3.W, literal.x, T2.Y, ; 808040FD 60600490 1063675494(9.000000e-01), 0(0.000000e+00) ; 3F666666 00000000 SETE_DX10 * T3.W, PV.W, 0.0, ; 801F0CFE 60600610 PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002104 ALU clause starting at 147: ; MOV * T3.W, literal.x, ; 800000FD 60600C90 1(1.401298e-45), 0(0.000000e+00) ; 00000001 00000000 ALU clause starting at 149: ; ADD T3.Z, T3.X, literal.x, ; 001FA003 40600010 MOV * T3.W, literal.y, ; 800004FD 60600C90 -1073741824(-2.000000e+00), 0(0.000000e+00) ; C0000000 00000000 ALU clause starting at 152: ; LSHL * T3.W, T3.W, literal.x, ; 801FAC03 60600B90 31(4.344025e-44), 0(0.000000e+00) ; 0000001F 00000000 ASHR * T3.W, PV.W, literal.x, ; 801FACFE 60600A90 31(4.344025e-44), 0(0.000000e+00) ; 0000001F 00000000 PRED_SETNE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002284 ALU clause starting at 157: ; ADD * T3.W, T3.X, literal.x, ; 801FA003 60600010 1069547520(1.500000e+00), 0(0.000000e+00) ; 3FC00000 00000000 MULADD_IEEE * T2.W, T2.Y, literal.x, PV.W, ; 801FA402 60430CFE -1073741824(-2.000000e+00), 0(0.000000e+00) ; C0000000 00000000 MOV T2.Z, literal.x, ; 000000FD 40400C90 MAX * T2.W, literal.y, PV.W, ; 819FC4FD 60400190 1069547520(1.500000e+00), -1048576000(-1.600000e+01) ; 3FC00000 C1800000 ALU clause starting at 164: ; MOV * T2.X, T2.Z, ; 80000802 00400C90 SETGE * T3.Y, PV.X, literal.x, ; 801FA0FE 20600510 1098907648(1.600000e+01), 0(0.000000e+00) ; 41800000 00000000 SETE_DX10 * T4.W, PV.Y, 0.0, ; 801F04FE 60800610 PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002104 ALU clause starting at 169: ; MOV * T4.W, literal.x, ; 800000FD 60800C90 1(1.401298e-45), 0(0.000000e+00) ; 00000001 00000000 ALU clause starting at 171: ; MULADD_IEEE T3.X, KC0[0].X, T2.X, T0.X, ; 00004080 00630000 MULADD_IEEE * T3.Y, KC0[0].Y, 0.0, T0.Y, ; 801F0480 20630400 ALU clause starting at 173: ; SETGT * T4.W, literal.x, T3.Y, ; 808060FD 60800490 1063675494(9.000000e-01), 0(0.000000e+00) ; 3F666666 00000000 SETE_DX10 * T4.W, PV.W, 0.0, ; 801F0CFE 60800610 PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002104 ALU clause starting at 177: ; MOV * T4.W, literal.x, ; 800000FD 60800C90 1(1.401298e-45), 0(0.000000e+00) ; 00000001 00000000 ALU clause starting at 179: ; ADD T2.Z, T2.X, literal.x, ; 001FA002 40400010 MOV * T4.W, literal.y, ; 800004FD 60800C90 1073741824(2.000000e+00), 0(0.000000e+00) ; 40000000 00000000 ALU clause starting at 182: ; LSHL * T4.W, T4.W, literal.x, ; 801FAC04 60800B90 31(4.344025e-44), 0(0.000000e+00) ; 0000001F 00000000 ASHR * T4.W, PV.W, literal.x, ; 801FACFE 60800A90 31(4.344025e-44), 0(0.000000e+00) ; 0000001F 00000000 PRED_SETNE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002284 ALU clause starting at 187: ; ADD T2.Z, T3.Y, T3.Y, ; 00806403 40400010 ADD * T3.W, T2.X, literal.x, ; 801FA002 60600010 -1077936128(-1.500000e+00), 0(0.000000e+00) ; BFC00000 00000000 ADD * T3.W, PV.Z, PV.W, ; 819FC8FE 60600010 MIN * T3.W, literal.x, PV.W, ; 819FC0FD 60600210 1098907648(1.600000e+01), 0(0.000000e+00) ; 41800000 00000000 MULADD_IEEE T4.X, T2.W, KC0[0].X, T0.X, ; 00100C02 00830000 ADD * T5.W, PV.W, 1.0, ; 801F2CFE 60A00010 MULADD_IEEE T5.X, PV.W, KC0[0].X, T0.X, ; 00100CFE 00A30000 MULADD_IEEE * T4.Y, KC0[0].Y, literal.x, T0.Y, ; 801FA480 20830400 -1098907648(-2.500000e-01), 0(0.000000e+00) ; BE800000 00000000 MOV * T5.Y, PV.Y, ; 800004FE 20A00C90 ALU clause starting at 199: ; MUL_IEEE * T4.W, T4.X, literal.x, ; 801FA004 60800110 1082130432(4.000000e+00), 0(0.000000e+00) ; 40800000 00000000 RNDNE T2.Y, PV.W, ; 00000CFE 20400990 MOV T2.Z, |T2.W|, ; 00000C02 40400C91 MUL_IEEE * T2.W, T5.X, literal.x, ; 801FA005 60400110 1082130432(4.000000e+00), 0(0.000000e+00) ; 40800000 00000000 RNDNE T3.Y, PV.W, ; 00000CFE 20600990 MOV T3.Z, |T3.W|, ; 00000C03 40600C91 MULADD_IEEE * T2.W, PV.Y, literal.x, PV.Z, ; 801FA4FE 604308FE 1107558400(3.300000e+01), 0(0.000000e+00) ; 42040000 00000000 MUL_IEEE T2.X, PV.W, literal.x, ; 001FACFE 00400110 MULADD_IEEE * T3.W, PV.Y, literal.y, PV.Z, ; 809FA4FE 606308FE 1002950154(6.097560e-03), 1107558400(3.300000e+01) ; 3BC7CE0A 42040000 MUL_IEEE * T2.Y, PV.W, literal.x, ; 801FACFE 20400110 1002950154(6.097560e-03), 0(0.000000e+00) ; 3BC7CE0A 00000000 ALU clause starting at 214: ; SETNE * T3.W, T1.X, 0.0, ; 801F0001 60600590 SETNE_DX10 * T3.W, PV.W, 0.0, ; 801F0CFE 60600790 PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002104 ALU clause starting at 217: ; MOV * T0.Y, literal.x, ; 800000FD 20000C90 0(0.000000e+00), 0(0.000000e+00) ; 00000000 00000000 MOV * T0.X, PV.Y, ; 800004FE 00000C90 ALU clause starting at 220: ; MOV * T3.Z, literal.x, ; 800000FD 40600C90 -1077936128(-1.500000e+00), 0(0.000000e+00) ; BFC00000 00000000 ALU clause starting at 222: ; MOV * T3.X, T3.Z, ; 80000803 00600C90 SETGE * T3.W, literal.x, PV.X, ; 801FC0FD 60600510 -1048576000(-1.600000e+01), 0(0.000000e+00) ; C1800000 00000000 SETE_DX10 * T3.W, PV.W, 0.0, ; 801F0CFE 60600610 PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002104 ALU clause starting at 227: ; MOV * T3.W, literal.x, ; 800000FD 60600C90 1(1.401298e-45), 0(0.000000e+00) ; 00000001 00000000 ALU clause starting at 229: ; MULADD_IEEE T1.X, KC0[0].X, 0.0, T0.X, ; 001F0080 00230000 MULADD_IEEE * T1.Y, KC0[0].Y, T3.X, T0.Y, ; 80006480 20230400 ALU clause starting at 231: ; SETGT * T3.W, literal.x, T1.X, ; 800020FD 60600490 1063675494(9.000000e-01), 0(0.000000e+00) ; 3F666666 00000000 SETE_DX10 * T3.W, PV.W, 0.0, ; 801F0CFE 60600610 PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002104 ALU clause starting at 235: ; MOV * T3.W, literal.x, ; 800000FD 60600C90 1(1.401298e-45), 0(0.000000e+00) ; 00000001 00000000 ALU clause starting at 237: ; ADD T3.Z, T3.X, literal.x, ; 001FA003 40600010 MOV * T3.W, literal.y, ; 800004FD 60600C90 -1073741824(-2.000000e+00), 0(0.000000e+00) ; C0000000 00000000 ALU clause starting at 240: ; LSHL * T3.W, T3.W, literal.x, ; 801FAC03 60600B90 31(4.344025e-44), 0(0.000000e+00) ; 0000001F 00000000 ASHR * T3.W, PV.W, literal.x, ; 801FACFE 60600A90 31(4.344025e-44), 0(0.000000e+00) ; 0000001F 00000000 PRED_SETNE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002284 ALU clause starting at 245: ; ADD * T3.W, T3.X, literal.x, ; 801FA003 60600010 1069547520(1.500000e+00), 0(0.000000e+00) ; 3FC00000 00000000 MULADD_IEEE * T1.W, T1.X, literal.x, PV.W, ; 801FA001 60230CFE -1073741824(-2.000000e+00), 0(0.000000e+00) ; C0000000 00000000 MAX * T1.W, literal.x, PV.W, ; 819FC0FD 60200190 -1048576000(-1.600000e+01), 0(0.000000e+00) ; C1800000 00000000 MOV T3.X, PV.W, ; 00000CFE 00600C90 MOV * T4.W, literal.x, ; 800000FD 60800C90 1069547520(1.500000e+00), 0(0.000000e+00) ; 3FC00000 00000000 ALU clause starting at 254: ; MOV * T1.X, T4.W, ; 80000C04 00200C90 SETGE * T4.W, PV.X, literal.x, ; 801FA0FE 60800510 1098907648(1.600000e+01), 0(0.000000e+00) ; 41800000 00000000 SETE_DX10 * T4.W, PV.W, 0.0, ; 801F0CFE 60800610 PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002104 ALU clause starting at 259: ; MOV * T5.W, literal.x, ; 800000FD 60A00C90 1(1.401298e-45), 0(0.000000e+00) ; 00000001 00000000 ALU clause starting at 261: ; MULADD_IEEE T3.X, KC0[0].X, 0.0, T0.X, ; 001F0080 00630000 MULADD_IEEE * T3.Y, KC0[0].Y, T1.X, T0.Y, ; 80002480 20630400 ALU clause starting at 263: ; SETGT * T4.W, literal.x, T3.X, ; 800060FD 60800490 1063675494(9.000000e-01), 0(0.000000e+00) ; 3F666666 00000000 SETE_DX10 * T4.W, PV.W, 0.0, ; 801F0CFE 60800610 PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002104 ALU clause starting at 267: ; MOV * T5.W, literal.x, ; 800000FD 60A00C90 1(1.401298e-45), 0(0.000000e+00) ; 00000001 00000000 ALU clause starting at 269: ; MOV * T5.W, literal.x, ; 800000FD 60A00C90 0(0.000000e+00), 0(0.000000e+00) ; 00000000 00000000 ADD * T4.W, T1.X, literal.x, ; 801FA001 60800010 1073741824(2.000000e+00), 0(0.000000e+00) ; 40000000 00000000 ALU clause starting at 273: ; LSHL * T5.W, T5.W, literal.x, ; 801FAC05 60A00B90 31(4.344025e-44), 0(0.000000e+00) ; 0000001F 00000000 ASHR * T5.W, PV.W, literal.x, ; 801FACFE 60A00A90 31(4.344025e-44), 0(0.000000e+00) ; 0000001F 00000000 PRED_SETNE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002284 ALU clause starting at 278: ; MULADD_IEEE T4.X, KC0[0].X, literal.x, T0.X, ; 001FA080 00830000 MULADD_IEEE * T4.Y, T1.W, KC0[0].Y, T0.Y, ; 80900C01 20830400 -1098907648(-2.500000e-01), 0(0.000000e+00) ; BE800000 00000000 ALU clause starting at 281: ; ADD T1.Z, T3.X, T3.X, ; 00006003 40200010 ADD * T3.W, T1.X, literal.x, BS:VEC_120/SCL_212 ; 801FA001 60680010 -1077936128(-1.500000e+00), 0(0.000000e+00) ; BFC00000 00000000 ADD * T3.W, PV.Z, PV.W, ; 819FC8FE 60600010 MIN * T3.W, literal.x, PV.W, ; 819FC0FD 60600210 1098907648(1.600000e+01), 0(0.000000e+00) ; 41800000 00000000 ADD * T6.W, PV.W, 1.0, ; 801F2CFE 60C00010 MULADD_IEEE * T0.W, PV.W, KC0[0].Y, T0.Y, ; 80900CFE 60030400 MOV * T4.Y, PV.W, ; 80000CFE 20800C90 ALU clause starting at 290: ; MUL_IEEE * T4.W, T5.Y, literal.x, ; 801FA405 60800110 1082130432(4.000000e+00), 0(0.000000e+00) ; 40800000 00000000 RNDNE T1.Y, PV.W, ; 00000CFE 20200990 MOV T1.Z, |T1.W|, ; 00000C01 40200C91 MUL_IEEE * T0.W, T0.Y, literal.x, ; 801FA400 60000110 1082130432(4.000000e+00), 0(0.000000e+00) ; 40800000 00000000 RNDNE T0.Y, PV.W, ; 00000CFE 20000990 MOV T0.Z, |T3.W|, ; 00000C03 40000C91 MULADD_IEEE * T0.W, PV.Y, literal.x, PV.Z, ; 801FA4FE 600308FE 1107558400(3.300000e+01), 0(0.000000e+00) ; 42040000 00000000 MUL_IEEE T1.X, PV.W, literal.x, ; 001FACFE 00200110 MULADD_IEEE * T0.W, PV.Y, literal.y, PV.Z, ; 809FA4FE 600308FE 1002950154(6.097560e-03), 1107558400(3.300000e+01) ; 3BC7CE0A 42040000 MUL_IEEE * T1.Y, PV.W, literal.x, ; 801FACFE 20200110 1002950154(6.097560e-03), 0(0.000000e+00) ; 3BC7CE0A 00000000 ALU clause starting at 305: ; MOV T2.Z, T0.X, ; 00000000 40400C90 MOV * T2.W, T0.Y, ; 80000400 60400C90 ===== SHADER #53 ======================================== PS/CAYMAN/CAYMAN ===== ===== 614 dw ===== 7 gprs ===== 3 stack ======================================== 0000 0000007a a00c0000 ALU 4 @244 0244 00380400 00146b10 1 x: INTERP_XY R0.x, R0.y, Param0.x VEC_210 0246 00380000 20146b10 y: INTERP_XY R0.y, R0.x, Param0.x VEC_210 0248 00380400 40146b00 z: INTERP_XY __.z, R0.y, Param0.x VEC_210 0250 80380000 60146b00 w: INTERP_XY __.w, R0.x, Param0.x VEC_210 0002 00000064 80400000 TEX 1 @200 0200 00001110 f00d1001 fc808000 SAMPLE R1.xyzw, R0.xy__, RID:17, SID:1 CT:NNNN 0004 0000007e a4080000 ALU_PUSH_BEFORE 3 @252 0252 801f0401 20400590 2 y: SETNE R2.y, R1.y, 0 0254 801f04fe 60600790 3 w: SETNE_DX10 R3.w, PV.y, 0 0256 801f0cfe 00002104 4 M x: PRED_SETE_INT __.x, PV.w, 0 0006 00000005 82800000 JUMP @10 0008 00000081 a0080000 ALU 3 @258 0258 800000fd 20400c90 5 y: MOV R2.y, [0x00000000 0].x 0260 00000000 0262 800004fe 00400c90 6 x: MOV R2.x, PV.y 0010 00000030 83400001 ELSE @96 POP:1 0012 00000084 a0040000 ALU 2 @264 0264 800000fd 40600c90 7 z: MOV R3.z, [0xbfc00000 -1.5].x 0266 bfc00000 0014 00000019 81800000 LOOP_START_DX10 @50 0016 00000086 a4100000 ALU_PUSH_BEFORE 5 @268 0268 80000803 00600c90 8 x: MOV R3.x, R3.z 0270 801fc0fd 60600510 9 w: SETGE R3.w, [0xc1800000 -16].x, PV.x 0272 c1800000 0274 801f0cfe 60600610 10 w: SETE_DX10 R3.w, PV.w, 0 0276 801f0cfe 00002104 11 M x: PRED_SETE_INT __.x, PV.w, 0 0018 0000000b 82800000 JUMP @22 0020 0000008b a0040000 ALU 2 @278 0278 800000fd 60600c90 12 w: MOV R3.w, [0x00000001 1.4013e-45].x 0280 00000001 0022 00000014 83400001 ELSE @40 POP:1 0024 8000008d a0040000 ALU 2 @282 KC0[CB0:0-31] 0282 00006080 00430000 13 x: MULADD_IEEE R2.x, KC0[0].x, R3.x, R0.x 0284 801f0480 20430400 y: MULADD_IEEE R2.y, KC0[0].y, 0, R0.y 0026 00000066 80400000 TEX 1 @204 0204 00021211 f00d1002 84810000 SAMPLE_L R2.xyzw, R2.xyy0, RID:18, SID:2 CT:NNNN 0028 0000008f a40c0000 ALU_PUSH_BEFORE 4 @286 0286 808040fd 60600490 14 w: SETGT R3.w, [0x3f666666 0.9].x, R2.y 0288 3f666666 0290 801f0cfe 60600610 15 w: SETE_DX10 R3.w, PV.w, 0 0292 801f0cfe 00002104 16 M x: PRED_SETE_INT __.x, PV.w, 0 0030 00000011 82800000 JUMP @34 0032 00000093 a0040000 ALU 2 @294 0294 800000fd 60600c90 17 w: MOV R3.w, [0x00000001 1.4013e-45].x 0296 00000001 0034 00000013 83400001 ELSE @38 POP:1 0036 00000095 a8080000 ALU_POP_AFTER 3 @298 0298 001fa003 40600010 18 z: ADD R3.z, R3.x, [0xc0000000 -2].x 0300 800004fd 60600c90 w: MOV R3.w, [0x00000000 0].y 0302 c0000000 0303 00000000 0038 00000014 83800001 POP @40 POP:1 0040 00000098 a4100000 ALU_PUSH_BEFORE 5 @304 0304 801fac03 60600b90 19 w: LSHL_INT R3.w, R3.w, [0x0000001f 4.34403e-44].x 0306 0000001f 0308 801facfe 60600a90 20 w: ASHR_INT R3.w, PV.w, [0x0000001f 4.34403e-44].x 0310 0000001f 0312 801f0cfe 00002284 21 M x: PRED_SETNE_INT __.x, PV.w, 0 0042 00000018 82800001 JUMP @48 POP:1 0044 00000018 82400000 LOOP_BREAK @48 0046 00000018 83800001 POP @48 POP:1 0048 00000008 81400000 LOOP_END @16 0050 0000009d a0180000 ALU 7 @314 0314 801fa003 60600010 22 w: ADD R3.w, R3.x, [0x3fc00000 1.5].x 0316 3fc00000 0318 801fa402 60430cfe 23 w: MULADD_IEEE R2.w, R2.y, [0xc0000000 -2].x, PV.w 0320 c0000000 0322 000000fd 40400c90 24 z: MOV R2.z, [0x3fc00000 1.5].x 0324 819fc4fd 60400190 w: MAX R2.w, [0xc1800000 -16].y, PV.w 0326 3fc00000 0327 c1800000 0052 0000002c 81800000 LOOP_START_DX10 @88 0054 000000a4 a4100000 ALU_PUSH_BEFORE 5 @328 0328 80000802 00400c90 25 x: MOV R2.x, R2.z 0330 801fa0fe 20600510 26 y: SETGE R3.y, PV.x, [0x41800000 16].x 0332 41800000 0334 801f04fe 60800610 27 w: SETE_DX10 R4.w, PV.y, 0 0336 801f0cfe 00002104 28 M x: PRED_SETE_INT __.x, PV.w, 0 0056 0000001e 82800000 JUMP @60 0058 000000a9 a0040000 ALU 2 @338 0338 800000fd 60800c90 29 w: MOV R4.w, [0x00000001 1.4013e-45].x 0340 00000001 0060 00000027 83400001 ELSE @78 POP:1 0062 800000ab a0040000 ALU 2 @342 KC0[CB0:0-31] 0342 00004080 00630000 30 x: MULADD_IEEE R3.x, KC0[0].x, R2.x, R0.x 0344 801f0480 20630400 y: MULADD_IEEE R3.y, KC0[0].y, 0, R0.y 0064 00000068 80400000 TEX 1 @208 0208 00031211 f00d1003 84810000 SAMPLE_L R3.xyzw, R3.xyy0, RID:18, SID:2 CT:NNNN 0066 000000ad a40c0000 ALU_PUSH_BEFORE 4 @346 0346 808060fd 60800490 31 w: SETGT R4.w, [0x3f666666 0.9].x, R3.y 0348 3f666666 0350 801f0cfe 60800610 32 w: SETE_DX10 R4.w, PV.w, 0 0352 801f0cfe 00002104 33 M x: PRED_SETE_INT __.x, PV.w, 0 0068 00000024 82800000 JUMP @72 0070 000000b1 a0040000 ALU 2 @354 0354 800000fd 60800c90 34 w: MOV R4.w, [0x00000001 1.4013e-45].x 0356 00000001 0072 00000026 83400001 ELSE @76 POP:1 0074 000000b3 a8080000 ALU_POP_AFTER 3 @358 0358 001fa002 40400010 35 z: ADD R2.z, R2.x, [0x40000000 2].x 0360 800004fd 60800c90 w: MOV R4.w, [0x00000000 0].y 0362 40000000 0363 00000000 0076 00000027 83800001 POP @78 POP:1 0078 000000b6 a4100000 ALU_PUSH_BEFORE 5 @364 0364 801fac04 60800b90 36 w: LSHL_INT R4.w, R4.w, [0x0000001f 4.34403e-44].x 0366 0000001f 0368 801facfe 60800a90 37 w: ASHR_INT R4.w, PV.w, [0x0000001f 4.34403e-44].x 0370 0000001f 0372 801f0cfe 00002284 38 M x: PRED_SETNE_INT __.x, PV.w, 0 0080 0000002b 82800001 JUMP @86 POP:1 0082 0000002b 82400000 LOOP_BREAK @86 0084 0000002b 83800001 POP @86 POP:1 0086 0000001b 81400000 LOOP_END @54 0088 800000bb a02c0000 ALU 12 @374 KC0[CB0:0-31] 0374 00806403 40400010 39 z: ADD R2.z, R3.y, R3.y 0376 801fa002 60600010 w: ADD R3.w, R2.x, [0xbfc00000 -1.5].x 0378 bfc00000 0380 819fc8fe 60600010 40 w: ADD R3.w, PV.z, PV.w 0382 819fc0fd 60600210 41 w: MIN R3.w, [0x41800000 16].x, PV.w 0384 41800000 0386 00100c02 00830000 42 x: MULADD_IEEE R4.x, R2.w, KC0[0].x, R0.x 0388 801f2cfe 60a00010 w: ADD R5.w, PV.w, 1.0 0390 00100cfe 00a30000 43 x: MULADD_IEEE R5.x, PV.w, KC0[0].x, R0.x 0392 801fa480 20830400 y: MULADD_IEEE R4.y, KC0[0].y, [0xbe800000 -0.25].x, R0.y 0394 be800000 0396 800004fe 20a00c90 44 y: MOV R5.y, PV.y 0090 0000006a 80400400 TEX 2 @212 0212 00051211 f00d1005 84810000 SAMPLE_L R5.xyzw, R5.xyy0, RID:18, SID:2 CT:NNNN 0216 00041211 f00d1004 84810000 SAMPLE_L R4.xyzw, R4.xyy0, RID:18, SID:2 CT:NNNN 0092 000000c7 a8380000 ALU_POP_AFTER 15 @398 0398 801fa004 60800110 45 w: MUL_IEEE R4.w, R4.x, [0x40800000 4].x 0400 40800000 0402 00000cfe 20400990 46 y: RNDNE R2.y, PV.w 0404 00000c02 40400c91 z: MOV R2.z, |R2.w| 0406 801fa005 60400110 w: MUL_IEEE R2.w, R5.x, [0x40800000 4].x 0408 40800000 0410 00000cfe 20600990 47 y: RNDNE R3.y, PV.w 0412 00000c03 40600c91 z: MOV R3.z, |R3.w| 0414 801fa4fe 604308fe w: MULADD_IEEE R2.w, PV.y, [0x42040000 33].x, PV.z 0416 42040000 0418 001facfe 00400110 48 x: MUL_IEEE R2.x, PV.w, [0x3bc7ce0a 0.00609756].x 0420 809fa4fe 606308fe w: MULADD_IEEE R3.w, PV.y, [0x42040000 33].y, PV.z 0422 3bc7ce0a 0423 42040000 0424 801facfe 20400110 49 y: MUL_IEEE R2.y, PV.w, [0x3bc7ce0a 0.00609756].x 0426 3bc7ce0a 0094 0000006e 80400000 TEX 1 @220 0220 00021011 f00d1002 84800000 SAMPLE_L R2.xyzw, R2.xyy0, RID:16, SID:0 CT:NNNN 0096 000000d6 a4080000 ALU_PUSH_BEFORE 3 @428 0428 801f0001 60600590 50 w: SETNE R3.w, R1.x, 0 0430 801f0cfe 60600790 51 w: SETNE_DX10 R3.w, PV.w, 0 0432 801f0cfe 00002104 52 M x: PRED_SETE_INT __.x, PV.w, 0 0098 00000033 82800000 JUMP @102 0100 000000d9 a0080000 ALU 3 @434 0434 800000fd 20000c90 53 y: MOV R0.y, [0x00000000 0].x 0436 00000000 0438 800004fe 00000c90 54 x: MOV R0.x, PV.y 0102 00000060 83400001 ELSE @192 POP:1 0104 000000dc a0040000 ALU 2 @440 0440 800000fd 40600c90 55 z: MOV R3.z, [0xbfc00000 -1.5].x 0442 bfc00000 0106 00000047 81800000 LOOP_START_DX10 @142 0108 000000de a4100000 ALU_PUSH_BEFORE 5 @444 0444 80000803 00600c90 56 x: MOV R3.x, R3.z 0446 801fc0fd 60600510 57 w: SETGE R3.w, [0xc1800000 -16].x, PV.x 0448 c1800000 0450 801f0cfe 60600610 58 w: SETE_DX10 R3.w, PV.w, 0 0452 801f0cfe 00002104 59 M x: PRED_SETE_INT __.x, PV.w, 0 0110 00000039 82800000 JUMP @114 0112 000000e3 a0040000 ALU 2 @454 0454 800000fd 60600c90 60 w: MOV R3.w, [0x00000001 1.4013e-45].x 0456 00000001 0114 00000042 83400001 ELSE @132 POP:1 0116 800000e5 a0040000 ALU 2 @458 KC0[CB0:0-31] 0458 001f0080 00230000 61 x: MULADD_IEEE R1.x, KC0[0].x, 0, R0.x 0460 80006480 20230400 y: MULADD_IEEE R1.y, KC0[0].y, R3.x, R0.y 0118 00000070 80400000 TEX 1 @224 0224 00011211 f00d1001 84810000 SAMPLE_L R1.xyzw, R1.xyy0, RID:18, SID:2 CT:NNNN 0120 000000e7 a40c0000 ALU_PUSH_BEFORE 4 @462 0462 800020fd 60600490 62 w: SETGT R3.w, [0x3f666666 0.9].x, R1.x 0464 3f666666 0466 801f0cfe 60600610 63 w: SETE_DX10 R3.w, PV.w, 0 0468 801f0cfe 00002104 64 M x: PRED_SETE_INT __.x, PV.w, 0 0122 0000003f 82800000 JUMP @126 0124 000000eb a0040000 ALU 2 @470 0470 800000fd 60600c90 65 w: MOV R3.w, [0x00000001 1.4013e-45].x 0472 00000001 0126 00000041 83400001 ELSE @130 POP:1 0128 000000ed a8080000 ALU_POP_AFTER 3 @474 0474 001fa003 40600010 66 z: ADD R3.z, R3.x, [0xc0000000 -2].x 0476 800004fd 60600c90 w: MOV R3.w, [0x00000000 0].y 0478 c0000000 0479 00000000 0130 00000042 83800001 POP @132 POP:1 0132 000000f0 a4100000 ALU_PUSH_BEFORE 5 @480 0480 801fac03 60600b90 67 w: LSHL_INT R3.w, R3.w, [0x0000001f 4.34403e-44].x 0482 0000001f 0484 801facfe 60600a90 68 w: ASHR_INT R3.w, PV.w, [0x0000001f 4.34403e-44].x 0486 0000001f 0488 801f0cfe 00002284 69 M x: PRED_SETNE_INT __.x, PV.w, 0 0134 00000046 82800001 JUMP @140 POP:1 0136 00000046 82400000 LOOP_BREAK @140 0138 00000046 83800001 POP @140 POP:1 0140 00000036 81400000 LOOP_END @108 0142 000000f5 a0200000 ALU 9 @490 0490 801fa003 60600010 70 w: ADD R3.w, R3.x, [0x3fc00000 1.5].x 0492 3fc00000 0494 801fa001 60230cfe 71 w: MULADD_IEEE R1.w, R1.x, [0xc0000000 -2].x, PV.w 0496 c0000000 0498 819fc0fd 60200190 72 w: MAX R1.w, [0xc1800000 -16].x, PV.w 0500 c1800000 0502 00000cfe 00600c90 73 x: MOV R3.x, PV.w 0504 800000fd 60800c90 w: MOV R4.w, [0x3fc00000 1.5].x 0506 3fc00000 0144 0000005a 81800000 LOOP_START_DX10 @180 0146 000000fe a4100000 ALU_PUSH_BEFORE 5 @508 0508 80000c04 00200c90 74 x: MOV R1.x, R4.w 0510 801fa0fe 60800510 75 w: SETGE R4.w, PV.x, [0x41800000 16].x 0512 41800000 0514 801f0cfe 60800610 76 w: SETE_DX10 R4.w, PV.w, 0 0516 801f0cfe 00002104 77 M x: PRED_SETE_INT __.x, PV.w, 0 0148 0000004c 82800000 JUMP @152 0150 00000103 a0040000 ALU 2 @518 0518 800000fd 60a00c90 78 w: MOV R5.w, [0x00000001 1.4013e-45].x 0520 00000001 0152 00000055 83400001 ELSE @170 POP:1 0154 80000105 a0040000 ALU 2 @522 KC0[CB0:0-31] 0522 001f0080 00630000 79 x: MULADD_IEEE R3.x, KC0[0].x, 0, R0.x 0524 80002480 20630400 y: MULADD_IEEE R3.y, KC0[0].y, R1.x, R0.y 0156 00000072 80400000 TEX 1 @228 0228 00031211 f00d1003 84810000 SAMPLE_L R3.xyzw, R3.xyy0, RID:18, SID:2 CT:NNNN 0158 00000107 a40c0000 ALU_PUSH_BEFORE 4 @526 0526 800060fd 60800490 80 w: SETGT R4.w, [0x3f666666 0.9].x, R3.x 0528 3f666666 0530 801f0cfe 60800610 81 w: SETE_DX10 R4.w, PV.w, 0 0532 801f0cfe 00002104 82 M x: PRED_SETE_INT __.x, PV.w, 0 0160 00000052 82800000 JUMP @164 0162 0000010b a0040000 ALU 2 @534 0534 800000fd 60a00c90 83 w: MOV R5.w, [0x00000001 1.4013e-45].x 0536 00000001 0164 00000054 83400001 ELSE @168 POP:1 0166 0000010d a80c0000 ALU_POP_AFTER 4 @538 0538 800000fd 60a00c90 84 w: MOV R5.w, [0x00000000 0].x 0540 00000000 0542 801fa001 60800010 85 w: ADD R4.w, R1.x, [0x40000000 2].x 0544 40000000 0168 00000055 83800001 POP @170 POP:1 0170 00000111 a4100000 ALU_PUSH_BEFORE 5 @546 0546 801fac05 60a00b90 86 w: LSHL_INT R5.w, R5.w, [0x0000001f 4.34403e-44].x 0548 0000001f 0550 801facfe 60a00a90 87 w: ASHR_INT R5.w, PV.w, [0x0000001f 4.34403e-44].x 0552 0000001f 0554 801f0cfe 00002284 88 M x: PRED_SETNE_INT __.x, PV.w, 0 0172 00000059 82800001 JUMP @178 POP:1 0174 00000059 82400000 LOOP_BREAK @178 0176 00000059 83800001 POP @178 POP:1 0178 00000049 81400000 LOOP_END @146 0180 80000116 a0080000 ALU 3 @556 KC0[CB0:0-31] 0556 001fa080 00830000 89 x: MULADD_IEEE R4.x, KC0[0].x, [0xbe800000 -0.25].x, R0.x 0558 80900c01 20830400 y: MULADD_IEEE R4.y, R1.w, KC0[0].y, R0.y 0560 be800000 0182 00000074 80400000 TEX 1 @232 0232 00041211 f00d1005 84810000 SAMPLE_L R5.xyzw, R4.xyy0, RID:18, SID:2 CT:NNNN 0184 80000119 a0200000 ALU 9 @562 KC0[CB0:0-31] 0562 00006003 40200010 90 z: ADD R1.z, R3.x, R3.x 0564 801fa001 60680010 w: ADD R3.w, R1.x, [0xbfc00000 -1.5].x VEC_120 0566 bfc00000 0568 819fc8fe 60600010 91 w: ADD R3.w, PV.z, PV.w 0570 819fc0fd 60600210 92 w: MIN R3.w, [0x41800000 16].x, PV.w 0572 41800000 0574 801f2cfe 60c00010 93 w: ADD R6.w, PV.w, 1.0 0576 80900cfe 60030400 94 w: MULADD_IEEE R0.w, PV.w, KC0[0].y, R0.y 0578 80000cfe 20800c90 95 y: MOV R4.y, PV.w 0186 00000076 80400000 TEX 1 @236 0236 00041211 f00d1000 84810000 SAMPLE_L R0.xyzw, R4.xyy0, RID:18, SID:2 CT:NNNN 0188 00000122 a8380000 ALU_POP_AFTER 15 @580 0580 801fa405 60800110 96 w: MUL_IEEE R4.w, R5.y, [0x40800000 4].x 0582 40800000 0584 00000cfe 20200990 97 y: RNDNE R1.y, PV.w 0586 00000c01 40200c91 z: MOV R1.z, |R1.w| 0588 801fa400 60000110 w: MUL_IEEE R0.w, R0.y, [0x40800000 4].x 0590 40800000 0592 00000cfe 20000990 98 y: RNDNE R0.y, PV.w 0594 00000c03 40000c91 z: MOV R0.z, |R3.w| 0596 801fa4fe 600308fe w: MULADD_IEEE R0.w, PV.y, [0x42040000 33].x, PV.z 0598 42040000 0600 001facfe 00200110 99 x: MUL_IEEE R1.x, PV.w, [0x3bc7ce0a 0.00609756].x 0602 809fa4fe 600308fe w: MULADD_IEEE R0.w, PV.y, [0x42040000 33].y, PV.z 0604 3bc7ce0a 0605 42040000 0606 801facfe 20200110 100 y: MUL_IEEE R1.y, PV.w, [0x3bc7ce0a 0.00609756].x 0608 3bc7ce0a 0190 00000078 80400000 TEX 1 @240 0240 00011011 f00d1000 84800000 SAMPLE_L R0.xyzw, R1.xyy0, RID:16, SID:0 CT:NNNN 0192 00000131 a0040000 ALU 2 @610 0610 00000000 40400c90 101 z: MOV R2.z, R0.x 0612 80000400 60400c90 w: MOV R2.w, R0.y 0194 c0010000 95200688 EXPORT_DONE PIXEL 0 R2.xyzw 0196 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #53 OPT ==================================== PS/CAYMAN/CAYMAN ===== ===== 520 dw ===== 6 gprs ===== 2 stack ======================================== 0000 00000052 a00c0000 ALU 4 @164 0164 00380400 00946b10 1 x: INTERP_XY R4.x, R0.y, Param0.x VEC_210 0166 00b80000 20946b10 y: INTERP_XY R4.y, R0.x, Param0.y VEC_210 0168 01380400 40146b00 z: INTERP_XY __.z, R0.y, Param0.z VEC_210 0170 81b80000 60146b00 w: INTERP_XY __.w, R0.x, Param0.w VEC_210 0002 00000056 80400000 TEX 1 @172 0172 00041110 f00d1001 fc808000 SAMPLE R1.xyzw, R4.xy__, RID:17, SID:1 CT:NNNN 0004 00000058 a4000000 ALU_PUSH_BEFORE 1 @176 0176 801f0401 00001004 2 M x: PRED_SETE __.x, R1.y, 0 0006 00000005 82800000 JUMP @10 0008 00000059 a0040000 ALU 2 @178 0178 000000f8 00400c90 3 x: MOV R2.x, 0 0180 800000f8 20400c90 y: MOV R2.y, 0 0010 00000029 83400001 ELSE @82 POP:1 0012 4000005b a00c0000 ALU 4 @182 KC0[CB0:0-15] 0182 801f0401 20400590 4 y: SETNE R2.y, R1.y, 0 0184 000000fd 00000c90 5 x: MOV R0.x, [0xbfc00000 -1.5].x 0186 801f0480 20630404 y: MULADD_IEEE R3.y, KC0[0].y, 0, R4.y 0188 bfc00000 0014 00000015 81800000 LOOP_START_DX10 @42 0016 0000005f a4040000 ALU_PUSH_BEFORE 2 @190 0190 800000fd 00001104 6 M x: PRED_SETGE __.x, [0xc1800000 -16].x, R0.x 0192 c1800000 0018 0000000b 82800000 JUMP @22 0020 00000061 a0040000 ALU 2 @194 0194 000000fa 20000c90 7 y: MOV R0.y, 1 0196 80000000 40000c90 z: MOV R0.z, R0.x 0022 0000000f 83400001 ELSE @30 POP:1 0024 40000063 a0000000 ALU 1 @198 KC0[CB0:0-15] 0198 80000080 00630004 8 x: MULADD_IEEE R3.x, KC0[0].x, R0.x, R4.x 0026 00000064 80400000 TEX 1 @200 0200 00031211 f00d1002 84810000 SAMPLE_L R2.xyzw, R3.xyy0, RID:18, SID:2 CT:NNNN 0028 00000066 a8100000 ALU_POP_AFTER 5 @204 0204 001fa402 2f800710 9 y: SETGE_DX10 T0.y, R2.y, [0x3f666666 0.9].x 0206 809fa000 4f800010 z: ADD T0.z, R0.x, [0xc0000000 -2].y 0208 3f666666 0209 c0000000 0210 001f447c 200380f8 10 y: CNDE_INT R0.y, T0.y, 1, 0 0212 8000047c 4003887c z: CNDE_INT R0.z, T0.y, R0.x, T0.z 0030 0000006b a4100000 ALU_PUSH_BEFORE 5 @214 0214 801fa400 6f800b90 11 w: LSHL_INT T0.w, R0.y, [0x0000001f 4.34403e-44].x 0216 0000001f 0218 801fac7c 0f800a90 12 x: ASHR_INT T0.x, T0.w, [0x0000001f 4.34403e-44].x 0220 0000001f 0222 801f007c 00002284 13 M x: PRED_SETNE_INT __.x, T0.x, 0 0032 00000013 82800001 JUMP @38 POP:1 0034 00000014 82400000 LOOP_BREAK @40 0036 00000013 83800001 POP @38 POP:1 0038 00000070 a0000000 ALU 1 @224 0224 80000800 00000c90 14 x: MOV R0.x, R0.z 0040 00000008 81400000 LOOP_END @16 0042 00000071 a0100000 ALU 5 @226 0226 801fa000 20a00010 15 y: ADD R5.y, R0.x, [0x3fc00000 1.5].x 0228 3fc00000 0230 000000fd 00400c90 16 x: MOV R2.x, [0x3fc00000 1.5].x 0232 80000405 60000c90 w: MOV R0.w, R5.y 0234 3fc00000 0044 00000024 81800000 LOOP_START_DX10 @72 0046 00000076 a4040000 ALU_PUSH_BEFORE 2 @236 0236 801fa002 00001104 17 M x: PRED_SETGE __.x, R2.x, [0x41800000 16].x 0238 41800000 0048 0000001a 82800000 JUMP @52 0050 00000078 a00c0000 ALU 4 @240 0240 001fa002 20000510 18 y: SETGE R0.y, R2.x, [0x41800000 16].x 0242 000000fa 40400c90 z: MOV R2.z, 1 0244 80000002 60400c90 w: MOV R2.w, R2.x 0246 41800000 0052 0000001e 83400001 ELSE @60 POP:1 0054 4000007c a0000000 ALU 1 @248 KC0[CB0:0-15] 0248 80004080 00630004 19 x: MULADD_IEEE R3.x, KC0[0].x, R2.x, R4.x 0056 0000007e 80400000 TEX 1 @252 0252 00031211 f00d1000 84810000 SAMPLE_L R0.xyzw, R3.xyy0, RID:18, SID:2 CT:NNNN 0058 00000080 a8100000 ALU_POP_AFTER 5 @256 0256 001fa400 4f800710 20 z: SETGE_DX10 T0.z, R0.y, [0x3f666666 0.9].x 0258 809fa002 6f800010 w: ADD T0.w, R2.x, [0x40000000 2].y 0260 3f666666 0261 40000000 0262 001f487c 404380f8 21 z: CNDE_INT R2.z, T0.z, 1, 0 0264 8000487c 60438c7c w: CNDE_INT R2.w, T0.z, R2.x, T0.w 0060 00000085 a4100000 ALU_PUSH_BEFORE 5 @266 0266 801fa802 0f800b90 22 x: LSHL_INT T0.x, R2.z, [0x0000001f 4.34403e-44].x 0268 0000001f 0270 801fa07c 2f800a90 23 y: ASHR_INT T0.y, T0.x, [0x0000001f 4.34403e-44].x 0272 0000001f 0274 801f047c 00002284 24 M x: PRED_SETNE_INT __.x, T0.y, 0 0062 00000022 82800001 JUMP @68 POP:1 0064 00000023 82400000 LOOP_BREAK @70 0066 00000022 83800001 POP @68 POP:1 0068 0000008a a0000000 ALU 1 @276 0276 80000c02 00400c90 25 x: MOV R2.x, R2.w 0070 00000017 81400000 LOOP_END @46 0072 4000008b a0340000 ALU 14 @278 KC0[CB0:0-15] 0278 801fa002 4f800010 26 z: ADD T0.z, R2.x, [0xbfc00000 -1.5].x 0280 bfc00000 0282 801fa400 6f82887c 27 w: MULADD T0.w, R0.y, [0x40000000 2].x, T0.z 0284 40000000 0286 001fa402 0f830405 28 x: MULADD_IEEE T0.x, R2.y, [0xc0000000 -2].x, R5.y 0288 809fac7c 20400210 y: MIN R2.y, T0.w, [0x41800000 16].y 0290 c0000000 0291 41800000 0292 001fa07c 40400190 29 z: MAX R2.z, T0.x, [0xc1800000 -16].x 0294 801f2402 6f800010 w: ADD T0.w, R2.y, 1.0 0296 c1800000 0298 00100802 00030004 30 x: MULADD_IEEE R0.x, R2.z, KC0[0].x, R4.x 0300 001fa480 20030404 y: MULADD_IEEE R0.y, KC0[0].y, [0xbe800000 -0.25].x, R4.y 0302 80100c7c 40030004 z: MULADD_IEEE R0.z, T0.w, KC0[0].x, R4.x 0304 be800000 0074 0000009a 80400400 TEX 2 @308 0308 00001211 f01c7e00 84a10000 SAMPLE_L R0.__x_, R0.zyy0, RID:18, SID:2 CT:NNNN 0312 00001211 f01ff000 84810000 SAMPLE_L R0.x___, R0.xyy0, RID:18, SID:2 CT:NNNN 0076 0000009e a0300000 ALU 13 @316 0316 001fa800 0f800110 31 x: MUL_IEEE T0.x, R0.z, [0x40800000 4].x 0318 801fa000 2f800110 y: MUL_IEEE T0.y, R0.x, [0x40800000 4].x 0320 40800000 0322 00000802 0f800c91 32 x: MOV T0.x, |R2.z| 0324 0000007c 20000990 y: RNDNE R0.y, T0.x 0326 00000402 4f800c91 z: MOV T0.z, |R2.y| 0328 8000047c 6f880990 w: RNDNE T0.w, T0.y VEC_120 0330 001fa400 2f83087c 33 y: MULADD_IEEE T0.y, R0.y, [0x42040000 33].x, T0.z 0332 801fac7c 4f83007c z: MULADD_IEEE T0.z, T0.w, [0x42040000 33].x, T0.x 0334 42040000 0336 001fa87c 00000110 34 x: MUL_IEEE R0.x, T0.z, [0x3bc7ce0a 0.00609756].x 0338 801fa47c 40000110 z: MUL_IEEE R0.z, T0.y, [0x3bc7ce0a 0.00609756].x 0340 3bc7ce0a 0078 000000ac 80400000 TEX 1 @344 0344 00001011 f01f9002 89000000 SAMPLE_L R2.xy__, R0.xzz0, RID:16, SID:0 CT:NNNN 0080 00000029 83800001 POP @82 POP:1 0082 000000ae a4000000 ALU_PUSH_BEFORE 1 @348 0348 801f0001 00001004 35 M x: PRED_SETE __.x, R1.x, 0 0084 0000002c 82800000 JUMP @88 0086 000000af a0040000 ALU 2 @350 0350 000000f8 40400c90 36 z: MOV R2.z, 0 0352 800000f8 60400c90 w: MOV R2.w, 0 0088 00000050 83400001 ELSE @160 POP:1 0090 400000b1 a0080000 ALU 3 @354 KC0[CB0:0-15] 0354 000000fd 00000c90 37 x: MOV R0.x, [0xbfc00000 -1.5].x 0356 801f0080 40430004 z: MULADD_IEEE R2.z, KC0[0].x, 0, R4.x 0358 bfc00000 0092 0000003c 81800000 LOOP_START_DX10 @120 0094 000000b4 a4040000 ALU_PUSH_BEFORE 2 @360 0360 800000fd 00001104 38 M x: PRED_SETGE __.x, [0xc1800000 -16].x, R0.x 0362 c1800000 0096 00000032 82800000 JUMP @100 0098 000000b6 a0040000 ALU 2 @364 0364 00000000 40000c90 39 z: MOV R0.z, R0.x 0366 800000fa 60000c90 w: MOV R0.w, 1 0100 00000036 83400001 ELSE @108 POP:1 0102 400000b8 a0000000 ALU 1 @368 KC0[CB0:0-15] 0368 80000480 60430404 40 w: MULADD_IEEE R2.w, KC0[0].y, R0.x, R4.y 0104 000000ba 80400000 TEX 1 @372 0372 00021211 f00d1001 8da10000 SAMPLE_L R1.xyzw, R2.zww0, RID:18, SID:2 CT:NNNN 0106 000000bc a8100000 ALU_POP_AFTER 5 @376 0376 001fa000 0f800010 41 x: ADD T0.x, R0.x, [0xc0000000 -2].x 0378 809fa001 6f880710 w: SETGE_DX10 T0.w, R1.x, [0x3f666666 0.9].y VEC_120 0380 c0000000 0381 3f666666 0382 00000c7c 4003807c 42 z: CNDE_INT R0.z, T0.w, R0.x, T0.x 0384 801f4c7c 600380f8 w: CNDE_INT R0.w, T0.w, 1, 0 0108 000000c1 a4100000 ALU_PUSH_BEFORE 5 @386 0386 801fac00 2f800b90 43 y: LSHL_INT T0.y, R0.w, [0x0000001f 4.34403e-44].x 0388 0000001f 0390 801fa47c 4f800a90 44 z: ASHR_INT T0.z, T0.y, [0x0000001f 4.34403e-44].x 0392 0000001f 0394 801f087c 00002284 45 M x: PRED_SETNE_INT __.x, T0.z, 0 0110 0000003a 82800001 JUMP @116 POP:1 0112 0000003b 82400000 LOOP_BREAK @118 0114 0000003a 83800001 POP @116 POP:1 0116 000000c6 a0000000 ALU 1 @396 0396 80000800 00000c90 46 x: MOV R0.x, R0.z 0118 0000002f 81400000 LOOP_END @94 0120 000000c7 a0200000 ALU 9 @398 0398 801fa000 60000010 47 w: ADD R0.w, R0.x, [0x3fc00000 1.5].x 0400 3fc00000 0402 801fa001 6f830c00 48 w: MULADD_IEEE T0.w, R1.x, [0xc0000000 -2].x, R0.w 0404 c0000000 0406 801fac7c 00600190 49 x: MAX R3.x, T0.w, [0xc1800000 -16].x 0408 c1800000 0410 800000fd 00200c90 50 x: MOV R1.x, [0x3fc00000 1.5].x 0412 3fc00000 0414 80000003 00000c90 51 x: MOV R0.x, R3.x 0122 0000004b 81800000 LOOP_START_DX10 @150 0124 000000d0 a4040000 ALU_PUSH_BEFORE 2 @416 0416 801fa001 00001104 52 M x: PRED_SETGE __.x, R1.x, [0x41800000 16].x 0418 41800000 0126 00000041 82800000 JUMP @130 0128 000000d2 a0080000 ALU 3 @420 0420 000000fa 20200c90 53 y: MOV R1.y, 1 0422 800020fd 40200690 z: SETGT_DX10 R1.z, [0x41800000 16].x, R1.x 0424 41800000 0130 00000045 83400001 ELSE @138 POP:1 0132 400000d5 a0000000 ALU 1 @426 KC0[CB0:0-15] 0426 80002480 60430404 54 w: MULADD_IEEE R2.w, KC0[0].y, R1.x, R4.y 0134 000000d6 80400000 TEX 1 @428 0428 00021211 f00d1000 8da10000 SAMPLE_L R0.xyzw, R2.zww0, RID:18, SID:2 CT:NNNN 0136 000000d8 a8100000 ALU_POP_AFTER 5 @432 0432 001fa000 2f800710 55 y: SETGE_DX10 T0.y, R0.x, [0x3f666666 0.9].x 0434 809fa001 4f880010 z: ADD T0.z, R1.x, [0x40000000 2].y VEC_120 0436 3f666666 0437 40000000 0438 001f447c 202380f8 56 y: CNDE_INT R1.y, T0.y, 1, 0 0440 808f847c 4023887c z: CNDE_INT R1.z, T0.y, T0.y, T0.z 0138 000000dd a4100000 ALU_PUSH_BEFORE 5 @442 0442 801fa401 6f800b90 57 w: LSHL_INT T0.w, R1.y, [0x0000001f 4.34403e-44].x 0444 0000001f 0446 801fac7c 0f800a90 58 x: ASHR_INT T0.x, T0.w, [0x0000001f 4.34403e-44].x 0448 0000001f 0450 801f007c 00002284 59 M x: PRED_SETNE_INT __.x, T0.x, 0 0140 00000049 82800001 JUMP @146 POP:1 0142 0000004a 82400000 LOOP_BREAK @148 0144 00000049 83800001 POP @146 POP:1 0146 000000e2 a0000000 ALU 1 @452 0452 80000801 00200c90 60 x: MOV R1.x, R1.z 0148 0000003e 81400000 LOOP_END @124 0150 400000e3 a0280000 ALU 11 @454 KC0[CB0:0-15] 0454 801fa001 2f800010 61 y: ADD T0.y, R1.x, [0xbfc00000 -1.5].x 0456 bfc00000 0458 801fa000 4f82847c 62 z: MULADD T0.z, R0.x, [0x40000000 2].x, T0.y 0460 40000000 0462 801fa87c 60000210 63 w: MIN R0.w, T0.z, [0x41800000 16].x 0464 41800000 0466 801f2c00 0f800010 64 x: ADD T0.x, R0.w, 1.0 0468 001fa080 00030004 65 x: MULADD_IEEE R0.x, KC0[0].x, [0xbe800000 -0.25].x, R4.x 0470 0090007c 20030404 y: MULADD_IEEE R0.y, T0.x, KC0[0].y, R4.y 0472 80900003 400b0404 z: MULADD_IEEE R0.z, R3.x, KC0[0].y, R4.y VEC_120 0474 be800000 0152 000000ee 80400400 TEX 2 @476 0476 00001211 f01f9e00 84810000 SAMPLE_L R0._y__, R0.xyy0, RID:18, SID:2 CT:NNNN 0480 00001211 f01ff200 89010000 SAMPLE_L R0.y___, R0.xzz0, RID:18, SID:2 CT:NNNN 0154 000000f2 a0300000 ALU 13 @484 0484 001fa400 2f800110 66 y: MUL_IEEE T0.y, R0.y, [0x40800000 4].x 0486 801fa000 4f800110 z: MUL_IEEE T0.z, R0.x, [0x40800000 4].x 0488 40800000 0490 00000c00 0f800c91 67 x: MOV T0.x, |R0.w| 0492 0000087c 2f800990 y: RNDNE T0.y, T0.z 0494 00000003 4f800c91 z: MOV T0.z, |R3.x| 0496 8000047c 6f800990 w: RNDNE T0.w, T0.y 0498 001fa47c 0f83087c 68 x: MULADD_IEEE T0.x, T0.y, [0x42040000 33].x, T0.z 0500 801fac7c 6f83007c w: MULADD_IEEE T0.w, T0.w, [0x42040000 33].x, T0.x 0502 42040000 0504 001fa07c 00000110 69 x: MUL_IEEE R0.x, T0.x, [0x3bc7ce0a 0.00609756].x 0506 801fac7c 20000110 y: MUL_IEEE R0.y, T0.w, [0x3bc7ce0a 0.00609756].x 0508 3bc7ce0a 0156 00000100 80400000 TEX 1 @512 0512 00001011 f01f9000 84800000 SAMPLE_L R0.xy__, R0.xyy0, RID:16, SID:0 CT:NNNN 0158 00000102 a8040000 ALU_POP_AFTER 2 @516 0516 00000000 40400c90 70 z: MOV R2.z, R0.x 0518 80000400 60400c90 w: MOV R2.w, R0.y 0160 c0010000 95000688 EXPORT_DONE PIXEL 0 R2.xyzw 0162 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], PERSPECTIVE DCL IN[1], GENERIC[10], PERSPECTIVE DCL IN[2], GENERIC[11], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL SAMP[1] DCL TEMP[0..8] IMM[0] FLT32 { 1.0000, 0.0000, 0.0000, 0.0000} 0: TEX TEMP[0], IN[0].xyyy, SAMP[1], 2D 1: MOV TEMP[1].x, TEMP[0].xxxx 2: TEX TEMP[2].y, IN[2].zwww, SAMP[1], 2D 3: MOV TEMP[1].y, TEMP[2].yyyy 4: MOV TEMP[1].z, TEMP[0].zzzz 5: TEX TEMP[1].w, IN[2].xyyy, SAMP[1], 2D 6: MUL TEMP[4], TEMP[1], TEMP[1] 7: MUL TEMP[5], TEMP[4], TEMP[1] 8: DP4 TEMP[1].x, TEMP[5], IMM[0].xxxx 9: SLT TEMP[4].x, TEMP[1].xxxx, IMM[0].yyyy 10: IF TEMP[4].xxxx :12 11: KILL 12: ENDIF 13: TEX TEMP[4], IN[0].xyyy, SAMP[0], 2D 14: TEX TEMP[6], IN[1].zwww, SAMP[0], 2D 15: ADD TEMP[7].x, IMM[0].xxxx, -TEMP[0].xxxx 16: MUL TEMP[8], TEMP[4], TEMP[7].xxxx 17: MAD TEMP[7], TEMP[6], TEMP[0].xxxx, TEMP[8] 18: MUL TEMP[6], TEMP[7], TEMP[5].xxxx 19: TEX TEMP[7], IN[2].zwww, SAMP[0], 2D 20: ADD TEMP[8].x, IMM[0].xxxx, -TEMP[2].yyyy 21: MUL TEMP[3], TEMP[4], TEMP[8].xxxx 22: MAD TEMP[8], TEMP[7], TEMP[2].yyyy, TEMP[3] 23: MAD TEMP[2], TEMP[8], TEMP[5].yyyy, TEMP[6] 24: TEX TEMP[6], IN[1].xyyy, SAMP[0], 2D 25: ADD TEMP[7].x, IMM[0].xxxx, -TEMP[0].zzzz 26: MUL TEMP[8], TEMP[4], TEMP[7].xxxx 27: MAD TEMP[7], TEMP[6], TEMP[0].zzzz, TEMP[8] 28: MAD TEMP[0], TEMP[7], TEMP[5].zzzz, TEMP[2] 29: TEX TEMP[2], IN[2].xyyy, SAMP[0], 2D 30: ADD TEMP[6].x, IMM[0].xxxx, -TEMP[1].wwww 31: MUL TEMP[7], TEMP[4], TEMP[6].xxxx 32: MAD TEMP[4], TEMP[2], TEMP[1].wwww, TEMP[7] 33: MAD TEMP[2], TEMP[4], TEMP[5].wwww, TEMP[0] 34: RCP TEMP[0].x, TEMP[1].xxxx 35: MUL OUT[0], TEMP[2], TEMP[0].xxxx 36: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg, <4 x float> inreg, <4 x float> inreg) #0 { main_body: %4 = extractelement <4 x float> %0, i32 0 %5 = extractelement <4 x float> %0, i32 1 %6 = call <2 x float> @llvm.R600.interp.xy(i32 0, float %4, float %5) %7 = call <2 x float> @llvm.R600.interp.zw(i32 0, float %4, float %5) %8 = shufflevector <2 x float> %6, <2 x float> %7, <4 x i32> %9 = extractelement <4 x float> %8, i32 0 %10 = extractelement <4 x float> %8, i32 1 %11 = extractelement <4 x float> %0, i32 0 %12 = extractelement <4 x float> %0, i32 1 %13 = call <2 x float> @llvm.R600.interp.xy(i32 1, float %11, float %12) %14 = call <2 x float> @llvm.R600.interp.zw(i32 1, float %11, float %12) %15 = shufflevector <2 x float> %13, <2 x float> %14, <4 x i32> %16 = extractelement <4 x float> %15, i32 0 %17 = extractelement <4 x float> %15, i32 1 %18 = extractelement <4 x float> %15, i32 2 %19 = extractelement <4 x float> %15, i32 3 %20 = extractelement <4 x float> %0, i32 0 %21 = extractelement <4 x float> %0, i32 1 %22 = call <2 x float> @llvm.R600.interp.xy(i32 2, float %20, float %21) %23 = call <2 x float> @llvm.R600.interp.zw(i32 2, float %20, float %21) %24 = shufflevector <2 x float> %22, <2 x float> %23, <4 x i32> %25 = extractelement <4 x float> %24, i32 0 %26 = extractelement <4 x float> %24, i32 1 %27 = extractelement <4 x float> %24, i32 2 %28 = extractelement <4 x float> %24, i32 3 %29 = insertelement <4 x float> undef, float %9, i32 0 %30 = insertelement <4 x float> %29, float %10, i32 1 %31 = insertelement <4 x float> %30, float %10, i32 2 %32 = insertelement <4 x float> %31, float %10, i32 3 %33 = extractelement <4 x float> %32, i32 0 %34 = extractelement <4 x float> %32, i32 1 %35 = insertelement <4 x float> undef, float %33, i32 0 %36 = insertelement <4 x float> %35, float %34, i32 1 %37 = insertelement <4 x float> %36, float undef, i32 2 %38 = insertelement <4 x float> %37, float undef, i32 3 %39 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %38, i32 17, i32 1, i32 2) %40 = extractelement <4 x float> %39, i32 0 %41 = extractelement <4 x float> %39, i32 2 %42 = insertelement <4 x float> undef, float %27, i32 0 %43 = insertelement <4 x float> %42, float %28, i32 1 %44 = insertelement <4 x float> %43, float %28, i32 2 %45 = insertelement <4 x float> %44, float %28, i32 3 %46 = extractelement <4 x float> %45, i32 0 %47 = extractelement <4 x float> %45, i32 1 %48 = insertelement <4 x float> undef, float %46, i32 0 %49 = insertelement <4 x float> %48, float %47, i32 1 %50 = insertelement <4 x float> %49, float undef, i32 2 %51 = insertelement <4 x float> %50, float undef, i32 3 %52 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %51, i32 17, i32 1, i32 2) %53 = extractelement <4 x float> %52, i32 1 %54 = insertelement <4 x float> undef, float %25, i32 0 %55 = insertelement <4 x float> %54, float %26, i32 1 %56 = insertelement <4 x float> %55, float %26, i32 2 %57 = insertelement <4 x float> %56, float %26, i32 3 %58 = extractelement <4 x float> %57, i32 0 %59 = extractelement <4 x float> %57, i32 1 %60 = insertelement <4 x float> undef, float %58, i32 0 %61 = insertelement <4 x float> %60, float %59, i32 1 %62 = insertelement <4 x float> %61, float undef, i32 2 %63 = insertelement <4 x float> %62, float undef, i32 3 %64 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %63, i32 17, i32 1, i32 2) %65 = extractelement <4 x float> %64, i32 3 %66 = fmul float %40, %40 %67 = fmul float %53, %53 %68 = fmul float %41, %41 %69 = fmul float %65, %65 %70 = fmul float %66, %40 %71 = fmul float %67, %53 %72 = fmul float %68, %41 %73 = fmul float %69, %65 %74 = insertelement <4 x float> undef, float %70, i32 0 %75 = insertelement <4 x float> %74, float %71, i32 1 %76 = insertelement <4 x float> %75, float %72, i32 2 %77 = insertelement <4 x float> %76, float %73, i32 3 %78 = call float @llvm.AMDGPU.dp4(<4 x float> %77, <4 x float> ) %79 = fcmp olt float %78, 0x3EE4F8B580000000 %80 = select i1 %79, float 1.000000e+00, float 0.000000e+00 %81 = fcmp une float %80, 0.000000e+00 br i1 %81, label %IF, label %ENDIF IF: ; preds = %main_body call void @llvm.AMDGPU.kilp() br label %ENDIF ENDIF: ; preds = %main_body, %IF %82 = insertelement <4 x float> undef, float %9, i32 0 %83 = insertelement <4 x float> %82, float %10, i32 1 %84 = insertelement <4 x float> %83, float %10, i32 2 %85 = insertelement <4 x float> %84, float %10, i32 3 %86 = extractelement <4 x float> %85, i32 0 %87 = extractelement <4 x float> %85, i32 1 %88 = insertelement <4 x float> undef, float %86, i32 0 %89 = insertelement <4 x float> %88, float %87, i32 1 %90 = insertelement <4 x float> %89, float undef, i32 2 %91 = insertelement <4 x float> %90, float undef, i32 3 %92 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %91, i32 16, i32 0, i32 2) %93 = extractelement <4 x float> %92, i32 0 %94 = extractelement <4 x float> %92, i32 1 %95 = extractelement <4 x float> %92, i32 2 %96 = extractelement <4 x float> %92, i32 3 %97 = insertelement <4 x float> undef, float %18, i32 0 %98 = insertelement <4 x float> %97, float %19, i32 1 %99 = insertelement <4 x float> %98, float %19, i32 2 %100 = insertelement <4 x float> %99, float %19, i32 3 %101 = extractelement <4 x float> %100, i32 0 %102 = extractelement <4 x float> %100, i32 1 %103 = insertelement <4 x float> undef, float %101, i32 0 %104 = insertelement <4 x float> %103, float %102, i32 1 %105 = insertelement <4 x float> %104, float undef, i32 2 %106 = insertelement <4 x float> %105, float undef, i32 3 %107 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %106, i32 16, i32 0, i32 2) %108 = extractelement <4 x float> %107, i32 0 %109 = extractelement <4 x float> %107, i32 1 %110 = extractelement <4 x float> %107, i32 2 %111 = extractelement <4 x float> %107, i32 3 %112 = fsub float -0.000000e+00, %40 %113 = fadd float 1.000000e+00, %112 %114 = fmul float %93, %113 %115 = fmul float %94, %113 %116 = fmul float %95, %113 %117 = fmul float %96, %113 %118 = fmul float %108, %40 %119 = fadd float %118, %114 %120 = fmul float %109, %40 %121 = fadd float %120, %115 %122 = fmul float %110, %40 %123 = fadd float %122, %116 %124 = fmul float %111, %40 %125 = fadd float %124, %117 %126 = fmul float %119, %70 %127 = fmul float %121, %70 %128 = fmul float %123, %70 %129 = fmul float %125, %70 %130 = insertelement <4 x float> undef, float %27, i32 0 %131 = insertelement <4 x float> %130, float %28, i32 1 %132 = insertelement <4 x float> %131, float %28, i32 2 %133 = insertelement <4 x float> %132, float %28, i32 3 %134 = extractelement <4 x float> %133, i32 0 %135 = extractelement <4 x float> %133, i32 1 %136 = insertelement <4 x float> undef, float %134, i32 0 %137 = insertelement <4 x float> %136, float %135, i32 1 %138 = insertelement <4 x float> %137, float undef, i32 2 %139 = insertelement <4 x float> %138, float undef, i32 3 %140 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %139, i32 16, i32 0, i32 2) %141 = extractelement <4 x float> %140, i32 0 %142 = extractelement <4 x float> %140, i32 1 %143 = extractelement <4 x float> %140, i32 2 %144 = extractelement <4 x float> %140, i32 3 %145 = fsub float -0.000000e+00, %53 %146 = fadd float 1.000000e+00, %145 %147 = fmul float %93, %146 %148 = fmul float %94, %146 %149 = fmul float %95, %146 %150 = fmul float %96, %146 %151 = fmul float %141, %53 %152 = fadd float %151, %147 %153 = fmul float %142, %53 %154 = fadd float %153, %148 %155 = fmul float %143, %53 %156 = fadd float %155, %149 %157 = fmul float %144, %53 %158 = fadd float %157, %150 %159 = fmul float %152, %71 %160 = fadd float %159, %126 %161 = fmul float %154, %71 %162 = fadd float %161, %127 %163 = fmul float %156, %71 %164 = fadd float %163, %128 %165 = fmul float %158, %71 %166 = fadd float %165, %129 %167 = insertelement <4 x float> undef, float %16, i32 0 %168 = insertelement <4 x float> %167, float %17, i32 1 %169 = insertelement <4 x float> %168, float %17, i32 2 %170 = insertelement <4 x float> %169, float %17, i32 3 %171 = extractelement <4 x float> %170, i32 0 %172 = extractelement <4 x float> %170, i32 1 %173 = insertelement <4 x float> undef, float %171, i32 0 %174 = insertelement <4 x float> %173, float %172, i32 1 %175 = insertelement <4 x float> %174, float undef, i32 2 %176 = insertelement <4 x float> %175, float undef, i32 3 %177 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %176, i32 16, i32 0, i32 2) %178 = extractelement <4 x float> %177, i32 0 %179 = extractelement <4 x float> %177, i32 1 %180 = extractelement <4 x float> %177, i32 2 %181 = extractelement <4 x float> %177, i32 3 %182 = fsub float -0.000000e+00, %41 %183 = fadd float 1.000000e+00, %182 %184 = fmul float %93, %183 %185 = fmul float %94, %183 %186 = fmul float %95, %183 %187 = fmul float %96, %183 %188 = fmul float %178, %41 %189 = fadd float %188, %184 %190 = fmul float %179, %41 %191 = fadd float %190, %185 %192 = fmul float %180, %41 %193 = fadd float %192, %186 %194 = fmul float %181, %41 %195 = fadd float %194, %187 %196 = fmul float %189, %72 %197 = fadd float %196, %160 %198 = fmul float %191, %72 %199 = fadd float %198, %162 %200 = fmul float %193, %72 %201 = fadd float %200, %164 %202 = fmul float %195, %72 %203 = fadd float %202, %166 %204 = insertelement <4 x float> undef, float %25, i32 0 %205 = insertelement <4 x float> %204, float %26, i32 1 %206 = insertelement <4 x float> %205, float %26, i32 2 %207 = insertelement <4 x float> %206, float %26, i32 3 %208 = extractelement <4 x float> %207, i32 0 %209 = extractelement <4 x float> %207, i32 1 %210 = insertelement <4 x float> undef, float %208, i32 0 %211 = insertelement <4 x float> %210, float %209, i32 1 %212 = insertelement <4 x float> %211, float undef, i32 2 %213 = insertelement <4 x float> %212, float undef, i32 3 %214 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %213, i32 16, i32 0, i32 2) %215 = extractelement <4 x float> %214, i32 0 %216 = extractelement <4 x float> %214, i32 1 %217 = extractelement <4 x float> %214, i32 2 %218 = extractelement <4 x float> %214, i32 3 %219 = fsub float -0.000000e+00, %65 %220 = fadd float 1.000000e+00, %219 %221 = fmul float %93, %220 %222 = fmul float %94, %220 %223 = fmul float %95, %220 %224 = fmul float %96, %220 %225 = fmul float %215, %65 %226 = fadd float %225, %221 %227 = fmul float %216, %65 %228 = fadd float %227, %222 %229 = fmul float %217, %65 %230 = fadd float %229, %223 %231 = fmul float %218, %65 %232 = fadd float %231, %224 %233 = fmul float %226, %73 %234 = fadd float %233, %197 %235 = fmul float %228, %73 %236 = fadd float %235, %199 %237 = fmul float %230, %73 %238 = fadd float %237, %201 %239 = fmul float %232, %73 %240 = fadd float %239, %203 %241 = fdiv float 1.000000e+00, %78 %242 = fmul float %234, %241 %243 = fmul float %236, %241 %244 = fmul float %238, %241 %245 = fmul float %240, %241 %246 = insertelement <4 x float> undef, float %242, i32 0 %247 = insertelement <4 x float> %246, float %243, i32 1 %248 = insertelement <4 x float> %247, float %244, i32 2 %249 = insertelement <4 x float> %248, float %245, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %249, i32 0, i32 0) ret void } ; Function Attrs: readnone declare <2 x float> @llvm.R600.interp.xy(i32, float, float) #1 ; Function Attrs: readnone declare <2 x float> @llvm.R600.interp.zw(i32, float, float) #1 ; Function Attrs: readnone declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32, i32) #1 ; Function Attrs: readnone declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1 declare void @llvm.AMDGPU.kilp() declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } Shader Disassembly: ALU 21, @26, KC0[], KC1[] ; 0000001A A0540000 TEX 2 @10 ; 0000000A 80400800 ALU_PUSH_BEFORE 15, @48, KC0[], KC1[] ; 00000030 A43C0000 JUMP @5 POP:1 ; 00000005 82800001 ALU_POP_AFTER 0, @64, KC0[], KC1[] ; 00000040 A8000000 ALU 3, @65, KC0[], KC1[] ; 00000041 A00C0000 TEX 4 @16 ; 00000010 80401000 ALU 59, @69, KC0[], KC1[] ; 00000045 A0EC0000 EXPORT T4.XYZW ; C0020000 95200688 CF_END ; 00000000 88000000 Fetch clause starting at 10: ; TEX_SAMPLE T2.XYZW, T0.XY__ RID:17 SID:1 CT:NNNN ; 00001110 F00D1002 FC808000 00000000 TEX_SAMPLE T0.XYZW, T4.XY__ RID:17 SID:1 CT:NNNN ; 00041110 F00D1000 FC808000 00000000 TEX_SAMPLE T1.XYZW, T7.XY__ RID:17 SID:1 CT:NNNN ; 00071110 F00D1001 FC808000 00000000 Fetch clause starting at 16: ; TEX_SAMPLE T7.XYZW, T7.XY__ RID:16 SID:0 CT:NNNN ; 00071010 F00D1007 FC800000 00000000 TEX_SAMPLE T6.XYZW, T6.XY__ RID:16 SID:0 CT:NNNN ; 00061010 F00D1006 FC800000 00000000 TEX_SAMPLE T8.XYZW, T10.XY__ RID:16 SID:0 CT:NNNN ; 000A1010 F00D1008 FC800000 00000000 TEX_SAMPLE T9.XYZW, T9.XY__ RID:16 SID:0 CT:NNNN ; 00091010 F00D1009 FC800000 00000000 TEX_SAMPLE T4.XYZW, T4.XY__ RID:16 SID:0 CT:NNNN ; 00041010 F00D1004 FC800000 00000000 ALU clause starting at 26: ; INTERP_XY T4.X, T0.Y, ARRAY_BASE, ; 00380400 00946B10 INTERP_XY T4.Y, T0.X, ARRAY_BASE, ; 00380000 20946B10 INTERP_XY T0.Z (MASKED), T0.Y, ARRAY_BASE, ; 00380400 40146B00 INTERP_XY * T0.W (MASKED), T0.X, ARRAY_BASE, ; 80380000 60146B00 INTERP_XY T6.X, T0.Y, ARRAY_BASE, ; 00382400 00D46B10 INTERP_XY T6.Y, T0.X, ARRAY_BASE, ; 00382000 20D46B10 INTERP_XY T0.Z (MASKED), T0.Y, ARRAY_BASE, ; 00382400 40146B00 INTERP_XY * T0.W (MASKED), T0.X, ARRAY_BASE, ; 80382000 60146B00 INTERP_ZW T0.X (MASKED), T0.Y, ARRAY_BASE, ; 00382400 00146B80 INTERP_ZW T0.Y (MASKED), T0.X, ARRAY_BASE, ; 00382000 20146B80 INTERP_ZW T8.Z, T0.Y, ARRAY_BASE, ; 00382400 41146B90 INTERP_ZW * T5.W, T0.X, ARRAY_BASE, ; 80382000 60B46B90 INTERP_XY T7.X, T0.Y, ARRAY_BASE, ; 00384400 00F46B10 INTERP_XY T7.Y, T0.X, ARRAY_BASE, ; 00384000 20F46B10 INTERP_XY T0.Z (MASKED), T0.Y, ARRAY_BASE, ; 00384400 40146B00 INTERP_XY * T0.W (MASKED), T0.X, ARRAY_BASE, ; 80384000 60146B00 INTERP_ZW T0.X (MASKED), T0.Y, ARRAY_BASE, ; 00384400 00146B80 INTERP_ZW T0.Y (MASKED), T0.X, ARRAY_BASE, ; 00384000 20146B80 INTERP_ZW T5.Z, T0.Y, ARRAY_BASE, ; 00384400 40B46B90 INTERP_ZW * T8.W, T0.X, ARRAY_BASE, ; 80384000 61146B90 MOV T0.X, PV.Z, ; 000008FE 00000C90 MOV * T0.Y, PV.W, ; 80000CFE 20000C90 ALU clause starting at 48: ; MUL_IEEE T3.X, T1.W, T1.W, ; 01802C01 00600110 MUL_IEEE T5.Y, T0.Z, T0.Z, ; 01000800 20A00110 MUL_IEEE T3.Z, T2.Y, T2.Y, ; 00804402 40600110 MUL_IEEE * T3.W, T0.X, T0.X, ; 80000000 60600110 MUL_IEEE T5.X, PV.W, T0.X, ; 00000CFE 00A00110 MUL_IEEE T3.Y, PV.Z, T2.Y, ; 008048FE 20600110 MUL_IEEE T3.Z, PV.Y, T0.Z, ; 010004FE 40600110 MUL_IEEE * T3.W, PV.X, T1.W, ; 818020FE 60600110 DOT4 T3.X, T5.X, 1.0, ; 001F2005 00605F10 DOT4 T3.Y (MASKED), T3.Y, 1.0, ; 001F2403 20605F00 DOT4 T3.Z (MASKED), T3.Z, 1.0, ; 001F2803 40605F00 DOT4 * T3.W (MASKED), T3.W, 1.0, ; 801F2C03 60605F00 SETGT * T9.W, literal.x, PV.X, ; 801FC0FD 61200490 925353388(1.000000e-05), 0(0.000000e+00) ; 3727C5AC 00000000 SETE_DX10 * T9.W, PV.W, 0.0, ; 801F0CFE 61200610 PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002104 ALU clause starting at 64: ; KILLGT * T5.Y (MASKED), 1.0, 0.0, ; 801F00F9 20A01680 ALU clause starting at 65: ; MOV * T9.X, T8.Z, ; 80000808 01200C90 MOV T10.X, T5.Z, ; 00000805 01400C90 MOV * T9.Y, T5.W, ; 80000C05 21200C90 MOV * T10.Y, T8.W, ; 80000C08 21400C90 ALU clause starting at 69: ; ADD * T5.W, -T0.X, 1.0, ; 801F3000 60A00010 MUL_IEEE T5.Z, T4.Z, PV.W, ; 019FC804 40A00110 ADD * T10.W, -T2.Y, 1.0, ; 801F3402 61400010 MUL_IEEE T5.Y, T4.Z, PV.W, ; 019FC804 20A00110 MULADD_IEEE T5.Z, T9.Z, T0.X, PV.Z, BS:VEC_120/SCL_212 ; 00000809 40AB08FE ADD * T11.W, -T0.Z, 1.0, BS:VEC_201 ; 801F3800 61700010 MUL_IEEE T10.X, T4.Z, PV.W, ; 019FC804 01400110 MUL_IEEE T10.Y, PV.Z, T5.X, ; 0000A8FE 21400110 MULADD_IEEE T5.Z, T8.Z, T2.Y, PV.Y, BS:VEC_120/SCL_212 ; 00804808 40AB04FE ADD * T12.W, -T1.W, 1.0, ; 801F3C01 61800010 MUL_IEEE T5.Y, T4.Z, PV.W, ; 019FC804 20A00110 MULADD_IEEE T5.Z, PV.Z, T3.Y, PV.Y, ; 008068FE 40A304FE MULADD_IEEE * T13.W, T6.Z, T0.Z, PV.X, BS:VEC_120/SCL_212 ; 81000806 61AB00FE MULADD_IEEE T10.X, PV.W, T3.Z, PV.Z, ; 01006CFE 014308FE MULADD_IEEE T5.Y, T7.Z, T1.W, PV.Y, ; 01802807 20A304FE MUL_IEEE * T5.Z, T4.W, T12.W, BS:VEC_021/SCL_122 ; 81818C04 40A40110 MUL_IEEE * T13.W, T4.X, T5.W, ; 8180A004 61A00110 MUL_IEEE T11.X, T4.W, T11.W, ; 01816C04 01600110 MUL_IEEE * T10.Y, T4.W, T5.W, BS:VEC_021/SCL_122 ; 8180AC04 21440110 MUL_IEEE T10.Z, T4.X, T10.W, ; 01814004 41400110 MULADD_IEEE * T13.W, T9.X, T0.X, T13.W, BS:VEC_120/SCL_212 ; 80000009 61AB0C0D MUL_IEEE T12.X, T4.X, T11.W, ; 01816004 01800110 MUL_IEEE T11.Y, PV.W, T5.X, ; 0000ACFE 21600110 MULADD_IEEE * T10.Z, T8.X, T2.Y, PV.Z, BS:VEC_201 ; 80804008 415308FE MULADD_IEEE * T13.W, T9.W, T0.X, T10.Y, ; 80000C09 61A3040A MUL_IEEE T13.X, PV.W, T5.X, ; 0000ACFE 01A00110 MUL_IEEE T10.Y, T4.Y, T5.W, ; 0180A404 21400110 MULADD_IEEE T10.Z, T10.Z, T3.Y, T11.Y, ; 0080680A 4143040B MULADD_IEEE * T5.W, T6.X, T0.Z, T12.X, ; 81000006 60A3000C MULADD_IEEE T12.X, PV.W, T3.Z, PV.Z, ; 01006CFE 018308FE MUL_IEEE T11.Y, T4.Y, T10.W, ; 01814404 21600110 MULADD_IEEE T9.Z, T9.Y, T0.X, PV.Y, BS:VEC_120/SCL_212 ; 00000409 412B04FE MUL_IEEE * T5.W, T4.X, T12.W, BS:VEC_021/SCL_122 ; 81818004 60A40110 MULADD_IEEE T9.X, T7.X, T1.W, PV.W, ; 01802007 01230CFE MUL_IEEE T9.Y, T4.Y, T11.W, BS:VEC_021/SCL_122 ; 01816404 21240110 MUL_IEEE T9.Z, PV.Z, T5.X, ; 0000A8FE 41200110 MULADD_IEEE * T5.W, T8.Y, T2.Y, PV.Y, BS:VEC_120/SCL_212 ; 80804408 60AB04FE MUL_IEEE T5.X, T4.Y, T12.W, ; 01818404 00A00110 MULADD_IEEE T10.Y, PV.W, T3.Y, PV.Z, ; 00806CFE 214308FE MULADD_IEEE T9.Z, T6.Y, T0.Z, PV.Y, BS:VEC_201 ; 01000406 413304FE MUL_IEEE * T4.W, T4.W, T10.W, BS:VEC_021/SCL_122 ; 81814C04 60840110 MULADD_IEEE T2.X, T8.W, T2.Y, PV.W, ; 00804C08 00430CFE MULADD_IEEE T2.Y, PV.Z, T3.Z, PV.Y, ; 010068FE 204304FE MULADD_IEEE T2.Z, T7.Y, T1.W, PV.X, ; 01802407 404300FE MULADD_IEEE * T2.W, T9.X, T3.W, T12.X, BS:VEC_021/SCL_122 ; 81806009 6047000C RECIP_IEEE T3.X, T3.X, ; 00000003 00604310 RECIP_IEEE T3.Y (MASKED), T3.X, ; 00000003 20604300 RECIP_IEEE T3.Z (MASKED), T3.X, ; 00000003 40604300 RECIP_IEEE * T3.W (MASKED), T3.X, ; 80000003 60604300 MUL_IEEE T4.X, T2.W, PV.X, ; 001FCC02 00800110 MULADD_IEEE T2.Y, T2.Z, T3.W, T2.Y, ; 01806802 20430402 MULADD_IEEE T2.Z, T2.X, T3.Y, T13.X, BS:VEC_102/SCL_221 ; 00806002 404F000D MULADD_IEEE * T0.W, T6.W, T0.Z, T11.X, BS:VEC_210 ; 81000C06 6017000B MULADD_IEEE T0.X, PV.W, T3.Z, PV.Z, ; 01006CFE 000308FE MUL_IEEE T4.Y, PV.Y, T3.X, ; 000064FE 20800110 MULADD_IEEE T0.Z, T7.W, T1.W, T5.Z, ; 01802C07 40030805 MULADD_IEEE * T0.W, T5.Y, T3.W, T10.X, BS:VEC_120/SCL_212 ; 81806405 600B000A MUL_IEEE T4.Z, PV.W, T3.X, ; 00006CFE 40800110 MULADD_IEEE * T0.W, PV.Z, T3.W, PV.X, ; 818068FE 600300FE MUL_IEEE * T4.W, PV.W, T3.X, ; 80006CFE 60800110 ===== SHADER #54 ======================================== PS/CAYMAN/CAYMAN ===== ===== 258 dw ===== 14 gprs ===== 1 stack ======================================= 0000 0000001a a0540000 ALU 22 @52 0052 00380400 00946b10 1 x: INTERP_XY R4.x, R0.y, Param0.x VEC_210 0054 00380000 20946b10 y: INTERP_XY R4.y, R0.x, Param0.x VEC_210 0056 00380400 40146b00 z: INTERP_XY __.z, R0.y, Param0.x VEC_210 0058 80380000 60146b00 w: INTERP_XY __.w, R0.x, Param0.x VEC_210 0060 00382400 00d46b10 2 x: INTERP_XY R6.x, R0.y, Param1.x VEC_210 0062 00382000 20d46b10 y: INTERP_XY R6.y, R0.x, Param1.x VEC_210 0064 00382400 40146b00 z: INTERP_XY __.z, R0.y, Param1.x VEC_210 0066 80382000 60146b00 w: INTERP_XY __.w, R0.x, Param1.x VEC_210 0068 00382400 00146b80 3 x: INTERP_ZW __.x, R0.y, Param1.x VEC_210 0070 00382000 20146b80 y: INTERP_ZW __.y, R0.x, Param1.x VEC_210 0072 00382400 41146b90 z: INTERP_ZW R8.z, R0.y, Param1.x VEC_210 0074 80382000 60b46b90 w: INTERP_ZW R5.w, R0.x, Param1.x VEC_210 0076 00384400 00f46b10 4 x: INTERP_XY R7.x, R0.y, Param2.x VEC_210 0078 00384000 20f46b10 y: INTERP_XY R7.y, R0.x, Param2.x VEC_210 0080 00384400 40146b00 z: INTERP_XY __.z, R0.y, Param2.x VEC_210 0082 80384000 60146b00 w: INTERP_XY __.w, R0.x, Param2.x VEC_210 0084 00384400 00146b80 5 x: INTERP_ZW __.x, R0.y, Param2.x VEC_210 0086 00384000 20146b80 y: INTERP_ZW __.y, R0.x, Param2.x VEC_210 0088 00384400 40b46b90 z: INTERP_ZW R5.z, R0.y, Param2.x VEC_210 0090 80384000 61146b90 w: INTERP_ZW R8.w, R0.x, Param2.x VEC_210 0092 000008fe 00000c90 6 x: MOV R0.x, PV.z 0094 80000cfe 20000c90 y: MOV R0.y, PV.w 0002 0000000a 80400800 TEX 3 @20 0020 00001110 f00d1002 fc808000 SAMPLE R2.xyzw, R0.xy__, RID:17, SID:1 CT:NNNN 0024 00041110 f00d1000 fc808000 SAMPLE R0.xyzw, R4.xy__, RID:17, SID:1 CT:NNNN 0028 00071110 f00d1001 fc808000 SAMPLE R1.xyzw, R7.xy__, RID:17, SID:1 CT:NNNN 0004 00000030 a43c0000 ALU_PUSH_BEFORE 16 @96 0096 01802c01 00600110 7 x: MUL_IEEE R3.x, R1.w, R1.w 0098 01000800 20a00110 y: MUL_IEEE R5.y, R0.z, R0.z 0100 00804402 40600110 z: MUL_IEEE R3.z, R2.y, R2.y 0102 80000000 60600110 w: MUL_IEEE R3.w, R0.x, R0.x 0104 00000cfe 00a00110 8 x: MUL_IEEE R5.x, PV.w, R0.x 0106 008048fe 20600110 y: MUL_IEEE R3.y, PV.z, R2.y 0108 010004fe 40600110 z: MUL_IEEE R3.z, PV.y, R0.z 0110 818020fe 60600110 w: MUL_IEEE R3.w, PV.x, R1.w 0112 001f2005 00605f10 9 x: DOT4 R3.x, R5.x, 1.0 0114 001f2403 20605f00 y: DOT4 __.y, R3.y, 1.0 0116 001f2803 40605f00 z: DOT4 __.z, R3.z, 1.0 0118 801f2c03 60605f00 w: DOT4 __.w, R3.w, 1.0 0120 801fc0fd 61200490 10 w: SETGT R9.w, [0x3727c5ac 1e-05].x, PV.x 0122 3727c5ac 0124 801f0cfe 61200610 11 w: SETE_DX10 R9.w, PV.w, 0 0126 801f0cfe 00002104 12 M x: PRED_SETE_INT __.x, PV.w, 0 0006 00000005 82800001 JUMP @10 POP:1 0008 00000040 a8000000 ALU_POP_AFTER 1 @128 0128 801f00f9 20a01680 13 y: KILLGT __.y, 1.0, 0 0010 00000041 a00c0000 ALU 4 @130 0130 80000808 01200c90 14 x: MOV R9.x, R8.z 0132 00000805 01400c90 15 x: MOV R10.x, R5.z 0134 80000c05 21200c90 y: MOV R9.y, R5.w 0136 80000c08 21400c90 16 y: MOV R10.y, R8.w 0012 00000010 80401000 TEX 5 @32 0032 00071010 f00d1007 fc800000 SAMPLE R7.xyzw, R7.xy__, RID:16, SID:0 CT:NNNN 0036 00061010 f00d1006 fc800000 SAMPLE R6.xyzw, R6.xy__, RID:16, SID:0 CT:NNNN 0040 000a1010 f00d1008 fc800000 SAMPLE R8.xyzw, R10.xy__, RID:16, SID:0 CT:NNNN 0044 00091010 f00d1009 fc800000 SAMPLE R9.xyzw, R9.xy__, RID:16, SID:0 CT:NNNN 0048 00041010 f00d1004 fc800000 SAMPLE R4.xyzw, R4.xy__, RID:16, SID:0 CT:NNNN 0014 00000045 a0ec0000 ALU 60 @138 0138 801f3000 60a00010 17 w: ADD R5.w, -R0.x, 1.0 0140 019fc804 40a00110 18 z: MUL_IEEE R5.z, R4.z, PV.w 0142 801f3402 61400010 w: ADD R10.w, -R2.y, 1.0 0144 019fc804 20a00110 19 y: MUL_IEEE R5.y, R4.z, PV.w 0146 00000809 40ab08fe z: MULADD_IEEE R5.z, R9.z, R0.x, PV.z VEC_120 0148 801f3800 61700010 w: ADD R11.w, -R0.z, 1.0 VEC_201 0150 019fc804 01400110 20 x: MUL_IEEE R10.x, R4.z, PV.w 0152 0000a8fe 21400110 y: MUL_IEEE R10.y, PV.z, R5.x 0154 00804808 40ab04fe z: MULADD_IEEE R5.z, R8.z, R2.y, PV.y VEC_120 0156 801f3c01 61800010 w: ADD R12.w, -R1.w, 1.0 0158 019fc804 20a00110 21 y: MUL_IEEE R5.y, R4.z, PV.w 0160 008068fe 40a304fe z: MULADD_IEEE R5.z, PV.z, R3.y, PV.y 0162 81000806 61ab00fe w: MULADD_IEEE R13.w, R6.z, R0.z, PV.x VEC_120 0164 01006cfe 014308fe 22 x: MULADD_IEEE R10.x, PV.w, R3.z, PV.z 0166 01802807 20a304fe y: MULADD_IEEE R5.y, R7.z, R1.w, PV.y 0168 81818c04 40a40110 z: MUL_IEEE R5.z, R4.w, R12.w VEC_021 0170 8180a004 61a00110 23 w: MUL_IEEE R13.w, R4.x, R5.w 0172 01816c04 01600110 24 x: MUL_IEEE R11.x, R4.w, R11.w 0174 8180ac04 21440110 y: MUL_IEEE R10.y, R4.w, R5.w VEC_021 0176 01814004 41400110 25 z: MUL_IEEE R10.z, R4.x, R10.w 0178 80000009 61ab0c0d w: MULADD_IEEE R13.w, R9.x, R0.x, R13.w VEC_120 0180 01816004 01800110 26 x: MUL_IEEE R12.x, R4.x, R11.w 0182 0000acfe 21600110 y: MUL_IEEE R11.y, PV.w, R5.x 0184 80804008 415308fe z: MULADD_IEEE R10.z, R8.x, R2.y, PV.z VEC_201 0186 80000c09 61a3040a 27 w: MULADD_IEEE R13.w, R9.w, R0.x, R10.y 0188 0000acfe 01a00110 28 x: MUL_IEEE R13.x, PV.w, R5.x 0190 0180a404 21400110 y: MUL_IEEE R10.y, R4.y, R5.w 0192 0080680a 4143040b z: MULADD_IEEE R10.z, R10.z, R3.y, R11.y 0194 81000006 60a3000c w: MULADD_IEEE R5.w, R6.x, R0.z, R12.x 0196 01006cfe 018308fe 29 x: MULADD_IEEE R12.x, PV.w, R3.z, PV.z 0198 01814404 21600110 y: MUL_IEEE R11.y, R4.y, R10.w 0200 00000409 412b04fe z: MULADD_IEEE R9.z, R9.y, R0.x, PV.y VEC_120 0202 81818004 60a40110 w: MUL_IEEE R5.w, R4.x, R12.w VEC_021 0204 01802007 01230cfe 30 x: MULADD_IEEE R9.x, R7.x, R1.w, PV.w 0206 01816404 21240110 y: MUL_IEEE R9.y, R4.y, R11.w VEC_021 0208 0000a8fe 41200110 z: MUL_IEEE R9.z, PV.z, R5.x 0210 80804408 60ab04fe w: MULADD_IEEE R5.w, R8.y, R2.y, PV.y VEC_120 0212 01818404 00a00110 31 x: MUL_IEEE R5.x, R4.y, R12.w 0214 00806cfe 214308fe y: MULADD_IEEE R10.y, PV.w, R3.y, PV.z 0216 01000406 413304fe z: MULADD_IEEE R9.z, R6.y, R0.z, PV.y VEC_201 0218 81814c04 60840110 w: MUL_IEEE R4.w, R4.w, R10.w VEC_021 0220 00804c08 00430cfe 32 x: MULADD_IEEE R2.x, R8.w, R2.y, PV.w 0222 010068fe 204304fe y: MULADD_IEEE R2.y, PV.z, R3.z, PV.y 0224 01802407 404300fe z: MULADD_IEEE R2.z, R7.y, R1.w, PV.x 0226 81806009 6047000c w: MULADD_IEEE R2.w, R9.x, R3.w, R12.x VEC_021 0228 00000003 00604310 33 x: RECIP_IEEE R3.x, R3.x 0230 00000003 20604300 y: RECIP_IEEE __.y, R3.x 0232 00000003 40604300 z: RECIP_IEEE __.z, R3.x 0234 80000003 60604300 w: RECIP_IEEE __.w, R3.x 0236 001fcc02 00800110 34 x: MUL_IEEE R4.x, R2.w, PV.x 0238 01806802 20430402 y: MULADD_IEEE R2.y, R2.z, R3.w, R2.y 0240 00806002 404f000d z: MULADD_IEEE R2.z, R2.x, R3.y, R13.x VEC_102 0242 81000c06 6017000b w: MULADD_IEEE R0.w, R6.w, R0.z, R11.x VEC_210 0244 01006cfe 000308fe 35 x: MULADD_IEEE R0.x, PV.w, R3.z, PV.z 0246 000064fe 20800110 y: MUL_IEEE R4.y, PV.y, R3.x 0248 01802c07 40030805 z: MULADD_IEEE R0.z, R7.w, R1.w, R5.z 0250 81806405 600b000a w: MULADD_IEEE R0.w, R5.y, R3.w, R10.x VEC_120 0252 00006cfe 40800110 36 z: MUL_IEEE R4.z, PV.w, R3.x 0254 818068fe 600300fe w: MULADD_IEEE R0.w, PV.z, R3.w, PV.x 0256 80006cfe 60800110 37 w: MUL_IEEE R4.w, PV.w, R3.x 0016 c0020000 95200688 EXPORT_DONE PIXEL 0 R4.xyzw 0018 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #54 OPT ==================================== PS/CAYMAN/CAYMAN ===== ===== 236 dw ===== 8 gprs ===== 0 stack ======================================== 0000 00000007 a02c0000 ALU 12 @14 0014 00384400 00146b80 1 x: INTERP_ZW __.x, R0.y, Param2.x VEC_210 0016 00b84000 20146b80 y: INTERP_ZW __.y, R0.x, Param2.y VEC_210 0018 01384400 40546b90 z: INTERP_ZW R2.z, R0.y, Param2.z VEC_210 0020 81b84000 60546b90 w: INTERP_ZW R2.w, R0.x, Param2.w VEC_210 0022 00380400 00346b10 2 x: INTERP_XY R1.x, R0.y, Param0.x VEC_210 0024 00b80000 20346b10 y: INTERP_XY R1.y, R0.x, Param0.y VEC_210 0026 01380400 40146b00 z: INTERP_XY __.z, R0.y, Param0.z VEC_210 0028 81b80000 60146b00 w: INTERP_XY __.w, R0.x, Param0.w VEC_210 0030 00384400 00946b10 3 x: INTERP_XY R4.x, R0.y, Param2.x VEC_210 0032 00b84000 20946b10 y: INTERP_XY R4.y, R0.x, Param2.y VEC_210 0034 01384400 40146b00 z: INTERP_XY __.z, R0.y, Param2.z VEC_210 0036 81b84000 60146b00 w: INTERP_XY __.w, R0.x, Param2.w VEC_210 0002 00000014 80400800 TEX 3 @40 0040 00041110 f01dfe05 fc808000 SAMPLE R5.__w_, R4.xy__, RID:17, SID:1 CT:NNNN 0044 00011110 f01fa005 fc808000 SAMPLE R5.xz__, R1.xy__, RID:17, SID:1 CT:NNNN 0048 00021110 f007fe05 fda08000 SAMPLE R5.___y, R2.zw__, RID:17, SID:1 CT:NNNN 0004 0000001a a0540000 ALU 22 @52 0052 0180ac05 0f800110 4 x: MUL_IEEE T0.x, R5.w, R5.w 0054 0000a005 2f800110 y: MUL_IEEE T0.y, R5.x, R5.x 0056 0100a805 4f800110 z: MUL_IEEE T0.z, R5.z, R5.z 0058 8080a405 6f800110 w: MUL_IEEE T0.w, R5.y, R5.y 0060 0000a47c 00c00110 5 x: MUL_IEEE R6.x, T0.y, R5.x 0062 0180a07c 20c00110 y: MUL_IEEE R6.y, T0.x, R5.w 0064 0080ac7c 40e00110 z: MUL_IEEE R7.z, T0.w, R5.y 0066 8100a87c 60c00110 w: MUL_IEEE R6.w, T0.z, R5.z 0068 001f2006 00005f00 6 x: DOT4 __.x, R6.x, 1.0 0070 001f2406 20005f00 y: DOT4 __.y, R6.y, 1.0 0072 001f2807 40c05f10 z: DOT4 R6.z, R7.z, 1.0 0074 801f2c06 60005f00 w: DOT4 __.w, R6.w, 1.0 0076 00382400 00746b10 7 x: INTERP_XY R3.x, R0.y, Param1.x VEC_210 0078 00b82000 20746b10 y: INTERP_XY R3.y, R0.x, Param1.y VEC_210 0080 01382400 40146b00 z: INTERP_XY __.z, R0.y, Param1.z VEC_210 0082 81b82000 60146b00 w: INTERP_XY __.w, R0.x, Param1.w VEC_210 0084 00382400 00146b80 8 x: INTERP_ZW __.x, R0.y, Param1.x VEC_210 0086 00b82000 20146b80 y: INTERP_ZW __.y, R0.x, Param1.y VEC_210 0088 01382400 40346b90 z: INTERP_ZW R1.z, R0.y, Param1.z VEC_210 0090 81b82000 60346b90 w: INTERP_ZW R1.w, R0.x, Param1.w VEC_210 0092 8100c0fd 00001680 9 x: KILLGT __.x, [0x3727c5ac 1e-05].x, R6.z 0094 3727c5ac 0006 00000030 80401000 TEX 5 @96 0096 00011010 f00d1000 fc800000 SAMPLE R0.xyzw, R1.xy__, RID:16, SID:0 CT:NNNN 0100 00011010 f00d1001 fda00000 SAMPLE R1.xyzw, R1.zw__, RID:16, SID:0 CT:NNNN 0104 00021010 f00d1002 fda00000 SAMPLE R2.xyzw, R2.zw__, RID:16, SID:0 CT:NNNN 0108 00031010 f00d1003 fc800000 SAMPLE R3.xyzw, R3.xy__, RID:16, SID:0 CT:NNNN 0112 00041010 f00d1004 fc800000 SAMPLE R4.xyzw, R4.xy__, RID:16, SID:0 CT:NNNN 0008 0000003a a0ec0000 ALU 60 @116 0116 801f3005 6f800010 10 w: ADD T0.w, -R5.x, 1.0 0118 818f8000 0f800110 11 x: MUL_IEEE T0.x, R0.x, T0.w 0120 001f3c05 0f800010 12 x: ADD T0.x, -R5.w, 1.0 0122 0000a001 2fa3007c y: MULADD_IEEE T1.y, R1.x, R5.x, T0.x 0124 818f8800 4fa00110 z: MUL_IEEE T1.z, R0.z, T0.w 0126 018f8c00 2f800110 13 y: MUL_IEEE T0.y, R0.w, T0.w 0128 000f8c00 4f800110 z: MUL_IEEE T0.z, R0.w, T0.x 0130 818f8400 6f800110 w: MUL_IEEE T0.w, R0.y, T0.w 0132 000f8000 0fa00110 14 x: MUL_IEEE T1.x, R0.x, T0.x 0134 001f3405 2ff00010 y: ADD T3.y, -R5.y, 1.0 VEC_201 0136 000f8400 4fc00110 z: MUL_IEEE T2.z, R0.y, T0.x 0138 8000ac01 6fc7047c w: MULADD_IEEE T2.w, R1.w, R5.x, T0.y VEC_021 0140 000f8800 0f900110 15 x: MUL_IEEE T0.x, R0.z, T0.x VEC_201 0142 0000a801 2f87087d y: MULADD_IEEE T0.y, R1.z, R5.x, T1.z VEC_021 0144 0000c47d 4fa00110 z: MUL_IEEE T1.z, T1.y, R6.x 0146 8000a401 6f8b0c7c w: MULADD_IEEE T0.w, R1.y, R5.x, T0.w VEC_120 0148 0180ac02 0fc3087c 16 x: MULADD_IEEE T2.x, R2.w, R5.w, T0.z 0150 0180a002 2fc7007d y: MULADD_IEEE T2.y, R2.x, R5.w, T1.x VEC_021 0152 001f3805 4fe80010 z: ADD T3.z, -R5.z, 1.0 VEC_120 0154 8180a802 6fa3007c w: MULADD_IEEE T1.w, R2.z, R5.w, T0.x 0156 0000c47c 0fa00110 17 x: MUL_IEEE T1.x, T0.y, R6.x 0158 0000cc7e 2fa80110 y: MUL_IEEE T1.y, T2.w, R6.x VEC_120 0160 008fe800 4f800110 z: MUL_IEEE T0.z, R0.z, T3.y 0162 808fec00 6fc00110 w: MUL_IEEE T2.w, R0.w, T3.y 0164 008fe000 0f800110 18 x: MUL_IEEE T0.x, R0.x, T3.y 0166 008fe400 2f940110 y: MUL_IEEE T0.y, R0.y, T3.y VEC_210 0168 0180a402 4fc3087e z: MULADD_IEEE T2.z, R2.y, R5.w, T2.z 0170 8000cc7c 6f800110 w: MUL_IEEE T0.w, T0.w, R6.x 0172 0080cc7d 0fe3007d 19 x: MULADD_IEEE T3.x, T1.w, R6.y, T1.x 0174 0080c07e 2fc3047d y: MULADD_IEEE T2.y, T2.x, R6.y, T1.y 0176 0080c47e 4fa3087d z: MULADD_IEEE T1.z, T2.y, R6.y, T1.z 0178 810fec00 6fac0110 w: MUL_IEEE T1.w, R0.w, T3.z VEC_102 0180 0080ac03 0fa30c7e 20 x: MULADD_IEEE T1.x, R3.w, R5.y, T2.w 0182 0080a003 2fa3007c y: MULADD_IEEE T1.y, R3.x, R5.y, T0.x 0184 0080a403 4f83047c z: MULADD_IEEE T0.z, R3.y, R5.y, T0.y 0186 8080a803 6fc3087c w: MULADD_IEEE T2.w, R3.z, R5.y, T0.z 0188 010fe000 0f800110 21 x: MUL_IEEE T0.x, R0.x, T3.z 0190 010fe400 2f940110 y: MUL_IEEE T0.y, R0.y, T3.z VEC_210 0192 010fe800 4fc00110 z: MUL_IEEE T2.z, R0.z, T3.z 0194 8080c87e 6f930c7c w: MULADD_IEEE T0.w, T2.z, R6.y, T0.w VEC_201 0196 0100e07d 0fc3047e 22 x: MULADD_IEEE T2.x, T1.x, R7.z, T2.y 0198 0100e47d 4fa3087d z: MULADD_IEEE T1.z, T1.y, R7.z, T1.z 0200 8100ac04 6faf0c7d w: MULADD_IEEE T1.w, R4.w, R5.z, T1.w VEC_102 0202 0100e87c 0fa30c7c 23 x: MULADD_IEEE T1.x, T0.z, R7.z, T0.w 0204 0100a004 2fa7007c y: MULADD_IEEE T1.y, R4.x, R5.z, T0.x VEC_021 0206 0100ec7e 4f83007f z: MULADD_IEEE T0.z, T2.w, R7.z, T3.x 0208 8100a404 6f87047c w: MULADD_IEEE T0.w, R4.y, R5.z, T0.y VEC_021 0210 00000806 0f804310 24 x: RECIP_IEEE T0.x, R6.z 0212 00000806 20004300 y: RECIP_IEEE __.y, R6.z 0214 00000806 40004300 z: RECIP_IEEE __.z, R6.z 0216 80000806 60004300 w: RECIP_IEEE __.w, R6.z 0218 0100a804 2f83087e 25 y: MULADD_IEEE T0.y, R4.z, R5.z, T2.z 0220 8180cc7d 6fa3007e w: MULADD_IEEE T1.w, T1.w, R6.w, T2.x 0222 0180c47c 2f8b087c 26 y: MULADD_IEEE T0.y, T0.y, R6.w, T0.z VEC_120 0224 0180cc7c 4f83007d z: MULADD_IEEE T0.z, T0.w, R6.w, T1.x 0226 8180c47d 6f83087d w: MULADD_IEEE T0.w, T1.y, R6.w, T1.z 0228 000f8c7c 00000110 27 x: MUL_IEEE R0.x, T0.w, T0.x 0230 000f887c 20000110 y: MUL_IEEE R0.y, T0.z, T0.x 0232 000f847c 40000110 z: MUL_IEEE R0.z, T0.y, T0.x 0234 800f8c7d 60080110 w: MUL_IEEE R0.w, T1.w, T0.x VEC_120 0010 c0000000 95000688 EXPORT_DONE PIXEL 0 R0.xyzw 0012 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== Installing breakpad exception handler for appid(steam)/version(1390852599_client) Installing breakpad exception handler for appid(steam)/version(1390852599_client) Installing breakpad exception handler for appid(steam)/version(1390852599_client) Installing breakpad exception handler for appid(steam)/version(1390852599_client) Installing breakpad exception handler for appid(steam)/version(1390852599_client) -------------------------------------------------------------- FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], COLOR, COLOR DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg) #0 { main_body: %2 = extractelement <4 x float> %0, i32 0 %3 = extractelement <4 x float> %0, i32 1 %4 = call <2 x float> @llvm.R600.interp.xy(i32 0, float %2, float %3) %5 = call <2 x float> @llvm.R600.interp.zw(i32 0, float %2, float %3) %6 = shufflevector <2 x float> %4, <2 x float> %5, <4 x i32> %7 = extractelement <4 x float> %6, i32 0 %8 = extractelement <4 x float> %6, i32 1 %9 = extractelement <4 x float> %6, i32 2 %10 = extractelement <4 x float> %6, i32 3 %11 = insertelement <4 x float> undef, float %7, i32 0 %12 = insertelement <4 x float> %11, float %8, i32 1 %13 = insertelement <4 x float> %12, float %9, i32 2 %14 = insertelement <4 x float> %13, float %10, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %14, i32 0, i32 0) ret void } ; Function Attrs: readnone declare <2 x float> @llvm.R600.interp.xy(i32, float, float) #1 ; Function Attrs: readnone declare <2 x float> @llvm.R600.interp.zw(i32, float, float) #1 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } Shader Disassembly: ALU 7, @4, KC0[], KC1[] ; 00000004 A01C0000 EXPORT T1.XYZW ; C0008000 95200688 CF_END ; 00000000 88000000 PAD ; 00000000 00000000 ALU clause starting at 4: ; INTERP_XY T1.X, T0.Y, ARRAY_BASE, ; 00380400 00346B10 INTERP_XY T1.Y, T0.X, ARRAY_BASE, ; 00380000 20346B10 INTERP_XY T0.Z (MASKED), T0.Y, ARRAY_BASE, ; 00380400 40146B00 INTERP_XY * T0.W (MASKED), T0.X, ARRAY_BASE, ; 80380000 60146B00 INTERP_ZW T0.X (MASKED), T0.Y, ARRAY_BASE, ; 00380400 00146B80 INTERP_ZW T0.Y (MASKED), T0.X, ARRAY_BASE, ; 00380000 20146B80 INTERP_ZW T1.Z, T0.Y, ARRAY_BASE, ; 00380400 40346B90 INTERP_ZW * T1.W, T0.X, ARRAY_BASE, ; 80380000 60346B90 ===== SHADER #55 ======================================== PS/CAYMAN/CAYMAN ===== ===== 24 dw ===== 2 gprs ===== 1 stack ========================================= 0000 00000004 a01c0000 ALU 8 @8 0008 00380400 00346b10 1 x: INTERP_XY R1.x, R0.y, Param0.x VEC_210 0010 00380000 20346b10 y: INTERP_XY R1.y, R0.x, Param0.x VEC_210 0012 00380400 40146b00 z: INTERP_XY __.z, R0.y, Param0.x VEC_210 0014 80380000 60146b00 w: INTERP_XY __.w, R0.x, Param0.x VEC_210 0016 00380400 00146b80 2 x: INTERP_ZW __.x, R0.y, Param0.x VEC_210 0018 00380000 20146b80 y: INTERP_ZW __.y, R0.x, Param0.x VEC_210 0020 00380400 40346b90 z: INTERP_ZW R1.z, R0.y, Param0.x VEC_210 0022 80380000 60346b90 w: INTERP_ZW R1.w, R0.x, Param0.x VEC_210 0002 c0008000 95200688 EXPORT_DONE PIXEL 0 R1.xyzw 0004 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #55 OPT ==================================== PS/CAYMAN/CAYMAN ===== ===== 22 dw ===== 1 gprs ===== 0 stack ========================================= 0000 00000003 a01c0000 ALU 8 @6 0006 00380400 00146b80 1 x: INTERP_ZW __.x, R0.y, Param0.x VEC_210 0008 00b80000 20146b80 y: INTERP_ZW __.y, R0.x, Param0.y VEC_210 0010 01380400 40146b90 z: INTERP_ZW R0.z, R0.y, Param0.z VEC_210 0012 81b80000 60146b90 w: INTERP_ZW R0.w, R0.x, Param0.w VEC_210 0014 00380400 00146b10 2 x: INTERP_XY R0.x, R0.y, Param0.x VEC_210 0016 00b80000 20146b10 y: INTERP_XY R0.y, R0.x, Param0.y VEC_210 0018 01380400 40146b00 z: INTERP_XY __.z, R0.y, Param0.z VEC_210 0020 81b80000 60146b00 w: INTERP_XY __.w, R0.x, Param0.w VEC_210 0002 c0000000 95000688 EXPORT_DONE PIXEL 0 R0.xyzw 0004 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], COLOR DCL CONST[0..3] DCL TEMP[0] 0: MUL TEMP[0], IN[0].xxxx, CONST[0] 1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0] 2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0] 3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0] 4: MOV_SAT OUT[1], IN[1] 5: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg, <4 x float> inreg) #0 { main_body: %3 = extractelement <4 x float> %1, i32 0 %4 = extractelement <4 x float> %1, i32 1 %5 = extractelement <4 x float> %1, i32 2 %6 = extractelement <4 x float> %1, i32 3 %7 = extractelement <4 x float> %2, i32 0 %8 = extractelement <4 x float> %2, i32 1 %9 = extractelement <4 x float> %2, i32 2 %10 = extractelement <4 x float> %2, i32 3 %11 = load <4 x float> addrspace(8)* null %12 = extractelement <4 x float> %11, i32 0 %13 = fmul float %3, %12 %14 = load <4 x float> addrspace(8)* null %15 = extractelement <4 x float> %14, i32 1 %16 = fmul float %3, %15 %17 = load <4 x float> addrspace(8)* null %18 = extractelement <4 x float> %17, i32 2 %19 = fmul float %3, %18 %20 = load <4 x float> addrspace(8)* null %21 = extractelement <4 x float> %20, i32 3 %22 = fmul float %3, %21 %23 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %24 = extractelement <4 x float> %23, i32 0 %25 = fmul float %4, %24 %26 = fadd float %25, %13 %27 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %28 = extractelement <4 x float> %27, i32 1 %29 = fmul float %4, %28 %30 = fadd float %29, %16 %31 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %32 = extractelement <4 x float> %31, i32 2 %33 = fmul float %4, %32 %34 = fadd float %33, %19 %35 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %36 = extractelement <4 x float> %35, i32 3 %37 = fmul float %4, %36 %38 = fadd float %37, %22 %39 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %40 = extractelement <4 x float> %39, i32 0 %41 = fmul float %5, %40 %42 = fadd float %41, %26 %43 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %44 = extractelement <4 x float> %43, i32 1 %45 = fmul float %5, %44 %46 = fadd float %45, %30 %47 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %48 = extractelement <4 x float> %47, i32 2 %49 = fmul float %5, %48 %50 = fadd float %49, %34 %51 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %52 = extractelement <4 x float> %51, i32 3 %53 = fmul float %5, %52 %54 = fadd float %53, %38 %55 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %56 = extractelement <4 x float> %55, i32 0 %57 = fmul float %6, %56 %58 = fadd float %57, %42 %59 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %60 = extractelement <4 x float> %59, i32 1 %61 = fmul float %6, %60 %62 = fadd float %61, %46 %63 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %64 = extractelement <4 x float> %63, i32 2 %65 = fmul float %6, %64 %66 = fadd float %65, %50 %67 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %68 = extractelement <4 x float> %67, i32 3 %69 = fmul float %6, %68 %70 = fadd float %69, %54 %71 = call float @llvm.AMDIL.clamp.(float %7, float 0.000000e+00, float 1.000000e+00) %72 = call float @llvm.AMDIL.clamp.(float %8, float 0.000000e+00, float 1.000000e+00) %73 = call float @llvm.AMDIL.clamp.(float %9, float 0.000000e+00, float 1.000000e+00) %74 = call float @llvm.AMDIL.clamp.(float %10, float 0.000000e+00, float 1.000000e+00) %75 = insertelement <4 x float> undef, float %58, i32 0 %76 = insertelement <4 x float> %75, float %62, i32 1 %77 = insertelement <4 x float> %76, float %66, i32 2 %78 = insertelement <4 x float> %77, float %70, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %78, i32 60, i32 1) %79 = insertelement <4 x float> undef, float %71, i32 0 %80 = insertelement <4 x float> %79, float %72, i32 1 %81 = insertelement <4 x float> %80, float %73, i32 2 %82 = insertelement <4 x float> %81, float %74, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %82, i32 0, i32 2) ret void } ; Function Attrs: readnone declare float @llvm.AMDIL.clamp.(float, float, float) #1 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="1" } attributes #1 = { readnone } Shader Disassembly: CALL_FS ; 00000000 84C00000 ALU 19, @6, KC0[CB0:0-32], KC1[] ; 80000006 A04C0000 EXPORT T0.XYZW ; C000203C 95000688 EXPORT T4.XYZW ; C0024000 95200688 CF_END ; 00000000 88000000 PAD ; 00000000 00000000 ALU clause starting at 6: ; MUL_IEEE * T0.W, T1.X, KC0[0].X, ; 80100001 60000110 MULADD_IEEE * T0.W, T1.Y, KC0[1].X, PV.W, ; 80102401 60030CFE MULADD_IEEE * T0.W, T1.Z, KC0[2].X, PV.W, ; 80104801 60030CFE MULADD_IEEE T0.X, T1.W, KC0[3].X, PV.W, ; 00106C01 00030CFE MUL_IEEE * T3.W, T1.X, KC0[0].Z, ; 81100001 60600110 MUL_IEEE T3.Z, T1.X, KC0[0].Y, ; 00900001 40600110 MULADD_IEEE * T3.W, T1.Y, KC0[1].Z, PV.W, ; 81102401 60630CFE MOV_SAT T4.X, T2.X, ; 00000002 80800C90 MULADD_IEEE T5.Z, T1.Z, KC0[2].Z, PV.W, ; 01104801 40A30CFE MULADD_IEEE * T3.W, T1.Y, KC0[1].Y, PV.Z, ; 80902401 606308FE MOV_SAT T4.Y, T2.Y, ; 00000402 A0800C90 MUL_IEEE T3.Z, T1.X, KC0[0].W, ; 01900001 40600110 MULADD_IEEE * T3.W, T1.Z, KC0[2].Y, PV.W, ; 80904801 60630CFE MULADD_IEEE T0.Y, T1.W, KC0[3].Y, PV.W, ; 00906C01 20030CFE MOV_SAT T4.Z, T2.Z, ; 00000802 C0800C90 MULADD_IEEE * T3.W, T1.Y, KC0[1].W, PV.Z, ; 81902401 606308FE MULADD_IEEE T3.Y, T1.Z, KC0[2].W, PV.W, ; 01904801 20630CFE MULADD_IEEE T0.Z, T1.W, KC0[3].Z, T5.Z, ; 01106C01 40030805 MOV_SAT * T4.W, T2.W, BS:VEC_120/SCL_212 ; 80000C02 E0880C90 MULADD_IEEE * T0.W, T1.W, KC0[3].W, PV.Y, ; 81906C01 600304FE ===== SHADER #56 ======================================== VS/CAYMAN/CAYMAN ===== ===== 52 dw ===== 6 gprs ===== 1 stack ========================================= 0000 00000000 84c00000 CALL_FS @0 0002 80000006 a04c0000 ALU 20 @12 KC0[CB0:0-31] 0012 80100001 60000110 1 w: MUL_IEEE R0.w, R1.x, KC0[0].x 0014 80102401 60030cfe 2 w: MULADD_IEEE R0.w, R1.y, KC0[1].x, PV.w 0016 80104801 60030cfe 3 w: MULADD_IEEE R0.w, R1.z, KC0[2].x, PV.w 0018 00106c01 00030cfe 4 x: MULADD_IEEE R0.x, R1.w, KC0[3].x, PV.w 0020 81100001 60600110 w: MUL_IEEE R3.w, R1.x, KC0[0].z 0022 00900001 40600110 5 z: MUL_IEEE R3.z, R1.x, KC0[0].y 0024 81102401 60630cfe w: MULADD_IEEE R3.w, R1.y, KC0[1].z, PV.w 0026 00000002 80800c90 6 x: MOV_sat R4.x, R2.x 0028 01104801 40a30cfe z: MULADD_IEEE R5.z, R1.z, KC0[2].z, PV.w 0030 80902401 606308fe w: MULADD_IEEE R3.w, R1.y, KC0[1].y, PV.z 0032 00000402 a0800c90 7 y: MOV_sat R4.y, R2.y 0034 01900001 40600110 z: MUL_IEEE R3.z, R1.x, KC0[0].w 0036 80904801 60630cfe w: MULADD_IEEE R3.w, R1.z, KC0[2].y, PV.w 0038 00906c01 20030cfe 8 y: MULADD_IEEE R0.y, R1.w, KC0[3].y, PV.w 0040 00000802 c0800c90 z: MOV_sat R4.z, R2.z 0042 81902401 606308fe w: MULADD_IEEE R3.w, R1.y, KC0[1].w, PV.z 0044 01904801 20630cfe 9 y: MULADD_IEEE R3.y, R1.z, KC0[2].w, PV.w 0046 01106c01 40030805 z: MULADD_IEEE R0.z, R1.w, KC0[3].z, R5.z 0048 80000c02 e0880c90 w: MOV_sat R4.w, R2.w VEC_120 0050 81906c01 600304fe 10 w: MULADD_IEEE R0.w, R1.w, KC0[3].w, PV.y 0004 c000203c 95000688 EXPORT_DONE POS 60 R0.xyzw 0006 c0024000 95200688 EXPORT_DONE PARAM 0 R4.xyzw 0008 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #56 OPT ==================================== VS/CAYMAN/CAYMAN ===== ===== 52 dw ===== 3 gprs ===== 1 stack ========================================= 0000 00000000 84c00000 CALL_FS @0 0002 40000005 a0500000 ALU 21 @10 KC0[CB0:0-15] 0010 00900001 4f800110 1 z: MUL_IEEE T0.z, R1.x, KC0[0].y 0012 80100001 6f800110 w: MUL_IEEE T0.w, R1.x, KC0[0].x 0014 01900001 0f800110 2 x: MUL_IEEE T0.x, R1.x, KC0[0].w 0016 01100001 2f800110 y: MUL_IEEE T0.y, R1.x, KC0[0].z 0018 80102401 6f830c7c w: MULADD_IEEE T0.w, R1.y, KC0[1].x, T0.w 0020 01902401 0f83007c 3 x: MULADD_IEEE T0.x, R1.y, KC0[1].w, T0.x 0022 01102401 2f83047c y: MULADD_IEEE T0.y, R1.y, KC0[1].z, T0.y 0024 00902401 4f83087c z: MULADD_IEEE T0.z, R1.y, KC0[1].y, T0.z 0026 80000c01 6fa00c90 w: MOV T1.w, R1.w 0028 01904801 0f83007c 4 x: MULADD_IEEE T0.x, R1.z, KC0[2].w, T0.x 0030 01104801 2f83047c y: MULADD_IEEE T0.y, R1.z, KC0[2].z, T0.y 0032 00904801 4f83087c z: MULADD_IEEE T0.z, R1.z, KC0[2].y, T0.z 0034 80104801 6f830c7c w: MULADD_IEEE T0.w, R1.z, KC0[2].x, T0.w 0036 00000002 80000c90 5 x: MOV_sat R0.x, R2.x 0038 00000402 a0000c90 y: MOV_sat R0.y, R2.y 0040 00000802 c0000c90 z: MOV_sat R0.z, R2.z 0042 80000c02 e0000c90 w: MOV_sat R0.w, R2.w 0044 00106c7d 00230c7c 6 x: MULADD_IEEE R1.x, T1.w, KC0[3].x, T0.w 0046 00906c7d 2023087c y: MULADD_IEEE R1.y, T1.w, KC0[3].y, T0.z 0048 01106c7d 4023047c z: MULADD_IEEE R1.z, T1.w, KC0[3].z, T0.y 0050 81906c7d 6023007c w: MULADD_IEEE R1.w, T1.w, KC0[3].w, T0.x 0004 c000a03c 95000688 EXPORT_DONE POS 60 R1.xyzw 0006 c0004000 95000688 EXPORT_DONE PARAM 0 R0.xyzw 0008 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg) #0 { main_body: %2 = call <4 x float> @llvm.R600.interp.const(i32 0) %3 = extractelement <4 x float> %2, i32 0 %4 = extractelement <4 x float> %2, i32 1 %5 = extractelement <4 x float> %2, i32 2 %6 = extractelement <4 x float> %2, i32 3 %7 = insertelement <4 x float> undef, float %3, i32 0 %8 = insertelement <4 x float> %7, float %4, i32 1 %9 = insertelement <4 x float> %8, float %5, i32 2 %10 = insertelement <4 x float> %9, float %6, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %10, i32 0, i32 0) ret void } ; Function Attrs: readnone declare <4 x float> @llvm.R600.interp.const(i32) #1 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } Shader Disassembly: ALU 3, @4, KC0[], KC1[] ; 00000004 A00C0000 EXPORT T0.XYZW ; C0000000 95200688 CF_END ; 00000000 88000000 PAD ; 00000000 00000000 ALU clause starting at 4: ; INTERP_LOAD_P0 T0.X, ARRAY_BASE, ; 000001C0 00007010 INTERP_LOAD_P0 T0.Y, ARRAY_BASE, ; 000001C0 20007010 INTERP_LOAD_P0 T0.Z, ARRAY_BASE, ; 000001C0 40007010 INTERP_LOAD_P0 * T0.W, ARRAY_BASE, ; 800001C0 60007010 ===== SHADER #57 ======================================== PS/CAYMAN/CAYMAN ===== ===== 16 dw ===== 1 gprs ===== 1 stack ========================================= 0000 00000004 a00c0000 ALU 4 @8 0008 000001c0 00007010 1 x: INTERP_LOAD_P0 R0.x, Param0.x 0010 000001c0 20007010 y: INTERP_LOAD_P0 R0.y, Param0.x 0012 000001c0 40007010 z: INTERP_LOAD_P0 R0.z, Param0.x 0014 800001c0 60007010 w: INTERP_LOAD_P0 R0.w, Param0.x 0002 c0000000 95200688 EXPORT_DONE PIXEL 0 R0.xyzw 0004 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #57 OPT ==================================== PS/CAYMAN/CAYMAN ===== ===== 14 dw ===== 1 gprs ===== 0 stack ========================================= 0000 00000003 a00c0000 ALU 4 @6 0006 000001c0 00007010 1 x: INTERP_LOAD_P0 R0.x, Param0.x 0008 000005c0 20007010 y: INTERP_LOAD_P0 R0.y, Param0.y 0010 000009c0 40007010 z: INTERP_LOAD_P0 R0.z, Param0.z 0012 80000dc0 60007010 w: INTERP_LOAD_P0 R0.w, Param0.w 0002 c0000000 95000688 EXPORT_DONE PIXEL 0 R0.xyzw 0004 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- FRAG DCL IN[0], GENERIC[0], LINEAR DCL OUT[0], COLOR DCL SAMP[0] 0: TEX OUT[0], IN[0], SAMP[0], 2D 1: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg) #0 { main_body: %2 = extractelement <4 x float> %0, i32 0 %3 = extractelement <4 x float> %0, i32 1 %4 = call <2 x float> @llvm.R600.interp.xy(i32 0, float %2, float %3) %5 = call <2 x float> @llvm.R600.interp.zw(i32 0, float %2, float %3) %6 = shufflevector <2 x float> %4, <2 x float> %5, <4 x i32> %7 = extractelement <4 x float> %6, i32 0 %8 = extractelement <4 x float> %6, i32 1 %9 = extractelement <4 x float> %6, i32 2 %10 = extractelement <4 x float> %6, i32 3 %11 = insertelement <4 x float> undef, float %7, i32 0 %12 = insertelement <4 x float> %11, float %8, i32 1 %13 = insertelement <4 x float> %12, float %9, i32 2 %14 = insertelement <4 x float> %13, float %10, i32 3 %15 = extractelement <4 x float> %14, i32 0 %16 = extractelement <4 x float> %14, i32 1 %17 = insertelement <4 x float> undef, float %15, i32 0 %18 = insertelement <4 x float> %17, float %16, i32 1 %19 = insertelement <4 x float> %18, float undef, i32 2 %20 = insertelement <4 x float> %19, float undef, i32 3 %21 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %20, i32 16, i32 0, i32 2) %22 = extractelement <4 x float> %21, i32 0 %23 = extractelement <4 x float> %21, i32 1 %24 = extractelement <4 x float> %21, i32 2 %25 = extractelement <4 x float> %21, i32 3 %26 = insertelement <4 x float> undef, float %22, i32 0 %27 = insertelement <4 x float> %26, float %23, i32 1 %28 = insertelement <4 x float> %27, float %24, i32 2 %29 = insertelement <4 x float> %28, float %25, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %29, i32 0, i32 0) ret void } ; Function Attrs: readnone declare <2 x float> @llvm.R600.interp.xy(i32, float, float) #1 ; Function Attrs: readnone declare <2 x float> @llvm.R600.interp.zw(i32, float, float) #1 ; Function Attrs: readnone declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32, i32) #1 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } Shader Disassembly: ALU 3, @6, KC0[], KC1[] ; 00000006 A00C0000 TEX 0 @4 ; 00000004 80400000 EXPORT T0.XYZW ; C0000000 95200688 CF_END ; 00000000 88000000 Fetch clause starting at 4: ; TEX_SAMPLE T0.XYZW, T0.XY__ RID:16 SID:0 CT:NNNN ; 00001010 F00D1000 FC800000 00000000 ALU clause starting at 6: ; INTERP_XY T0.X, T0.Y, ARRAY_BASE, ; 00380400 00146B10 INTERP_XY T0.Y, T0.X, ARRAY_BASE, ; 00380000 20146B10 INTERP_XY T0.Z (MASKED), T0.Y, ARRAY_BASE, ; 00380400 40146B00 INTERP_XY * T0.W (MASKED), T0.X, ARRAY_BASE, ; 80380000 60146B00 ===== SHADER #58 ======================================== PS/CAYMAN/CAYMAN ===== ===== 20 dw ===== 1 gprs ===== 1 stack ========================================= 0000 00000006 a00c0000 ALU 4 @12 0012 00380400 00146b10 1 x: INTERP_XY R0.x, R0.y, Param0.x VEC_210 0014 00380000 20146b10 y: INTERP_XY R0.y, R0.x, Param0.x VEC_210 0016 00380400 40146b00 z: INTERP_XY __.z, R0.y, Param0.x VEC_210 0018 80380000 60146b00 w: INTERP_XY __.w, R0.x, Param0.x VEC_210 0002 00000004 80400000 TEX 1 @8 0008 00001010 f00d1000 fc800000 SAMPLE R0.xyzw, R0.xy__, RID:16, SID:0 CT:NNNN 0004 c0000000 95200688 EXPORT_DONE PIXEL 0 R0.xyzw 0006 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #58 OPT ==================================== PS/CAYMAN/CAYMAN ===== ===== 20 dw ===== 1 gprs ===== 0 stack ========================================= 0000 00000004 a00c0000 ALU 4 @8 0008 00380400 00146b10 1 x: INTERP_XY R0.x, R0.y, Param0.x VEC_210 0010 00b80000 20146b10 y: INTERP_XY R0.y, R0.x, Param0.y VEC_210 0012 01380400 40146b00 z: INTERP_XY __.z, R0.y, Param0.z VEC_210 0014 81b80000 60146b00 w: INTERP_XY __.w, R0.x, Param0.w VEC_210 0002 00000008 80400000 TEX 1 @16 0016 00001010 f00d1000 fc800000 SAMPLE R0.xyzw, R0.xy__, RID:16, SID:0 CT:NNNN 0004 c0000000 95000688 EXPORT_DONE PIXEL 0 R0.xyzw 0006 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], PERSPECTIVE DCL IN[1], GENERIC[10], PERSPECTIVE DCL IN[2], GENERIC[11], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL TEMP[0..2] IMM[0] FLT32 { 0.0030, 0.0000, 1.0000, 0.0000} 0: TEX TEMP[0].x, IN[1].xyyy, SAMP[0], 2D 1: MOV TEMP[1].x, TEMP[0].xxxx 2: TEX TEMP[0].x, IN[1].zwww, SAMP[0], 2D 3: MOV TEMP[1].y, TEMP[0].xxxx 4: TEX TEMP[0].x, IN[2].xyyy, SAMP[0], 2D 5: MOV TEMP[1].z, TEMP[0].xxxx 6: TEX TEMP[0].x, IN[2].zwww, SAMP[0], 2D 7: MOV TEMP[1].w, TEMP[0].xxxx 8: TEX TEMP[0].x, IN[0].xyyy, SAMP[0], 2D 9: ADD TEMP[2], TEMP[0].xxxx, -TEMP[1] 10: ABS TEMP[0], TEMP[2] 11: SGE TEMP[2], TEMP[0], IMM[0].xxxx 12: DP4 TEMP[0].x, TEMP[2], IMM[0].zzzz 13: SEQ TEMP[1].x, TEMP[0].xxxx, IMM[0].yyyy 14: IF TEMP[1].xxxx :16 15: KILL 16: ENDIF 17: MOV OUT[0], TEMP[2] 18: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg, <4 x float> inreg, <4 x float> inreg) #0 { main_body: %4 = extractelement <4 x float> %0, i32 0 %5 = extractelement <4 x float> %0, i32 1 %6 = call <2 x float> @llvm.R600.interp.xy(i32 0, float %4, float %5) %7 = call <2 x float> @llvm.R600.interp.zw(i32 0, float %4, float %5) %8 = shufflevector <2 x float> %6, <2 x float> %7, <4 x i32> %9 = extractelement <4 x float> %8, i32 0 %10 = extractelement <4 x float> %8, i32 1 %11 = extractelement <4 x float> %0, i32 0 %12 = extractelement <4 x float> %0, i32 1 %13 = call <2 x float> @llvm.R600.interp.xy(i32 1, float %11, float %12) %14 = call <2 x float> @llvm.R600.interp.zw(i32 1, float %11, float %12) %15 = shufflevector <2 x float> %13, <2 x float> %14, <4 x i32> %16 = extractelement <4 x float> %15, i32 0 %17 = extractelement <4 x float> %15, i32 1 %18 = extractelement <4 x float> %15, i32 2 %19 = extractelement <4 x float> %15, i32 3 %20 = extractelement <4 x float> %0, i32 0 %21 = extractelement <4 x float> %0, i32 1 %22 = call <2 x float> @llvm.R600.interp.xy(i32 2, float %20, float %21) %23 = call <2 x float> @llvm.R600.interp.zw(i32 2, float %20, float %21) %24 = shufflevector <2 x float> %22, <2 x float> %23, <4 x i32> %25 = extractelement <4 x float> %24, i32 0 %26 = extractelement <4 x float> %24, i32 1 %27 = extractelement <4 x float> %24, i32 2 %28 = extractelement <4 x float> %24, i32 3 %29 = insertelement <4 x float> undef, float %16, i32 0 %30 = insertelement <4 x float> %29, float %17, i32 1 %31 = insertelement <4 x float> %30, float %17, i32 2 %32 = insertelement <4 x float> %31, float %17, i32 3 %33 = extractelement <4 x float> %32, i32 0 %34 = extractelement <4 x float> %32, i32 1 %35 = insertelement <4 x float> undef, float %33, i32 0 %36 = insertelement <4 x float> %35, float %34, i32 1 %37 = insertelement <4 x float> %36, float undef, i32 2 %38 = insertelement <4 x float> %37, float undef, i32 3 %39 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %38, i32 16, i32 0, i32 2) %40 = extractelement <4 x float> %39, i32 0 %41 = insertelement <4 x float> undef, float %18, i32 0 %42 = insertelement <4 x float> %41, float %19, i32 1 %43 = insertelement <4 x float> %42, float %19, i32 2 %44 = insertelement <4 x float> %43, float %19, i32 3 %45 = extractelement <4 x float> %44, i32 0 %46 = extractelement <4 x float> %44, i32 1 %47 = insertelement <4 x float> undef, float %45, i32 0 %48 = insertelement <4 x float> %47, float %46, i32 1 %49 = insertelement <4 x float> %48, float undef, i32 2 %50 = insertelement <4 x float> %49, float undef, i32 3 %51 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %50, i32 16, i32 0, i32 2) %52 = extractelement <4 x float> %51, i32 0 %53 = insertelement <4 x float> undef, float %25, i32 0 %54 = insertelement <4 x float> %53, float %26, i32 1 %55 = insertelement <4 x float> %54, float %26, i32 2 %56 = insertelement <4 x float> %55, float %26, i32 3 %57 = extractelement <4 x float> %56, i32 0 %58 = extractelement <4 x float> %56, i32 1 %59 = insertelement <4 x float> undef, float %57, i32 0 %60 = insertelement <4 x float> %59, float %58, i32 1 %61 = insertelement <4 x float> %60, float undef, i32 2 %62 = insertelement <4 x float> %61, float undef, i32 3 %63 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %62, i32 16, i32 0, i32 2) %64 = extractelement <4 x float> %63, i32 0 %65 = insertelement <4 x float> undef, float %27, i32 0 %66 = insertelement <4 x float> %65, float %28, i32 1 %67 = insertelement <4 x float> %66, float %28, i32 2 %68 = insertelement <4 x float> %67, float %28, i32 3 %69 = extractelement <4 x float> %68, i32 0 %70 = extractelement <4 x float> %68, i32 1 %71 = insertelement <4 x float> undef, float %69, i32 0 %72 = insertelement <4 x float> %71, float %70, i32 1 %73 = insertelement <4 x float> %72, float undef, i32 2 %74 = insertelement <4 x float> %73, float undef, i32 3 %75 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %74, i32 16, i32 0, i32 2) %76 = extractelement <4 x float> %75, i32 0 %77 = insertelement <4 x float> undef, float %9, i32 0 %78 = insertelement <4 x float> %77, float %10, i32 1 %79 = insertelement <4 x float> %78, float %10, i32 2 %80 = insertelement <4 x float> %79, float %10, i32 3 %81 = extractelement <4 x float> %80, i32 0 %82 = extractelement <4 x float> %80, i32 1 %83 = insertelement <4 x float> undef, float %81, i32 0 %84 = insertelement <4 x float> %83, float %82, i32 1 %85 = insertelement <4 x float> %84, float undef, i32 2 %86 = insertelement <4 x float> %85, float undef, i32 3 %87 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %86, i32 16, i32 0, i32 2) %88 = extractelement <4 x float> %87, i32 0 %89 = fsub float -0.000000e+00, %40 %90 = fadd float %88, %89 %91 = fsub float -0.000000e+00, %52 %92 = fadd float %88, %91 %93 = fsub float -0.000000e+00, %64 %94 = fadd float %88, %93 %95 = fsub float -0.000000e+00, %76 %96 = fadd float %88, %95 %97 = call float @fabs(float %90) %98 = call float @fabs(float %92) %99 = call float @fabs(float %94) %100 = call float @fabs(float %96) %101 = fcmp oge float %97, 0x3F689374C0000000 %102 = select i1 %101, float 1.000000e+00, float 0.000000e+00 %103 = fcmp oge float %98, 0x3F689374C0000000 %104 = select i1 %103, float 1.000000e+00, float 0.000000e+00 %105 = fcmp oge float %99, 0x3F689374C0000000 %106 = select i1 %105, float 1.000000e+00, float 0.000000e+00 %107 = fcmp oge float %100, 0x3F689374C0000000 %108 = select i1 %107, float 1.000000e+00, float 0.000000e+00 %109 = insertelement <4 x float> undef, float %102, i32 0 %110 = insertelement <4 x float> %109, float %104, i32 1 %111 = insertelement <4 x float> %110, float %106, i32 2 %112 = insertelement <4 x float> %111, float %108, i32 3 %113 = call float @llvm.AMDGPU.dp4(<4 x float> %112, <4 x float> ) %114 = fcmp oeq float %113, 0.000000e+00 %115 = select i1 %114, float 1.000000e+00, float 0.000000e+00 %116 = fcmp une float %115, 0.000000e+00 br i1 %116, label %IF, label %ENDIF IF: ; preds = %main_body call void @llvm.AMDGPU.kilp() br label %ENDIF ENDIF: ; preds = %main_body, %IF %117 = insertelement <4 x float> undef, float %102, i32 0 %118 = insertelement <4 x float> %117, float %104, i32 1 %119 = insertelement <4 x float> %118, float %106, i32 2 %120 = insertelement <4 x float> %119, float %108, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %120, i32 0, i32 0) ret void } ; Function Attrs: readnone declare <2 x float> @llvm.R600.interp.xy(i32, float, float) #1 ; Function Attrs: readnone declare <2 x float> @llvm.R600.interp.zw(i32, float, float) #1 ; Function Attrs: readnone declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32, i32) #1 ; Function Attrs: readonly declare float @fabs(float) #2 ; Function Attrs: readnone declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1 declare void @llvm.AMDGPU.kilp() declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } attributes #2 = { readonly } Shader Disassembly: ALU 23, @18, KC0[], KC1[] ; 00000012 A05C0000 TEX 4 @8 ; 00000008 80401000 ALU_PUSH_BEFORE 18, @42, KC0[], KC1[] ; 0000002A A4480000 JUMP @5 POP:1 ; 00000005 82800001 ALU_POP_AFTER 0, @61, KC0[], KC1[] ; 0000003D A8000000 EXPORT T0.XYZW ; C0000000 95200688 CF_END ; 00000000 88000000 PAD ; 00000000 00000000 Fetch clause starting at 8: ; TEX_SAMPLE T3.XYZW, T6.XY__ RID:16 SID:0 CT:NNNN ; 00061010 F00D1003 FC800000 00000000 TEX_SAMPLE T5.XYZW, T5.XY__ RID:16 SID:0 CT:NNNN ; 00051010 F00D1005 FC800000 00000000 TEX_SAMPLE T4.XYZW, T4.XY__ RID:16 SID:0 CT:NNNN ; 00041010 F00D1004 FC800000 00000000 TEX_SAMPLE T1.XYZW, T1.XY__ RID:16 SID:0 CT:NNNN ; 00011010 F00D1001 FC800000 00000000 TEX_SAMPLE T0.XYZW, T2.XY__ RID:16 SID:0 CT:NNNN ; 00021010 F00D1000 FC800000 00000000 ALU clause starting at 18: ; INTERP_XY T1.X, T0.Y, ARRAY_BASE, ; 00380400 00346B10 INTERP_XY T1.Y, T0.X, ARRAY_BASE, ; 00380000 20346B10 INTERP_XY T0.Z (MASKED), T0.Y, ARRAY_BASE, ; 00380400 40146B00 INTERP_XY * T0.W (MASKED), T0.X, ARRAY_BASE, ; 80380000 60146B00 INTERP_XY T2.X, T0.Y, ARRAY_BASE, ; 00382400 00546B10 INTERP_XY T2.Y, T0.X, ARRAY_BASE, ; 00382000 20546B10 INTERP_XY T0.Z (MASKED), T0.Y, ARRAY_BASE, ; 00382400 40146B00 INTERP_XY * T0.W (MASKED), T0.X, ARRAY_BASE, ; 80382000 60146B00 INTERP_ZW T0.X (MASKED), T0.Y, ARRAY_BASE, ; 00382400 00146B80 INTERP_ZW T0.Y (MASKED), T0.X, ARRAY_BASE, ; 00382000 20146B80 INTERP_ZW T3.Z, T0.Y, ARRAY_BASE, ; 00382400 40746B90 INTERP_ZW * T3.W, T0.X, ARRAY_BASE, ; 80382000 60746B90 MOV * T4.X, PV.Z, ; 800008FE 00800C90 INTERP_XY T5.X, T0.Y, ARRAY_BASE, ; 00384400 00B46B10 INTERP_XY T5.Y, T0.X, ARRAY_BASE, ; 00384000 20B46B10 INTERP_XY T0.Z (MASKED), T0.Y, ARRAY_BASE, ; 00384400 40146B00 INTERP_XY * T0.W (MASKED), T0.X, ARRAY_BASE, ; 80384000 60146B00 INTERP_ZW T0.X (MASKED), T0.Y, ARRAY_BASE, ; 00384400 00146B80 INTERP_ZW T0.Y (MASKED), T0.X, ARRAY_BASE, ; 00384000 20146B80 INTERP_ZW T0.Z, T0.Y, ARRAY_BASE, ; 00384400 40146B90 INTERP_ZW * T0.W, T0.X, ARRAY_BASE, ; 80384000 60146B90 MOV T6.X, PV.Z, ; 000008FE 00C00C90 MOV * T4.Y, T3.W, ; 80000C03 20800C90 MOV * T6.Y, T0.W, ; 80000C00 20C00C90 ALU clause starting at 42: ; ADD * T0.W, T1.X, -T0.X, ; 82000001 60000010 SETGE T0.X, |PV.W|, literal.x, ; 001FACFE 00000511 ADD * T2.W, T1.X, -T4.X, ; 82008001 60400010 994352038(3.000000e-03), 0(0.000000e+00) ; 3B449BA6 00000000 SETGE T0.Y, |PV.W|, literal.x, ; 001FACFE 20000511 ADD * T2.W, T1.X, -T5.X, ; 8200A001 60400010 994352038(3.000000e-03), 0(0.000000e+00) ; 3B449BA6 00000000 SETGE T0.Z, |PV.W|, literal.x, ; 001FACFE 40000511 ADD * T1.W, T1.X, -T3.X, ; 82006001 60200010 994352038(3.000000e-03), 0(0.000000e+00) ; 3B449BA6 00000000 SETGE * T0.W, |PV.W|, literal.x, ; 801FACFE 60000511 994352038(3.000000e-03), 0(0.000000e+00) ; 3B449BA6 00000000 DOT4 T1.X, T0.X, 1.0, ; 001F2000 00205F10 DOT4 T1.Y (MASKED), T0.Y, 1.0, ; 001F2400 20205F00 DOT4 T1.Z (MASKED), T0.Z, 1.0, ; 001F2800 40205F00 DOT4 * T1.W (MASKED), T0.W, 1.0, ; 801F2C00 60205F00 SETE * T1.W, PV.X, 0.0, ; 801F00FE 60200410 SETE_DX10 * T1.W, PV.W, 0.0, ; 801F0CFE 60200610 PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002104 ALU clause starting at 61: ; KILLGT * T1.X (MASKED), 1.0, 0.0, ; 801F00F9 00201680 ===== SHADER #60 ======================================== PS/CAYMAN/CAYMAN ===== ===== 124 dw ===== 7 gprs ===== 1 stack ======================================== 0000 00000012 a05c0000 ALU 24 @36 0036 00380400 00346b10 1 x: INTERP_XY R1.x, R0.y, Param0.x VEC_210 0038 00380000 20346b10 y: INTERP_XY R1.y, R0.x, Param0.x VEC_210 0040 00380400 40146b00 z: INTERP_XY __.z, R0.y, Param0.x VEC_210 0042 80380000 60146b00 w: INTERP_XY __.w, R0.x, Param0.x VEC_210 0044 00382400 00546b10 2 x: INTERP_XY R2.x, R0.y, Param1.x VEC_210 0046 00382000 20546b10 y: INTERP_XY R2.y, R0.x, Param1.x VEC_210 0048 00382400 40146b00 z: INTERP_XY __.z, R0.y, Param1.x VEC_210 0050 80382000 60146b00 w: INTERP_XY __.w, R0.x, Param1.x VEC_210 0052 00382400 00146b80 3 x: INTERP_ZW __.x, R0.y, Param1.x VEC_210 0054 00382000 20146b80 y: INTERP_ZW __.y, R0.x, Param1.x VEC_210 0056 00382400 40746b90 z: INTERP_ZW R3.z, R0.y, Param1.x VEC_210 0058 80382000 60746b90 w: INTERP_ZW R3.w, R0.x, Param1.x VEC_210 0060 800008fe 00800c90 4 x: MOV R4.x, PV.z 0062 00384400 00b46b10 5 x: INTERP_XY R5.x, R0.y, Param2.x VEC_210 0064 00384000 20b46b10 y: INTERP_XY R5.y, R0.x, Param2.x VEC_210 0066 00384400 40146b00 z: INTERP_XY __.z, R0.y, Param2.x VEC_210 0068 80384000 60146b00 w: INTERP_XY __.w, R0.x, Param2.x VEC_210 0070 00384400 00146b80 6 x: INTERP_ZW __.x, R0.y, Param2.x VEC_210 0072 00384000 20146b80 y: INTERP_ZW __.y, R0.x, Param2.x VEC_210 0074 00384400 40146b90 z: INTERP_ZW R0.z, R0.y, Param2.x VEC_210 0076 80384000 60146b90 w: INTERP_ZW R0.w, R0.x, Param2.x VEC_210 0078 000008fe 00c00c90 7 x: MOV R6.x, PV.z 0080 80000c03 20800c90 y: MOV R4.y, R3.w 0082 80000c00 20c00c90 8 y: MOV R6.y, R0.w 0002 00000008 80401000 TEX 5 @16 0016 00061010 f00d1003 fc800000 SAMPLE R3.xyzw, R6.xy__, RID:16, SID:0 CT:NNNN 0020 00051010 f00d1005 fc800000 SAMPLE R5.xyzw, R5.xy__, RID:16, SID:0 CT:NNNN 0024 00041010 f00d1004 fc800000 SAMPLE R4.xyzw, R4.xy__, RID:16, SID:0 CT:NNNN 0028 00011010 f00d1001 fc800000 SAMPLE R1.xyzw, R1.xy__, RID:16, SID:0 CT:NNNN 0032 00021010 f00d1000 fc800000 SAMPLE R0.xyzw, R2.xy__, RID:16, SID:0 CT:NNNN 0004 0000002a a4480000 ALU_PUSH_BEFORE 19 @84 0084 82000001 60000010 9 w: ADD R0.w, R1.x, -R0.x 0086 001facfe 00000511 10 x: SETGE R0.x, |PV.w|, [0x3b449ba6 0.003].x 0088 82008001 60400010 w: ADD R2.w, R1.x, -R4.x 0090 3b449ba6 0092 001facfe 20000511 11 y: SETGE R0.y, |PV.w|, [0x3b449ba6 0.003].x 0094 8200a001 60400010 w: ADD R2.w, R1.x, -R5.x 0096 3b449ba6 0098 001facfe 40000511 12 z: SETGE R0.z, |PV.w|, [0x3b449ba6 0.003].x 0100 82006001 60200010 w: ADD R1.w, R1.x, -R3.x 0102 3b449ba6 0104 801facfe 60000511 13 w: SETGE R0.w, |PV.w|, [0x3b449ba6 0.003].x 0106 3b449ba6 0108 001f2000 00205f10 14 x: DOT4 R1.x, R0.x, 1.0 0110 001f2400 20205f00 y: DOT4 __.y, R0.y, 1.0 0112 001f2800 40205f00 z: DOT4 __.z, R0.z, 1.0 0114 801f2c00 60205f00 w: DOT4 __.w, R0.w, 1.0 0116 801f00fe 60200410 15 w: SETE R1.w, PV.x, 0 0118 801f0cfe 60200610 16 w: SETE_DX10 R1.w, PV.w, 0 0120 801f0cfe 00002104 17 M x: PRED_SETE_INT __.x, PV.w, 0 0006 00000005 82800001 JUMP @10 POP:1 0008 0000003d a8000000 ALU_POP_AFTER 1 @122 0122 801f00f9 00201680 18 x: KILLGT __.x, 1.0, 0 0010 c0000000 95200688 EXPORT_DONE PIXEL 0 R0.xyzw 0012 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #60 OPT ==================================== PS/CAYMAN/CAYMAN ===== ===== 100 dw ===== 4 gprs ===== 0 stack ======================================== 0000 00000005 a04c0000 ALU 20 @10 0010 00382400 00346b10 1 x: INTERP_XY R1.x, R0.y, Param1.x VEC_210 0012 00b82000 20346b10 y: INTERP_XY R1.y, R0.x, Param1.y VEC_210 0014 01382400 40146b00 z: INTERP_XY __.z, R0.y, Param1.z VEC_210 0016 81b82000 60146b00 w: INTERP_XY __.w, R0.x, Param1.w VEC_210 0018 00382400 00146b80 2 x: INTERP_ZW __.x, R0.y, Param1.x VEC_210 0020 00b82000 20146b80 y: INTERP_ZW __.y, R0.x, Param1.y VEC_210 0022 01382400 40146b90 z: INTERP_ZW R0.z, R0.y, Param1.z VEC_210 0024 81b82000 60146b90 w: INTERP_ZW R0.w, R0.x, Param1.w VEC_210 0026 00384400 00746b10 3 x: INTERP_XY R3.x, R0.y, Param2.x VEC_210 0028 00b84000 20746b10 y: INTERP_XY R3.y, R0.x, Param2.y VEC_210 0030 01384400 40146b00 z: INTERP_XY __.z, R0.y, Param2.z VEC_210 0032 81b84000 60146b00 w: INTERP_XY __.w, R0.x, Param2.w VEC_210 0034 00380400 00546b10 4 x: INTERP_XY R2.x, R0.y, Param0.x VEC_210 0036 00b80000 20546b10 y: INTERP_XY R2.y, R0.x, Param0.y VEC_210 0038 01380400 40146b00 z: INTERP_XY __.z, R0.y, Param0.z VEC_210 0040 81b80000 60146b00 w: INTERP_XY __.w, R0.x, Param0.w VEC_210 0042 00384400 00146b80 5 x: INTERP_ZW __.x, R0.y, Param2.x VEC_210 0044 00b84000 20146b80 y: INTERP_ZW __.y, R0.x, Param2.y VEC_210 0046 01384400 40346b90 z: INTERP_ZW R1.z, R0.y, Param2.z VEC_210 0048 81b84000 60346b90 w: INTERP_ZW R1.w, R0.x, Param2.w VEC_210 0002 0000001a 80401000 TEX 5 @52 0052 00011010 f003fe01 fda00000 SAMPLE R1.___x, R1.zw__, RID:16, SID:0 CT:NNNN 0056 00021010 f01f8e00 fc800000 SAMPLE R0._x__, R2.xy__, RID:16, SID:0 CT:NNNN 0060 00031010 f01c7e01 fc800000 SAMPLE R1.__x_, R3.xy__, RID:16, SID:0 CT:NNNN 0064 00001010 f01c7e00 fda00000 SAMPLE R0.__x_, R0.zw__, RID:16, SID:0 CT:NNNN 0068 00011010 f01ff000 fc800000 SAMPLE R0.x___, R1.xy__, RID:16, SID:0 CT:NNNN 0004 00000024 a0340000 ALU 14 @72 0072 03002400 0f840010 6 x: ADD T0.x, R0.y, -R1.z VEC_021 0074 03000400 2f800010 y: ADD T0.y, R0.y, -R0.z 0076 02000400 4f800010 z: ADD T0.z, R0.y, -R0.x 0078 83802400 6f800010 w: ADD T0.w, R0.y, -R1.w 0080 001fa87c 00000511 7 x: SETGE R0.x, |T0.z|, [0x3b449ba6 0.003].x 0082 001fa47c 20000511 y: SETGE R0.y, |T0.y|, [0x3b449ba6 0.003].x 0084 001fa07c 40000511 z: SETGE R0.z, |T0.x|, [0x3b449ba6 0.003].x 0086 801fac7c 60000511 w: SETGE R0.w, |T0.w|, [0x3b449ba6 0.003].x 0088 3b449ba6 0090 001f2000 00005f00 8 x: DOT4 __.x, R0.x, 1.0 0092 001f2400 20005f00 y: DOT4 __.y, R0.y, 1.0 0094 001f2800 40005f00 z: DOT4 __.z, R0.z, 1.0 0096 801f2c00 6f805f10 w: DOT4 T0.w, R0.w, 1.0 0098 801f0c7c 00001600 9 x: KILLE __.x, T0.w, 0 0006 c0000000 95000688 EXPORT_DONE PIXEL 0 R0.xyzw 0008 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- FRAG DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg) #0 { main_body: %2 = call <4 x float> @llvm.R600.interp.const(i32 0) %3 = extractelement <4 x float> %2, i32 0 %4 = extractelement <4 x float> %2, i32 1 %5 = extractelement <4 x float> %2, i32 2 %6 = extractelement <4 x float> %2, i32 3 %7 = insertelement <4 x float> undef, float %3, i32 0 %8 = insertelement <4 x float> %7, float %4, i32 1 %9 = insertelement <4 x float> %8, float %5, i32 2 %10 = insertelement <4 x float> %9, float %6, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %10, i32 0, i32 0) ret void } ; Function Attrs: readnone declare <4 x float> @llvm.R600.interp.const(i32) #1 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } Shader Disassembly: ALU 3, @4, KC0[], KC1[] ; 00000004 A00C0000 EXPORT T0.XYZW ; C0000000 95200688 CF_END ; 00000000 88000000 PAD ; 00000000 00000000 ALU clause starting at 4: ; INTERP_LOAD_P0 T0.X, ARRAY_BASE, ; 000001C0 00007010 INTERP_LOAD_P0 T0.Y, ARRAY_BASE, ; 000001C0 20007010 INTERP_LOAD_P0 T0.Z, ARRAY_BASE, ; 000001C0 40007010 INTERP_LOAD_P0 * T0.W, ARRAY_BASE, ; 800001C0 60007010 ===== SHADER #61 ======================================== PS/CAYMAN/CAYMAN ===== ===== 16 dw ===== 1 gprs ===== 1 stack ========================================= 0000 00000004 a00c0000 ALU 4 @8 0008 000001c0 00007010 1 x: INTERP_LOAD_P0 R0.x, Param0.x 0010 000001c0 20007010 y: INTERP_LOAD_P0 R0.y, Param0.x 0012 000001c0 40007010 z: INTERP_LOAD_P0 R0.z, Param0.x 0014 800001c0 60007010 w: INTERP_LOAD_P0 R0.w, Param0.x 0002 c0000000 95200688 EXPORT_DONE PIXEL 0 R0.xyzw 0004 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #61 OPT ==================================== PS/CAYMAN/CAYMAN ===== ===== 14 dw ===== 1 gprs ===== 0 stack ========================================= 0000 00000003 a00c0000 ALU 4 @6 0006 000001c0 00007010 1 x: INTERP_LOAD_P0 R0.x, Param0.x 0008 000005c0 20007010 y: INTERP_LOAD_P0 R0.y, Param0.y 0010 000009c0 40007010 z: INTERP_LOAD_P0 R0.z, Param0.z 0012 80000dc0 60007010 w: INTERP_LOAD_P0 R0.w, Param0.w 0002 c0000000 95000688 EXPORT_DONE PIXEL 0 R0.xyzw 0004 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL SAMP[1] DCL SAMP[2] DCL CONST[0] DCL TEMP[0..6] IMM[0] FLT32 { 0.0000, -0.2500, 0.0061, 0.5000} IMM[1] FLT32 { -1.5000, -2.0000, 0.9000, 1.5000} IMM[2] FLT32 { 2.0000, 1.0000, 4.0000, 33.0000} IMM[3] FLT32 { 8.0000, 0.0000, 0.0000, 0.0000} 0: MOV TEMP[0], IMM[0].xxxx 1: TEX TEMP[1], IN[0].xyyy, SAMP[1], 2D 2: MOV TEMP[2].x, TEMP[1] 3: SNE TEMP[3].x, TEMP[1].yyyy, IMM[0].xxxx 4: IF TEMP[3].xxxx :76 5: MOV TEMP[1].xy, IN[0].xyxx 6: MOV TEMP[4].x, IMM[1].xxxx 7: BGNLOOP :24 8: MUL TEMP[5].x, IMM[1].yyyy, IMM[3].xxxx 9: SLE TEMP[6].x, TEMP[4].xxxx, TEMP[5].xxxx 10: IF TEMP[6].xxxx :12 11: BRK 12: ENDIF 13: MOV TEMP[4].y, IMM[0].xxxx 14: MAD TEMP[3].xyz, CONST[0].xyyy, TEMP[4].xyyy, TEMP[1].xyyy 15: MOV TEMP[3].w, IMM[0].xxxx 16: TXL TEMP[5], TEMP[3], SAMP[2], 2D 17: MOV TEMP[3].x, TEMP[5].yyyy 18: SLT TEMP[6].x, TEMP[5].yyyy, IMM[1].zzzz 19: IF TEMP[6].xxxx :21 20: BRK 21: ENDIF 22: ADD TEMP[6].x, TEMP[4].xxxx, IMM[1].yyyy 23: MOV TEMP[4].x, TEMP[6].xxxx 24: ENDLOOP :7 25: ADD TEMP[1].x, TEMP[4].xxxx, IMM[1].wwww 26: MAD TEMP[6].x, -IMM[2].xxxx, TEMP[3].xxxx, TEMP[1].xxxx 27: MUL TEMP[1].x, IMM[1].yyyy, IMM[3].xxxx 28: MAX TEMP[4].x, TEMP[6].xxxx, TEMP[1].xxxx 29: MOV TEMP[1].x, TEMP[4].xxxx 30: MOV TEMP[3].xy, IN[0].xyxx 31: MOV TEMP[5].x, IMM[1].wwww 32: BGNLOOP :49 33: MUL TEMP[6].x, IMM[2].xxxx, IMM[3].xxxx 34: SGE TEMP[4].x, TEMP[5].xxxx, TEMP[6].xxxx 35: IF TEMP[4].xxxx :37 36: BRK 37: ENDIF 38: MOV TEMP[5].y, IMM[0].xxxx 39: MAD TEMP[4].xyz, CONST[0].xyyy, TEMP[5].xyyy, TEMP[3].xyyy 40: MOV TEMP[4].w, IMM[0].xxxx 41: TXL TEMP[6].xy, TEMP[4], SAMP[2], 2D 42: MOV TEMP[4].x, TEMP[6].yyyy 43: SLT TEMP[0].x, TEMP[6].yyyy, IMM[1].zzzz 44: IF TEMP[0].xxxx :46 45: BRK 46: ENDIF 47: ADD TEMP[6].x, TEMP[5].xxxx, IMM[2].xxxx 48: MOV TEMP[5].x, TEMP[6].xxxx 49: ENDLOOP :32 50: ADD TEMP[3].x, TEMP[5].xxxx, IMM[1].xxxx 51: MAD TEMP[5].x, IMM[2].xxxx, TEMP[4].xxxx, TEMP[3].xxxx 52: MUL TEMP[3].x, IMM[2].xxxx, IMM[3].xxxx 53: MIN TEMP[4].x, TEMP[5].xxxx, TEMP[3].xxxx 54: MOV TEMP[3].x, TEMP[1].xxxx 55: MOV TEMP[3].y, TEMP[4].xxxx 56: MOV TEMP[5].yw, IMM[0].yyyy 57: MOV TEMP[5].x, TEMP[1].xxxx 58: ADD TEMP[1].x, TEMP[4].xxxx, IMM[2].yyyy 59: MOV TEMP[5].z, TEMP[1].xxxx 60: MAD TEMP[1], TEMP[5], CONST[0].xyxy, IN[0].xyxy 61: MOV TEMP[4], TEMP[1].xyyy 62: MOV TEMP[4].w, IMM[0].xxxx 63: TXL TEMP[5].x, TEMP[4], SAMP[2], 2D 64: MOV TEMP[4].x, TEMP[5].xxxx 65: MOV TEMP[5], TEMP[1].zwww 66: MOV TEMP[5].w, IMM[0].xxxx 67: TXL TEMP[1].x, TEMP[5], SAMP[2], 2D 68: MOV TEMP[4].y, TEMP[1].xxxx 69: MUL TEMP[5].xy, IMM[2].zzzz, TEMP[4].xyyy 70: ROUND TEMP[1].xy, TEMP[5].xyyy 71: ABS TEMP[4].xy, TEMP[3].xyyy 72: MAD TEMP[3].xy, IMM[2].wwww, TEMP[1].xyyy, TEMP[4].xyyy 73: MUL TEMP[5].xyz, TEMP[3].xyyy, IMM[0].zzzz 74: MOV TEMP[5].w, IMM[0].xxxx 75: TXL TEMP[0].xy, TEMP[5], SAMP[0], 2D 76: ENDIF 77: SNE TEMP[1].x, TEMP[2].xxxx, IMM[0].xxxx 78: IF TEMP[1].xxxx :151 79: MOV TEMP[1].xy, IN[0].xyxx 80: MOV TEMP[3].x, IMM[1].xxxx 81: BGNLOOP :98 82: MUL TEMP[4].x, IMM[1].yyyy, IMM[3].xxxx 83: SLE TEMP[5].x, TEMP[3].xxxx, TEMP[4].xxxx 84: IF TEMP[5].xxxx :86 85: BRK 86: ENDIF 87: MOV TEMP[3].y, IMM[0].xxxx 88: MAD TEMP[5].xyz, CONST[0].xyyy, TEMP[3].yxxx, TEMP[1].xyyy 89: MOV TEMP[5].w, IMM[0].xxxx 90: TXL TEMP[4], TEMP[5], SAMP[2], 2D 91: MOV TEMP[2].x, TEMP[4].xxxx 92: SLT TEMP[5].x, TEMP[4].xxxx, IMM[1].zzzz 93: IF TEMP[5].xxxx :95 94: BRK 95: ENDIF 96: ADD TEMP[4].x, TEMP[3].xxxx, IMM[1].yyyy 97: MOV TEMP[3].x, TEMP[4].xxxx 98: ENDLOOP :81 99: ADD TEMP[1].x, TEMP[3].xxxx, IMM[1].wwww 100: MAD TEMP[6].x, -IMM[2].xxxx, TEMP[2].xxxx, TEMP[1].xxxx 101: MUL TEMP[1].x, IMM[1].yyyy, IMM[3].xxxx 102: MAX TEMP[3].x, TEMP[6].xxxx, TEMP[1].xxxx 103: MOV TEMP[1].x, TEMP[3].xxxx 104: MOV TEMP[2].xy, IN[0].xyxx 105: MOV TEMP[4].x, IMM[1].wwww 106: BGNLOOP :123 107: MUL TEMP[5].x, IMM[2].xxxx, IMM[3].xxxx 108: SGE TEMP[6].x, TEMP[4].xxxx, TEMP[5].xxxx 109: IF TEMP[6].xxxx :111 110: BRK 111: ENDIF 112: MOV TEMP[4].y, IMM[0].xxxx 113: MAD TEMP[5].xyz, CONST[0].xyyy, TEMP[4].yxxx, TEMP[2].xyyy 114: MOV TEMP[5].w, IMM[0].xxxx 115: TXL TEMP[6], TEMP[5], SAMP[2], 2D 116: MOV TEMP[3].x, TEMP[6].xxxx 117: SLT TEMP[5].x, TEMP[6].xxxx, IMM[1].zzzz 118: IF TEMP[5].xxxx :120 119: BRK 120: ENDIF 121: ADD TEMP[6].x, TEMP[4].xxxx, IMM[2].xxxx 122: MOV TEMP[4].x, TEMP[6].xxxx 123: ENDLOOP :106 124: ADD TEMP[2].x, TEMP[4].xxxx, IMM[1].xxxx 125: MAD TEMP[4].x, IMM[2].xxxx, TEMP[3].xxxx, TEMP[2].xxxx 126: MUL TEMP[2].x, IMM[2].xxxx, IMM[3].xxxx 127: MIN TEMP[3].x, TEMP[4].xxxx, TEMP[2].xxxx 128: MOV TEMP[2].x, TEMP[1].xxxx 129: MOV TEMP[2].y, TEMP[3].xxxx 130: MOV TEMP[4].xz, IMM[0].yyyy 131: MOV TEMP[4].y, TEMP[1].xxxx 132: ADD TEMP[1].x, TEMP[3].xxxx, IMM[2].yyyy 133: MOV TEMP[4].w, TEMP[1].xxxx 134: MAD TEMP[1], TEMP[4], CONST[0].xyxy, IN[0].xyxy 135: MOV TEMP[3], TEMP[1].xyyy 136: MOV TEMP[3].w, IMM[0].xxxx 137: TXL TEMP[4].y, TEMP[3], SAMP[2], 2D 138: MOV TEMP[3].x, TEMP[4].yyyy 139: MOV TEMP[4], TEMP[1].zwww 140: MOV TEMP[4].w, IMM[0].xxxx 141: TXL TEMP[1].y, TEMP[4], SAMP[2], 2D 142: MOV TEMP[3].y, TEMP[1].yyyy 143: MUL TEMP[4].xy, IMM[2].zzzz, TEMP[3].xyyy 144: ROUND TEMP[1].xy, TEMP[4].xyyy 145: ABS TEMP[3].xy, TEMP[2].xyyy 146: MAD TEMP[2].xy, IMM[2].wwww, TEMP[1].xyyy, TEMP[3].xyyy 147: MUL TEMP[3].xyz, TEMP[2].xyyy, IMM[0].zzzz 148: MOV TEMP[3].w, IMM[0].xxxx 149: TXL TEMP[1].xy, TEMP[3], SAMP[0], 2D 150: MOV TEMP[0].zw, TEMP[1].yyxy 151: ENDIF 152: MOV OUT[0], TEMP[0] 153: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg) #0 { main_body: %2 = extractelement <4 x float> %0, i32 0 %3 = extractelement <4 x float> %0, i32 1 %4 = call <2 x float> @llvm.R600.interp.xy(i32 0, float %2, float %3) %5 = call <2 x float> @llvm.R600.interp.zw(i32 0, float %2, float %3) %6 = shufflevector <2 x float> %4, <2 x float> %5, <4 x i32> %7 = extractelement <4 x float> %6, i32 0 %8 = extractelement <4 x float> %6, i32 1 %9 = insertelement <4 x float> undef, float %7, i32 0 %10 = insertelement <4 x float> %9, float %8, i32 1 %11 = insertelement <4 x float> %10, float %8, i32 2 %12 = insertelement <4 x float> %11, float %8, i32 3 %13 = extractelement <4 x float> %12, i32 0 %14 = extractelement <4 x float> %12, i32 1 %15 = insertelement <4 x float> undef, float %13, i32 0 %16 = insertelement <4 x float> %15, float %14, i32 1 %17 = insertelement <4 x float> %16, float undef, i32 2 %18 = insertelement <4 x float> %17, float undef, i32 3 %19 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %18, i32 17, i32 1, i32 2) %20 = extractelement <4 x float> %19, i32 0 %21 = extractelement <4 x float> %19, i32 1 %22 = fcmp une float %21, 0.000000e+00 %23 = select i1 %22, float 1.000000e+00, float 0.000000e+00 %24 = fcmp une float %23, 0.000000e+00 br i1 %24, label %LOOP, label %ENDIF ENDIF: ; preds = %main_body, %ENDLOOP34 %temp.0 = phi float [ %113, %ENDLOOP34 ], [ 0.000000e+00, %main_body ] %temp1.0 = phi float [ %114, %ENDLOOP34 ], [ 0.000000e+00, %main_body ] %25 = fcmp une float %20, 0.000000e+00 %26 = select i1 %25, float 1.000000e+00, float 0.000000e+00 %27 = fcmp une float %26, 0.000000e+00 br i1 %27, label %LOOP46, label %ENDIF42 LOOP: ; preds = %main_body, %ENDIF31 %temp12.0 = phi float [ %53, %ENDIF31 ], [ %23, %main_body ] %temp16.0 = phi float [ %57, %ENDIF31 ], [ -1.500000e+00, %main_body ] %28 = fcmp ole float %temp16.0, -1.600000e+01 %29 = select i1 %28, float 1.000000e+00, float 0.000000e+00 %30 = fcmp une float %29, 0.000000e+00 br i1 %30, label %ENDLOOP, label %ENDIF28 ENDLOOP: ; preds = %ENDIF28, %LOOP %temp12.1 = phi float [ %temp12.0, %LOOP ], [ %53, %ENDIF28 ] %31 = fadd float %temp16.0, 1.500000e+00 %32 = fmul float -2.000000e+00, %temp12.1 %33 = fadd float %32, %31 %34 = fcmp uge float %33, -1.600000e+01 %35 = select i1 %34, float %33, float -1.600000e+01 br label %LOOP35 ENDIF28: ; preds = %LOOP %36 = load <4 x float> addrspace(8)* null %37 = extractelement <4 x float> %36, i32 0 %38 = fmul float %37, %temp16.0 %39 = fadd float %38, %7 %40 = load <4 x float> addrspace(8)* null %41 = extractelement <4 x float> %40, i32 1 %42 = fmul float %41, 0.000000e+00 %43 = fadd float %42, %8 %44 = load <4 x float> addrspace(8)* null %45 = extractelement <4 x float> %44, i32 1 %46 = fmul float %45, 0.000000e+00 %47 = fadd float %46, %8 %48 = insertelement <4 x float> undef, float %39, i32 0 %49 = insertelement <4 x float> %48, float %43, i32 1 %50 = insertelement <4 x float> %49, float %47, i32 2 %51 = insertelement <4 x float> %50, float 0.000000e+00, i32 3 %52 = call <4 x float> @llvm.AMDGPU.txl(<4 x float> %51, i32 18, i32 2, i32 2) %53 = extractelement <4 x float> %52, i32 1 %54 = fcmp olt float %53, 0x3FECCCCCC0000000 %55 = select i1 %54, float 1.000000e+00, float 0.000000e+00 %56 = fcmp une float %55, 0.000000e+00 br i1 %56, label %ENDLOOP, label %ENDIF31 ENDIF31: ; preds = %ENDIF28 %57 = fadd float %temp16.0, -2.000000e+00 br label %LOOP LOOP35: ; preds = %ENDIF39, %ENDLOOP %temp20.0 = phi float [ 1.500000e+00, %ENDLOOP ], [ %136, %ENDIF39 ] %58 = fcmp oge float %temp20.0, 1.600000e+01 %59 = select i1 %58, float 1.000000e+00, float 0.000000e+00 %60 = fcmp une float %59, 0.000000e+00 br i1 %60, label %ENDLOOP34, label %ENDIF36 ENDLOOP34: ; preds = %ENDIF36, %LOOP35 %temp16.1 = phi float [ %59, %LOOP35 ], [ %132, %ENDIF36 ] %61 = fadd float %temp20.0, -1.500000e+00 %62 = fmul float 2.000000e+00, %temp16.1 %63 = fadd float %62, %61 %64 = fcmp uge float %63, 1.600000e+01 %65 = select i1 %64, float 1.600000e+01, float %63 %66 = fadd float %65, 1.000000e+00 %67 = load <4 x float> addrspace(8)* null %68 = extractelement <4 x float> %67, i32 0 %69 = fmul float %35, %68 %70 = fadd float %69, %7 %71 = load <4 x float> addrspace(8)* null %72 = extractelement <4 x float> %71, i32 1 %73 = fmul float -2.500000e-01, %72 %74 = fadd float %73, %8 %75 = load <4 x float> addrspace(8)* null %76 = extractelement <4 x float> %75, i32 0 %77 = fmul float %66, %76 %78 = fadd float %77, %7 %79 = load <4 x float> addrspace(8)* null %80 = extractelement <4 x float> %79, i32 1 %81 = fmul float -2.500000e-01, %80 %82 = fadd float %81, %8 %83 = insertelement <4 x float> undef, float %70, i32 0 %84 = insertelement <4 x float> %83, float %74, i32 1 %85 = insertelement <4 x float> %84, float %74, i32 2 %86 = insertelement <4 x float> %85, float 0.000000e+00, i32 3 %87 = call <4 x float> @llvm.AMDGPU.txl(<4 x float> %86, i32 18, i32 2, i32 2) %88 = extractelement <4 x float> %87, i32 0 %89 = insertelement <4 x float> undef, float %78, i32 0 %90 = insertelement <4 x float> %89, float %82, i32 1 %91 = insertelement <4 x float> %90, float %82, i32 2 %92 = insertelement <4 x float> %91, float 0.000000e+00, i32 3 %93 = call <4 x float> @llvm.AMDGPU.txl(<4 x float> %92, i32 18, i32 2, i32 2) %94 = extractelement <4 x float> %93, i32 0 %95 = fmul float 4.000000e+00, %88 %96 = fmul float 4.000000e+00, %94 %97 = call float @llvm.AMDIL.round.nearest.(float %95) %98 = call float @llvm.AMDIL.round.nearest.(float %96) %99 = call float @fabs(float %35) %100 = call float @fabs(float %65) %101 = fmul float 3.300000e+01, %97 %102 = fadd float %101, %99 %103 = fmul float 3.300000e+01, %98 %104 = fadd float %103, %100 %105 = fmul float %102, 0x3F78F9C140000000 %106 = fmul float %104, 0x3F78F9C140000000 %107 = fmul float %104, 0x3F78F9C140000000 %108 = insertelement <4 x float> undef, float %105, i32 0 %109 = insertelement <4 x float> %108, float %106, i32 1 %110 = insertelement <4 x float> %109, float %107, i32 2 %111 = insertelement <4 x float> %110, float 0.000000e+00, i32 3 %112 = call <4 x float> @llvm.AMDGPU.txl(<4 x float> %111, i32 16, i32 0, i32 2) %113 = extractelement <4 x float> %112, i32 0 %114 = extractelement <4 x float> %112, i32 1 br label %ENDIF ENDIF36: ; preds = %LOOP35 %115 = load <4 x float> addrspace(8)* null %116 = extractelement <4 x float> %115, i32 0 %117 = fmul float %116, %temp20.0 %118 = fadd float %117, %7 %119 = load <4 x float> addrspace(8)* null %120 = extractelement <4 x float> %119, i32 1 %121 = fmul float %120, 0.000000e+00 %122 = fadd float %121, %8 %123 = load <4 x float> addrspace(8)* null %124 = extractelement <4 x float> %123, i32 1 %125 = fmul float %124, 0.000000e+00 %126 = fadd float %125, %8 %127 = insertelement <4 x float> undef, float %118, i32 0 %128 = insertelement <4 x float> %127, float %122, i32 1 %129 = insertelement <4 x float> %128, float %126, i32 2 %130 = insertelement <4 x float> %129, float 0.000000e+00, i32 3 %131 = call <4 x float> @llvm.AMDGPU.txl(<4 x float> %130, i32 18, i32 2, i32 2) %132 = extractelement <4 x float> %131, i32 1 %133 = fcmp olt float %132, 0x3FECCCCCC0000000 %134 = select i1 %133, float 1.000000e+00, float 0.000000e+00 %135 = fcmp une float %134, 0.000000e+00 br i1 %135, label %ENDLOOP34, label %ENDIF39 ENDIF39: ; preds = %ENDIF36 %136 = fadd float %temp20.0, 2.000000e+00 br label %LOOP35 ENDIF42: ; preds = %ENDIF, %ENDLOOP53 %temp2.0 = phi float [ %226, %ENDLOOP53 ], [ 0.000000e+00, %ENDIF ] %temp3.0 = phi float [ %227, %ENDLOOP53 ], [ 0.000000e+00, %ENDIF ] %137 = insertelement <4 x float> undef, float %temp.0, i32 0 %138 = insertelement <4 x float> %137, float %temp1.0, i32 1 %139 = insertelement <4 x float> %138, float %temp2.0, i32 2 %140 = insertelement <4 x float> %139, float %temp3.0, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %140, i32 0, i32 0) ret void LOOP46: ; preds = %ENDIF, %ENDIF50 %temp8.0 = phi float [ %166, %ENDIF50 ], [ %20, %ENDIF ] %temp12.2 = phi float [ %170, %ENDIF50 ], [ -1.500000e+00, %ENDIF ] %141 = fcmp ole float %temp12.2, -1.600000e+01 %142 = select i1 %141, float 1.000000e+00, float 0.000000e+00 %143 = fcmp une float %142, 0.000000e+00 br i1 %143, label %ENDLOOP45, label %ENDIF47 ENDLOOP45: ; preds = %ENDIF47, %LOOP46 %temp8.1 = phi float [ %temp8.0, %LOOP46 ], [ %166, %ENDIF47 ] %144 = fadd float %temp12.2, 1.500000e+00 %145 = fmul float -2.000000e+00, %temp8.1 %146 = fadd float %145, %144 %147 = fcmp uge float %146, -1.600000e+01 %148 = select i1 %147, float %146, float -1.600000e+01 br label %LOOP54 ENDIF47: ; preds = %LOOP46 %149 = load <4 x float> addrspace(8)* null %150 = extractelement <4 x float> %149, i32 0 %151 = fmul float %150, 0.000000e+00 %152 = fadd float %151, %7 %153 = load <4 x float> addrspace(8)* null %154 = extractelement <4 x float> %153, i32 1 %155 = fmul float %154, %temp12.2 %156 = fadd float %155, %8 %157 = load <4 x float> addrspace(8)* null %158 = extractelement <4 x float> %157, i32 1 %159 = fmul float %158, %temp12.2 %160 = fadd float %159, %8 %161 = insertelement <4 x float> undef, float %152, i32 0 %162 = insertelement <4 x float> %161, float %156, i32 1 %163 = insertelement <4 x float> %162, float %160, i32 2 %164 = insertelement <4 x float> %163, float 0.000000e+00, i32 3 %165 = call <4 x float> @llvm.AMDGPU.txl(<4 x float> %164, i32 18, i32 2, i32 2) %166 = extractelement <4 x float> %165, i32 0 %167 = fcmp olt float %166, 0x3FECCCCCC0000000 %168 = select i1 %167, float 1.000000e+00, float 0.000000e+00 %169 = fcmp une float %168, 0.000000e+00 br i1 %169, label %ENDLOOP45, label %ENDIF50 ENDIF50: ; preds = %ENDIF47 %170 = fadd float %temp12.2, -2.000000e+00 br label %LOOP46 LOOP54: ; preds = %ENDIF58, %ENDLOOP45 %temp12.3 = phi float [ %148, %ENDLOOP45 ], [ %245, %ENDIF58 ] %temp16.2 = phi float [ 1.500000e+00, %ENDLOOP45 ], [ %249, %ENDIF58 ] %171 = fcmp oge float %temp16.2, 1.600000e+01 %172 = select i1 %171, float 1.000000e+00, float 0.000000e+00 %173 = fcmp une float %172, 0.000000e+00 br i1 %173, label %ENDLOOP53, label %ENDIF55 ENDLOOP53: ; preds = %ENDIF55, %LOOP54 %temp12.4 = phi float [ %temp12.3, %LOOP54 ], [ %245, %ENDIF55 ] %174 = fadd float %temp16.2, -1.500000e+00 %175 = fmul float 2.000000e+00, %temp12.4 %176 = fadd float %175, %174 %177 = fcmp uge float %176, 1.600000e+01 %178 = select i1 %177, float 1.600000e+01, float %176 %179 = fadd float %178, 1.000000e+00 %180 = load <4 x float> addrspace(8)* null %181 = extractelement <4 x float> %180, i32 0 %182 = fmul float -2.500000e-01, %181 %183 = fadd float %182, %7 %184 = load <4 x float> addrspace(8)* null %185 = extractelement <4 x float> %184, i32 1 %186 = fmul float %148, %185 %187 = fadd float %186, %8 %188 = load <4 x float> addrspace(8)* null %189 = extractelement <4 x float> %188, i32 0 %190 = fmul float -2.500000e-01, %189 %191 = fadd float %190, %7 %192 = load <4 x float> addrspace(8)* null %193 = extractelement <4 x float> %192, i32 1 %194 = fmul float %179, %193 %195 = fadd float %194, %8 %196 = insertelement <4 x float> undef, float %183, i32 0 %197 = insertelement <4 x float> %196, float %187, i32 1 %198 = insertelement <4 x float> %197, float %187, i32 2 %199 = insertelement <4 x float> %198, float 0.000000e+00, i32 3 %200 = call <4 x float> @llvm.AMDGPU.txl(<4 x float> %199, i32 18, i32 2, i32 2) %201 = extractelement <4 x float> %200, i32 1 %202 = insertelement <4 x float> undef, float %191, i32 0 %203 = insertelement <4 x float> %202, float %195, i32 1 %204 = insertelement <4 x float> %203, float %195, i32 2 %205 = insertelement <4 x float> %204, float 0.000000e+00, i32 3 %206 = call <4 x float> @llvm.AMDGPU.txl(<4 x float> %205, i32 18, i32 2, i32 2) %207 = extractelement <4 x float> %206, i32 1 %208 = fmul float 4.000000e+00, %201 %209 = fmul float 4.000000e+00, %207 %210 = call float @llvm.AMDIL.round.nearest.(float %208) %211 = call float @llvm.AMDIL.round.nearest.(float %209) %212 = call float @fabs(float %148) %213 = call float @fabs(float %178) %214 = fmul float 3.300000e+01, %210 %215 = fadd float %214, %212 %216 = fmul float 3.300000e+01, %211 %217 = fadd float %216, %213 %218 = fmul float %215, 0x3F78F9C140000000 %219 = fmul float %217, 0x3F78F9C140000000 %220 = fmul float %217, 0x3F78F9C140000000 %221 = insertelement <4 x float> undef, float %218, i32 0 %222 = insertelement <4 x float> %221, float %219, i32 1 %223 = insertelement <4 x float> %222, float %220, i32 2 %224 = insertelement <4 x float> %223, float 0.000000e+00, i32 3 %225 = call <4 x float> @llvm.AMDGPU.txl(<4 x float> %224, i32 16, i32 0, i32 2) %226 = extractelement <4 x float> %225, i32 0 %227 = extractelement <4 x float> %225, i32 1 br label %ENDIF42 ENDIF55: ; preds = %LOOP54 %228 = load <4 x float> addrspace(8)* null %229 = extractelement <4 x float> %228, i32 0 %230 = fmul float %229, 0.000000e+00 %231 = fadd float %230, %7 %232 = load <4 x float> addrspace(8)* null %233 = extractelement <4 x float> %232, i32 1 %234 = fmul float %233, %temp16.2 %235 = fadd float %234, %8 %236 = load <4 x float> addrspace(8)* null %237 = extractelement <4 x float> %236, i32 1 %238 = fmul float %237, %temp16.2 %239 = fadd float %238, %8 %240 = insertelement <4 x float> undef, float %231, i32 0 %241 = insertelement <4 x float> %240, float %235, i32 1 %242 = insertelement <4 x float> %241, float %239, i32 2 %243 = insertelement <4 x float> %242, float 0.000000e+00, i32 3 %244 = call <4 x float> @llvm.AMDGPU.txl(<4 x float> %243, i32 18, i32 2, i32 2) %245 = extractelement <4 x float> %244, i32 0 %246 = fcmp olt float %245, 0x3FECCCCCC0000000 %247 = select i1 %246, float 1.000000e+00, float 0.000000e+00 %248 = fcmp une float %247, 0.000000e+00 br i1 %248, label %ENDLOOP53, label %ENDIF58 ENDIF58: ; preds = %ENDIF55 %249 = fadd float %temp16.2, 2.000000e+00 br label %LOOP54 } ; Function Attrs: readnone declare <2 x float> @llvm.R600.interp.xy(i32, float, float) #1 ; Function Attrs: readnone declare <2 x float> @llvm.R600.interp.zw(i32, float, float) #1 ; Function Attrs: readnone declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32, i32) #1 ; Function Attrs: readnone declare <4 x float> @llvm.AMDGPU.txl(<4 x float>, i32, i32, i32) #1 ; Function Attrs: readnone declare float @llvm.AMDIL.round.nearest.(float) #1 ; Function Attrs: readonly declare float @fabs(float) #2 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } attributes #2 = { readonly } Shader Disassembly: ALU 3, @122, KC0[], KC1[] ; 0000007A A00C0000 TEX 0 @100 ; 00000064 80400000 ALU_PUSH_BEFORE 2, @126, KC0[], KC1[] ; 0000007E A4080000 JUMP @5 POP:0 ; 00000005 82800000 ALU 2, @129, KC0[], KC1[] ; 00000081 A0080000 ELSE @48 POP:1 ; 00000030 83400001 ALU 1, @132, KC0[], KC1[] ; 00000084 A0040000 LOOP_START_DX10 @25 ; 00000019 81800000 ALU_PUSH_BEFORE 4, @134, KC0[], KC1[] ; 00000086 A4100000 JUMP @11 POP:0 ; 0000000B 82800000 ALU 1, @139, KC0[], KC1[] ; 0000008B A0040000 ELSE @20 POP:1 ; 00000014 83400001 ALU 1, @141, KC0[CB0:0-32], KC1[] ; 8000008D A0040000 TEX 0 @102 ; 00000066 80400000 ALU_PUSH_BEFORE 3, @143, KC0[], KC1[] ; 0000008F A40C0000 JUMP @17 POP:0 ; 00000011 82800000 ALU 1, @147, KC0[], KC1[] ; 00000093 A0040000 ELSE @19 POP:1 ; 00000013 83400001 ALU_POP_AFTER 2, @149, KC0[], KC1[] ; 00000095 A8080000 POP @20 POP:1 ; 00000014 83800001 ALU_PUSH_BEFORE 4, @152, KC0[], KC1[] ; 00000098 A4100000 JUMP @24 POP:1 ; 00000018 82800001 LOOP_BREAK @24 ; 00000018 82400000 POP @24 POP:1 ; 00000018 83800001 END_LOOP @8 ; 00000008 81400000 ALU 6, @157, KC0[], KC1[] ; 0000009D A0180000 LOOP_START_DX10 @44 ; 0000002C 81800000 ALU_PUSH_BEFORE 4, @164, KC0[], KC1[] ; 000000A4 A4100000 JUMP @30 POP:0 ; 0000001E 82800000 ALU 1, @169, KC0[], KC1[] ; 000000A9 A0040000 ELSE @39 POP:1 ; 00000027 83400001 ALU 1, @171, KC0[CB0:0-32], KC1[] ; 800000AB A0040000 TEX 0 @104 ; 00000068 80400000 ALU_PUSH_BEFORE 3, @173, KC0[], KC1[] ; 000000AD A40C0000 JUMP @36 POP:0 ; 00000024 82800000 ALU 1, @177, KC0[], KC1[] ; 000000B1 A0040000 ELSE @38 POP:1 ; 00000026 83400001 ALU_POP_AFTER 2, @179, KC0[], KC1[] ; 000000B3 A8080000 POP @39 POP:1 ; 00000027 83800001 ALU_PUSH_BEFORE 4, @182, KC0[], KC1[] ; 000000B6 A4100000 JUMP @43 POP:1 ; 0000002B 82800001 LOOP_BREAK @43 ; 0000002B 82400000 POP @43 POP:1 ; 0000002B 83800001 END_LOOP @27 ; 0000001B 81400000 ALU 11, @187, KC0[CB0:0-32], KC1[] ; 800000BB A02C0000 TEX 1 @106 ; 0000006A 80400400 ALU_POP_AFTER 14, @199, KC0[], KC1[] ; 000000C7 A8380000 TEX 0 @110 ; 0000006E 80400000 ALU_PUSH_BEFORE 2, @214, KC0[], KC1[] ; 000000D6 A4080000 JUMP @51 POP:0 ; 00000033 82800000 ALU 2, @217, KC0[], KC1[] ; 000000D9 A0080000 ELSE @96 POP:1 ; 00000060 83400001 ALU 1, @220, KC0[], KC1[] ; 000000DC A0040000 LOOP_START_DX10 @71 ; 00000047 81800000 ALU_PUSH_BEFORE 4, @222, KC0[], KC1[] ; 000000DE A4100000 JUMP @57 POP:0 ; 00000039 82800000 ALU 1, @227, KC0[], KC1[] ; 000000E3 A0040000 ELSE @66 POP:1 ; 00000042 83400001 ALU 1, @229, KC0[CB0:0-32], KC1[] ; 800000E5 A0040000 TEX 0 @112 ; 00000070 80400000 ALU_PUSH_BEFORE 3, @231, KC0[], KC1[] ; 000000E7 A40C0000 JUMP @63 POP:0 ; 0000003F 82800000 ALU 1, @235, KC0[], KC1[] ; 000000EB A0040000 ELSE @65 POP:1 ; 00000041 83400001 ALU_POP_AFTER 2, @237, KC0[], KC1[] ; 000000ED A8080000 POP @66 POP:1 ; 00000042 83800001 ALU_PUSH_BEFORE 4, @240, KC0[], KC1[] ; 000000F0 A4100000 JUMP @70 POP:1 ; 00000046 82800001 LOOP_BREAK @70 ; 00000046 82400000 POP @70 POP:1 ; 00000046 83800001 END_LOOP @54 ; 00000036 81400000 ALU 8, @245, KC0[], KC1[] ; 000000F5 A0200000 LOOP_START_DX10 @90 ; 0000005A 81800000 ALU_PUSH_BEFORE 4, @254, KC0[], KC1[] ; 000000FE A4100000 JUMP @76 POP:0 ; 0000004C 82800000 ALU 1, @259, KC0[], KC1[] ; 00000103 A0040000 ELSE @85 POP:1 ; 00000055 83400001 ALU 1, @261, KC0[CB0:0-32], KC1[] ; 80000105 A0040000 TEX 0 @114 ; 00000072 80400000 ALU_PUSH_BEFORE 3, @263, KC0[], KC1[] ; 00000107 A40C0000 JUMP @82 POP:0 ; 00000052 82800000 ALU 1, @267, KC0[], KC1[] ; 0000010B A0040000 ELSE @84 POP:1 ; 00000054 83400001 ALU_POP_AFTER 3, @269, KC0[], KC1[] ; 0000010D A80C0000 POP @85 POP:1 ; 00000055 83800001 ALU_PUSH_BEFORE 4, @273, KC0[], KC1[] ; 00000111 A4100000 JUMP @89 POP:1 ; 00000059 82800001 LOOP_BREAK @89 ; 00000059 82400000 POP @89 POP:1 ; 00000059 83800001 END_LOOP @73 ; 00000049 81400000 ALU 2, @278, KC0[CB0:0-32], KC1[] ; 80000116 A0080000 TEX 0 @116 ; 00000074 80400000 ALU 8, @281, KC0[CB0:0-32], KC1[] ; 80000119 A0200000 TEX 0 @118 ; 00000076 80400000 ALU_POP_AFTER 14, @290, KC0[], KC1[] ; 00000122 A8380000 TEX 0 @120 ; 00000078 80400000 ALU 1, @305, KC0[], KC1[] ; 00000131 A0040000 EXPORT T2.XYZW ; C0010000 95200688 CF_END ; 00000000 88000000 PAD ; 00000000 00000000 Fetch clause starting at 100: ; TEX_SAMPLE T1.XYZW, T0.XY__ RID:17 SID:1 CT:NNNN ; 00001110 F00D1001 FC808000 00000000 Fetch clause starting at 102: ; TEX_SAMPLE_L T2.XYZW, T2.XYY0 RID:18 SID:2 CT:NNNN ; 00021211 F00D1002 84810000 00000000 Fetch clause starting at 104: ; TEX_SAMPLE_L T3.XYZW, T3.XYY0 RID:18 SID:2 CT:NNNN ; 00031211 F00D1003 84810000 00000000 Fetch clause starting at 106: ; TEX_SAMPLE_L T5.XYZW, T5.XYY0 RID:18 SID:2 CT:NNNN ; 00051211 F00D1005 84810000 00000000 TEX_SAMPLE_L T4.XYZW, T4.XYY0 RID:18 SID:2 CT:NNNN ; 00041211 F00D1004 84810000 00000000 Fetch clause starting at 110: ; TEX_SAMPLE_L T2.XYZW, T2.XYY0 RID:16 SID:0 CT:NNNN ; 00021011 F00D1002 84800000 00000000 Fetch clause starting at 112: ; TEX_SAMPLE_L T1.XYZW, T1.XYY0 RID:18 SID:2 CT:NNNN ; 00011211 F00D1001 84810000 00000000 Fetch clause starting at 114: ; TEX_SAMPLE_L T3.XYZW, T3.XYY0 RID:18 SID:2 CT:NNNN ; 00031211 F00D1003 84810000 00000000 Fetch clause starting at 116: ; TEX_SAMPLE_L T5.XYZW, T4.XYY0 RID:18 SID:2 CT:NNNN ; 00041211 F00D1005 84810000 00000000 Fetch clause starting at 118: ; TEX_SAMPLE_L T0.XYZW, T4.XYY0 RID:18 SID:2 CT:NNNN ; 00041211 F00D1000 84810000 00000000 Fetch clause starting at 120: ; TEX_SAMPLE_L T0.XYZW, T1.XYY0 RID:16 SID:0 CT:NNNN ; 00011011 F00D1000 84800000 00000000 ALU clause starting at 122: ; INTERP_XY T0.X, T0.Y, ARRAY_BASE, ; 00380400 00146B10 INTERP_XY T0.Y, T0.X, ARRAY_BASE, ; 00380000 20146B10 INTERP_XY T0.Z (MASKED), T0.Y, ARRAY_BASE, ; 00380400 40146B00 INTERP_XY * T0.W (MASKED), T0.X, ARRAY_BASE, ; 80380000 60146B00 ALU clause starting at 126: ; SETNE * T2.Y, T1.Y, 0.0, ; 801F0401 20400590 SETNE_DX10 * T3.W, PV.Y, 0.0, ; 801F04FE 60600790 PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002104 ALU clause starting at 129: ; MOV * T2.Y, literal.x, ; 800000FD 20400C90 0(0.000000e+00), 0(0.000000e+00) ; 00000000 00000000 MOV * T2.X, PV.Y, ; 800004FE 00400C90 ALU clause starting at 132: ; MOV * T3.Z, literal.x, ; 800000FD 40600C90 -1077936128(-1.500000e+00), 0(0.000000e+00) ; BFC00000 00000000 ALU clause starting at 134: ; MOV * T3.X, T3.Z, ; 80000803 00600C90 SETGE * T3.W, literal.x, PV.X, ; 801FC0FD 60600510 -1048576000(-1.600000e+01), 0(0.000000e+00) ; C1800000 00000000 SETE_DX10 * T3.W, PV.W, 0.0, ; 801F0CFE 60600610 PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002104 ALU clause starting at 139: ; MOV * T3.W, literal.x, ; 800000FD 60600C90 1(1.401298e-45), 0(0.000000e+00) ; 00000001 00000000 ALU clause starting at 141: ; MULADD_IEEE T2.X, KC0[0].X, T3.X, T0.X, ; 00006080 00430000 MULADD_IEEE * T2.Y, KC0[0].Y, 0.0, T0.Y, ; 801F0480 20430400 ALU clause starting at 143: ; SETGT * T3.W, literal.x, T2.Y, ; 808040FD 60600490 1063675494(9.000000e-01), 0(0.000000e+00) ; 3F666666 00000000 SETE_DX10 * T3.W, PV.W, 0.0, ; 801F0CFE 60600610 PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002104 ALU clause starting at 147: ; MOV * T3.W, literal.x, ; 800000FD 60600C90 1(1.401298e-45), 0(0.000000e+00) ; 00000001 00000000 ALU clause starting at 149: ; ADD T3.Z, T3.X, literal.x, ; 001FA003 40600010 MOV * T3.W, literal.y, ; 800004FD 60600C90 -1073741824(-2.000000e+00), 0(0.000000e+00) ; C0000000 00000000 ALU clause starting at 152: ; LSHL * T3.W, T3.W, literal.x, ; 801FAC03 60600B90 31(4.344025e-44), 0(0.000000e+00) ; 0000001F 00000000 ASHR * T3.W, PV.W, literal.x, ; 801FACFE 60600A90 31(4.344025e-44), 0(0.000000e+00) ; 0000001F 00000000 PRED_SETNE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002284 ALU clause starting at 157: ; ADD * T3.W, T3.X, literal.x, ; 801FA003 60600010 1069547520(1.500000e+00), 0(0.000000e+00) ; 3FC00000 00000000 MULADD_IEEE * T2.W, T2.Y, literal.x, PV.W, ; 801FA402 60430CFE -1073741824(-2.000000e+00), 0(0.000000e+00) ; C0000000 00000000 MOV T2.Z, literal.x, ; 000000FD 40400C90 MAX * T2.W, literal.y, PV.W, ; 819FC4FD 60400190 1069547520(1.500000e+00), -1048576000(-1.600000e+01) ; 3FC00000 C1800000 ALU clause starting at 164: ; MOV * T2.X, T2.Z, ; 80000802 00400C90 SETGE * T3.Y, PV.X, literal.x, ; 801FA0FE 20600510 1098907648(1.600000e+01), 0(0.000000e+00) ; 41800000 00000000 SETE_DX10 * T4.W, PV.Y, 0.0, ; 801F04FE 60800610 PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002104 ALU clause starting at 169: ; MOV * T4.W, literal.x, ; 800000FD 60800C90 1(1.401298e-45), 0(0.000000e+00) ; 00000001 00000000 ALU clause starting at 171: ; MULADD_IEEE T3.X, KC0[0].X, T2.X, T0.X, ; 00004080 00630000 MULADD_IEEE * T3.Y, KC0[0].Y, 0.0, T0.Y, ; 801F0480 20630400 ALU clause starting at 173: ; SETGT * T4.W, literal.x, T3.Y, ; 808060FD 60800490 1063675494(9.000000e-01), 0(0.000000e+00) ; 3F666666 00000000 SETE_DX10 * T4.W, PV.W, 0.0, ; 801F0CFE 60800610 PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002104 ALU clause starting at 177: ; MOV * T4.W, literal.x, ; 800000FD 60800C90 1(1.401298e-45), 0(0.000000e+00) ; 00000001 00000000 ALU clause starting at 179: ; ADD T2.Z, T2.X, literal.x, ; 001FA002 40400010 MOV * T4.W, literal.y, ; 800004FD 60800C90 1073741824(2.000000e+00), 0(0.000000e+00) ; 40000000 00000000 ALU clause starting at 182: ; LSHL * T4.W, T4.W, literal.x, ; 801FAC04 60800B90 31(4.344025e-44), 0(0.000000e+00) ; 0000001F 00000000 ASHR * T4.W, PV.W, literal.x, ; 801FACFE 60800A90 31(4.344025e-44), 0(0.000000e+00) ; 0000001F 00000000 PRED_SETNE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002284 ALU clause starting at 187: ; ADD T2.Z, T3.Y, T3.Y, ; 00806403 40400010 ADD * T3.W, T2.X, literal.x, ; 801FA002 60600010 -1077936128(-1.500000e+00), 0(0.000000e+00) ; BFC00000 00000000 ADD * T3.W, PV.Z, PV.W, ; 819FC8FE 60600010 MIN * T3.W, literal.x, PV.W, ; 819FC0FD 60600210 1098907648(1.600000e+01), 0(0.000000e+00) ; 41800000 00000000 MULADD_IEEE T4.X, T2.W, KC0[0].X, T0.X, ; 00100C02 00830000 ADD * T5.W, PV.W, 1.0, ; 801F2CFE 60A00010 MULADD_IEEE T5.X, PV.W, KC0[0].X, T0.X, ; 00100CFE 00A30000 MULADD_IEEE * T4.Y, KC0[0].Y, literal.x, T0.Y, ; 801FA480 20830400 -1098907648(-2.500000e-01), 0(0.000000e+00) ; BE800000 00000000 MOV * T5.Y, PV.Y, ; 800004FE 20A00C90 ALU clause starting at 199: ; MUL_IEEE * T4.W, T4.X, literal.x, ; 801FA004 60800110 1082130432(4.000000e+00), 0(0.000000e+00) ; 40800000 00000000 RNDNE T2.Y, PV.W, ; 00000CFE 20400990 MOV T2.Z, |T2.W|, ; 00000C02 40400C91 MUL_IEEE * T2.W, T5.X, literal.x, ; 801FA005 60400110 1082130432(4.000000e+00), 0(0.000000e+00) ; 40800000 00000000 RNDNE T3.Y, PV.W, ; 00000CFE 20600990 MOV T3.Z, |T3.W|, ; 00000C03 40600C91 MULADD_IEEE * T2.W, PV.Y, literal.x, PV.Z, ; 801FA4FE 604308FE 1107558400(3.300000e+01), 0(0.000000e+00) ; 42040000 00000000 MUL_IEEE T2.X, PV.W, literal.x, ; 001FACFE 00400110 MULADD_IEEE * T3.W, PV.Y, literal.y, PV.Z, ; 809FA4FE 606308FE 1002950154(6.097560e-03), 1107558400(3.300000e+01) ; 3BC7CE0A 42040000 MUL_IEEE * T2.Y, PV.W, literal.x, ; 801FACFE 20400110 1002950154(6.097560e-03), 0(0.000000e+00) ; 3BC7CE0A 00000000 ALU clause starting at 214: ; SETNE * T3.W, T1.X, 0.0, ; 801F0001 60600590 SETNE_DX10 * T3.W, PV.W, 0.0, ; 801F0CFE 60600790 PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002104 ALU clause starting at 217: ; MOV * T0.Y, literal.x, ; 800000FD 20000C90 0(0.000000e+00), 0(0.000000e+00) ; 00000000 00000000 MOV * T0.X, PV.Y, ; 800004FE 00000C90 ALU clause starting at 220: ; MOV * T3.Z, literal.x, ; 800000FD 40600C90 -1077936128(-1.500000e+00), 0(0.000000e+00) ; BFC00000 00000000 ALU clause starting at 222: ; MOV * T3.X, T3.Z, ; 80000803 00600C90 SETGE * T3.W, literal.x, PV.X, ; 801FC0FD 60600510 -1048576000(-1.600000e+01), 0(0.000000e+00) ; C1800000 00000000 SETE_DX10 * T3.W, PV.W, 0.0, ; 801F0CFE 60600610 PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002104 ALU clause starting at 227: ; MOV * T3.W, literal.x, ; 800000FD 60600C90 1(1.401298e-45), 0(0.000000e+00) ; 00000001 00000000 ALU clause starting at 229: ; MULADD_IEEE T1.X, KC0[0].X, 0.0, T0.X, ; 001F0080 00230000 MULADD_IEEE * T1.Y, KC0[0].Y, T3.X, T0.Y, ; 80006480 20230400 ALU clause starting at 231: ; SETGT * T3.W, literal.x, T1.X, ; 800020FD 60600490 1063675494(9.000000e-01), 0(0.000000e+00) ; 3F666666 00000000 SETE_DX10 * T3.W, PV.W, 0.0, ; 801F0CFE 60600610 PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002104 ALU clause starting at 235: ; MOV * T3.W, literal.x, ; 800000FD 60600C90 1(1.401298e-45), 0(0.000000e+00) ; 00000001 00000000 ALU clause starting at 237: ; ADD T3.Z, T3.X, literal.x, ; 001FA003 40600010 MOV * T3.W, literal.y, ; 800004FD 60600C90 -1073741824(-2.000000e+00), 0(0.000000e+00) ; C0000000 00000000 ALU clause starting at 240: ; LSHL * T3.W, T3.W, literal.x, ; 801FAC03 60600B90 31(4.344025e-44), 0(0.000000e+00) ; 0000001F 00000000 ASHR * T3.W, PV.W, literal.x, ; 801FACFE 60600A90 31(4.344025e-44), 0(0.000000e+00) ; 0000001F 00000000 PRED_SETNE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002284 ALU clause starting at 245: ; ADD * T3.W, T3.X, literal.x, ; 801FA003 60600010 1069547520(1.500000e+00), 0(0.000000e+00) ; 3FC00000 00000000 MULADD_IEEE * T1.W, T1.X, literal.x, PV.W, ; 801FA001 60230CFE -1073741824(-2.000000e+00), 0(0.000000e+00) ; C0000000 00000000 MAX * T1.W, literal.x, PV.W, ; 819FC0FD 60200190 -1048576000(-1.600000e+01), 0(0.000000e+00) ; C1800000 00000000 MOV T3.X, PV.W, ; 00000CFE 00600C90 MOV * T4.W, literal.x, ; 800000FD 60800C90 1069547520(1.500000e+00), 0(0.000000e+00) ; 3FC00000 00000000 ALU clause starting at 254: ; MOV * T1.X, T4.W, ; 80000C04 00200C90 SETGE * T4.W, PV.X, literal.x, ; 801FA0FE 60800510 1098907648(1.600000e+01), 0(0.000000e+00) ; 41800000 00000000 SETE_DX10 * T4.W, PV.W, 0.0, ; 801F0CFE 60800610 PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002104 ALU clause starting at 259: ; MOV * T5.W, literal.x, ; 800000FD 60A00C90 1(1.401298e-45), 0(0.000000e+00) ; 00000001 00000000 ALU clause starting at 261: ; MULADD_IEEE T3.X, KC0[0].X, 0.0, T0.X, ; 001F0080 00630000 MULADD_IEEE * T3.Y, KC0[0].Y, T1.X, T0.Y, ; 80002480 20630400 ALU clause starting at 263: ; SETGT * T4.W, literal.x, T3.X, ; 800060FD 60800490 1063675494(9.000000e-01), 0(0.000000e+00) ; 3F666666 00000000 SETE_DX10 * T4.W, PV.W, 0.0, ; 801F0CFE 60800610 PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002104 ALU clause starting at 267: ; MOV * T5.W, literal.x, ; 800000FD 60A00C90 1(1.401298e-45), 0(0.000000e+00) ; 00000001 00000000 ALU clause starting at 269: ; MOV * T5.W, literal.x, ; 800000FD 60A00C90 0(0.000000e+00), 0(0.000000e+00) ; 00000000 00000000 ADD * T4.W, T1.X, literal.x, ; 801FA001 60800010 1073741824(2.000000e+00), 0(0.000000e+00) ; 40000000 00000000 ALU clause starting at 273: ; LSHL * T5.W, T5.W, literal.x, ; 801FAC05 60A00B90 31(4.344025e-44), 0(0.000000e+00) ; 0000001F 00000000 ASHR * T5.W, PV.W, literal.x, ; 801FACFE 60A00A90 31(4.344025e-44), 0(0.000000e+00) ; 0000001F 00000000 PRED_SETNE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002284 ALU clause starting at 278: ; MULADD_IEEE T4.X, KC0[0].X, literal.x, T0.X, ; 001FA080 00830000 MULADD_IEEE * T4.Y, T1.W, KC0[0].Y, T0.Y, ; 80900C01 20830400 -1098907648(-2.500000e-01), 0(0.000000e+00) ; BE800000 00000000 ALU clause starting at 281: ; ADD T1.Z, T3.X, T3.X, ; 00006003 40200010 ADD * T3.W, T1.X, literal.x, BS:VEC_120/SCL_212 ; 801FA001 60680010 -1077936128(-1.500000e+00), 0(0.000000e+00) ; BFC00000 00000000 ADD * T3.W, PV.Z, PV.W, ; 819FC8FE 60600010 MIN * T3.W, literal.x, PV.W, ; 819FC0FD 60600210 1098907648(1.600000e+01), 0(0.000000e+00) ; 41800000 00000000 ADD * T6.W, PV.W, 1.0, ; 801F2CFE 60C00010 MULADD_IEEE * T0.W, PV.W, KC0[0].Y, T0.Y, ; 80900CFE 60030400 MOV * T4.Y, PV.W, ; 80000CFE 20800C90 ALU clause starting at 290: ; MUL_IEEE * T4.W, T5.Y, literal.x, ; 801FA405 60800110 1082130432(4.000000e+00), 0(0.000000e+00) ; 40800000 00000000 RNDNE T1.Y, PV.W, ; 00000CFE 20200990 MOV T1.Z, |T1.W|, ; 00000C01 40200C91 MUL_IEEE * T0.W, T0.Y, literal.x, ; 801FA400 60000110 1082130432(4.000000e+00), 0(0.000000e+00) ; 40800000 00000000 RNDNE T0.Y, PV.W, ; 00000CFE 20000990 MOV T0.Z, |T3.W|, ; 00000C03 40000C91 MULADD_IEEE * T0.W, PV.Y, literal.x, PV.Z, ; 801FA4FE 600308FE 1107558400(3.300000e+01), 0(0.000000e+00) ; 42040000 00000000 MUL_IEEE T1.X, PV.W, literal.x, ; 001FACFE 00200110 MULADD_IEEE * T0.W, PV.Y, literal.y, PV.Z, ; 809FA4FE 600308FE 1002950154(6.097560e-03), 1107558400(3.300000e+01) ; 3BC7CE0A 42040000 MUL_IEEE * T1.Y, PV.W, literal.x, ; 801FACFE 20200110 1002950154(6.097560e-03), 0(0.000000e+00) ; 3BC7CE0A 00000000 ALU clause starting at 305: ; MOV T2.Z, T0.X, ; 00000000 40400C90 MOV * T2.W, T0.Y, ; 80000400 60400C90 ===== SHADER #62 ======================================== PS/CAYMAN/CAYMAN ===== ===== 614 dw ===== 7 gprs ===== 3 stack ======================================== 0000 0000007a a00c0000 ALU 4 @244 0244 00380400 00146b10 1 x: INTERP_XY R0.x, R0.y, Param0.x VEC_210 0246 00380000 20146b10 y: INTERP_XY R0.y, R0.x, Param0.x VEC_210 0248 00380400 40146b00 z: INTERP_XY __.z, R0.y, Param0.x VEC_210 0250 80380000 60146b00 w: INTERP_XY __.w, R0.x, Param0.x VEC_210 0002 00000064 80400000 TEX 1 @200 0200 00001110 f00d1001 fc808000 SAMPLE R1.xyzw, R0.xy__, RID:17, SID:1 CT:NNNN 0004 0000007e a4080000 ALU_PUSH_BEFORE 3 @252 0252 801f0401 20400590 2 y: SETNE R2.y, R1.y, 0 0254 801f04fe 60600790 3 w: SETNE_DX10 R3.w, PV.y, 0 0256 801f0cfe 00002104 4 M x: PRED_SETE_INT __.x, PV.w, 0 0006 00000005 82800000 JUMP @10 0008 00000081 a0080000 ALU 3 @258 0258 800000fd 20400c90 5 y: MOV R2.y, [0x00000000 0].x 0260 00000000 0262 800004fe 00400c90 6 x: MOV R2.x, PV.y 0010 00000030 83400001 ELSE @96 POP:1 0012 00000084 a0040000 ALU 2 @264 0264 800000fd 40600c90 7 z: MOV R3.z, [0xbfc00000 -1.5].x 0266 bfc00000 0014 00000019 81800000 LOOP_START_DX10 @50 0016 00000086 a4100000 ALU_PUSH_BEFORE 5 @268 0268 80000803 00600c90 8 x: MOV R3.x, R3.z 0270 801fc0fd 60600510 9 w: SETGE R3.w, [0xc1800000 -16].x, PV.x 0272 c1800000 0274 801f0cfe 60600610 10 w: SETE_DX10 R3.w, PV.w, 0 0276 801f0cfe 00002104 11 M x: PRED_SETE_INT __.x, PV.w, 0 0018 0000000b 82800000 JUMP @22 0020 0000008b a0040000 ALU 2 @278 0278 800000fd 60600c90 12 w: MOV R3.w, [0x00000001 1.4013e-45].x 0280 00000001 0022 00000014 83400001 ELSE @40 POP:1 0024 8000008d a0040000 ALU 2 @282 KC0[CB0:0-31] 0282 00006080 00430000 13 x: MULADD_IEEE R2.x, KC0[0].x, R3.x, R0.x 0284 801f0480 20430400 y: MULADD_IEEE R2.y, KC0[0].y, 0, R0.y 0026 00000066 80400000 TEX 1 @204 0204 00021211 f00d1002 84810000 SAMPLE_L R2.xyzw, R2.xyy0, RID:18, SID:2 CT:NNNN 0028 0000008f a40c0000 ALU_PUSH_BEFORE 4 @286 0286 808040fd 60600490 14 w: SETGT R3.w, [0x3f666666 0.9].x, R2.y 0288 3f666666 0290 801f0cfe 60600610 15 w: SETE_DX10 R3.w, PV.w, 0 0292 801f0cfe 00002104 16 M x: PRED_SETE_INT __.x, PV.w, 0 0030 00000011 82800000 JUMP @34 0032 00000093 a0040000 ALU 2 @294 0294 800000fd 60600c90 17 w: MOV R3.w, [0x00000001 1.4013e-45].x 0296 00000001 0034 00000013 83400001 ELSE @38 POP:1 0036 00000095 a8080000 ALU_POP_AFTER 3 @298 0298 001fa003 40600010 18 z: ADD R3.z, R3.x, [0xc0000000 -2].x 0300 800004fd 60600c90 w: MOV R3.w, [0x00000000 0].y 0302 c0000000 0303 00000000 0038 00000014 83800001 POP @40 POP:1 0040 00000098 a4100000 ALU_PUSH_BEFORE 5 @304 0304 801fac03 60600b90 19 w: LSHL_INT R3.w, R3.w, [0x0000001f 4.34403e-44].x 0306 0000001f 0308 801facfe 60600a90 20 w: ASHR_INT R3.w, PV.w, [0x0000001f 4.34403e-44].x 0310 0000001f 0312 801f0cfe 00002284 21 M x: PRED_SETNE_INT __.x, PV.w, 0 0042 00000018 82800001 JUMP @48 POP:1 0044 00000018 82400000 LOOP_BREAK @48 0046 00000018 83800001 POP @48 POP:1 0048 00000008 81400000 LOOP_END @16 0050 0000009d a0180000 ALU 7 @314 0314 801fa003 60600010 22 w: ADD R3.w, R3.x, [0x3fc00000 1.5].x 0316 3fc00000 0318 801fa402 60430cfe 23 w: MULADD_IEEE R2.w, R2.y, [0xc0000000 -2].x, PV.w 0320 c0000000 0322 000000fd 40400c90 24 z: MOV R2.z, [0x3fc00000 1.5].x 0324 819fc4fd 60400190 w: MAX R2.w, [0xc1800000 -16].y, PV.w 0326 3fc00000 0327 c1800000 0052 0000002c 81800000 LOOP_START_DX10 @88 0054 000000a4 a4100000 ALU_PUSH_BEFORE 5 @328 0328 80000802 00400c90 25 x: MOV R2.x, R2.z 0330 801fa0fe 20600510 26 y: SETGE R3.y, PV.x, [0x41800000 16].x 0332 41800000 0334 801f04fe 60800610 27 w: SETE_DX10 R4.w, PV.y, 0 0336 801f0cfe 00002104 28 M x: PRED_SETE_INT __.x, PV.w, 0 0056 0000001e 82800000 JUMP @60 0058 000000a9 a0040000 ALU 2 @338 0338 800000fd 60800c90 29 w: MOV R4.w, [0x00000001 1.4013e-45].x 0340 00000001 0060 00000027 83400001 ELSE @78 POP:1 0062 800000ab a0040000 ALU 2 @342 KC0[CB0:0-31] 0342 00004080 00630000 30 x: MULADD_IEEE R3.x, KC0[0].x, R2.x, R0.x 0344 801f0480 20630400 y: MULADD_IEEE R3.y, KC0[0].y, 0, R0.y 0064 00000068 80400000 TEX 1 @208 0208 00031211 f00d1003 84810000 SAMPLE_L R3.xyzw, R3.xyy0, RID:18, SID:2 CT:NNNN 0066 000000ad a40c0000 ALU_PUSH_BEFORE 4 @346 0346 808060fd 60800490 31 w: SETGT R4.w, [0x3f666666 0.9].x, R3.y 0348 3f666666 0350 801f0cfe 60800610 32 w: SETE_DX10 R4.w, PV.w, 0 0352 801f0cfe 00002104 33 M x: PRED_SETE_INT __.x, PV.w, 0 0068 00000024 82800000 JUMP @72 0070 000000b1 a0040000 ALU 2 @354 0354 800000fd 60800c90 34 w: MOV R4.w, [0x00000001 1.4013e-45].x 0356 00000001 0072 00000026 83400001 ELSE @76 POP:1 0074 000000b3 a8080000 ALU_POP_AFTER 3 @358 0358 001fa002 40400010 35 z: ADD R2.z, R2.x, [0x40000000 2].x 0360 800004fd 60800c90 w: MOV R4.w, [0x00000000 0].y 0362 40000000 0363 00000000 0076 00000027 83800001 POP @78 POP:1 0078 000000b6 a4100000 ALU_PUSH_BEFORE 5 @364 0364 801fac04 60800b90 36 w: LSHL_INT R4.w, R4.w, [0x0000001f 4.34403e-44].x 0366 0000001f 0368 801facfe 60800a90 37 w: ASHR_INT R4.w, PV.w, [0x0000001f 4.34403e-44].x 0370 0000001f 0372 801f0cfe 00002284 38 M x: PRED_SETNE_INT __.x, PV.w, 0 0080 0000002b 82800001 JUMP @86 POP:1 0082 0000002b 82400000 LOOP_BREAK @86 0084 0000002b 83800001 POP @86 POP:1 0086 0000001b 81400000 LOOP_END @54 0088 800000bb a02c0000 ALU 12 @374 KC0[CB0:0-31] 0374 00806403 40400010 39 z: ADD R2.z, R3.y, R3.y 0376 801fa002 60600010 w: ADD R3.w, R2.x, [0xbfc00000 -1.5].x 0378 bfc00000 0380 819fc8fe 60600010 40 w: ADD R3.w, PV.z, PV.w 0382 819fc0fd 60600210 41 w: MIN R3.w, [0x41800000 16].x, PV.w 0384 41800000 0386 00100c02 00830000 42 x: MULADD_IEEE R4.x, R2.w, KC0[0].x, R0.x 0388 801f2cfe 60a00010 w: ADD R5.w, PV.w, 1.0 0390 00100cfe 00a30000 43 x: MULADD_IEEE R5.x, PV.w, KC0[0].x, R0.x 0392 801fa480 20830400 y: MULADD_IEEE R4.y, KC0[0].y, [0xbe800000 -0.25].x, R0.y 0394 be800000 0396 800004fe 20a00c90 44 y: MOV R5.y, PV.y 0090 0000006a 80400400 TEX 2 @212 0212 00051211 f00d1005 84810000 SAMPLE_L R5.xyzw, R5.xyy0, RID:18, SID:2 CT:NNNN 0216 00041211 f00d1004 84810000 SAMPLE_L R4.xyzw, R4.xyy0, RID:18, SID:2 CT:NNNN 0092 000000c7 a8380000 ALU_POP_AFTER 15 @398 0398 801fa004 60800110 45 w: MUL_IEEE R4.w, R4.x, [0x40800000 4].x 0400 40800000 0402 00000cfe 20400990 46 y: RNDNE R2.y, PV.w 0404 00000c02 40400c91 z: MOV R2.z, |R2.w| 0406 801fa005 60400110 w: MUL_IEEE R2.w, R5.x, [0x40800000 4].x 0408 40800000 0410 00000cfe 20600990 47 y: RNDNE R3.y, PV.w 0412 00000c03 40600c91 z: MOV R3.z, |R3.w| 0414 801fa4fe 604308fe w: MULADD_IEEE R2.w, PV.y, [0x42040000 33].x, PV.z 0416 42040000 0418 001facfe 00400110 48 x: MUL_IEEE R2.x, PV.w, [0x3bc7ce0a 0.00609756].x 0420 809fa4fe 606308fe w: MULADD_IEEE R3.w, PV.y, [0x42040000 33].y, PV.z 0422 3bc7ce0a 0423 42040000 0424 801facfe 20400110 49 y: MUL_IEEE R2.y, PV.w, [0x3bc7ce0a 0.00609756].x 0426 3bc7ce0a 0094 0000006e 80400000 TEX 1 @220 0220 00021011 f00d1002 84800000 SAMPLE_L R2.xyzw, R2.xyy0, RID:16, SID:0 CT:NNNN 0096 000000d6 a4080000 ALU_PUSH_BEFORE 3 @428 0428 801f0001 60600590 50 w: SETNE R3.w, R1.x, 0 0430 801f0cfe 60600790 51 w: SETNE_DX10 R3.w, PV.w, 0 0432 801f0cfe 00002104 52 M x: PRED_SETE_INT __.x, PV.w, 0 0098 00000033 82800000 JUMP @102 0100 000000d9 a0080000 ALU 3 @434 0434 800000fd 20000c90 53 y: MOV R0.y, [0x00000000 0].x 0436 00000000 0438 800004fe 00000c90 54 x: MOV R0.x, PV.y 0102 00000060 83400001 ELSE @192 POP:1 0104 000000dc a0040000 ALU 2 @440 0440 800000fd 40600c90 55 z: MOV R3.z, [0xbfc00000 -1.5].x 0442 bfc00000 0106 00000047 81800000 LOOP_START_DX10 @142 0108 000000de a4100000 ALU_PUSH_BEFORE 5 @444 0444 80000803 00600c90 56 x: MOV R3.x, R3.z 0446 801fc0fd 60600510 57 w: SETGE R3.w, [0xc1800000 -16].x, PV.x 0448 c1800000 0450 801f0cfe 60600610 58 w: SETE_DX10 R3.w, PV.w, 0 0452 801f0cfe 00002104 59 M x: PRED_SETE_INT __.x, PV.w, 0 0110 00000039 82800000 JUMP @114 0112 000000e3 a0040000 ALU 2 @454 0454 800000fd 60600c90 60 w: MOV R3.w, [0x00000001 1.4013e-45].x 0456 00000001 0114 00000042 83400001 ELSE @132 POP:1 0116 800000e5 a0040000 ALU 2 @458 KC0[CB0:0-31] 0458 001f0080 00230000 61 x: MULADD_IEEE R1.x, KC0[0].x, 0, R0.x 0460 80006480 20230400 y: MULADD_IEEE R1.y, KC0[0].y, R3.x, R0.y 0118 00000070 80400000 TEX 1 @224 0224 00011211 f00d1001 84810000 SAMPLE_L R1.xyzw, R1.xyy0, RID:18, SID:2 CT:NNNN 0120 000000e7 a40c0000 ALU_PUSH_BEFORE 4 @462 0462 800020fd 60600490 62 w: SETGT R3.w, [0x3f666666 0.9].x, R1.x 0464 3f666666 0466 801f0cfe 60600610 63 w: SETE_DX10 R3.w, PV.w, 0 0468 801f0cfe 00002104 64 M x: PRED_SETE_INT __.x, PV.w, 0 0122 0000003f 82800000 JUMP @126 0124 000000eb a0040000 ALU 2 @470 0470 800000fd 60600c90 65 w: MOV R3.w, [0x00000001 1.4013e-45].x 0472 00000001 0126 00000041 83400001 ELSE @130 POP:1 0128 000000ed a8080000 ALU_POP_AFTER 3 @474 0474 001fa003 40600010 66 z: ADD R3.z, R3.x, [0xc0000000 -2].x 0476 800004fd 60600c90 w: MOV R3.w, [0x00000000 0].y 0478 c0000000 0479 00000000 0130 00000042 83800001 POP @132 POP:1 0132 000000f0 a4100000 ALU_PUSH_BEFORE 5 @480 0480 801fac03 60600b90 67 w: LSHL_INT R3.w, R3.w, [0x0000001f 4.34403e-44].x 0482 0000001f 0484 801facfe 60600a90 68 w: ASHR_INT R3.w, PV.w, [0x0000001f 4.34403e-44].x 0486 0000001f 0488 801f0cfe 00002284 69 M x: PRED_SETNE_INT __.x, PV.w, 0 0134 00000046 82800001 JUMP @140 POP:1 0136 00000046 82400000 LOOP_BREAK @140 0138 00000046 83800001 POP @140 POP:1 0140 00000036 81400000 LOOP_END @108 0142 000000f5 a0200000 ALU 9 @490 0490 801fa003 60600010 70 w: ADD R3.w, R3.x, [0x3fc00000 1.5].x 0492 3fc00000 0494 801fa001 60230cfe 71 w: MULADD_IEEE R1.w, R1.x, [0xc0000000 -2].x, PV.w 0496 c0000000 0498 819fc0fd 60200190 72 w: MAX R1.w, [0xc1800000 -16].x, PV.w 0500 c1800000 0502 00000cfe 00600c90 73 x: MOV R3.x, PV.w 0504 800000fd 60800c90 w: MOV R4.w, [0x3fc00000 1.5].x 0506 3fc00000 0144 0000005a 81800000 LOOP_START_DX10 @180 0146 000000fe a4100000 ALU_PUSH_BEFORE 5 @508 0508 80000c04 00200c90 74 x: MOV R1.x, R4.w 0510 801fa0fe 60800510 75 w: SETGE R4.w, PV.x, [0x41800000 16].x 0512 41800000 0514 801f0cfe 60800610 76 w: SETE_DX10 R4.w, PV.w, 0 0516 801f0cfe 00002104 77 M x: PRED_SETE_INT __.x, PV.w, 0 0148 0000004c 82800000 JUMP @152 0150 00000103 a0040000 ALU 2 @518 0518 800000fd 60a00c90 78 w: MOV R5.w, [0x00000001 1.4013e-45].x 0520 00000001 0152 00000055 83400001 ELSE @170 POP:1 0154 80000105 a0040000 ALU 2 @522 KC0[CB0:0-31] 0522 001f0080 00630000 79 x: MULADD_IEEE R3.x, KC0[0].x, 0, R0.x 0524 80002480 20630400 y: MULADD_IEEE R3.y, KC0[0].y, R1.x, R0.y 0156 00000072 80400000 TEX 1 @228 0228 00031211 f00d1003 84810000 SAMPLE_L R3.xyzw, R3.xyy0, RID:18, SID:2 CT:NNNN 0158 00000107 a40c0000 ALU_PUSH_BEFORE 4 @526 0526 800060fd 60800490 80 w: SETGT R4.w, [0x3f666666 0.9].x, R3.x 0528 3f666666 0530 801f0cfe 60800610 81 w: SETE_DX10 R4.w, PV.w, 0 0532 801f0cfe 00002104 82 M x: PRED_SETE_INT __.x, PV.w, 0 0160 00000052 82800000 JUMP @164 0162 0000010b a0040000 ALU 2 @534 0534 800000fd 60a00c90 83 w: MOV R5.w, [0x00000001 1.4013e-45].x 0536 00000001 0164 00000054 83400001 ELSE @168 POP:1 0166 0000010d a80c0000 ALU_POP_AFTER 4 @538 0538 800000fd 60a00c90 84 w: MOV R5.w, [0x00000000 0].x 0540 00000000 0542 801fa001 60800010 85 w: ADD R4.w, R1.x, [0x40000000 2].x 0544 40000000 0168 00000055 83800001 POP @170 POP:1 0170 00000111 a4100000 ALU_PUSH_BEFORE 5 @546 0546 801fac05 60a00b90 86 w: LSHL_INT R5.w, R5.w, [0x0000001f 4.34403e-44].x 0548 0000001f 0550 801facfe 60a00a90 87 w: ASHR_INT R5.w, PV.w, [0x0000001f 4.34403e-44].x 0552 0000001f 0554 801f0cfe 00002284 88 M x: PRED_SETNE_INT __.x, PV.w, 0 0172 00000059 82800001 JUMP @178 POP:1 0174 00000059 82400000 LOOP_BREAK @178 0176 00000059 83800001 POP @178 POP:1 0178 00000049 81400000 LOOP_END @146 0180 80000116 a0080000 ALU 3 @556 KC0[CB0:0-31] 0556 001fa080 00830000 89 x: MULADD_IEEE R4.x, KC0[0].x, [0xbe800000 -0.25].x, R0.x 0558 80900c01 20830400 y: MULADD_IEEE R4.y, R1.w, KC0[0].y, R0.y 0560 be800000 0182 00000074 80400000 TEX 1 @232 0232 00041211 f00d1005 84810000 SAMPLE_L R5.xyzw, R4.xyy0, RID:18, SID:2 CT:NNNN 0184 80000119 a0200000 ALU 9 @562 KC0[CB0:0-31] 0562 00006003 40200010 90 z: ADD R1.z, R3.x, R3.x 0564 801fa001 60680010 w: ADD R3.w, R1.x, [0xbfc00000 -1.5].x VEC_120 0566 bfc00000 0568 819fc8fe 60600010 91 w: ADD R3.w, PV.z, PV.w 0570 819fc0fd 60600210 92 w: MIN R3.w, [0x41800000 16].x, PV.w 0572 41800000 0574 801f2cfe 60c00010 93 w: ADD R6.w, PV.w, 1.0 0576 80900cfe 60030400 94 w: MULADD_IEEE R0.w, PV.w, KC0[0].y, R0.y 0578 80000cfe 20800c90 95 y: MOV R4.y, PV.w 0186 00000076 80400000 TEX 1 @236 0236 00041211 f00d1000 84810000 SAMPLE_L R0.xyzw, R4.xyy0, RID:18, SID:2 CT:NNNN 0188 00000122 a8380000 ALU_POP_AFTER 15 @580 0580 801fa405 60800110 96 w: MUL_IEEE R4.w, R5.y, [0x40800000 4].x 0582 40800000 0584 00000cfe 20200990 97 y: RNDNE R1.y, PV.w 0586 00000c01 40200c91 z: MOV R1.z, |R1.w| 0588 801fa400 60000110 w: MUL_IEEE R0.w, R0.y, [0x40800000 4].x 0590 40800000 0592 00000cfe 20000990 98 y: RNDNE R0.y, PV.w 0594 00000c03 40000c91 z: MOV R0.z, |R3.w| 0596 801fa4fe 600308fe w: MULADD_IEEE R0.w, PV.y, [0x42040000 33].x, PV.z 0598 42040000 0600 001facfe 00200110 99 x: MUL_IEEE R1.x, PV.w, [0x3bc7ce0a 0.00609756].x 0602 809fa4fe 600308fe w: MULADD_IEEE R0.w, PV.y, [0x42040000 33].y, PV.z 0604 3bc7ce0a 0605 42040000 0606 801facfe 20200110 100 y: MUL_IEEE R1.y, PV.w, [0x3bc7ce0a 0.00609756].x 0608 3bc7ce0a 0190 00000078 80400000 TEX 1 @240 0240 00011011 f00d1000 84800000 SAMPLE_L R0.xyzw, R1.xyy0, RID:16, SID:0 CT:NNNN 0192 00000131 a0040000 ALU 2 @610 0610 00000000 40400c90 101 z: MOV R2.z, R0.x 0612 80000400 60400c90 w: MOV R2.w, R0.y 0194 c0010000 95200688 EXPORT_DONE PIXEL 0 R2.xyzw 0196 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== Installing breakpad exception handler for appid(steam)/version(1390852599_client) ===== SHADER #62 OPT ==================================== PS/CAYMAN/CAYMAN ===== ===== 520 dw ===== 6 gprs ===== 2 stack ======================================== 0000 00000052 a00c0000 ALU 4 @164 0164 00380400 00946b10 1 x: INTERP_XY R4.x, R0.y, Param0.x VEC_210 0166 00b80000 20946b10 y: INTERP_XY R4.y, R0.x, Param0.y VEC_210 0168 01380400 40146b00 z: INTERP_XY __.z, R0.y, Param0.z VEC_210 0170 81b80000 60146b00 w: INTERP_XY __.w, R0.x, Param0.w VEC_210 0002 00000056 80400000 TEX 1 @172 0172 00041110 f00d1001 fc808000 SAMPLE R1.xyzw, R4.xy__, RID:17, SID:1 CT:NNNN 0004 00000058 a4000000 ALU_PUSH_BEFORE 1 @176 0176 801f0401 00001004 2 M x: PRED_SETE __.x, R1.y, 0 0006 00000005 82800000 JUMP @10 0008 00000059 a0040000 ALU 2 @178 0178 000000f8 00400c90 3 x: MOV R2.x, 0 0180 800000f8 20400c90 y: MOV R2.y, 0 0010 00000029 83400001 ELSE @82 POP:1 0012 4000005b a00c0000 ALU 4 @182 KC0[CB0:0-15] 0182 801f0401 20400590 4 y: SETNE R2.y, R1.y, 0 0184 000000fd 00000c90 5 x: MOV R0.x, [0xbfc00000 -1.5].x 0186 801f0480 20630404 y: MULADD_IEEE R3.y, KC0[0].y, 0, R4.y 0188 bfc00000 0014 00000015 81800000 LOOP_START_DX10 @42 0016 0000005f a4040000 ALU_PUSH_BEFORE 2 @190 0190 800000fd 00001104 6 M x: PRED_SETGE __.x, [0xc1800000 -16].x, R0.x 0192 c1800000 0018 0000000b 82800000 JUMP @22 0020 00000061 a0040000 ALU 2 @194 0194 000000fa 20000c90 7 y: MOV R0.y, 1 0196 80000000 40000c90 z: MOV R0.z, R0.x 0022 0000000f 83400001 ELSE @30 POP:1 0024 40000063 a0000000 ALU 1 @198 KC0[CB0:0-15] 0198 80000080 00630004 8 x: MULADD_IEEE R3.x, KC0[0].x, R0.x, R4.x 0026 00000064 80400000 TEX 1 @200 0200 00031211 f00d1002 84810000 SAMPLE_L R2.xyzw, R3.xyy0, RID:18, SID:2 CT:NNNN 0028 00000066 a8100000 ALU_POP_AFTER 5 @204 0204 001fa402 2f800710 9 y: SETGE_DX10 T0.y, R2.y, [0x3f666666 0.9].x 0206 809fa000 4f800010 z: ADD T0.z, R0.x, [0xc0000000 -2].y 0208 3f666666 0209 c0000000 0210 001f447c 200380f8 10 y: CNDE_INT R0.y, T0.y, 1, 0 0212 8000047c 4003887c z: CNDE_INT R0.z, T0.y, R0.x, T0.z 0030 0000006b a4100000 ALU_PUSH_BEFORE 5 @214 0214 801fa400 6f800b90 11 w: LSHL_INT T0.w, R0.y, [0x0000001f 4.34403e-44].x 0216 0000001f 0218 801fac7c 0f800a90 12 x: ASHR_INT T0.x, T0.w, [0x0000001f 4.34403e-44].x 0220 0000001f 0222 801f007c 00002284 13 M x: PRED_SETNE_INT __.x, T0.x, 0 0032 00000013 82800001 JUMP @38 POP:1 0034 00000014 82400000 LOOP_BREAK @40 0036 00000013 83800001 POP @38 POP:1 0038 00000070 a0000000 ALU 1 @224 0224 80000800 00000c90 14 x: MOV R0.x, R0.z 0040 00000008 81400000 LOOP_END @16 0042 00000071 a0100000 ALU 5 @226 0226 801fa000 20a00010 15 y: ADD R5.y, R0.x, [0x3fc00000 1.5].x 0228 3fc00000 0230 000000fd 00400c90 16 x: MOV R2.x, [0x3fc00000 1.5].x 0232 80000405 60000c90 w: MOV R0.w, R5.y 0234 3fc00000 0044 00000024 81800000 LOOP_START_DX10 @72 0046 00000076 a4040000 ALU_PUSH_BEFORE 2 @236 0236 801fa002 00001104 17 M x: PRED_SETGE __.x, R2.x, [0x41800000 16].x 0238 41800000 0048 0000001a 82800000 JUMP @52 0050 00000078 a00c0000 ALU 4 @240 0240 001fa002 20000510 18 y: SETGE R0.y, R2.x, [0x41800000 16].x 0242 000000fa 40400c90 z: MOV R2.z, 1 0244 80000002 60400c90 w: MOV R2.w, R2.x 0246 41800000 0052 0000001e 83400001 ELSE @60 POP:1 0054 4000007c a0000000 ALU 1 @248 KC0[CB0:0-15] 0248 80004080 00630004 19 x: MULADD_IEEE R3.x, KC0[0].x, R2.x, R4.x 0056 0000007e 80400000 TEX 1 @252 0252 00031211 f00d1000 84810000 SAMPLE_L R0.xyzw, R3.xyy0, RID:18, SID:2 CT:NNNN 0058 00000080 a8100000 ALU_POP_AFTER 5 @256 0256 001fa400 4f800710 20 z: SETGE_DX10 T0.z, R0.y, [0x3f666666 0.9].x 0258 809fa002 6f800010 w: ADD T0.w, R2.x, [0x40000000 2].y 0260 3f666666 0261 40000000 0262 001f487c 404380f8 21 z: CNDE_INT R2.z, T0.z, 1, 0 0264 8000487c 60438c7c w: CNDE_INT R2.w, T0.z, R2.x, T0.w 0060 00000085 a4100000 ALU_PUSH_BEFORE 5 @266 0266 801fa802 0f800b90 22 x: LSHL_INT T0.x, R2.z, [0x0000001f 4.34403e-44].x 0268 0000001f 0270 801fa07c 2f800a90 23 y: ASHR_INT T0.y, T0.x, [0x0000001f 4.34403e-44].x 0272 0000001f 0274 801f047c 00002284 24 M x: PRED_SETNE_INT __.x, T0.y, 0 0062 00000022 82800001 JUMP @68 POP:1 0064 00000023 82400000 LOOP_BREAK @70 0066 00000022 83800001 POP @68 POP:1 0068 0000008a a0000000 ALU 1 @276 0276 80000c02 00400c90 25 x: MOV R2.x, R2.w 0070 00000017 81400000 LOOP_END @46 0072 4000008b a0340000 ALU 14 @278 KC0[CB0:0-15] 0278 801fa002 4f800010 26 z: ADD T0.z, R2.x, [0xbfc00000 -1.5].x 0280 bfc00000 0282 801fa400 6f82887c 27 w: MULADD T0.w, R0.y, [0x40000000 2].x, T0.z 0284 40000000 0286 001fa402 0f830405 28 x: MULADD_IEEE T0.x, R2.y, [0xc0000000 -2].x, R5.y 0288 809fac7c 20400210 y: MIN R2.y, T0.w, [0x41800000 16].y 0290 c0000000 0291 41800000 0292 001fa07c 40400190 29 z: MAX R2.z, T0.x, [0xc1800000 -16].x 0294 801f2402 6f800010 w: ADD T0.w, R2.y, 1.0 0296 c1800000 0298 00100802 00030004 30 x: MULADD_IEEE R0.x, R2.z, KC0[0].x, R4.x 0300 001fa480 20030404 y: MULADD_IEEE R0.y, KC0[0].y, [0xbe800000 -0.25].x, R4.y 0302 80100c7c 40030004 z: MULADD_IEEE R0.z, T0.w, KC0[0].x, R4.x 0304 be800000 0074 0000009a 80400400 TEX 2 @308 0308 00001211 f01c7e00 84a10000 SAMPLE_L R0.__x_, R0.zyy0, RID:18, SID:2 CT:NNNN 0312 00001211 f01ff000 84810000 SAMPLE_L R0.x___, R0.xyy0, RID:18, SID:2 CT:NNNN 0076 0000009e a0300000 ALU 13 @316 0316 001fa800 0f800110 31 x: MUL_IEEE T0.x, R0.z, [0x40800000 4].x 0318 801fa000 2f800110 y: MUL_IEEE T0.y, R0.x, [0x40800000 4].x 0320 40800000 0322 00000802 0f800c91 32 x: MOV T0.x, |R2.z| 0324 0000007c 20000990 y: RNDNE R0.y, T0.x 0326 00000402 4f800c91 z: MOV T0.z, |R2.y| 0328 8000047c 6f880990 w: RNDNE T0.w, T0.y VEC_120 0330 001fa400 2f83087c 33 y: MULADD_IEEE T0.y, R0.y, [0x42040000 33].x, T0.z 0332 801fac7c 4f83007c z: MULADD_IEEE T0.z, T0.w, [0x42040000 33].x, T0.x 0334 42040000 0336 001fa87c 00000110 34 x: MUL_IEEE R0.x, T0.z, [0x3bc7ce0a 0.00609756].x 0338 801fa47c 40000110 z: MUL_IEEE R0.z, T0.y, [0x3bc7ce0a 0.00609756].x 0340 3bc7ce0a 0078 000000ac 80400000 TEX 1 @344 0344 00001011 f01f9002 89000000 SAMPLE_L R2.xy__, R0.xzz0, RID:16, SID:0 CT:NNNN 0080 00000029 83800001 POP @82 POP:1 0082 000000ae a4000000 ALU_PUSH_BEFORE 1 @348 0348 801f0001 00001004 35 M x: PRED_SETE __.x, R1.x, 0 0084 0000002c 82800000 JUMP @88 0086 000000af a0040000 ALU 2 @350 0350 000000f8 40400c90 36 z: MOV R2.z, 0 0352 800000f8 60400c90 w: MOV R2.w, 0 0088 00000050 83400001 ELSE @160 POP:1 0090 400000b1 a0080000 ALU 3 @354 KC0[CB0:0-15] 0354 000000fd 00000c90 37 x: MOV R0.x, [0xbfc00000 -1.5].x 0356 801f0080 40430004 z: MULADD_IEEE R2.z, KC0[0].x, 0, R4.x 0358 bfc00000 0092 0000003c 81800000 LOOP_START_DX10 @120 0094 000000b4 a4040000 ALU_PUSH_BEFORE 2 @360 0360 800000fd 00001104 38 M x: PRED_SETGE __.x, [0xc1800000 -16].x, R0.x 0362 c1800000 0096 00000032 82800000 JUMP @100 0098 000000b6 a0040000 ALU 2 @364 0364 00000000 40000c90 39 z: MOV R0.z, R0.x 0366 800000fa 60000c90 w: MOV R0.w, 1 0100 00000036 83400001 ELSE @108 POP:1 0102 400000b8 a0000000 ALU 1 @368 KC0[CB0:0-15] 0368 80000480 60430404 40 w: MULADD_IEEE R2.w, KC0[0].y, R0.x, R4.y 0104 000000ba 80400000 TEX 1 @372 0372 00021211 f00d1001 8da10000 SAMPLE_L R1.xyzw, R2.zww0, RID:18, SID:2 CT:NNNN 0106 000000bc a8100000 ALU_POP_AFTER 5 @376 0376 001fa000 0f800010 41 x: ADD T0.x, R0.x, [0xc0000000 -2].x 0378 809fa001 6f880710 w: SETGE_DX10 T0.w, R1.x, [0x3f666666 0.9].y VEC_120 0380 c0000000 0381 3f666666 0382 00000c7c 4003807c 42 z: CNDE_INT R0.z, T0.w, R0.x, T0.x 0384 801f4c7c 600380f8 w: CNDE_INT R0.w, T0.w, 1, 0 0108 000000c1 a4100000 ALU_PUSH_BEFORE 5 @386 0386 801fac00 2f800b90 43 y: LSHL_INT T0.y, R0.w, [0x0000001f 4.34403e-44].x 0388 0000001f 0390 801fa47c 4f800a90 44 z: ASHR_INT T0.z, T0.y, [0x0000001f 4.34403e-44].x 0392 0000001f 0394 801f087c 00002284 45 M x: PRED_SETNE_INT __.x, T0.z, 0 0110 0000003a 82800001 JUMP @116 POP:1 0112 0000003b 82400000 LOOP_BREAK @118 0114 0000003a 83800001 POP @116 POP:1 0116 000000c6 a0000000 ALU 1 @396 0396 80000800 00000c90 46 x: MOV R0.x, R0.z 0118 0000002f 81400000 LOOP_END @94 0120 000000c7 a0200000 ALU 9 @398 0398 801fa000 60000010 47 w: ADD R0.w, R0.x, [0x3fc00000 1.5].x 0400 3fc00000 0402 801fa001 6f830c00 48 w: MULADD_IEEE T0.w, R1.x, [0xc0000000 -2].x, R0.w 0404 c0000000 0406 801fac7c 00600190 49 x: MAX R3.x, T0.w, [0xc1800000 -16].x 0408 c1800000 0410 800000fd 00200c90 50 x: MOV R1.x, [0x3fc00000 1.5].x 0412 3fc00000 0414 80000003 00000c90 51 x: MOV R0.x, R3.x 0122 0000004b 81800000 LOOP_START_DX10 @150 0124 000000d0 a4040000 ALU_PUSH_BEFORE 2 @416 0416 801fa001 00001104 52 M x: PRED_SETGE __.x, R1.x, [0x41800000 16].x 0418 41800000 0126 00000041 82800000 JUMP @130 0128 000000d2 a0080000 ALU 3 @420 0420 000000fa 20200c90 53 y: MOV R1.y, 1 0422 800020fd 40200690 z: SETGT_DX10 R1.z, [0x41800000 16].x, R1.x 0424 41800000 0130 00000045 83400001 ELSE @138 POP:1 0132 400000d5 a0000000 ALU 1 @426 KC0[CB0:0-15] 0426 80002480 60430404 54 w: MULADD_IEEE R2.w, KC0[0].y, R1.x, R4.y 0134 000000d6 80400000 TEX 1 @428 0428 00021211 f00d1000 8da10000 SAMPLE_L R0.xyzw, R2.zww0, RID:18, SID:2 CT:NNNN 0136 000000d8 a8100000 ALU_POP_AFTER 5 @432 0432 001fa000 2f800710 55 y: SETGE_DX10 T0.y, R0.x, [0x3f666666 0.9].x 0434 809fa001 4f880010 z: ADD T0.z, R1.x, [0x40000000 2].y VEC_120 0436 3f666666 0437 40000000 0438 001f447c 202380f8 56 y: CNDE_INT R1.y, T0.y, 1, 0 0440 808f847c 4023887c z: CNDE_INT R1.z, T0.y, T0.y, T0.z 0138 000000dd a4100000 ALU_PUSH_BEFORE 5 @442 0442 801fa401 6f800b90 57 w: LSHL_INT T0.w, R1.y, [0x0000001f 4.34403e-44].x 0444 0000001f 0446 801fac7c 0f800a90 58 x: ASHR_INT T0.x, T0.w, [0x0000001f 4.34403e-44].x 0448 0000001f 0450 801f007c 00002284 59 M x: PRED_SETNE_INT __.x, T0.x, 0 0140 00000049 82800001 JUMP @146 POP:1 0142 0000004a 82400000 LOOP_BREAK @148 0144 00000049 83800001 POP @146 POP:1 0146 000000e2 a0000000 ALU 1 @452 0452 80000801 00200c90 60 x: MOV R1.x, R1.z 0148 0000003e 81400000 LOOP_END @124 0150 400000e3 a0280000 ALU 11 @454 KC0[CB0:0-15] 0454 801fa001 2f800010 61 y: ADD T0.y, R1.x, [0xbfc00000 -1.5].x 0456 bfc00000 0458 801fa000 4f82847c 62 z: MULADD T0.z, R0.x, [0x40000000 2].x, T0.y 0460 40000000 0462 801fa87c 60000210 63 w: MIN R0.w, T0.z, [0x41800000 16].x 0464 41800000 0466 801f2c00 0f800010 64 x: ADD T0.x, R0.w, 1.0 0468 001fa080 00030004 65 x: MULADD_IEEE R0.x, KC0[0].x, [0xbe800000 -0.25].x, R4.x 0470 0090007c 20030404 y: MULADD_IEEE R0.y, T0.x, KC0[0].y, R4.y 0472 80900003 400b0404 z: MULADD_IEEE R0.z, R3.x, KC0[0].y, R4.y VEC_120 0474 be800000 0152 000000ee 80400400 TEX 2 @476 0476 00001211 f01f9e00 84810000 SAMPLE_L R0._y__, R0.xyy0, RID:18, SID:2 CT:NNNN 0480 00001211 f01ff200 89010000 SAMPLE_L R0.y___, R0.xzz0, RID:18, SID:2 CT:NNNN 0154 000000f2 a0300000 ALU 13 @484 0484 001fa400 2f800110 66 y: MUL_IEEE T0.y, R0.y, [0x40800000 4].x 0486 801fa000 4f800110 z: MUL_IEEE T0.z, R0.x, [0x40800000 4].x 0488 40800000 0490 00000c00 0f800c91 67 x: MOV T0.x, |R0.w| 0492 0000087c 2f800990 y: RNDNE T0.y, T0.z 0494 00000003 4f800c91 z: MOV T0.z, |R3.x| 0496 8000047c 6f800990 w: RNDNE T0.w, T0.y 0498 001fa47c 0f83087c 68 x: MULADD_IEEE T0.x, T0.y, [0x42040000 33].x, T0.z 0500 801fac7c 6f83007c w: MULADD_IEEE T0.w, T0.w, [0x42040000 33].x, T0.x 0502 42040000 0504 001fa07c 00000110 69 x: MUL_IEEE R0.x, T0.x, [0x3bc7ce0a 0.00609756].x 0506 801fac7c 20000110 y: MUL_IEEE R0.y, T0.w, [0x3bc7ce0a 0.00609756].x 0508 3bc7ce0a 0156 00000100 80400000 TEX 1 @512 0512 00001011 f01f9000 84800000 SAMPLE_L R0.xy__, R0.xyy0, RID:16, SID:0 CT:NNNN 0158 00000102 a8040000 ALU_POP_AFTER 2 @516 0516 00000000 40400c90 70 z: MOV R2.z, R0.x 0518 80000400 60400c90 w: MOV R2.w, R0.y 0160 c0010000 95000688 EXPORT_DONE PIXEL 0 R2.xyzw 0162 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], PERSPECTIVE DCL IN[1], GENERIC[10], PERSPECTIVE DCL IN[2], GENERIC[11], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL SAMP[1] DCL TEMP[0..8] IMM[0] FLT32 { 1.0000, 0.0000, 0.0000, 0.0000} 0: TEX TEMP[0], IN[0].xyyy, SAMP[1], 2D 1: MOV TEMP[1].x, TEMP[0].xxxx 2: TEX TEMP[2].y, IN[2].zwww, SAMP[1], 2D 3: MOV TEMP[1].y, TEMP[2].yyyy 4: MOV TEMP[1].z, TEMP[0].zzzz 5: TEX TEMP[1].w, IN[2].xyyy, SAMP[1], 2D 6: MUL TEMP[4], TEMP[1], TEMP[1] 7: MUL TEMP[5], TEMP[4], TEMP[1] 8: DP4 TEMP[1].x, TEMP[5], IMM[0].xxxx 9: SLT TEMP[4].x, TEMP[1].xxxx, IMM[0].yyyy 10: IF TEMP[4].xxxx :12 11: KILL 12: ENDIF 13: TEX TEMP[4], IN[0].xyyy, SAMP[0], 2D 14: TEX TEMP[6], IN[1].zwww, SAMP[0], 2D 15: ADD TEMP[7].x, IMM[0].xxxx, -TEMP[0].xxxx 16: MUL TEMP[8], TEMP[4], TEMP[7].xxxx 17: MAD TEMP[7], TEMP[6], TEMP[0].xxxx, TEMP[8] 18: MUL TEMP[6], TEMP[7], TEMP[5].xxxx 19: TEX TEMP[7], IN[2].zwww, SAMP[0], 2D 20: ADD TEMP[8].x, IMM[0].xxxx, -TEMP[2].yyyy 21: MUL TEMP[3], TEMP[4], TEMP[8].xxxx 22: MAD TEMP[8], TEMP[7], TEMP[2].yyyy, TEMP[3] 23: MAD TEMP[2], TEMP[8], TEMP[5].yyyy, TEMP[6] 24: TEX TEMP[6], IN[1].xyyy, SAMP[0], 2D 25: ADD TEMP[7].x, IMM[0].xxxx, -TEMP[0].zzzz 26: MUL TEMP[8], TEMP[4], TEMP[7].xxxx 27: MAD TEMP[7], TEMP[6], TEMP[0].zzzz, TEMP[8] 28: MAD TEMP[0], TEMP[7], TEMP[5].zzzz, TEMP[2] 29: TEX TEMP[2], IN[2].xyyy, SAMP[0], 2D 30: ADD TEMP[6].x, IMM[0].xxxx, -TEMP[1].wwww 31: MUL TEMP[7], TEMP[4], TEMP[6].xxxx 32: MAD TEMP[4], TEMP[2], TEMP[1].wwww, TEMP[7] 33: MAD TEMP[2], TEMP[4], TEMP[5].wwww, TEMP[0] 34: RCP TEMP[0].x, TEMP[1].xxxx 35: MUL OUT[0], TEMP[2], TEMP[0].xxxx 36: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg, <4 x float> inreg, <4 x float> inreg) #0 { main_body: %4 = extractelement <4 x float> %0, i32 0 %5 = extractelement <4 x float> %0, i32 1 %6 = call <2 x float> @llvm.R600.interp.xy(i32 0, float %4, float %5) %7 = call <2 x float> @llvm.R600.interp.zw(i32 0, float %4, float %5) %8 = shufflevector <2 x float> %6, <2 x float> %7, <4 x i32> %9 = extractelement <4 x float> %8, i32 0 %10 = extractelement <4 x float> %8, i32 1 %11 = extractelement <4 x float> %0, i32 0 %12 = extractelement <4 x float> %0, i32 1 %13 = call <2 x float> @llvm.R600.interp.xy(i32 1, float %11, float %12) %14 = call <2 x float> @llvm.R600.interp.zw(i32 1, float %11, float %12) %15 = shufflevector <2 x float> %13, <2 x float> %14, <4 x i32> %16 = extractelement <4 x float> %15, i32 0 %17 = extractelement <4 x float> %15, i32 1 %18 = extractelement <4 x float> %15, i32 2 %19 = extractelement <4 x float> %15, i32 3 %20 = extractelement <4 x float> %0, i32 0 %21 = extractelement <4 x float> %0, i32 1 %22 = call <2 x float> @llvm.R600.interp.xy(i32 2, float %20, float %21) %23 = call <2 x float> @llvm.R600.interp.zw(i32 2, float %20, float %21) %24 = shufflevector <2 x float> %22, <2 x float> %23, <4 x i32> %25 = extractelement <4 x float> %24, i32 0 %26 = extractelement <4 x float> %24, i32 1 %27 = extractelement <4 x float> %24, i32 2 %28 = extractelement <4 x float> %24, i32 3 %29 = insertelement <4 x float> undef, float %9, i32 0 %30 = insertelement <4 x float> %29, float %10, i32 1 %31 = insertelement <4 x float> %30, float %10, i32 2 %32 = insertelement <4 x float> %31, float %10, i32 3 %33 = extractelement <4 x float> %32, i32 0 %34 = extractelement <4 x float> %32, i32 1 %35 = insertelement <4 x float> undef, float %33, i32 0 %36 = insertelement <4 x float> %35, float %34, i32 1 %37 = insertelement <4 x float> %36, float undef, i32 2 %38 = insertelement <4 x float> %37, float undef, i32 3 %39 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %38, i32 17, i32 1, i32 2) %40 = extractelement <4 x float> %39, i32 0 %41 = extractelement <4 x float> %39, i32 2 %42 = insertelement <4 x float> undef, float %27, i32 0 %43 = insertelement <4 x float> %42, float %28, i32 1 %44 = insertelement <4 x float> %43, float %28, i32 2 %45 = insertelement <4 x float> %44, float %28, i32 3 %46 = extractelement <4 x float> %45, i32 0 %47 = extractelement <4 x float> %45, i32 1 %48 = insertelement <4 x float> undef, float %46, i32 0 %49 = insertelement <4 x float> %48, float %47, i32 1 %50 = insertelement <4 x float> %49, float undef, i32 2 %51 = insertelement <4 x float> %50, float undef, i32 3 %52 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %51, i32 17, i32 1, i32 2) %53 = extractelement <4 x float> %52, i32 1 %54 = insertelement <4 x float> undef, float %25, i32 0 %55 = insertelement <4 x float> %54, float %26, i32 1 %56 = insertelement <4 x float> %55, float %26, i32 2 %57 = insertelement <4 x float> %56, float %26, i32 3 %58 = extractelement <4 x float> %57, i32 0 %59 = extractelement <4 x float> %57, i32 1 %60 = insertelement <4 x float> undef, float %58, i32 0 %61 = insertelement <4 x float> %60, float %59, i32 1 %62 = insertelement <4 x float> %61, float undef, i32 2 %63 = insertelement <4 x float> %62, float undef, i32 3 %64 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %63, i32 17, i32 1, i32 2) %65 = extractelement <4 x float> %64, i32 3 %66 = fmul float %40, %40 %67 = fmul float %53, %53 %68 = fmul float %41, %41 %69 = fmul float %65, %65 %70 = fmul float %66, %40 %71 = fmul float %67, %53 %72 = fmul float %68, %41 %73 = fmul float %69, %65 %74 = insertelement <4 x float> undef, float %70, i32 0 %75 = insertelement <4 x float> %74, float %71, i32 1 %76 = insertelement <4 x float> %75, float %72, i32 2 %77 = insertelement <4 x float> %76, float %73, i32 3 %78 = call float @llvm.AMDGPU.dp4(<4 x float> %77, <4 x float> ) %79 = fcmp olt float %78, 0x3EE4F8B580000000 %80 = select i1 %79, float 1.000000e+00, float 0.000000e+00 %81 = fcmp une float %80, 0.000000e+00 br i1 %81, label %IF, label %ENDIF IF: ; preds = %main_body call void @llvm.AMDGPU.kilp() br label %ENDIF ENDIF: ; preds = %main_body, %IF %82 = insertelement <4 x float> undef, float %9, i32 0 %83 = insertelement <4 x float> %82, float %10, i32 1 %84 = insertelement <4 x float> %83, float %10, i32 2 %85 = insertelement <4 x float> %84, float %10, i32 3 %86 = extractelement <4 x float> %85, i32 0 %87 = extractelement <4 x float> %85, i32 1 %88 = insertelement <4 x float> undef, float %86, i32 0 %89 = insertelement <4 x float> %88, float %87, i32 1 %90 = insertelement <4 x float> %89, float undef, i32 2 %91 = insertelement <4 x float> %90, float undef, i32 3 %92 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %91, i32 16, i32 0, i32 2) %93 = extractelement <4 x float> %92, i32 0 %94 = extractelement <4 x float> %92, i32 1 %95 = extractelement <4 x float> %92, i32 2 %96 = extractelement <4 x float> %92, i32 3 %97 = insertelement <4 x float> undef, float %18, i32 0 %98 = insertelement <4 x float> %97, float %19, i32 1 %99 = insertelement <4 x float> %98, float %19, i32 2 %100 = insertelement <4 x float> %99, float %19, i32 3 %101 = extractelement <4 x float> %100, i32 0 %102 = extractelement <4 x float> %100, i32 1 %103 = insertelement <4 x float> undef, float %101, i32 0 %104 = insertelement <4 x float> %103, float %102, i32 1 %105 = insertelement <4 x float> %104, float undef, i32 2 %106 = insertelement <4 x float> %105, float undef, i32 3 %107 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %106, i32 16, i32 0, i32 2) %108 = extractelement <4 x float> %107, i32 0 %109 = extractelement <4 x float> %107, i32 1 %110 = extractelement <4 x float> %107, i32 2 %111 = extractelement <4 x float> %107, i32 3 %112 = fsub float -0.000000e+00, %40 %113 = fadd float 1.000000e+00, %112 %114 = fmul float %93, %113 %115 = fmul float %94, %113 %116 = fmul float %95, %113 %117 = fmul float %96, %113 %118 = fmul float %108, %40 %119 = fadd float %118, %114 %120 = fmul float %109, %40 %121 = fadd float %120, %115 %122 = fmul float %110, %40 %123 = fadd float %122, %116 %124 = fmul float %111, %40 %125 = fadd float %124, %117 %126 = fmul float %119, %70 %127 = fmul float %121, %70 %128 = fmul float %123, %70 %129 = fmul float %125, %70 %130 = insertelement <4 x float> undef, float %27, i32 0 %131 = insertelement <4 x float> %130, float %28, i32 1 %132 = insertelement <4 x float> %131, float %28, i32 2 %133 = insertelement <4 x float> %132, float %28, i32 3 %134 = extractelement <4 x float> %133, i32 0 %135 = extractelement <4 x float> %133, i32 1 %136 = insertelement <4 x float> undef, float %134, i32 0 %137 = insertelement <4 x float> %136, float %135, i32 1 %138 = insertelement <4 x float> %137, float undef, i32 2 %139 = insertelement <4 x float> %138, float undef, i32 3 %140 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %139, i32 16, i32 0, i32 2) %141 = extractelement <4 x float> %140, i32 0 %142 = extractelement <4 x float> %140, i32 1 %143 = extractelement <4 x float> %140, i32 2 %144 = extractelement <4 x float> %140, i32 3 %145 = fsub float -0.000000e+00, %53 %146 = fadd float 1.000000e+00, %145 %147 = fmul float %93, %146 %148 = fmul float %94, %146 %149 = fmul float %95, %146 %150 = fmul float %96, %146 %151 = fmul float %141, %53 %152 = fadd float %151, %147 %153 = fmul float %142, %53 %154 = fadd float %153, %148 %155 = fmul float %143, %53 %156 = fadd float %155, %149 %157 = fmul float %144, %53 %158 = fadd float %157, %150 %159 = fmul float %152, %71 %160 = fadd float %159, %126 %161 = fmul float %154, %71 %162 = fadd float %161, %127 %163 = fmul float %156, %71 %164 = fadd float %163, %128 %165 = fmul float %158, %71 %166 = fadd float %165, %129 %167 = insertelement <4 x float> undef, float %16, i32 0 %168 = insertelement <4 x float> %167, float %17, i32 1 %169 = insertelement <4 x float> %168, float %17, i32 2 %170 = insertelement <4 x float> %169, float %17, i32 3 %171 = extractelement <4 x float> %170, i32 0 %172 = extractelement <4 x float> %170, i32 1 %173 = insertelement <4 x float> undef, float %171, i32 0 %174 = insertelement <4 x float> %173, float %172, i32 1 %175 = insertelement <4 x float> %174, float undef, i32 2 %176 = insertelement <4 x float> %175, float undef, i32 3 %177 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %176, i32 16, i32 0, i32 2) %178 = extractelement <4 x float> %177, i32 0 %179 = extractelement <4 x float> %177, i32 1 %180 = extractelement <4 x float> %177, i32 2 %181 = extractelement <4 x float> %177, i32 3 %182 = fsub float -0.000000e+00, %41 %183 = fadd float 1.000000e+00, %182 %184 = fmul float %93, %183 %185 = fmul float %94, %183 %186 = fmul float %95, %183 %187 = fmul float %96, %183 %188 = fmul float %178, %41 %189 = fadd float %188, %184 %190 = fmul float %179, %41 %191 = fadd float %190, %185 %192 = fmul float %180, %41 %193 = fadd float %192, %186 %194 = fmul float %181, %41 %195 = fadd float %194, %187 %196 = fmul float %189, %72 %197 = fadd float %196, %160 %198 = fmul float %191, %72 %199 = fadd float %198, %162 %200 = fmul float %193, %72 %201 = fadd float %200, %164 %202 = fmul float %195, %72 %203 = fadd float %202, %166 %204 = insertelement <4 x float> undef, float %25, i32 0 %205 = insertelement <4 x float> %204, float %26, i32 1 %206 = insertelement <4 x float> %205, float %26, i32 2 %207 = insertelement <4 x float> %206, float %26, i32 3 %208 = extractelement <4 x float> %207, i32 0 %209 = extractelement <4 x float> %207, i32 1 %210 = insertelement <4 x float> undef, float %208, i32 0 %211 = insertelement <4 x float> %210, float %209, i32 1 %212 = insertelement <4 x float> %211, float undef, i32 2 %213 = insertelement <4 x float> %212, float undef, i32 3 %214 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %213, i32 16, i32 0, i32 2) %215 = extractelement <4 x float> %214, i32 0 %216 = extractelement <4 x float> %214, i32 1 %217 = extractelement <4 x float> %214, i32 2 %218 = extractelement <4 x float> %214, i32 3 %219 = fsub float -0.000000e+00, %65 %220 = fadd float 1.000000e+00, %219 %221 = fmul float %93, %220 %222 = fmul float %94, %220 %223 = fmul float %95, %220 %224 = fmul float %96, %220 %225 = fmul float %215, %65 %226 = fadd float %225, %221 %227 = fmul float %216, %65 %228 = fadd float %227, %222 %229 = fmul float %217, %65 %230 = fadd float %229, %223 %231 = fmul float %218, %65 %232 = fadd float %231, %224 %233 = fmul float %226, %73 %234 = fadd float %233, %197 %235 = fmul float %228, %73 %236 = fadd float %235, %199 %237 = fmul float %230, %73 %238 = fadd float %237, %201 %239 = fmul float %232, %73 %240 = fadd float %239, %203 %241 = fdiv float 1.000000e+00, %78 %242 = fmul float %234, %241 %243 = fmul float %236, %241 %244 = fmul float %238, %241 %245 = fmul float %240, %241 %246 = insertelement <4 x float> undef, float %242, i32 0 %247 = insertelement <4 x float> %246, float %243, i32 1 %248 = insertelement <4 x float> %247, float %244, i32 2 %249 = insertelement <4 x float> %248, float %245, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %249, i32 0, i32 0) ret void } ; Function Attrs: readnone declare <2 x float> @llvm.R600.interp.xy(i32, float, float) #1 ; Function Attrs: readnone declare <2 x float> @llvm.R600.interp.zw(i32, float, float) #1 ; Function Attrs: readnone declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32, i32) #1 ; Function Attrs: readnone declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1 declare void @llvm.AMDGPU.kilp() declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } Shader Disassembly: ALU 21, @26, KC0[], KC1[] ; 0000001A A0540000 TEX 2 @10 ; 0000000A 80400800 ALU_PUSH_BEFORE 15, @48, KC0[], KC1[] ; 00000030 A43C0000 JUMP @5 POP:1 ; 00000005 82800001 ALU_POP_AFTER 0, @64, KC0[], KC1[] ; 00000040 A8000000 ALU 3, @65, KC0[], KC1[] ; 00000041 A00C0000 TEX 4 @16 ; 00000010 80401000 ALU 59, @69, KC0[], KC1[] ; 00000045 A0EC0000 EXPORT T4.XYZW ; C0020000 95200688 CF_END ; 00000000 88000000 Fetch clause starting at 10: ; TEX_SAMPLE T2.XYZW, T0.XY__ RID:17 SID:1 CT:NNNN ; 00001110 F00D1002 FC808000 00000000 TEX_SAMPLE T0.XYZW, T4.XY__ RID:17 SID:1 CT:NNNN ; 00041110 F00D1000 FC808000 00000000 TEX_SAMPLE T1.XYZW, T7.XY__ RID:17 SID:1 CT:NNNN ; 00071110 F00D1001 FC808000 00000000 Fetch clause starting at 16: ; TEX_SAMPLE T7.XYZW, T7.XY__ RID:16 SID:0 CT:NNNN ; 00071010 F00D1007 FC800000 00000000 TEX_SAMPLE T6.XYZW, T6.XY__ RID:16 SID:0 CT:NNNN ; 00061010 F00D1006 FC800000 00000000 TEX_SAMPLE T8.XYZW, T10.XY__ RID:16 SID:0 CT:NNNN ; 000A1010 F00D1008 FC800000 00000000 TEX_SAMPLE T9.XYZW, T9.XY__ RID:16 SID:0 CT:NNNN ; 00091010 F00D1009 FC800000 00000000 TEX_SAMPLE T4.XYZW, T4.XY__ RID:16 SID:0 CT:NNNN ; 00041010 F00D1004 FC800000 00000000 ALU clause starting at 26: ; INTERP_XY T4.X, T0.Y, ARRAY_BASE, ; 00380400 00946B10 INTERP_XY T4.Y, T0.X, ARRAY_BASE, ; 00380000 20946B10 INTERP_XY T0.Z (MASKED), T0.Y, ARRAY_BASE, ; 00380400 40146B00 INTERP_XY * T0.W (MASKED), T0.X, ARRAY_BASE, ; 80380000 60146B00 INTERP_XY T6.X, T0.Y, ARRAY_BASE, ; 00382400 00D46B10 INTERP_XY T6.Y, T0.X, ARRAY_BASE, ; 00382000 20D46B10 INTERP_XY T0.Z (MASKED), T0.Y, ARRAY_BASE, ; 00382400 40146B00 INTERP_XY * T0.W (MASKED), T0.X, ARRAY_BASE, ; 80382000 60146B00 INTERP_ZW T0.X (MASKED), T0.Y, ARRAY_BASE, ; 00382400 00146B80 INTERP_ZW T0.Y (MASKED), T0.X, ARRAY_BASE, ; 00382000 20146B80 INTERP_ZW T8.Z, T0.Y, ARRAY_BASE, ; 00382400 41146B90 INTERP_ZW * T5.W, T0.X, ARRAY_BASE, ; 80382000 60B46B90 INTERP_XY T7.X, T0.Y, ARRAY_BASE, ; 00384400 00F46B10 INTERP_XY T7.Y, T0.X, ARRAY_BASE, ; 00384000 20F46B10 INTERP_XY T0.Z (MASKED), T0.Y, ARRAY_BASE, ; 00384400 40146B00 INTERP_XY * T0.W (MASKED), T0.X, ARRAY_BASE, ; 80384000 60146B00 INTERP_ZW T0.X (MASKED), T0.Y, ARRAY_BASE, ; 00384400 00146B80 INTERP_ZW T0.Y (MASKED), T0.X, ARRAY_BASE, ; 00384000 20146B80 INTERP_ZW T5.Z, T0.Y, ARRAY_BASE, ; 00384400 40B46B90 INTERP_ZW * T8.W, T0.X, ARRAY_BASE, ; 80384000 61146B90 MOV T0.X, PV.Z, ; 000008FE 00000C90 MOV * T0.Y, PV.W, ; 80000CFE 20000C90 ALU clause starting at 48: ; MUL_IEEE T3.X, T1.W, T1.W, ; 01802C01 00600110 MUL_IEEE T5.Y, T0.Z, T0.Z, ; 01000800 20A00110 MUL_IEEE T3.Z, T2.Y, T2.Y, ; 00804402 40600110 MUL_IEEE * T3.W, T0.X, T0.X, ; 80000000 60600110 MUL_IEEE T5.X, PV.W, T0.X, ; 00000CFE 00A00110 MUL_IEEE T3.Y, PV.Z, T2.Y, ; 008048FE 20600110 MUL_IEEE T3.Z, PV.Y, T0.Z, ; 010004FE 40600110 MUL_IEEE * T3.W, PV.X, T1.W, ; 818020FE 60600110 DOT4 T3.X, T5.X, 1.0, ; 001F2005 00605F10 DOT4 T3.Y (MASKED), T3.Y, 1.0, ; 001F2403 20605F00 DOT4 T3.Z (MASKED), T3.Z, 1.0, ; 001F2803 40605F00 DOT4 * T3.W (MASKED), T3.W, 1.0, ; 801F2C03 60605F00 SETGT * T9.W, literal.x, PV.X, ; 801FC0FD 61200490 925353388(1.000000e-05), 0(0.000000e+00) ; 3727C5AC 00000000 SETE_DX10 * T9.W, PV.W, 0.0, ; 801F0CFE 61200610 PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002104 ALU clause starting at 64: ; KILLGT * T5.Y (MASKED), 1.0, 0.0, ; 801F00F9 20A01680 ALU clause starting at 65: ; MOV * T9.X, T8.Z, ; 80000808 01200C90 MOV T10.X, T5.Z, ; 00000805 01400C90 MOV * T9.Y, T5.W, ; 80000C05 21200C90 MOV * T10.Y, T8.W, ; 80000C08 21400C90 ALU clause starting at 69: ; ADD * T5.W, -T0.X, 1.0, ; 801F3000 60A00010 MUL_IEEE T5.Z, T4.Z, PV.W, ; 019FC804 40A00110 ADD * T10.W, -T2.Y, 1.0, ; 801F3402 61400010 MUL_IEEE T5.Y, T4.Z, PV.W, ; 019FC804 20A00110 MULADD_IEEE T5.Z, T9.Z, T0.X, PV.Z, BS:VEC_120/SCL_212 ; 00000809 40AB08FE ADD * T11.W, -T0.Z, 1.0, BS:VEC_201 ; 801F3800 61700010 MUL_IEEE T10.X, T4.Z, PV.W, ; 019FC804 01400110 MUL_IEEE T10.Y, PV.Z, T5.X, ; 0000A8FE 21400110 MULADD_IEEE T5.Z, T8.Z, T2.Y, PV.Y, BS:VEC_120/SCL_212 ; 00804808 40AB04FE ADD * T12.W, -T1.W, 1.0, ; 801F3C01 61800010 MUL_IEEE T5.Y, T4.Z, PV.W, ; 019FC804 20A00110 MULADD_IEEE T5.Z, PV.Z, T3.Y, PV.Y, ; 008068FE 40A304FE MULADD_IEEE * T13.W, T6.Z, T0.Z, PV.X, BS:VEC_120/SCL_212 ; 81000806 61AB00FE MULADD_IEEE T10.X, PV.W, T3.Z, PV.Z, ; 01006CFE 014308FE MULADD_IEEE T5.Y, T7.Z, T1.W, PV.Y, ; 01802807 20A304FE MUL_IEEE * T5.Z, T4.W, T12.W, BS:VEC_021/SCL_122 ; 81818C04 40A40110 MUL_IEEE * T13.W, T4.X, T5.W, ; 8180A004 61A00110 MUL_IEEE T11.X, T4.W, T11.W, ; 01816C04 01600110 MUL_IEEE * T10.Y, T4.W, T5.W, BS:VEC_021/SCL_122 ; 8180AC04 21440110 MUL_IEEE T10.Z, T4.X, T10.W, ; 01814004 41400110 MULADD_IEEE * T13.W, T9.X, T0.X, T13.W, BS:VEC_120/SCL_212 ; 80000009 61AB0C0D MUL_IEEE T12.X, T4.X, T11.W, ; 01816004 01800110 MUL_IEEE T11.Y, PV.W, T5.X, ; 0000ACFE 21600110 MULADD_IEEE * T10.Z, T8.X, T2.Y, PV.Z, BS:VEC_201 ; 80804008 415308FE MULADD_IEEE * T13.W, T9.W, T0.X, T10.Y, ; 80000C09 61A3040A MUL_IEEE T13.X, PV.W, T5.X, ; 0000ACFE 01A00110 MUL_IEEE T10.Y, T4.Y, T5.W, ; 0180A404 21400110 MULADD_IEEE T10.Z, T10.Z, T3.Y, T11.Y, ; 0080680A 4143040B MULADD_IEEE * T5.W, T6.X, T0.Z, T12.X, ; 81000006 60A3000C MULADD_IEEE T12.X, PV.W, T3.Z, PV.Z, ; 01006CFE 018308FE MUL_IEEE T11.Y, T4.Y, T10.W, ; 01814404 21600110 MULADD_IEEE T9.Z, T9.Y, T0.X, PV.Y, BS:VEC_120/SCL_212 ; 00000409 412B04FE MUL_IEEE * T5.W, T4.X, T12.W, BS:VEC_021/SCL_122 ; 81818004 60A40110 MULADD_IEEE T9.X, T7.X, T1.W, PV.W, ; 01802007 01230CFE MUL_IEEE T9.Y, T4.Y, T11.W, BS:VEC_021/SCL_122 ; 01816404 21240110 MUL_IEEE T9.Z, PV.Z, T5.X, ; 0000A8FE 41200110 MULADD_IEEE * T5.W, T8.Y, T2.Y, PV.Y, BS:VEC_120/SCL_212 ; 80804408 60AB04FE MUL_IEEE T5.X, T4.Y, T12.W, ; 01818404 00A00110 MULADD_IEEE T10.Y, PV.W, T3.Y, PV.Z, ; 00806CFE 214308FE MULADD_IEEE T9.Z, T6.Y, T0.Z, PV.Y, BS:VEC_201 ; 01000406 413304FE MUL_IEEE * T4.W, T4.W, T10.W, BS:VEC_021/SCL_122 ; 81814C04 60840110 MULADD_IEEE T2.X, T8.W, T2.Y, PV.W, ; 00804C08 00430CFE MULADD_IEEE T2.Y, PV.Z, T3.Z, PV.Y, ; 010068FE 204304FE MULADD_IEEE T2.Z, T7.Y, T1.W, PV.X, ; 01802407 404300FE MULADD_IEEE * T2.W, T9.X, T3.W, T12.X, BS:VEC_021/SCL_122 ; 81806009 6047000C RECIP_IEEE T3.X, T3.X, ; 00000003 00604310 RECIP_IEEE T3.Y (MASKED), T3.X, ; 00000003 20604300 RECIP_IEEE T3.Z (MASKED), T3.X, ; 00000003 40604300 RECIP_IEEE * T3.W (MASKED), T3.X, ; 80000003 60604300 MUL_IEEE T4.X, T2.W, PV.X, ; 001FCC02 00800110 MULADD_IEEE T2.Y, T2.Z, T3.W, T2.Y, ; 01806802 20430402 MULADD_IEEE T2.Z, T2.X, T3.Y, T13.X, BS:VEC_102/SCL_221 ; 00806002 404F000D MULADD_IEEE * T0.W, T6.W, T0.Z, T11.X, BS:VEC_210 ; 81000C06 6017000B MULADD_IEEE T0.X, PV.W, T3.Z, PV.Z, ; 01006CFE 000308FE MUL_IEEE T4.Y, PV.Y, T3.X, ; 000064FE 20800110 MULADD_IEEE T0.Z, T7.W, T1.W, T5.Z, ; 01802C07 40030805 MULADD_IEEE * T0.W, T5.Y, T3.W, T10.X, BS:VEC_120/SCL_212 ; 81806405 600B000A MUL_IEEE T4.Z, PV.W, T3.X, ; 00006CFE 40800110 MULADD_IEEE * T0.W, PV.Z, T3.W, PV.X, ; 818068FE 600300FE MUL_IEEE * T4.W, PV.W, T3.X, ; 80006CFE 60800110 ===== SHADER #63 ======================================== PS/CAYMAN/CAYMAN ===== ===== 258 dw ===== 14 gprs ===== 1 stack ======================================= 0000 0000001a a0540000 ALU 22 @52 0052 00380400 00946b10 1 x: INTERP_XY R4.x, R0.y, Param0.x VEC_210 0054 00380000 20946b10 y: INTERP_XY R4.y, R0.x, Param0.x VEC_210 0056 00380400 40146b00 z: INTERP_XY __.z, R0.y, Param0.x VEC_210 0058 80380000 60146b00 w: INTERP_XY __.w, R0.x, Param0.x VEC_210 0060 00382400 00d46b10 2 x: INTERP_XY R6.x, R0.y, Param1.x VEC_210 0062 00382000 20d46b10 y: INTERP_XY R6.y, R0.x, Param1.x VEC_210 0064 00382400 40146b00 z: INTERP_XY __.z, R0.y, Param1.x VEC_210 0066 80382000 60146b00 w: INTERP_XY __.w, R0.x, Param1.x VEC_210 0068 00382400 00146b80 3 x: INTERP_ZW __.x, R0.y, Param1.x VEC_210 0070 00382000 20146b80 y: INTERP_ZW __.y, R0.x, Param1.x VEC_210 0072 00382400 41146b90 z: INTERP_ZW R8.z, R0.y, Param1.x VEC_210 0074 80382000 60b46b90 w: INTERP_ZW R5.w, R0.x, Param1.x VEC_210 0076 00384400 00f46b10 4 x: INTERP_XY R7.x, R0.y, Param2.x VEC_210 0078 00384000 20f46b10 y: INTERP_XY R7.y, R0.x, Param2.x VEC_210 0080 00384400 40146b00 z: INTERP_XY __.z, R0.y, Param2.x VEC_210 0082 80384000 60146b00 w: INTERP_XY __.w, R0.x, Param2.x VEC_210 0084 00384400 00146b80 5 x: INTERP_ZW __.x, R0.y, Param2.x VEC_210 0086 00384000 20146b80 y: INTERP_ZW __.y, R0.x, Param2.x VEC_210 0088 00384400 40b46b90 z: INTERP_ZW R5.z, R0.y, Param2.x VEC_210 0090 80384000 61146b90 w: INTERP_ZW R8.w, R0.x, Param2.x VEC_210 0092 000008fe 00000c90 6 x: MOV R0.x, PV.z 0094 80000cfe 20000c90 y: MOV R0.y, PV.w 0002 0000000a 80400800 TEX 3 @20 0020 00001110 f00d1002 fc808000 SAMPLE R2.xyzw, R0.xy__, RID:17, SID:1 CT:NNNN 0024 00041110 f00d1000 fc808000 SAMPLE R0.xyzw, R4.xy__, RID:17, SID:1 CT:NNNN 0028 00071110 f00d1001 fc808000 SAMPLE R1.xyzw, R7.xy__, RID:17, SID:1 CT:NNNN 0004 00000030 a43c0000 ALU_PUSH_BEFORE 16 @96 0096 01802c01 00600110 7 x: MUL_IEEE R3.x, R1.w, R1.w 0098 01000800 20a00110 y: MUL_IEEE R5.y, R0.z, R0.z 0100 00804402 40600110 z: MUL_IEEE R3.z, R2.y, R2.y 0102 80000000 60600110 w: MUL_IEEE R3.w, R0.x, R0.x 0104 00000cfe 00a00110 8 x: MUL_IEEE R5.x, PV.w, R0.x 0106 008048fe 20600110 y: MUL_IEEE R3.y, PV.z, R2.y 0108 010004fe 40600110 z: MUL_IEEE R3.z, PV.y, R0.z 0110 818020fe 60600110 w: MUL_IEEE R3.w, PV.x, R1.w 0112 001f2005 00605f10 9 x: DOT4 R3.x, R5.x, 1.0 0114 001f2403 20605f00 y: DOT4 __.y, R3.y, 1.0 0116 001f2803 40605f00 z: DOT4 __.z, R3.z, 1.0 0118 801f2c03 60605f00 w: DOT4 __.w, R3.w, 1.0 0120 801fc0fd 61200490 10 w: SETGT R9.w, [0x3727c5ac 1e-05].x, PV.x 0122 3727c5ac 0124 801f0cfe 61200610 11 w: SETE_DX10 R9.w, PV.w, 0 0126 801f0cfe 00002104 12 M x: PRED_SETE_INT __.x, PV.w, 0 0006 00000005 82800001 JUMP @10 POP:1 0008 00000040 a8000000 ALU_POP_AFTER 1 @128 0128 801f00f9 20a01680 13 y: KILLGT __.y, 1.0, 0 0010 00000041 a00c0000 ALU 4 @130 0130 80000808 01200c90 14 x: MOV R9.x, R8.z 0132 00000805 01400c90 15 x: MOV R10.x, R5.z 0134 80000c05 21200c90 y: MOV R9.y, R5.w 0136 80000c08 21400c90 16 y: MOV R10.y, R8.w 0012 00000010 80401000 TEX 5 @32 0032 00071010 f00d1007 fc800000 SAMPLE R7.xyzw, R7.xy__, RID:16, SID:0 CT:NNNN 0036 00061010 f00d1006 fc800000 SAMPLE R6.xyzw, R6.xy__, RID:16, SID:0 CT:NNNN 0040 000a1010 f00d1008 fc800000 SAMPLE R8.xyzw, R10.xy__, RID:16, SID:0 CT:NNNN 0044 00091010 f00d1009 fc800000 SAMPLE R9.xyzw, R9.xy__, RID:16, SID:0 CT:NNNN 0048 00041010 f00d1004 fc800000 SAMPLE R4.xyzw, R4.xy__, RID:16, SID:0 CT:NNNN 0014 00000045 a0ec0000 ALU 60 @138 0138 801f3000 60a00010 17 w: ADD R5.w, -R0.x, 1.0 0140 019fc804 40a00110 18 z: MUL_IEEE R5.z, R4.z, PV.w 0142 801f3402 61400010 w: ADD R10.w, -R2.y, 1.0 0144 019fc804 20a00110 19 y: MUL_IEEE R5.y, R4.z, PV.w 0146 00000809 40ab08fe z: MULADD_IEEE R5.z, R9.z, R0.x, PV.z VEC_120 0148 801f3800 61700010 w: ADD R11.w, -R0.z, 1.0 VEC_201 0150 019fc804 01400110 20 x: MUL_IEEE R10.x, R4.z, PV.w 0152 0000a8fe 21400110 y: MUL_IEEE R10.y, PV.z, R5.x 0154 00804808 40ab04fe z: MULADD_IEEE R5.z, R8.z, R2.y, PV.y VEC_120 0156 801f3c01 61800010 w: ADD R12.w, -R1.w, 1.0 0158 019fc804 20a00110 21 y: MUL_IEEE R5.y, R4.z, PV.w 0160 008068fe 40a304fe z: MULADD_IEEE R5.z, PV.z, R3.y, PV.y 0162 81000806 61ab00fe w: MULADD_IEEE R13.w, R6.z, R0.z, PV.x VEC_120 0164 01006cfe 014308fe 22 x: MULADD_IEEE R10.x, PV.w, R3.z, PV.z 0166 01802807 20a304fe y: MULADD_IEEE R5.y, R7.z, R1.w, PV.y 0168 81818c04 40a40110 z: MUL_IEEE R5.z, R4.w, R12.w VEC_021 0170 8180a004 61a00110 23 w: MUL_IEEE R13.w, R4.x, R5.w 0172 01816c04 01600110 24 x: MUL_IEEE R11.x, R4.w, R11.w 0174 8180ac04 21440110 y: MUL_IEEE R10.y, R4.w, R5.w VEC_021 0176 01814004 41400110 25 z: MUL_IEEE R10.z, R4.x, R10.w 0178 80000009 61ab0c0d w: MULADD_IEEE R13.w, R9.x, R0.x, R13.w VEC_120 0180 01816004 01800110 26 x: MUL_IEEE R12.x, R4.x, R11.w 0182 0000acfe 21600110 y: MUL_IEEE R11.y, PV.w, R5.x 0184 80804008 415308fe z: MULADD_IEEE R10.z, R8.x, R2.y, PV.z VEC_201 0186 80000c09 61a3040a 27 w: MULADD_IEEE R13.w, R9.w, R0.x, R10.y 0188 0000acfe 01a00110 28 x: MUL_IEEE R13.x, PV.w, R5.x 0190 0180a404 21400110 y: MUL_IEEE R10.y, R4.y, R5.w 0192 0080680a 4143040b z: MULADD_IEEE R10.z, R10.z, R3.y, R11.y 0194 81000006 60a3000c w: MULADD_IEEE R5.w, R6.x, R0.z, R12.x 0196 01006cfe 018308fe 29 x: MULADD_IEEE R12.x, PV.w, R3.z, PV.z 0198 01814404 21600110 y: MUL_IEEE R11.y, R4.y, R10.w 0200 00000409 412b04fe z: MULADD_IEEE R9.z, R9.y, R0.x, PV.y VEC_120 0202 81818004 60a40110 w: MUL_IEEE R5.w, R4.x, R12.w VEC_021 0204 01802007 01230cfe 30 x: MULADD_IEEE R9.x, R7.x, R1.w, PV.w 0206 01816404 21240110 y: MUL_IEEE R9.y, R4.y, R11.w VEC_021 0208 0000a8fe 41200110 z: MUL_IEEE R9.z, PV.z, R5.x 0210 80804408 60ab04fe w: MULADD_IEEE R5.w, R8.y, R2.y, PV.y VEC_120 0212 01818404 00a00110 31 x: MUL_IEEE R5.x, R4.y, R12.w 0214 00806cfe 214308fe y: MULADD_IEEE R10.y, PV.w, R3.y, PV.z 0216 01000406 413304fe z: MULADD_IEEE R9.z, R6.y, R0.z, PV.y VEC_201 0218 81814c04 60840110 w: MUL_IEEE R4.w, R4.w, R10.w VEC_021 0220 00804c08 00430cfe 32 x: MULADD_IEEE R2.x, R8.w, R2.y, PV.w 0222 010068fe 204304fe y: MULADD_IEEE R2.y, PV.z, R3.z, PV.y 0224 01802407 404300fe z: MULADD_IEEE R2.z, R7.y, R1.w, PV.x 0226 81806009 6047000c w: MULADD_IEEE R2.w, R9.x, R3.w, R12.x VEC_021 0228 00000003 00604310 33 x: RECIP_IEEE R3.x, R3.x 0230 00000003 20604300 y: RECIP_IEEE __.y, R3.x 0232 00000003 40604300 z: RECIP_IEEE __.z, R3.x 0234 80000003 60604300 w: RECIP_IEEE __.w, R3.x 0236 001fcc02 00800110 34 x: MUL_IEEE R4.x, R2.w, PV.x 0238 01806802 20430402 y: MULADD_IEEE R2.y, R2.z, R3.w, R2.y 0240 00806002 404f000d z: MULADD_IEEE R2.z, R2.x, R3.y, R13.x VEC_102 0242 81000c06 6017000b w: MULADD_IEEE R0.w, R6.w, R0.z, R11.x VEC_210 0244 01006cfe 000308fe 35 x: MULADD_IEEE R0.x, PV.w, R3.z, PV.z 0246 000064fe 20800110 y: MUL_IEEE R4.y, PV.y, R3.x 0248 01802c07 40030805 z: MULADD_IEEE R0.z, R7.w, R1.w, R5.z 0250 81806405 600b000a w: MULADD_IEEE R0.w, R5.y, R3.w, R10.x VEC_120 0252 00006cfe 40800110 36 z: MUL_IEEE R4.z, PV.w, R3.x 0254 818068fe 600300fe w: MULADD_IEEE R0.w, PV.z, R3.w, PV.x 0256 80006cfe 60800110 37 w: MUL_IEEE R4.w, PV.w, R3.x 0016 c0020000 95200688 EXPORT_DONE PIXEL 0 R4.xyzw 0018 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #63 OPT ==================================== PS/CAYMAN/CAYMAN ===== ===== 236 dw ===== 8 gprs ===== 0 stack ======================================== 0000 00000007 a02c0000 ALU 12 @14 0014 00384400 00146b80 1 x: INTERP_ZW __.x, R0.y, Param2.x VEC_210 0016 00b84000 20146b80 y: INTERP_ZW __.y, R0.x, Param2.y VEC_210 0018 01384400 40546b90 z: INTERP_ZW R2.z, R0.y, Param2.z VEC_210 0020 81b84000 60546b90 w: INTERP_ZW R2.w, R0.x, Param2.w VEC_210 0022 00380400 00346b10 2 x: INTERP_XY R1.x, R0.y, Param0.x VEC_210 0024 00b80000 20346b10 y: INTERP_XY R1.y, R0.x, Param0.y VEC_210 0026 01380400 40146b00 z: INTERP_XY __.z, R0.y, Param0.z VEC_210 0028 81b80000 60146b00 w: INTERP_XY __.w, R0.x, Param0.w VEC_210 0030 00384400 00946b10 3 x: INTERP_XY R4.x, R0.y, Param2.x VEC_210 0032 00b84000 20946b10 y: INTERP_XY R4.y, R0.x, Param2.y VEC_210 0034 01384400 40146b00 z: INTERP_XY __.z, R0.y, Param2.z VEC_210 0036 81b84000 60146b00 w: INTERP_XY __.w, R0.x, Param2.w VEC_210 0002 00000014 80400800 TEX 3 @40 0040 00041110 f01dfe05 fc808000 SAMPLE R5.__w_, R4.xy__, RID:17, SID:1 CT:NNNN 0044 00011110 f01fa005 fc808000 SAMPLE R5.xz__, R1.xy__, RID:17, SID:1 CT:NNNN 0048 00021110 f007fe05 fda08000 SAMPLE R5.___y, R2.zw__, RID:17, SID:1 CT:NNNN 0004 0000001a a0540000 ALU 22 @52 0052 0180ac05 0f800110 4 x: MUL_IEEE T0.x, R5.w, R5.w 0054 0000a005 2f800110 y: MUL_IEEE T0.y, R5.x, R5.x 0056 0100a805 4f800110 z: MUL_IEEE T0.z, R5.z, R5.z 0058 8080a405 6f800110 w: MUL_IEEE T0.w, R5.y, R5.y 0060 0000a47c 00c00110 5 x: MUL_IEEE R6.x, T0.y, R5.x 0062 0180a07c 20c00110 y: MUL_IEEE R6.y, T0.x, R5.w 0064 0080ac7c 40e00110 z: MUL_IEEE R7.z, T0.w, R5.y 0066 8100a87c 60c00110 w: MUL_IEEE R6.w, T0.z, R5.z 0068 001f2006 00005f00 6 x: DOT4 __.x, R6.x, 1.0 0070 001f2406 20005f00 y: DOT4 __.y, R6.y, 1.0 0072 001f2807 40c05f10 z: DOT4 R6.z, R7.z, 1.0 0074 801f2c06 60005f00 w: DOT4 __.w, R6.w, 1.0 0076 00382400 00746b10 7 x: INTERP_XY R3.x, R0.y, Param1.x VEC_210 0078 00b82000 20746b10 y: INTERP_XY R3.y, R0.x, Param1.y VEC_210 0080 01382400 40146b00 z: INTERP_XY __.z, R0.y, Param1.z VEC_210 0082 81b82000 60146b00 w: INTERP_XY __.w, R0.x, Param1.w VEC_210 0084 00382400 00146b80 8 x: INTERP_ZW __.x, R0.y, Param1.x VEC_210 0086 00b82000 20146b80 y: INTERP_ZW __.y, R0.x, Param1.y VEC_210 0088 01382400 40346b90 z: INTERP_ZW R1.z, R0.y, Param1.z VEC_210 0090 81b82000 60346b90 w: INTERP_ZW R1.w, R0.x, Param1.w VEC_210 0092 8100c0fd 00001680 9 x: KILLGT __.x, [0x3727c5ac 1e-05].x, R6.z 0094 3727c5ac 0006 00000030 80401000 TEX 5 @96 0096 00011010 f00d1000 fc800000 SAMPLE R0.xyzw, R1.xy__, RID:16, SID:0 CT:NNNN 0100 00011010 f00d1001 fda00000 SAMPLE R1.xyzw, R1.zw__, RID:16, SID:0 CT:NNNN 0104 00021010 f00d1002 fda00000 SAMPLE R2.xyzw, R2.zw__, RID:16, SID:0 CT:NNNN 0108 00031010 f00d1003 fc800000 SAMPLE R3.xyzw, R3.xy__, RID:16, SID:0 CT:NNNN 0112 00041010 f00d1004 fc800000 SAMPLE R4.xyzw, R4.xy__, RID:16, SID:0 CT:NNNN 0008 0000003a a0ec0000 ALU 60 @116 0116 801f3005 6f800010 10 w: ADD T0.w, -R5.x, 1.0 0118 818f8000 0f800110 11 x: MUL_IEEE T0.x, R0.x, T0.w 0120 001f3c05 0f800010 12 x: ADD T0.x, -R5.w, 1.0 0122 0000a001 2fa3007c y: MULADD_IEEE T1.y, R1.x, R5.x, T0.x 0124 818f8800 4fa00110 z: MUL_IEEE T1.z, R0.z, T0.w 0126 018f8c00 2f800110 13 y: MUL_IEEE T0.y, R0.w, T0.w 0128 000f8c00 4f800110 z: MUL_IEEE T0.z, R0.w, T0.x 0130 818f8400 6f800110 w: MUL_IEEE T0.w, R0.y, T0.w 0132 000f8000 0fa00110 14 x: MUL_IEEE T1.x, R0.x, T0.x 0134 001f3405 2ff00010 y: ADD T3.y, -R5.y, 1.0 VEC_201 0136 000f8400 4fc00110 z: MUL_IEEE T2.z, R0.y, T0.x 0138 8000ac01 6fc7047c w: MULADD_IEEE T2.w, R1.w, R5.x, T0.y VEC_021 0140 000f8800 0f900110 15 x: MUL_IEEE T0.x, R0.z, T0.x VEC_201 0142 0000a801 2f87087d y: MULADD_IEEE T0.y, R1.z, R5.x, T1.z VEC_021 0144 0000c47d 4fa00110 z: MUL_IEEE T1.z, T1.y, R6.x 0146 8000a401 6f8b0c7c w: MULADD_IEEE T0.w, R1.y, R5.x, T0.w VEC_120 0148 0180ac02 0fc3087c 16 x: MULADD_IEEE T2.x, R2.w, R5.w, T0.z 0150 0180a002 2fc7007d y: MULADD_IEEE T2.y, R2.x, R5.w, T1.x VEC_021 0152 001f3805 4fe80010 z: ADD T3.z, -R5.z, 1.0 VEC_120 0154 8180a802 6fa3007c w: MULADD_IEEE T1.w, R2.z, R5.w, T0.x 0156 0000c47c 0fa00110 17 x: MUL_IEEE T1.x, T0.y, R6.x 0158 0000cc7e 2fa80110 y: MUL_IEEE T1.y, T2.w, R6.x VEC_120 0160 008fe800 4f800110 z: MUL_IEEE T0.z, R0.z, T3.y 0162 808fec00 6fc00110 w: MUL_IEEE T2.w, R0.w, T3.y 0164 008fe000 0f800110 18 x: MUL_IEEE T0.x, R0.x, T3.y 0166 008fe400 2f940110 y: MUL_IEEE T0.y, R0.y, T3.y VEC_210 0168 0180a402 4fc3087e z: MULADD_IEEE T2.z, R2.y, R5.w, T2.z 0170 8000cc7c 6f800110 w: MUL_IEEE T0.w, T0.w, R6.x 0172 0080cc7d 0fe3007d 19 x: MULADD_IEEE T3.x, T1.w, R6.y, T1.x 0174 0080c07e 2fc3047d y: MULADD_IEEE T2.y, T2.x, R6.y, T1.y 0176 0080c47e 4fa3087d z: MULADD_IEEE T1.z, T2.y, R6.y, T1.z 0178 810fec00 6fac0110 w: MUL_IEEE T1.w, R0.w, T3.z VEC_102 0180 0080ac03 0fa30c7e 20 x: MULADD_IEEE T1.x, R3.w, R5.y, T2.w 0182 0080a003 2fa3007c y: MULADD_IEEE T1.y, R3.x, R5.y, T0.x 0184 0080a403 4f83047c z: MULADD_IEEE T0.z, R3.y, R5.y, T0.y 0186 8080a803 6fc3087c w: MULADD_IEEE T2.w, R3.z, R5.y, T0.z 0188 010fe000 0f800110 21 x: MUL_IEEE T0.x, R0.x, T3.z 0190 010fe400 2f940110 y: MUL_IEEE T0.y, R0.y, T3.z VEC_210 0192 010fe800 4fc00110 z: MUL_IEEE T2.z, R0.z, T3.z 0194 8080c87e 6f930c7c w: MULADD_IEEE T0.w, T2.z, R6.y, T0.w VEC_201 0196 0100e07d 0fc3047e 22 x: MULADD_IEEE T2.x, T1.x, R7.z, T2.y 0198 0100e47d 4fa3087d z: MULADD_IEEE T1.z, T1.y, R7.z, T1.z 0200 8100ac04 6faf0c7d w: MULADD_IEEE T1.w, R4.w, R5.z, T1.w VEC_102 0202 0100e87c 0fa30c7c 23 x: MULADD_IEEE T1.x, T0.z, R7.z, T0.w 0204 0100a004 2fa7007c y: MULADD_IEEE T1.y, R4.x, R5.z, T0.x VEC_021 0206 0100ec7e 4f83007f z: MULADD_IEEE T0.z, T2.w, R7.z, T3.x 0208 8100a404 6f87047c w: MULADD_IEEE T0.w, R4.y, R5.z, T0.y VEC_021 0210 00000806 0f804310 24 x: RECIP_IEEE T0.x, R6.z 0212 00000806 20004300 y: RECIP_IEEE __.y, R6.z 0214 00000806 40004300 z: RECIP_IEEE __.z, R6.z 0216 80000806 60004300 w: RECIP_IEEE __.w, R6.z 0218 0100a804 2f83087e 25 y: MULADD_IEEE T0.y, R4.z, R5.z, T2.z 0220 8180cc7d 6fa3007e w: MULADD_IEEE T1.w, T1.w, R6.w, T2.x 0222 0180c47c 2f8b087c 26 y: MULADD_IEEE T0.y, T0.y, R6.w, T0.z VEC_120 0224 0180cc7c 4f83007d z: MULADD_IEEE T0.z, T0.w, R6.w, T1.x 0226 8180c47d 6f83087d w: MULADD_IEEE T0.w, T1.y, R6.w, T1.z 0228 000f8c7c 00000110 27 x: MUL_IEEE R0.x, T0.w, T0.x 0230 000f887c 20000110 y: MUL_IEEE R0.y, T0.z, T0.x 0232 000f847c 40000110 z: MUL_IEEE R0.z, T0.y, T0.x 0234 800f8c7d 60080110 w: MUL_IEEE R0.w, T1.w, T0.x VEC_120 0010 c0000000 95000688 EXPORT_DONE PIXEL 0 R0.xyzw 0012 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL CONST[1..4] DCL TEMP[0], LOCAL 0: MOV TEMP[0].xy, IN[0].xyyy 1: MOV TEMP[0].w, IN[0].wwww 2: TXP TEMP[0], TEMP[0], SAMP[0], 2D 3: MUL TEMP[0], TEMP[0], CONST[4] 4: MOV OUT[0], TEMP[0] 5: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg) #0 { main_body: %2 = extractelement <4 x float> %0, i32 0 %3 = extractelement <4 x float> %0, i32 1 %4 = call <2 x float> @llvm.R600.interp.xy(i32 0, float %2, float %3) %5 = call <2 x float> @llvm.R600.interp.zw(i32 0, float %2, float %3) %6 = shufflevector <2 x float> %4, <2 x float> %5, <4 x i32> %7 = extractelement <4 x float> %6, i32 0 %8 = extractelement <4 x float> %6, i32 1 %9 = extractelement <4 x float> %6, i32 3 %10 = fdiv float %7, %9 %11 = fdiv float %8, %9 %12 = fdiv float 0.000000e+00, %9 %13 = insertelement <4 x float> undef, float %10, i32 0 %14 = insertelement <4 x float> %13, float %11, i32 1 %15 = insertelement <4 x float> %14, float %12, i32 2 %16 = insertelement <4 x float> %15, float 1.000000e+00, i32 3 %17 = extractelement <4 x float> %16, i32 0 %18 = extractelement <4 x float> %16, i32 1 %19 = insertelement <4 x float> undef, float %17, i32 0 %20 = insertelement <4 x float> %19, float %18, i32 1 %21 = insertelement <4 x float> %20, float undef, i32 2 %22 = insertelement <4 x float> %21, float undef, i32 3 %23 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %22, i32 16, i32 0, i32 2) %24 = extractelement <4 x float> %23, i32 0 %25 = extractelement <4 x float> %23, i32 1 %26 = extractelement <4 x float> %23, i32 2 %27 = extractelement <4 x float> %23, i32 3 %28 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) %29 = extractelement <4 x float> %28, i32 0 %30 = fmul float %24, %29 %31 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) %32 = extractelement <4 x float> %31, i32 1 %33 = fmul float %25, %32 %34 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) %35 = extractelement <4 x float> %34, i32 2 %36 = fmul float %26, %35 %37 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) %38 = extractelement <4 x float> %37, i32 3 %39 = fmul float %27, %38 %40 = insertelement <4 x float> undef, float %30, i32 0 %41 = insertelement <4 x float> %40, float %33, i32 1 %42 = insertelement <4 x float> %41, float %36, i32 2 %43 = insertelement <4 x float> %42, float %39, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %43, i32 0, i32 0) ret void } ; Function Attrs: readnone declare <2 x float> @llvm.R600.interp.xy(i32, float, float) #1 ; Function Attrs: readnone declare <2 x float> @llvm.R600.interp.zw(i32, float, float) #1 ; Function Attrs: readnone declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32, i32) #1 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } Shader Disassembly: ALU 13, @8, KC0[], KC1[] ; 00000008 A0340000 TEX 0 @6 ; 00000006 80400000 ALU 3, @22, KC0[CB0:0-32], KC1[] ; 80000016 A00C0000 EXPORT T1.XYZW ; C0008000 95200688 CF_END ; 00000000 88000000 PAD ; 00000000 00000000 Fetch clause starting at 6: ; TEX_SAMPLE T0.XYZW, T2.XY__ RID:16 SID:0 CT:NNNN ; 00021010 F00D1000 FC800000 00000000 ALU clause starting at 8: ; INTERP_XY T1.X, T0.Y, ARRAY_BASE, ; 00380400 00346B10 INTERP_XY T1.Y, T0.X, ARRAY_BASE, ; 00380000 20346B10 INTERP_XY T0.Z (MASKED), T0.Y, ARRAY_BASE, ; 00380400 40146B00 INTERP_XY * T0.W (MASKED), T0.X, ARRAY_BASE, ; 80380000 60146B00 INTERP_ZW T0.X (MASKED), T0.Y, ARRAY_BASE, ; 00380400 00146B80 INTERP_ZW T0.Y (MASKED), T0.X, ARRAY_BASE, ; 00380000 20146B80 INTERP_ZW T0.Z, T0.Y, ARRAY_BASE, ; 00380400 40146B90 INTERP_ZW * T0.W, T0.X, ARRAY_BASE, ; 80380000 60146B90 RECIP_IEEE T0.X, T0.W, ; 00000C00 00004310 RECIP_IEEE T0.Y (MASKED), T0.W, ; 00000C00 20004300 RECIP_IEEE T0.Z (MASKED), T0.W, ; 00000C00 40004300 RECIP_IEEE * T0.W (MASKED), T0.W, ; 80000C00 60004300 MUL_IEEE T2.X, T1.X, PV.X, ; 001FC001 00400110 MUL_IEEE * T2.Y, T1.Y, PV.X, ; 801FC401 20400110 ALU clause starting at 22: ; MUL_IEEE T1.X, T0.X, KC0[4].X, ; 00108000 00200110 MUL_IEEE T1.Y, T0.Y, KC0[4].Y, ; 00908400 20200110 MUL_IEEE T1.Z, T0.Z, KC0[4].Z, ; 01108800 40200110 MUL_IEEE * T1.W, T0.W, KC0[4].W, ; 81908C00 60200110 ===== SHADER #64 ======================================== PS/CAYMAN/CAYMAN ===== ===== 52 dw ===== 3 gprs ===== 1 stack ========================================= 0000 00000008 a0340000 ALU 14 @16 0016 00380400 00346b10 1 x: INTERP_XY R1.x, R0.y, Param0.x VEC_210 0018 00380000 20346b10 y: INTERP_XY R1.y, R0.x, Param0.x VEC_210 0020 00380400 40146b00 z: INTERP_XY __.z, R0.y, Param0.x VEC_210 0022 80380000 60146b00 w: INTERP_XY __.w, R0.x, Param0.x VEC_210 0024 00380400 00146b80 2 x: INTERP_ZW __.x, R0.y, Param0.x VEC_210 0026 00380000 20146b80 y: INTERP_ZW __.y, R0.x, Param0.x VEC_210 0028 00380400 40146b90 z: INTERP_ZW R0.z, R0.y, Param0.x VEC_210 0030 80380000 60146b90 w: INTERP_ZW R0.w, R0.x, Param0.x VEC_210 0032 00000c00 00004310 3 x: RECIP_IEEE R0.x, R0.w 0034 00000c00 20004300 y: RECIP_IEEE __.y, R0.w 0036 00000c00 40004300 z: RECIP_IEEE __.z, R0.w 0038 80000c00 60004300 w: RECIP_IEEE __.w, R0.w 0040 001fc001 00400110 4 x: MUL_IEEE R2.x, R1.x, PV.x 0042 801fc401 20400110 y: MUL_IEEE R2.y, R1.y, PV.x 0002 00000006 80400000 TEX 1 @12 0012 00021010 f00d1000 fc800000 SAMPLE R0.xyzw, R2.xy__, RID:16, SID:0 CT:NNNN 0004 80000016 a00c0000 ALU 4 @44 KC0[CB0:0-31] 0044 00108000 00200110 5 x: MUL_IEEE R1.x, R0.x, KC0[4].x 0046 00908400 20200110 y: MUL_IEEE R1.y, R0.y, KC0[4].y 0048 01108800 40200110 z: MUL_IEEE R1.z, R0.z, KC0[4].z 0050 81908c00 60200110 w: MUL_IEEE R1.w, R0.w, KC0[4].w 0006 c0008000 95200688 EXPORT_DONE PIXEL 0 R1.xyzw 0008 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #64 OPT ==================================== PS/CAYMAN/CAYMAN ===== ===== 52 dw ===== 1 gprs ===== 0 stack ========================================= 0000 00000005 a0340000 ALU 14 @10 0010 00380400 00146b80 1 x: INTERP_ZW __.x, R0.y, Param0.x VEC_210 0012 00b80000 20146b80 y: INTERP_ZW __.y, R0.x, Param0.y VEC_210 0014 01380400 40146b80 z: INTERP_ZW __.z, R0.y, Param0.z VEC_210 0016 81b80000 6f946b90 w: INTERP_ZW T0.w, R0.x, Param0.w VEC_210 0018 00000c7c 00004300 2 x: RECIP_IEEE __.x, T0.w 0020 00000c7c 20004300 y: RECIP_IEEE __.y, T0.w 0022 00000c7c 4f804310 z: RECIP_IEEE T0.z, T0.w 0024 80000c7c 60004300 w: RECIP_IEEE __.w, T0.w 0026 00380400 0f946b10 3 x: INTERP_XY T0.x, R0.y, Param0.x VEC_210 0028 00b80000 2f946b10 y: INTERP_XY T0.y, R0.x, Param0.y VEC_210 0030 01380400 40146b00 z: INTERP_XY __.z, R0.y, Param0.z VEC_210 0032 81b80000 60146b00 w: INTERP_XY __.w, R0.x, Param0.w VEC_210 0034 010f807c 00000110 4 x: MUL_IEEE R0.x, T0.x, T0.z 0036 810f847c 20000110 y: MUL_IEEE R0.y, T0.y, T0.z 0002 00000014 80400000 TEX 1 @40 0040 00001010 f00d1000 fc800000 SAMPLE R0.xyzw, R0.xy__, RID:16, SID:0 CT:NNNN 0004 40000016 a00c0000 ALU 4 @44 KC0[CB0:0-15] 0044 00108000 00000110 5 x: MUL_IEEE R0.x, R0.x, KC0[4].x 0046 00908400 20000110 y: MUL_IEEE R0.y, R0.y, KC0[4].y 0048 01108800 40000110 z: MUL_IEEE R0.z, R0.z, KC0[4].z 0050 81908c00 60000110 w: MUL_IEEE R0.w, R0.w, KC0[4].w 0006 c0000000 95000688 EXPORT_DONE PIXEL 0 R0.xyzw 0008 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] DCL CONST[0..3] DCL TEMP[0] 0: MUL TEMP[0], IN[0].xxxx, CONST[0] 1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0] 2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0] 3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0] 4: MOV OUT[1], IN[1] 5: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg, <4 x float> inreg) #0 { main_body: %3 = extractelement <4 x float> %1, i32 0 %4 = extractelement <4 x float> %1, i32 1 %5 = extractelement <4 x float> %1, i32 2 %6 = extractelement <4 x float> %1, i32 3 %7 = extractelement <4 x float> %2, i32 0 %8 = extractelement <4 x float> %2, i32 1 %9 = extractelement <4 x float> %2, i32 2 %10 = extractelement <4 x float> %2, i32 3 %11 = load <4 x float> addrspace(8)* null %12 = extractelement <4 x float> %11, i32 0 %13 = fmul float %3, %12 %14 = load <4 x float> addrspace(8)* null %15 = extractelement <4 x float> %14, i32 1 %16 = fmul float %3, %15 %17 = load <4 x float> addrspace(8)* null %18 = extractelement <4 x float> %17, i32 2 %19 = fmul float %3, %18 %20 = load <4 x float> addrspace(8)* null %21 = extractelement <4 x float> %20, i32 3 %22 = fmul float %3, %21 %23 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %24 = extractelement <4 x float> %23, i32 0 %25 = fmul float %4, %24 %26 = fadd float %25, %13 %27 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %28 = extractelement <4 x float> %27, i32 1 %29 = fmul float %4, %28 %30 = fadd float %29, %16 %31 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %32 = extractelement <4 x float> %31, i32 2 %33 = fmul float %4, %32 %34 = fadd float %33, %19 %35 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %36 = extractelement <4 x float> %35, i32 3 %37 = fmul float %4, %36 %38 = fadd float %37, %22 %39 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %40 = extractelement <4 x float> %39, i32 0 %41 = fmul float %5, %40 %42 = fadd float %41, %26 %43 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %44 = extractelement <4 x float> %43, i32 1 %45 = fmul float %5, %44 %46 = fadd float %45, %30 %47 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %48 = extractelement <4 x float> %47, i32 2 %49 = fmul float %5, %48 %50 = fadd float %49, %34 %51 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %52 = extractelement <4 x float> %51, i32 3 %53 = fmul float %5, %52 %54 = fadd float %53, %38 %55 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %56 = extractelement <4 x float> %55, i32 0 %57 = fmul float %6, %56 %58 = fadd float %57, %42 %59 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %60 = extractelement <4 x float> %59, i32 1 %61 = fmul float %6, %60 %62 = fadd float %61, %46 %63 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %64 = extractelement <4 x float> %63, i32 2 %65 = fmul float %6, %64 %66 = fadd float %65, %50 %67 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %68 = extractelement <4 x float> %67, i32 3 %69 = fmul float %6, %68 %70 = fadd float %69, %54 %71 = insertelement <4 x float> undef, float %58, i32 0 %72 = insertelement <4 x float> %71, float %62, i32 1 %73 = insertelement <4 x float> %72, float %66, i32 2 %74 = insertelement <4 x float> %73, float %70, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %74, i32 60, i32 1) %75 = insertelement <4 x float> undef, float %7, i32 0 %76 = insertelement <4 x float> %75, float %8, i32 1 %77 = insertelement <4 x float> %76, float %9, i32 2 %78 = insertelement <4 x float> %77, float %10, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %78, i32 0, i32 2) ret void } declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="1" } Shader Disassembly: CALL_FS ; 00000000 84C00000 ALU 15, @6, KC0[CB0:0-32], KC1[] ; 80000006 A03C0000 EXPORT T0.XYZW ; C000203C 95000688 EXPORT T2.XYZW ; C0014000 95200688 CF_END ; 00000000 88000000 PAD ; 00000000 00000000 ALU clause starting at 6: ; MUL_IEEE * T0.W, T1.X, KC0[0].X, ; 80100001 60000110 MULADD_IEEE T0.Z, T1.Y, KC0[1].X, PV.W, ; 00102401 40030CFE MUL_IEEE * T0.W, T1.X, KC0[0].Y, ; 80900001 60000110 MULADD_IEEE T3.Z, T1.Y, KC0[1].Y, PV.W, ; 00902401 40630CFE MULADD_IEEE * T0.W, T1.Z, KC0[2].X, PV.Z, ; 80104801 600308FE MULADD_IEEE T0.X, T1.W, KC0[3].X, PV.W, ; 00106C01 00030CFE MULADD_IEEE * T3.W, T1.Z, KC0[2].Y, PV.Z, ; 80904801 606308FE MULADD_IEEE T0.Y, T1.W, KC0[3].Y, PV.W, ; 00906C01 20030CFE MUL_IEEE * T3.W, T1.X, KC0[0].Z, ; 81100001 60600110 MULADD_IEEE T3.Z, T1.Y, KC0[1].Z, PV.W, ; 01102401 40630CFE MUL_IEEE * T3.W, T1.X, KC0[0].W, ; 81900001 60600110 MULADD_IEEE T4.Z, T1.Y, KC0[1].W, PV.W, ; 01902401 40830CFE MULADD_IEEE * T3.W, T1.Z, KC0[2].Z, PV.Z, ; 81104801 606308FE MULADD_IEEE T0.Z, T1.W, KC0[3].Z, PV.W, ; 01106C01 40030CFE MULADD_IEEE * T3.W, T1.Z, KC0[2].W, PV.Z, ; 81904801 606308FE MULADD_IEEE * T0.W, T1.W, KC0[3].W, PV.W, ; 81906C01 60030CFE ===== SHADER #65 ======================================== VS/CAYMAN/CAYMAN ===== ===== 44 dw ===== 5 gprs ===== 1 stack ========================================= 0000 00000000 84c00000 CALL_FS @0 0002 80000006 a03c0000 ALU 16 @12 KC0[CB0:0-31] 0012 80100001 60000110 1 w: MUL_IEEE R0.w, R1.x, KC0[0].x 0014 00102401 40030cfe 2 z: MULADD_IEEE R0.z, R1.y, KC0[1].x, PV.w 0016 80900001 60000110 w: MUL_IEEE R0.w, R1.x, KC0[0].y 0018 00902401 40630cfe 3 z: MULADD_IEEE R3.z, R1.y, KC0[1].y, PV.w 0020 80104801 600308fe w: MULADD_IEEE R0.w, R1.z, KC0[2].x, PV.z 0022 00106c01 00030cfe 4 x: MULADD_IEEE R0.x, R1.w, KC0[3].x, PV.w 0024 80904801 606308fe w: MULADD_IEEE R3.w, R1.z, KC0[2].y, PV.z 0026 00906c01 20030cfe 5 y: MULADD_IEEE R0.y, R1.w, KC0[3].y, PV.w 0028 81100001 60600110 w: MUL_IEEE R3.w, R1.x, KC0[0].z 0030 01102401 40630cfe 6 z: MULADD_IEEE R3.z, R1.y, KC0[1].z, PV.w 0032 81900001 60600110 w: MUL_IEEE R3.w, R1.x, KC0[0].w 0034 01902401 40830cfe 7 z: MULADD_IEEE R4.z, R1.y, KC0[1].w, PV.w 0036 81104801 606308fe w: MULADD_IEEE R3.w, R1.z, KC0[2].z, PV.z 0038 01106c01 40030cfe 8 z: MULADD_IEEE R0.z, R1.w, KC0[3].z, PV.w 0040 81904801 606308fe w: MULADD_IEEE R3.w, R1.z, KC0[2].w, PV.z 0042 81906c01 60030cfe 9 w: MULADD_IEEE R0.w, R1.w, KC0[3].w, PV.w 0004 c000203c 95000688 EXPORT_DONE POS 60 R0.xyzw 0006 c0014000 95200688 EXPORT_DONE PARAM 0 R2.xyzw 0008 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #65 OPT ==================================== VS/CAYMAN/CAYMAN ===== ===== 42 dw ===== 3 gprs ===== 1 stack ========================================= 0000 00000000 84c00000 CALL_FS @0 0002 40000005 a03c0000 ALU 16 @10 KC0[CB0:0-15] 0010 01900001 0f800110 1 x: MUL_IEEE T0.x, R1.x, KC0[0].w 0012 01100001 2f800110 y: MUL_IEEE T0.y, R1.x, KC0[0].z 0014 00900001 4f800110 z: MUL_IEEE T0.z, R1.x, KC0[0].y 0016 80100001 6f800110 w: MUL_IEEE T0.w, R1.x, KC0[0].x 0018 01902401 0f83007c 2 x: MULADD_IEEE T0.x, R1.y, KC0[1].w, T0.x 0020 01102401 2f83047c y: MULADD_IEEE T0.y, R1.y, KC0[1].z, T0.y 0022 00902401 4f83087c z: MULADD_IEEE T0.z, R1.y, KC0[1].y, T0.z 0024 80102401 6f830c7c w: MULADD_IEEE T0.w, R1.y, KC0[1].x, T0.w 0026 01904801 0f83007c 3 x: MULADD_IEEE T0.x, R1.z, KC0[2].w, T0.x 0028 01104801 2f83047c y: MULADD_IEEE T0.y, R1.z, KC0[2].z, T0.y 0030 00904801 4f83087c z: MULADD_IEEE T0.z, R1.z, KC0[2].y, T0.z 0032 80104801 6f830c7c w: MULADD_IEEE T0.w, R1.z, KC0[2].x, T0.w 0034 00106c01 00030c7c 4 x: MULADD_IEEE R0.x, R1.w, KC0[3].x, T0.w 0036 00906c01 2003087c y: MULADD_IEEE R0.y, R1.w, KC0[3].y, T0.z 0038 01106c01 4003047c z: MULADD_IEEE R0.z, R1.w, KC0[3].z, T0.y 0040 81906c01 6003007c w: MULADD_IEEE R0.w, R1.w, KC0[3].w, T0.x 0004 c000203c 95000688 EXPORT_DONE POS 60 R0.xyzw 0006 c0014000 95000688 EXPORT_DONE PARAM 0 R2.xyzw 0008 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== Generating new string page texture 2: 48x256, total string texture memory is 49.15 KB -------------------------------------------------------------- FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], COLOR, COLOR DCL IN[1], GENERIC[0], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL TEMP[0], LOCAL 0: MOV TEMP[0].xy, IN[1].xyyy 1: MOV TEMP[0].w, IN[1].wwww 2: TXP TEMP[0], TEMP[0], SAMP[0], 2D 3: MUL TEMP[0], TEMP[0], IN[0] 4: MOV OUT[0], TEMP[0] 5: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg, <4 x float> inreg) #0 { main_body: %3 = extractelement <4 x float> %0, i32 0 %4 = extractelement <4 x float> %0, i32 1 %5 = call <2 x float> @llvm.R600.interp.xy(i32 0, float %3, float %4) %6 = call <2 x float> @llvm.R600.interp.zw(i32 0, float %3, float %4) %7 = shufflevector <2 x float> %5, <2 x float> %6, <4 x i32> %8 = extractelement <4 x float> %7, i32 0 %9 = extractelement <4 x float> %7, i32 1 %10 = extractelement <4 x float> %7, i32 2 %11 = extractelement <4 x float> %7, i32 3 %12 = extractelement <4 x float> %0, i32 0 %13 = extractelement <4 x float> %0, i32 1 %14 = call <2 x float> @llvm.R600.interp.xy(i32 1, float %12, float %13) %15 = call <2 x float> @llvm.R600.interp.zw(i32 1, float %12, float %13) %16 = shufflevector <2 x float> %14, <2 x float> %15, <4 x i32> %17 = extractelement <4 x float> %16, i32 0 %18 = extractelement <4 x float> %16, i32 1 %19 = extractelement <4 x float> %16, i32 3 %20 = fdiv float %17, %19 %21 = fdiv float %18, %19 %22 = fdiv float 0.000000e+00, %19 %23 = insertelement <4 x float> undef, float %20, i32 0 %24 = insertelement <4 x float> %23, float %21, i32 1 %25 = insertelement <4 x float> %24, float %22, i32 2 %26 = insertelement <4 x float> %25, float 1.000000e+00, i32 3 %27 = extractelement <4 x float> %26, i32 0 %28 = extractelement <4 x float> %26, i32 1 %29 = insertelement <4 x float> undef, float %27, i32 0 %30 = insertelement <4 x float> %29, float %28, i32 1 %31 = insertelement <4 x float> %30, float undef, i32 2 %32 = insertelement <4 x float> %31, float undef, i32 3 %33 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %32, i32 16, i32 0, i32 2) %34 = extractelement <4 x float> %33, i32 0 %35 = extractelement <4 x float> %33, i32 1 %36 = extractelement <4 x float> %33, i32 2 %37 = extractelement <4 x float> %33, i32 3 %38 = fmul float %34, %8 %39 = fmul float %35, %9 %40 = fmul float %36, %10 %41 = fmul float %37, %11 %42 = insertelement <4 x float> undef, float %38, i32 0 %43 = insertelement <4 x float> %42, float %39, i32 1 %44 = insertelement <4 x float> %43, float %40, i32 2 %45 = insertelement <4 x float> %44, float %41, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %45, i32 0, i32 0) ret void } ; Function Attrs: readnone declare <2 x float> @llvm.R600.interp.xy(i32, float, float) #1 ; Function Attrs: readnone declare <2 x float> @llvm.R600.interp.zw(i32, float, float) #1 ; Function Attrs: readnone declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32, i32) #1 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } Shader Disassembly: ALU 21, @8, KC0[], KC1[] ; 00000008 A0540000 TEX 0 @6 ; 00000006 80400000 ALU 3, @30, KC0[], KC1[] ; 0000001E A00C0000 EXPORT T2.XYZW ; C0010000 95200688 CF_END ; 00000000 88000000 PAD ; 00000000 00000000 Fetch clause starting at 6: ; TEX_SAMPLE T0.XYZW, T3.XY__ RID:16 SID:0 CT:NNNN ; 00031010 F00D1000 FC800000 00000000 ALU clause starting at 8: ; INTERP_XY T1.X, T0.Y, ARRAY_BASE, ; 00380400 00346B10 INTERP_XY T1.Y, T0.X, ARRAY_BASE, ; 00380000 20346B10 INTERP_XY T0.Z (MASKED), T0.Y, ARRAY_BASE, ; 00380400 40146B00 INTERP_XY * T0.W (MASKED), T0.X, ARRAY_BASE, ; 80380000 60146B00 INTERP_ZW T0.X (MASKED), T0.Y, ARRAY_BASE, ; 00380400 00146B80 INTERP_ZW T0.Y (MASKED), T0.X, ARRAY_BASE, ; 00380000 20146B80 INTERP_ZW T1.Z, T0.Y, ARRAY_BASE, ; 00380400 40346B90 INTERP_ZW * T1.W, T0.X, ARRAY_BASE, ; 80380000 60346B90 INTERP_XY T2.X, T0.Y, ARRAY_BASE, ; 00382400 00546B10 INTERP_XY T2.Y, T0.X, ARRAY_BASE, ; 00382000 20546B10 INTERP_XY T0.Z (MASKED), T0.Y, ARRAY_BASE, ; 00382400 40146B00 INTERP_XY * T0.W (MASKED), T0.X, ARRAY_BASE, ; 80382000 60146B00 INTERP_ZW T0.X (MASKED), T0.Y, ARRAY_BASE, ; 00382400 00146B80 INTERP_ZW T0.Y (MASKED), T0.X, ARRAY_BASE, ; 00382000 20146B80 INTERP_ZW T0.Z, T0.Y, ARRAY_BASE, ; 00382400 40146B90 INTERP_ZW * T0.W, T0.X, ARRAY_BASE, ; 80382000 60146B90 RECIP_IEEE T0.X, T0.W, ; 00000C00 00004310 RECIP_IEEE T0.Y (MASKED), T0.W, ; 00000C00 20004300 RECIP_IEEE T0.Z (MASKED), T0.W, ; 00000C00 40004300 RECIP_IEEE * T0.W (MASKED), T0.W, ; 80000C00 60004300 MUL_IEEE T3.X, T2.X, PV.X, ; 001FC002 00600110 MUL_IEEE * T3.Y, T2.Y, PV.X, ; 801FC402 20600110 ALU clause starting at 30: ; MUL_IEEE T2.X, T0.X, T1.X, ; 00002000 00400110 MUL_IEEE T2.Y, T0.Y, T1.Y, ; 00802400 20400110 MUL_IEEE T2.Z, T0.Z, T1.Z, ; 01002800 40400110 MUL_IEEE * T2.W, T0.W, T1.W, ; 81802C00 60400110 ===== SHADER #67 ======================================== PS/CAYMAN/CAYMAN ===== ===== 68 dw ===== 4 gprs ===== 1 stack ========================================= 0000 00000008 a0540000 ALU 22 @16 0016 00380400 00346b10 1 x: INTERP_XY R1.x, R0.y, Param0.x VEC_210 0018 00380000 20346b10 y: INTERP_XY R1.y, R0.x, Param0.x VEC_210 0020 00380400 40146b00 z: INTERP_XY __.z, R0.y, Param0.x VEC_210 0022 80380000 60146b00 w: INTERP_XY __.w, R0.x, Param0.x VEC_210 0024 00380400 00146b80 2 x: INTERP_ZW __.x, R0.y, Param0.x VEC_210 0026 00380000 20146b80 y: INTERP_ZW __.y, R0.x, Param0.x VEC_210 0028 00380400 40346b90 z: INTERP_ZW R1.z, R0.y, Param0.x VEC_210 0030 80380000 60346b90 w: INTERP_ZW R1.w, R0.x, Param0.x VEC_210 0032 00382400 00546b10 3 x: INTERP_XY R2.x, R0.y, Param1.x VEC_210 0034 00382000 20546b10 y: INTERP_XY R2.y, R0.x, Param1.x VEC_210 0036 00382400 40146b00 z: INTERP_XY __.z, R0.y, Param1.x VEC_210 0038 80382000 60146b00 w: INTERP_XY __.w, R0.x, Param1.x VEC_210 0040 00382400 00146b80 4 x: INTERP_ZW __.x, R0.y, Param1.x VEC_210 0042 00382000 20146b80 y: INTERP_ZW __.y, R0.x, Param1.x VEC_210 0044 00382400 40146b90 z: INTERP_ZW R0.z, R0.y, Param1.x VEC_210 0046 80382000 60146b90 w: INTERP_ZW R0.w, R0.x, Param1.x VEC_210 0048 00000c00 00004310 5 x: RECIP_IEEE R0.x, R0.w 0050 00000c00 20004300 y: RECIP_IEEE __.y, R0.w 0052 00000c00 40004300 z: RECIP_IEEE __.z, R0.w 0054 80000c00 60004300 w: RECIP_IEEE __.w, R0.w 0056 001fc002 00600110 6 x: MUL_IEEE R3.x, R2.x, PV.x 0058 801fc402 20600110 y: MUL_IEEE R3.y, R2.y, PV.x 0002 00000006 80400000 TEX 1 @12 0012 00031010 f00d1000 fc800000 SAMPLE R0.xyzw, R3.xy__, RID:16, SID:0 CT:NNNN 0004 0000001e a00c0000 ALU 4 @60 0060 00002000 00400110 7 x: MUL_IEEE R2.x, R0.x, R1.x 0062 00802400 20400110 y: MUL_IEEE R2.y, R0.y, R1.y 0064 01002800 40400110 z: MUL_IEEE R2.z, R0.z, R1.z 0066 81802c00 60400110 w: MUL_IEEE R2.w, R0.w, R1.w 0006 c0010000 95200688 EXPORT_DONE PIXEL 0 R2.xyzw 0008 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #67 OPT ==================================== PS/CAYMAN/CAYMAN ===== ===== 68 dw ===== 2 gprs ===== 0 stack ========================================= 0000 00000005 a0340000 ALU 14 @10 0010 00382400 00146b80 1 x: INTERP_ZW __.x, R0.y, Param1.x VEC_210 0012 00b82000 20146b80 y: INTERP_ZW __.y, R0.x, Param1.y VEC_210 0014 01382400 40146b80 z: INTERP_ZW __.z, R0.y, Param1.z VEC_210 0016 81b82000 6f946b90 w: INTERP_ZW T0.w, R0.x, Param1.w VEC_210 0018 00000c7c 00004300 2 x: RECIP_IEEE __.x, T0.w 0020 00000c7c 20004300 y: RECIP_IEEE __.y, T0.w 0022 00000c7c 4f804310 z: RECIP_IEEE T0.z, T0.w 0024 80000c7c 60004300 w: RECIP_IEEE __.w, T0.w 0026 00382400 0f946b10 3 x: INTERP_XY T0.x, R0.y, Param1.x VEC_210 0028 00b82000 2f946b10 y: INTERP_XY T0.y, R0.x, Param1.y VEC_210 0030 01382400 40146b00 z: INTERP_XY __.z, R0.y, Param1.z VEC_210 0032 81b82000 60146b00 w: INTERP_XY __.w, R0.x, Param1.w VEC_210 0034 010f807c 40000110 4 z: MUL_IEEE R0.z, T0.x, T0.z 0036 810f847c 60000110 w: MUL_IEEE R0.w, T0.y, T0.z 0002 00000014 80400000 TEX 1 @40 0040 00001010 f00d1001 fda00000 SAMPLE R1.xyzw, R0.zw__, RID:16, SID:0 CT:NNNN 0004 00000016 a02c0000 ALU 12 @44 0044 00380400 00146b80 5 x: INTERP_ZW __.x, R0.y, Param0.x VEC_210 0046 00b80000 20146b80 y: INTERP_ZW __.y, R0.x, Param0.y VEC_210 0048 01380400 4f946b90 z: INTERP_ZW T0.z, R0.y, Param0.z VEC_210 0050 81b80000 6f946b90 w: INTERP_ZW T0.w, R0.x, Param0.w VEC_210 0052 00380400 0f946b10 6 x: INTERP_XY T0.x, R0.y, Param0.x VEC_210 0054 00b80000 2f946b10 y: INTERP_XY T0.y, R0.x, Param0.y VEC_210 0056 01380400 40146b00 z: INTERP_XY __.z, R0.y, Param0.z VEC_210 0058 81b80000 60146b00 w: INTERP_XY __.w, R0.x, Param0.w VEC_210 0060 000f8001 00000110 7 x: MUL_IEEE R0.x, R1.x, T0.x 0062 008f8401 20000110 y: MUL_IEEE R0.y, R1.y, T0.y 0064 010f8801 40000110 z: MUL_IEEE R0.z, R1.z, T0.z 0066 818f8c01 60000110 w: MUL_IEEE R0.w, R1.w, T0.w 0006 c0000000 95000688 EXPORT_DONE PIXEL 0 R0.xyzw 0008 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- VERT DCL IN[0] DCL IN[1] DCL IN[2] DCL OUT[0], POSITION DCL OUT[1], COLOR DCL OUT[2], GENERIC[0] DCL CONST[0..3] DCL TEMP[0] 0: MUL TEMP[0], IN[0].xxxx, CONST[0] 1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0] 2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0] 3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0] 4: MOV_SAT OUT[1], IN[1] 5: MOV OUT[2], IN[2] 6: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg, <4 x float> inreg, <4 x float> inreg) #0 { main_body: %4 = extractelement <4 x float> %1, i32 0 %5 = extractelement <4 x float> %1, i32 1 %6 = extractelement <4 x float> %1, i32 2 %7 = extractelement <4 x float> %1, i32 3 %8 = extractelement <4 x float> %2, i32 0 %9 = extractelement <4 x float> %2, i32 1 %10 = extractelement <4 x float> %2, i32 2 %11 = extractelement <4 x float> %2, i32 3 %12 = extractelement <4 x float> %3, i32 0 %13 = extractelement <4 x float> %3, i32 1 %14 = extractelement <4 x float> %3, i32 2 %15 = extractelement <4 x float> %3, i32 3 %16 = load <4 x float> addrspace(8)* null %17 = extractelement <4 x float> %16, i32 0 %18 = fmul float %4, %17 %19 = load <4 x float> addrspace(8)* null %20 = extractelement <4 x float> %19, i32 1 %21 = fmul float %4, %20 %22 = load <4 x float> addrspace(8)* null %23 = extractelement <4 x float> %22, i32 2 %24 = fmul float %4, %23 %25 = load <4 x float> addrspace(8)* null %26 = extractelement <4 x float> %25, i32 3 %27 = fmul float %4, %26 %28 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %29 = extractelement <4 x float> %28, i32 0 %30 = fmul float %5, %29 %31 = fadd float %30, %18 %32 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %33 = extractelement <4 x float> %32, i32 1 %34 = fmul float %5, %33 %35 = fadd float %34, %21 %36 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %37 = extractelement <4 x float> %36, i32 2 %38 = fmul float %5, %37 %39 = fadd float %38, %24 %40 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %41 = extractelement <4 x float> %40, i32 3 %42 = fmul float %5, %41 %43 = fadd float %42, %27 %44 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %45 = extractelement <4 x float> %44, i32 0 %46 = fmul float %6, %45 %47 = fadd float %46, %31 %48 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %49 = extractelement <4 x float> %48, i32 1 %50 = fmul float %6, %49 %51 = fadd float %50, %35 %52 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %53 = extractelement <4 x float> %52, i32 2 %54 = fmul float %6, %53 %55 = fadd float %54, %39 %56 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %57 = extractelement <4 x float> %56, i32 3 %58 = fmul float %6, %57 %59 = fadd float %58, %43 %60 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %61 = extractelement <4 x float> %60, i32 0 %62 = fmul float %7, %61 %63 = fadd float %62, %47 %64 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %65 = extractelement <4 x float> %64, i32 1 %66 = fmul float %7, %65 %67 = fadd float %66, %51 %68 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %69 = extractelement <4 x float> %68, i32 2 %70 = fmul float %7, %69 %71 = fadd float %70, %55 %72 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) %73 = extractelement <4 x float> %72, i32 3 %74 = fmul float %7, %73 %75 = fadd float %74, %59 %76 = call float @llvm.AMDIL.clamp.(float %8, float 0.000000e+00, float 1.000000e+00) %77 = call float @llvm.AMDIL.clamp.(float %9, float 0.000000e+00, float 1.000000e+00) %78 = call float @llvm.AMDIL.clamp.(float %10, float 0.000000e+00, float 1.000000e+00) %79 = call float @llvm.AMDIL.clamp.(float %11, float 0.000000e+00, float 1.000000e+00) %80 = insertelement <4 x float> undef, float %63, i32 0 %81 = insertelement <4 x float> %80, float %67, i32 1 %82 = insertelement <4 x float> %81, float %71, i32 2 %83 = insertelement <4 x float> %82, float %75, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %83, i32 60, i32 1) %84 = insertelement <4 x float> undef, float %76, i32 0 %85 = insertelement <4 x float> %84, float %77, i32 1 %86 = insertelement <4 x float> %85, float %78, i32 2 %87 = insertelement <4 x float> %86, float %79, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %87, i32 0, i32 2) %88 = insertelement <4 x float> undef, float %12, i32 0 %89 = insertelement <4 x float> %88, float %13, i32 1 %90 = insertelement <4 x float> %89, float %14, i32 2 %91 = insertelement <4 x float> %90, float %15, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %91, i32 1, i32 2) ret void } ; Function Attrs: readnone declare float @llvm.AMDIL.clamp.(float, float, float) #1 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="1" } attributes #1 = { readnone } Shader Disassembly: CALL_FS ; 00000000 84C00000 ALU 19, @6, KC0[CB0:0-32], KC1[] ; 80000006 A04C0000 EXPORT T0.XYZW ; C000203C 95000688 EXPORT T5.XYZW ; C002C000 94C00688 EXPORT T3.XYZW ; C001C001 95200688 CF_END ; 00000000 88000000 ALU clause starting at 6: ; MUL_IEEE * T0.W, T1.X, KC0[0].X, ; 80100001 60000110 MULADD_IEEE * T0.W, T1.Y, KC0[1].X, PV.W, ; 80102401 60030CFE MULADD_IEEE * T0.W, T1.Z, KC0[2].X, PV.W, ; 80104801 60030CFE MULADD_IEEE T0.X, T1.W, KC0[3].X, PV.W, ; 00106C01 00030CFE MUL_IEEE * T4.W, T1.X, KC0[0].Z, ; 81100001 60800110 MUL_IEEE T4.Z, T1.X, KC0[0].Y, ; 00900001 40800110 MULADD_IEEE * T4.W, T1.Y, KC0[1].Z, PV.W, ; 81102401 60830CFE MOV_SAT T5.X, T2.X, ; 00000002 80A00C90 MULADD_IEEE T6.Z, T1.Z, KC0[2].Z, PV.W, ; 01104801 40C30CFE MULADD_IEEE * T4.W, T1.Y, KC0[1].Y, PV.Z, ; 80902401 608308FE MOV_SAT T5.Y, T2.Y, ; 00000402 A0A00C90 MUL_IEEE T4.Z, T1.X, KC0[0].W, ; 01900001 40800110 MULADD_IEEE * T4.W, T1.Z, KC0[2].Y, PV.W, ; 80904801 60830CFE MULADD_IEEE T0.Y, T1.W, KC0[3].Y, PV.W, ; 00906C01 20030CFE MOV_SAT T5.Z, T2.Z, ; 00000802 C0A00C90 MULADD_IEEE * T4.W, T1.Y, KC0[1].W, PV.Z, ; 81902401 608308FE MULADD_IEEE T4.Y, T1.Z, KC0[2].W, PV.W, ; 01904801 20830CFE MULADD_IEEE T0.Z, T1.W, KC0[3].Z, T6.Z, ; 01106C01 40030806 MOV_SAT * T5.W, T2.W, BS:VEC_120/SCL_212 ; 80000C02 E0A80C90 MULADD_IEEE * T0.W, T1.W, KC0[3].W, PV.Y, ; 81906C01 600304FE ===== SHADER #68 ======================================== VS/CAYMAN/CAYMAN ===== ===== 52 dw ===== 7 gprs ===== 1 stack ========================================= 0000 00000000 84c00000 CALL_FS @0 0002 80000006 a04c0000 ALU 20 @12 KC0[CB0:0-31] 0012 80100001 60000110 1 w: MUL_IEEE R0.w, R1.x, KC0[0].x 0014 80102401 60030cfe 2 w: MULADD_IEEE R0.w, R1.y, KC0[1].x, PV.w 0016 80104801 60030cfe 3 w: MULADD_IEEE R0.w, R1.z, KC0[2].x, PV.w 0018 00106c01 00030cfe 4 x: MULADD_IEEE R0.x, R1.w, KC0[3].x, PV.w 0020 81100001 60800110 w: MUL_IEEE R4.w, R1.x, KC0[0].z 0022 00900001 40800110 5 z: MUL_IEEE R4.z, R1.x, KC0[0].y 0024 81102401 60830cfe w: MULADD_IEEE R4.w, R1.y, KC0[1].z, PV.w 0026 00000002 80a00c90 6 x: MOV_sat R5.x, R2.x 0028 01104801 40c30cfe z: MULADD_IEEE R6.z, R1.z, KC0[2].z, PV.w 0030 80902401 608308fe w: MULADD_IEEE R4.w, R1.y, KC0[1].y, PV.z 0032 00000402 a0a00c90 7 y: MOV_sat R5.y, R2.y 0034 01900001 40800110 z: MUL_IEEE R4.z, R1.x, KC0[0].w 0036 80904801 60830cfe w: MULADD_IEEE R4.w, R1.z, KC0[2].y, PV.w 0038 00906c01 20030cfe 8 y: MULADD_IEEE R0.y, R1.w, KC0[3].y, PV.w 0040 00000802 c0a00c90 z: MOV_sat R5.z, R2.z 0042 81902401 608308fe w: MULADD_IEEE R4.w, R1.y, KC0[1].w, PV.z 0044 01904801 20830cfe 9 y: MULADD_IEEE R4.y, R1.z, KC0[2].w, PV.w 0046 01106c01 40030806 z: MULADD_IEEE R0.z, R1.w, KC0[3].z, R6.z 0048 80000c02 e0a80c90 w: MOV_sat R5.w, R2.w VEC_120 0050 81906c01 600304fe 10 w: MULADD_IEEE R0.w, R1.w, KC0[3].w, PV.y 0004 c000203c 95000688 EXPORT_DONE POS 60 R0.xyzw 0006 c002c000 94c00688 EXPORT PARAM 0 R5.xyzw 0008 c001c001 95200688 EXPORT_DONE PARAM 1 R3.xyzw 0010 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #68 OPT ==================================== VS/CAYMAN/CAYMAN ===== ===== 54 dw ===== 4 gprs ===== 1 stack ========================================= 0000 00000000 84c00000 CALL_FS @0 0002 40000006 a0500000 ALU 21 @12 KC0[CB0:0-15] 0012 00900001 4f800110 1 z: MUL_IEEE T0.z, R1.x, KC0[0].y 0014 80100001 6f800110 w: MUL_IEEE T0.w, R1.x, KC0[0].x 0016 01900001 0f800110 2 x: MUL_IEEE T0.x, R1.x, KC0[0].w 0018 01100001 2f800110 y: MUL_IEEE T0.y, R1.x, KC0[0].z 0020 80102401 6f830c7c w: MULADD_IEEE T0.w, R1.y, KC0[1].x, T0.w 0022 01902401 0f83007c 3 x: MULADD_IEEE T0.x, R1.y, KC0[1].w, T0.x 0024 01102401 2f83047c y: MULADD_IEEE T0.y, R1.y, KC0[1].z, T0.y 0026 00902401 4f83087c z: MULADD_IEEE T0.z, R1.y, KC0[1].y, T0.z 0028 80000c01 6fa00c90 w: MOV T1.w, R1.w 0030 01904801 0f83007c 4 x: MULADD_IEEE T0.x, R1.z, KC0[2].w, T0.x 0032 01104801 2f83047c y: MULADD_IEEE T0.y, R1.z, KC0[2].z, T0.y 0034 00904801 4f83087c z: MULADD_IEEE T0.z, R1.z, KC0[2].y, T0.z 0036 80104801 6f830c7c w: MULADD_IEEE T0.w, R1.z, KC0[2].x, T0.w 0038 00000002 80000c90 5 x: MOV_sat R0.x, R2.x 0040 00000402 a0000c90 y: MOV_sat R0.y, R2.y 0042 00000802 c0000c90 z: MOV_sat R0.z, R2.z 0044 80000c02 e0000c90 w: MOV_sat R0.w, R2.w 0046 00106c7d 00230c7c 6 x: MULADD_IEEE R1.x, T1.w, KC0[3].x, T0.w 0048 00906c7d 2023087c y: MULADD_IEEE R1.y, T1.w, KC0[3].y, T0.z 0050 01106c7d 4023047c z: MULADD_IEEE R1.z, T1.w, KC0[3].z, T0.y 0052 81906c7d 6023007c w: MULADD_IEEE R1.w, T1.w, KC0[3].w, T0.x 0004 c000a03c 95000688 EXPORT_DONE POS 60 R1.xyzw 0006 c0004000 94c00688 EXPORT PARAM 0 R0.xyzw 0008 c001c001 95000688 EXPORT_DONE PARAM 1 R3.xyzw 0010 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== Generating new string page texture 3: 256x256, total string texture memory is 311.30 KB Installing breakpad exception handler for appid(steam)/version(1390852599_client) Installing breakpad exception handler for appid(steam)/version(1390852599_client) Focused window is now 1, 0 Adding license for package 0 Adding license for package 216 Adding license for package 470 Adding license for package 2481 Adding license for package 7359 Adding license for package 11072 Adding license for package 11857 Adding license for package 12328 Adding license for package 12985 Adding license for package 14335 Adding license for package 16167 Adding license for package 16531 Adding license for package 16536 Adding license for package 17250 Adding license for package 17355 Adding license for package 17366 Adding license for package 17641 Adding license for package 18485 Adding license for package 19099 Adding license for package 26585 Adding license for package 27035 Adding license for package 32889 roaming config store loaded successfully - 2578 bytes. migrating temporary roaming config store Installing breakpad exception handler for appid(steam)/version(1390852599_client) -------------------------------------------------------------- FRAG 0: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg) #0 { main_body: call void @llvm.R600.store.dummy(i32 0) ret void } declare void @llvm.R600.store.dummy(i32) attributes #0 = { "ShaderType"="0" } Shader Disassembly: EXPORT T0.____ ; C0000000 95200FFF CF_END ; 00000000 88000000 ===== SHADER #75 ======================================== PS/CAYMAN/CAYMAN ===== ===== 4 dw ===== 1 gprs ===== 1 stack ========================================== 0000 c0000000 95200fff EXPORT_DONE PIXEL 0 R0.____ 0002 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #75 OPT ==================================== PS/CAYMAN/CAYMAN ===== ===== 4 dw ===== 0 gprs ===== 0 stack ========================================== 0000 c0000000 95000fff EXPORT_DONE PIXEL 0 R0.____ 0002 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- FRAG DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg) #0 { main_body: %2 = call <4 x float> @llvm.R600.interp.const(i32 0) %3 = extractelement <4 x float> %2, i32 0 %4 = extractelement <4 x float> %2, i32 1 %5 = extractelement <4 x float> %2, i32 2 %6 = extractelement <4 x float> %2, i32 3 %7 = insertelement <4 x float> undef, float %3, i32 0 %8 = insertelement <4 x float> %7, float %4, i32 1 %9 = insertelement <4 x float> %8, float %5, i32 2 %10 = insertelement <4 x float> %9, float %6, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %10, i32 0, i32 0) ret void } ; Function Attrs: readnone declare <4 x float> @llvm.R600.interp.const(i32) #1 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } Shader Disassembly: ALU 3, @4, KC0[], KC1[] ; 00000004 A00C0000 EXPORT T0.XYZW ; C0000000 95200688 CF_END ; 00000000 88000000 PAD ; 00000000 00000000 ALU clause starting at 4: ; INTERP_LOAD_P0 T0.X, ARRAY_BASE, ; 000001C0 00007010 INTERP_LOAD_P0 T0.Y, ARRAY_BASE, ; 000001C0 20007010 INTERP_LOAD_P0 T0.Z, ARRAY_BASE, ; 000001C0 40007010 INTERP_LOAD_P0 * T0.W, ARRAY_BASE, ; 800001C0 60007010 ===== SHADER #76 ======================================== PS/CAYMAN/CAYMAN ===== ===== 16 dw ===== 1 gprs ===== 1 stack ========================================= 0000 00000004 a00c0000 ALU 4 @8 0008 000001c0 00007010 1 x: INTERP_LOAD_P0 R0.x, Param0.x 0010 000001c0 20007010 y: INTERP_LOAD_P0 R0.y, Param0.x 0012 000001c0 40007010 z: INTERP_LOAD_P0 R0.z, Param0.x 0014 800001c0 60007010 w: INTERP_LOAD_P0 R0.w, Param0.x 0002 c0000000 95200688 EXPORT_DONE PIXEL 0 R0.xyzw 0004 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #76 OPT ==================================== PS/CAYMAN/CAYMAN ===== ===== 14 dw ===== 1 gprs ===== 0 stack ========================================= 0000 00000003 a00c0000 ALU 4 @6 0006 000001c0 00007010 1 x: INTERP_LOAD_P0 R0.x, Param0.x 0008 000005c0 20007010 y: INTERP_LOAD_P0 R0.y, Param0.y 0010 000009c0 40007010 z: INTERP_LOAD_P0 R0.z, Param0.z 0012 80000dc0 60007010 w: INTERP_LOAD_P0 R0.w, Param0.w 0002 c0000000 95000688 EXPORT_DONE PIXEL 0 R0.xyzw 0004 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg) #0 { main_body: %2 = call <4 x float> @llvm.R600.interp.const(i32 0) %3 = extractelement <4 x float> %2, i32 0 %4 = extractelement <4 x float> %2, i32 1 %5 = extractelement <4 x float> %2, i32 2 %6 = extractelement <4 x float> %2, i32 3 %7 = insertelement <4 x float> undef, float %3, i32 0 %8 = insertelement <4 x float> %7, float %4, i32 1 %9 = insertelement <4 x float> %8, float %5, i32 2 %10 = insertelement <4 x float> %9, float %6, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %10, i32 0, i32 0) ret void } ; Function Attrs: readnone declare <4 x float> @llvm.R600.interp.const(i32) #1 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } Shader Disassembly: ALU 3, @4, KC0[], KC1[] ; 00000004 A00C0000 EXPORT T0.XYZW ; C0000000 95200688 CF_END ; 00000000 88000000 PAD ; 00000000 00000000 ALU clause starting at 4: ; INTERP_LOAD_P0 T0.X, ARRAY_BASE, ; 000001C0 00007010 INTERP_LOAD_P0 T0.Y, ARRAY_BASE, ; 000001C0 20007010 INTERP_LOAD_P0 T0.Z, ARRAY_BASE, ; 000001C0 40007010 INTERP_LOAD_P0 * T0.W, ARRAY_BASE, ; 800001C0 60007010 ===== SHADER #77 ======================================== PS/CAYMAN/CAYMAN ===== ===== 16 dw ===== 1 gprs ===== 1 stack ========================================= 0000 00000004 a00c0000 ALU 4 @8 0008 000001c0 00007010 1 x: INTERP_LOAD_P0 R0.x, Param0.x 0010 000001c0 20007010 y: INTERP_LOAD_P0 R0.y, Param0.x 0012 000001c0 40007010 z: INTERP_LOAD_P0 R0.z, Param0.x 0014 800001c0 60007010 w: INTERP_LOAD_P0 R0.w, Param0.x 0002 c0000000 95200688 EXPORT_DONE PIXEL 0 R0.xyzw 0004 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #77 OPT ==================================== PS/CAYMAN/CAYMAN ===== ===== 14 dw ===== 1 gprs ===== 0 stack ========================================= 0000 00000003 a00c0000 ALU 4 @6 0006 000001c0 00007010 1 x: INTERP_LOAD_P0 R0.x, Param0.x 0008 000005c0 20007010 y: INTERP_LOAD_P0 R0.y, Param0.y 0010 000009c0 40007010 z: INTERP_LOAD_P0 R0.z, Param0.z 0012 80000dc0 60007010 w: INTERP_LOAD_P0 R0.w, Param0.w 0002 c0000000 95000688 EXPORT_DONE PIXEL 0 R0.xyzw 0004 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] 0: MOV OUT[0], IN[0] 1: MOV OUT[1], IN[1] 2: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg, <4 x float> inreg) #0 { main_body: %3 = extractelement <4 x float> %1, i32 0 %4 = extractelement <4 x float> %1, i32 1 %5 = extractelement <4 x float> %1, i32 2 %6 = extractelement <4 x float> %1, i32 3 %7 = extractelement <4 x float> %2, i32 0 %8 = extractelement <4 x float> %2, i32 1 %9 = extractelement <4 x float> %2, i32 2 %10 = extractelement <4 x float> %2, i32 3 %11 = insertelement <4 x float> undef, float %3, i32 0 %12 = insertelement <4 x float> %11, float %4, i32 1 %13 = insertelement <4 x float> %12, float %5, i32 2 %14 = insertelement <4 x float> %13, float %6, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %14, i32 60, i32 1) %15 = insertelement <4 x float> undef, float %7, i32 0 %16 = insertelement <4 x float> %15, float %8, i32 1 %17 = insertelement <4 x float> %16, float %9, i32 2 %18 = insertelement <4 x float> %17, float %10, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %18, i32 0, i32 2) ret void } declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="1" } Shader Disassembly: CALL_FS ; 00000000 84C00000 EXPORT T1.XYZW ; C000A03C 95000688 EXPORT T2.XYZW ; C0014000 95200688 CF_END ; 00000000 88000000 ===== SHADER #78 ======================================== VS/CAYMAN/CAYMAN ===== ===== 8 dw ===== 3 gprs ===== 1 stack ========================================== 0000 00000000 84c00000 CALL_FS @0 0002 c000a03c 95000688 EXPORT_DONE POS 60 R1.xyzw 0004 c0014000 95200688 EXPORT_DONE PARAM 0 R2.xyzw 0006 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #78 OPT ==================================== VS/CAYMAN/CAYMAN ===== ===== 8 dw ===== 3 gprs ===== 1 stack ========================================== 0000 00000000 84c00000 CALL_FS @0 0002 c0014000 95000688 EXPORT_DONE PARAM 0 R2.xyzw 0004 c000a03c 95000688 EXPORT_DONE POS 60 R1.xyzw 0006 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- VERT DCL IN[0] DCL OUT[0], POSITION 0: MOV OUT[0], IN[0] 1: END STREAMOUT 0: MEM_STREAM0_BUF0[0..0] <- OUT[0].x ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg) #0 { main_body: %2 = extractelement <4 x float> %1, i32 0 %3 = extractelement <4 x float> %1, i32 1 %4 = extractelement <4 x float> %1, i32 2 %5 = extractelement <4 x float> %1, i32 3 %6 = insertelement <4 x float> undef, float %2, i32 0 %7 = insertelement <4 x float> %6, float %3, i32 1 %8 = insertelement <4 x float> %7, float %4, i32 2 %9 = insertelement <4 x float> %8, float %5, i32 3 call void @llvm.R600.store.stream.output(<4 x float> %9, i32 0, i32 0, i32 1) %10 = insertelement <4 x float> undef, float %2, i32 0 %11 = insertelement <4 x float> %10, float %3, i32 1 %12 = insertelement <4 x float> %11, float %4, i32 2 %13 = insertelement <4 x float> %12, float %5, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %13, i32 60, i32 1) call void @llvm.R600.store.dummy(i32 2) ret void } declare void @llvm.R600.store.stream.output(<4 x float>, i32, i32, i32) declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) declare void @llvm.R600.store.dummy(i32) attributes #0 = { "ShaderType"="1" } Shader Disassembly: CALL_FS ; 00000000 84C00000 EXPORT T1 ; 00008000 90001FFF EXPORT T1.XYZW ; C000A03C 95000688 EXPORT T0.____ ; C0004000 95200FFF CF_END ; 00000000 88000000 PAD ; 00000000 00000000 ===== SHADER #79 ======================================== VS/CAYMAN/CAYMAN ===== ===== 12 dw ===== 2 gprs ===== 1 stack ========================================= 0000 00000000 84c00000 CALL_FS @0 0002 00008000 90001fff MEM_STREAM0_BUF0 WRITE 0 R1.x___ ES:0 0004 c000a03c 95000688 EXPORT_DONE POS 60 R1.xyzw 0006 c0004000 95200fff EXPORT_DONE PARAM 0 R0.____ 0008 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #79 OPT ==================================== VS/CAYMAN/CAYMAN ===== ===== 10 dw ===== 2 gprs ===== 1 stack ========================================= 0000 00000000 84c00000 CALL_FS @0 0002 c000a03c 95000688 EXPORT_DONE POS 60 R1.xyzw 0004 00008000 90001fff MEM_STREAM0_BUF0 WRITE 0 R1.x___ ES:0 0006 c0004000 95000fff EXPORT_DONE PARAM 0 R0.____ 0008 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- FRAG DCL IN[0], GENERIC[0], CONSTANT 0: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg) #0 { main_body: %2 = call <4 x float> @llvm.R600.interp.const(i32 0) call void @llvm.R600.store.dummy(i32 0) ret void } ; Function Attrs: readnone declare <4 x float> @llvm.R600.interp.const(i32) #1 declare void @llvm.R600.store.dummy(i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } Shader Disassembly: EXPORT T0.____ ; C0000000 95200FFF CF_END ; 00000000 88000000 ===== SHADER #80 ======================================== PS/CAYMAN/CAYMAN ===== ===== 4 dw ===== 1 gprs ===== 1 stack ========================================== 0000 c0000000 95200fff EXPORT_DONE PIXEL 0 R0.____ 0002 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #80 OPT ==================================== PS/CAYMAN/CAYMAN ===== ===== 4 dw ===== 0 gprs ===== 0 stack ========================================== 0000 c0000000 95000fff EXPORT_DONE PIXEL 0 R0.____ 0002 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] 0: MOV OUT[0], IN[0] 1: MOV OUT[1], IN[1] 2: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg, <4 x float> inreg) #0 { main_body: %3 = extractelement <4 x float> %1, i32 0 %4 = extractelement <4 x float> %1, i32 1 %5 = extractelement <4 x float> %1, i32 2 %6 = extractelement <4 x float> %1, i32 3 %7 = extractelement <4 x float> %2, i32 0 %8 = extractelement <4 x float> %2, i32 1 %9 = extractelement <4 x float> %2, i32 2 %10 = extractelement <4 x float> %2, i32 3 %11 = insertelement <4 x float> undef, float %3, i32 0 %12 = insertelement <4 x float> %11, float %4, i32 1 %13 = insertelement <4 x float> %12, float %5, i32 2 %14 = insertelement <4 x float> %13, float %6, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %14, i32 60, i32 1) %15 = insertelement <4 x float> undef, float %7, i32 0 %16 = insertelement <4 x float> %15, float %8, i32 1 %17 = insertelement <4 x float> %16, float %9, i32 2 %18 = insertelement <4 x float> %17, float %10, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %18, i32 0, i32 2) ret void } declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="1" } Shader Disassembly: CALL_FS ; 00000000 84C00000 EXPORT T1.XYZW ; C000A03C 95000688 EXPORT T2.XYZW ; C0014000 95200688 CF_END ; 00000000 88000000 ===== SHADER #81 ======================================== VS/CAYMAN/CAYMAN ===== ===== 8 dw ===== 3 gprs ===== 1 stack ========================================== 0000 00000000 84c00000 CALL_FS @0 0002 c000a03c 95000688 EXPORT_DONE POS 60 R1.xyzw 0004 c0014000 95200688 EXPORT_DONE PARAM 0 R2.xyzw 0006 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #81 OPT ==================================== VS/CAYMAN/CAYMAN ===== ===== 8 dw ===== 3 gprs ===== 1 stack ========================================== 0000 00000000 84c00000 CALL_FS @0 0002 c0014000 95000688 EXPORT_DONE PARAM 0 R2.xyzw 0004 c000a03c 95000688 EXPORT_DONE POS 60 R1.xyzw 0006 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] DCL OUT[2], GENERIC[10] DCL OUT[3], GENERIC[11] DCL CONST[0] IMM[0] FLT32 { 1.0000, 0.0000, -1.0000, 0.0000} 0: MOV OUT[0], IN[0] 1: MOV OUT[1], IN[1] 2: MAD OUT[2], CONST[0].xyxy, IMM[0].zyyz, IN[1].xyxy 3: MAD OUT[3], CONST[0].xyxy, IMM[0].xyyx, IN[1].xyxy 4: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg, <4 x float> inreg) #0 { main_body: %3 = extractelement <4 x float> %1, i32 0 %4 = extractelement <4 x float> %1, i32 1 %5 = extractelement <4 x float> %1, i32 2 %6 = extractelement <4 x float> %1, i32 3 %7 = extractelement <4 x float> %2, i32 0 %8 = extractelement <4 x float> %2, i32 1 %9 = extractelement <4 x float> %2, i32 2 %10 = extractelement <4 x float> %2, i32 3 %11 = load <4 x float> addrspace(8)* null %12 = extractelement <4 x float> %11, i32 0 %13 = fmul float %12, -1.000000e+00 %14 = fadd float %13, %7 %15 = load <4 x float> addrspace(8)* null %16 = extractelement <4 x float> %15, i32 1 %17 = fmul float %16, 0.000000e+00 %18 = fadd float %17, %8 %19 = load <4 x float> addrspace(8)* null %20 = extractelement <4 x float> %19, i32 0 %21 = fmul float %20, 0.000000e+00 %22 = fadd float %21, %7 %23 = load <4 x float> addrspace(8)* null %24 = extractelement <4 x float> %23, i32 1 %25 = fmul float %24, -1.000000e+00 %26 = fadd float %25, %8 %27 = load <4 x float> addrspace(8)* null %28 = extractelement <4 x float> %27, i32 0 %29 = fmul float %28, 1.000000e+00 %30 = fadd float %29, %7 %31 = load <4 x float> addrspace(8)* null %32 = extractelement <4 x float> %31, i32 1 %33 = fmul float %32, 0.000000e+00 %34 = fadd float %33, %8 %35 = load <4 x float> addrspace(8)* null %36 = extractelement <4 x float> %35, i32 0 %37 = fmul float %36, 0.000000e+00 %38 = fadd float %37, %7 %39 = load <4 x float> addrspace(8)* null %40 = extractelement <4 x float> %39, i32 1 %41 = fmul float %40, 1.000000e+00 %42 = fadd float %41, %8 %43 = insertelement <4 x float> undef, float %3, i32 0 %44 = insertelement <4 x float> %43, float %4, i32 1 %45 = insertelement <4 x float> %44, float %5, i32 2 %46 = insertelement <4 x float> %45, float %6, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %46, i32 60, i32 1) %47 = insertelement <4 x float> undef, float %7, i32 0 %48 = insertelement <4 x float> %47, float %8, i32 1 %49 = insertelement <4 x float> %48, float %9, i32 2 %50 = insertelement <4 x float> %49, float %10, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %50, i32 0, i32 2) %51 = insertelement <4 x float> undef, float %14, i32 0 %52 = insertelement <4 x float> %51, float %18, i32 1 %53 = insertelement <4 x float> %52, float %22, i32 2 %54 = insertelement <4 x float> %53, float %26, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %54, i32 1, i32 2) %55 = insertelement <4 x float> undef, float %30, i32 0 %56 = insertelement <4 x float> %55, float %34, i32 1 %57 = insertelement <4 x float> %56, float %38, i32 2 %58 = insertelement <4 x float> %57, float %42, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %58, i32 2, i32 2) ret void } declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="1" } Shader Disassembly: CALL_FS ; 00000000 84C00000 ALU 7, @8, KC0[CB0:0-32], KC1[] ; 80000008 A01C0000 EXPORT T1.XYZW ; C000A03C 95000688 EXPORT T2.XYZW ; C0014000 94C00688 EXPORT T0.XYZW ; C0004001 94C00688 EXPORT T3.XYZW ; C001C002 95200688 CF_END ; 00000000 88000000 PAD ; 00000000 00000000 ALU clause starting at 8: ; ADD T0.X, T2.X, -KC0[0].X, ; 02100002 00000010 MULADD_IEEE T0.Y, KC0[0].Y, 0.0, T2.Y, ; 001F0480 20030402 MULADD_IEEE * T0.Z, KC0[0].X, 0.0, T2.X, ; 801F0080 40030002 ADD T3.X, KC0[0].X, T2.X, ; 00004080 00600010 ADD * T0.W, T2.Y, -KC0[0].Y, ; 82900402 60000010 ADD * T3.W, KC0[0].Y, T2.Y, ; 80804480 60600010 MOV T3.Y, T0.Y, ; 00000400 20600C90 MOV * T3.Z, T0.Z, ; 80000800 40600C90 ===== SHADER #82 ======================================== VS/CAYMAN/CAYMAN ===== ===== 32 dw ===== 4 gprs ===== 1 stack ========================================= 0000 00000000 84c00000 CALL_FS @0 0002 80000008 a01c0000 ALU 8 @16 KC0[CB0:0-31] 0016 02100002 00000010 1 x: ADD R0.x, R2.x, -KC0[0].x 0018 001f0480 20030402 y: MULADD_IEEE R0.y, KC0[0].y, 0, R2.y 0020 801f0080 40030002 z: MULADD_IEEE R0.z, KC0[0].x, 0, R2.x 0022 00004080 00600010 2 x: ADD R3.x, KC0[0].x, R2.x 0024 82900402 60000010 w: ADD R0.w, R2.y, -KC0[0].y 0026 80804480 60600010 3 w: ADD R3.w, KC0[0].y, R2.y 0028 00000400 20600c90 4 y: MOV R3.y, R0.y 0030 80000800 40600c90 z: MOV R3.z, R0.z 0004 c000a03c 95000688 EXPORT_DONE POS 60 R1.xyzw 0006 c0014000 94c00688 EXPORT PARAM 0 R2.xyzw 0008 c0004001 94c00688 EXPORT PARAM 1 R0.xyzw 0010 c001c002 95200688 EXPORT_DONE PARAM 2 R3.xyzw 0012 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #82 OPT ==================================== VS/CAYMAN/CAYMAN ===== ===== 30 dw ===== 4 gprs ===== 1 stack ========================================= 0000 00000000 84c00000 CALL_FS @0 0002 40000007 a01c0000 ALU 8 @14 KC0[CB0:0-15] 0014 00004080 00000010 1 x: ADD R0.x, KC0[0].x, R2.x 0016 001f0480 20030402 y: MULADD_IEEE R0.y, KC0[0].y, 0, R2.y 0018 001f0080 40030002 z: MULADD_IEEE R0.z, KC0[0].x, 0, R2.x 0020 80804480 60000010 w: ADD R0.w, KC0[0].y, R2.y 0022 02100002 00600010 2 x: ADD R3.x, R2.x, -KC0[0].x 0024 00000400 20600c90 y: MOV R3.y, R0.y 0026 00000800 40600c90 z: MOV R3.z, R0.z 0028 82900402 60680010 w: ADD R3.w, R2.y, -KC0[0].y VEC_120 0004 c001c001 94c00688 EXPORT PARAM 1 R3.xyzw 0006 c0004002 94c00688 EXPORT PARAM 2 R0.xyzw 0008 c0014000 95000688 EXPORT_DONE PARAM 0 R2.xyzw 0010 c000a03c 95000688 EXPORT_DONE POS 60 R1.xyzw 0012 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], PERSPECTIVE DCL IN[1], GENERIC[10], PERSPECTIVE DCL IN[2], GENERIC[11], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL TEMP[0..2] IMM[0] FLT32 { 0.0030, 0.0000, 1.0000, 0.0000} 0: TEX TEMP[0].x, IN[1].xyyy, SAMP[0], 2D 1: MOV TEMP[1].x, TEMP[0].xxxx 2: TEX TEMP[0].x, IN[1].zwww, SAMP[0], 2D 3: MOV TEMP[1].y, TEMP[0].xxxx 4: TEX TEMP[0].x, IN[2].xyyy, SAMP[0], 2D 5: MOV TEMP[1].z, TEMP[0].xxxx 6: TEX TEMP[0].x, IN[2].zwww, SAMP[0], 2D 7: MOV TEMP[1].w, TEMP[0].xxxx 8: TEX TEMP[0].x, IN[0].xyyy, SAMP[0], 2D 9: ADD TEMP[2], TEMP[0].xxxx, -TEMP[1] 10: ABS TEMP[0], TEMP[2] 11: SGE TEMP[2], TEMP[0], IMM[0].xxxx 12: DP4 TEMP[0].x, TEMP[2], IMM[0].zzzz 13: SEQ TEMP[1].x, TEMP[0].xxxx, IMM[0].yyyy 14: IF TEMP[1].xxxx :16 15: KILL 16: ENDIF 17: MOV OUT[0], TEMP[2] 18: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg, <4 x float> inreg, <4 x float> inreg) #0 { main_body: %4 = extractelement <4 x float> %0, i32 0 %5 = extractelement <4 x float> %0, i32 1 %6 = call <2 x float> @llvm.R600.interp.xy(i32 0, float %4, float %5) %7 = call <2 x float> @llvm.R600.interp.zw(i32 0, float %4, float %5) %8 = shufflevector <2 x float> %6, <2 x float> %7, <4 x i32> %9 = extractelement <4 x float> %8, i32 0 %10 = extractelement <4 x float> %8, i32 1 %11 = extractelement <4 x float> %0, i32 0 %12 = extractelement <4 x float> %0, i32 1 %13 = call <2 x float> @llvm.R600.interp.xy(i32 1, float %11, float %12) %14 = call <2 x float> @llvm.R600.interp.zw(i32 1, float %11, float %12) %15 = shufflevector <2 x float> %13, <2 x float> %14, <4 x i32> %16 = extractelement <4 x float> %15, i32 0 %17 = extractelement <4 x float> %15, i32 1 %18 = extractelement <4 x float> %15, i32 2 %19 = extractelement <4 x float> %15, i32 3 %20 = extractelement <4 x float> %0, i32 0 %21 = extractelement <4 x float> %0, i32 1 %22 = call <2 x float> @llvm.R600.interp.xy(i32 2, float %20, float %21) %23 = call <2 x float> @llvm.R600.interp.zw(i32 2, float %20, float %21) %24 = shufflevector <2 x float> %22, <2 x float> %23, <4 x i32> %25 = extractelement <4 x float> %24, i32 0 %26 = extractelement <4 x float> %24, i32 1 %27 = extractelement <4 x float> %24, i32 2 %28 = extractelement <4 x float> %24, i32 3 %29 = insertelement <4 x float> undef, float %16, i32 0 %30 = insertelement <4 x float> %29, float %17, i32 1 %31 = insertelement <4 x float> %30, float %17, i32 2 %32 = insertelement <4 x float> %31, float %17, i32 3 %33 = extractelement <4 x float> %32, i32 0 %34 = extractelement <4 x float> %32, i32 1 %35 = insertelement <4 x float> undef, float %33, i32 0 %36 = insertelement <4 x float> %35, float %34, i32 1 %37 = insertelement <4 x float> %36, float undef, i32 2 %38 = insertelement <4 x float> %37, float undef, i32 3 %39 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %38, i32 16, i32 0, i32 2) %40 = extractelement <4 x float> %39, i32 0 %41 = insertelement <4 x float> undef, float %18, i32 0 %42 = insertelement <4 x float> %41, float %19, i32 1 %43 = insertelement <4 x float> %42, float %19, i32 2 %44 = insertelement <4 x float> %43, float %19, i32 3 %45 = extractelement <4 x float> %44, i32 0 %46 = extractelement <4 x float> %44, i32 1 %47 = insertelement <4 x float> undef, float %45, i32 0 %48 = insertelement <4 x float> %47, float %46, i32 1 %49 = insertelement <4 x float> %48, float undef, i32 2 %50 = insertelement <4 x float> %49, float undef, i32 3 %51 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %50, i32 16, i32 0, i32 2) %52 = extractelement <4 x float> %51, i32 0 %53 = insertelement <4 x float> undef, float %25, i32 0 %54 = insertelement <4 x float> %53, float %26, i32 1 %55 = insertelement <4 x float> %54, float %26, i32 2 %56 = insertelement <4 x float> %55, float %26, i32 3 %57 = extractelement <4 x float> %56, i32 0 %58 = extractelement <4 x float> %56, i32 1 %59 = insertelement <4 x float> undef, float %57, i32 0 %60 = insertelement <4 x float> %59, float %58, i32 1 %61 = insertelement <4 x float> %60, float undef, i32 2 %62 = insertelement <4 x float> %61, float undef, i32 3 %63 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %62, i32 16, i32 0, i32 2) %64 = extractelement <4 x float> %63, i32 0 %65 = insertelement <4 x float> undef, float %27, i32 0 %66 = insertelement <4 x float> %65, float %28, i32 1 %67 = insertelement <4 x float> %66, float %28, i32 2 %68 = insertelement <4 x float> %67, float %28, i32 3 %69 = extractelement <4 x float> %68, i32 0 %70 = extractelement <4 x float> %68, i32 1 %71 = insertelement <4 x float> undef, float %69, i32 0 %72 = insertelement <4 x float> %71, float %70, i32 1 %73 = insertelement <4 x float> %72, float undef, i32 2 %74 = insertelement <4 x float> %73, float undef, i32 3 %75 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %74, i32 16, i32 0, i32 2) %76 = extractelement <4 x float> %75, i32 0 %77 = insertelement <4 x float> undef, float %9, i32 0 %78 = insertelement <4 x float> %77, float %10, i32 1 %79 = insertelement <4 x float> %78, float %10, i32 2 %80 = insertelement <4 x float> %79, float %10, i32 3 %81 = extractelement <4 x float> %80, i32 0 %82 = extractelement <4 x float> %80, i32 1 %83 = insertelement <4 x float> undef, float %81, i32 0 %84 = insertelement <4 x float> %83, float %82, i32 1 %85 = insertelement <4 x float> %84, float undef, i32 2 %86 = insertelement <4 x float> %85, float undef, i32 3 %87 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %86, i32 16, i32 0, i32 2) %88 = extractelement <4 x float> %87, i32 0 %89 = fsub float -0.000000e+00, %40 %90 = fadd float %88, %89 %91 = fsub float -0.000000e+00, %52 %92 = fadd float %88, %91 %93 = fsub float -0.000000e+00, %64 %94 = fadd float %88, %93 %95 = fsub float -0.000000e+00, %76 %96 = fadd float %88, %95 %97 = call float @fabs(float %90) %98 = call float @fabs(float %92) %99 = call float @fabs(float %94) %100 = call float @fabs(float %96) %101 = fcmp oge float %97, 0x3F689374C0000000 %102 = select i1 %101, float 1.000000e+00, float 0.000000e+00 %103 = fcmp oge float %98, 0x3F689374C0000000 %104 = select i1 %103, float 1.000000e+00, float 0.000000e+00 %105 = fcmp oge float %99, 0x3F689374C0000000 %106 = select i1 %105, float 1.000000e+00, float 0.000000e+00 %107 = fcmp oge float %100, 0x3F689374C0000000 %108 = select i1 %107, float 1.000000e+00, float 0.000000e+00 %109 = insertelement <4 x float> undef, float %102, i32 0 %110 = insertelement <4 x float> %109, float %104, i32 1 %111 = insertelement <4 x float> %110, float %106, i32 2 %112 = insertelement <4 x float> %111, float %108, i32 3 %113 = call float @llvm.AMDGPU.dp4(<4 x float> %112, <4 x float> ) %114 = fcmp oeq float %113, 0.000000e+00 %115 = select i1 %114, float 1.000000e+00, float 0.000000e+00 %116 = fcmp une float %115, 0.000000e+00 br i1 %116, label %IF, label %ENDIF IF: ; preds = %main_body call void @llvm.AMDGPU.kilp() br label %ENDIF ENDIF: ; preds = %main_body, %IF %117 = insertelement <4 x float> undef, float %102, i32 0 %118 = insertelement <4 x float> %117, float %104, i32 1 %119 = insertelement <4 x float> %118, float %106, i32 2 %120 = insertelement <4 x float> %119, float %108, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %120, i32 0, i32 0) ret void } ; Function Attrs: readnone declare <2 x float> @llvm.R600.interp.xy(i32, float, float) #1 ; Function Attrs: readnone declare <2 x float> @llvm.R600.interp.zw(i32, float, float) #1 ; Function Attrs: readnone declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32, i32) #1 ; Function Attrs: readonly declare float @fabs(float) #2 ; Function Attrs: readnone declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1 declare void @llvm.AMDGPU.kilp() declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } attributes #2 = { readonly } Shader Disassembly: ALU 23, @18, KC0[], KC1[] ; 00000012 A05C0000 TEX 4 @8 ; 00000008 80401000 ALU_PUSH_BEFORE 18, @42, KC0[], KC1[] ; 0000002A A4480000 JUMP @5 POP:1 ; 00000005 82800001 ALU_POP_AFTER 0, @61, KC0[], KC1[] ; 0000003D A8000000 EXPORT T0.XYZW ; C0000000 95200688 CF_END ; 00000000 88000000 PAD ; 00000000 00000000 Fetch clause starting at 8: ; TEX_SAMPLE T3.XYZW, T6.XY__ RID:16 SID:0 CT:NNNN ; 00061010 F00D1003 FC800000 00000000 TEX_SAMPLE T5.XYZW, T5.XY__ RID:16 SID:0 CT:NNNN ; 00051010 F00D1005 FC800000 00000000 TEX_SAMPLE T4.XYZW, T4.XY__ RID:16 SID:0 CT:NNNN ; 00041010 F00D1004 FC800000 00000000 TEX_SAMPLE T1.XYZW, T1.XY__ RID:16 SID:0 CT:NNNN ; 00011010 F00D1001 FC800000 00000000 TEX_SAMPLE T0.XYZW, T2.XY__ RID:16 SID:0 CT:NNNN ; 00021010 F00D1000 FC800000 00000000 ALU clause starting at 18: ; INTERP_XY T1.X, T0.Y, ARRAY_BASE, ; 00380400 00346B10 INTERP_XY T1.Y, T0.X, ARRAY_BASE, ; 00380000 20346B10 INTERP_XY T0.Z (MASKED), T0.Y, ARRAY_BASE, ; 00380400 40146B00 INTERP_XY * T0.W (MASKED), T0.X, ARRAY_BASE, ; 80380000 60146B00 INTERP_XY T2.X, T0.Y, ARRAY_BASE, ; 00382400 00546B10 INTERP_XY T2.Y, T0.X, ARRAY_BASE, ; 00382000 20546B10 INTERP_XY T0.Z (MASKED), T0.Y, ARRAY_BASE, ; 00382400 40146B00 INTERP_XY * T0.W (MASKED), T0.X, ARRAY_BASE, ; 80382000 60146B00 INTERP_ZW T0.X (MASKED), T0.Y, ARRAY_BASE, ; 00382400 00146B80 INTERP_ZW T0.Y (MASKED), T0.X, ARRAY_BASE, ; 00382000 20146B80 INTERP_ZW T3.Z, T0.Y, ARRAY_BASE, ; 00382400 40746B90 INTERP_ZW * T3.W, T0.X, ARRAY_BASE, ; 80382000 60746B90 MOV * T4.X, PV.Z, ; 800008FE 00800C90 INTERP_XY T5.X, T0.Y, ARRAY_BASE, ; 00384400 00B46B10 INTERP_XY T5.Y, T0.X, ARRAY_BASE, ; 00384000 20B46B10 INTERP_XY T0.Z (MASKED), T0.Y, ARRAY_BASE, ; 00384400 40146B00 INTERP_XY * T0.W (MASKED), T0.X, ARRAY_BASE, ; 80384000 60146B00 INTERP_ZW T0.X (MASKED), T0.Y, ARRAY_BASE, ; 00384400 00146B80 INTERP_ZW T0.Y (MASKED), T0.X, ARRAY_BASE, ; 00384000 20146B80 INTERP_ZW T0.Z, T0.Y, ARRAY_BASE, ; 00384400 40146B90 INTERP_ZW * T0.W, T0.X, ARRAY_BASE, ; 80384000 60146B90 MOV T6.X, PV.Z, ; 000008FE 00C00C90 MOV * T4.Y, T3.W, ; 80000C03 20800C90 MOV * T6.Y, T0.W, ; 80000C00 20C00C90 ALU clause starting at 42: ; ADD * T0.W, T1.X, -T0.X, ; 82000001 60000010 SETGE T0.X, |PV.W|, literal.x, ; 001FACFE 00000511 ADD * T2.W, T1.X, -T4.X, ; 82008001 60400010 994352038(3.000000e-03), 0(0.000000e+00) ; 3B449BA6 00000000 SETGE T0.Y, |PV.W|, literal.x, ; 001FACFE 20000511 ADD * T2.W, T1.X, -T5.X, ; 8200A001 60400010 994352038(3.000000e-03), 0(0.000000e+00) ; 3B449BA6 00000000 SETGE T0.Z, |PV.W|, literal.x, ; 001FACFE 40000511 ADD * T1.W, T1.X, -T3.X, ; 82006001 60200010 994352038(3.000000e-03), 0(0.000000e+00) ; 3B449BA6 00000000 SETGE * T0.W, |PV.W|, literal.x, ; 801FACFE 60000511 994352038(3.000000e-03), 0(0.000000e+00) ; 3B449BA6 00000000 DOT4 T1.X, T0.X, 1.0, ; 001F2000 00205F10 DOT4 T1.Y (MASKED), T0.Y, 1.0, ; 001F2400 20205F00 DOT4 T1.Z (MASKED), T0.Z, 1.0, ; 001F2800 40205F00 DOT4 * T1.W (MASKED), T0.W, 1.0, ; 801F2C00 60205F00 SETE * T1.W, PV.X, 0.0, ; 801F00FE 60200410 SETE_DX10 * T1.W, PV.W, 0.0, ; 801F0CFE 60200610 PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002104 ALU clause starting at 61: ; KILLGT * T1.X (MASKED), 1.0, 0.0, ; 801F00F9 00201680 ===== SHADER #83 ======================================== PS/CAYMAN/CAYMAN ===== ===== 124 dw ===== 7 gprs ===== 1 stack ======================================== 0000 00000012 a05c0000 ALU 24 @36 0036 00380400 00346b10 1 x: INTERP_XY R1.x, R0.y, Param0.x VEC_210 0038 00380000 20346b10 y: INTERP_XY R1.y, R0.x, Param0.x VEC_210 0040 00380400 40146b00 z: INTERP_XY __.z, R0.y, Param0.x VEC_210 0042 80380000 60146b00 w: INTERP_XY __.w, R0.x, Param0.x VEC_210 0044 00382400 00546b10 2 x: INTERP_XY R2.x, R0.y, Param1.x VEC_210 0046 00382000 20546b10 y: INTERP_XY R2.y, R0.x, Param1.x VEC_210 0048 00382400 40146b00 z: INTERP_XY __.z, R0.y, Param1.x VEC_210 0050 80382000 60146b00 w: INTERP_XY __.w, R0.x, Param1.x VEC_210 0052 00382400 00146b80 3 x: INTERP_ZW __.x, R0.y, Param1.x VEC_210 0054 00382000 20146b80 y: INTERP_ZW __.y, R0.x, Param1.x VEC_210 0056 00382400 40746b90 z: INTERP_ZW R3.z, R0.y, Param1.x VEC_210 0058 80382000 60746b90 w: INTERP_ZW R3.w, R0.x, Param1.x VEC_210 0060 800008fe 00800c90 4 x: MOV R4.x, PV.z 0062 00384400 00b46b10 5 x: INTERP_XY R5.x, R0.y, Param2.x VEC_210 0064 00384000 20b46b10 y: INTERP_XY R5.y, R0.x, Param2.x VEC_210 0066 00384400 40146b00 z: INTERP_XY __.z, R0.y, Param2.x VEC_210 0068 80384000 60146b00 w: INTERP_XY __.w, R0.x, Param2.x VEC_210 0070 00384400 00146b80 6 x: INTERP_ZW __.x, R0.y, Param2.x VEC_210 0072 00384000 20146b80 y: INTERP_ZW __.y, R0.x, Param2.x VEC_210 0074 00384400 40146b90 z: INTERP_ZW R0.z, R0.y, Param2.x VEC_210 0076 80384000 60146b90 w: INTERP_ZW R0.w, R0.x, Param2.x VEC_210 0078 000008fe 00c00c90 7 x: MOV R6.x, PV.z 0080 80000c03 20800c90 y: MOV R4.y, R3.w 0082 80000c00 20c00c90 8 y: MOV R6.y, R0.w 0002 00000008 80401000 TEX 5 @16 0016 00061010 f00d1003 fc800000 SAMPLE R3.xyzw, R6.xy__, RID:16, SID:0 CT:NNNN 0020 00051010 f00d1005 fc800000 SAMPLE R5.xyzw, R5.xy__, RID:16, SID:0 CT:NNNN 0024 00041010 f00d1004 fc800000 SAMPLE R4.xyzw, R4.xy__, RID:16, SID:0 CT:NNNN 0028 00011010 f00d1001 fc800000 SAMPLE R1.xyzw, R1.xy__, RID:16, SID:0 CT:NNNN 0032 00021010 f00d1000 fc800000 SAMPLE R0.xyzw, R2.xy__, RID:16, SID:0 CT:NNNN 0004 0000002a a4480000 ALU_PUSH_BEFORE 19 @84 0084 82000001 60000010 9 w: ADD R0.w, R1.x, -R0.x 0086 001facfe 00000511 10 x: SETGE R0.x, |PV.w|, [0x3b449ba6 0.003].x 0088 82008001 60400010 w: ADD R2.w, R1.x, -R4.x 0090 3b449ba6 0092 001facfe 20000511 11 y: SETGE R0.y, |PV.w|, [0x3b449ba6 0.003].x 0094 8200a001 60400010 w: ADD R2.w, R1.x, -R5.x 0096 3b449ba6 0098 001facfe 40000511 12 z: SETGE R0.z, |PV.w|, [0x3b449ba6 0.003].x 0100 82006001 60200010 w: ADD R1.w, R1.x, -R3.x 0102 3b449ba6 0104 801facfe 60000511 13 w: SETGE R0.w, |PV.w|, [0x3b449ba6 0.003].x 0106 3b449ba6 0108 001f2000 00205f10 14 x: DOT4 R1.x, R0.x, 1.0 0110 001f2400 20205f00 y: DOT4 __.y, R0.y, 1.0 0112 001f2800 40205f00 z: DOT4 __.z, R0.z, 1.0 0114 801f2c00 60205f00 w: DOT4 __.w, R0.w, 1.0 0116 801f00fe 60200410 15 w: SETE R1.w, PV.x, 0 0118 801f0cfe 60200610 16 w: SETE_DX10 R1.w, PV.w, 0 0120 801f0cfe 00002104 17 M x: PRED_SETE_INT __.x, PV.w, 0 0006 00000005 82800001 JUMP @10 POP:1 0008 0000003d a8000000 ALU_POP_AFTER 1 @122 0122 801f00f9 00201680 18 x: KILLGT __.x, 1.0, 0 0010 c0000000 95200688 EXPORT_DONE PIXEL 0 R0.xyzw 0012 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #83 OPT ==================================== PS/CAYMAN/CAYMAN ===== ===== 100 dw ===== 4 gprs ===== 0 stack ======================================== 0000 00000005 a04c0000 ALU 20 @10 0010 00382400 00346b10 1 x: INTERP_XY R1.x, R0.y, Param1.x VEC_210 0012 00b82000 20346b10 y: INTERP_XY R1.y, R0.x, Param1.y VEC_210 0014 01382400 40146b00 z: INTERP_XY __.z, R0.y, Param1.z VEC_210 0016 81b82000 60146b00 w: INTERP_XY __.w, R0.x, Param1.w VEC_210 0018 00382400 00146b80 2 x: INTERP_ZW __.x, R0.y, Param1.x VEC_210 0020 00b82000 20146b80 y: INTERP_ZW __.y, R0.x, Param1.y VEC_210 0022 01382400 40146b90 z: INTERP_ZW R0.z, R0.y, Param1.z VEC_210 0024 81b82000 60146b90 w: INTERP_ZW R0.w, R0.x, Param1.w VEC_210 0026 00384400 00746b10 3 x: INTERP_XY R3.x, R0.y, Param2.x VEC_210 0028 00b84000 20746b10 y: INTERP_XY R3.y, R0.x, Param2.y VEC_210 0030 01384400 40146b00 z: INTERP_XY __.z, R0.y, Param2.z VEC_210 0032 81b84000 60146b00 w: INTERP_XY __.w, R0.x, Param2.w VEC_210 0034 00380400 00546b10 4 x: INTERP_XY R2.x, R0.y, Param0.x VEC_210 0036 00b80000 20546b10 y: INTERP_XY R2.y, R0.x, Param0.y VEC_210 0038 01380400 40146b00 z: INTERP_XY __.z, R0.y, Param0.z VEC_210 0040 81b80000 60146b00 w: INTERP_XY __.w, R0.x, Param0.w VEC_210 0042 00384400 00146b80 5 x: INTERP_ZW __.x, R0.y, Param2.x VEC_210 0044 00b84000 20146b80 y: INTERP_ZW __.y, R0.x, Param2.y VEC_210 0046 01384400 40346b90 z: INTERP_ZW R1.z, R0.y, Param2.z VEC_210 0048 81b84000 60346b90 w: INTERP_ZW R1.w, R0.x, Param2.w VEC_210 0002 0000001a 80401000 TEX 5 @52 0052 00011010 f003fe01 fda00000 SAMPLE R1.___x, R1.zw__, RID:16, SID:0 CT:NNNN 0056 00021010 f01f8e00 fc800000 SAMPLE R0._x__, R2.xy__, RID:16, SID:0 CT:NNNN 0060 00031010 f01c7e01 fc800000 SAMPLE R1.__x_, R3.xy__, RID:16, SID:0 CT:NNNN 0064 00001010 f01c7e00 fda00000 SAMPLE R0.__x_, R0.zw__, RID:16, SID:0 CT:NNNN 0068 00011010 f01ff000 fc800000 SAMPLE R0.x___, R1.xy__, RID:16, SID:0 CT:NNNN 0004 00000024 a0340000 ALU 14 @72 0072 03002400 0f840010 6 x: ADD T0.x, R0.y, -R1.z VEC_021 0074 03000400 2f800010 y: ADD T0.y, R0.y, -R0.z 0076 02000400 4f800010 z: ADD T0.z, R0.y, -R0.x 0078 83802400 6f800010 w: ADD T0.w, R0.y, -R1.w 0080 001fa87c 00000511 7 x: SETGE R0.x, |T0.z|, [0x3b449ba6 0.003].x 0082 001fa47c 20000511 y: SETGE R0.y, |T0.y|, [0x3b449ba6 0.003].x 0084 001fa07c 40000511 z: SETGE R0.z, |T0.x|, [0x3b449ba6 0.003].x 0086 801fac7c 60000511 w: SETGE R0.w, |T0.w|, [0x3b449ba6 0.003].x 0088 3b449ba6 0090 001f2000 00005f00 8 x: DOT4 __.x, R0.x, 1.0 0092 001f2400 20005f00 y: DOT4 __.y, R0.y, 1.0 0094 001f2800 40005f00 z: DOT4 __.z, R0.z, 1.0 0096 801f2c00 6f805f10 w: DOT4 T0.w, R0.w, 1.0 0098 801f0c7c 00001600 9 x: KILLE __.x, T0.w, 0 0006 c0000000 95000688 EXPORT_DONE PIXEL 0 R0.xyzw 0008 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL SAMP[1] DCL SAMP[2] DCL CONST[0] DCL TEMP[0..6] IMM[0] FLT32 { 0.0000, -0.2500, 0.0061, 0.5000} IMM[1] FLT32 { -1.5000, -2.0000, 0.9000, 1.5000} IMM[2] FLT32 { 2.0000, 1.0000, 4.0000, 33.0000} IMM[3] FLT32 { 8.0000, 0.0000, 0.0000, 0.0000} 0: MOV TEMP[0], IMM[0].xxxx 1: TEX TEMP[1], IN[0].xyyy, SAMP[1], 2D 2: MOV TEMP[2].x, TEMP[1] 3: SNE TEMP[3].x, TEMP[1].yyyy, IMM[0].xxxx 4: IF TEMP[3].xxxx :76 5: MOV TEMP[1].xy, IN[0].xyxx 6: MOV TEMP[4].x, IMM[1].xxxx 7: BGNLOOP :24 8: MUL TEMP[5].x, IMM[1].yyyy, IMM[3].xxxx 9: SLE TEMP[6].x, TEMP[4].xxxx, TEMP[5].xxxx 10: IF TEMP[6].xxxx :12 11: BRK 12: ENDIF 13: MOV TEMP[4].y, IMM[0].xxxx 14: MAD TEMP[3].xyz, CONST[0].xyyy, TEMP[4].xyyy, TEMP[1].xyyy 15: MOV TEMP[3].w, IMM[0].xxxx 16: TXL TEMP[5], TEMP[3], SAMP[2], 2D 17: MOV TEMP[3].x, TEMP[5].yyyy 18: SLT TEMP[6].x, TEMP[5].yyyy, IMM[1].zzzz 19: IF TEMP[6].xxxx :21 20: BRK 21: ENDIF 22: ADD TEMP[6].x, TEMP[4].xxxx, IMM[1].yyyy 23: MOV TEMP[4].x, TEMP[6].xxxx 24: ENDLOOP :7 25: ADD TEMP[1].x, TEMP[4].xxxx, IMM[1].wwww 26: MAD TEMP[6].x, -IMM[2].xxxx, TEMP[3].xxxx, TEMP[1].xxxx 27: MUL TEMP[1].x, IMM[1].yyyy, IMM[3].xxxx 28: MAX TEMP[4].x, TEMP[6].xxxx, TEMP[1].xxxx 29: MOV TEMP[1].x, TEMP[4].xxxx 30: MOV TEMP[3].xy, IN[0].xyxx 31: MOV TEMP[5].x, IMM[1].wwww 32: BGNLOOP :49 33: MUL TEMP[6].x, IMM[2].xxxx, IMM[3].xxxx 34: SGE TEMP[4].x, TEMP[5].xxxx, TEMP[6].xxxx 35: IF TEMP[4].xxxx :37 36: BRK 37: ENDIF 38: MOV TEMP[5].y, IMM[0].xxxx 39: MAD TEMP[4].xyz, CONST[0].xyyy, TEMP[5].xyyy, TEMP[3].xyyy 40: MOV TEMP[4].w, IMM[0].xxxx 41: TXL TEMP[6].xy, TEMP[4], SAMP[2], 2D 42: MOV TEMP[4].x, TEMP[6].yyyy 43: SLT TEMP[0].x, TEMP[6].yyyy, IMM[1].zzzz 44: IF TEMP[0].xxxx :46 45: BRK 46: ENDIF 47: ADD TEMP[6].x, TEMP[5].xxxx, IMM[2].xxxx 48: MOV TEMP[5].x, TEMP[6].xxxx 49: ENDLOOP :32 50: ADD TEMP[3].x, TEMP[5].xxxx, IMM[1].xxxx 51: MAD TEMP[5].x, IMM[2].xxxx, TEMP[4].xxxx, TEMP[3].xxxx 52: MUL TEMP[3].x, IMM[2].xxxx, IMM[3].xxxx 53: MIN TEMP[4].x, TEMP[5].xxxx, TEMP[3].xxxx 54: MOV TEMP[3].x, TEMP[1].xxxx 55: MOV TEMP[3].y, TEMP[4].xxxx 56: MOV TEMP[5].yw, IMM[0].yyyy 57: MOV TEMP[5].x, TEMP[1].xxxx 58: ADD TEMP[1].x, TEMP[4].xxxx, IMM[2].yyyy 59: MOV TEMP[5].z, TEMP[1].xxxx 60: MAD TEMP[1], TEMP[5], CONST[0].xyxy, IN[0].xyxy 61: MOV TEMP[4], TEMP[1].xyyy 62: MOV TEMP[4].w, IMM[0].xxxx 63: TXL TEMP[5].x, TEMP[4], SAMP[2], 2D 64: MOV TEMP[4].x, TEMP[5].xxxx 65: MOV TEMP[5], TEMP[1].zwww 66: MOV TEMP[5].w, IMM[0].xxxx 67: TXL TEMP[1].x, TEMP[5], SAMP[2], 2D 68: MOV TEMP[4].y, TEMP[1].xxxx 69: MUL TEMP[5].xy, IMM[2].zzzz, TEMP[4].xyyy 70: ROUND TEMP[1].xy, TEMP[5].xyyy 71: ABS TEMP[4].xy, TEMP[3].xyyy 72: MAD TEMP[3].xy, IMM[2].wwww, TEMP[1].xyyy, TEMP[4].xyyy 73: MUL TEMP[5].xyz, TEMP[3].xyyy, IMM[0].zzzz 74: MOV TEMP[5].w, IMM[0].xxxx 75: TXL TEMP[0].xy, TEMP[5], SAMP[0], 2D 76: ENDIF 77: SNE TEMP[1].x, TEMP[2].xxxx, IMM[0].xxxx 78: IF TEMP[1].xxxx :151 79: MOV TEMP[1].xy, IN[0].xyxx 80: MOV TEMP[3].x, IMM[1].xxxx 81: BGNLOOP :98 82: MUL TEMP[4].x, IMM[1].yyyy, IMM[3].xxxx 83: SLE TEMP[5].x, TEMP[3].xxxx, TEMP[4].xxxx 84: IF TEMP[5].xxxx :86 85: BRK 86: ENDIF 87: MOV TEMP[3].y, IMM[0].xxxx 88: MAD TEMP[5].xyz, CONST[0].xyyy, TEMP[3].yxxx, TEMP[1].xyyy 89: MOV TEMP[5].w, IMM[0].xxxx 90: TXL TEMP[4], TEMP[5], SAMP[2], 2D 91: MOV TEMP[2].x, TEMP[4].xxxx 92: SLT TEMP[5].x, TEMP[4].xxxx, IMM[1].zzzz 93: IF TEMP[5].xxxx :95 94: BRK 95: ENDIF 96: ADD TEMP[4].x, TEMP[3].xxxx, IMM[1].yyyy 97: MOV TEMP[3].x, TEMP[4].xxxx 98: ENDLOOP :81 99: ADD TEMP[1].x, TEMP[3].xxxx, IMM[1].wwww 100: MAD TEMP[6].x, -IMM[2].xxxx, TEMP[2].xxxx, TEMP[1].xxxx 101: MUL TEMP[1].x, IMM[1].yyyy, IMM[3].xxxx 102: MAX TEMP[3].x, TEMP[6].xxxx, TEMP[1].xxxx 103: MOV TEMP[1].x, TEMP[3].xxxx 104: MOV TEMP[2].xy, IN[0].xyxx 105: MOV TEMP[4].x, IMM[1].wwww 106: BGNLOOP :123 107: MUL TEMP[5].x, IMM[2].xxxx, IMM[3].xxxx 108: SGE TEMP[6].x, TEMP[4].xxxx, TEMP[5].xxxx 109: IF TEMP[6].xxxx :111 110: BRK 111: ENDIF 112: MOV TEMP[4].y, IMM[0].xxxx 113: MAD TEMP[5].xyz, CONST[0].xyyy, TEMP[4].yxxx, TEMP[2].xyyy 114: MOV TEMP[5].w, IMM[0].xxxx 115: TXL TEMP[6], TEMP[5], SAMP[2], 2D 116: MOV TEMP[3].x, TEMP[6].xxxx 117: SLT TEMP[5].x, TEMP[6].xxxx, IMM[1].zzzz 118: IF TEMP[5].xxxx :120 119: BRK 120: ENDIF 121: ADD TEMP[6].x, TEMP[4].xxxx, IMM[2].xxxx 122: MOV TEMP[4].x, TEMP[6].xxxx 123: ENDLOOP :106 124: ADD TEMP[2].x, TEMP[4].xxxx, IMM[1].xxxx 125: MAD TEMP[4].x, IMM[2].xxxx, TEMP[3].xxxx, TEMP[2].xxxx 126: MUL TEMP[2].x, IMM[2].xxxx, IMM[3].xxxx 127: MIN TEMP[3].x, TEMP[4].xxxx, TEMP[2].xxxx 128: MOV TEMP[2].x, TEMP[1].xxxx 129: MOV TEMP[2].y, TEMP[3].xxxx 130: MOV TEMP[4].xz, IMM[0].yyyy 131: MOV TEMP[4].y, TEMP[1].xxxx 132: ADD TEMP[1].x, TEMP[3].xxxx, IMM[2].yyyy 133: MOV TEMP[4].w, TEMP[1].xxxx 134: MAD TEMP[1], TEMP[4], CONST[0].xyxy, IN[0].xyxy 135: MOV TEMP[3], TEMP[1].xyyy 136: MOV TEMP[3].w, IMM[0].xxxx 137: TXL TEMP[4].y, TEMP[3], SAMP[2], 2D 138: MOV TEMP[3].x, TEMP[4].yyyy 139: MOV TEMP[4], TEMP[1].zwww 140: MOV TEMP[4].w, IMM[0].xxxx 141: TXL TEMP[1].y, TEMP[4], SAMP[2], 2D 142: MOV TEMP[3].y, TEMP[1].yyyy 143: MUL TEMP[4].xy, IMM[2].zzzz, TEMP[3].xyyy 144: ROUND TEMP[1].xy, TEMP[4].xyyy 145: ABS TEMP[3].xy, TEMP[2].xyyy 146: MAD TEMP[2].xy, IMM[2].wwww, TEMP[1].xyyy, TEMP[3].xyyy 147: MUL TEMP[3].xyz, TEMP[2].xyyy, IMM[0].zzzz 148: MOV TEMP[3].w, IMM[0].xxxx 149: TXL TEMP[1].xy, TEMP[3], SAMP[0], 2D 150: MOV TEMP[0].zw, TEMP[1].yyxy 151: ENDIF 152: MOV OUT[0], TEMP[0] 153: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg) #0 { main_body: %2 = extractelement <4 x float> %0, i32 0 %3 = extractelement <4 x float> %0, i32 1 %4 = call <2 x float> @llvm.R600.interp.xy(i32 0, float %2, float %3) %5 = call <2 x float> @llvm.R600.interp.zw(i32 0, float %2, float %3) %6 = shufflevector <2 x float> %4, <2 x float> %5, <4 x i32> %7 = extractelement <4 x float> %6, i32 0 %8 = extractelement <4 x float> %6, i32 1 %9 = insertelement <4 x float> undef, float %7, i32 0 %10 = insertelement <4 x float> %9, float %8, i32 1 %11 = insertelement <4 x float> %10, float %8, i32 2 %12 = insertelement <4 x float> %11, float %8, i32 3 %13 = extractelement <4 x float> %12, i32 0 %14 = extractelement <4 x float> %12, i32 1 %15 = insertelement <4 x float> undef, float %13, i32 0 %16 = insertelement <4 x float> %15, float %14, i32 1 %17 = insertelement <4 x float> %16, float undef, i32 2 %18 = insertelement <4 x float> %17, float undef, i32 3 %19 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %18, i32 17, i32 1, i32 2) %20 = extractelement <4 x float> %19, i32 0 %21 = extractelement <4 x float> %19, i32 1 %22 = fcmp une float %21, 0.000000e+00 %23 = select i1 %22, float 1.000000e+00, float 0.000000e+00 %24 = fcmp une float %23, 0.000000e+00 br i1 %24, label %LOOP, label %ENDIF ENDIF: ; preds = %main_body, %ENDLOOP34 %temp.0 = phi float [ %113, %ENDLOOP34 ], [ 0.000000e+00, %main_body ] %temp1.0 = phi float [ %114, %ENDLOOP34 ], [ 0.000000e+00, %main_body ] %25 = fcmp une float %20, 0.000000e+00 %26 = select i1 %25, float 1.000000e+00, float 0.000000e+00 %27 = fcmp une float %26, 0.000000e+00 br i1 %27, label %LOOP46, label %ENDIF42 LOOP: ; preds = %main_body, %ENDIF31 %temp12.0 = phi float [ %53, %ENDIF31 ], [ %23, %main_body ] %temp16.0 = phi float [ %57, %ENDIF31 ], [ -1.500000e+00, %main_body ] %28 = fcmp ole float %temp16.0, -1.600000e+01 %29 = select i1 %28, float 1.000000e+00, float 0.000000e+00 %30 = fcmp une float %29, 0.000000e+00 br i1 %30, label %ENDLOOP, label %ENDIF28 ENDLOOP: ; preds = %ENDIF28, %LOOP %temp12.1 = phi float [ %temp12.0, %LOOP ], [ %53, %ENDIF28 ] %31 = fadd float %temp16.0, 1.500000e+00 %32 = fmul float -2.000000e+00, %temp12.1 %33 = fadd float %32, %31 %34 = fcmp uge float %33, -1.600000e+01 %35 = select i1 %34, float %33, float -1.600000e+01 br label %LOOP35 ENDIF28: ; preds = %LOOP %36 = load <4 x float> addrspace(8)* null %37 = extractelement <4 x float> %36, i32 0 %38 = fmul float %37, %temp16.0 %39 = fadd float %38, %7 %40 = load <4 x float> addrspace(8)* null %41 = extractelement <4 x float> %40, i32 1 %42 = fmul float %41, 0.000000e+00 %43 = fadd float %42, %8 %44 = load <4 x float> addrspace(8)* null %45 = extractelement <4 x float> %44, i32 1 %46 = fmul float %45, 0.000000e+00 %47 = fadd float %46, %8 %48 = insertelement <4 x float> undef, float %39, i32 0 %49 = insertelement <4 x float> %48, float %43, i32 1 %50 = insertelement <4 x float> %49, float %47, i32 2 %51 = insertelement <4 x float> %50, float 0.000000e+00, i32 3 %52 = call <4 x float> @llvm.AMDGPU.txl(<4 x float> %51, i32 18, i32 2, i32 2) %53 = extractelement <4 x float> %52, i32 1 %54 = fcmp olt float %53, 0x3FECCCCCC0000000 %55 = select i1 %54, float 1.000000e+00, float 0.000000e+00 %56 = fcmp une float %55, 0.000000e+00 br i1 %56, label %ENDLOOP, label %ENDIF31 ENDIF31: ; preds = %ENDIF28 %57 = fadd float %temp16.0, -2.000000e+00 br label %LOOP LOOP35: ; preds = %ENDIF39, %ENDLOOP %temp20.0 = phi float [ 1.500000e+00, %ENDLOOP ], [ %136, %ENDIF39 ] %58 = fcmp oge float %temp20.0, 1.600000e+01 %59 = select i1 %58, float 1.000000e+00, float 0.000000e+00 %60 = fcmp une float %59, 0.000000e+00 br i1 %60, label %ENDLOOP34, label %ENDIF36 ENDLOOP34: ; preds = %ENDIF36, %LOOP35 %temp16.1 = phi float [ %59, %LOOP35 ], [ %132, %ENDIF36 ] %61 = fadd float %temp20.0, -1.500000e+00 %62 = fmul float 2.000000e+00, %temp16.1 %63 = fadd float %62, %61 %64 = fcmp uge float %63, 1.600000e+01 %65 = select i1 %64, float 1.600000e+01, float %63 %66 = fadd float %65, 1.000000e+00 %67 = load <4 x float> addrspace(8)* null %68 = extractelement <4 x float> %67, i32 0 %69 = fmul float %35, %68 %70 = fadd float %69, %7 %71 = load <4 x float> addrspace(8)* null %72 = extractelement <4 x float> %71, i32 1 %73 = fmul float -2.500000e-01, %72 %74 = fadd float %73, %8 %75 = load <4 x float> addrspace(8)* null %76 = extractelement <4 x float> %75, i32 0 %77 = fmul float %66, %76 %78 = fadd float %77, %7 %79 = load <4 x float> addrspace(8)* null %80 = extractelement <4 x float> %79, i32 1 %81 = fmul float -2.500000e-01, %80 %82 = fadd float %81, %8 %83 = insertelement <4 x float> undef, float %70, i32 0 %84 = insertelement <4 x float> %83, float %74, i32 1 %85 = insertelement <4 x float> %84, float %74, i32 2 %86 = insertelement <4 x float> %85, float 0.000000e+00, i32 3 %87 = call <4 x float> @llvm.AMDGPU.txl(<4 x float> %86, i32 18, i32 2, i32 2) %88 = extractelement <4 x float> %87, i32 0 %89 = insertelement <4 x float> undef, float %78, i32 0 %90 = insertelement <4 x float> %89, float %82, i32 1 %91 = insertelement <4 x float> %90, float %82, i32 2 %92 = insertelement <4 x float> %91, float 0.000000e+00, i32 3 %93 = call <4 x float> @llvm.AMDGPU.txl(<4 x float> %92, i32 18, i32 2, i32 2) %94 = extractelement <4 x float> %93, i32 0 %95 = fmul float 4.000000e+00, %88 %96 = fmul float 4.000000e+00, %94 %97 = call float @llvm.AMDIL.round.nearest.(float %95) %98 = call float @llvm.AMDIL.round.nearest.(float %96) %99 = call float @fabs(float %35) %100 = call float @fabs(float %65) %101 = fmul float 3.300000e+01, %97 %102 = fadd float %101, %99 %103 = fmul float 3.300000e+01, %98 %104 = fadd float %103, %100 %105 = fmul float %102, 0x3F78F9C140000000 %106 = fmul float %104, 0x3F78F9C140000000 %107 = fmul float %104, 0x3F78F9C140000000 %108 = insertelement <4 x float> undef, float %105, i32 0 %109 = insertelement <4 x float> %108, float %106, i32 1 %110 = insertelement <4 x float> %109, float %107, i32 2 %111 = insertelement <4 x float> %110, float 0.000000e+00, i32 3 %112 = call <4 x float> @llvm.AMDGPU.txl(<4 x float> %111, i32 16, i32 0, i32 2) %113 = extractelement <4 x float> %112, i32 0 %114 = extractelement <4 x float> %112, i32 1 br label %ENDIF ENDIF36: ; preds = %LOOP35 %115 = load <4 x float> addrspace(8)* null %116 = extractelement <4 x float> %115, i32 0 %117 = fmul float %116, %temp20.0 %118 = fadd float %117, %7 %119 = load <4 x float> addrspace(8)* null %120 = extractelement <4 x float> %119, i32 1 %121 = fmul float %120, 0.000000e+00 %122 = fadd float %121, %8 %123 = load <4 x float> addrspace(8)* null %124 = extractelement <4 x float> %123, i32 1 %125 = fmul float %124, 0.000000e+00 %126 = fadd float %125, %8 %127 = insertelement <4 x float> undef, float %118, i32 0 %128 = insertelement <4 x float> %127, float %122, i32 1 %129 = insertelement <4 x float> %128, float %126, i32 2 %130 = insertelement <4 x float> %129, float 0.000000e+00, i32 3 %131 = call <4 x float> @llvm.AMDGPU.txl(<4 x float> %130, i32 18, i32 2, i32 2) %132 = extractelement <4 x float> %131, i32 1 %133 = fcmp olt float %132, 0x3FECCCCCC0000000 %134 = select i1 %133, float 1.000000e+00, float 0.000000e+00 %135 = fcmp une float %134, 0.000000e+00 br i1 %135, label %ENDLOOP34, label %ENDIF39 ENDIF39: ; preds = %ENDIF36 %136 = fadd float %temp20.0, 2.000000e+00 br label %LOOP35 ENDIF42: ; preds = %ENDIF, %ENDLOOP53 %temp2.0 = phi float [ %226, %ENDLOOP53 ], [ 0.000000e+00, %ENDIF ] %temp3.0 = phi float [ %227, %ENDLOOP53 ], [ 0.000000e+00, %ENDIF ] %137 = insertelement <4 x float> undef, float %temp.0, i32 0 %138 = insertelement <4 x float> %137, float %temp1.0, i32 1 %139 = insertelement <4 x float> %138, float %temp2.0, i32 2 %140 = insertelement <4 x float> %139, float %temp3.0, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %140, i32 0, i32 0) ret void LOOP46: ; preds = %ENDIF, %ENDIF50 %temp8.0 = phi float [ %166, %ENDIF50 ], [ %20, %ENDIF ] %temp12.2 = phi float [ %170, %ENDIF50 ], [ -1.500000e+00, %ENDIF ] %141 = fcmp ole float %temp12.2, -1.600000e+01 %142 = select i1 %141, float 1.000000e+00, float 0.000000e+00 %143 = fcmp une float %142, 0.000000e+00 br i1 %143, label %ENDLOOP45, label %ENDIF47 ENDLOOP45: ; preds = %ENDIF47, %LOOP46 %temp8.1 = phi float [ %temp8.0, %LOOP46 ], [ %166, %ENDIF47 ] %144 = fadd float %temp12.2, 1.500000e+00 %145 = fmul float -2.000000e+00, %temp8.1 %146 = fadd float %145, %144 %147 = fcmp uge float %146, -1.600000e+01 %148 = select i1 %147, float %146, float -1.600000e+01 br label %LOOP54 ENDIF47: ; preds = %LOOP46 %149 = load <4 x float> addrspace(8)* null %150 = extractelement <4 x float> %149, i32 0 %151 = fmul float %150, 0.000000e+00 %152 = fadd float %151, %7 %153 = load <4 x float> addrspace(8)* null %154 = extractelement <4 x float> %153, i32 1 %155 = fmul float %154, %temp12.2 %156 = fadd float %155, %8 %157 = load <4 x float> addrspace(8)* null %158 = extractelement <4 x float> %157, i32 1 %159 = fmul float %158, %temp12.2 %160 = fadd float %159, %8 %161 = insertelement <4 x float> undef, float %152, i32 0 %162 = insertelement <4 x float> %161, float %156, i32 1 %163 = insertelement <4 x float> %162, float %160, i32 2 %164 = insertelement <4 x float> %163, float 0.000000e+00, i32 3 %165 = call <4 x float> @llvm.AMDGPU.txl(<4 x float> %164, i32 18, i32 2, i32 2) %166 = extractelement <4 x float> %165, i32 0 %167 = fcmp olt float %166, 0x3FECCCCCC0000000 %168 = select i1 %167, float 1.000000e+00, float 0.000000e+00 %169 = fcmp une float %168, 0.000000e+00 br i1 %169, label %ENDLOOP45, label %ENDIF50 ENDIF50: ; preds = %ENDIF47 %170 = fadd float %temp12.2, -2.000000e+00 br label %LOOP46 LOOP54: ; preds = %ENDIF58, %ENDLOOP45 %temp12.3 = phi float [ %148, %ENDLOOP45 ], [ %245, %ENDIF58 ] %temp16.2 = phi float [ 1.500000e+00, %ENDLOOP45 ], [ %249, %ENDIF58 ] %171 = fcmp oge float %temp16.2, 1.600000e+01 %172 = select i1 %171, float 1.000000e+00, float 0.000000e+00 %173 = fcmp une float %172, 0.000000e+00 br i1 %173, label %ENDLOOP53, label %ENDIF55 ENDLOOP53: ; preds = %ENDIF55, %LOOP54 %temp12.4 = phi float [ %temp12.3, %LOOP54 ], [ %245, %ENDIF55 ] %174 = fadd float %temp16.2, -1.500000e+00 %175 = fmul float 2.000000e+00, %temp12.4 %176 = fadd float %175, %174 %177 = fcmp uge float %176, 1.600000e+01 %178 = select i1 %177, float 1.600000e+01, float %176 %179 = fadd float %178, 1.000000e+00 %180 = load <4 x float> addrspace(8)* null %181 = extractelement <4 x float> %180, i32 0 %182 = fmul float -2.500000e-01, %181 %183 = fadd float %182, %7 %184 = load <4 x float> addrspace(8)* null %185 = extractelement <4 x float> %184, i32 1 %186 = fmul float %148, %185 %187 = fadd float %186, %8 %188 = load <4 x float> addrspace(8)* null %189 = extractelement <4 x float> %188, i32 0 %190 = fmul float -2.500000e-01, %189 %191 = fadd float %190, %7 %192 = load <4 x float> addrspace(8)* null %193 = extractelement <4 x float> %192, i32 1 %194 = fmul float %179, %193 %195 = fadd float %194, %8 %196 = insertelement <4 x float> undef, float %183, i32 0 %197 = insertelement <4 x float> %196, float %187, i32 1 %198 = insertelement <4 x float> %197, float %187, i32 2 %199 = insertelement <4 x float> %198, float 0.000000e+00, i32 3 %200 = call <4 x float> @llvm.AMDGPU.txl(<4 x float> %199, i32 18, i32 2, i32 2) %201 = extractelement <4 x float> %200, i32 1 %202 = insertelement <4 x float> undef, float %191, i32 0 %203 = insertelement <4 x float> %202, float %195, i32 1 %204 = insertelement <4 x float> %203, float %195, i32 2 %205 = insertelement <4 x float> %204, float 0.000000e+00, i32 3 %206 = call <4 x float> @llvm.AMDGPU.txl(<4 x float> %205, i32 18, i32 2, i32 2) %207 = extractelement <4 x float> %206, i32 1 %208 = fmul float 4.000000e+00, %201 %209 = fmul float 4.000000e+00, %207 %210 = call float @llvm.AMDIL.round.nearest.(float %208) %211 = call float @llvm.AMDIL.round.nearest.(float %209) %212 = call float @fabs(float %148) %213 = call float @fabs(float %178) %214 = fmul float 3.300000e+01, %210 %215 = fadd float %214, %212 %216 = fmul float 3.300000e+01, %211 %217 = fadd float %216, %213 %218 = fmul float %215, 0x3F78F9C140000000 %219 = fmul float %217, 0x3F78F9C140000000 %220 = fmul float %217, 0x3F78F9C140000000 %221 = insertelement <4 x float> undef, float %218, i32 0 %222 = insertelement <4 x float> %221, float %219, i32 1 %223 = insertelement <4 x float> %222, float %220, i32 2 %224 = insertelement <4 x float> %223, float 0.000000e+00, i32 3 %225 = call <4 x float> @llvm.AMDGPU.txl(<4 x float> %224, i32 16, i32 0, i32 2) %226 = extractelement <4 x float> %225, i32 0 %227 = extractelement <4 x float> %225, i32 1 br label %ENDIF42 ENDIF55: ; preds = %LOOP54 %228 = load <4 x float> addrspace(8)* null %229 = extractelement <4 x float> %228, i32 0 %230 = fmul float %229, 0.000000e+00 %231 = fadd float %230, %7 %232 = load <4 x float> addrspace(8)* null %233 = extractelement <4 x float> %232, i32 1 %234 = fmul float %233, %temp16.2 %235 = fadd float %234, %8 %236 = load <4 x float> addrspace(8)* null %237 = extractelement <4 x float> %236, i32 1 %238 = fmul float %237, %temp16.2 %239 = fadd float %238, %8 %240 = insertelement <4 x float> undef, float %231, i32 0 %241 = insertelement <4 x float> %240, float %235, i32 1 %242 = insertelement <4 x float> %241, float %239, i32 2 %243 = insertelement <4 x float> %242, float 0.000000e+00, i32 3 %244 = call <4 x float> @llvm.AMDGPU.txl(<4 x float> %243, i32 18, i32 2, i32 2) %245 = extractelement <4 x float> %244, i32 0 %246 = fcmp olt float %245, 0x3FECCCCCC0000000 %247 = select i1 %246, float 1.000000e+00, float 0.000000e+00 %248 = fcmp une float %247, 0.000000e+00 br i1 %248, label %ENDLOOP53, label %ENDIF58 ENDIF58: ; preds = %ENDIF55 %249 = fadd float %temp16.2, 2.000000e+00 br label %LOOP54 } ; Function Attrs: readnone declare <2 x float> @llvm.R600.interp.xy(i32, float, float) #1 ; Function Attrs: readnone declare <2 x float> @llvm.R600.interp.zw(i32, float, float) #1 ; Function Attrs: readnone declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32, i32) #1 ; Function Attrs: readnone declare <4 x float> @llvm.AMDGPU.txl(<4 x float>, i32, i32, i32) #1 ; Function Attrs: readnone declare float @llvm.AMDIL.round.nearest.(float) #1 ; Function Attrs: readonly declare float @fabs(float) #2 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } attributes #2 = { readonly } Shader Disassembly: ALU 3, @122, KC0[], KC1[] ; 0000007A A00C0000 TEX 0 @100 ; 00000064 80400000 ALU_PUSH_BEFORE 2, @126, KC0[], KC1[] ; 0000007E A4080000 JUMP @5 POP:0 ; 00000005 82800000 ALU 2, @129, KC0[], KC1[] ; 00000081 A0080000 ELSE @48 POP:1 ; 00000030 83400001 ALU 1, @132, KC0[], KC1[] ; 00000084 A0040000 LOOP_START_DX10 @25 ; 00000019 81800000 ALU_PUSH_BEFORE 4, @134, KC0[], KC1[] ; 00000086 A4100000 JUMP @11 POP:0 ; 0000000B 82800000 ALU 1, @139, KC0[], KC1[] ; 0000008B A0040000 ELSE @20 POP:1 ; 00000014 83400001 ALU 1, @141, KC0[CB0:0-32], KC1[] ; 8000008D A0040000 TEX 0 @102 ; 00000066 80400000 ALU_PUSH_BEFORE 3, @143, KC0[], KC1[] ; 0000008F A40C0000 JUMP @17 POP:0 ; 00000011 82800000 ALU 1, @147, KC0[], KC1[] ; 00000093 A0040000 ELSE @19 POP:1 ; 00000013 83400001 ALU_POP_AFTER 2, @149, KC0[], KC1[] ; 00000095 A8080000 POP @20 POP:1 ; 00000014 83800001 ALU_PUSH_BEFORE 4, @152, KC0[], KC1[] ; 00000098 A4100000 JUMP @24 POP:1 ; 00000018 82800001 LOOP_BREAK @24 ; 00000018 82400000 POP @24 POP:1 ; 00000018 83800001 END_LOOP @8 ; 00000008 81400000 ALU 6, @157, KC0[], KC1[] ; 0000009D A0180000 LOOP_START_DX10 @44 ; 0000002C 81800000 ALU_PUSH_BEFORE 4, @164, KC0[], KC1[] ; 000000A4 A4100000 JUMP @30 POP:0 ; 0000001E 82800000 ALU 1, @169, KC0[], KC1[] ; 000000A9 A0040000 ELSE @39 POP:1 ; 00000027 83400001 ALU 1, @171, KC0[CB0:0-32], KC1[] ; 800000AB A0040000 TEX 0 @104 ; 00000068 80400000 ALU_PUSH_BEFORE 3, @173, KC0[], KC1[] ; 000000AD A40C0000 JUMP @36 POP:0 ; 00000024 82800000 ALU 1, @177, KC0[], KC1[] ; 000000B1 A0040000 ELSE @38 POP:1 ; 00000026 83400001 ALU_POP_AFTER 2, @179, KC0[], KC1[] ; 000000B3 A8080000 POP @39 POP:1 ; 00000027 83800001 ALU_PUSH_BEFORE 4, @182, KC0[], KC1[] ; 000000B6 A4100000 JUMP @43 POP:1 ; 0000002B 82800001 LOOP_BREAK @43 ; 0000002B 82400000 POP @43 POP:1 ; 0000002B 83800001 END_LOOP @27 ; 0000001B 81400000 ALU 11, @187, KC0[CB0:0-32], KC1[] ; 800000BB A02C0000 TEX 1 @106 ; 0000006A 80400400 ALU_POP_AFTER 14, @199, KC0[], KC1[] ; 000000C7 A8380000 TEX 0 @110 ; 0000006E 80400000 ALU_PUSH_BEFORE 2, @214, KC0[], KC1[] ; 000000D6 A4080000 JUMP @51 POP:0 ; 00000033 82800000 ALU 2, @217, KC0[], KC1[] ; 000000D9 A0080000 ELSE @96 POP:1 ; 00000060 83400001 ALU 1, @220, KC0[], KC1[] ; 000000DC A0040000 LOOP_START_DX10 @71 ; 00000047 81800000 ALU_PUSH_BEFORE 4, @222, KC0[], KC1[] ; 000000DE A4100000 JUMP @57 POP:0 ; 00000039 82800000 ALU 1, @227, KC0[], KC1[] ; 000000E3 A0040000 ELSE @66 POP:1 ; 00000042 83400001 ALU 1, @229, KC0[CB0:0-32], KC1[] ; 800000E5 A0040000 TEX 0 @112 ; 00000070 80400000 ALU_PUSH_BEFORE 3, @231, KC0[], KC1[] ; 000000E7 A40C0000 JUMP @63 POP:0 ; 0000003F 82800000 ALU 1, @235, KC0[], KC1[] ; 000000EB A0040000 ELSE @65 POP:1 ; 00000041 83400001 ALU_POP_AFTER 2, @237, KC0[], KC1[] ; 000000ED A8080000 POP @66 POP:1 ; 00000042 83800001 ALU_PUSH_BEFORE 4, @240, KC0[], KC1[] ; 000000F0 A4100000 JUMP @70 POP:1 ; 00000046 82800001 LOOP_BREAK @70 ; 00000046 82400000 POP @70 POP:1 ; 00000046 83800001 END_LOOP @54 ; 00000036 81400000 ALU 8, @245, KC0[], KC1[] ; 000000F5 A0200000 LOOP_START_DX10 @90 ; 0000005A 81800000 ALU_PUSH_BEFORE 4, @254, KC0[], KC1[] ; 000000FE A4100000 JUMP @76 POP:0 ; 0000004C 82800000 ALU 1, @259, KC0[], KC1[] ; 00000103 A0040000 ELSE @85 POP:1 ; 00000055 83400001 ALU 1, @261, KC0[CB0:0-32], KC1[] ; 80000105 A0040000 TEX 0 @114 ; 00000072 80400000 ALU_PUSH_BEFORE 3, @263, KC0[], KC1[] ; 00000107 A40C0000 JUMP @82 POP:0 ; 00000052 82800000 ALU 1, @267, KC0[], KC1[] ; 0000010B A0040000 ELSE @84 POP:1 ; 00000054 83400001 ALU_POP_AFTER 3, @269, KC0[], KC1[] ; 0000010D A80C0000 POP @85 POP:1 ; 00000055 83800001 ALU_PUSH_BEFORE 4, @273, KC0[], KC1[] ; 00000111 A4100000 JUMP @89 POP:1 ; 00000059 82800001 LOOP_BREAK @89 ; 00000059 82400000 POP @89 POP:1 ; 00000059 83800001 END_LOOP @73 ; 00000049 81400000 ALU 2, @278, KC0[CB0:0-32], KC1[] ; 80000116 A0080000 TEX 0 @116 ; 00000074 80400000 ALU 8, @281, KC0[CB0:0-32], KC1[] ; 80000119 A0200000 TEX 0 @118 ; 00000076 80400000 ALU_POP_AFTER 14, @290, KC0[], KC1[] ; 00000122 A8380000 TEX 0 @120 ; 00000078 80400000 ALU 1, @305, KC0[], KC1[] ; 00000131 A0040000 EXPORT T2.XYZW ; C0010000 95200688 CF_END ; 00000000 88000000 PAD ; 00000000 00000000 Fetch clause starting at 100: ; TEX_SAMPLE T1.XYZW, T0.XY__ RID:17 SID:1 CT:NNNN ; 00001110 F00D1001 FC808000 00000000 Fetch clause starting at 102: ; TEX_SAMPLE_L T2.XYZW, T2.XYY0 RID:18 SID:2 CT:NNNN ; 00021211 F00D1002 84810000 00000000 Fetch clause starting at 104: ; TEX_SAMPLE_L T3.XYZW, T3.XYY0 RID:18 SID:2 CT:NNNN ; 00031211 F00D1003 84810000 00000000 Fetch clause starting at 106: ; TEX_SAMPLE_L T5.XYZW, T5.XYY0 RID:18 SID:2 CT:NNNN ; 00051211 F00D1005 84810000 00000000 TEX_SAMPLE_L T4.XYZW, T4.XYY0 RID:18 SID:2 CT:NNNN ; 00041211 F00D1004 84810000 00000000 Fetch clause starting at 110: ; TEX_SAMPLE_L T2.XYZW, T2.XYY0 RID:16 SID:0 CT:NNNN ; 00021011 F00D1002 84800000 00000000 Fetch clause starting at 112: ; TEX_SAMPLE_L T1.XYZW, T1.XYY0 RID:18 SID:2 CT:NNNN ; 00011211 F00D1001 84810000 00000000 Fetch clause starting at 114: ; TEX_SAMPLE_L T3.XYZW, T3.XYY0 RID:18 SID:2 CT:NNNN ; 00031211 F00D1003 84810000 00000000 Fetch clause starting at 116: ; TEX_SAMPLE_L T5.XYZW, T4.XYY0 RID:18 SID:2 CT:NNNN ; 00041211 F00D1005 84810000 00000000 Fetch clause starting at 118: ; TEX_SAMPLE_L T0.XYZW, T4.XYY0 RID:18 SID:2 CT:NNNN ; 00041211 F00D1000 84810000 00000000 Fetch clause starting at 120: ; TEX_SAMPLE_L T0.XYZW, T1.XYY0 RID:16 SID:0 CT:NNNN ; 00011011 F00D1000 84800000 00000000 ALU clause starting at 122: ; INTERP_XY T0.X, T0.Y, ARRAY_BASE, ; 00380400 00146B10 INTERP_XY T0.Y, T0.X, ARRAY_BASE, ; 00380000 20146B10 INTERP_XY T0.Z (MASKED), T0.Y, ARRAY_BASE, ; 00380400 40146B00 INTERP_XY * T0.W (MASKED), T0.X, ARRAY_BASE, ; 80380000 60146B00 ALU clause starting at 126: ; SETNE * T2.Y, T1.Y, 0.0, ; 801F0401 20400590 SETNE_DX10 * T3.W, PV.Y, 0.0, ; 801F04FE 60600790 PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002104 ALU clause starting at 129: ; MOV * T2.Y, literal.x, ; 800000FD 20400C90 0(0.000000e+00), 0(0.000000e+00) ; 00000000 00000000 MOV * T2.X, PV.Y, ; 800004FE 00400C90 ALU clause starting at 132: ; MOV * T3.Z, literal.x, ; 800000FD 40600C90 -1077936128(-1.500000e+00), 0(0.000000e+00) ; BFC00000 00000000 ALU clause starting at 134: ; MOV * T3.X, T3.Z, ; 80000803 00600C90 SETGE * T3.W, literal.x, PV.X, ; 801FC0FD 60600510 -1048576000(-1.600000e+01), 0(0.000000e+00) ; C1800000 00000000 SETE_DX10 * T3.W, PV.W, 0.0, ; 801F0CFE 60600610 PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002104 ALU clause starting at 139: ; MOV * T3.W, literal.x, ; 800000FD 60600C90 1(1.401298e-45), 0(0.000000e+00) ; 00000001 00000000 ALU clause starting at 141: ; MULADD_IEEE T2.X, KC0[0].X, T3.X, T0.X, ; 00006080 00430000 MULADD_IEEE * T2.Y, KC0[0].Y, 0.0, T0.Y, ; 801F0480 20430400 ALU clause starting at 143: ; SETGT * T3.W, literal.x, T2.Y, ; 808040FD 60600490 1063675494(9.000000e-01), 0(0.000000e+00) ; 3F666666 00000000 SETE_DX10 * T3.W, PV.W, 0.0, ; 801F0CFE 60600610 PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002104 ALU clause starting at 147: ; MOV * T3.W, literal.x, ; 800000FD 60600C90 1(1.401298e-45), 0(0.000000e+00) ; 00000001 00000000 ALU clause starting at 149: ; ADD T3.Z, T3.X, literal.x, ; 001FA003 40600010 MOV * T3.W, literal.y, ; 800004FD 60600C90 -1073741824(-2.000000e+00), 0(0.000000e+00) ; C0000000 00000000 ALU clause starting at 152: ; LSHL * T3.W, T3.W, literal.x, ; 801FAC03 60600B90 31(4.344025e-44), 0(0.000000e+00) ; 0000001F 00000000 ASHR * T3.W, PV.W, literal.x, ; 801FACFE 60600A90 31(4.344025e-44), 0(0.000000e+00) ; 0000001F 00000000 PRED_SETNE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002284 ALU clause starting at 157: ; ADD * T3.W, T3.X, literal.x, ; 801FA003 60600010 1069547520(1.500000e+00), 0(0.000000e+00) ; 3FC00000 00000000 MULADD_IEEE * T2.W, T2.Y, literal.x, PV.W, ; 801FA402 60430CFE -1073741824(-2.000000e+00), 0(0.000000e+00) ; C0000000 00000000 MOV T2.Z, literal.x, ; 000000FD 40400C90 MAX * T2.W, literal.y, PV.W, ; 819FC4FD 60400190 1069547520(1.500000e+00), -1048576000(-1.600000e+01) ; 3FC00000 C1800000 ALU clause starting at 164: ; MOV * T2.X, T2.Z, ; 80000802 00400C90 SETGE * T3.Y, PV.X, literal.x, ; 801FA0FE 20600510 1098907648(1.600000e+01), 0(0.000000e+00) ; 41800000 00000000 SETE_DX10 * T4.W, PV.Y, 0.0, ; 801F04FE 60800610 PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002104 ALU clause starting at 169: ; MOV * T4.W, literal.x, ; 800000FD 60800C90 1(1.401298e-45), 0(0.000000e+00) ; 00000001 00000000 ALU clause starting at 171: ; MULADD_IEEE T3.X, KC0[0].X, T2.X, T0.X, ; 00004080 00630000 MULADD_IEEE * T3.Y, KC0[0].Y, 0.0, T0.Y, ; 801F0480 20630400 ALU clause starting at 173: ; SETGT * T4.W, literal.x, T3.Y, ; 808060FD 60800490 1063675494(9.000000e-01), 0(0.000000e+00) ; 3F666666 00000000 SETE_DX10 * T4.W, PV.W, 0.0, ; 801F0CFE 60800610 PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002104 ALU clause starting at 177: ; MOV * T4.W, literal.x, ; 800000FD 60800C90 1(1.401298e-45), 0(0.000000e+00) ; 00000001 00000000 ALU clause starting at 179: ; ADD T2.Z, T2.X, literal.x, ; 001FA002 40400010 MOV * T4.W, literal.y, ; 800004FD 60800C90 1073741824(2.000000e+00), 0(0.000000e+00) ; 40000000 00000000 ALU clause starting at 182: ; LSHL * T4.W, T4.W, literal.x, ; 801FAC04 60800B90 31(4.344025e-44), 0(0.000000e+00) ; 0000001F 00000000 ASHR * T4.W, PV.W, literal.x, ; 801FACFE 60800A90 31(4.344025e-44), 0(0.000000e+00) ; 0000001F 00000000 PRED_SETNE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002284 ALU clause starting at 187: ; ADD T2.Z, T3.Y, T3.Y, ; 00806403 40400010 ADD * T3.W, T2.X, literal.x, ; 801FA002 60600010 -1077936128(-1.500000e+00), 0(0.000000e+00) ; BFC00000 00000000 ADD * T3.W, PV.Z, PV.W, ; 819FC8FE 60600010 MIN * T3.W, literal.x, PV.W, ; 819FC0FD 60600210 1098907648(1.600000e+01), 0(0.000000e+00) ; 41800000 00000000 MULADD_IEEE T4.X, T2.W, KC0[0].X, T0.X, ; 00100C02 00830000 ADD * T5.W, PV.W, 1.0, ; 801F2CFE 60A00010 MULADD_IEEE T5.X, PV.W, KC0[0].X, T0.X, ; 00100CFE 00A30000 MULADD_IEEE * T4.Y, KC0[0].Y, literal.x, T0.Y, ; 801FA480 20830400 -1098907648(-2.500000e-01), 0(0.000000e+00) ; BE800000 00000000 MOV * T5.Y, PV.Y, ; 800004FE 20A00C90 ALU clause starting at 199: ; MUL_IEEE * T4.W, T4.X, literal.x, ; 801FA004 60800110 1082130432(4.000000e+00), 0(0.000000e+00) ; 40800000 00000000 RNDNE T2.Y, PV.W, ; 00000CFE 20400990 MOV T2.Z, |T2.W|, ; 00000C02 40400C91 MUL_IEEE * T2.W, T5.X, literal.x, ; 801FA005 60400110 1082130432(4.000000e+00), 0(0.000000e+00) ; 40800000 00000000 RNDNE T3.Y, PV.W, ; 00000CFE 20600990 MOV T3.Z, |T3.W|, ; 00000C03 40600C91 MULADD_IEEE * T2.W, PV.Y, literal.x, PV.Z, ; 801FA4FE 604308FE 1107558400(3.300000e+01), 0(0.000000e+00) ; 42040000 00000000 MUL_IEEE T2.X, PV.W, literal.x, ; 001FACFE 00400110 MULADD_IEEE * T3.W, PV.Y, literal.y, PV.Z, ; 809FA4FE 606308FE 1002950154(6.097560e-03), 1107558400(3.300000e+01) ; 3BC7CE0A 42040000 MUL_IEEE * T2.Y, PV.W, literal.x, ; 801FACFE 20400110 1002950154(6.097560e-03), 0(0.000000e+00) ; 3BC7CE0A 00000000 ALU clause starting at 214: ; SETNE * T3.W, T1.X, 0.0, ; 801F0001 60600590 SETNE_DX10 * T3.W, PV.W, 0.0, ; 801F0CFE 60600790 PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002104 ALU clause starting at 217: ; MOV * T0.Y, literal.x, ; 800000FD 20000C90 0(0.000000e+00), 0(0.000000e+00) ; 00000000 00000000 MOV * T0.X, PV.Y, ; 800004FE 00000C90 ALU clause starting at 220: ; MOV * T3.Z, literal.x, ; 800000FD 40600C90 -1077936128(-1.500000e+00), 0(0.000000e+00) ; BFC00000 00000000 ALU clause starting at 222: ; MOV * T3.X, T3.Z, ; 80000803 00600C90 SETGE * T3.W, literal.x, PV.X, ; 801FC0FD 60600510 -1048576000(-1.600000e+01), 0(0.000000e+00) ; C1800000 00000000 SETE_DX10 * T3.W, PV.W, 0.0, ; 801F0CFE 60600610 PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002104 ALU clause starting at 227: ; MOV * T3.W, literal.x, ; 800000FD 60600C90 1(1.401298e-45), 0(0.000000e+00) ; 00000001 00000000 ALU clause starting at 229: ; MULADD_IEEE T1.X, KC0[0].X, 0.0, T0.X, ; 001F0080 00230000 MULADD_IEEE * T1.Y, KC0[0].Y, T3.X, T0.Y, ; 80006480 20230400 ALU clause starting at 231: ; SETGT * T3.W, literal.x, T1.X, ; 800020FD 60600490 1063675494(9.000000e-01), 0(0.000000e+00) ; 3F666666 00000000 SETE_DX10 * T3.W, PV.W, 0.0, ; 801F0CFE 60600610 PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002104 ALU clause starting at 235: ; MOV * T3.W, literal.x, ; 800000FD 60600C90 1(1.401298e-45), 0(0.000000e+00) ; 00000001 00000000 ALU clause starting at 237: ; ADD T3.Z, T3.X, literal.x, ; 001FA003 40600010 MOV * T3.W, literal.y, ; 800004FD 60600C90 -1073741824(-2.000000e+00), 0(0.000000e+00) ; C0000000 00000000 ALU clause starting at 240: ; LSHL * T3.W, T3.W, literal.x, ; 801FAC03 60600B90 31(4.344025e-44), 0(0.000000e+00) ; 0000001F 00000000 ASHR * T3.W, PV.W, literal.x, ; 801FACFE 60600A90 31(4.344025e-44), 0(0.000000e+00) ; 0000001F 00000000 PRED_SETNE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002284 ALU clause starting at 245: ; ADD * T3.W, T3.X, literal.x, ; 801FA003 60600010 1069547520(1.500000e+00), 0(0.000000e+00) ; 3FC00000 00000000 MULADD_IEEE * T1.W, T1.X, literal.x, PV.W, ; 801FA001 60230CFE -1073741824(-2.000000e+00), 0(0.000000e+00) ; C0000000 00000000 MAX * T1.W, literal.x, PV.W, ; 819FC0FD 60200190 -1048576000(-1.600000e+01), 0(0.000000e+00) ; C1800000 00000000 MOV T3.X, PV.W, ; 00000CFE 00600C90 MOV * T4.W, literal.x, ; 800000FD 60800C90 1069547520(1.500000e+00), 0(0.000000e+00) ; 3FC00000 00000000 ALU clause starting at 254: ; MOV * T1.X, T4.W, ; 80000C04 00200C90 SETGE * T4.W, PV.X, literal.x, ; 801FA0FE 60800510 1098907648(1.600000e+01), 0(0.000000e+00) ; 41800000 00000000 SETE_DX10 * T4.W, PV.W, 0.0, ; 801F0CFE 60800610 PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002104 ALU clause starting at 259: ; MOV * T5.W, literal.x, ; 800000FD 60A00C90 1(1.401298e-45), 0(0.000000e+00) ; 00000001 00000000 ALU clause starting at 261: ; MULADD_IEEE T3.X, KC0[0].X, 0.0, T0.X, ; 001F0080 00630000 MULADD_IEEE * T3.Y, KC0[0].Y, T1.X, T0.Y, ; 80002480 20630400 ALU clause starting at 263: ; SETGT * T4.W, literal.x, T3.X, ; 800060FD 60800490 1063675494(9.000000e-01), 0(0.000000e+00) ; 3F666666 00000000 SETE_DX10 * T4.W, PV.W, 0.0, ; 801F0CFE 60800610 PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002104 ALU clause starting at 267: ; MOV * T5.W, literal.x, ; 800000FD 60A00C90 1(1.401298e-45), 0(0.000000e+00) ; 00000001 00000000 ALU clause starting at 269: ; MOV * T5.W, literal.x, ; 800000FD 60A00C90 0(0.000000e+00), 0(0.000000e+00) ; 00000000 00000000 ADD * T4.W, T1.X, literal.x, ; 801FA001 60800010 1073741824(2.000000e+00), 0(0.000000e+00) ; 40000000 00000000 ALU clause starting at 273: ; LSHL * T5.W, T5.W, literal.x, ; 801FAC05 60A00B90 31(4.344025e-44), 0(0.000000e+00) ; 0000001F 00000000 ASHR * T5.W, PV.W, literal.x, ; 801FACFE 60A00A90 31(4.344025e-44), 0(0.000000e+00) ; 0000001F 00000000 PRED_SETNE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002284 ALU clause starting at 278: ; MULADD_IEEE T4.X, KC0[0].X, literal.x, T0.X, ; 001FA080 00830000 MULADD_IEEE * T4.Y, T1.W, KC0[0].Y, T0.Y, ; 80900C01 20830400 -1098907648(-2.500000e-01), 0(0.000000e+00) ; BE800000 00000000 ALU clause starting at 281: ; ADD T1.Z, T3.X, T3.X, ; 00006003 40200010 ADD * T3.W, T1.X, literal.x, BS:VEC_120/SCL_212 ; 801FA001 60680010 -1077936128(-1.500000e+00), 0(0.000000e+00) ; BFC00000 00000000 ADD * T3.W, PV.Z, PV.W, ; 819FC8FE 60600010 MIN * T3.W, literal.x, PV.W, ; 819FC0FD 60600210 1098907648(1.600000e+01), 0(0.000000e+00) ; 41800000 00000000 ADD * T6.W, PV.W, 1.0, ; 801F2CFE 60C00010 MULADD_IEEE * T0.W, PV.W, KC0[0].Y, T0.Y, ; 80900CFE 60030400 MOV * T4.Y, PV.W, ; 80000CFE 20800C90 ALU clause starting at 290: ; MUL_IEEE * T4.W, T5.Y, literal.x, ; 801FA405 60800110 1082130432(4.000000e+00), 0(0.000000e+00) ; 40800000 00000000 RNDNE T1.Y, PV.W, ; 00000CFE 20200990 MOV T1.Z, |T1.W|, ; 00000C01 40200C91 MUL_IEEE * T0.W, T0.Y, literal.x, ; 801FA400 60000110 1082130432(4.000000e+00), 0(0.000000e+00) ; 40800000 00000000 RNDNE T0.Y, PV.W, ; 00000CFE 20000990 MOV T0.Z, |T3.W|, ; 00000C03 40000C91 MULADD_IEEE * T0.W, PV.Y, literal.x, PV.Z, ; 801FA4FE 600308FE 1107558400(3.300000e+01), 0(0.000000e+00) ; 42040000 00000000 MUL_IEEE T1.X, PV.W, literal.x, ; 001FACFE 00200110 MULADD_IEEE * T0.W, PV.Y, literal.y, PV.Z, ; 809FA4FE 600308FE 1002950154(6.097560e-03), 1107558400(3.300000e+01) ; 3BC7CE0A 42040000 MUL_IEEE * T1.Y, PV.W, literal.x, ; 801FACFE 20200110 1002950154(6.097560e-03), 0(0.000000e+00) ; 3BC7CE0A 00000000 ALU clause starting at 305: ; MOV T2.Z, T0.X, ; 00000000 40400C90 MOV * T2.W, T0.Y, ; 80000400 60400C90 ===== SHADER #84 ======================================== PS/CAYMAN/CAYMAN ===== ===== 614 dw ===== 7 gprs ===== 3 stack ======================================== 0000 0000007a a00c0000 ALU 4 @244 0244 00380400 00146b10 1 x: INTERP_XY R0.x, R0.y, Param0.x VEC_210 0246 00380000 20146b10 y: INTERP_XY R0.y, R0.x, Param0.x VEC_210 0248 00380400 40146b00 z: INTERP_XY __.z, R0.y, Param0.x VEC_210 0250 80380000 60146b00 w: INTERP_XY __.w, R0.x, Param0.x VEC_210 0002 00000064 80400000 TEX 1 @200 0200 00001110 f00d1001 fc808000 SAMPLE R1.xyzw, R0.xy__, RID:17, SID:1 CT:NNNN 0004 0000007e a4080000 ALU_PUSH_BEFORE 3 @252 0252 801f0401 20400590 2 y: SETNE R2.y, R1.y, 0 0254 801f04fe 60600790 3 w: SETNE_DX10 R3.w, PV.y, 0 0256 801f0cfe 00002104 4 M x: PRED_SETE_INT __.x, PV.w, 0 0006 00000005 82800000 JUMP @10 0008 00000081 a0080000 ALU 3 @258 0258 800000fd 20400c90 5 y: MOV R2.y, [0x00000000 0].x 0260 00000000 0262 800004fe 00400c90 6 x: MOV R2.x, PV.y 0010 00000030 83400001 ELSE @96 POP:1 0012 00000084 a0040000 ALU 2 @264 0264 800000fd 40600c90 7 z: MOV R3.z, [0xbfc00000 -1.5].x 0266 bfc00000 0014 00000019 81800000 LOOP_START_DX10 @50 0016 00000086 a4100000 ALU_PUSH_BEFORE 5 @268 0268 80000803 00600c90 8 x: MOV R3.x, R3.z 0270 801fc0fd 60600510 9 w: SETGE R3.w, [0xc1800000 -16].x, PV.x 0272 c1800000 0274 801f0cfe 60600610 10 w: SETE_DX10 R3.w, PV.w, 0 0276 801f0cfe 00002104 11 M x: PRED_SETE_INT __.x, PV.w, 0 0018 0000000b 82800000 JUMP @22 0020 0000008b a0040000 ALU 2 @278 0278 800000fd 60600c90 12 w: MOV R3.w, [0x00000001 1.4013e-45].x 0280 00000001 0022 00000014 83400001 ELSE @40 POP:1 0024 8000008d a0040000 ALU 2 @282 KC0[CB0:0-31] 0282 00006080 00430000 13 x: MULADD_IEEE R2.x, KC0[0].x, R3.x, R0.x 0284 801f0480 20430400 y: MULADD_IEEE R2.y, KC0[0].y, 0, R0.y 0026 00000066 80400000 TEX 1 @204 0204 00021211 f00d1002 84810000 SAMPLE_L R2.xyzw, R2.xyy0, RID:18, SID:2 CT:NNNN 0028 0000008f a40c0000 ALU_PUSH_BEFORE 4 @286 0286 808040fd 60600490 14 w: SETGT R3.w, [0x3f666666 0.9].x, R2.y 0288 3f666666 0290 801f0cfe 60600610 15 w: SETE_DX10 R3.w, PV.w, 0 0292 801f0cfe 00002104 16 M x: PRED_SETE_INT __.x, PV.w, 0 0030 00000011 82800000 JUMP @34 0032 00000093 a0040000 ALU 2 @294 0294 800000fd 60600c90 17 w: MOV R3.w, [0x00000001 1.4013e-45].x 0296 00000001 0034 00000013 83400001 ELSE @38 POP:1 0036 00000095 a8080000 ALU_POP_AFTER 3 @298 0298 001fa003 40600010 18 z: ADD R3.z, R3.x, [0xc0000000 -2].x 0300 800004fd 60600c90 w: MOV R3.w, [0x00000000 0].y 0302 c0000000 0303 00000000 0038 00000014 83800001 POP @40 POP:1 0040 00000098 a4100000 ALU_PUSH_BEFORE 5 @304 0304 801fac03 60600b90 19 w: LSHL_INT R3.w, R3.w, [0x0000001f 4.34403e-44].x 0306 0000001f 0308 801facfe 60600a90 20 w: ASHR_INT R3.w, PV.w, [0x0000001f 4.34403e-44].x 0310 0000001f 0312 801f0cfe 00002284 21 M x: PRED_SETNE_INT __.x, PV.w, 0 0042 00000018 82800001 JUMP @48 POP:1 0044 00000018 82400000 LOOP_BREAK @48 0046 00000018 83800001 POP @48 POP:1 0048 00000008 81400000 LOOP_END @16 0050 0000009d a0180000 ALU 7 @314 0314 801fa003 60600010 22 w: ADD R3.w, R3.x, [0x3fc00000 1.5].x 0316 3fc00000 0318 801fa402 60430cfe 23 w: MULADD_IEEE R2.w, R2.y, [0xc0000000 -2].x, PV.w 0320 c0000000 0322 000000fd 40400c90 24 z: MOV R2.z, [0x3fc00000 1.5].x 0324 819fc4fd 60400190 w: MAX R2.w, [0xc1800000 -16].y, PV.w 0326 3fc00000 0327 c1800000 0052 0000002c 81800000 LOOP_START_DX10 @88 0054 000000a4 a4100000 ALU_PUSH_BEFORE 5 @328 0328 80000802 00400c90 25 x: MOV R2.x, R2.z 0330 801fa0fe 20600510 26 y: SETGE R3.y, PV.x, [0x41800000 16].x 0332 41800000 0334 801f04fe 60800610 27 w: SETE_DX10 R4.w, PV.y, 0 0336 801f0cfe 00002104 28 M x: PRED_SETE_INT __.x, PV.w, 0 0056 0000001e 82800000 JUMP @60 0058 000000a9 a0040000 ALU 2 @338 0338 800000fd 60800c90 29 w: MOV R4.w, [0x00000001 1.4013e-45].x 0340 00000001 0060 00000027 83400001 ELSE @78 POP:1 0062 800000ab a0040000 ALU 2 @342 KC0[CB0:0-31] 0342 00004080 00630000 30 x: MULADD_IEEE R3.x, KC0[0].x, R2.x, R0.x 0344 801f0480 20630400 y: MULADD_IEEE R3.y, KC0[0].y, 0, R0.y 0064 00000068 80400000 TEX 1 @208 0208 00031211 f00d1003 84810000 SAMPLE_L R3.xyzw, R3.xyy0, RID:18, SID:2 CT:NNNN 0066 000000ad a40c0000 ALU_PUSH_BEFORE 4 @346 0346 808060fd 60800490 31 w: SETGT R4.w, [0x3f666666 0.9].x, R3.y 0348 3f666666 0350 801f0cfe 60800610 32 w: SETE_DX10 R4.w, PV.w, 0 0352 801f0cfe 00002104 33 M x: PRED_SETE_INT __.x, PV.w, 0 0068 00000024 82800000 JUMP @72 0070 000000b1 a0040000 ALU 2 @354 0354 800000fd 60800c90 34 w: MOV R4.w, [0x00000001 1.4013e-45].x 0356 00000001 0072 00000026 83400001 ELSE @76 POP:1 0074 000000b3 a8080000 ALU_POP_AFTER 3 @358 0358 001fa002 40400010 35 z: ADD R2.z, R2.x, [0x40000000 2].x 0360 800004fd 60800c90 w: MOV R4.w, [0x00000000 0].y 0362 40000000 0363 00000000 0076 00000027 83800001 POP @78 POP:1 0078 000000b6 a4100000 ALU_PUSH_BEFORE 5 @364 0364 801fac04 60800b90 36 w: LSHL_INT R4.w, R4.w, [0x0000001f 4.34403e-44].x 0366 0000001f 0368 801facfe 60800a90 37 w: ASHR_INT R4.w, PV.w, [0x0000001f 4.34403e-44].x 0370 0000001f 0372 801f0cfe 00002284 38 M x: PRED_SETNE_INT __.x, PV.w, 0 0080 0000002b 82800001 JUMP @86 POP:1 0082 0000002b 82400000 LOOP_BREAK @86 0084 0000002b 83800001 POP @86 POP:1 0086 0000001b 81400000 LOOP_END @54 0088 800000bb a02c0000 ALU 12 @374 KC0[CB0:0-31] 0374 00806403 40400010 39 z: ADD R2.z, R3.y, R3.y 0376 801fa002 60600010 w: ADD R3.w, R2.x, [0xbfc00000 -1.5].x 0378 bfc00000 0380 819fc8fe 60600010 40 w: ADD R3.w, PV.z, PV.w 0382 819fc0fd 60600210 41 w: MIN R3.w, [0x41800000 16].x, PV.w 0384 41800000 0386 00100c02 00830000 42 x: MULADD_IEEE R4.x, R2.w, KC0[0].x, R0.x 0388 801f2cfe 60a00010 w: ADD R5.w, PV.w, 1.0 0390 00100cfe 00a30000 43 x: MULADD_IEEE R5.x, PV.w, KC0[0].x, R0.x 0392 801fa480 20830400 y: MULADD_IEEE R4.y, KC0[0].y, [0xbe800000 -0.25].x, R0.y 0394 be800000 0396 800004fe 20a00c90 44 y: MOV R5.y, PV.y 0090 0000006a 80400400 TEX 2 @212 0212 00051211 f00d1005 84810000 SAMPLE_L R5.xyzw, R5.xyy0, RID:18, SID:2 CT:NNNN 0216 00041211 f00d1004 84810000 SAMPLE_L R4.xyzw, R4.xyy0, RID:18, SID:2 CT:NNNN 0092 000000c7 a8380000 ALU_POP_AFTER 15 @398 0398 801fa004 60800110 45 w: MUL_IEEE R4.w, R4.x, [0x40800000 4].x 0400 40800000 0402 00000cfe 20400990 46 y: RNDNE R2.y, PV.w 0404 00000c02 40400c91 z: MOV R2.z, |R2.w| 0406 801fa005 60400110 w: MUL_IEEE R2.w, R5.x, [0x40800000 4].x 0408 40800000 0410 00000cfe 20600990 47 y: RNDNE R3.y, PV.w 0412 00000c03 40600c91 z: MOV R3.z, |R3.w| 0414 801fa4fe 604308fe w: MULADD_IEEE R2.w, PV.y, [0x42040000 33].x, PV.z 0416 42040000 0418 001facfe 00400110 48 x: MUL_IEEE R2.x, PV.w, [0x3bc7ce0a 0.00609756].x 0420 809fa4fe 606308fe w: MULADD_IEEE R3.w, PV.y, [0x42040000 33].y, PV.z 0422 3bc7ce0a 0423 42040000 0424 801facfe 20400110 49 y: MUL_IEEE R2.y, PV.w, [0x3bc7ce0a 0.00609756].x 0426 3bc7ce0a 0094 0000006e 80400000 TEX 1 @220 0220 00021011 f00d1002 84800000 SAMPLE_L R2.xyzw, R2.xyy0, RID:16, SID:0 CT:NNNN 0096 000000d6 a4080000 ALU_PUSH_BEFORE 3 @428 0428 801f0001 60600590 50 w: SETNE R3.w, R1.x, 0 0430 801f0cfe 60600790 51 w: SETNE_DX10 R3.w, PV.w, 0 0432 801f0cfe 00002104 52 M x: PRED_SETE_INT __.x, PV.w, 0 0098 00000033 82800000 JUMP @102 0100 000000d9 a0080000 ALU 3 @434 0434 800000fd 20000c90 53 y: MOV R0.y, [0x00000000 0].x 0436 00000000 0438 800004fe 00000c90 54 x: MOV R0.x, PV.y 0102 00000060 83400001 ELSE @192 POP:1 0104 000000dc a0040000 ALU 2 @440 0440 800000fd 40600c90 55 z: MOV R3.z, [0xbfc00000 -1.5].x 0442 bfc00000 0106 00000047 81800000 LOOP_START_DX10 @142 0108 000000de a4100000 ALU_PUSH_BEFORE 5 @444 0444 80000803 00600c90 56 x: MOV R3.x, R3.z 0446 801fc0fd 60600510 57 w: SETGE R3.w, [0xc1800000 -16].x, PV.x 0448 c1800000 0450 801f0cfe 60600610 58 w: SETE_DX10 R3.w, PV.w, 0 0452 801f0cfe 00002104 59 M x: PRED_SETE_INT __.x, PV.w, 0 0110 00000039 82800000 JUMP @114 0112 000000e3 a0040000 ALU 2 @454 0454 800000fd 60600c90 60 w: MOV R3.w, [0x00000001 1.4013e-45].x 0456 00000001 0114 00000042 83400001 ELSE @132 POP:1 0116 800000e5 a0040000 ALU 2 @458 KC0[CB0:0-31] 0458 001f0080 00230000 61 x: MULADD_IEEE R1.x, KC0[0].x, 0, R0.x 0460 80006480 20230400 y: MULADD_IEEE R1.y, KC0[0].y, R3.x, R0.y 0118 00000070 80400000 TEX 1 @224 0224 00011211 f00d1001 84810000 SAMPLE_L R1.xyzw, R1.xyy0, RID:18, SID:2 CT:NNNN 0120 000000e7 a40c0000 ALU_PUSH_BEFORE 4 @462 0462 800020fd 60600490 62 w: SETGT R3.w, [0x3f666666 0.9].x, R1.x 0464 3f666666 0466 801f0cfe 60600610 63 w: SETE_DX10 R3.w, PV.w, 0 0468 801f0cfe 00002104 64 M x: PRED_SETE_INT __.x, PV.w, 0 0122 0000003f 82800000 JUMP @126 0124 000000eb a0040000 ALU 2 @470 0470 800000fd 60600c90 65 w: MOV R3.w, [0x00000001 1.4013e-45].x 0472 00000001 0126 00000041 83400001 ELSE @130 POP:1 0128 000000ed a8080000 ALU_POP_AFTER 3 @474 0474 001fa003 40600010 66 z: ADD R3.z, R3.x, [0xc0000000 -2].x 0476 800004fd 60600c90 w: MOV R3.w, [0x00000000 0].y 0478 c0000000 0479 00000000 0130 00000042 83800001 POP @132 POP:1 0132 000000f0 a4100000 ALU_PUSH_BEFORE 5 @480 0480 801fac03 60600b90 67 w: LSHL_INT R3.w, R3.w, [0x0000001f 4.34403e-44].x 0482 0000001f 0484 801facfe 60600a90 68 w: ASHR_INT R3.w, PV.w, [0x0000001f 4.34403e-44].x 0486 0000001f 0488 801f0cfe 00002284 69 M x: PRED_SETNE_INT __.x, PV.w, 0 0134 00000046 82800001 JUMP @140 POP:1 0136 00000046 82400000 LOOP_BREAK @140 0138 00000046 83800001 POP @140 POP:1 0140 00000036 81400000 LOOP_END @108 0142 000000f5 a0200000 ALU 9 @490 0490 801fa003 60600010 70 w: ADD R3.w, R3.x, [0x3fc00000 1.5].x 0492 3fc00000 0494 801fa001 60230cfe 71 w: MULADD_IEEE R1.w, R1.x, [0xc0000000 -2].x, PV.w 0496 c0000000 0498 819fc0fd 60200190 72 w: MAX R1.w, [0xc1800000 -16].x, PV.w 0500 c1800000 0502 00000cfe 00600c90 73 x: MOV R3.x, PV.w 0504 800000fd 60800c90 w: MOV R4.w, [0x3fc00000 1.5].x 0506 3fc00000 0144 0000005a 81800000 LOOP_START_DX10 @180 0146 000000fe a4100000 ALU_PUSH_BEFORE 5 @508 0508 80000c04 00200c90 74 x: MOV R1.x, R4.w 0510 801fa0fe 60800510 75 w: SETGE R4.w, PV.x, [0x41800000 16].x 0512 41800000 0514 801f0cfe 60800610 76 w: SETE_DX10 R4.w, PV.w, 0 0516 801f0cfe 00002104 77 M x: PRED_SETE_INT __.x, PV.w, 0 0148 0000004c 82800000 JUMP @152 0150 00000103 a0040000 ALU 2 @518 0518 800000fd 60a00c90 78 w: MOV R5.w, [0x00000001 1.4013e-45].x 0520 00000001 0152 00000055 83400001 ELSE @170 POP:1 0154 80000105 a0040000 ALU 2 @522 KC0[CB0:0-31] 0522 001f0080 00630000 79 x: MULADD_IEEE R3.x, KC0[0].x, 0, R0.x 0524 80002480 20630400 y: MULADD_IEEE R3.y, KC0[0].y, R1.x, R0.y 0156 00000072 80400000 TEX 1 @228 0228 00031211 f00d1003 84810000 SAMPLE_L R3.xyzw, R3.xyy0, RID:18, SID:2 CT:NNNN 0158 00000107 a40c0000 ALU_PUSH_BEFORE 4 @526 0526 800060fd 60800490 80 w: SETGT R4.w, [0x3f666666 0.9].x, R3.x 0528 3f666666 0530 801f0cfe 60800610 81 w: SETE_DX10 R4.w, PV.w, 0 0532 801f0cfe 00002104 82 M x: PRED_SETE_INT __.x, PV.w, 0 0160 00000052 82800000 JUMP @164 0162 0000010b a0040000 ALU 2 @534 0534 800000fd 60a00c90 83 w: MOV R5.w, [0x00000001 1.4013e-45].x 0536 00000001 0164 00000054 83400001 ELSE @168 POP:1 0166 0000010d a80c0000 ALU_POP_AFTER 4 @538 0538 800000fd 60a00c90 84 w: MOV R5.w, [0x00000000 0].x 0540 00000000 0542 801fa001 60800010 85 w: ADD R4.w, R1.x, [0x40000000 2].x 0544 40000000 0168 00000055 83800001 POP @170 POP:1 0170 00000111 a4100000 ALU_PUSH_BEFORE 5 @546 0546 801fac05 60a00b90 86 w: LSHL_INT R5.w, R5.w, [0x0000001f 4.34403e-44].x 0548 0000001f 0550 801facfe 60a00a90 87 w: ASHR_INT R5.w, PV.w, [0x0000001f 4.34403e-44].x 0552 0000001f 0554 801f0cfe 00002284 88 M x: PRED_SETNE_INT __.x, PV.w, 0 0172 00000059 82800001 JUMP @178 POP:1 0174 00000059 82400000 LOOP_BREAK @178 0176 00000059 83800001 POP @178 POP:1 0178 00000049 81400000 LOOP_END @146 0180 80000116 a0080000 ALU 3 @556 KC0[CB0:0-31] 0556 001fa080 00830000 89 x: MULADD_IEEE R4.x, KC0[0].x, [0xbe800000 -0.25].x, R0.x 0558 80900c01 20830400 y: MULADD_IEEE R4.y, R1.w, KC0[0].y, R0.y 0560 be800000 0182 00000074 80400000 TEX 1 @232 0232 00041211 f00d1005 84810000 SAMPLE_L R5.xyzw, R4.xyy0, RID:18, SID:2 CT:NNNN 0184 80000119 a0200000 ALU 9 @562 KC0[CB0:0-31] 0562 00006003 40200010 90 z: ADD R1.z, R3.x, R3.x 0564 801fa001 60680010 w: ADD R3.w, R1.x, [0xbfc00000 -1.5].x VEC_120 0566 bfc00000 0568 819fc8fe 60600010 91 w: ADD R3.w, PV.z, PV.w 0570 819fc0fd 60600210 92 w: MIN R3.w, [0x41800000 16].x, PV.w 0572 41800000 0574 801f2cfe 60c00010 93 w: ADD R6.w, PV.w, 1.0 0576 80900cfe 60030400 94 w: MULADD_IEEE R0.w, PV.w, KC0[0].y, R0.y 0578 80000cfe 20800c90 95 y: MOV R4.y, PV.w 0186 00000076 80400000 TEX 1 @236 0236 00041211 f00d1000 84810000 SAMPLE_L R0.xyzw, R4.xyy0, RID:18, SID:2 CT:NNNN 0188 00000122 a8380000 ALU_POP_AFTER 15 @580 0580 801fa405 60800110 96 w: MUL_IEEE R4.w, R5.y, [0x40800000 4].x 0582 40800000 0584 00000cfe 20200990 97 y: RNDNE R1.y, PV.w 0586 00000c01 40200c91 z: MOV R1.z, |R1.w| 0588 801fa400 60000110 w: MUL_IEEE R0.w, R0.y, [0x40800000 4].x 0590 40800000 0592 00000cfe 20000990 98 y: RNDNE R0.y, PV.w 0594 00000c03 40000c91 z: MOV R0.z, |R3.w| 0596 801fa4fe 600308fe w: MULADD_IEEE R0.w, PV.y, [0x42040000 33].x, PV.z 0598 42040000 0600 001facfe 00200110 99 x: MUL_IEEE R1.x, PV.w, [0x3bc7ce0a 0.00609756].x 0602 809fa4fe 600308fe w: MULADD_IEEE R0.w, PV.y, [0x42040000 33].y, PV.z 0604 3bc7ce0a 0605 42040000 0606 801facfe 20200110 100 y: MUL_IEEE R1.y, PV.w, [0x3bc7ce0a 0.00609756].x 0608 3bc7ce0a 0190 00000078 80400000 TEX 1 @240 0240 00011011 f00d1000 84800000 SAMPLE_L R0.xyzw, R1.xyy0, RID:16, SID:0 CT:NNNN 0192 00000131 a0040000 ALU 2 @610 0610 00000000 40400c90 101 z: MOV R2.z, R0.x 0612 80000400 60400c90 w: MOV R2.w, R0.y 0194 c0010000 95200688 EXPORT_DONE PIXEL 0 R2.xyzw 0196 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #84 OPT ==================================== PS/CAYMAN/CAYMAN ===== ===== 520 dw ===== 6 gprs ===== 2 stack ======================================== 0000 00000052 a00c0000 ALU 4 @164 0164 00380400 00946b10 1 x: INTERP_XY R4.x, R0.y, Param0.x VEC_210 0166 00b80000 20946b10 y: INTERP_XY R4.y, R0.x, Param0.y VEC_210 0168 01380400 40146b00 z: INTERP_XY __.z, R0.y, Param0.z VEC_210 0170 81b80000 60146b00 w: INTERP_XY __.w, R0.x, Param0.w VEC_210 0002 00000056 80400000 TEX 1 @172 0172 00041110 f00d1001 fc808000 SAMPLE R1.xyzw, R4.xy__, RID:17, SID:1 CT:NNNN 0004 00000058 a4000000 ALU_PUSH_BEFORE 1 @176 0176 801f0401 00001004 2 M x: PRED_SETE __.x, R1.y, 0 0006 00000005 82800000 JUMP @10 0008 00000059 a0040000 ALU 2 @178 0178 000000f8 00400c90 3 x: MOV R2.x, 0 0180 800000f8 20400c90 y: MOV R2.y, 0 0010 00000029 83400001 ELSE @82 POP:1 0012 4000005b a00c0000 ALU 4 @182 KC0[CB0:0-15] 0182 801f0401 20400590 4 y: SETNE R2.y, R1.y, 0 0184 000000fd 00000c90 5 x: MOV R0.x, [0xbfc00000 -1.5].x 0186 801f0480 20630404 y: MULADD_IEEE R3.y, KC0[0].y, 0, R4.y 0188 bfc00000 0014 00000015 81800000 LOOP_START_DX10 @42 0016 0000005f a4040000 ALU_PUSH_BEFORE 2 @190 0190 800000fd 00001104 6 M x: PRED_SETGE __.x, [0xc1800000 -16].x, R0.x 0192 c1800000 0018 0000000b 82800000 JUMP @22 0020 00000061 a0040000 ALU 2 @194 0194 000000fa 20000c90 7 y: MOV R0.y, 1 0196 80000000 40000c90 z: MOV R0.z, R0.x 0022 0000000f 83400001 ELSE @30 POP:1 0024 40000063 a0000000 ALU 1 @198 KC0[CB0:0-15] 0198 80000080 00630004 8 x: MULADD_IEEE R3.x, KC0[0].x, R0.x, R4.x 0026 00000064 80400000 TEX 1 @200 0200 00031211 f00d1002 84810000 SAMPLE_L R2.xyzw, R3.xyy0, RID:18, SID:2 CT:NNNN 0028 00000066 a8100000 ALU_POP_AFTER 5 @204 0204 001fa402 2f800710 9 y: SETGE_DX10 T0.y, R2.y, [0x3f666666 0.9].x 0206 809fa000 4f800010 z: ADD T0.z, R0.x, [0xc0000000 -2].y 0208 3f666666 0209 c0000000 0210 001f447c 200380f8 10 y: CNDE_INT R0.y, T0.y, 1, 0 0212 8000047c 4003887c z: CNDE_INT R0.z, T0.y, R0.x, T0.z 0030 0000006b a4100000 ALU_PUSH_BEFORE 5 @214 0214 801fa400 6f800b90 11 w: LSHL_INT T0.w, R0.y, [0x0000001f 4.34403e-44].x 0216 0000001f 0218 801fac7c 0f800a90 12 x: ASHR_INT T0.x, T0.w, [0x0000001f 4.34403e-44].x 0220 0000001f 0222 801f007c 00002284 13 M x: PRED_SETNE_INT __.x, T0.x, 0 0032 00000013 82800001 JUMP @38 POP:1 0034 00000014 82400000 LOOP_BREAK @40 0036 00000013 83800001 POP @38 POP:1 0038 00000070 a0000000 ALU 1 @224 0224 80000800 00000c90 14 x: MOV R0.x, R0.z 0040 00000008 81400000 LOOP_END @16 0042 00000071 a0100000 ALU 5 @226 0226 801fa000 20a00010 15 y: ADD R5.y, R0.x, [0x3fc00000 1.5].x 0228 3fc00000 0230 000000fd 00400c90 16 x: MOV R2.x, [0x3fc00000 1.5].x 0232 80000405 60000c90 w: MOV R0.w, R5.y 0234 3fc00000 0044 00000024 81800000 LOOP_START_DX10 @72 0046 00000076 a4040000 ALU_PUSH_BEFORE 2 @236 0236 801fa002 00001104 17 M x: PRED_SETGE __.x, R2.x, [0x41800000 16].x 0238 41800000 0048 0000001a 82800000 JUMP @52 0050 00000078 a00c0000 ALU 4 @240 0240 001fa002 20000510 18 y: SETGE R0.y, R2.x, [0x41800000 16].x 0242 000000fa 40400c90 z: MOV R2.z, 1 0244 80000002 60400c90 w: MOV R2.w, R2.x 0246 41800000 0052 0000001e 83400001 ELSE @60 POP:1 0054 4000007c a0000000 ALU 1 @248 KC0[CB0:0-15] 0248 80004080 00630004 19 x: MULADD_IEEE R3.x, KC0[0].x, R2.x, R4.x 0056 0000007e 80400000 TEX 1 @252 0252 00031211 f00d1000 84810000 SAMPLE_L R0.xyzw, R3.xyy0, RID:18, SID:2 CT:NNNN 0058 00000080 a8100000 ALU_POP_AFTER 5 @256 0256 001fa400 4f800710 20 z: SETGE_DX10 T0.z, R0.y, [0x3f666666 0.9].x 0258 809fa002 6f800010 w: ADD T0.w, R2.x, [0x40000000 2].y 0260 3f666666 0261 40000000 0262 001f487c 404380f8 21 z: CNDE_INT R2.z, T0.z, 1, 0 0264 8000487c 60438c7c w: CNDE_INT R2.w, T0.z, R2.x, T0.w 0060 00000085 a4100000 ALU_PUSH_BEFORE 5 @266 0266 801fa802 0f800b90 22 x: LSHL_INT T0.x, R2.z, [0x0000001f 4.34403e-44].x 0268 0000001f 0270 801fa07c 2f800a90 23 y: ASHR_INT T0.y, T0.x, [0x0000001f 4.34403e-44].x 0272 0000001f 0274 801f047c 00002284 24 M x: PRED_SETNE_INT __.x, T0.y, 0 0062 00000022 82800001 JUMP @68 POP:1 0064 00000023 82400000 LOOP_BREAK @70 0066 00000022 83800001 POP @68 POP:1 0068 0000008a a0000000 ALU 1 @276 0276 80000c02 00400c90 25 x: MOV R2.x, R2.w 0070 00000017 81400000 LOOP_END @46 0072 4000008b a0340000 ALU 14 @278 KC0[CB0:0-15] 0278 801fa002 4f800010 26 z: ADD T0.z, R2.x, [0xbfc00000 -1.5].x 0280 bfc00000 0282 801fa400 6f82887c 27 w: MULADD T0.w, R0.y, [0x40000000 2].x, T0.z 0284 40000000 0286 001fa402 0f830405 28 x: MULADD_IEEE T0.x, R2.y, [0xc0000000 -2].x, R5.y 0288 809fac7c 20400210 y: MIN R2.y, T0.w, [0x41800000 16].y 0290 c0000000 0291 41800000 0292 001fa07c 40400190 29 z: MAX R2.z, T0.x, [0xc1800000 -16].x 0294 801f2402 6f800010 w: ADD T0.w, R2.y, 1.0 0296 c1800000 0298 00100802 00030004 30 x: MULADD_IEEE R0.x, R2.z, KC0[0].x, R4.x 0300 001fa480 20030404 y: MULADD_IEEE R0.y, KC0[0].y, [0xbe800000 -0.25].x, R4.y 0302 80100c7c 40030004 z: MULADD_IEEE R0.z, T0.w, KC0[0].x, R4.x 0304 be800000 0074 0000009a 80400400 TEX 2 @308 0308 00001211 f01c7e00 84a10000 SAMPLE_L R0.__x_, R0.zyy0, RID:18, SID:2 CT:NNNN 0312 00001211 f01ff000 84810000 SAMPLE_L R0.x___, R0.xyy0, RID:18, SID:2 CT:NNNN 0076 0000009e a0300000 ALU 13 @316 0316 001fa800 0f800110 31 x: MUL_IEEE T0.x, R0.z, [0x40800000 4].x 0318 801fa000 2f800110 y: MUL_IEEE T0.y, R0.x, [0x40800000 4].x 0320 40800000 0322 00000802 0f800c91 32 x: MOV T0.x, |R2.z| 0324 0000007c 20000990 y: RNDNE R0.y, T0.x 0326 00000402 4f800c91 z: MOV T0.z, |R2.y| 0328 8000047c 6f880990 w: RNDNE T0.w, T0.y VEC_120 0330 001fa400 2f83087c 33 y: MULADD_IEEE T0.y, R0.y, [0x42040000 33].x, T0.z 0332 801fac7c 4f83007c z: MULADD_IEEE T0.z, T0.w, [0x42040000 33].x, T0.x 0334 42040000 0336 001fa87c 00000110 34 x: MUL_IEEE R0.x, T0.z, [0x3bc7ce0a 0.00609756].x 0338 801fa47c 40000110 z: MUL_IEEE R0.z, T0.y, [0x3bc7ce0a 0.00609756].x 0340 3bc7ce0a 0078 000000ac 80400000 TEX 1 @344 0344 00001011 f01f9002 89000000 SAMPLE_L R2.xy__, R0.xzz0, RID:16, SID:0 CT:NNNN 0080 00000029 83800001 POP @82 POP:1 0082 000000ae a4000000 ALU_PUSH_BEFORE 1 @348 0348 801f0001 00001004 35 M x: PRED_SETE __.x, R1.x, 0 0084 0000002c 82800000 JUMP @88 0086 000000af a0040000 ALU 2 @350 0350 000000f8 40400c90 36 z: MOV R2.z, 0 0352 800000f8 60400c90 w: MOV R2.w, 0 0088 00000050 83400001 ELSE @160 POP:1 0090 400000b1 a0080000 ALU 3 @354 KC0[CB0:0-15] 0354 000000fd 00000c90 37 x: MOV R0.x, [0xbfc00000 -1.5].x 0356 801f0080 40430004 z: MULADD_IEEE R2.z, KC0[0].x, 0, R4.x 0358 bfc00000 0092 0000003c 81800000 LOOP_START_DX10 @120 0094 000000b4 a4040000 ALU_PUSH_BEFORE 2 @360 0360 800000fd 00001104 38 M x: PRED_SETGE __.x, [0xc1800000 -16].x, R0.x 0362 c1800000 0096 00000032 82800000 JUMP @100 0098 000000b6 a0040000 ALU 2 @364 0364 00000000 40000c90 39 z: MOV R0.z, R0.x 0366 800000fa 60000c90 w: MOV R0.w, 1 0100 00000036 83400001 ELSE @108 POP:1 0102 400000b8 a0000000 ALU 1 @368 KC0[CB0:0-15] 0368 80000480 60430404 40 w: MULADD_IEEE R2.w, KC0[0].y, R0.x, R4.y 0104 000000ba 80400000 TEX 1 @372 0372 00021211 f00d1001 8da10000 SAMPLE_L R1.xyzw, R2.zww0, RID:18, SID:2 CT:NNNN 0106 000000bc a8100000 ALU_POP_AFTER 5 @376 0376 001fa000 0f800010 41 x: ADD T0.x, R0.x, [0xc0000000 -2].x 0378 809fa001 6f880710 w: SETGE_DX10 T0.w, R1.x, [0x3f666666 0.9].y VEC_120 0380 c0000000 0381 3f666666 0382 00000c7c 4003807c 42 z: CNDE_INT R0.z, T0.w, R0.x, T0.x 0384 801f4c7c 600380f8 w: CNDE_INT R0.w, T0.w, 1, 0 0108 000000c1 a4100000 ALU_PUSH_BEFORE 5 @386 0386 801fac00 2f800b90 43 y: LSHL_INT T0.y, R0.w, [0x0000001f 4.34403e-44].x 0388 0000001f 0390 801fa47c 4f800a90 44 z: ASHR_INT T0.z, T0.y, [0x0000001f 4.34403e-44].x 0392 0000001f 0394 801f087c 00002284 45 M x: PRED_SETNE_INT __.x, T0.z, 0 0110 0000003a 82800001 JUMP @116 POP:1 0112 0000003b 82400000 LOOP_BREAK @118 0114 0000003a 83800001 POP @116 POP:1 0116 000000c6 a0000000 ALU 1 @396 0396 80000800 00000c90 46 x: MOV R0.x, R0.z 0118 0000002f 81400000 LOOP_END @94 0120 000000c7 a0200000 ALU 9 @398 0398 801fa000 60000010 47 w: ADD R0.w, R0.x, [0x3fc00000 1.5].x 0400 3fc00000 0402 801fa001 6f830c00 48 w: MULADD_IEEE T0.w, R1.x, [0xc0000000 -2].x, R0.w 0404 c0000000 0406 801fac7c 00600190 49 x: MAX R3.x, T0.w, [0xc1800000 -16].x 0408 c1800000 0410 800000fd 00200c90 50 x: MOV R1.x, [0x3fc00000 1.5].x 0412 3fc00000 0414 80000003 00000c90 51 x: MOV R0.x, R3.x 0122 0000004b 81800000 LOOP_START_DX10 @150 0124 000000d0 a4040000 ALU_PUSH_BEFORE 2 @416 0416 801fa001 00001104 52 M x: PRED_SETGE __.x, R1.x, [0x41800000 16].x 0418 41800000 0126 00000041 82800000 JUMP @130 0128 000000d2 a0080000 ALU 3 @420 0420 000000fa 20200c90 53 y: MOV R1.y, 1 0422 800020fd 40200690 z: SETGT_DX10 R1.z, [0x41800000 16].x, R1.x 0424 41800000 0130 00000045 83400001 ELSE @138 POP:1 0132 400000d5 a0000000 ALU 1 @426 KC0[CB0:0-15] 0426 80002480 60430404 54 w: MULADD_IEEE R2.w, KC0[0].y, R1.x, R4.y 0134 000000d6 80400000 TEX 1 @428 0428 00021211 f00d1000 8da10000 SAMPLE_L R0.xyzw, R2.zww0, RID:18, SID:2 CT:NNNN 0136 000000d8 a8100000 ALU_POP_AFTER 5 @432 0432 001fa000 2f800710 55 y: SETGE_DX10 T0.y, R0.x, [0x3f666666 0.9].x 0434 809fa001 4f880010 z: ADD T0.z, R1.x, [0x40000000 2].y VEC_120 0436 3f666666 0437 40000000 0438 001f447c 202380f8 56 y: CNDE_INT R1.y, T0.y, 1, 0 0440 808f847c 4023887c z: CNDE_INT R1.z, T0.y, T0.y, T0.z 0138 000000dd a4100000 ALU_PUSH_BEFORE 5 @442 0442 801fa401 6f800b90 57 w: LSHL_INT T0.w, R1.y, [0x0000001f 4.34403e-44].x 0444 0000001f 0446 801fac7c 0f800a90 58 x: ASHR_INT T0.x, T0.w, [0x0000001f 4.34403e-44].x 0448 0000001f 0450 801f007c 00002284 59 M x: PRED_SETNE_INT __.x, T0.x, 0 0140 00000049 82800001 JUMP @146 POP:1 0142 0000004a 82400000 LOOP_BREAK @148 0144 00000049 83800001 POP @146 POP:1 0146 000000e2 a0000000 ALU 1 @452 0452 80000801 00200c90 60 x: MOV R1.x, R1.z 0148 0000003e 81400000 LOOP_END @124 0150 400000e3 a0280000 ALU 11 @454 KC0[CB0:0-15] 0454 801fa001 2f800010 61 y: ADD T0.y, R1.x, [0xbfc00000 -1.5].x 0456 bfc00000 0458 801fa000 4f82847c 62 z: MULADD T0.z, R0.x, [0x40000000 2].x, T0.y 0460 40000000 0462 801fa87c 60000210 63 w: MIN R0.w, T0.z, [0x41800000 16].x 0464 41800000 0466 801f2c00 0f800010 64 x: ADD T0.x, R0.w, 1.0 0468 001fa080 00030004 65 x: MULADD_IEEE R0.x, KC0[0].x, [0xbe800000 -0.25].x, R4.x 0470 0090007c 20030404 y: MULADD_IEEE R0.y, T0.x, KC0[0].y, R4.y 0472 80900003 400b0404 z: MULADD_IEEE R0.z, R3.x, KC0[0].y, R4.y VEC_120 0474 be800000 0152 000000ee 80400400 TEX 2 @476 0476 00001211 f01f9e00 84810000 SAMPLE_L R0._y__, R0.xyy0, RID:18, SID:2 CT:NNNN 0480 00001211 f01ff200 89010000 SAMPLE_L R0.y___, R0.xzz0, RID:18, SID:2 CT:NNNN 0154 000000f2 a0300000 ALU 13 @484 0484 001fa400 2f800110 66 y: MUL_IEEE T0.y, R0.y, [0x40800000 4].x 0486 801fa000 4f800110 z: MUL_IEEE T0.z, R0.x, [0x40800000 4].x 0488 40800000 0490 00000c00 0f800c91 67 x: MOV T0.x, |R0.w| 0492 0000087c 2f800990 y: RNDNE T0.y, T0.z 0494 00000003 4f800c91 z: MOV T0.z, |R3.x| 0496 8000047c 6f800990 w: RNDNE T0.w, T0.y 0498 001fa47c 0f83087c 68 x: MULADD_IEEE T0.x, T0.y, [0x42040000 33].x, T0.z 0500 801fac7c 6f83007c w: MULADD_IEEE T0.w, T0.w, [0x42040000 33].x, T0.x 0502 42040000 0504 001fa07c 00000110 69 x: MUL_IEEE R0.x, T0.x, [0x3bc7ce0a 0.00609756].x 0506 801fac7c 20000110 y: MUL_IEEE R0.y, T0.w, [0x3bc7ce0a 0.00609756].x 0508 3bc7ce0a 0156 00000100 80400000 TEX 1 @512 0512 00001011 f01f9000 84800000 SAMPLE_L R0.xy__, R0.xyy0, RID:16, SID:0 CT:NNNN 0158 00000102 a8040000 ALU_POP_AFTER 2 @516 0516 00000000 40400c90 70 z: MOV R2.z, R0.x 0518 80000400 60400c90 w: MOV R2.w, R0.y 0160 c0010000 95000688 EXPORT_DONE PIXEL 0 R2.xyzw 0162 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], PERSPECTIVE DCL IN[1], GENERIC[10], PERSPECTIVE DCL IN[2], GENERIC[11], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL SAMP[1] DCL TEMP[0..8] IMM[0] FLT32 { 1.0000, 0.0000, 0.0000, 0.0000} 0: TEX TEMP[0], IN[0].xyyy, SAMP[1], 2D 1: MOV TEMP[1].x, TEMP[0].xxxx 2: TEX TEMP[2].y, IN[2].zwww, SAMP[1], 2D 3: MOV TEMP[1].y, TEMP[2].yyyy 4: MOV TEMP[1].z, TEMP[0].zzzz 5: TEX TEMP[1].w, IN[2].xyyy, SAMP[1], 2D 6: MUL TEMP[4], TEMP[1], TEMP[1] 7: MUL TEMP[5], TEMP[4], TEMP[1] 8: DP4 TEMP[1].x, TEMP[5], IMM[0].xxxx 9: SLT TEMP[4].x, TEMP[1].xxxx, IMM[0].yyyy 10: IF TEMP[4].xxxx :12 11: KILL 12: ENDIF 13: TEX TEMP[4], IN[0].xyyy, SAMP[0], 2D 14: TEX TEMP[6], IN[1].zwww, SAMP[0], 2D 15: ADD TEMP[7].x, IMM[0].xxxx, -TEMP[0].xxxx 16: MUL TEMP[8], TEMP[4], TEMP[7].xxxx 17: MAD TEMP[7], TEMP[6], TEMP[0].xxxx, TEMP[8] 18: MUL TEMP[6], TEMP[7], TEMP[5].xxxx 19: TEX TEMP[7], IN[2].zwww, SAMP[0], 2D 20: ADD TEMP[8].x, IMM[0].xxxx, -TEMP[2].yyyy 21: MUL TEMP[3], TEMP[4], TEMP[8].xxxx 22: MAD TEMP[8], TEMP[7], TEMP[2].yyyy, TEMP[3] 23: MAD TEMP[2], TEMP[8], TEMP[5].yyyy, TEMP[6] 24: TEX TEMP[6], IN[1].xyyy, SAMP[0], 2D 25: ADD TEMP[7].x, IMM[0].xxxx, -TEMP[0].zzzz 26: MUL TEMP[8], TEMP[4], TEMP[7].xxxx 27: MAD TEMP[7], TEMP[6], TEMP[0].zzzz, TEMP[8] 28: MAD TEMP[0], TEMP[7], TEMP[5].zzzz, TEMP[2] 29: TEX TEMP[2], IN[2].xyyy, SAMP[0], 2D 30: ADD TEMP[6].x, IMM[0].xxxx, -TEMP[1].wwww 31: MUL TEMP[7], TEMP[4], TEMP[6].xxxx 32: MAD TEMP[4], TEMP[2], TEMP[1].wwww, TEMP[7] 33: MAD TEMP[2], TEMP[4], TEMP[5].wwww, TEMP[0] 34: RCP TEMP[0].x, TEMP[1].xxxx 35: MUL OUT[0], TEMP[2], TEMP[0].xxxx 36: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg, <4 x float> inreg, <4 x float> inreg) #0 { main_body: %4 = extractelement <4 x float> %0, i32 0 %5 = extractelement <4 x float> %0, i32 1 %6 = call <2 x float> @llvm.R600.interp.xy(i32 0, float %4, float %5) %7 = call <2 x float> @llvm.R600.interp.zw(i32 0, float %4, float %5) %8 = shufflevector <2 x float> %6, <2 x float> %7, <4 x i32> %9 = extractelement <4 x float> %8, i32 0 %10 = extractelement <4 x float> %8, i32 1 %11 = extractelement <4 x float> %0, i32 0 %12 = extractelement <4 x float> %0, i32 1 %13 = call <2 x float> @llvm.R600.interp.xy(i32 1, float %11, float %12) %14 = call <2 x float> @llvm.R600.interp.zw(i32 1, float %11, float %12) %15 = shufflevector <2 x float> %13, <2 x float> %14, <4 x i32> %16 = extractelement <4 x float> %15, i32 0 %17 = extractelement <4 x float> %15, i32 1 %18 = extractelement <4 x float> %15, i32 2 %19 = extractelement <4 x float> %15, i32 3 %20 = extractelement <4 x float> %0, i32 0 %21 = extractelement <4 x float> %0, i32 1 %22 = call <2 x float> @llvm.R600.interp.xy(i32 2, float %20, float %21) %23 = call <2 x float> @llvm.R600.interp.zw(i32 2, float %20, float %21) %24 = shufflevector <2 x float> %22, <2 x float> %23, <4 x i32> %25 = extractelement <4 x float> %24, i32 0 %26 = extractelement <4 x float> %24, i32 1 %27 = extractelement <4 x float> %24, i32 2 %28 = extractelement <4 x float> %24, i32 3 %29 = insertelement <4 x float> undef, float %9, i32 0 %30 = insertelement <4 x float> %29, float %10, i32 1 %31 = insertelement <4 x float> %30, float %10, i32 2 %32 = insertelement <4 x float> %31, float %10, i32 3 %33 = extractelement <4 x float> %32, i32 0 %34 = extractelement <4 x float> %32, i32 1 %35 = insertelement <4 x float> undef, float %33, i32 0 %36 = insertelement <4 x float> %35, float %34, i32 1 %37 = insertelement <4 x float> %36, float undef, i32 2 %38 = insertelement <4 x float> %37, float undef, i32 3 %39 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %38, i32 17, i32 1, i32 2) %40 = extractelement <4 x float> %39, i32 0 %41 = extractelement <4 x float> %39, i32 2 %42 = insertelement <4 x float> undef, float %27, i32 0 %43 = insertelement <4 x float> %42, float %28, i32 1 %44 = insertelement <4 x float> %43, float %28, i32 2 %45 = insertelement <4 x float> %44, float %28, i32 3 %46 = extractelement <4 x float> %45, i32 0 %47 = extractelement <4 x float> %45, i32 1 %48 = insertelement <4 x float> undef, float %46, i32 0 %49 = insertelement <4 x float> %48, float %47, i32 1 %50 = insertelement <4 x float> %49, float undef, i32 2 %51 = insertelement <4 x float> %50, float undef, i32 3 %52 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %51, i32 17, i32 1, i32 2) %53 = extractelement <4 x float> %52, i32 1 %54 = insertelement <4 x float> undef, float %25, i32 0 %55 = insertelement <4 x float> %54, float %26, i32 1 %56 = insertelement <4 x float> %55, float %26, i32 2 %57 = insertelement <4 x float> %56, float %26, i32 3 %58 = extractelement <4 x float> %57, i32 0 %59 = extractelement <4 x float> %57, i32 1 %60 = insertelement <4 x float> undef, float %58, i32 0 %61 = insertelement <4 x float> %60, float %59, i32 1 %62 = insertelement <4 x float> %61, float undef, i32 2 %63 = insertelement <4 x float> %62, float undef, i32 3 %64 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %63, i32 17, i32 1, i32 2) %65 = extractelement <4 x float> %64, i32 3 %66 = fmul float %40, %40 %67 = fmul float %53, %53 %68 = fmul float %41, %41 %69 = fmul float %65, %65 %70 = fmul float %66, %40 %71 = fmul float %67, %53 %72 = fmul float %68, %41 %73 = fmul float %69, %65 %74 = insertelement <4 x float> undef, float %70, i32 0 %75 = insertelement <4 x float> %74, float %71, i32 1 %76 = insertelement <4 x float> %75, float %72, i32 2 %77 = insertelement <4 x float> %76, float %73, i32 3 %78 = call float @llvm.AMDGPU.dp4(<4 x float> %77, <4 x float> ) %79 = fcmp olt float %78, 0x3EE4F8B580000000 %80 = select i1 %79, float 1.000000e+00, float 0.000000e+00 %81 = fcmp une float %80, 0.000000e+00 br i1 %81, label %IF, label %ENDIF IF: ; preds = %main_body call void @llvm.AMDGPU.kilp() br label %ENDIF ENDIF: ; preds = %main_body, %IF %82 = insertelement <4 x float> undef, float %9, i32 0 %83 = insertelement <4 x float> %82, float %10, i32 1 %84 = insertelement <4 x float> %83, float %10, i32 2 %85 = insertelement <4 x float> %84, float %10, i32 3 %86 = extractelement <4 x float> %85, i32 0 %87 = extractelement <4 x float> %85, i32 1 %88 = insertelement <4 x float> undef, float %86, i32 0 %89 = insertelement <4 x float> %88, float %87, i32 1 %90 = insertelement <4 x float> %89, float undef, i32 2 %91 = insertelement <4 x float> %90, float undef, i32 3 %92 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %91, i32 16, i32 0, i32 2) %93 = extractelement <4 x float> %92, i32 0 %94 = extractelement <4 x float> %92, i32 1 %95 = extractelement <4 x float> %92, i32 2 %96 = extractelement <4 x float> %92, i32 3 %97 = insertelement <4 x float> undef, float %18, i32 0 %98 = insertelement <4 x float> %97, float %19, i32 1 %99 = insertelement <4 x float> %98, float %19, i32 2 %100 = insertelement <4 x float> %99, float %19, i32 3 %101 = extractelement <4 x float> %100, i32 0 %102 = extractelement <4 x float> %100, i32 1 %103 = insertelement <4 x float> undef, float %101, i32 0 %104 = insertelement <4 x float> %103, float %102, i32 1 %105 = insertelement <4 x float> %104, float undef, i32 2 %106 = insertelement <4 x float> %105, float undef, i32 3 %107 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %106, i32 16, i32 0, i32 2) %108 = extractelement <4 x float> %107, i32 0 %109 = extractelement <4 x float> %107, i32 1 %110 = extractelement <4 x float> %107, i32 2 %111 = extractelement <4 x float> %107, i32 3 %112 = fsub float -0.000000e+00, %40 %113 = fadd float 1.000000e+00, %112 %114 = fmul float %93, %113 %115 = fmul float %94, %113 %116 = fmul float %95, %113 %117 = fmul float %96, %113 %118 = fmul float %108, %40 %119 = fadd float %118, %114 %120 = fmul float %109, %40 %121 = fadd float %120, %115 %122 = fmul float %110, %40 %123 = fadd float %122, %116 %124 = fmul float %111, %40 %125 = fadd float %124, %117 %126 = fmul float %119, %70 %127 = fmul float %121, %70 %128 = fmul float %123, %70 %129 = fmul float %125, %70 %130 = insertelement <4 x float> undef, float %27, i32 0 %131 = insertelement <4 x float> %130, float %28, i32 1 %132 = insertelement <4 x float> %131, float %28, i32 2 %133 = insertelement <4 x float> %132, float %28, i32 3 %134 = extractelement <4 x float> %133, i32 0 %135 = extractelement <4 x float> %133, i32 1 %136 = insertelement <4 x float> undef, float %134, i32 0 %137 = insertelement <4 x float> %136, float %135, i32 1 %138 = insertelement <4 x float> %137, float undef, i32 2 %139 = insertelement <4 x float> %138, float undef, i32 3 %140 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %139, i32 16, i32 0, i32 2) %141 = extractelement <4 x float> %140, i32 0 %142 = extractelement <4 x float> %140, i32 1 %143 = extractelement <4 x float> %140, i32 2 %144 = extractelement <4 x float> %140, i32 3 %145 = fsub float -0.000000e+00, %53 %146 = fadd float 1.000000e+00, %145 %147 = fmul float %93, %146 %148 = fmul float %94, %146 %149 = fmul float %95, %146 %150 = fmul float %96, %146 %151 = fmul float %141, %53 %152 = fadd float %151, %147 %153 = fmul float %142, %53 %154 = fadd float %153, %148 %155 = fmul float %143, %53 %156 = fadd float %155, %149 %157 = fmul float %144, %53 %158 = fadd float %157, %150 %159 = fmul float %152, %71 %160 = fadd float %159, %126 %161 = fmul float %154, %71 %162 = fadd float %161, %127 %163 = fmul float %156, %71 %164 = fadd float %163, %128 %165 = fmul float %158, %71 %166 = fadd float %165, %129 %167 = insertelement <4 x float> undef, float %16, i32 0 %168 = insertelement <4 x float> %167, float %17, i32 1 %169 = insertelement <4 x float> %168, float %17, i32 2 %170 = insertelement <4 x float> %169, float %17, i32 3 %171 = extractelement <4 x float> %170, i32 0 %172 = extractelement <4 x float> %170, i32 1 %173 = insertelement <4 x float> undef, float %171, i32 0 %174 = insertelement <4 x float> %173, float %172, i32 1 %175 = insertelement <4 x float> %174, float undef, i32 2 %176 = insertelement <4 x float> %175, float undef, i32 3 %177 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %176, i32 16, i32 0, i32 2) %178 = extractelement <4 x float> %177, i32 0 %179 = extractelement <4 x float> %177, i32 1 %180 = extractelement <4 x float> %177, i32 2 %181 = extractelement <4 x float> %177, i32 3 %182 = fsub float -0.000000e+00, %41 %183 = fadd float 1.000000e+00, %182 %184 = fmul float %93, %183 %185 = fmul float %94, %183 %186 = fmul float %95, %183 %187 = fmul float %96, %183 %188 = fmul float %178, %41 %189 = fadd float %188, %184 %190 = fmul float %179, %41 %191 = fadd float %190, %185 %192 = fmul float %180, %41 %193 = fadd float %192, %186 %194 = fmul float %181, %41 %195 = fadd float %194, %187 %196 = fmul float %189, %72 %197 = fadd float %196, %160 %198 = fmul float %191, %72 %199 = fadd float %198, %162 %200 = fmul float %193, %72 %201 = fadd float %200, %164 %202 = fmul float %195, %72 %203 = fadd float %202, %166 %204 = insertelement <4 x float> undef, float %25, i32 0 %205 = insertelement <4 x float> %204, float %26, i32 1 %206 = insertelement <4 x float> %205, float %26, i32 2 %207 = insertelement <4 x float> %206, float %26, i32 3 %208 = extractelement <4 x float> %207, i32 0 %209 = extractelement <4 x float> %207, i32 1 %210 = insertelement <4 x float> undef, float %208, i32 0 %211 = insertelement <4 x float> %210, float %209, i32 1 %212 = insertelement <4 x float> %211, float undef, i32 2 %213 = insertelement <4 x float> %212, float undef, i32 3 %214 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %213, i32 16, i32 0, i32 2) %215 = extractelement <4 x float> %214, i32 0 %216 = extractelement <4 x float> %214, i32 1 %217 = extractelement <4 x float> %214, i32 2 %218 = extractelement <4 x float> %214, i32 3 %219 = fsub float -0.000000e+00, %65 %220 = fadd float 1.000000e+00, %219 %221 = fmul float %93, %220 %222 = fmul float %94, %220 %223 = fmul float %95, %220 %224 = fmul float %96, %220 %225 = fmul float %215, %65 %226 = fadd float %225, %221 %227 = fmul float %216, %65 %228 = fadd float %227, %222 %229 = fmul float %217, %65 %230 = fadd float %229, %223 %231 = fmul float %218, %65 %232 = fadd float %231, %224 %233 = fmul float %226, %73 %234 = fadd float %233, %197 %235 = fmul float %228, %73 %236 = fadd float %235, %199 %237 = fmul float %230, %73 %238 = fadd float %237, %201 %239 = fmul float %232, %73 %240 = fadd float %239, %203 %241 = fdiv float 1.000000e+00, %78 %242 = fmul float %234, %241 %243 = fmul float %236, %241 %244 = fmul float %238, %241 %245 = fmul float %240, %241 %246 = insertelement <4 x float> undef, float %242, i32 0 %247 = insertelement <4 x float> %246, float %243, i32 1 %248 = insertelement <4 x float> %247, float %244, i32 2 %249 = insertelement <4 x float> %248, float %245, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %249, i32 0, i32 0) ret void } ; Function Attrs: readnone declare <2 x float> @llvm.R600.interp.xy(i32, float, float) #1 ; Function Attrs: readnone declare <2 x float> @llvm.R600.interp.zw(i32, float, float) #1 ; Function Attrs: readnone declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32, i32) #1 ; Function Attrs: readnone declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1 declare void @llvm.AMDGPU.kilp() declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } Shader Disassembly: ALU 21, @26, KC0[], KC1[] ; 0000001A A0540000 TEX 2 @10 ; 0000000A 80400800 ALU_PUSH_BEFORE 15, @48, KC0[], KC1[] ; 00000030 A43C0000 JUMP @5 POP:1 ; 00000005 82800001 ALU_POP_AFTER 0, @64, KC0[], KC1[] ; 00000040 A8000000 ALU 3, @65, KC0[], KC1[] ; 00000041 A00C0000 TEX 4 @16 ; 00000010 80401000 ALU 59, @69, KC0[], KC1[] ; 00000045 A0EC0000 EXPORT T4.XYZW ; C0020000 95200688 CF_END ; 00000000 88000000 Fetch clause starting at 10: ; TEX_SAMPLE T2.XYZW, T0.XY__ RID:17 SID:1 CT:NNNN ; 00001110 F00D1002 FC808000 00000000 TEX_SAMPLE T0.XYZW, T4.XY__ RID:17 SID:1 CT:NNNN ; 00041110 F00D1000 FC808000 00000000 TEX_SAMPLE T1.XYZW, T7.XY__ RID:17 SID:1 CT:NNNN ; 00071110 F00D1001 FC808000 00000000 Fetch clause starting at 16: ; TEX_SAMPLE T7.XYZW, T7.XY__ RID:16 SID:0 CT:NNNN ; 00071010 F00D1007 FC800000 00000000 TEX_SAMPLE T6.XYZW, T6.XY__ RID:16 SID:0 CT:NNNN ; 00061010 F00D1006 FC800000 00000000 TEX_SAMPLE T8.XYZW, T10.XY__ RID:16 SID:0 CT:NNNN ; 000A1010 F00D1008 FC800000 00000000 TEX_SAMPLE T9.XYZW, T9.XY__ RID:16 SID:0 CT:NNNN ; 00091010 F00D1009 FC800000 00000000 TEX_SAMPLE T4.XYZW, T4.XY__ RID:16 SID:0 CT:NNNN ; 00041010 F00D1004 FC800000 00000000 ALU clause starting at 26: ; INTERP_XY T4.X, T0.Y, ARRAY_BASE, ; 00380400 00946B10 INTERP_XY T4.Y, T0.X, ARRAY_BASE, ; 00380000 20946B10 INTERP_XY T0.Z (MASKED), T0.Y, ARRAY_BASE, ; 00380400 40146B00 INTERP_XY * T0.W (MASKED), T0.X, ARRAY_BASE, ; 80380000 60146B00 INTERP_XY T6.X, T0.Y, ARRAY_BASE, ; 00382400 00D46B10 INTERP_XY T6.Y, T0.X, ARRAY_BASE, ; 00382000 20D46B10 INTERP_XY T0.Z (MASKED), T0.Y, ARRAY_BASE, ; 00382400 40146B00 INTERP_XY * T0.W (MASKED), T0.X, ARRAY_BASE, ; 80382000 60146B00 INTERP_ZW T0.X (MASKED), T0.Y, ARRAY_BASE, ; 00382400 00146B80 INTERP_ZW T0.Y (MASKED), T0.X, ARRAY_BASE, ; 00382000 20146B80 INTERP_ZW T8.Z, T0.Y, ARRAY_BASE, ; 00382400 41146B90 INTERP_ZW * T5.W, T0.X, ARRAY_BASE, ; 80382000 60B46B90 INTERP_XY T7.X, T0.Y, ARRAY_BASE, ; 00384400 00F46B10 INTERP_XY T7.Y, T0.X, ARRAY_BASE, ; 00384000 20F46B10 INTERP_XY T0.Z (MASKED), T0.Y, ARRAY_BASE, ; 00384400 40146B00 INTERP_XY * T0.W (MASKED), T0.X, ARRAY_BASE, ; 80384000 60146B00 INTERP_ZW T0.X (MASKED), T0.Y, ARRAY_BASE, ; 00384400 00146B80 INTERP_ZW T0.Y (MASKED), T0.X, ARRAY_BASE, ; 00384000 20146B80 INTERP_ZW T5.Z, T0.Y, ARRAY_BASE, ; 00384400 40B46B90 INTERP_ZW * T8.W, T0.X, ARRAY_BASE, ; 80384000 61146B90 MOV T0.X, PV.Z, ; 000008FE 00000C90 MOV * T0.Y, PV.W, ; 80000CFE 20000C90 ALU clause starting at 48: ; MUL_IEEE T3.X, T1.W, T1.W, ; 01802C01 00600110 MUL_IEEE T5.Y, T0.Z, T0.Z, ; 01000800 20A00110 MUL_IEEE T3.Z, T2.Y, T2.Y, ; 00804402 40600110 MUL_IEEE * T3.W, T0.X, T0.X, ; 80000000 60600110 MUL_IEEE T5.X, PV.W, T0.X, ; 00000CFE 00A00110 MUL_IEEE T3.Y, PV.Z, T2.Y, ; 008048FE 20600110 MUL_IEEE T3.Z, PV.Y, T0.Z, ; 010004FE 40600110 MUL_IEEE * T3.W, PV.X, T1.W, ; 818020FE 60600110 DOT4 T3.X, T5.X, 1.0, ; 001F2005 00605F10 DOT4 T3.Y (MASKED), T3.Y, 1.0, ; 001F2403 20605F00 DOT4 T3.Z (MASKED), T3.Z, 1.0, ; 001F2803 40605F00 DOT4 * T3.W (MASKED), T3.W, 1.0, ; 801F2C03 60605F00 SETGT * T9.W, literal.x, PV.X, ; 801FC0FD 61200490 925353388(1.000000e-05), 0(0.000000e+00) ; 3727C5AC 00000000 SETE_DX10 * T9.W, PV.W, 0.0, ; 801F0CFE 61200610 PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002104 ALU clause starting at 64: ; KILLGT * T5.Y (MASKED), 1.0, 0.0, ; 801F00F9 20A01680 ALU clause starting at 65: ; MOV * T9.X, T8.Z, ; 80000808 01200C90 MOV T10.X, T5.Z, ; 00000805 01400C90 MOV * T9.Y, T5.W, ; 80000C05 21200C90 MOV * T10.Y, T8.W, ; 80000C08 21400C90 ALU clause starting at 69: ; ADD * T5.W, -T0.X, 1.0, ; 801F3000 60A00010 MUL_IEEE T5.Z, T4.Z, PV.W, ; 019FC804 40A00110 ADD * T10.W, -T2.Y, 1.0, ; 801F3402 61400010 MUL_IEEE T5.Y, T4.Z, PV.W, ; 019FC804 20A00110 MULADD_IEEE T5.Z, T9.Z, T0.X, PV.Z, BS:VEC_120/SCL_212 ; 00000809 40AB08FE ADD * T11.W, -T0.Z, 1.0, BS:VEC_201 ; 801F3800 61700010 MUL_IEEE T10.X, T4.Z, PV.W, ; 019FC804 01400110 MUL_IEEE T10.Y, PV.Z, T5.X, ; 0000A8FE 21400110 MULADD_IEEE T5.Z, T8.Z, T2.Y, PV.Y, BS:VEC_120/SCL_212 ; 00804808 40AB04FE ADD * T12.W, -T1.W, 1.0, ; 801F3C01 61800010 MUL_IEEE T5.Y, T4.Z, PV.W, ; 019FC804 20A00110 MULADD_IEEE T5.Z, PV.Z, T3.Y, PV.Y, ; 008068FE 40A304FE MULADD_IEEE * T13.W, T6.Z, T0.Z, PV.X, BS:VEC_120/SCL_212 ; 81000806 61AB00FE MULADD_IEEE T10.X, PV.W, T3.Z, PV.Z, ; 01006CFE 014308FE MULADD_IEEE T5.Y, T7.Z, T1.W, PV.Y, ; 01802807 20A304FE MUL_IEEE * T5.Z, T4.W, T12.W, BS:VEC_021/SCL_122 ; 81818C04 40A40110 MUL_IEEE * T13.W, T4.X, T5.W, ; 8180A004 61A00110 MUL_IEEE T11.X, T4.W, T11.W, ; 01816C04 01600110 MUL_IEEE * T10.Y, T4.W, T5.W, BS:VEC_021/SCL_122 ; 8180AC04 21440110 MUL_IEEE T10.Z, T4.X, T10.W, ; 01814004 41400110 MULADD_IEEE * T13.W, T9.X, T0.X, T13.W, BS:VEC_120/SCL_212 ; 80000009 61AB0C0D MUL_IEEE T12.X, T4.X, T11.W, ; 01816004 01800110 MUL_IEEE T11.Y, PV.W, T5.X, ; 0000ACFE 21600110 MULADD_IEEE * T10.Z, T8.X, T2.Y, PV.Z, BS:VEC_201 ; 80804008 415308FE MULADD_IEEE * T13.W, T9.W, T0.X, T10.Y, ; 80000C09 61A3040A MUL_IEEE T13.X, PV.W, T5.X, ; 0000ACFE 01A00110 MUL_IEEE T10.Y, T4.Y, T5.W, ; 0180A404 21400110 MULADD_IEEE T10.Z, T10.Z, T3.Y, T11.Y, ; 0080680A 4143040B MULADD_IEEE * T5.W, T6.X, T0.Z, T12.X, ; 81000006 60A3000C MULADD_IEEE T12.X, PV.W, T3.Z, PV.Z, ; 01006CFE 018308FE MUL_IEEE T11.Y, T4.Y, T10.W, ; 01814404 21600110 MULADD_IEEE T9.Z, T9.Y, T0.X, PV.Y, BS:VEC_120/SCL_212 ; 00000409 412B04FE MUL_IEEE * T5.W, T4.X, T12.W, BS:VEC_021/SCL_122 ; 81818004 60A40110 MULADD_IEEE T9.X, T7.X, T1.W, PV.W, ; 01802007 01230CFE MUL_IEEE T9.Y, T4.Y, T11.W, BS:VEC_021/SCL_122 ; 01816404 21240110 MUL_IEEE T9.Z, PV.Z, T5.X, ; 0000A8FE 41200110 MULADD_IEEE * T5.W, T8.Y, T2.Y, PV.Y, BS:VEC_120/SCL_212 ; 80804408 60AB04FE MUL_IEEE T5.X, T4.Y, T12.W, ; 01818404 00A00110 MULADD_IEEE T10.Y, PV.W, T3.Y, PV.Z, ; 00806CFE 214308FE MULADD_IEEE T9.Z, T6.Y, T0.Z, PV.Y, BS:VEC_201 ; 01000406 413304FE MUL_IEEE * T4.W, T4.W, T10.W, BS:VEC_021/SCL_122 ; 81814C04 60840110 MULADD_IEEE T2.X, T8.W, T2.Y, PV.W, ; 00804C08 00430CFE MULADD_IEEE T2.Y, PV.Z, T3.Z, PV.Y, ; 010068FE 204304FE MULADD_IEEE T2.Z, T7.Y, T1.W, PV.X, ; 01802407 404300FE MULADD_IEEE * T2.W, T9.X, T3.W, T12.X, BS:VEC_021/SCL_122 ; 81806009 6047000C RECIP_IEEE T3.X, T3.X, ; 00000003 00604310 RECIP_IEEE T3.Y (MASKED), T3.X, ; 00000003 20604300 RECIP_IEEE T3.Z (MASKED), T3.X, ; 00000003 40604300 RECIP_IEEE * T3.W (MASKED), T3.X, ; 80000003 60604300 MUL_IEEE T4.X, T2.W, PV.X, ; 001FCC02 00800110 MULADD_IEEE T2.Y, T2.Z, T3.W, T2.Y, ; 01806802 20430402 MULADD_IEEE T2.Z, T2.X, T3.Y, T13.X, BS:VEC_102/SCL_221 ; 00806002 404F000D MULADD_IEEE * T0.W, T6.W, T0.Z, T11.X, BS:VEC_210 ; 81000C06 6017000B MULADD_IEEE T0.X, PV.W, T3.Z, PV.Z, ; 01006CFE 000308FE MUL_IEEE T4.Y, PV.Y, T3.X, ; 000064FE 20800110 MULADD_IEEE T0.Z, T7.W, T1.W, T5.Z, ; 01802C07 40030805 MULADD_IEEE * T0.W, T5.Y, T3.W, T10.X, BS:VEC_120/SCL_212 ; 81806405 600B000A MUL_IEEE T4.Z, PV.W, T3.X, ; 00006CFE 40800110 MULADD_IEEE * T0.W, PV.Z, T3.W, PV.X, ; 818068FE 600300FE MUL_IEEE * T4.W, PV.W, T3.X, ; 80006CFE 60800110 ===== SHADER #85 ======================================== PS/CAYMAN/CAYMAN ===== ===== 258 dw ===== 14 gprs ===== 1 stack ======================================= 0000 0000001a a0540000 ALU 22 @52 0052 00380400 00946b10 1 x: INTERP_XY R4.x, R0.y, Param0.x VEC_210 0054 00380000 20946b10 y: INTERP_XY R4.y, R0.x, Param0.x VEC_210 0056 00380400 40146b00 z: INTERP_XY __.z, R0.y, Param0.x VEC_210 0058 80380000 60146b00 w: INTERP_XY __.w, R0.x, Param0.x VEC_210 0060 00382400 00d46b10 2 x: INTERP_XY R6.x, R0.y, Param1.x VEC_210 0062 00382000 20d46b10 y: INTERP_XY R6.y, R0.x, Param1.x VEC_210 0064 00382400 40146b00 z: INTERP_XY __.z, R0.y, Param1.x VEC_210 0066 80382000 60146b00 w: INTERP_XY __.w, R0.x, Param1.x VEC_210 0068 00382400 00146b80 3 x: INTERP_ZW __.x, R0.y, Param1.x VEC_210 0070 00382000 20146b80 y: INTERP_ZW __.y, R0.x, Param1.x VEC_210 0072 00382400 41146b90 z: INTERP_ZW R8.z, R0.y, Param1.x VEC_210 0074 80382000 60b46b90 w: INTERP_ZW R5.w, R0.x, Param1.x VEC_210 0076 00384400 00f46b10 4 x: INTERP_XY R7.x, R0.y, Param2.x VEC_210 0078 00384000 20f46b10 y: INTERP_XY R7.y, R0.x, Param2.x VEC_210 0080 00384400 40146b00 z: INTERP_XY __.z, R0.y, Param2.x VEC_210 0082 80384000 60146b00 w: INTERP_XY __.w, R0.x, Param2.x VEC_210 0084 00384400 00146b80 5 x: INTERP_ZW __.x, R0.y, Param2.x VEC_210 0086 00384000 20146b80 y: INTERP_ZW __.y, R0.x, Param2.x VEC_210 0088 00384400 40b46b90 z: INTERP_ZW R5.z, R0.y, Param2.x VEC_210 0090 80384000 61146b90 w: INTERP_ZW R8.w, R0.x, Param2.x VEC_210 0092 000008fe 00000c90 6 x: MOV R0.x, PV.z 0094 80000cfe 20000c90 y: MOV R0.y, PV.w 0002 0000000a 80400800 TEX 3 @20 0020 00001110 f00d1002 fc808000 SAMPLE R2.xyzw, R0.xy__, RID:17, SID:1 CT:NNNN 0024 00041110 f00d1000 fc808000 SAMPLE R0.xyzw, R4.xy__, RID:17, SID:1 CT:NNNN 0028 00071110 f00d1001 fc808000 SAMPLE R1.xyzw, R7.xy__, RID:17, SID:1 CT:NNNN 0004 00000030 a43c0000 ALU_PUSH_BEFORE 16 @96 0096 01802c01 00600110 7 x: MUL_IEEE R3.x, R1.w, R1.w 0098 01000800 20a00110 y: MUL_IEEE R5.y, R0.z, R0.z 0100 00804402 40600110 z: MUL_IEEE R3.z, R2.y, R2.y 0102 80000000 60600110 w: MUL_IEEE R3.w, R0.x, R0.x 0104 00000cfe 00a00110 8 x: MUL_IEEE R5.x, PV.w, R0.x 0106 008048fe 20600110 y: MUL_IEEE R3.y, PV.z, R2.y 0108 010004fe 40600110 z: MUL_IEEE R3.z, PV.y, R0.z 0110 818020fe 60600110 w: MUL_IEEE R3.w, PV.x, R1.w 0112 001f2005 00605f10 9 x: DOT4 R3.x, R5.x, 1.0 0114 001f2403 20605f00 y: DOT4 __.y, R3.y, 1.0 0116 001f2803 40605f00 z: DOT4 __.z, R3.z, 1.0 0118 801f2c03 60605f00 w: DOT4 __.w, R3.w, 1.0 0120 801fc0fd 61200490 10 w: SETGT R9.w, [0x3727c5ac 1e-05].x, PV.x 0122 3727c5ac 0124 801f0cfe 61200610 11 w: SETE_DX10 R9.w, PV.w, 0 0126 801f0cfe 00002104 12 M x: PRED_SETE_INT __.x, PV.w, 0 0006 00000005 82800001 JUMP @10 POP:1 0008 00000040 a8000000 ALU_POP_AFTER 1 @128 0128 801f00f9 20a01680 13 y: KILLGT __.y, 1.0, 0 0010 00000041 a00c0000 ALU 4 @130 0130 80000808 01200c90 14 x: MOV R9.x, R8.z 0132 00000805 01400c90 15 x: MOV R10.x, R5.z 0134 80000c05 21200c90 y: MOV R9.y, R5.w 0136 80000c08 21400c90 16 y: MOV R10.y, R8.w 0012 00000010 80401000 TEX 5 @32 0032 00071010 f00d1007 fc800000 SAMPLE R7.xyzw, R7.xy__, RID:16, SID:0 CT:NNNN 0036 00061010 f00d1006 fc800000 SAMPLE R6.xyzw, R6.xy__, RID:16, SID:0 CT:NNNN 0040 000a1010 f00d1008 fc800000 SAMPLE R8.xyzw, R10.xy__, RID:16, SID:0 CT:NNNN 0044 00091010 f00d1009 fc800000 SAMPLE R9.xyzw, R9.xy__, RID:16, SID:0 CT:NNNN 0048 00041010 f00d1004 fc800000 SAMPLE R4.xyzw, R4.xy__, RID:16, SID:0 CT:NNNN 0014 00000045 a0ec0000 ALU 60 @138 0138 801f3000 60a00010 17 w: ADD R5.w, -R0.x, 1.0 0140 019fc804 40a00110 18 z: MUL_IEEE R5.z, R4.z, PV.w 0142 801f3402 61400010 w: ADD R10.w, -R2.y, 1.0 0144 019fc804 20a00110 19 y: MUL_IEEE R5.y, R4.z, PV.w 0146 00000809 40ab08fe z: MULADD_IEEE R5.z, R9.z, R0.x, PV.z VEC_120 0148 801f3800 61700010 w: ADD R11.w, -R0.z, 1.0 VEC_201 0150 019fc804 01400110 20 x: MUL_IEEE R10.x, R4.z, PV.w 0152 0000a8fe 21400110 y: MUL_IEEE R10.y, PV.z, R5.x 0154 00804808 40ab04fe z: MULADD_IEEE R5.z, R8.z, R2.y, PV.y VEC_120 0156 801f3c01 61800010 w: ADD R12.w, -R1.w, 1.0 0158 019fc804 20a00110 21 y: MUL_IEEE R5.y, R4.z, PV.w 0160 008068fe 40a304fe z: MULADD_IEEE R5.z, PV.z, R3.y, PV.y 0162 81000806 61ab00fe w: MULADD_IEEE R13.w, R6.z, R0.z, PV.x VEC_120 0164 01006cfe 014308fe 22 x: MULADD_IEEE R10.x, PV.w, R3.z, PV.z 0166 01802807 20a304fe y: MULADD_IEEE R5.y, R7.z, R1.w, PV.y 0168 81818c04 40a40110 z: MUL_IEEE R5.z, R4.w, R12.w VEC_021 0170 8180a004 61a00110 23 w: MUL_IEEE R13.w, R4.x, R5.w 0172 01816c04 01600110 24 x: MUL_IEEE R11.x, R4.w, R11.w 0174 8180ac04 21440110 y: MUL_IEEE R10.y, R4.w, R5.w VEC_021 0176 01814004 41400110 25 z: MUL_IEEE R10.z, R4.x, R10.w 0178 80000009 61ab0c0d w: MULADD_IEEE R13.w, R9.x, R0.x, R13.w VEC_120 0180 01816004 01800110 26 x: MUL_IEEE R12.x, R4.x, R11.w 0182 0000acfe 21600110 y: MUL_IEEE R11.y, PV.w, R5.x 0184 80804008 415308fe z: MULADD_IEEE R10.z, R8.x, R2.y, PV.z VEC_201 0186 80000c09 61a3040a 27 w: MULADD_IEEE R13.w, R9.w, R0.x, R10.y 0188 0000acfe 01a00110 28 x: MUL_IEEE R13.x, PV.w, R5.x 0190 0180a404 21400110 y: MUL_IEEE R10.y, R4.y, R5.w 0192 0080680a 4143040b z: MULADD_IEEE R10.z, R10.z, R3.y, R11.y 0194 81000006 60a3000c w: MULADD_IEEE R5.w, R6.x, R0.z, R12.x 0196 01006cfe 018308fe 29 x: MULADD_IEEE R12.x, PV.w, R3.z, PV.z 0198 01814404 21600110 y: MUL_IEEE R11.y, R4.y, R10.w 0200 00000409 412b04fe z: MULADD_IEEE R9.z, R9.y, R0.x, PV.y VEC_120 0202 81818004 60a40110 w: MUL_IEEE R5.w, R4.x, R12.w VEC_021 0204 01802007 01230cfe 30 x: MULADD_IEEE R9.x, R7.x, R1.w, PV.w 0206 01816404 21240110 y: MUL_IEEE R9.y, R4.y, R11.w VEC_021 0208 0000a8fe 41200110 z: MUL_IEEE R9.z, PV.z, R5.x 0210 80804408 60ab04fe w: MULADD_IEEE R5.w, R8.y, R2.y, PV.y VEC_120 0212 01818404 00a00110 31 x: MUL_IEEE R5.x, R4.y, R12.w 0214 00806cfe 214308fe y: MULADD_IEEE R10.y, PV.w, R3.y, PV.z 0216 01000406 413304fe z: MULADD_IEEE R9.z, R6.y, R0.z, PV.y VEC_201 0218 81814c04 60840110 w: MUL_IEEE R4.w, R4.w, R10.w VEC_021 0220 00804c08 00430cfe 32 x: MULADD_IEEE R2.x, R8.w, R2.y, PV.w 0222 010068fe 204304fe y: MULADD_IEEE R2.y, PV.z, R3.z, PV.y 0224 01802407 404300fe z: MULADD_IEEE R2.z, R7.y, R1.w, PV.x 0226 81806009 6047000c w: MULADD_IEEE R2.w, R9.x, R3.w, R12.x VEC_021 0228 00000003 00604310 33 x: RECIP_IEEE R3.x, R3.x 0230 00000003 20604300 y: RECIP_IEEE __.y, R3.x 0232 00000003 40604300 z: RECIP_IEEE __.z, R3.x 0234 80000003 60604300 w: RECIP_IEEE __.w, R3.x 0236 001fcc02 00800110 34 x: MUL_IEEE R4.x, R2.w, PV.x 0238 01806802 20430402 y: MULADD_IEEE R2.y, R2.z, R3.w, R2.y 0240 00806002 404f000d z: MULADD_IEEE R2.z, R2.x, R3.y, R13.x VEC_102 0242 81000c06 6017000b w: MULADD_IEEE R0.w, R6.w, R0.z, R11.x VEC_210 0244 01006cfe 000308fe 35 x: MULADD_IEEE R0.x, PV.w, R3.z, PV.z 0246 000064fe 20800110 y: MUL_IEEE R4.y, PV.y, R3.x 0248 01802c07 40030805 z: MULADD_IEEE R0.z, R7.w, R1.w, R5.z 0250 81806405 600b000a w: MULADD_IEEE R0.w, R5.y, R3.w, R10.x VEC_120 0252 00006cfe 40800110 36 z: MUL_IEEE R4.z, PV.w, R3.x 0254 818068fe 600300fe w: MULADD_IEEE R0.w, PV.z, R3.w, PV.x 0256 80006cfe 60800110 37 w: MUL_IEEE R4.w, PV.w, R3.x 0016 c0020000 95200688 EXPORT_DONE PIXEL 0 R4.xyzw 0018 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #85 OPT ==================================== PS/CAYMAN/CAYMAN ===== ===== 236 dw ===== 8 gprs ===== 0 stack ======================================== 0000 00000007 a02c0000 ALU 12 @14 0014 00384400 00146b80 1 x: INTERP_ZW __.x, R0.y, Param2.x VEC_210 0016 00b84000 20146b80 y: INTERP_ZW __.y, R0.x, Param2.y VEC_210 0018 01384400 40546b90 z: INTERP_ZW R2.z, R0.y, Param2.z VEC_210 0020 81b84000 60546b90 w: INTERP_ZW R2.w, R0.x, Param2.w VEC_210 0022 00380400 00346b10 2 x: INTERP_XY R1.x, R0.y, Param0.x VEC_210 0024 00b80000 20346b10 y: INTERP_XY R1.y, R0.x, Param0.y VEC_210 0026 01380400 40146b00 z: INTERP_XY __.z, R0.y, Param0.z VEC_210 0028 81b80000 60146b00 w: INTERP_XY __.w, R0.x, Param0.w VEC_210 0030 00384400 00946b10 3 x: INTERP_XY R4.x, R0.y, Param2.x VEC_210 0032 00b84000 20946b10 y: INTERP_XY R4.y, R0.x, Param2.y VEC_210 0034 01384400 40146b00 z: INTERP_XY __.z, R0.y, Param2.z VEC_210 0036 81b84000 60146b00 w: INTERP_XY __.w, R0.x, Param2.w VEC_210 0002 00000014 80400800 TEX 3 @40 0040 00041110 f01dfe05 fc808000 SAMPLE R5.__w_, R4.xy__, RID:17, SID:1 CT:NNNN 0044 00011110 f01fa005 fc808000 SAMPLE R5.xz__, R1.xy__, RID:17, SID:1 CT:NNNN 0048 00021110 f007fe05 fda08000 SAMPLE R5.___y, R2.zw__, RID:17, SID:1 CT:NNNN 0004 0000001a a0540000 ALU 22 @52 0052 0180ac05 0f800110 4 x: MUL_IEEE T0.x, R5.w, R5.w 0054 0000a005 2f800110 y: MUL_IEEE T0.y, R5.x, R5.x 0056 0100a805 4f800110 z: MUL_IEEE T0.z, R5.z, R5.z 0058 8080a405 6f800110 w: MUL_IEEE T0.w, R5.y, R5.y 0060 0000a47c 00c00110 5 x: MUL_IEEE R6.x, T0.y, R5.x 0062 0180a07c 20c00110 y: MUL_IEEE R6.y, T0.x, R5.w 0064 0080ac7c 40e00110 z: MUL_IEEE R7.z, T0.w, R5.y 0066 8100a87c 60c00110 w: MUL_IEEE R6.w, T0.z, R5.z 0068 001f2006 00005f00 6 x: DOT4 __.x, R6.x, 1.0 0070 001f2406 20005f00 y: DOT4 __.y, R6.y, 1.0 0072 001f2807 40c05f10 z: DOT4 R6.z, R7.z, 1.0 0074 801f2c06 60005f00 w: DOT4 __.w, R6.w, 1.0 0076 00382400 00746b10 7 x: INTERP_XY R3.x, R0.y, Param1.x VEC_210 0078 00b82000 20746b10 y: INTERP_XY R3.y, R0.x, Param1.y VEC_210 0080 01382400 40146b00 z: INTERP_XY __.z, R0.y, Param1.z VEC_210 0082 81b82000 60146b00 w: INTERP_XY __.w, R0.x, Param1.w VEC_210 0084 00382400 00146b80 8 x: INTERP_ZW __.x, R0.y, Param1.x VEC_210 0086 00b82000 20146b80 y: INTERP_ZW __.y, R0.x, Param1.y VEC_210 0088 01382400 40346b90 z: INTERP_ZW R1.z, R0.y, Param1.z VEC_210 0090 81b82000 60346b90 w: INTERP_ZW R1.w, R0.x, Param1.w VEC_210 0092 8100c0fd 00001680 9 x: KILLGT __.x, [0x3727c5ac 1e-05].x, R6.z 0094 3727c5ac 0006 00000030 80401000 TEX 5 @96 0096 00011010 f00d1000 fc800000 SAMPLE R0.xyzw, R1.xy__, RID:16, SID:0 CT:NNNN 0100 00011010 f00d1001 fda00000 SAMPLE R1.xyzw, R1.zw__, RID:16, SID:0 CT:NNNN 0104 00021010 f00d1002 fda00000 SAMPLE R2.xyzw, R2.zw__, RID:16, SID:0 CT:NNNN 0108 00031010 f00d1003 fc800000 SAMPLE R3.xyzw, R3.xy__, RID:16, SID:0 CT:NNNN 0112 00041010 f00d1004 fc800000 SAMPLE R4.xyzw, R4.xy__, RID:16, SID:0 CT:NNNN 0008 0000003a a0ec0000 ALU 60 @116 0116 801f3005 6f800010 10 w: ADD T0.w, -R5.x, 1.0 0118 818f8000 0f800110 11 x: MUL_IEEE T0.x, R0.x, T0.w 0120 001f3c05 0f800010 12 x: ADD T0.x, -R5.w, 1.0 0122 0000a001 2fa3007c y: MULADD_IEEE T1.y, R1.x, R5.x, T0.x 0124 818f8800 4fa00110 z: MUL_IEEE T1.z, R0.z, T0.w 0126 018f8c00 2f800110 13 y: MUL_IEEE T0.y, R0.w, T0.w 0128 000f8c00 4f800110 z: MUL_IEEE T0.z, R0.w, T0.x 0130 818f8400 6f800110 w: MUL_IEEE T0.w, R0.y, T0.w 0132 000f8000 0fa00110 14 x: MUL_IEEE T1.x, R0.x, T0.x 0134 001f3405 2ff00010 y: ADD T3.y, -R5.y, 1.0 VEC_201 0136 000f8400 4fc00110 z: MUL_IEEE T2.z, R0.y, T0.x 0138 8000ac01 6fc7047c w: MULADD_IEEE T2.w, R1.w, R5.x, T0.y VEC_021 0140 000f8800 0f900110 15 x: MUL_IEEE T0.x, R0.z, T0.x VEC_201 0142 0000a801 2f87087d y: MULADD_IEEE T0.y, R1.z, R5.x, T1.z VEC_021 0144 0000c47d 4fa00110 z: MUL_IEEE T1.z, T1.y, R6.x 0146 8000a401 6f8b0c7c w: MULADD_IEEE T0.w, R1.y, R5.x, T0.w VEC_120 0148 0180ac02 0fc3087c 16 x: MULADD_IEEE T2.x, R2.w, R5.w, T0.z 0150 0180a002 2fc7007d y: MULADD_IEEE T2.y, R2.x, R5.w, T1.x VEC_021 0152 001f3805 4fe80010 z: ADD T3.z, -R5.z, 1.0 VEC_120 0154 8180a802 6fa3007c w: MULADD_IEEE T1.w, R2.z, R5.w, T0.x 0156 0000c47c 0fa00110 17 x: MUL_IEEE T1.x, T0.y, R6.x 0158 0000cc7e 2fa80110 y: MUL_IEEE T1.y, T2.w, R6.x VEC_120 0160 008fe800 4f800110 z: MUL_IEEE T0.z, R0.z, T3.y 0162 808fec00 6fc00110 w: MUL_IEEE T2.w, R0.w, T3.y 0164 008fe000 0f800110 18 x: MUL_IEEE T0.x, R0.x, T3.y 0166 008fe400 2f940110 y: MUL_IEEE T0.y, R0.y, T3.y VEC_210 0168 0180a402 4fc3087e z: MULADD_IEEE T2.z, R2.y, R5.w, T2.z 0170 8000cc7c 6f800110 w: MUL_IEEE T0.w, T0.w, R6.x 0172 0080cc7d 0fe3007d 19 x: MULADD_IEEE T3.x, T1.w, R6.y, T1.x 0174 0080c07e 2fc3047d y: MULADD_IEEE T2.y, T2.x, R6.y, T1.y 0176 0080c47e 4fa3087d z: MULADD_IEEE T1.z, T2.y, R6.y, T1.z 0178 810fec00 6fac0110 w: MUL_IEEE T1.w, R0.w, T3.z VEC_102 0180 0080ac03 0fa30c7e 20 x: MULADD_IEEE T1.x, R3.w, R5.y, T2.w 0182 0080a003 2fa3007c y: MULADD_IEEE T1.y, R3.x, R5.y, T0.x 0184 0080a403 4f83047c z: MULADD_IEEE T0.z, R3.y, R5.y, T0.y 0186 8080a803 6fc3087c w: MULADD_IEEE T2.w, R3.z, R5.y, T0.z 0188 010fe000 0f800110 21 x: MUL_IEEE T0.x, R0.x, T3.z 0190 010fe400 2f940110 y: MUL_IEEE T0.y, R0.y, T3.z VEC_210 0192 010fe800 4fc00110 z: MUL_IEEE T2.z, R0.z, T3.z 0194 8080c87e 6f930c7c w: MULADD_IEEE T0.w, T2.z, R6.y, T0.w VEC_201 0196 0100e07d 0fc3047e 22 x: MULADD_IEEE T2.x, T1.x, R7.z, T2.y 0198 0100e47d 4fa3087d z: MULADD_IEEE T1.z, T1.y, R7.z, T1.z 0200 8100ac04 6faf0c7d w: MULADD_IEEE T1.w, R4.w, R5.z, T1.w VEC_102 0202 0100e87c 0fa30c7c 23 x: MULADD_IEEE T1.x, T0.z, R7.z, T0.w 0204 0100a004 2fa7007c y: MULADD_IEEE T1.y, R4.x, R5.z, T0.x VEC_021 0206 0100ec7e 4f83007f z: MULADD_IEEE T0.z, T2.w, R7.z, T3.x 0208 8100a404 6f87047c w: MULADD_IEEE T0.w, R4.y, R5.z, T0.y VEC_021 0210 00000806 0f804310 24 x: RECIP_IEEE T0.x, R6.z 0212 00000806 20004300 y: RECIP_IEEE __.y, R6.z 0214 00000806 40004300 z: RECIP_IEEE __.z, R6.z 0216 80000806 60004300 w: RECIP_IEEE __.w, R6.z 0218 0100a804 2f83087e 25 y: MULADD_IEEE T0.y, R4.z, R5.z, T2.z 0220 8180cc7d 6fa3007e w: MULADD_IEEE T1.w, T1.w, R6.w, T2.x 0222 0180c47c 2f8b087c 26 y: MULADD_IEEE T0.y, T0.y, R6.w, T0.z VEC_120 0224 0180cc7c 4f83007d z: MULADD_IEEE T0.z, T0.w, R6.w, T1.x 0226 8180c47d 6f83087d w: MULADD_IEEE T0.w, T1.y, R6.w, T1.z 0228 000f8c7c 00000110 27 x: MUL_IEEE R0.x, T0.w, T0.x 0230 000f887c 20000110 y: MUL_IEEE R0.y, T0.z, T0.x 0232 000f847c 40000110 z: MUL_IEEE R0.z, T0.y, T0.x 0234 800f8c7d 60080110 w: MUL_IEEE R0.w, T1.w, T0.x VEC_120 0010 c0000000 95000688 EXPORT_DONE PIXEL 0 R0.xyzw 0012 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ExecCommandLine: "/home/dema1701/.local/share/Steam/ubuntu12_32/steam" System startup time: 8.40 seconds -------------------------------------------------------------- FRAG 0: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg) #0 { main_body: call void @llvm.R600.store.dummy(i32 0) ret void } declare void @llvm.R600.store.dummy(i32) attributes #0 = { "ShaderType"="0" } Shader Disassembly: EXPORT T0.____ ; C0000000 95200FFF CF_END ; 00000000 88000000 ===== SHADER #91 ======================================== PS/CAYMAN/CAYMAN ===== ===== 4 dw ===== 1 gprs ===== 1 stack ========================================== 0000 c0000000 95200fff EXPORT_DONE PIXEL 0 R0.____ 0002 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #91 OPT ==================================== PS/CAYMAN/CAYMAN ===== ===== 4 dw ===== 0 gprs ===== 0 stack ========================================== 0000 c0000000 95000fff EXPORT_DONE PIXEL 0 R0.____ 0002 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- FRAG DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg) #0 { main_body: %2 = call <4 x float> @llvm.R600.interp.const(i32 0) %3 = extractelement <4 x float> %2, i32 0 %4 = extractelement <4 x float> %2, i32 1 %5 = extractelement <4 x float> %2, i32 2 %6 = extractelement <4 x float> %2, i32 3 %7 = insertelement <4 x float> undef, float %3, i32 0 %8 = insertelement <4 x float> %7, float %4, i32 1 %9 = insertelement <4 x float> %8, float %5, i32 2 %10 = insertelement <4 x float> %9, float %6, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %10, i32 0, i32 0) ret void } ; Function Attrs: readnone declare <4 x float> @llvm.R600.interp.const(i32) #1 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } Shader Disassembly: ALU 3, @4, KC0[], KC1[] ; 00000004 A00C0000 EXPORT T0.XYZW ; C0000000 95200688 CF_END ; 00000000 88000000 PAD ; 00000000 00000000 ALU clause starting at 4: ; INTERP_LOAD_P0 T0.X, ARRAY_BASE, ; 000001C0 00007010 INTERP_LOAD_P0 T0.Y, ARRAY_BASE, ; 000001C0 20007010 INTERP_LOAD_P0 T0.Z, ARRAY_BASE, ; 000001C0 40007010 INTERP_LOAD_P0 * T0.W, ARRAY_BASE, ; 800001C0 60007010 ===== SHADER #92 ======================================== PS/CAYMAN/CAYMAN ===== ===== 16 dw ===== 1 gprs ===== 1 stack ========================================= 0000 00000004 a00c0000 ALU 4 @8 0008 000001c0 00007010 1 x: INTERP_LOAD_P0 R0.x, Param0.x 0010 000001c0 20007010 y: INTERP_LOAD_P0 R0.y, Param0.x 0012 000001c0 40007010 z: INTERP_LOAD_P0 R0.z, Param0.x 0014 800001c0 60007010 w: INTERP_LOAD_P0 R0.w, Param0.x 0002 c0000000 95200688 EXPORT_DONE PIXEL 0 R0.xyzw 0004 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #92 OPT ==================================== PS/CAYMAN/CAYMAN ===== ===== 14 dw ===== 1 gprs ===== 0 stack ========================================= 0000 00000003 a00c0000 ALU 4 @6 0006 000001c0 00007010 1 x: INTERP_LOAD_P0 R0.x, Param0.x 0008 000005c0 20007010 y: INTERP_LOAD_P0 R0.y, Param0.y 0010 000009c0 40007010 z: INTERP_LOAD_P0 R0.z, Param0.z 0012 80000dc0 60007010 w: INTERP_LOAD_P0 R0.w, Param0.w 0002 c0000000 95000688 EXPORT_DONE PIXEL 0 R0.xyzw 0004 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg) #0 { main_body: %2 = call <4 x float> @llvm.R600.interp.const(i32 0) %3 = extractelement <4 x float> %2, i32 0 %4 = extractelement <4 x float> %2, i32 1 %5 = extractelement <4 x float> %2, i32 2 %6 = extractelement <4 x float> %2, i32 3 %7 = insertelement <4 x float> undef, float %3, i32 0 %8 = insertelement <4 x float> %7, float %4, i32 1 %9 = insertelement <4 x float> %8, float %5, i32 2 %10 = insertelement <4 x float> %9, float %6, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %10, i32 0, i32 0) ret void } ; Function Attrs: readnone declare <4 x float> @llvm.R600.interp.const(i32) #1 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } Shader Disassembly: ALU 3, @4, KC0[], KC1[] ; 00000004 A00C0000 EXPORT T0.XYZW ; C0000000 95200688 CF_END ; 00000000 88000000 PAD ; 00000000 00000000 ALU clause starting at 4: ; INTERP_LOAD_P0 T0.X, ARRAY_BASE, ; 000001C0 00007010 INTERP_LOAD_P0 T0.Y, ARRAY_BASE, ; 000001C0 20007010 INTERP_LOAD_P0 T0.Z, ARRAY_BASE, ; 000001C0 40007010 INTERP_LOAD_P0 * T0.W, ARRAY_BASE, ; 800001C0 60007010 ===== SHADER #93 ======================================== PS/CAYMAN/CAYMAN ===== ===== 16 dw ===== 1 gprs ===== 1 stack ========================================= 0000 00000004 a00c0000 ALU 4 @8 0008 000001c0 00007010 1 x: INTERP_LOAD_P0 R0.x, Param0.x 0010 000001c0 20007010 y: INTERP_LOAD_P0 R0.y, Param0.x 0012 000001c0 40007010 z: INTERP_LOAD_P0 R0.z, Param0.x 0014 800001c0 60007010 w: INTERP_LOAD_P0 R0.w, Param0.x 0002 c0000000 95200688 EXPORT_DONE PIXEL 0 R0.xyzw 0004 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #93 OPT ==================================== PS/CAYMAN/CAYMAN ===== ===== 14 dw ===== 1 gprs ===== 0 stack ========================================= 0000 00000003 a00c0000 ALU 4 @6 0006 000001c0 00007010 1 x: INTERP_LOAD_P0 R0.x, Param0.x 0008 000005c0 20007010 y: INTERP_LOAD_P0 R0.y, Param0.y 0010 000009c0 40007010 z: INTERP_LOAD_P0 R0.z, Param0.z 0012 80000dc0 60007010 w: INTERP_LOAD_P0 R0.w, Param0.w 0002 c0000000 95000688 EXPORT_DONE PIXEL 0 R0.xyzw 0004 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] 0: MOV OUT[0], IN[0] 1: MOV OUT[1], IN[1] 2: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg, <4 x float> inreg) #0 { main_body: %3 = extractelement <4 x float> %1, i32 0 %4 = extractelement <4 x float> %1, i32 1 %5 = extractelement <4 x float> %1, i32 2 %6 = extractelement <4 x float> %1, i32 3 %7 = extractelement <4 x float> %2, i32 0 %8 = extractelement <4 x float> %2, i32 1 %9 = extractelement <4 x float> %2, i32 2 %10 = extractelement <4 x float> %2, i32 3 %11 = insertelement <4 x float> undef, float %3, i32 0 %12 = insertelement <4 x float> %11, float %4, i32 1 %13 = insertelement <4 x float> %12, float %5, i32 2 %14 = insertelement <4 x float> %13, float %6, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %14, i32 60, i32 1) %15 = insertelement <4 x float> undef, float %7, i32 0 %16 = insertelement <4 x float> %15, float %8, i32 1 %17 = insertelement <4 x float> %16, float %9, i32 2 %18 = insertelement <4 x float> %17, float %10, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %18, i32 0, i32 2) ret void } declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="1" } Shader Disassembly: CALL_FS ; 00000000 84C00000 EXPORT T1.XYZW ; C000A03C 95000688 EXPORT T2.XYZW ; C0014000 95200688 CF_END ; 00000000 88000000 ===== SHADER #94 ======================================== VS/CAYMAN/CAYMAN ===== ===== 8 dw ===== 3 gprs ===== 1 stack ========================================== 0000 00000000 84c00000 CALL_FS @0 0002 c000a03c 95000688 EXPORT_DONE POS 60 R1.xyzw 0004 c0014000 95200688 EXPORT_DONE PARAM 0 R2.xyzw 0006 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #94 OPT ==================================== VS/CAYMAN/CAYMAN ===== ===== 8 dw ===== 3 gprs ===== 1 stack ========================================== 0000 00000000 84c00000 CALL_FS @0 0002 c0014000 95000688 EXPORT_DONE PARAM 0 R2.xyzw 0004 c000a03c 95000688 EXPORT_DONE POS 60 R1.xyzw 0006 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- VERT DCL IN[0] DCL OUT[0], POSITION 0: MOV OUT[0], IN[0] 1: END STREAMOUT 0: MEM_STREAM0_BUF0[0..0] <- OUT[0].x ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg) #0 { main_body: %2 = extractelement <4 x float> %1, i32 0 %3 = extractelement <4 x float> %1, i32 1 %4 = extractelement <4 x float> %1, i32 2 %5 = extractelement <4 x float> %1, i32 3 %6 = insertelement <4 x float> undef, float %2, i32 0 %7 = insertelement <4 x float> %6, float %3, i32 1 %8 = insertelement <4 x float> %7, float %4, i32 2 %9 = insertelement <4 x float> %8, float %5, i32 3 call void @llvm.R600.store.stream.output(<4 x float> %9, i32 0, i32 0, i32 1) %10 = insertelement <4 x float> undef, float %2, i32 0 %11 = insertelement <4 x float> %10, float %3, i32 1 %12 = insertelement <4 x float> %11, float %4, i32 2 %13 = insertelement <4 x float> %12, float %5, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %13, i32 60, i32 1) call void @llvm.R600.store.dummy(i32 2) ret void } declare void @llvm.R600.store.stream.output(<4 x float>, i32, i32, i32) declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) declare void @llvm.R600.store.dummy(i32) attributes #0 = { "ShaderType"="1" } Shader Disassembly: CALL_FS ; 00000000 84C00000 EXPORT T1 ; 00008000 90001FFF EXPORT T1.XYZW ; C000A03C 95000688 EXPORT T0.____ ; C0004000 95200FFF CF_END ; 00000000 88000000 PAD ; 00000000 00000000 ===== SHADER #95 ======================================== VS/CAYMAN/CAYMAN ===== ===== 12 dw ===== 2 gprs ===== 1 stack ========================================= 0000 00000000 84c00000 CALL_FS @0 0002 00008000 90001fff MEM_STREAM0_BUF0 WRITE 0 R1.x___ ES:0 0004 c000a03c 95000688 EXPORT_DONE POS 60 R1.xyzw 0006 c0004000 95200fff EXPORT_DONE PARAM 0 R0.____ 0008 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #95 OPT ==================================== VS/CAYMAN/CAYMAN ===== ===== 10 dw ===== 2 gprs ===== 1 stack ========================================= 0000 00000000 84c00000 CALL_FS @0 0002 c000a03c 95000688 EXPORT_DONE POS 60 R1.xyzw 0004 00008000 90001fff MEM_STREAM0_BUF0 WRITE 0 R1.x___ ES:0 0006 c0004000 95000fff EXPORT_DONE PARAM 0 R0.____ 0008 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- FRAG DCL IN[0], GENERIC[0], CONSTANT 0: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg) #0 { main_body: %2 = call <4 x float> @llvm.R600.interp.const(i32 0) call void @llvm.R600.store.dummy(i32 0) ret void } ; Function Attrs: readnone declare <4 x float> @llvm.R600.interp.const(i32) #1 declare void @llvm.R600.store.dummy(i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } Shader Disassembly: EXPORT T0.____ ; C0000000 95200FFF CF_END ; 00000000 88000000 ===== SHADER #96 ======================================== PS/CAYMAN/CAYMAN ===== ===== 4 dw ===== 1 gprs ===== 1 stack ========================================== 0000 c0000000 95200fff EXPORT_DONE PIXEL 0 R0.____ 0002 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #96 OPT ==================================== PS/CAYMAN/CAYMAN ===== ===== 4 dw ===== 0 gprs ===== 0 stack ========================================== 0000 c0000000 95000fff EXPORT_DONE PIXEL 0 R0.____ 0002 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] 0: MOV OUT[0], IN[0] 1: MOV OUT[1], IN[1] 2: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg, <4 x float> inreg) #0 { main_body: %3 = extractelement <4 x float> %1, i32 0 %4 = extractelement <4 x float> %1, i32 1 %5 = extractelement <4 x float> %1, i32 2 %6 = extractelement <4 x float> %1, i32 3 %7 = extractelement <4 x float> %2, i32 0 %8 = extractelement <4 x float> %2, i32 1 %9 = extractelement <4 x float> %2, i32 2 %10 = extractelement <4 x float> %2, i32 3 %11 = insertelement <4 x float> undef, float %3, i32 0 %12 = insertelement <4 x float> %11, float %4, i32 1 %13 = insertelement <4 x float> %12, float %5, i32 2 %14 = insertelement <4 x float> %13, float %6, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %14, i32 60, i32 1) %15 = insertelement <4 x float> undef, float %7, i32 0 %16 = insertelement <4 x float> %15, float %8, i32 1 %17 = insertelement <4 x float> %16, float %9, i32 2 %18 = insertelement <4 x float> %17, float %10, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %18, i32 0, i32 2) ret void } declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="1" } Shader Disassembly: CALL_FS ; 00000000 84C00000 EXPORT T1.XYZW ; C000A03C 95000688 EXPORT T2.XYZW ; C0014000 95200688 CF_END ; 00000000 88000000 ===== SHADER #97 ======================================== VS/CAYMAN/CAYMAN ===== ===== 8 dw ===== 3 gprs ===== 1 stack ========================================== 0000 00000000 84c00000 CALL_FS @0 0002 c000a03c 95000688 EXPORT_DONE POS 60 R1.xyzw 0004 c0014000 95200688 EXPORT_DONE PARAM 0 R2.xyzw 0006 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #97 OPT ==================================== VS/CAYMAN/CAYMAN ===== ===== 8 dw ===== 3 gprs ===== 1 stack ========================================== 0000 00000000 84c00000 CALL_FS @0 0002 c0014000 95000688 EXPORT_DONE PARAM 0 R2.xyzw 0004 c000a03c 95000688 EXPORT_DONE POS 60 R1.xyzw 0006 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] DCL OUT[2], GENERIC[10] DCL OUT[3], GENERIC[11] DCL CONST[0] IMM[0] FLT32 { 1.0000, 0.0000, -1.0000, 0.0000} 0: MOV OUT[0], IN[0] 1: MOV OUT[1], IN[1] 2: MAD OUT[2], CONST[0].xyxy, IMM[0].zyyz, IN[1].xyxy 3: MAD OUT[3], CONST[0].xyxy, IMM[0].xyyx, IN[1].xyxy 4: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg, <4 x float> inreg) #0 { main_body: %3 = extractelement <4 x float> %1, i32 0 %4 = extractelement <4 x float> %1, i32 1 %5 = extractelement <4 x float> %1, i32 2 %6 = extractelement <4 x float> %1, i32 3 %7 = extractelement <4 x float> %2, i32 0 %8 = extractelement <4 x float> %2, i32 1 %9 = extractelement <4 x float> %2, i32 2 %10 = extractelement <4 x float> %2, i32 3 %11 = load <4 x float> addrspace(8)* null %12 = extractelement <4 x float> %11, i32 0 %13 = fmul float %12, -1.000000e+00 %14 = fadd float %13, %7 %15 = load <4 x float> addrspace(8)* null %16 = extractelement <4 x float> %15, i32 1 %17 = fmul float %16, 0.000000e+00 %18 = fadd float %17, %8 %19 = load <4 x float> addrspace(8)* null %20 = extractelement <4 x float> %19, i32 0 %21 = fmul float %20, 0.000000e+00 %22 = fadd float %21, %7 %23 = load <4 x float> addrspace(8)* null %24 = extractelement <4 x float> %23, i32 1 %25 = fmul float %24, -1.000000e+00 %26 = fadd float %25, %8 %27 = load <4 x float> addrspace(8)* null %28 = extractelement <4 x float> %27, i32 0 %29 = fmul float %28, 1.000000e+00 %30 = fadd float %29, %7 %31 = load <4 x float> addrspace(8)* null %32 = extractelement <4 x float> %31, i32 1 %33 = fmul float %32, 0.000000e+00 %34 = fadd float %33, %8 %35 = load <4 x float> addrspace(8)* null %36 = extractelement <4 x float> %35, i32 0 %37 = fmul float %36, 0.000000e+00 %38 = fadd float %37, %7 %39 = load <4 x float> addrspace(8)* null %40 = extractelement <4 x float> %39, i32 1 %41 = fmul float %40, 1.000000e+00 %42 = fadd float %41, %8 %43 = insertelement <4 x float> undef, float %3, i32 0 %44 = insertelement <4 x float> %43, float %4, i32 1 %45 = insertelement <4 x float> %44, float %5, i32 2 %46 = insertelement <4 x float> %45, float %6, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %46, i32 60, i32 1) %47 = insertelement <4 x float> undef, float %7, i32 0 %48 = insertelement <4 x float> %47, float %8, i32 1 %49 = insertelement <4 x float> %48, float %9, i32 2 %50 = insertelement <4 x float> %49, float %10, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %50, i32 0, i32 2) %51 = insertelement <4 x float> undef, float %14, i32 0 %52 = insertelement <4 x float> %51, float %18, i32 1 %53 = insertelement <4 x float> %52, float %22, i32 2 %54 = insertelement <4 x float> %53, float %26, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %54, i32 1, i32 2) %55 = insertelement <4 x float> undef, float %30, i32 0 %56 = insertelement <4 x float> %55, float %34, i32 1 %57 = insertelement <4 x float> %56, float %38, i32 2 %58 = insertelement <4 x float> %57, float %42, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %58, i32 2, i32 2) ret void } declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="1" } Shader Disassembly: CALL_FS ; 00000000 84C00000 ALU 7, @8, KC0[CB0:0-32], KC1[] ; 80000008 A01C0000 EXPORT T1.XYZW ; C000A03C 95000688 EXPORT T2.XYZW ; C0014000 94C00688 EXPORT T0.XYZW ; C0004001 94C00688 EXPORT T3.XYZW ; C001C002 95200688 CF_END ; 00000000 88000000 PAD ; 00000000 00000000 ALU clause starting at 8: ; ADD T0.X, T2.X, -KC0[0].X, ; 02100002 00000010 MULADD_IEEE T0.Y, KC0[0].Y, 0.0, T2.Y, ; 001F0480 20030402 MULADD_IEEE * T0.Z, KC0[0].X, 0.0, T2.X, ; 801F0080 40030002 ADD T3.X, KC0[0].X, T2.X, ; 00004080 00600010 ADD * T0.W, T2.Y, -KC0[0].Y, ; 82900402 60000010 ADD * T3.W, KC0[0].Y, T2.Y, ; 80804480 60600010 MOV T3.Y, T0.Y, ; 00000400 20600C90 MOV * T3.Z, T0.Z, ; 80000800 40600C90 ===== SHADER #98 ======================================== VS/CAYMAN/CAYMAN ===== ===== 32 dw ===== 4 gprs ===== 1 stack ========================================= 0000 00000000 84c00000 CALL_FS @0 0002 80000008 a01c0000 ALU 8 @16 KC0[CB0:0-31] 0016 02100002 00000010 1 x: ADD R0.x, R2.x, -KC0[0].x 0018 001f0480 20030402 y: MULADD_IEEE R0.y, KC0[0].y, 0, R2.y 0020 801f0080 40030002 z: MULADD_IEEE R0.z, KC0[0].x, 0, R2.x 0022 00004080 00600010 2 x: ADD R3.x, KC0[0].x, R2.x 0024 82900402 60000010 w: ADD R0.w, R2.y, -KC0[0].y 0026 80804480 60600010 3 w: ADD R3.w, KC0[0].y, R2.y 0028 00000400 20600c90 4 y: MOV R3.y, R0.y 0030 80000800 40600c90 z: MOV R3.z, R0.z 0004 c000a03c 95000688 EXPORT_DONE POS 60 R1.xyzw 0006 c0014000 94c00688 EXPORT PARAM 0 R2.xyzw 0008 c0004001 94c00688 EXPORT PARAM 1 R0.xyzw 0010 c001c002 95200688 EXPORT_DONE PARAM 2 R3.xyzw 0012 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #98 OPT ==================================== VS/CAYMAN/CAYMAN ===== ===== 30 dw ===== 4 gprs ===== 1 stack ========================================= 0000 00000000 84c00000 CALL_FS @0 0002 40000007 a01c0000 ALU 8 @14 KC0[CB0:0-15] 0014 00004080 00000010 1 x: ADD R0.x, KC0[0].x, R2.x 0016 001f0480 20030402 y: MULADD_IEEE R0.y, KC0[0].y, 0, R2.y 0018 001f0080 40030002 z: MULADD_IEEE R0.z, KC0[0].x, 0, R2.x 0020 80804480 60000010 w: ADD R0.w, KC0[0].y, R2.y 0022 02100002 00600010 2 x: ADD R3.x, R2.x, -KC0[0].x 0024 00000400 20600c90 y: MOV R3.y, R0.y 0026 00000800 40600c90 z: MOV R3.z, R0.z 0028 82900402 60680010 w: ADD R3.w, R2.y, -KC0[0].y VEC_120 0004 c001c001 94c00688 EXPORT PARAM 1 R3.xyzw 0006 c0004002 94c00688 EXPORT PARAM 2 R0.xyzw 0008 c0014000 95000688 EXPORT_DONE PARAM 0 R2.xyzw 0010 c000a03c 95000688 EXPORT_DONE POS 60 R1.xyzw 0012 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], PERSPECTIVE DCL IN[1], GENERIC[10], PERSPECTIVE DCL IN[2], GENERIC[11], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL TEMP[0..2] IMM[0] FLT32 { 0.0030, 0.0000, 1.0000, 0.0000} 0: TEX TEMP[0].x, IN[1].xyyy, SAMP[0], 2D 1: MOV TEMP[1].x, TEMP[0].xxxx 2: TEX TEMP[0].x, IN[1].zwww, SAMP[0], 2D 3: MOV TEMP[1].y, TEMP[0].xxxx 4: TEX TEMP[0].x, IN[2].xyyy, SAMP[0], 2D 5: MOV TEMP[1].z, TEMP[0].xxxx 6: TEX TEMP[0].x, IN[2].zwww, SAMP[0], 2D 7: MOV TEMP[1].w, TEMP[0].xxxx 8: TEX TEMP[0].x, IN[0].xyyy, SAMP[0], 2D 9: ADD TEMP[2], TEMP[0].xxxx, -TEMP[1] 10: ABS TEMP[0], TEMP[2] 11: SGE TEMP[2], TEMP[0], IMM[0].xxxx 12: DP4 TEMP[0].x, TEMP[2], IMM[0].zzzz 13: SEQ TEMP[1].x, TEMP[0].xxxx, IMM[0].yyyy 14: IF TEMP[1].xxxx :16 15: KILL 16: ENDIF 17: MOV OUT[0], TEMP[2] 18: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg, <4 x float> inreg, <4 x float> inreg) #0 { main_body: %4 = extractelement <4 x float> %0, i32 0 %5 = extractelement <4 x float> %0, i32 1 %6 = call <2 x float> @llvm.R600.interp.xy(i32 0, float %4, float %5) %7 = call <2 x float> @llvm.R600.interp.zw(i32 0, float %4, float %5) %8 = shufflevector <2 x float> %6, <2 x float> %7, <4 x i32> %9 = extractelement <4 x float> %8, i32 0 %10 = extractelement <4 x float> %8, i32 1 %11 = extractelement <4 x float> %0, i32 0 %12 = extractelement <4 x float> %0, i32 1 %13 = call <2 x float> @llvm.R600.interp.xy(i32 1, float %11, float %12) %14 = call <2 x float> @llvm.R600.interp.zw(i32 1, float %11, float %12) %15 = shufflevector <2 x float> %13, <2 x float> %14, <4 x i32> %16 = extractelement <4 x float> %15, i32 0 %17 = extractelement <4 x float> %15, i32 1 %18 = extractelement <4 x float> %15, i32 2 %19 = extractelement <4 x float> %15, i32 3 %20 = extractelement <4 x float> %0, i32 0 %21 = extractelement <4 x float> %0, i32 1 %22 = call <2 x float> @llvm.R600.interp.xy(i32 2, float %20, float %21) %23 = call <2 x float> @llvm.R600.interp.zw(i32 2, float %20, float %21) %24 = shufflevector <2 x float> %22, <2 x float> %23, <4 x i32> %25 = extractelement <4 x float> %24, i32 0 %26 = extractelement <4 x float> %24, i32 1 %27 = extractelement <4 x float> %24, i32 2 %28 = extractelement <4 x float> %24, i32 3 %29 = insertelement <4 x float> undef, float %16, i32 0 %30 = insertelement <4 x float> %29, float %17, i32 1 %31 = insertelement <4 x float> %30, float %17, i32 2 %32 = insertelement <4 x float> %31, float %17, i32 3 %33 = extractelement <4 x float> %32, i32 0 %34 = extractelement <4 x float> %32, i32 1 %35 = insertelement <4 x float> undef, float %33, i32 0 %36 = insertelement <4 x float> %35, float %34, i32 1 %37 = insertelement <4 x float> %36, float undef, i32 2 %38 = insertelement <4 x float> %37, float undef, i32 3 %39 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %38, i32 16, i32 0, i32 2) %40 = extractelement <4 x float> %39, i32 0 %41 = insertelement <4 x float> undef, float %18, i32 0 %42 = insertelement <4 x float> %41, float %19, i32 1 %43 = insertelement <4 x float> %42, float %19, i32 2 %44 = insertelement <4 x float> %43, float %19, i32 3 %45 = extractelement <4 x float> %44, i32 0 %46 = extractelement <4 x float> %44, i32 1 %47 = insertelement <4 x float> undef, float %45, i32 0 %48 = insertelement <4 x float> %47, float %46, i32 1 %49 = insertelement <4 x float> %48, float undef, i32 2 %50 = insertelement <4 x float> %49, float undef, i32 3 %51 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %50, i32 16, i32 0, i32 2) %52 = extractelement <4 x float> %51, i32 0 %53 = insertelement <4 x float> undef, float %25, i32 0 %54 = insertelement <4 x float> %53, float %26, i32 1 %55 = insertelement <4 x float> %54, float %26, i32 2 %56 = insertelement <4 x float> %55, float %26, i32 3 %57 = extractelement <4 x float> %56, i32 0 %58 = extractelement <4 x float> %56, i32 1 %59 = insertelement <4 x float> undef, float %57, i32 0 %60 = insertelement <4 x float> %59, float %58, i32 1 %61 = insertelement <4 x float> %60, float undef, i32 2 %62 = insertelement <4 x float> %61, float undef, i32 3 %63 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %62, i32 16, i32 0, i32 2) %64 = extractelement <4 x float> %63, i32 0 %65 = insertelement <4 x float> undef, float %27, i32 0 %66 = insertelement <4 x float> %65, float %28, i32 1 %67 = insertelement <4 x float> %66, float %28, i32 2 %68 = insertelement <4 x float> %67, float %28, i32 3 %69 = extractelement <4 x float> %68, i32 0 %70 = extractelement <4 x float> %68, i32 1 %71 = insertelement <4 x float> undef, float %69, i32 0 %72 = insertelement <4 x float> %71, float %70, i32 1 %73 = insertelement <4 x float> %72, float undef, i32 2 %74 = insertelement <4 x float> %73, float undef, i32 3 %75 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %74, i32 16, i32 0, i32 2) %76 = extractelement <4 x float> %75, i32 0 %77 = insertelement <4 x float> undef, float %9, i32 0 %78 = insertelement <4 x float> %77, float %10, i32 1 %79 = insertelement <4 x float> %78, float %10, i32 2 %80 = insertelement <4 x float> %79, float %10, i32 3 %81 = extractelement <4 x float> %80, i32 0 %82 = extractelement <4 x float> %80, i32 1 %83 = insertelement <4 x float> undef, float %81, i32 0 %84 = insertelement <4 x float> %83, float %82, i32 1 %85 = insertelement <4 x float> %84, float undef, i32 2 %86 = insertelement <4 x float> %85, float undef, i32 3 %87 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %86, i32 16, i32 0, i32 2) %88 = extractelement <4 x float> %87, i32 0 %89 = fsub float -0.000000e+00, %40 %90 = fadd float %88, %89 %91 = fsub float -0.000000e+00, %52 %92 = fadd float %88, %91 %93 = fsub float -0.000000e+00, %64 %94 = fadd float %88, %93 %95 = fsub float -0.000000e+00, %76 %96 = fadd float %88, %95 %97 = call float @fabs(float %90) %98 = call float @fabs(float %92) %99 = call float @fabs(float %94) %100 = call float @fabs(float %96) %101 = fcmp oge float %97, 0x3F689374C0000000 %102 = select i1 %101, float 1.000000e+00, float 0.000000e+00 %103 = fcmp oge float %98, 0x3F689374C0000000 %104 = select i1 %103, float 1.000000e+00, float 0.000000e+00 %105 = fcmp oge float %99, 0x3F689374C0000000 %106 = select i1 %105, float 1.000000e+00, float 0.000000e+00 %107 = fcmp oge float %100, 0x3F689374C0000000 %108 = select i1 %107, float 1.000000e+00, float 0.000000e+00 %109 = insertelement <4 x float> undef, float %102, i32 0 %110 = insertelement <4 x float> %109, float %104, i32 1 %111 = insertelement <4 x float> %110, float %106, i32 2 %112 = insertelement <4 x float> %111, float %108, i32 3 %113 = call float @llvm.AMDGPU.dp4(<4 x float> %112, <4 x float> ) %114 = fcmp oeq float %113, 0.000000e+00 %115 = select i1 %114, float 1.000000e+00, float 0.000000e+00 %116 = fcmp une float %115, 0.000000e+00 br i1 %116, label %IF, label %ENDIF IF: ; preds = %main_body call void @llvm.AMDGPU.kilp() br label %ENDIF ENDIF: ; preds = %main_body, %IF %117 = insertelement <4 x float> undef, float %102, i32 0 %118 = insertelement <4 x float> %117, float %104, i32 1 %119 = insertelement <4 x float> %118, float %106, i32 2 %120 = insertelement <4 x float> %119, float %108, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %120, i32 0, i32 0) ret void } ; Function Attrs: readnone declare <2 x float> @llvm.R600.interp.xy(i32, float, float) #1 ; Function Attrs: readnone declare <2 x float> @llvm.R600.interp.zw(i32, float, float) #1 ; Function Attrs: readnone declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32, i32) #1 ; Function Attrs: readonly declare float @fabs(float) #2 ; Function Attrs: readnone declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1 declare void @llvm.AMDGPU.kilp() declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } attributes #2 = { readonly } Shader Disassembly: ALU 23, @18, KC0[], KC1[] ; 00000012 A05C0000 TEX 4 @8 ; 00000008 80401000 ALU_PUSH_BEFORE 18, @42, KC0[], KC1[] ; 0000002A A4480000 JUMP @5 POP:1 ; 00000005 82800001 ALU_POP_AFTER 0, @61, KC0[], KC1[] ; 0000003D A8000000 EXPORT T0.XYZW ; C0000000 95200688 CF_END ; 00000000 88000000 PAD ; 00000000 00000000 Fetch clause starting at 8: ; TEX_SAMPLE T3.XYZW, T6.XY__ RID:16 SID:0 CT:NNNN ; 00061010 F00D1003 FC800000 00000000 TEX_SAMPLE T5.XYZW, T5.XY__ RID:16 SID:0 CT:NNNN ; 00051010 F00D1005 FC800000 00000000 TEX_SAMPLE T4.XYZW, T4.XY__ RID:16 SID:0 CT:NNNN ; 00041010 F00D1004 FC800000 00000000 TEX_SAMPLE T1.XYZW, T1.XY__ RID:16 SID:0 CT:NNNN ; 00011010 F00D1001 FC800000 00000000 TEX_SAMPLE T0.XYZW, T2.XY__ RID:16 SID:0 CT:NNNN ; 00021010 F00D1000 FC800000 00000000 ALU clause starting at 18: ; INTERP_XY T1.X, T0.Y, ARRAY_BASE, ; 00380400 00346B10 INTERP_XY T1.Y, T0.X, ARRAY_BASE, ; 00380000 20346B10 INTERP_XY T0.Z (MASKED), T0.Y, ARRAY_BASE, ; 00380400 40146B00 INTERP_XY * T0.W (MASKED), T0.X, ARRAY_BASE, ; 80380000 60146B00 INTERP_XY T2.X, T0.Y, ARRAY_BASE, ; 00382400 00546B10 INTERP_XY T2.Y, T0.X, ARRAY_BASE, ; 00382000 20546B10 INTERP_XY T0.Z (MASKED), T0.Y, ARRAY_BASE, ; 00382400 40146B00 INTERP_XY * T0.W (MASKED), T0.X, ARRAY_BASE, ; 80382000 60146B00 INTERP_ZW T0.X (MASKED), T0.Y, ARRAY_BASE, ; 00382400 00146B80 INTERP_ZW T0.Y (MASKED), T0.X, ARRAY_BASE, ; 00382000 20146B80 INTERP_ZW T3.Z, T0.Y, ARRAY_BASE, ; 00382400 40746B90 INTERP_ZW * T3.W, T0.X, ARRAY_BASE, ; 80382000 60746B90 MOV * T4.X, PV.Z, ; 800008FE 00800C90 INTERP_XY T5.X, T0.Y, ARRAY_BASE, ; 00384400 00B46B10 INTERP_XY T5.Y, T0.X, ARRAY_BASE, ; 00384000 20B46B10 INTERP_XY T0.Z (MASKED), T0.Y, ARRAY_BASE, ; 00384400 40146B00 INTERP_XY * T0.W (MASKED), T0.X, ARRAY_BASE, ; 80384000 60146B00 INTERP_ZW T0.X (MASKED), T0.Y, ARRAY_BASE, ; 00384400 00146B80 INTERP_ZW T0.Y (MASKED), T0.X, ARRAY_BASE, ; 00384000 20146B80 INTERP_ZW T0.Z, T0.Y, ARRAY_BASE, ; 00384400 40146B90 INTERP_ZW * T0.W, T0.X, ARRAY_BASE, ; 80384000 60146B90 MOV T6.X, PV.Z, ; 000008FE 00C00C90 MOV * T4.Y, T3.W, ; 80000C03 20800C90 MOV * T6.Y, T0.W, ; 80000C00 20C00C90 ALU clause starting at 42: ; ADD * T0.W, T1.X, -T0.X, ; 82000001 60000010 SETGE T0.X, |PV.W|, literal.x, ; 001FACFE 00000511 ADD * T2.W, T1.X, -T4.X, ; 82008001 60400010 994352038(3.000000e-03), 0(0.000000e+00) ; 3B449BA6 00000000 SETGE T0.Y, |PV.W|, literal.x, ; 001FACFE 20000511 ADD * T2.W, T1.X, -T5.X, ; 8200A001 60400010 994352038(3.000000e-03), 0(0.000000e+00) ; 3B449BA6 00000000 SETGE T0.Z, |PV.W|, literal.x, ; 001FACFE 40000511 ADD * T1.W, T1.X, -T3.X, ; 82006001 60200010 994352038(3.000000e-03), 0(0.000000e+00) ; 3B449BA6 00000000 SETGE * T0.W, |PV.W|, literal.x, ; 801FACFE 60000511 994352038(3.000000e-03), 0(0.000000e+00) ; 3B449BA6 00000000 DOT4 T1.X, T0.X, 1.0, ; 001F2000 00205F10 DOT4 T1.Y (MASKED), T0.Y, 1.0, ; 001F2400 20205F00 DOT4 T1.Z (MASKED), T0.Z, 1.0, ; 001F2800 40205F00 DOT4 * T1.W (MASKED), T0.W, 1.0, ; 801F2C00 60205F00 SETE * T1.W, PV.X, 0.0, ; 801F00FE 60200410 SETE_DX10 * T1.W, PV.W, 0.0, ; 801F0CFE 60200610 PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002104 ALU clause starting at 61: ; KILLGT * T1.X (MASKED), 1.0, 0.0, ; 801F00F9 00201680 ===== SHADER #99 ======================================== PS/CAYMAN/CAYMAN ===== ===== 124 dw ===== 7 gprs ===== 1 stack ======================================== 0000 00000012 a05c0000 ALU 24 @36 0036 00380400 00346b10 1 x: INTERP_XY R1.x, R0.y, Param0.x VEC_210 0038 00380000 20346b10 y: INTERP_XY R1.y, R0.x, Param0.x VEC_210 0040 00380400 40146b00 z: INTERP_XY __.z, R0.y, Param0.x VEC_210 0042 80380000 60146b00 w: INTERP_XY __.w, R0.x, Param0.x VEC_210 0044 00382400 00546b10 2 x: INTERP_XY R2.x, R0.y, Param1.x VEC_210 0046 00382000 20546b10 y: INTERP_XY R2.y, R0.x, Param1.x VEC_210 0048 00382400 40146b00 z: INTERP_XY __.z, R0.y, Param1.x VEC_210 0050 80382000 60146b00 w: INTERP_XY __.w, R0.x, Param1.x VEC_210 0052 00382400 00146b80 3 x: INTERP_ZW __.x, R0.y, Param1.x VEC_210 0054 00382000 20146b80 y: INTERP_ZW __.y, R0.x, Param1.x VEC_210 0056 00382400 40746b90 z: INTERP_ZW R3.z, R0.y, Param1.x VEC_210 0058 80382000 60746b90 w: INTERP_ZW R3.w, R0.x, Param1.x VEC_210 0060 800008fe 00800c90 4 x: MOV R4.x, PV.z 0062 00384400 00b46b10 5 x: INTERP_XY R5.x, R0.y, Param2.x VEC_210 0064 00384000 20b46b10 y: INTERP_XY R5.y, R0.x, Param2.x VEC_210 0066 00384400 40146b00 z: INTERP_XY __.z, R0.y, Param2.x VEC_210 0068 80384000 60146b00 w: INTERP_XY __.w, R0.x, Param2.x VEC_210 0070 00384400 00146b80 6 x: INTERP_ZW __.x, R0.y, Param2.x VEC_210 0072 00384000 20146b80 y: INTERP_ZW __.y, R0.x, Param2.x VEC_210 0074 00384400 40146b90 z: INTERP_ZW R0.z, R0.y, Param2.x VEC_210 0076 80384000 60146b90 w: INTERP_ZW R0.w, R0.x, Param2.x VEC_210 0078 000008fe 00c00c90 7 x: MOV R6.x, PV.z 0080 80000c03 20800c90 y: MOV R4.y, R3.w 0082 80000c00 20c00c90 8 y: MOV R6.y, R0.w 0002 00000008 80401000 TEX 5 @16 0016 00061010 f00d1003 fc800000 SAMPLE R3.xyzw, R6.xy__, RID:16, SID:0 CT:NNNN 0020 00051010 f00d1005 fc800000 SAMPLE R5.xyzw, R5.xy__, RID:16, SID:0 CT:NNNN 0024 00041010 f00d1004 fc800000 SAMPLE R4.xyzw, R4.xy__, RID:16, SID:0 CT:NNNN 0028 00011010 f00d1001 fc800000 SAMPLE R1.xyzw, R1.xy__, RID:16, SID:0 CT:NNNN 0032 00021010 f00d1000 fc800000 SAMPLE R0.xyzw, R2.xy__, RID:16, SID:0 CT:NNNN 0004 0000002a a4480000 ALU_PUSH_BEFORE 19 @84 0084 82000001 60000010 9 w: ADD R0.w, R1.x, -R0.x 0086 001facfe 00000511 10 x: SETGE R0.x, |PV.w|, [0x3b449ba6 0.003].x 0088 82008001 60400010 w: ADD R2.w, R1.x, -R4.x 0090 3b449ba6 0092 001facfe 20000511 11 y: SETGE R0.y, |PV.w|, [0x3b449ba6 0.003].x 0094 8200a001 60400010 w: ADD R2.w, R1.x, -R5.x 0096 3b449ba6 0098 001facfe 40000511 12 z: SETGE R0.z, |PV.w|, [0x3b449ba6 0.003].x 0100 82006001 60200010 w: ADD R1.w, R1.x, -R3.x 0102 3b449ba6 0104 801facfe 60000511 13 w: SETGE R0.w, |PV.w|, [0x3b449ba6 0.003].x 0106 3b449ba6 0108 001f2000 00205f10 14 x: DOT4 R1.x, R0.x, 1.0 0110 001f2400 20205f00 y: DOT4 __.y, R0.y, 1.0 0112 001f2800 40205f00 z: DOT4 __.z, R0.z, 1.0 0114 801f2c00 60205f00 w: DOT4 __.w, R0.w, 1.0 0116 801f00fe 60200410 15 w: SETE R1.w, PV.x, 0 0118 801f0cfe 60200610 16 w: SETE_DX10 R1.w, PV.w, 0 0120 801f0cfe 00002104 17 M x: PRED_SETE_INT __.x, PV.w, 0 0006 00000005 82800001 JUMP @10 POP:1 0008 0000003d a8000000 ALU_POP_AFTER 1 @122 0122 801f00f9 00201680 18 x: KILLGT __.x, 1.0, 0 0010 c0000000 95200688 EXPORT_DONE PIXEL 0 R0.xyzw 0012 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #99 OPT ==================================== PS/CAYMAN/CAYMAN ===== ===== 100 dw ===== 4 gprs ===== 0 stack ======================================== 0000 00000005 a04c0000 ALU 20 @10 0010 00382400 00346b10 1 x: INTERP_XY R1.x, R0.y, Param1.x VEC_210 0012 00b82000 20346b10 y: INTERP_XY R1.y, R0.x, Param1.y VEC_210 0014 01382400 40146b00 z: INTERP_XY __.z, R0.y, Param1.z VEC_210 0016 81b82000 60146b00 w: INTERP_XY __.w, R0.x, Param1.w VEC_210 0018 00382400 00146b80 2 x: INTERP_ZW __.x, R0.y, Param1.x VEC_210 0020 00b82000 20146b80 y: INTERP_ZW __.y, R0.x, Param1.y VEC_210 0022 01382400 40146b90 z: INTERP_ZW R0.z, R0.y, Param1.z VEC_210 0024 81b82000 60146b90 w: INTERP_ZW R0.w, R0.x, Param1.w VEC_210 0026 00384400 00746b10 3 x: INTERP_XY R3.x, R0.y, Param2.x VEC_210 0028 00b84000 20746b10 y: INTERP_XY R3.y, R0.x, Param2.y VEC_210 0030 01384400 40146b00 z: INTERP_XY __.z, R0.y, Param2.z VEC_210 0032 81b84000 60146b00 w: INTERP_XY __.w, R0.x, Param2.w VEC_210 0034 00380400 00546b10 4 x: INTERP_XY R2.x, R0.y, Param0.x VEC_210 0036 00b80000 20546b10 y: INTERP_XY R2.y, R0.x, Param0.y VEC_210 0038 01380400 40146b00 z: INTERP_XY __.z, R0.y, Param0.z VEC_210 0040 81b80000 60146b00 w: INTERP_XY __.w, R0.x, Param0.w VEC_210 0042 00384400 00146b80 5 x: INTERP_ZW __.x, R0.y, Param2.x VEC_210 0044 00b84000 20146b80 y: INTERP_ZW __.y, R0.x, Param2.y VEC_210 0046 01384400 40346b90 z: INTERP_ZW R1.z, R0.y, Param2.z VEC_210 0048 81b84000 60346b90 w: INTERP_ZW R1.w, R0.x, Param2.w VEC_210 0002 0000001a 80401000 TEX 5 @52 0052 00011010 f003fe01 fda00000 SAMPLE R1.___x, R1.zw__, RID:16, SID:0 CT:NNNN 0056 00021010 f01f8e00 fc800000 SAMPLE R0._x__, R2.xy__, RID:16, SID:0 CT:NNNN 0060 00031010 f01c7e01 fc800000 SAMPLE R1.__x_, R3.xy__, RID:16, SID:0 CT:NNNN 0064 00001010 f01c7e00 fda00000 SAMPLE R0.__x_, R0.zw__, RID:16, SID:0 CT:NNNN 0068 00011010 f01ff000 fc800000 SAMPLE R0.x___, R1.xy__, RID:16, SID:0 CT:NNNN 0004 00000024 a0340000 ALU 14 @72 0072 03002400 0f840010 6 x: ADD T0.x, R0.y, -R1.z VEC_021 0074 03000400 2f800010 y: ADD T0.y, R0.y, -R0.z 0076 02000400 4f800010 z: ADD T0.z, R0.y, -R0.x 0078 83802400 6f800010 w: ADD T0.w, R0.y, -R1.w 0080 001fa87c 00000511 7 x: SETGE R0.x, |T0.z|, [0x3b449ba6 0.003].x 0082 001fa47c 20000511 y: SETGE R0.y, |T0.y|, [0x3b449ba6 0.003].x 0084 001fa07c 40000511 z: SETGE R0.z, |T0.x|, [0x3b449ba6 0.003].x 0086 801fac7c 60000511 w: SETGE R0.w, |T0.w|, [0x3b449ba6 0.003].x 0088 3b449ba6 0090 001f2000 00005f00 8 x: DOT4 __.x, R0.x, 1.0 0092 001f2400 20005f00 y: DOT4 __.y, R0.y, 1.0 0094 001f2800 40005f00 z: DOT4 __.z, R0.z, 1.0 0096 801f2c00 6f805f10 w: DOT4 T0.w, R0.w, 1.0 0098 801f0c7c 00001600 9 x: KILLE __.x, T0.w, 0 0006 c0000000 95000688 EXPORT_DONE PIXEL 0 R0.xyzw 0008 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL SAMP[1] DCL SAMP[2] DCL CONST[0] DCL TEMP[0..6] IMM[0] FLT32 { 0.0000, -0.2500, 0.0061, 0.5000} IMM[1] FLT32 { -1.5000, -2.0000, 0.9000, 1.5000} IMM[2] FLT32 { 2.0000, 1.0000, 4.0000, 33.0000} IMM[3] FLT32 { 8.0000, 0.0000, 0.0000, 0.0000} 0: MOV TEMP[0], IMM[0].xxxx 1: TEX TEMP[1], IN[0].xyyy, SAMP[1], 2D 2: MOV TEMP[2].x, TEMP[1] 3: SNE TEMP[3].x, TEMP[1].yyyy, IMM[0].xxxx 4: IF TEMP[3].xxxx :76 5: MOV TEMP[1].xy, IN[0].xyxx 6: MOV TEMP[4].x, IMM[1].xxxx 7: BGNLOOP :24 8: MUL TEMP[5].x, IMM[1].yyyy, IMM[3].xxxx 9: SLE TEMP[6].x, TEMP[4].xxxx, TEMP[5].xxxx 10: IF TEMP[6].xxxx :12 11: BRK 12: ENDIF 13: MOV TEMP[4].y, IMM[0].xxxx 14: MAD TEMP[3].xyz, CONST[0].xyyy, TEMP[4].xyyy, TEMP[1].xyyy 15: MOV TEMP[3].w, IMM[0].xxxx 16: TXL TEMP[5], TEMP[3], SAMP[2], 2D 17: MOV TEMP[3].x, TEMP[5].yyyy 18: SLT TEMP[6].x, TEMP[5].yyyy, IMM[1].zzzz 19: IF TEMP[6].xxxx :21 20: BRK 21: ENDIF 22: ADD TEMP[6].x, TEMP[4].xxxx, IMM[1].yyyy 23: MOV TEMP[4].x, TEMP[6].xxxx 24: ENDLOOP :7 25: ADD TEMP[1].x, TEMP[4].xxxx, IMM[1].wwww 26: MAD TEMP[6].x, -IMM[2].xxxx, TEMP[3].xxxx, TEMP[1].xxxx 27: MUL TEMP[1].x, IMM[1].yyyy, IMM[3].xxxx 28: MAX TEMP[4].x, TEMP[6].xxxx, TEMP[1].xxxx 29: MOV TEMP[1].x, TEMP[4].xxxx 30: MOV TEMP[3].xy, IN[0].xyxx 31: MOV TEMP[5].x, IMM[1].wwww 32: BGNLOOP :49 33: MUL TEMP[6].x, IMM[2].xxxx, IMM[3].xxxx 34: SGE TEMP[4].x, TEMP[5].xxxx, TEMP[6].xxxx 35: IF TEMP[4].xxxx :37 36: BRK 37: ENDIF 38: MOV TEMP[5].y, IMM[0].xxxx 39: MAD TEMP[4].xyz, CONST[0].xyyy, TEMP[5].xyyy, TEMP[3].xyyy 40: MOV TEMP[4].w, IMM[0].xxxx 41: TXL TEMP[6].xy, TEMP[4], SAMP[2], 2D 42: MOV TEMP[4].x, TEMP[6].yyyy 43: SLT TEMP[0].x, TEMP[6].yyyy, IMM[1].zzzz 44: IF TEMP[0].xxxx :46 45: BRK 46: ENDIF 47: ADD TEMP[6].x, TEMP[5].xxxx, IMM[2].xxxx 48: MOV TEMP[5].x, TEMP[6].xxxx 49: ENDLOOP :32 50: ADD TEMP[3].x, TEMP[5].xxxx, IMM[1].xxxx 51: MAD TEMP[5].x, IMM[2].xxxx, TEMP[4].xxxx, TEMP[3].xxxx 52: MUL TEMP[3].x, IMM[2].xxxx, IMM[3].xxxx 53: MIN TEMP[4].x, TEMP[5].xxxx, TEMP[3].xxxx 54: MOV TEMP[3].x, TEMP[1].xxxx 55: MOV TEMP[3].y, TEMP[4].xxxx 56: MOV TEMP[5].yw, IMM[0].yyyy 57: MOV TEMP[5].x, TEMP[1].xxxx 58: ADD TEMP[1].x, TEMP[4].xxxx, IMM[2].yyyy 59: MOV TEMP[5].z, TEMP[1].xxxx 60: MAD TEMP[1], TEMP[5], CONST[0].xyxy, IN[0].xyxy 61: MOV TEMP[4], TEMP[1].xyyy 62: MOV TEMP[4].w, IMM[0].xxxx 63: TXL TEMP[5].x, TEMP[4], SAMP[2], 2D 64: MOV TEMP[4].x, TEMP[5].xxxx 65: MOV TEMP[5], TEMP[1].zwww 66: MOV TEMP[5].w, IMM[0].xxxx 67: TXL TEMP[1].x, TEMP[5], SAMP[2], 2D 68: MOV TEMP[4].y, TEMP[1].xxxx 69: MUL TEMP[5].xy, IMM[2].zzzz, TEMP[4].xyyy 70: ROUND TEMP[1].xy, TEMP[5].xyyy 71: ABS TEMP[4].xy, TEMP[3].xyyy 72: MAD TEMP[3].xy, IMM[2].wwww, TEMP[1].xyyy, TEMP[4].xyyy 73: MUL TEMP[5].xyz, TEMP[3].xyyy, IMM[0].zzzz 74: MOV TEMP[5].w, IMM[0].xxxx 75: TXL TEMP[0].xy, TEMP[5], SAMP[0], 2D 76: ENDIF 77: SNE TEMP[1].x, TEMP[2].xxxx, IMM[0].xxxx 78: IF TEMP[1].xxxx :151 79: MOV TEMP[1].xy, IN[0].xyxx 80: MOV TEMP[3].x, IMM[1].xxxx 81: BGNLOOP :98 82: MUL TEMP[4].x, IMM[1].yyyy, IMM[3].xxxx 83: SLE TEMP[5].x, TEMP[3].xxxx, TEMP[4].xxxx 84: IF TEMP[5].xxxx :86 85: BRK 86: ENDIF 87: MOV TEMP[3].y, IMM[0].xxxx 88: MAD TEMP[5].xyz, CONST[0].xyyy, TEMP[3].yxxx, TEMP[1].xyyy 89: MOV TEMP[5].w, IMM[0].xxxx 90: TXL TEMP[4], TEMP[5], SAMP[2], 2D 91: MOV TEMP[2].x, TEMP[4].xxxx 92: SLT TEMP[5].x, TEMP[4].xxxx, IMM[1].zzzz 93: IF TEMP[5].xxxx :95 94: BRK 95: ENDIF 96: ADD TEMP[4].x, TEMP[3].xxxx, IMM[1].yyyy 97: MOV TEMP[3].x, TEMP[4].xxxx 98: ENDLOOP :81 99: ADD TEMP[1].x, TEMP[3].xxxx, IMM[1].wwww 100: MAD TEMP[6].x, -IMM[2].xxxx, TEMP[2].xxxx, TEMP[1].xxxx 101: MUL TEMP[1].x, IMM[1].yyyy, IMM[3].xxxx 102: MAX TEMP[3].x, TEMP[6].xxxx, TEMP[1].xxxx 103: MOV TEMP[1].x, TEMP[3].xxxx 104: MOV TEMP[2].xy, IN[0].xyxx 105: MOV TEMP[4].x, IMM[1].wwww 106: BGNLOOP :123 107: MUL TEMP[5].x, IMM[2].xxxx, IMM[3].xxxx 108: SGE TEMP[6].x, TEMP[4].xxxx, TEMP[5].xxxx 109: IF TEMP[6].xxxx :111 110: BRK 111: ENDIF 112: MOV TEMP[4].y, IMM[0].xxxx 113: MAD TEMP[5].xyz, CONST[0].xyyy, TEMP[4].yxxx, TEMP[2].xyyy 114: MOV TEMP[5].w, IMM[0].xxxx 115: TXL TEMP[6], TEMP[5], SAMP[2], 2D 116: MOV TEMP[3].x, TEMP[6].xxxx 117: SLT TEMP[5].x, TEMP[6].xxxx, IMM[1].zzzz 118: IF TEMP[5].xxxx :120 119: BRK 120: ENDIF 121: ADD TEMP[6].x, TEMP[4].xxxx, IMM[2].xxxx 122: MOV TEMP[4].x, TEMP[6].xxxx 123: ENDLOOP :106 124: ADD TEMP[2].x, TEMP[4].xxxx, IMM[1].xxxx 125: MAD TEMP[4].x, IMM[2].xxxx, TEMP[3].xxxx, TEMP[2].xxxx 126: MUL TEMP[2].x, IMM[2].xxxx, IMM[3].xxxx 127: MIN TEMP[3].x, TEMP[4].xxxx, TEMP[2].xxxx 128: MOV TEMP[2].x, TEMP[1].xxxx 129: MOV TEMP[2].y, TEMP[3].xxxx 130: MOV TEMP[4].xz, IMM[0].yyyy 131: MOV TEMP[4].y, TEMP[1].xxxx 132: ADD TEMP[1].x, TEMP[3].xxxx, IMM[2].yyyy 133: MOV TEMP[4].w, TEMP[1].xxxx 134: MAD TEMP[1], TEMP[4], CONST[0].xyxy, IN[0].xyxy 135: MOV TEMP[3], TEMP[1].xyyy 136: MOV TEMP[3].w, IMM[0].xxxx 137: TXL TEMP[4].y, TEMP[3], SAMP[2], 2D 138: MOV TEMP[3].x, TEMP[4].yyyy 139: MOV TEMP[4], TEMP[1].zwww 140: MOV TEMP[4].w, IMM[0].xxxx 141: TXL TEMP[1].y, TEMP[4], SAMP[2], 2D 142: MOV TEMP[3].y, TEMP[1].yyyy 143: MUL TEMP[4].xy, IMM[2].zzzz, TEMP[3].xyyy 144: ROUND TEMP[1].xy, TEMP[4].xyyy 145: ABS TEMP[3].xy, TEMP[2].xyyy 146: MAD TEMP[2].xy, IMM[2].wwww, TEMP[1].xyyy, TEMP[3].xyyy 147: MUL TEMP[3].xyz, TEMP[2].xyyy, IMM[0].zzzz 148: MOV TEMP[3].w, IMM[0].xxxx 149: TXL TEMP[1].xy, TEMP[3], SAMP[0], 2D 150: MOV TEMP[0].zw, TEMP[1].yyxy 151: ENDIF 152: MOV OUT[0], TEMP[0] 153: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg) #0 { main_body: %2 = extractelement <4 x float> %0, i32 0 %3 = extractelement <4 x float> %0, i32 1 %4 = call <2 x float> @llvm.R600.interp.xy(i32 0, float %2, float %3) %5 = call <2 x float> @llvm.R600.interp.zw(i32 0, float %2, float %3) %6 = shufflevector <2 x float> %4, <2 x float> %5, <4 x i32> %7 = extractelement <4 x float> %6, i32 0 %8 = extractelement <4 x float> %6, i32 1 %9 = insertelement <4 x float> undef, float %7, i32 0 %10 = insertelement <4 x float> %9, float %8, i32 1 %11 = insertelement <4 x float> %10, float %8, i32 2 %12 = insertelement <4 x float> %11, float %8, i32 3 %13 = extractelement <4 x float> %12, i32 0 %14 = extractelement <4 x float> %12, i32 1 %15 = insertelement <4 x float> undef, float %13, i32 0 %16 = insertelement <4 x float> %15, float %14, i32 1 %17 = insertelement <4 x float> %16, float undef, i32 2 %18 = insertelement <4 x float> %17, float undef, i32 3 %19 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %18, i32 17, i32 1, i32 2) %20 = extractelement <4 x float> %19, i32 0 %21 = extractelement <4 x float> %19, i32 1 %22 = fcmp une float %21, 0.000000e+00 %23 = select i1 %22, float 1.000000e+00, float 0.000000e+00 %24 = fcmp une float %23, 0.000000e+00 br i1 %24, label %LOOP, label %ENDIF ENDIF: ; preds = %main_body, %ENDLOOP34 %temp.0 = phi float [ %113, %ENDLOOP34 ], [ 0.000000e+00, %main_body ] %temp1.0 = phi float [ %114, %ENDLOOP34 ], [ 0.000000e+00, %main_body ] %25 = fcmp une float %20, 0.000000e+00 %26 = select i1 %25, float 1.000000e+00, float 0.000000e+00 %27 = fcmp une float %26, 0.000000e+00 br i1 %27, label %LOOP46, label %ENDIF42 LOOP: ; preds = %main_body, %ENDIF31 %temp12.0 = phi float [ %53, %ENDIF31 ], [ %23, %main_body ] %temp16.0 = phi float [ %57, %ENDIF31 ], [ -1.500000e+00, %main_body ] %28 = fcmp ole float %temp16.0, -1.600000e+01 %29 = select i1 %28, float 1.000000e+00, float 0.000000e+00 %30 = fcmp une float %29, 0.000000e+00 br i1 %30, label %ENDLOOP, label %ENDIF28 ENDLOOP: ; preds = %ENDIF28, %LOOP %temp12.1 = phi float [ %temp12.0, %LOOP ], [ %53, %ENDIF28 ] %31 = fadd float %temp16.0, 1.500000e+00 %32 = fmul float -2.000000e+00, %temp12.1 %33 = fadd float %32, %31 %34 = fcmp uge float %33, -1.600000e+01 %35 = select i1 %34, float %33, float -1.600000e+01 br label %LOOP35 ENDIF28: ; preds = %LOOP %36 = load <4 x float> addrspace(8)* null %37 = extractelement <4 x float> %36, i32 0 %38 = fmul float %37, %temp16.0 %39 = fadd float %38, %7 %40 = load <4 x float> addrspace(8)* null %41 = extractelement <4 x float> %40, i32 1 %42 = fmul float %41, 0.000000e+00 %43 = fadd float %42, %8 %44 = load <4 x float> addrspace(8)* null %45 = extractelement <4 x float> %44, i32 1 %46 = fmul float %45, 0.000000e+00 %47 = fadd float %46, %8 %48 = insertelement <4 x float> undef, float %39, i32 0 %49 = insertelement <4 x float> %48, float %43, i32 1 %50 = insertelement <4 x float> %49, float %47, i32 2 %51 = insertelement <4 x float> %50, float 0.000000e+00, i32 3 %52 = call <4 x float> @llvm.AMDGPU.txl(<4 x float> %51, i32 18, i32 2, i32 2) %53 = extractelement <4 x float> %52, i32 1 %54 = fcmp olt float %53, 0x3FECCCCCC0000000 %55 = select i1 %54, float 1.000000e+00, float 0.000000e+00 %56 = fcmp une float %55, 0.000000e+00 br i1 %56, label %ENDLOOP, label %ENDIF31 ENDIF31: ; preds = %ENDIF28 %57 = fadd float %temp16.0, -2.000000e+00 br label %LOOP LOOP35: ; preds = %ENDIF39, %ENDLOOP %temp20.0 = phi float [ 1.500000e+00, %ENDLOOP ], [ %136, %ENDIF39 ] %58 = fcmp oge float %temp20.0, 1.600000e+01 %59 = select i1 %58, float 1.000000e+00, float 0.000000e+00 %60 = fcmp une float %59, 0.000000e+00 br i1 %60, label %ENDLOOP34, label %ENDIF36 ENDLOOP34: ; preds = %ENDIF36, %LOOP35 %temp16.1 = phi float [ %59, %LOOP35 ], [ %132, %ENDIF36 ] %61 = fadd float %temp20.0, -1.500000e+00 %62 = fmul float 2.000000e+00, %temp16.1 %63 = fadd float %62, %61 %64 = fcmp uge float %63, 1.600000e+01 %65 = select i1 %64, float 1.600000e+01, float %63 %66 = fadd float %65, 1.000000e+00 %67 = load <4 x float> addrspace(8)* null %68 = extractelement <4 x float> %67, i32 0 %69 = fmul float %35, %68 %70 = fadd float %69, %7 %71 = load <4 x float> addrspace(8)* null %72 = extractelement <4 x float> %71, i32 1 %73 = fmul float -2.500000e-01, %72 %74 = fadd float %73, %8 %75 = load <4 x float> addrspace(8)* null %76 = extractelement <4 x float> %75, i32 0 %77 = fmul float %66, %76 %78 = fadd float %77, %7 %79 = load <4 x float> addrspace(8)* null %80 = extractelement <4 x float> %79, i32 1 %81 = fmul float -2.500000e-01, %80 %82 = fadd float %81, %8 %83 = insertelement <4 x float> undef, float %70, i32 0 %84 = insertelement <4 x float> %83, float %74, i32 1 %85 = insertelement <4 x float> %84, float %74, i32 2 %86 = insertelement <4 x float> %85, float 0.000000e+00, i32 3 %87 = call <4 x float> @llvm.AMDGPU.txl(<4 x float> %86, i32 18, i32 2, i32 2) %88 = extractelement <4 x float> %87, i32 0 %89 = insertelement <4 x float> undef, float %78, i32 0 %90 = insertelement <4 x float> %89, float %82, i32 1 %91 = insertelement <4 x float> %90, float %82, i32 2 %92 = insertelement <4 x float> %91, float 0.000000e+00, i32 3 %93 = call <4 x float> @llvm.AMDGPU.txl(<4 x float> %92, i32 18, i32 2, i32 2) %94 = extractelement <4 x float> %93, i32 0 %95 = fmul float 4.000000e+00, %88 %96 = fmul float 4.000000e+00, %94 %97 = call float @llvm.AMDIL.round.nearest.(float %95) %98 = call float @llvm.AMDIL.round.nearest.(float %96) %99 = call float @fabs(float %35) %100 = call float @fabs(float %65) %101 = fmul float 3.300000e+01, %97 %102 = fadd float %101, %99 %103 = fmul float 3.300000e+01, %98 %104 = fadd float %103, %100 %105 = fmul float %102, 0x3F78F9C140000000 %106 = fmul float %104, 0x3F78F9C140000000 %107 = fmul float %104, 0x3F78F9C140000000 %108 = insertelement <4 x float> undef, float %105, i32 0 %109 = insertelement <4 x float> %108, float %106, i32 1 %110 = insertelement <4 x float> %109, float %107, i32 2 %111 = insertelement <4 x float> %110, float 0.000000e+00, i32 3 %112 = call <4 x float> @llvm.AMDGPU.txl(<4 x float> %111, i32 16, i32 0, i32 2) %113 = extractelement <4 x float> %112, i32 0 %114 = extractelement <4 x float> %112, i32 1 br label %ENDIF ENDIF36: ; preds = %LOOP35 %115 = load <4 x float> addrspace(8)* null %116 = extractelement <4 x float> %115, i32 0 %117 = fmul float %116, %temp20.0 %118 = fadd float %117, %7 %119 = load <4 x float> addrspace(8)* null %120 = extractelement <4 x float> %119, i32 1 %121 = fmul float %120, 0.000000e+00 %122 = fadd float %121, %8 %123 = load <4 x float> addrspace(8)* null %124 = extractelement <4 x float> %123, i32 1 %125 = fmul float %124, 0.000000e+00 %126 = fadd float %125, %8 %127 = insertelement <4 x float> undef, float %118, i32 0 %128 = insertelement <4 x float> %127, float %122, i32 1 %129 = insertelement <4 x float> %128, float %126, i32 2 %130 = insertelement <4 x float> %129, float 0.000000e+00, i32 3 %131 = call <4 x float> @llvm.AMDGPU.txl(<4 x float> %130, i32 18, i32 2, i32 2) %132 = extractelement <4 x float> %131, i32 1 %133 = fcmp olt float %132, 0x3FECCCCCC0000000 %134 = select i1 %133, float 1.000000e+00, float 0.000000e+00 %135 = fcmp une float %134, 0.000000e+00 br i1 %135, label %ENDLOOP34, label %ENDIF39 ENDIF39: ; preds = %ENDIF36 %136 = fadd float %temp20.0, 2.000000e+00 br label %LOOP35 ENDIF42: ; preds = %ENDIF, %ENDLOOP53 %temp2.0 = phi float [ %226, %ENDLOOP53 ], [ 0.000000e+00, %ENDIF ] %temp3.0 = phi float [ %227, %ENDLOOP53 ], [ 0.000000e+00, %ENDIF ] %137 = insertelement <4 x float> undef, float %temp.0, i32 0 %138 = insertelement <4 x float> %137, float %temp1.0, i32 1 %139 = insertelement <4 x float> %138, float %temp2.0, i32 2 %140 = insertelement <4 x float> %139, float %temp3.0, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %140, i32 0, i32 0) ret void LOOP46: ; preds = %ENDIF, %ENDIF50 %temp8.0 = phi float [ %166, %ENDIF50 ], [ %20, %ENDIF ] %temp12.2 = phi float [ %170, %ENDIF50 ], [ -1.500000e+00, %ENDIF ] %141 = fcmp ole float %temp12.2, -1.600000e+01 %142 = select i1 %141, float 1.000000e+00, float 0.000000e+00 %143 = fcmp une float %142, 0.000000e+00 br i1 %143, label %ENDLOOP45, label %ENDIF47 ENDLOOP45: ; preds = %ENDIF47, %LOOP46 %temp8.1 = phi float [ %temp8.0, %LOOP46 ], [ %166, %ENDIF47 ] %144 = fadd float %temp12.2, 1.500000e+00 %145 = fmul float -2.000000e+00, %temp8.1 %146 = fadd float %145, %144 %147 = fcmp uge float %146, -1.600000e+01 %148 = select i1 %147, float %146, float -1.600000e+01 br label %LOOP54 ENDIF47: ; preds = %LOOP46 %149 = load <4 x float> addrspace(8)* null %150 = extractelement <4 x float> %149, i32 0 %151 = fmul float %150, 0.000000e+00 %152 = fadd float %151, %7 %153 = load <4 x float> addrspace(8)* null %154 = extractelement <4 x float> %153, i32 1 %155 = fmul float %154, %temp12.2 %156 = fadd float %155, %8 %157 = load <4 x float> addrspace(8)* null %158 = extractelement <4 x float> %157, i32 1 %159 = fmul float %158, %temp12.2 %160 = fadd float %159, %8 %161 = insertelement <4 x float> undef, float %152, i32 0 %162 = insertelement <4 x float> %161, float %156, i32 1 %163 = insertelement <4 x float> %162, float %160, i32 2 %164 = insertelement <4 x float> %163, float 0.000000e+00, i32 3 %165 = call <4 x float> @llvm.AMDGPU.txl(<4 x float> %164, i32 18, i32 2, i32 2) %166 = extractelement <4 x float> %165, i32 0 %167 = fcmp olt float %166, 0x3FECCCCCC0000000 %168 = select i1 %167, float 1.000000e+00, float 0.000000e+00 %169 = fcmp une float %168, 0.000000e+00 br i1 %169, label %ENDLOOP45, label %ENDIF50 ENDIF50: ; preds = %ENDIF47 %170 = fadd float %temp12.2, -2.000000e+00 br label %LOOP46 LOOP54: ; preds = %ENDIF58, %ENDLOOP45 %temp12.3 = phi float [ %148, %ENDLOOP45 ], [ %245, %ENDIF58 ] %temp16.2 = phi float [ 1.500000e+00, %ENDLOOP45 ], [ %249, %ENDIF58 ] %171 = fcmp oge float %temp16.2, 1.600000e+01 %172 = select i1 %171, float 1.000000e+00, float 0.000000e+00 %173 = fcmp une float %172, 0.000000e+00 br i1 %173, label %ENDLOOP53, label %ENDIF55 ENDLOOP53: ; preds = %ENDIF55, %LOOP54 %temp12.4 = phi float [ %temp12.3, %LOOP54 ], [ %245, %ENDIF55 ] %174 = fadd float %temp16.2, -1.500000e+00 %175 = fmul float 2.000000e+00, %temp12.4 %176 = fadd float %175, %174 %177 = fcmp uge float %176, 1.600000e+01 %178 = select i1 %177, float 1.600000e+01, float %176 %179 = fadd float %178, 1.000000e+00 %180 = load <4 x float> addrspace(8)* null %181 = extractelement <4 x float> %180, i32 0 %182 = fmul float -2.500000e-01, %181 %183 = fadd float %182, %7 %184 = load <4 x float> addrspace(8)* null %185 = extractelement <4 x float> %184, i32 1 %186 = fmul float %148, %185 %187 = fadd float %186, %8 %188 = load <4 x float> addrspace(8)* null %189 = extractelement <4 x float> %188, i32 0 %190 = fmul float -2.500000e-01, %189 %191 = fadd float %190, %7 %192 = load <4 x float> addrspace(8)* null %193 = extractelement <4 x float> %192, i32 1 %194 = fmul float %179, %193 %195 = fadd float %194, %8 %196 = insertelement <4 x float> undef, float %183, i32 0 %197 = insertelement <4 x float> %196, float %187, i32 1 %198 = insertelement <4 x float> %197, float %187, i32 2 %199 = insertelement <4 x float> %198, float 0.000000e+00, i32 3 %200 = call <4 x float> @llvm.AMDGPU.txl(<4 x float> %199, i32 18, i32 2, i32 2) %201 = extractelement <4 x float> %200, i32 1 %202 = insertelement <4 x float> undef, float %191, i32 0 %203 = insertelement <4 x float> %202, float %195, i32 1 %204 = insertelement <4 x float> %203, float %195, i32 2 %205 = insertelement <4 x float> %204, float 0.000000e+00, i32 3 %206 = call <4 x float> @llvm.AMDGPU.txl(<4 x float> %205, i32 18, i32 2, i32 2) %207 = extractelement <4 x float> %206, i32 1 %208 = fmul float 4.000000e+00, %201 %209 = fmul float 4.000000e+00, %207 %210 = call float @llvm.AMDIL.round.nearest.(float %208) %211 = call float @llvm.AMDIL.round.nearest.(float %209) %212 = call float @fabs(float %148) %213 = call float @fabs(float %178) %214 = fmul float 3.300000e+01, %210 %215 = fadd float %214, %212 %216 = fmul float 3.300000e+01, %211 %217 = fadd float %216, %213 %218 = fmul float %215, 0x3F78F9C140000000 %219 = fmul float %217, 0x3F78F9C140000000 %220 = fmul float %217, 0x3F78F9C140000000 %221 = insertelement <4 x float> undef, float %218, i32 0 %222 = insertelement <4 x float> %221, float %219, i32 1 %223 = insertelement <4 x float> %222, float %220, i32 2 %224 = insertelement <4 x float> %223, float 0.000000e+00, i32 3 %225 = call <4 x float> @llvm.AMDGPU.txl(<4 x float> %224, i32 16, i32 0, i32 2) %226 = extractelement <4 x float> %225, i32 0 %227 = extractelement <4 x float> %225, i32 1 br label %ENDIF42 ENDIF55: ; preds = %LOOP54 %228 = load <4 x float> addrspace(8)* null %229 = extractelement <4 x float> %228, i32 0 %230 = fmul float %229, 0.000000e+00 %231 = fadd float %230, %7 %232 = load <4 x float> addrspace(8)* null %233 = extractelement <4 x float> %232, i32 1 %234 = fmul float %233, %temp16.2 %235 = fadd float %234, %8 %236 = load <4 x float> addrspace(8)* null %237 = extractelement <4 x float> %236, i32 1 %238 = fmul float %237, %temp16.2 %239 = fadd float %238, %8 %240 = insertelement <4 x float> undef, float %231, i32 0 %241 = insertelement <4 x float> %240, float %235, i32 1 %242 = insertelement <4 x float> %241, float %239, i32 2 %243 = insertelement <4 x float> %242, float 0.000000e+00, i32 3 %244 = call <4 x float> @llvm.AMDGPU.txl(<4 x float> %243, i32 18, i32 2, i32 2) %245 = extractelement <4 x float> %244, i32 0 %246 = fcmp olt float %245, 0x3FECCCCCC0000000 %247 = select i1 %246, float 1.000000e+00, float 0.000000e+00 %248 = fcmp une float %247, 0.000000e+00 br i1 %248, label %ENDLOOP53, label %ENDIF58 ENDIF58: ; preds = %ENDIF55 %249 = fadd float %temp16.2, 2.000000e+00 br label %LOOP54 } ; Function Attrs: readnone declare <2 x float> @llvm.R600.interp.xy(i32, float, float) #1 ; Function Attrs: readnone declare <2 x float> @llvm.R600.interp.zw(i32, float, float) #1 ; Function Attrs: readnone declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32, i32) #1 ; Function Attrs: readnone declare <4 x float> @llvm.AMDGPU.txl(<4 x float>, i32, i32, i32) #1 ; Function Attrs: readnone declare float @llvm.AMDIL.round.nearest.(float) #1 ; Function Attrs: readonly declare float @fabs(float) #2 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } attributes #2 = { readonly } Shader Disassembly: ALU 3, @122, KC0[], KC1[] ; 0000007A A00C0000 TEX 0 @100 ; 00000064 80400000 ALU_PUSH_BEFORE 2, @126, KC0[], KC1[] ; 0000007E A4080000 JUMP @5 POP:0 ; 00000005 82800000 ALU 2, @129, KC0[], KC1[] ; 00000081 A0080000 ELSE @48 POP:1 ; 00000030 83400001 ALU 1, @132, KC0[], KC1[] ; 00000084 A0040000 LOOP_START_DX10 @25 ; 00000019 81800000 ALU_PUSH_BEFORE 4, @134, KC0[], KC1[] ; 00000086 A4100000 JUMP @11 POP:0 ; 0000000B 82800000 ALU 1, @139, KC0[], KC1[] ; 0000008B A0040000 ELSE @20 POP:1 ; 00000014 83400001 ALU 1, @141, KC0[CB0:0-32], KC1[] ; 8000008D A0040000 TEX 0 @102 ; 00000066 80400000 ALU_PUSH_BEFORE 3, @143, KC0[], KC1[] ; 0000008F A40C0000 JUMP @17 POP:0 ; 00000011 82800000 ALU 1, @147, KC0[], KC1[] ; 00000093 A0040000 ELSE @19 POP:1 ; 00000013 83400001 ALU_POP_AFTER 2, @149, KC0[], KC1[] ; 00000095 A8080000 POP @20 POP:1 ; 00000014 83800001 ALU_PUSH_BEFORE 4, @152, KC0[], KC1[] ; 00000098 A4100000 JUMP @24 POP:1 ; 00000018 82800001 LOOP_BREAK @24 ; 00000018 82400000 POP @24 POP:1 ; 00000018 83800001 END_LOOP @8 ; 00000008 81400000 ALU 6, @157, KC0[], KC1[] ; 0000009D A0180000 LOOP_START_DX10 @44 ; 0000002C 81800000 ALU_PUSH_BEFORE 4, @164, KC0[], KC1[] ; 000000A4 A4100000 JUMP @30 POP:0 ; 0000001E 82800000 ALU 1, @169, KC0[], KC1[] ; 000000A9 A0040000 ELSE @39 POP:1 ; 00000027 83400001 ALU 1, @171, KC0[CB0:0-32], KC1[] ; 800000AB A0040000 TEX 0 @104 ; 00000068 80400000 ALU_PUSH_BEFORE 3, @173, KC0[], KC1[] ; 000000AD A40C0000 JUMP @36 POP:0 ; 00000024 82800000 ALU 1, @177, KC0[], KC1[] ; 000000B1 A0040000 ELSE @38 POP:1 ; 00000026 83400001 ALU_POP_AFTER 2, @179, KC0[], KC1[] ; 000000B3 A8080000 POP @39 POP:1 ; 00000027 83800001 ALU_PUSH_BEFORE 4, @182, KC0[], KC1[] ; 000000B6 A4100000 JUMP @43 POP:1 ; 0000002B 82800001 LOOP_BREAK @43 ; 0000002B 82400000 POP @43 POP:1 ; 0000002B 83800001 END_LOOP @27 ; 0000001B 81400000 ALU 11, @187, KC0[CB0:0-32], KC1[] ; 800000BB A02C0000 TEX 1 @106 ; 0000006A 80400400 ALU_POP_AFTER 14, @199, KC0[], KC1[] ; 000000C7 A8380000 TEX 0 @110 ; 0000006E 80400000 ALU_PUSH_BEFORE 2, @214, KC0[], KC1[] ; 000000D6 A4080000 JUMP @51 POP:0 ; 00000033 82800000 ALU 2, @217, KC0[], KC1[] ; 000000D9 A0080000 ELSE @96 POP:1 ; 00000060 83400001 ALU 1, @220, KC0[], KC1[] ; 000000DC A0040000 LOOP_START_DX10 @71 ; 00000047 81800000 ALU_PUSH_BEFORE 4, @222, KC0[], KC1[] ; 000000DE A4100000 JUMP @57 POP:0 ; 00000039 82800000 ALU 1, @227, KC0[], KC1[] ; 000000E3 A0040000 ELSE @66 POP:1 ; 00000042 83400001 ALU 1, @229, KC0[CB0:0-32], KC1[] ; 800000E5 A0040000 TEX 0 @112 ; 00000070 80400000 ALU_PUSH_BEFORE 3, @231, KC0[], KC1[] ; 000000E7 A40C0000 JUMP @63 POP:0 ; 0000003F 82800000 ALU 1, @235, KC0[], KC1[] ; 000000EB A0040000 ELSE @65 POP:1 ; 00000041 83400001 ALU_POP_AFTER 2, @237, KC0[], KC1[] ; 000000ED A8080000 POP @66 POP:1 ; 00000042 83800001 ALU_PUSH_BEFORE 4, @240, KC0[], KC1[] ; 000000F0 A4100000 JUMP @70 POP:1 ; 00000046 82800001 LOOP_BREAK @70 ; 00000046 82400000 POP @70 POP:1 ; 00000046 83800001 END_LOOP @54 ; 00000036 81400000 ALU 8, @245, KC0[], KC1[] ; 000000F5 A0200000 LOOP_START_DX10 @90 ; 0000005A 81800000 ALU_PUSH_BEFORE 4, @254, KC0[], KC1[] ; 000000FE A4100000 JUMP @76 POP:0 ; 0000004C 82800000 ALU 1, @259, KC0[], KC1[] ; 00000103 A0040000 ELSE @85 POP:1 ; 00000055 83400001 ALU 1, @261, KC0[CB0:0-32], KC1[] ; 80000105 A0040000 TEX 0 @114 ; 00000072 80400000 ALU_PUSH_BEFORE 3, @263, KC0[], KC1[] ; 00000107 A40C0000 JUMP @82 POP:0 ; 00000052 82800000 ALU 1, @267, KC0[], KC1[] ; 0000010B A0040000 ELSE @84 POP:1 ; 00000054 83400001 ALU_POP_AFTER 3, @269, KC0[], KC1[] ; 0000010D A80C0000 POP @85 POP:1 ; 00000055 83800001 ALU_PUSH_BEFORE 4, @273, KC0[], KC1[] ; 00000111 A4100000 JUMP @89 POP:1 ; 00000059 82800001 LOOP_BREAK @89 ; 00000059 82400000 POP @89 POP:1 ; 00000059 83800001 END_LOOP @73 ; 00000049 81400000 ALU 2, @278, KC0[CB0:0-32], KC1[] ; 80000116 A0080000 TEX 0 @116 ; 00000074 80400000 ALU 8, @281, KC0[CB0:0-32], KC1[] ; 80000119 A0200000 TEX 0 @118 ; 00000076 80400000 ALU_POP_AFTER 14, @290, KC0[], KC1[] ; 00000122 A8380000 TEX 0 @120 ; 00000078 80400000 ALU 1, @305, KC0[], KC1[] ; 00000131 A0040000 EXPORT T2.XYZW ; C0010000 95200688 CF_END ; 00000000 88000000 PAD ; 00000000 00000000 Fetch clause starting at 100: ; TEX_SAMPLE T1.XYZW, T0.XY__ RID:17 SID:1 CT:NNNN ; 00001110 F00D1001 FC808000 00000000 Fetch clause starting at 102: ; TEX_SAMPLE_L T2.XYZW, T2.XYY0 RID:18 SID:2 CT:NNNN ; 00021211 F00D1002 84810000 00000000 Fetch clause starting at 104: ; TEX_SAMPLE_L T3.XYZW, T3.XYY0 RID:18 SID:2 CT:NNNN ; 00031211 F00D1003 84810000 00000000 Fetch clause starting at 106: ; TEX_SAMPLE_L T5.XYZW, T5.XYY0 RID:18 SID:2 CT:NNNN ; 00051211 F00D1005 84810000 00000000 TEX_SAMPLE_L T4.XYZW, T4.XYY0 RID:18 SID:2 CT:NNNN ; 00041211 F00D1004 84810000 00000000 Fetch clause starting at 110: ; TEX_SAMPLE_L T2.XYZW, T2.XYY0 RID:16 SID:0 CT:NNNN ; 00021011 F00D1002 84800000 00000000 Fetch clause starting at 112: ; TEX_SAMPLE_L T1.XYZW, T1.XYY0 RID:18 SID:2 CT:NNNN ; 00011211 F00D1001 84810000 00000000 Fetch clause starting at 114: ; TEX_SAMPLE_L T3.XYZW, T3.XYY0 RID:18 SID:2 CT:NNNN ; 00031211 F00D1003 84810000 00000000 Fetch clause starting at 116: ; TEX_SAMPLE_L T5.XYZW, T4.XYY0 RID:18 SID:2 CT:NNNN ; 00041211 F00D1005 84810000 00000000 Fetch clause starting at 118: ; TEX_SAMPLE_L T0.XYZW, T4.XYY0 RID:18 SID:2 CT:NNNN ; 00041211 F00D1000 84810000 00000000 Fetch clause starting at 120: ; TEX_SAMPLE_L T0.XYZW, T1.XYY0 RID:16 SID:0 CT:NNNN ; 00011011 F00D1000 84800000 00000000 ALU clause starting at 122: ; INTERP_XY T0.X, T0.Y, ARRAY_BASE, ; 00380400 00146B10 INTERP_XY T0.Y, T0.X, ARRAY_BASE, ; 00380000 20146B10 INTERP_XY T0.Z (MASKED), T0.Y, ARRAY_BASE, ; 00380400 40146B00 INTERP_XY * T0.W (MASKED), T0.X, ARRAY_BASE, ; 80380000 60146B00 ALU clause starting at 126: ; SETNE * T2.Y, T1.Y, 0.0, ; 801F0401 20400590 SETNE_DX10 * T3.W, PV.Y, 0.0, ; 801F04FE 60600790 PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002104 ALU clause starting at 129: ; MOV * T2.Y, literal.x, ; 800000FD 20400C90 0(0.000000e+00), 0(0.000000e+00) ; 00000000 00000000 MOV * T2.X, PV.Y, ; 800004FE 00400C90 ALU clause starting at 132: ; MOV * T3.Z, literal.x, ; 800000FD 40600C90 -1077936128(-1.500000e+00), 0(0.000000e+00) ; BFC00000 00000000 ALU clause starting at 134: ; MOV * T3.X, T3.Z, ; 80000803 00600C90 SETGE * T3.W, literal.x, PV.X, ; 801FC0FD 60600510 -1048576000(-1.600000e+01), 0(0.000000e+00) ; C1800000 00000000 SETE_DX10 * T3.W, PV.W, 0.0, ; 801F0CFE 60600610 PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002104 ALU clause starting at 139: ; MOV * T3.W, literal.x, ; 800000FD 60600C90 1(1.401298e-45), 0(0.000000e+00) ; 00000001 00000000 ALU clause starting at 141: ; MULADD_IEEE T2.X, KC0[0].X, T3.X, T0.X, ; 00006080 00430000 MULADD_IEEE * T2.Y, KC0[0].Y, 0.0, T0.Y, ; 801F0480 20430400 ALU clause starting at 143: ; SETGT * T3.W, literal.x, T2.Y, ; 808040FD 60600490 1063675494(9.000000e-01), 0(0.000000e+00) ; 3F666666 00000000 SETE_DX10 * T3.W, PV.W, 0.0, ; 801F0CFE 60600610 PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002104 ALU clause starting at 147: ; MOV * T3.W, literal.x, ; 800000FD 60600C90 1(1.401298e-45), 0(0.000000e+00) ; 00000001 00000000 ALU clause starting at 149: ; ADD T3.Z, T3.X, literal.x, ; 001FA003 40600010 MOV * T3.W, literal.y, ; 800004FD 60600C90 -1073741824(-2.000000e+00), 0(0.000000e+00) ; C0000000 00000000 ALU clause starting at 152: ; LSHL * T3.W, T3.W, literal.x, ; 801FAC03 60600B90 31(4.344025e-44), 0(0.000000e+00) ; 0000001F 00000000 ASHR * T3.W, PV.W, literal.x, ; 801FACFE 60600A90 31(4.344025e-44), 0(0.000000e+00) ; 0000001F 00000000 PRED_SETNE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002284 ALU clause starting at 157: ; ADD * T3.W, T3.X, literal.x, ; 801FA003 60600010 1069547520(1.500000e+00), 0(0.000000e+00) ; 3FC00000 00000000 MULADD_IEEE * T2.W, T2.Y, literal.x, PV.W, ; 801FA402 60430CFE -1073741824(-2.000000e+00), 0(0.000000e+00) ; C0000000 00000000 MOV T2.Z, literal.x, ; 000000FD 40400C90 MAX * T2.W, literal.y, PV.W, ; 819FC4FD 60400190 1069547520(1.500000e+00), -1048576000(-1.600000e+01) ; 3FC00000 C1800000 ALU clause starting at 164: ; MOV * T2.X, T2.Z, ; 80000802 00400C90 SETGE * T3.Y, PV.X, literal.x, ; 801FA0FE 20600510 1098907648(1.600000e+01), 0(0.000000e+00) ; 41800000 00000000 SETE_DX10 * T4.W, PV.Y, 0.0, ; 801F04FE 60800610 PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002104 ALU clause starting at 169: ; MOV * T4.W, literal.x, ; 800000FD 60800C90 1(1.401298e-45), 0(0.000000e+00) ; 00000001 00000000 ALU clause starting at 171: ; MULADD_IEEE T3.X, KC0[0].X, T2.X, T0.X, ; 00004080 00630000 MULADD_IEEE * T3.Y, KC0[0].Y, 0.0, T0.Y, ; 801F0480 20630400 ALU clause starting at 173: ; SETGT * T4.W, literal.x, T3.Y, ; 808060FD 60800490 1063675494(9.000000e-01), 0(0.000000e+00) ; 3F666666 00000000 SETE_DX10 * T4.W, PV.W, 0.0, ; 801F0CFE 60800610 PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002104 ALU clause starting at 177: ; MOV * T4.W, literal.x, ; 800000FD 60800C90 1(1.401298e-45), 0(0.000000e+00) ; 00000001 00000000 ALU clause starting at 179: ; ADD T2.Z, T2.X, literal.x, ; 001FA002 40400010 MOV * T4.W, literal.y, ; 800004FD 60800C90 1073741824(2.000000e+00), 0(0.000000e+00) ; 40000000 00000000 ALU clause starting at 182: ; LSHL * T4.W, T4.W, literal.x, ; 801FAC04 60800B90 31(4.344025e-44), 0(0.000000e+00) ; 0000001F 00000000 ASHR * T4.W, PV.W, literal.x, ; 801FACFE 60800A90 31(4.344025e-44), 0(0.000000e+00) ; 0000001F 00000000 PRED_SETNE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002284 ALU clause starting at 187: ; ADD T2.Z, T3.Y, T3.Y, ; 00806403 40400010 ADD * T3.W, T2.X, literal.x, ; 801FA002 60600010 -1077936128(-1.500000e+00), 0(0.000000e+00) ; BFC00000 00000000 ADD * T3.W, PV.Z, PV.W, ; 819FC8FE 60600010 MIN * T3.W, literal.x, PV.W, ; 819FC0FD 60600210 1098907648(1.600000e+01), 0(0.000000e+00) ; 41800000 00000000 MULADD_IEEE T4.X, T2.W, KC0[0].X, T0.X, ; 00100C02 00830000 ADD * T5.W, PV.W, 1.0, ; 801F2CFE 60A00010 MULADD_IEEE T5.X, PV.W, KC0[0].X, T0.X, ; 00100CFE 00A30000 MULADD_IEEE * T4.Y, KC0[0].Y, literal.x, T0.Y, ; 801FA480 20830400 -1098907648(-2.500000e-01), 0(0.000000e+00) ; BE800000 00000000 MOV * T5.Y, PV.Y, ; 800004FE 20A00C90 ALU clause starting at 199: ; MUL_IEEE * T4.W, T4.X, literal.x, ; 801FA004 60800110 1082130432(4.000000e+00), 0(0.000000e+00) ; 40800000 00000000 RNDNE T2.Y, PV.W, ; 00000CFE 20400990 MOV T2.Z, |T2.W|, ; 00000C02 40400C91 MUL_IEEE * T2.W, T5.X, literal.x, ; 801FA005 60400110 1082130432(4.000000e+00), 0(0.000000e+00) ; 40800000 00000000 RNDNE T3.Y, PV.W, ; 00000CFE 20600990 MOV T3.Z, |T3.W|, ; 00000C03 40600C91 MULADD_IEEE * T2.W, PV.Y, literal.x, PV.Z, ; 801FA4FE 604308FE 1107558400(3.300000e+01), 0(0.000000e+00) ; 42040000 00000000 MUL_IEEE T2.X, PV.W, literal.x, ; 001FACFE 00400110 MULADD_IEEE * T3.W, PV.Y, literal.y, PV.Z, ; 809FA4FE 606308FE 1002950154(6.097560e-03), 1107558400(3.300000e+01) ; 3BC7CE0A 42040000 MUL_IEEE * T2.Y, PV.W, literal.x, ; 801FACFE 20400110 1002950154(6.097560e-03), 0(0.000000e+00) ; 3BC7CE0A 00000000 ALU clause starting at 214: ; SETNE * T3.W, T1.X, 0.0, ; 801F0001 60600590 SETNE_DX10 * T3.W, PV.W, 0.0, ; 801F0CFE 60600790 PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002104 ALU clause starting at 217: ; MOV * T0.Y, literal.x, ; 800000FD 20000C90 0(0.000000e+00), 0(0.000000e+00) ; 00000000 00000000 MOV * T0.X, PV.Y, ; 800004FE 00000C90 ALU clause starting at 220: ; MOV * T3.Z, literal.x, ; 800000FD 40600C90 -1077936128(-1.500000e+00), 0(0.000000e+00) ; BFC00000 00000000 ALU clause starting at 222: ; MOV * T3.X, T3.Z, ; 80000803 00600C90 SETGE * T3.W, literal.x, PV.X, ; 801FC0FD 60600510 -1048576000(-1.600000e+01), 0(0.000000e+00) ; C1800000 00000000 SETE_DX10 * T3.W, PV.W, 0.0, ; 801F0CFE 60600610 PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002104 ALU clause starting at 227: ; MOV * T3.W, literal.x, ; 800000FD 60600C90 1(1.401298e-45), 0(0.000000e+00) ; 00000001 00000000 ALU clause starting at 229: ; MULADD_IEEE T1.X, KC0[0].X, 0.0, T0.X, ; 001F0080 00230000 MULADD_IEEE * T1.Y, KC0[0].Y, T3.X, T0.Y, ; 80006480 20230400 ALU clause starting at 231: ; SETGT * T3.W, literal.x, T1.X, ; 800020FD 60600490 1063675494(9.000000e-01), 0(0.000000e+00) ; 3F666666 00000000 SETE_DX10 * T3.W, PV.W, 0.0, ; 801F0CFE 60600610 PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002104 ALU clause starting at 235: ; MOV * T3.W, literal.x, ; 800000FD 60600C90 1(1.401298e-45), 0(0.000000e+00) ; 00000001 00000000 ALU clause starting at 237: ; ADD T3.Z, T3.X, literal.x, ; 001FA003 40600010 MOV * T3.W, literal.y, ; 800004FD 60600C90 -1073741824(-2.000000e+00), 0(0.000000e+00) ; C0000000 00000000 ALU clause starting at 240: ; LSHL * T3.W, T3.W, literal.x, ; 801FAC03 60600B90 31(4.344025e-44), 0(0.000000e+00) ; 0000001F 00000000 ASHR * T3.W, PV.W, literal.x, ; 801FACFE 60600A90 31(4.344025e-44), 0(0.000000e+00) ; 0000001F 00000000 PRED_SETNE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002284 ALU clause starting at 245: ; ADD * T3.W, T3.X, literal.x, ; 801FA003 60600010 1069547520(1.500000e+00), 0(0.000000e+00) ; 3FC00000 00000000 MULADD_IEEE * T1.W, T1.X, literal.x, PV.W, ; 801FA001 60230CFE -1073741824(-2.000000e+00), 0(0.000000e+00) ; C0000000 00000000 MAX * T1.W, literal.x, PV.W, ; 819FC0FD 60200190 -1048576000(-1.600000e+01), 0(0.000000e+00) ; C1800000 00000000 MOV T3.X, PV.W, ; 00000CFE 00600C90 MOV * T4.W, literal.x, ; 800000FD 60800C90 1069547520(1.500000e+00), 0(0.000000e+00) ; 3FC00000 00000000 ALU clause starting at 254: ; MOV * T1.X, T4.W, ; 80000C04 00200C90 SETGE * T4.W, PV.X, literal.x, ; 801FA0FE 60800510 1098907648(1.600000e+01), 0(0.000000e+00) ; 41800000 00000000 SETE_DX10 * T4.W, PV.W, 0.0, ; 801F0CFE 60800610 PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002104 ALU clause starting at 259: ; MOV * T5.W, literal.x, ; 800000FD 60A00C90 1(1.401298e-45), 0(0.000000e+00) ; 00000001 00000000 ALU clause starting at 261: ; MULADD_IEEE T3.X, KC0[0].X, 0.0, T0.X, ; 001F0080 00630000 MULADD_IEEE * T3.Y, KC0[0].Y, T1.X, T0.Y, ; 80002480 20630400 ALU clause starting at 263: ; SETGT * T4.W, literal.x, T3.X, ; 800060FD 60800490 1063675494(9.000000e-01), 0(0.000000e+00) ; 3F666666 00000000 SETE_DX10 * T4.W, PV.W, 0.0, ; 801F0CFE 60800610 PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002104 ALU clause starting at 267: ; MOV * T5.W, literal.x, ; 800000FD 60A00C90 1(1.401298e-45), 0(0.000000e+00) ; 00000001 00000000 ALU clause starting at 269: ; MOV * T5.W, literal.x, ; 800000FD 60A00C90 0(0.000000e+00), 0(0.000000e+00) ; 00000000 00000000 ADD * T4.W, T1.X, literal.x, ; 801FA001 60800010 1073741824(2.000000e+00), 0(0.000000e+00) ; 40000000 00000000 ALU clause starting at 273: ; LSHL * T5.W, T5.W, literal.x, ; 801FAC05 60A00B90 31(4.344025e-44), 0(0.000000e+00) ; 0000001F 00000000 ASHR * T5.W, PV.W, literal.x, ; 801FACFE 60A00A90 31(4.344025e-44), 0(0.000000e+00) ; 0000001F 00000000 PRED_SETNE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002284 ALU clause starting at 278: ; MULADD_IEEE T4.X, KC0[0].X, literal.x, T0.X, ; 001FA080 00830000 MULADD_IEEE * T4.Y, T1.W, KC0[0].Y, T0.Y, ; 80900C01 20830400 -1098907648(-2.500000e-01), 0(0.000000e+00) ; BE800000 00000000 ALU clause starting at 281: ; ADD T1.Z, T3.X, T3.X, ; 00006003 40200010 ADD * T3.W, T1.X, literal.x, BS:VEC_120/SCL_212 ; 801FA001 60680010 -1077936128(-1.500000e+00), 0(0.000000e+00) ; BFC00000 00000000 ADD * T3.W, PV.Z, PV.W, ; 819FC8FE 60600010 MIN * T3.W, literal.x, PV.W, ; 819FC0FD 60600210 1098907648(1.600000e+01), 0(0.000000e+00) ; 41800000 00000000 ADD * T6.W, PV.W, 1.0, ; 801F2CFE 60C00010 MULADD_IEEE * T0.W, PV.W, KC0[0].Y, T0.Y, ; 80900CFE 60030400 MOV * T4.Y, PV.W, ; 80000CFE 20800C90 ALU clause starting at 290: ; MUL_IEEE * T4.W, T5.Y, literal.x, ; 801FA405 60800110 1082130432(4.000000e+00), 0(0.000000e+00) ; 40800000 00000000 RNDNE T1.Y, PV.W, ; 00000CFE 20200990 MOV T1.Z, |T1.W|, ; 00000C01 40200C91 MUL_IEEE * T0.W, T0.Y, literal.x, ; 801FA400 60000110 1082130432(4.000000e+00), 0(0.000000e+00) ; 40800000 00000000 RNDNE T0.Y, PV.W, ; 00000CFE 20000990 MOV T0.Z, |T3.W|, ; 00000C03 40000C91 MULADD_IEEE * T0.W, PV.Y, literal.x, PV.Z, ; 801FA4FE 600308FE 1107558400(3.300000e+01), 0(0.000000e+00) ; 42040000 00000000 MUL_IEEE T1.X, PV.W, literal.x, ; 001FACFE 00200110 MULADD_IEEE * T0.W, PV.Y, literal.y, PV.Z, ; 809FA4FE 600308FE 1002950154(6.097560e-03), 1107558400(3.300000e+01) ; 3BC7CE0A 42040000 MUL_IEEE * T1.Y, PV.W, literal.x, ; 801FACFE 20200110 1002950154(6.097560e-03), 0(0.000000e+00) ; 3BC7CE0A 00000000 ALU clause starting at 305: ; MOV T2.Z, T0.X, ; 00000000 40400C90 MOV * T2.W, T0.Y, ; 80000400 60400C90 ===== SHADER #100 ======================================= PS/CAYMAN/CAYMAN ===== ===== 614 dw ===== 7 gprs ===== 3 stack ======================================== 0000 0000007a a00c0000 ALU 4 @244 0244 00380400 00146b10 1 x: INTERP_XY R0.x, R0.y, Param0.x VEC_210 0246 00380000 20146b10 y: INTERP_XY R0.y, R0.x, Param0.x VEC_210 0248 00380400 40146b00 z: INTERP_XY __.z, R0.y, Param0.x VEC_210 0250 80380000 60146b00 w: INTERP_XY __.w, R0.x, Param0.x VEC_210 0002 00000064 80400000 TEX 1 @200 0200 00001110 f00d1001 fc808000 SAMPLE R1.xyzw, R0.xy__, RID:17, SID:1 CT:NNNN 0004 0000007e a4080000 ALU_PUSH_BEFORE 3 @252 0252 801f0401 20400590 2 y: SETNE R2.y, R1.y, 0 0254 801f04fe 60600790 3 w: SETNE_DX10 R3.w, PV.y, 0 0256 801f0cfe 00002104 4 M x: PRED_SETE_INT __.x, PV.w, 0 0006 00000005 82800000 JUMP @10 0008 00000081 a0080000 ALU 3 @258 0258 800000fd 20400c90 5 y: MOV R2.y, [0x00000000 0].x 0260 00000000 0262 800004fe 00400c90 6 x: MOV R2.x, PV.y 0010 00000030 83400001 ELSE @96 POP:1 0012 00000084 a0040000 ALU 2 @264 0264 800000fd 40600c90 7 z: MOV R3.z, [0xbfc00000 -1.5].x 0266 bfc00000 0014 00000019 81800000 LOOP_START_DX10 @50 0016 00000086 a4100000 ALU_PUSH_BEFORE 5 @268 0268 80000803 00600c90 8 x: MOV R3.x, R3.z 0270 801fc0fd 60600510 9 w: SETGE R3.w, [0xc1800000 -16].x, PV.x 0272 c1800000 0274 801f0cfe 60600610 10 w: SETE_DX10 R3.w, PV.w, 0 0276 801f0cfe 00002104 11 M x: PRED_SETE_INT __.x, PV.w, 0 0018 0000000b 82800000 JUMP @22 0020 0000008b a0040000 ALU 2 @278 0278 800000fd 60600c90 12 w: MOV R3.w, [0x00000001 1.4013e-45].x 0280 00000001 0022 00000014 83400001 ELSE @40 POP:1 0024 8000008d a0040000 ALU 2 @282 KC0[CB0:0-31] 0282 00006080 00430000 13 x: MULADD_IEEE R2.x, KC0[0].x, R3.x, R0.x 0284 801f0480 20430400 y: MULADD_IEEE R2.y, KC0[0].y, 0, R0.y 0026 00000066 80400000 TEX 1 @204 0204 00021211 f00d1002 84810000 SAMPLE_L R2.xyzw, R2.xyy0, RID:18, SID:2 CT:NNNN 0028 0000008f a40c0000 ALU_PUSH_BEFORE 4 @286 0286 808040fd 60600490 14 w: SETGT R3.w, [0x3f666666 0.9].x, R2.y 0288 3f666666 0290 801f0cfe 60600610 15 w: SETE_DX10 R3.w, PV.w, 0 0292 801f0cfe 00002104 16 M x: PRED_SETE_INT __.x, PV.w, 0 0030 00000011 82800000 JUMP @34 0032 00000093 a0040000 ALU 2 @294 0294 800000fd 60600c90 17 w: MOV R3.w, [0x00000001 1.4013e-45].x 0296 00000001 0034 00000013 83400001 ELSE @38 POP:1 0036 00000095 a8080000 ALU_POP_AFTER 3 @298 0298 001fa003 40600010 18 z: ADD R3.z, R3.x, [0xc0000000 -2].x 0300 800004fd 60600c90 w: MOV R3.w, [0x00000000 0].y 0302 c0000000 0303 00000000 0038 00000014 83800001 POP @40 POP:1 0040 00000098 a4100000 ALU_PUSH_BEFORE 5 @304 0304 801fac03 60600b90 19 w: LSHL_INT R3.w, R3.w, [0x0000001f 4.34403e-44].x 0306 0000001f 0308 801facfe 60600a90 20 w: ASHR_INT R3.w, PV.w, [0x0000001f 4.34403e-44].x 0310 0000001f 0312 801f0cfe 00002284 21 M x: PRED_SETNE_INT __.x, PV.w, 0 0042 00000018 82800001 JUMP @48 POP:1 0044 00000018 82400000 LOOP_BREAK @48 0046 00000018 83800001 POP @48 POP:1 0048 00000008 81400000 LOOP_END @16 0050 0000009d a0180000 ALU 7 @314 0314 801fa003 60600010 22 w: ADD R3.w, R3.x, [0x3fc00000 1.5].x 0316 3fc00000 0318 801fa402 60430cfe 23 w: MULADD_IEEE R2.w, R2.y, [0xc0000000 -2].x, PV.w 0320 c0000000 0322 000000fd 40400c90 24 z: MOV R2.z, [0x3fc00000 1.5].x 0324 819fc4fd 60400190 w: MAX R2.w, [0xc1800000 -16].y, PV.w 0326 3fc00000 0327 c1800000 0052 0000002c 81800000 LOOP_START_DX10 @88 0054 000000a4 a4100000 ALU_PUSH_BEFORE 5 @328 0328 80000802 00400c90 25 x: MOV R2.x, R2.z 0330 801fa0fe 20600510 26 y: SETGE R3.y, PV.x, [0x41800000 16].x 0332 41800000 0334 801f04fe 60800610 27 w: SETE_DX10 R4.w, PV.y, 0 0336 801f0cfe 00002104 28 M x: PRED_SETE_INT __.x, PV.w, 0 0056 0000001e 82800000 JUMP @60 0058 000000a9 a0040000 ALU 2 @338 0338 800000fd 60800c90 29 w: MOV R4.w, [0x00000001 1.4013e-45].x 0340 00000001 0060 00000027 83400001 ELSE @78 POP:1 0062 800000ab a0040000 ALU 2 @342 KC0[CB0:0-31] 0342 00004080 00630000 30 x: MULADD_IEEE R3.x, KC0[0].x, R2.x, R0.x 0344 801f0480 20630400 y: MULADD_IEEE R3.y, KC0[0].y, 0, R0.y 0064 00000068 80400000 TEX 1 @208 0208 00031211 f00d1003 84810000 SAMPLE_L R3.xyzw, R3.xyy0, RID:18, SID:2 CT:NNNN 0066 000000ad a40c0000 ALU_PUSH_BEFORE 4 @346 0346 808060fd 60800490 31 w: SETGT R4.w, [0x3f666666 0.9].x, R3.y 0348 3f666666 0350 801f0cfe 60800610 32 w: SETE_DX10 R4.w, PV.w, 0 0352 801f0cfe 00002104 33 M x: PRED_SETE_INT __.x, PV.w, 0 0068 00000024 82800000 JUMP @72 0070 000000b1 a0040000 ALU 2 @354 0354 800000fd 60800c90 34 w: MOV R4.w, [0x00000001 1.4013e-45].x 0356 00000001 0072 00000026 83400001 ELSE @76 POP:1 0074 000000b3 a8080000 ALU_POP_AFTER 3 @358 0358 001fa002 40400010 35 z: ADD R2.z, R2.x, [0x40000000 2].x 0360 800004fd 60800c90 w: MOV R4.w, [0x00000000 0].y 0362 40000000 0363 00000000 0076 00000027 83800001 POP @78 POP:1 0078 000000b6 a4100000 ALU_PUSH_BEFORE 5 @364 0364 801fac04 60800b90 36 w: LSHL_INT R4.w, R4.w, [0x0000001f 4.34403e-44].x 0366 0000001f 0368 801facfe 60800a90 37 w: ASHR_INT R4.w, PV.w, [0x0000001f 4.34403e-44].x 0370 0000001f 0372 801f0cfe 00002284 38 M x: PRED_SETNE_INT __.x, PV.w, 0 0080 0000002b 82800001 JUMP @86 POP:1 0082 0000002b 82400000 LOOP_BREAK @86 0084 0000002b 83800001 POP @86 POP:1 0086 0000001b 81400000 LOOP_END @54 0088 800000bb a02c0000 ALU 12 @374 KC0[CB0:0-31] 0374 00806403 40400010 39 z: ADD R2.z, R3.y, R3.y 0376 801fa002 60600010 w: ADD R3.w, R2.x, [0xbfc00000 -1.5].x 0378 bfc00000 0380 819fc8fe 60600010 40 w: ADD R3.w, PV.z, PV.w 0382 819fc0fd 60600210 41 w: MIN R3.w, [0x41800000 16].x, PV.w 0384 41800000 0386 00100c02 00830000 42 x: MULADD_IEEE R4.x, R2.w, KC0[0].x, R0.x 0388 801f2cfe 60a00010 w: ADD R5.w, PV.w, 1.0 0390 00100cfe 00a30000 43 x: MULADD_IEEE R5.x, PV.w, KC0[0].x, R0.x 0392 801fa480 20830400 y: MULADD_IEEE R4.y, KC0[0].y, [0xbe800000 -0.25].x, R0.y 0394 be800000 0396 800004fe 20a00c90 44 y: MOV R5.y, PV.y 0090 0000006a 80400400 TEX 2 @212 0212 00051211 f00d1005 84810000 SAMPLE_L R5.xyzw, R5.xyy0, RID:18, SID:2 CT:NNNN 0216 00041211 f00d1004 84810000 SAMPLE_L R4.xyzw, R4.xyy0, RID:18, SID:2 CT:NNNN 0092 000000c7 a8380000 ALU_POP_AFTER 15 @398 0398 801fa004 60800110 45 w: MUL_IEEE R4.w, R4.x, [0x40800000 4].x 0400 40800000 0402 00000cfe 20400990 46 y: RNDNE R2.y, PV.w 0404 00000c02 40400c91 z: MOV R2.z, |R2.w| 0406 801fa005 60400110 w: MUL_IEEE R2.w, R5.x, [0x40800000 4].x 0408 40800000 0410 00000cfe 20600990 47 y: RNDNE R3.y, PV.w 0412 00000c03 40600c91 z: MOV R3.z, |R3.w| 0414 801fa4fe 604308fe w: MULADD_IEEE R2.w, PV.y, [0x42040000 33].x, PV.z 0416 42040000 0418 001facfe 00400110 48 x: MUL_IEEE R2.x, PV.w, [0x3bc7ce0a 0.00609756].x 0420 809fa4fe 606308fe w: MULADD_IEEE R3.w, PV.y, [0x42040000 33].y, PV.z 0422 3bc7ce0a 0423 42040000 0424 801facfe 20400110 49 y: MUL_IEEE R2.y, PV.w, [0x3bc7ce0a 0.00609756].x 0426 3bc7ce0a 0094 0000006e 80400000 TEX 1 @220 0220 00021011 f00d1002 84800000 SAMPLE_L R2.xyzw, R2.xyy0, RID:16, SID:0 CT:NNNN 0096 000000d6 a4080000 ALU_PUSH_BEFORE 3 @428 0428 801f0001 60600590 50 w: SETNE R3.w, R1.x, 0 0430 801f0cfe 60600790 51 w: SETNE_DX10 R3.w, PV.w, 0 0432 801f0cfe 00002104 52 M x: PRED_SETE_INT __.x, PV.w, 0 0098 00000033 82800000 JUMP @102 0100 000000d9 a0080000 ALU 3 @434 0434 800000fd 20000c90 53 y: MOV R0.y, [0x00000000 0].x 0436 00000000 0438 800004fe 00000c90 54 x: MOV R0.x, PV.y 0102 00000060 83400001 ELSE @192 POP:1 0104 000000dc a0040000 ALU 2 @440 0440 800000fd 40600c90 55 z: MOV R3.z, [0xbfc00000 -1.5].x 0442 bfc00000 0106 00000047 81800000 LOOP_START_DX10 @142 0108 000000de a4100000 ALU_PUSH_BEFORE 5 @444 0444 80000803 00600c90 56 x: MOV R3.x, R3.z 0446 801fc0fd 60600510 57 w: SETGE R3.w, [0xc1800000 -16].x, PV.x 0448 c1800000 0450 801f0cfe 60600610 58 w: SETE_DX10 R3.w, PV.w, 0 0452 801f0cfe 00002104 59 M x: PRED_SETE_INT __.x, PV.w, 0 0110 00000039 82800000 JUMP @114 0112 000000e3 a0040000 ALU 2 @454 0454 800000fd 60600c90 60 w: MOV R3.w, [0x00000001 1.4013e-45].x 0456 00000001 0114 00000042 83400001 ELSE @132 POP:1 0116 800000e5 a0040000 ALU 2 @458 KC0[CB0:0-31] 0458 001f0080 00230000 61 x: MULADD_IEEE R1.x, KC0[0].x, 0, R0.x 0460 80006480 20230400 y: MULADD_IEEE R1.y, KC0[0].y, R3.x, R0.y 0118 00000070 80400000 TEX 1 @224 0224 00011211 f00d1001 84810000 SAMPLE_L R1.xyzw, R1.xyy0, RID:18, SID:2 CT:NNNN 0120 000000e7 a40c0000 ALU_PUSH_BEFORE 4 @462 0462 800020fd 60600490 62 w: SETGT R3.w, [0x3f666666 0.9].x, R1.x 0464 3f666666 0466 801f0cfe 60600610 63 w: SETE_DX10 R3.w, PV.w, 0 0468 801f0cfe 00002104 64 M x: PRED_SETE_INT __.x, PV.w, 0 0122 0000003f 82800000 JUMP @126 0124 000000eb a0040000 ALU 2 @470 0470 800000fd 60600c90 65 w: MOV R3.w, [0x00000001 1.4013e-45].x 0472 00000001 0126 00000041 83400001 ELSE @130 POP:1 0128 000000ed a8080000 ALU_POP_AFTER 3 @474 0474 001fa003 40600010 66 z: ADD R3.z, R3.x, [0xc0000000 -2].x 0476 800004fd 60600c90 w: MOV R3.w, [0x00000000 0].y 0478 c0000000 0479 00000000 0130 00000042 83800001 POP @132 POP:1 0132 000000f0 a4100000 ALU_PUSH_BEFORE 5 @480 0480 801fac03 60600b90 67 w: LSHL_INT R3.w, R3.w, [0x0000001f 4.34403e-44].x 0482 0000001f 0484 801facfe 60600a90 68 w: ASHR_INT R3.w, PV.w, [0x0000001f 4.34403e-44].x 0486 0000001f 0488 801f0cfe 00002284 69 M x: PRED_SETNE_INT __.x, PV.w, 0 0134 00000046 82800001 JUMP @140 POP:1 0136 00000046 82400000 LOOP_BREAK @140 0138 00000046 83800001 POP @140 POP:1 0140 00000036 81400000 LOOP_END @108 0142 000000f5 a0200000 ALU 9 @490 0490 801fa003 60600010 70 w: ADD R3.w, R3.x, [0x3fc00000 1.5].x 0492 3fc00000 0494 801fa001 60230cfe 71 w: MULADD_IEEE R1.w, R1.x, [0xc0000000 -2].x, PV.w 0496 c0000000 0498 819fc0fd 60200190 72 w: MAX R1.w, [0xc1800000 -16].x, PV.w 0500 c1800000 0502 00000cfe 00600c90 73 x: MOV R3.x, PV.w 0504 800000fd 60800c90 w: MOV R4.w, [0x3fc00000 1.5].x 0506 3fc00000 0144 0000005a 81800000 LOOP_START_DX10 @180 0146 000000fe a4100000 ALU_PUSH_BEFORE 5 @508 0508 80000c04 00200c90 74 x: MOV R1.x, R4.w 0510 801fa0fe 60800510 75 w: SETGE R4.w, PV.x, [0x41800000 16].x 0512 41800000 0514 801f0cfe 60800610 76 w: SETE_DX10 R4.w, PV.w, 0 0516 801f0cfe 00002104 77 M x: PRED_SETE_INT __.x, PV.w, 0 0148 0000004c 82800000 JUMP @152 0150 00000103 a0040000 ALU 2 @518 0518 800000fd 60a00c90 78 w: MOV R5.w, [0x00000001 1.4013e-45].x 0520 00000001 0152 00000055 83400001 ELSE @170 POP:1 0154 80000105 a0040000 ALU 2 @522 KC0[CB0:0-31] 0522 001f0080 00630000 79 x: MULADD_IEEE R3.x, KC0[0].x, 0, R0.x 0524 80002480 20630400 y: MULADD_IEEE R3.y, KC0[0].y, R1.x, R0.y 0156 00000072 80400000 TEX 1 @228 0228 00031211 f00d1003 84810000 SAMPLE_L R3.xyzw, R3.xyy0, RID:18, SID:2 CT:NNNN 0158 00000107 a40c0000 ALU_PUSH_BEFORE 4 @526 0526 800060fd 60800490 80 w: SETGT R4.w, [0x3f666666 0.9].x, R3.x 0528 3f666666 0530 801f0cfe 60800610 81 w: SETE_DX10 R4.w, PV.w, 0 0532 801f0cfe 00002104 82 M x: PRED_SETE_INT __.x, PV.w, 0 0160 00000052 82800000 JUMP @164 0162 0000010b a0040000 ALU 2 @534 0534 800000fd 60a00c90 83 w: MOV R5.w, [0x00000001 1.4013e-45].x 0536 00000001 0164 00000054 83400001 ELSE @168 POP:1 0166 0000010d a80c0000 ALU_POP_AFTER 4 @538 0538 800000fd 60a00c90 84 w: MOV R5.w, [0x00000000 0].x 0540 00000000 0542 801fa001 60800010 85 w: ADD R4.w, R1.x, [0x40000000 2].x 0544 40000000 0168 00000055 83800001 POP @170 POP:1 0170 00000111 a4100000 ALU_PUSH_BEFORE 5 @546 0546 801fac05 60a00b90 86 w: LSHL_INT R5.w, R5.w, [0x0000001f 4.34403e-44].x 0548 0000001f 0550 801facfe 60a00a90 87 w: ASHR_INT R5.w, PV.w, [0x0000001f 4.34403e-44].x 0552 0000001f 0554 801f0cfe 00002284 88 M x: PRED_SETNE_INT __.x, PV.w, 0 0172 00000059 82800001 JUMP @178 POP:1 0174 00000059 82400000 LOOP_BREAK @178 0176 00000059 83800001 POP @178 POP:1 0178 00000049 81400000 LOOP_END @146 0180 80000116 a0080000 ALU 3 @556 KC0[CB0:0-31] 0556 001fa080 00830000 89 x: MULADD_IEEE R4.x, KC0[0].x, [0xbe800000 -0.25].x, R0.x 0558 80900c01 20830400 y: MULADD_IEEE R4.y, R1.w, KC0[0].y, R0.y 0560 be800000 0182 00000074 80400000 TEX 1 @232 0232 00041211 f00d1005 84810000 SAMPLE_L R5.xyzw, R4.xyy0, RID:18, SID:2 CT:NNNN 0184 80000119 a0200000 ALU 9 @562 KC0[CB0:0-31] 0562 00006003 40200010 90 z: ADD R1.z, R3.x, R3.x 0564 801fa001 60680010 w: ADD R3.w, R1.x, [0xbfc00000 -1.5].x VEC_120 0566 bfc00000 0568 819fc8fe 60600010 91 w: ADD R3.w, PV.z, PV.w 0570 819fc0fd 60600210 92 w: MIN R3.w, [0x41800000 16].x, PV.w 0572 41800000 0574 801f2cfe 60c00010 93 w: ADD R6.w, PV.w, 1.0 0576 80900cfe 60030400 94 w: MULADD_IEEE R0.w, PV.w, KC0[0].y, R0.y 0578 80000cfe 20800c90 95 y: MOV R4.y, PV.w 0186 00000076 80400000 TEX 1 @236 0236 00041211 f00d1000 84810000 SAMPLE_L R0.xyzw, R4.xyy0, RID:18, SID:2 CT:NNNN 0188 00000122 a8380000 ALU_POP_AFTER 15 @580 0580 801fa405 60800110 96 w: MUL_IEEE R4.w, R5.y, [0x40800000 4].x 0582 40800000 0584 00000cfe 20200990 97 y: RNDNE R1.y, PV.w 0586 00000c01 40200c91 z: MOV R1.z, |R1.w| 0588 801fa400 60000110 w: MUL_IEEE R0.w, R0.y, [0x40800000 4].x 0590 40800000 0592 00000cfe 20000990 98 y: RNDNE R0.y, PV.w 0594 00000c03 40000c91 z: MOV R0.z, |R3.w| 0596 801fa4fe 600308fe w: MULADD_IEEE R0.w, PV.y, [0x42040000 33].x, PV.z 0598 42040000 0600 001facfe 00200110 99 x: MUL_IEEE R1.x, PV.w, [0x3bc7ce0a 0.00609756].x 0602 809fa4fe 600308fe w: MULADD_IEEE R0.w, PV.y, [0x42040000 33].y, PV.z 0604 3bc7ce0a 0605 42040000 0606 801facfe 20200110 100 y: MUL_IEEE R1.y, PV.w, [0x3bc7ce0a 0.00609756].x 0608 3bc7ce0a 0190 00000078 80400000 TEX 1 @240 0240 00011011 f00d1000 84800000 SAMPLE_L R0.xyzw, R1.xyy0, RID:16, SID:0 CT:NNNN 0192 00000131 a0040000 ALU 2 @610 0610 00000000 40400c90 101 z: MOV R2.z, R0.x 0612 80000400 60400c90 w: MOV R2.w, R0.y 0194 c0010000 95200688 EXPORT_DONE PIXEL 0 R2.xyzw 0196 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #100 OPT =================================== PS/CAYMAN/CAYMAN ===== ===== 520 dw ===== 6 gprs ===== 2 stack ======================================== 0000 00000052 a00c0000 ALU 4 @164 0164 00380400 00946b10 1 x: INTERP_XY R4.x, R0.y, Param0.x VEC_210 0166 00b80000 20946b10 y: INTERP_XY R4.y, R0.x, Param0.y VEC_210 0168 01380400 40146b00 z: INTERP_XY __.z, R0.y, Param0.z VEC_210 0170 81b80000 60146b00 w: INTERP_XY __.w, R0.x, Param0.w VEC_210 0002 00000056 80400000 TEX 1 @172 0172 00041110 f00d1001 fc808000 SAMPLE R1.xyzw, R4.xy__, RID:17, SID:1 CT:NNNN 0004 00000058 a4000000 ALU_PUSH_BEFORE 1 @176 0176 801f0401 00001004 2 M x: PRED_SETE __.x, R1.y, 0 0006 00000005 82800000 JUMP @10 0008 00000059 a0040000 ALU 2 @178 0178 000000f8 00400c90 3 x: MOV R2.x, 0 0180 800000f8 20400c90 y: MOV R2.y, 0 0010 00000029 83400001 ELSE @82 POP:1 0012 4000005b a00c0000 ALU 4 @182 KC0[CB0:0-15] 0182 801f0401 20400590 4 y: SETNE R2.y, R1.y, 0 0184 000000fd 00000c90 5 x: MOV R0.x, [0xbfc00000 -1.5].x 0186 801f0480 20630404 y: MULADD_IEEE R3.y, KC0[0].y, 0, R4.y 0188 bfc00000 0014 00000015 81800000 LOOP_START_DX10 @42 0016 0000005f a4040000 ALU_PUSH_BEFORE 2 @190 0190 800000fd 00001104 6 M x: PRED_SETGE __.x, [0xc1800000 -16].x, R0.x 0192 c1800000 0018 0000000b 82800000 JUMP @22 0020 00000061 a0040000 ALU 2 @194 0194 000000fa 20000c90 7 y: MOV R0.y, 1 0196 80000000 40000c90 z: MOV R0.z, R0.x 0022 0000000f 83400001 ELSE @30 POP:1 0024 40000063 a0000000 ALU 1 @198 KC0[CB0:0-15] 0198 80000080 00630004 8 x: MULADD_IEEE R3.x, KC0[0].x, R0.x, R4.x 0026 00000064 80400000 TEX 1 @200 0200 00031211 f00d1002 84810000 SAMPLE_L R2.xyzw, R3.xyy0, RID:18, SID:2 CT:NNNN 0028 00000066 a8100000 ALU_POP_AFTER 5 @204 0204 001fa402 2f800710 9 y: SETGE_DX10 T0.y, R2.y, [0x3f666666 0.9].x 0206 809fa000 4f800010 z: ADD T0.z, R0.x, [0xc0000000 -2].y 0208 3f666666 0209 c0000000 0210 001f447c 200380f8 10 y: CNDE_INT R0.y, T0.y, 1, 0 0212 8000047c 4003887c z: CNDE_INT R0.z, T0.y, R0.x, T0.z 0030 0000006b a4100000 ALU_PUSH_BEFORE 5 @214 0214 801fa400 6f800b90 11 w: LSHL_INT T0.w, R0.y, [0x0000001f 4.34403e-44].x 0216 0000001f 0218 801fac7c 0f800a90 12 x: ASHR_INT T0.x, T0.w, [0x0000001f 4.34403e-44].x 0220 0000001f 0222 801f007c 00002284 13 M x: PRED_SETNE_INT __.x, T0.x, 0 0032 00000013 82800001 JUMP @38 POP:1 0034 00000014 82400000 LOOP_BREAK @40 0036 00000013 83800001 POP @38 POP:1 0038 00000070 a0000000 ALU 1 @224 0224 80000800 00000c90 14 x: MOV R0.x, R0.z 0040 00000008 81400000 LOOP_END @16 0042 00000071 a0100000 ALU 5 @226 0226 801fa000 20a00010 15 y: ADD R5.y, R0.x, [0x3fc00000 1.5].x 0228 3fc00000 0230 000000fd 00400c90 16 x: MOV R2.x, [0x3fc00000 1.5].x 0232 80000405 60000c90 w: MOV R0.w, R5.y 0234 3fc00000 0044 00000024 81800000 LOOP_START_DX10 @72 0046 00000076 a4040000 ALU_PUSH_BEFORE 2 @236 0236 801fa002 00001104 17 M x: PRED_SETGE __.x, R2.x, [0x41800000 16].x 0238 41800000 0048 0000001a 82800000 JUMP @52 0050 00000078 a00c0000 ALU 4 @240 0240 001fa002 20000510 18 y: SETGE R0.y, R2.x, [0x41800000 16].x 0242 000000fa 40400c90 z: MOV R2.z, 1 0244 80000002 60400c90 w: MOV R2.w, R2.x 0246 41800000 0052 0000001e 83400001 ELSE @60 POP:1 0054 4000007c a0000000 ALU 1 @248 KC0[CB0:0-15] 0248 80004080 00630004 19 x: MULADD_IEEE R3.x, KC0[0].x, R2.x, R4.x 0056 0000007e 80400000 TEX 1 @252 0252 00031211 f00d1000 84810000 SAMPLE_L R0.xyzw, R3.xyy0, RID:18, SID:2 CT:NNNN 0058 00000080 a8100000 ALU_POP_AFTER 5 @256 0256 001fa400 4f800710 20 z: SETGE_DX10 T0.z, R0.y, [0x3f666666 0.9].x 0258 809fa002 6f800010 w: ADD T0.w, R2.x, [0x40000000 2].y 0260 3f666666 0261 40000000 0262 001f487c 404380f8 21 z: CNDE_INT R2.z, T0.z, 1, 0 0264 8000487c 60438c7c w: CNDE_INT R2.w, T0.z, R2.x, T0.w 0060 00000085 a4100000 ALU_PUSH_BEFORE 5 @266 0266 801fa802 0f800b90 22 x: LSHL_INT T0.x, R2.z, [0x0000001f 4.34403e-44].x 0268 0000001f 0270 801fa07c 2f800a90 23 y: ASHR_INT T0.y, T0.x, [0x0000001f 4.34403e-44].x 0272 0000001f 0274 801f047c 00002284 24 M x: PRED_SETNE_INT __.x, T0.y, 0 0062 00000022 82800001 JUMP @68 POP:1 0064 00000023 82400000 LOOP_BREAK @70 0066 00000022 83800001 POP @68 POP:1 0068 0000008a a0000000 ALU 1 @276 0276 80000c02 00400c90 25 x: MOV R2.x, R2.w 0070 00000017 81400000 LOOP_END @46 0072 4000008b a0340000 ALU 14 @278 KC0[CB0:0-15] 0278 801fa002 4f800010 26 z: ADD T0.z, R2.x, [0xbfc00000 -1.5].x 0280 bfc00000 0282 801fa400 6f82887c 27 w: MULADD T0.w, R0.y, [0x40000000 2].x, T0.z 0284 40000000 0286 001fa402 0f830405 28 x: MULADD_IEEE T0.x, R2.y, [0xc0000000 -2].x, R5.y 0288 809fac7c 20400210 y: MIN R2.y, T0.w, [0x41800000 16].y 0290 c0000000 0291 41800000 0292 001fa07c 40400190 29 z: MAX R2.z, T0.x, [0xc1800000 -16].x 0294 801f2402 6f800010 w: ADD T0.w, R2.y, 1.0 0296 c1800000 0298 00100802 00030004 30 x: MULADD_IEEE R0.x, R2.z, KC0[0].x, R4.x 0300 001fa480 20030404 y: MULADD_IEEE R0.y, KC0[0].y, [0xbe800000 -0.25].x, R4.y 0302 80100c7c 40030004 z: MULADD_IEEE R0.z, T0.w, KC0[0].x, R4.x 0304 be800000 0074 0000009a 80400400 TEX 2 @308 0308 00001211 f01c7e00 84a10000 SAMPLE_L R0.__x_, R0.zyy0, RID:18, SID:2 CT:NNNN 0312 00001211 f01ff000 84810000 SAMPLE_L R0.x___, R0.xyy0, RID:18, SID:2 CT:NNNN 0076 0000009e a0300000 ALU 13 @316 0316 001fa800 0f800110 31 x: MUL_IEEE T0.x, R0.z, [0x40800000 4].x 0318 801fa000 2f800110 y: MUL_IEEE T0.y, R0.x, [0x40800000 4].x 0320 40800000 0322 00000802 0f800c91 32 x: MOV T0.x, |R2.z| 0324 0000007c 20000990 y: RNDNE R0.y, T0.x 0326 00000402 4f800c91 z: MOV T0.z, |R2.y| 0328 8000047c 6f880990 w: RNDNE T0.w, T0.y VEC_120 0330 001fa400 2f83087c 33 y: MULADD_IEEE T0.y, R0.y, [0x42040000 33].x, T0.z 0332 801fac7c 4f83007c z: MULADD_IEEE T0.z, T0.w, [0x42040000 33].x, T0.x 0334 42040000 0336 001fa87c 00000110 34 x: MUL_IEEE R0.x, T0.z, [0x3bc7ce0a 0.00609756].x 0338 801fa47c 40000110 z: MUL_IEEE R0.z, T0.y, [0x3bc7ce0a 0.00609756].x 0340 3bc7ce0a 0078 000000ac 80400000 TEX 1 @344 0344 00001011 f01f9002 89000000 SAMPLE_L R2.xy__, R0.xzz0, RID:16, SID:0 CT:NNNN 0080 00000029 83800001 POP @82 POP:1 0082 000000ae a4000000 ALU_PUSH_BEFORE 1 @348 0348 801f0001 00001004 35 M x: PRED_SETE __.x, R1.x, 0 0084 0000002c 82800000 JUMP @88 0086 000000af a0040000 ALU 2 @350 0350 000000f8 40400c90 36 z: MOV R2.z, 0 0352 800000f8 60400c90 w: MOV R2.w, 0 0088 00000050 83400001 ELSE @160 POP:1 0090 400000b1 a0080000 ALU 3 @354 KC0[CB0:0-15] 0354 000000fd 00000c90 37 x: MOV R0.x, [0xbfc00000 -1.5].x 0356 801f0080 40430004 z: MULADD_IEEE R2.z, KC0[0].x, 0, R4.x 0358 bfc00000 0092 0000003c 81800000 LOOP_START_DX10 @120 0094 000000b4 a4040000 ALU_PUSH_BEFORE 2 @360 0360 800000fd 00001104 38 M x: PRED_SETGE __.x, [0xc1800000 -16].x, R0.x 0362 c1800000 0096 00000032 82800000 JUMP @100 0098 000000b6 a0040000 ALU 2 @364 0364 00000000 40000c90 39 z: MOV R0.z, R0.x 0366 800000fa 60000c90 w: MOV R0.w, 1 0100 00000036 83400001 ELSE @108 POP:1 0102 400000b8 a0000000 ALU 1 @368 KC0[CB0:0-15] 0368 80000480 60430404 40 w: MULADD_IEEE R2.w, KC0[0].y, R0.x, R4.y 0104 000000ba 80400000 TEX 1 @372 0372 00021211 f00d1001 8da10000 SAMPLE_L R1.xyzw, R2.zww0, RID:18, SID:2 CT:NNNN 0106 000000bc a8100000 ALU_POP_AFTER 5 @376 0376 001fa000 0f800010 41 x: ADD T0.x, R0.x, [0xc0000000 -2].x 0378 809fa001 6f880710 w: SETGE_DX10 T0.w, R1.x, [0x3f666666 0.9].y VEC_120 0380 c0000000 0381 3f666666 0382 00000c7c 4003807c 42 z: CNDE_INT R0.z, T0.w, R0.x, T0.x 0384 801f4c7c 600380f8 w: CNDE_INT R0.w, T0.w, 1, 0 0108 000000c1 a4100000 ALU_PUSH_BEFORE 5 @386 0386 801fac00 2f800b90 43 y: LSHL_INT T0.y, R0.w, [0x0000001f 4.34403e-44].x 0388 0000001f 0390 801fa47c 4f800a90 44 z: ASHR_INT T0.z, T0.y, [0x0000001f 4.34403e-44].x 0392 0000001f 0394 801f087c 00002284 45 M x: PRED_SETNE_INT __.x, T0.z, 0 0110 0000003a 82800001 JUMP @116 POP:1 0112 0000003b 82400000 LOOP_BREAK @118 0114 0000003a 83800001 POP @116 POP:1 0116 000000c6 a0000000 ALU 1 @396 0396 80000800 00000c90 46 x: MOV R0.x, R0.z 0118 0000002f 81400000 LOOP_END @94 0120 000000c7 a0200000 ALU 9 @398 0398 801fa000 60000010 47 w: ADD R0.w, R0.x, [0x3fc00000 1.5].x 0400 3fc00000 0402 801fa001 6f830c00 48 w: MULADD_IEEE T0.w, R1.x, [0xc0000000 -2].x, R0.w 0404 c0000000 0406 801fac7c 00600190 49 x: MAX R3.x, T0.w, [0xc1800000 -16].x 0408 c1800000 0410 800000fd 00200c90 50 x: MOV R1.x, [0x3fc00000 1.5].x 0412 3fc00000 0414 80000003 00000c90 51 x: MOV R0.x, R3.x 0122 0000004b 81800000 LOOP_START_DX10 @150 0124 000000d0 a4040000 ALU_PUSH_BEFORE 2 @416 0416 801fa001 00001104 52 M x: PRED_SETGE __.x, R1.x, [0x41800000 16].x 0418 41800000 0126 00000041 82800000 JUMP @130 0128 000000d2 a0080000 ALU 3 @420 0420 000000fa 20200c90 53 y: MOV R1.y, 1 0422 800020fd 40200690 z: SETGT_DX10 R1.z, [0x41800000 16].x, R1.x 0424 41800000 0130 00000045 83400001 ELSE @138 POP:1 0132 400000d5 a0000000 ALU 1 @426 KC0[CB0:0-15] 0426 80002480 60430404 54 w: MULADD_IEEE R2.w, KC0[0].y, R1.x, R4.y 0134 000000d6 80400000 TEX 1 @428 0428 00021211 f00d1000 8da10000 SAMPLE_L R0.xyzw, R2.zww0, RID:18, SID:2 CT:NNNN 0136 000000d8 a8100000 ALU_POP_AFTER 5 @432 0432 001fa000 2f800710 55 y: SETGE_DX10 T0.y, R0.x, [0x3f666666 0.9].x 0434 809fa001 4f880010 z: ADD T0.z, R1.x, [0x40000000 2].y VEC_120 0436 3f666666 0437 40000000 0438 001f447c 202380f8 56 y: CNDE_INT R1.y, T0.y, 1, 0 0440 808f847c 4023887c z: CNDE_INT R1.z, T0.y, T0.y, T0.z 0138 000000dd a4100000 ALU_PUSH_BEFORE 5 @442 0442 801fa401 6f800b90 57 w: LSHL_INT T0.w, R1.y, [0x0000001f 4.34403e-44].x 0444 0000001f 0446 801fac7c 0f800a90 58 x: ASHR_INT T0.x, T0.w, [0x0000001f 4.34403e-44].x 0448 0000001f 0450 801f007c 00002284 59 M x: PRED_SETNE_INT __.x, T0.x, 0 0140 00000049 82800001 JUMP @146 POP:1 0142 0000004a 82400000 LOOP_BREAK @148 0144 00000049 83800001 POP @146 POP:1 0146 000000e2 a0000000 ALU 1 @452 0452 80000801 00200c90 60 x: MOV R1.x, R1.z 0148 0000003e 81400000 LOOP_END @124 0150 400000e3 a0280000 ALU 11 @454 KC0[CB0:0-15] 0454 801fa001 2f800010 61 y: ADD T0.y, R1.x, [0xbfc00000 -1.5].x 0456 bfc00000 0458 801fa000 4f82847c 62 z: MULADD T0.z, R0.x, [0x40000000 2].x, T0.y 0460 40000000 0462 801fa87c 60000210 63 w: MIN R0.w, T0.z, [0x41800000 16].x 0464 41800000 0466 801f2c00 0f800010 64 x: ADD T0.x, R0.w, 1.0 0468 001fa080 00030004 65 x: MULADD_IEEE R0.x, KC0[0].x, [0xbe800000 -0.25].x, R4.x 0470 0090007c 20030404 y: MULADD_IEEE R0.y, T0.x, KC0[0].y, R4.y 0472 80900003 400b0404 z: MULADD_IEEE R0.z, R3.x, KC0[0].y, R4.y VEC_120 0474 be800000 0152 000000ee 80400400 TEX 2 @476 0476 00001211 f01f9e00 84810000 SAMPLE_L R0._y__, R0.xyy0, RID:18, SID:2 CT:NNNN 0480 00001211 f01ff200 89010000 SAMPLE_L R0.y___, R0.xzz0, RID:18, SID:2 CT:NNNN 0154 000000f2 a0300000 ALU 13 @484 0484 001fa400 2f800110 66 y: MUL_IEEE T0.y, R0.y, [0x40800000 4].x 0486 801fa000 4f800110 z: MUL_IEEE T0.z, R0.x, [0x40800000 4].x 0488 40800000 0490 00000c00 0f800c91 67 x: MOV T0.x, |R0.w| 0492 0000087c 2f800990 y: RNDNE T0.y, T0.z 0494 00000003 4f800c91 z: MOV T0.z, |R3.x| 0496 8000047c 6f800990 w: RNDNE T0.w, T0.y 0498 001fa47c 0f83087c 68 x: MULADD_IEEE T0.x, T0.y, [0x42040000 33].x, T0.z 0500 801fac7c 6f83007c w: MULADD_IEEE T0.w, T0.w, [0x42040000 33].x, T0.x 0502 42040000 0504 001fa07c 00000110 69 x: MUL_IEEE R0.x, T0.x, [0x3bc7ce0a 0.00609756].x 0506 801fac7c 20000110 y: MUL_IEEE R0.y, T0.w, [0x3bc7ce0a 0.00609756].x 0508 3bc7ce0a 0156 00000100 80400000 TEX 1 @512 0512 00001011 f01f9000 84800000 SAMPLE_L R0.xy__, R0.xyy0, RID:16, SID:0 CT:NNNN 0158 00000102 a8040000 ALU_POP_AFTER 2 @516 0516 00000000 40400c90 70 z: MOV R2.z, R0.x 0518 80000400 60400c90 w: MOV R2.w, R0.y 0160 c0010000 95000688 EXPORT_DONE PIXEL 0 R2.xyzw 0162 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], PERSPECTIVE DCL IN[1], GENERIC[10], PERSPECTIVE DCL IN[2], GENERIC[11], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL SAMP[1] DCL TEMP[0..8] IMM[0] FLT32 { 1.0000, 0.0000, 0.0000, 0.0000} 0: TEX TEMP[0], IN[0].xyyy, SAMP[1], 2D 1: MOV TEMP[1].x, TEMP[0].xxxx 2: TEX TEMP[2].y, IN[2].zwww, SAMP[1], 2D 3: MOV TEMP[1].y, TEMP[2].yyyy 4: MOV TEMP[1].z, TEMP[0].zzzz 5: TEX TEMP[1].w, IN[2].xyyy, SAMP[1], 2D 6: MUL TEMP[4], TEMP[1], TEMP[1] 7: MUL TEMP[5], TEMP[4], TEMP[1] 8: DP4 TEMP[1].x, TEMP[5], IMM[0].xxxx 9: SLT TEMP[4].x, TEMP[1].xxxx, IMM[0].yyyy 10: IF TEMP[4].xxxx :12 11: KILL 12: ENDIF 13: TEX TEMP[4], IN[0].xyyy, SAMP[0], 2D 14: TEX TEMP[6], IN[1].zwww, SAMP[0], 2D 15: ADD TEMP[7].x, IMM[0].xxxx, -TEMP[0].xxxx 16: MUL TEMP[8], TEMP[4], TEMP[7].xxxx 17: MAD TEMP[7], TEMP[6], TEMP[0].xxxx, TEMP[8] 18: MUL TEMP[6], TEMP[7], TEMP[5].xxxx 19: TEX TEMP[7], IN[2].zwww, SAMP[0], 2D 20: ADD TEMP[8].x, IMM[0].xxxx, -TEMP[2].yyyy 21: MUL TEMP[3], TEMP[4], TEMP[8].xxxx 22: MAD TEMP[8], TEMP[7], TEMP[2].yyyy, TEMP[3] 23: MAD TEMP[2], TEMP[8], TEMP[5].yyyy, TEMP[6] 24: TEX TEMP[6], IN[1].xyyy, SAMP[0], 2D 25: ADD TEMP[7].x, IMM[0].xxxx, -TEMP[0].zzzz 26: MUL TEMP[8], TEMP[4], TEMP[7].xxxx 27: MAD TEMP[7], TEMP[6], TEMP[0].zzzz, TEMP[8] 28: MAD TEMP[0], TEMP[7], TEMP[5].zzzz, TEMP[2] 29: TEX TEMP[2], IN[2].xyyy, SAMP[0], 2D 30: ADD TEMP[6].x, IMM[0].xxxx, -TEMP[1].wwww 31: MUL TEMP[7], TEMP[4], TEMP[6].xxxx 32: MAD TEMP[4], TEMP[2], TEMP[1].wwww, TEMP[7] 33: MAD TEMP[2], TEMP[4], TEMP[5].wwww, TEMP[0] 34: RCP TEMP[0].x, TEMP[1].xxxx 35: MUL OUT[0], TEMP[2], TEMP[0].xxxx 36: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg, <4 x float> inreg, <4 x float> inreg) #0 { main_body: %4 = extractelement <4 x float> %0, i32 0 %5 = extractelement <4 x float> %0, i32 1 %6 = call <2 x float> @llvm.R600.interp.xy(i32 0, float %4, float %5) %7 = call <2 x float> @llvm.R600.interp.zw(i32 0, float %4, float %5) %8 = shufflevector <2 x float> %6, <2 x float> %7, <4 x i32> %9 = extractelement <4 x float> %8, i32 0 %10 = extractelement <4 x float> %8, i32 1 %11 = extractelement <4 x float> %0, i32 0 %12 = extractelement <4 x float> %0, i32 1 %13 = call <2 x float> @llvm.R600.interp.xy(i32 1, float %11, float %12) %14 = call <2 x float> @llvm.R600.interp.zw(i32 1, float %11, float %12) %15 = shufflevector <2 x float> %13, <2 x float> %14, <4 x i32> %16 = extractelement <4 x float> %15, i32 0 %17 = extractelement <4 x float> %15, i32 1 %18 = extractelement <4 x float> %15, i32 2 %19 = extractelement <4 x float> %15, i32 3 %20 = extractelement <4 x float> %0, i32 0 %21 = extractelement <4 x float> %0, i32 1 %22 = call <2 x float> @llvm.R600.interp.xy(i32 2, float %20, float %21) %23 = call <2 x float> @llvm.R600.interp.zw(i32 2, float %20, float %21) %24 = shufflevector <2 x float> %22, <2 x float> %23, <4 x i32> %25 = extractelement <4 x float> %24, i32 0 %26 = extractelement <4 x float> %24, i32 1 %27 = extractelement <4 x float> %24, i32 2 %28 = extractelement <4 x float> %24, i32 3 %29 = insertelement <4 x float> undef, float %9, i32 0 %30 = insertelement <4 x float> %29, float %10, i32 1 %31 = insertelement <4 x float> %30, float %10, i32 2 %32 = insertelement <4 x float> %31, float %10, i32 3 %33 = extractelement <4 x float> %32, i32 0 %34 = extractelement <4 x float> %32, i32 1 %35 = insertelement <4 x float> undef, float %33, i32 0 %36 = insertelement <4 x float> %35, float %34, i32 1 %37 = insertelement <4 x float> %36, float undef, i32 2 %38 = insertelement <4 x float> %37, float undef, i32 3 %39 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %38, i32 17, i32 1, i32 2) %40 = extractelement <4 x float> %39, i32 0 %41 = extractelement <4 x float> %39, i32 2 %42 = insertelement <4 x float> undef, float %27, i32 0 %43 = insertelement <4 x float> %42, float %28, i32 1 %44 = insertelement <4 x float> %43, float %28, i32 2 %45 = insertelement <4 x float> %44, float %28, i32 3 %46 = extractelement <4 x float> %45, i32 0 %47 = extractelement <4 x float> %45, i32 1 %48 = insertelement <4 x float> undef, float %46, i32 0 %49 = insertelement <4 x float> %48, float %47, i32 1 %50 = insertelement <4 x float> %49, float undef, i32 2 %51 = insertelement <4 x float> %50, float undef, i32 3 %52 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %51, i32 17, i32 1, i32 2) %53 = extractelement <4 x float> %52, i32 1 %54 = insertelement <4 x float> undef, float %25, i32 0 %55 = insertelement <4 x float> %54, float %26, i32 1 %56 = insertelement <4 x float> %55, float %26, i32 2 %57 = insertelement <4 x float> %56, float %26, i32 3 %58 = extractelement <4 x float> %57, i32 0 %59 = extractelement <4 x float> %57, i32 1 %60 = insertelement <4 x float> undef, float %58, i32 0 %61 = insertelement <4 x float> %60, float %59, i32 1 %62 = insertelement <4 x float> %61, float undef, i32 2 %63 = insertelement <4 x float> %62, float undef, i32 3 %64 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %63, i32 17, i32 1, i32 2) %65 = extractelement <4 x float> %64, i32 3 %66 = fmul float %40, %40 %67 = fmul float %53, %53 %68 = fmul float %41, %41 %69 = fmul float %65, %65 %70 = fmul float %66, %40 %71 = fmul float %67, %53 %72 = fmul float %68, %41 %73 = fmul float %69, %65 %74 = insertelement <4 x float> undef, float %70, i32 0 %75 = insertelement <4 x float> %74, float %71, i32 1 %76 = insertelement <4 x float> %75, float %72, i32 2 %77 = insertelement <4 x float> %76, float %73, i32 3 %78 = call float @llvm.AMDGPU.dp4(<4 x float> %77, <4 x float> ) %79 = fcmp olt float %78, 0x3EE4F8B580000000 %80 = select i1 %79, float 1.000000e+00, float 0.000000e+00 %81 = fcmp une float %80, 0.000000e+00 br i1 %81, label %IF, label %ENDIF IF: ; preds = %main_body call void @llvm.AMDGPU.kilp() br label %ENDIF ENDIF: ; preds = %main_body, %IF %82 = insertelement <4 x float> undef, float %9, i32 0 %83 = insertelement <4 x float> %82, float %10, i32 1 %84 = insertelement <4 x float> %83, float %10, i32 2 %85 = insertelement <4 x float> %84, float %10, i32 3 %86 = extractelement <4 x float> %85, i32 0 %87 = extractelement <4 x float> %85, i32 1 %88 = insertelement <4 x float> undef, float %86, i32 0 %89 = insertelement <4 x float> %88, float %87, i32 1 %90 = insertelement <4 x float> %89, float undef, i32 2 %91 = insertelement <4 x float> %90, float undef, i32 3 %92 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %91, i32 16, i32 0, i32 2) %93 = extractelement <4 x float> %92, i32 0 %94 = extractelement <4 x float> %92, i32 1 %95 = extractelement <4 x float> %92, i32 2 %96 = extractelement <4 x float> %92, i32 3 %97 = insertelement <4 x float> undef, float %18, i32 0 %98 = insertelement <4 x float> %97, float %19, i32 1 %99 = insertelement <4 x float> %98, float %19, i32 2 %100 = insertelement <4 x float> %99, float %19, i32 3 %101 = extractelement <4 x float> %100, i32 0 %102 = extractelement <4 x float> %100, i32 1 %103 = insertelement <4 x float> undef, float %101, i32 0 %104 = insertelement <4 x float> %103, float %102, i32 1 %105 = insertelement <4 x float> %104, float undef, i32 2 %106 = insertelement <4 x float> %105, float undef, i32 3 %107 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %106, i32 16, i32 0, i32 2) %108 = extractelement <4 x float> %107, i32 0 %109 = extractelement <4 x float> %107, i32 1 %110 = extractelement <4 x float> %107, i32 2 %111 = extractelement <4 x float> %107, i32 3 %112 = fsub float -0.000000e+00, %40 %113 = fadd float 1.000000e+00, %112 %114 = fmul float %93, %113 %115 = fmul float %94, %113 %116 = fmul float %95, %113 %117 = fmul float %96, %113 %118 = fmul float %108, %40 %119 = fadd float %118, %114 %120 = fmul float %109, %40 %121 = fadd float %120, %115 %122 = fmul float %110, %40 %123 = fadd float %122, %116 %124 = fmul float %111, %40 %125 = fadd float %124, %117 %126 = fmul float %119, %70 %127 = fmul float %121, %70 %128 = fmul float %123, %70 %129 = fmul float %125, %70 %130 = insertelement <4 x float> undef, float %27, i32 0 %131 = insertelement <4 x float> %130, float %28, i32 1 %132 = insertelement <4 x float> %131, float %28, i32 2 %133 = insertelement <4 x float> %132, float %28, i32 3 %134 = extractelement <4 x float> %133, i32 0 %135 = extractelement <4 x float> %133, i32 1 %136 = insertelement <4 x float> undef, float %134, i32 0 %137 = insertelement <4 x float> %136, float %135, i32 1 %138 = insertelement <4 x float> %137, float undef, i32 2 %139 = insertelement <4 x float> %138, float undef, i32 3 %140 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %139, i32 16, i32 0, i32 2) %141 = extractelement <4 x float> %140, i32 0 %142 = extractelement <4 x float> %140, i32 1 %143 = extractelement <4 x float> %140, i32 2 %144 = extractelement <4 x float> %140, i32 3 %145 = fsub float -0.000000e+00, %53 %146 = fadd float 1.000000e+00, %145 %147 = fmul float %93, %146 %148 = fmul float %94, %146 %149 = fmul float %95, %146 %150 = fmul float %96, %146 %151 = fmul float %141, %53 %152 = fadd float %151, %147 %153 = fmul float %142, %53 %154 = fadd float %153, %148 %155 = fmul float %143, %53 %156 = fadd float %155, %149 %157 = fmul float %144, %53 %158 = fadd float %157, %150 %159 = fmul float %152, %71 %160 = fadd float %159, %126 %161 = fmul float %154, %71 %162 = fadd float %161, %127 %163 = fmul float %156, %71 %164 = fadd float %163, %128 %165 = fmul float %158, %71 %166 = fadd float %165, %129 %167 = insertelement <4 x float> undef, float %16, i32 0 %168 = insertelement <4 x float> %167, float %17, i32 1 %169 = insertelement <4 x float> %168, float %17, i32 2 %170 = insertelement <4 x float> %169, float %17, i32 3 %171 = extractelement <4 x float> %170, i32 0 %172 = extractelement <4 x float> %170, i32 1 %173 = insertelement <4 x float> undef, float %171, i32 0 %174 = insertelement <4 x float> %173, float %172, i32 1 %175 = insertelement <4 x float> %174, float undef, i32 2 %176 = insertelement <4 x float> %175, float undef, i32 3 %177 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %176, i32 16, i32 0, i32 2) %178 = extractelement <4 x float> %177, i32 0 %179 = extractelement <4 x float> %177, i32 1 %180 = extractelement <4 x float> %177, i32 2 %181 = extractelement <4 x float> %177, i32 3 %182 = fsub float -0.000000e+00, %41 %183 = fadd float 1.000000e+00, %182 %184 = fmul float %93, %183 %185 = fmul float %94, %183 %186 = fmul float %95, %183 %187 = fmul float %96, %183 %188 = fmul float %178, %41 %189 = fadd float %188, %184 %190 = fmul float %179, %41 %191 = fadd float %190, %185 %192 = fmul float %180, %41 %193 = fadd float %192, %186 %194 = fmul float %181, %41 %195 = fadd float %194, %187 %196 = fmul float %189, %72 %197 = fadd float %196, %160 %198 = fmul float %191, %72 %199 = fadd float %198, %162 %200 = fmul float %193, %72 %201 = fadd float %200, %164 %202 = fmul float %195, %72 %203 = fadd float %202, %166 %204 = insertelement <4 x float> undef, float %25, i32 0 %205 = insertelement <4 x float> %204, float %26, i32 1 %206 = insertelement <4 x float> %205, float %26, i32 2 %207 = insertelement <4 x float> %206, float %26, i32 3 %208 = extractelement <4 x float> %207, i32 0 %209 = extractelement <4 x float> %207, i32 1 %210 = insertelement <4 x float> undef, float %208, i32 0 %211 = insertelement <4 x float> %210, float %209, i32 1 %212 = insertelement <4 x float> %211, float undef, i32 2 %213 = insertelement <4 x float> %212, float undef, i32 3 %214 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %213, i32 16, i32 0, i32 2) %215 = extractelement <4 x float> %214, i32 0 %216 = extractelement <4 x float> %214, i32 1 %217 = extractelement <4 x float> %214, i32 2 %218 = extractelement <4 x float> %214, i32 3 %219 = fsub float -0.000000e+00, %65 %220 = fadd float 1.000000e+00, %219 %221 = fmul float %93, %220 %222 = fmul float %94, %220 %223 = fmul float %95, %220 %224 = fmul float %96, %220 %225 = fmul float %215, %65 %226 = fadd float %225, %221 %227 = fmul float %216, %65 %228 = fadd float %227, %222 %229 = fmul float %217, %65 %230 = fadd float %229, %223 %231 = fmul float %218, %65 %232 = fadd float %231, %224 %233 = fmul float %226, %73 %234 = fadd float %233, %197 %235 = fmul float %228, %73 %236 = fadd float %235, %199 %237 = fmul float %230, %73 %238 = fadd float %237, %201 %239 = fmul float %232, %73 %240 = fadd float %239, %203 %241 = fdiv float 1.000000e+00, %78 %242 = fmul float %234, %241 %243 = fmul float %236, %241 %244 = fmul float %238, %241 %245 = fmul float %240, %241 %246 = insertelement <4 x float> undef, float %242, i32 0 %247 = insertelement <4 x float> %246, float %243, i32 1 %248 = insertelement <4 x float> %247, float %244, i32 2 %249 = insertelement <4 x float> %248, float %245, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %249, i32 0, i32 0) ret void } ; Function Attrs: readnone declare <2 x float> @llvm.R600.interp.xy(i32, float, float) #1 ; Function Attrs: readnone declare <2 x float> @llvm.R600.interp.zw(i32, float, float) #1 ; Function Attrs: readnone declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32, i32) #1 ; Function Attrs: readnone declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1 declare void @llvm.AMDGPU.kilp() declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } Shader Disassembly: ALU 21, @26, KC0[], KC1[] ; 0000001A A0540000 TEX 2 @10 ; 0000000A 80400800 ALU_PUSH_BEFORE 15, @48, KC0[], KC1[] ; 00000030 A43C0000 JUMP @5 POP:1 ; 00000005 82800001 ALU_POP_AFTER 0, @64, KC0[], KC1[] ; 00000040 A8000000 ALU 3, @65, KC0[], KC1[] ; 00000041 A00C0000 TEX 4 @16 ; 00000010 80401000 ALU 59, @69, KC0[], KC1[] ; 00000045 A0EC0000 EXPORT T4.XYZW ; C0020000 95200688 CF_END ; 00000000 88000000 Fetch clause starting at 10: ; TEX_SAMPLE T2.XYZW, T0.XY__ RID:17 SID:1 CT:NNNN ; 00001110 F00D1002 FC808000 00000000 TEX_SAMPLE T0.XYZW, T4.XY__ RID:17 SID:1 CT:NNNN ; 00041110 F00D1000 FC808000 00000000 TEX_SAMPLE T1.XYZW, T7.XY__ RID:17 SID:1 CT:NNNN ; 00071110 F00D1001 FC808000 00000000 Fetch clause starting at 16: ; TEX_SAMPLE T7.XYZW, T7.XY__ RID:16 SID:0 CT:NNNN ; 00071010 F00D1007 FC800000 00000000 TEX_SAMPLE T6.XYZW, T6.XY__ RID:16 SID:0 CT:NNNN ; 00061010 F00D1006 FC800000 00000000 TEX_SAMPLE T8.XYZW, T10.XY__ RID:16 SID:0 CT:NNNN ; 000A1010 F00D1008 FC800000 00000000 TEX_SAMPLE T9.XYZW, T9.XY__ RID:16 SID:0 CT:NNNN ; 00091010 F00D1009 FC800000 00000000 TEX_SAMPLE T4.XYZW, T4.XY__ RID:16 SID:0 CT:NNNN ; 00041010 F00D1004 FC800000 00000000 ALU clause starting at 26: ; INTERP_XY T4.X, T0.Y, ARRAY_BASE, ; 00380400 00946B10 INTERP_XY T4.Y, T0.X, ARRAY_BASE, ; 00380000 20946B10 INTERP_XY T0.Z (MASKED), T0.Y, ARRAY_BASE, ; 00380400 40146B00 INTERP_XY * T0.W (MASKED), T0.X, ARRAY_BASE, ; 80380000 60146B00 INTERP_XY T6.X, T0.Y, ARRAY_BASE, ; 00382400 00D46B10 INTERP_XY T6.Y, T0.X, ARRAY_BASE, ; 00382000 20D46B10 INTERP_XY T0.Z (MASKED), T0.Y, ARRAY_BASE, ; 00382400 40146B00 INTERP_XY * T0.W (MASKED), T0.X, ARRAY_BASE, ; 80382000 60146B00 INTERP_ZW T0.X (MASKED), T0.Y, ARRAY_BASE, ; 00382400 00146B80 INTERP_ZW T0.Y (MASKED), T0.X, ARRAY_BASE, ; 00382000 20146B80 INTERP_ZW T8.Z, T0.Y, ARRAY_BASE, ; 00382400 41146B90 INTERP_ZW * T5.W, T0.X, ARRAY_BASE, ; 80382000 60B46B90 INTERP_XY T7.X, T0.Y, ARRAY_BASE, ; 00384400 00F46B10 INTERP_XY T7.Y, T0.X, ARRAY_BASE, ; 00384000 20F46B10 INTERP_XY T0.Z (MASKED), T0.Y, ARRAY_BASE, ; 00384400 40146B00 INTERP_XY * T0.W (MASKED), T0.X, ARRAY_BASE, ; 80384000 60146B00 INTERP_ZW T0.X (MASKED), T0.Y, ARRAY_BASE, ; 00384400 00146B80 INTERP_ZW T0.Y (MASKED), T0.X, ARRAY_BASE, ; 00384000 20146B80 INTERP_ZW T5.Z, T0.Y, ARRAY_BASE, ; 00384400 40B46B90 INTERP_ZW * T8.W, T0.X, ARRAY_BASE, ; 80384000 61146B90 MOV T0.X, PV.Z, ; 000008FE 00000C90 MOV * T0.Y, PV.W, ; 80000CFE 20000C90 ALU clause starting at 48: ; MUL_IEEE T3.X, T1.W, T1.W, ; 01802C01 00600110 MUL_IEEE T5.Y, T0.Z, T0.Z, ; 01000800 20A00110 MUL_IEEE T3.Z, T2.Y, T2.Y, ; 00804402 40600110 MUL_IEEE * T3.W, T0.X, T0.X, ; 80000000 60600110 MUL_IEEE T5.X, PV.W, T0.X, ; 00000CFE 00A00110 MUL_IEEE T3.Y, PV.Z, T2.Y, ; 008048FE 20600110 MUL_IEEE T3.Z, PV.Y, T0.Z, ; 010004FE 40600110 MUL_IEEE * T3.W, PV.X, T1.W, ; 818020FE 60600110 DOT4 T3.X, T5.X, 1.0, ; 001F2005 00605F10 DOT4 T3.Y (MASKED), T3.Y, 1.0, ; 001F2403 20605F00 DOT4 T3.Z (MASKED), T3.Z, 1.0, ; 001F2803 40605F00 DOT4 * T3.W (MASKED), T3.W, 1.0, ; 801F2C03 60605F00 SETGT * T9.W, literal.x, PV.X, ; 801FC0FD 61200490 925353388(1.000000e-05), 0(0.000000e+00) ; 3727C5AC 00000000 SETE_DX10 * T9.W, PV.W, 0.0, ; 801F0CFE 61200610 PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PV.W, 0.0, ; 801F0CFE 00002104 ALU clause starting at 64: ; KILLGT * T5.Y (MASKED), 1.0, 0.0, ; 801F00F9 20A01680 ALU clause starting at 65: ; MOV * T9.X, T8.Z, ; 80000808 01200C90 MOV T10.X, T5.Z, ; 00000805 01400C90 MOV * T9.Y, T5.W, ; 80000C05 21200C90 MOV * T10.Y, T8.W, ; 80000C08 21400C90 ALU clause starting at 69: ; ADD * T5.W, -T0.X, 1.0, ; 801F3000 60A00010 MUL_IEEE T5.Z, T4.Z, PV.W, ; 019FC804 40A00110 ADD * T10.W, -T2.Y, 1.0, ; 801F3402 61400010 MUL_IEEE T5.Y, T4.Z, PV.W, ; 019FC804 20A00110 MULADD_IEEE T5.Z, T9.Z, T0.X, PV.Z, BS:VEC_120/SCL_212 ; 00000809 40AB08FE ADD * T11.W, -T0.Z, 1.0, BS:VEC_201 ; 801F3800 61700010 MUL_IEEE T10.X, T4.Z, PV.W, ; 019FC804 01400110 MUL_IEEE T10.Y, PV.Z, T5.X, ; 0000A8FE 21400110 MULADD_IEEE T5.Z, T8.Z, T2.Y, PV.Y, BS:VEC_120/SCL_212 ; 00804808 40AB04FE ADD * T12.W, -T1.W, 1.0, ; 801F3C01 61800010 MUL_IEEE T5.Y, T4.Z, PV.W, ; 019FC804 20A00110 MULADD_IEEE T5.Z, PV.Z, T3.Y, PV.Y, ; 008068FE 40A304FE MULADD_IEEE * T13.W, T6.Z, T0.Z, PV.X, BS:VEC_120/SCL_212 ; 81000806 61AB00FE MULADD_IEEE T10.X, PV.W, T3.Z, PV.Z, ; 01006CFE 014308FE MULADD_IEEE T5.Y, T7.Z, T1.W, PV.Y, ; 01802807 20A304FE MUL_IEEE * T5.Z, T4.W, T12.W, BS:VEC_021/SCL_122 ; 81818C04 40A40110 MUL_IEEE * T13.W, T4.X, T5.W, ; 8180A004 61A00110 MUL_IEEE T11.X, T4.W, T11.W, ; 01816C04 01600110 MUL_IEEE * T10.Y, T4.W, T5.W, BS:VEC_021/SCL_122 ; 8180AC04 21440110 MUL_IEEE T10.Z, T4.X, T10.W, ; 01814004 41400110 MULADD_IEEE * T13.W, T9.X, T0.X, T13.W, BS:VEC_120/SCL_212 ; 80000009 61AB0C0D MUL_IEEE T12.X, T4.X, T11.W, ; 01816004 01800110 MUL_IEEE T11.Y, PV.W, T5.X, ; 0000ACFE 21600110 MULADD_IEEE * T10.Z, T8.X, T2.Y, PV.Z, BS:VEC_201 ; 80804008 415308FE MULADD_IEEE * T13.W, T9.W, T0.X, T10.Y, ; 80000C09 61A3040A MUL_IEEE T13.X, PV.W, T5.X, ; 0000ACFE 01A00110 MUL_IEEE T10.Y, T4.Y, T5.W, ; 0180A404 21400110 MULADD_IEEE T10.Z, T10.Z, T3.Y, T11.Y, ; 0080680A 4143040B MULADD_IEEE * T5.W, T6.X, T0.Z, T12.X, ; 81000006 60A3000C MULADD_IEEE T12.X, PV.W, T3.Z, PV.Z, ; 01006CFE 018308FE MUL_IEEE T11.Y, T4.Y, T10.W, ; 01814404 21600110 MULADD_IEEE T9.Z, T9.Y, T0.X, PV.Y, BS:VEC_120/SCL_212 ; 00000409 412B04FE MUL_IEEE * T5.W, T4.X, T12.W, BS:VEC_021/SCL_122 ; 81818004 60A40110 MULADD_IEEE T9.X, T7.X, T1.W, PV.W, ; 01802007 01230CFE MUL_IEEE T9.Y, T4.Y, T11.W, BS:VEC_021/SCL_122 ; 01816404 21240110 MUL_IEEE T9.Z, PV.Z, T5.X, ; 0000A8FE 41200110 MULADD_IEEE * T5.W, T8.Y, T2.Y, PV.Y, BS:VEC_120/SCL_212 ; 80804408 60AB04FE MUL_IEEE T5.X, T4.Y, T12.W, ; 01818404 00A00110 MULADD_IEEE T10.Y, PV.W, T3.Y, PV.Z, ; 00806CFE 214308FE MULADD_IEEE T9.Z, T6.Y, T0.Z, PV.Y, BS:VEC_201 ; 01000406 413304FE MUL_IEEE * T4.W, T4.W, T10.W, BS:VEC_021/SCL_122 ; 81814C04 60840110 MULADD_IEEE T2.X, T8.W, T2.Y, PV.W, ; 00804C08 00430CFE MULADD_IEEE T2.Y, PV.Z, T3.Z, PV.Y, ; 010068FE 204304FE MULADD_IEEE T2.Z, T7.Y, T1.W, PV.X, ; 01802407 404300FE MULADD_IEEE * T2.W, T9.X, T3.W, T12.X, BS:VEC_021/SCL_122 ; 81806009 6047000C RECIP_IEEE T3.X, T3.X, ; 00000003 00604310 RECIP_IEEE T3.Y (MASKED), T3.X, ; 00000003 20604300 RECIP_IEEE T3.Z (MASKED), T3.X, ; 00000003 40604300 RECIP_IEEE * T3.W (MASKED), T3.X, ; 80000003 60604300 MUL_IEEE T4.X, T2.W, PV.X, ; 001FCC02 00800110 MULADD_IEEE T2.Y, T2.Z, T3.W, T2.Y, ; 01806802 20430402 MULADD_IEEE T2.Z, T2.X, T3.Y, T13.X, BS:VEC_102/SCL_221 ; 00806002 404F000D MULADD_IEEE * T0.W, T6.W, T0.Z, T11.X, BS:VEC_210 ; 81000C06 6017000B MULADD_IEEE T0.X, PV.W, T3.Z, PV.Z, ; 01006CFE 000308FE MUL_IEEE T4.Y, PV.Y, T3.X, ; 000064FE 20800110 MULADD_IEEE T0.Z, T7.W, T1.W, T5.Z, ; 01802C07 40030805 MULADD_IEEE * T0.W, T5.Y, T3.W, T10.X, BS:VEC_120/SCL_212 ; 81806405 600B000A MUL_IEEE T4.Z, PV.W, T3.X, ; 00006CFE 40800110 MULADD_IEEE * T0.W, PV.Z, T3.W, PV.X, ; 818068FE 600300FE MUL_IEEE * T4.W, PV.W, T3.X, ; 80006CFE 60800110 ===== SHADER #101 ======================================= PS/CAYMAN/CAYMAN ===== ===== 258 dw ===== 14 gprs ===== 1 stack ======================================= 0000 0000001a a0540000 ALU 22 @52 0052 00380400 00946b10 1 x: INTERP_XY R4.x, R0.y, Param0.x VEC_210 0054 00380000 20946b10 y: INTERP_XY R4.y, R0.x, Param0.x VEC_210 0056 00380400 40146b00 z: INTERP_XY __.z, R0.y, Param0.x VEC_210 0058 80380000 60146b00 w: INTERP_XY __.w, R0.x, Param0.x VEC_210 0060 00382400 00d46b10 2 x: INTERP_XY R6.x, R0.y, Param1.x VEC_210 0062 00382000 20d46b10 y: INTERP_XY R6.y, R0.x, Param1.x VEC_210 0064 00382400 40146b00 z: INTERP_XY __.z, R0.y, Param1.x VEC_210 0066 80382000 60146b00 w: INTERP_XY __.w, R0.x, Param1.x VEC_210 0068 00382400 00146b80 3 x: INTERP_ZW __.x, R0.y, Param1.x VEC_210 0070 00382000 20146b80 y: INTERP_ZW __.y, R0.x, Param1.x VEC_210 0072 00382400 41146b90 z: INTERP_ZW R8.z, R0.y, Param1.x VEC_210 0074 80382000 60b46b90 w: INTERP_ZW R5.w, R0.x, Param1.x VEC_210 0076 00384400 00f46b10 4 x: INTERP_XY R7.x, R0.y, Param2.x VEC_210 0078 00384000 20f46b10 y: INTERP_XY R7.y, R0.x, Param2.x VEC_210 0080 00384400 40146b00 z: INTERP_XY __.z, R0.y, Param2.x VEC_210 0082 80384000 60146b00 w: INTERP_XY __.w, R0.x, Param2.x VEC_210 0084 00384400 00146b80 5 x: INTERP_ZW __.x, R0.y, Param2.x VEC_210 0086 00384000 20146b80 y: INTERP_ZW __.y, R0.x, Param2.x VEC_210 0088 00384400 40b46b90 z: INTERP_ZW R5.z, R0.y, Param2.x VEC_210 0090 80384000 61146b90 w: INTERP_ZW R8.w, R0.x, Param2.x VEC_210 0092 000008fe 00000c90 6 x: MOV R0.x, PV.z 0094 80000cfe 20000c90 y: MOV R0.y, PV.w 0002 0000000a 80400800 TEX 3 @20 0020 00001110 f00d1002 fc808000 SAMPLE R2.xyzw, R0.xy__, RID:17, SID:1 CT:NNNN 0024 00041110 f00d1000 fc808000 SAMPLE R0.xyzw, R4.xy__, RID:17, SID:1 CT:NNNN 0028 00071110 f00d1001 fc808000 SAMPLE R1.xyzw, R7.xy__, RID:17, SID:1 CT:NNNN 0004 00000030 a43c0000 ALU_PUSH_BEFORE 16 @96 0096 01802c01 00600110 7 x: MUL_IEEE R3.x, R1.w, R1.w 0098 01000800 20a00110 y: MUL_IEEE R5.y, R0.z, R0.z 0100 00804402 40600110 z: MUL_IEEE R3.z, R2.y, R2.y 0102 80000000 60600110 w: MUL_IEEE R3.w, R0.x, R0.x 0104 00000cfe 00a00110 8 x: MUL_IEEE R5.x, PV.w, R0.x 0106 008048fe 20600110 y: MUL_IEEE R3.y, PV.z, R2.y 0108 010004fe 40600110 z: MUL_IEEE R3.z, PV.y, R0.z 0110 818020fe 60600110 w: MUL_IEEE R3.w, PV.x, R1.w 0112 001f2005 00605f10 9 x: DOT4 R3.x, R5.x, 1.0 0114 001f2403 20605f00 y: DOT4 __.y, R3.y, 1.0 0116 001f2803 40605f00 z: DOT4 __.z, R3.z, 1.0 0118 801f2c03 60605f00 w: DOT4 __.w, R3.w, 1.0 0120 801fc0fd 61200490 10 w: SETGT R9.w, [0x3727c5ac 1e-05].x, PV.x 0122 3727c5ac 0124 801f0cfe 61200610 11 w: SETE_DX10 R9.w, PV.w, 0 0126 801f0cfe 00002104 12 M x: PRED_SETE_INT __.x, PV.w, 0 0006 00000005 82800001 JUMP @10 POP:1 0008 00000040 a8000000 ALU_POP_AFTER 1 @128 0128 801f00f9 20a01680 13 y: KILLGT __.y, 1.0, 0 0010 00000041 a00c0000 ALU 4 @130 0130 80000808 01200c90 14 x: MOV R9.x, R8.z 0132 00000805 01400c90 15 x: MOV R10.x, R5.z 0134 80000c05 21200c90 y: MOV R9.y, R5.w 0136 80000c08 21400c90 16 y: MOV R10.y, R8.w 0012 00000010 80401000 TEX 5 @32 0032 00071010 f00d1007 fc800000 SAMPLE R7.xyzw, R7.xy__, RID:16, SID:0 CT:NNNN 0036 00061010 f00d1006 fc800000 SAMPLE R6.xyzw, R6.xy__, RID:16, SID:0 CT:NNNN 0040 000a1010 f00d1008 fc800000 SAMPLE R8.xyzw, R10.xy__, RID:16, SID:0 CT:NNNN 0044 00091010 f00d1009 fc800000 SAMPLE R9.xyzw, R9.xy__, RID:16, SID:0 CT:NNNN 0048 00041010 f00d1004 fc800000 SAMPLE R4.xyzw, R4.xy__, RID:16, SID:0 CT:NNNN 0014 00000045 a0ec0000 ALU 60 @138 0138 801f3000 60a00010 17 w: ADD R5.w, -R0.x, 1.0 0140 019fc804 40a00110 18 z: MUL_IEEE R5.z, R4.z, PV.w 0142 801f3402 61400010 w: ADD R10.w, -R2.y, 1.0 0144 019fc804 20a00110 19 y: MUL_IEEE R5.y, R4.z, PV.w 0146 00000809 40ab08fe z: MULADD_IEEE R5.z, R9.z, R0.x, PV.z VEC_120 0148 801f3800 61700010 w: ADD R11.w, -R0.z, 1.0 VEC_201 0150 019fc804 01400110 20 x: MUL_IEEE R10.x, R4.z, PV.w 0152 0000a8fe 21400110 y: MUL_IEEE R10.y, PV.z, R5.x 0154 00804808 40ab04fe z: MULADD_IEEE R5.z, R8.z, R2.y, PV.y VEC_120 0156 801f3c01 61800010 w: ADD R12.w, -R1.w, 1.0 0158 019fc804 20a00110 21 y: MUL_IEEE R5.y, R4.z, PV.w 0160 008068fe 40a304fe z: MULADD_IEEE R5.z, PV.z, R3.y, PV.y 0162 81000806 61ab00fe w: MULADD_IEEE R13.w, R6.z, R0.z, PV.x VEC_120 0164 01006cfe 014308fe 22 x: MULADD_IEEE R10.x, PV.w, R3.z, PV.z 0166 01802807 20a304fe y: MULADD_IEEE R5.y, R7.z, R1.w, PV.y 0168 81818c04 40a40110 z: MUL_IEEE R5.z, R4.w, R12.w VEC_021 0170 8180a004 61a00110 23 w: MUL_IEEE R13.w, R4.x, R5.w 0172 01816c04 01600110 24 x: MUL_IEEE R11.x, R4.w, R11.w 0174 8180ac04 21440110 y: MUL_IEEE R10.y, R4.w, R5.w VEC_021 0176 01814004 41400110 25 z: MUL_IEEE R10.z, R4.x, R10.w 0178 80000009 61ab0c0d w: MULADD_IEEE R13.w, R9.x, R0.x, R13.w VEC_120 0180 01816004 01800110 26 x: MUL_IEEE R12.x, R4.x, R11.w 0182 0000acfe 21600110 y: MUL_IEEE R11.y, PV.w, R5.x 0184 80804008 415308fe z: MULADD_IEEE R10.z, R8.x, R2.y, PV.z VEC_201 0186 80000c09 61a3040a 27 w: MULADD_IEEE R13.w, R9.w, R0.x, R10.y 0188 0000acfe 01a00110 28 x: MUL_IEEE R13.x, PV.w, R5.x 0190 0180a404 21400110 y: MUL_IEEE R10.y, R4.y, R5.w 0192 0080680a 4143040b z: MULADD_IEEE R10.z, R10.z, R3.y, R11.y 0194 81000006 60a3000c w: MULADD_IEEE R5.w, R6.x, R0.z, R12.x 0196 01006cfe 018308fe 29 x: MULADD_IEEE R12.x, PV.w, R3.z, PV.z 0198 01814404 21600110 y: MUL_IEEE R11.y, R4.y, R10.w 0200 00000409 412b04fe z: MULADD_IEEE R9.z, R9.y, R0.x, PV.y VEC_120 0202 81818004 60a40110 w: MUL_IEEE R5.w, R4.x, R12.w VEC_021 0204 01802007 01230cfe 30 x: MULADD_IEEE R9.x, R7.x, R1.w, PV.w 0206 01816404 21240110 y: MUL_IEEE R9.y, R4.y, R11.w VEC_021 0208 0000a8fe 41200110 z: MUL_IEEE R9.z, PV.z, R5.x 0210 80804408 60ab04fe w: MULADD_IEEE R5.w, R8.y, R2.y, PV.y VEC_120 0212 01818404 00a00110 31 x: MUL_IEEE R5.x, R4.y, R12.w 0214 00806cfe 214308fe y: MULADD_IEEE R10.y, PV.w, R3.y, PV.z 0216 01000406 413304fe z: MULADD_IEEE R9.z, R6.y, R0.z, PV.y VEC_201 0218 81814c04 60840110 w: MUL_IEEE R4.w, R4.w, R10.w VEC_021 0220 00804c08 00430cfe 32 x: MULADD_IEEE R2.x, R8.w, R2.y, PV.w 0222 010068fe 204304fe y: MULADD_IEEE R2.y, PV.z, R3.z, PV.y 0224 01802407 404300fe z: MULADD_IEEE R2.z, R7.y, R1.w, PV.x 0226 81806009 6047000c w: MULADD_IEEE R2.w, R9.x, R3.w, R12.x VEC_021 0228 00000003 00604310 33 x: RECIP_IEEE R3.x, R3.x 0230 00000003 20604300 y: RECIP_IEEE __.y, R3.x 0232 00000003 40604300 z: RECIP_IEEE __.z, R3.x 0234 80000003 60604300 w: RECIP_IEEE __.w, R3.x 0236 001fcc02 00800110 34 x: MUL_IEEE R4.x, R2.w, PV.x 0238 01806802 20430402 y: MULADD_IEEE R2.y, R2.z, R3.w, R2.y 0240 00806002 404f000d z: MULADD_IEEE R2.z, R2.x, R3.y, R13.x VEC_102 0242 81000c06 6017000b w: MULADD_IEEE R0.w, R6.w, R0.z, R11.x VEC_210 0244 01006cfe 000308fe 35 x: MULADD_IEEE R0.x, PV.w, R3.z, PV.z 0246 000064fe 20800110 y: MUL_IEEE R4.y, PV.y, R3.x 0248 01802c07 40030805 z: MULADD_IEEE R0.z, R7.w, R1.w, R5.z 0250 81806405 600b000a w: MULADD_IEEE R0.w, R5.y, R3.w, R10.x VEC_120 0252 00006cfe 40800110 36 z: MUL_IEEE R4.z, PV.w, R3.x 0254 818068fe 600300fe w: MULADD_IEEE R0.w, PV.z, R3.w, PV.x 0256 80006cfe 60800110 37 w: MUL_IEEE R4.w, PV.w, R3.x 0016 c0020000 95200688 EXPORT_DONE PIXEL 0 R4.xyzw 0018 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #101 OPT =================================== PS/CAYMAN/CAYMAN ===== ===== 236 dw ===== 8 gprs ===== 0 stack ======================================== 0000 00000007 a02c0000 ALU 12 @14 0014 00384400 00146b80 1 x: INTERP_ZW __.x, R0.y, Param2.x VEC_210 0016 00b84000 20146b80 y: INTERP_ZW __.y, R0.x, Param2.y VEC_210 0018 01384400 40546b90 z: INTERP_ZW R2.z, R0.y, Param2.z VEC_210 0020 81b84000 60546b90 w: INTERP_ZW R2.w, R0.x, Param2.w VEC_210 0022 00380400 00346b10 2 x: INTERP_XY R1.x, R0.y, Param0.x VEC_210 0024 00b80000 20346b10 y: INTERP_XY R1.y, R0.x, Param0.y VEC_210 0026 01380400 40146b00 z: INTERP_XY __.z, R0.y, Param0.z VEC_210 0028 81b80000 60146b00 w: INTERP_XY __.w, R0.x, Param0.w VEC_210 0030 00384400 00946b10 3 x: INTERP_XY R4.x, R0.y, Param2.x VEC_210 0032 00b84000 20946b10 y: INTERP_XY R4.y, R0.x, Param2.y VEC_210 0034 01384400 40146b00 z: INTERP_XY __.z, R0.y, Param2.z VEC_210 0036 81b84000 60146b00 w: INTERP_XY __.w, R0.x, Param2.w VEC_210 0002 00000014 80400800 TEX 3 @40 0040 00041110 f01dfe05 fc808000 SAMPLE R5.__w_, R4.xy__, RID:17, SID:1 CT:NNNN 0044 00011110 f01fa005 fc808000 SAMPLE R5.xz__, R1.xy__, RID:17, SID:1 CT:NNNN 0048 00021110 f007fe05 fda08000 SAMPLE R5.___y, R2.zw__, RID:17, SID:1 CT:NNNN 0004 0000001a a0540000 ALU 22 @52 0052 0180ac05 0f800110 4 x: MUL_IEEE T0.x, R5.w, R5.w 0054 0000a005 2f800110 y: MUL_IEEE T0.y, R5.x, R5.x 0056 0100a805 4f800110 z: MUL_IEEE T0.z, R5.z, R5.z 0058 8080a405 6f800110 w: MUL_IEEE T0.w, R5.y, R5.y 0060 0000a47c 00c00110 5 x: MUL_IEEE R6.x, T0.y, R5.x 0062 0180a07c 20c00110 y: MUL_IEEE R6.y, T0.x, R5.w 0064 0080ac7c 40e00110 z: MUL_IEEE R7.z, T0.w, R5.y 0066 8100a87c 60c00110 w: MUL_IEEE R6.w, T0.z, R5.z 0068 001f2006 00005f00 6 x: DOT4 __.x, R6.x, 1.0 0070 001f2406 20005f00 y: DOT4 __.y, R6.y, 1.0 0072 001f2807 40c05f10 z: DOT4 R6.z, R7.z, 1.0 0074 801f2c06 60005f00 w: DOT4 __.w, R6.w, 1.0 0076 00382400 00746b10 7 x: INTERP_XY R3.x, R0.y, Param1.x VEC_210 0078 00b82000 20746b10 y: INTERP_XY R3.y, R0.x, Param1.y VEC_210 0080 01382400 40146b00 z: INTERP_XY __.z, R0.y, Param1.z VEC_210 0082 81b82000 60146b00 w: INTERP_XY __.w, R0.x, Param1.w VEC_210 0084 00382400 00146b80 8 x: INTERP_ZW __.x, R0.y, Param1.x VEC_210 0086 00b82000 20146b80 y: INTERP_ZW __.y, R0.x, Param1.y VEC_210 0088 01382400 40346b90 z: INTERP_ZW R1.z, R0.y, Param1.z VEC_210 0090 81b82000 60346b90 w: INTERP_ZW R1.w, R0.x, Param1.w VEC_210 0092 8100c0fd 00001680 9 x: KILLGT __.x, [0x3727c5ac 1e-05].x, R6.z 0094 3727c5ac 0006 00000030 80401000 TEX 5 @96 0096 00011010 f00d1000 fc800000 SAMPLE R0.xyzw, R1.xy__, RID:16, SID:0 CT:NNNN 0100 00011010 f00d1001 fda00000 SAMPLE R1.xyzw, R1.zw__, RID:16, SID:0 CT:NNNN 0104 00021010 f00d1002 fda00000 SAMPLE R2.xyzw, R2.zw__, RID:16, SID:0 CT:NNNN 0108 00031010 f00d1003 fc800000 SAMPLE R3.xyzw, R3.xy__, RID:16, SID:0 CT:NNNN 0112 00041010 f00d1004 fc800000 SAMPLE R4.xyzw, R4.xy__, RID:16, SID:0 CT:NNNN 0008 0000003a a0ec0000 ALU 60 @116 0116 801f3005 6f800010 10 w: ADD T0.w, -R5.x, 1.0 0118 818f8000 0f800110 11 x: MUL_IEEE T0.x, R0.x, T0.w 0120 001f3c05 0f800010 12 x: ADD T0.x, -R5.w, 1.0 0122 0000a001 2fa3007c y: MULADD_IEEE T1.y, R1.x, R5.x, T0.x 0124 818f8800 4fa00110 z: MUL_IEEE T1.z, R0.z, T0.w 0126 018f8c00 2f800110 13 y: MUL_IEEE T0.y, R0.w, T0.w 0128 000f8c00 4f800110 z: MUL_IEEE T0.z, R0.w, T0.x 0130 818f8400 6f800110 w: MUL_IEEE T0.w, R0.y, T0.w 0132 000f8000 0fa00110 14 x: MUL_IEEE T1.x, R0.x, T0.x 0134 001f3405 2ff00010 y: ADD T3.y, -R5.y, 1.0 VEC_201 0136 000f8400 4fc00110 z: MUL_IEEE T2.z, R0.y, T0.x 0138 8000ac01 6fc7047c w: MULADD_IEEE T2.w, R1.w, R5.x, T0.y VEC_021 0140 000f8800 0f900110 15 x: MUL_IEEE T0.x, R0.z, T0.x VEC_201 0142 0000a801 2f87087d y: MULADD_IEEE T0.y, R1.z, R5.x, T1.z VEC_021 0144 0000c47d 4fa00110 z: MUL_IEEE T1.z, T1.y, R6.x 0146 8000a401 6f8b0c7c w: MULADD_IEEE T0.w, R1.y, R5.x, T0.w VEC_120 0148 0180ac02 0fc3087c 16 x: MULADD_IEEE T2.x, R2.w, R5.w, T0.z 0150 0180a002 2fc7007d y: MULADD_IEEE T2.y, R2.x, R5.w, T1.x VEC_021 0152 001f3805 4fe80010 z: ADD T3.z, -R5.z, 1.0 VEC_120 0154 8180a802 6fa3007c w: MULADD_IEEE T1.w, R2.z, R5.w, T0.x 0156 0000c47c 0fa00110 17 x: MUL_IEEE T1.x, T0.y, R6.x 0158 0000cc7e 2fa80110 y: MUL_IEEE T1.y, T2.w, R6.x VEC_120 0160 008fe800 4f800110 z: MUL_IEEE T0.z, R0.z, T3.y 0162 808fec00 6fc00110 w: MUL_IEEE T2.w, R0.w, T3.y 0164 008fe000 0f800110 18 x: MUL_IEEE T0.x, R0.x, T3.y 0166 008fe400 2f940110 y: MUL_IEEE T0.y, R0.y, T3.y VEC_210 0168 0180a402 4fc3087e z: MULADD_IEEE T2.z, R2.y, R5.w, T2.z 0170 8000cc7c 6f800110 w: MUL_IEEE T0.w, T0.w, R6.x 0172 0080cc7d 0fe3007d 19 x: MULADD_IEEE T3.x, T1.w, R6.y, T1.x 0174 0080c07e 2fc3047d y: MULADD_IEEE T2.y, T2.x, R6.y, T1.y 0176 0080c47e 4fa3087d z: MULADD_IEEE T1.z, T2.y, R6.y, T1.z 0178 810fec00 6fac0110 w: MUL_IEEE T1.w, R0.w, T3.z VEC_102 0180 0080ac03 0fa30c7e 20 x: MULADD_IEEE T1.x, R3.w, R5.y, T2.w 0182 0080a003 2fa3007c y: MULADD_IEEE T1.y, R3.x, R5.y, T0.x 0184 0080a403 4f83047c z: MULADD_IEEE T0.z, R3.y, R5.y, T0.y 0186 8080a803 6fc3087c w: MULADD_IEEE T2.w, R3.z, R5.y, T0.z 0188 010fe000 0f800110 21 x: MUL_IEEE T0.x, R0.x, T3.z 0190 010fe400 2f940110 y: MUL_IEEE T0.y, R0.y, T3.z VEC_210 0192 010fe800 4fc00110 z: MUL_IEEE T2.z, R0.z, T3.z 0194 8080c87e 6f930c7c w: MULADD_IEEE T0.w, T2.z, R6.y, T0.w VEC_201 0196 0100e07d 0fc3047e 22 x: MULADD_IEEE T2.x, T1.x, R7.z, T2.y 0198 0100e47d 4fa3087d z: MULADD_IEEE T1.z, T1.y, R7.z, T1.z 0200 8100ac04 6faf0c7d w: MULADD_IEEE T1.w, R4.w, R5.z, T1.w VEC_102 0202 0100e87c 0fa30c7c 23 x: MULADD_IEEE T1.x, T0.z, R7.z, T0.w 0204 0100a004 2fa7007c y: MULADD_IEEE T1.y, R4.x, R5.z, T0.x VEC_021 0206 0100ec7e 4f83007f z: MULADD_IEEE T0.z, T2.w, R7.z, T3.x 0208 8100a404 6f87047c w: MULADD_IEEE T0.w, R4.y, R5.z, T0.y VEC_021 0210 00000806 0f804310 24 x: RECIP_IEEE T0.x, R6.z 0212 00000806 20004300 y: RECIP_IEEE __.y, R6.z 0214 00000806 40004300 z: RECIP_IEEE __.z, R6.z 0216 80000806 60004300 w: RECIP_IEEE __.w, R6.z 0218 0100a804 2f83087e 25 y: MULADD_IEEE T0.y, R4.z, R5.z, T2.z 0220 8180cc7d 6fa3007e w: MULADD_IEEE T1.w, T1.w, R6.w, T2.x 0222 0180c47c 2f8b087c 26 y: MULADD_IEEE T0.y, T0.y, R6.w, T0.z VEC_120 0224 0180cc7c 4f83007d z: MULADD_IEEE T0.z, T0.w, R6.w, T1.x 0226 8180c47d 6f83087d w: MULADD_IEEE T0.w, T1.y, R6.w, T1.z 0228 000f8c7c 00000110 27 x: MUL_IEEE R0.x, T0.w, T0.x 0230 000f887c 20000110 y: MUL_IEEE R0.y, T0.z, T0.x 0232 000f847c 40000110 z: MUL_IEEE R0.z, T0.y, T0.x 0234 800f8c7d 60080110 w: MUL_IEEE R0.w, T1.w, T0.x VEC_120 0010 c0000000 95000688 EXPORT_DONE PIXEL 0 R0.xyzw 0012 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== OnFocusWindowChanged to window type: k_EWindowTypeSteamDesktop, 0 Running Steam on arch rolling 64-bit STEAM_RUNTIME is disabled by the user Generating new string page texture 82: 64x256, total string texture memory is 376.83 KB Generating new string page texture 83: 128x256, total string texture memory is 507.90 KB Generating new string page texture 84: 128x256, total string texture memory is 638.98 KB Generating new string page texture 85: 32x256, total string texture memory is 671.74 KB Generating new string page texture 90: 1024x256, total string texture memory is 1.72 MB Generating new string page texture 91: 128x256, total string texture memory is 131.07 KB Generating new string page texture 92: 256x256, total string texture memory is 1.98 MB ExecCommandLine: "/home/dema1701/.steam/root/ubuntu12_32/steam steam://open/driverhelperready" ExecSteamURL: "steam://open/driverhelperready" Generating new string page texture 96: 128x256, total string texture memory is 2.11 MB Generating new string page texture 97: 128x256, total string texture memory is 2.24 MB Generating new string page texture 98: 48x256, total string texture memory is 2.29 MB Generating new string page texture 99: 384x256, total string texture memory is 2.69 MB Generating new string page texture 100: 512x256, total string texture memory is 3.21 MB Generating new string page texture 121: 256x256, total string texture memory is 3.47 MB Game update: AppID 204300 "Awesomenauts", ProcID 15209, IP 0.0.0.0:0 ERROR: ld.so: object '/home/dema1701/.local/share/Steam/ubuntu12_32/gameoverlayrenderer.so' from LD_PRELOAD cannot be preloaded: ignored. CGameStreamThread: Added instance ID 15209 for appid 204300 CGameStreamThread: Set render instance ID 15209 for appid 204300 ERROR: ld.so: object '/home/dema1701/.local/share/Steam/ubuntu12_32/gameoverlayrenderer.so' from LD_PRELOAD cannot be preloaded: ignored. ERROR: ld.so: object '/home/dema1701/.local/share/Steam/ubuntu12_64/gameoverlayrenderer.so' from LD_PRELOAD cannot be preloaded: ignored. CGameStreamThread: Added instance ID 15210 for appid 204300 CGameStreamThread: Added instance ID 15211 for appid 204300 -------------------------------------------------------------- SystemManager constructor starts SystemManager constructor ends SDLWindowAndEventManager constructor starts Game version: Version 2.1.1a SDLWindowAndEventManager constructor ends SDLWindowAndEventManager::run() starts SDLWindowAndEventManager::createWindow() starts Loading binary file: "Data/Config.txt" xRes: 1280 yRes: 1024 graphicsQuality: HIGH fullScreen: 1 renderApi: OPENGL vSyncEnabled: 1 multiThreadingEnabled: 1 SDL_SetVideoMode starts FRAG 0: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg) #0 { main_body: call void @llvm.R600.store.dummy(i32 0) ret void } declare void @llvm.R600.store.dummy(i32) attributes #0 = { "ShaderType"="0" } Shader Disassembly: EXPORT T0.____ ; C0000000 95200FFF CF_END ; 00000000 88000000 ===== SHADER #6 ========================================= PS/CAYMAN/CAYMAN ===== ===== 4 dw ===== 1 gprs ===== 1 stack ========================================== 0000 c0000000 95200fff EXPORT_DONE PIXEL 0 R0.____ 0002 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #6 OPT ===================================== PS/CAYMAN/CAYMAN ===== ===== 4 dw ===== 0 gprs ===== 0 stack ========================================== 0000 c0000000 95000fff EXPORT_DONE PIXEL 0 R0.____ 0002 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- FRAG DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg) #0 { main_body: %2 = call <4 x float> @llvm.R600.interp.const(i32 0) %3 = extractelement <4 x float> %2, i32 0 %4 = extractelement <4 x float> %2, i32 1 %5 = extractelement <4 x float> %2, i32 2 %6 = extractelement <4 x float> %2, i32 3 %7 = insertelement <4 x float> undef, float %3, i32 0 %8 = insertelement <4 x float> %7, float %4, i32 1 %9 = insertelement <4 x float> %8, float %5, i32 2 %10 = insertelement <4 x float> %9, float %6, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %10, i32 0, i32 0) ret void } ; Function Attrs: readnone declare <4 x float> @llvm.R600.interp.const(i32) #1 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } Shader Disassembly: ALU 3, @4, KC0[], KC1[] ; 00000004 A00C0000 EXPORT T0.XYZW ; C0000000 95200688 CF_END ; 00000000 88000000 PAD ; 00000000 00000000 ALU clause starting at 4: ; INTERP_LOAD_P0 T0.X, ARRAY_BASE, ; 000001C0 00007010 INTERP_LOAD_P0 T0.Y, ARRAY_BASE, ; 000001C0 20007010 INTERP_LOAD_P0 T0.Z, ARRAY_BASE, ; 000001C0 40007010 INTERP_LOAD_P0 * T0.W, ARRAY_BASE, ; 800001C0 60007010 ===== SHADER #7 ========================================= PS/CAYMAN/CAYMAN ===== ===== 16 dw ===== 1 gprs ===== 1 stack ========================================= 0000 00000004 a00c0000 ALU 4 @8 0008 000001c0 00007010 1 x: INTERP_LOAD_P0 R0.x, Param0.x 0010 000001c0 20007010 y: INTERP_LOAD_P0 R0.y, Param0.x 0012 000001c0 40007010 z: INTERP_LOAD_P0 R0.z, Param0.x 0014 800001c0 60007010 w: INTERP_LOAD_P0 R0.w, Param0.x 0002 c0000000 95200688 EXPORT_DONE PIXEL 0 R0.xyzw 0004 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #7 OPT ===================================== PS/CAYMAN/CAYMAN ===== ===== 14 dw ===== 1 gprs ===== 0 stack ========================================= 0000 00000003 a00c0000 ALU 4 @6 0006 000001c0 00007010 1 x: INTERP_LOAD_P0 R0.x, Param0.x 0008 000005c0 20007010 y: INTERP_LOAD_P0 R0.y, Param0.y 0010 000009c0 40007010 z: INTERP_LOAD_P0 R0.z, Param0.z 0012 80000dc0 60007010 w: INTERP_LOAD_P0 R0.w, Param0.w 0002 c0000000 95000688 EXPORT_DONE PIXEL 0 R0.xyzw 0004 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg) #0 { main_body: %2 = call <4 x float> @llvm.R600.interp.const(i32 0) %3 = extractelement <4 x float> %2, i32 0 %4 = extractelement <4 x float> %2, i32 1 %5 = extractelement <4 x float> %2, i32 2 %6 = extractelement <4 x float> %2, i32 3 %7 = insertelement <4 x float> undef, float %3, i32 0 %8 = insertelement <4 x float> %7, float %4, i32 1 %9 = insertelement <4 x float> %8, float %5, i32 2 %10 = insertelement <4 x float> %9, float %6, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %10, i32 0, i32 0) ret void } ; Function Attrs: readnone declare <4 x float> @llvm.R600.interp.const(i32) #1 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } Shader Disassembly: ALU 3, @4, KC0[], KC1[] ; 00000004 A00C0000 EXPORT T0.XYZW ; C0000000 95200688 CF_END ; 00000000 88000000 PAD ; 00000000 00000000 ALU clause starting at 4: ; INTERP_LOAD_P0 T0.X, ARRAY_BASE, ; 000001C0 00007010 INTERP_LOAD_P0 T0.Y, ARRAY_BASE, ; 000001C0 20007010 INTERP_LOAD_P0 T0.Z, ARRAY_BASE, ; 000001C0 40007010 INTERP_LOAD_P0 * T0.W, ARRAY_BASE, ; 800001C0 60007010 ===== SHADER #8 ========================================= PS/CAYMAN/CAYMAN ===== ===== 16 dw ===== 1 gprs ===== 1 stack ========================================= 0000 00000004 a00c0000 ALU 4 @8 0008 000001c0 00007010 1 x: INTERP_LOAD_P0 R0.x, Param0.x 0010 000001c0 20007010 y: INTERP_LOAD_P0 R0.y, Param0.x 0012 000001c0 40007010 z: INTERP_LOAD_P0 R0.z, Param0.x 0014 800001c0 60007010 w: INTERP_LOAD_P0 R0.w, Param0.x 0002 c0000000 95200688 EXPORT_DONE PIXEL 0 R0.xyzw 0004 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #8 OPT ===================================== PS/CAYMAN/CAYMAN ===== ===== 14 dw ===== 1 gprs ===== 0 stack ========================================= 0000 00000003 a00c0000 ALU 4 @6 0006 000001c0 00007010 1 x: INTERP_LOAD_P0 R0.x, Param0.x 0008 000005c0 20007010 y: INTERP_LOAD_P0 R0.y, Param0.y 0010 000009c0 40007010 z: INTERP_LOAD_P0 R0.z, Param0.z 0012 80000dc0 60007010 w: INTERP_LOAD_P0 R0.w, Param0.w 0002 c0000000 95000688 EXPORT_DONE PIXEL 0 R0.xyzw 0004 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] 0: MOV OUT[0], IN[0] 1: MOV OUT[1], IN[1] 2: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg, <4 x float> inreg) #0 { main_body: %3 = extractelement <4 x float> %1, i32 0 %4 = extractelement <4 x float> %1, i32 1 %5 = extractelement <4 x float> %1, i32 2 %6 = extractelement <4 x float> %1, i32 3 %7 = extractelement <4 x float> %2, i32 0 %8 = extractelement <4 x float> %2, i32 1 %9 = extractelement <4 x float> %2, i32 2 %10 = extractelement <4 x float> %2, i32 3 %11 = insertelement <4 x float> undef, float %3, i32 0 %12 = insertelement <4 x float> %11, float %4, i32 1 %13 = insertelement <4 x float> %12, float %5, i32 2 %14 = insertelement <4 x float> %13, float %6, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %14, i32 60, i32 1) %15 = insertelement <4 x float> undef, float %7, i32 0 %16 = insertelement <4 x float> %15, float %8, i32 1 %17 = insertelement <4 x float> %16, float %9, i32 2 %18 = insertelement <4 x float> %17, float %10, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %18, i32 0, i32 2) ret void } declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="1" } Shader Disassembly: CALL_FS ; 00000000 84C00000 EXPORT T1.XYZW ; C000A03C 95000688 EXPORT T2.XYZW ; C0014000 95200688 CF_END ; 00000000 88000000 ===== SHADER #9 ========================================= VS/CAYMAN/CAYMAN ===== ===== 8 dw ===== 3 gprs ===== 1 stack ========================================== 0000 00000000 84c00000 CALL_FS @0 0002 c000a03c 95000688 EXPORT_DONE POS 60 R1.xyzw 0004 c0014000 95200688 EXPORT_DONE PARAM 0 R2.xyzw 0006 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #9 OPT ===================================== VS/CAYMAN/CAYMAN ===== ===== 8 dw ===== 3 gprs ===== 1 stack ========================================== 0000 00000000 84c00000 CALL_FS @0 0002 c0014000 95000688 EXPORT_DONE PARAM 0 R2.xyzw 0004 c000a03c 95000688 EXPORT_DONE POS 60 R1.xyzw 0006 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- VERT DCL IN[0] DCL OUT[0], POSITION 0: MOV OUT[0], IN[0] 1: END STREAMOUT 0: MEM_STREAM0_BUF0[0..0] <- OUT[0].x ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg) #0 { main_body: %2 = extractelement <4 x float> %1, i32 0 %3 = extractelement <4 x float> %1, i32 1 %4 = extractelement <4 x float> %1, i32 2 %5 = extractelement <4 x float> %1, i32 3 %6 = insertelement <4 x float> undef, float %2, i32 0 %7 = insertelement <4 x float> %6, float %3, i32 1 %8 = insertelement <4 x float> %7, float %4, i32 2 %9 = insertelement <4 x float> %8, float %5, i32 3 call void @llvm.R600.store.stream.output(<4 x float> %9, i32 0, i32 0, i32 1) %10 = insertelement <4 x float> undef, float %2, i32 0 %11 = insertelement <4 x float> %10, float %3, i32 1 %12 = insertelement <4 x float> %11, float %4, i32 2 %13 = insertelement <4 x float> %12, float %5, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %13, i32 60, i32 1) call void @llvm.R600.store.dummy(i32 2) ret void } declare void @llvm.R600.store.stream.output(<4 x float>, i32, i32, i32) declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) declare void @llvm.R600.store.dummy(i32) attributes #0 = { "ShaderType"="1" } Shader Disassembly: CALL_FS ; 00000000 84C00000 EXPORT T1 ; 00008000 90001FFF EXPORT T1.XYZW ; C000A03C 95000688 EXPORT T0.____ ; C0004000 95200FFF CF_END ; 00000000 88000000 PAD ; 00000000 00000000 ===== SHADER #10 ======================================== VS/CAYMAN/CAYMAN ===== ===== 12 dw ===== 2 gprs ===== 1 stack ========================================= 0000 00000000 84c00000 CALL_FS @0 0002 00008000 90001fff MEM_STREAM0_BUF0 WRITE 0 R1.x___ ES:0 0004 c000a03c 95000688 EXPORT_DONE POS 60 R1.xyzw 0006 c0004000 95200fff EXPORT_DONE PARAM 0 R0.____ 0008 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #10 OPT ==================================== VS/CAYMAN/CAYMAN ===== ===== 10 dw ===== 2 gprs ===== 1 stack ========================================= 0000 00000000 84c00000 CALL_FS @0 0002 c000a03c 95000688 EXPORT_DONE POS 60 R1.xyzw 0004 00008000 90001fff MEM_STREAM0_BUF0 WRITE 0 R1.x___ ES:0 0006 c0004000 95000fff EXPORT_DONE PARAM 0 R0.____ 0008 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- FRAG DCL IN[0], GENERIC[0], CONSTANT 0: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg) #0 { main_body: %2 = call <4 x float> @llvm.R600.interp.const(i32 0) call void @llvm.R600.store.dummy(i32 0) ret void } ; Function Attrs: readnone declare <4 x float> @llvm.R600.interp.const(i32) #1 declare void @llvm.R600.store.dummy(i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } Shader Disassembly: EXPORT T0.____ ; C0000000 95200FFF CF_END ; 00000000 88000000 ===== SHADER #11 ======================================== PS/CAYMAN/CAYMAN ===== ===== 4 dw ===== 1 gprs ===== 1 stack ========================================== 0000 c0000000 95200fff EXPORT_DONE PIXEL 0 R0.____ 0002 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #11 OPT ==================================== PS/CAYMAN/CAYMAN ===== ===== 4 dw ===== 0 gprs ===== 0 stack ========================================== 0000 c0000000 95000fff EXPORT_DONE PIXEL 0 R0.____ 0002 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- FRAG 0: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg) #0 { main_body: call void @llvm.R600.store.dummy(i32 0) ret void } declare void @llvm.R600.store.dummy(i32) attributes #0 = { "ShaderType"="0" } Shader Disassembly: EXPORT T0.____ ; C0000000 95200FFF CF_END ; 00000000 88000000 ===== SHADER #17 ======================================== PS/CAYMAN/CAYMAN ===== ===== 4 dw ===== 1 gprs ===== 1 stack ========================================== 0000 c0000000 95200fff EXPORT_DONE PIXEL 0 R0.____ 0002 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #17 OPT ==================================== PS/CAYMAN/CAYMAN ===== ===== 4 dw ===== 0 gprs ===== 0 stack ========================================== 0000 c0000000 95000fff EXPORT_DONE PIXEL 0 R0.____ 0002 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- FRAG DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg) #0 { main_body: %2 = call <4 x float> @llvm.R600.interp.const(i32 0) %3 = extractelement <4 x float> %2, i32 0 %4 = extractelement <4 x float> %2, i32 1 %5 = extractelement <4 x float> %2, i32 2 %6 = extractelement <4 x float> %2, i32 3 %7 = insertelement <4 x float> undef, float %3, i32 0 %8 = insertelement <4 x float> %7, float %4, i32 1 %9 = insertelement <4 x float> %8, float %5, i32 2 %10 = insertelement <4 x float> %9, float %6, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %10, i32 0, i32 0) ret void } ; Function Attrs: readnone declare <4 x float> @llvm.R600.interp.const(i32) #1 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } Shader Disassembly: ALU 3, @4, KC0[], KC1[] ; 00000004 A00C0000 EXPORT T0.XYZW ; C0000000 95200688 CF_END ; 00000000 88000000 PAD ; 00000000 00000000 ALU clause starting at 4: ; INTERP_LOAD_P0 T0.X, ARRAY_BASE, ; 000001C0 00007010 INTERP_LOAD_P0 T0.Y, ARRAY_BASE, ; 000001C0 20007010 INTERP_LOAD_P0 T0.Z, ARRAY_BASE, ; 000001C0 40007010 INTERP_LOAD_P0 * T0.W, ARRAY_BASE, ; 800001C0 60007010 ===== SHADER #18 ======================================== PS/CAYMAN/CAYMAN ===== ===== 16 dw ===== 1 gprs ===== 1 stack ========================================= 0000 00000004 a00c0000 ALU 4 @8 0008 000001c0 00007010 1 x: INTERP_LOAD_P0 R0.x, Param0.x 0010 000001c0 20007010 y: INTERP_LOAD_P0 R0.y, Param0.x 0012 000001c0 40007010 z: INTERP_LOAD_P0 R0.z, Param0.x 0014 800001c0 60007010 w: INTERP_LOAD_P0 R0.w, Param0.x 0002 c0000000 95200688 EXPORT_DONE PIXEL 0 R0.xyzw 0004 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #18 OPT ==================================== PS/CAYMAN/CAYMAN ===== ===== 14 dw ===== 1 gprs ===== 0 stack ========================================= 0000 00000003 a00c0000 ALU 4 @6 0006 000001c0 00007010 1 x: INTERP_LOAD_P0 R0.x, Param0.x 0008 000005c0 20007010 y: INTERP_LOAD_P0 R0.y, Param0.y 0010 000009c0 40007010 z: INTERP_LOAD_P0 R0.z, Param0.z 0012 80000dc0 60007010 w: INTERP_LOAD_P0 R0.w, Param0.w 0002 c0000000 95000688 EXPORT_DONE PIXEL 0 R0.xyzw 0004 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg) #0 { main_body: %2 = call <4 x float> @llvm.R600.interp.const(i32 0) %3 = extractelement <4 x float> %2, i32 0 %4 = extractelement <4 x float> %2, i32 1 %5 = extractelement <4 x float> %2, i32 2 %6 = extractelement <4 x float> %2, i32 3 %7 = insertelement <4 x float> undef, float %3, i32 0 %8 = insertelement <4 x float> %7, float %4, i32 1 %9 = insertelement <4 x float> %8, float %5, i32 2 %10 = insertelement <4 x float> %9, float %6, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %10, i32 0, i32 0) ret void } ; Function Attrs: readnone declare <4 x float> @llvm.R600.interp.const(i32) #1 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } Shader Disassembly: ALU 3, @4, KC0[], KC1[] ; 00000004 A00C0000 EXPORT T0.XYZW ; C0000000 95200688 CF_END ; 00000000 88000000 PAD ; 00000000 00000000 ALU clause starting at 4: ; INTERP_LOAD_P0 T0.X, ARRAY_BASE, ; 000001C0 00007010 INTERP_LOAD_P0 T0.Y, ARRAY_BASE, ; 000001C0 20007010 INTERP_LOAD_P0 T0.Z, ARRAY_BASE, ; 000001C0 40007010 INTERP_LOAD_P0 * T0.W, ARRAY_BASE, ; 800001C0 60007010 ===== SHADER #19 ======================================== PS/CAYMAN/CAYMAN ===== ===== 16 dw ===== 1 gprs ===== 1 stack ========================================= 0000 00000004 a00c0000 ALU 4 @8 0008 000001c0 00007010 1 x: INTERP_LOAD_P0 R0.x, Param0.x 0010 000001c0 20007010 y: INTERP_LOAD_P0 R0.y, Param0.x 0012 000001c0 40007010 z: INTERP_LOAD_P0 R0.z, Param0.x 0014 800001c0 60007010 w: INTERP_LOAD_P0 R0.w, Param0.x 0002 c0000000 95200688 EXPORT_DONE PIXEL 0 R0.xyzw 0004 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #19 OPT ==================================== PS/CAYMAN/CAYMAN ===== ===== 14 dw ===== 1 gprs ===== 0 stack ========================================= 0000 00000003 a00c0000 ALU 4 @6 0006 000001c0 00007010 1 x: INTERP_LOAD_P0 R0.x, Param0.x 0008 000005c0 20007010 y: INTERP_LOAD_P0 R0.y, Param0.y 0010 000009c0 40007010 z: INTERP_LOAD_P0 R0.z, Param0.z 0012 80000dc0 60007010 w: INTERP_LOAD_P0 R0.w, Param0.w 0002 c0000000 95000688 EXPORT_DONE PIXEL 0 R0.xyzw 0004 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] 0: MOV OUT[0], IN[0] 1: MOV OUT[1], IN[1] 2: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg, <4 x float> inreg) #0 { main_body: %3 = extractelement <4 x float> %1, i32 0 %4 = extractelement <4 x float> %1, i32 1 %5 = extractelement <4 x float> %1, i32 2 %6 = extractelement <4 x float> %1, i32 3 %7 = extractelement <4 x float> %2, i32 0 %8 = extractelement <4 x float> %2, i32 1 %9 = extractelement <4 x float> %2, i32 2 %10 = extractelement <4 x float> %2, i32 3 %11 = insertelement <4 x float> undef, float %3, i32 0 %12 = insertelement <4 x float> %11, float %4, i32 1 %13 = insertelement <4 x float> %12, float %5, i32 2 %14 = insertelement <4 x float> %13, float %6, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %14, i32 60, i32 1) %15 = insertelement <4 x float> undef, float %7, i32 0 %16 = insertelement <4 x float> %15, float %8, i32 1 %17 = insertelement <4 x float> %16, float %9, i32 2 %18 = insertelement <4 x float> %17, float %10, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %18, i32 0, i32 2) ret void } declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="1" } Shader Disassembly: CALL_FS ; 00000000 84C00000 EXPORT T1.XYZW ; C000A03C 95000688 EXPORT T2.XYZW ; C0014000 95200688 CF_END ; 00000000 88000000 ===== SHADER #20 ======================================== VS/CAYMAN/CAYMAN ===== ===== 8 dw ===== 3 gprs ===== 1 stack ========================================== 0000 00000000 84c00000 CALL_FS @0 0002 c000a03c 95000688 EXPORT_DONE POS 60 R1.xyzw 0004 c0014000 95200688 EXPORT_DONE PARAM 0 R2.xyzw 0006 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #20 OPT ==================================== VS/CAYMAN/CAYMAN ===== ===== 8 dw ===== 3 gprs ===== 1 stack ========================================== 0000 00000000 84c00000 CALL_FS @0 0002 c0014000 95000688 EXPORT_DONE PARAM 0 R2.xyzw 0004 c000a03c 95000688 EXPORT_DONE POS 60 R1.xyzw 0006 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- VERT DCL IN[0] DCL OUT[0], POSITION 0: MOV OUT[0], IN[0] 1: END STREAMOUT 0: MEM_STREAM0_BUF0[0..0] <- OUT[0].x ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg) #0 { main_body: %2 = extractelement <4 x float> %1, i32 0 %3 = extractelement <4 x float> %1, i32 1 %4 = extractelement <4 x float> %1, i32 2 %5 = extractelement <4 x float> %1, i32 3 %6 = insertelement <4 x float> undef, float %2, i32 0 %7 = insertelement <4 x float> %6, float %3, i32 1 %8 = insertelement <4 x float> %7, float %4, i32 2 %9 = insertelement <4 x float> %8, float %5, i32 3 call void @llvm.R600.store.stream.output(<4 x float> %9, i32 0, i32 0, i32 1) %10 = insertelement <4 x float> undef, float %2, i32 0 %11 = insertelement <4 x float> %10, float %3, i32 1 %12 = insertelement <4 x float> %11, float %4, i32 2 %13 = insertelement <4 x float> %12, float %5, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %13, i32 60, i32 1) call void @llvm.R600.store.dummy(i32 2) ret void } declare void @llvm.R600.store.stream.output(<4 x float>, i32, i32, i32) declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) declare void @llvm.R600.store.dummy(i32) attributes #0 = { "ShaderType"="1" } Shader Disassembly: CALL_FS ; 00000000 84C00000 EXPORT T1 ; 00008000 90001FFF EXPORT T1.XYZW ; C000A03C 95000688 EXPORT T0.____ ; C0004000 95200FFF CF_END ; 00000000 88000000 PAD ; 00000000 00000000 ===== SHADER #21 ======================================== VS/CAYMAN/CAYMAN ===== ===== 12 dw ===== 2 gprs ===== 1 stack ========================================= 0000 00000000 84c00000 CALL_FS @0 0002 00008000 90001fff MEM_STREAM0_BUF0 WRITE 0 R1.x___ ES:0 0004 c000a03c 95000688 EXPORT_DONE POS 60 R1.xyzw 0006 c0004000 95200fff EXPORT_DONE PARAM 0 R0.____ 0008 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #21 OPT ==================================== VS/CAYMAN/CAYMAN ===== ===== 10 dw ===== 2 gprs ===== 1 stack ========================================= 0000 00000000 84c00000 CALL_FS @0 0002 c000a03c 95000688 EXPORT_DONE POS 60 R1.xyzw 0004 00008000 90001fff MEM_STREAM0_BUF0 WRITE 0 R1.x___ ES:0 0006 c0004000 95000fff EXPORT_DONE PARAM 0 R0.____ 0008 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- FRAG DCL IN[0], GENERIC[0], CONSTANT 0: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg) #0 { main_body: %2 = call <4 x float> @llvm.R600.interp.const(i32 0) call void @llvm.R600.store.dummy(i32 0) ret void } ; Function Attrs: readnone declare <4 x float> @llvm.R600.interp.const(i32) #1 declare void @llvm.R600.store.dummy(i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } Shader Disassembly: EXPORT T0.____ ; C0000000 95200FFF CF_END ; 00000000 88000000 ===== SHADER #22 ======================================== PS/CAYMAN/CAYMAN ===== ===== 4 dw ===== 1 gprs ===== 1 stack ========================================== 0000 c0000000 95200fff EXPORT_DONE PIXEL 0 R0.____ 0002 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #22 OPT ==================================== PS/CAYMAN/CAYMAN ===== ===== 4 dw ===== 0 gprs ===== 0 stack ========================================== 0000 c0000000 95000fff EXPORT_DONE PIXEL 0 R0.____ 0002 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] 0: MOV OUT[0], IN[0] 1: MOV OUT[1], IN[1] 2: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg, <4 x float> inreg) #0 { main_body: %3 = extractelement <4 x float> %1, i32 0 %4 = extractelement <4 x float> %1, i32 1 %5 = extractelement <4 x float> %1, i32 2 %6 = extractelement <4 x float> %1, i32 3 %7 = extractelement <4 x float> %2, i32 0 %8 = extractelement <4 x float> %2, i32 1 %9 = extractelement <4 x float> %2, i32 2 %10 = extractelement <4 x float> %2, i32 3 %11 = insertelement <4 x float> undef, float %3, i32 0 %12 = insertelement <4 x float> %11, float %4, i32 1 %13 = insertelement <4 x float> %12, float %5, i32 2 %14 = insertelement <4 x float> %13, float %6, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %14, i32 60, i32 1) %15 = insertelement <4 x float> undef, float %7, i32 0 %16 = insertelement <4 x float> %15, float %8, i32 1 %17 = insertelement <4 x float> %16, float %9, i32 2 %18 = insertelement <4 x float> %17, float %10, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %18, i32 0, i32 2) ret void } declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="1" } Shader Disassembly: CALL_FS ; 00000000 84C00000 EXPORT T1.XYZW ; C000A03C 95000688 EXPORT T2.XYZW ; C0014000 95200688 CF_END ; 00000000 88000000 ===== SHADER #23 ======================================== VS/CAYMAN/CAYMAN ===== ===== 8 dw ===== 3 gprs ===== 1 stack ========================================== 0000 00000000 84c00000 CALL_FS @0 0002 c000a03c 95000688 EXPORT_DONE POS 60 R1.xyzw 0004 c0014000 95200688 EXPORT_DONE PARAM 0 R2.xyzw 0006 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #23 OPT ==================================== VS/CAYMAN/CAYMAN ===== ===== 8 dw ===== 3 gprs ===== 1 stack ========================================== 0000 00000000 84c00000 CALL_FS @0 0002 c0014000 95000688 EXPORT_DONE PARAM 0 R2.xyzw 0004 c000a03c 95000688 EXPORT_DONE POS 60 R1.xyzw 0006 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] DCL OUT[2], GENERIC[10] DCL OUT[3], GENERIC[11] DCL CONST[0] IMM[0] FLT32 { 1.0000, 0.0000, -1.0000, 0.0000} 0: MOV OUT[0], IN[0] 1: MOV OUT[1], IN[1] 2: MAD OUT[2], CONST[0].xyxy, IMM[0].zyyz, IN[1].xyxy 3: MAD OUT[3], CONST[0].xyxy, IMM[0].xyyx, IN[1].xyxy 4: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg, <4 x float> inreg) #0 { main_body: %3 = extractelement <4 x float> %1, i32 0 %4 = extractelement <4 x float> %1, i32 1 %5 = extractelement <4 x float> %1, i32 2 %6 = extractelement <4 x float> %1, i32 3 %7 = extractelement <4 x float> %2, i32 0 %8 = extractelement <4 x float> %2, i32 1 %9 = extractelement <4 x float> %2, i32 2 %10 = extractelement <4 x float> %2, i32 3 %11 = load <4 x float> addrspace(8)* null %12 = extractelement <4 x float> %11, i32 0 %13 = fmul float %12, -1.000000e+00 %14 = fadd float %13, %7 %15 = load <4 x float> addrspace(8)* null %16 = extractelement <4 x float> %15, i32 1 %17 = fmul float %16, 0.000000e+00 %18 = fadd float %17, %8 %19 = load <4 x float> addrspace(8)* null %20 = extractelement <4 x float> %19, i32 0 %21 = fmul float %20, 0.000000e+00 %22 = fadd float %21, %7 %23 = load <4 x float> addrspace(8)* null %24 = extractelement <4 x float> %23, i32 1 %25 = fmul float %24, -1.000000e+00 %26 = fadd float %25, %8 %27 = load <4 x float> addrspace(8)* null %28 = extractelement <4 x float> %27, i32 0 %29 = fmul float %28, 1.000000e+00 %30 = fadd float %29, %7 %31 = load <4 x float> addrspace(8)* null %32 = extractelement <4 x float> %31, i32 1 %33 = fmul float %32, 0.000000e+00 %34 = fadd float %33, %8 %35 = load <4 x float> addrspace(8)* null %36 = extractelement <4 x float> %35, i32 0 %37 = fmul float %36, 0.000000e+00 %38 = fadd float %37, %7 %39 = load <4 x float> addrspace(8)* null %40 = extractelement <4 x float> %39, i32 1 %41 = fmul float %40, 1.000000e+00 %42 = fadd float %41, %8 %43 = insertelement <4 x float> undef, float %3, i32 0 %44 = insertelement <4 x float> %43, float %4, i32 1 %45 = insertelement <4 x float> %44, float %5, i32 2 %46 = insertelement <4 x float> %45, float %6, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %46, i32 60, i32 1) %47 = insertelement <4 x float> undef, float %7, i32 0 %48 = insertelement <4 x float> %47, float %8, i32 1 %49 = insertelement <4 x float> %48, float %9, i32 2 %50 = insertelement <4 x float> %49, float %10, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %50, i32 0, i32 2) %51 = insertelement <4 x float> undef, float %14, i32 0 %52 = insertelement <4 x float> %51, float %18, i32 1 %53 = insertelement <4 x float> %52, float %22, i32 2 %54 = insertelement <4 x float> %53, float %26, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %54, i32 1, i32 2) %55 = insertelement <4 x float> undef, float %30, i32 0 %56 = insertelement <4 x float> %55, float %34, i32 1 %57 = insertelement <4 x float> %56, float %38, i32 2 %58 = insertelement <4 x float> %57, float %42, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %58, i32 2, i32 2) ret void } declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="1" } Shader Disassembly: CALL_FS ; 00000000 84C00000 ALU 7, @8, KC0[CB0:0-32], KC1[] ; 80000008 A01C0000 EXPORT T1.XYZW ; C000A03C 95000688 EXPORT T2.XYZW ; C0014000 94C00688 EXPORT T0.XYZW ; C0004001 94C00688 EXPORT T3.XYZW ; C001C002 95200688 CF_END ; 00000000 88000000 PAD ; 00000000 00000000 ALU clause starting at 8: ; ADD T0.X, T2.X, -KC0[0].X, ; 02100002 00000010 MULADD_IEEE T0.Y, KC0[0].Y, 0.0, T2.Y, ; 001F0480 20030402 MULADD_IEEE * T0.Z, KC0[0].X, 0.0, T2.X, ; 801F0080 40030002 ADD T3.X, KC0[0].X, T2.X, ; 00004080 00600010 ADD * T0.W, T2.Y, -KC0[0].Y, ; 82900402 60000010 ADD * T3.W, KC0[0].Y, T2.Y, ; 80804480 60600010 MOV T3.Y, T0.Y, ; 00000400 20600C90 MOV * T3.Z, T0.Z, ; 80000800 40600C90 ===== SHADER #24 ======================================== VS/CAYMAN/CAYMAN ===== ===== 32 dw ===== 4 gprs ===== 1 stack ========================================= 0000 00000000 84c00000 CALL_FS @0 0002 80000008 a01c0000 ALU 8 @16 KC0[CB0:0-31] 0016 02100002 00000010 1 x: ADD R0.x, R2.x, -KC0[0].x 0018 001f0480 20030402 y: MULADD_IEEE R0.y, KC0[0].y, 0, R2.y 0020 801f0080 40030002 z: MULADD_IEEE R0.z, KC0[0].x, 0, R2.x 0022 00004080 00600010 2 x: ADD R3.x, KC0[0].x, R2.x 0024 82900402 60000010 w: ADD R0.w, R2.y, -KC0[0].y 0026 80804480 60600010 3 w: ADD R3.w, KC0[0].y, R2.y 0028 00000400 20600c90 4 y: MOV R3.y, R0.y 0030 80000800 40600c90 z: MOV R3.z, R0.z 0004 c000a03c 95000688 EXPORT_DONE POS 60 R1.xyzw 0006 c0014000 94c00688 EXPORT PARAM 0 R2.xyzw 0008 c0004001 94c00688 EXPORT PARAM 1 R0.xyzw 0010 c001c002 95200688 EXPORT_DONE PARAM 2 R3.xyzw 0012 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== ===== SHADER #24 OPT ==================================== VS/CAYMAN/CAYMAN ===== ===== 30 dw ===== 4 gprs ===== 1 stack ========================================= 0000 00000000 84c00000 CALL_FS @0 0002 40000007 a01c0000 ALU 8 @14 KC0[CB0:0-15] 0014 00004080 00000010 1 x: ADD R0.x, KC0[0].x, R2.x 0016 001f0480 20030402 y: MULADD_IEEE R0.y, KC0[0].y, 0, R2.y 0018 001f0080 40030002 z: MULADD_IEEE R0.z, KC0[0].x, 0, R2.x 0020 80804480 60000010 w: ADD R0.w, KC0[0].y, R2.y 0022 02100002 00600010 2 x: ADD R3.x, R2.x, -KC0[0].x 0024 00000400 20600c90 y: MOV R3.y, R0.y 0026 00000800 40600c90 z: MOV R3.z, R0.z 0028 82900402 60680010 w: ADD R3.w, R2.y, -KC0[0].y VEC_120 0004 c001c001 94c00688 EXPORT PARAM 1 R3.xyzw 0006 c0004002 94c00688 EXPORT PARAM 2 R0.xyzw 0008 c0014000 95000688 EXPORT_DONE PARAM 0 R2.xyzw 0010 c000a03c 95000688 EXPORT_DONE POS 60 R1.xyzw 0012 00000000 88000000 CF_END @0 ===== SHADER_END =============================================================== -------------------------------------------------------------- FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], PERSPECTIVE DCL IN[1], GENERIC[10], PERSPECTIVE DCL IN[2], GENERIC[11], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL TEMP[0..2] IMM[0] FLT32 { 0.0030, 0.0000, 1.0000, 0.0000} 0: TEX TEMP[0].x, IN[1].xyyy, SAMP[0], 2D 1: MOV TEMP[1].x, TEMP[0].xxxx 2: TEX TEMP[0].x, IN[1].zwww, SAMP[0], 2D 3: MOV TEMP[1].y, TEMP[0].xxxx 4: TEX TEMP[0].x, IN[2].xyyy, SAMP[0], 2D 5: MOV TEMP[1].z, TEMP[0].xxxx 6: TEX TEMP[0].x, IN[2].zwww, SAMP[0], 2D 7: MOV TEMP[1].w, TEMP[0].xxxx 8: TEX TEMP[0].x, IN[0].xyyy, SAMP[0], 2D 9: ADD TEMP[2], TEMP[0].xxxx, -TEMP[1] 10: ABS TEMP[0], TEMP[2] 11: SGE TEMP[2], TEMP[0], IMM[0].xxxx 12: DP4 TEMP[0].x, TEMP[2], IMM[0].zzzz 13: SEQ TEMP[1].x, TEMP[0].xxxx, IMM[0].yyyy 14: IF TEMP[1].xxxx :16 15: KILL 16: ENDIF 17: MOV OUT[0], TEMP[2] 18: END ; ModuleID = 'tgsi' define void @main(<4 x float> inreg, <4 x float> inreg, <4 x float> inreg, <4 x float> inreg) #0 { main_body: %4 = extractelement <4 x float> %0, i32 0 %5 = extractelement <4 x float> %0, i32 1 %6 = call <2 x float> @llvm.R600.interp.xy(i32 0, float %4, float %5) %7 = call <2 x float> @llvm.R600.interp.zw(i32 0, float %4, float %5) %8 = shufflevector <2 x float> %6, <2 x float> %7, <4 x i32> %9 = extractelement <4 x float> %8, i32 0 %10 = extractelement <4 x float> %8, i32 1 %11 = extractelement <4 x float> %0, i32 0 %12 = extractelement <4 x float> %0, i32 1 %13 = call <2 x float> @llvm.R600.interp.xy(i32 1, float %11, float %12) %14 = call <2 x float> @llvm.R600.interp.zw(i32 1, float %11, float %12) %15 = shufflevector <2 x float> %13, <2 x float> %14, <4 x i32> %16 = extractelement <4 x float> %15, i32 0 %17 = extractelement <4 x float> %15, i32 1 %18 = extractelement <4 x float> %15, i32 2 %19 = extractelement <4 x float> %15, i32 3 %20 = extractelement <4 x float> %0, i32 0 %21 = extractelement <4 x float> %0, i32 1 %22 = call <2 x float> @llvm.R600.interp.xy(i32 2, float %20, float %21) %23 = call <2 x float> @llvm.R600.interp.zw(i32 2, float %20, float %21) %24 = shufflevector <2 x float> %22, <2 x float> %23, <4 x i32> %25 = extractelement <4 x float> %24, i32 0 %26 = extractelement <4 x float> %24, i32 1 %27 = extractelement <4 x float> %24, i32 2 %28 = extractelement <4 x float> %24, i32 3 %29 = insertelement <4 x float> undef, float %16, i32 0 %30 = insertelement <4 x float> %29, float %17, i32 1 %31 = insertelement <4 x float> %30, float %17, i32 2 %32 = insertelement <4 x float> %31, float %17, i32 3 %33 = extractelement <4 x float> %32, i32 0 %34 = extractelement <4 x float> %32, i32 1 %35 = insertelement <4 x float> undef, float %33, i32 0 %36 = insertelement <4 x float> %35, float %34, i32 1 %37 = insertelement <4 x float> %36, float undef, i32 2 %38 = insertelement <4 x float> %37, float undef, i32 3 %39 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %38, i32 16, i32 0, i32 2) %40 = extractelement <4 x float> %39, i32 0 %41 = insertelement <4 x float> undef, float %18, i32 0 %42 = insertelement <4 x float> %41, float %19, i32 1 %43 = insertelement <4 x float> %42, float %19, i32 2 %44 = insertelement <4 x float> %43, float %19, i32 3 %45 = extractelement <4 x float> %44, i32 0 %46 = extractelement <4 x float> %44, i32 1 %47 = insertelement <4 x float> undef, float %45, i32 0 %48 = insertelement <4 x float> %47, float %46, i32 1 %49 = insertelement <4 x float> %48, float undef, i32 2 %50 = insertelement <4 x float> %49, float undef, i32 3 %51 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %50, i32 16, i32 0, i32 2) %52 = extractelement <4 x float> %51, i32 0 %53 = insertelement <4 x float> undef, float %25, i32 0 %54 = insertelement <4 x float> %53, float %26, i32 1 %55 = insertelement <4 x float> %54, float %26, i32 2 %56 = insertelement <4 x float> %55, float %26, i32 3 %57 = extractelement <4 x float> %56, i32 0 %58 = extractelement <4 x float> %56, i32 1 %59 = insertelement <4 x float> undef, float %57, i32 0 %60 = insertelement <4 x float> %59, float %58, i32 1 %61 = insertelement <4 x float> %60, float undef, i32 2 %62 = insertelement <4 x float> %61, float undef, i32 3 %63 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %62, i32 16, i32 0, i32 2) %64 = extractelement <4 x float> %63, i32 0 %65 = insertelement <4 x float> undef, float %27, i32 0 %66 = insertelement <4 x float> %65, float %28, i32 1 %67 = insertelement <4 x float> %66, float %28, i32 2 %68 = insertelement <4 x float> %67, float %28, i32 3 %69 = extractelement <4 x float> %68, i32 0 %70 = extractelement <4 x float> %68, i32 1 %71 = insertelement <4 x float> undef, float %69, i32 0 %72 = insertelement <4 x float> %71, float %70, i32 1 %73 = insertelement <4 x float> %72, float undef, i32 2 %74 = insertelement <4 x float> %73, float undef, i32 3 %75 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %74, i32 16, i32 0, i32 2) %76 = extractelement <4 x float> %75, i32 0 %77 = insertelement <4 x float> undef, float %9, i32 0 %78 = insertelement <4 x float> %77, float %10, i32 1 %79 = insertelement <4 x float> %78, float %10, i32 2 %80 = insertelement <4 x float> %79, float %10, i32 3 %81 = extractelement <4 x float> %80, i32 0 %82 = extractelement <4 x float> %80, i32 1 %83 = insertelement <4 x float> undef, float %81, i32 0 %84 = insertelement <4 x float> %83, float %82, i32 1 %85 = insertelement <4 x float> %84, float undef, i32 2 %86 = insertelement <4 x float> %85, float undef, i32 3 %87 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %86, i32 16, i32 0, i32 2) %88 = extractelement <4 x float> %87, i32 0 %89 = fsub float -0.000000e+00, %40 %90 = fadd float %88, %89 %91 = fsub float -0.000000e+00, %52 %92 = fadd float %88, %91 %93 = fsub float -0.000000e+00, %64 %94 = fadd float %88, %93 %95 = fsub float -0.000000e+00, %76 %96 = fadd float %88, %95 %97 = call float @fabs(float %90) %98 = call float @fabs(float %92) %99 = call float @fabs(float %94) %100 = call float @fabs(float %96) %101 = fcmp oge float %97, 0x3F689374C0000000 %102 = select i1 %101, float 1.000000e+00, float 0.000000e+00 %103 = fcmp oge float %98, 0x3F689374C0000000 %104 = select i1 %103, float 1.000000e+00, float 0.000000e+00 %105 = fcmp oge float %99, 0x3F689374C0000000 %106 = select i1 %105, float 1.000000e+00, float 0.000000e+00 %107 = fcmp oge float %100, 0x3F689374C0000000 %108 = select i1 %107, float 1.000000e+00, float 0.000000e+00 %109 = insertelement <4 x float> undef, float %102, i32 0 %110 = insertelement <4 x float> %109, float %104, i32 1 %111 = insertelement <4 x float> %110, float %106, i32 2 %112 = insertelement <4 x float> %111, float %108, i32 3 %113 = call float @llvm.AMDGPU.dp4(<4 x float> %112, <4 x float> ) %114 = fcmp oeq float %113, 0.000000e+00 %115 = select i1 %114, float 1.000000e+00, float 0.000000e+00 %116 = fcmp une float %115, 0.000000e+00 br i1 %116, label %IF, label %ENDIF IF: ; preds = %main_body call void @llvm.AMDGPU.kilp() br label %ENDIF ENDIF: ; preds = %main_body, %IF %117 = insertelement <4 x float> undef, float %102, i32 0 %118 = insertelement <4 x float> %117, float %104, i32 1 %119 = insertelement <4 x float> %118, float %106, i32 2 %120 = insertelement <4 x float> %119, float %108, i32 3 call void @llvm.R600.store.swizzle(<4 x float> %120, i32 0, i32 0) ret void } ; Function Attrs: readnone declare <2 x float> @llvm.R600.interp.xy(i32, float, float) #1 ; Function Attrs: readnone declare <2 x float> @llvm.R600.interp.zw(i32, float, float) #1 ; Function Attrs: readnone declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32, i32) #1 ; Function Attrs: readonly declare float @fabs(float) #2 ; Function Attrs: readnone declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1 declare void @llvm.AMDGPU.kilp() declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { readnone } attributes #2 = { readonly } /opt/Steam/SteamApps/common/Awesomenauts/run_game.sh: line 3: 15211 Aborted (core dumped) ./Awesomenauts.bin.x86 Game removed: AppID 204300 "Awesomenauts", ProcID 15209 Generating new string page texture 177: 128x256, total string texture memory is 3.60 MB unlinked 2 orphaned pipes CAsyncIOManager: 0 threads terminating. 0 reads, 0 writes, 0 deferrals. CAsyncIOManager: 11167 single object sleeps, 0 multi object sleeps CAsyncIOManager: 0 single object alertable sleeps, 1 multi object alertable sleeps Shutting down. . . [2014-01-31 18:51:24] Shutdown