From 52b5e7303096b9d38fba176a3cff471eb5d5d149 Mon Sep 17 00:00:00 2001 From: Edward Sheldrake Date: Sun, 2 Feb 2014 16:50:38 +0000 Subject: [PATCH] sna/gen4,5: Fix setting pipe control cache flush bits Cache flush bits are in dword 0 on gen4 and gen5. --- src/sna/gen4_render.c | 12 ++++++++---- src/sna/gen5_render.c | 6 ++++-- 2 files changed, 12 insertions(+), 6 deletions(-) diff --git a/src/sna/gen4_render.c b/src/sna/gen4_render.c index 1d164b6..894418b 100644 --- a/src/sna/gen4_render.c +++ b/src/sna/gen4_render.c @@ -575,8 +575,10 @@ inline static void gen4_emit_pipe_flush(struct sna *sna) { #if 1 - OUT_BATCH(GEN4_PIPE_CONTROL | (4 - 2)); - OUT_BATCH(GEN4_PIPE_CONTROL_WC_FLUSH); + OUT_BATCH(GEN4_PIPE_CONTROL | + GEN4_PIPE_CONTROL_WC_FLUSH | + (4 - 2)); + OUT_BATCH(0); OUT_BATCH(0); OUT_BATCH(0); #else @@ -601,8 +603,10 @@ inline static void gen4_emit_pipe_invalidate(struct sna *sna) { #if 0 - OUT_BATCH(GEN4_PIPE_CONTROL | (4 - 2)); - OUT_BATCH(GEN4_PIPE_CONTROL_WC_FLUSH | GEN4_PIPE_CONTROL_TC_FLUSH); + OUT_BATCH(GEN4_PIPE_CONTROL | + GEN4_PIPE_CONTROL_WC_FLUSH | GEN4_PIPE_CONTROL_TC_FLUSH | + (4 - 2)); + OUT_BATCH(0); OUT_BATCH(0); OUT_BATCH(0); #else diff --git a/src/sna/gen5_render.c b/src/sna/gen5_render.c index 8fb47cb..25555e0 100644 --- a/src/sna/gen5_render.c +++ b/src/sna/gen5_render.c @@ -1016,8 +1016,10 @@ inline static void gen5_emit_pipe_flush(struct sna *sna) { #if 0 - OUT_BATCH(GEN5_PIPE_CONTROL | (4 - 2)); - OUT_BATCH(GEN5_PIPE_CONTROL_WC_FLUSH); + OUT_BATCH(GEN5_PIPE_CONTROL | + GEN5_PIPE_CONTROL_WC_FLUSH | + (4 - 2)); + OUT_BATCH(0); OUT_BATCH(0); OUT_BATCH(0); #else -- 1.8.5.3