diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnva3.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnva3.c
index f4ae8aa..143c6ce 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnva3.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnva3.c
@@ -353,6 +353,65 @@ nva3_ram_init(struct nouveau_object *object)
 		}
 	}
 		break;
+	case NV_MEM_TYPE_GDDR5: {
+		static const u32 pattern[] = {
+			0x8b8b8b59, 0x747474a6,
+			0x74747474, 0x8b8b8b8b,
+		};
+		static const u32 offsets[] = {
+			0x00, 0x20, 0x04, 0x24,
+		};
+		int idx, o;
+		/* XXX this algorithm is insane, find some sanity to it. */
+		/* [1] MMIO32 R 0x100268 0x30030200 PFB.SUBPART_CONFIG => { SELECT_MASK = 0x2 | UNK16 = 0x3 | ENABLE_MASK = 0x3 } */
+		nv_wr32(pfb, 0x10fcac, 0x00001f01);
+		for (o = 0; o < 4; o++) {
+			int off = offsets[i];
+			for (i = 0, idx = 0; i < 0x20; i++, idx++) {
+				int pat = pattern[idx % 2];
+				if (i == 8 || i == 9 ||
+				    i == 18 || i == 19 ||
+				    i == 26 || i == 27) {
+					pat = 0;
+					if (i % 2)
+						idx++;
+				}
+				nv_wr32(pfb, 0x10f8c0 + off, (i << 8) | i);
+				nv_wr32(pfb, 0x10f940 + off, 0xf << (i % 2));
+				nv_wr32(pfb, 0x10f900 + off, pat);
+				nv_wr32(pfb, 0x10f940 + off, 0x100 | (0xf << (i % 2)));
+				nv_wr32(pfb, 0x10f900 + off, pat);
+				nv_wr32(pfb, 0x10f840 + off, i);
+				nv_wr32(pfb, 0x10f840 + off, 0x01000000 | i);
+			}
+			for (i = 0x20, idx = 0; i < 0x30; i++, idx++) {
+				int pat = pattern[2 + (idx % 2)];
+				if (i == 0x26)
+					pat = 0;
+				if (i == 0x1f)
+					pat = 0x8b8b8b59;
+				nv_wr32(pfb, 0x10f8c0 + off, (i << 8) | i);
+				nv_wr32(pfb, 0x10f940 + off, 0xf << (i % 2));
+				nv_wr32(pfb, 0x10f900 + off, pat);
+				nv_wr32(pfb, 0x10f940 + off, 0x100 | (0xf << (i % 2)));
+				nv_wr32(pfb, 0x10f900 + off, pat);
+				nv_wr32(pfb, 0x10f840 + off, i);
+				nv_wr32(pfb, 0x10f840 + off, 0x01000000 | i);
+			}
+			for (i = 0x30; i < 0x80; i++) {
+				nv_wr32(pfb, 0x10f8c0 + off, (i << 8) | i);
+				nv_wr32(pfb, 0x10f840 + off, i);
+				nv_wr32(pfb, 0x10f840 + off, 0x01000000 | i);
+			}
+		}
+
+		nv_wr32(pfb, 0x10fc20, 0x00010c04);
+		nv_wr32(pfb, 0x10fc40, 0x00000100);
+		nv_wr32(pfb, 0x10f810, 0x20012001);
+		nv_wr32(pfb, 0x10fcac, 0x00001e01);
+		nv_wr32(pfb, 0x10fc60, 0x00010808);
+	}
+		break;
 	default:
 		break;
 	}