From ddf5ca1cc0b4dcb96a2dd5cdd87622d632687ac0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Thu, 13 Mar 2014 11:32:44 +0200 Subject: [PATCH 1/3] drm/i915: Double the gen3 SR latency MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Gen4+ used 12usec as the memory latency value for self-refresh watermarks. Gen3 currently uses 6usec. Double the gen3 value to 12usec. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_pm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index e1fc35a..3d09738 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -1553,7 +1553,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc) /* Calc sr entries for one plane configs */ if (HAS_FW_BLC(dev) && enabled) { /* self-refresh has much higher latency */ - static const int sr_latency_ns = 6000; + static const int sr_latency_ns = 12000; const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config.adjusted_mode; int clock = adjusted_mode->crtc_clock; -- 1.8.3.2