diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ad58ce3b7675..4bc84fc408ae 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1550,12 +1550,6 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
 	 */
 	cwm = 2;
 
-	/* Play safe and disable self-refresh before adjusting watermarks. */
-	if (IS_I945G(dev) || IS_I945GM(dev))
-		I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
-	else if (IS_I915GM(dev))
-		I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_SELF_EN));
-
 	/* Calc sr entries for one plane configs */
 	if (HAS_FW_BLC(dev) && enabled) {
 		/* self-refresh has much higher latency */
@@ -1608,8 +1602,13 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
 			else if (IS_I915GM(dev))
 				I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_SELF_EN));
 			DRM_DEBUG_KMS("memory self refresh enabled\n");
-		} else
+		} else {
+			if (IS_I945G(dev) || IS_I945GM(dev))
+				I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
+			else if (IS_I915GM(dev))
+				I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_SELF_EN));
 			DRM_DEBUG_KMS("memory self refresh disabled\n");
+		}
 	}
 }