diff --git a/drivers/gpu/drm/radeon/ci_dpm.c b/drivers/gpu/drm/radeon/ci_dpm.c index 8d49104..b833e0d 100644 --- a/drivers/gpu/drm/radeon/ci_dpm.c +++ b/drivers/gpu/drm/radeon/ci_dpm.c @@ -236,7 +236,7 @@ static void ci_initialize_powertune_defaults(struct radeon_device *rdev) pi->dte_tj_offset = 0; - pi->caps_power_containment = true; + pi->caps_power_containment = false; pi->caps_cac = false; pi->caps_sq_ramping = false; pi->caps_db_ramping = false; @@ -5102,11 +5102,11 @@ int ci_dpm_init(struct radeon_device *rdev) pi->mclk_activity_target = CISLAND_MCLK_TARGETACTIVITY_DFLT; - pi->sclk_dpm_key_disabled = 0; - pi->mclk_dpm_key_disabled = 0; - pi->pcie_dpm_key_disabled = 0; + pi->sclk_dpm_key_disabled = 1; + pi->mclk_dpm_key_disabled = 1; + pi->pcie_dpm_key_disabled = 1; - pi->caps_sclk_ds = true; + pi->caps_sclk_ds = false; pi->mclk_strobe_mode_threshold = 40000; pi->mclk_stutter_mode_threshold = 40000; @@ -5188,24 +5188,24 @@ int ci_dpm_init(struct radeon_device *rdev) rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_MVDDCONTROL; } - pi->vddc_phase_shed_control = true; + pi->vddc_phase_shed_control = false; #if defined(CONFIG_ACPI) - pi->pcie_performance_request = - radeon_acpi_is_pcie_performance_request_supported(rdev); + pi->pcie_performance_request = false; +// radeon_acpi_is_pcie_performance_request_supported(rdev); #else pi->pcie_performance_request = false; #endif if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, &frev, &crev, &data_offset)) { - pi->caps_sclk_ss_support = true; - pi->caps_mclk_ss_support = true; - pi->dynamic_ss = true; + pi->caps_sclk_ss_support = false; + pi->caps_mclk_ss_support = false; + pi->dynamic_ss = false; } else { pi->caps_sclk_ss_support = false; pi->caps_mclk_ss_support = false; - pi->dynamic_ss = true; + pi->dynamic_ss = false; } if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE) diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c index dda02bf..bc730e4 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.c +++ b/drivers/gpu/drm/radeon/radeon_asic.c @@ -2457,7 +2457,7 @@ int radeon_asic_init(struct radeon_device *rdev) rdev->num_crtc = 6; rdev->has_uvd = true; if (rdev->family == CHIP_BONAIRE) { - rdev->cg_flags = + rdev->cg_flags = 0; /* RADEON_CG_SUPPORT_GFX_MGCG | RADEON_CG_SUPPORT_GFX_MGLS | RADEON_CG_SUPPORT_GFX_CGCG | @@ -2474,6 +2474,7 @@ int radeon_asic_init(struct radeon_device *rdev) RADEON_CG_SUPPORT_UVD_MGCG | RADEON_CG_SUPPORT_HDP_LS | RADEON_CG_SUPPORT_HDP_MGCG; + */ rdev->pg_flags = 0; } else { rdev->cg_flags =