[   41.308304] switching from power state:
[   41.308311] 	ui class: performance
[   41.308314] 	internal class: none
[   41.308317] 	caps: 
[   41.308320] 	uvd    vclk: 0 dclk: 0
[   41.308324] 		power level 0    sclk: 30000 mclk: 15000 pcie gen: 2 pcie lanes: 16
[   41.308328] 		power level 1    sclk: 115000 mclk: 165000 pcie gen: 2 pcie lanes: 16
[   41.308329] 	status: c r 
[   41.308333] switching to power state:
[   41.308334] 	ui class: performance
[   41.308336] 	internal class: none
[   41.308338] 	caps: 
[   41.308340] 	uvd    vclk: 0 dclk: 0
[   41.308342] 		power level 0    sclk: 30000 mclk: 15000 pcie gen: 2 pcie lanes: 16
[   41.308345] 		power level 1    sclk: 115000 mclk: 165000 pcie gen: 2 pcie lanes: 16
[   41.308346] 	status: c r 
[   41.508460] [drm:ci_dpm_set_power_state] *ERROR* ci_upload_dpm_level_enable_mask failed