FRAG 0: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) ret void } declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32) attributes #0 = { "ShaderType"="0" } Shader Disassembly: V_MOV_B32_e32 v0, 0 ; 7E000280 EXP 0, 0, 0, 1, 1, v0, v0, v0, v0 ; F8001800 00000000 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %22 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %5) %23 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %5) %24 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %5) %25 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %5) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %23, float %24, float %25) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s9 ; BEFC0309 V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302 V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202 V_INTERP_MOV_F32 v2, P0, 1, 0, [m0] ; C80A0102 V_INTERP_MOV_F32 v3, P0, 0, 0, [m0] ; C80E0002 EXP 15, 0, 0, 1, 1, v3, v2, v1, v0 ; F800180F 00010203 S_ENDPGM ; BF810000 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %22 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %5) %23 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %5) %24 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %5) %25 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %5) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %23, float %24, float %25) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s9 ; BEFC0309 V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302 V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202 V_INTERP_MOV_F32 v2, P0, 1, 0, [m0] ; C80A0102 V_INTERP_MOV_F32 v3, P0, 0, 0, [m0] ; C80E0002 EXP 15, 0, 0, 1, 1, v3, v2, v1, v0 ; F800180F 00010203 S_ENDPGM ; BF810000 VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] 0: MOV OUT[0], IN[0] 1: MOV OUT[1], IN[1] 2: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 0 %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0 %12 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %11, i32 0, i32 %6) %13 = extractelement <4 x float> %12, i32 0 %14 = extractelement <4 x float> %12, i32 1 %15 = extractelement <4 x float> %12, i32 2 %16 = extractelement <4 x float> %12, i32 3 %17 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 1 %18 = load <16 x i8> addrspace(2)* %17, !tbaa !0 %19 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %18, i32 0, i32 %6) %20 = extractelement <4 x float> %19, i32 0 %21 = extractelement <4 x float> %19, i32 1 %22 = extractelement <4 x float> %19, i32 2 %23 = extractelement <4 x float> %19, i32 3 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %20, float %21, float %22, float %23) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %13, float %14, float %15, float %16) ret void } ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_LOAD_DWORDX4 s[0:3], s[8:9], 4 ; C0800904 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[1:4], s[0:3][v0] + 0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80000100 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 32, 0, 0, 0, v1, v2, v3, v4 ; F800020F 04030201 S_LOAD_DWORDX4 s[0:3], s[8:9], 0 ; C0800900 S_WAITCNT expcnt(0) lgkmcnt(0) ; BF8C000F BUFFER_LOAD_FORMAT_XYZW v[0:3], s[0:3][v0] + 0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80000000 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 12, 0, 1, 0, v0, v1, v2, v3 ; F80008CF 03020100 S_ENDPGM ; BF810000 VERT DCL IN[0] DCL OUT[0], POSITION 0: MOV OUT[0], IN[0] 1: END STREAMOUT 0: BUF0[0..0] <- OUT[0].x ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %13 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 2 %14 = load <16 x i8> addrspace(2)* %13, !tbaa !0 %15 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 0 %16 = load <16 x i8> addrspace(2)* %15, !tbaa !0 %17 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %16, i32 0, i32 %9) %18 = extractelement <4 x float> %17, i32 0 %19 = extractelement <4 x float> %17, i32 1 %20 = extractelement <4 x float> %17, i32 2 %21 = extractelement <4 x float> %17, i32 3 %22 = lshr i32 %6, 16 %23 = and i32 %22, 127 %24 = call i32 @llvm.SI.tid() %25 = icmp ult i32 %24, %23 br i1 %25, label %if-true-block, label %endif-block if-true-block: ; preds = %main_body %26 = add i32 %7, %24 %27 = mul i32 %8, 4 %28 = mul i32 %26, 4 %29 = add i32 %28, %27 %30 = bitcast float %18 to i32 call void @llvm.SI.tbuffer.store.i32(<16 x i8> %14, i32 %30, i32 1, i32 %29, i32 0, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0) br label %endif-block endif-block: ; preds = %main_body, %if-true-block call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %18, float %19, float %20, float %21) ret void } ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 ; Function Attrs: readnone declare i32 @llvm.SI.tid() #2 declare void @llvm.SI.tbuffer.store.i32(<16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32) declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_LOAD_DWORDX4 s[0:3], s[8:9], 0 ; C0800900 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[0:3], s[0:3][v0] + 0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80000000 S_LSHR_B32 s0, s11, 16 ; 9000900B V_MOV_B32_e32 v4, 127 ; 7E0802FF 0000007F V_AND_B32_e32 v5, s0, v4 ; 360A0800 V_MBCNT_LO_U32_B32_e64 v4, -1, 0, 0, 0, 0, 0 ; D2460004 020100C1 V_MBCNT_HI_U32_B32_e32 v4, -1, v4 ; 480808C1 V_CMP_LT_U32_e64 s[0:1], v4, v5, 0, 0, 0, 0 ; D1820000 02020B04 S_WAITCNT vmcnt(0) ; BF8C0770 S_AND_SAVEEXEC_B64 s[0:1], s[0:1] ; BE802400 S_XOR_B64 s[0:1], exec, s[0:1] ; 8980007E V_ADD_I32_e32 v4, s12, v4 ; 4A08080C V_LSHLREV_B32_e32 v4, 2, v4 ; 34080882 S_LSHL_B32 s2, s13, 2 ; 8F02820D V_ADD_I32_e32 v4, s2, v4 ; 4A080802 S_LOAD_DWORDX4 s[4:7], s[6:7], 8 ; C0820708 S_WAITCNT lgkmcnt(0) ; BF8C007F TBUFFER_STORE_FORMAT_X v0, 0, -1, 0, -1, 0, 4, 4, v4, s[4:7], -1, 0, 0 ; EA245000 80410004 S_WAITCNT vmcnt(0) expcnt(0) ; BF8C0700 S_OR_B64 exec, exec, s[0:1] ; 88FE007E EXP 15, 12, 0, 1, 0, v0, v1, v2, v3 ; F80008CF 03020100 S_ENDPGM ; BF810000 VERT DCL IN[0] DCL IN[1] DCL SV[0], INSTANCEID DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] DCL OUT[2], LAYER 0: MOV OUT[0], IN[0] 1: MOV OUT[1], IN[1] 2: MOV OUT[2], SV[0] 3: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 0 %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0 %12 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %11, i32 0, i32 %6) %13 = extractelement <4 x float> %12, i32 0 %14 = extractelement <4 x float> %12, i32 1 %15 = extractelement <4 x float> %12, i32 2 %16 = extractelement <4 x float> %12, i32 3 %17 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 1 %18 = load <16 x i8> addrspace(2)* %17, !tbaa !0 %19 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %18, i32 0, i32 %6) %20 = extractelement <4 x float> %19, i32 0 %21 = extractelement <4 x float> %19, i32 1 %22 = extractelement <4 x float> %19, i32 2 %23 = extractelement <4 x float> %19, i32 3 %24 = bitcast i32 %9 to float call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %20, float %21, float %22, float %23) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 12, i32 0, float %13, float %14, float %15, float %16) call void @llvm.SI.export(i32 4, i32 0, i32 1, i32 13, i32 0, float 0.000000e+00, float 0.000000e+00, float %24, float 0.000000e+00) ret void } ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_LOAD_DWORDX4 s[0:3], s[8:9], 4 ; C0800904 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[4:7], s[0:3][v0] + 0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80000400 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 32, 0, 0, 0, v4, v5, v6, v7 ; F800020F 07060504 S_LOAD_DWORDX4 s[0:3], s[8:9], 0 ; C0800900 S_WAITCNT expcnt(0) lgkmcnt(0) ; BF8C000F BUFFER_LOAD_FORMAT_XYZW v[4:7], s[0:3][v0] + 0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80000400 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 12, 0, 0, 0, v4, v5, v6, v7 ; F80000CF 07060504 V_MOV_B32_e32 v0, 0.000000e+00 ; 7E000280 EXP 4, 13, 0, 1, 0, v0, v0, v3, v0 ; F80008D4 00030000 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[0], CONSTANT 0: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } Shader Disassembly: V_MOV_B32_e32 v0, 0 ; 7E000280 EXP 0, 0, 0, 1, 1, v0, v0, v0, v0 ; F8001800 00000000 S_ENDPGM ; BF810000 FRAG 0: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) ret void } declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32) attributes #0 = { "ShaderType"="0" } Shader Disassembly: V_MOV_B32_e32 v0, 0 ; 7E000280 EXP 0, 0, 0, 1, 1, v0, v0, v0, v0 ; F8001800 00000000 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %22 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %5) %23 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %5) %24 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %5) %25 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %5) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %23, float %24, float %25) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s9 ; BEFC0309 V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302 V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202 V_INTERP_MOV_F32 v2, P0, 1, 0, [m0] ; C80A0102 V_INTERP_MOV_F32 v3, P0, 0, 0, [m0] ; C80E0002 EXP 15, 0, 0, 1, 1, v3, v2, v1, v0 ; F800180F 00010203 S_ENDPGM ; BF810000 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %22 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %5) %23 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %5) %24 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %5) %25 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %5) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %23, float %24, float %25) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s9 ; BEFC0309 V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302 V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202 V_INTERP_MOV_F32 v2, P0, 1, 0, [m0] ; C80A0102 V_INTERP_MOV_F32 v3, P0, 0, 0, [m0] ; C80E0002 EXP 15, 0, 0, 1, 1, v3, v2, v1, v0 ; F800180F 00010203 S_ENDPGM ; BF810000 VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] 0: MOV OUT[0], IN[0] 1: MOV OUT[1], IN[1] 2: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 0 %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0 %12 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %11, i32 0, i32 %6) %13 = extractelement <4 x float> %12, i32 0 %14 = extractelement <4 x float> %12, i32 1 %15 = extractelement <4 x float> %12, i32 2 %16 = extractelement <4 x float> %12, i32 3 %17 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 1 %18 = load <16 x i8> addrspace(2)* %17, !tbaa !0 %19 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %18, i32 0, i32 %6) %20 = extractelement <4 x float> %19, i32 0 %21 = extractelement <4 x float> %19, i32 1 %22 = extractelement <4 x float> %19, i32 2 %23 = extractelement <4 x float> %19, i32 3 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %20, float %21, float %22, float %23) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %13, float %14, float %15, float %16) ret void } ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_LOAD_DWORDX4 s[0:3], s[8:9], 4 ; C0800904 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[1:4], s[0:3][v0] + 0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80000100 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 32, 0, 0, 0, v1, v2, v3, v4 ; F800020F 04030201 S_LOAD_DWORDX4 s[0:3], s[8:9], 0 ; C0800900 S_WAITCNT expcnt(0) lgkmcnt(0) ; BF8C000F BUFFER_LOAD_FORMAT_XYZW v[0:3], s[0:3][v0] + 0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80000000 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 12, 0, 1, 0, v0, v1, v2, v3 ; F80008CF 03020100 S_ENDPGM ; BF810000 VERT DCL IN[0] DCL OUT[0], POSITION 0: MOV OUT[0], IN[0] 1: END STREAMOUT 0: BUF0[0..0] <- OUT[0].x ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %13 = getelementptr [17 x <16 x i8>] addrspace(2)* %3, i64 0, i32 2 %14 = load <16 x i8> addrspace(2)* %13, !tbaa !0 %15 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 0 %16 = load <16 x i8> addrspace(2)* %15, !tbaa !0 %17 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %16, i32 0, i32 %9) %18 = extractelement <4 x float> %17, i32 0 %19 = extractelement <4 x float> %17, i32 1 %20 = extractelement <4 x float> %17, i32 2 %21 = extractelement <4 x float> %17, i32 3 %22 = lshr i32 %6, 16 %23 = and i32 %22, 127 %24 = call i32 @llvm.SI.tid() %25 = icmp ult i32 %24, %23 br i1 %25, label %if-true-block, label %endif-block if-true-block: ; preds = %main_body %26 = add i32 %7, %24 %27 = mul i32 %8, 4 %28 = mul i32 %26, 4 %29 = add i32 %28, %27 %30 = bitcast float %18 to i32 call void @llvm.SI.tbuffer.store.i32(<16 x i8> %14, i32 %30, i32 1, i32 %29, i32 0, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0) br label %endif-block endif-block: ; preds = %main_body, %if-true-block call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %18, float %19, float %20, float %21) ret void } ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 ; Function Attrs: readnone declare i32 @llvm.SI.tid() #2 declare void @llvm.SI.tbuffer.store.i32(<16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32) declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_LOAD_DWORDX4 s[0:3], s[8:9], 0 ; C0800900 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[0:3], s[0:3][v0] + 0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80000000 S_LSHR_B32 s0, s11, 16 ; 9000900B V_MOV_B32_e32 v4, 127 ; 7E0802FF 0000007F V_AND_B32_e32 v5, s0, v4 ; 360A0800 V_MBCNT_LO_U32_B32_e64 v4, -1, 0, 0, 0, 0, 0 ; D2460004 020100C1 V_MBCNT_HI_U32_B32_e32 v4, -1, v4 ; 480808C1 V_CMP_LT_U32_e64 s[0:1], v4, v5, 0, 0, 0, 0 ; D1820000 02020B04 S_WAITCNT vmcnt(0) ; BF8C0770 S_AND_SAVEEXEC_B64 s[0:1], s[0:1] ; BE802400 S_XOR_B64 s[0:1], exec, s[0:1] ; 8980007E V_ADD_I32_e32 v4, s12, v4 ; 4A08080C V_LSHLREV_B32_e32 v4, 2, v4 ; 34080882 S_LSHL_B32 s2, s13, 2 ; 8F02820D V_ADD_I32_e32 v4, s2, v4 ; 4A080802 S_LOAD_DWORDX4 s[4:7], s[6:7], 8 ; C0820708 S_WAITCNT lgkmcnt(0) ; BF8C007F TBUFFER_STORE_FORMAT_X v0, 0, -1, 0, -1, 0, 4, 4, v4, s[4:7], -1, 0, 0 ; EA245000 80410004 S_WAITCNT vmcnt(0) expcnt(0) ; BF8C0700 S_OR_B64 exec, exec, s[0:1] ; 88FE007E EXP 15, 12, 0, 1, 0, v0, v1, v2, v3 ; F80008CF 03020100 S_ENDPGM ; BF810000 VERT DCL IN[0] DCL IN[1] DCL SV[0], INSTANCEID DCL OUT[0], POSITION DCL OUT[1], GENERIC[0] DCL OUT[2], LAYER 0: MOV OUT[0], IN[0] 1: MOV OUT[1], IN[1] 2: MOV OUT[2], SV[0] 3: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 0 %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0 %12 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %11, i32 0, i32 %6) %13 = extractelement <4 x float> %12, i32 0 %14 = extractelement <4 x float> %12, i32 1 %15 = extractelement <4 x float> %12, i32 2 %16 = extractelement <4 x float> %12, i32 3 %17 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 1 %18 = load <16 x i8> addrspace(2)* %17, !tbaa !0 %19 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %18, i32 0, i32 %6) %20 = extractelement <4 x float> %19, i32 0 %21 = extractelement <4 x float> %19, i32 1 %22 = extractelement <4 x float> %19, i32 2 %23 = extractelement <4 x float> %19, i32 3 %24 = bitcast i32 %9 to float call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %20, float %21, float %22, float %23) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 12, i32 0, float %13, float %14, float %15, float %16) call void @llvm.SI.export(i32 4, i32 0, i32 1, i32 13, i32 0, float 0.000000e+00, float 0.000000e+00, float %24, float 0.000000e+00) ret void } ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_LOAD_DWORDX4 s[0:3], s[8:9], 4 ; C0800904 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[4:7], s[0:3][v0] + 0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80000400 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 32, 0, 0, 0, v4, v5, v6, v7 ; F800020F 07060504 S_LOAD_DWORDX4 s[0:3], s[8:9], 0 ; C0800900 S_WAITCNT expcnt(0) lgkmcnt(0) ; BF8C000F BUFFER_LOAD_FORMAT_XYZW v[4:7], s[0:3][v0] + 0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80000400 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 12, 0, 0, 0, v4, v5, v6, v7 ; F80000CF 07060504 V_MOV_B32_e32 v0, 0.000000e+00 ; 7E000280 EXP 4, 13, 0, 1, 0, v0, v0, v3, v0 ; F80008D4 00030000 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[0], CONSTANT 0: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } Shader Disassembly: V_MOV_B32_e32 v0, 0 ; 7E000280 EXP 0, 0, 0, 1, 1, v0, v0, v0, v0 ; F8001800 00000000 S_ENDPGM ; BF810000 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], COLOR, CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %22 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %5) %23 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %5) %24 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %5) %25 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %5) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %23, float %24, float %25) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s9 ; BEFC0309 V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302 V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202 V_INTERP_MOV_F32 v2, P0, 1, 0, [m0] ; C80A0102 V_INTERP_MOV_F32 v3, P0, 0, 0, [m0] ; C80E0002 EXP 15, 0, 0, 1, 1, v3, v2, v1, v0 ; F800180F 00010203 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[0], LINEAR DCL SAMP[0] DCL OUT[0], COLOR DCL TEMP[0] 0: TEX TEMP[0], IN[0], SAMP[0], RECT 1: MOV OUT[0], TEMP[0].xxxx 2: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %22 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0 %23 = load <32 x i8> addrspace(2)* %22, !tbaa !0 %24 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0 %25 = load <16 x i8> addrspace(2)* %24, !tbaa !0 %26 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %11) %27 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %11) %28 = bitcast float %26 to i32 %29 = bitcast float %27 to i32 %30 = insertelement <2 x i32> undef, i32 %28, i32 0 %31 = insertelement <2 x i32> %30, i32 %29, i32 1 %32 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %31, <32 x i8> %23, <16 x i8> %25, i32 5) %33 = extractelement <4 x float> %32, i32 0 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %33, float %33, float %33, float %33) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s9 ; BEFC0309 V_INTERP_P1_F32 v3, v0, 1, 0, [m0] ; C80C0100 V_INTERP_P2_F32 v3, [v3], v1, 1, 0, [m0] ; C80D0101 V_INTERP_P1_F32 v2, v0, 0, 0, [m0] ; C8080000 V_INTERP_P2_F32 v2, [v2], v1, 0, 0, [m0] ; C8090001 S_LOAD_DWORDX4 s[0:3], s[2:3], 0 ; C0800300 S_LOAD_DWORDX8 s[4:11], s[4:5], 0 ; C0C20500 S_WAITCNT lgkmcnt(0) ; BF8C007F IMAGE_SAMPLE v0, 1, -1, 0, 0, 0, 0, 0, 0, v[2:3], s[4:11], s[0:3] ; F0801100 00010002 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 0, 0, 1, 1, v0, v0, v0, v0 ; F800180F 00000000 S_ENDPGM ; BF810000 VERT DCL IN[0..1] DCL OUT[0], POSITION DCL OUT[1], COLOR DCL OUT[2], GENERIC[0] DCL CONST[0..2] DCL TEMP[0] IMM[0] FLT32 { -1.0000, 0.0000, 0.0000, 1.0000} 0: MAD TEMP[0].xy, IN[0], CONST[2].xyyy, CONST[1].zwww 1: MAD OUT[0].xy, TEMP[0], CONST[1].xyyy, IMM[0].xxxx 2: MOV OUT[0].zw, IMM[0] 3: MOV OUT[1], CONST[0] 4: MOV OUT[2], IN[1] 5: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0 %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0 %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0) %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4) %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8) %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12) %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16) %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20) %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24) %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28) %20 = call float @llvm.SI.load.const(<16 x i8> %11, i32 32) %21 = call float @llvm.SI.load.const(<16 x i8> %11, i32 36) %22 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 0 %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0 %24 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %23, i32 0, i32 %6) %25 = extractelement <4 x float> %24, i32 0 %26 = extractelement <4 x float> %24, i32 1 %27 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 1 %28 = load <16 x i8> addrspace(2)* %27, !tbaa !0 %29 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %28, i32 0, i32 %6) %30 = extractelement <4 x float> %29, i32 0 %31 = extractelement <4 x float> %29, i32 1 %32 = extractelement <4 x float> %29, i32 2 %33 = extractelement <4 x float> %29, i32 3 %34 = fmul float %25, %20 %35 = fadd float %34, %18 %36 = fmul float %26, %21 %37 = fadd float %36, %19 %38 = fmul float %35, %16 %39 = fadd float %38, -1.000000e+00 %40 = fmul float %37, %17 %41 = fadd float %40, -1.000000e+00 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %12, float %13, float %14, float %15) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %30, float %31, float %32, float %33) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %39, float %41, float 0.000000e+00, float 1.000000e+00) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_LOAD_DWORDX4 s[0:3], s[0:1], 0 ; C0800100 S_WAITCNT lgkmcnt(0) ; BF8C007F S_BUFFER_LOAD_DWORD s4, s[0:3], 3 ; C2020103 S_BUFFER_LOAD_DWORD s5, s[0:3], 2 ; C2028102 S_BUFFER_LOAD_DWORD s6, s[0:3], 1 ; C2030101 S_BUFFER_LOAD_DWORD s7, s[0:3], 0 ; C2038100 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v1, s7 ; 7E020207 V_MOV_B32_e32 v2, s6 ; 7E040206 V_MOV_B32_e32 v3, s5 ; 7E060205 V_MOV_B32_e32 v4, s4 ; 7E080204 EXP 15, 32, 0, 0, 0, v1, v2, v3, v4 ; F800020F 04030201 S_LOAD_DWORDX4 s[4:7], s[8:9], 4 ; C0820904 S_WAITCNT expcnt(0) lgkmcnt(0) ; BF8C000F BUFFER_LOAD_FORMAT_XYZW v[1:4], s[4:7][v0] + 0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80010100 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 33, 0, 0, 0, v1, v2, v3, v4 ; F800021F 04030201 S_LOAD_DWORDX4 s[4:7], s[8:9], 0 ; C0820900 S_WAITCNT expcnt(0) lgkmcnt(0) ; BF8C000F BUFFER_LOAD_FORMAT_XYZW v[0:3], s[4:7][v0] + 0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80010000 S_BUFFER_LOAD_DWORD s4, s[0:3], 7 ; C2020107 S_WAITCNT vmcnt(0) lgkmcnt(0) ; BF8C0070 V_MOV_B32_e32 v4, s4 ; 7E080204 S_BUFFER_LOAD_DWORD s4, s[0:3], 9 ; C2020109 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v5, s4 ; 7E0A0204 V_MAD_F32 v4, v1, v5, v4, 0, 0, 0, 0 ; D2820004 04120B01 S_BUFFER_LOAD_DWORD s4, s[0:3], 5 ; C2020105 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v4, v4, s4, -1.000000e+00, 0, 0, 0, 0 ; D2820004 03CC0904 S_BUFFER_LOAD_DWORD s4, s[0:3], 6 ; C2020106 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v5, s4 ; 7E0A0204 S_BUFFER_LOAD_DWORD s4, s[0:3], 8 ; C2020108 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v6, s4 ; 7E0C0204 V_MAD_F32 v0, v0, v6, v5, 0, 0, 0, 0 ; D2820000 04160D00 S_BUFFER_LOAD_DWORD s0, s[0:3], 4 ; C2000104 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v0, v0, s0, -1.000000e+00, 0, 0, 0, 0 ; D2820000 03CC0100 V_MOV_B32_e32 v1, 1.000000e+00 ; 7E0202F2 V_MOV_B32_e32 v2, 0.000000e+00 ; 7E040280 EXP 15, 12, 0, 1, 0, v0, v4, v2, v1 ; F80008CF 01020400 S_ENDPGM ; BF810000 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], COLOR, COLOR DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %22 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %7) %23 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %7) %24 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %5, <2 x i32> %7) %25 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %5, <2 x i32> %7) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %23, float %24, float %25) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s9 ; BEFC0309 V_INTERP_P1_F32 v2, v0, 3, 0, [m0] ; C8080300 V_INTERP_P2_F32 v2, [v2], v1, 3, 0, [m0] ; C8090301 V_INTERP_P1_F32 v3, v0, 2, 0, [m0] ; C80C0200 V_INTERP_P2_F32 v3, [v3], v1, 2, 0, [m0] ; C80D0201 V_INTERP_P1_F32 v4, v0, 1, 0, [m0] ; C8100100 V_INTERP_P2_F32 v4, [v4], v1, 1, 0, [m0] ; C8110101 V_INTERP_P1_F32 v5, v0, 0, 0, [m0] ; C8140000 V_INTERP_P2_F32 v5, [v5], v1, 0, 0, [m0] ; C8150001 EXP 15, 0, 0, 1, 1, v5, v4, v3, v2 ; F800180F 02030405 S_ENDPGM ; BF810000 VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], COLOR DCL CONST[0..3] DCL TEMP[0] 0: MUL TEMP[0], IN[0].xxxx, CONST[0] 1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0] 2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0] 3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0] 4: MOV OUT[1], IN[1] 5: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0 %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0 %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0) %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4) %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8) %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12) %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16) %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20) %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24) %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28) %20 = call float @llvm.SI.load.const(<16 x i8> %11, i32 32) %21 = call float @llvm.SI.load.const(<16 x i8> %11, i32 36) %22 = call float @llvm.SI.load.const(<16 x i8> %11, i32 40) %23 = call float @llvm.SI.load.const(<16 x i8> %11, i32 44) %24 = call float @llvm.SI.load.const(<16 x i8> %11, i32 48) %25 = call float @llvm.SI.load.const(<16 x i8> %11, i32 52) %26 = call float @llvm.SI.load.const(<16 x i8> %11, i32 56) %27 = call float @llvm.SI.load.const(<16 x i8> %11, i32 60) %28 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 0 %29 = load <16 x i8> addrspace(2)* %28, !tbaa !0 %30 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %29, i32 0, i32 %6) %31 = extractelement <4 x float> %30, i32 0 %32 = extractelement <4 x float> %30, i32 1 %33 = extractelement <4 x float> %30, i32 2 %34 = extractelement <4 x float> %30, i32 3 %35 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 1 %36 = load <16 x i8> addrspace(2)* %35, !tbaa !0 %37 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %36, i32 0, i32 %6) %38 = extractelement <4 x float> %37, i32 0 %39 = extractelement <4 x float> %37, i32 1 %40 = extractelement <4 x float> %37, i32 2 %41 = extractelement <4 x float> %37, i32 3 %42 = fmul float %31, %12 %43 = fmul float %31, %13 %44 = fmul float %31, %14 %45 = fmul float %31, %15 %46 = fmul float %32, %16 %47 = fadd float %46, %42 %48 = fmul float %32, %17 %49 = fadd float %48, %43 %50 = fmul float %32, %18 %51 = fadd float %50, %44 %52 = fmul float %32, %19 %53 = fadd float %52, %45 %54 = fmul float %33, %20 %55 = fadd float %54, %47 %56 = fmul float %33, %21 %57 = fadd float %56, %49 %58 = fmul float %33, %22 %59 = fadd float %58, %51 %60 = fmul float %33, %23 %61 = fadd float %60, %53 %62 = fmul float %34, %24 %63 = fadd float %62, %55 %64 = fmul float %34, %25 %65 = fadd float %64, %57 %66 = fmul float %34, %26 %67 = fadd float %66, %59 %68 = fmul float %34, %27 %69 = fadd float %68, %61 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %38, float %39, float %40, float %41) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %63, float %65, float %67, float %69) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_LOAD_DWORDX4 s[4:7], s[8:9], 4 ; C0820904 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[1:4], s[4:7][v0] + 0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80010100 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 32, 0, 0, 0, v1, v2, v3, v4 ; F800020F 04030201 S_LOAD_DWORDX4 s[4:7], s[8:9], 0 ; C0820900 S_WAITCNT expcnt(0) lgkmcnt(0) ; BF8C000F BUFFER_LOAD_FORMAT_XYZW v[0:3], s[4:7][v0] + 0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80010000 S_LOAD_DWORDX4 s[0:3], s[0:1], 0 ; C0800100 S_WAITCNT vmcnt(0) lgkmcnt(0) ; BF8C0070 S_BUFFER_LOAD_DWORD s4, s[0:3], 3 ; C2020103 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v4, s4 ; 7E080204 V_MUL_F32_e64 v4, v0, v4, 0, 0, 0, 0 ; D2100004 02020900 S_BUFFER_LOAD_DWORD s4, s[0:3], 7 ; C2020107 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v5, s4 ; 7E0A0204 V_MAD_F32 v4, v1, v5, v4, 0, 0, 0, 0 ; D2820004 04120B01 S_BUFFER_LOAD_DWORD s4, s[0:3], 11 ; C202010B S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v5, s4 ; 7E0A0204 V_MAD_F32 v4, v2, v5, v4, 0, 0, 0, 0 ; D2820004 04120B02 S_BUFFER_LOAD_DWORD s4, s[0:3], 15 ; C202010F S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v5, s4 ; 7E0A0204 V_MAD_F32 v4, v3, v5, v4, 0, 0, 0, 0 ; D2820004 04120B03 S_BUFFER_LOAD_DWORD s4, s[0:3], 2 ; C2020102 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v5, s4 ; 7E0A0204 V_MUL_F32_e64 v5, v0, v5, 0, 0, 0, 0 ; D2100005 02020B00 S_BUFFER_LOAD_DWORD s4, s[0:3], 6 ; C2020106 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v6, s4 ; 7E0C0204 V_MAD_F32 v5, v1, v6, v5, 0, 0, 0, 0 ; D2820005 04160D01 S_BUFFER_LOAD_DWORD s4, s[0:3], 10 ; C202010A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v6, s4 ; 7E0C0204 V_MAD_F32 v5, v2, v6, v5, 0, 0, 0, 0 ; D2820005 04160D02 S_BUFFER_LOAD_DWORD s4, s[0:3], 14 ; C202010E S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v6, s4 ; 7E0C0204 V_MAD_F32 v5, v3, v6, v5, 0, 0, 0, 0 ; D2820005 04160D03 S_BUFFER_LOAD_DWORD s4, s[0:3], 1 ; C2020101 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v6, s4 ; 7E0C0204 V_MUL_F32_e64 v6, v0, v6, 0, 0, 0, 0 ; D2100006 02020D00 S_BUFFER_LOAD_DWORD s4, s[0:3], 5 ; C2020105 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v7, s4 ; 7E0E0204 V_MAD_F32 v6, v1, v7, v6, 0, 0, 0, 0 ; D2820006 041A0F01 S_BUFFER_LOAD_DWORD s4, s[0:3], 9 ; C2020109 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v7, s4 ; 7E0E0204 V_MAD_F32 v6, v2, v7, v6, 0, 0, 0, 0 ; D2820006 041A0F02 S_BUFFER_LOAD_DWORD s4, s[0:3], 13 ; C202010D S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v7, s4 ; 7E0E0204 V_MAD_F32 v6, v3, v7, v6, 0, 0, 0, 0 ; D2820006 041A0F03 S_BUFFER_LOAD_DWORD s4, s[0:3], 0 ; C2020100 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v7, s4 ; 7E0E0204 V_MUL_F32_e64 v7, v0, v7, 0, 0, 0, 0 ; D2100007 02020F00 S_BUFFER_LOAD_DWORD s4, s[0:3], 4 ; C2020104 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v8, s4 ; 7E100204 V_MAD_F32 v7, v1, v8, v7, 0, 0, 0, 0 ; D2820007 041E1101 S_BUFFER_LOAD_DWORD s4, s[0:3], 8 ; C2020108 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v8, s4 ; 7E100204 V_MAD_F32 v7, v2, v8, v7, 0, 0, 0, 0 ; D2820007 041E1102 S_BUFFER_LOAD_DWORD s0, s[0:3], 12 ; C200010C S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v8, s0 ; 7E100200 V_MAD_F32 v0, v3, v8, v7, 0, 0, 0, 0 ; D2820000 041E1103 EXP 15, 12, 0, 1, 0, v0, v6, v5, v4 ; F80008CF 04050600 S_ENDPGM ; BF810000 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %22 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %5) %23 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %5) %24 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %5) %25 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %5) %26 = call i32 @llvm.SI.packf16(float %22, float %23) %27 = bitcast i32 %26 to float %28 = call i32 @llvm.SI.packf16(float %24, float %25) %29 = bitcast i32 %28 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %27, float %29, float %27, float %29) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s9 ; BEFC0309 V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302 V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202 V_CVT_PKRTZ_F16_F32_e32 v0, v1, v0 ; 5E000101 V_INTERP_MOV_F32 v1, P0, 1, 0, [m0] ; C8060102 V_INTERP_MOV_F32 v2, P0, 0, 0, [m0] ; C80A0002 V_CVT_PKRTZ_F16_F32_e32 v1, v2, v1 ; 5E020302 EXP 15, 0, 1, 1, 1, v1, v0, v1, v0 ; F8001C0F 00010001 S_ENDPGM ; BF810000 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], COLOR, CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %22 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %5) %23 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %5) %24 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %5) %25 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %5) %26 = call i32 @llvm.SI.packf16(float %22, float %23) %27 = bitcast i32 %26 to float %28 = call i32 @llvm.SI.packf16(float %24, float %25) %29 = bitcast i32 %28 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %27, float %29, float %27, float %29) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s9 ; BEFC0309 V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302 V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202 V_CVT_PKRTZ_F16_F32_e32 v0, v1, v0 ; 5E000101 V_INTERP_MOV_F32 v1, P0, 1, 0, [m0] ; C8060102 V_INTERP_MOV_F32 v2, P0, 0, 0, [m0] ; C80A0002 V_CVT_PKRTZ_F16_F32_e32 v1, v2, v1 ; 5E020302 EXP 15, 0, 1, 1, 1, v1, v0, v1, v0 ; F8001C0F 00010001 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[0], LINEAR DCL SAMP[0] DCL OUT[0], COLOR DCL TEMP[0] 0: TEX TEMP[0], IN[0], SAMP[0], RECT 1: MOV OUT[0], TEMP[0].xxxx 2: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %22 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0 %23 = load <32 x i8> addrspace(2)* %22, !tbaa !0 %24 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0 %25 = load <16 x i8> addrspace(2)* %24, !tbaa !0 %26 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %11) %27 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %11) %28 = bitcast float %26 to i32 %29 = bitcast float %27 to i32 %30 = insertelement <2 x i32> undef, i32 %28, i32 0 %31 = insertelement <2 x i32> %30, i32 %29, i32 1 %32 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %31, <32 x i8> %23, <16 x i8> %25, i32 5) %33 = extractelement <4 x float> %32, i32 0 %34 = call i32 @llvm.SI.packf16(float %33, float %33) %35 = bitcast i32 %34 to float %36 = call i32 @llvm.SI.packf16(float %33, float %33) %37 = bitcast i32 %36 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %35, float %37, float %35, float %37) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s9 ; BEFC0309 V_INTERP_P1_F32 v3, v0, 1, 0, [m0] ; C80C0100 V_INTERP_P2_F32 v3, [v3], v1, 1, 0, [m0] ; C80D0101 V_INTERP_P1_F32 v2, v0, 0, 0, [m0] ; C8080000 V_INTERP_P2_F32 v2, [v2], v1, 0, 0, [m0] ; C8090001 S_LOAD_DWORDX4 s[0:3], s[2:3], 0 ; C0800300 S_LOAD_DWORDX8 s[4:11], s[4:5], 0 ; C0C20500 S_WAITCNT lgkmcnt(0) ; BF8C007F IMAGE_SAMPLE v0, 1, -1, 0, 0, 0, 0, 0, 0, v[2:3], s[4:11], s[0:3] ; F0801100 00010002 S_WAITCNT vmcnt(0) ; BF8C0770 V_CVT_PKRTZ_F16_F32_e32 v0, v0, v0 ; 5E000100 EXP 15, 0, 1, 1, 1, v0, v0, v0, v0 ; F8001C0F 00000000 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %22 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %5) %23 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %5) %24 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %5) %25 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %5) %26 = call i32 @llvm.SI.packf16(float %22, float %23) %27 = bitcast i32 %26 to float %28 = call i32 @llvm.SI.packf16(float %24, float %25) %29 = bitcast i32 %28 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %27, float %29, float %27, float %29) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s9 ; BEFC0309 V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302 V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202 V_CVT_PKRTZ_F16_F32_e32 v0, v1, v0 ; 5E000101 V_INTERP_MOV_F32 v1, P0, 1, 0, [m0] ; C8060102 V_INTERP_MOV_F32 v2, P0, 0, 0, [m0] ; C80A0002 V_CVT_PKRTZ_F16_F32_e32 v1, v2, v1 ; 5E020302 EXP 15, 0, 1, 1, 1, v1, v0, v1, v0 ; F8001C0F 00010001 S_ENDPGM ; BF810000 "Qt Warning - invalid keysym: dead_actute" AL lib: oss.c:169: Could not open /dev/dsp: Datei oder Verzeichnis nicht gefunden libpng warning: iCCP: Not recognizing known sRGB profile that has been edited FRAG DCL IN[0], GENERIC[0], LINEAR DCL OUT[0], COLOR DCL SAMP[0] 0: TEX OUT[0], IN[0], SAMP[0], 2D 1: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %22 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0 %23 = load <32 x i8> addrspace(2)* %22, !tbaa !0 %24 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0 %25 = load <16 x i8> addrspace(2)* %24, !tbaa !0 %26 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %11) %27 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %11) %28 = bitcast float %26 to i32 %29 = bitcast float %27 to i32 %30 = insertelement <2 x i32> undef, i32 %28, i32 0 %31 = insertelement <2 x i32> %30, i32 %29, i32 1 %32 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %31, <32 x i8> %23, <16 x i8> %25, i32 2) %33 = extractelement <4 x float> %32, i32 0 %34 = extractelement <4 x float> %32, i32 1 %35 = extractelement <4 x float> %32, i32 2 %36 = extractelement <4 x float> %32, i32 3 %37 = call i32 @llvm.SI.packf16(float %33, float %34) %38 = bitcast i32 %37 to float %39 = call i32 @llvm.SI.packf16(float %35, float %36) %40 = bitcast i32 %39 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %38, float %40, float %38, float %40) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s9 ; BEFC0309 V_INTERP_P1_F32 v3, v0, 1, 0, [m0] ; C80C0100 V_INTERP_P2_F32 v3, [v3], v1, 1, 0, [m0] ; C80D0101 V_INTERP_P1_F32 v2, v0, 0, 0, [m0] ; C8080000 V_INTERP_P2_F32 v2, [v2], v1, 0, 0, [m0] ; C8090001 S_LOAD_DWORDX4 s[0:3], s[2:3], 0 ; C0800300 S_LOAD_DWORDX8 s[4:11], s[4:5], 0 ; C0C20500 S_WAITCNT lgkmcnt(0) ; BF8C007F IMAGE_SAMPLE v[0:3], 15, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[4:11], s[0:3] ; F0800F00 00010002 S_WAITCNT vmcnt(0) ; BF8C0770 V_CVT_PKRTZ_F16_F32_e32 v4, v2, v3 ; 5E080702 V_CVT_PKRTZ_F16_F32_e32 v0, v0, v1 ; 5E000300 EXP 15, 0, 1, 1, 1, v0, v4, v0, v4 ; F8001C0F 04000400 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[0], LINEAR DCL OUT[0], COLOR DCL SAMP[0] 0: TEX OUT[0], IN[0], SAMP[0], 2D 1: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %22 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0 %23 = load <32 x i8> addrspace(2)* %22, !tbaa !0 %24 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0 %25 = load <16 x i8> addrspace(2)* %24, !tbaa !0 %26 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %11) %27 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %11) %28 = bitcast float %26 to i32 %29 = bitcast float %27 to i32 %30 = insertelement <2 x i32> undef, i32 %28, i32 0 %31 = insertelement <2 x i32> %30, i32 %29, i32 1 %32 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %31, <32 x i8> %23, <16 x i8> %25, i32 2) %33 = extractelement <4 x float> %32, i32 0 %34 = extractelement <4 x float> %32, i32 1 %35 = extractelement <4 x float> %32, i32 2 %36 = extractelement <4 x float> %32, i32 3 %37 = call i32 @llvm.SI.packf16(float %33, float %34) %38 = bitcast i32 %37 to float %39 = call i32 @llvm.SI.packf16(float %35, float %36) %40 = bitcast i32 %39 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %38, float %40, float %38, float %40) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s9 ; BEFC0309 V_INTERP_P1_F32 v3, v0, 1, 0, [m0] ; C80C0100 V_INTERP_P2_F32 v3, [v3], v1, 1, 0, [m0] ; C80D0101 V_INTERP_P1_F32 v2, v0, 0, 0, [m0] ; C8080000 V_INTERP_P2_F32 v2, [v2], v1, 0, 0, [m0] ; C8090001 S_LOAD_DWORDX4 s[0:3], s[2:3], 0 ; C0800300 S_LOAD_DWORDX8 s[4:11], s[4:5], 0 ; C0C20500 S_WAITCNT lgkmcnt(0) ; BF8C007F IMAGE_SAMPLE v[0:3], 15, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[4:11], s[0:3] ; F0800F00 00010002 S_WAITCNT vmcnt(0) ; BF8C0770 V_CVT_PKRTZ_F16_F32_e32 v4, v2, v3 ; 5E080702 V_CVT_PKRTZ_F16_F32_e32 v0, v0, v1 ; 5E000300 EXP 15, 0, 1, 1, 1, v0, v4, v0, v4 ; F8001C0F 04000400 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[20], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL SAMP[1] DCL SAMP[2] DCL CONST[3..5] DCL CONST[1][0..96] DCL CONST[2][0..68] DCL TEMP[0..6], LOCAL DCL ADDR[0] IMM[0] UINT32 {0, 256, 272, 288} IMM[1] INT32 {16, 17, 18, 19} IMM[2] UINT32 {304, 192, 208, 224} IMM[3] FLT32 { -0.8000, 0.5000, 2.0000, 1.0000} IMM[4] INT32 {12, 13, 14, 15} IMM[5] UINT32 {240, 0, 0, 0} IMM[6] FLT32 { -2.0000, 0.0000, 0.0000, 0.0000} 0: UARL ADDR[0].x, IMM[1].xxxx 1: UARL ADDR[0].x, IMM[1].xxxx 2: MOV TEMP[0], CONST[1][ADDR[0].x] 3: UARL ADDR[0].x, IMM[1].yyyy 4: UARL ADDR[0].x, IMM[1].yyyy 5: MOV TEMP[1], CONST[1][ADDR[0].x] 6: UARL ADDR[0].x, IMM[1].zzzz 7: UARL ADDR[0].x, IMM[1].zzzz 8: MOV TEMP[2], CONST[1][ADDR[0].x] 9: UARL ADDR[0].x, IMM[1].wwww 10: UARL ADDR[0].x, IMM[1].wwww 11: MOV TEMP[3], CONST[1][ADDR[0].x] 12: MUL TEMP[4], TEMP[0], IN[0].xxxx 13: MAD TEMP[4], TEMP[1], IN[0].yyyy, TEMP[4] 14: MAD TEMP[4], TEMP[2], IMM[3].xxxx, TEMP[4] 15: ADD TEMP[4], TEMP[4], TEMP[3] 16: MUL TEMP[0], TEMP[0], IN[0].xxxx 17: MAD TEMP[0], TEMP[1], IN[0].yyyy, TEMP[0] 18: MAD TEMP[0], TEMP[2], IMM[3].yyyy, TEMP[0] 19: ADD TEMP[0], TEMP[0], TEMP[3] 20: RCP TEMP[1].x, TEMP[4].wwww 21: MUL TEMP[1], TEMP[4], TEMP[1].xxxx 22: RCP TEMP[2].x, TEMP[0].wwww 23: MUL TEMP[0], TEMP[0], TEMP[2].xxxx 24: UARL ADDR[0].x, IMM[4].xxxx 25: UARL ADDR[0].x, IMM[4].xxxx 26: MOV TEMP[2], CONST[1][ADDR[0].x] 27: UARL ADDR[0].x, IMM[4].yyyy 28: UARL ADDR[0].x, IMM[4].yyyy 29: MOV TEMP[3], CONST[1][ADDR[0].x] 30: UARL ADDR[0].x, IMM[4].zzzz 31: UARL ADDR[0].x, IMM[4].zzzz 32: MOV TEMP[4], CONST[1][ADDR[0].x] 33: UARL ADDR[0].x, IMM[4].wwww 34: UARL ADDR[0].x, IMM[4].wwww 35: MOV TEMP[5], CONST[1][ADDR[0].x] 36: MUL TEMP[6], TEMP[2], TEMP[1].xxxx 37: MAD TEMP[6], TEMP[3], TEMP[1].yyyy, TEMP[6] 38: MAD TEMP[6], TEMP[4], TEMP[1].zzzz, TEMP[6] 39: MAD TEMP[1], TEMP[5], TEMP[1].wwww, TEMP[6] 40: MUL TEMP[2], TEMP[2], TEMP[0].xxxx 41: MAD TEMP[2], TEMP[3], TEMP[0].yyyy, TEMP[2] 42: MAD TEMP[2], TEMP[4], TEMP[0].zzzz, TEMP[2] 43: MAD TEMP[0], TEMP[5], TEMP[0].wwww, TEMP[2] 44: ADD TEMP[0].xyz, TEMP[0], -TEMP[1] 45: DP3 TEMP[1].x, TEMP[0].xyzz, TEMP[0].xyzz 46: RSQ TEMP[1].x, TEMP[1].xxxx 47: MUL TEMP[0].xyz, TEMP[0].xyzz, TEMP[1].xxxx 48: MUL TEMP[1].x, IMM[3].zzzz, CONST[3].xxxx 49: MUL TEMP[2].x, CONST[3].xxxx, CONST[3].xxxx 50: MOV TEMP[3].xyz, TEMP[0].xyzz 51: TEX TEMP[3], TEMP[3], SAMP[2], CUBE 52: ADD TEMP[4].x, TEMP[2].xxxx, -TEMP[1].xxxx 53: ADD TEMP[4].x, TEMP[4].xxxx, IMM[3].wwww 54: MUL TEMP[4].x, TEMP[4].xxxx, IMM[3].yyyy 55: MOV TEMP[5].xyz, TEMP[0].xyzz 56: TEX TEMP[5], TEMP[5], SAMP[1], CUBE 57: MUL TEMP[6].x, IMM[6].xxxx, CONST[3].xxxx 58: MAD TEMP[1].x, TEMP[6].xxxx, CONST[3].xxxx, TEMP[1].xxxx 59: ADD TEMP[1].x, TEMP[1].xxxx, IMM[3].wwww 60: MUL TEMP[1].x, TEMP[1].xxxx, IMM[3].yyyy 61: MOV TEMP[0].xyz, TEMP[0].xyzz 62: TEX TEMP[0], TEMP[0], SAMP[0], CUBE 63: MUL TEMP[2].x, TEMP[2].xxxx, IMM[3].yyyy 64: MUL TEMP[0], TEMP[0], TEMP[2].xxxx 65: MAD TEMP[0], TEMP[5], TEMP[1].xxxx, TEMP[0] 66: MAD TEMP[0].xyz, TEMP[3], TEMP[4].xxxx, TEMP[0] 67: MOV TEMP[0].xyz, TEMP[0].xyzx 68: MOV OUT[0], TEMP[0] 69: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %22 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0 %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0 %24 = call float @llvm.SI.load.const(<16 x i8> %23, i32 48) %25 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 1 %26 = load <16 x i8> addrspace(2)* %25, !tbaa !0 %27 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0 %28 = load <32 x i8> addrspace(2)* %27, !tbaa !0 %29 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0 %30 = load <16 x i8> addrspace(2)* %29, !tbaa !0 %31 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 1 %32 = load <32 x i8> addrspace(2)* %31, !tbaa !0 %33 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 1 %34 = load <16 x i8> addrspace(2)* %33, !tbaa !0 %35 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 2 %36 = load <32 x i8> addrspace(2)* %35, !tbaa !0 %37 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 2 %38 = load <16 x i8> addrspace(2)* %37, !tbaa !0 %39 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %7) %40 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %7) %41 = shl i32 16, 4 %42 = call float @llvm.SI.load.const(<16 x i8> %26, i32 %41) %43 = shl i32 16, 4 %44 = add i32 %43, 4 %45 = call float @llvm.SI.load.const(<16 x i8> %26, i32 %44) %46 = shl i32 16, 4 %47 = add i32 %46, 8 %48 = call float @llvm.SI.load.const(<16 x i8> %26, i32 %47) %49 = shl i32 16, 4 %50 = add i32 %49, 12 %51 = call float @llvm.SI.load.const(<16 x i8> %26, i32 %50) %52 = shl i32 17, 4 %53 = call float @llvm.SI.load.const(<16 x i8> %26, i32 %52) %54 = shl i32 17, 4 %55 = add i32 %54, 4 %56 = call float @llvm.SI.load.const(<16 x i8> %26, i32 %55) %57 = shl i32 17, 4 %58 = add i32 %57, 8 %59 = call float @llvm.SI.load.const(<16 x i8> %26, i32 %58) %60 = shl i32 17, 4 %61 = add i32 %60, 12 %62 = call float @llvm.SI.load.const(<16 x i8> %26, i32 %61) %63 = shl i32 18, 4 %64 = call float @llvm.SI.load.const(<16 x i8> %26, i32 %63) %65 = shl i32 18, 4 %66 = add i32 %65, 4 %67 = call float @llvm.SI.load.const(<16 x i8> %26, i32 %66) %68 = shl i32 18, 4 %69 = add i32 %68, 8 %70 = call float @llvm.SI.load.const(<16 x i8> %26, i32 %69) %71 = shl i32 18, 4 %72 = add i32 %71, 12 %73 = call float @llvm.SI.load.const(<16 x i8> %26, i32 %72) %74 = shl i32 19, 4 %75 = call float @llvm.SI.load.const(<16 x i8> %26, i32 %74) %76 = shl i32 19, 4 %77 = add i32 %76, 4 %78 = call float @llvm.SI.load.const(<16 x i8> %26, i32 %77) %79 = shl i32 19, 4 %80 = add i32 %79, 8 %81 = call float @llvm.SI.load.const(<16 x i8> %26, i32 %80) %82 = shl i32 19, 4 %83 = add i32 %82, 12 %84 = call float @llvm.SI.load.const(<16 x i8> %26, i32 %83) %85 = fmul float %42, %39 %86 = fmul float %45, %39 %87 = fmul float %48, %39 %88 = fmul float %51, %39 %89 = fmul float %53, %40 %90 = fadd float %89, %85 %91 = fmul float %56, %40 %92 = fadd float %91, %86 %93 = fmul float %59, %40 %94 = fadd float %93, %87 %95 = fmul float %62, %40 %96 = fadd float %95, %88 %97 = fmul float %64, 0xBFE99999A0000000 %98 = fadd float %97, %90 %99 = fmul float %67, 0xBFE99999A0000000 %100 = fadd float %99, %92 %101 = fmul float %70, 0xBFE99999A0000000 %102 = fadd float %101, %94 %103 = fmul float %73, 0xBFE99999A0000000 %104 = fadd float %103, %96 %105 = fadd float %98, %75 %106 = fadd float %100, %78 %107 = fadd float %102, %81 %108 = fadd float %104, %84 %109 = fmul float %42, %39 %110 = fmul float %45, %39 %111 = fmul float %48, %39 %112 = fmul float %51, %39 %113 = fmul float %53, %40 %114 = fadd float %113, %109 %115 = fmul float %56, %40 %116 = fadd float %115, %110 %117 = fmul float %59, %40 %118 = fadd float %117, %111 %119 = fmul float %62, %40 %120 = fadd float %119, %112 %121 = fmul float %64, 5.000000e-01 %122 = fadd float %121, %114 %123 = fmul float %67, 5.000000e-01 %124 = fadd float %123, %116 %125 = fmul float %70, 5.000000e-01 %126 = fadd float %125, %118 %127 = fmul float %73, 5.000000e-01 %128 = fadd float %127, %120 %129 = fadd float %122, %75 %130 = fadd float %124, %78 %131 = fadd float %126, %81 %132 = fadd float %128, %84 %133 = fdiv float 1.000000e+00, %108 %134 = fmul float %105, %133 %135 = fmul float %106, %133 %136 = fmul float %107, %133 %137 = fmul float %108, %133 %138 = fdiv float 1.000000e+00, %132 %139 = fmul float %129, %138 %140 = fmul float %130, %138 %141 = fmul float %131, %138 %142 = fmul float %132, %138 %143 = shl i32 12, 4 %144 = call float @llvm.SI.load.const(<16 x i8> %26, i32 %143) %145 = shl i32 12, 4 %146 = add i32 %145, 4 %147 = call float @llvm.SI.load.const(<16 x i8> %26, i32 %146) %148 = shl i32 12, 4 %149 = add i32 %148, 8 %150 = call float @llvm.SI.load.const(<16 x i8> %26, i32 %149) %151 = shl i32 12, 4 %152 = add i32 %151, 12 %153 = call float @llvm.SI.load.const(<16 x i8> %26, i32 %152) %154 = shl i32 13, 4 %155 = call float @llvm.SI.load.const(<16 x i8> %26, i32 %154) %156 = shl i32 13, 4 %157 = add i32 %156, 4 %158 = call float @llvm.SI.load.const(<16 x i8> %26, i32 %157) %159 = shl i32 13, 4 %160 = add i32 %159, 8 %161 = call float @llvm.SI.load.const(<16 x i8> %26, i32 %160) %162 = shl i32 13, 4 %163 = add i32 %162, 12 %164 = call float @llvm.SI.load.const(<16 x i8> %26, i32 %163) %165 = shl i32 14, 4 %166 = call float @llvm.SI.load.const(<16 x i8> %26, i32 %165) %167 = shl i32 14, 4 %168 = add i32 %167, 4 %169 = call float @llvm.SI.load.const(<16 x i8> %26, i32 %168) %170 = shl i32 14, 4 %171 = add i32 %170, 8 %172 = call float @llvm.SI.load.const(<16 x i8> %26, i32 %171) %173 = shl i32 14, 4 %174 = add i32 %173, 12 %175 = call float @llvm.SI.load.const(<16 x i8> %26, i32 %174) %176 = shl i32 15, 4 %177 = call float @llvm.SI.load.const(<16 x i8> %26, i32 %176) %178 = shl i32 15, 4 %179 = add i32 %178, 4 %180 = call float @llvm.SI.load.const(<16 x i8> %26, i32 %179) %181 = shl i32 15, 4 %182 = add i32 %181, 8 %183 = call float @llvm.SI.load.const(<16 x i8> %26, i32 %182) %184 = shl i32 15, 4 %185 = add i32 %184, 12 %186 = call float @llvm.SI.load.const(<16 x i8> %26, i32 %185) %187 = fmul float %144, %134 %188 = fmul float %147, %134 %189 = fmul float %150, %134 %190 = fmul float %155, %135 %191 = fadd float %190, %187 %192 = fmul float %158, %135 %193 = fadd float %192, %188 %194 = fmul float %161, %135 %195 = fadd float %194, %189 %196 = fmul float %166, %136 %197 = fadd float %196, %191 %198 = fmul float %169, %136 %199 = fadd float %198, %193 %200 = fmul float %172, %136 %201 = fadd float %200, %195 %202 = fmul float %177, %137 %203 = fadd float %202, %197 %204 = fmul float %180, %137 %205 = fadd float %204, %199 %206 = fmul float %183, %137 %207 = fadd float %206, %201 %208 = fmul float %144, %139 %209 = fmul float %147, %139 %210 = fmul float %150, %139 %211 = fmul float %153, %139 %212 = fmul float %155, %140 %213 = fadd float %212, %208 %214 = fmul float %158, %140 %215 = fadd float %214, %209 %216 = fmul float %161, %140 %217 = fadd float %216, %210 %218 = fmul float %164, %140 %219 = fadd float %218, %211 %220 = fmul float %166, %141 %221 = fadd float %220, %213 %222 = fmul float %169, %141 %223 = fadd float %222, %215 %224 = fmul float %172, %141 %225 = fadd float %224, %217 %226 = fmul float %175, %141 %227 = fadd float %226, %219 %228 = fmul float %177, %142 %229 = fadd float %228, %221 %230 = fmul float %180, %142 %231 = fadd float %230, %223 %232 = fmul float %183, %142 %233 = fadd float %232, %225 %234 = fmul float %186, %142 %235 = fadd float %234, %227 %236 = fsub float -0.000000e+00, %203 %237 = fadd float %229, %236 %238 = fsub float -0.000000e+00, %205 %239 = fadd float %231, %238 %240 = fsub float -0.000000e+00, %207 %241 = fadd float %233, %240 %242 = fmul float %237, %237 %243 = fmul float %239, %239 %244 = fadd float %243, %242 %245 = fmul float %241, %241 %246 = fadd float %244, %245 %247 = call float @llvm.AMDGPU.rsq(float %246) %248 = fmul float %237, %247 %249 = fmul float %239, %247 %250 = fmul float %241, %247 %251 = fmul float 2.000000e+00, %24 %252 = fmul float %24, %24 %253 = insertelement <4 x float> undef, float %248, i32 0 %254 = insertelement <4 x float> %253, float %249, i32 1 %255 = insertelement <4 x float> %254, float %250, i32 2 %256 = insertelement <4 x float> %255, float %164, i32 3 %257 = call <4 x float> @llvm.AMDGPU.cube(<4 x float> %256) %258 = extractelement <4 x float> %257, i32 0 %259 = extractelement <4 x float> %257, i32 1 %260 = extractelement <4 x float> %257, i32 2 %261 = extractelement <4 x float> %257, i32 3 %262 = call float @fabs(float %260) %263 = fdiv float 1.000000e+00, %262 %264 = fmul float %258, %263 %265 = fadd float %264, 1.500000e+00 %266 = fmul float %259, %263 %267 = fadd float %266, 1.500000e+00 %268 = bitcast float %267 to i32 %269 = bitcast float %265 to i32 %270 = bitcast float %261 to i32 %271 = insertelement <4 x i32> undef, i32 %268, i32 0 %272 = insertelement <4 x i32> %271, i32 %269, i32 1 %273 = insertelement <4 x i32> %272, i32 %270, i32 2 %274 = insertelement <4 x i32> %273, i32 undef, i32 3 %275 = call <4 x float> @llvm.SI.sample.v4i32(<4 x i32> %274, <32 x i8> %36, <16 x i8> %38, i32 4) %276 = extractelement <4 x float> %275, i32 0 %277 = extractelement <4 x float> %275, i32 1 %278 = extractelement <4 x float> %275, i32 2 %279 = fsub float -0.000000e+00, %251 %280 = fadd float %252, %279 %281 = fadd float %280, 1.000000e+00 %282 = fmul float %281, 5.000000e-01 %283 = insertelement <4 x float> undef, float %248, i32 0 %284 = insertelement <4 x float> %283, float %249, i32 1 %285 = insertelement <4 x float> %284, float %250, i32 2 %286 = insertelement <4 x float> %285, float %186, i32 3 %287 = call <4 x float> @llvm.AMDGPU.cube(<4 x float> %286) %288 = extractelement <4 x float> %287, i32 0 %289 = extractelement <4 x float> %287, i32 1 %290 = extractelement <4 x float> %287, i32 2 %291 = extractelement <4 x float> %287, i32 3 %292 = call float @fabs(float %290) %293 = fdiv float 1.000000e+00, %292 %294 = fmul float %288, %293 %295 = fadd float %294, 1.500000e+00 %296 = fmul float %289, %293 %297 = fadd float %296, 1.500000e+00 %298 = bitcast float %297 to i32 %299 = bitcast float %295 to i32 %300 = bitcast float %291 to i32 %301 = insertelement <4 x i32> undef, i32 %298, i32 0 %302 = insertelement <4 x i32> %301, i32 %299, i32 1 %303 = insertelement <4 x i32> %302, i32 %300, i32 2 %304 = insertelement <4 x i32> %303, i32 undef, i32 3 %305 = call <4 x float> @llvm.SI.sample.v4i32(<4 x i32> %304, <32 x i8> %32, <16 x i8> %34, i32 4) %306 = extractelement <4 x float> %305, i32 0 %307 = extractelement <4 x float> %305, i32 1 %308 = extractelement <4 x float> %305, i32 2 %309 = extractelement <4 x float> %305, i32 3 %310 = fmul float -2.000000e+00, %24 %311 = fmul float %310, %24 %312 = fadd float %311, %251 %313 = fadd float %312, 1.000000e+00 %314 = fmul float %313, 5.000000e-01 %315 = insertelement <4 x float> undef, float %248, i32 0 %316 = insertelement <4 x float> %315, float %249, i32 1 %317 = insertelement <4 x float> %316, float %250, i32 2 %318 = insertelement <4 x float> %317, float %235, i32 3 %319 = call <4 x float> @llvm.AMDGPU.cube(<4 x float> %318) %320 = extractelement <4 x float> %319, i32 0 %321 = extractelement <4 x float> %319, i32 1 %322 = extractelement <4 x float> %319, i32 2 %323 = extractelement <4 x float> %319, i32 3 %324 = call float @fabs(float %322) %325 = fdiv float 1.000000e+00, %324 %326 = fmul float %320, %325 %327 = fadd float %326, 1.500000e+00 %328 = fmul float %321, %325 %329 = fadd float %328, 1.500000e+00 %330 = bitcast float %329 to i32 %331 = bitcast float %327 to i32 %332 = bitcast float %323 to i32 %333 = insertelement <4 x i32> undef, i32 %330, i32 0 %334 = insertelement <4 x i32> %333, i32 %331, i32 1 %335 = insertelement <4 x i32> %334, i32 %332, i32 2 %336 = insertelement <4 x i32> %335, i32 undef, i32 3 %337 = call <4 x float> @llvm.SI.sample.v4i32(<4 x i32> %336, <32 x i8> %28, <16 x i8> %30, i32 4) %338 = extractelement <4 x float> %337, i32 0 %339 = extractelement <4 x float> %337, i32 1 %340 = extractelement <4 x float> %337, i32 2 %341 = extractelement <4 x float> %337, i32 3 %342 = fmul float %252, 5.000000e-01 %343 = fmul float %338, %342 %344 = fmul float %339, %342 %345 = fmul float %340, %342 %346 = fmul float %341, %342 %347 = fmul float %306, %314 %348 = fadd float %347, %343 %349 = fmul float %307, %314 %350 = fadd float %349, %344 %351 = fmul float %308, %314 %352 = fadd float %351, %345 %353 = fmul float %309, %314 %354 = fadd float %353, %346 %355 = fmul float %276, %282 %356 = fadd float %355, %348 %357 = fmul float %277, %282 %358 = fadd float %357, %350 %359 = fmul float %278, %282 %360 = fadd float %359, %352 %361 = call i32 @llvm.SI.packf16(float %356, float %358) %362 = bitcast i32 %361 to float %363 = call i32 @llvm.SI.packf16(float %360, float %354) %364 = bitcast i32 %363 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %362, float %364, float %362, float %364) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: readnone declare float @llvm.AMDGPU.rsq(float) #2 ; Function Attrs: readnone declare <4 x float> @llvm.AMDGPU.cube(<4 x float>) #2 ; Function Attrs: readnone declare float @fabs(float) #2 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.sample.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s9 ; BEFC0309 V_INTERP_P1_F32 v2, v0, 1, 0, [m0] ; C8080100 V_INTERP_P2_F32 v2, [v2], v1, 1, 0, [m0] ; C8090101 V_INTERP_P1_F32 v3, v0, 0, 0, [m0] ; C80C0000 V_INTERP_P2_F32 v3, [v3], v1, 0, 0, [m0] ; C80D0001 S_LOAD_DWORDX4 s[8:11], s[0:1], 4 ; C0840104 S_WAITCNT lgkmcnt(0) ; BF8C007F S_BUFFER_LOAD_DWORD s6, s[8:11], 65 ; C2030941 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v0, s6, v3 ; 10000606 S_BUFFER_LOAD_DWORD s6, s[8:11], 69 ; C2030945 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v0, s6, v2, v0, 0, 0, 0, 0 ; D2820000 04020406 S_BUFFER_LOAD_DWORD s6, s[8:11], 73 ; C2030949 V_MOV_B32_e32 v1, -8.000000e-01 ; 7E0202FF BF4CCCCD S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v4, s6, v1, v0, 0, 0, 0, 0 ; D2820004 04020206 S_BUFFER_LOAD_DWORD s7, s[8:11], 77 ; C203894D S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v4, s7, v4 ; 06080807 S_BUFFER_LOAD_DWORD s12, s[8:11], 67 ; C2060943 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v5, s12, v3 ; 100A060C S_BUFFER_LOAD_DWORD s12, s[8:11], 71 ; C2060947 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v5, s12, v2, v5, 0, 0, 0, 0 ; D2820005 0416040C S_BUFFER_LOAD_DWORD s12, s[8:11], 75 ; C206094B S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v6, s12, v1, v5, 0, 0, 0, 0 ; D2820006 0416020C S_BUFFER_LOAD_DWORD s13, s[8:11], 79 ; C206894F S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v6, s13, v6 ; 060C0C0D V_RCP_F32_e32 v7, v6 ; 7E0E5506 V_MUL_F32_e32 v4, v4, v7 ; 10080F04 S_BUFFER_LOAD_DWORD s14, s[8:11], 64 ; C2070940 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v8, s14, v3 ; 1010060E S_BUFFER_LOAD_DWORD s14, s[8:11], 68 ; C2070944 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v8, s14, v2, v8, 0, 0, 0, 0 ; D2820008 0422040E S_BUFFER_LOAD_DWORD s14, s[8:11], 72 ; C2070948 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v9, s14, v1, v8, 0, 0, 0, 0 ; D2820009 0422020E S_BUFFER_LOAD_DWORD s15, s[8:11], 76 ; C207894C S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v9, s15, v9 ; 0612120F V_MUL_F32_e32 v9, v9, v7 ; 10120F09 S_BUFFER_LOAD_DWORD s16, s[8:11], 49 ; C2080931 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v10, s16, v9 ; 10141210 S_BUFFER_LOAD_DWORD s17, s[8:11], 53 ; C2088935 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v10, s17, v4, v10, 0, 0, 0, 0 ; D282000A 042A0811 S_BUFFER_LOAD_DWORD s18, s[8:11], 66 ; C2090942 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v3, s18, v3 ; 10060612 S_BUFFER_LOAD_DWORD s18, s[8:11], 70 ; C2090946 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v2, s18, v2, v3, 0, 0, 0, 0 ; D2820002 040E0412 S_BUFFER_LOAD_DWORD s18, s[8:11], 74 ; C209094A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v1, s18, v1, v2, 0, 0, 0, 0 ; D2820001 040A0212 S_BUFFER_LOAD_DWORD s19, s[8:11], 78 ; C209894E S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v1, s19, v1 ; 06020213 V_MUL_F32_e32 v1, v1, v7 ; 10020F01 S_BUFFER_LOAD_DWORD s20, s[8:11], 57 ; C20A0939 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v3, s20, v1, v10, 0, 0, 0, 0 ; D2820003 042A0214 V_MUL_F32_e32 v6, v6, v7 ; 100C0F06 S_BUFFER_LOAD_DWORD s21, s[8:11], 61 ; C20A893D S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v3, s21, v6, v3, 0, 0, 0, 0 ; D2820003 040E0C15 V_MAD_F32 v0, s6, 5.000000e-01, v0, 0, 0, 0, 0 ; D2820000 0401E006 V_ADD_F32_e32 v0, s7, v0 ; 06000007 V_MAD_F32 v5, s12, 5.000000e-01, v5, 0, 0, 0, 0 ; D2820005 0415E00C V_ADD_F32_e32 v5, s13, v5 ; 060A0A0D V_RCP_F32_e32 v7, v5 ; 7E0E5505 V_MUL_F32_e32 v0, v0, v7 ; 10000F00 V_MAD_F32 v8, s14, 5.000000e-01, v8, 0, 0, 0, 0 ; D2820008 0421E00E V_ADD_F32_e32 v8, s15, v8 ; 0610100F V_MUL_F32_e32 v8, v8, v7 ; 10100F08 V_MUL_F32_e32 v10, s16, v8 ; 10141010 V_MAD_F32 v10, s17, v0, v10, 0, 0, 0, 0 ; D282000A 042A0011 V_MAD_F32 v2, s18, 5.000000e-01, v2, 0, 0, 0, 0 ; D2820002 0409E012 V_ADD_F32_e32 v2, s19, v2 ; 06040413 V_MUL_F32_e32 v2, v2, v7 ; 10040F02 V_MAD_F32 v10, s20, v2, v10, 0, 0, 0, 0 ; D282000A 042A0414 V_MUL_F32_e32 v5, v5, v7 ; 100A0F05 V_MAD_F32 v7, s21, v5, v10, 0, 0, 0, 0 ; D2820007 042A0A15 V_SUB_F32_e32 v3, v7, v3 ; 08060707 S_BUFFER_LOAD_DWORD s6, s[8:11], 48 ; C2030930 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v7, s6, v9 ; 100E1206 S_BUFFER_LOAD_DWORD s7, s[8:11], 52 ; C2038934 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v7, s7, v4, v7, 0, 0, 0, 0 ; D2820007 041E0807 S_BUFFER_LOAD_DWORD s12, s[8:11], 56 ; C2060938 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v7, s12, v1, v7, 0, 0, 0, 0 ; D2820007 041E020C S_BUFFER_LOAD_DWORD s13, s[8:11], 60 ; C206893C S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v7, s13, v6, v7, 0, 0, 0, 0 ; D2820007 041E0C0D V_MUL_F32_e32 v10, s6, v8 ; 10141006 V_MAD_F32 v10, s7, v0, v10, 0, 0, 0, 0 ; D282000A 042A0007 V_MAD_F32 v10, s12, v2, v10, 0, 0, 0, 0 ; D282000A 042A040C V_MAD_F32 v10, s13, v5, v10, 0, 0, 0, 0 ; D282000A 042A0A0D V_SUB_F32_e32 v7, v10, v7 ; 080E0F0A V_MUL_F32_e32 v10, v7, v7 ; 10140F07 V_MAD_F32 v10, v3, v3, v10, 0, 0, 0, 0 ; D282000A 042A0703 S_BUFFER_LOAD_DWORD s6, s[8:11], 50 ; C2030932 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v9, s6, v9 ; 10121206 S_BUFFER_LOAD_DWORD s7, s[8:11], 54 ; C2038936 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v4, s7, v4, v9, 0, 0, 0, 0 ; D2820004 04260807 S_BUFFER_LOAD_DWORD s12, s[8:11], 58 ; C206093A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v1, s12, v1, v4, 0, 0, 0, 0 ; D2820001 0412020C S_BUFFER_LOAD_DWORD s13, s[8:11], 62 ; C206893E S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v1, s13, v6, v1, 0, 0, 0, 0 ; D2820001 04060C0D V_MUL_F32_e32 v4, s6, v8 ; 10081006 V_MAD_F32 v4, s7, v0, v4, 0, 0, 0, 0 ; D2820004 04120007 V_MAD_F32 v4, s12, v2, v4, 0, 0, 0, 0 ; D2820004 0412040C V_MAD_F32 v4, s13, v5, v4, 0, 0, 0, 0 ; D2820004 04120A0D V_SUB_F32_e32 v1, v4, v1 ; 08020304 V_MAD_F32 v4, v1, v1, v10, 0, 0, 0, 0 ; D2820004 042A0301 V_RSQ_LEGACY_F32_e32 v4, v4 ; 7E085B04 V_MUL_F32_e32 v11, v1, v4 ; 10160901 V_MUL_F32_e32 v10, v3, v4 ; 10140903 V_MUL_F32_e32 v9, v7, v4 ; 10120907 S_BUFFER_LOAD_DWORD s6, s[8:11], 51 ; C2030933 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v1, s6, v8 ; 10021006 S_BUFFER_LOAD_DWORD s6, s[8:11], 55 ; C2030937 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v0, s6, v0, v1, 0, 0, 0, 0 ; D2820000 04060006 S_BUFFER_LOAD_DWORD s7, s[8:11], 59 ; C203893B S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v0, s7, v2, v0, 0, 0, 0, 0 ; D2820000 04020407 S_BUFFER_LOAD_DWORD s7, s[8:11], 63 ; C203893F S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v12, s7, v5, v0, 0, 0, 0, 0 ; D282000C 04020A07 V_CUBESC_F32 v1, v9, v10, v11, 0, 0, 0, 0 ; D28A0001 042E1509 V_CUBETC_F32 v0, v9, v10, v11, 0, 0, 0, 0 ; D28C0000 042E1509 V_CUBEMA_F32 v2, v9, v10, v11, 0, 0, 0, 0 ; D28E0002 042E1509 V_CUBEID_F32 v3, v9, v10, v11, 0, 0, 0, 0 ; D2880003 042E1509 V_MOV_B32_e32 v8, 2147483647 ; 7E1002FF 7FFFFFFF V_AND_B32_e32 v13, v2, v8 ; 361A1102 V_RCP_F32_e32 v13, v13 ; 7E1A550D V_MOV_B32_e32 v14, 1.500000e+00 ; 7E1C02FF 3FC00000 V_MAD_F32 v2, v0, v13, v14, 0, 0, 0, 0 ; D2820002 043A1B00 V_MAD_F32 v1, v1, v13, v14, 0, 0, 0, 0 ; D2820001 043A1B01 S_LOAD_DWORDX4 s[8:11], s[2:3], 0 ; C0840300 S_LOAD_DWORDX8 s[12:19], s[4:5], 0 ; C0C60500 S_WAITCNT lgkmcnt(0) ; BF8C007F IMAGE_SAMPLE v[0:3], 15, 0, 0, 0, 0, 0, 0, 0, v[1:4], s[12:19], s[8:11] ; F0800F00 00430001 S_LOAD_DWORDX4 s[8:11], s[0:1], 0 ; C0840100 S_WAITCNT vmcnt(0) lgkmcnt(0) ; BF8C0070 S_BUFFER_LOAD_DWORD s0, s[8:11], 12 ; C200090C S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v4, s0 ; 7E080200 V_MUL_F32_e64 v5, s0, v4, 0, 0, 0, 0 ; D2100005 02020800 V_MUL_F32_e32 v6, 5.000000e-01, v5 ; 100C0AF0 V_MUL_F32_e32 v7, v3, v6 ; 100E0D03 V_CUBESC_F32 v16, v9, v10, v11, 0, 0, 0, 0 ; D28A0010 042E1509 V_CUBETC_F32 v15, v9, v10, v11, 0, 0, 0, 0 ; D28C000F 042E1509 V_CUBEMA_F32 v17, v9, v10, v11, 0, 0, 0, 0 ; D28E0011 042E1509 V_CUBEID_F32 v18, v9, v10, v11, 0, 0, 0, 0 ; D2880012 042E1509 V_AND_B32_e32 v13, v17, v8 ; 361A1111 V_RCP_F32_e32 v13, v13 ; 7E1A550D V_MAD_F32 v17, v15, v13, v14, 0, 0, 0, 0 ; D2820011 043A1B0F V_MAD_F32 v16, v16, v13, v14, 0, 0, 0, 0 ; D2820010 043A1B10 S_LOAD_DWORDX4 s[8:11], s[2:3], 4 ; C0840304 S_LOAD_DWORDX8 s[12:19], s[4:5], 8 ; C0C60508 S_WAITCNT lgkmcnt(0) ; BF8C007F IMAGE_SAMPLE v[15:18], 15, 0, 0, 0, 0, 0, 0, 0, v[16:19], s[12:19], s[8:11] ; F0800F00 00430F10 V_ADD_F32_e64 v4, s0, v4, 0, 0, 0, 0 ; D2060004 02020800 V_MUL_F32_e64 v13, s0, -2.000000e+00, 0, 0, 0, 0 ; D210000D 0201EA00 V_MAD_F32 v13, v13, s0, v4, 0, 0, 0, 0 ; D282000D 0410010D V_ADD_F32_e32 v13, 1.000000e+00, v13 ; 061A1AF2 V_MUL_F32_e32 v13, 5.000000e-01, v13 ; 101A1AF0 S_WAITCNT vmcnt(0) ; BF8C0770 V_MAD_F32 v7, v18, v13, v7, 0, 0, 0, 0 ; D2820007 041E1B12 V_MUL_F32_e32 v19, v2, v6 ; 10260D02 V_MAD_F32 v19, v17, v13, v19, 0, 0, 0, 0 ; D2820013 044E1B11 V_MOV_B32_e32 v12, s6 ; 7E180206 V_CUBESC_F32 v21, v9, v10, v11, 0, 0, 0, 0 ; D28A0015 042E1509 V_CUBETC_F32 v20, v9, v10, v11, 0, 0, 0, 0 ; D28C0014 042E1509 V_CUBEMA_F32 v22, v9, v10, v11, 0, 0, 0, 0 ; D28E0016 042E1509 V_CUBEID_F32 v23, v9, v10, v11, 0, 0, 0, 0 ; D2880017 042E1509 V_AND_B32_e32 v8, v22, v8 ; 36101116 V_RCP_F32_e32 v8, v8 ; 7E105508 V_MAD_F32 v22, v20, v8, v14, 0, 0, 0, 0 ; D2820016 043A1114 V_MAD_F32 v21, v21, v8, v14, 0, 0, 0, 0 ; D2820015 043A1115 S_LOAD_DWORDX4 s[0:3], s[2:3], 8 ; C0800308 S_LOAD_DWORDX8 s[4:11], s[4:5], 16 ; C0C20510 S_WAITCNT lgkmcnt(0) ; BF8C007F IMAGE_SAMPLE v[8:10], 7, 0, 0, 0, 0, 0, 0, 0, v[21:24], s[4:11], s[0:3] ; F0800700 00010815 V_SUB_F32_e32 v4, v5, v4 ; 08080905 V_ADD_F32_e32 v4, 1.000000e+00, v4 ; 060808F2 V_MUL_F32_e32 v4, 5.000000e-01, v4 ; 100808F0 S_WAITCNT vmcnt(0) ; BF8C0770 V_MAD_F32 v5, v10, v4, v19, 0, 0, 0, 0 ; D2820005 044E090A V_CVT_PKRTZ_F16_F32_e32 v5, v5, v7 ; 5E0A0F05 V_MUL_F32_e32 v7, v1, v6 ; 100E0D01 V_MAD_F32 v7, v16, v13, v7, 0, 0, 0, 0 ; D2820007 041E1B10 V_MAD_F32 v7, v9, v4, v7, 0, 0, 0, 0 ; D2820007 041E0909 V_MUL_F32_e32 v0, v0, v6 ; 10000D00 V_MAD_F32 v0, v15, v13, v0, 0, 0, 0, 0 ; D2820000 04021B0F V_MAD_F32 v0, v8, v4, v0, 0, 0, 0, 0 ; D2820000 04020908 V_CVT_PKRTZ_F16_F32_e32 v0, v0, v7 ; 5E000F00 EXP 15, 0, 1, 1, 1, v0, v5, v0, v5 ; F8001C0F 05000500 S_ENDPGM ; BF810000 VERT DCL IN[0] DCL OUT[0], POSITION DCL OUT[1], GENERIC[20] DCL CONST[1][0..96] DCL CONST[2][0..68] DCL TEMP[0..1], LOCAL IMM[0] FLT32 { 1.0000, 0.0000, 0.0000, 0.0000} 0: MOV TEMP[0].w, IMM[0].xxxx 1: MOV TEMP[0].xyz, IN[0].xyzx 2: MOV TEMP[1].xy, IN[0].xyxx 3: MOV OUT[1], TEMP[1] 4: MOV OUT[0], TEMP[0] 5: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 0 %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0 %12 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %11, i32 0, i32 %6) %13 = extractelement <4 x float> %12, i32 0 %14 = extractelement <4 x float> %12, i32 1 %15 = extractelement <4 x float> %12, i32 2 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %13, float %14, float 0.000000e+00, float 0.000000e+00) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %13, float %14, float %15, float 1.000000e+00) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_LOAD_DWORDX4 s[0:3], s[8:9], 0 ; C0800900 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[0:3], s[0:3][v0] + 0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80000000 V_MOV_B32_e32 v4, 0.000000e+00 ; 7E080280 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 32, 0, 0, 0, v0, v1, v4, v4 ; F800020F 04040100 S_WAITCNT expcnt(0) ; BF8C070F V_MOV_B32_e32 v4, 1.000000e+00 ; 7E0802F2 EXP 15, 12, 0, 1, 0, v0, v1, v2, v4 ; F80008CF 04020100 S_ENDPGM ; BF810000 FRAG PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1 DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %22 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %5) %23 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %5) %24 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %5) %25 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %5) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %23, float %24, float %25) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s9 ; BEFC0309 V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302 V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202 V_INTERP_MOV_F32 v2, P0, 1, 0, [m0] ; C80A0102 V_INTERP_MOV_F32 v3, P0, 0, 0, [m0] ; C80E0002 EXP 15, 0, 0, 1, 1, v3, v2, v1, v0 ; F800180F 00010203 S_ENDPGM ; BF810000 FRAG DCL IN[0], POSITION, LINEAR DCL OUT[0], COLOR DCL SAMP[0] DCL SAMP[1] DCL CONST[2] DCL TEMP[0] DCL TEMP[1..3], LOCAL 0: MOV TEMP[0], IN[0] 1: MAD TEMP[0].y, IN[0], CONST[2].xxxx, CONST[2].yyyy 2: MOV TEMP[1].xy, TEMP[0].xyyy 3: TEX TEMP[1], TEMP[1], SAMP[0], RECT 4: MOV TEMP[2].xy, TEMP[0].xyyy 5: TEX TEMP[2].xyz, TEMP[2], SAMP[1], RECT 6: MOV_SAT TEMP[3].x, TEMP[1].wwww 7: MAD TEMP[1].xyz, TEMP[2].xyzz, TEMP[3].xxxx, TEMP[1].xyzz 8: MOV OUT[0], TEMP[1] 9: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %22 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0 %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0 %24 = call float @llvm.SI.load.const(<16 x i8> %23, i32 32) %25 = call float @llvm.SI.load.const(<16 x i8> %23, i32 36) %26 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0 %27 = load <32 x i8> addrspace(2)* %26, !tbaa !0 %28 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0 %29 = load <16 x i8> addrspace(2)* %28, !tbaa !0 %30 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 1 %31 = load <32 x i8> addrspace(2)* %30, !tbaa !0 %32 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 1 %33 = load <16 x i8> addrspace(2)* %32, !tbaa !0 %34 = fmul float %15, %24 %35 = fadd float %34, %25 %36 = bitcast float %14 to i32 %37 = bitcast float %35 to i32 %38 = insertelement <2 x i32> undef, i32 %36, i32 0 %39 = insertelement <2 x i32> %38, i32 %37, i32 1 %40 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %39, <32 x i8> %27, <16 x i8> %29, i32 5) %41 = extractelement <4 x float> %40, i32 0 %42 = extractelement <4 x float> %40, i32 1 %43 = extractelement <4 x float> %40, i32 2 %44 = extractelement <4 x float> %40, i32 3 %45 = bitcast float %14 to i32 %46 = bitcast float %35 to i32 %47 = insertelement <2 x i32> undef, i32 %45, i32 0 %48 = insertelement <2 x i32> %47, i32 %46, i32 1 %49 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %48, <32 x i8> %31, <16 x i8> %33, i32 5) %50 = extractelement <4 x float> %49, i32 0 %51 = extractelement <4 x float> %49, i32 1 %52 = extractelement <4 x float> %49, i32 2 %53 = call float @llvm.AMDIL.clamp.(float %44, float 0.000000e+00, float 1.000000e+00) %54 = fmul float %50, %53 %55 = fadd float %54, %41 %56 = fmul float %51, %53 %57 = fadd float %56, %42 %58 = fmul float %52, %53 %59 = fadd float %58, %43 %60 = call i32 @llvm.SI.packf16(float %55, float %57) %61 = bitcast i32 %60 to float %62 = call i32 @llvm.SI.packf16(float %59, float %44) %63 = bitcast i32 %62 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %61, float %63, float %61, float %63) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1 ; Function Attrs: readnone declare float @llvm.AMDIL.clamp.(float, float, float) #2 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: V_MOV_B32_e32 v0, v2 ; 7E000302 S_LOAD_DWORDX4 s[8:11], s[0:1], 0 ; C0840100 S_WAITCNT lgkmcnt(0) ; BF8C007F S_BUFFER_LOAD_DWORD s0, s[8:11], 8 ; C2000908 S_BUFFER_LOAD_DWORD s1, s[8:11], 9 ; C2008909 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v2, s1 ; 7E040201 V_MAD_F32 v1, v3, s0, v2, 0, 0, 0, 0 ; D2820001 04080103 S_LOAD_DWORDX4 s[8:11], s[2:3], 4 ; C0840304 S_LOAD_DWORDX8 s[12:19], s[4:5], 8 ; C0C60508 S_WAITCNT lgkmcnt(0) ; BF8C007F IMAGE_SAMPLE v[2:4], 7, -1, 0, 0, 0, 0, 0, 0, v[0:1], s[12:19], s[8:11] ; F0801700 00430200 S_LOAD_DWORDX4 s[0:3], s[2:3], 0 ; C0800300 S_LOAD_DWORDX8 s[4:11], s[4:5], 0 ; C0C20500 S_WAITCNT vmcnt(0) lgkmcnt(0) ; BF8C0070 IMAGE_SAMPLE v[5:8], 15, -1, 0, 0, 0, 0, 0, 0, v[0:1], s[4:11], s[0:3] ; F0801F00 00010500 S_WAITCNT vmcnt(0) ; BF8C0770 V_ADD_F32_e64 v0, 0, v8, 0, 1, 0, 0 ; D2060800 02021080 V_MAD_F32 v1, v3, v0, v6, 0, 0, 0, 0 ; D2820001 041A0103 V_MAD_F32 v9, v2, v0, v5, 0, 0, 0, 0 ; D2820009 04160102 V_CVT_PKRTZ_F16_F32_e32 v1, v9, v1 ; 5E020309 V_MAD_F32 v0, v4, v0, v7, 0, 0, 0, 0 ; D2820000 041E0104 V_CVT_PKRTZ_F16_F32_e32 v0, v0, v8 ; 5E001100 EXP 15, 0, 1, 1, 1, v1, v0, v1, v0 ; F8001C0F 00010001 S_ENDPGM ; BF810000 VERT DCL IN[0] DCL OUT[0], POSITION DCL TEMP[0], LOCAL IMM[0] FLT32 { 1.0000, 0.0000, 0.0000, 0.0000} 0: MOV TEMP[0].w, IMM[0].xxxx 1: MOV TEMP[0].xyz, IN[0].xyzx 2: MOV OUT[0], TEMP[0] 3: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 0 %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0 %12 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %11, i32 0, i32 %6) %13 = extractelement <4 x float> %12, i32 0 %14 = extractelement <4 x float> %12, i32 1 %15 = extractelement <4 x float> %12, i32 2 call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %13, float %14, float %15, float 1.000000e+00) ret void } ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_LOAD_DWORDX4 s[0:3], s[8:9], 0 ; C0800900 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[0:3], s[0:3][v0] + 0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80000000 V_MOV_B32_e32 v4, 1.000000e+00 ; 7E0802F2 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 12, 0, 1, 0, v0, v1, v2, v4 ; F80008CF 04020100 S_ENDPGM ; BF810000 FRAG DCL IN[0], POSITION, LINEAR DCL OUT[0], COLOR DCL SAMP[0] DCL SAMP[1] DCL CONST[10] DCL CONST[0..7] DCL CONST[1][0..96] DCL CONST[2][0..68] DCL TEMP[0] DCL TEMP[1..37], LOCAL DCL ADDR[0] IMM[0] FLT32 { 0.0000, 0.5000, 2.0000, 10.0000} IMM[1] UINT32 {1, 192, 0, 160} IMM[2] INT32 {12, 10, 9, 8} IMM[3] UINT32 {144, 128, 352, 208} IMM[4] INT32 {22, 13, 0, 1} IMM[5] FLT32 { 100.0000, 1.3000, 1.0000, -1.0000} IMM[6] FLT32 { 0.7000, 0.0010, 2.2000, 35.0000} 0: MOV TEMP[0], IN[0] 1: MAD TEMP[0].y, IN[0], CONST[10].xxxx, CONST[10].yyyy 2: MOV TEMP[1].xyz, IMM[0].xxxx 3: UARL ADDR[0].x, IMM[2].xxxx 4: UARL ADDR[0].x, IMM[2].xxxx 5: MOV TEMP[2].xyz, CONST[2][ADDR[0].x].xyzz 6: UARL ADDR[0].x, IMM[2].yyyy 7: MOV TEMP[3], CONST[1][ADDR[0].x] 8: UARL ADDR[0].x, IMM[2].zzzz 9: MOV TEMP[4], CONST[1][ADDR[0].x] 10: UARL ADDR[0].x, IMM[2].wwww 11: MOV TEMP[5], CONST[1][ADDR[0].x] 12: MUL TEMP[5], TEMP[5], TEMP[2].xxxx 13: MAD TEMP[4], TEMP[4], TEMP[2].yyyy, TEMP[5] 14: MAD TEMP[2], TEMP[3], TEMP[2].zzzz, TEMP[4] 15: MOV TEMP[3], TEMP[2] 16: FSLT TEMP[4].x, IMM[0].xxxx, TEMP[2].zzzz 17: UIF TEMP[4].xxxx :2 18: RCP TEMP[4].x, TEMP[2].wwww 19: MUL TEMP[3], TEMP[2], TEMP[4].xxxx 20: MAD TEMP[2].xy, TEMP[3].xyyy, IMM[0].yyyy, IMM[0].yyyy 21: UARL ADDR[0].x, IMM[4].xxxx 22: MOV TEMP[4].xy, CONST[1][ADDR[0].x].xyyy 23: MUL TEMP[2].xy, TEMP[2].xyyy, TEMP[4].xyyy 24: MUL TEMP[3].xy, TEMP[2].xyyy, IMM[0].yyyy 25: FSLT TEMP[2].x, IMM[0].xxxx, CONST[7].xxxx 26: UIF TEMP[2].xxxx :2 27: MOV TEMP[2].xy, TEMP[3].xyxx 28: MOV TEMP[4].xy, TEMP[0].xyxx 29: ADD TEMP[5].xy, TEMP[0].xyyy, -TEMP[3].xyyy 30: MUL TEMP[6].xy, TEMP[0].xyyy, IMM[0].zzzz 31: UARL ADDR[0].x, IMM[4].yyyy 32: MOV TEMP[7].xyz, CONST[2][ADDR[0].x].xyzz 33: DP2 TEMP[5].x, TEMP[5].xyyy, TEMP[5].xyyy 34: RSQ TEMP[8].x, TEMP[5].xxxx 35: MUL TEMP[8].x, TEMP[8].xxxx, TEMP[5].xxxx 36: CMP TEMP[8].x, -TEMP[5].xxxx, TEMP[8].xxxx, IMM[0].xxxx 37: ADD TEMP[5].x, TEMP[8].xxxx, IMM[5].xxxx 38: POW TEMP[5].x, TEMP[5].xxxx, IMM[5].yyyy 39: ADD TEMP[5].x, IMM[5].xxxx, TEMP[5].xxxx 40: RCP TEMP[5].x, TEMP[5].xxxx 41: MUL TEMP[5].x, IMM[0].wwww, TEMP[5].xxxx 42: ADD TEMP[8].xy, TEMP[6].xyyy, IMM[5].zzzz 43: MOV TEMP[8].xy, TEMP[8].xyyy 44: TEX TEMP[8], TEMP[8], SAMP[1], RECT 45: FSEQ TEMP[8].x, TEMP[8].xxxx, IMM[5].zzzz 46: AND TEMP[8].x, TEMP[8].xxxx, IMM[5].zzzz 47: MUL TEMP[5].x, TEMP[5].xxxx, TEMP[8].xxxx 48: MUL TEMP[5].xyz, TEMP[7].xyzz, TEMP[5].xxxx 49: ADD TEMP[6].xy, TEMP[6].xyyy, IMM[5].zzzz 50: MOV TEMP[6].xy, TEMP[6].xyyy 51: TEX TEMP[6], TEMP[6], SAMP[0], RECT 52: MOV_SAT TEMP[6].x, TEMP[6].wwww 53: MUL TEMP[5].xyz, TEMP[5].xyzz, TEMP[6].xxxx 54: MOV TEMP[6].x, IMM[4].zzzz 55: BGNLOOP :2 56: ISGE TEMP[7].x, TEMP[6].xxxx, CONST[6].xxxx 57: UIF TEMP[7].xxxx :2 58: BRK 59: ENDIF 60: I2F TEMP[8].x, TEMP[6].xxxx 61: I2F TEMP[9].x, CONST[6].xxxx 62: ADD TEMP[10].x, TEMP[9].xxxx, IMM[5].wwww 63: RCP TEMP[11].x, TEMP[10].xxxx 64: MUL TEMP[12].x, TEMP[8].xxxx, TEMP[11].xxxx 65: MUL TEMP[13].x, TEMP[12].xxxx, TEMP[12].xxxx 66: ADD TEMP[14].xy, TEMP[2].xyyy, -TEMP[0].xyyy 67: MUL TEMP[15].xy, TEMP[13].xxxx, TEMP[14].xyyy 68: MUL TEMP[16].xy, TEMP[15].xyyy, CONST[3].xxxx 69: MAD TEMP[4].xy, TEMP[16].xyyy, IMM[6].xxxx, TEMP[0].xyyy 70: ADD TEMP[17].xy, TEMP[0].xyyy, -TEMP[2].xyyy 71: UARL ADDR[0].x, IMM[4].yyyy 72: MOV TEMP[18].xyz, CONST[2][ADDR[0].x].xyzz 73: DP2 TEMP[19].x, TEMP[17].xyyy, TEMP[17].xyyy 74: RSQ TEMP[20].x, TEMP[19].xxxx 75: MUL TEMP[20].x, TEMP[20].xxxx, TEMP[19].xxxx 76: CMP TEMP[20].x, -TEMP[19].xxxx, TEMP[20].xxxx, IMM[0].xxxx 77: ADD TEMP[21].x, TEMP[20].xxxx, IMM[5].xxxx 78: POW TEMP[22].x, TEMP[21].xxxx, IMM[5].yyyy 79: ADD TEMP[23].x, IMM[5].xxxx, TEMP[22].xxxx 80: RCP TEMP[24].x, TEMP[23].xxxx 81: MUL TEMP[25].x, IMM[0].wwww, TEMP[24].xxxx 82: MAD TEMP[26].xy, TEMP[4].xyyy, IMM[0].zzzz, IMM[5].zzzz 83: MOV TEMP[27].xy, TEMP[26].xyyy 84: TEX TEMP[28], TEMP[27], SAMP[1], RECT 85: FSEQ TEMP[29].x, TEMP[28].xxxx, IMM[5].zzzz 86: AND TEMP[30].x, TEMP[29].xxxx, IMM[5].zzzz 87: MUL TEMP[31].x, TEMP[25].xxxx, TEMP[30].xxxx 88: MUL TEMP[32].xyz, TEMP[18].xyzz, TEMP[31].xxxx 89: MAD TEMP[33].xy, TEMP[4].xyyy, IMM[0].zzzz, IMM[5].zzzz 90: MOV TEMP[34].xy, TEMP[33].xyyy 91: TEX TEMP[35], TEMP[34], SAMP[0], RECT 92: MOV_SAT TEMP[36].x, TEMP[35].wwww 93: MUL TEMP[37].xyz, TEMP[32].xyzz, TEMP[36].xxxx 94: MAD TEMP[5].xyz, TEMP[37].xyzz, CONST[4].xxxx, TEMP[5].xyzz 95: UADD TEMP[6].x, TEMP[6].xxxx, IMM[4].wwww 96: ENDLOOP :2 97: I2F TEMP[2].x, CONST[6].xxxx 98: RCP TEMP[2].x, TEMP[2].xxxx 99: MUL TEMP[2].x, CONST[5].xxxx, TEMP[2].xxxx 100: MUL TEMP[2].xyz, TEMP[5].xyzz, TEMP[2].xxxx 101: MAX TEMP[2].xyz, IMM[6].yyyy, TEMP[2].xyzz 102: POW TEMP[4].x, TEMP[2].xxxx, IMM[6].zzzz 103: POW TEMP[4].y, TEMP[2].yyyy, IMM[6].zzzz 104: POW TEMP[4].z, TEMP[2].zzzz, IMM[6].zzzz 105: MOV TEMP[1].xyz, TEMP[4].xyzx 106: ELSE :2 107: ADD TEMP[2].xy, TEMP[0].xyyy, -TEMP[3].xyyy 108: MUL TEMP[3].xy, TEMP[0].xyyy, IMM[0].zzzz 109: UARL ADDR[0].x, IMM[4].yyyy 110: MOV TEMP[4].xyz, CONST[2][ADDR[0].x].xyzz 111: ADD TEMP[5].xy, TEMP[3].xyyy, IMM[5].zzzz 112: MOV TEMP[5].xy, TEMP[5].xyyy 113: TEX TEMP[5].x, TEMP[5], SAMP[1], RECT 114: FSEQ TEMP[5].x, TEMP[5].xxxx, IMM[5].zzzz 115: AND TEMP[5].x, TEMP[5].xxxx, IMM[5].zzzz 116: MUL TEMP[5].x, IMM[6].wwww, TEMP[5].xxxx 117: MUL TEMP[4].xyz, TEMP[4].xyzz, TEMP[5].xxxx 118: ADD TEMP[3].xy, TEMP[3].xyyy, IMM[5].zzzz 119: MOV TEMP[3].xy, TEMP[3].xyyy 120: TEX TEMP[3].w, TEMP[3], SAMP[0], RECT 121: MOV_SAT TEMP[3].x, TEMP[3].wwww 122: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[3].xxxx 123: DP2 TEMP[2].x, TEMP[2].xyyy, TEMP[2].xyyy 124: RSQ TEMP[4].x, TEMP[2].xxxx 125: MUL TEMP[4].x, TEMP[4].xxxx, TEMP[2].xxxx 126: CMP TEMP[4].x, -TEMP[2].xxxx, TEMP[4].xxxx, IMM[0].xxxx 127: ADD TEMP[2].x, TEMP[4].xxxx, IMM[5].xxxx 128: POW TEMP[2].x, TEMP[2].xxxx, IMM[5].yyyy 129: ADD TEMP[2].x, IMM[5].xxxx, TEMP[2].xxxx 130: RCP TEMP[2].x, TEMP[2].xxxx 131: MAD TEMP[1].xyz, TEMP[3].xyzz, TEMP[2].xxxx, TEMP[1].xyzz 132: ENDIF 133: ENDIF 134: MOV OUT[0].xyz, TEMP[1].xyzx 135: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %22 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0 %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0 %24 = call float @llvm.SI.load.const(<16 x i8> %23, i32 48) %25 = call float @llvm.SI.load.const(<16 x i8> %23, i32 64) %26 = call float @llvm.SI.load.const(<16 x i8> %23, i32 80) %27 = call float @llvm.SI.load.const(<16 x i8> %23, i32 96) %28 = call float @llvm.SI.load.const(<16 x i8> %23, i32 112) %29 = call float @llvm.SI.load.const(<16 x i8> %23, i32 160) %30 = call float @llvm.SI.load.const(<16 x i8> %23, i32 164) %31 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 1 %32 = load <16 x i8> addrspace(2)* %31, !tbaa !0 %33 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 2 %34 = load <16 x i8> addrspace(2)* %33, !tbaa !0 %35 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0 %36 = load <32 x i8> addrspace(2)* %35, !tbaa !0 %37 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0 %38 = load <16 x i8> addrspace(2)* %37, !tbaa !0 %39 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 1 %40 = load <32 x i8> addrspace(2)* %39, !tbaa !0 %41 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 1 %42 = load <16 x i8> addrspace(2)* %41, !tbaa !0 %43 = fmul float %15, %29 %44 = fadd float %43, %30 %45 = shl i32 12, 4 %46 = call float @llvm.SI.load.const(<16 x i8> %34, i32 %45) %47 = shl i32 12, 4 %48 = add i32 %47, 4 %49 = call float @llvm.SI.load.const(<16 x i8> %34, i32 %48) %50 = shl i32 12, 4 %51 = add i32 %50, 8 %52 = call float @llvm.SI.load.const(<16 x i8> %34, i32 %51) %53 = shl i32 10, 4 %54 = call float @llvm.SI.load.const(<16 x i8> %32, i32 %53) %55 = shl i32 10, 4 %56 = add i32 %55, 4 %57 = call float @llvm.SI.load.const(<16 x i8> %32, i32 %56) %58 = shl i32 10, 4 %59 = add i32 %58, 8 %60 = call float @llvm.SI.load.const(<16 x i8> %32, i32 %59) %61 = shl i32 10, 4 %62 = add i32 %61, 12 %63 = call float @llvm.SI.load.const(<16 x i8> %32, i32 %62) %64 = shl i32 9, 4 %65 = call float @llvm.SI.load.const(<16 x i8> %32, i32 %64) %66 = shl i32 9, 4 %67 = add i32 %66, 4 %68 = call float @llvm.SI.load.const(<16 x i8> %32, i32 %67) %69 = shl i32 9, 4 %70 = add i32 %69, 8 %71 = call float @llvm.SI.load.const(<16 x i8> %32, i32 %70) %72 = shl i32 9, 4 %73 = add i32 %72, 12 %74 = call float @llvm.SI.load.const(<16 x i8> %32, i32 %73) %75 = shl i32 8, 4 %76 = call float @llvm.SI.load.const(<16 x i8> %32, i32 %75) %77 = shl i32 8, 4 %78 = add i32 %77, 4 %79 = call float @llvm.SI.load.const(<16 x i8> %32, i32 %78) %80 = shl i32 8, 4 %81 = add i32 %80, 8 %82 = call float @llvm.SI.load.const(<16 x i8> %32, i32 %81) %83 = shl i32 8, 4 %84 = add i32 %83, 12 %85 = call float @llvm.SI.load.const(<16 x i8> %32, i32 %84) %86 = fmul float %76, %46 %87 = fmul float %79, %46 %88 = fmul float %82, %46 %89 = fmul float %85, %46 %90 = fmul float %65, %49 %91 = fadd float %90, %86 %92 = fmul float %68, %49 %93 = fadd float %92, %87 %94 = fmul float %71, %49 %95 = fadd float %94, %88 %96 = fmul float %74, %49 %97 = fadd float %96, %89 %98 = fmul float %54, %52 %99 = fadd float %98, %91 %100 = fmul float %57, %52 %101 = fadd float %100, %93 %102 = fmul float %60, %52 %103 = fadd float %102, %95 %104 = fmul float %63, %52 %105 = fadd float %104, %97 %106 = fcmp olt float 0.000000e+00, %103 %107 = sext i1 %106 to i32 %108 = bitcast i32 %107 to float %109 = bitcast float %108 to i32 %110 = icmp ne i32 %109, 0 br i1 %110, label %IF, label %ENDIF IF: ; preds = %main_body %111 = fdiv float 1.000000e+00, %105 %112 = fmul float %99, %111 %113 = fmul float %101, %111 %114 = fmul float %112, 5.000000e-01 %115 = fadd float %114, 5.000000e-01 %116 = fmul float %113, 5.000000e-01 %117 = fadd float %116, 5.000000e-01 %118 = shl i32 22, 4 %119 = call float @llvm.SI.load.const(<16 x i8> %32, i32 %118) %120 = shl i32 22, 4 %121 = add i32 %120, 4 %122 = call float @llvm.SI.load.const(<16 x i8> %32, i32 %121) %123 = fmul float %115, %119 %124 = fmul float %117, %122 %125 = fmul float %123, 5.000000e-01 %126 = fmul float %124, 5.000000e-01 %127 = fcmp olt float 0.000000e+00, %28 %128 = sext i1 %127 to i32 %129 = bitcast i32 %128 to float %130 = bitcast float %129 to i32 %131 = icmp ne i32 %130, 0 %132 = fsub float -0.000000e+00, %125 %133 = fadd float %14, %132 %134 = fsub float -0.000000e+00, %126 %135 = fadd float %44, %134 %136 = fmul float %14, 2.000000e+00 %137 = fmul float %44, 2.000000e+00 %138 = shl i32 13, 4 %139 = call float @llvm.SI.load.const(<16 x i8> %34, i32 %138) %140 = shl i32 13, 4 %141 = add i32 %140, 4 %142 = call float @llvm.SI.load.const(<16 x i8> %34, i32 %141) %143 = shl i32 13, 4 %144 = add i32 %143, 8 %145 = call float @llvm.SI.load.const(<16 x i8> %34, i32 %144) br i1 %131, label %IF169, label %ELSE170 ENDIF: ; preds = %IF175, %ELSE170, %main_body %temp6.0 = phi float [ 0.000000e+00, %main_body ], [ %277, %IF175 ], [ %255, %ELSE170 ] %temp5.0 = phi float [ 0.000000e+00, %main_body ], [ %276, %IF175 ], [ %253, %ELSE170 ] %temp4.0 = phi float [ 0.000000e+00, %main_body ], [ %275, %IF175 ], [ %251, %ELSE170 ] %146 = call i32 @llvm.SI.packf16(float %temp4.0, float %temp5.0) %147 = bitcast i32 %146 to float %148 = call i32 @llvm.SI.packf16(float %temp6.0, float 0.000000e+00) %149 = bitcast i32 %148 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %147, float %149, float %147, float %149) ret void IF169: ; preds = %IF %150 = fmul float %133, %133 %151 = fmul float %135, %135 %152 = fadd float %150, %151 %153 = call float @llvm.AMDGPU.rsq(float %152) %154 = fmul float %153, %152 %155 = fsub float -0.000000e+00, %152 %156 = call float @llvm.AMDGPU.cndlt(float %155, float %154, float 0.000000e+00) %157 = fadd float %156, 1.000000e+02 %158 = call float @llvm.pow.f32(float %157, float 0x3FF4CCCCC0000000) %159 = fadd float 1.000000e+02, %158 %160 = fdiv float 1.000000e+00, %159 %161 = fmul float 1.000000e+01, %160 %162 = fadd float %136, 1.000000e+00 %163 = fadd float %137, 1.000000e+00 %164 = bitcast float %162 to i32 %165 = bitcast float %163 to i32 %166 = insertelement <2 x i32> undef, i32 %164, i32 0 %167 = insertelement <2 x i32> %166, i32 %165, i32 1 %168 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %167, <32 x i8> %40, <16 x i8> %42, i32 5) %169 = extractelement <4 x float> %168, i32 0 %170 = fcmp oeq float %169, 1.000000e+00 %171 = sext i1 %170 to i32 %172 = bitcast i32 %171 to float %173 = bitcast float %172 to i32 %174 = and i32 %173, 1065353216 %175 = bitcast i32 %174 to float %176 = fmul float %161, %175 %177 = fmul float %139, %176 %178 = fmul float %142, %176 %179 = fmul float %145, %176 %180 = fadd float %136, 1.000000e+00 %181 = fadd float %137, 1.000000e+00 %182 = bitcast float %180 to i32 %183 = bitcast float %181 to i32 %184 = insertelement <2 x i32> undef, i32 %182, i32 0 %185 = insertelement <2 x i32> %184, i32 %183, i32 1 %186 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %185, <32 x i8> %36, <16 x i8> %38, i32 5) %187 = extractelement <4 x float> %186, i32 3 %188 = call float @llvm.AMDIL.clamp.(float %187, float 0.000000e+00, float 1.000000e+00) %189 = fmul float %177, %188 %190 = fmul float %178, %188 %191 = fmul float %179, %188 %192 = bitcast float %27 to i32 %193 = bitcast float %27 to i32 %194 = sitofp i32 %193 to float %195 = fadd float %194, -1.000000e+00 %196 = fdiv float 1.000000e+00, %195 %197 = fsub float -0.000000e+00, %14 %198 = fadd float %125, %197 %199 = fsub float -0.000000e+00, %44 %200 = fadd float %126, %199 %201 = fsub float -0.000000e+00, %125 %202 = fadd float %14, %201 %203 = fsub float -0.000000e+00, %126 %204 = fadd float %44, %203 %205 = fmul float %202, %202 %206 = fmul float %204, %204 %207 = fadd float %205, %206 %208 = fsub float -0.000000e+00, %207 br label %LOOP ELSE170: ; preds = %IF %209 = fadd float %136, 1.000000e+00 %210 = fadd float %137, 1.000000e+00 %211 = bitcast float %209 to i32 %212 = bitcast float %210 to i32 %213 = insertelement <2 x i32> undef, i32 %211, i32 0 %214 = insertelement <2 x i32> %213, i32 %212, i32 1 %215 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %214, <32 x i8> %40, <16 x i8> %42, i32 5) %216 = extractelement <4 x float> %215, i32 0 %217 = fcmp oeq float %216, 1.000000e+00 %218 = sext i1 %217 to i32 %219 = bitcast i32 %218 to float %220 = bitcast float %219 to i32 %221 = and i32 %220, 1065353216 %222 = bitcast i32 %221 to float %223 = fmul float 3.500000e+01, %222 %224 = fmul float %139, %223 %225 = fmul float %142, %223 %226 = fmul float %145, %223 %227 = fadd float %136, 1.000000e+00 %228 = fadd float %137, 1.000000e+00 %229 = bitcast float %227 to i32 %230 = bitcast float %228 to i32 %231 = insertelement <2 x i32> undef, i32 %229, i32 0 %232 = insertelement <2 x i32> %231, i32 %230, i32 1 %233 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %232, <32 x i8> %36, <16 x i8> %38, i32 5) %234 = extractelement <4 x float> %233, i32 3 %235 = call float @llvm.AMDIL.clamp.(float %234, float 0.000000e+00, float 1.000000e+00) %236 = fmul float %224, %235 %237 = fmul float %225, %235 %238 = fmul float %226, %235 %239 = fmul float %133, %133 %240 = fmul float %135, %135 %241 = fadd float %239, %240 %242 = call float @llvm.AMDGPU.rsq(float %241) %243 = fmul float %242, %241 %244 = fsub float -0.000000e+00, %241 %245 = call float @llvm.AMDGPU.cndlt(float %244, float %243, float 0.000000e+00) %246 = fadd float %245, 1.000000e+02 %247 = call float @llvm.pow.f32(float %246, float 0x3FF4CCCCC0000000) %248 = fadd float 1.000000e+02, %247 %249 = fdiv float 1.000000e+00, %248 %250 = fmul float %236, %249 %251 = fadd float %250, 0.000000e+00 %252 = fmul float %237, %249 %253 = fadd float %252, 0.000000e+00 %254 = fmul float %238, %249 %255 = fadd float %254, 0.000000e+00 br label %ENDIF LOOP: ; preds = %ENDIF174, %IF169 %temp24.0 = phi float [ 0.000000e+00, %IF169 ], [ %343, %ENDIF174 ] %temp22.0 = phi float [ %191, %IF169 ], [ %340, %ENDIF174 ] %temp21.0 = phi float [ %190, %IF169 ], [ %338, %ENDIF174 ] %temp20.0 = phi float [ %189, %IF169 ], [ %336, %ENDIF174 ] %256 = bitcast float %temp24.0 to i32 %257 = icmp sge i32 %256, %192 %258 = sext i1 %257 to i32 %259 = bitcast i32 %258 to float %260 = bitcast float %259 to i32 %261 = icmp ne i32 %260, 0 br i1 %261, label %IF175, label %ENDIF174 IF175: ; preds = %LOOP %temp20.0.lcssa = phi float [ %temp20.0, %LOOP ] %temp21.0.lcssa = phi float [ %temp21.0, %LOOP ] %temp22.0.lcssa = phi float [ %temp22.0, %LOOP ] %262 = bitcast float %27 to i32 %263 = sitofp i32 %262 to float %264 = fdiv float 1.000000e+00, %263 %265 = fmul float %26, %264 %266 = fmul float %temp20.0.lcssa, %265 %267 = fmul float %temp21.0.lcssa, %265 %268 = fmul float %temp22.0.lcssa, %265 %269 = fcmp uge float 0x3F50624DE0000000, %266 %270 = select i1 %269, float 0x3F50624DE0000000, float %266 %271 = fcmp uge float 0x3F50624DE0000000, %267 %272 = select i1 %271, float 0x3F50624DE0000000, float %267 %273 = fcmp uge float 0x3F50624DE0000000, %268 %274 = select i1 %273, float 0x3F50624DE0000000, float %268 %275 = call float @llvm.pow.f32(float %270, float 0x40019999A0000000) %276 = call float @llvm.pow.f32(float %272, float 0x40019999A0000000) %277 = call float @llvm.pow.f32(float %274, float 0x40019999A0000000) br label %ENDIF ENDIF174: ; preds = %LOOP %278 = bitcast float %temp24.0 to i32 %279 = sitofp i32 %278 to float %280 = fmul float %279, %196 %281 = fmul float %280, %280 %282 = fmul float %281, %198 %283 = fmul float %281, %200 %284 = fmul float %282, %24 %285 = fmul float %283, %24 %286 = fmul float %284, 0x3FE6666660000000 %287 = fadd float %286, %14 %288 = fmul float %285, 0x3FE6666660000000 %289 = fadd float %288, %44 %290 = call float @llvm.SI.load.const(<16 x i8> %34, i32 208) %291 = call float @llvm.SI.load.const(<16 x i8> %34, i32 212) %292 = call float @llvm.SI.load.const(<16 x i8> %34, i32 216) %293 = call float @llvm.AMDGPU.rsq(float %207) %294 = fmul float %293, %207 %295 = call float @llvm.AMDGPU.cndlt(float %208, float %294, float 0.000000e+00) %296 = fadd float %295, 1.000000e+02 %297 = call float @llvm.pow.f32(float %296, float 0x3FF4CCCCC0000000) %298 = fadd float 1.000000e+02, %297 %299 = fdiv float 1.000000e+00, %298 %300 = fmul float 1.000000e+01, %299 %301 = fmul float %287, 2.000000e+00 %302 = fadd float %301, 1.000000e+00 %303 = fmul float %289, 2.000000e+00 %304 = fadd float %303, 1.000000e+00 %305 = bitcast float %302 to i32 %306 = bitcast float %304 to i32 %307 = insertelement <2 x i32> undef, i32 %305, i32 0 %308 = insertelement <2 x i32> %307, i32 %306, i32 1 %309 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %308, <32 x i8> %40, <16 x i8> %42, i32 5) %310 = extractelement <4 x float> %309, i32 0 %311 = fcmp oeq float %310, 1.000000e+00 %312 = sext i1 %311 to i32 %313 = bitcast i32 %312 to float %314 = bitcast float %313 to i32 %315 = and i32 %314, 1065353216 %316 = bitcast i32 %315 to float %317 = fmul float %300, %316 %318 = fmul float %290, %317 %319 = fmul float %291, %317 %320 = fmul float %292, %317 %321 = fmul float %287, 2.000000e+00 %322 = fadd float %321, 1.000000e+00 %323 = fmul float %289, 2.000000e+00 %324 = fadd float %323, 1.000000e+00 %325 = bitcast float %322 to i32 %326 = bitcast float %324 to i32 %327 = insertelement <2 x i32> undef, i32 %325, i32 0 %328 = insertelement <2 x i32> %327, i32 %326, i32 1 %329 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %328, <32 x i8> %36, <16 x i8> %38, i32 5) %330 = extractelement <4 x float> %329, i32 3 %331 = call float @llvm.AMDIL.clamp.(float %330, float 0.000000e+00, float 1.000000e+00) %332 = fmul float %318, %331 %333 = fmul float %319, %331 %334 = fmul float %320, %331 %335 = fmul float %332, %25 %336 = fadd float %335, %temp20.0 %337 = fmul float %333, %25 %338 = fadd float %337, %temp21.0 %339 = fmul float %334, %25 %340 = fadd float %339, %temp22.0 %341 = bitcast float %temp24.0 to i32 %342 = add i32 %341, 1 %343 = bitcast i32 %342 to float br label %LOOP } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: readnone declare float @llvm.AMDGPU.rsq(float) #2 ; Function Attrs: readnone declare float @llvm.AMDGPU.cndlt(float, float, float) #2 ; Function Attrs: nounwind readonly declare float @llvm.pow.f32(float, float) #3 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1 ; Function Attrs: readnone declare float @llvm.AMDIL.clamp.(float, float, float) #2 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } attributes #3 = { nounwind readonly } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_LOAD_DWORDX4 s[8:11], s[0:1], 4 ; C0840104 S_WAITCNT lgkmcnt(0) ; BF8C007F S_BUFFER_LOAD_DWORD s6, s[8:11], 34 ; C2030922 S_LOAD_DWORDX4 s[12:15], s[0:1], 8 ; C0860108 S_WAITCNT lgkmcnt(0) ; BF8C007F S_BUFFER_LOAD_DWORD s16, s[12:15], 48 ; C2080D30 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v0, s16 ; 7E000210 V_MUL_F32_e64 v0, s6, v0, 0, 0, 0, 0 ; D2100000 02020006 S_BUFFER_LOAD_DWORD s6, s[8:11], 38 ; C2030926 S_BUFFER_LOAD_DWORD s17, s[12:15], 49 ; C2088D31 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v1, s17 ; 7E020211 V_MAD_F32 v0, s6, v1, v0, 0, 0, 0, 0 ; D2820000 04020206 S_BUFFER_LOAD_DWORD s6, s[8:11], 42 ; C203092A S_BUFFER_LOAD_DWORD s18, s[12:15], 50 ; C2090D32 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v1, s18 ; 7E020212 V_MAD_F32 v0, s6, v1, v0, 0, 0, 0, 0 ; D2820000 04020206 V_CMP_GT_F32_e64 s[6:7], v0, 0.000000e+00, 0, 0, 0, 0 ; D0080006 02010100 V_MOV_B32_e32 v8, 0.000000e+00 ; 7E100280 V_MOV_B32_e32 v9, v8 ; 7E120308 V_MOV_B32_e32 v10, v8 ; 7E140308 S_AND_SAVEEXEC_B64 s[6:7], s[6:7] ; BE862406 S_XOR_B64 s[6:7], exec, s[6:7] ; 8986067E S_CBRANCH_EXECZ BB0_2 ; BF880000 S_LOAD_DWORDX4 s[36:39], s[0:1], 0 ; C0920100 S_WAITCNT lgkmcnt(0) ; BF8C007F S_BUFFER_LOAD_DWORD s0, s[36:39], 40 ; C2002528 S_BUFFER_LOAD_DWORD s1, s[36:39], 41 ; C200A529 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v0, s1 ; 7E000201 V_MAD_F32 v0, v3, s0, v0, 0, 0, 0, 0 ; D2820000 04000103 V_MOV_B32_e32 v3, s16 ; 7E060210 S_BUFFER_LOAD_DWORD s0, s[8:11], 33 ; C2000921 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v1, s0, v3, 0, 0, 0, 0 ; D2100001 02020600 V_MOV_B32_e32 v4, s17 ; 7E080211 S_BUFFER_LOAD_DWORD s0, s[8:11], 37 ; C2000925 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v1, s0, v4, v1, 0, 0, 0, 0 ; D2820001 04060800 V_MOV_B32_e32 v6, s18 ; 7E0C0212 S_BUFFER_LOAD_DWORD s0, s[8:11], 41 ; C2000929 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v1, s0, v6, v1, 0, 0, 0, 0 ; D2820001 04060C00 S_BUFFER_LOAD_DWORD s0, s[8:11], 35 ; C2000923 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v5, s0, v3, 0, 0, 0, 0 ; D2100005 02020600 S_BUFFER_LOAD_DWORD s0, s[8:11], 39 ; C2000927 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v5, s0, v4, v5, 0, 0, 0, 0 ; D2820005 04160800 S_BUFFER_LOAD_DWORD s0, s[8:11], 43 ; C200092B S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v5, s0, v6, v5, 0, 0, 0, 0 ; D2820005 04160C00 V_RCP_F32_e32 v7, v5 ; 7E0E5505 V_MUL_F32_e32 v1, v1, v7 ; 10020F01 V_MAD_F32 v1, v1, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0 ; D2820001 03C1E101 S_BUFFER_LOAD_DWORD s0, s[8:11], 89 ; C2000959 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v1, s0, v1 ; 10020200 V_MUL_F32_e32 v1, 5.000000e-01, v1 ; 100202F0 V_SUB_F32_e32 v5, v0, v1 ; 080A0300 S_BUFFER_LOAD_DWORD s0, s[8:11], 32 ; C2000920 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v3, s0, v3, 0, 0, 0, 0 ; D2100003 02020600 S_BUFFER_LOAD_DWORD s0, s[8:11], 36 ; C2000924 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v3, s0, v4, v3, 0, 0, 0, 0 ; D2820003 040E0800 S_BUFFER_LOAD_DWORD s0, s[8:11], 40 ; C2000928 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v3, s0, v6, v3, 0, 0, 0, 0 ; D2820003 040E0C00 V_MUL_F32_e32 v3, v3, v7 ; 10060F03 V_MAD_F32 v3, v3, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0 ; D2820003 03C1E103 S_BUFFER_LOAD_DWORD s0, s[8:11], 88 ; C2000958 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v3, s0, v3 ; 10060600 V_MUL_F32_e32 v3, 5.000000e-01, v3 ; 100606F0 V_SUB_F32_e32 v7, v2, v3 ; 080E0702 V_ADD_F32_e32 v4, v0, v0 ; 06080100 S_BUFFER_LOAD_DWORD s8, s[12:15], 54 ; C2040D36 S_BUFFER_LOAD_DWORD s9, s[12:15], 53 ; C2048D35 S_BUFFER_LOAD_DWORD s10, s[12:15], 52 ; C2050D34 V_ADD_F32_e32 v6, v2, v2 ; 060C0502 S_LOAD_DWORDX4 s[12:15], s[2:3], 4 ; C0860304 S_LOAD_DWORDX8 s[16:23], s[4:5], 8 ; C0C80508 S_LOAD_DWORDX4 s[24:27], s[2:3], 0 ; C08C0300 S_LOAD_DWORDX8 s[28:35], s[4:5], 0 ; C0CE0500 S_BUFFER_LOAD_DWORD s0, s[36:39], 28 ; C200251C S_WAITCNT lgkmcnt(0) ; BF8C007F V_CMP_GT_F32_e64 s[0:1], s0, 0.000000e+00, 0, 0, 0, 0 ; D0080000 02010000 V_CNDMASK_B32_e64 v8, 0, -1, s[0:1], 0, 0, 0, 0 ; D2000008 00018280 V_CMP_EQ_I32_e64 s[0:1], v8, 0, 0, 0, 0, 0 ; D1040000 02010108 S_AND_SAVEEXEC_B64 s[0:1], s[0:1] ; BE802400 S_XOR_B64 s[0:1], exec, s[0:1] ; 8980007E S_CBRANCH_EXECZ BB0_3 ; BF880000 V_ADD_F32_e64 v9, v4, 1.000000e+00, 0, 0, 0, 0 ; D2060009 0201E504 V_ADD_F32_e64 v8, v6, 1.000000e+00, 0, 0, 0, 0 ; D2060008 0201E506 IMAGE_SAMPLE v10, 1, -1, 0, 0, 0, 0, 0, 0, v[8:9], s[16:23], s[12:15] ; F0801100 00640A08 S_WAITCNT vmcnt(0) ; BF8C0770 V_CMP_EQ_F32_e64 s[2:3], v10, 1.000000e+00, 0, 0, 0, 0 ; D0040002 0201E50A V_CNDMASK_B32_e64 v10, 0, -1, s[2:3], 0, 0, 0, 0 ; D200000A 00098280 V_AND_B32_e32 v10, 1065353216, v10 ; 361414F2 V_MUL_F32_e32 v10, 3.500000e+01, v10 ; 101414FF 420C0000 V_MUL_F32_e32 v11, s8, v10 ; 10161408 IMAGE_SAMPLE v8, 8, -1, 0, 0, 0, 0, 0, 0, v[8:9], s[28:35], s[24:27] ; F0801800 00C70808 S_WAITCNT vmcnt(0) ; BF8C0770 V_ADD_F32_e64 v12, 0, v8, 0, 1, 0, 0 ; D206080C 02021080 V_MUL_F32_e32 v8, v11, v12 ; 1010190B V_MUL_F32_e64 v9, v5, v5, 0, 0, 0, 0 ; D2100009 02020B05 V_MAD_F32 v9, v7, v7, v9, 0, 0, 0, 0 ; D2820009 04260F07 V_RSQ_LEGACY_F32_e32 v11, v9 ; 7E165B09 V_MUL_F32_e32 v11, v11, v9 ; 1016130B V_XOR_B32_e32 v9, -2147483648, v9 ; 3A1212FF 80000000 V_CMP_GT_F32_e64 s[2:3], 0, v9, 0, 0, 0, 0 ; D0080002 02021280 V_CNDMASK_B32_e64 v9, 0.000000e+00, v11, s[2:3], 0, 0, 0, 0 ; D2000009 000A1680 V_ADD_F32_e32 v9, 1.000000e+02, v9 ; 061212FF 42C80000 V_LOG_F32_e32 v9, v9 ; 7E124F09 V_MUL_LEGACY_F32_e32 v9, 1.300000e+00, v9 ; 0E1212FF 3FA66666 V_EXP_F32_e32 v9, v9 ; 7E124B09 V_ADD_F32_e32 v9, 1.000000e+02, v9 ; 061212FF 42C80000 V_RCP_F32_e32 v11, v9 ; 7E165509 V_MAD_F32 v8, v8, v11, 0.000000e+00, 0, 0, 0, 0 ; D2820008 02021708 V_MUL_F32_e32 v9, s9, v10 ; 10121409 V_MUL_F32_e32 v9, v9, v12 ; 10121909 V_MAD_F32 v9, v9, v11, 0.000000e+00, 0, 0, 0, 0 ; D2820009 02021709 V_MUL_F32_e32 v10, s10, v10 ; 1014140A V_MUL_F32_e32 v10, v10, v12 ; 1014190A V_MAD_F32 v10, v10, v11, 0.000000e+00, 0, 0, 0, 0 ; D282000A 0202170A S_OR_SAVEEXEC_B64 s[0:1], s[0:1] ; BE802500 S_WAITCNT expcnt(0) ; BF8C070F S_XOR_B64 exec, exec, s[0:1] ; 89FE007E S_CBRANCH_EXECZ BB0_6 ; BF880000 S_BUFFER_LOAD_DWORD s2, s[36:39], 24 ; C2012518 S_BUFFER_LOAD_DWORD s4, s[36:39], 16 ; C2022510 S_BUFFER_LOAD_DWORD s5, s[36:39], 12 ; C202A50C S_BUFFER_LOAD_DWORD s3, s[36:39], 20 ; C201A514 V_MUL_F32_e64 v5, v5, v5, 0, 0, 0, 0 ; D2100005 02020B05 V_MAD_F32 v5, v7, v7, v5, 0, 0, 0, 0 ; D2820005 04160F07 V_RSQ_LEGACY_F32_e32 v7, v5 ; 7E0E5B05 V_MUL_F32_e32 v7, v7, v5 ; 100E0B07 V_XOR_B32_e32 v5, -2147483648, v5 ; 3A0A0AFF 80000000 V_CMP_GT_F32_e64 s[36:37], 0, v5, 0, 0, 0, 0 ; D0080024 02020A80 V_CNDMASK_B32_e64 v5, 0.000000e+00, v7, s[36:37], 0, 0, 0, 0 ; D2000005 00920E80 V_ADD_F32_e32 v5, 1.000000e+02, v5 ; 060A0AFF 42C80000 V_LOG_F32_e32 v5, v5 ; 7E0A4F05 V_MUL_LEGACY_F32_e32 v5, 1.300000e+00, v5 ; 0E0A0AFF 3FA66666 V_EXP_F32_e32 v5, v5 ; 7E0A4B05 V_ADD_F32_e32 v5, 1.000000e+02, v5 ; 060A0AFF 42C80000 V_RCP_F32_e32 v5, v5 ; 7E0A5505 V_MUL_F32_e32 v5, 1.000000e+01, v5 ; 100A0AFF 41200000 V_ADD_F32_e64 v8, v4, 1.000000e+00, 0, 0, 0, 0 ; D2060008 0201E504 V_ADD_F32_e64 v7, v6, 1.000000e+00, 0, 0, 0, 0 ; D2060007 0201E506 IMAGE_SAMPLE v4, 1, -1, 0, 0, 0, 0, 0, 0, v[7:8], s[16:23], s[12:15] ; F0801100 00640407 S_WAITCNT vmcnt(0) lgkmcnt(0) ; BF8C0070 V_CMP_EQ_F32_e64 s[36:37], v4, 1.000000e+00, 0, 0, 0, 0 ; D0040024 0201E504 V_CNDMASK_B32_e64 v4, 0, -1, s[36:37], 0, 0, 0, 0 ; D2000004 00918280 V_AND_B32_e32 v4, 1065353216, v4 ; 360808F2 V_MUL_F32_e32 v4, v5, v4 ; 10080905 V_MUL_F32_e32 v5, s8, v4 ; 100A0808 IMAGE_SAMPLE v6, 8, -1, 0, 0, 0, 0, 0, 0, v[7:8], s[28:35], s[24:27] ; F0801800 00C70607 S_WAITCNT vmcnt(0) ; BF8C0770 V_ADD_F32_e64 v6, 0, v6, 0, 1, 0, 0 ; D2060806 02020C80 V_MUL_F32_e32 v12, v5, v6 ; 10180D05 V_MUL_F32_e32 v5, s9, v4 ; 100A0809 V_MUL_F32_e32 v13, v5, v6 ; 101A0D05 V_MUL_F32_e32 v4, s10, v4 ; 1008080A V_MUL_F32_e32 v14, v4, v6 ; 101C0D04 V_SUBREV_F32_e32 v4, v3, v2 ; 0A080503 V_SUB_F32_e64 v5, v0, v1, 0, 0, 0, 0 ; D2080005 02020300 V_MUL_F32_e32 v5, v5, v5 ; 100A0B05 V_MAD_F32 v4, v4, v4, v5, 0, 0, 0, 0 ; D2820004 04160904 V_XOR_B32_e32 v5, -2147483648, v4 ; 3A0A08FF 80000000 V_SUB_F32_e32 v3, v3, v2 ; 08060503 V_SUB_F32_e64 v6, v1, v0, 0, 0, 0, 0 ; D2080006 02020101 V_CVT_F32_I32_e32 v1, s2 ; 7E020A02 V_ADD_F32_e32 v1, -1.000000e+00, v1 ; 060202F3 V_RCP_F32_e32 v7, v1 ; 7E0E5501 V_MOV_B32_e32 v8, 0.000000e+00 ; 7E100280 S_MOV_B64 s[36:37], 0 ; BEA40480 V_MOV_B32_e32 v10, s2 ; 7E140202 V_MOV_B32_e32 v1, v14 ; 7E02030E V_MOV_B32_e32 v9, v13 ; 7E12030D V_MOV_B32_e32 v11, v12 ; 7E16030C V_CMP_GE_I32_e64 s[38:39], v8, v10, 0, 0, 0, 0 ; D10C0026 02021508 V_CNDMASK_B32_e64 v12, 0, -1, s[38:39], 0, 0, 0, 0 ; D200000C 00998280 V_CMP_EQ_I32_e64 s[38:39], v12, 0, 0, 0, 0, 0 ; D1040026 0201010C S_AND_SAVEEXEC_B64 s[38:39], s[38:39] ; BEA62426 S_XOR_B64 s[38:39], exec, s[38:39] ; 89A6267E S_CBRANCH_EXECZ BB0_8 ; BF880000 V_CVT_F32_I32_e32 v12, v8 ; 7E180B08 V_MUL_F32_e32 v12, v7, v12 ; 10181907 V_MUL_F32_e32 v12, v12, v12 ; 1018190C V_MUL_F32_e32 v13, v6, v12 ; 101A1906 V_MUL_F32_e32 v13, s5, v13 ; 101A1A05 V_MOV_B32_e32 v14, 7.000000e-01 ; 7E1C02FF 3F333333 V_MAD_F32 v13, v13, v14, v0, 0, 0, 0, 0 ; D282000D 04021D0D V_ADD_F32_e32 v13, v13, v13 ; 061A1B0D V_ADD_F32_e32 v16, 1.000000e+00, v13 ; 06201AF2 V_MUL_F32_e32 v12, v3, v12 ; 10181903 V_MUL_F32_e32 v12, s5, v12 ; 10181805 V_MAD_F32 v12, v12, v14, v2, 0, 0, 0, 0 ; D282000C 040A1D0C V_ADD_F32_e32 v12, v12, v12 ; 0618190C V_ADD_F32_e32 v15, 1.000000e+00, v12 ; 061E18F2 IMAGE_SAMPLE v12, 1, -1, 0, 0, 0, 0, 0, 0, v[15:16], s[16:23], s[12:15] ; F0801100 00640C0F S_WAITCNT vmcnt(0) ; BF8C0770 V_CMP_EQ_F32_e64 s[40:41], v12, 1.000000e+00, 0, 0, 0, 0 ; D0040028 0201E50C V_CNDMASK_B32_e64 v12, 0, -1, s[40:41], 0, 0, 0, 0 ; D200000C 00A18280 V_AND_B32_e32 v12, 1065353216, v12 ; 361818F2 V_RSQ_LEGACY_F32_e32 v13, v4 ; 7E1A5B04 V_MUL_F32_e32 v13, v4, v13 ; 101A1B04 V_CMP_GT_F32_e64 s[40:41], 0, v5, 0, 0, 0, 0 ; D0080028 02020A80 V_CNDMASK_B32_e64 v13, 0.000000e+00, v13, s[40:41], 0, 0, 0, 0 ; D200000D 00A21A80 V_ADD_F32_e32 v13, 1.000000e+02, v13 ; 061A1AFF 42C80000 V_LOG_F32_e32 v13, v13 ; 7E1A4F0D V_MUL_LEGACY_F32_e32 v13, 1.300000e+00, v13 ; 0E1A1AFF 3FA66666 V_EXP_F32_e32 v13, v13 ; 7E1A4B0D V_ADD_F32_e32 v13, 1.000000e+02, v13 ; 061A1AFF 42C80000 V_RCP_F32_e32 v13, v13 ; 7E1A550D V_MUL_F32_e32 v13, 1.000000e+01, v13 ; 101A1AFF 41200000 V_MUL_F32_e32 v14, v13, v12 ; 101C190D V_MUL_F32_e32 v12, s8, v14 ; 10181C08 IMAGE_SAMPLE v13, 8, -1, 0, 0, 0, 0, 0, 0, v[15:16], s[28:35], s[24:27] ; F0801800 00C70D0F S_WAITCNT vmcnt(0) ; BF8C0770 V_ADD_F32_e64 v15, 0, v13, 0, 1, 0, 0 ; D206080F 02021A80 V_MUL_F32_e32 v12, v12, v15 ; 10181F0C V_MAD_F32 v12, v12, s4, v11, 0, 0, 0, 0 ; D282000C 042C090C V_MUL_F32_e32 v13, s9, v14 ; 101A1C09 V_MUL_F32_e32 v13, v13, v15 ; 101A1F0D V_MAD_F32 v13, v13, s4, v9, 0, 0, 0, 0 ; D282000D 0424090D V_MUL_F32_e32 v14, s10, v14 ; 101C1C0A V_MUL_F32_e32 v14, v14, v15 ; 101C1F0E V_MAD_F32 v14, v14, s4, v1, 0, 0, 0, 0 ; D282000E 0404090E V_ADD_I32_e32 v8, 1, v8 ; 4A101081 S_OR_B64 exec, exec, s[38:39] ; 88FE267E S_OR_B64 s[36:37], s[38:39], s[36:37] ; 88A42426 S_ANDN2_B64 exec, exec, s[36:37] ; 8AFE247E S_CBRANCH_EXECNZ BB0_7 ; BF890000 S_OR_B64 exec, exec, s[36:37] ; 88FE247E V_CVT_F32_I32_e32 v0, s2 ; 7E000A02 V_RCP_F32_e32 v0, v0 ; 7E005500 V_MUL_F32_e32 v0, s3, v0 ; 10000003 V_MUL_F32_e32 v2, v11, v0 ; 1004010B V_MOV_B32_e32 v3, 1.000000e-03 ; 7E0602FF 3A83126F V_CMP_LE_F32_e64 s[2:3], v2, v3, 0, 0, 0, 0 ; D0060002 02020702 V_CMP_U_F32_e64 s[4:5], v2, v2, 0, 0, 0, 0 ; D0100004 02020502 S_OR_B64 s[2:3], s[2:3], s[4:5] ; 88820402 V_CNDMASK_B32_e64 v2, v2, v3, s[2:3], 0, 0, 0, 0 ; D2000002 000A0702 V_LOG_F32_e32 v2, v2 ; 7E044F02 V_MUL_LEGACY_F32_e32 v2, 2.200000e+00, v2 ; 0E0404FF 400CCCCD V_EXP_F32_e32 v8, v2 ; 7E104B02 V_MUL_F32_e32 v2, v9, v0 ; 10040109 V_CMP_LE_F32_e64 s[2:3], v2, v3, 0, 0, 0, 0 ; D0060002 02020702 V_CMP_U_F32_e64 s[4:5], v2, v2, 0, 0, 0, 0 ; D0100004 02020502 S_OR_B64 s[2:3], s[2:3], s[4:5] ; 88820402 V_CNDMASK_B32_e64 v2, v2, v3, s[2:3], 0, 0, 0, 0 ; D2000002 000A0702 V_LOG_F32_e32 v2, v2 ; 7E044F02 V_MUL_LEGACY_F32_e32 v2, 2.200000e+00, v2 ; 0E0404FF 400CCCCD V_EXP_F32_e32 v9, v2 ; 7E124B02 V_MUL_F32_e32 v0, v1, v0 ; 10000101 V_CMP_LE_F32_e64 s[2:3], v0, v3, 0, 0, 0, 0 ; D0060002 02020700 V_CMP_U_F32_e64 s[4:5], v0, v0, 0, 0, 0, 0 ; D0100004 02020100 S_OR_B64 s[2:3], s[2:3], s[4:5] ; 88820402 V_CNDMASK_B32_e64 v0, v0, v3, s[2:3], 0, 0, 0, 0 ; D2000000 000A0700 V_LOG_F32_e32 v0, v0 ; 7E004F00 V_MUL_LEGACY_F32_e32 v0, 2.200000e+00, v0 ; 0E0000FF 400CCCCD V_EXP_F32_e32 v10, v0 ; 7E144B00 S_OR_B64 exec, exec, s[0:1] ; 88FE007E S_OR_B64 exec, exec, s[6:7] ; 88FE067E V_CVT_PKRTZ_F16_F32_e64 v0, v10, v9, 0, 0, 0, 0 ; D25E0000 0202130A V_CVT_PKRTZ_F16_F32_e64 v1, v8, 0.000000e+00, 0, 0, 0, 0 ; D25E0001 02010108 EXP 15, 0, 1, 1, 1, v0, v1, v0, v1 ; F8001C0F 01000100 S_ENDPGM ; BF810000 VERT DCL IN[0] DCL OUT[0], POSITION DCL CONST[1][0..96] DCL CONST[2][0..68] DCL TEMP[0], LOCAL IMM[0] FLT32 { 1.0000, 0.0000, 0.0000, 0.0000} 0: MOV TEMP[0].w, IMM[0].xxxx 1: MOV TEMP[0].xyz, IN[0].xyzx 2: MOV OUT[0], TEMP[0] 3: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 0 %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0 %12 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %11, i32 0, i32 %6) %13 = extractelement <4 x float> %12, i32 0 %14 = extractelement <4 x float> %12, i32 1 %15 = extractelement <4 x float> %12, i32 2 call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %13, float %14, float %15, float 1.000000e+00) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_LOAD_DWORDX4 s[0:3], s[8:9], 0 ; C0800900 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[0:3], s[0:3][v0] + 0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80000000 V_MOV_B32_e32 v4, 1.000000e+00 ; 7E0802F2 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 12, 0, 1, 0, v0, v1, v2, v4 ; F80008CF 04020100 S_ENDPGM ; BF810000 FRAG 0: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: call void @llvm.SI.export(i32 0, i32 1, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) ret void } declare void @llvm.SI.export(i32, i32, i32, i32, i32, i32, i32, i32, i32) attributes #0 = { "ShaderType"="0" } Shader Disassembly: V_MOV_B32_e32 v0, 0 ; 7E000280 EXP 0, 0, 0, 1, 1, v0, v0, v0, v0 ; F8001800 00000000 S_ENDPGM ; BF810000 FRAG DCL IN[0], POSITION, LINEAR DCL OUT[0], COLOR DCL SAMP[0] DCL SAMP[1] DCL CONST[2] DCL TEMP[0] DCL TEMP[1..2], LOCAL IMM[0] FLT32 { 0.5000, 0.0000, 0.0000, 0.0000} 0: MOV TEMP[0], IN[0] 1: MAD TEMP[0].y, IN[0], CONST[2].xxxx, CONST[2].yyyy 2: MOV TEMP[1].xy, TEMP[0].xyyy 3: TEX TEMP[1].xyz, TEMP[1], SAMP[1], RECT 4: MUL TEMP[2].xy, TEMP[0].xyyy, IMM[0].xxxx 5: MOV TEMP[2].xy, TEMP[2].xyyy 6: TEX TEMP[2].xyz, TEMP[2], SAMP[0], RECT 7: ADD TEMP[1].xyz, TEMP[1].xyzz, TEMP[2].xyzz 8: MOV OUT[0], TEMP[1] 9: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %22 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0 %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0 %24 = call float @llvm.SI.load.const(<16 x i8> %23, i32 32) %25 = call float @llvm.SI.load.const(<16 x i8> %23, i32 36) %26 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0 %27 = load <32 x i8> addrspace(2)* %26, !tbaa !0 %28 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0 %29 = load <16 x i8> addrspace(2)* %28, !tbaa !0 %30 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 1 %31 = load <32 x i8> addrspace(2)* %30, !tbaa !0 %32 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 1 %33 = load <16 x i8> addrspace(2)* %32, !tbaa !0 %34 = fmul float %15, %24 %35 = fadd float %34, %25 %36 = bitcast float %14 to i32 %37 = bitcast float %35 to i32 %38 = insertelement <2 x i32> undef, i32 %36, i32 0 %39 = insertelement <2 x i32> %38, i32 %37, i32 1 %40 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %39, <32 x i8> %31, <16 x i8> %33, i32 5) %41 = extractelement <4 x float> %40, i32 0 %42 = extractelement <4 x float> %40, i32 1 %43 = extractelement <4 x float> %40, i32 2 %44 = fmul float %14, 5.000000e-01 %45 = fmul float %35, 5.000000e-01 %46 = bitcast float %44 to i32 %47 = bitcast float %45 to i32 %48 = insertelement <2 x i32> undef, i32 %46, i32 0 %49 = insertelement <2 x i32> %48, i32 %47, i32 1 %50 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %49, <32 x i8> %27, <16 x i8> %29, i32 5) %51 = extractelement <4 x float> %50, i32 0 %52 = extractelement <4 x float> %50, i32 1 %53 = extractelement <4 x float> %50, i32 2 %54 = fadd float %41, %51 %55 = fadd float %42, %52 %56 = fadd float %43, %53 %57 = call i32 @llvm.SI.packf16(float %54, float %55) %58 = bitcast i32 %57 to float %59 = call i32 @llvm.SI.packf16(float %56, float 0.000000e+00) %60 = bitcast i32 %59 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %58, float %60, float %58, float %60) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: V_MOV_B32_e32 v0, v2 ; 7E000302 S_LOAD_DWORDX4 s[8:11], s[0:1], 0 ; C0840100 S_WAITCNT lgkmcnt(0) ; BF8C007F S_BUFFER_LOAD_DWORD s0, s[8:11], 8 ; C2000908 S_BUFFER_LOAD_DWORD s1, s[8:11], 9 ; C2008909 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v2, s1 ; 7E040201 V_MAD_F32 v1, v3, s0, v2, 0, 0, 0, 0 ; D2820001 04080103 S_LOAD_DWORDX4 s[8:11], s[2:3], 4 ; C0840304 S_LOAD_DWORDX8 s[12:19], s[4:5], 8 ; C0C60508 S_WAITCNT lgkmcnt(0) ; BF8C007F IMAGE_SAMPLE v[2:4], 7, -1, 0, 0, 0, 0, 0, 0, v[0:1], s[12:19], s[8:11] ; F0801700 00430200 V_MUL_F32_e32 v6, 5.000000e-01, v1 ; 100C02F0 V_MUL_F32_e32 v5, 5.000000e-01, v0 ; 100A00F0 S_LOAD_DWORDX4 s[0:3], s[2:3], 0 ; C0800300 S_LOAD_DWORDX8 s[4:11], s[4:5], 0 ; C0C20500 S_WAITCNT vmcnt(0) lgkmcnt(0) ; BF8C0070 IMAGE_SAMPLE v[5:7], 7, -1, 0, 0, 0, 0, 0, 0, v[5:6], s[4:11], s[0:3] ; F0801700 00010505 S_WAITCNT vmcnt(0) ; BF8C0770 V_ADD_F32_e32 v0, v3, v6 ; 06000D03 V_ADD_F32_e32 v1, v2, v5 ; 06020B02 V_CVT_PKRTZ_F16_F32_e32 v0, v1, v0 ; 5E000101 V_ADD_F32_e32 v1, v4, v7 ; 06020F04 V_CVT_PKRTZ_F16_F32_e64 v1, v1, 0.000000e+00, 0, 0, 0, 0 ; D25E0001 02010101 EXP 15, 0, 1, 1, 1, v0, v1, v0, v1 ; F8001C0F 01000100 S_ENDPGM ; BF810000 VERT DCL IN[0] DCL OUT[0], POSITION DCL TEMP[0], LOCAL IMM[0] FLT32 { 1.0000, 0.0000, 0.0000, 0.0000} 0: MOV TEMP[0].w, IMM[0].xxxx 1: MOV TEMP[0].xyz, IN[0].xyzx 2: MOV OUT[0], TEMP[0] 3: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 0 %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0 %12 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %11, i32 0, i32 %6) %13 = extractelement <4 x float> %12, i32 0 %14 = extractelement <4 x float> %12, i32 1 %15 = extractelement <4 x float> %12, i32 2 call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %13, float %14, float %15, float 1.000000e+00) ret void } ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_LOAD_DWORDX4 s[0:3], s[8:9], 0 ; C0800900 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[0:3], s[0:3][v0] + 0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80000000 V_MOV_B32_e32 v4, 1.000000e+00 ; 7E0802F2 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 12, 0, 1, 0, v0, v1, v2, v4 ; F80008CF 04020100 S_ENDPGM ; BF810000 FRAG DCL IN[0], POSITION, LINEAR DCL OUT[0], COLOR DCL SAMP[0] DCL SAMP[1] DCL CONST[2] DCL TEMP[0] DCL TEMP[1..4], LOCAL IMM[0] UINT32 {0, 0, 0, 0} IMM[1] FLT32 { 0.0001, 0.0010, 2.2000, 1.0000} 0: MOV TEMP[0], IN[0] 1: MAD TEMP[0].y, IN[0], CONST[2].xxxx, CONST[2].yyyy 2: MOV TEMP[1].x, TEMP[0].xxxx 3: TXQ TEMP[2].y, IMM[0].xxxx, SAMP[0], RECT 4: I2F TEMP[2].x, TEMP[2].yyyy 5: ADD TEMP[2].x, TEMP[2].xxxx, -TEMP[0].yyyy 6: MOV TEMP[1].y, TEMP[2].xxxx 7: MOV TEMP[1].xy, TEMP[1].xyyy 8: TEX TEMP[1], TEMP[1], SAMP[0], RECT 9: ADD TEMP[3].x, TEMP[1].wwww, IMM[1].xxxx 10: RCP TEMP[3].x, TEMP[3].xxxx 11: MUL TEMP[2].xyz, TEMP[1].zyxx, TEMP[3].xxxx 12: MAX TEMP[3].xyz, IMM[1].yyyy, TEMP[2].xyzz 13: POW TEMP[4].x, TEMP[3].xxxx, IMM[1].zzzz 14: POW TEMP[4].y, TEMP[3].yyyy, IMM[1].zzzz 15: POW TEMP[4].z, TEMP[3].zzzz, IMM[1].zzzz 16: MOV TEMP[3].xy, TEMP[0].xyyy 17: TEX TEMP[3].xyz, TEMP[3], SAMP[1], RECT 18: ADD TEMP[1].x, IMM[1].wwww, -TEMP[1].wwww 19: LRP TEMP[2].xyz, TEMP[1].xxxx, TEMP[3].xyzz, TEMP[4].xyzz 20: MOV TEMP[1].xyz, TEMP[2].xyzx 21: MOV OUT[0], TEMP[1] 22: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %22 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0 %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0 %24 = call float @llvm.SI.load.const(<16 x i8> %23, i32 32) %25 = call float @llvm.SI.load.const(<16 x i8> %23, i32 36) %26 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0 %27 = load <32 x i8> addrspace(2)* %26, !tbaa !0 %28 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0 %29 = load <16 x i8> addrspace(2)* %28, !tbaa !0 %30 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 1 %31 = load <32 x i8> addrspace(2)* %30, !tbaa !0 %32 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 1 %33 = load <16 x i8> addrspace(2)* %32, !tbaa !0 %34 = fmul float %15, %24 %35 = fadd float %34, %25 %36 = call <4 x i32> @llvm.SI.resinfo(i32 0, <32 x i8> %27, i32 5) %37 = extractelement <4 x i32> %36, i32 1 %38 = bitcast i32 %37 to float %39 = bitcast float %38 to i32 %40 = sitofp i32 %39 to float %41 = fsub float -0.000000e+00, %35 %42 = fadd float %40, %41 %43 = bitcast float %14 to i32 %44 = bitcast float %42 to i32 %45 = insertelement <2 x i32> undef, i32 %43, i32 0 %46 = insertelement <2 x i32> %45, i32 %44, i32 1 %47 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %46, <32 x i8> %27, <16 x i8> %29, i32 5) %48 = extractelement <4 x float> %47, i32 0 %49 = extractelement <4 x float> %47, i32 1 %50 = extractelement <4 x float> %47, i32 2 %51 = extractelement <4 x float> %47, i32 3 %52 = fadd float %51, 0x3F1A36E2E0000000 %53 = fdiv float 1.000000e+00, %52 %54 = fmul float %50, %53 %55 = fmul float %49, %53 %56 = fmul float %48, %53 %57 = fcmp uge float 0x3F50624DE0000000, %54 %58 = select i1 %57, float 0x3F50624DE0000000, float %54 %59 = fcmp uge float 0x3F50624DE0000000, %55 %60 = select i1 %59, float 0x3F50624DE0000000, float %55 %61 = fcmp uge float 0x3F50624DE0000000, %56 %62 = select i1 %61, float 0x3F50624DE0000000, float %56 %63 = call float @llvm.pow.f32(float %58, float 0x40019999A0000000) %64 = call float @llvm.pow.f32(float %60, float 0x40019999A0000000) %65 = call float @llvm.pow.f32(float %62, float 0x40019999A0000000) %66 = bitcast float %14 to i32 %67 = bitcast float %35 to i32 %68 = insertelement <2 x i32> undef, i32 %66, i32 0 %69 = insertelement <2 x i32> %68, i32 %67, i32 1 %70 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %69, <32 x i8> %31, <16 x i8> %33, i32 5) %71 = extractelement <4 x float> %70, i32 0 %72 = extractelement <4 x float> %70, i32 1 %73 = extractelement <4 x float> %70, i32 2 %74 = fsub float -0.000000e+00, %51 %75 = fadd float 1.000000e+00, %74 %76 = call float @llvm.AMDGPU.lrp(float %75, float %71, float %63) %77 = call float @llvm.AMDGPU.lrp(float %75, float %72, float %64) %78 = call float @llvm.AMDGPU.lrp(float %75, float %73, float %65) %79 = call i32 @llvm.SI.packf16(float %76, float %77) %80 = bitcast i32 %79 to float %81 = call i32 @llvm.SI.packf16(float %78, float %51) %82 = bitcast i32 %81 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %80, float %82, float %80, float %82) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: readnone declare <4 x i32> @llvm.SI.resinfo(i32, <32 x i8>, i32) #2 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1 ; Function Attrs: nounwind readonly declare float @llvm.pow.f32(float, float) #3 ; Function Attrs: readnone declare float @llvm.AMDGPU.lrp(float, float, float) #2 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } attributes #3 = { nounwind readonly } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: V_MOV_B32_e32 v0, v2 ; 7E000302 S_LOAD_DWORDX4 s[8:11], s[0:1], 0 ; C0840100 S_WAITCNT lgkmcnt(0) ; BF8C007F S_BUFFER_LOAD_DWORD s0, s[8:11], 8 ; C2000908 S_BUFFER_LOAD_DWORD s1, s[8:11], 9 ; C2008909 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v2, s1 ; 7E040201 V_MAD_F32 v2, v3, s0, v2, 0, 0, 0, 0 ; D2820002 04080103 S_LOAD_DWORDX8 s[8:15], s[4:5], 0 ; C0C40500 V_MOV_B32_e32 v3, 0 ; 7E060280 S_WAITCNT lgkmcnt(0) ; BF8C007F IMAGE_GET_RESINFO v3, 2, 0, 0, 0, 0, 0, 0, 0, v3, s[8:15] ; F0380200 00020303 S_WAITCNT vmcnt(0) ; BF8C0770 V_CVT_F32_I32_e32 v3, v3 ; 7E060B03 V_SUB_F32_e32 v1, v3, v2 ; 08020503 S_LOAD_DWORDX4 s[16:19], s[2:3], 0 ; C0880300 S_WAITCNT lgkmcnt(0) ; BF8C007F IMAGE_SAMPLE v[3:6], 15, -1, 0, 0, 0, 0, 0, 0, v[0:1], s[8:15], s[16:19] ; F0801F00 00820300 V_MOV_B32_e32 v7, 1.000000e-04 ; 7E0E02FF 38D1B717 S_WAITCNT vmcnt(0) ; BF8C0770 V_ADD_F32_e32 v7, v6, v7 ; 060E0F06 V_RCP_F32_e32 v7, v7 ; 7E0E5507 V_MUL_F32_e32 v8, v4, v7 ; 10100F04 V_MOV_B32_e32 v9, 1.000000e-03 ; 7E1202FF 3A83126F V_CMP_LE_F32_e64 s[0:1], v8, v9, 0, 0, 0, 0 ; D0060000 02021308 V_CMP_U_F32_e64 s[6:7], v8, v8, 0, 0, 0, 0 ; D0100006 02021108 S_OR_B64 s[0:1], s[0:1], s[6:7] ; 88800600 V_CNDMASK_B32_e64 v8, v8, v9, s[0:1], 0, 0, 0, 0 ; D2000008 00021308 V_LOG_F32_e32 v8, v8 ; 7E104F08 V_MUL_LEGACY_F32_e32 v8, 2.200000e+00, v8 ; 0E1010FF 400CCCCD V_EXP_F32_e32 v8, v8 ; 7E104B08 V_SUB_F32_e32 v10, 1.000000e+00, v6 ; 08140CF2 V_SUB_F32_e32 v11, 1.000000e+00, v10 ; 081614F2 V_MUL_F32_e32 v8, v11, v8 ; 1010110B V_MOV_B32_e32 v1, v2 ; 7E020302 S_LOAD_DWORDX4 s[0:3], s[2:3], 4 ; C0800304 S_LOAD_DWORDX8 s[4:11], s[4:5], 8 ; C0C20508 S_WAITCNT lgkmcnt(0) ; BF8C007F IMAGE_SAMPLE v[0:2], 7, -1, 0, 0, 0, 0, 0, 0, v[0:1], s[4:11], s[0:3] ; F0801700 00010000 S_WAITCNT vmcnt(0) ; BF8C0770 V_MAD_F32 v8, v10, v1, v8, 0, 0, 0, 0 ; D2820008 0422030A V_MUL_F32_e32 v12, v5, v7 ; 10180F05 V_CMP_LE_F32_e64 s[0:1], v12, v9, 0, 0, 0, 0 ; D0060000 0202130C V_CMP_U_F32_e64 s[2:3], v12, v12, 0, 0, 0, 0 ; D0100002 0202190C S_OR_B64 s[0:1], s[0:1], s[2:3] ; 88800200 V_CNDMASK_B32_e64 v12, v12, v9, s[0:1], 0, 0, 0, 0 ; D200000C 0002130C V_LOG_F32_e32 v12, v12 ; 7E184F0C V_MUL_LEGACY_F32_e32 v12, 2.200000e+00, v12 ; 0E1818FF 400CCCCD V_EXP_F32_e32 v12, v12 ; 7E184B0C V_MUL_F32_e32 v12, v11, v12 ; 1018190B V_MAD_F32 v12, v10, v0, v12, 0, 0, 0, 0 ; D282000C 0432010A V_CVT_PKRTZ_F16_F32_e32 v8, v12, v8 ; 5E10110C V_MUL_F32_e32 v7, v3, v7 ; 100E0F03 V_CMP_LE_F32_e64 s[0:1], v7, v9, 0, 0, 0, 0 ; D0060000 02021307 V_CMP_U_F32_e64 s[2:3], v7, v7, 0, 0, 0, 0 ; D0100002 02020F07 S_OR_B64 s[0:1], s[0:1], s[2:3] ; 88800200 V_CNDMASK_B32_e64 v7, v7, v9, s[0:1], 0, 0, 0, 0 ; D2000007 00021307 V_LOG_F32_e32 v7, v7 ; 7E0E4F07 V_MUL_LEGACY_F32_e32 v7, 2.200000e+00, v7 ; 0E0E0EFF 400CCCCD V_EXP_F32_e32 v7, v7 ; 7E0E4B07 V_MUL_F32_e32 v7, v11, v7 ; 100E0F0B V_MAD_F32 v0, v10, v2, v7, 0, 0, 0, 0 ; D2820000 041E050A V_CVT_PKRTZ_F16_F32_e32 v0, v0, v6 ; 5E000D00 EXP 15, 0, 1, 1, 1, v8, v0, v8, v0 ; F8001C0F 00080008 S_ENDPGM ; BF810000 VERT DCL IN[0] DCL OUT[0], POSITION DCL TEMP[0], LOCAL IMM[0] FLT32 { 1.0000, 0.0000, 0.0000, 0.0000} 0: MOV TEMP[0].w, IMM[0].xxxx 1: MOV TEMP[0].xyz, IN[0].xyzx 2: MOV OUT[0], TEMP[0] 3: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 0 %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0 %12 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %11, i32 0, i32 %6) %13 = extractelement <4 x float> %12, i32 0 %14 = extractelement <4 x float> %12, i32 1 %15 = extractelement <4 x float> %12, i32 2 call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %13, float %14, float %15, float 1.000000e+00) ret void } ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_LOAD_DWORDX4 s[0:3], s[8:9], 0 ; C0800900 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[0:3], s[0:3][v0] + 0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80000000 V_MOV_B32_e32 v4, 1.000000e+00 ; 7E0802F2 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 12, 0, 1, 0, v0, v1, v2, v4 ; F80008CF 04020100 S_ENDPGM ; BF810000 FRAG DCL IN[0], POSITION, LINEAR DCL OUT[0], COLOR DCL SAMP[0] DCL CONST[2] DCL CONST[0] DCL TEMP[0] DCL TEMP[1..3], LOCAL IMM[0] FLT32 { 1.0000, 0.0010, 0.4545, 0.0000} 0: MOV TEMP[0], IN[0] 1: MAD TEMP[0].y, IN[0], CONST[2].xxxx, CONST[2].yyyy 2: MOV TEMP[1].w, IMM[0].xxxx 3: MUL TEMP[2].xy, TEMP[0].xyyy, CONST[0].xyyy 4: MOV TEMP[2].xy, TEMP[2].xyyy 5: TEX TEMP[2].xyz, TEMP[2], SAMP[0], RECT 6: MAX TEMP[2].xyz, IMM[0].yyyy, TEMP[2].xyzz 7: POW TEMP[3].x, TEMP[2].xxxx, IMM[0].zzzz 8: POW TEMP[3].y, TEMP[2].yyyy, IMM[0].zzzz 9: POW TEMP[3].z, TEMP[2].zzzz, IMM[0].zzzz 10: MOV TEMP[1].xyz, TEMP[3].xyzx 11: MOV OUT[0], TEMP[1] 12: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %22 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0 %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0 %24 = call float @llvm.SI.load.const(<16 x i8> %23, i32 0) %25 = call float @llvm.SI.load.const(<16 x i8> %23, i32 4) %26 = call float @llvm.SI.load.const(<16 x i8> %23, i32 32) %27 = call float @llvm.SI.load.const(<16 x i8> %23, i32 36) %28 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0 %29 = load <32 x i8> addrspace(2)* %28, !tbaa !0 %30 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0 %31 = load <16 x i8> addrspace(2)* %30, !tbaa !0 %32 = fmul float %15, %26 %33 = fadd float %32, %27 %34 = fmul float %14, %24 %35 = fmul float %33, %25 %36 = bitcast float %34 to i32 %37 = bitcast float %35 to i32 %38 = insertelement <2 x i32> undef, i32 %36, i32 0 %39 = insertelement <2 x i32> %38, i32 %37, i32 1 %40 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %39, <32 x i8> %29, <16 x i8> %31, i32 5) %41 = extractelement <4 x float> %40, i32 0 %42 = extractelement <4 x float> %40, i32 1 %43 = extractelement <4 x float> %40, i32 2 %44 = fcmp uge float 0x3F50624DE0000000, %41 %45 = select i1 %44, float 0x3F50624DE0000000, float %41 %46 = fcmp uge float 0x3F50624DE0000000, %42 %47 = select i1 %46, float 0x3F50624DE0000000, float %42 %48 = fcmp uge float 0x3F50624DE0000000, %43 %49 = select i1 %48, float 0x3F50624DE0000000, float %43 %50 = call float @llvm.pow.f32(float %45, float 0x3FDD1745C0000000) %51 = call float @llvm.pow.f32(float %47, float 0x3FDD1745C0000000) %52 = call float @llvm.pow.f32(float %49, float 0x3FDD1745C0000000) %53 = call i32 @llvm.SI.packf16(float %50, float %51) %54 = bitcast i32 %53 to float %55 = call i32 @llvm.SI.packf16(float %52, float 1.000000e+00) %56 = bitcast i32 %55 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %54, float %56, float %54, float %56) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1 ; Function Attrs: nounwind readonly declare float @llvm.pow.f32(float, float) #2 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } attributes #2 = { nounwind readonly } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_LOAD_DWORDX4 s[8:11], s[0:1], 0 ; C0840100 S_WAITCNT lgkmcnt(0) ; BF8C007F S_BUFFER_LOAD_DWORD s0, s[8:11], 8 ; C2000908 S_BUFFER_LOAD_DWORD s1, s[8:11], 9 ; C2008909 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v0, s1 ; 7E000201 V_MAD_F32 v0, v3, s0, v0, 0, 0, 0, 0 ; D2820000 04000103 S_BUFFER_LOAD_DWORD s0, s[8:11], 1 ; C2000901 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v1, s0, v0 ; 10020000 S_BUFFER_LOAD_DWORD s0, s[8:11], 0 ; C2000900 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v0, s0, v2 ; 10000400 S_LOAD_DWORDX4 s[0:3], s[2:3], 0 ; C0800300 S_LOAD_DWORDX8 s[4:11], s[4:5], 0 ; C0C20500 S_WAITCNT lgkmcnt(0) ; BF8C007F IMAGE_SAMPLE v[0:2], 7, -1, 0, 0, 0, 0, 0, 0, v[0:1], s[4:11], s[0:3] ; F0801700 00010000 S_WAITCNT vmcnt(0) ; BF8C0770 V_CMP_U_F32_e64 s[0:1], v1, v1, 0, 0, 0, 0 ; D0100000 02020301 V_MOV_B32_e32 v3, 1.000000e-03 ; 7E0602FF 3A83126F V_CMP_LE_F32_e64 s[2:3], v1, v3, 0, 0, 0, 0 ; D0060002 02020701 S_OR_B64 s[0:1], s[2:3], s[0:1] ; 88800002 V_CNDMASK_B32_e64 v4, v1, v3, s[0:1], 0, 0, 0, 0 ; D2000004 00020701 V_LOG_F32_e32 v4, v4 ; 7E084F04 V_MUL_LEGACY_F32_e32 v4, 4.545454e-01, v4 ; 0E0808FF 3EE8BA2E V_EXP_F32_e32 v4, v4 ; 7E084B04 V_CMP_U_F32_e64 s[0:1], v0, v0, 0, 0, 0, 0 ; D0100000 02020100 V_CMP_LE_F32_e64 s[2:3], v0, v3, 0, 0, 0, 0 ; D0060002 02020700 S_OR_B64 s[0:1], s[2:3], s[0:1] ; 88800002 V_CNDMASK_B32_e64 v5, v0, v3, s[0:1], 0, 0, 0, 0 ; D2000005 00020700 V_LOG_F32_e32 v5, v5 ; 7E0A4F05 V_MUL_LEGACY_F32_e32 v5, 4.545454e-01, v5 ; 0E0A0AFF 3EE8BA2E V_EXP_F32_e32 v5, v5 ; 7E0A4B05 V_CVT_PKRTZ_F16_F32_e32 v4, v5, v4 ; 5E080905 V_CMP_U_F32_e64 s[0:1], v2, v2, 0, 0, 0, 0 ; D0100000 02020502 V_CMP_LE_F32_e64 s[2:3], v2, v3, 0, 0, 0, 0 ; D0060002 02020702 S_OR_B64 s[0:1], s[2:3], s[0:1] ; 88800002 V_CNDMASK_B32_e64 v0, v2, v3, s[0:1], 0, 0, 0, 0 ; D2000000 00020702 V_LOG_F32_e32 v0, v0 ; 7E004F00 V_MUL_LEGACY_F32_e32 v0, 4.545454e-01, v0 ; 0E0000FF 3EE8BA2E V_EXP_F32_e32 v0, v0 ; 7E004B00 V_CVT_PKRTZ_F16_F32_e64 v0, v0, 1.000000e+00, 0, 0, 0, 0 ; D25E0000 0201E500 EXP 15, 0, 1, 1, 1, v4, v0, v4, v0 ; F8001C0F 00040004 S_ENDPGM ; BF810000 VERT DCL IN[0] DCL OUT[0], POSITION DCL TEMP[0], LOCAL IMM[0] FLT32 { 1.0000, 0.0000, 0.0000, 0.0000} 0: MOV TEMP[0].w, IMM[0].xxxx 1: MOV TEMP[0].xyz, IN[0].xyzx 2: MOV OUT[0], TEMP[0] 3: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 0 %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0 %12 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %11, i32 0, i32 %6) %13 = extractelement <4 x float> %12, i32 0 %14 = extractelement <4 x float> %12, i32 1 %15 = extractelement <4 x float> %12, i32 2 call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %13, float %14, float %15, float 1.000000e+00) ret void } ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_LOAD_DWORDX4 s[0:3], s[8:9], 0 ; C0800900 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[0:3], s[0:3][v0] + 0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80000000 V_MOV_B32_e32 v4, 1.000000e+00 ; 7E0802F2 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 12, 0, 1, 0, v0, v1, v2, v4 ; F80008CF 04020100 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[20], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL CONST[0..1] DCL CONST[3..16] DCL CONST[1][0..96] DCL CONST[2][0..68] DCL TEMP[0..6], LOCAL IMM[0] FLT32 { 0.5000, 2.0000, -1.0000, -1523613696.0000} IMM[1] FLT32 { -0.0000, 400000.0000, 0.0000, 177.5000} IMM[2] FLT32 { 0.0000, 0.4123, 0.3579, 0.7000} IMM[3] FLT32 { 0.0003, 0.1000, 0.7341, 0.4325} IMM[4] FLT32 { 0.9000, 0.0020, 0.2141, 0.9246} IMM[5] FLT32 { 0.3000, 0.4000, 3.0000, 1.4000} IMM[6] FLT32 { 1.0000, 0.0000, 0.0000, 0.0000} 0: MAD TEMP[0].xy, IN[0].xyyy, IMM[0].xxxx, IMM[0].xxxx 1: ADD TEMP[0].xy, CONST[6].xyyy, TEMP[0].xyyy 2: RCP TEMP[1].x, CONST[7].xxxx 3: MUL TEMP[0].xy, TEMP[0].xyyy, TEMP[1].xxxx 4: MAD TEMP[0].xy, TEMP[0].xyyy, IMM[0].yyyy, IMM[0].zzzz 5: MAD TEMP[1].xyz, CONST[4].xyzz, TEMP[0].xxxx, CONST[3].xyzz 6: MAD TEMP[0].xyz, CONST[5].xyzz, TEMP[0].yyyy, TEMP[1].xyzz 7: DP3 TEMP[1].x, TEMP[0].xyzz, TEMP[0].xyzz 8: RSQ TEMP[1].x, TEMP[1].xxxx 9: MUL TEMP[0].xyz, TEMP[0].xyzz, TEMP[1].xxxx 10: DP3 TEMP[1].x, TEMP[0].xyzz, IMM[1].xyxx 11: DP3 TEMP[2].x, TEMP[0].xyzz, TEMP[0].xyzz 12: MUL TEMP[2].x, TEMP[2].xxxx, IMM[0].wwww 13: MAD TEMP[2].x, TEMP[1].xxxx, TEMP[1].xxxx, -TEMP[2].xxxx 14: RSQ TEMP[3].x, TEMP[2].xxxx 15: MUL TEMP[3].x, TEMP[3].xxxx, TEMP[2].xxxx 16: CMP TEMP[3].x, -TEMP[2].xxxx, TEMP[3].xxxx, IMM[1].zzzz 17: ADD TEMP[1].x, -TEMP[1].xxxx, TEMP[3].xxxx 18: MUL TEMP[1].xz, TEMP[1].xxxx, TEMP[0].xyzz 19: MUL TEMP[2].x, IMM[1].wwww, CONST[15].xxxx 20: MUL TEMP[2].xy, CONST[14].xyyy, TEMP[2].xxxx 21: MAD TEMP[3].xy, TEMP[1].xzzz, IMM[2].xxxx, IMM[2].yzzz 22: MAD TEMP[3].xy, TEMP[2].xyyy, IMM[2].xxxx, TEMP[3].xyyy 23: MOV TEMP[3].xy, TEMP[3].xyyy 24: TEX TEMP[3].xyz, TEMP[3], SAMP[0], 2D 25: ADD TEMP[4].x, IMM[0].xxxx, CONST[16].xxxx 26: ADD TEMP[5].x, TEMP[3].xxxx, -TEMP[4].xxxx 27: ADD TEMP[6].x, IMM[2].wwww, CONST[16].xxxx 28: ADD TEMP[4].x, TEMP[6].xxxx, -TEMP[4].xxxx 29: RCP TEMP[4].x, TEMP[4].xxxx 30: MUL_SAT TEMP[4].x, TEMP[5].xxxx, TEMP[4].xxxx 31: MUL TEMP[3].xy, TEMP[3].yzzz, IMM[3].yyyy 32: MAD TEMP[3].xy, TEMP[1].xzzz, IMM[3].xxxx, TEMP[3].xyyy 33: ADD TEMP[3].xy, TEMP[3].xyyy, IMM[3].zwww 34: MAD TEMP[3].xy, TEMP[2].xyyy, IMM[3].xxxx, TEMP[3].xyyy 35: MOV TEMP[3].xy, TEMP[3].xyyy 36: TEX TEMP[3].x, TEMP[3], SAMP[0], 2D 37: MAD TEMP[1].xy, TEMP[1].xzzz, IMM[4].yyyy, IMM[4].zwww 38: MAD TEMP[1].xy, TEMP[2].xyyy, IMM[4].yyyy, TEMP[1].xyyy 39: MOV TEMP[1].xy, TEMP[1].xyyy 40: TEX TEMP[1].x, TEMP[1], SAMP[0], 2D 41: MAD TEMP[1].x, TEMP[1].xxxx, IMM[5].xxxx, IMM[5].yyyy 42: MAD TEMP[1].x, TEMP[3].xxxx, IMM[4].xxxx, TEMP[1].xxxx 43: MUL TEMP[2].x, IMM[0].yyyy, TEMP[4].xxxx 44: ADD TEMP[2].x, IMM[5].zzzz, -TEMP[2].xxxx 45: MUL TEMP[2].x, TEMP[4].xxxx, TEMP[2].xxxx 46: MUL TEMP[2].x, TEMP[4].xxxx, TEMP[2].xxxx 47: MUL TEMP[1].x, TEMP[1].xxxx, TEMP[2].xxxx 48: MOV_SAT TEMP[1].x, TEMP[1].xxxx 49: POW TEMP[1].x, TEMP[1].xxxx, IMM[4].xxxx 50: DP3_SAT TEMP[2].x, TEMP[0].xyzz, CONST[8].xyzz 51: POW TEMP[2].x, TEMP[2].xxxx, CONST[10].xxxx 52: MOV_SAT TEMP[2].x, TEMP[2].xxxx 53: MUL TEMP[2].xyz, CONST[9].xyzz, TEMP[2].xxxx 54: ADD TEMP[3].x, IMM[5].wwww, -TEMP[1].xxxx 55: ADD_SAT TEMP[0].x, IMM[6].xxxx, -TEMP[0].yyyy 56: POW TEMP[0].x, TEMP[0].xxxx, IMM[5].zzzz 57: LRP TEMP[0].xyz, TEMP[0].xxxx, CONST[12].xyzz, CONST[11].xyzz 58: LRP TEMP[0].xyz, TEMP[1].xxxx, CONST[13].xyzz, TEMP[0].xyzz 59: MAD TEMP[0].xyz, TEMP[2].xyzz, TEMP[3].xxxx, TEMP[0].xyzz 60: MOV TEMP[0].w, TEMP[1].xxxx 61: MOV OUT[0], TEMP[0] 62: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %22 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0 %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0 %24 = call float @llvm.SI.load.const(<16 x i8> %23, i32 48) %25 = call float @llvm.SI.load.const(<16 x i8> %23, i32 52) %26 = call float @llvm.SI.load.const(<16 x i8> %23, i32 56) %27 = call float @llvm.SI.load.const(<16 x i8> %23, i32 64) %28 = call float @llvm.SI.load.const(<16 x i8> %23, i32 68) %29 = call float @llvm.SI.load.const(<16 x i8> %23, i32 72) %30 = call float @llvm.SI.load.const(<16 x i8> %23, i32 80) %31 = call float @llvm.SI.load.const(<16 x i8> %23, i32 84) %32 = call float @llvm.SI.load.const(<16 x i8> %23, i32 88) %33 = call float @llvm.SI.load.const(<16 x i8> %23, i32 96) %34 = call float @llvm.SI.load.const(<16 x i8> %23, i32 100) %35 = call float @llvm.SI.load.const(<16 x i8> %23, i32 112) %36 = call float @llvm.SI.load.const(<16 x i8> %23, i32 128) %37 = call float @llvm.SI.load.const(<16 x i8> %23, i32 132) %38 = call float @llvm.SI.load.const(<16 x i8> %23, i32 136) %39 = call float @llvm.SI.load.const(<16 x i8> %23, i32 144) %40 = call float @llvm.SI.load.const(<16 x i8> %23, i32 148) %41 = call float @llvm.SI.load.const(<16 x i8> %23, i32 152) %42 = call float @llvm.SI.load.const(<16 x i8> %23, i32 160) %43 = call float @llvm.SI.load.const(<16 x i8> %23, i32 176) %44 = call float @llvm.SI.load.const(<16 x i8> %23, i32 180) %45 = call float @llvm.SI.load.const(<16 x i8> %23, i32 184) %46 = call float @llvm.SI.load.const(<16 x i8> %23, i32 192) %47 = call float @llvm.SI.load.const(<16 x i8> %23, i32 196) %48 = call float @llvm.SI.load.const(<16 x i8> %23, i32 200) %49 = call float @llvm.SI.load.const(<16 x i8> %23, i32 208) %50 = call float @llvm.SI.load.const(<16 x i8> %23, i32 212) %51 = call float @llvm.SI.load.const(<16 x i8> %23, i32 216) %52 = call float @llvm.SI.load.const(<16 x i8> %23, i32 224) %53 = call float @llvm.SI.load.const(<16 x i8> %23, i32 228) %54 = call float @llvm.SI.load.const(<16 x i8> %23, i32 240) %55 = call float @llvm.SI.load.const(<16 x i8> %23, i32 256) %56 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0 %57 = load <32 x i8> addrspace(2)* %56, !tbaa !0 %58 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0 %59 = load <16 x i8> addrspace(2)* %58, !tbaa !0 %60 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %7) %61 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %7) %62 = fmul float %60, 5.000000e-01 %63 = fadd float %62, 5.000000e-01 %64 = fmul float %61, 5.000000e-01 %65 = fadd float %64, 5.000000e-01 %66 = fadd float %33, %63 %67 = fadd float %34, %65 %68 = fdiv float 1.000000e+00, %35 %69 = fmul float %66, %68 %70 = fmul float %67, %68 %71 = fmul float %69, 2.000000e+00 %72 = fadd float %71, -1.000000e+00 %73 = fmul float %70, 2.000000e+00 %74 = fadd float %73, -1.000000e+00 %75 = fmul float %27, %72 %76 = fadd float %75, %24 %77 = fmul float %28, %72 %78 = fadd float %77, %25 %79 = fmul float %29, %72 %80 = fadd float %79, %26 %81 = fmul float %30, %74 %82 = fadd float %81, %76 %83 = fmul float %31, %74 %84 = fadd float %83, %78 %85 = fmul float %32, %74 %86 = fadd float %85, %80 %87 = fmul float %82, %82 %88 = fmul float %84, %84 %89 = fadd float %88, %87 %90 = fmul float %86, %86 %91 = fadd float %89, %90 %92 = call float @llvm.AMDGPU.rsq(float %91) %93 = fmul float %82, %92 %94 = fmul float %84, %92 %95 = fmul float %86, %92 %96 = fmul float %93, -0.000000e+00 %97 = fmul float %94, 4.000000e+05 %98 = fadd float %97, %96 %99 = fmul float %95, -0.000000e+00 %100 = fadd float %98, %99 %101 = fmul float %93, %93 %102 = fmul float %94, %94 %103 = fadd float %102, %101 %104 = fmul float %95, %95 %105 = fadd float %103, %104 %106 = fmul float %105, 0xC1D6B42000000000 %107 = fsub float -0.000000e+00, %106 %108 = fmul float %100, %100 %109 = fadd float %108, %107 %110 = call float @llvm.AMDGPU.rsq(float %109) %111 = fmul float %110, %109 %112 = fsub float -0.000000e+00, %109 %113 = call float @llvm.AMDGPU.cndlt(float %112, float %111, float 0.000000e+00) %114 = fsub float -0.000000e+00, %100 %115 = fadd float %114, %113 %116 = fmul float %115, %93 %117 = fmul float %115, %95 %118 = fmul float 1.775000e+02, %54 %119 = fmul float %52, %118 %120 = fmul float %53, %118 %121 = fmul float %116, 0x3F06AA7440000000 %122 = fadd float %121, 0x3FDA635620000000 %123 = fmul float %117, 0x3F06AA7440000000 %124 = fadd float %123, 0x3FD6E78680000000 %125 = fmul float %119, 0x3F06AA7440000000 %126 = fadd float %125, %122 %127 = fmul float %120, 0x3F06AA7440000000 %128 = fadd float %127, %124 %129 = bitcast float %126 to i32 %130 = bitcast float %128 to i32 %131 = insertelement <2 x i32> undef, i32 %129, i32 0 %132 = insertelement <2 x i32> %131, i32 %130, i32 1 %133 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %132, <32 x i8> %57, <16 x i8> %59, i32 2) %134 = extractelement <4 x float> %133, i32 0 %135 = extractelement <4 x float> %133, i32 1 %136 = extractelement <4 x float> %133, i32 2 %137 = fadd float 5.000000e-01, %55 %138 = fsub float -0.000000e+00, %137 %139 = fadd float %134, %138 %140 = fadd float 0x3FE6666660000000, %55 %141 = fsub float -0.000000e+00, %137 %142 = fadd float %140, %141 %143 = fdiv float 1.000000e+00, %142 %144 = fmul float %139, %143 %145 = call float @llvm.AMDIL.clamp.(float %144, float 0.000000e+00, float 1.000000e+00) %146 = fmul float %135, 0x3FB99999A0000000 %147 = fmul float %136, 0x3FB99999A0000000 %148 = fmul float %116, 0x3F34BD3EE0000000 %149 = fadd float %148, %146 %150 = fmul float %117, 0x3F34BD3EE0000000 %151 = fadd float %150, %147 %152 = fadd float %149, 0x3FE77E1540000000 %153 = fadd float %151, 0x3FDBAE6EA0000000 %154 = fmul float %119, 0x3F34BD3EE0000000 %155 = fadd float %154, %152 %156 = fmul float %120, 0x3F34BD3EE0000000 %157 = fadd float %156, %153 %158 = bitcast float %155 to i32 %159 = bitcast float %157 to i32 %160 = insertelement <2 x i32> undef, i32 %158, i32 0 %161 = insertelement <2 x i32> %160, i32 %159, i32 1 %162 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %161, <32 x i8> %57, <16 x i8> %59, i32 2) %163 = extractelement <4 x float> %162, i32 0 %164 = fmul float %116, 0x3F60624DE0000000 %165 = fadd float %164, 0x3FCB686A40000000 %166 = fmul float %117, 0x3F60624DE0000000 %167 = fadd float %166, 0x3FED966CC0000000 %168 = fmul float %119, 0x3F60624DE0000000 %169 = fadd float %168, %165 %170 = fmul float %120, 0x3F60624DE0000000 %171 = fadd float %170, %167 %172 = bitcast float %169 to i32 %173 = bitcast float %171 to i32 %174 = insertelement <2 x i32> undef, i32 %172, i32 0 %175 = insertelement <2 x i32> %174, i32 %173, i32 1 %176 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %175, <32 x i8> %57, <16 x i8> %59, i32 2) %177 = extractelement <4 x float> %176, i32 0 %178 = fmul float %177, 0x3FD3333340000000 %179 = fadd float %178, 0x3FD99999A0000000 %180 = fmul float %163, 0x3FECCCCCC0000000 %181 = fadd float %180, %179 %182 = fmul float 2.000000e+00, %145 %183 = fsub float -0.000000e+00, %182 %184 = fadd float 3.000000e+00, %183 %185 = fmul float %145, %184 %186 = fmul float %145, %185 %187 = fmul float %181, %186 %188 = call float @llvm.AMDIL.clamp.(float %187, float 0.000000e+00, float 1.000000e+00) %189 = call float @llvm.pow.f32(float %188, float 0x3FECCCCCC0000000) %190 = fmul float %93, %36 %191 = fmul float %94, %37 %192 = fadd float %191, %190 %193 = fmul float %95, %38 %194 = fadd float %192, %193 %195 = call float @llvm.AMDIL.clamp.(float %194, float 0.000000e+00, float 1.000000e+00) %196 = call float @llvm.pow.f32(float %195, float %42) %197 = call float @llvm.AMDIL.clamp.(float %196, float 0.000000e+00, float 1.000000e+00) %198 = fmul float %39, %197 %199 = fmul float %40, %197 %200 = fmul float %41, %197 %201 = fsub float -0.000000e+00, %189 %202 = fadd float 0x3FF6666660000000, %201 %203 = fsub float -0.000000e+00, %94 %204 = fadd float 1.000000e+00, %203 %205 = call float @llvm.AMDIL.clamp.(float %204, float 0.000000e+00, float 1.000000e+00) %206 = call float @llvm.pow.f32(float %205, float 3.000000e+00) %207 = call float @llvm.AMDGPU.lrp(float %206, float %46, float %43) %208 = call float @llvm.AMDGPU.lrp(float %206, float %47, float %44) %209 = call float @llvm.AMDGPU.lrp(float %206, float %48, float %45) %210 = call float @llvm.AMDGPU.lrp(float %189, float %49, float %207) %211 = call float @llvm.AMDGPU.lrp(float %189, float %50, float %208) %212 = call float @llvm.AMDGPU.lrp(float %189, float %51, float %209) %213 = fmul float %198, %202 %214 = fadd float %213, %210 %215 = fmul float %199, %202 %216 = fadd float %215, %211 %217 = fmul float %200, %202 %218 = fadd float %217, %212 %219 = call i32 @llvm.SI.packf16(float %214, float %216) %220 = bitcast i32 %219 to float %221 = call i32 @llvm.SI.packf16(float %218, float %189) %222 = bitcast i32 %221 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %220, float %222, float %220, float %222) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: readnone declare float @llvm.AMDGPU.rsq(float) #2 ; Function Attrs: readnone declare float @llvm.AMDGPU.cndlt(float, float, float) #2 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1 ; Function Attrs: readnone declare float @llvm.AMDIL.clamp.(float, float, float) #2 ; Function Attrs: nounwind readonly declare float @llvm.pow.f32(float, float) #3 ; Function Attrs: readnone declare float @llvm.AMDGPU.lrp(float, float, float) #2 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } attributes #3 = { nounwind readonly } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s9 ; BEFC0309 V_INTERP_P1_F32 v2, v0, 0, 0, [m0] ; C8080000 V_INTERP_P2_F32 v2, [v2], v1, 0, 0, [m0] ; C8090001 V_MAD_F32 v2, v2, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0 ; D2820002 03C1E102 S_LOAD_DWORDX4 s[12:15], s[0:1], 0 ; C0860100 S_WAITCNT lgkmcnt(0) ; BF8C007F S_BUFFER_LOAD_DWORD s0, s[12:15], 24 ; C2000D18 S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v2, s0, v2 ; 06040400 S_BUFFER_LOAD_DWORD s0, s[12:15], 28 ; C2000D1C S_WAITCNT lgkmcnt(0) ; BF8C007F V_RCP_F32_e32 v3, s0 ; 7E065400 V_MUL_F32_e32 v4, v2, v3 ; 10080702 V_MAD_F32 v2, v2, v3, v4, 0, 0, 0, 0 ; D2820002 04120702 V_ADD_F32_e32 v2, -1.000000e+00, v2 ; 060404F3 S_BUFFER_LOAD_DWORD s0, s[12:15], 17 ; C2000D11 S_BUFFER_LOAD_DWORD s1, s[12:15], 13 ; C2008D0D S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v4, s1 ; 7E080201 V_MAD_F32 v4, s0, v2, v4, 0, 0, 0, 0 ; D2820004 04120400 V_INTERP_P1_F32 v5, v0, 1, 0, [m0] ; C8140100 V_INTERP_P2_F32 v5, [v5], v1, 1, 0, [m0] ; C8150101 V_MAD_F32 v0, v5, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0 ; D2820000 03C1E105 S_BUFFER_LOAD_DWORD s0, s[12:15], 25 ; C2000D19 S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v0, s0, v0 ; 06000000 V_MUL_F32_e32 v1, v0, v3 ; 10020700 V_MAD_F32 v0, v0, v3, v1, 0, 0, 0, 0 ; D2820000 04060700 V_ADD_F32_e32 v0, -1.000000e+00, v0 ; 060000F3 S_BUFFER_LOAD_DWORD s0, s[12:15], 21 ; C2000D15 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v1, s0, v0, v4, 0, 0, 0, 0 ; D2820001 04120000 S_BUFFER_LOAD_DWORD s0, s[12:15], 16 ; C2000D10 S_BUFFER_LOAD_DWORD s1, s[12:15], 12 ; C2008D0C S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v3, s1 ; 7E060201 V_MAD_F32 v3, s0, v2, v3, 0, 0, 0, 0 ; D2820003 040E0400 S_BUFFER_LOAD_DWORD s0, s[12:15], 20 ; C2000D14 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v3, s0, v0, v3, 0, 0, 0, 0 ; D2820003 040E0000 V_MUL_F32_e32 v4, v3, v3 ; 10080703 V_MAD_F32 v4, v1, v1, v4, 0, 0, 0, 0 ; D2820004 04120301 S_BUFFER_LOAD_DWORD s0, s[12:15], 18 ; C2000D12 S_BUFFER_LOAD_DWORD s1, s[12:15], 14 ; C2008D0E S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v5, s1 ; 7E0A0201 V_MAD_F32 v2, s0, v2, v5, 0, 0, 0, 0 ; D2820002 04160400 S_BUFFER_LOAD_DWORD s0, s[12:15], 22 ; C2000D16 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v0, s0, v0, v2, 0, 0, 0, 0 ; D2820000 040A0000 V_MAD_F32 v2, v0, v0, v4, 0, 0, 0, 0 ; D2820002 04120100 V_RSQ_LEGACY_F32_e32 v2, v2 ; 7E045B02 V_MUL_F32_e32 v1, v1, v2 ; 10020501 V_MUL_F32_e32 v3, v3, v2 ; 10060503 V_MUL_F32_e32 v4, -0.000000e+00, v3 ; 100806FF 80000000 V_MOV_B32_e32 v5, 4.000000e+05 ; 7E0A02FF 48C35000 V_MAD_F32 v4, v1, v5, v4, 0, 0, 0, 0 ; D2820004 04120B01 V_MUL_F32_e32 v0, v0, v2 ; 10000500 V_MOV_B32_e32 v2, -0.000000e+00 ; 7E0402FF 80000000 V_MAD_F32 v2, v0, v2, v4, 0, 0, 0, 0 ; D2820002 04120500 V_MUL_F32_e32 v4, v3, v3 ; 10080703 V_MAD_F32 v4, v1, v1, v4, 0, 0, 0, 0 ; D2820004 04120301 V_MAD_F32 v4, v0, v0, v4, 0, 0, 0, 0 ; D2820004 04120100 V_MUL_F32_e32 v4, 1.523614e+09, v4 ; 100808FF 4EB5A100 V_MAD_F32 v4, v2, v2, v4, 0, 0, 0, 0 ; D2820004 04120502 V_RSQ_LEGACY_F32_e32 v5, v4 ; 7E0A5B04 V_MUL_F32_e32 v5, v5, v4 ; 100A0905 V_XOR_B32_e32 v4, -2147483648, v4 ; 3A0808FF 80000000 V_CMP_GT_F32_e64 s[0:1], 0, v4, 0, 0, 0, 0 ; D0080000 02020880 V_CNDMASK_B32_e64 v4, 0.000000e+00, v5, s[0:1], 0, 0, 0, 0 ; D2000004 00020A80 V_SUB_F32_e32 v2, v4, v2 ; 08040504 V_MUL_F32_e32 v4, v2, v0 ; 10080102 V_MOV_B32_e32 v5, 3.578812e-01 ; 7E0A02FF 3EB73C34 V_MOV_B32_e32 v6, 4.323165e-05 ; 7E0C02FF 383553A2 V_MAD_F32 v5, v4, v6, v5, 0, 0, 0, 0 ; D2820005 04160D04 S_BUFFER_LOAD_DWORD s0, s[12:15], 60 ; C2000D3C V_MOV_B32_e32 v7, 1.775000e+02 ; 7E0E02FF 43318000 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v7, s0, v7 ; 100E0E00 S_BUFFER_LOAD_DWORD s0, s[12:15], 57 ; C2000D39 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v8, s0, v7 ; 10100E00 V_MAD_F32 v10, v8, v6, v5, 0, 0, 0, 0 ; D282000A 04160D08 V_MUL_F32_e32 v2, v2, v3 ; 10040702 V_MOV_B32_e32 v5, 4.123130e-01 ; 7E0A02FF 3ED31AB1 V_MAD_F32 v5, v2, v6, v5, 0, 0, 0, 0 ; D2820005 04160D02 S_BUFFER_LOAD_DWORD s0, s[12:15], 56 ; C2000D38 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v7, s0, v7 ; 100E0E00 V_MAD_F32 v9, v7, v6, v5, 0, 0, 0, 0 ; D2820009 04160D07 S_LOAD_DWORDX4 s[0:3], s[2:3], 0 ; C0800300 S_LOAD_DWORDX8 s[4:11], s[4:5], 0 ; C0C20500 S_WAITCNT lgkmcnt(0) ; BF8C007F IMAGE_SAMPLE v[9:11], 7, 0, 0, 0, 0, 0, 0, 0, v[9:10], s[4:11], s[0:3] ; F0800700 00010909 V_MOV_B32_e32 v5, 1.000000e-01 ; 7E0A02FF 3DCCCCCD S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v6, v11, v5 ; 100C0B0B V_MOV_B32_e32 v12, 3.164557e-04 ; 7E1802FF 39A5E9F7 V_MAD_F32 v6, v4, v12, v6, 0, 0, 0, 0 ; D2820006 041A1904 V_ADD_F32_e32 v6, 4.325215e-01, v6 ; 060C0CFF 3EDD7375 V_MAD_F32 v14, v8, v12, v6, 0, 0, 0, 0 ; D282000E 041A1908 V_MUL_F32_e32 v5, v10, v5 ; 100A0B0A V_MAD_F32 v5, v2, v12, v5, 0, 0, 0, 0 ; D2820005 04161902 V_ADD_F32_e32 v5, 7.341410e-01, v5 ; 060A0AFF 3F3BF0AA V_MAD_F32 v13, v7, v12, v5, 0, 0, 0, 0 ; D282000D 04161907 IMAGE_SAMPLE v5, 1, 0, 0, 0, 0, 0, 0, 0, v[13:14], s[4:11], s[0:3] ; F0800100 0001050D V_MOV_B32_e32 v6, 9.246124e-01 ; 7E0C02FF 3F6CB366 V_MOV_B32_e32 v12, 2.000000e-03 ; 7E1802FF 3B03126F V_MAD_F32 v4, v4, v12, v6, 0, 0, 0, 0 ; D2820004 041A1904 V_MAD_F32 v14, v8, v12, v4, 0, 0, 0, 0 ; D282000E 04121908 V_MOV_B32_e32 v4, 2.141240e-01 ; 7E0802FF 3E5B4352 V_MAD_F32 v2, v2, v12, v4, 0, 0, 0, 0 ; D2820002 04121902 V_MAD_F32 v13, v7, v12, v2, 0, 0, 0, 0 ; D282000D 040A1907 IMAGE_SAMPLE v2, 1, 0, 0, 0, 0, 0, 0, 0, v[13:14], s[4:11], s[0:3] ; F0800100 0001020D V_MOV_B32_e32 v4, 4.000000e-01 ; 7E0802FF 3ECCCCCD V_MOV_B32_e32 v6, 3.000000e-01 ; 7E0C02FF 3E99999A S_WAITCNT vmcnt(0) ; BF8C0770 V_MAD_F32 v2, v2, v6, v4, 0, 0, 0, 0 ; D2820002 04120D02 V_MOV_B32_e32 v4, 9.000000e-01 ; 7E0802FF 3F666666 V_MAD_F32 v2, v5, v4, v2, 0, 0, 0, 0 ; D2820002 040A0905 S_BUFFER_LOAD_DWORD s0, s[12:15], 64 ; C2000D40 S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e64 v4, s0, 5.000000e-01, 0, 0, 0, 0 ; D2060004 0201E000 V_SUB_F32_e32 v5, v9, v4 ; 080A0909 V_MOV_B32_e32 v6, 7.000000e-01 ; 7E0C02FF 3F333333 V_ADD_F32_e32 v6, s0, v6 ; 060C0C00 V_SUB_F32_e32 v4, v6, v4 ; 08080906 V_RCP_F32_e32 v4, v4 ; 7E085504 V_MUL_F32_e32 v4, v5, v4 ; 10080905 V_ADD_F32_e64 v4, 0, v4, 0, 1, 0, 0 ; D2060804 02020880 V_ADD_F32_e32 v5, v4, v4 ; 060A0904 V_SUB_F32_e32 v5, 3.000000e+00, v5 ; 080A0AFF 40400000 V_MUL_F32_e32 v5, v4, v5 ; 100A0B04 V_MUL_F32_e32 v4, v4, v5 ; 10080B04 V_MUL_F32_e32 v2, v2, v4 ; 10040902 V_ADD_F32_e64 v2, 0, v2, 0, 1, 0, 0 ; D2060802 02020480 V_LOG_F32_e32 v2, v2 ; 7E044F02 V_MUL_LEGACY_F32_e32 v2, 9.000000e-01, v2 ; 0E0404FF 3F666666 V_EXP_F32_e32 v2, v2 ; 7E044B02 V_SUB_F32_e32 v4, 1.000000e+00, v2 ; 080804F2 V_SUB_F32_e32 v5, 1.000000e+00, v1 ; 080A02F2 V_ADD_F32_e64 v5, 0, v5, 0, 1, 0, 0 ; D2060805 02020A80 V_LOG_F32_e32 v5, v5 ; 7E0A4F05 V_MUL_LEGACY_F32_e32 v5, 3.000000e+00, v5 ; 0E0A0AFF 40400000 V_EXP_F32_e32 v5, v5 ; 7E0A4B05 V_SUB_F32_e32 v6, 1.000000e+00, v5 ; 080C0AF2 S_BUFFER_LOAD_DWORD s0, s[12:15], 45 ; C2000D2D S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v7, s0, v6 ; 100E0C00 S_BUFFER_LOAD_DWORD s0, s[12:15], 49 ; C2000D31 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v7, v5, s0, v7, 0, 0, 0, 0 ; D2820007 041C0105 V_MUL_F32_e32 v7, v4, v7 ; 100E0F04 S_BUFFER_LOAD_DWORD s0, s[12:15], 53 ; C2000D35 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v7, v2, s0, v7, 0, 0, 0, 0 ; D2820007 041C0102 V_SUB_F32_e32 v8, 1.400000e+00, v2 ; 081004FF 3FB33333 S_BUFFER_LOAD_DWORD s0, s[12:15], 32 ; C2000D20 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v3, s0, v3 ; 10060600 S_BUFFER_LOAD_DWORD s0, s[12:15], 33 ; C2000D21 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v1, v1, s0, v3, 0, 0, 0, 0 ; D2820001 040C0101 S_BUFFER_LOAD_DWORD s0, s[12:15], 34 ; C2000D22 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v0, v0, s0, v1, 0, 0, 0, 0 ; D2820000 04040100 V_ADD_F32_e64 v0, 0, v0, 0, 1, 0, 0 ; D2060800 02020080 V_LOG_F32_e32 v0, v0 ; 7E004F00 S_BUFFER_LOAD_DWORD s0, s[12:15], 40 ; C2000D28 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_LEGACY_F32_e32 v0, s0, v0 ; 0E000000 V_EXP_F32_e32 v0, v0 ; 7E004B00 V_ADD_F32_e64 v0, 0, v0, 0, 1, 0, 0 ; D2060800 02020080 S_BUFFER_LOAD_DWORD s0, s[12:15], 37 ; C2000D25 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v1, s0, v0 ; 10020000 V_MAD_F32 v1, v1, v8, v7, 0, 0, 0, 0 ; D2820001 041E1101 S_BUFFER_LOAD_DWORD s0, s[12:15], 44 ; C2000D2C S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v3, s0, v6 ; 10060C00 S_BUFFER_LOAD_DWORD s0, s[12:15], 48 ; C2000D30 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v3, v5, s0, v3, 0, 0, 0, 0 ; D2820003 040C0105 V_MUL_F32_e32 v3, v4, v3 ; 10060704 S_BUFFER_LOAD_DWORD s0, s[12:15], 52 ; C2000D34 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v3, v2, s0, v3, 0, 0, 0, 0 ; D2820003 040C0102 S_BUFFER_LOAD_DWORD s0, s[12:15], 36 ; C2000D24 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v7, s0, v0 ; 100E0000 V_MAD_F32 v3, v7, v8, v3, 0, 0, 0, 0 ; D2820003 040E1107 V_CVT_PKRTZ_F16_F32_e32 v1, v3, v1 ; 5E020303 S_BUFFER_LOAD_DWORD s0, s[12:15], 46 ; C2000D2E S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v3, s0, v6 ; 10060C00 S_BUFFER_LOAD_DWORD s0, s[12:15], 50 ; C2000D32 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v3, v5, s0, v3, 0, 0, 0, 0 ; D2820003 040C0105 V_MUL_F32_e32 v3, v4, v3 ; 10060704 S_BUFFER_LOAD_DWORD s0, s[12:15], 54 ; C2000D36 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v3, v2, s0, v3, 0, 0, 0, 0 ; D2820003 040C0102 S_BUFFER_LOAD_DWORD s0, s[12:15], 38 ; C2000D26 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v0, s0, v0 ; 10000000 V_MAD_F32 v0, v0, v8, v3, 0, 0, 0, 0 ; D2820000 040E1100 V_CVT_PKRTZ_F16_F32_e32 v0, v0, v2 ; 5E000500 EXP 15, 0, 1, 1, 1, v1, v0, v1, v0 ; F8001C0F 00010001 S_ENDPGM ; BF810000 VERT DCL IN[0] DCL OUT[0], POSITION DCL OUT[1], GENERIC[20] DCL CONST[1][0..96] DCL CONST[2][0..68] DCL TEMP[0..1], LOCAL IMM[0] FLT32 { 1.0000, 0.0000, 0.0000, 0.0000} 0: MOV TEMP[0].w, IMM[0].xxxx 1: MOV TEMP[0].xyz, IN[0].xyzx 2: MOV TEMP[1].xy, IN[0].xyxx 3: MOV OUT[1], TEMP[1] 4: MOV OUT[0], TEMP[0] 5: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 0 %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0 %12 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %11, i32 0, i32 %6) %13 = extractelement <4 x float> %12, i32 0 %14 = extractelement <4 x float> %12, i32 1 %15 = extractelement <4 x float> %12, i32 2 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %13, float %14, float 0.000000e+00, float 0.000000e+00) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %13, float %14, float %15, float 1.000000e+00) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_LOAD_DWORDX4 s[0:3], s[8:9], 0 ; C0800900 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[0:3], s[0:3][v0] + 0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80000000 V_MOV_B32_e32 v4, 0.000000e+00 ; 7E080280 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 32, 0, 0, 0, v0, v1, v4, v4 ; F800020F 04040100 S_WAITCNT expcnt(0) ; BF8C070F V_MOV_B32_e32 v4, 1.000000e+00 ; 7E0802F2 EXP 15, 12, 0, 1, 0, v0, v1, v2, v4 ; F80008CF 04020100 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[20], PERSPECTIVE DCL OUT[0], COLOR DCL CONST[0] DCL TEMP[0], LOCAL IMM[0] FLT32 { 1.0000, 0.5000, 1.4427, 0.0000} 0: ADD TEMP[0].x, IN[0].xxxx, IMM[0].xxxx 1: MUL TEMP[0].x, TEMP[0].xxxx, IMM[0].yyyy 2: MOV_SAT TEMP[0].x, TEMP[0].xxxx 3: MUL TEMP[0].x, CONST[0].xxxx, TEMP[0].xxxx 4: MUL TEMP[0].x, TEMP[0].xxxx, IMM[0].zzzz 5: EX2 TEMP[0].x, TEMP[0].xxxx 6: MOV OUT[0], TEMP[0].xxxx 7: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %22 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0 %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0 %24 = call float @llvm.SI.load.const(<16 x i8> %23, i32 0) %25 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %7) %26 = fadd float %25, 1.000000e+00 %27 = fmul float %26, 5.000000e-01 %28 = call float @llvm.AMDIL.clamp.(float %27, float 0.000000e+00, float 1.000000e+00) %29 = fmul float %24, %28 %30 = fmul float %29, 0x3FF7154760000000 %31 = call float @llvm.AMDIL.exp.(float %30) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %31, float %31, float %31, float %31) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: readnone declare float @llvm.AMDIL.clamp.(float, float, float) #2 ; Function Attrs: readnone declare float @llvm.AMDIL.exp.(float) #2 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s9 ; BEFC0309 V_INTERP_P1_F32 v2, v0, 0, 0, [m0] ; C8080000 V_INTERP_P2_F32 v2, [v2], v1, 0, 0, [m0] ; C8090001 V_ADD_F32_e32 v0, 1.000000e+00, v2 ; 060004F2 V_MUL_F32_e32 v0, 5.000000e-01, v0 ; 100000F0 V_ADD_F32_e64 v0, 0, v0, 0, 1, 0, 0 ; D2060800 02020080 S_LOAD_DWORDX4 s[0:3], s[0:1], 0 ; C0800100 S_WAITCNT lgkmcnt(0) ; BF8C007F S_BUFFER_LOAD_DWORD s0, s[0:3], 0 ; C2000100 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v0, s0, v0 ; 10000000 V_MUL_F32_e32 v0, 1.442695e+00, v0 ; 100000FF 3FB8AA3B V_EXP_F32_e32 v0, v0 ; 7E004B00 EXP 15, 0, 0, 1, 1, v0, v0, v0, v0 ; F800180F 00000000 S_ENDPGM ; BF810000 VERT DCL IN[0] DCL OUT[0], POSITION DCL OUT[1], GENERIC[20] DCL CONST[0..7] DCL TEMP[0..2], LOCAL 0: MUL TEMP[0], CONST[0], CONST[6].xxxx 1: MAD TEMP[0], CONST[1], CONST[6].yyyy, TEMP[0] 2: MAD TEMP[0], CONST[2], CONST[6].zzzz, TEMP[0] 3: MAD TEMP[0], CONST[3], CONST[6].wwww, TEMP[0] 4: MUL TEMP[1], CONST[0], CONST[5].xxxx 5: MAD TEMP[1], CONST[1], CONST[5].yyyy, TEMP[1] 6: MAD TEMP[1], CONST[2], CONST[5].zzzz, TEMP[1] 7: MAD TEMP[1], CONST[3], CONST[5].wwww, TEMP[1] 8: MUL TEMP[2], CONST[0], CONST[4].xxxx 9: MAD TEMP[2], CONST[1], CONST[4].yyyy, TEMP[2] 10: MAD TEMP[2], CONST[2], CONST[4].zzzz, TEMP[2] 11: MAD TEMP[2], CONST[3], CONST[4].wwww, TEMP[2] 12: MUL TEMP[2], TEMP[2], IN[0].xxxx 13: MAD TEMP[1], TEMP[1], IN[0].yyyy, TEMP[2] 14: MAD TEMP[0], TEMP[0], IN[0].zzzz, TEMP[1] 15: MUL TEMP[1], CONST[0], CONST[7].xxxx 16: MAD TEMP[1], CONST[1], CONST[7].yyyy, TEMP[1] 17: MAD TEMP[1], CONST[2], CONST[7].zzzz, TEMP[1] 18: MAD TEMP[1], CONST[3], CONST[7].wwww, TEMP[1] 19: ADD TEMP[0], TEMP[0], TEMP[1] 20: MOV TEMP[1].x, TEMP[0].zzzz 21: MOV OUT[1], TEMP[1] 22: MOV OUT[0], TEMP[0] 23: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0 %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0 %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0) %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4) %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8) %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12) %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16) %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20) %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24) %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28) %20 = call float @llvm.SI.load.const(<16 x i8> %11, i32 32) %21 = call float @llvm.SI.load.const(<16 x i8> %11, i32 36) %22 = call float @llvm.SI.load.const(<16 x i8> %11, i32 40) %23 = call float @llvm.SI.load.const(<16 x i8> %11, i32 44) %24 = call float @llvm.SI.load.const(<16 x i8> %11, i32 48) %25 = call float @llvm.SI.load.const(<16 x i8> %11, i32 52) %26 = call float @llvm.SI.load.const(<16 x i8> %11, i32 56) %27 = call float @llvm.SI.load.const(<16 x i8> %11, i32 60) %28 = call float @llvm.SI.load.const(<16 x i8> %11, i32 64) %29 = call float @llvm.SI.load.const(<16 x i8> %11, i32 68) %30 = call float @llvm.SI.load.const(<16 x i8> %11, i32 72) %31 = call float @llvm.SI.load.const(<16 x i8> %11, i32 76) %32 = call float @llvm.SI.load.const(<16 x i8> %11, i32 80) %33 = call float @llvm.SI.load.const(<16 x i8> %11, i32 84) %34 = call float @llvm.SI.load.const(<16 x i8> %11, i32 88) %35 = call float @llvm.SI.load.const(<16 x i8> %11, i32 92) %36 = call float @llvm.SI.load.const(<16 x i8> %11, i32 96) %37 = call float @llvm.SI.load.const(<16 x i8> %11, i32 100) %38 = call float @llvm.SI.load.const(<16 x i8> %11, i32 104) %39 = call float @llvm.SI.load.const(<16 x i8> %11, i32 108) %40 = call float @llvm.SI.load.const(<16 x i8> %11, i32 112) %41 = call float @llvm.SI.load.const(<16 x i8> %11, i32 116) %42 = call float @llvm.SI.load.const(<16 x i8> %11, i32 120) %43 = call float @llvm.SI.load.const(<16 x i8> %11, i32 124) %44 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 0 %45 = load <16 x i8> addrspace(2)* %44, !tbaa !0 %46 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %45, i32 0, i32 %6) %47 = extractelement <4 x float> %46, i32 0 %48 = extractelement <4 x float> %46, i32 1 %49 = extractelement <4 x float> %46, i32 2 %50 = fmul float %12, %36 %51 = fmul float %13, %36 %52 = fmul float %14, %36 %53 = fmul float %15, %36 %54 = fmul float %16, %37 %55 = fadd float %54, %50 %56 = fmul float %17, %37 %57 = fadd float %56, %51 %58 = fmul float %18, %37 %59 = fadd float %58, %52 %60 = fmul float %19, %37 %61 = fadd float %60, %53 %62 = fmul float %20, %38 %63 = fadd float %62, %55 %64 = fmul float %21, %38 %65 = fadd float %64, %57 %66 = fmul float %22, %38 %67 = fadd float %66, %59 %68 = fmul float %23, %38 %69 = fadd float %68, %61 %70 = fmul float %24, %39 %71 = fadd float %70, %63 %72 = fmul float %25, %39 %73 = fadd float %72, %65 %74 = fmul float %26, %39 %75 = fadd float %74, %67 %76 = fmul float %27, %39 %77 = fadd float %76, %69 %78 = fmul float %12, %32 %79 = fmul float %13, %32 %80 = fmul float %14, %32 %81 = fmul float %15, %32 %82 = fmul float %16, %33 %83 = fadd float %82, %78 %84 = fmul float %17, %33 %85 = fadd float %84, %79 %86 = fmul float %18, %33 %87 = fadd float %86, %80 %88 = fmul float %19, %33 %89 = fadd float %88, %81 %90 = fmul float %20, %34 %91 = fadd float %90, %83 %92 = fmul float %21, %34 %93 = fadd float %92, %85 %94 = fmul float %22, %34 %95 = fadd float %94, %87 %96 = fmul float %23, %34 %97 = fadd float %96, %89 %98 = fmul float %24, %35 %99 = fadd float %98, %91 %100 = fmul float %25, %35 %101 = fadd float %100, %93 %102 = fmul float %26, %35 %103 = fadd float %102, %95 %104 = fmul float %27, %35 %105 = fadd float %104, %97 %106 = fmul float %12, %28 %107 = fmul float %13, %28 %108 = fmul float %14, %28 %109 = fmul float %15, %28 %110 = fmul float %16, %29 %111 = fadd float %110, %106 %112 = fmul float %17, %29 %113 = fadd float %112, %107 %114 = fmul float %18, %29 %115 = fadd float %114, %108 %116 = fmul float %19, %29 %117 = fadd float %116, %109 %118 = fmul float %20, %30 %119 = fadd float %118, %111 %120 = fmul float %21, %30 %121 = fadd float %120, %113 %122 = fmul float %22, %30 %123 = fadd float %122, %115 %124 = fmul float %23, %30 %125 = fadd float %124, %117 %126 = fmul float %24, %31 %127 = fadd float %126, %119 %128 = fmul float %25, %31 %129 = fadd float %128, %121 %130 = fmul float %26, %31 %131 = fadd float %130, %123 %132 = fmul float %27, %31 %133 = fadd float %132, %125 %134 = fmul float %127, %47 %135 = fmul float %129, %47 %136 = fmul float %131, %47 %137 = fmul float %133, %47 %138 = fmul float %99, %48 %139 = fadd float %138, %134 %140 = fmul float %101, %48 %141 = fadd float %140, %135 %142 = fmul float %103, %48 %143 = fadd float %142, %136 %144 = fmul float %105, %48 %145 = fadd float %144, %137 %146 = fmul float %71, %49 %147 = fadd float %146, %139 %148 = fmul float %73, %49 %149 = fadd float %148, %141 %150 = fmul float %75, %49 %151 = fadd float %150, %143 %152 = fmul float %77, %49 %153 = fadd float %152, %145 %154 = fmul float %12, %40 %155 = fmul float %13, %40 %156 = fmul float %14, %40 %157 = fmul float %15, %40 %158 = fmul float %16, %41 %159 = fadd float %158, %154 %160 = fmul float %17, %41 %161 = fadd float %160, %155 %162 = fmul float %18, %41 %163 = fadd float %162, %156 %164 = fmul float %19, %41 %165 = fadd float %164, %157 %166 = fmul float %20, %42 %167 = fadd float %166, %159 %168 = fmul float %21, %42 %169 = fadd float %168, %161 %170 = fmul float %22, %42 %171 = fadd float %170, %163 %172 = fmul float %23, %42 %173 = fadd float %172, %165 %174 = fmul float %24, %43 %175 = fadd float %174, %167 %176 = fmul float %25, %43 %177 = fadd float %176, %169 %178 = fmul float %26, %43 %179 = fadd float %178, %171 %180 = fmul float %27, %43 %181 = fadd float %180, %173 %182 = fadd float %147, %175 %183 = fadd float %149, %177 %184 = fadd float %151, %179 %185 = fadd float %153, %181 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %184, float %177, float %179, float %181) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %182, float %183, float %184, float %185) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_LOAD_DWORDX4 s[0:3], s[0:1], 0 ; C0800100 S_WAITCNT lgkmcnt(0) ; BF8C007F S_BUFFER_LOAD_DWORD s4, s[0:3], 2 ; C2020102 S_BUFFER_LOAD_DWORD s5, s[0:3], 16 ; C2028110 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v1, s5 ; 7E020205 V_MUL_F32_e64 v2, s4, v1, 0, 0, 0, 0 ; D2100002 02020204 S_BUFFER_LOAD_DWORD s5, s[0:3], 6 ; C2028106 S_BUFFER_LOAD_DWORD s6, s[0:3], 17 ; C2030111 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v3, s6 ; 7E060206 V_MAD_F32 v2, s5, v3, v2, 0, 0, 0, 0 ; D2820002 040A0605 S_BUFFER_LOAD_DWORD s6, s[0:3], 10 ; C203010A S_BUFFER_LOAD_DWORD s7, s[0:3], 18 ; C2038112 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v4, s7 ; 7E080207 V_MAD_F32 v2, s6, v4, v2, 0, 0, 0, 0 ; D2820002 040A0806 S_BUFFER_LOAD_DWORD s7, s[0:3], 14 ; C203810E S_BUFFER_LOAD_DWORD s10, s[0:3], 19 ; C2050113 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v5, s10 ; 7E0A020A V_MAD_F32 v2, s7, v5, v2, 0, 0, 0, 0 ; D2820002 040A0A07 S_LOAD_DWORDX4 s[8:11], s[8:9], 0 ; C0840900 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[6:9], s[8:11][v0] + 0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80020600 S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v0, v2, v6 ; 10000D02 S_BUFFER_LOAD_DWORD s8, s[0:3], 20 ; C2040114 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v2, s8 ; 7E040208 V_MUL_F32_e64 v10, s4, v2, 0, 0, 0, 0 ; D210000A 02020404 S_BUFFER_LOAD_DWORD s8, s[0:3], 21 ; C2040115 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v11, s8 ; 7E160208 V_MAD_F32 v10, s5, v11, v10, 0, 0, 0, 0 ; D282000A 042A1605 S_BUFFER_LOAD_DWORD s8, s[0:3], 22 ; C2040116 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v12, s8 ; 7E180208 V_MAD_F32 v10, s6, v12, v10, 0, 0, 0, 0 ; D282000A 042A1806 S_BUFFER_LOAD_DWORD s8, s[0:3], 23 ; C2040117 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v13, s8 ; 7E1A0208 V_MAD_F32 v10, s7, v13, v10, 0, 0, 0, 0 ; D282000A 042A1A07 V_MAD_F32 v0, v10, v7, v0, 0, 0, 0, 0 ; D2820000 04020F0A S_BUFFER_LOAD_DWORD s8, s[0:3], 24 ; C2040118 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v10, s8 ; 7E140208 V_MUL_F32_e64 v14, s4, v10, 0, 0, 0, 0 ; D210000E 02021404 S_BUFFER_LOAD_DWORD s8, s[0:3], 25 ; C2040119 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v15, s8 ; 7E1E0208 V_MAD_F32 v14, s5, v15, v14, 0, 0, 0, 0 ; D282000E 043A1E05 S_BUFFER_LOAD_DWORD s8, s[0:3], 26 ; C204011A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v16, s8 ; 7E200208 V_MAD_F32 v14, s6, v16, v14, 0, 0, 0, 0 ; D282000E 043A2006 S_BUFFER_LOAD_DWORD s8, s[0:3], 27 ; C204011B S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v17, s8 ; 7E220208 V_MAD_F32 v14, s7, v17, v14, 0, 0, 0, 0 ; D282000E 043A2207 V_MAD_F32 v0, v14, v8, v0, 0, 0, 0, 0 ; D2820000 0402110E S_BUFFER_LOAD_DWORD s8, s[0:3], 28 ; C204011C S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v14, s8 ; 7E1C0208 V_MUL_F32_e64 v18, s4, v14, 0, 0, 0, 0 ; D2100012 02021C04 S_BUFFER_LOAD_DWORD s4, s[0:3], 29 ; C202011D S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v19, s4 ; 7E260204 V_MAD_F32 v18, s5, v19, v18, 0, 0, 0, 0 ; D2820012 044A2605 S_BUFFER_LOAD_DWORD s4, s[0:3], 30 ; C202011E S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v20, s4 ; 7E280204 V_MAD_F32 v18, s6, v20, v18, 0, 0, 0, 0 ; D2820012 044A2806 S_BUFFER_LOAD_DWORD s4, s[0:3], 31 ; C202011F S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v21, s4 ; 7E2A0204 V_MAD_F32 v18, s7, v21, v18, 0, 0, 0, 0 ; D2820012 044A2A07 V_ADD_F32_e32 v0, v0, v18 ; 06002500 S_BUFFER_LOAD_DWORD s4, s[0:3], 3 ; C2020103 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v22, s4, v14, 0, 0, 0, 0 ; D2100016 02021C04 S_BUFFER_LOAD_DWORD s5, s[0:3], 7 ; C2028107 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v22, s5, v19, v22, 0, 0, 0, 0 ; D2820016 045A2605 S_BUFFER_LOAD_DWORD s6, s[0:3], 11 ; C203010B S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v22, s6, v20, v22, 0, 0, 0, 0 ; D2820016 045A2806 S_BUFFER_LOAD_DWORD s7, s[0:3], 15 ; C203810F S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v22, s7, v21, v22, 0, 0, 0, 0 ; D2820016 045A2A07 S_BUFFER_LOAD_DWORD s8, s[0:3], 1 ; C2040101 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v23, s8, v14, 0, 0, 0, 0 ; D2100017 02021C08 S_BUFFER_LOAD_DWORD s9, s[0:3], 5 ; C2048105 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v23, s9, v19, v23, 0, 0, 0, 0 ; D2820017 045E2609 S_BUFFER_LOAD_DWORD s10, s[0:3], 9 ; C2050109 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v23, s10, v20, v23, 0, 0, 0, 0 ; D2820017 045E280A S_BUFFER_LOAD_DWORD s11, s[0:3], 13 ; C205810D S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v23, s11, v21, v23, 0, 0, 0, 0 ; D2820017 045E2A0B EXP 15, 32, 0, 0, 0, v0, v23, v18, v22 ; F800020F 16121700 S_WAITCNT expcnt(0) ; BF8C070F V_MUL_F32_e64 v18, s4, v1, 0, 0, 0, 0 ; D2100012 02020204 V_MAD_F32 v18, s5, v3, v18, 0, 0, 0, 0 ; D2820012 044A0605 V_MAD_F32 v18, s6, v4, v18, 0, 0, 0, 0 ; D2820012 044A0806 V_MAD_F32 v18, s7, v5, v18, 0, 0, 0, 0 ; D2820012 044A0A07 V_MUL_F32_e32 v18, v18, v6 ; 10240D12 V_MUL_F32_e64 v24, s4, v2, 0, 0, 0, 0 ; D2100018 02020404 V_MAD_F32 v24, s5, v11, v24, 0, 0, 0, 0 ; D2820018 04621605 V_MAD_F32 v24, s6, v12, v24, 0, 0, 0, 0 ; D2820018 04621806 V_MAD_F32 v24, s7, v13, v24, 0, 0, 0, 0 ; D2820018 04621A07 V_MAD_F32 v18, v24, v7, v18, 0, 0, 0, 0 ; D2820012 044A0F18 V_MUL_F32_e64 v24, s4, v10, 0, 0, 0, 0 ; D2100018 02021404 V_MAD_F32 v24, s5, v15, v24, 0, 0, 0, 0 ; D2820018 04621E05 V_MAD_F32 v24, s6, v16, v24, 0, 0, 0, 0 ; D2820018 04622006 V_MAD_F32 v24, s7, v17, v24, 0, 0, 0, 0 ; D2820018 04622207 V_MAD_F32 v18, v24, v8, v18, 0, 0, 0, 0 ; D2820012 044A1118 V_ADD_F32_e32 v18, v18, v22 ; 06242D12 V_MUL_F32_e64 v22, s8, v1, 0, 0, 0, 0 ; D2100016 02020208 V_MAD_F32 v22, s9, v3, v22, 0, 0, 0, 0 ; D2820016 045A0609 V_MAD_F32 v22, s10, v4, v22, 0, 0, 0, 0 ; D2820016 045A080A V_MAD_F32 v22, s11, v5, v22, 0, 0, 0, 0 ; D2820016 045A0A0B V_MUL_F32_e32 v22, v22, v6 ; 102C0D16 V_MUL_F32_e64 v24, s8, v2, 0, 0, 0, 0 ; D2100018 02020408 V_MAD_F32 v24, s9, v11, v24, 0, 0, 0, 0 ; D2820018 04621609 V_MAD_F32 v24, s10, v12, v24, 0, 0, 0, 0 ; D2820018 0462180A V_MAD_F32 v24, s11, v13, v24, 0, 0, 0, 0 ; D2820018 04621A0B V_MAD_F32 v22, v24, v7, v22, 0, 0, 0, 0 ; D2820016 045A0F18 V_MUL_F32_e64 v24, s8, v10, 0, 0, 0, 0 ; D2100018 02021408 V_MAD_F32 v24, s9, v15, v24, 0, 0, 0, 0 ; D2820018 04621E09 V_MAD_F32 v24, s10, v16, v24, 0, 0, 0, 0 ; D2820018 0462200A V_MAD_F32 v24, s11, v17, v24, 0, 0, 0, 0 ; D2820018 0462220B V_MAD_F32 v22, v24, v8, v22, 0, 0, 0, 0 ; D2820016 045A1118 V_ADD_F32_e32 v22, v22, v23 ; 062C2F16 S_BUFFER_LOAD_DWORD s4, s[0:3], 0 ; C2020100 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v1, s4, v1, 0, 0, 0, 0 ; D2100001 02020204 S_BUFFER_LOAD_DWORD s5, s[0:3], 4 ; C2028104 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v1, s5, v3, v1, 0, 0, 0, 0 ; D2820001 04060605 S_BUFFER_LOAD_DWORD s6, s[0:3], 8 ; C2030108 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v1, s6, v4, v1, 0, 0, 0, 0 ; D2820001 04060806 S_BUFFER_LOAD_DWORD s0, s[0:3], 12 ; C200010C S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v1, s0, v5, v1, 0, 0, 0, 0 ; D2820001 04060A00 V_MUL_F32_e32 v1, v1, v6 ; 10020D01 V_MUL_F32_e64 v2, s4, v2, 0, 0, 0, 0 ; D2100002 02020404 V_MAD_F32 v2, s5, v11, v2, 0, 0, 0, 0 ; D2820002 040A1605 V_MAD_F32 v2, s6, v12, v2, 0, 0, 0, 0 ; D2820002 040A1806 V_MAD_F32 v2, s0, v13, v2, 0, 0, 0, 0 ; D2820002 040A1A00 V_MAD_F32 v1, v2, v7, v1, 0, 0, 0, 0 ; D2820001 04060F02 V_MUL_F32_e64 v2, s4, v10, 0, 0, 0, 0 ; D2100002 02021404 V_MAD_F32 v2, s5, v15, v2, 0, 0, 0, 0 ; D2820002 040A1E05 V_MAD_F32 v2, s6, v16, v2, 0, 0, 0, 0 ; D2820002 040A2006 V_MAD_F32 v2, s0, v17, v2, 0, 0, 0, 0 ; D2820002 040A2200 V_MAD_F32 v1, v2, v8, v1, 0, 0, 0, 0 ; D2820001 04061102 V_MUL_F32_e64 v2, s4, v14, 0, 0, 0, 0 ; D2100002 02021C04 V_MAD_F32 v2, s5, v19, v2, 0, 0, 0, 0 ; D2820002 040A2605 V_MAD_F32 v2, s6, v20, v2, 0, 0, 0, 0 ; D2820002 040A2806 V_MAD_F32 v2, s0, v21, v2, 0, 0, 0, 0 ; D2820002 040A2A00 V_ADD_F32_e32 v1, v1, v2 ; 06020501 EXP 15, 12, 0, 1, 0, v1, v22, v0, v18 ; F80008CF 12001601 S_ENDPGM ; BF810000 FRAG DCL IN[0], POSITION, LINEAR DCL OUT[0], COLOR DCL SAMP[0] DCL CONST[1] DCL TEMP[0] DCL TEMP[1..2], LOCAL IMM[0] FLT32 { -2.0000, 0.0000, 0.0600, -1.0000} IMM[1] FLT32 { 0.2500, 0.3800, 1.0000, 0.0000} IMM[2] FLT32 { 2.0000, 0.0000, 0.0000, 0.0000} 0: MOV TEMP[0], IN[0] 1: MAD TEMP[0].y, IN[0], CONST[1].xxxx, CONST[1].yyyy 2: ADD TEMP[1].xy, TEMP[0].xyyy, IMM[0].xyyy 3: MOV TEMP[1].xy, TEMP[1].xyyy 4: TEX TEMP[1].x, TEMP[1], SAMP[0], RECT 5: MUL TEMP[1].x, TEMP[1].xxxx, IMM[0].zzzz 6: ADD TEMP[2].xy, TEMP[0].xyyy, IMM[0].wyyy 7: MOV TEMP[2].xy, TEMP[2].xyyy 8: TEX TEMP[2].x, TEMP[2], SAMP[0], RECT 9: MAD TEMP[1].x, TEMP[2].xxxx, IMM[1].xxxx, TEMP[1].xxxx 10: MOV TEMP[2].xy, TEMP[0].xyyy 11: TEX TEMP[2].x, TEMP[2], SAMP[0], RECT 12: MAD TEMP[1].x, TEMP[2].xxxx, IMM[1].yyyy, TEMP[1].xxxx 13: ADD TEMP[2].xy, TEMP[0].xyyy, IMM[1].zwww 14: MOV TEMP[2].xy, TEMP[2].xyyy 15: TEX TEMP[2].x, TEMP[2], SAMP[0], RECT 16: MAD TEMP[1].x, TEMP[2].xxxx, IMM[1].xxxx, TEMP[1].xxxx 17: ADD TEMP[2].xy, TEMP[0].xyyy, IMM[2].xyyy 18: MOV TEMP[2].xy, TEMP[2].xyyy 19: TEX TEMP[2].x, TEMP[2], SAMP[0], RECT 20: MAD TEMP[1].x, TEMP[2].xxxx, IMM[0].zzzz, TEMP[1].xxxx 21: MOV OUT[0], TEMP[1].xxxx 22: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %22 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0 %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0 %24 = call float @llvm.SI.load.const(<16 x i8> %23, i32 16) %25 = call float @llvm.SI.load.const(<16 x i8> %23, i32 20) %26 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0 %27 = load <32 x i8> addrspace(2)* %26, !tbaa !0 %28 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0 %29 = load <16 x i8> addrspace(2)* %28, !tbaa !0 %30 = fmul float %15, %24 %31 = fadd float %30, %25 %32 = fadd float %14, -2.000000e+00 %33 = fadd float %31, 0.000000e+00 %34 = bitcast float %32 to i32 %35 = bitcast float %33 to i32 %36 = insertelement <2 x i32> undef, i32 %34, i32 0 %37 = insertelement <2 x i32> %36, i32 %35, i32 1 %38 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %37, <32 x i8> %27, <16 x i8> %29, i32 5) %39 = extractelement <4 x float> %38, i32 0 %40 = fmul float %39, 0x3FAEB851E0000000 %41 = fadd float %14, -1.000000e+00 %42 = fadd float %31, 0.000000e+00 %43 = bitcast float %41 to i32 %44 = bitcast float %42 to i32 %45 = insertelement <2 x i32> undef, i32 %43, i32 0 %46 = insertelement <2 x i32> %45, i32 %44, i32 1 %47 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %46, <32 x i8> %27, <16 x i8> %29, i32 5) %48 = extractelement <4 x float> %47, i32 0 %49 = fmul float %48, 2.500000e-01 %50 = fadd float %49, %40 %51 = bitcast float %14 to i32 %52 = bitcast float %31 to i32 %53 = insertelement <2 x i32> undef, i32 %51, i32 0 %54 = insertelement <2 x i32> %53, i32 %52, i32 1 %55 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %54, <32 x i8> %27, <16 x i8> %29, i32 5) %56 = extractelement <4 x float> %55, i32 0 %57 = fmul float %56, 0x3FD851EB80000000 %58 = fadd float %57, %50 %59 = fadd float %14, 1.000000e+00 %60 = fadd float %31, 0.000000e+00 %61 = bitcast float %59 to i32 %62 = bitcast float %60 to i32 %63 = insertelement <2 x i32> undef, i32 %61, i32 0 %64 = insertelement <2 x i32> %63, i32 %62, i32 1 %65 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %64, <32 x i8> %27, <16 x i8> %29, i32 5) %66 = extractelement <4 x float> %65, i32 0 %67 = fmul float %66, 2.500000e-01 %68 = fadd float %67, %58 %69 = fadd float %14, 2.000000e+00 %70 = fadd float %31, 0.000000e+00 %71 = bitcast float %69 to i32 %72 = bitcast float %70 to i32 %73 = insertelement <2 x i32> undef, i32 %71, i32 0 %74 = insertelement <2 x i32> %73, i32 %72, i32 1 %75 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %74, <32 x i8> %27, <16 x i8> %29, i32 5) %76 = extractelement <4 x float> %75, i32 0 %77 = fmul float %76, 0x3FAEB851E0000000 %78 = fadd float %77, %68 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %78, float %78, float %78, float %78) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: V_MOV_B32_e32 v0, v2 ; 7E000302 S_LOAD_DWORDX4 s[8:11], s[0:1], 0 ; C0840100 S_WAITCNT lgkmcnt(0) ; BF8C007F S_BUFFER_LOAD_DWORD s0, s[8:11], 4 ; C2000904 S_BUFFER_LOAD_DWORD s1, s[8:11], 5 ; C2008905 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v2, s1 ; 7E040201 V_MAD_F32 v1, v3, s0, v2, 0, 0, 0, 0 ; D2820001 04080103 V_ADD_F32_e32 v3, 0.000000e+00, v1 ; 06060280 V_ADD_F32_e32 v2, -1.000000e+00, v0 ; 060400F3 S_LOAD_DWORDX4 s[0:3], s[2:3], 0 ; C0800300 S_LOAD_DWORDX8 s[4:11], s[4:5], 0 ; C0C20500 S_WAITCNT lgkmcnt(0) ; BF8C007F IMAGE_SAMPLE v4, 1, -1, 0, 0, 0, 0, 0, 0, v[2:3], s[4:11], s[0:3] ; F0801100 00010402 V_ADD_F32_e32 v2, -2.000000e+00, v0 ; 060400F5 IMAGE_SAMPLE v5, 1, -1, 0, 0, 0, 0, 0, 0, v[2:3], s[4:11], s[0:3] ; F0801100 00010502 S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v5, 6.000000e-02, v5 ; 100A0AFF 3D75C28F V_MOV_B32_e32 v6, 2.500000e-01 ; 7E0C02FF 3E800000 V_MAD_F32 v4, v4, v6, v5, 0, 0, 0, 0 ; D2820004 04160D04 IMAGE_SAMPLE v5, 1, -1, 0, 0, 0, 0, 0, 0, v[0:1], s[4:11], s[0:3] ; F0801100 00010500 V_MOV_B32_e32 v7, 3.800000e-01 ; 7E0E02FF 3EC28F5C S_WAITCNT vmcnt(0) ; BF8C0770 V_MAD_F32 v4, v5, v7, v4, 0, 0, 0, 0 ; D2820004 04120F05 V_ADD_F32_e32 v2, 1.000000e+00, v0 ; 060400F2 IMAGE_SAMPLE v5, 1, -1, 0, 0, 0, 0, 0, 0, v[2:3], s[4:11], s[0:3] ; F0801100 00010502 S_WAITCNT vmcnt(0) ; BF8C0770 V_MAD_F32 v4, v5, v6, v4, 0, 0, 0, 0 ; D2820004 04120D05 V_ADD_F32_e32 v2, 2.000000e+00, v0 ; 060400F4 IMAGE_SAMPLE v0, 1, -1, 0, 0, 0, 0, 0, 0, v[2:3], s[4:11], s[0:3] ; F0801100 00010002 V_MOV_B32_e32 v1, 6.000000e-02 ; 7E0202FF 3D75C28F S_WAITCNT vmcnt(0) ; BF8C0770 V_MAD_F32 v0, v0, v1, v4, 0, 0, 0, 0 ; D2820000 04120300 EXP 15, 0, 0, 1, 1, v0, v0, v0, v0 ; F800180F 00000000 S_ENDPGM ; BF810000 VERT DCL IN[0] DCL OUT[0], POSITION DCL TEMP[0], LOCAL IMM[0] FLT32 { 1.0000, 0.0000, 0.0000, 0.0000} 0: MOV TEMP[0].w, IMM[0].xxxx 1: MOV TEMP[0].xyz, IN[0].xyzx 2: MOV OUT[0], TEMP[0] 3: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 0 %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0 %12 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %11, i32 0, i32 %6) %13 = extractelement <4 x float> %12, i32 0 %14 = extractelement <4 x float> %12, i32 1 %15 = extractelement <4 x float> %12, i32 2 call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %13, float %14, float %15, float 1.000000e+00) ret void } ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_LOAD_DWORDX4 s[0:3], s[8:9], 0 ; C0800900 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[0:3], s[0:3][v0] + 0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80000000 V_MOV_B32_e32 v4, 1.000000e+00 ; 7E0802F2 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 12, 0, 1, 0, v0, v1, v2, v4 ; F80008CF 04020100 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[0], CONSTANT DCL OUT[0], COLOR 0: MOV OUT[0], IN[0] 1: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %22 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %5) %23 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %5) %24 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %5) %25 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %5) call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %23, float %24, float %25) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.constant(i32, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s9 ; BEFC0309 V_INTERP_MOV_F32 v0, P0, 3, 0, [m0] ; C8020302 V_INTERP_MOV_F32 v1, P0, 2, 0, [m0] ; C8060202 V_INTERP_MOV_F32 v2, P0, 1, 0, [m0] ; C80A0102 V_INTERP_MOV_F32 v3, P0, 0, 0, [m0] ; C80E0002 EXP 15, 0, 0, 1, 1, v3, v2, v1, v0 ; F800180F 00010203 S_ENDPGM ; BF810000 FRAG DCL IN[0], POSITION, LINEAR DCL OUT[0], COLOR DCL SAMP[0] DCL CONST[1] DCL TEMP[0] DCL TEMP[1..2], LOCAL IMM[0] FLT32 { 0.0000, -2.0000, 0.0600, -1.0000} IMM[1] FLT32 { 0.2500, 0.3800, 0.0000, 1.0000} IMM[2] FLT32 { 0.0000, 2.0000, 0.0000, 0.0000} 0: MOV TEMP[0], IN[0] 1: MAD TEMP[0].y, IN[0], CONST[1].xxxx, CONST[1].yyyy 2: ADD TEMP[1].xy, TEMP[0].xyyy, IMM[0].xyyy 3: MOV TEMP[1].xy, TEMP[1].xyyy 4: TEX TEMP[1].x, TEMP[1], SAMP[0], RECT 5: MUL TEMP[1].x, TEMP[1].xxxx, IMM[0].zzzz 6: ADD TEMP[2].xy, TEMP[0].xyyy, IMM[0].xwww 7: MOV TEMP[2].xy, TEMP[2].xyyy 8: TEX TEMP[2].x, TEMP[2], SAMP[0], RECT 9: MAD TEMP[1].x, TEMP[2].xxxx, IMM[1].xxxx, TEMP[1].xxxx 10: MOV TEMP[2].xy, TEMP[0].xyyy 11: TEX TEMP[2].x, TEMP[2], SAMP[0], RECT 12: MAD TEMP[1].x, TEMP[2].xxxx, IMM[1].yyyy, TEMP[1].xxxx 13: ADD TEMP[2].xy, TEMP[0].xyyy, IMM[1].zwww 14: MOV TEMP[2].xy, TEMP[2].xyyy 15: TEX TEMP[2].x, TEMP[2], SAMP[0], RECT 16: MAD TEMP[1].x, TEMP[2].xxxx, IMM[1].xxxx, TEMP[1].xxxx 17: ADD TEMP[2].xy, TEMP[0].xyyy, IMM[2].xyyy 18: MOV TEMP[2].xy, TEMP[2].xyyy 19: TEX TEMP[2].x, TEMP[2], SAMP[0], RECT 20: MAD TEMP[1].x, TEMP[2].xxxx, IMM[0].zzzz, TEMP[1].xxxx 21: MOV OUT[0], TEMP[1].xxxx 22: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %22 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0 %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0 %24 = call float @llvm.SI.load.const(<16 x i8> %23, i32 16) %25 = call float @llvm.SI.load.const(<16 x i8> %23, i32 20) %26 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0 %27 = load <32 x i8> addrspace(2)* %26, !tbaa !0 %28 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0 %29 = load <16 x i8> addrspace(2)* %28, !tbaa !0 %30 = fmul float %15, %24 %31 = fadd float %30, %25 %32 = fadd float %14, 0.000000e+00 %33 = fadd float %31, -2.000000e+00 %34 = bitcast float %32 to i32 %35 = bitcast float %33 to i32 %36 = insertelement <2 x i32> undef, i32 %34, i32 0 %37 = insertelement <2 x i32> %36, i32 %35, i32 1 %38 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %37, <32 x i8> %27, <16 x i8> %29, i32 5) %39 = extractelement <4 x float> %38, i32 0 %40 = fmul float %39, 0x3FAEB851E0000000 %41 = fadd float %14, 0.000000e+00 %42 = fadd float %31, -1.000000e+00 %43 = bitcast float %41 to i32 %44 = bitcast float %42 to i32 %45 = insertelement <2 x i32> undef, i32 %43, i32 0 %46 = insertelement <2 x i32> %45, i32 %44, i32 1 %47 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %46, <32 x i8> %27, <16 x i8> %29, i32 5) %48 = extractelement <4 x float> %47, i32 0 %49 = fmul float %48, 2.500000e-01 %50 = fadd float %49, %40 %51 = bitcast float %14 to i32 %52 = bitcast float %31 to i32 %53 = insertelement <2 x i32> undef, i32 %51, i32 0 %54 = insertelement <2 x i32> %53, i32 %52, i32 1 %55 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %54, <32 x i8> %27, <16 x i8> %29, i32 5) %56 = extractelement <4 x float> %55, i32 0 %57 = fmul float %56, 0x3FD851EB80000000 %58 = fadd float %57, %50 %59 = fadd float %14, 0.000000e+00 %60 = fadd float %31, 1.000000e+00 %61 = bitcast float %59 to i32 %62 = bitcast float %60 to i32 %63 = insertelement <2 x i32> undef, i32 %61, i32 0 %64 = insertelement <2 x i32> %63, i32 %62, i32 1 %65 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %64, <32 x i8> %27, <16 x i8> %29, i32 5) %66 = extractelement <4 x float> %65, i32 0 %67 = fmul float %66, 2.500000e-01 %68 = fadd float %67, %58 %69 = fadd float %14, 0.000000e+00 %70 = fadd float %31, 2.000000e+00 %71 = bitcast float %69 to i32 %72 = bitcast float %70 to i32 %73 = insertelement <2 x i32> undef, i32 %71, i32 0 %74 = insertelement <2 x i32> %73, i32 %72, i32 1 %75 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %74, <32 x i8> %27, <16 x i8> %29, i32 5) %76 = extractelement <4 x float> %75, i32 0 %77 = fmul float %76, 0x3FAEB851E0000000 %78 = fadd float %77, %68 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %78, float %78, float %78, float %78) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: V_MOV_B32_e32 v0, v2 ; 7E000302 S_LOAD_DWORDX4 s[8:11], s[0:1], 0 ; C0840100 S_WAITCNT lgkmcnt(0) ; BF8C007F S_BUFFER_LOAD_DWORD s0, s[8:11], 4 ; C2000904 S_BUFFER_LOAD_DWORD s1, s[8:11], 5 ; C2008905 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v2, s1 ; 7E040201 V_MAD_F32 v1, v3, s0, v2, 0, 0, 0, 0 ; D2820001 04080103 V_ADD_F32_e32 v3, -1.000000e+00, v1 ; 060602F3 V_ADD_F32_e32 v2, 0.000000e+00, v0 ; 06040080 S_LOAD_DWORDX4 s[0:3], s[2:3], 0 ; C0800300 S_LOAD_DWORDX8 s[4:11], s[4:5], 0 ; C0C20500 S_WAITCNT lgkmcnt(0) ; BF8C007F IMAGE_SAMPLE v4, 1, -1, 0, 0, 0, 0, 0, 0, v[2:3], s[4:11], s[0:3] ; F0801100 00010402 V_ADD_F32_e32 v3, -2.000000e+00, v1 ; 060602F5 IMAGE_SAMPLE v5, 1, -1, 0, 0, 0, 0, 0, 0, v[2:3], s[4:11], s[0:3] ; F0801100 00010502 S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v5, 6.000000e-02, v5 ; 100A0AFF 3D75C28F V_MOV_B32_e32 v6, 2.500000e-01 ; 7E0C02FF 3E800000 V_MAD_F32 v4, v4, v6, v5, 0, 0, 0, 0 ; D2820004 04160D04 IMAGE_SAMPLE v5, 1, -1, 0, 0, 0, 0, 0, 0, v[0:1], s[4:11], s[0:3] ; F0801100 00010500 V_MOV_B32_e32 v7, 3.800000e-01 ; 7E0E02FF 3EC28F5C S_WAITCNT vmcnt(0) ; BF8C0770 V_MAD_F32 v4, v5, v7, v4, 0, 0, 0, 0 ; D2820004 04120F05 V_ADD_F32_e32 v3, 1.000000e+00, v1 ; 060602F2 IMAGE_SAMPLE v5, 1, -1, 0, 0, 0, 0, 0, 0, v[2:3], s[4:11], s[0:3] ; F0801100 00010502 S_WAITCNT vmcnt(0) ; BF8C0770 V_MAD_F32 v4, v5, v6, v4, 0, 0, 0, 0 ; D2820004 04120D05 V_ADD_F32_e32 v3, 2.000000e+00, v1 ; 060602F4 IMAGE_SAMPLE v0, 1, -1, 0, 0, 0, 0, 0, 0, v[2:3], s[4:11], s[0:3] ; F0801100 00010002 V_MOV_B32_e32 v1, 6.000000e-02 ; 7E0202FF 3D75C28F S_WAITCNT vmcnt(0) ; BF8C0770 V_MAD_F32 v0, v0, v1, v4, 0, 0, 0, 0 ; D2820000 04120300 EXP 15, 0, 0, 1, 1, v0, v0, v0, v0 ; F800180F 00000000 S_ENDPGM ; BF810000 VERT DCL IN[0] DCL OUT[0], POSITION DCL TEMP[0], LOCAL IMM[0] FLT32 { 1.0000, 0.0000, 0.0000, 0.0000} 0: MOV TEMP[0].w, IMM[0].xxxx 1: MOV TEMP[0].xyz, IN[0].xyzx 2: MOV OUT[0], TEMP[0] 3: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 0 %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0 %12 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %11, i32 0, i32 %6) %13 = extractelement <4 x float> %12, i32 0 %14 = extractelement <4 x float> %12, i32 1 %15 = extractelement <4 x float> %12, i32 2 call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %13, float %14, float %15, float 1.000000e+00) ret void } ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_LOAD_DWORDX4 s[0:3], s[8:9], 0 ; C0800900 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[0:3], s[0:3][v0] + 0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80000000 V_MOV_B32_e32 v4, 1.000000e+00 ; 7E0802F2 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 12, 0, 1, 0, v0, v1, v2, v4 ; F80008CF 04020100 S_ENDPGM ; BF810000 FRAG DCL OUT[0], COLOR DCL CONST[1][0..96] DCL TEMP[0], LOCAL IMM[0] FLT32 { 0.0000, 0.0000, 0.0000, 0.0000} 0: MOV TEMP[0].xyz, IMM[0].xxxx 1: MOV OUT[0], TEMP[0] 2: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } Shader Disassembly: V_MOV_B32_e32 v0, 0.000000e+00 ; 7E000280 EXP 15, 0, 0, 1, 1, v0, v0, v0, v0 ; F800180F 00000000 S_ENDPGM ; BF810000 VERT DCL IN[0] DCL OUT[0], POSITION DCL CONST[0..3] DCL CONST[1][0..96] DCL TEMP[0..4], LOCAL DCL ADDR[0] IMM[0] UINT32 {0, 176, 160, 144} IMM[1] INT32 {11, 10, 9, 8} IMM[2] UINT32 {128, 0, 0, 0} 0: MUL TEMP[0], CONST[0], IN[0].xxxx 1: MAD TEMP[0], CONST[1], IN[0].yyyy, TEMP[0] 2: MAD TEMP[0], CONST[2], IN[0].zzzz, TEMP[0] 3: ADD TEMP[0], TEMP[0], CONST[3] 4: UARL ADDR[0].x, IMM[1].xxxx 5: MOV TEMP[1], CONST[1][ADDR[0].x] 6: UARL ADDR[0].x, IMM[1].yyyy 7: MOV TEMP[2], CONST[1][ADDR[0].x] 8: UARL ADDR[0].x, IMM[1].zzzz 9: MOV TEMP[3], CONST[1][ADDR[0].x] 10: UARL ADDR[0].x, IMM[1].wwww 11: MOV TEMP[4], CONST[1][ADDR[0].x] 12: MUL TEMP[4], TEMP[4], TEMP[0].xxxx 13: MAD TEMP[3], TEMP[3], TEMP[0].yyyy, TEMP[4] 14: MAD TEMP[2], TEMP[2], TEMP[0].zzzz, TEMP[3] 15: MAD TEMP[0], TEMP[1], TEMP[0].wwww, TEMP[2] 16: MOV OUT[0], TEMP[0] 17: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0 %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0 %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0) %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4) %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8) %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12) %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16) %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20) %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24) %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28) %20 = call float @llvm.SI.load.const(<16 x i8> %11, i32 32) %21 = call float @llvm.SI.load.const(<16 x i8> %11, i32 36) %22 = call float @llvm.SI.load.const(<16 x i8> %11, i32 40) %23 = call float @llvm.SI.load.const(<16 x i8> %11, i32 44) %24 = call float @llvm.SI.load.const(<16 x i8> %11, i32 48) %25 = call float @llvm.SI.load.const(<16 x i8> %11, i32 52) %26 = call float @llvm.SI.load.const(<16 x i8> %11, i32 56) %27 = call float @llvm.SI.load.const(<16 x i8> %11, i32 60) %28 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 1 %29 = load <16 x i8> addrspace(2)* %28, !tbaa !0 %30 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 0 %31 = load <16 x i8> addrspace(2)* %30, !tbaa !0 %32 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %31, i32 0, i32 %6) %33 = extractelement <4 x float> %32, i32 0 %34 = extractelement <4 x float> %32, i32 1 %35 = extractelement <4 x float> %32, i32 2 %36 = fmul float %12, %33 %37 = fmul float %13, %33 %38 = fmul float %14, %33 %39 = fmul float %15, %33 %40 = fmul float %16, %34 %41 = fadd float %40, %36 %42 = fmul float %17, %34 %43 = fadd float %42, %37 %44 = fmul float %18, %34 %45 = fadd float %44, %38 %46 = fmul float %19, %34 %47 = fadd float %46, %39 %48 = fmul float %20, %35 %49 = fadd float %48, %41 %50 = fmul float %21, %35 %51 = fadd float %50, %43 %52 = fmul float %22, %35 %53 = fadd float %52, %45 %54 = fmul float %23, %35 %55 = fadd float %54, %47 %56 = fadd float %49, %24 %57 = fadd float %51, %25 %58 = fadd float %53, %26 %59 = fadd float %55, %27 %60 = shl i32 11, 4 %61 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %60) %62 = shl i32 11, 4 %63 = add i32 %62, 4 %64 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %63) %65 = shl i32 11, 4 %66 = add i32 %65, 8 %67 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %66) %68 = shl i32 11, 4 %69 = add i32 %68, 12 %70 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %69) %71 = shl i32 10, 4 %72 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %71) %73 = shl i32 10, 4 %74 = add i32 %73, 4 %75 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %74) %76 = shl i32 10, 4 %77 = add i32 %76, 8 %78 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %77) %79 = shl i32 10, 4 %80 = add i32 %79, 12 %81 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %80) %82 = shl i32 9, 4 %83 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %82) %84 = shl i32 9, 4 %85 = add i32 %84, 4 %86 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %85) %87 = shl i32 9, 4 %88 = add i32 %87, 8 %89 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %88) %90 = shl i32 9, 4 %91 = add i32 %90, 12 %92 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %91) %93 = shl i32 8, 4 %94 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %93) %95 = shl i32 8, 4 %96 = add i32 %95, 4 %97 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %96) %98 = shl i32 8, 4 %99 = add i32 %98, 8 %100 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %99) %101 = shl i32 8, 4 %102 = add i32 %101, 12 %103 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %102) %104 = fmul float %94, %56 %105 = fmul float %97, %56 %106 = fmul float %100, %56 %107 = fmul float %103, %56 %108 = fmul float %83, %57 %109 = fadd float %108, %104 %110 = fmul float %86, %57 %111 = fadd float %110, %105 %112 = fmul float %89, %57 %113 = fadd float %112, %106 %114 = fmul float %92, %57 %115 = fadd float %114, %107 %116 = fmul float %72, %58 %117 = fadd float %116, %109 %118 = fmul float %75, %58 %119 = fadd float %118, %111 %120 = fmul float %78, %58 %121 = fadd float %120, %113 %122 = fmul float %81, %58 %123 = fadd float %122, %115 %124 = fmul float %61, %59 %125 = fadd float %124, %117 %126 = fmul float %64, %59 %127 = fadd float %126, %119 %128 = fmul float %67, %59 %129 = fadd float %128, %121 %130 = fmul float %70, %59 %131 = fadd float %130, %123 call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %125, float %127, float %129, float %131) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_LOAD_DWORDX4 s[4:7], s[8:9], 0 ; C0820900 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[0:3], s[4:7][v0] + 0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80010000 S_LOAD_DWORDX4 s[4:7], s[0:1], 0 ; C0820100 S_WAITCNT vmcnt(0) lgkmcnt(0) ; BF8C0070 S_BUFFER_LOAD_DWORD s2, s[4:7], 1 ; C2010501 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v4, s2, v0 ; 10080002 S_BUFFER_LOAD_DWORD s2, s[4:7], 5 ; C2010505 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v4, s2, v1, v4, 0, 0, 0, 0 ; D2820004 04120202 S_BUFFER_LOAD_DWORD s2, s[4:7], 9 ; C2010509 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v4, s2, v2, v4, 0, 0, 0, 0 ; D2820004 04120402 S_BUFFER_LOAD_DWORD s2, s[4:7], 13 ; C201050D S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v4, s2, v4 ; 06080802 S_BUFFER_LOAD_DWORD s2, s[4:7], 0 ; C2010500 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v5, s2, v0 ; 100A0002 S_BUFFER_LOAD_DWORD s2, s[4:7], 4 ; C2010504 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v5, s2, v1, v5, 0, 0, 0, 0 ; D2820005 04160202 S_BUFFER_LOAD_DWORD s2, s[4:7], 8 ; C2010508 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v5, s2, v2, v5, 0, 0, 0, 0 ; D2820005 04160402 S_BUFFER_LOAD_DWORD s2, s[4:7], 12 ; C201050C S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v5, s2, v5 ; 060A0A02 S_LOAD_DWORDX4 s[0:3], s[0:1], 4 ; C0800104 S_WAITCNT lgkmcnt(0) ; BF8C007F S_BUFFER_LOAD_DWORD s8, s[0:3], 35 ; C2040123 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v6, s8, v5 ; 100C0A08 S_BUFFER_LOAD_DWORD s8, s[0:3], 39 ; C2040127 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v6, s8, v4, v6, 0, 0, 0, 0 ; D2820006 041A0808 S_BUFFER_LOAD_DWORD s8, s[4:7], 2 ; C2040502 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v7, s8, v0 ; 100E0008 S_BUFFER_LOAD_DWORD s8, s[4:7], 6 ; C2040506 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v7, s8, v1, v7, 0, 0, 0, 0 ; D2820007 041E0208 S_BUFFER_LOAD_DWORD s8, s[4:7], 10 ; C204050A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v7, s8, v2, v7, 0, 0, 0, 0 ; D2820007 041E0408 S_BUFFER_LOAD_DWORD s8, s[4:7], 14 ; C204050E S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v7, s8, v7 ; 060E0E08 S_BUFFER_LOAD_DWORD s8, s[0:3], 43 ; C204012B S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v6, s8, v7, v6, 0, 0, 0, 0 ; D2820006 041A0E08 S_BUFFER_LOAD_DWORD s8, s[4:7], 3 ; C2040503 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v8, s8, v0 ; 10100008 S_BUFFER_LOAD_DWORD s8, s[4:7], 7 ; C2040507 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v8, s8, v1, v8, 0, 0, 0, 0 ; D2820008 04220208 S_BUFFER_LOAD_DWORD s8, s[4:7], 11 ; C204050B S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v0, s8, v2, v8, 0, 0, 0, 0 ; D2820000 04220408 S_BUFFER_LOAD_DWORD s4, s[4:7], 15 ; C202050F S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v0, s4, v0 ; 06000004 S_BUFFER_LOAD_DWORD s4, s[0:3], 47 ; C202012F S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v1, s4, v0, v6, 0, 0, 0, 0 ; D2820001 041A0004 S_BUFFER_LOAD_DWORD s4, s[0:3], 34 ; C2020122 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v2, s4, v5 ; 10040A04 S_BUFFER_LOAD_DWORD s4, s[0:3], 38 ; C2020126 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v2, s4, v4, v2, 0, 0, 0, 0 ; D2820002 040A0804 S_BUFFER_LOAD_DWORD s4, s[0:3], 42 ; C202012A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v2, s4, v7, v2, 0, 0, 0, 0 ; D2820002 040A0E04 S_BUFFER_LOAD_DWORD s4, s[0:3], 46 ; C202012E S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v2, s4, v0, v2, 0, 0, 0, 0 ; D2820002 040A0004 S_BUFFER_LOAD_DWORD s4, s[0:3], 33 ; C2020121 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v3, s4, v5 ; 10060A04 S_BUFFER_LOAD_DWORD s4, s[0:3], 37 ; C2020125 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v3, s4, v4, v3, 0, 0, 0, 0 ; D2820003 040E0804 S_BUFFER_LOAD_DWORD s4, s[0:3], 41 ; C2020129 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v3, s4, v7, v3, 0, 0, 0, 0 ; D2820003 040E0E04 S_BUFFER_LOAD_DWORD s4, s[0:3], 45 ; C202012D S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v3, s4, v0, v3, 0, 0, 0, 0 ; D2820003 040E0004 S_BUFFER_LOAD_DWORD s4, s[0:3], 32 ; C2020120 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v5, s4, v5 ; 100A0A04 S_BUFFER_LOAD_DWORD s4, s[0:3], 36 ; C2020124 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v4, s4, v4, v5, 0, 0, 0, 0 ; D2820004 04160804 S_BUFFER_LOAD_DWORD s4, s[0:3], 40 ; C2020128 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v4, s4, v7, v4, 0, 0, 0, 0 ; D2820004 04120E04 S_BUFFER_LOAD_DWORD s0, s[0:3], 44 ; C200012C S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v0, s0, v0, v4, 0, 0, 0, 0 ; D2820000 04120000 EXP 15, 12, 0, 1, 0, v0, v3, v2, v1 ; F80008CF 01020300 S_ENDPGM ; BF810000 FRAG DCL OUT[0], COLOR DCL CONST[1][0..96] DCL TEMP[0], LOCAL IMM[0] FLT32 { 0.0000, 0.0000, 0.0000, 0.0000} 0: MOV TEMP[0].xyz, IMM[0].xxxx 1: MOV OUT[0], TEMP[0] 2: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %22 = call i32 @llvm.SI.packf16(float 0.000000e+00, float 0.000000e+00) %23 = bitcast i32 %22 to float %24 = call i32 @llvm.SI.packf16(float 0.000000e+00, float 0.000000e+00) %25 = bitcast i32 %24 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %23, float %25, float %23, float %25) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } Shader Disassembly: V_CVT_PKRTZ_F16_F32_e64 v0, 0.000000e+00, 0.000000e+00, 0, 0, 0, 0 ; D25E0000 02010080 EXP 15, 0, 1, 1, 1, v0, v0, v0, v0 ; F8001C0F 00000000 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[20], PERSPECTIVE DCL IN[1], GENERIC[21], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL SAMP[1] DCL CONST[2..75] DCL CONST[1][0..96] DCL CONST[2][0..68] DCL TEMP[0..41], LOCAL DCL ADDR[0] IMM[0] UINT32 {0, 224, 208, 192} IMM[1] INT32 {14, 13, 12, 15} IMM[2] UINT32 {240, 320, 1, 256} IMM[3] INT32 {20, 16, 6, 5} IMM[4] FLT32 { 2.0000, 1.0500, 0.0000, 0.0010} IMM[5] FLT32 { 0.8000, 0.7213, -1.0000, 1.0000} IMM[6] UINT32 {96, 80, 64, 112} IMM[7] INT32 {4, 7, 10, 9} IMM[8] UINT32 {252, 264, 160, 144} IMM[9] FLT32 { 0.5000, -0.8000, 5.0000, 3.0000} IMM[10] UINT32 {128, 176, 260, 0} IMM[11] INT32 {8, 11, 0, 1} IMM[12] INT32 {2, 3, 0, 0} 0: DP3 TEMP[0].x, IN[0].xyzz, IN[0].xyzz 1: RSQ TEMP[0].x, TEMP[0].xxxx 2: MUL TEMP[0].xyz, IN[0].xyzz, TEMP[0].xxxx 3: MOV TEMP[1].xyz, TEMP[0].xyzx 4: MOV TEMP[2].xyz, CONST[74].xyzx 5: MOV TEMP[3], CONST[75] 6: UARL ADDR[0].x, IMM[1].xxxx 7: MOV TEMP[4], CONST[1][ADDR[0].x] 8: UARL ADDR[0].x, IMM[1].yyyy 9: MOV TEMP[5], CONST[1][ADDR[0].x] 10: UARL ADDR[0].x, IMM[1].zzzz 11: MOV TEMP[6], CONST[1][ADDR[0].x] 12: MUL TEMP[6], TEMP[6], IN[0].wwww 13: MAD TEMP[5], TEMP[5], IN[1].xxxx, TEMP[6] 14: MAD TEMP[4], TEMP[4], IN[1].yyyy, TEMP[5] 15: UARL ADDR[0].x, IMM[1].wwww 16: MOV TEMP[5], CONST[1][ADDR[0].x] 17: ADD TEMP[4], TEMP[4], TEMP[5] 18: MOV TEMP[5].xyz, TEMP[4].xyzx 19: UARL ADDR[0].x, IMM[3].xxxx 20: MOV TEMP[6].xyz, CONST[1][ADDR[0].x].xyzz 21: ADD TEMP[6].xyz, TEMP[4].xyzz, -TEMP[6].xyzz 22: DP3 TEMP[7].x, TEMP[6].xyzz, TEMP[6].xyzz 23: RSQ TEMP[7].x, TEMP[7].xxxx 24: MUL TEMP[6].xyz, TEMP[6].xyzz, TEMP[7].xxxx 25: DP3 TEMP[7].x, TEMP[0].xyzz, TEMP[6].xyzz 26: MUL TEMP[7].xyz, TEMP[7].xxxx, TEMP[0].xyzz 27: MUL TEMP[7].xyz, IMM[4].xxxx, TEMP[7].xyzz 28: ADD TEMP[6].xyz, TEMP[6].xyzz, -TEMP[7].xyzz 29: MOV TEMP[7].xyz, TEMP[6].xyzx 30: ADD_SAT TEMP[8].x, TEMP[0].yyyy, IMM[4].yyyy 31: UARL ADDR[0].x, IMM[1].xxxx 32: MOV TEMP[9].xyz, CONST[2][ADDR[0].x].xyzz 33: MUL TEMP[8].xyz, TEMP[8].xxxx, TEMP[9].xyzz 34: MUL TEMP[8].xyz, CONST[74].xyzz, TEMP[8].xyzz 35: UARL ADDR[0].x, IMM[1].zzzz 36: UARL ADDR[0].x, IMM[1].zzzz 37: MOV TEMP[9].xyz, CONST[2][ADDR[0].x].xyzz 38: UARL ADDR[0].x, IMM[1].yyyy 39: UARL ADDR[0].x, IMM[1].yyyy 40: MOV TEMP[10].xyz, CONST[2][ADDR[0].x].xyzz 41: DP3 TEMP[0].x, TEMP[0].xyzz, TEMP[9].xyzz 42: MAX TEMP[0].x, IMM[4].zzzz, TEMP[0].xxxx 43: MUL TEMP[0].xyz, TEMP[0].xxxx, TEMP[10].xyzz 44: MUL TEMP[0].xyz, TEMP[0].xyzz, CONST[74].xyzz 45: DP3 TEMP[6].x, TEMP[6].xyzz, TEMP[9].xyzz 46: MAX TEMP[6].x, IMM[4].wwww, TEMP[6].xxxx 47: POW TEMP[6].x, TEMP[6].xxxx, CONST[75].wwww 48: MUL TEMP[6].xyz, TEMP[6].xxxx, TEMP[10].xyzz 49: MAD TEMP[0].xyz, TEMP[6].xyzz, CONST[75].xyzz, TEMP[0].xyzz 50: UARL ADDR[0].x, IMM[1].wwww 51: MOV TEMP[6].xyz, CONST[2][ADDR[0].x].xyzz 52: ADD TEMP[6].xyz, TEMP[4].xyzz, -TEMP[6].xyzz 53: DP3 TEMP[6].x, TEMP[6].xyzz, TEMP[6].xyzz 54: RSQ TEMP[9].x, TEMP[6].xxxx 55: MUL TEMP[9].x, TEMP[9].xxxx, TEMP[6].xxxx 56: CMP TEMP[6].x, -TEMP[6].xxxx, TEMP[9].xxxx, IMM[4].zzzz 57: MOV TEMP[9].x, IMM[4].zzzz 58: UARL ADDR[0].x, IMM[3].yyyy 59: UARL ADDR[0].x, IMM[3].yyyy 60: MOV TEMP[10].x, CONST[2][ADDR[0].x].xxxx 61: MUL TEMP[10].x, IMM[5].xxxx, TEMP[10].xxxx 62: FSLT TEMP[10].x, TEMP[6].xxxx, TEMP[10].xxxx 63: UIF TEMP[10].xxxx :0 64: UARL ADDR[0].x, IMM[3].zzzz 65: MOV TEMP[10], CONST[2][ADDR[0].x] 66: UARL ADDR[0].x, IMM[3].wwww 67: MOV TEMP[11], CONST[2][ADDR[0].x] 68: UARL ADDR[0].x, IMM[7].xxxx 69: MOV TEMP[12], CONST[2][ADDR[0].x] 70: MUL TEMP[12], TEMP[12], TEMP[4].xxxx 71: MAD TEMP[11], TEMP[11], TEMP[4].yyyy, TEMP[12] 72: MAD TEMP[10], TEMP[10], TEMP[4].zzzz, TEMP[11] 73: UARL ADDR[0].x, IMM[7].yyyy 74: MOV TEMP[11], CONST[2][ADDR[0].x] 75: ADD TEMP[10], TEMP[10], TEMP[11] 76: UARL ADDR[0].x, IMM[1].wwww 77: MOV TEMP[11].x, CONST[2][ADDR[0].x].wwww 78: MAX TEMP[12].x, TEMP[10].zzzz, IMM[5].zzzz 79: MIN TEMP[12].x, TEMP[12].xxxx, IMM[5].wwww 80: ADD TEMP[12].x, TEMP[12].xxxx, IMM[5].wwww 81: MUL TEMP[11].x, -TEMP[11].xxxx, TEMP[12].xxxx 82: MUL TEMP[11].x, IMM[5].yyyy, TEMP[11].xxxx 83: EX2 TEMP[11].x, TEMP[11].xxxx 84: MAD TEMP[10].xy, TEMP[10].xyyy, IMM[9].xxxx, IMM[9].xxxx 85: UARL ADDR[0].x, IMM[3].yyyy 86: MOV TEMP[12].x, CONST[2][ADDR[0].x].zzzz 87: MUL TEMP[10].xy, TEMP[10].xyyy, TEMP[12].xxxx 88: MOV TEMP[10].xy, TEMP[10].xyyy 89: TEX TEMP[10], TEMP[10], SAMP[0], RECT 90: MUL_SAT TEMP[10].x, TEMP[11].xxxx, TEMP[10].xxxx 91: MOV TEMP[9].x, TEMP[10].xxxx 92: ELSE :0 93: UARL ADDR[0].x, IMM[3].yyyy 94: UARL ADDR[0].x, IMM[3].yyyy 95: MOV TEMP[10].x, CONST[2][ADDR[0].x].xxxx 96: FSLT TEMP[10].x, TEMP[10].xxxx, TEMP[6].xxxx 97: UIF TEMP[10].xxxx :0 98: UARL ADDR[0].x, IMM[7].zzzz 99: MOV TEMP[10], CONST[2][ADDR[0].x] 100: UARL ADDR[0].x, IMM[7].wwww 101: MOV TEMP[11], CONST[2][ADDR[0].x] 102: UARL ADDR[0].x, IMM[11].xxxx 103: MOV TEMP[12], CONST[2][ADDR[0].x] 104: MUL TEMP[12], TEMP[12], TEMP[4].xxxx 105: MAD TEMP[11], TEMP[11], TEMP[4].yyyy, TEMP[12] 106: MAD TEMP[10], TEMP[10], TEMP[4].zzzz, TEMP[11] 107: UARL ADDR[0].x, IMM[11].yyyy 108: MOV TEMP[11], CONST[2][ADDR[0].x] 109: ADD TEMP[10], TEMP[10], TEMP[11] 110: UARL ADDR[0].x, IMM[1].wwww 111: MOV TEMP[11].xyz, CONST[2][ADDR[0].x].xyzz 112: ADD TEMP[11].xyz, TEMP[4].xyzz, -TEMP[11].xyzz 113: DP3 TEMP[11].x, TEMP[11].xyzz, TEMP[11].xyzz 114: RSQ TEMP[12].x, TEMP[11].xxxx 115: MUL TEMP[12].x, TEMP[12].xxxx, TEMP[11].xxxx 116: CMP TEMP[12].x, -TEMP[11].xxxx, TEMP[12].xxxx, IMM[4].zzzz 117: UARL ADDR[0].x, IMM[3].yyyy 118: MOV TEMP[11].x, CONST[2][ADDR[0].x].yyyy 119: RCP TEMP[11].x, TEMP[11].xxxx 120: MAD TEMP[11].x, TEMP[12].xxxx, TEMP[11].xxxx, IMM[9].yyyy 121: MUL_SAT TEMP[11].x, TEMP[11].xxxx, IMM[9].zzzz 122: UARL ADDR[0].x, IMM[1].wwww 123: MOV TEMP[12].x, CONST[2][ADDR[0].x].wwww 124: MAX TEMP[13].x, TEMP[10].zzzz, IMM[5].zzzz 125: MIN TEMP[13].x, TEMP[13].xxxx, IMM[5].wwww 126: ADD TEMP[13].x, TEMP[13].xxxx, IMM[5].wwww 127: MUL TEMP[12].x, -TEMP[12].xxxx, TEMP[13].xxxx 128: MUL TEMP[12].x, IMM[5].yyyy, TEMP[12].xxxx 129: EX2 TEMP[12].x, TEMP[12].xxxx 130: MAD TEMP[10].xy, TEMP[10].xyyy, IMM[9].xxxx, IMM[9].xxxx 131: UARL ADDR[0].x, IMM[3].yyyy 132: MOV TEMP[13].x, CONST[2][ADDR[0].x].zzzz 133: MUL TEMP[10].xy, TEMP[10].xyyy, TEMP[13].xxxx 134: MOV TEMP[10].xy, TEMP[10].xyyy 135: TEX TEMP[10], TEMP[10], SAMP[1], RECT 136: MUL_SAT TEMP[10].x, TEMP[12].xxxx, TEMP[10].xxxx 137: MUL TEMP[12].x, IMM[4].xxxx, TEMP[11].xxxx 138: ADD TEMP[12].x, IMM[9].wwww, -TEMP[12].xxxx 139: MUL TEMP[12].x, TEMP[11].xxxx, TEMP[12].xxxx 140: MUL TEMP[11].x, TEMP[11].xxxx, TEMP[12].xxxx 141: LRP TEMP[9].x, TEMP[11].xxxx, IMM[5].wwww, TEMP[10].xxxx 142: ELSE :0 143: UARL ADDR[0].x, IMM[3].zzzz 144: MOV TEMP[10], CONST[2][ADDR[0].x] 145: UARL ADDR[0].x, IMM[3].wwww 146: MOV TEMP[11], CONST[2][ADDR[0].x] 147: UARL ADDR[0].x, IMM[7].xxxx 148: MOV TEMP[12], CONST[2][ADDR[0].x] 149: MUL TEMP[12], TEMP[12], TEMP[4].xxxx 150: MAD TEMP[11], TEMP[11], TEMP[4].yyyy, TEMP[12] 151: MAD TEMP[10], TEMP[10], TEMP[4].zzzz, TEMP[11] 152: UARL ADDR[0].x, IMM[7].yyyy 153: MOV TEMP[11], CONST[2][ADDR[0].x] 154: ADD TEMP[10], TEMP[10], TEMP[11] 155: UARL ADDR[0].x, IMM[7].zzzz 156: MOV TEMP[11], CONST[2][ADDR[0].x] 157: UARL ADDR[0].x, IMM[7].wwww 158: MOV TEMP[12], CONST[2][ADDR[0].x] 159: UARL ADDR[0].x, IMM[11].xxxx 160: MOV TEMP[13], CONST[2][ADDR[0].x] 161: MUL TEMP[13], TEMP[13], TEMP[4].xxxx 162: MAD TEMP[12], TEMP[12], TEMP[4].yyyy, TEMP[13] 163: MAD TEMP[4], TEMP[11], TEMP[4].zzzz, TEMP[12] 164: UARL ADDR[0].x, IMM[11].yyyy 165: MOV TEMP[11], CONST[2][ADDR[0].x] 166: ADD TEMP[4], TEMP[4], TEMP[11] 167: UARL ADDR[0].x, IMM[3].yyyy 168: UARL ADDR[0].x, IMM[3].yyyy 169: MOV TEMP[11].x, CONST[2][ADDR[0].x].xxxx 170: MUL TEMP[12].x, IMM[5].xxxx, TEMP[11].xxxx 171: ADD TEMP[6].x, TEMP[6].xxxx, -TEMP[12].xxxx 172: ADD TEMP[11].x, TEMP[11].xxxx, -TEMP[12].xxxx 173: RCP TEMP[11].x, TEMP[11].xxxx 174: MUL_SAT TEMP[6].x, TEMP[6].xxxx, TEMP[11].xxxx 175: UARL ADDR[0].x, IMM[1].wwww 176: UARL ADDR[0].x, IMM[1].wwww 177: MOV TEMP[11].x, CONST[2][ADDR[0].x].wwww 178: UARL ADDR[0].x, IMM[3].yyyy 179: UARL ADDR[0].x, IMM[3].yyyy 180: MOV TEMP[12].x, CONST[2][ADDR[0].x].zzzz 181: MAX TEMP[13].x, TEMP[10].zzzz, IMM[5].zzzz 182: MIN TEMP[13].x, TEMP[13].xxxx, IMM[5].wwww 183: ADD TEMP[13].x, TEMP[13].xxxx, IMM[5].wwww 184: MUL TEMP[13].x, -TEMP[11].xxxx, TEMP[13].xxxx 185: MUL TEMP[13].x, IMM[5].yyyy, TEMP[13].xxxx 186: EX2 TEMP[13].x, TEMP[13].xxxx 187: MAD TEMP[10].xy, TEMP[10].xyyy, IMM[9].xxxx, IMM[9].xxxx 188: MUL TEMP[10].xy, TEMP[10].xyyy, TEMP[12].xxxx 189: MOV TEMP[10].xy, TEMP[10].xyyy 190: TEX TEMP[10], TEMP[10], SAMP[0], RECT 191: MUL_SAT TEMP[10].x, TEMP[13].xxxx, TEMP[10].xxxx 192: MAX TEMP[13].x, TEMP[4].zzzz, IMM[5].zzzz 193: MIN TEMP[13].x, TEMP[13].xxxx, IMM[5].wwww 194: ADD TEMP[13].x, TEMP[13].xxxx, IMM[5].wwww 195: MUL TEMP[11].x, -TEMP[11].xxxx, TEMP[13].xxxx 196: MUL TEMP[11].x, IMM[5].yyyy, TEMP[11].xxxx 197: EX2 TEMP[11].x, TEMP[11].xxxx 198: MAD TEMP[4].xy, TEMP[4].xyyy, IMM[9].xxxx, IMM[9].xxxx 199: MUL TEMP[4].xy, TEMP[4].xyyy, TEMP[12].xxxx 200: MOV TEMP[4].xy, TEMP[4].xyyy 201: TEX TEMP[4], TEMP[4], SAMP[1], RECT 202: MUL_SAT TEMP[4].x, TEMP[11].xxxx, TEMP[4].xxxx 203: MUL TEMP[11].x, IMM[4].xxxx, TEMP[6].xxxx 204: ADD TEMP[11].x, IMM[9].wwww, -TEMP[11].xxxx 205: MUL TEMP[11].x, TEMP[6].xxxx, TEMP[11].xxxx 206: MUL TEMP[6].x, TEMP[6].xxxx, TEMP[11].xxxx 207: LRP TEMP[9].x, TEMP[6].xxxx, TEMP[4].xxxx, TEMP[10].xxxx 208: ENDIF 209: ENDIF 210: ADD TEMP[4].x, TEMP[9].xxxx, IMM[9].yyyy 211: MUL_SAT TEMP[4].x, TEMP[4].xxxx, IMM[9].zzzz 212: MUL TEMP[6].x, IMM[4].xxxx, TEMP[4].xxxx 213: ADD TEMP[6].x, IMM[9].wwww, -TEMP[6].xxxx 214: MUL TEMP[6].x, TEMP[4].xxxx, TEMP[6].xxxx 215: MUL TEMP[4].x, TEMP[4].xxxx, TEMP[6].xxxx 216: MUL TEMP[0].xyz, TEMP[0].xyzz, TEMP[4].xxxx 217: ADD TEMP[8].xyz, TEMP[8].xyzz, TEMP[0].xyzz 218: MOV TEMP[0].x, IMM[11].zzzz 219: BGNLOOP :0 220: ISGE TEMP[4].x, TEMP[0].xxxx, CONST[3].xxxx 221: UIF TEMP[4].xxxx :0 222: BRK 223: ENDIF 224: UMUL TEMP[6].x, TEMP[0].xxxx, IMM[7].yyyy 225: UARL ADDR[0].x, TEMP[6].xxxx 226: MOV TEMP[9].x, CONST[ADDR[0].x+4].xxxx 227: UADD TEMP[10].x, TEMP[6].xxxx, IMM[11].wwww 228: UARL ADDR[0].x, TEMP[10].xxxx 229: MOV TEMP[9].y, CONST[ADDR[0].x+4].xxxx 230: UADD TEMP[11].x, TEMP[6].xxxx, IMM[12].xxxx 231: UARL ADDR[0].x, TEMP[11].xxxx 232: MOV TEMP[9].z, CONST[ADDR[0].x+4].xxxx 233: UADD TEMP[12].x, TEMP[6].xxxx, IMM[12].yyyy 234: UARL ADDR[0].x, TEMP[12].xxxx 235: MOV TEMP[13].x, CONST[ADDR[0].x+4].xxxx 236: UADD TEMP[14].x, TEMP[6].xxxx, IMM[7].xxxx 237: UARL ADDR[0].x, TEMP[14].xxxx 238: MOV TEMP[13].y, CONST[ADDR[0].x+4].xxxx 239: UADD TEMP[15].x, TEMP[6].xxxx, IMM[3].wwww 240: UARL ADDR[0].x, TEMP[15].xxxx 241: MOV TEMP[13].z, CONST[ADDR[0].x+4].xxxx 242: UADD TEMP[16].x, TEMP[6].xxxx, IMM[3].zzzz 243: UARL ADDR[0].x, TEMP[16].xxxx 244: MOV TEMP[17].x, CONST[ADDR[0].x+4].xxxx 245: ADD TEMP[18].xyz, TEMP[9].xyzz, -TEMP[5].xyzz 246: DP3 TEMP[19].x, TEMP[18].xyzz, TEMP[18].xyzz 247: RSQ TEMP[20].x, TEMP[19].xxxx 248: MUL TEMP[20].x, TEMP[20].xxxx, TEMP[19].xxxx 249: CMP TEMP[21].x, -TEMP[19].xxxx, TEMP[20].xxxx, IMM[4].zzzz 250: RCP TEMP[22].x, TEMP[21].xxxx 251: MUL TEMP[23].xyz, TEMP[18].xyzz, TEMP[22].xxxx 252: DP3 TEMP[24].x, TEMP[1].xyzz, TEMP[23].xyzz 253: MAX TEMP[25].x, IMM[4].zzzz, TEMP[24].xxxx 254: MUL TEMP[26].xyz, TEMP[25].xxxx, TEMP[13].xyzz 255: MUL TEMP[27].xyz, TEMP[26].xyzz, TEMP[2].xyzz 256: DP3 TEMP[28].x, TEMP[7].xyzz, TEMP[23].xyzz 257: MAX TEMP[29].x, IMM[4].wwww, TEMP[28].xxxx 258: POW TEMP[30].x, TEMP[29].xxxx, TEMP[3].wwww 259: MUL TEMP[31].xyz, TEMP[30].xxxx, TEMP[13].xyzz 260: MAD TEMP[27].xyz, TEMP[31].xyzz, TEMP[3].xyzz, TEMP[27].xyzz 261: MUL TEMP[32].x, TEMP[17].xxxx, IMM[9].xxxx 262: ADD TEMP[33].x, TEMP[21].xxxx, -TEMP[32].xxxx 263: ADD TEMP[34].x, TEMP[17].xxxx, -TEMP[32].xxxx 264: RCP TEMP[35].x, TEMP[34].xxxx 265: MUL_SAT TEMP[36].x, TEMP[33].xxxx, TEMP[35].xxxx 266: MUL TEMP[37].x, IMM[4].xxxx, TEMP[36].xxxx 267: ADD TEMP[38].x, IMM[9].wwww, -TEMP[37].xxxx 268: MUL TEMP[39].x, TEMP[36].xxxx, TEMP[38].xxxx 269: MUL TEMP[40].x, TEMP[36].xxxx, TEMP[39].xxxx 270: ADD TEMP[41].x, IMM[5].wwww, -TEMP[40].xxxx 271: MUL TEMP[27].xyz, TEMP[27].xyzz, TEMP[41].xxxx 272: ADD TEMP[8].xyz, TEMP[8].xyzz, TEMP[27].xyzz 273: UADD TEMP[0].x, TEMP[0].xxxx, IMM[11].wwww 274: ENDLOOP :0 275: MOV TEMP[0].xyz, TEMP[8].xyzx 276: MOV OUT[0], TEMP[0] 277: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %22 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0 %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0 %24 = call float @llvm.SI.load.const(<16 x i8> %23, i32 48) %25 = call float @llvm.SI.load.const(<16 x i8> %23, i32 1184) %26 = call float @llvm.SI.load.const(<16 x i8> %23, i32 1188) %27 = call float @llvm.SI.load.const(<16 x i8> %23, i32 1192) %28 = call float @llvm.SI.load.const(<16 x i8> %23, i32 1200) %29 = call float @llvm.SI.load.const(<16 x i8> %23, i32 1204) %30 = call float @llvm.SI.load.const(<16 x i8> %23, i32 1208) %31 = call float @llvm.SI.load.const(<16 x i8> %23, i32 1212) %32 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 1 %33 = load <16 x i8> addrspace(2)* %32, !tbaa !0 %34 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 2 %35 = load <16 x i8> addrspace(2)* %34, !tbaa !0 %36 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0 %37 = load <32 x i8> addrspace(2)* %36, !tbaa !0 %38 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0 %39 = load <16 x i8> addrspace(2)* %38, !tbaa !0 %40 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 1 %41 = load <32 x i8> addrspace(2)* %40, !tbaa !0 %42 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 1 %43 = load <16 x i8> addrspace(2)* %42, !tbaa !0 %44 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %7) %45 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %7) %46 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %5, <2 x i32> %7) %47 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %5, <2 x i32> %7) %48 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %5, <2 x i32> %7) %49 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %5, <2 x i32> %7) %50 = fmul float %44, %44 %51 = fmul float %45, %45 %52 = fadd float %51, %50 %53 = fmul float %46, %46 %54 = fadd float %52, %53 %55 = call float @llvm.AMDGPU.rsq(float %54) %56 = fmul float %44, %55 %57 = fmul float %45, %55 %58 = fmul float %46, %55 %59 = shl i32 14, 4 %60 = call float @llvm.SI.load.const(<16 x i8> %33, i32 %59) %61 = shl i32 14, 4 %62 = add i32 %61, 4 %63 = call float @llvm.SI.load.const(<16 x i8> %33, i32 %62) %64 = shl i32 14, 4 %65 = add i32 %64, 8 %66 = call float @llvm.SI.load.const(<16 x i8> %33, i32 %65) %67 = shl i32 13, 4 %68 = call float @llvm.SI.load.const(<16 x i8> %33, i32 %67) %69 = shl i32 13, 4 %70 = add i32 %69, 4 %71 = call float @llvm.SI.load.const(<16 x i8> %33, i32 %70) %72 = shl i32 13, 4 %73 = add i32 %72, 8 %74 = call float @llvm.SI.load.const(<16 x i8> %33, i32 %73) %75 = shl i32 12, 4 %76 = call float @llvm.SI.load.const(<16 x i8> %33, i32 %75) %77 = shl i32 12, 4 %78 = add i32 %77, 4 %79 = call float @llvm.SI.load.const(<16 x i8> %33, i32 %78) %80 = shl i32 12, 4 %81 = add i32 %80, 8 %82 = call float @llvm.SI.load.const(<16 x i8> %33, i32 %81) %83 = fmul float %76, %47 %84 = fmul float %79, %47 %85 = fmul float %82, %47 %86 = fmul float %68, %48 %87 = fadd float %86, %83 %88 = fmul float %71, %48 %89 = fadd float %88, %84 %90 = fmul float %74, %48 %91 = fadd float %90, %85 %92 = fmul float %60, %49 %93 = fadd float %92, %87 %94 = fmul float %63, %49 %95 = fadd float %94, %89 %96 = fmul float %66, %49 %97 = fadd float %96, %91 %98 = shl i32 15, 4 %99 = call float @llvm.SI.load.const(<16 x i8> %33, i32 %98) %100 = shl i32 15, 4 %101 = add i32 %100, 4 %102 = call float @llvm.SI.load.const(<16 x i8> %33, i32 %101) %103 = shl i32 15, 4 %104 = add i32 %103, 8 %105 = call float @llvm.SI.load.const(<16 x i8> %33, i32 %104) %106 = fadd float %93, %99 %107 = fadd float %95, %102 %108 = fadd float %97, %105 %109 = shl i32 20, 4 %110 = call float @llvm.SI.load.const(<16 x i8> %33, i32 %109) %111 = shl i32 20, 4 %112 = add i32 %111, 4 %113 = call float @llvm.SI.load.const(<16 x i8> %33, i32 %112) %114 = shl i32 20, 4 %115 = add i32 %114, 8 %116 = call float @llvm.SI.load.const(<16 x i8> %33, i32 %115) %117 = fsub float -0.000000e+00, %110 %118 = fadd float %106, %117 %119 = fsub float -0.000000e+00, %113 %120 = fadd float %107, %119 %121 = fsub float -0.000000e+00, %116 %122 = fadd float %108, %121 %123 = fmul float %118, %118 %124 = fmul float %120, %120 %125 = fadd float %124, %123 %126 = fmul float %122, %122 %127 = fadd float %125, %126 %128 = call float @llvm.AMDGPU.rsq(float %127) %129 = fmul float %118, %128 %130 = fmul float %120, %128 %131 = fmul float %122, %128 %132 = fmul float %56, %129 %133 = fmul float %57, %130 %134 = fadd float %133, %132 %135 = fmul float %58, %131 %136 = fadd float %134, %135 %137 = fmul float %136, %56 %138 = fmul float %136, %57 %139 = fmul float %136, %58 %140 = fmul float 2.000000e+00, %137 %141 = fmul float 2.000000e+00, %138 %142 = fmul float 2.000000e+00, %139 %143 = fsub float -0.000000e+00, %140 %144 = fadd float %129, %143 %145 = fsub float -0.000000e+00, %141 %146 = fadd float %130, %145 %147 = fsub float -0.000000e+00, %142 %148 = fadd float %131, %147 %149 = fadd float %57, 0x3FF0CCCCC0000000 %150 = call float @llvm.AMDIL.clamp.(float %149, float 0.000000e+00, float 1.000000e+00) %151 = shl i32 14, 4 %152 = call float @llvm.SI.load.const(<16 x i8> %35, i32 %151) %153 = shl i32 14, 4 %154 = add i32 %153, 4 %155 = call float @llvm.SI.load.const(<16 x i8> %35, i32 %154) %156 = shl i32 14, 4 %157 = add i32 %156, 8 %158 = call float @llvm.SI.load.const(<16 x i8> %35, i32 %157) %159 = fmul float %150, %152 %160 = fmul float %150, %155 %161 = fmul float %150, %158 %162 = fmul float %25, %159 %163 = fmul float %26, %160 %164 = fmul float %27, %161 %165 = shl i32 12, 4 %166 = call float @llvm.SI.load.const(<16 x i8> %35, i32 %165) %167 = shl i32 12, 4 %168 = add i32 %167, 4 %169 = call float @llvm.SI.load.const(<16 x i8> %35, i32 %168) %170 = shl i32 12, 4 %171 = add i32 %170, 8 %172 = call float @llvm.SI.load.const(<16 x i8> %35, i32 %171) %173 = shl i32 13, 4 %174 = call float @llvm.SI.load.const(<16 x i8> %35, i32 %173) %175 = shl i32 13, 4 %176 = add i32 %175, 4 %177 = call float @llvm.SI.load.const(<16 x i8> %35, i32 %176) %178 = shl i32 13, 4 %179 = add i32 %178, 8 %180 = call float @llvm.SI.load.const(<16 x i8> %35, i32 %179) %181 = fmul float %56, %166 %182 = fmul float %57, %169 %183 = fadd float %182, %181 %184 = fmul float %58, %172 %185 = fadd float %183, %184 %186 = fcmp uge float 0.000000e+00, %185 %187 = select i1 %186, float 0.000000e+00, float %185 %188 = fmul float %187, %174 %189 = fmul float %187, %177 %190 = fmul float %187, %180 %191 = fmul float %188, %25 %192 = fmul float %189, %26 %193 = fmul float %190, %27 %194 = fmul float %144, %166 %195 = fmul float %146, %169 %196 = fadd float %195, %194 %197 = fmul float %148, %172 %198 = fadd float %196, %197 %199 = fcmp uge float 0x3F50624DE0000000, %198 %200 = select i1 %199, float 0x3F50624DE0000000, float %198 %201 = call float @llvm.pow.f32(float %200, float %31) %202 = fmul float %201, %174 %203 = fmul float %201, %177 %204 = fmul float %201, %180 %205 = fmul float %202, %28 %206 = fadd float %205, %191 %207 = fmul float %203, %29 %208 = fadd float %207, %192 %209 = fmul float %204, %30 %210 = fadd float %209, %193 %211 = shl i32 15, 4 %212 = call float @llvm.SI.load.const(<16 x i8> %35, i32 %211) %213 = shl i32 15, 4 %214 = add i32 %213, 4 %215 = call float @llvm.SI.load.const(<16 x i8> %35, i32 %214) %216 = shl i32 15, 4 %217 = add i32 %216, 8 %218 = call float @llvm.SI.load.const(<16 x i8> %35, i32 %217) %219 = fsub float -0.000000e+00, %212 %220 = fadd float %106, %219 %221 = fsub float -0.000000e+00, %215 %222 = fadd float %107, %221 %223 = fsub float -0.000000e+00, %218 %224 = fadd float %108, %223 %225 = fmul float %220, %220 %226 = fmul float %222, %222 %227 = fadd float %226, %225 %228 = fmul float %224, %224 %229 = fadd float %227, %228 %230 = call float @llvm.AMDGPU.rsq(float %229) %231 = fmul float %230, %229 %232 = fsub float -0.000000e+00, %229 %233 = call float @llvm.AMDGPU.cndlt(float %232, float %231, float 0.000000e+00) %234 = shl i32 16, 4 %235 = call float @llvm.SI.load.const(<16 x i8> %35, i32 %234) %236 = fmul float 0x3FE99999A0000000, %235 %237 = fcmp olt float %233, %236 %238 = sext i1 %237 to i32 %239 = bitcast i32 %238 to float %240 = bitcast float %239 to i32 %241 = icmp ne i32 %240, 0 br i1 %241, label %IF, label %ELSE IF: ; preds = %main_body %242 = shl i32 6, 4 %243 = call float @llvm.SI.load.const(<16 x i8> %35, i32 %242) %244 = shl i32 6, 4 %245 = add i32 %244, 4 %246 = call float @llvm.SI.load.const(<16 x i8> %35, i32 %245) %247 = shl i32 6, 4 %248 = add i32 %247, 8 %249 = call float @llvm.SI.load.const(<16 x i8> %35, i32 %248) %250 = shl i32 5, 4 %251 = call float @llvm.SI.load.const(<16 x i8> %35, i32 %250) %252 = shl i32 5, 4 %253 = add i32 %252, 4 %254 = call float @llvm.SI.load.const(<16 x i8> %35, i32 %253) %255 = shl i32 5, 4 %256 = add i32 %255, 8 %257 = call float @llvm.SI.load.const(<16 x i8> %35, i32 %256) %258 = shl i32 4, 4 %259 = call float @llvm.SI.load.const(<16 x i8> %35, i32 %258) %260 = shl i32 4, 4 %261 = add i32 %260, 4 %262 = call float @llvm.SI.load.const(<16 x i8> %35, i32 %261) %263 = shl i32 4, 4 %264 = add i32 %263, 8 %265 = call float @llvm.SI.load.const(<16 x i8> %35, i32 %264) %266 = fmul float %259, %106 %267 = fmul float %262, %106 %268 = fmul float %265, %106 %269 = fmul float %251, %107 %270 = fadd float %269, %266 %271 = fmul float %254, %107 %272 = fadd float %271, %267 %273 = fmul float %257, %107 %274 = fadd float %273, %268 %275 = fmul float %243, %108 %276 = fadd float %275, %270 %277 = fmul float %246, %108 %278 = fadd float %277, %272 %279 = fmul float %249, %108 %280 = fadd float %279, %274 %281 = shl i32 7, 4 %282 = call float @llvm.SI.load.const(<16 x i8> %35, i32 %281) %283 = shl i32 7, 4 %284 = add i32 %283, 4 %285 = call float @llvm.SI.load.const(<16 x i8> %35, i32 %284) %286 = shl i32 7, 4 %287 = add i32 %286, 8 %288 = call float @llvm.SI.load.const(<16 x i8> %35, i32 %287) %289 = fadd float %276, %282 %290 = fadd float %278, %285 %291 = fadd float %280, %288 %292 = shl i32 15, 4 %293 = add i32 %292, 12 %294 = call float @llvm.SI.load.const(<16 x i8> %35, i32 %293) %295 = fcmp uge float %291, -1.000000e+00 %296 = select i1 %295, float %291, float -1.000000e+00 %297 = fcmp uge float %296, 1.000000e+00 %298 = select i1 %297, float 1.000000e+00, float %296 %299 = fadd float %298, 1.000000e+00 %300 = fsub float -0.000000e+00, %294 %301 = fmul float %300, %299 %302 = fmul float 0x3FE7154760000000, %301 %303 = call float @llvm.AMDIL.exp.(float %302) %304 = fmul float %289, 5.000000e-01 %305 = fadd float %304, 5.000000e-01 %306 = fmul float %290, 5.000000e-01 %307 = fadd float %306, 5.000000e-01 %308 = shl i32 16, 4 %309 = add i32 %308, 8 %310 = call float @llvm.SI.load.const(<16 x i8> %35, i32 %309) %311 = fmul float %305, %310 %312 = fmul float %307, %310 %313 = bitcast float %311 to i32 %314 = bitcast float %312 to i32 %315 = insertelement <2 x i32> undef, i32 %313, i32 0 %316 = insertelement <2 x i32> %315, i32 %314, i32 1 %317 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %316, <32 x i8> %37, <16 x i8> %39, i32 5) %318 = extractelement <4 x float> %317, i32 0 %319 = fmul float %303, %318 %320 = call float @llvm.AMDIL.clamp.(float %319, float 0.000000e+00, float 1.000000e+00) br label %ENDIF ELSE: ; preds = %main_body %321 = shl i32 16, 4 %322 = call float @llvm.SI.load.const(<16 x i8> %35, i32 %321) %323 = fcmp olt float %322, %233 %324 = sext i1 %323 to i32 %325 = bitcast i32 %324 to float %326 = bitcast float %325 to i32 %327 = icmp ne i32 %326, 0 br i1 %327, label %IF219, label %ELSE220 ENDIF: ; preds = %IF219, %ELSE220, %IF %temp36.0 = phi float [ %320, %IF ], [ %461, %IF219 ], [ %629, %ELSE220 ] %328 = fadd float %temp36.0, 0xBFE99999A0000000 %329 = fmul float %328, 0x4014000020000000 %330 = call float @llvm.AMDIL.clamp.(float %329, float 0.000000e+00, float 1.000000e+00) %331 = fmul float 2.000000e+00, %330 %332 = fsub float -0.000000e+00, %331 %333 = fadd float 3.000000e+00, %332 %334 = fmul float %330, %333 %335 = fmul float %330, %334 %336 = fmul float %206, %335 %337 = fmul float %208, %335 %338 = fmul float %210, %335 %339 = fadd float %162, %336 %340 = fadd float %163, %337 %341 = fadd float %164, %338 %342 = bitcast float %24 to i32 %343 = fsub float -0.000000e+00, %106 %344 = fsub float -0.000000e+00, %107 %345 = fsub float -0.000000e+00, %108 br label %LOOP IF219: ; preds = %ELSE %346 = shl i32 10, 4 %347 = call float @llvm.SI.load.const(<16 x i8> %35, i32 %346) %348 = shl i32 10, 4 %349 = add i32 %348, 4 %350 = call float @llvm.SI.load.const(<16 x i8> %35, i32 %349) %351 = shl i32 10, 4 %352 = add i32 %351, 8 %353 = call float @llvm.SI.load.const(<16 x i8> %35, i32 %352) %354 = shl i32 9, 4 %355 = call float @llvm.SI.load.const(<16 x i8> %35, i32 %354) %356 = shl i32 9, 4 %357 = add i32 %356, 4 %358 = call float @llvm.SI.load.const(<16 x i8> %35, i32 %357) %359 = shl i32 9, 4 %360 = add i32 %359, 8 %361 = call float @llvm.SI.load.const(<16 x i8> %35, i32 %360) %362 = shl i32 8, 4 %363 = call float @llvm.SI.load.const(<16 x i8> %35, i32 %362) %364 = shl i32 8, 4 %365 = add i32 %364, 4 %366 = call float @llvm.SI.load.const(<16 x i8> %35, i32 %365) %367 = shl i32 8, 4 %368 = add i32 %367, 8 %369 = call float @llvm.SI.load.const(<16 x i8> %35, i32 %368) %370 = fmul float %363, %106 %371 = fmul float %366, %106 %372 = fmul float %369, %106 %373 = fmul float %355, %107 %374 = fadd float %373, %370 %375 = fmul float %358, %107 %376 = fadd float %375, %371 %377 = fmul float %361, %107 %378 = fadd float %377, %372 %379 = fmul float %347, %108 %380 = fadd float %379, %374 %381 = fmul float %350, %108 %382 = fadd float %381, %376 %383 = fmul float %353, %108 %384 = fadd float %383, %378 %385 = shl i32 11, 4 %386 = call float @llvm.SI.load.const(<16 x i8> %35, i32 %385) %387 = shl i32 11, 4 %388 = add i32 %387, 4 %389 = call float @llvm.SI.load.const(<16 x i8> %35, i32 %388) %390 = shl i32 11, 4 %391 = add i32 %390, 8 %392 = call float @llvm.SI.load.const(<16 x i8> %35, i32 %391) %393 = fadd float %380, %386 %394 = fadd float %382, %389 %395 = fadd float %384, %392 %396 = shl i32 15, 4 %397 = call float @llvm.SI.load.const(<16 x i8> %35, i32 %396) %398 = shl i32 15, 4 %399 = add i32 %398, 4 %400 = call float @llvm.SI.load.const(<16 x i8> %35, i32 %399) %401 = shl i32 15, 4 %402 = add i32 %401, 8 %403 = call float @llvm.SI.load.const(<16 x i8> %35, i32 %402) %404 = fsub float -0.000000e+00, %397 %405 = fadd float %106, %404 %406 = fsub float -0.000000e+00, %400 %407 = fadd float %107, %406 %408 = fsub float -0.000000e+00, %403 %409 = fadd float %108, %408 %410 = fmul float %405, %405 %411 = fmul float %407, %407 %412 = fadd float %411, %410 %413 = fmul float %409, %409 %414 = fadd float %412, %413 %415 = call float @llvm.AMDGPU.rsq(float %414) %416 = fmul float %415, %414 %417 = fsub float -0.000000e+00, %414 %418 = call float @llvm.AMDGPU.cndlt(float %417, float %416, float 0.000000e+00) %419 = shl i32 16, 4 %420 = add i32 %419, 4 %421 = call float @llvm.SI.load.const(<16 x i8> %35, i32 %420) %422 = fdiv float 1.000000e+00, %421 %423 = fmul float %418, %422 %424 = fadd float %423, 0xBFE99999A0000000 %425 = fmul float %424, 0x4014000020000000 %426 = call float @llvm.AMDIL.clamp.(float %425, float 0.000000e+00, float 1.000000e+00) %427 = shl i32 15, 4 %428 = add i32 %427, 12 %429 = call float @llvm.SI.load.const(<16 x i8> %35, i32 %428) %430 = fcmp uge float %395, -1.000000e+00 %431 = select i1 %430, float %395, float -1.000000e+00 %432 = fcmp uge float %431, 1.000000e+00 %433 = select i1 %432, float 1.000000e+00, float %431 %434 = fadd float %433, 1.000000e+00 %435 = fsub float -0.000000e+00, %429 %436 = fmul float %435, %434 %437 = fmul float 0x3FE7154760000000, %436 %438 = call float @llvm.AMDIL.exp.(float %437) %439 = fmul float %393, 5.000000e-01 %440 = fadd float %439, 5.000000e-01 %441 = fmul float %394, 5.000000e-01 %442 = fadd float %441, 5.000000e-01 %443 = shl i32 16, 4 %444 = add i32 %443, 8 %445 = call float @llvm.SI.load.const(<16 x i8> %35, i32 %444) %446 = fmul float %440, %445 %447 = fmul float %442, %445 %448 = bitcast float %446 to i32 %449 = bitcast float %447 to i32 %450 = insertelement <2 x i32> undef, i32 %448, i32 0 %451 = insertelement <2 x i32> %450, i32 %449, i32 1 %452 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %451, <32 x i8> %41, <16 x i8> %43, i32 5) %453 = extractelement <4 x float> %452, i32 0 %454 = fmul float %438, %453 %455 = call float @llvm.AMDIL.clamp.(float %454, float 0.000000e+00, float 1.000000e+00) %456 = fmul float 2.000000e+00, %426 %457 = fsub float -0.000000e+00, %456 %458 = fadd float 3.000000e+00, %457 %459 = fmul float %426, %458 %460 = fmul float %426, %459 %461 = call float @llvm.AMDGPU.lrp(float %460, float 1.000000e+00, float %455) br label %ENDIF ELSE220: ; preds = %ELSE %462 = shl i32 6, 4 %463 = call float @llvm.SI.load.const(<16 x i8> %35, i32 %462) %464 = shl i32 6, 4 %465 = add i32 %464, 4 %466 = call float @llvm.SI.load.const(<16 x i8> %35, i32 %465) %467 = shl i32 6, 4 %468 = add i32 %467, 8 %469 = call float @llvm.SI.load.const(<16 x i8> %35, i32 %468) %470 = shl i32 5, 4 %471 = call float @llvm.SI.load.const(<16 x i8> %35, i32 %470) %472 = shl i32 5, 4 %473 = add i32 %472, 4 %474 = call float @llvm.SI.load.const(<16 x i8> %35, i32 %473) %475 = shl i32 5, 4 %476 = add i32 %475, 8 %477 = call float @llvm.SI.load.const(<16 x i8> %35, i32 %476) %478 = shl i32 4, 4 %479 = call float @llvm.SI.load.const(<16 x i8> %35, i32 %478) %480 = shl i32 4, 4 %481 = add i32 %480, 4 %482 = call float @llvm.SI.load.const(<16 x i8> %35, i32 %481) %483 = shl i32 4, 4 %484 = add i32 %483, 8 %485 = call float @llvm.SI.load.const(<16 x i8> %35, i32 %484) %486 = fmul float %479, %106 %487 = fmul float %482, %106 %488 = fmul float %485, %106 %489 = fmul float %471, %107 %490 = fadd float %489, %486 %491 = fmul float %474, %107 %492 = fadd float %491, %487 %493 = fmul float %477, %107 %494 = fadd float %493, %488 %495 = fmul float %463, %108 %496 = fadd float %495, %490 %497 = fmul float %466, %108 %498 = fadd float %497, %492 %499 = fmul float %469, %108 %500 = fadd float %499, %494 %501 = shl i32 7, 4 %502 = call float @llvm.SI.load.const(<16 x i8> %35, i32 %501) %503 = shl i32 7, 4 %504 = add i32 %503, 4 %505 = call float @llvm.SI.load.const(<16 x i8> %35, i32 %504) %506 = shl i32 7, 4 %507 = add i32 %506, 8 %508 = call float @llvm.SI.load.const(<16 x i8> %35, i32 %507) %509 = fadd float %496, %502 %510 = fadd float %498, %505 %511 = fadd float %500, %508 %512 = shl i32 10, 4 %513 = call float @llvm.SI.load.const(<16 x i8> %35, i32 %512) %514 = shl i32 10, 4 %515 = add i32 %514, 4 %516 = call float @llvm.SI.load.const(<16 x i8> %35, i32 %515) %517 = shl i32 10, 4 %518 = add i32 %517, 8 %519 = call float @llvm.SI.load.const(<16 x i8> %35, i32 %518) %520 = shl i32 9, 4 %521 = call float @llvm.SI.load.const(<16 x i8> %35, i32 %520) %522 = shl i32 9, 4 %523 = add i32 %522, 4 %524 = call float @llvm.SI.load.const(<16 x i8> %35, i32 %523) %525 = shl i32 9, 4 %526 = add i32 %525, 8 %527 = call float @llvm.SI.load.const(<16 x i8> %35, i32 %526) %528 = shl i32 8, 4 %529 = call float @llvm.SI.load.const(<16 x i8> %35, i32 %528) %530 = shl i32 8, 4 %531 = add i32 %530, 4 %532 = call float @llvm.SI.load.const(<16 x i8> %35, i32 %531) %533 = shl i32 8, 4 %534 = add i32 %533, 8 %535 = call float @llvm.SI.load.const(<16 x i8> %35, i32 %534) %536 = fmul float %529, %106 %537 = fmul float %532, %106 %538 = fmul float %535, %106 %539 = fmul float %521, %107 %540 = fadd float %539, %536 %541 = fmul float %524, %107 %542 = fadd float %541, %537 %543 = fmul float %527, %107 %544 = fadd float %543, %538 %545 = fmul float %513, %108 %546 = fadd float %545, %540 %547 = fmul float %516, %108 %548 = fadd float %547, %542 %549 = fmul float %519, %108 %550 = fadd float %549, %544 %551 = shl i32 11, 4 %552 = call float @llvm.SI.load.const(<16 x i8> %35, i32 %551) %553 = shl i32 11, 4 %554 = add i32 %553, 4 %555 = call float @llvm.SI.load.const(<16 x i8> %35, i32 %554) %556 = shl i32 11, 4 %557 = add i32 %556, 8 %558 = call float @llvm.SI.load.const(<16 x i8> %35, i32 %557) %559 = fadd float %546, %552 %560 = fadd float %548, %555 %561 = fadd float %550, %558 %562 = shl i32 16, 4 %563 = call float @llvm.SI.load.const(<16 x i8> %35, i32 %562) %564 = fmul float 0x3FE99999A0000000, %563 %565 = fsub float -0.000000e+00, %564 %566 = fadd float %233, %565 %567 = fsub float -0.000000e+00, %564 %568 = fadd float %563, %567 %569 = fdiv float 1.000000e+00, %568 %570 = fmul float %566, %569 %571 = call float @llvm.AMDIL.clamp.(float %570, float 0.000000e+00, float 1.000000e+00) %572 = shl i32 15, 4 %573 = add i32 %572, 12 %574 = call float @llvm.SI.load.const(<16 x i8> %35, i32 %573) %575 = shl i32 16, 4 %576 = add i32 %575, 8 %577 = call float @llvm.SI.load.const(<16 x i8> %35, i32 %576) %578 = fcmp uge float %511, -1.000000e+00 %579 = select i1 %578, float %511, float -1.000000e+00 %580 = fcmp uge float %579, 1.000000e+00 %581 = select i1 %580, float 1.000000e+00, float %579 %582 = fadd float %581, 1.000000e+00 %583 = fsub float -0.000000e+00, %574 %584 = fmul float %583, %582 %585 = fmul float 0x3FE7154760000000, %584 %586 = call float @llvm.AMDIL.exp.(float %585) %587 = fmul float %509, 5.000000e-01 %588 = fadd float %587, 5.000000e-01 %589 = fmul float %510, 5.000000e-01 %590 = fadd float %589, 5.000000e-01 %591 = fmul float %588, %577 %592 = fmul float %590, %577 %593 = bitcast float %591 to i32 %594 = bitcast float %592 to i32 %595 = insertelement <2 x i32> undef, i32 %593, i32 0 %596 = insertelement <2 x i32> %595, i32 %594, i32 1 %597 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %596, <32 x i8> %37, <16 x i8> %39, i32 5) %598 = extractelement <4 x float> %597, i32 0 %599 = fmul float %586, %598 %600 = call float @llvm.AMDIL.clamp.(float %599, float 0.000000e+00, float 1.000000e+00) %601 = fcmp uge float %561, -1.000000e+00 %602 = select i1 %601, float %561, float -1.000000e+00 %603 = fcmp uge float %602, 1.000000e+00 %604 = select i1 %603, float 1.000000e+00, float %602 %605 = fadd float %604, 1.000000e+00 %606 = fsub float -0.000000e+00, %574 %607 = fmul float %606, %605 %608 = fmul float 0x3FE7154760000000, %607 %609 = call float @llvm.AMDIL.exp.(float %608) %610 = fmul float %559, 5.000000e-01 %611 = fadd float %610, 5.000000e-01 %612 = fmul float %560, 5.000000e-01 %613 = fadd float %612, 5.000000e-01 %614 = fmul float %611, %577 %615 = fmul float %613, %577 %616 = bitcast float %614 to i32 %617 = bitcast float %615 to i32 %618 = insertelement <2 x i32> undef, i32 %616, i32 0 %619 = insertelement <2 x i32> %618, i32 %617, i32 1 %620 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %619, <32 x i8> %41, <16 x i8> %43, i32 5) %621 = extractelement <4 x float> %620, i32 0 %622 = fmul float %609, %621 %623 = call float @llvm.AMDIL.clamp.(float %622, float 0.000000e+00, float 1.000000e+00) %624 = fmul float 2.000000e+00, %571 %625 = fsub float -0.000000e+00, %624 %626 = fadd float 3.000000e+00, %625 %627 = fmul float %571, %626 %628 = fmul float %571, %627 %629 = call float @llvm.AMDGPU.lrp(float %628, float %623, float %600) br label %ENDIF LOOP: ; preds = %ENDIF278, %ENDIF %temp34.0 = phi float [ %341, %ENDIF ], [ %755, %ENDIF278 ] %temp33.0 = phi float [ %340, %ENDIF ], [ %754, %ENDIF278 ] %temp32.0 = phi float [ %339, %ENDIF ], [ %753, %ENDIF278 ] %temp.0 = phi float [ 0.000000e+00, %ENDIF ], [ %758, %ENDIF278 ] %630 = bitcast float %temp.0 to i32 %631 = icmp sge i32 %630, %342 %632 = sext i1 %631 to i32 %633 = bitcast i32 %632 to float %634 = bitcast float %633 to i32 %635 = icmp ne i32 %634, 0 br i1 %635, label %IF279, label %ENDIF278 IF279: ; preds = %LOOP %temp32.0.lcssa = phi float [ %temp32.0, %LOOP ] %temp33.0.lcssa = phi float [ %temp33.0, %LOOP ] %temp34.0.lcssa = phi float [ %temp34.0, %LOOP ] %636 = call i32 @llvm.SI.packf16(float %temp32.0.lcssa, float %temp33.0.lcssa) %637 = bitcast i32 %636 to float %638 = call i32 @llvm.SI.packf16(float %temp34.0.lcssa, float 0.000000e+00) %639 = bitcast i32 %638 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %637, float %639, float %637, float %639) ret void ENDIF278: ; preds = %LOOP %640 = bitcast float %temp.0 to i32 %641 = mul i32 %640, 7 %642 = bitcast i32 %641 to float %643 = bitcast float %642 to i32 %644 = shl i32 %643, 4 %645 = add i32 %644, 64 %646 = call float @llvm.SI.load.const(<16 x i8> %23, i32 %645) %647 = bitcast float %642 to i32 %648 = add i32 %647, 1 %649 = bitcast i32 %648 to float %650 = bitcast float %649 to i32 %651 = shl i32 %650, 4 %652 = add i32 %651, 64 %653 = call float @llvm.SI.load.const(<16 x i8> %23, i32 %652) %654 = bitcast float %642 to i32 %655 = add i32 %654, 2 %656 = bitcast i32 %655 to float %657 = bitcast float %656 to i32 %658 = shl i32 %657, 4 %659 = add i32 %658, 64 %660 = call float @llvm.SI.load.const(<16 x i8> %23, i32 %659) %661 = bitcast float %642 to i32 %662 = add i32 %661, 3 %663 = bitcast i32 %662 to float %664 = bitcast float %663 to i32 %665 = shl i32 %664, 4 %666 = add i32 %665, 64 %667 = call float @llvm.SI.load.const(<16 x i8> %23, i32 %666) %668 = bitcast float %642 to i32 %669 = add i32 %668, 4 %670 = bitcast i32 %669 to float %671 = bitcast float %670 to i32 %672 = shl i32 %671, 4 %673 = add i32 %672, 64 %674 = call float @llvm.SI.load.const(<16 x i8> %23, i32 %673) %675 = bitcast float %642 to i32 %676 = add i32 %675, 5 %677 = bitcast i32 %676 to float %678 = bitcast float %677 to i32 %679 = shl i32 %678, 4 %680 = add i32 %679, 64 %681 = call float @llvm.SI.load.const(<16 x i8> %23, i32 %680) %682 = bitcast float %642 to i32 %683 = add i32 %682, 6 %684 = bitcast i32 %683 to float %685 = bitcast float %684 to i32 %686 = shl i32 %685, 4 %687 = add i32 %686, 64 %688 = call float @llvm.SI.load.const(<16 x i8> %23, i32 %687) %689 = fadd float %646, %343 %690 = fadd float %653, %344 %691 = fadd float %660, %345 %692 = fmul float %689, %689 %693 = fmul float %690, %690 %694 = fadd float %693, %692 %695 = fmul float %691, %691 %696 = fadd float %694, %695 %697 = call float @llvm.AMDGPU.rsq(float %696) %698 = fmul float %697, %696 %699 = fsub float -0.000000e+00, %696 %700 = call float @llvm.AMDGPU.cndlt(float %699, float %698, float 0.000000e+00) %701 = fdiv float 1.000000e+00, %700 %702 = fmul float %689, %701 %703 = fmul float %690, %701 %704 = fmul float %691, %701 %705 = fmul float %56, %702 %706 = fmul float %57, %703 %707 = fadd float %706, %705 %708 = fmul float %58, %704 %709 = fadd float %707, %708 %710 = fcmp uge float 0.000000e+00, %709 %711 = select i1 %710, float 0.000000e+00, float %709 %712 = fmul float %711, %667 %713 = fmul float %711, %674 %714 = fmul float %711, %681 %715 = fmul float %712, %25 %716 = fmul float %713, %26 %717 = fmul float %714, %27 %718 = fmul float %144, %702 %719 = fmul float %146, %703 %720 = fadd float %719, %718 %721 = fmul float %148, %704 %722 = fadd float %720, %721 %723 = fcmp uge float 0x3F50624DE0000000, %722 %724 = select i1 %723, float 0x3F50624DE0000000, float %722 %725 = call float @llvm.pow.f32(float %724, float %31) %726 = fmul float %725, %667 %727 = fmul float %725, %674 %728 = fmul float %725, %681 %729 = fmul float %726, %28 %730 = fadd float %729, %715 %731 = fmul float %727, %29 %732 = fadd float %731, %716 %733 = fmul float %728, %30 %734 = fadd float %733, %717 %735 = fmul float %688, 5.000000e-01 %736 = fsub float -0.000000e+00, %735 %737 = fadd float %700, %736 %738 = fsub float -0.000000e+00, %735 %739 = fadd float %688, %738 %740 = fdiv float 1.000000e+00, %739 %741 = fmul float %737, %740 %742 = call float @llvm.AMDIL.clamp.(float %741, float 0.000000e+00, float 1.000000e+00) %743 = fmul float 2.000000e+00, %742 %744 = fsub float -0.000000e+00, %743 %745 = fadd float 3.000000e+00, %744 %746 = fmul float %742, %745 %747 = fmul float %742, %746 %748 = fsub float -0.000000e+00, %747 %749 = fadd float 1.000000e+00, %748 %750 = fmul float %730, %749 %751 = fmul float %732, %749 %752 = fmul float %734, %749 %753 = fadd float %temp32.0, %750 %754 = fadd float %temp33.0, %751 %755 = fadd float %temp34.0, %752 %756 = bitcast float %temp.0 to i32 %757 = add i32 %756, 1 %758 = bitcast i32 %757 to float br label %LOOP } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: readnone declare float @llvm.AMDGPU.rsq(float) #2 ; Function Attrs: readnone declare float @llvm.AMDIL.clamp.(float, float, float) #2 ; Function Attrs: nounwind readonly declare float @llvm.pow.f32(float, float) #3 ; Function Attrs: readnone declare float @llvm.AMDGPU.cndlt(float, float, float) #2 ; Function Attrs: readnone declare float @llvm.AMDIL.exp.(float) #2 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1 ; Function Attrs: readnone declare float @llvm.AMDGPU.lrp(float, float, float) #2 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } attributes #3 = { nounwind readonly } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s9 ; BEFC0309 V_INTERP_P1_F32 v2, v0, 0, 1, [m0] ; C8080400 V_INTERP_P2_F32 v2, [v2], v1, 0, 1, [m0] ; C8090401 V_INTERP_P1_F32 v3, v0, 3, 0, [m0] ; C80C0300 V_INTERP_P2_F32 v3, [v3], v1, 3, 0, [m0] ; C80D0301 S_LOAD_DWORDX4 s[12:15], s[0:1], 4 ; C0860104 S_WAITCNT lgkmcnt(0) ; BF8C007F S_BUFFER_LOAD_DWORD s6, s[12:15], 49 ; C2030D31 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v4, s6, v3 ; 10080606 S_BUFFER_LOAD_DWORD s6, s[12:15], 53 ; C2030D35 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v4, s6, v2, v4, 0, 0, 0, 0 ; D2820004 04120406 V_INTERP_P1_F32 v5, v0, 1, 1, [m0] ; C8140500 V_INTERP_P2_F32 v5, [v5], v1, 1, 1, [m0] ; C8150501 S_BUFFER_LOAD_DWORD s6, s[12:15], 57 ; C2030D39 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v4, s6, v5, v4, 0, 0, 0, 0 ; D2820004 04120A06 S_BUFFER_LOAD_DWORD s6, s[12:15], 61 ; C2030D3D S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v6, s6, v4 ; 060C0806 S_BUFFER_LOAD_DWORD s6, s[12:15], 81 ; C2030D51 S_WAITCNT lgkmcnt(0) ; BF8C007F V_SUBREV_F32_e32 v4, s6, v6 ; 0A080C06 S_BUFFER_LOAD_DWORD s6, s[12:15], 48 ; C2030D30 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v7, s6, v3 ; 100E0606 S_BUFFER_LOAD_DWORD s6, s[12:15], 52 ; C2030D34 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v7, s6, v2, v7, 0, 0, 0, 0 ; D2820007 041E0406 S_BUFFER_LOAD_DWORD s6, s[12:15], 56 ; C2030D38 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v7, s6, v5, v7, 0, 0, 0, 0 ; D2820007 041E0A06 S_BUFFER_LOAD_DWORD s6, s[12:15], 60 ; C2030D3C S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v7, s6, v7 ; 060E0E06 S_BUFFER_LOAD_DWORD s6, s[12:15], 80 ; C2030D50 S_WAITCNT lgkmcnt(0) ; BF8C007F V_SUBREV_F32_e32 v9, s6, v7 ; 0A120E06 V_MUL_F32_e32 v8, v9, v9 ; 10101309 V_MAD_F32 v10, v4, v4, v8, 0, 0, 0, 0 ; D282000A 04220904 S_BUFFER_LOAD_DWORD s6, s[12:15], 50 ; C2030D32 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v3, s6, v3 ; 10060606 S_BUFFER_LOAD_DWORD s6, s[12:15], 54 ; C2030D36 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v2, s6, v2, v3, 0, 0, 0, 0 ; D2820002 040E0406 S_BUFFER_LOAD_DWORD s6, s[12:15], 58 ; C2030D3A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v2, s6, v5, v2, 0, 0, 0, 0 ; D2820002 040A0A06 S_BUFFER_LOAD_DWORD s6, s[12:15], 62 ; C2030D3E S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v8, s6, v2 ; 06100406 S_BUFFER_LOAD_DWORD s6, s[12:15], 82 ; C2030D52 S_WAITCNT lgkmcnt(0) ; BF8C007F V_SUBREV_F32_e32 v2, s6, v8 ; 0A041006 V_MAD_F32 v3, v2, v2, v10, 0, 0, 0, 0 ; D2820003 042A0502 V_RSQ_LEGACY_F32_e32 v3, v3 ; 7E065B03 V_MUL_F32_e32 v4, v4, v3 ; 10080704 V_MUL_F32_e32 v5, v9, v3 ; 100A0709 V_INTERP_P1_F32 v10, v0, 1, 0, [m0] ; C8280100 V_INTERP_P2_F32 v10, [v10], v1, 1, 0, [m0] ; C8290101 V_INTERP_P1_F32 v9, v0, 0, 0, [m0] ; C8240000 V_INTERP_P2_F32 v9, [v9], v1, 0, 0, [m0] ; C8250001 V_MUL_F32_e32 v11, v9, v9 ; 10161309 V_MAD_F32 v11, v10, v10, v11, 0, 0, 0, 0 ; D282000B 042E150A V_INTERP_P1_F32 v12, v0, 2, 0, [m0] ; C8300200 V_INTERP_P2_F32 v12, [v12], v1, 2, 0, [m0] ; C8310201 V_MAD_F32 v0, v12, v12, v11, 0, 0, 0, 0 ; D2820000 042E190C V_RSQ_LEGACY_F32_e32 v13, v0 ; 7E1A5B00 V_MUL_F32_e32 v0, v9, v13 ; 10001B09 V_MUL_F32_e32 v9, v0, v5 ; 10120B00 V_MUL_F32_e32 v1, v10, v13 ; 10021B0A V_MAD_F32 v9, v1, v4, v9, 0, 0, 0, 0 ; D2820009 04260901 V_MUL_F32_e32 v11, v2, v3 ; 10160702 V_MUL_F32_e32 v2, v12, v13 ; 10041B0C V_MAD_F32 v9, v2, v11, v9, 0, 0, 0, 0 ; D2820009 04261702 V_MUL_F32_e32 v3, v9, v1 ; 10060309 V_MAD_F32 v3, v9, v1, v3, 0, 0, 0, 0 ; D2820003 040E0309 V_SUB_F32_e32 v3, v4, v3 ; 08060704 V_MUL_F32_e32 v4, v9, v0 ; 10080109 V_MAD_F32 v4, v9, v0, v4, 0, 0, 0, 0 ; D2820004 04120109 V_SUB_F32_e32 v4, v5, v4 ; 08080905 S_LOAD_DWORDX4 s[16:19], s[0:1], 8 ; C0880108 S_WAITCNT lgkmcnt(0) ; BF8C007F S_BUFFER_LOAD_DWORD s15, s[16:19], 48 ; C2079130 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v5, s15, v4 ; 100A080F S_BUFFER_LOAD_DWORD s22, s[16:19], 49 ; C20B1131 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v12, v3, s22, v5, 0, 0, 0, 0 ; D282000C 04142D03 V_MUL_F32_e32 v5, v9, v2 ; 100A0509 V_MAD_F32 v5, v9, v2, v5, 0, 0, 0, 0 ; D2820005 04160509 V_SUB_F32_e32 v5, v11, v5 ; 080A0B0B S_BUFFER_LOAD_DWORD s23, s[16:19], 50 ; C20B9132 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v9, v5, s23, v12, 0, 0, 0, 0 ; D2820009 04302F05 V_MOV_B32_e32 v11, 1.000000e-03 ; 7E1602FF 3A83126F V_CMP_LE_F32_e64 s[6:7], v9, v11, 0, 0, 0, 0 ; D0060006 02021709 V_CMP_U_F32_e64 s[8:9], v9, v9, 0, 0, 0, 0 ; D0100008 02021309 S_OR_B64 s[6:7], s[6:7], s[8:9] ; 88860806 V_CNDMASK_B32_e64 v9, v9, v11, s[6:7], 0, 0, 0, 0 ; D2000009 001A1709 V_LOG_F32_e32 v9, v9 ; 7E124F09 S_LOAD_DWORDX4 s[8:11], s[0:1], 0 ; C0840100 S_MOV_B32 s0, 1212 ; BE8003FF 000004BC S_WAITCNT lgkmcnt(0) ; BF8C007F S_BUFFER_LOAD_DWORD s0, s[8:11], s0 ; C2000800 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_LEGACY_F32_e32 v9, s0, v9 ; 0E121200 V_EXP_F32_e32 v9, v9 ; 7E124B09 S_BUFFER_LOAD_DWORD s48, s[16:19], 61 ; C218113D S_WAITCNT lgkmcnt(0) ; BF8C007F V_SUBREV_F32_e32 v11, s48, v6 ; 0A160C30 S_BUFFER_LOAD_DWORD s49, s[16:19], 60 ; C218913C S_WAITCNT lgkmcnt(0) ; BF8C007F V_SUBREV_F32_e32 v12, s49, v7 ; 0A180E31 V_MUL_F32_e32 v12, v12, v12 ; 1018190C V_MAD_F32 v11, v11, v11, v12, 0, 0, 0, 0 ; D282000B 0432170B S_BUFFER_LOAD_DWORD s50, s[16:19], 62 ; C219113E S_WAITCNT lgkmcnt(0) ; BF8C007F V_SUBREV_F32_e32 v12, s50, v8 ; 0A181032 V_MAD_F32 v11, v12, v12, v11, 0, 0, 0, 0 ; D282000B 042E190C V_RSQ_LEGACY_F32_e32 v12, v11 ; 7E185B0B V_MUL_F32_e32 v12, v12, v11 ; 1018170C V_XOR_B32_e32 v11, -2147483648, v11 ; 3A1616FF 80000000 V_CMP_GT_F32_e64 s[6:7], 0, v11, 0, 0, 0, 0 ; D0080006 02021680 V_CNDMASK_B32_e64 v11, 0.000000e+00, v12, s[6:7], 0, 0, 0, 0 ; D200000B 001A1880 S_BUFFER_LOAD_DWORD s51, s[16:19], 64 ; C2199140 V_MOV_B32_e32 v12, 8.000000e-01 ; 7E1802FF 3F4CCCCD S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v12, s51, v12 ; 10181833 V_CMP_LT_F32_e64 s[6:7], v11, v12, 0, 0, 0, 0 ; D0020006 0202190B V_CNDMASK_B32_e64 v12, 0, -1, s[6:7], 0, 0, 0, 0 ; D200000C 00198280 V_CMP_EQ_I32_e64 s[20:21], v12, 0, 0, 0, 0, 0 ; D1040014 0201010C V_MOV_B32_e32 v12, 1.050000e+00 ; 7E1802FF 3F866666 V_MAD_F32 v10, v10, v13, v12, 0, 0, 0, 0 ; D282000A 04321B0A V_ADD_F32_e64 v10, 0, v10, 0, 1, 0, 0 ; D206080A 02021480 S_MOV_B32 s1, 1208 ; BE8103FF 000004B8 S_BUFFER_LOAD_DWORD s1, s[8:11], s1 ; C2008801 S_MOV_B32 s6, 1204 ; BE8603FF 000004B4 S_BUFFER_LOAD_DWORD s6, s[8:11], s6 ; C2030806 S_MOV_B32 s7, 1200 ; BE8703FF 000004B0 S_BUFFER_LOAD_DWORD s7, s[8:11], s7 ; C2038807 S_MOV_B32 s12, 1192 ; BE8C03FF 000004A8 S_BUFFER_LOAD_DWORD s12, s[8:11], s12 ; C206080C S_MOV_B32 s13, 1188 ; BE8D03FF 000004A4 S_BUFFER_LOAD_DWORD s13, s[8:11], s13 ; C206880D S_MOV_B32 s14, 1184 ; BE8E03FF 000004A0 S_BUFFER_LOAD_DWORD s14, s[8:11], s14 ; C207080E S_LOAD_DWORDX4 s[24:27], s[2:3], 0 ; C08C0300 S_LOAD_DWORDX8 s[28:35], s[4:5], 0 ; C0CE0500 S_WAITCNT lgkmcnt(0) ; BF8C007F S_AND_SAVEEXEC_B64 s[20:21], s[20:21] ; BE942414 S_XOR_B64 s[20:21], exec, s[20:21] ; 8994147E S_CBRANCH_EXECZ BB0_1 ; BF880000 V_CMP_LT_F32_e64 s[36:37], s51, v11, 0, 0, 0, 0 ; D0020024 02021633 V_CNDMASK_B32_e64 v12, 0, -1, s[36:37], 0, 0, 0, 0 ; D200000C 00918280 V_CMP_EQ_I32_e64 s[52:53], v12, 0, 0, 0, 0, 0 ; D1040034 0201010C S_LOAD_DWORDX4 s[36:39], s[2:3], 4 ; C0920304 S_LOAD_DWORDX8 s[40:47], s[4:5], 8 ; C0D40508 S_WAITCNT lgkmcnt(0) ; BF8C007F S_AND_SAVEEXEC_B64 s[2:3], s[52:53] ; BE822434 S_XOR_B64 s[2:3], exec, s[2:3] ; 8982027E S_CBRANCH_EXECZ BB0_6 ; BF880000 V_MOV_B32_e32 v12, -8.000000e-01 ; 7E1802FF BF4CCCCD V_MAD_F32 v11, s51, v12, v11, 0, 0, 0, 0 ; D282000B 042E1833 V_MOV_B32_e32 v13, s51 ; 7E1A0233 V_MAD_F32 v12, s51, v12, v13, 0, 0, 0, 0 ; D282000C 04361833 V_RCP_F32_e32 v12, v12 ; 7E18550C V_MUL_F32_e32 v11, v11, v12 ; 1016190B V_ADD_F32_e64 v11, 0, v11, 0, 1, 0, 0 ; D206080B 02021680 V_ADD_F32_e32 v12, v11, v11 ; 0618170B V_SUB_F32_e32 v12, 3.000000e+00, v12 ; 081818FF 40400000 V_MUL_F32_e32 v12, v11, v12 ; 1018190B V_MUL_F32_e32 v11, v11, v12 ; 1016190B V_SUB_F32_e32 v12, 1.000000e+00, v11 ; 081816F2 S_BUFFER_LOAD_DWORD s4, s[16:19], 18 ; C2021112 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v13, s4, v7, 0, 0, 0, 0 ; D210000D 02020E04 S_BUFFER_LOAD_DWORD s4, s[16:19], 22 ; C2021116 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v13, s4, v6, v13, 0, 0, 0, 0 ; D282000D 04360C04 S_BUFFER_LOAD_DWORD s4, s[16:19], 26 ; C202111A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v13, s4, v8, v13, 0, 0, 0, 0 ; D282000D 04361004 S_BUFFER_LOAD_DWORD s4, s[16:19], 30 ; C202111E S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v13, s4, v13 ; 061A1A04 V_CMP_U_F32_e64 s[4:5], v13, v13, 0, 0, 0, 0 ; D0100004 02021B0D V_CMP_GE_F32_e64 s[52:53], v13, -1.000000e+00, 0, 0, 0, 0 ; D00C0034 0201E70D S_OR_B64 s[4:5], s[52:53], s[4:5] ; 88840434 V_CNDMASK_B32_e64 v13, -1.000000e+00, v13, s[4:5], 0, 0, 0, 0 ; D200000D 00121AF3 V_CMP_U_F32_e64 s[4:5], v13, v13, 0, 0, 0, 0 ; D0100004 02021B0D V_CMP_GE_F32_e64 s[52:53], v13, 1.000000e+00, 0, 0, 0, 0 ; D00C0034 0201E50D S_OR_B64 s[4:5], s[52:53], s[4:5] ; 88840434 V_CNDMASK_B32_e64 v13, v13, 1.000000e+00, s[4:5], 0, 0, 0, 0 ; D200000D 0011E50D V_ADD_F32_e32 v13, 1.000000e+00, v13 ; 061A1AF2 S_BUFFER_LOAD_DWORD s4, s[16:19], 63 ; C202113F V_MOV_B32_e32 v14, -2147483648 ; 7E1C02FF 80000000 S_WAITCNT lgkmcnt(0) ; BF8C007F V_XOR_B32_e32 v14, s4, v14 ; 3A1C1C04 V_MUL_F32_e32 v13, v14, v13 ; 101A1B0E V_MUL_F32_e32 v13, 7.213475e-01, v13 ; 101A1AFF 3F38AA3B V_EXP_F32_e32 v13, v13 ; 7E1A4B0D S_BUFFER_LOAD_DWORD s4, s[16:19], 17 ; C2021111 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v15, s4, v7, 0, 0, 0, 0 ; D210000F 02020E04 S_BUFFER_LOAD_DWORD s4, s[16:19], 21 ; C2021115 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v15, s4, v6, v15, 0, 0, 0, 0 ; D282000F 043E0C04 S_BUFFER_LOAD_DWORD s4, s[16:19], 25 ; C2021119 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v15, s4, v8, v15, 0, 0, 0, 0 ; D282000F 043E1004 S_BUFFER_LOAD_DWORD s4, s[16:19], 29 ; C202111D S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v15, s4, v15 ; 061E1E04 V_MAD_F32 v15, v15, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0 ; D282000F 03C1E10F S_BUFFER_LOAD_DWORD s4, s[16:19], 66 ; C2021142 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v16, s4, v15 ; 10201E04 S_BUFFER_LOAD_DWORD s5, s[16:19], 16 ; C2029110 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v17, s5, v7, 0, 0, 0, 0 ; D2100011 02020E05 S_BUFFER_LOAD_DWORD s5, s[16:19], 20 ; C2029114 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v17, s5, v6, v17, 0, 0, 0, 0 ; D2820011 04460C05 S_BUFFER_LOAD_DWORD s5, s[16:19], 24 ; C2029118 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v17, s5, v8, v17, 0, 0, 0, 0 ; D2820011 04461005 S_BUFFER_LOAD_DWORD s5, s[16:19], 28 ; C202911C S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v17, s5, v17 ; 06222205 V_MAD_F32 v17, v17, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0 ; D2820011 03C1E111 V_MUL_F32_e32 v15, s4, v17 ; 101E2204 IMAGE_SAMPLE v15, 1, -1, 0, 0, 0, 0, 0, 0, v[15:16], s[28:35], s[24:27] ; F0801100 00C70F0F S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v13, v13, v15 ; 101A1F0D V_ADD_F32_e64 v13, 0, v13, 0, 1, 0, 0 ; D206080D 02021A80 V_MUL_F32_e32 v12, v12, v13 ; 10181B0C S_BUFFER_LOAD_DWORD s5, s[16:19], 34 ; C2029122 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v13, s5, v7, 0, 0, 0, 0 ; D210000D 02020E05 S_BUFFER_LOAD_DWORD s5, s[16:19], 38 ; C2029126 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v13, s5, v6, v13, 0, 0, 0, 0 ; D282000D 04360C05 S_BUFFER_LOAD_DWORD s5, s[16:19], 42 ; C202912A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v13, s5, v8, v13, 0, 0, 0, 0 ; D282000D 04361005 S_BUFFER_LOAD_DWORD s5, s[16:19], 46 ; C202912E S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v13, s5, v13 ; 061A1A05 V_CMP_U_F32_e64 s[52:53], v13, v13, 0, 0, 0, 0 ; D0100034 02021B0D V_CMP_GE_F32_e64 s[54:55], v13, -1.000000e+00, 0, 0, 0, 0 ; D00C0036 0201E70D S_OR_B64 s[52:53], s[54:55], s[52:53] ; 88B43436 V_CNDMASK_B32_e64 v13, -1.000000e+00, v13, s[52:53], 0, 0, 0, 0 ; D200000D 00D21AF3 V_CMP_U_F32_e64 s[52:53], v13, v13, 0, 0, 0, 0 ; D0100034 02021B0D V_CMP_GE_F32_e64 s[54:55], v13, 1.000000e+00, 0, 0, 0, 0 ; D00C0036 0201E50D S_OR_B64 s[52:53], s[54:55], s[52:53] ; 88B43436 V_CNDMASK_B32_e64 v13, v13, 1.000000e+00, s[52:53], 0, 0, 0, 0 ; D200000D 00D1E50D V_ADD_F32_e32 v13, 1.000000e+00, v13 ; 061A1AF2 V_MUL_F32_e32 v13, v14, v13 ; 101A1B0E V_MUL_F32_e32 v13, 7.213475e-01, v13 ; 101A1AFF 3F38AA3B V_EXP_F32_e32 v13, v13 ; 7E1A4B0D S_BUFFER_LOAD_DWORD s5, s[16:19], 33 ; C2029121 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v14, s5, v7, 0, 0, 0, 0 ; D210000E 02020E05 S_BUFFER_LOAD_DWORD s5, s[16:19], 37 ; C2029125 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v14, s5, v6, v14, 0, 0, 0, 0 ; D282000E 043A0C05 S_BUFFER_LOAD_DWORD s5, s[16:19], 41 ; C2029129 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v14, s5, v8, v14, 0, 0, 0, 0 ; D282000E 043A1005 S_BUFFER_LOAD_DWORD s5, s[16:19], 45 ; C202912D S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v14, s5, v14 ; 061C1C05 V_MAD_F32 v14, v14, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0 ; D282000E 03C1E10E V_MUL_F32_e32 v15, s4, v14 ; 101E1C04 S_BUFFER_LOAD_DWORD s5, s[16:19], 32 ; C2029120 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v16, s5, v7, 0, 0, 0, 0 ; D2100010 02020E05 S_BUFFER_LOAD_DWORD s5, s[16:19], 36 ; C2029124 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v16, s5, v6, v16, 0, 0, 0, 0 ; D2820010 04420C05 S_BUFFER_LOAD_DWORD s5, s[16:19], 40 ; C2029128 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v16, s5, v8, v16, 0, 0, 0, 0 ; D2820010 04421005 S_BUFFER_LOAD_DWORD s5, s[16:19], 44 ; C202912C S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v16, s5, v16 ; 06202005 V_MAD_F32 v16, v16, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0 ; D2820010 03C1E110 V_MUL_F32_e32 v14, s4, v16 ; 101C2004 IMAGE_SAMPLE v14, 1, -1, 0, 0, 0, 0, 0, 0, v[14:15], s[40:47], s[36:39] ; F0801100 012A0E0E S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v13, v13, v14 ; 101A1D0D V_ADD_F32_e64 v13, 0, v13, 0, 1, 0, 0 ; D206080D 02021A80 V_MAD_F32 v19, v11, v13, v12, 0, 0, 0, 0 ; D2820013 04321B0B S_OR_SAVEEXEC_B64 s[2:3], s[2:3] ; BE822502 S_XOR_B64 exec, exec, s[2:3] ; 89FE027E S_CBRANCH_EXECZ BB0_4 ; BF880000 V_MOV_B32_e32 v11, s48 ; 7E160230 V_SUB_F32_e64 v11, v6, v11, 0, 0, 0, 0 ; D208000B 02021706 V_MOV_B32_e32 v12, s49 ; 7E180231 V_SUB_F32_e64 v12, v7, v12, 0, 0, 0, 0 ; D208000C 02021907 V_MUL_F32_e32 v12, v12, v12 ; 1018190C V_MAD_F32 v11, v11, v11, v12, 0, 0, 0, 0 ; D282000B 0432170B V_MOV_B32_e32 v12, s50 ; 7E180232 V_SUB_F32_e64 v12, v8, v12, 0, 0, 0, 0 ; D208000C 02021908 V_MAD_F32 v11, v12, v12, v11, 0, 0, 0, 0 ; D282000B 042E190C V_RSQ_LEGACY_F32_e32 v12, v11 ; 7E185B0B V_MUL_F32_e32 v12, v12, v11 ; 1018170C V_XOR_B32_e32 v11, -2147483648, v11 ; 3A1616FF 80000000 V_CMP_GT_F32_e64 s[4:5], 0, v11, 0, 0, 0, 0 ; D0080004 02021680 V_CNDMASK_B32_e64 v11, 0.000000e+00, v12, s[4:5], 0, 0, 0, 0 ; D200000B 00121880 S_BUFFER_LOAD_DWORD s4, s[16:19], 65 ; C2021141 S_WAITCNT lgkmcnt(0) ; BF8C007F V_RCP_F32_e32 v12, s4 ; 7E185404 V_MOV_B32_e32 v13, -8.000000e-01 ; 7E1A02FF BF4CCCCD V_MAD_F32 v11, v11, v12, v13, 0, 0, 0, 0 ; D282000B 0436190B V_MUL_F32_e32 v11, 5.000000e+00, v11 ; 101616FF 40A00001 V_ADD_F32_e64 v11, 0, v11, 0, 1, 0, 0 ; D206080B 02021680 V_ADD_F32_e32 v12, v11, v11 ; 0618170B V_SUB_F32_e32 v12, 3.000000e+00, v12 ; 081818FF 40400000 V_MUL_F32_e32 v12, v11, v12 ; 1018190B V_MUL_F32_e32 v13, v11, v12 ; 101A190B V_SUB_F32_e32 v13, 1.000000e+00, v13 ; 081A1AF2 S_BUFFER_LOAD_DWORD s4, s[16:19], 34 ; C2021122 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v14, s4, v7, 0, 0, 0, 0 ; D210000E 02020E04 S_BUFFER_LOAD_DWORD s4, s[16:19], 38 ; C2021126 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v14, s4, v6, v14, 0, 0, 0, 0 ; D282000E 043A0C04 S_BUFFER_LOAD_DWORD s4, s[16:19], 42 ; C202112A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v14, s4, v8, v14, 0, 0, 0, 0 ; D282000E 043A1004 S_BUFFER_LOAD_DWORD s4, s[16:19], 46 ; C202112E S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v14, s4, v14 ; 061C1C04 V_CMP_U_F32_e64 s[4:5], v14, v14, 0, 0, 0, 0 ; D0100004 02021D0E V_CMP_GE_F32_e64 s[48:49], v14, -1.000000e+00, 0, 0, 0, 0 ; D00C0030 0201E70E S_OR_B64 s[4:5], s[48:49], s[4:5] ; 88840430 V_CNDMASK_B32_e64 v14, -1.000000e+00, v14, s[4:5], 0, 0, 0, 0 ; D200000E 00121CF3 V_CMP_U_F32_e64 s[4:5], v14, v14, 0, 0, 0, 0 ; D0100004 02021D0E V_CMP_GE_F32_e64 s[48:49], v14, 1.000000e+00, 0, 0, 0, 0 ; D00C0030 0201E50E S_OR_B64 s[4:5], s[48:49], s[4:5] ; 88840430 V_CNDMASK_B32_e64 v14, v14, 1.000000e+00, s[4:5], 0, 0, 0, 0 ; D200000E 0011E50E V_ADD_F32_e32 v14, 1.000000e+00, v14 ; 061C1CF2 S_BUFFER_LOAD_DWORD s4, s[16:19], 63 ; C202113F S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v14, s4, v14 ; 101C1C04 V_MUL_F32_e32 v14, -7.213475e-01, v14 ; 101C1CFF BF38AA3B V_EXP_F32_e32 v14, v14 ; 7E1C4B0E S_BUFFER_LOAD_DWORD s4, s[16:19], 33 ; C2021121 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v15, s4, v7, 0, 0, 0, 0 ; D210000F 02020E04 S_BUFFER_LOAD_DWORD s4, s[16:19], 37 ; C2021125 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v15, s4, v6, v15, 0, 0, 0, 0 ; D282000F 043E0C04 S_BUFFER_LOAD_DWORD s4, s[16:19], 41 ; C2021129 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v15, s4, v8, v15, 0, 0, 0, 0 ; D282000F 043E1004 S_BUFFER_LOAD_DWORD s4, s[16:19], 45 ; C202112D S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v15, s4, v15 ; 061E1E04 V_MAD_F32 v15, v15, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0 ; D282000F 03C1E10F S_BUFFER_LOAD_DWORD s4, s[16:19], 66 ; C2021142 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v16, s4, v15 ; 10201E04 S_BUFFER_LOAD_DWORD s5, s[16:19], 32 ; C2029120 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v17, s5, v7, 0, 0, 0, 0 ; D2100011 02020E05 S_BUFFER_LOAD_DWORD s5, s[16:19], 36 ; C2029124 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v17, s5, v6, v17, 0, 0, 0, 0 ; D2820011 04460C05 S_BUFFER_LOAD_DWORD s5, s[16:19], 40 ; C2029128 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v17, s5, v8, v17, 0, 0, 0, 0 ; D2820011 04461005 S_BUFFER_LOAD_DWORD s5, s[16:19], 44 ; C202912C S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v17, s5, v17 ; 06222205 V_MAD_F32 v17, v17, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0 ; D2820011 03C1E111 V_MUL_F32_e32 v15, s4, v17 ; 101E2204 IMAGE_SAMPLE v15, 1, -1, 0, 0, 0, 0, 0, 0, v[15:16], s[40:47], s[36:39] ; F0801100 012A0F0F S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v14, v14, v15 ; 101C1F0E V_ADD_F32_e64 v14, 0, v14, 0, 1, 0, 0 ; D206080E 02021C80 V_MUL_F32_e32 v13, v13, v14 ; 101A1D0D V_MAD_F32 v19, v11, v12, v13, 0, 0, 0, 0 ; D2820013 0436190B S_OR_B64 exec, exec, s[2:3] ; 88FE027E S_OR_SAVEEXEC_B64 s[20:21], s[20:21] ; BE942514 S_BUFFER_LOAD_DWORD s2, s[16:19], 54 ; C2011136 S_BUFFER_LOAD_DWORD s3, s[16:19], 53 ; C2019135 S_BUFFER_LOAD_DWORD s5, s[16:19], 52 ; C2029134 S_BUFFER_LOAD_DWORD s36, s[16:19], 58 ; C212113A S_BUFFER_LOAD_DWORD s37, s[16:19], 57 ; C2129139 S_BUFFER_LOAD_DWORD s38, s[16:19], 56 ; C2131138 S_BUFFER_LOAD_DWORD s4, s[8:11], 12 ; C202090C S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v16, s2 ; 7E200202 V_MOV_B32_e32 v13, s3 ; 7E1A0203 V_MOV_B32_e32 v11, s5 ; 7E160205 V_MOV_B32_e32 v17, s23 ; 7E220217 V_MOV_B32_e32 v18, s22 ; 7E240216 V_MOV_B32_e32 v20, s15 ; 7E28020F V_MOV_B32_e32 v15, s36 ; 7E1E0224 V_MOV_B32_e32 v14, s37 ; 7E1C0225 V_MOV_B32_e32 v12, s38 ; 7E180226 S_XOR_B64 exec, exec, s[20:21] ; 89FE147E S_CBRANCH_EXECZ BB0_5 ; BF880000 S_BUFFER_LOAD_DWORD s2, s[16:19], 18 ; C2011112 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v19, s2, v7, 0, 0, 0, 0 ; D2100013 02020E02 S_BUFFER_LOAD_DWORD s2, s[16:19], 22 ; C2011116 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v19, s2, v6, v19, 0, 0, 0, 0 ; D2820013 044E0C02 S_BUFFER_LOAD_DWORD s2, s[16:19], 26 ; C201111A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v19, s2, v8, v19, 0, 0, 0, 0 ; D2820013 044E1002 S_BUFFER_LOAD_DWORD s2, s[16:19], 30 ; C201111E S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v19, s2, v19 ; 06262602 V_CMP_U_F32_e64 s[2:3], v19, v19, 0, 0, 0, 0 ; D0100002 02022713 V_CMP_GE_F32_e64 s[22:23], v19, -1.000000e+00, 0, 0, 0, 0 ; D00C0016 0201E713 S_OR_B64 s[2:3], s[22:23], s[2:3] ; 88820216 V_CNDMASK_B32_e64 v19, -1.000000e+00, v19, s[2:3], 0, 0, 0, 0 ; D2000013 000A26F3 V_CMP_U_F32_e64 s[2:3], v19, v19, 0, 0, 0, 0 ; D0100002 02022713 V_CMP_GE_F32_e64 s[22:23], v19, 1.000000e+00, 0, 0, 0, 0 ; D00C0016 0201E513 S_OR_B64 s[2:3], s[22:23], s[2:3] ; 88820216 V_CNDMASK_B32_e64 v19, v19, 1.000000e+00, s[2:3], 0, 0, 0, 0 ; D2000013 0009E513 V_ADD_F32_e32 v19, 1.000000e+00, v19 ; 062626F2 S_BUFFER_LOAD_DWORD s2, s[16:19], 63 ; C201113F S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v19, s2, v19 ; 10262602 V_MUL_F32_e32 v19, -7.213475e-01, v19 ; 102626FF BF38AA3B V_EXP_F32_e32 v19, v19 ; 7E264B13 S_BUFFER_LOAD_DWORD s2, s[16:19], 17 ; C2011111 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v21, s2, v7, 0, 0, 0, 0 ; D2100015 02020E02 S_BUFFER_LOAD_DWORD s2, s[16:19], 21 ; C2011115 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v21, s2, v6, v21, 0, 0, 0, 0 ; D2820015 04560C02 S_BUFFER_LOAD_DWORD s2, s[16:19], 25 ; C2011119 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v21, s2, v8, v21, 0, 0, 0, 0 ; D2820015 04561002 S_BUFFER_LOAD_DWORD s2, s[16:19], 29 ; C201111D S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v21, s2, v21 ; 062A2A02 V_MAD_F32 v21, v21, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0 ; D2820015 03C1E115 S_BUFFER_LOAD_DWORD s2, s[16:19], 66 ; C2011142 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v22, s2, v21 ; 102C2A02 S_BUFFER_LOAD_DWORD s3, s[16:19], 16 ; C2019110 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v23, s3, v7, 0, 0, 0, 0 ; D2100017 02020E03 S_BUFFER_LOAD_DWORD s3, s[16:19], 20 ; C2019114 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v23, s3, v6, v23, 0, 0, 0, 0 ; D2820017 045E0C03 S_BUFFER_LOAD_DWORD s3, s[16:19], 24 ; C2019118 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v23, s3, v8, v23, 0, 0, 0, 0 ; D2820017 045E1003 S_BUFFER_LOAD_DWORD s3, s[16:19], 28 ; C201911C S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v23, s3, v23 ; 062E2E03 V_MAD_F32 v23, v23, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0 ; D2820017 03C1E117 V_MUL_F32_e32 v21, s2, v23 ; 102A2E02 IMAGE_SAMPLE v21, 1, -1, 0, 0, 0, 0, 0, 0, v[21:22], s[28:35], s[24:27] ; F0801100 00C71515 S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v19, v19, v21 ; 10262B13 V_ADD_F32_e64 v19, 0, v19, 0, 1, 0, 0 ; D2060813 02022680 S_OR_B64 exec, exec, s[20:21] ; 88FE147E V_MUL_F32_e64 v20, v0, v20, 0, 0, 0, 0 ; D2100014 02022900 V_MAD_F32 v18, v1, v18, v20, 0, 0, 0, 0 ; D2820012 04522501 V_MAD_F32 v17, v2, v17, v18, 0, 0, 0, 0 ; D2820011 044A2302 V_CMP_U_F32_e64 s[2:3], v17, v17, 0, 0, 0, 0 ; D0100002 02022311 V_CMP_LE_F32_e64 s[16:17], v17, 0.000000e+00, 0, 0, 0, 0 ; D0060010 02010111 S_OR_B64 s[2:3], s[16:17], s[2:3] ; 88820210 V_CNDMASK_B32_e64 v17, v17, 0.000000e+00, s[2:3], 0, 0, 0, 0 ; D2000011 00090111 V_MUL_F32_e32 v18, v16, v17 ; 10242310 V_MUL_F32_e32 v18, s12, v18 ; 1024240C V_MUL_F32_e64 v16, v9, v16, 0, 0, 0, 0 ; D2100010 02022109 V_MAD_F32 v16, v16, s1, v18, 0, 0, 0, 0 ; D2820010 04480310 V_MOV_B32_e32 v18, -8.000000e-01 ; 7E2402FF BF4CCCCD V_ADD_F32_e32 v18, v19, v18 ; 06242513 V_MUL_F32_e32 v18, 5.000000e+00, v18 ; 102424FF 40A00001 V_ADD_F32_e64 v18, 0, v18, 0, 1, 0, 0 ; D2060812 02022480 V_ADD_F32_e32 v19, v18, v18 ; 06262512 V_SUB_F32_e32 v19, 3.000000e+00, v19 ; 082626FF 40400000 V_MUL_F32_e32 v19, v18, v19 ; 10262712 V_MUL_F32_e32 v18, v18, v19 ; 10242712 V_MUL_F32_e32 v16, v16, v18 ; 10202510 V_MUL_F32_e64 v15, v10, v15, 0, 0, 0, 0 ; D210000F 02021F0A V_MAD_F32 v15, s12, v15, v16, 0, 0, 0, 0 ; D282000F 04421E0C V_MUL_F32_e32 v16, v13, v17 ; 1020230D V_MUL_F32_e32 v16, s13, v16 ; 1020200D V_MUL_F32_e64 v13, v9, v13, 0, 0, 0, 0 ; D210000D 02021B09 V_MAD_F32 v13, v13, s6, v16, 0, 0, 0, 0 ; D282000D 04400D0D V_MUL_F32_e32 v13, v13, v18 ; 101A250D V_MUL_F32_e64 v14, v10, v14, 0, 0, 0, 0 ; D210000E 02021D0A V_MAD_F32 v14, s13, v14, v13, 0, 0, 0, 0 ; D282000E 04361C0D V_MUL_F32_e32 v13, v11, v17 ; 101A230B V_MUL_F32_e32 v13, s14, v13 ; 101A1A0E V_MUL_F32_e64 v9, v9, v11, 0, 0, 0, 0 ; D2100009 02021709 V_MAD_F32 v9, v9, s7, v13, 0, 0, 0, 0 ; D2820009 04340F09 V_MUL_F32_e32 v9, v9, v18 ; 10122509 V_MUL_F32_e64 v10, v10, v12, 0, 0, 0, 0 ; D210000A 0202190A V_MAD_F32 v16, s14, v10, v9, 0, 0, 0, 0 ; D2820010 0426140E V_MOV_B32_e32 v9, -2147483648 ; 7E1202FF 80000000 V_XOR_B32_e32 v8, v8, v9 ; 3A101308 V_XOR_B32_e32 v6, v6, v9 ; 3A0C1306 V_XOR_B32_e32 v7, v7, v9 ; 3A0E1307 V_MOV_B32_e32 v9, 0.000000e+00 ; 7E120280 S_MOV_B64 s[2:3], 0 ; BE820480 V_MOV_B32_e32 v10, s4 ; 7E140204 V_MOV_B32_e32 v11, v16 ; 7E160310 V_MOV_B32_e32 v13, v14 ; 7E1A030E V_MOV_B32_e32 v12, v15 ; 7E18030F V_CMP_GE_I32_e64 s[4:5], v9, v10, 0, 0, 0, 0 ; D10C0004 02021509 V_CNDMASK_B32_e64 v14, 0, -1, s[4:5], 0, 0, 0, 0 ; D200000E 00118280 V_CMP_EQ_I32_e64 s[4:5], v14, 0, 0, 0, 0, 0 ; D1040004 0201010E S_AND_SAVEEXEC_B64 s[4:5], s[4:5] ; BE842404 S_XOR_B64 s[4:5], exec, s[4:5] ; 8984047E S_CBRANCH_EXECZ BB0_10 ; BF880000 V_MUL_LO_I32 v14, 7, v9, 0, 0, 0, 0, 0 ; D2D6000E 02021287 V_LSHLREV_B32_e32 v16, 4, v14 ; 34201C84 V_ADD_I32_e32 v14, 80, v16 ; 4A1C20FF 00000050 BUFFER_LOAD_DWORD v14, s[8:11] + v14 + 0, glc=0, slc=0, tfe=0 ; E0301000 80020E0E S_WAITCNT vmcnt(0) expcnt(0) ; BF8C0700 V_ADD_F32_e32 v14, v6, v14 ; 061C1D06 V_ADD_I32_e32 v15, 64, v16 ; 4A1E20C0 BUFFER_LOAD_DWORD v15, s[8:11] + v15 + 0, glc=0, slc=0, tfe=0 ; E0301000 80020F0F S_WAITCNT vmcnt(0) ; BF8C0770 V_ADD_F32_e32 v15, v7, v15 ; 061E1F07 V_MUL_F32_e32 v17, v15, v15 ; 10221F0F V_MAD_F32 v17, v14, v14, v17, 0, 0, 0, 0 ; D2820011 04461D0E V_ADD_I32_e32 v18, 96, v16 ; 4A2420FF 00000060 BUFFER_LOAD_DWORD v18, s[8:11] + v18 + 0, glc=0, slc=0, tfe=0 ; E0301000 80021212 S_WAITCNT vmcnt(0) ; BF8C0770 V_ADD_F32_e32 v18, v8, v18 ; 06242508 V_MAD_F32 v17, v18, v18, v17, 0, 0, 0, 0 ; D2820011 04462512 V_RSQ_LEGACY_F32_e32 v19, v17 ; 7E265B11 V_MUL_F32_e32 v19, v19, v17 ; 10262313 V_XOR_B32_e32 v17, -2147483648, v17 ; 3A2222FF 80000000 V_CMP_GT_F32_e64 s[16:17], 0, v17, 0, 0, 0, 0 ; D0080010 02022280 V_CNDMASK_B32_e64 v17, 0.000000e+00, v19, s[16:17], 0, 0, 0, 0 ; D2000011 00422680 V_RCP_F32_e32 v19, v17 ; 7E265511 V_MUL_F32_e32 v14, v14, v19 ; 101C270E V_MUL_F32_e32 v15, v15, v19 ; 101E270F V_MUL_F32_e32 v20, v0, v15 ; 10281F00 V_MAD_F32 v20, v1, v14, v20, 0, 0, 0, 0 ; D2820014 04521D01 V_MUL_F32_e32 v18, v18, v19 ; 10242712 V_MAD_F32 v19, v2, v18, v20, 0, 0, 0, 0 ; D2820013 04522502 V_CMP_U_F32_e64 s[16:17], v19, v19, 0, 0, 0, 0 ; D0100010 02022713 V_CMP_LE_F32_e64 s[18:19], v19, 0.000000e+00, 0, 0, 0, 0 ; D0060012 02010113 S_OR_B64 s[16:17], s[18:19], s[16:17] ; 88901012 V_CNDMASK_B32_e64 v19, v19, 0.000000e+00, s[16:17], 0, 0, 0, 0 ; D2000013 00410113 V_ADD_I32_e32 v20, 144, v16 ; 4A2820FF 00000090 BUFFER_LOAD_DWORD v20, s[8:11] + v20 + 0, glc=0, slc=0, tfe=0 ; E0301000 80021414 S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v21, v19, v20 ; 102A2913 V_MUL_F32_e32 v21, s12, v21 ; 102A2A0C V_MUL_F32_e32 v15, v4, v15 ; 101E1F04 V_MAD_F32 v14, v3, v14, v15, 0, 0, 0, 0 ; D282000E 043E1D03 V_MAD_F32 v14, v5, v18, v14, 0, 0, 0, 0 ; D282000E 043A2505 V_MOV_B32_e32 v15, 1.000000e-03 ; 7E1E02FF 3A83126F V_CMP_LE_F32_e64 s[16:17], v14, v15, 0, 0, 0, 0 ; D0060010 02021F0E V_CMP_U_F32_e64 s[18:19], v14, v14, 0, 0, 0, 0 ; D0100012 02021D0E S_OR_B64 s[16:17], s[16:17], s[18:19] ; 88901210 V_CNDMASK_B32_e64 v14, v14, v15, s[16:17], 0, 0, 0, 0 ; D200000E 00421F0E V_LOG_F32_e32 v14, v14 ; 7E1C4F0E V_MUL_LEGACY_F32_e32 v14, s0, v14 ; 0E1C1C00 V_EXP_F32_e32 v18, v14 ; 7E244B0E V_MUL_F32_e32 v14, v18, v20 ; 101C2912 V_MAD_F32 v14, v14, s1, v21, 0, 0, 0, 0 ; D282000E 0454030E V_ADD_I32_e32 v15, 160, v16 ; 4A1E20FF 000000A0 BUFFER_LOAD_DWORD v15, s[8:11] + v15 + 0, glc=0, slc=0, tfe=0 ; E0301000 80020F0F S_WAITCNT vmcnt(0) ; BF8C0770 V_MAD_F32 v17, v15, -5.000000e-01, v17, 0, 0, 0, 0 ; D2820011 0445E30F V_MAD_F32 v15, v15, -5.000000e-01, v15, 0, 0, 0, 0 ; D282000F 043DE30F V_RCP_F32_e32 v15, v15 ; 7E1E550F V_MUL_F32_e32 v15, v17, v15 ; 101E1F11 V_ADD_F32_e64 v15, 0, v15, 0, 1, 0, 0 ; D206080F 02021E80 V_ADD_F32_e32 v17, v15, v15 ; 06221F0F V_SUB_F32_e32 v17, 3.000000e+00, v17 ; 082222FF 40400000 V_MUL_F32_e32 v17, v15, v17 ; 1022230F V_MUL_F32_e32 v15, v15, v17 ; 101E230F V_SUB_F32_e32 v17, 1.000000e+00, v15 ; 08221EF2 V_MAD_F32 v15, v14, v17, v12, 0, 0, 0, 0 ; D282000F 0432230E V_ADD_I32_e32 v14, 128, v16 ; 4A1C20FF 00000080 BUFFER_LOAD_DWORD v14, s[8:11] + v14 + 0, glc=0, slc=0, tfe=0 ; E0301000 80020E0E S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v20, v19, v14 ; 10281D13 V_MUL_F32_e32 v20, s13, v20 ; 1028280D V_MUL_F32_e32 v14, v18, v14 ; 101C1D12 V_MAD_F32 v14, v14, s6, v20, 0, 0, 0, 0 ; D282000E 04500D0E V_MAD_F32 v14, v14, v17, v13, 0, 0, 0, 0 ; D282000E 0436230E V_ADD_I32_e32 v16, 112, v16 ; 4A2020FF 00000070 BUFFER_LOAD_DWORD v16, s[8:11] + v16 + 0, glc=0, slc=0, tfe=0 ; E0301000 80021010 S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v19, v19, v16 ; 10262113 V_MUL_F32_e32 v19, s14, v19 ; 1026260E V_MUL_F32_e32 v16, v18, v16 ; 10202112 V_MAD_F32 v16, v16, s7, v19, 0, 0, 0, 0 ; D2820010 044C0F10 V_MAD_F32 v16, v16, v17, v11, 0, 0, 0, 0 ; D2820010 042E2310 V_ADD_I32_e32 v9, 1, v9 ; 4A121281 S_OR_B64 exec, exec, s[4:5] ; 88FE047E S_OR_B64 s[2:3], s[4:5], s[2:3] ; 88820204 S_ANDN2_B64 exec, exec, s[2:3] ; 8AFE027E S_CBRANCH_EXECNZ BB0_9 ; BF890000 S_OR_B64 exec, exec, s[2:3] ; 88FE027E V_CVT_PKRTZ_F16_F32_e64 v0, v11, v13, 0, 0, 0, 0 ; D25E0000 02021B0B V_CVT_PKRTZ_F16_F32_e64 v1, v12, 0.000000e+00, 0, 0, 0, 0 ; D25E0001 0201010C EXP 15, 0, 1, 1, 1, v0, v1, v0, v1 ; F8001C0F 01000100 S_ENDPGM ; BF810000 VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[20] DCL OUT[2], GENERIC[21] DCL CONST[0..3] DCL CONST[1][0..96] DCL CONST[2][0..68] DCL TEMP[0..5], LOCAL DCL ADDR[0] IMM[0] UINT32 {0, 48, 32, 16} IMM[1] INT32 {3, 2, 1, 0} IMM[2] UINT32 {176, 160, 144, 128} IMM[3] INT32 {11, 10, 9, 8} 0: MUL TEMP[0], CONST[0], IN[0].xxxx 1: MAD TEMP[0], CONST[1], IN[0].yyyy, TEMP[0] 2: MAD TEMP[0], CONST[2], IN[0].zzzz, TEMP[0] 3: ADD TEMP[0], TEMP[0], CONST[3] 4: UARL ADDR[0].x, IMM[1].xxxx 5: MOV TEMP[1], CONST[1][ADDR[0].x] 6: UARL ADDR[0].x, IMM[1].yyyy 7: MOV TEMP[2], CONST[1][ADDR[0].x] 8: UARL ADDR[0].x, IMM[1].zzzz 9: MOV TEMP[3], CONST[1][ADDR[0].x] 10: UARL ADDR[0].x, IMM[1].wwww 11: MOV TEMP[4], CONST[1][ADDR[0].x] 12: MUL TEMP[4], TEMP[4], TEMP[0].xxxx 13: MAD TEMP[3], TEMP[3], TEMP[0].yyyy, TEMP[4] 14: MAD TEMP[2], TEMP[2], TEMP[0].zzzz, TEMP[3] 15: MAD TEMP[1].xyz, TEMP[1], TEMP[0].wwww, TEMP[2] 16: UARL ADDR[0].x, IMM[3].xxxx 17: MOV TEMP[2], CONST[1][ADDR[0].x] 18: UARL ADDR[0].x, IMM[3].yyyy 19: MOV TEMP[3], CONST[1][ADDR[0].x] 20: UARL ADDR[0].x, IMM[3].zzzz 21: MOV TEMP[4], CONST[1][ADDR[0].x] 22: UARL ADDR[0].x, IMM[3].wwww 23: MOV TEMP[5], CONST[1][ADDR[0].x] 24: MUL TEMP[5], TEMP[5], TEMP[0].xxxx 25: MAD TEMP[4], TEMP[4], TEMP[0].yyyy, TEMP[5] 26: MAD TEMP[3], TEMP[3], TEMP[0].zzzz, TEMP[4] 27: MAD TEMP[0], TEMP[2], TEMP[0].wwww, TEMP[3] 28: MUL TEMP[2].xyz, CONST[0].xyzz, IN[1].xxxx 29: MAD TEMP[2].xyz, CONST[1].xyzz, IN[1].yyyy, TEMP[2].xyzz 30: MAD TEMP[2].xyz, CONST[2].xyzz, IN[1].zzzz, TEMP[2].xyzz 31: MOV TEMP[2].w, TEMP[1].xxxx 32: MOV TEMP[1].xy, TEMP[1].yzyy 33: MOV OUT[2], TEMP[1] 34: MOV OUT[1], TEMP[2] 35: MOV OUT[0], TEMP[0] 36: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0 %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0 %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0) %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4) %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8) %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12) %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16) %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20) %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24) %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28) %20 = call float @llvm.SI.load.const(<16 x i8> %11, i32 32) %21 = call float @llvm.SI.load.const(<16 x i8> %11, i32 36) %22 = call float @llvm.SI.load.const(<16 x i8> %11, i32 40) %23 = call float @llvm.SI.load.const(<16 x i8> %11, i32 44) %24 = call float @llvm.SI.load.const(<16 x i8> %11, i32 48) %25 = call float @llvm.SI.load.const(<16 x i8> %11, i32 52) %26 = call float @llvm.SI.load.const(<16 x i8> %11, i32 56) %27 = call float @llvm.SI.load.const(<16 x i8> %11, i32 60) %28 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 1 %29 = load <16 x i8> addrspace(2)* %28, !tbaa !0 %30 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 0 %31 = load <16 x i8> addrspace(2)* %30, !tbaa !0 %32 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %31, i32 0, i32 %6) %33 = extractelement <4 x float> %32, i32 0 %34 = extractelement <4 x float> %32, i32 1 %35 = extractelement <4 x float> %32, i32 2 %36 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 1 %37 = load <16 x i8> addrspace(2)* %36, !tbaa !0 %38 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %37, i32 0, i32 %6) %39 = extractelement <4 x float> %38, i32 0 %40 = extractelement <4 x float> %38, i32 1 %41 = extractelement <4 x float> %38, i32 2 %42 = fmul float %12, %33 %43 = fmul float %13, %33 %44 = fmul float %14, %33 %45 = fmul float %15, %33 %46 = fmul float %16, %34 %47 = fadd float %46, %42 %48 = fmul float %17, %34 %49 = fadd float %48, %43 %50 = fmul float %18, %34 %51 = fadd float %50, %44 %52 = fmul float %19, %34 %53 = fadd float %52, %45 %54 = fmul float %20, %35 %55 = fadd float %54, %47 %56 = fmul float %21, %35 %57 = fadd float %56, %49 %58 = fmul float %22, %35 %59 = fadd float %58, %51 %60 = fmul float %23, %35 %61 = fadd float %60, %53 %62 = fadd float %55, %24 %63 = fadd float %57, %25 %64 = fadd float %59, %26 %65 = fadd float %61, %27 %66 = shl i32 3, 4 %67 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %66) %68 = shl i32 3, 4 %69 = add i32 %68, 4 %70 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %69) %71 = shl i32 3, 4 %72 = add i32 %71, 8 %73 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %72) %74 = shl i32 3, 4 %75 = add i32 %74, 12 %76 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %75) %77 = shl i32 2, 4 %78 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %77) %79 = shl i32 2, 4 %80 = add i32 %79, 4 %81 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %80) %82 = shl i32 2, 4 %83 = add i32 %82, 8 %84 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %83) %85 = shl i32 1, 4 %86 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %85) %87 = shl i32 1, 4 %88 = add i32 %87, 4 %89 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %88) %90 = shl i32 1, 4 %91 = add i32 %90, 8 %92 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %91) %93 = shl i32 0, 4 %94 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %93) %95 = shl i32 0, 4 %96 = add i32 %95, 4 %97 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %96) %98 = shl i32 0, 4 %99 = add i32 %98, 8 %100 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %99) %101 = fmul float %94, %62 %102 = fmul float %97, %62 %103 = fmul float %100, %62 %104 = fmul float %86, %63 %105 = fadd float %104, %101 %106 = fmul float %89, %63 %107 = fadd float %106, %102 %108 = fmul float %92, %63 %109 = fadd float %108, %103 %110 = fmul float %78, %64 %111 = fadd float %110, %105 %112 = fmul float %81, %64 %113 = fadd float %112, %107 %114 = fmul float %84, %64 %115 = fadd float %114, %109 %116 = fmul float %67, %65 %117 = fadd float %116, %111 %118 = fmul float %70, %65 %119 = fadd float %118, %113 %120 = fmul float %73, %65 %121 = fadd float %120, %115 %122 = shl i32 11, 4 %123 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %122) %124 = shl i32 11, 4 %125 = add i32 %124, 4 %126 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %125) %127 = shl i32 11, 4 %128 = add i32 %127, 8 %129 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %128) %130 = shl i32 11, 4 %131 = add i32 %130, 12 %132 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %131) %133 = shl i32 10, 4 %134 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %133) %135 = shl i32 10, 4 %136 = add i32 %135, 4 %137 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %136) %138 = shl i32 10, 4 %139 = add i32 %138, 8 %140 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %139) %141 = shl i32 10, 4 %142 = add i32 %141, 12 %143 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %142) %144 = shl i32 9, 4 %145 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %144) %146 = shl i32 9, 4 %147 = add i32 %146, 4 %148 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %147) %149 = shl i32 9, 4 %150 = add i32 %149, 8 %151 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %150) %152 = shl i32 9, 4 %153 = add i32 %152, 12 %154 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %153) %155 = shl i32 8, 4 %156 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %155) %157 = shl i32 8, 4 %158 = add i32 %157, 4 %159 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %158) %160 = shl i32 8, 4 %161 = add i32 %160, 8 %162 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %161) %163 = shl i32 8, 4 %164 = add i32 %163, 12 %165 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %164) %166 = fmul float %156, %62 %167 = fmul float %159, %62 %168 = fmul float %162, %62 %169 = fmul float %165, %62 %170 = fmul float %145, %63 %171 = fadd float %170, %166 %172 = fmul float %148, %63 %173 = fadd float %172, %167 %174 = fmul float %151, %63 %175 = fadd float %174, %168 %176 = fmul float %154, %63 %177 = fadd float %176, %169 %178 = fmul float %134, %64 %179 = fadd float %178, %171 %180 = fmul float %137, %64 %181 = fadd float %180, %173 %182 = fmul float %140, %64 %183 = fadd float %182, %175 %184 = fmul float %143, %64 %185 = fadd float %184, %177 %186 = fmul float %123, %65 %187 = fadd float %186, %179 %188 = fmul float %126, %65 %189 = fadd float %188, %181 %190 = fmul float %129, %65 %191 = fadd float %190, %183 %192 = fmul float %132, %65 %193 = fadd float %192, %185 %194 = fmul float %12, %39 %195 = fmul float %13, %39 %196 = fmul float %14, %39 %197 = fmul float %16, %40 %198 = fadd float %197, %194 %199 = fmul float %17, %40 %200 = fadd float %199, %195 %201 = fmul float %18, %40 %202 = fadd float %201, %196 %203 = fmul float %20, %41 %204 = fadd float %203, %198 %205 = fmul float %21, %41 %206 = fadd float %205, %200 %207 = fmul float %22, %41 %208 = fadd float %207, %202 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %204, float %206, float %208, float %117) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %119, float %121, float %121, float %76) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %187, float %189, float %191, float %193) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_LOAD_DWORDX4 s[4:7], s[8:9], 0 ; C0820900 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[1:4], s[4:7][v0] + 0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80010100 S_LOAD_DWORDX4 s[4:7], s[0:1], 0 ; C0820100 S_WAITCNT vmcnt(0) lgkmcnt(0) ; BF8C0070 S_BUFFER_LOAD_DWORD s10, s[4:7], 1 ; C2050501 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v5, s10, v1 ; 100A020A S_BUFFER_LOAD_DWORD s11, s[4:7], 5 ; C2058505 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v5, s11, v2, v5, 0, 0, 0, 0 ; D2820005 0416040B S_BUFFER_LOAD_DWORD s12, s[4:7], 9 ; C2060509 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v5, s12, v3, v5, 0, 0, 0, 0 ; D2820005 0416060C S_BUFFER_LOAD_DWORD s2, s[4:7], 13 ; C201050D S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v5, s2, v5 ; 060A0A02 S_BUFFER_LOAD_DWORD s13, s[4:7], 0 ; C2068500 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v6, s13, v1 ; 100C020D S_BUFFER_LOAD_DWORD s14, s[4:7], 4 ; C2070504 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v6, s14, v2, v6, 0, 0, 0, 0 ; D2820006 041A040E S_BUFFER_LOAD_DWORD s15, s[4:7], 8 ; C2078508 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v6, s15, v3, v6, 0, 0, 0, 0 ; D2820006 041A060F S_BUFFER_LOAD_DWORD s2, s[4:7], 12 ; C201050C S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v6, s2, v6 ; 060C0C02 S_LOAD_DWORDX4 s[0:3], s[0:1], 4 ; C0800104 S_WAITCNT lgkmcnt(0) ; BF8C007F S_BUFFER_LOAD_DWORD s16, s[0:3], 0 ; C2080100 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v7, s16, v6 ; 100E0C10 S_BUFFER_LOAD_DWORD s16, s[0:3], 4 ; C2080104 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v7, s16, v5, v7, 0, 0, 0, 0 ; D2820007 041E0A10 S_BUFFER_LOAD_DWORD s16, s[4:7], 2 ; C2080502 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v8, s16, v1 ; 10100210 S_BUFFER_LOAD_DWORD s17, s[4:7], 6 ; C2088506 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v8, s17, v2, v8, 0, 0, 0, 0 ; D2820008 04220411 S_BUFFER_LOAD_DWORD s18, s[4:7], 10 ; C209050A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v8, s18, v3, v8, 0, 0, 0, 0 ; D2820008 04220612 S_BUFFER_LOAD_DWORD s19, s[4:7], 14 ; C209850E S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v8, s19, v8 ; 06101013 S_BUFFER_LOAD_DWORD s19, s[0:3], 8 ; C2098108 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v7, s19, v8, v7, 0, 0, 0, 0 ; D2820007 041E1013 S_BUFFER_LOAD_DWORD s19, s[4:7], 3 ; C2098503 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v9, s19, v1 ; 10120213 S_BUFFER_LOAD_DWORD s19, s[4:7], 7 ; C2098507 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v9, s19, v2, v9, 0, 0, 0, 0 ; D2820009 04260413 S_BUFFER_LOAD_DWORD s19, s[4:7], 11 ; C209850B S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v1, s19, v3, v9, 0, 0, 0, 0 ; D2820001 04260613 S_BUFFER_LOAD_DWORD s4, s[4:7], 15 ; C202050F S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v1, s4, v1 ; 06020204 S_BUFFER_LOAD_DWORD s4, s[0:3], 12 ; C202010C S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v2, s4, v1, v7, 0, 0, 0, 0 ; D2820002 041E0204 S_LOAD_DWORDX4 s[4:7], s[8:9], 4 ; C0820904 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[9:12], s[4:7][v0] + 0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80010900 S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v0, s16, v9 ; 10001210 V_MAD_F32 v0, s17, v10, v0, 0, 0, 0, 0 ; D2820000 04021411 V_MAD_F32 v0, s18, v11, v0, 0, 0, 0, 0 ; D2820000 04021612 V_MUL_F32_e32 v3, s10, v9 ; 1006120A V_MAD_F32 v3, s11, v10, v3, 0, 0, 0, 0 ; D2820003 040E140B V_MAD_F32 v3, s12, v11, v3, 0, 0, 0, 0 ; D2820003 040E160C V_MUL_F32_e32 v4, s13, v9 ; 1008120D V_MAD_F32 v4, s14, v10, v4, 0, 0, 0, 0 ; D2820004 0412140E V_MAD_F32 v4, s15, v11, v4, 0, 0, 0, 0 ; D2820004 0412160F EXP 15, 32, 0, 0, 0, v4, v3, v0, v2 ; F800020F 02000304 S_BUFFER_LOAD_DWORD s4, s[0:3], 2 ; C2020102 S_WAITCNT expcnt(0) lgkmcnt(0) ; BF8C000F V_MUL_F32_e32 v0, s4, v6 ; 10000C04 S_BUFFER_LOAD_DWORD s4, s[0:3], 6 ; C2020106 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v0, s4, v5, v0, 0, 0, 0, 0 ; D2820000 04020A04 S_BUFFER_LOAD_DWORD s4, s[0:3], 10 ; C202010A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v0, s4, v8, v0, 0, 0, 0, 0 ; D2820000 04021004 S_BUFFER_LOAD_DWORD s4, s[0:3], 14 ; C202010E S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v0, s4, v1, v0, 0, 0, 0, 0 ; D2820000 04020204 S_BUFFER_LOAD_DWORD s4, s[0:3], 1 ; C2020101 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v2, s4, v6 ; 10040C04 S_BUFFER_LOAD_DWORD s4, s[0:3], 5 ; C2020105 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v2, s4, v5, v2, 0, 0, 0, 0 ; D2820002 040A0A04 S_BUFFER_LOAD_DWORD s4, s[0:3], 9 ; C2020109 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v2, s4, v8, v2, 0, 0, 0, 0 ; D2820002 040A1004 S_BUFFER_LOAD_DWORD s4, s[0:3], 13 ; C202010D S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v2, s4, v1, v2, 0, 0, 0, 0 ; D2820002 040A0204 S_BUFFER_LOAD_DWORD s4, s[0:3], 15 ; C202010F S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v3, s4 ; 7E060204 EXP 15, 33, 0, 0, 0, v2, v0, v0, v3 ; F800021F 03000002 S_BUFFER_LOAD_DWORD s4, s[0:3], 35 ; C2020123 S_WAITCNT expcnt(0) lgkmcnt(0) ; BF8C000F V_MUL_F32_e32 v0, s4, v6 ; 10000C04 S_BUFFER_LOAD_DWORD s4, s[0:3], 39 ; C2020127 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v0, s4, v5, v0, 0, 0, 0, 0 ; D2820000 04020A04 S_BUFFER_LOAD_DWORD s4, s[0:3], 43 ; C202012B S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v0, s4, v8, v0, 0, 0, 0, 0 ; D2820000 04021004 S_BUFFER_LOAD_DWORD s4, s[0:3], 47 ; C202012F S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v0, s4, v1, v0, 0, 0, 0, 0 ; D2820000 04020204 S_BUFFER_LOAD_DWORD s4, s[0:3], 34 ; C2020122 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v2, s4, v6 ; 10040C04 S_BUFFER_LOAD_DWORD s4, s[0:3], 38 ; C2020126 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v2, s4, v5, v2, 0, 0, 0, 0 ; D2820002 040A0A04 S_BUFFER_LOAD_DWORD s4, s[0:3], 42 ; C202012A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v2, s4, v8, v2, 0, 0, 0, 0 ; D2820002 040A1004 S_BUFFER_LOAD_DWORD s4, s[0:3], 46 ; C202012E S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v2, s4, v1, v2, 0, 0, 0, 0 ; D2820002 040A0204 S_BUFFER_LOAD_DWORD s4, s[0:3], 33 ; C2020121 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v3, s4, v6 ; 10060C04 S_BUFFER_LOAD_DWORD s4, s[0:3], 37 ; C2020125 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v3, s4, v5, v3, 0, 0, 0, 0 ; D2820003 040E0A04 S_BUFFER_LOAD_DWORD s4, s[0:3], 41 ; C2020129 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v3, s4, v8, v3, 0, 0, 0, 0 ; D2820003 040E1004 S_BUFFER_LOAD_DWORD s4, s[0:3], 45 ; C202012D S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v3, s4, v1, v3, 0, 0, 0, 0 ; D2820003 040E0204 S_BUFFER_LOAD_DWORD s4, s[0:3], 32 ; C2020120 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v4, s4, v6 ; 10080C04 S_BUFFER_LOAD_DWORD s4, s[0:3], 36 ; C2020124 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v4, s4, v5, v4, 0, 0, 0, 0 ; D2820004 04120A04 S_BUFFER_LOAD_DWORD s4, s[0:3], 40 ; C2020128 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v4, s4, v8, v4, 0, 0, 0, 0 ; D2820004 04121004 S_BUFFER_LOAD_DWORD s0, s[0:3], 44 ; C200012C S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v1, s0, v1, v4, 0, 0, 0, 0 ; D2820001 04120200 EXP 15, 12, 0, 1, 0, v1, v3, v2, v0 ; F80008CF 00020301 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[20], PERSPECTIVE DCL IN[1], GENERIC[21], PERSPECTIVE DCL IN[2], GENERIC[22], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL SAMP[1] DCL SAMP[2] DCL SAMP[3] DCL SAMP[4] DCL SAMP[5] DCL SAMP[6] DCL SAMP[7] DCL CONST[2..73] DCL CONST[80..93] DCL CONST[1][0..96] DCL CONST[2][0..68] DCL TEMP[0..41], LOCAL DCL ADDR[0] IMM[0] UINT32 {0, 224, 208, 192} IMM[1] INT32 {14, 13, 12, 15} IMM[2] UINT32 {240, 320, 1, 256} IMM[3] INT32 {20, 16, 6, 5} IMM[4] FLT32 { 0.0000, 1.0000, 0.6931, 0.0010} IMM[5] FLT32 { 2.0000, -1.0039, 0.5000, 3.0000} IMM[6] FLT32 { 1.0500, 0.8000, 0.7213, -1.0000} IMM[7] UINT32 {96, 80, 64, 112} IMM[8] INT32 {4, 7, 10, 9} IMM[9] UINT32 {252, 264, 160, 144} IMM[10] UINT32 {128, 176, 260, 0} IMM[11] INT32 {8, 11, 0, 1} IMM[12] FLT32 { -0.8000, 5.0000, 0.0000, 0.0000} IMM[13] INT32 {2, 3, 0, 0} 0: MOV TEMP[0].xy, IN[1].zwzz 1: MOV TEMP[0].z, IN[2].xxxx 2: UARL ADDR[0].x, IMM[1].xxxx 3: MOV TEMP[1], CONST[1][ADDR[0].x] 4: UARL ADDR[0].x, IMM[1].yyyy 5: MOV TEMP[2], CONST[1][ADDR[0].x] 6: UARL ADDR[0].x, IMM[1].zzzz 7: MOV TEMP[3], CONST[1][ADDR[0].x] 8: MUL TEMP[3], TEMP[3], IN[0].wwww 9: MAD TEMP[2], TEMP[2], IN[1].xxxx, TEMP[3] 10: MAD TEMP[1], TEMP[1], IN[1].yyyy, TEMP[2] 11: UARL ADDR[0].x, IMM[1].wwww 12: MOV TEMP[2], CONST[1][ADDR[0].x] 13: ADD TEMP[1], TEMP[1], TEMP[2] 14: UARL ADDR[0].x, IMM[3].xxxx 15: MOV TEMP[2].xyz, CONST[1][ADDR[0].x].xyzz 16: ADD TEMP[1].xyz, TEMP[1].xyzz, -TEMP[2].xyzz 17: DP3 TEMP[1].x, TEMP[1].xyzz, TEMP[1].xyzz 18: RSQ TEMP[2].x, TEMP[1].xxxx 19: MUL TEMP[2].x, TEMP[2].xxxx, TEMP[1].xxxx 20: CMP TEMP[2].x, -TEMP[1].xxxx, TEMP[2].xxxx, IMM[4].xxxx 21: RCP TEMP[1].x, CONST[85].xxxx 22: MAD TEMP[1].x, TEMP[2].xxxx, TEMP[1].xxxx, IMM[4].yyyy 23: LG2 TEMP[1].x, TEMP[1].xxxx 24: MUL TEMP[1].x, TEMP[1].xxxx, IMM[4].zzzz 25: LG2 TEMP[2].x, CONST[86].xxxx 26: MUL TEMP[2].x, TEMP[2].xxxx, IMM[4].zzzz 27: RCP TEMP[2].x, TEMP[2].xxxx 28: MUL TEMP[1].x, TEMP[1].xxxx, TEMP[2].xxxx 29: FLR TEMP[2].x, TEMP[1].xxxx 30: EX2 TEMP[2].x, TEMP[2].xxxx 31: FRC TEMP[1].x, TEMP[1].xxxx 32: ABS TEMP[3].xyz, IN[2].yzww 33: ADD TEMP[4].xyz, TEMP[3].xyzz, IMM[4].wwww 34: POW TEMP[5].x, TEMP[4].xxxx, CONST[84].xxxx 35: POW TEMP[5].y, TEMP[4].yyyy, CONST[84].xxxx 36: POW TEMP[5].z, TEMP[4].zzzz, CONST[84].xxxx 37: ADD TEMP[4].x, TEMP[5].xxxx, TEMP[5].yyyy 38: ADD TEMP[4].x, TEMP[4].xxxx, TEMP[5].zzzz 39: RCP TEMP[4].x, TEMP[4].xxxx 40: MUL TEMP[4].xyz, TEMP[5].xyzz, TEMP[4].xxxx 41: MUL TEMP[5].x, CONST[83].xxxx, TEMP[2].xxxx 42: RCP TEMP[5].x, TEMP[5].xxxx 43: MUL TEMP[5].xy, TEMP[0].zyyy, TEMP[5].xxxx 44: MOV TEMP[5].xy, TEMP[5].xyyy 45: TEX TEMP[5], TEMP[5], SAMP[4], 2D 46: MUL TEMP[6].x, CONST[82].xxxx, TEMP[2].xxxx 47: RCP TEMP[6].x, TEMP[6].xxxx 48: MUL TEMP[6].xy, TEMP[0].xzzz, TEMP[6].xxxx 49: MOV TEMP[6].xy, TEMP[6].xyyy 50: TEX TEMP[6], TEMP[6], SAMP[3], 2D 51: MUL TEMP[7].x, CONST[81].xxxx, TEMP[2].xxxx 52: RCP TEMP[7].x, TEMP[7].xxxx 53: MUL TEMP[7].xy, IN[1].zwww, TEMP[7].xxxx 54: MOV TEMP[7].xy, TEMP[7].xyyy 55: TEX TEMP[7], TEMP[7], SAMP[2], 2D 56: MUL TEMP[7].xyz, TEMP[7].xyzz, TEMP[4].zzzz 57: MAD TEMP[6].xyz, TEMP[6].xyzz, TEMP[4].yyyy, TEMP[7].xyzz 58: MAD TEMP[4].xyz, TEMP[5].xyzz, TEMP[4].xxxx, TEMP[6].xyzz 59: MUL TEMP[5].x, CONST[81].xxxx, TEMP[2].xxxx 60: RCP TEMP[5].x, TEMP[5].xxxx 61: MUL TEMP[5].xy, IN[1].zwww, TEMP[5].xxxx 62: MOV TEMP[5].xy, TEMP[5].xyyy 63: TEX TEMP[5], TEMP[5], SAMP[5], 2D 64: MAD TEMP[6].xy, TEMP[5].xyyy, IMM[5].xxxx, IMM[5].yyyy 65: MOV TEMP[6].z, TEMP[5].zzzz 66: MUL TEMP[5].x, CONST[82].xxxx, TEMP[2].xxxx 67: RCP TEMP[5].x, TEMP[5].xxxx 68: MUL TEMP[5].xy, TEMP[0].xzzz, TEMP[5].xxxx 69: MOV TEMP[5].xy, TEMP[5].xyyy 70: TEX TEMP[5], TEMP[5], SAMP[6], 2D 71: MAD TEMP[7].xy, TEMP[5].xyyy, IMM[5].xxxx, IMM[5].yyyy 72: MOV TEMP[7].z, TEMP[5].zzzz 73: MUL TEMP[5].x, CONST[83].xxxx, TEMP[2].xxxx 74: RCP TEMP[5].x, TEMP[5].xxxx 75: MUL TEMP[5].xy, TEMP[0].zyyy, TEMP[5].xxxx 76: MOV TEMP[5].xy, TEMP[5].xyyy 77: TEX TEMP[5], TEMP[5], SAMP[7], 2D 78: MAD TEMP[8].xy, TEMP[5].xyyy, IMM[5].xxxx, IMM[5].yyyy 79: MOV TEMP[8].z, TEMP[5].zzzz 80: ADD TEMP[5].x, TEMP[3].xxxx, TEMP[3].yyyy 81: ADD TEMP[5].x, TEMP[5].xxxx, TEMP[3].zzzz 82: RCP TEMP[5].x, TEMP[5].xxxx 83: MUL TEMP[3].xyz, TEMP[3].xyzz, TEMP[5].xxxx 84: SSG TEMP[5].x, IN[2].yyyy 85: MUL TEMP[5].xyz, TEMP[8].zyxx, TEMP[5].xxxx 86: SSG TEMP[8].x, IN[2].zzzz 87: MUL TEMP[7].xyz, TEMP[7].xzyy, TEMP[8].xxxx 88: SSG TEMP[8].x, IN[2].wwww 89: MUL TEMP[6].xyz, TEMP[6].xyzz, TEMP[8].xxxx 90: MUL TEMP[6].xyz, TEMP[6].xyzz, TEMP[3].zzzz 91: MAD TEMP[6].xyz, TEMP[7].xyzz, TEMP[3].yyyy, TEMP[6].xyzz 92: MAD TEMP[3].xyz, TEMP[5].xyzz, TEMP[3].xxxx, TEMP[6].xyzz 93: MOV TEMP[5].xyz, TEMP[4].xyzx 94: MOV TEMP[6].xyz, TEMP[3].xyzx 95: FSLT TEMP[7].x, TEMP[1].xxxx, CONST[87].xxxx 96: UIF TEMP[7].xxxx :0 97: MUL TEMP[2].x, TEMP[2].xxxx, IMM[5].zzzz 98: ABS TEMP[7].xyz, IN[2].yzww 99: ADD TEMP[8].xyz, TEMP[7].xyzz, IMM[4].wwww 100: POW TEMP[9].x, TEMP[8].xxxx, CONST[84].xxxx 101: POW TEMP[9].y, TEMP[8].yyyy, CONST[84].xxxx 102: POW TEMP[9].z, TEMP[8].zzzz, CONST[84].xxxx 103: ADD TEMP[8].x, TEMP[9].xxxx, TEMP[9].yyyy 104: ADD TEMP[8].x, TEMP[8].xxxx, TEMP[9].zzzz 105: RCP TEMP[8].x, TEMP[8].xxxx 106: MUL TEMP[8].xyz, TEMP[9].xyzz, TEMP[8].xxxx 107: MUL TEMP[9].x, CONST[81].xxxx, TEMP[2].xxxx 108: RCP TEMP[9].x, TEMP[9].xxxx 109: MUL TEMP[9].xy, IN[1].zwww, TEMP[9].xxxx 110: MOV TEMP[9].xy, TEMP[9].xyyy 111: TEX TEMP[9], TEMP[9], SAMP[5], 2D 112: MAD TEMP[10].xy, TEMP[9].xyyy, IMM[5].xxxx, IMM[5].yyyy 113: MOV TEMP[10].z, TEMP[9].zzzz 114: MUL TEMP[9].x, CONST[82].xxxx, TEMP[2].xxxx 115: RCP TEMP[9].x, TEMP[9].xxxx 116: MUL TEMP[9].xy, TEMP[0].xzzz, TEMP[9].xxxx 117: MOV TEMP[9].xy, TEMP[9].xyyy 118: TEX TEMP[9], TEMP[9], SAMP[6], 2D 119: MAD TEMP[11].xy, TEMP[9].xyyy, IMM[5].xxxx, IMM[5].yyyy 120: MOV TEMP[11].z, TEMP[9].zzzz 121: MUL TEMP[9].x, CONST[83].xxxx, TEMP[2].xxxx 122: RCP TEMP[9].x, TEMP[9].xxxx 123: MUL TEMP[9].xy, TEMP[0].zyyy, TEMP[9].xxxx 124: MOV TEMP[9].xy, TEMP[9].xyyy 125: TEX TEMP[9], TEMP[9], SAMP[7], 2D 126: MAD TEMP[12].xy, TEMP[9].xyyy, IMM[5].xxxx, IMM[5].yyyy 127: MOV TEMP[12].z, TEMP[9].zzzz 128: ADD TEMP[9].x, TEMP[7].xxxx, TEMP[7].yyyy 129: ADD TEMP[9].x, TEMP[9].xxxx, TEMP[7].zzzz 130: RCP TEMP[9].x, TEMP[9].xxxx 131: MUL TEMP[7].xyz, TEMP[7].xyzz, TEMP[9].xxxx 132: RCP TEMP[9].x, CONST[87].xxxx 133: MUL_SAT TEMP[1].x, TEMP[1].xxxx, TEMP[9].xxxx 134: MUL TEMP[9].x, IMM[5].xxxx, TEMP[1].xxxx 135: ADD TEMP[9].x, IMM[5].wwww, -TEMP[9].xxxx 136: MUL TEMP[9].x, TEMP[1].xxxx, TEMP[9].xxxx 137: MUL TEMP[1].x, TEMP[1].xxxx, TEMP[9].xxxx 138: MUL TEMP[9].x, CONST[83].xxxx, TEMP[2].xxxx 139: RCP TEMP[9].x, TEMP[9].xxxx 140: MUL TEMP[9].xy, TEMP[0].zyyy, TEMP[9].xxxx 141: MOV TEMP[9].xy, TEMP[9].xyyy 142: TEX TEMP[9], TEMP[9], SAMP[4], 2D 143: MUL TEMP[13].x, CONST[82].xxxx, TEMP[2].xxxx 144: RCP TEMP[13].x, TEMP[13].xxxx 145: MUL TEMP[0].xy, TEMP[0].xzzz, TEMP[13].xxxx 146: MOV TEMP[0].xy, TEMP[0].xyyy 147: TEX TEMP[0], TEMP[0], SAMP[3], 2D 148: MUL TEMP[2].x, CONST[81].xxxx, TEMP[2].xxxx 149: RCP TEMP[2].x, TEMP[2].xxxx 150: MUL TEMP[2].xy, IN[1].zwww, TEMP[2].xxxx 151: MOV TEMP[2].xy, TEMP[2].xyyy 152: TEX TEMP[2], TEMP[2], SAMP[2], 2D 153: MUL TEMP[2].xyz, TEMP[2].xyzz, TEMP[8].zzzz 154: MAD TEMP[0].xyz, TEMP[0].xyzz, TEMP[8].yyyy, TEMP[2].xyzz 155: MAD TEMP[0].xyz, TEMP[9].xyzz, TEMP[8].xxxx, TEMP[0].xyzz 156: LRP TEMP[5].xyz, TEMP[1].xxxx, TEMP[4].xyzz, TEMP[0].xyzz 157: SSG TEMP[0].x, IN[2].yyyy 158: MUL TEMP[0].xyz, TEMP[12].zyxx, TEMP[0].xxxx 159: SSG TEMP[2].x, IN[2].zzzz 160: MUL TEMP[2].xyz, TEMP[11].xzyy, TEMP[2].xxxx 161: SSG TEMP[4].x, IN[2].wwww 162: MUL TEMP[4].xyz, TEMP[10].xyzz, TEMP[4].xxxx 163: MUL TEMP[4].xyz, TEMP[4].xyzz, TEMP[7].zzzz 164: MAD TEMP[2].xyz, TEMP[2].xyzz, TEMP[7].yyyy, TEMP[4].xyzz 165: MAD TEMP[0].xyz, TEMP[0].xyzz, TEMP[7].xxxx, TEMP[2].xyzz 166: LRP TEMP[6].xyz, TEMP[1].xxxx, TEMP[3].xyzz, TEMP[0].xyzz 167: ENDIF 168: FSLT TEMP[0].x, IMM[5].zzzz, CONST[88].xxxx 169: UIF TEMP[0].xxxx :0 170: MUL TEMP[5].xyz, TEMP[5].xyzz, IN[0].xyzz 171: ENDIF 172: MUL TEMP[0].xyz, CONST[90].xyzz, TEMP[6].xxxx 173: MAD TEMP[0].xyz, CONST[91].xyzz, TEMP[6].yyyy, TEMP[0].xyzz 174: MAD TEMP[0].xyz, CONST[92].xyzz, TEMP[6].zzzz, TEMP[0].xyzz 175: DP3 TEMP[1].x, TEMP[0].xyzz, TEMP[0].xyzz 176: RSQ TEMP[1].x, TEMP[1].xxxx 177: MUL TEMP[0].xyz, TEMP[0].xyzz, TEMP[1].xxxx 178: MOV TEMP[1].xyz, TEMP[0].xyzx 179: MOV TEMP[2].xyz, TEMP[5].xyzx 180: MOV TEMP[3], CONST[80] 181: UARL ADDR[0].x, IMM[1].xxxx 182: MOV TEMP[4], CONST[1][ADDR[0].x] 183: UARL ADDR[0].x, IMM[1].yyyy 184: MOV TEMP[6], CONST[1][ADDR[0].x] 185: UARL ADDR[0].x, IMM[1].zzzz 186: MOV TEMP[7], CONST[1][ADDR[0].x] 187: MUL TEMP[7], TEMP[7], IN[0].wwww 188: MAD TEMP[6], TEMP[6], IN[1].xxxx, TEMP[7] 189: MAD TEMP[4], TEMP[4], IN[1].yyyy, TEMP[6] 190: UARL ADDR[0].x, IMM[1].wwww 191: MOV TEMP[6], CONST[1][ADDR[0].x] 192: ADD TEMP[4], TEMP[4], TEMP[6] 193: MOV TEMP[6].xyz, TEMP[4].xyzx 194: UARL ADDR[0].x, IMM[3].xxxx 195: MOV TEMP[7].xyz, CONST[1][ADDR[0].x].xyzz 196: ADD TEMP[7].xyz, TEMP[4].xyzz, -TEMP[7].xyzz 197: DP3 TEMP[8].x, TEMP[7].xyzz, TEMP[7].xyzz 198: RSQ TEMP[8].x, TEMP[8].xxxx 199: MUL TEMP[7].xyz, TEMP[7].xyzz, TEMP[8].xxxx 200: DP3 TEMP[8].x, TEMP[0].xyzz, TEMP[7].xyzz 201: MUL TEMP[8].xyz, TEMP[8].xxxx, TEMP[0].xyzz 202: MUL TEMP[8].xyz, IMM[5].xxxx, TEMP[8].xyzz 203: ADD TEMP[7].xyz, TEMP[7].xyzz, -TEMP[8].xyzz 204: MOV TEMP[8].xyz, TEMP[7].xyzx 205: ADD_SAT TEMP[9].x, TEMP[0].yyyy, IMM[6].xxxx 206: UARL ADDR[0].x, IMM[1].xxxx 207: MOV TEMP[10].xyz, CONST[2][ADDR[0].x].xyzz 208: MUL TEMP[9].xyz, TEMP[9].xxxx, TEMP[10].xyzz 209: MUL TEMP[9].xyz, TEMP[5].xyzz, TEMP[9].xyzz 210: UARL ADDR[0].x, IMM[1].zzzz 211: UARL ADDR[0].x, IMM[1].zzzz 212: MOV TEMP[10].xyz, CONST[2][ADDR[0].x].xyzz 213: UARL ADDR[0].x, IMM[1].yyyy 214: UARL ADDR[0].x, IMM[1].yyyy 215: MOV TEMP[11].xyz, CONST[2][ADDR[0].x].xyzz 216: DP3 TEMP[0].x, TEMP[0].xyzz, TEMP[10].xyzz 217: MAX TEMP[0].x, IMM[4].xxxx, TEMP[0].xxxx 218: MUL TEMP[0].xyz, TEMP[0].xxxx, TEMP[11].xyzz 219: MUL TEMP[0].xyz, TEMP[0].xyzz, TEMP[5].xyzz 220: DP3 TEMP[5].x, TEMP[7].xyzz, TEMP[10].xyzz 221: MAX TEMP[5].x, IMM[4].wwww, TEMP[5].xxxx 222: POW TEMP[5].x, TEMP[5].xxxx, CONST[80].wwww 223: MUL TEMP[5].xyz, TEMP[5].xxxx, TEMP[11].xyzz 224: MAD TEMP[0].xyz, TEMP[5].xyzz, CONST[80].xyzz, TEMP[0].xyzz 225: UARL ADDR[0].x, IMM[1].wwww 226: MOV TEMP[5].xyz, CONST[2][ADDR[0].x].xyzz 227: ADD TEMP[5].xyz, TEMP[4].xyzz, -TEMP[5].xyzz 228: DP3 TEMP[5].x, TEMP[5].xyzz, TEMP[5].xyzz 229: RSQ TEMP[7].x, TEMP[5].xxxx 230: MUL TEMP[7].x, TEMP[7].xxxx, TEMP[5].xxxx 231: CMP TEMP[5].x, -TEMP[5].xxxx, TEMP[7].xxxx, IMM[4].xxxx 232: MOV TEMP[7].x, IMM[4].xxxx 233: UARL ADDR[0].x, IMM[3].yyyy 234: UARL ADDR[0].x, IMM[3].yyyy 235: MOV TEMP[10].x, CONST[2][ADDR[0].x].xxxx 236: MUL TEMP[10].x, IMM[6].yyyy, TEMP[10].xxxx 237: FSLT TEMP[10].x, TEMP[5].xxxx, TEMP[10].xxxx 238: UIF TEMP[10].xxxx :0 239: UARL ADDR[0].x, IMM[3].zzzz 240: MOV TEMP[10], CONST[2][ADDR[0].x] 241: UARL ADDR[0].x, IMM[3].wwww 242: MOV TEMP[11], CONST[2][ADDR[0].x] 243: UARL ADDR[0].x, IMM[8].xxxx 244: MOV TEMP[12], CONST[2][ADDR[0].x] 245: MUL TEMP[12], TEMP[12], TEMP[4].xxxx 246: MAD TEMP[11], TEMP[11], TEMP[4].yyyy, TEMP[12] 247: MAD TEMP[10], TEMP[10], TEMP[4].zzzz, TEMP[11] 248: UARL ADDR[0].x, IMM[8].yyyy 249: MOV TEMP[11], CONST[2][ADDR[0].x] 250: ADD TEMP[10], TEMP[10], TEMP[11] 251: UARL ADDR[0].x, IMM[1].wwww 252: MOV TEMP[11].x, CONST[2][ADDR[0].x].wwww 253: MAX TEMP[12].x, TEMP[10].zzzz, IMM[6].wwww 254: MIN TEMP[12].x, TEMP[12].xxxx, IMM[4].yyyy 255: ADD TEMP[12].x, TEMP[12].xxxx, IMM[4].yyyy 256: MUL TEMP[11].x, -TEMP[11].xxxx, TEMP[12].xxxx 257: MUL TEMP[11].x, IMM[6].zzzz, TEMP[11].xxxx 258: EX2 TEMP[11].x, TEMP[11].xxxx 259: MAD TEMP[10].xy, TEMP[10].xyyy, IMM[5].zzzz, IMM[5].zzzz 260: UARL ADDR[0].x, IMM[3].yyyy 261: MOV TEMP[12].x, CONST[2][ADDR[0].x].zzzz 262: MUL TEMP[10].xy, TEMP[10].xyyy, TEMP[12].xxxx 263: MOV TEMP[10].xy, TEMP[10].xyyy 264: TEX TEMP[10], TEMP[10], SAMP[0], RECT 265: MUL_SAT TEMP[10].x, TEMP[11].xxxx, TEMP[10].xxxx 266: MOV TEMP[7].x, TEMP[10].xxxx 267: ELSE :0 268: UARL ADDR[0].x, IMM[3].yyyy 269: UARL ADDR[0].x, IMM[3].yyyy 270: MOV TEMP[10].x, CONST[2][ADDR[0].x].xxxx 271: FSLT TEMP[10].x, TEMP[10].xxxx, TEMP[5].xxxx 272: UIF TEMP[10].xxxx :0 273: UARL ADDR[0].x, IMM[8].zzzz 274: MOV TEMP[10], CONST[2][ADDR[0].x] 275: UARL ADDR[0].x, IMM[8].wwww 276: MOV TEMP[11], CONST[2][ADDR[0].x] 277: UARL ADDR[0].x, IMM[11].xxxx 278: MOV TEMP[12], CONST[2][ADDR[0].x] 279: MUL TEMP[12], TEMP[12], TEMP[4].xxxx 280: MAD TEMP[11], TEMP[11], TEMP[4].yyyy, TEMP[12] 281: MAD TEMP[10], TEMP[10], TEMP[4].zzzz, TEMP[11] 282: UARL ADDR[0].x, IMM[11].yyyy 283: MOV TEMP[11], CONST[2][ADDR[0].x] 284: ADD TEMP[10], TEMP[10], TEMP[11] 285: UARL ADDR[0].x, IMM[1].wwww 286: MOV TEMP[11].xyz, CONST[2][ADDR[0].x].xyzz 287: ADD TEMP[11].xyz, TEMP[4].xyzz, -TEMP[11].xyzz 288: DP3 TEMP[11].x, TEMP[11].xyzz, TEMP[11].xyzz 289: RSQ TEMP[12].x, TEMP[11].xxxx 290: MUL TEMP[12].x, TEMP[12].xxxx, TEMP[11].xxxx 291: CMP TEMP[12].x, -TEMP[11].xxxx, TEMP[12].xxxx, IMM[4].xxxx 292: UARL ADDR[0].x, IMM[3].yyyy 293: MOV TEMP[11].x, CONST[2][ADDR[0].x].yyyy 294: RCP TEMP[11].x, TEMP[11].xxxx 295: MAD TEMP[11].x, TEMP[12].xxxx, TEMP[11].xxxx, IMM[12].xxxx 296: MUL_SAT TEMP[11].x, TEMP[11].xxxx, IMM[12].yyyy 297: UARL ADDR[0].x, IMM[1].wwww 298: MOV TEMP[12].x, CONST[2][ADDR[0].x].wwww 299: MAX TEMP[13].x, TEMP[10].zzzz, IMM[6].wwww 300: MIN TEMP[13].x, TEMP[13].xxxx, IMM[4].yyyy 301: ADD TEMP[13].x, TEMP[13].xxxx, IMM[4].yyyy 302: MUL TEMP[12].x, -TEMP[12].xxxx, TEMP[13].xxxx 303: MUL TEMP[12].x, IMM[6].zzzz, TEMP[12].xxxx 304: EX2 TEMP[12].x, TEMP[12].xxxx 305: MAD TEMP[10].xy, TEMP[10].xyyy, IMM[5].zzzz, IMM[5].zzzz 306: UARL ADDR[0].x, IMM[3].yyyy 307: MOV TEMP[13].x, CONST[2][ADDR[0].x].zzzz 308: MUL TEMP[10].xy, TEMP[10].xyyy, TEMP[13].xxxx 309: MOV TEMP[10].xy, TEMP[10].xyyy 310: TEX TEMP[10], TEMP[10], SAMP[1], RECT 311: MUL_SAT TEMP[10].x, TEMP[12].xxxx, TEMP[10].xxxx 312: MUL TEMP[12].x, IMM[5].xxxx, TEMP[11].xxxx 313: ADD TEMP[12].x, IMM[5].wwww, -TEMP[12].xxxx 314: MUL TEMP[12].x, TEMP[11].xxxx, TEMP[12].xxxx 315: MUL TEMP[11].x, TEMP[11].xxxx, TEMP[12].xxxx 316: LRP TEMP[7].x, TEMP[11].xxxx, IMM[4].yyyy, TEMP[10].xxxx 317: ELSE :0 318: UARL ADDR[0].x, IMM[3].zzzz 319: MOV TEMP[10], CONST[2][ADDR[0].x] 320: UARL ADDR[0].x, IMM[3].wwww 321: MOV TEMP[11], CONST[2][ADDR[0].x] 322: UARL ADDR[0].x, IMM[8].xxxx 323: MOV TEMP[12], CONST[2][ADDR[0].x] 324: MUL TEMP[12], TEMP[12], TEMP[4].xxxx 325: MAD TEMP[11], TEMP[11], TEMP[4].yyyy, TEMP[12] 326: MAD TEMP[10], TEMP[10], TEMP[4].zzzz, TEMP[11] 327: UARL ADDR[0].x, IMM[8].yyyy 328: MOV TEMP[11], CONST[2][ADDR[0].x] 329: ADD TEMP[10], TEMP[10], TEMP[11] 330: UARL ADDR[0].x, IMM[8].zzzz 331: MOV TEMP[11], CONST[2][ADDR[0].x] 332: UARL ADDR[0].x, IMM[8].wwww 333: MOV TEMP[12], CONST[2][ADDR[0].x] 334: UARL ADDR[0].x, IMM[11].xxxx 335: MOV TEMP[13], CONST[2][ADDR[0].x] 336: MUL TEMP[13], TEMP[13], TEMP[4].xxxx 337: MAD TEMP[12], TEMP[12], TEMP[4].yyyy, TEMP[13] 338: MAD TEMP[4], TEMP[11], TEMP[4].zzzz, TEMP[12] 339: UARL ADDR[0].x, IMM[11].yyyy 340: MOV TEMP[11], CONST[2][ADDR[0].x] 341: ADD TEMP[4], TEMP[4], TEMP[11] 342: UARL ADDR[0].x, IMM[3].yyyy 343: UARL ADDR[0].x, IMM[3].yyyy 344: MOV TEMP[11].x, CONST[2][ADDR[0].x].xxxx 345: MUL TEMP[12].x, IMM[6].yyyy, TEMP[11].xxxx 346: ADD TEMP[5].x, TEMP[5].xxxx, -TEMP[12].xxxx 347: ADD TEMP[11].x, TEMP[11].xxxx, -TEMP[12].xxxx 348: RCP TEMP[11].x, TEMP[11].xxxx 349: MUL_SAT TEMP[5].x, TEMP[5].xxxx, TEMP[11].xxxx 350: UARL ADDR[0].x, IMM[1].wwww 351: UARL ADDR[0].x, IMM[1].wwww 352: MOV TEMP[11].x, CONST[2][ADDR[0].x].wwww 353: UARL ADDR[0].x, IMM[3].yyyy 354: UARL ADDR[0].x, IMM[3].yyyy 355: MOV TEMP[12].x, CONST[2][ADDR[0].x].zzzz 356: MAX TEMP[13].x, TEMP[10].zzzz, IMM[6].wwww 357: MIN TEMP[13].x, TEMP[13].xxxx, IMM[4].yyyy 358: ADD TEMP[13].x, TEMP[13].xxxx, IMM[4].yyyy 359: MUL TEMP[13].x, -TEMP[11].xxxx, TEMP[13].xxxx 360: MUL TEMP[13].x, IMM[6].zzzz, TEMP[13].xxxx 361: EX2 TEMP[13].x, TEMP[13].xxxx 362: MAD TEMP[10].xy, TEMP[10].xyyy, IMM[5].zzzz, IMM[5].zzzz 363: MUL TEMP[10].xy, TEMP[10].xyyy, TEMP[12].xxxx 364: MOV TEMP[10].xy, TEMP[10].xyyy 365: TEX TEMP[10], TEMP[10], SAMP[0], RECT 366: MUL_SAT TEMP[10].x, TEMP[13].xxxx, TEMP[10].xxxx 367: MAX TEMP[13].x, TEMP[4].zzzz, IMM[6].wwww 368: MIN TEMP[13].x, TEMP[13].xxxx, IMM[4].yyyy 369: ADD TEMP[13].x, TEMP[13].xxxx, IMM[4].yyyy 370: MUL TEMP[11].x, -TEMP[11].xxxx, TEMP[13].xxxx 371: MUL TEMP[11].x, IMM[6].zzzz, TEMP[11].xxxx 372: EX2 TEMP[11].x, TEMP[11].xxxx 373: MAD TEMP[4].xy, TEMP[4].xyyy, IMM[5].zzzz, IMM[5].zzzz 374: MUL TEMP[4].xy, TEMP[4].xyyy, TEMP[12].xxxx 375: MOV TEMP[4].xy, TEMP[4].xyyy 376: TEX TEMP[4], TEMP[4], SAMP[1], RECT 377: MUL_SAT TEMP[4].x, TEMP[11].xxxx, TEMP[4].xxxx 378: MUL TEMP[11].x, IMM[5].xxxx, TEMP[5].xxxx 379: ADD TEMP[11].x, IMM[5].wwww, -TEMP[11].xxxx 380: MUL TEMP[11].x, TEMP[5].xxxx, TEMP[11].xxxx 381: MUL TEMP[5].x, TEMP[5].xxxx, TEMP[11].xxxx 382: LRP TEMP[7].x, TEMP[5].xxxx, TEMP[4].xxxx, TEMP[10].xxxx 383: ENDIF 384: ENDIF 385: ADD TEMP[4].x, TEMP[7].xxxx, IMM[12].xxxx 386: MUL_SAT TEMP[4].x, TEMP[4].xxxx, IMM[12].yyyy 387: MUL TEMP[5].x, IMM[5].xxxx, TEMP[4].xxxx 388: ADD TEMP[5].x, IMM[5].wwww, -TEMP[5].xxxx 389: MUL TEMP[5].x, TEMP[4].xxxx, TEMP[5].xxxx 390: MUL TEMP[4].x, TEMP[4].xxxx, TEMP[5].xxxx 391: MUL TEMP[0].xyz, TEMP[0].xyzz, TEMP[4].xxxx 392: ADD TEMP[9].xyz, TEMP[9].xyzz, TEMP[0].xyzz 393: MOV TEMP[0].x, IMM[11].zzzz 394: BGNLOOP :0 395: ISGE TEMP[4].x, TEMP[0].xxxx, CONST[3].xxxx 396: UIF TEMP[4].xxxx :0 397: BRK 398: ENDIF 399: UMUL TEMP[5].x, TEMP[0].xxxx, IMM[8].yyyy 400: UARL ADDR[0].x, TEMP[5].xxxx 401: MOV TEMP[7].x, CONST[ADDR[0].x+4].xxxx 402: UADD TEMP[10].x, TEMP[5].xxxx, IMM[11].wwww 403: UARL ADDR[0].x, TEMP[10].xxxx 404: MOV TEMP[7].y, CONST[ADDR[0].x+4].xxxx 405: UADD TEMP[11].x, TEMP[5].xxxx, IMM[13].xxxx 406: UARL ADDR[0].x, TEMP[11].xxxx 407: MOV TEMP[7].z, CONST[ADDR[0].x+4].xxxx 408: UADD TEMP[12].x, TEMP[5].xxxx, IMM[13].yyyy 409: UARL ADDR[0].x, TEMP[12].xxxx 410: MOV TEMP[13].x, CONST[ADDR[0].x+4].xxxx 411: UADD TEMP[14].x, TEMP[5].xxxx, IMM[8].xxxx 412: UARL ADDR[0].x, TEMP[14].xxxx 413: MOV TEMP[13].y, CONST[ADDR[0].x+4].xxxx 414: UADD TEMP[15].x, TEMP[5].xxxx, IMM[3].wwww 415: UARL ADDR[0].x, TEMP[15].xxxx 416: MOV TEMP[13].z, CONST[ADDR[0].x+4].xxxx 417: UADD TEMP[16].x, TEMP[5].xxxx, IMM[3].zzzz 418: UARL ADDR[0].x, TEMP[16].xxxx 419: MOV TEMP[17].x, CONST[ADDR[0].x+4].xxxx 420: ADD TEMP[18].xyz, TEMP[7].xyzz, -TEMP[6].xyzz 421: DP3 TEMP[19].x, TEMP[18].xyzz, TEMP[18].xyzz 422: RSQ TEMP[20].x, TEMP[19].xxxx 423: MUL TEMP[20].x, TEMP[20].xxxx, TEMP[19].xxxx 424: CMP TEMP[21].x, -TEMP[19].xxxx, TEMP[20].xxxx, IMM[4].xxxx 425: RCP TEMP[22].x, TEMP[21].xxxx 426: MUL TEMP[23].xyz, TEMP[18].xyzz, TEMP[22].xxxx 427: DP3 TEMP[24].x, TEMP[1].xyzz, TEMP[23].xyzz 428: MAX TEMP[25].x, IMM[4].xxxx, TEMP[24].xxxx 429: MUL TEMP[26].xyz, TEMP[25].xxxx, TEMP[13].xyzz 430: MUL TEMP[27].xyz, TEMP[26].xyzz, TEMP[2].xyzz 431: DP3 TEMP[28].x, TEMP[8].xyzz, TEMP[23].xyzz 432: MAX TEMP[29].x, IMM[4].wwww, TEMP[28].xxxx 433: POW TEMP[30].x, TEMP[29].xxxx, TEMP[3].wwww 434: MUL TEMP[31].xyz, TEMP[30].xxxx, TEMP[13].xyzz 435: MAD TEMP[27].xyz, TEMP[31].xyzz, TEMP[3].xyzz, TEMP[27].xyzz 436: MUL TEMP[32].x, TEMP[17].xxxx, IMM[5].zzzz 437: ADD TEMP[33].x, TEMP[21].xxxx, -TEMP[32].xxxx 438: ADD TEMP[34].x, TEMP[17].xxxx, -TEMP[32].xxxx 439: RCP TEMP[35].x, TEMP[34].xxxx 440: MUL_SAT TEMP[36].x, TEMP[33].xxxx, TEMP[35].xxxx 441: MUL TEMP[37].x, IMM[5].xxxx, TEMP[36].xxxx 442: ADD TEMP[38].x, IMM[5].wwww, -TEMP[37].xxxx 443: MUL TEMP[39].x, TEMP[36].xxxx, TEMP[38].xxxx 444: MUL TEMP[40].x, TEMP[36].xxxx, TEMP[39].xxxx 445: ADD TEMP[41].x, IMM[4].yyyy, -TEMP[40].xxxx 446: MUL TEMP[27].xyz, TEMP[27].xyzz, TEMP[41].xxxx 447: ADD TEMP[9].xyz, TEMP[9].xyzz, TEMP[27].xyzz 448: UADD TEMP[0].x, TEMP[0].xxxx, IMM[11].wwww 449: ENDLOOP :0 450: MOV TEMP[0].xyz, TEMP[9].xyzx 451: MOV OUT[0], TEMP[0] 452: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %22 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0 %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0 %24 = call float @llvm.SI.load.const(<16 x i8> %23, i32 48) %25 = call float @llvm.SI.load.const(<16 x i8> %23, i32 1280) %26 = call float @llvm.SI.load.const(<16 x i8> %23, i32 1284) %27 = call float @llvm.SI.load.const(<16 x i8> %23, i32 1288) %28 = call float @llvm.SI.load.const(<16 x i8> %23, i32 1292) %29 = call float @llvm.SI.load.const(<16 x i8> %23, i32 1296) %30 = call float @llvm.SI.load.const(<16 x i8> %23, i32 1312) %31 = call float @llvm.SI.load.const(<16 x i8> %23, i32 1328) %32 = call float @llvm.SI.load.const(<16 x i8> %23, i32 1344) %33 = call float @llvm.SI.load.const(<16 x i8> %23, i32 1360) %34 = call float @llvm.SI.load.const(<16 x i8> %23, i32 1376) %35 = call float @llvm.SI.load.const(<16 x i8> %23, i32 1392) %36 = call float @llvm.SI.load.const(<16 x i8> %23, i32 1408) %37 = call float @llvm.SI.load.const(<16 x i8> %23, i32 1440) %38 = call float @llvm.SI.load.const(<16 x i8> %23, i32 1444) %39 = call float @llvm.SI.load.const(<16 x i8> %23, i32 1448) %40 = call float @llvm.SI.load.const(<16 x i8> %23, i32 1456) %41 = call float @llvm.SI.load.const(<16 x i8> %23, i32 1460) %42 = call float @llvm.SI.load.const(<16 x i8> %23, i32 1464) %43 = call float @llvm.SI.load.const(<16 x i8> %23, i32 1472) %44 = call float @llvm.SI.load.const(<16 x i8> %23, i32 1476) %45 = call float @llvm.SI.load.const(<16 x i8> %23, i32 1480) %46 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 1 %47 = load <16 x i8> addrspace(2)* %46, !tbaa !0 %48 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 2 %49 = load <16 x i8> addrspace(2)* %48, !tbaa !0 %50 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0 %51 = load <32 x i8> addrspace(2)* %50, !tbaa !0 %52 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0 %53 = load <16 x i8> addrspace(2)* %52, !tbaa !0 %54 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 1 %55 = load <32 x i8> addrspace(2)* %54, !tbaa !0 %56 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 1 %57 = load <16 x i8> addrspace(2)* %56, !tbaa !0 %58 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 2 %59 = load <32 x i8> addrspace(2)* %58, !tbaa !0 %60 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 2 %61 = load <16 x i8> addrspace(2)* %60, !tbaa !0 %62 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 3 %63 = load <32 x i8> addrspace(2)* %62, !tbaa !0 %64 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 3 %65 = load <16 x i8> addrspace(2)* %64, !tbaa !0 %66 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 4 %67 = load <32 x i8> addrspace(2)* %66, !tbaa !0 %68 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 4 %69 = load <16 x i8> addrspace(2)* %68, !tbaa !0 %70 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 5 %71 = load <32 x i8> addrspace(2)* %70, !tbaa !0 %72 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 5 %73 = load <16 x i8> addrspace(2)* %72, !tbaa !0 %74 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 6 %75 = load <32 x i8> addrspace(2)* %74, !tbaa !0 %76 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 6 %77 = load <16 x i8> addrspace(2)* %76, !tbaa !0 %78 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 7 %79 = load <32 x i8> addrspace(2)* %78, !tbaa !0 %80 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 7 %81 = load <16 x i8> addrspace(2)* %80, !tbaa !0 %82 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %7) %83 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %7) %84 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %5, <2 x i32> %7) %85 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %5, <2 x i32> %7) %86 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %5, <2 x i32> %7) %87 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %5, <2 x i32> %7) %88 = call float @llvm.SI.fs.interp(i32 2, i32 1, i32 %5, <2 x i32> %7) %89 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %5, <2 x i32> %7) %90 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %5, <2 x i32> %7) %91 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %5, <2 x i32> %7) %92 = call float @llvm.SI.fs.interp(i32 2, i32 2, i32 %5, <2 x i32> %7) %93 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %5, <2 x i32> %7) %94 = shl i32 14, 4 %95 = call float @llvm.SI.load.const(<16 x i8> %47, i32 %94) %96 = shl i32 14, 4 %97 = add i32 %96, 4 %98 = call float @llvm.SI.load.const(<16 x i8> %47, i32 %97) %99 = shl i32 14, 4 %100 = add i32 %99, 8 %101 = call float @llvm.SI.load.const(<16 x i8> %47, i32 %100) %102 = shl i32 13, 4 %103 = call float @llvm.SI.load.const(<16 x i8> %47, i32 %102) %104 = shl i32 13, 4 %105 = add i32 %104, 4 %106 = call float @llvm.SI.load.const(<16 x i8> %47, i32 %105) %107 = shl i32 13, 4 %108 = add i32 %107, 8 %109 = call float @llvm.SI.load.const(<16 x i8> %47, i32 %108) %110 = shl i32 12, 4 %111 = call float @llvm.SI.load.const(<16 x i8> %47, i32 %110) %112 = shl i32 12, 4 %113 = add i32 %112, 4 %114 = call float @llvm.SI.load.const(<16 x i8> %47, i32 %113) %115 = shl i32 12, 4 %116 = add i32 %115, 8 %117 = call float @llvm.SI.load.const(<16 x i8> %47, i32 %116) %118 = fmul float %111, %85 %119 = fmul float %114, %85 %120 = fmul float %117, %85 %121 = fmul float %103, %86 %122 = fadd float %121, %118 %123 = fmul float %106, %86 %124 = fadd float %123, %119 %125 = fmul float %109, %86 %126 = fadd float %125, %120 %127 = fmul float %95, %87 %128 = fadd float %127, %122 %129 = fmul float %98, %87 %130 = fadd float %129, %124 %131 = fmul float %101, %87 %132 = fadd float %131, %126 %133 = shl i32 15, 4 %134 = call float @llvm.SI.load.const(<16 x i8> %47, i32 %133) %135 = shl i32 15, 4 %136 = add i32 %135, 4 %137 = call float @llvm.SI.load.const(<16 x i8> %47, i32 %136) %138 = shl i32 15, 4 %139 = add i32 %138, 8 %140 = call float @llvm.SI.load.const(<16 x i8> %47, i32 %139) %141 = fadd float %128, %134 %142 = fadd float %130, %137 %143 = fadd float %132, %140 %144 = shl i32 20, 4 %145 = call float @llvm.SI.load.const(<16 x i8> %47, i32 %144) %146 = shl i32 20, 4 %147 = add i32 %146, 4 %148 = call float @llvm.SI.load.const(<16 x i8> %47, i32 %147) %149 = shl i32 20, 4 %150 = add i32 %149, 8 %151 = call float @llvm.SI.load.const(<16 x i8> %47, i32 %150) %152 = fsub float -0.000000e+00, %145 %153 = fadd float %141, %152 %154 = fsub float -0.000000e+00, %148 %155 = fadd float %142, %154 %156 = fsub float -0.000000e+00, %151 %157 = fadd float %143, %156 %158 = fmul float %153, %153 %159 = fmul float %155, %155 %160 = fadd float %159, %158 %161 = fmul float %157, %157 %162 = fadd float %160, %161 %163 = call float @llvm.AMDGPU.rsq(float %162) %164 = fmul float %163, %162 %165 = fsub float -0.000000e+00, %162 %166 = call float @llvm.AMDGPU.cndlt(float %165, float %164, float 0.000000e+00) %167 = fdiv float 1.000000e+00, %33 %168 = fmul float %166, %167 %169 = fadd float %168, 1.000000e+00 %170 = call float @llvm.log2.f32(float %169) %171 = fmul float %170, 0x3FE62E4300000000 %172 = call float @llvm.log2.f32(float %34) %173 = fmul float %172, 0x3FE62E4300000000 %174 = fdiv float 1.000000e+00, %173 %175 = fmul float %171, %174 %176 = call float @floor(float %175) %177 = call float @llvm.AMDIL.exp.(float %176) %178 = call float @llvm.AMDIL.fraction.(float %175) %179 = call float @fabs(float %91) %180 = call float @fabs(float %92) %181 = call float @fabs(float %93) %182 = fadd float %179, 0x3F50624DE0000000 %183 = fadd float %180, 0x3F50624DE0000000 %184 = fadd float %181, 0x3F50624DE0000000 %185 = call float @llvm.pow.f32(float %182, float %32) %186 = call float @llvm.pow.f32(float %183, float %32) %187 = call float @llvm.pow.f32(float %184, float %32) %188 = fadd float %185, %186 %189 = fadd float %188, %187 %190 = fdiv float 1.000000e+00, %189 %191 = fmul float %185, %190 %192 = fmul float %186, %190 %193 = fmul float %187, %190 %194 = fmul float %31, %177 %195 = fdiv float 1.000000e+00, %194 %196 = fmul float %90, %195 %197 = fmul float %89, %195 %198 = bitcast float %196 to i32 %199 = bitcast float %197 to i32 %200 = insertelement <2 x i32> undef, i32 %198, i32 0 %201 = insertelement <2 x i32> %200, i32 %199, i32 1 %202 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %201, <32 x i8> %67, <16 x i8> %69, i32 2) %203 = extractelement <4 x float> %202, i32 0 %204 = extractelement <4 x float> %202, i32 1 %205 = extractelement <4 x float> %202, i32 2 %206 = fmul float %30, %177 %207 = fdiv float 1.000000e+00, %206 %208 = fmul float %88, %207 %209 = fmul float %90, %207 %210 = bitcast float %208 to i32 %211 = bitcast float %209 to i32 %212 = insertelement <2 x i32> undef, i32 %210, i32 0 %213 = insertelement <2 x i32> %212, i32 %211, i32 1 %214 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %213, <32 x i8> %63, <16 x i8> %65, i32 2) %215 = extractelement <4 x float> %214, i32 0 %216 = extractelement <4 x float> %214, i32 1 %217 = extractelement <4 x float> %214, i32 2 %218 = fmul float %29, %177 %219 = fdiv float 1.000000e+00, %218 %220 = fmul float %88, %219 %221 = fmul float %89, %219 %222 = bitcast float %220 to i32 %223 = bitcast float %221 to i32 %224 = insertelement <2 x i32> undef, i32 %222, i32 0 %225 = insertelement <2 x i32> %224, i32 %223, i32 1 %226 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %225, <32 x i8> %59, <16 x i8> %61, i32 2) %227 = extractelement <4 x float> %226, i32 0 %228 = extractelement <4 x float> %226, i32 1 %229 = extractelement <4 x float> %226, i32 2 %230 = fmul float %227, %193 %231 = fmul float %228, %193 %232 = fmul float %229, %193 %233 = fmul float %215, %192 %234 = fadd float %233, %230 %235 = fmul float %216, %192 %236 = fadd float %235, %231 %237 = fmul float %217, %192 %238 = fadd float %237, %232 %239 = fmul float %203, %191 %240 = fadd float %239, %234 %241 = fmul float %204, %191 %242 = fadd float %241, %236 %243 = fmul float %205, %191 %244 = fadd float %243, %238 %245 = fmul float %29, %177 %246 = fdiv float 1.000000e+00, %245 %247 = fmul float %88, %246 %248 = fmul float %89, %246 %249 = bitcast float %247 to i32 %250 = bitcast float %248 to i32 %251 = insertelement <2 x i32> undef, i32 %249, i32 0 %252 = insertelement <2 x i32> %251, i32 %250, i32 1 %253 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %252, <32 x i8> %71, <16 x i8> %73, i32 2) %254 = extractelement <4 x float> %253, i32 0 %255 = extractelement <4 x float> %253, i32 1 %256 = extractelement <4 x float> %253, i32 2 %257 = fmul float %254, 2.000000e+00 %258 = fadd float %257, 0xBFF0100000000000 %259 = fmul float %255, 2.000000e+00 %260 = fadd float %259, 0xBFF0100000000000 %261 = fmul float %30, %177 %262 = fdiv float 1.000000e+00, %261 %263 = fmul float %88, %262 %264 = fmul float %90, %262 %265 = bitcast float %263 to i32 %266 = bitcast float %264 to i32 %267 = insertelement <2 x i32> undef, i32 %265, i32 0 %268 = insertelement <2 x i32> %267, i32 %266, i32 1 %269 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %268, <32 x i8> %75, <16 x i8> %77, i32 2) %270 = extractelement <4 x float> %269, i32 0 %271 = extractelement <4 x float> %269, i32 1 %272 = extractelement <4 x float> %269, i32 2 %273 = fmul float %270, 2.000000e+00 %274 = fadd float %273, 0xBFF0100000000000 %275 = fmul float %271, 2.000000e+00 %276 = fadd float %275, 0xBFF0100000000000 %277 = fmul float %31, %177 %278 = fdiv float 1.000000e+00, %277 %279 = fmul float %90, %278 %280 = fmul float %89, %278 %281 = bitcast float %279 to i32 %282 = bitcast float %280 to i32 %283 = insertelement <2 x i32> undef, i32 %281, i32 0 %284 = insertelement <2 x i32> %283, i32 %282, i32 1 %285 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %284, <32 x i8> %79, <16 x i8> %81, i32 2) %286 = extractelement <4 x float> %285, i32 0 %287 = extractelement <4 x float> %285, i32 1 %288 = extractelement <4 x float> %285, i32 2 %289 = fmul float %286, 2.000000e+00 %290 = fadd float %289, 0xBFF0100000000000 %291 = fmul float %287, 2.000000e+00 %292 = fadd float %291, 0xBFF0100000000000 %293 = fadd float %179, %180 %294 = fadd float %293, %181 %295 = fdiv float 1.000000e+00, %294 %296 = fmul float %179, %295 %297 = fmul float %180, %295 %298 = fmul float %181, %295 %299 = fcmp ugt float %91, 0.000000e+00 %300 = select i1 %299, float 1.000000e+00, float %91 %301 = fcmp uge float %300, 0.000000e+00 %302 = select i1 %301, float %300, float -1.000000e+00 %303 = fmul float %288, %302 %304 = fmul float %292, %302 %305 = fmul float %290, %302 %306 = fcmp ugt float %92, 0.000000e+00 %307 = select i1 %306, float 1.000000e+00, float %92 %308 = fcmp uge float %307, 0.000000e+00 %309 = select i1 %308, float %307, float -1.000000e+00 %310 = fmul float %274, %309 %311 = fmul float %272, %309 %312 = fmul float %276, %309 %313 = fcmp ugt float %93, 0.000000e+00 %314 = select i1 %313, float 1.000000e+00, float %93 %315 = fcmp uge float %314, 0.000000e+00 %316 = select i1 %315, float %314, float -1.000000e+00 %317 = fmul float %258, %316 %318 = fmul float %260, %316 %319 = fmul float %256, %316 %320 = fmul float %317, %298 %321 = fmul float %318, %298 %322 = fmul float %319, %298 %323 = fmul float %310, %297 %324 = fadd float %323, %320 %325 = fmul float %311, %297 %326 = fadd float %325, %321 %327 = fmul float %312, %297 %328 = fadd float %327, %322 %329 = fmul float %303, %296 %330 = fadd float %329, %324 %331 = fmul float %304, %296 %332 = fadd float %331, %326 %333 = fmul float %305, %296 %334 = fadd float %333, %328 %335 = fcmp olt float %178, %35 %336 = sext i1 %335 to i32 %337 = bitcast i32 %336 to float %338 = bitcast float %337 to i32 %339 = icmp ne i32 %338, 0 br i1 %339, label %IF, label %ENDIF IF: ; preds = %main_body %340 = fmul float %177, 5.000000e-01 %341 = call float @fabs(float %91) %342 = call float @fabs(float %92) %343 = call float @fabs(float %93) %344 = fadd float %341, 0x3F50624DE0000000 %345 = fadd float %342, 0x3F50624DE0000000 %346 = fadd float %343, 0x3F50624DE0000000 %347 = call float @llvm.pow.f32(float %344, float %32) %348 = call float @llvm.pow.f32(float %345, float %32) %349 = call float @llvm.pow.f32(float %346, float %32) %350 = fadd float %347, %348 %351 = fadd float %350, %349 %352 = fdiv float 1.000000e+00, %351 %353 = fmul float %347, %352 %354 = fmul float %348, %352 %355 = fmul float %349, %352 %356 = fmul float %29, %340 %357 = fdiv float 1.000000e+00, %356 %358 = fmul float %88, %357 %359 = fmul float %89, %357 %360 = bitcast float %358 to i32 %361 = bitcast float %359 to i32 %362 = insertelement <2 x i32> undef, i32 %360, i32 0 %363 = insertelement <2 x i32> %362, i32 %361, i32 1 %364 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %363, <32 x i8> %71, <16 x i8> %73, i32 2) %365 = extractelement <4 x float> %364, i32 0 %366 = extractelement <4 x float> %364, i32 1 %367 = extractelement <4 x float> %364, i32 2 %368 = fmul float %365, 2.000000e+00 %369 = fadd float %368, 0xBFF0100000000000 %370 = fmul float %366, 2.000000e+00 %371 = fadd float %370, 0xBFF0100000000000 %372 = fmul float %30, %340 %373 = fdiv float 1.000000e+00, %372 %374 = fmul float %88, %373 %375 = fmul float %90, %373 %376 = bitcast float %374 to i32 %377 = bitcast float %375 to i32 %378 = insertelement <2 x i32> undef, i32 %376, i32 0 %379 = insertelement <2 x i32> %378, i32 %377, i32 1 %380 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %379, <32 x i8> %75, <16 x i8> %77, i32 2) %381 = extractelement <4 x float> %380, i32 0 %382 = extractelement <4 x float> %380, i32 1 %383 = extractelement <4 x float> %380, i32 2 %384 = fmul float %381, 2.000000e+00 %385 = fadd float %384, 0xBFF0100000000000 %386 = fmul float %382, 2.000000e+00 %387 = fadd float %386, 0xBFF0100000000000 %388 = fmul float %31, %340 %389 = fdiv float 1.000000e+00, %388 %390 = fmul float %90, %389 %391 = fmul float %89, %389 %392 = bitcast float %390 to i32 %393 = bitcast float %391 to i32 %394 = insertelement <2 x i32> undef, i32 %392, i32 0 %395 = insertelement <2 x i32> %394, i32 %393, i32 1 %396 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %395, <32 x i8> %79, <16 x i8> %81, i32 2) %397 = extractelement <4 x float> %396, i32 0 %398 = extractelement <4 x float> %396, i32 1 %399 = extractelement <4 x float> %396, i32 2 %400 = fmul float %397, 2.000000e+00 %401 = fadd float %400, 0xBFF0100000000000 %402 = fmul float %398, 2.000000e+00 %403 = fadd float %402, 0xBFF0100000000000 %404 = fadd float %341, %342 %405 = fadd float %404, %343 %406 = fdiv float 1.000000e+00, %405 %407 = fmul float %341, %406 %408 = fmul float %342, %406 %409 = fmul float %343, %406 %410 = fdiv float 1.000000e+00, %35 %411 = fmul float %178, %410 %412 = call float @llvm.AMDIL.clamp.(float %411, float 0.000000e+00, float 1.000000e+00) %413 = fmul float 2.000000e+00, %412 %414 = fsub float -0.000000e+00, %413 %415 = fadd float 3.000000e+00, %414 %416 = fmul float %412, %415 %417 = fmul float %412, %416 %418 = fmul float %31, %340 %419 = fdiv float 1.000000e+00, %418 %420 = fmul float %90, %419 %421 = fmul float %89, %419 %422 = bitcast float %420 to i32 %423 = bitcast float %421 to i32 %424 = insertelement <2 x i32> undef, i32 %422, i32 0 %425 = insertelement <2 x i32> %424, i32 %423, i32 1 %426 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %425, <32 x i8> %67, <16 x i8> %69, i32 2) %427 = extractelement <4 x float> %426, i32 0 %428 = extractelement <4 x float> %426, i32 1 %429 = extractelement <4 x float> %426, i32 2 %430 = fmul float %30, %340 %431 = fdiv float 1.000000e+00, %430 %432 = fmul float %88, %431 %433 = fmul float %90, %431 %434 = bitcast float %432 to i32 %435 = bitcast float %433 to i32 %436 = insertelement <2 x i32> undef, i32 %434, i32 0 %437 = insertelement <2 x i32> %436, i32 %435, i32 1 %438 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %437, <32 x i8> %63, <16 x i8> %65, i32 2) %439 = extractelement <4 x float> %438, i32 0 %440 = extractelement <4 x float> %438, i32 1 %441 = extractelement <4 x float> %438, i32 2 %442 = extractelement <4 x float> %438, i32 3 %443 = fmul float %29, %340 %444 = fdiv float 1.000000e+00, %443 %445 = fmul float %88, %444 %446 = fmul float %89, %444 %447 = bitcast float %445 to i32 %448 = bitcast float %446 to i32 %449 = insertelement <2 x i32> undef, i32 %447, i32 0 %450 = insertelement <2 x i32> %449, i32 %448, i32 1 %451 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %450, <32 x i8> %59, <16 x i8> %61, i32 2) %452 = extractelement <4 x float> %451, i32 0 %453 = extractelement <4 x float> %451, i32 1 %454 = extractelement <4 x float> %451, i32 2 %455 = fmul float %452, %355 %456 = fmul float %453, %355 %457 = fmul float %454, %355 %458 = fmul float %439, %354 %459 = fadd float %458, %455 %460 = fmul float %440, %354 %461 = fadd float %460, %456 %462 = fmul float %441, %354 %463 = fadd float %462, %457 %464 = fmul float %427, %353 %465 = fadd float %464, %459 %466 = fmul float %428, %353 %467 = fadd float %466, %461 %468 = fmul float %429, %353 %469 = fadd float %468, %463 %470 = call float @llvm.AMDGPU.lrp(float %417, float %240, float %465) %471 = call float @llvm.AMDGPU.lrp(float %417, float %242, float %467) %472 = call float @llvm.AMDGPU.lrp(float %417, float %244, float %469) %473 = fcmp ugt float %91, 0.000000e+00 %474 = select i1 %473, float 1.000000e+00, float %91 %475 = fcmp uge float %474, 0.000000e+00 %476 = select i1 %475, float %474, float -1.000000e+00 %477 = fmul float %399, %476 %478 = fmul float %403, %476 %479 = fmul float %401, %476 %480 = fcmp ugt float %92, 0.000000e+00 %481 = select i1 %480, float 1.000000e+00, float %92 %482 = fcmp uge float %481, 0.000000e+00 %483 = select i1 %482, float %481, float -1.000000e+00 %484 = fmul float %385, %483 %485 = fmul float %383, %483 %486 = fmul float %387, %483 %487 = fcmp ugt float %93, 0.000000e+00 %488 = select i1 %487, float 1.000000e+00, float %93 %489 = fcmp uge float %488, 0.000000e+00 %490 = select i1 %489, float %488, float -1.000000e+00 %491 = fmul float %369, %490 %492 = fmul float %371, %490 %493 = fmul float %367, %490 %494 = fmul float %491, %409 %495 = fmul float %492, %409 %496 = fmul float %493, %409 %497 = fmul float %484, %408 %498 = fadd float %497, %494 %499 = fmul float %485, %408 %500 = fadd float %499, %495 %501 = fmul float %486, %408 %502 = fadd float %501, %496 %503 = fmul float %477, %407 %504 = fadd float %503, %498 %505 = fmul float %478, %407 %506 = fadd float %505, %500 %507 = fmul float %479, %407 %508 = fadd float %507, %502 %509 = call float @llvm.AMDGPU.lrp(float %417, float %330, float %504) %510 = call float @llvm.AMDGPU.lrp(float %417, float %332, float %506) %511 = call float @llvm.AMDGPU.lrp(float %417, float %334, float %508) br label %ENDIF ENDIF: ; preds = %main_body, %IF %temp26.0 = phi float [ %511, %IF ], [ %334, %main_body ] %temp25.0 = phi float [ %510, %IF ], [ %332, %main_body ] %temp24.0 = phi float [ %509, %IF ], [ %330, %main_body ] %temp22.0 = phi float [ %472, %IF ], [ %244, %main_body ] %temp21.0 = phi float [ %471, %IF ], [ %242, %main_body ] %temp20.0 = phi float [ %470, %IF ], [ %240, %main_body ] %temp3.0 = phi float [ %442, %IF ], [ 0.000000e+00, %main_body ] %512 = fcmp olt float 5.000000e-01, %36 %513 = sext i1 %512 to i32 %514 = bitcast i32 %513 to float %515 = bitcast float %514 to i32 %516 = icmp ne i32 %515, 0 br i1 %516, label %IF187, label %ENDIF186 IF187: ; preds = %ENDIF %517 = fmul float %temp20.0, %82 %518 = fmul float %temp21.0, %83 %519 = fmul float %temp22.0, %84 br label %ENDIF186 ENDIF186: ; preds = %ENDIF, %IF187 %temp22.1 = phi float [ %519, %IF187 ], [ %temp22.0, %ENDIF ] %temp21.1 = phi float [ %518, %IF187 ], [ %temp21.0, %ENDIF ] %temp20.1 = phi float [ %517, %IF187 ], [ %temp20.0, %ENDIF ] %520 = fmul float %37, %temp24.0 %521 = fmul float %38, %temp24.0 %522 = fmul float %39, %temp24.0 %523 = fmul float %40, %temp25.0 %524 = fadd float %523, %520 %525 = fmul float %41, %temp25.0 %526 = fadd float %525, %521 %527 = fmul float %42, %temp25.0 %528 = fadd float %527, %522 %529 = fmul float %43, %temp26.0 %530 = fadd float %529, %524 %531 = fmul float %44, %temp26.0 %532 = fadd float %531, %526 %533 = fmul float %45, %temp26.0 %534 = fadd float %533, %528 %535 = fmul float %530, %530 %536 = fmul float %532, %532 %537 = fadd float %536, %535 %538 = fmul float %534, %534 %539 = fadd float %537, %538 %540 = call float @llvm.AMDGPU.rsq(float %539) %541 = fmul float %530, %540 %542 = fmul float %532, %540 %543 = fmul float %534, %540 %544 = shl i32 14, 4 %545 = call float @llvm.SI.load.const(<16 x i8> %47, i32 %544) %546 = shl i32 14, 4 %547 = add i32 %546, 4 %548 = call float @llvm.SI.load.const(<16 x i8> %47, i32 %547) %549 = shl i32 14, 4 %550 = add i32 %549, 8 %551 = call float @llvm.SI.load.const(<16 x i8> %47, i32 %550) %552 = shl i32 13, 4 %553 = call float @llvm.SI.load.const(<16 x i8> %47, i32 %552) %554 = shl i32 13, 4 %555 = add i32 %554, 4 %556 = call float @llvm.SI.load.const(<16 x i8> %47, i32 %555) %557 = shl i32 13, 4 %558 = add i32 %557, 8 %559 = call float @llvm.SI.load.const(<16 x i8> %47, i32 %558) %560 = shl i32 12, 4 %561 = call float @llvm.SI.load.const(<16 x i8> %47, i32 %560) %562 = shl i32 12, 4 %563 = add i32 %562, 4 %564 = call float @llvm.SI.load.const(<16 x i8> %47, i32 %563) %565 = shl i32 12, 4 %566 = add i32 %565, 8 %567 = call float @llvm.SI.load.const(<16 x i8> %47, i32 %566) %568 = fmul float %561, %85 %569 = fmul float %564, %85 %570 = fmul float %567, %85 %571 = fmul float %553, %86 %572 = fadd float %571, %568 %573 = fmul float %556, %86 %574 = fadd float %573, %569 %575 = fmul float %559, %86 %576 = fadd float %575, %570 %577 = fmul float %545, %87 %578 = fadd float %577, %572 %579 = fmul float %548, %87 %580 = fadd float %579, %574 %581 = fmul float %551, %87 %582 = fadd float %581, %576 %583 = shl i32 15, 4 %584 = call float @llvm.SI.load.const(<16 x i8> %47, i32 %583) %585 = shl i32 15, 4 %586 = add i32 %585, 4 %587 = call float @llvm.SI.load.const(<16 x i8> %47, i32 %586) %588 = shl i32 15, 4 %589 = add i32 %588, 8 %590 = call float @llvm.SI.load.const(<16 x i8> %47, i32 %589) %591 = fadd float %578, %584 %592 = fadd float %580, %587 %593 = fadd float %582, %590 %594 = shl i32 20, 4 %595 = call float @llvm.SI.load.const(<16 x i8> %47, i32 %594) %596 = shl i32 20, 4 %597 = add i32 %596, 4 %598 = call float @llvm.SI.load.const(<16 x i8> %47, i32 %597) %599 = shl i32 20, 4 %600 = add i32 %599, 8 %601 = call float @llvm.SI.load.const(<16 x i8> %47, i32 %600) %602 = fsub float -0.000000e+00, %595 %603 = fadd float %591, %602 %604 = fsub float -0.000000e+00, %598 %605 = fadd float %592, %604 %606 = fsub float -0.000000e+00, %601 %607 = fadd float %593, %606 %608 = fmul float %603, %603 %609 = fmul float %605, %605 %610 = fadd float %609, %608 %611 = fmul float %607, %607 %612 = fadd float %610, %611 %613 = call float @llvm.AMDGPU.rsq(float %612) %614 = fmul float %603, %613 %615 = fmul float %605, %613 %616 = fmul float %607, %613 %617 = fmul float %541, %614 %618 = fmul float %542, %615 %619 = fadd float %618, %617 %620 = fmul float %543, %616 %621 = fadd float %619, %620 %622 = fmul float %621, %541 %623 = fmul float %621, %542 %624 = fmul float %621, %543 %625 = fmul float 2.000000e+00, %622 %626 = fmul float 2.000000e+00, %623 %627 = fmul float 2.000000e+00, %624 %628 = fsub float -0.000000e+00, %625 %629 = fadd float %614, %628 %630 = fsub float -0.000000e+00, %626 %631 = fadd float %615, %630 %632 = fsub float -0.000000e+00, %627 %633 = fadd float %616, %632 %634 = fadd float %542, 0x3FF0CCCCC0000000 %635 = call float @llvm.AMDIL.clamp.(float %634, float 0.000000e+00, float 1.000000e+00) %636 = shl i32 14, 4 %637 = call float @llvm.SI.load.const(<16 x i8> %49, i32 %636) %638 = shl i32 14, 4 %639 = add i32 %638, 4 %640 = call float @llvm.SI.load.const(<16 x i8> %49, i32 %639) %641 = shl i32 14, 4 %642 = add i32 %641, 8 %643 = call float @llvm.SI.load.const(<16 x i8> %49, i32 %642) %644 = fmul float %635, %637 %645 = fmul float %635, %640 %646 = fmul float %635, %643 %647 = fmul float %temp20.1, %644 %648 = fmul float %temp21.1, %645 %649 = fmul float %temp22.1, %646 %650 = shl i32 12, 4 %651 = call float @llvm.SI.load.const(<16 x i8> %49, i32 %650) %652 = shl i32 12, 4 %653 = add i32 %652, 4 %654 = call float @llvm.SI.load.const(<16 x i8> %49, i32 %653) %655 = shl i32 12, 4 %656 = add i32 %655, 8 %657 = call float @llvm.SI.load.const(<16 x i8> %49, i32 %656) %658 = shl i32 13, 4 %659 = call float @llvm.SI.load.const(<16 x i8> %49, i32 %658) %660 = shl i32 13, 4 %661 = add i32 %660, 4 %662 = call float @llvm.SI.load.const(<16 x i8> %49, i32 %661) %663 = shl i32 13, 4 %664 = add i32 %663, 8 %665 = call float @llvm.SI.load.const(<16 x i8> %49, i32 %664) %666 = fmul float %541, %651 %667 = fmul float %542, %654 %668 = fadd float %667, %666 %669 = fmul float %543, %657 %670 = fadd float %668, %669 %671 = fcmp uge float 0.000000e+00, %670 %672 = select i1 %671, float 0.000000e+00, float %670 %673 = fmul float %672, %659 %674 = fmul float %672, %662 %675 = fmul float %672, %665 %676 = fmul float %673, %temp20.1 %677 = fmul float %674, %temp21.1 %678 = fmul float %675, %temp22.1 %679 = fmul float %629, %651 %680 = fmul float %631, %654 %681 = fadd float %680, %679 %682 = fmul float %633, %657 %683 = fadd float %681, %682 %684 = fcmp uge float 0x3F50624DE0000000, %683 %685 = select i1 %684, float 0x3F50624DE0000000, float %683 %686 = call float @llvm.pow.f32(float %685, float %28) %687 = fmul float %686, %659 %688 = fmul float %686, %662 %689 = fmul float %686, %665 %690 = fmul float %687, %25 %691 = fadd float %690, %676 %692 = fmul float %688, %26 %693 = fadd float %692, %677 %694 = fmul float %689, %27 %695 = fadd float %694, %678 %696 = shl i32 15, 4 %697 = call float @llvm.SI.load.const(<16 x i8> %49, i32 %696) %698 = shl i32 15, 4 %699 = add i32 %698, 4 %700 = call float @llvm.SI.load.const(<16 x i8> %49, i32 %699) %701 = shl i32 15, 4 %702 = add i32 %701, 8 %703 = call float @llvm.SI.load.const(<16 x i8> %49, i32 %702) %704 = fsub float -0.000000e+00, %697 %705 = fadd float %591, %704 %706 = fsub float -0.000000e+00, %700 %707 = fadd float %592, %706 %708 = fsub float -0.000000e+00, %703 %709 = fadd float %593, %708 %710 = fmul float %705, %705 %711 = fmul float %707, %707 %712 = fadd float %711, %710 %713 = fmul float %709, %709 %714 = fadd float %712, %713 %715 = call float @llvm.AMDGPU.rsq(float %714) %716 = fmul float %715, %714 %717 = fsub float -0.000000e+00, %714 %718 = call float @llvm.AMDGPU.cndlt(float %717, float %716, float 0.000000e+00) %719 = shl i32 16, 4 %720 = call float @llvm.SI.load.const(<16 x i8> %49, i32 %719) %721 = fmul float 0x3FE99999A0000000, %720 %722 = fcmp olt float %718, %721 %723 = sext i1 %722 to i32 %724 = bitcast i32 %723 to float %725 = bitcast float %724 to i32 %726 = icmp ne i32 %725, 0 br i1 %726, label %IF222, label %ELSE223 IF222: ; preds = %ENDIF186 %727 = shl i32 6, 4 %728 = call float @llvm.SI.load.const(<16 x i8> %49, i32 %727) %729 = shl i32 6, 4 %730 = add i32 %729, 4 %731 = call float @llvm.SI.load.const(<16 x i8> %49, i32 %730) %732 = shl i32 6, 4 %733 = add i32 %732, 8 %734 = call float @llvm.SI.load.const(<16 x i8> %49, i32 %733) %735 = shl i32 5, 4 %736 = call float @llvm.SI.load.const(<16 x i8> %49, i32 %735) %737 = shl i32 5, 4 %738 = add i32 %737, 4 %739 = call float @llvm.SI.load.const(<16 x i8> %49, i32 %738) %740 = shl i32 5, 4 %741 = add i32 %740, 8 %742 = call float @llvm.SI.load.const(<16 x i8> %49, i32 %741) %743 = shl i32 4, 4 %744 = call float @llvm.SI.load.const(<16 x i8> %49, i32 %743) %745 = shl i32 4, 4 %746 = add i32 %745, 4 %747 = call float @llvm.SI.load.const(<16 x i8> %49, i32 %746) %748 = shl i32 4, 4 %749 = add i32 %748, 8 %750 = call float @llvm.SI.load.const(<16 x i8> %49, i32 %749) %751 = fmul float %744, %591 %752 = fmul float %747, %591 %753 = fmul float %750, %591 %754 = fmul float %736, %592 %755 = fadd float %754, %751 %756 = fmul float %739, %592 %757 = fadd float %756, %752 %758 = fmul float %742, %592 %759 = fadd float %758, %753 %760 = fmul float %728, %593 %761 = fadd float %760, %755 %762 = fmul float %731, %593 %763 = fadd float %762, %757 %764 = fmul float %734, %593 %765 = fadd float %764, %759 %766 = shl i32 7, 4 %767 = call float @llvm.SI.load.const(<16 x i8> %49, i32 %766) %768 = shl i32 7, 4 %769 = add i32 %768, 4 %770 = call float @llvm.SI.load.const(<16 x i8> %49, i32 %769) %771 = shl i32 7, 4 %772 = add i32 %771, 8 %773 = call float @llvm.SI.load.const(<16 x i8> %49, i32 %772) %774 = fadd float %761, %767 %775 = fadd float %763, %770 %776 = fadd float %765, %773 %777 = shl i32 15, 4 %778 = add i32 %777, 12 %779 = call float @llvm.SI.load.const(<16 x i8> %49, i32 %778) %780 = fcmp uge float %776, -1.000000e+00 %781 = select i1 %780, float %776, float -1.000000e+00 %782 = fcmp uge float %781, 1.000000e+00 %783 = select i1 %782, float 1.000000e+00, float %781 %784 = fadd float %783, 1.000000e+00 %785 = fsub float -0.000000e+00, %779 %786 = fmul float %785, %784 %787 = fmul float 0x3FE7154760000000, %786 %788 = call float @llvm.AMDIL.exp.(float %787) %789 = fmul float %774, 5.000000e-01 %790 = fadd float %789, 5.000000e-01 %791 = fmul float %775, 5.000000e-01 %792 = fadd float %791, 5.000000e-01 %793 = shl i32 16, 4 %794 = add i32 %793, 8 %795 = call float @llvm.SI.load.const(<16 x i8> %49, i32 %794) %796 = fmul float %790, %795 %797 = fmul float %792, %795 %798 = bitcast float %796 to i32 %799 = bitcast float %797 to i32 %800 = insertelement <2 x i32> undef, i32 %798, i32 0 %801 = insertelement <2 x i32> %800, i32 %799, i32 1 %802 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %801, <32 x i8> %51, <16 x i8> %53, i32 5) %803 = extractelement <4 x float> %802, i32 0 %804 = fmul float %788, %803 %805 = call float @llvm.AMDIL.clamp.(float %804, float 0.000000e+00, float 1.000000e+00) br label %ENDIF221 ELSE223: ; preds = %ENDIF186 %806 = shl i32 16, 4 %807 = call float @llvm.SI.load.const(<16 x i8> %49, i32 %806) %808 = fcmp olt float %807, %718 %809 = sext i1 %808 to i32 %810 = bitcast i32 %809 to float %811 = bitcast float %810 to i32 %812 = icmp ne i32 %811, 0 br i1 %812, label %IF244, label %ELSE245 ENDIF221: ; preds = %IF244, %ELSE245, %IF222 %temp28.0 = phi float [ %805, %IF222 ], [ %946, %IF244 ], [ %1114, %ELSE245 ] %813 = fadd float %temp28.0, 0xBFE99999A0000000 %814 = fmul float %813, 0x4014000020000000 %815 = call float @llvm.AMDIL.clamp.(float %814, float 0.000000e+00, float 1.000000e+00) %816 = fmul float 2.000000e+00, %815 %817 = fsub float -0.000000e+00, %816 %818 = fadd float 3.000000e+00, %817 %819 = fmul float %815, %818 %820 = fmul float %815, %819 %821 = fmul float %691, %820 %822 = fmul float %693, %820 %823 = fmul float %695, %820 %824 = fadd float %647, %821 %825 = fadd float %648, %822 %826 = fadd float %649, %823 %827 = bitcast float %24 to i32 %828 = fsub float -0.000000e+00, %591 %829 = fsub float -0.000000e+00, %592 %830 = fsub float -0.000000e+00, %593 br label %LOOP IF244: ; preds = %ELSE223 %831 = shl i32 10, 4 %832 = call float @llvm.SI.load.const(<16 x i8> %49, i32 %831) %833 = shl i32 10, 4 %834 = add i32 %833, 4 %835 = call float @llvm.SI.load.const(<16 x i8> %49, i32 %834) %836 = shl i32 10, 4 %837 = add i32 %836, 8 %838 = call float @llvm.SI.load.const(<16 x i8> %49, i32 %837) %839 = shl i32 9, 4 %840 = call float @llvm.SI.load.const(<16 x i8> %49, i32 %839) %841 = shl i32 9, 4 %842 = add i32 %841, 4 %843 = call float @llvm.SI.load.const(<16 x i8> %49, i32 %842) %844 = shl i32 9, 4 %845 = add i32 %844, 8 %846 = call float @llvm.SI.load.const(<16 x i8> %49, i32 %845) %847 = shl i32 8, 4 %848 = call float @llvm.SI.load.const(<16 x i8> %49, i32 %847) %849 = shl i32 8, 4 %850 = add i32 %849, 4 %851 = call float @llvm.SI.load.const(<16 x i8> %49, i32 %850) %852 = shl i32 8, 4 %853 = add i32 %852, 8 %854 = call float @llvm.SI.load.const(<16 x i8> %49, i32 %853) %855 = fmul float %848, %591 %856 = fmul float %851, %591 %857 = fmul float %854, %591 %858 = fmul float %840, %592 %859 = fadd float %858, %855 %860 = fmul float %843, %592 %861 = fadd float %860, %856 %862 = fmul float %846, %592 %863 = fadd float %862, %857 %864 = fmul float %832, %593 %865 = fadd float %864, %859 %866 = fmul float %835, %593 %867 = fadd float %866, %861 %868 = fmul float %838, %593 %869 = fadd float %868, %863 %870 = shl i32 11, 4 %871 = call float @llvm.SI.load.const(<16 x i8> %49, i32 %870) %872 = shl i32 11, 4 %873 = add i32 %872, 4 %874 = call float @llvm.SI.load.const(<16 x i8> %49, i32 %873) %875 = shl i32 11, 4 %876 = add i32 %875, 8 %877 = call float @llvm.SI.load.const(<16 x i8> %49, i32 %876) %878 = fadd float %865, %871 %879 = fadd float %867, %874 %880 = fadd float %869, %877 %881 = shl i32 15, 4 %882 = call float @llvm.SI.load.const(<16 x i8> %49, i32 %881) %883 = shl i32 15, 4 %884 = add i32 %883, 4 %885 = call float @llvm.SI.load.const(<16 x i8> %49, i32 %884) %886 = shl i32 15, 4 %887 = add i32 %886, 8 %888 = call float @llvm.SI.load.const(<16 x i8> %49, i32 %887) %889 = fsub float -0.000000e+00, %882 %890 = fadd float %591, %889 %891 = fsub float -0.000000e+00, %885 %892 = fadd float %592, %891 %893 = fsub float -0.000000e+00, %888 %894 = fadd float %593, %893 %895 = fmul float %890, %890 %896 = fmul float %892, %892 %897 = fadd float %896, %895 %898 = fmul float %894, %894 %899 = fadd float %897, %898 %900 = call float @llvm.AMDGPU.rsq(float %899) %901 = fmul float %900, %899 %902 = fsub float -0.000000e+00, %899 %903 = call float @llvm.AMDGPU.cndlt(float %902, float %901, float 0.000000e+00) %904 = shl i32 16, 4 %905 = add i32 %904, 4 %906 = call float @llvm.SI.load.const(<16 x i8> %49, i32 %905) %907 = fdiv float 1.000000e+00, %906 %908 = fmul float %903, %907 %909 = fadd float %908, 0xBFE99999A0000000 %910 = fmul float %909, 0x4014000020000000 %911 = call float @llvm.AMDIL.clamp.(float %910, float 0.000000e+00, float 1.000000e+00) %912 = shl i32 15, 4 %913 = add i32 %912, 12 %914 = call float @llvm.SI.load.const(<16 x i8> %49, i32 %913) %915 = fcmp uge float %880, -1.000000e+00 %916 = select i1 %915, float %880, float -1.000000e+00 %917 = fcmp uge float %916, 1.000000e+00 %918 = select i1 %917, float 1.000000e+00, float %916 %919 = fadd float %918, 1.000000e+00 %920 = fsub float -0.000000e+00, %914 %921 = fmul float %920, %919 %922 = fmul float 0x3FE7154760000000, %921 %923 = call float @llvm.AMDIL.exp.(float %922) %924 = fmul float %878, 5.000000e-01 %925 = fadd float %924, 5.000000e-01 %926 = fmul float %879, 5.000000e-01 %927 = fadd float %926, 5.000000e-01 %928 = shl i32 16, 4 %929 = add i32 %928, 8 %930 = call float @llvm.SI.load.const(<16 x i8> %49, i32 %929) %931 = fmul float %925, %930 %932 = fmul float %927, %930 %933 = bitcast float %931 to i32 %934 = bitcast float %932 to i32 %935 = insertelement <2 x i32> undef, i32 %933, i32 0 %936 = insertelement <2 x i32> %935, i32 %934, i32 1 %937 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %936, <32 x i8> %55, <16 x i8> %57, i32 5) %938 = extractelement <4 x float> %937, i32 0 %939 = fmul float %923, %938 %940 = call float @llvm.AMDIL.clamp.(float %939, float 0.000000e+00, float 1.000000e+00) %941 = fmul float 2.000000e+00, %911 %942 = fsub float -0.000000e+00, %941 %943 = fadd float 3.000000e+00, %942 %944 = fmul float %911, %943 %945 = fmul float %911, %944 %946 = call float @llvm.AMDGPU.lrp(float %945, float 1.000000e+00, float %940) br label %ENDIF221 ELSE245: ; preds = %ELSE223 %947 = shl i32 6, 4 %948 = call float @llvm.SI.load.const(<16 x i8> %49, i32 %947) %949 = shl i32 6, 4 %950 = add i32 %949, 4 %951 = call float @llvm.SI.load.const(<16 x i8> %49, i32 %950) %952 = shl i32 6, 4 %953 = add i32 %952, 8 %954 = call float @llvm.SI.load.const(<16 x i8> %49, i32 %953) %955 = shl i32 5, 4 %956 = call float @llvm.SI.load.const(<16 x i8> %49, i32 %955) %957 = shl i32 5, 4 %958 = add i32 %957, 4 %959 = call float @llvm.SI.load.const(<16 x i8> %49, i32 %958) %960 = shl i32 5, 4 %961 = add i32 %960, 8 %962 = call float @llvm.SI.load.const(<16 x i8> %49, i32 %961) %963 = shl i32 4, 4 %964 = call float @llvm.SI.load.const(<16 x i8> %49, i32 %963) %965 = shl i32 4, 4 %966 = add i32 %965, 4 %967 = call float @llvm.SI.load.const(<16 x i8> %49, i32 %966) %968 = shl i32 4, 4 %969 = add i32 %968, 8 %970 = call float @llvm.SI.load.const(<16 x i8> %49, i32 %969) %971 = fmul float %964, %591 %972 = fmul float %967, %591 %973 = fmul float %970, %591 %974 = fmul float %956, %592 %975 = fadd float %974, %971 %976 = fmul float %959, %592 %977 = fadd float %976, %972 %978 = fmul float %962, %592 %979 = fadd float %978, %973 %980 = fmul float %948, %593 %981 = fadd float %980, %975 %982 = fmul float %951, %593 %983 = fadd float %982, %977 %984 = fmul float %954, %593 %985 = fadd float %984, %979 %986 = shl i32 7, 4 %987 = call float @llvm.SI.load.const(<16 x i8> %49, i32 %986) %988 = shl i32 7, 4 %989 = add i32 %988, 4 %990 = call float @llvm.SI.load.const(<16 x i8> %49, i32 %989) %991 = shl i32 7, 4 %992 = add i32 %991, 8 %993 = call float @llvm.SI.load.const(<16 x i8> %49, i32 %992) %994 = fadd float %981, %987 %995 = fadd float %983, %990 %996 = fadd float %985, %993 %997 = shl i32 10, 4 %998 = call float @llvm.SI.load.const(<16 x i8> %49, i32 %997) %999 = shl i32 10, 4 %1000 = add i32 %999, 4 %1001 = call float @llvm.SI.load.const(<16 x i8> %49, i32 %1000) %1002 = shl i32 10, 4 %1003 = add i32 %1002, 8 %1004 = call float @llvm.SI.load.const(<16 x i8> %49, i32 %1003) %1005 = shl i32 9, 4 %1006 = call float @llvm.SI.load.const(<16 x i8> %49, i32 %1005) %1007 = shl i32 9, 4 %1008 = add i32 %1007, 4 %1009 = call float @llvm.SI.load.const(<16 x i8> %49, i32 %1008) %1010 = shl i32 9, 4 %1011 = add i32 %1010, 8 %1012 = call float @llvm.SI.load.const(<16 x i8> %49, i32 %1011) %1013 = shl i32 8, 4 %1014 = call float @llvm.SI.load.const(<16 x i8> %49, i32 %1013) %1015 = shl i32 8, 4 %1016 = add i32 %1015, 4 %1017 = call float @llvm.SI.load.const(<16 x i8> %49, i32 %1016) %1018 = shl i32 8, 4 %1019 = add i32 %1018, 8 %1020 = call float @llvm.SI.load.const(<16 x i8> %49, i32 %1019) %1021 = fmul float %1014, %591 %1022 = fmul float %1017, %591 %1023 = fmul float %1020, %591 %1024 = fmul float %1006, %592 %1025 = fadd float %1024, %1021 %1026 = fmul float %1009, %592 %1027 = fadd float %1026, %1022 %1028 = fmul float %1012, %592 %1029 = fadd float %1028, %1023 %1030 = fmul float %998, %593 %1031 = fadd float %1030, %1025 %1032 = fmul float %1001, %593 %1033 = fadd float %1032, %1027 %1034 = fmul float %1004, %593 %1035 = fadd float %1034, %1029 %1036 = shl i32 11, 4 %1037 = call float @llvm.SI.load.const(<16 x i8> %49, i32 %1036) %1038 = shl i32 11, 4 %1039 = add i32 %1038, 4 %1040 = call float @llvm.SI.load.const(<16 x i8> %49, i32 %1039) %1041 = shl i32 11, 4 %1042 = add i32 %1041, 8 %1043 = call float @llvm.SI.load.const(<16 x i8> %49, i32 %1042) %1044 = fadd float %1031, %1037 %1045 = fadd float %1033, %1040 %1046 = fadd float %1035, %1043 %1047 = shl i32 16, 4 %1048 = call float @llvm.SI.load.const(<16 x i8> %49, i32 %1047) %1049 = fmul float 0x3FE99999A0000000, %1048 %1050 = fsub float -0.000000e+00, %1049 %1051 = fadd float %718, %1050 %1052 = fsub float -0.000000e+00, %1049 %1053 = fadd float %1048, %1052 %1054 = fdiv float 1.000000e+00, %1053 %1055 = fmul float %1051, %1054 %1056 = call float @llvm.AMDIL.clamp.(float %1055, float 0.000000e+00, float 1.000000e+00) %1057 = shl i32 15, 4 %1058 = add i32 %1057, 12 %1059 = call float @llvm.SI.load.const(<16 x i8> %49, i32 %1058) %1060 = shl i32 16, 4 %1061 = add i32 %1060, 8 %1062 = call float @llvm.SI.load.const(<16 x i8> %49, i32 %1061) %1063 = fcmp uge float %996, -1.000000e+00 %1064 = select i1 %1063, float %996, float -1.000000e+00 %1065 = fcmp uge float %1064, 1.000000e+00 %1066 = select i1 %1065, float 1.000000e+00, float %1064 %1067 = fadd float %1066, 1.000000e+00 %1068 = fsub float -0.000000e+00, %1059 %1069 = fmul float %1068, %1067 %1070 = fmul float 0x3FE7154760000000, %1069 %1071 = call float @llvm.AMDIL.exp.(float %1070) %1072 = fmul float %994, 5.000000e-01 %1073 = fadd float %1072, 5.000000e-01 %1074 = fmul float %995, 5.000000e-01 %1075 = fadd float %1074, 5.000000e-01 %1076 = fmul float %1073, %1062 %1077 = fmul float %1075, %1062 %1078 = bitcast float %1076 to i32 %1079 = bitcast float %1077 to i32 %1080 = insertelement <2 x i32> undef, i32 %1078, i32 0 %1081 = insertelement <2 x i32> %1080, i32 %1079, i32 1 %1082 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1081, <32 x i8> %51, <16 x i8> %53, i32 5) %1083 = extractelement <4 x float> %1082, i32 0 %1084 = fmul float %1071, %1083 %1085 = call float @llvm.AMDIL.clamp.(float %1084, float 0.000000e+00, float 1.000000e+00) %1086 = fcmp uge float %1046, -1.000000e+00 %1087 = select i1 %1086, float %1046, float -1.000000e+00 %1088 = fcmp uge float %1087, 1.000000e+00 %1089 = select i1 %1088, float 1.000000e+00, float %1087 %1090 = fadd float %1089, 1.000000e+00 %1091 = fsub float -0.000000e+00, %1059 %1092 = fmul float %1091, %1090 %1093 = fmul float 0x3FE7154760000000, %1092 %1094 = call float @llvm.AMDIL.exp.(float %1093) %1095 = fmul float %1044, 5.000000e-01 %1096 = fadd float %1095, 5.000000e-01 %1097 = fmul float %1045, 5.000000e-01 %1098 = fadd float %1097, 5.000000e-01 %1099 = fmul float %1096, %1062 %1100 = fmul float %1098, %1062 %1101 = bitcast float %1099 to i32 %1102 = bitcast float %1100 to i32 %1103 = insertelement <2 x i32> undef, i32 %1101, i32 0 %1104 = insertelement <2 x i32> %1103, i32 %1102, i32 1 %1105 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1104, <32 x i8> %55, <16 x i8> %57, i32 5) %1106 = extractelement <4 x float> %1105, i32 0 %1107 = fmul float %1094, %1106 %1108 = call float @llvm.AMDIL.clamp.(float %1107, float 0.000000e+00, float 1.000000e+00) %1109 = fmul float 2.000000e+00, %1056 %1110 = fsub float -0.000000e+00, %1109 %1111 = fadd float 3.000000e+00, %1110 %1112 = fmul float %1056, %1111 %1113 = fmul float %1056, %1112 %1114 = call float @llvm.AMDGPU.lrp(float %1113, float %1108, float %1085) br label %ENDIF221 LOOP: ; preds = %ENDIF303, %ENDIF221 %temp38.0 = phi float [ %826, %ENDIF221 ], [ %1240, %ENDIF303 ] %temp37.0 = phi float [ %825, %ENDIF221 ], [ %1239, %ENDIF303 ] %temp36.0 = phi float [ %824, %ENDIF221 ], [ %1238, %ENDIF303 ] %temp.0 = phi float [ 0.000000e+00, %ENDIF221 ], [ %1243, %ENDIF303 ] %1115 = bitcast float %temp.0 to i32 %1116 = icmp sge i32 %1115, %827 %1117 = sext i1 %1116 to i32 %1118 = bitcast i32 %1117 to float %1119 = bitcast float %1118 to i32 %1120 = icmp ne i32 %1119, 0 br i1 %1120, label %IF304, label %ENDIF303 IF304: ; preds = %LOOP %temp36.0.lcssa = phi float [ %temp36.0, %LOOP ] %temp37.0.lcssa = phi float [ %temp37.0, %LOOP ] %temp38.0.lcssa = phi float [ %temp38.0, %LOOP ] %1121 = call i32 @llvm.SI.packf16(float %temp36.0.lcssa, float %temp37.0.lcssa) %1122 = bitcast i32 %1121 to float %1123 = call i32 @llvm.SI.packf16(float %temp38.0.lcssa, float %temp3.0) %1124 = bitcast i32 %1123 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %1122, float %1124, float %1122, float %1124) ret void ENDIF303: ; preds = %LOOP %1125 = bitcast float %temp.0 to i32 %1126 = mul i32 %1125, 7 %1127 = bitcast i32 %1126 to float %1128 = bitcast float %1127 to i32 %1129 = shl i32 %1128, 4 %1130 = add i32 %1129, 64 %1131 = call float @llvm.SI.load.const(<16 x i8> %23, i32 %1130) %1132 = bitcast float %1127 to i32 %1133 = add i32 %1132, 1 %1134 = bitcast i32 %1133 to float %1135 = bitcast float %1134 to i32 %1136 = shl i32 %1135, 4 %1137 = add i32 %1136, 64 %1138 = call float @llvm.SI.load.const(<16 x i8> %23, i32 %1137) %1139 = bitcast float %1127 to i32 %1140 = add i32 %1139, 2 %1141 = bitcast i32 %1140 to float %1142 = bitcast float %1141 to i32 %1143 = shl i32 %1142, 4 %1144 = add i32 %1143, 64 %1145 = call float @llvm.SI.load.const(<16 x i8> %23, i32 %1144) %1146 = bitcast float %1127 to i32 %1147 = add i32 %1146, 3 %1148 = bitcast i32 %1147 to float %1149 = bitcast float %1148 to i32 %1150 = shl i32 %1149, 4 %1151 = add i32 %1150, 64 %1152 = call float @llvm.SI.load.const(<16 x i8> %23, i32 %1151) %1153 = bitcast float %1127 to i32 %1154 = add i32 %1153, 4 %1155 = bitcast i32 %1154 to float %1156 = bitcast float %1155 to i32 %1157 = shl i32 %1156, 4 %1158 = add i32 %1157, 64 %1159 = call float @llvm.SI.load.const(<16 x i8> %23, i32 %1158) %1160 = bitcast float %1127 to i32 %1161 = add i32 %1160, 5 %1162 = bitcast i32 %1161 to float %1163 = bitcast float %1162 to i32 %1164 = shl i32 %1163, 4 %1165 = add i32 %1164, 64 %1166 = call float @llvm.SI.load.const(<16 x i8> %23, i32 %1165) %1167 = bitcast float %1127 to i32 %1168 = add i32 %1167, 6 %1169 = bitcast i32 %1168 to float %1170 = bitcast float %1169 to i32 %1171 = shl i32 %1170, 4 %1172 = add i32 %1171, 64 %1173 = call float @llvm.SI.load.const(<16 x i8> %23, i32 %1172) %1174 = fadd float %1131, %828 %1175 = fadd float %1138, %829 %1176 = fadd float %1145, %830 %1177 = fmul float %1174, %1174 %1178 = fmul float %1175, %1175 %1179 = fadd float %1178, %1177 %1180 = fmul float %1176, %1176 %1181 = fadd float %1179, %1180 %1182 = call float @llvm.AMDGPU.rsq(float %1181) %1183 = fmul float %1182, %1181 %1184 = fsub float -0.000000e+00, %1181 %1185 = call float @llvm.AMDGPU.cndlt(float %1184, float %1183, float 0.000000e+00) %1186 = fdiv float 1.000000e+00, %1185 %1187 = fmul float %1174, %1186 %1188 = fmul float %1175, %1186 %1189 = fmul float %1176, %1186 %1190 = fmul float %541, %1187 %1191 = fmul float %542, %1188 %1192 = fadd float %1191, %1190 %1193 = fmul float %543, %1189 %1194 = fadd float %1192, %1193 %1195 = fcmp uge float 0.000000e+00, %1194 %1196 = select i1 %1195, float 0.000000e+00, float %1194 %1197 = fmul float %1196, %1152 %1198 = fmul float %1196, %1159 %1199 = fmul float %1196, %1166 %1200 = fmul float %1197, %temp20.1 %1201 = fmul float %1198, %temp21.1 %1202 = fmul float %1199, %temp22.1 %1203 = fmul float %629, %1187 %1204 = fmul float %631, %1188 %1205 = fadd float %1204, %1203 %1206 = fmul float %633, %1189 %1207 = fadd float %1205, %1206 %1208 = fcmp uge float 0x3F50624DE0000000, %1207 %1209 = select i1 %1208, float 0x3F50624DE0000000, float %1207 %1210 = call float @llvm.pow.f32(float %1209, float %28) %1211 = fmul float %1210, %1152 %1212 = fmul float %1210, %1159 %1213 = fmul float %1210, %1166 %1214 = fmul float %1211, %25 %1215 = fadd float %1214, %1200 %1216 = fmul float %1212, %26 %1217 = fadd float %1216, %1201 %1218 = fmul float %1213, %27 %1219 = fadd float %1218, %1202 %1220 = fmul float %1173, 5.000000e-01 %1221 = fsub float -0.000000e+00, %1220 %1222 = fadd float %1185, %1221 %1223 = fsub float -0.000000e+00, %1220 %1224 = fadd float %1173, %1223 %1225 = fdiv float 1.000000e+00, %1224 %1226 = fmul float %1222, %1225 %1227 = call float @llvm.AMDIL.clamp.(float %1226, float 0.000000e+00, float 1.000000e+00) %1228 = fmul float 2.000000e+00, %1227 %1229 = fsub float -0.000000e+00, %1228 %1230 = fadd float 3.000000e+00, %1229 %1231 = fmul float %1227, %1230 %1232 = fmul float %1227, %1231 %1233 = fsub float -0.000000e+00, %1232 %1234 = fadd float 1.000000e+00, %1233 %1235 = fmul float %1215, %1234 %1236 = fmul float %1217, %1234 %1237 = fmul float %1219, %1234 %1238 = fadd float %temp36.0, %1235 %1239 = fadd float %temp37.0, %1236 %1240 = fadd float %temp38.0, %1237 %1241 = bitcast float %temp.0 to i32 %1242 = add i32 %1241, 1 %1243 = bitcast i32 %1242 to float br label %LOOP } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: readnone declare float @llvm.AMDGPU.rsq(float) #2 ; Function Attrs: readnone declare float @llvm.AMDGPU.cndlt(float, float, float) #2 ; Function Attrs: nounwind readonly declare float @llvm.log2.f32(float) #3 ; Function Attrs: readonly declare float @floor(float) #4 ; Function Attrs: readnone declare float @llvm.AMDIL.exp.(float) #2 ; Function Attrs: readnone declare float @llvm.AMDIL.fraction.(float) #2 ; Function Attrs: readonly declare float @fabs(float) #4 ; Function Attrs: nounwind readonly declare float @llvm.pow.f32(float, float) #3 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1 ; Function Attrs: readnone declare float @llvm.AMDIL.clamp.(float, float, float) #2 ; Function Attrs: readnone declare float @llvm.AMDGPU.lrp(float, float, float) #2 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } attributes #3 = { nounwind readonly } attributes #4 = { readonly } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s9 ; BEFC0309 V_INTERP_P1_F32 v9, v0, 0, 1, [m0] ; C8240400 V_INTERP_P2_F32 v9, [v9], v1, 0, 1, [m0] ; C8250401 V_INTERP_P1_F32 v10, v0, 3, 0, [m0] ; C8280300 V_INTERP_P2_F32 v10, [v10], v1, 3, 0, [m0] ; C8290301 S_LOAD_DWORDX4 s[12:15], s[0:1], 4 ; C0860104 S_WAITCNT lgkmcnt(0) ; BF8C007F S_BUFFER_LOAD_DWORD s6, s[12:15], 49 ; C2030D31 S_WAITCNT lgkmcnt(0) ; BF8C007F V_WRITELANE_B32 v42, s6, 0 ; 04550006 V_MUL_F32_e32 v2, s6, v10 ; 10041406 S_BUFFER_LOAD_DWORD s6, s[12:15], 53 ; C2030D35 S_WAITCNT lgkmcnt(0) ; BF8C007F V_WRITELANE_B32 v42, s6, 1 ; 04550206 V_MAD_F32 v2, s6, v9, v2, 0, 0, 0, 0 ; D2820002 040A1206 V_INTERP_P1_F32 v11, v0, 1, 1, [m0] ; C82C0500 V_INTERP_P2_F32 v11, [v11], v1, 1, 1, [m0] ; C82D0501 S_BUFFER_LOAD_DWORD s6, s[12:15], 57 ; C2030D39 S_WAITCNT lgkmcnt(0) ; BF8C007F V_WRITELANE_B32 v42, s6, 2 ; 04550406 V_MAD_F32 v2, s6, v11, v2, 0, 0, 0, 0 ; D2820002 040A1606 S_BUFFER_LOAD_DWORD s6, s[12:15], 61 ; C2030D3D S_WAITCNT lgkmcnt(0) ; BF8C007F V_WRITELANE_B32 v42, s6, 3 ; 04550606 V_ADD_F32_e32 v2, s6, v2 ; 06040406 S_BUFFER_LOAD_DWORD s6, s[12:15], 81 ; C2030D51 S_WAITCNT lgkmcnt(0) ; BF8C007F V_WRITELANE_B32 v42, s6, 4 ; 04550806 V_SUBREV_F32_e32 v2, s6, v2 ; 0A040406 S_BUFFER_LOAD_DWORD s6, s[12:15], 48 ; C2030D30 S_WAITCNT lgkmcnt(0) ; BF8C007F V_WRITELANE_B32 v42, s6, 5 ; 04550A06 V_MUL_F32_e32 v3, s6, v10 ; 10061406 S_BUFFER_LOAD_DWORD s6, s[12:15], 52 ; C2030D34 S_WAITCNT lgkmcnt(0) ; BF8C007F V_WRITELANE_B32 v42, s6, 6 ; 04550C06 V_MAD_F32 v3, s6, v9, v3, 0, 0, 0, 0 ; D2820003 040E1206 S_BUFFER_LOAD_DWORD s6, s[12:15], 56 ; C2030D38 S_WAITCNT lgkmcnt(0) ; BF8C007F V_WRITELANE_B32 v42, s6, 7 ; 04550E06 V_MAD_F32 v3, s6, v11, v3, 0, 0, 0, 0 ; D2820003 040E1606 S_BUFFER_LOAD_DWORD s6, s[12:15], 60 ; C2030D3C S_WAITCNT lgkmcnt(0) ; BF8C007F V_WRITELANE_B32 v42, s6, 8 ; 04551006 V_ADD_F32_e32 v3, s6, v3 ; 06060606 S_BUFFER_LOAD_DWORD s6, s[12:15], 80 ; C2030D50 S_WAITCNT lgkmcnt(0) ; BF8C007F V_WRITELANE_B32 v42, s6, 9 ; 04551206 V_SUBREV_F32_e32 v3, s6, v3 ; 0A060606 V_MUL_F32_e32 v3, v3, v3 ; 10060703 V_MAD_F32 v2, v2, v2, v3, 0, 0, 0, 0 ; D2820002 040E0502 S_BUFFER_LOAD_DWORD s79, s[12:15], 50 ; C2278D32 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v3, s79, v10 ; 1006144F S_BUFFER_LOAD_DWORD s82, s[12:15], 54 ; C2290D36 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v3, s82, v9, v3, 0, 0, 0, 0 ; D2820003 040E1252 S_BUFFER_LOAD_DWORD s83, s[12:15], 58 ; C2298D3A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v3, s83, v11, v3, 0, 0, 0, 0 ; D2820003 040E1653 S_BUFFER_LOAD_DWORD s100, s[12:15], 62 ; C2320D3E S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v3, s100, v3 ; 06060664 S_BUFFER_LOAD_DWORD s28, s[12:15], 82 ; C20E0D52 S_WAITCNT lgkmcnt(0) ; BF8C007F V_SUBREV_F32_e32 v3, s28, v3 ; 0A06061C V_MAD_F32 v2, v3, v3, v2, 0, 0, 0, 0 ; D2820002 040A0703 V_RSQ_LEGACY_F32_e32 v3, v2 ; 7E065B02 V_MUL_F32_e32 v3, v3, v2 ; 10060503 V_XOR_B32_e32 v2, -2147483648, v2 ; 3A0404FF 80000000 V_CMP_GT_F32_e64 s[6:7], 0, v2, 0, 0, 0, 0 ; D0080006 02020480 V_CNDMASK_B32_e64 v2, 0.000000e+00, v3, s[6:7], 0, 0, 0, 0 ; D2000002 001A0680 S_LOAD_DWORDX4 s[12:15], s[0:1], 0 ; C0860100 S_MOV_B32 s6, 1360 ; BE8603FF 00000550 S_WAITCNT lgkmcnt(0) ; BF8C007F S_BUFFER_LOAD_DWORD s6, s[12:15], s6 ; C2030C06 S_WAITCNT lgkmcnt(0) ; BF8C007F V_RCP_F32_e32 v3, s6 ; 7E065406 V_MAD_F32 v2, v2, v3, 1.000000e+00, 0, 0, 0, 0 ; D2820002 03CA0702 V_LOG_F32_e32 v2, v2 ; 7E044F02 V_MUL_F32_e32 v2, 6.931472e-01, v2 ; 100404FF 3F317218 S_MOV_B32 s6, 1376 ; BE8603FF 00000560 S_BUFFER_LOAD_DWORD s6, s[12:15], s6 ; C2030C06 S_WAITCNT lgkmcnt(0) ; BF8C007F V_LOG_F32_e32 v3, s6 ; 7E064E06 V_MUL_F32_e32 v3, 6.931472e-01, v3 ; 100606FF 3F317218 V_RCP_F32_e32 v3, v3 ; 7E065503 V_MUL_F32_e32 v5, v2, v3 ; 100A0702 V_FLOOR_F32_e32 v2, v5 ; 7E044905 V_EXP_F32_e32 v18, v2 ; 7E244B02 S_MOV_B32 s6, 1296 ; BE8603FF 00000510 S_BUFFER_LOAD_DWORD s68, s[12:15], s6 ; C2220C06 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v2, s68, v18 ; 10042444 V_RCP_F32_e32 v2, v2 ; 7E045502 V_INTERP_P1_F32 v13, v0, 3, 1, [m0] ; C8340700 V_INTERP_P2_F32 v13, [v13], v1, 3, 1, [m0] ; C8350701 V_MUL_F32_e32 v7, v13, v2 ; 100E050D V_INTERP_P1_F32 v16, v0, 2, 1, [m0] ; C8400600 V_INTERP_P2_F32 v16, [v16], v1, 2, 1, [m0] ; C8410601 V_MUL_F32_e32 v6, v16, v2 ; 100C0510 S_LOAD_DWORDX4 s[40:43], s[2:3], 8 ; C0940308 S_LOAD_DWORDX8 s[16:23], s[4:5], 16 ; C0C80510 S_WAITCNT lgkmcnt(0) ; BF8C007F V_WRITELANE_B32 v42, s16, 10 ; 04551410 V_WRITELANE_B32 v42, s17, 11 ; 04551611 V_WRITELANE_B32 v42, s18, 12 ; 04551812 V_WRITELANE_B32 v42, s19, 13 ; 04551A13 V_WRITELANE_B32 v42, s20, 14 ; 04551C14 V_WRITELANE_B32 v42, s21, 15 ; 04551E15 V_WRITELANE_B32 v42, s22, 16 ; 04552016 V_WRITELANE_B32 v42, s23, 17 ; 04552217 IMAGE_SAMPLE v[25:27], 7, 0, 0, 0, 0, 0, 0, 0, v[6:7], s[16:23], s[40:43] ; F0800700 01441906 V_INTERP_P1_F32 v19, v0, 2, 2, [m0] ; C84C0A00 V_INTERP_P2_F32 v19, [v19], v1, 2, 2, [m0] ; C84D0A01 V_AND_B32_e32 v8, 2147483647, v19 ; 361026FF 7FFFFFFF V_ADD_F32_e32 v2, 1.000000e-03, v8 ; 060410FF 3A83126F V_LOG_F32_e32 v2, v2 ; 7E044F02 S_MOV_B32 s6, 1344 ; BE8603FF 00000540 S_BUFFER_LOAD_DWORD s29, s[12:15], s6 ; C20E8C06 S_WAITCNT vmcnt(0) lgkmcnt(0) ; BF8C0070 V_MUL_LEGACY_F32_e32 v2, s29, v2 ; 0E04041D V_EXP_F32_e32 v2, v2 ; 7E044B02 V_INTERP_P1_F32 v17, v0, 1, 2, [m0] ; C8440900 V_INTERP_P2_F32 v17, [v17], v1, 1, 2, [m0] ; C8450901 V_AND_B32_e32 v12, 2147483647, v17 ; 361822FF 7FFFFFFF V_ADD_F32_e32 v3, 1.000000e-03, v12 ; 060618FF 3A83126F V_LOG_F32_e32 v3, v3 ; 7E064F03 V_MUL_LEGACY_F32_e32 v3, s29, v3 ; 0E06061D V_EXP_F32_e32 v3, v3 ; 7E064B03 V_ADD_F32_e32 v4, v3, v2 ; 06080503 V_INTERP_P1_F32 v24, v0, 3, 2, [m0] ; C8600B00 V_INTERP_P2_F32 v24, [v24], v1, 3, 2, [m0] ; C8610B01 V_AND_B32_e32 v14, 2147483647, v24 ; 361C30FF 7FFFFFFF V_ADD_F32_e32 v15, 1.000000e-03, v14 ; 061E1CFF 3A83126F V_LOG_F32_e32 v15, v15 ; 7E1E4F0F V_MUL_LEGACY_F32_e32 v15, s29, v15 ; 0E1E1E1D V_EXP_F32_e32 v15, v15 ; 7E1E4B0F V_ADD_F32_e32 v4, v4, v15 ; 06081F04 V_RCP_F32_e32 v4, v4 ; 7E085504 V_MUL_F32_e32 v15, v15, v4 ; 101E090F V_MUL_F32_e32 v20, v27, v15 ; 10281F1B S_MOV_B32 s6, 1312 ; BE8603FF 00000520 S_BUFFER_LOAD_DWORD s77, s[12:15], s6 ; C2268C06 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v21, s77, v18 ; 102A244D V_RCP_F32_e32 v21, v21 ; 7E2A5515 V_INTERP_P1_F32 v22, v0, 0, 2, [m0] ; C8580800 V_INTERP_P2_F32 v22, [v22], v1, 0, 2, [m0] ; C8590801 V_MUL_F32_e32 v29, v22, v21 ; 103A2B16 V_MUL_F32_e32 v28, v16, v21 ; 10382B10 S_LOAD_DWORDX4 s[44:47], s[2:3], 12 ; C096030C S_LOAD_DWORDX8 s[48:55], s[4:5], 24 ; C0D80518 S_WAITCNT lgkmcnt(0) ; BF8C007F IMAGE_SAMPLE v[30:32], 7, 0, 0, 0, 0, 0, 0, 0, v[28:29], s[48:55], s[44:47] ; F0800700 016C1E1C V_MUL_F32_e32 v21, v2, v4 ; 102A0902 S_WAITCNT vmcnt(0) ; BF8C0770 V_MAD_F32 v2, v32, v21, v20, 0, 0, 0, 0 ; D2820002 04522B20 S_MOV_B32 s6, 1328 ; BE8603FF 00000530 S_BUFFER_LOAD_DWORD s76, s[12:15], s6 ; C2260C06 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v20, s76, v18 ; 1028244C V_RCP_F32_e32 v20, v20 ; 7E285514 V_MUL_F32_e32 v34, v13, v20 ; 1044290D V_MUL_F32_e32 v33, v22, v20 ; 10422916 S_LOAD_DWORDX4 s[56:59], s[2:3], 16 ; C09C0310 S_LOAD_DWORDX8 s[60:67], s[4:5], 32 ; C0DE0520 S_WAITCNT lgkmcnt(0) ; BF8C007F IMAGE_SAMPLE v[35:37], 7, 0, 0, 0, 0, 0, 0, 0, v[33:34], s[60:67], s[56:59] ; F0800700 01CF2321 V_MUL_F32_e32 v4, v3, v4 ; 10080903 S_WAITCNT vmcnt(0) ; BF8C0770 V_MAD_F32 v2, v37, v4, v2, 0, 0, 0, 0 ; D2820002 040A0925 V_MUL_F32_e32 v3, v26, v15 ; 10061F1A V_MAD_F32 v3, v31, v21, v3, 0, 0, 0, 0 ; D2820003 040E2B1F V_MAD_F32 v3, v36, v4, v3, 0, 0, 0, 0 ; D2820003 040E0924 V_MUL_F32_e32 v15, v25, v15 ; 101E1F19 V_MAD_F32 v15, v30, v21, v15, 0, 0, 0, 0 ; D282000F 043E2B1E V_MAD_F32 v4, v35, v4, v15, 0, 0, 0, 0 ; D2820004 043E0923 S_LOAD_DWORDX4 s[24:27], s[2:3], 20 ; C08C0314 S_LOAD_DWORDX8 s[32:39], s[4:5], 40 ; C0D00528 S_WAITCNT lgkmcnt(0) ; BF8C007F IMAGE_SAMPLE v[25:27], 7, 0, 0, 0, 0, 0, 0, 0, v[6:7], s[32:39], s[24:27] ; F0800700 00C81906 V_CMP_U_F32_e64 s[6:7], v24, v24, 0, 0, 0, 0 ; D0100006 02023118 V_CMP_GT_F32_e64 s[16:17], v24, 0.000000e+00, 0, 0, 0, 0 ; D0080010 02010118 S_OR_B64 s[6:7], s[16:17], s[6:7] ; 88860610 V_CNDMASK_B32_e64 v6, v24, 1.000000e+00, s[6:7], 0, 0, 0, 0 ; D2000006 0019E518 V_CMP_U_F32_e64 s[6:7], v6, v6, 0, 0, 0, 0 ; D0100006 02020D06 V_CMP_GE_F32_e64 s[16:17], v6, 0.000000e+00, 0, 0, 0, 0 ; D00C0010 02010106 S_OR_B64 s[6:7], s[16:17], s[6:7] ; 88860610 V_CNDMASK_B32_e64 v6, -1.000000e+00, v6, s[6:7], 0, 0, 0, 0 ; D2000006 001A0CF3 S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v7, v27, v6 ; 100E0D1B V_ADD_F32_e32 v15, v12, v8 ; 061E110C V_ADD_F32_e32 v15, v15, v14 ; 061E1D0F V_RCP_F32_e32 v15, v15 ; 7E1E550F V_MUL_F32_e32 v20, v14, v15 ; 10281F0E V_MUL_F32_e32 v7, v7, v20 ; 100E2907 S_LOAD_DWORDX4 s[96:99], s[2:3], 24 ; C0B00318 S_LOAD_DWORDX8 s[16:23], s[4:5], 48 ; C0C80530 S_WAITCNT lgkmcnt(0) ; BF8C007F IMAGE_SAMPLE v[28:30], 7, 0, 0, 0, 0, 0, 0, 0, v[28:29], s[16:23], s[96:99] ; F0800700 03041C1C S_WAITCNT vmcnt(0) ; BF8C0770 V_ADD_F32_e32 v14, v29, v29 ; 061C3B1D V_ADD_F32_e32 v14, -1.003906e+00, v14 ; 061C1CFF BF808000 V_CMP_U_F32_e64 s[6:7], v19, v19, 0, 0, 0, 0 ; D0100006 02022713 V_CMP_GT_F32_e64 s[30:31], v19, 0.000000e+00, 0, 0, 0, 0 ; D008001E 02010113 S_OR_B64 s[6:7], s[30:31], s[6:7] ; 8886061E V_CNDMASK_B32_e64 v21, v19, 1.000000e+00, s[6:7], 0, 0, 0, 0 ; D2000015 0019E513 V_CMP_U_F32_e64 s[6:7], v21, v21, 0, 0, 0, 0 ; D0100006 02022B15 V_CMP_GE_F32_e64 s[30:31], v21, 0.000000e+00, 0, 0, 0, 0 ; D00C001E 02010115 S_OR_B64 s[6:7], s[30:31], s[6:7] ; 8886061E V_CNDMASK_B32_e64 v21, -1.000000e+00, v21, s[6:7], 0, 0, 0, 0 ; D2000015 001A2AF3 V_MUL_F32_e32 v14, v14, v21 ; 101C2B0E V_MUL_F32_e32 v8, v8, v15 ; 10101F08 V_MAD_F32 v7, v14, v8, v7, 0, 0, 0, 0 ; D2820007 041E110E S_LOAD_DWORDX4 s[84:87], s[2:3], 28 ; C0AA031C S_LOAD_DWORDX8 s[88:95], s[4:5], 56 ; C0EC0538 S_WAITCNT lgkmcnt(0) ; BF8C007F IMAGE_SAMPLE v[31:33], 7, 0, 0, 0, 0, 0, 0, 0, v[33:34], s[88:95], s[84:87] ; F0800700 02B61F21 S_WAITCNT vmcnt(0) ; BF8C0770 V_ADD_F32_e32 v14, v31, v31 ; 061C3F1F V_ADD_F32_e32 v14, -1.003906e+00, v14 ; 061C1CFF BF808000 V_CMP_U_F32_e64 s[6:7], v17, v17, 0, 0, 0, 0 ; D0100006 02022311 V_CMP_GT_F32_e64 s[30:31], v17, 0.000000e+00, 0, 0, 0, 0 ; D008001E 02010111 S_OR_B64 s[6:7], s[30:31], s[6:7] ; 8886061E V_CNDMASK_B32_e64 v23, v17, 1.000000e+00, s[6:7], 0, 0, 0, 0 ; D2000017 0019E511 V_CMP_U_F32_e64 s[6:7], v23, v23, 0, 0, 0, 0 ; D0100006 02022F17 V_CMP_GE_F32_e64 s[30:31], v23, 0.000000e+00, 0, 0, 0, 0 ; D00C001E 02010117 S_OR_B64 s[6:7], s[30:31], s[6:7] ; 8886061E V_CNDMASK_B32_e64 v23, -1.000000e+00, v23, s[6:7], 0, 0, 0, 0 ; D2000017 001A2EF3 V_MUL_F32_e32 v14, v14, v23 ; 101C2F0E V_MUL_F32_e32 v15, v12, v15 ; 101E1F0C V_MAD_F32 v12, v14, v15, v7, 0, 0, 0, 0 ; D282000C 041E1F0E V_MUL_F32_e32 v7, v30, v21 ; 100E2B1E V_ADD_F32_e32 v14, v26, v26 ; 061C351A V_ADD_F32_e32 v14, -1.003906e+00, v14 ; 061C1CFF BF808000 V_MUL_F32_e32 v14, v14, v6 ; 101C0D0E V_MUL_F32_e32 v14, v14, v20 ; 101C290E V_MAD_F32 v7, v7, v8, v14, 0, 0, 0, 0 ; D2820007 043A1107 V_ADD_F32_e32 v14, v32, v32 ; 061C4120 V_ADD_F32_e32 v14, -1.003906e+00, v14 ; 061C1CFF BF808000 V_MUL_F32_e32 v14, v14, v23 ; 101C2F0E V_MAD_F32 v14, v14, v15, v7, 0, 0, 0, 0 ; D282000E 041E1F0E V_ADD_F32_e32 v7, v28, v28 ; 060E391C V_ADD_F32_e32 v7, -1.003906e+00, v7 ; 060E0EFF BF808000 V_MUL_F32_e32 v7, v7, v21 ; 100E2B07 V_ADD_F32_e32 v21, v25, v25 ; 062A3319 V_ADD_F32_e32 v21, -1.003906e+00, v21 ; 062A2AFF BF808000 V_MUL_F32_e32 v6, v21, v6 ; 100C0D15 V_MUL_F32_e32 v6, v6, v20 ; 100C2906 V_MAD_F32 v6, v7, v8, v6, 0, 0, 0, 0 ; D2820006 041A1107 V_MUL_F32_e32 v7, v33, v23 ; 100E2F21 V_MAD_F32 v15, v7, v15, v6, 0, 0, 0, 0 ; D282000F 041A1F07 V_FRACT_F32_e32 v25, v5 ; 7E324105 S_MOV_B32 s6, 1392 ; BE8603FF 00000570 S_BUFFER_LOAD_DWORD s101, s[12:15], s6 ; C2328C06 S_WAITCNT lgkmcnt(0) ; BF8C007F V_CMP_LT_F32_e64 s[80:81], v25, s101, 0, 0, 0, 0 ; D0020050 0200CB19 V_INTERP_P1_F32 v20, v0, 2, 0, [m0] ; C8500200 V_INTERP_P2_F32 v20, [v20], v1, 2, 0, [m0] ; C8510201 V_INTERP_P1_F32 v21, v0, 1, 0, [m0] ; C8540100 V_INTERP_P2_F32 v21, [v21], v1, 1, 0, [m0] ; C8550101 V_INTERP_P1_F32 v23, v0, 0, 0, [m0] ; C85C0000 V_INTERP_P2_F32 v23, [v23], v1, 0, 0, [m0] ; C85D0001 S_MOV_B32 s6, 1480 ; BE8603FF 000005C8 S_BUFFER_LOAD_DWORD s30, s[12:15], s6 ; C20F0C06 S_MOV_B32 s6, 1476 ; BE8603FF 000005C4 S_BUFFER_LOAD_DWORD s70, s[12:15], s6 ; C2230C06 S_MOV_B32 s6, 1472 ; BE8603FF 000005C0 S_BUFFER_LOAD_DWORD s69, s[12:15], s6 ; C2228C06 S_MOV_B32 s6, 1464 ; BE8603FF 000005B8 S_BUFFER_LOAD_DWORD s31, s[12:15], s6 ; C20F8C06 S_MOV_B32 s6, 1460 ; BE8603FF 000005B4 S_BUFFER_LOAD_DWORD s73, s[12:15], s6 ; C2248C06 S_MOV_B32 s6, 1456 ; BE8603FF 000005B0 S_BUFFER_LOAD_DWORD s72, s[12:15], s6 ; C2240C06 S_MOV_B32 s6, 1448 ; BE8603FF 000005A8 S_BUFFER_LOAD_DWORD s71, s[12:15], s6 ; C2238C06 S_MOV_B32 s6, 1444 ; BE8603FF 000005A4 S_BUFFER_LOAD_DWORD s75, s[12:15], s6 ; C2258C06 S_MOV_B32 s6, 1440 ; BE8603FF 000005A0 S_BUFFER_LOAD_DWORD s74, s[12:15], s6 ; C2250C06 S_MOV_B32 s6, 1408 ; BE8603FF 00000580 S_BUFFER_LOAD_DWORD s78, s[12:15], s6 ; C2270C06 S_MOV_B32 s6, 1292 ; BE8603FF 0000050C S_BUFFER_LOAD_DWORD s6, s[12:15], s6 ; C2030C06 S_MOV_B32 s7, 1288 ; BE8703FF 00000508 S_BUFFER_LOAD_DWORD s7, s[12:15], s7 ; C2038C07 S_MOV_B32 s8, 1284 ; BE8803FF 00000504 S_BUFFER_LOAD_DWORD s8, s[12:15], s8 ; C2040C08 S_MOV_B32 s9, 1280 ; BE8903FF 00000500 S_BUFFER_LOAD_DWORD s9, s[12:15], s9 ; C2048C09 V_MOV_B32_e32 v8, 0.000000e+00 ; 7E100280 S_WAITCNT lgkmcnt(0) ; BF8C007F S_AND_SAVEEXEC_B64 s[80:81], s[80:81] ; BED02450 S_XOR_B64 s[80:81], exec, s[80:81] ; 89D0507E S_CBRANCH_EXECZ BB0_2 ; BF880000 V_CMP_U_F32_e64 vcc, v24, v24, 0, 0, 0, 0 ; D010006A 02023118 V_CMP_GT_F32_e64 s[10:11], v24, 0.000000e+00, 0, 0, 0, 0 ; D008000A 02010118 S_OR_B64 s[10:11], s[10:11], vcc ; 888A6A0A V_CNDMASK_B32_e64 v0, v24, 1.000000e+00, s[10:11], 0, 0, 0, 0 ; D2000000 0029E518 V_CMP_U_F32_e64 s[10:11], v0, v0, 0, 0, 0, 0 ; D010000A 02020100 V_CMP_GE_F32_e64 vcc, v0, 0.000000e+00, 0, 0, 0, 0 ; D00C006A 02010100 S_OR_B64 s[10:11], vcc, s[10:11] ; 888A0A6A V_CNDMASK_B32_e64 v0, -1.000000e+00, v0, s[10:11], 0, 0, 0, 0 ; D2000000 002A00F3 V_MUL_F32_e64 v1, v18, 5.000000e-01, 0, 0, 0, 0 ; D2100001 0201E112 V_MUL_F32_e32 v5, s68, v1 ; 100A0244 V_RCP_F32_e32 v5, v5 ; 7E0A5505 V_MUL_F32_e32 v7, v13, v5 ; 100E0B0D V_MUL_F32_e32 v6, v16, v5 ; 100C0B10 IMAGE_SAMPLE v[26:28], 7, 0, 0, 0, 0, 0, 0, 0, v[6:7], s[32:39], s[24:27] ; F0800700 00C81A06 S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v5, v28, v0 ; 100A011C V_MOV_B32_e32 v8, 2147483647 ; 7E1002FF 7FFFFFFF V_AND_B32_e32 v18, v19, v8 ; 36241113 V_AND_B32_e32 v29, v17, v8 ; 363A1111 V_ADD_F32_e32 v30, v29, v18 ; 063C251D V_AND_B32_e32 v8, v24, v8 ; 36101118 V_ADD_F32_e32 v24, v30, v8 ; 0630111E V_RCP_F32_e32 v24, v24 ; 7E305518 V_MUL_F32_e32 v30, v8, v24 ; 103C3108 V_MUL_F32_e32 v5, v5, v30 ; 100A3D05 V_CMP_U_F32_e64 s[10:11], v19, v19, 0, 0, 0, 0 ; D010000A 02022713 V_CMP_GT_F32_e64 s[24:25], v19, 0.000000e+00, 0, 0, 0, 0 ; D0080018 02010113 S_OR_B64 s[10:11], s[24:25], s[10:11] ; 888A0A18 V_CNDMASK_B32_e64 v19, v19, 1.000000e+00, s[10:11], 0, 0, 0, 0 ; D2000013 0029E513 V_CMP_U_F32_e64 s[10:11], v19, v19, 0, 0, 0, 0 ; D010000A 02022713 V_CMP_GE_F32_e64 s[24:25], v19, 0.000000e+00, 0, 0, 0, 0 ; D00C0018 02010113 S_OR_B64 s[10:11], s[24:25], s[10:11] ; 888A0A18 V_CNDMASK_B32_e64 v19, -1.000000e+00, v19, s[10:11], 0, 0, 0, 0 ; D2000013 002A26F3 V_MUL_F32_e32 v31, s77, v1 ; 103E024D V_RCP_F32_e32 v31, v31 ; 7E3E551F V_MUL_F32_e32 v33, v22, v31 ; 10423F16 V_MUL_F32_e32 v32, v16, v31 ; 10403F10 IMAGE_SAMPLE v[34:36], 7, 0, 0, 0, 0, 0, 0, 0, v[32:33], s[16:23], s[96:99] ; F0800700 03042220 S_WAITCNT vmcnt(0) ; BF8C0770 V_ADD_F32_e32 v16, v35, v35 ; 06204723 V_ADD_F32_e32 v16, -1.003906e+00, v16 ; 062020FF BF808000 V_MUL_F32_e32 v16, v16, v19 ; 10202710 V_MUL_F32_e32 v31, v18, v24 ; 103E3112 V_MAD_F32 v5, v16, v31, v5, 0, 0, 0, 0 ; D2820005 04163F10 V_CMP_U_F32_e64 s[10:11], v17, v17, 0, 0, 0, 0 ; D010000A 02022311 V_CMP_GT_F32_e64 s[16:17], v17, 0.000000e+00, 0, 0, 0, 0 ; D0080010 02010111 S_OR_B64 s[10:11], s[16:17], s[10:11] ; 888A0A10 V_CNDMASK_B32_e64 v16, v17, 1.000000e+00, s[10:11], 0, 0, 0, 0 ; D2000010 0029E511 V_CMP_U_F32_e64 s[10:11], v16, v16, 0, 0, 0, 0 ; D010000A 02022110 V_CMP_GE_F32_e64 s[16:17], v16, 0.000000e+00, 0, 0, 0, 0 ; D00C0010 02010110 S_OR_B64 s[10:11], s[16:17], s[10:11] ; 888A0A10 V_CNDMASK_B32_e64 v16, -1.000000e+00, v16, s[10:11], 0, 0, 0, 0 ; D2000010 002A20F3 V_MUL_F32_e32 v1, s76, v1 ; 1002024C V_RCP_F32_e32 v1, v1 ; 7E025501 V_MUL_F32_e32 v38, v13, v1 ; 104C030D V_MUL_F32_e32 v37, v22, v1 ; 104A0316 IMAGE_SAMPLE v[39:41], 7, 0, 0, 0, 0, 0, 0, 0, v[37:38], s[88:95], s[84:87] ; F0800700 02B62725 S_WAITCNT vmcnt(0) ; BF8C0770 V_ADD_F32_e32 v1, v39, v39 ; 06024F27 V_ADD_F32_e32 v1, -1.003906e+00, v1 ; 060202FF BF808000 V_MUL_F32_e32 v1, v1, v16 ; 10022101 V_MUL_F32_e32 v13, v29, v24 ; 101A311D V_MAD_F32 v1, v1, v13, v5, 0, 0, 0, 0 ; D2820001 04161B01 V_RCP_F32_e32 v5, s101 ; 7E0A5465 V_MUL_F32_e32 v5, v25, v5 ; 100A0B19 V_ADD_F32_e64 v5, 0, v5, 0, 1, 0, 0 ; D2060805 02020A80 V_ADD_F32_e32 v17, v5, v5 ; 06220B05 V_SUB_F32_e32 v17, 3.000000e+00, v17 ; 082222FF 40400000 V_MUL_F32_e32 v17, v5, v17 ; 10222305 V_MUL_F32_e32 v17, v5, v17 ; 10222305 V_SUB_F32_e32 v22, 1.000000e+00, v17 ; 082C22F2 V_MUL_F32_e32 v1, v22, v1 ; 10020316 V_MAD_F32 v12, v17, v12, v1, 0, 0, 0, 0 ; D282000C 04061911 V_MUL_F32_e32 v1, v36, v19 ; 10022724 V_ADD_F32_e32 v5, v27, v27 ; 060A371B V_ADD_F32_e32 v5, -1.003906e+00, v5 ; 060A0AFF BF808000 V_MUL_F32_e32 v5, v5, v0 ; 100A0105 V_MUL_F32_e32 v5, v5, v30 ; 100A3D05 V_MAD_F32 v1, v1, v31, v5, 0, 0, 0, 0 ; D2820001 04163F01 V_ADD_F32_e32 v5, v40, v40 ; 060A5128 V_ADD_F32_e32 v5, -1.003906e+00, v5 ; 060A0AFF BF808000 V_MUL_F32_e32 v5, v5, v16 ; 100A2105 V_MAD_F32 v1, v5, v13, v1, 0, 0, 0, 0 ; D2820001 04061B05 V_MUL_F32_e32 v1, v22, v1 ; 10020316 V_MAD_F32 v14, v17, v14, v1, 0, 0, 0, 0 ; D282000E 04061D11 V_ADD_F32_e32 v1, v34, v34 ; 06024522 V_ADD_F32_e32 v1, -1.003906e+00, v1 ; 060202FF BF808000 V_MUL_F32_e32 v1, v1, v19 ; 10022701 V_ADD_F32_e32 v5, v26, v26 ; 060A351A V_ADD_F32_e32 v5, -1.003906e+00, v5 ; 060A0AFF BF808000 V_MUL_F32_e32 v0, v5, v0 ; 10000105 V_MUL_F32_e32 v0, v0, v30 ; 10003D00 V_MAD_F32 v0, v1, v31, v0, 0, 0, 0, 0 ; D2820000 04023F01 V_MUL_F32_e32 v1, v41, v16 ; 10022129 V_MAD_F32 v0, v1, v13, v0, 0, 0, 0, 0 ; D2820000 04021B01 V_MUL_F32_e32 v0, v22, v0 ; 10000116 V_MAD_F32 v15, v17, v15, v0, 0, 0, 0, 0 ; D282000F 04021F11 V_ADD_F32_e32 v0, 1.000000e-03, v18 ; 060024FF 3A83126F V_LOG_F32_e32 v0, v0 ; 7E004F00 V_MUL_LEGACY_F32_e32 v0, s29, v0 ; 0E00001D V_EXP_F32_e32 v0, v0 ; 7E004B00 V_ADD_F32_e32 v1, 1.000000e-03, v29 ; 06023AFF 3A83126F V_LOG_F32_e32 v1, v1 ; 7E024F01 V_MUL_LEGACY_F32_e32 v1, s29, v1 ; 0E02021D V_EXP_F32_e32 v1, v1 ; 7E024B01 V_ADD_F32_e32 v5, v1, v0 ; 060A0101 V_ADD_F32_e32 v8, 1.000000e-03, v8 ; 061010FF 3A83126F V_LOG_F32_e32 v8, v8 ; 7E104F08 V_MUL_LEGACY_F32_e32 v8, s29, v8 ; 0E10101D V_EXP_F32_e32 v8, v8 ; 7E104B08 V_ADD_F32_e32 v5, v5, v8 ; 060A1105 V_RCP_F32_e32 v13, v5 ; 7E1A5505 V_MUL_F32_e32 v16, v8, v13 ; 10201B08 V_READLANE_B32 s16, v42, 10 ; 0221152A V_READLANE_B32 s17, v42, 11 ; 0223172A V_READLANE_B32 s18, v42, 12 ; 0225192A V_READLANE_B32 s19, v42, 13 ; 02271B2A V_READLANE_B32 s20, v42, 14 ; 02291D2A V_READLANE_B32 s21, v42, 15 ; 022B1F2A V_READLANE_B32 s22, v42, 16 ; 022D212A V_READLANE_B32 s23, v42, 17 ; 022F232A IMAGE_SAMPLE v[24:26], 7, 0, 0, 0, 0, 0, 0, 0, v[6:7], s[16:23], s[40:43] ; F0800700 01441806 S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v18, v26, v16 ; 1024211A V_MUL_F32_e32 v0, v0, v13 ; 10001B00 IMAGE_SAMPLE v[5:8], 15, 0, 0, 0, 0, 0, 0, 0, v[32:33], s[48:55], s[44:47] ; F0800F00 016C0520 S_WAITCNT vmcnt(0) ; BF8C0770 V_MAD_F32 v18, v7, v0, v18, 0, 0, 0, 0 ; D2820012 044A0107 V_MUL_F32_e32 v1, v1, v13 ; 10021B01 IMAGE_SAMPLE v[27:29], 7, 0, 0, 0, 0, 0, 0, 0, v[37:38], s[60:67], s[56:59] ; F0800700 01CF1B25 S_WAITCNT vmcnt(0) ; BF8C0770 V_MAD_F32 v13, v29, v1, v18, 0, 0, 0, 0 ; D282000D 044A031D V_MUL_F32_e32 v13, v22, v13 ; 101A1B16 V_MAD_F32 v2, v17, v2, v13, 0, 0, 0, 0 ; D2820002 04360511 V_MUL_F32_e32 v13, v25, v16 ; 101A2119 V_MAD_F32 v13, v6, v0, v13, 0, 0, 0, 0 ; D282000D 04360106 V_MAD_F32 v13, v28, v1, v13, 0, 0, 0, 0 ; D282000D 0436031C V_MUL_F32_e32 v13, v22, v13 ; 101A1B16 V_MAD_F32 v3, v17, v3, v13, 0, 0, 0, 0 ; D2820003 04360711 V_MUL_F32_e32 v13, v24, v16 ; 101A2118 V_MAD_F32 v0, v5, v0, v13, 0, 0, 0, 0 ; D2820000 04360105 V_MAD_F32 v0, v27, v1, v0, 0, 0, 0, 0 ; D2820000 0402031B V_MUL_F32_e32 v0, v22, v0 ; 10000116 V_MAD_F32 v4, v17, v4, v0, 0, 0, 0, 0 ; D2820004 04020911 S_OR_B64 exec, exec, s[80:81] ; 88FE507E V_CMP_GT_F32_e64 s[10:11], s78, 5.000000e-01, 0, 0, 0, 0 ; D008000A 0201E04E S_AND_SAVEEXEC_B64 s[16:17], s[10:11] ; BE90240A S_XOR_B64 s[16:17], exec, s[16:17] ; 8990107E V_MUL_F32_e64 v2, v2, v20, 0, 0, 0, 0 ; D2100002 02022902 V_MUL_F32_e64 v3, v3, v21, 0, 0, 0, 0 ; D2100003 02022B03 V_MUL_F32_e64 v4, v4, v23, 0, 0, 0, 0 ; D2100004 02022F04 S_OR_B64 exec, exec, s[16:17] ; 88FE107E S_LOAD_DWORDX4 s[32:35], s[2:3], 0 ; C0900300 S_LOAD_DWORDX8 s[36:43], s[4:5], 0 ; C0D20500 V_MUL_F32_e64 v0, s75, v15, 0, 0, 0, 0 ; D2100000 02021E4B V_MAD_F32 v0, s73, v14, v0, 0, 0, 0, 0 ; D2820000 04021C49 V_MAD_F32 v17, s70, v12, v0, 0, 0, 0, 0 ; D2820011 04021846 V_MUL_F32_e64 v0, s74, v15, 0, 0, 0, 0 ; D2100000 02021E4A V_MAD_F32 v0, s72, v14, v0, 0, 0, 0, 0 ; D2820000 04021C48 V_MAD_F32 v0, s69, v12, v0, 0, 0, 0, 0 ; D2820000 04021845 V_MUL_F32_e32 v1, v0, v0 ; 10020100 V_MAD_F32 v1, v17, v17, v1, 0, 0, 0, 0 ; D2820001 04062311 V_MUL_F32_e64 v13, s71, v15, 0, 0, 0, 0 ; D210000D 02021E47 V_MAD_F32 v13, s31, v14, v13, 0, 0, 0, 0 ; D282000D 04361C1F V_MAD_F32 v12, s30, v12, v13, 0, 0, 0, 0 ; D282000C 0436181E V_MAD_F32 v1, v12, v12, v1, 0, 0, 0, 0 ; D2820001 0406190C V_RSQ_LEGACY_F32_e32 v19, v1 ; 7E265B01 V_MUL_F32_e32 v0, v0, v19 ; 10002700 V_READLANE_B32 s10, v42, 0 ; 0215012A V_MUL_F32_e64 v1, s10, v10, 0, 0, 0, 0 ; D2100001 0202140A V_READLANE_B32 s10, v42, 1 ; 0215032A V_MAD_F32 v1, s10, v9, v1, 0, 0, 0, 0 ; D2820001 0406120A V_READLANE_B32 s10, v42, 2 ; 0215052A V_MAD_F32 v1, s10, v11, v1, 0, 0, 0, 0 ; D2820001 0406160A V_READLANE_B32 s10, v42, 3 ; 0215072A V_ADD_F32_e32 v13, s10, v1 ; 061A020A V_READLANE_B32 s10, v42, 4 ; 0215092A V_SUBREV_F32_e32 v16, s10, v13 ; 0A201A0A V_READLANE_B32 s10, v42, 5 ; 02150B2A V_MUL_F32_e64 v1, s10, v10, 0, 0, 0, 0 ; D2100001 0202140A V_READLANE_B32 s10, v42, 6 ; 02150D2A V_MAD_F32 v1, s10, v9, v1, 0, 0, 0, 0 ; D2820001 0406120A V_READLANE_B32 s10, v42, 7 ; 02150F2A V_MAD_F32 v1, s10, v11, v1, 0, 0, 0, 0 ; D2820001 0406160A V_READLANE_B32 s10, v42, 8 ; 0215112A V_ADD_F32_e32 v14, s10, v1 ; 061C020A V_READLANE_B32 s10, v42, 9 ; 0215132A V_SUBREV_F32_e32 v1, s10, v14 ; 0A021C0A V_MUL_F32_e32 v15, v1, v1 ; 101E0301 V_MAD_F32 v18, v16, v16, v15, 0, 0, 0, 0 ; D2820012 043E2110 V_MUL_F32_e64 v10, s79, v10, 0, 0, 0, 0 ; D210000A 0202144F V_MAD_F32 v9, s82, v9, v10, 0, 0, 0, 0 ; D2820009 042A1252 V_MAD_F32 v9, s83, v11, v9, 0, 0, 0, 0 ; D2820009 04261653 V_ADD_F32_e32 v15, s100, v9 ; 061E1264 V_SUBREV_F32_e32 v10, s28, v15 ; 0A141E1C V_MAD_F32 v9, v10, v10, v18, 0, 0, 0, 0 ; D2820009 044A150A V_RSQ_LEGACY_F32_e32 v11, v9 ; 7E165B09 V_MUL_F32_e32 v18, v1, v11 ; 10241701 V_MUL_F32_e32 v9, v0, v18 ; 10122500 V_MUL_F32_e32 v1, v17, v19 ; 10022711 V_MUL_F32_e32 v16, v16, v11 ; 10201710 V_MAD_F32 v20, v1, v16, v9, 0, 0, 0, 0 ; D2820014 04262101 V_MUL_F32_e32 v9, v12, v19 ; 1012270C V_MUL_F32_e32 v12, v10, v11 ; 1018170A V_MAD_F32 v20, v9, v12, v20, 0, 0, 0, 0 ; D2820014 04521909 V_MUL_F32_e32 v10, v20, v1 ; 10140314 V_MAD_F32 v10, v20, v1, v10, 0, 0, 0, 0 ; D282000A 042A0314 V_SUB_F32_e32 v10, v16, v10 ; 08141510 V_MUL_F32_e32 v11, v20, v0 ; 10160114 V_MAD_F32 v11, v20, v0, v11, 0, 0, 0, 0 ; D282000B 042E0114 V_SUB_F32_e32 v11, v18, v11 ; 08161712 S_LOAD_DWORDX4 s[16:19], s[0:1], 8 ; C0880108 S_WAITCNT lgkmcnt(0) ; BF8C007F S_BUFFER_LOAD_DWORD s10, s[16:19], 48 ; C2051130 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v16, s10, v11 ; 1020160A S_BUFFER_LOAD_DWORD s11, s[16:19], 49 ; C2059131 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v16, v10, s11, v16, 0, 0, 0, 0 ; D2820010 0440170A V_MUL_F32_e32 v18, v20, v9 ; 10241314 V_MAD_F32 v18, v20, v9, v18, 0, 0, 0, 0 ; D2820012 044A1314 V_SUB_F32_e32 v12, v12, v18 ; 0818250C S_BUFFER_LOAD_DWORD s20, s[16:19], 50 ; C20A1132 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v16, v12, s20, v16, 0, 0, 0, 0 ; D2820010 0440290C V_MOV_B32_e32 v18, 1.000000e-03 ; 7E2402FF 3A83126F V_CMP_LE_F32_e64 s[0:1], v16, v18, 0, 0, 0, 0 ; D0060000 02022510 V_CMP_U_F32_e64 s[22:23], v16, v16, 0, 0, 0, 0 ; D0100016 02022110 S_OR_B64 s[0:1], s[0:1], s[22:23] ; 88801600 V_CNDMASK_B32_e64 v16, v16, v18, s[0:1], 0, 0, 0, 0 ; D2000010 00022510 V_LOG_F32_e32 v16, v16 ; 7E204F10 V_MUL_LEGACY_F32_e32 v16, s6, v16 ; 0E202006 V_EXP_F32_e32 v16, v16 ; 7E204B10 S_BUFFER_LOAD_DWORD s21, s[16:19], 61 ; C20A913D S_WAITCNT lgkmcnt(0) ; BF8C007F V_SUBREV_F32_e32 v18, s21, v13 ; 0A241A15 S_BUFFER_LOAD_DWORD s22, s[16:19], 60 ; C20B113C S_WAITCNT lgkmcnt(0) ; BF8C007F V_SUBREV_F32_e32 v20, s22, v14 ; 0A281C16 V_MUL_F32_e32 v20, v20, v20 ; 10282914 V_MAD_F32 v18, v18, v18, v20, 0, 0, 0, 0 ; D2820012 04522512 S_BUFFER_LOAD_DWORD s23, s[16:19], 62 ; C20B913E S_WAITCNT lgkmcnt(0) ; BF8C007F V_SUBREV_F32_e32 v20, s23, v15 ; 0A281E17 V_MAD_F32 v18, v20, v20, v18, 0, 0, 0, 0 ; D2820012 044A2914 V_RSQ_LEGACY_F32_e32 v20, v18 ; 7E285B12 V_MUL_F32_e32 v20, v20, v18 ; 10282514 V_XOR_B32_e32 v18, -2147483648, v18 ; 3A2424FF 80000000 V_CMP_GT_F32_e64 s[0:1], 0, v18, 0, 0, 0, 0 ; D0080000 02022480 V_CNDMASK_B32_e64 v18, 0.000000e+00, v20, s[0:1], 0, 0, 0, 0 ; D2000012 00022880 S_BUFFER_LOAD_DWORD s28, s[16:19], 64 ; C20E1140 V_MOV_B32_e32 v20, 8.000000e-01 ; 7E2802FF 3F4CCCCD S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v20, s28, v20 ; 1028281C V_CMP_LT_F32_e64 s[0:1], v18, v20, 0, 0, 0, 0 ; D0020000 02022912 V_CNDMASK_B32_e64 v20, 0, -1, s[0:1], 0, 0, 0, 0 ; D2000014 00018280 V_CMP_EQ_I32_e64 s[0:1], v20, 0, 0, 0, 0, 0 ; D1040000 02010114 V_MOV_B32_e32 v20, 1.050000e+00 ; 7E2802FF 3F866666 V_MAD_F32 v17, v17, v19, v20, 0, 0, 0, 0 ; D2820011 04522711 V_ADD_F32_e64 v17, 0, v17, 0, 1, 0, 0 ; D2060811 02022280 S_AND_SAVEEXEC_B64 s[0:1], s[0:1] ; BE802400 S_XOR_B64 s[0:1], exec, s[0:1] ; 8980007E S_CBRANCH_EXECZ BB0_5 ; BF880000 V_CMP_LT_F32_e64 s[24:25], s28, v18, 0, 0, 0, 0 ; D0020018 0202241C V_CNDMASK_B32_e64 v19, 0, -1, s[24:25], 0, 0, 0, 0 ; D2000013 00618280 V_CMP_EQ_I32_e64 s[30:31], v19, 0, 0, 0, 0, 0 ; D104001E 02010113 S_LOAD_DWORDX4 s[24:27], s[2:3], 4 ; C08C0304 S_LOAD_DWORDX8 s[44:51], s[4:5], 8 ; C0D60508 S_WAITCNT lgkmcnt(0) ; BF8C007F S_AND_SAVEEXEC_B64 s[2:3], s[30:31] ; BE82241E S_XOR_B64 s[2:3], exec, s[2:3] ; 8982027E S_CBRANCH_EXECZ BB0_10 ; BF880000 V_MOV_B32_e32 v19, -8.000000e-01 ; 7E2602FF BF4CCCCD V_MAD_F32 v18, s28, v19, v18, 0, 0, 0, 0 ; D2820012 044A261C V_MOV_B32_e32 v20, s28 ; 7E28021C V_MAD_F32 v19, s28, v19, v20, 0, 0, 0, 0 ; D2820013 0452261C V_RCP_F32_e32 v19, v19 ; 7E265513 V_MUL_F32_e32 v18, v18, v19 ; 10242712 V_ADD_F32_e64 v18, 0, v18, 0, 1, 0, 0 ; D2060812 02022480 V_ADD_F32_e32 v19, v18, v18 ; 06262512 V_SUB_F32_e32 v19, 3.000000e+00, v19 ; 082626FF 40400000 V_MUL_F32_e32 v19, v18, v19 ; 10262712 V_MUL_F32_e32 v18, v18, v19 ; 10242712 V_SUB_F32_e32 v19, 1.000000e+00, v18 ; 082624F2 S_BUFFER_LOAD_DWORD s4, s[16:19], 18 ; C2021112 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v20, s4, v14, 0, 0, 0, 0 ; D2100014 02021C04 S_BUFFER_LOAD_DWORD s4, s[16:19], 22 ; C2021116 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v20, s4, v13, v20, 0, 0, 0, 0 ; D2820014 04521A04 S_BUFFER_LOAD_DWORD s4, s[16:19], 26 ; C202111A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v20, s4, v15, v20, 0, 0, 0, 0 ; D2820014 04521E04 S_BUFFER_LOAD_DWORD s4, s[16:19], 30 ; C202111E S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v20, s4, v20 ; 06282804 V_CMP_U_F32_e64 s[4:5], v20, v20, 0, 0, 0, 0 ; D0100004 02022914 V_CMP_GE_F32_e64 s[28:29], v20, -1.000000e+00, 0, 0, 0, 0 ; D00C001C 0201E714 S_OR_B64 s[4:5], s[28:29], s[4:5] ; 8884041C V_CNDMASK_B32_e64 v20, -1.000000e+00, v20, s[4:5], 0, 0, 0, 0 ; D2000014 001228F3 V_CMP_U_F32_e64 s[4:5], v20, v20, 0, 0, 0, 0 ; D0100004 02022914 V_CMP_GE_F32_e64 s[28:29], v20, 1.000000e+00, 0, 0, 0, 0 ; D00C001C 0201E514 S_OR_B64 s[4:5], s[28:29], s[4:5] ; 8884041C V_CNDMASK_B32_e64 v20, v20, 1.000000e+00, s[4:5], 0, 0, 0, 0 ; D2000014 0011E514 V_ADD_F32_e32 v20, 1.000000e+00, v20 ; 062828F2 S_BUFFER_LOAD_DWORD s4, s[16:19], 63 ; C202113F V_MOV_B32_e32 v21, -2147483648 ; 7E2A02FF 80000000 S_WAITCNT lgkmcnt(0) ; BF8C007F V_XOR_B32_e32 v21, s4, v21 ; 3A2A2A04 V_MUL_F32_e32 v20, v21, v20 ; 10282915 V_MUL_F32_e32 v20, 7.213475e-01, v20 ; 102828FF 3F38AA3B V_EXP_F32_e32 v20, v20 ; 7E284B14 S_BUFFER_LOAD_DWORD s4, s[16:19], 17 ; C2021111 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v22, s4, v14, 0, 0, 0, 0 ; D2100016 02021C04 S_BUFFER_LOAD_DWORD s4, s[16:19], 21 ; C2021115 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v22, s4, v13, v22, 0, 0, 0, 0 ; D2820016 045A1A04 S_BUFFER_LOAD_DWORD s4, s[16:19], 25 ; C2021119 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v22, s4, v15, v22, 0, 0, 0, 0 ; D2820016 045A1E04 S_BUFFER_LOAD_DWORD s4, s[16:19], 29 ; C202111D S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v22, s4, v22 ; 062C2C04 V_MAD_F32 v22, v22, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0 ; D2820016 03C1E116 S_BUFFER_LOAD_DWORD s4, s[16:19], 66 ; C2021142 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v23, s4, v22 ; 102E2C04 S_BUFFER_LOAD_DWORD s5, s[16:19], 16 ; C2029110 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v24, s5, v14, 0, 0, 0, 0 ; D2100018 02021C05 S_BUFFER_LOAD_DWORD s5, s[16:19], 20 ; C2029114 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v24, s5, v13, v24, 0, 0, 0, 0 ; D2820018 04621A05 S_BUFFER_LOAD_DWORD s5, s[16:19], 24 ; C2029118 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v24, s5, v15, v24, 0, 0, 0, 0 ; D2820018 04621E05 S_BUFFER_LOAD_DWORD s5, s[16:19], 28 ; C202911C S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v24, s5, v24 ; 06303005 V_MAD_F32 v24, v24, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0 ; D2820018 03C1E118 V_MUL_F32_e32 v22, s4, v24 ; 102C3004 IMAGE_SAMPLE v22, 1, -1, 0, 0, 0, 0, 0, 0, v[22:23], s[36:43], s[32:35] ; F0801100 01091616 S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v20, v20, v22 ; 10282D14 V_ADD_F32_e64 v20, 0, v20, 0, 1, 0, 0 ; D2060814 02022880 V_MUL_F32_e32 v19, v19, v20 ; 10262913 S_BUFFER_LOAD_DWORD s5, s[16:19], 34 ; C2029122 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v20, s5, v14, 0, 0, 0, 0 ; D2100014 02021C05 S_BUFFER_LOAD_DWORD s5, s[16:19], 38 ; C2029126 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v20, s5, v13, v20, 0, 0, 0, 0 ; D2820014 04521A05 S_BUFFER_LOAD_DWORD s5, s[16:19], 42 ; C202912A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v20, s5, v15, v20, 0, 0, 0, 0 ; D2820014 04521E05 S_BUFFER_LOAD_DWORD s5, s[16:19], 46 ; C202912E S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v20, s5, v20 ; 06282805 V_CMP_U_F32_e64 s[28:29], v20, v20, 0, 0, 0, 0 ; D010001C 02022914 V_CMP_GE_F32_e64 s[30:31], v20, -1.000000e+00, 0, 0, 0, 0 ; D00C001E 0201E714 S_OR_B64 s[28:29], s[30:31], s[28:29] ; 889C1C1E V_CNDMASK_B32_e64 v20, -1.000000e+00, v20, s[28:29], 0, 0, 0, 0 ; D2000014 007228F3 V_CMP_U_F32_e64 s[28:29], v20, v20, 0, 0, 0, 0 ; D010001C 02022914 V_CMP_GE_F32_e64 s[30:31], v20, 1.000000e+00, 0, 0, 0, 0 ; D00C001E 0201E514 S_OR_B64 s[28:29], s[30:31], s[28:29] ; 889C1C1E V_CNDMASK_B32_e64 v20, v20, 1.000000e+00, s[28:29], 0, 0, 0, 0 ; D2000014 0071E514 V_ADD_F32_e32 v20, 1.000000e+00, v20 ; 062828F2 V_MUL_F32_e32 v20, v21, v20 ; 10282915 V_MUL_F32_e32 v20, 7.213475e-01, v20 ; 102828FF 3F38AA3B V_EXP_F32_e32 v20, v20 ; 7E284B14 S_BUFFER_LOAD_DWORD s5, s[16:19], 33 ; C2029121 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v21, s5, v14, 0, 0, 0, 0 ; D2100015 02021C05 S_BUFFER_LOAD_DWORD s5, s[16:19], 37 ; C2029125 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v21, s5, v13, v21, 0, 0, 0, 0 ; D2820015 04561A05 S_BUFFER_LOAD_DWORD s5, s[16:19], 41 ; C2029129 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v21, s5, v15, v21, 0, 0, 0, 0 ; D2820015 04561E05 S_BUFFER_LOAD_DWORD s5, s[16:19], 45 ; C202912D S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v21, s5, v21 ; 062A2A05 V_MAD_F32 v21, v21, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0 ; D2820015 03C1E115 V_MUL_F32_e32 v22, s4, v21 ; 102C2A04 S_BUFFER_LOAD_DWORD s5, s[16:19], 32 ; C2029120 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v23, s5, v14, 0, 0, 0, 0 ; D2100017 02021C05 S_BUFFER_LOAD_DWORD s5, s[16:19], 36 ; C2029124 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v23, s5, v13, v23, 0, 0, 0, 0 ; D2820017 045E1A05 S_BUFFER_LOAD_DWORD s5, s[16:19], 40 ; C2029128 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v23, s5, v15, v23, 0, 0, 0, 0 ; D2820017 045E1E05 S_BUFFER_LOAD_DWORD s5, s[16:19], 44 ; C202912C S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v23, s5, v23 ; 062E2E05 V_MAD_F32 v23, v23, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0 ; D2820017 03C1E117 V_MUL_F32_e32 v21, s4, v23 ; 102A2E04 IMAGE_SAMPLE v21, 1, -1, 0, 0, 0, 0, 0, 0, v[21:22], s[44:51], s[24:27] ; F0801100 00CB1515 S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v20, v20, v21 ; 10282B14 V_ADD_F32_e64 v20, 0, v20, 0, 1, 0, 0 ; D2060814 02022880 V_MAD_F32 v24, v18, v20, v19, 0, 0, 0, 0 ; D2820018 044E2912 S_OR_SAVEEXEC_B64 s[2:3], s[2:3] ; BE822502 S_XOR_B64 exec, exec, s[2:3] ; 89FE027E S_CBRANCH_EXECZ BB0_8 ; BF880000 V_MOV_B32_e32 v18, s21 ; 7E240215 V_SUB_F32_e64 v18, v13, v18, 0, 0, 0, 0 ; D2080012 0202250D V_MOV_B32_e32 v19, s22 ; 7E260216 V_SUB_F32_e64 v19, v14, v19, 0, 0, 0, 0 ; D2080013 0202270E V_MUL_F32_e32 v19, v19, v19 ; 10262713 V_MAD_F32 v18, v18, v18, v19, 0, 0, 0, 0 ; D2820012 044E2512 V_MOV_B32_e32 v19, s23 ; 7E260217 V_SUB_F32_e64 v19, v15, v19, 0, 0, 0, 0 ; D2080013 0202270F V_MAD_F32 v18, v19, v19, v18, 0, 0, 0, 0 ; D2820012 044A2713 V_RSQ_LEGACY_F32_e32 v19, v18 ; 7E265B12 V_MUL_F32_e32 v19, v19, v18 ; 10262513 V_XOR_B32_e32 v18, -2147483648, v18 ; 3A2424FF 80000000 V_CMP_GT_F32_e64 s[4:5], 0, v18, 0, 0, 0, 0 ; D0080004 02022480 V_CNDMASK_B32_e64 v18, 0.000000e+00, v19, s[4:5], 0, 0, 0, 0 ; D2000012 00122680 S_BUFFER_LOAD_DWORD s4, s[16:19], 65 ; C2021141 S_WAITCNT lgkmcnt(0) ; BF8C007F V_RCP_F32_e32 v19, s4 ; 7E265404 V_MOV_B32_e32 v20, -8.000000e-01 ; 7E2802FF BF4CCCCD V_MAD_F32 v18, v18, v19, v20, 0, 0, 0, 0 ; D2820012 04522712 V_MUL_F32_e32 v18, 5.000000e+00, v18 ; 102424FF 40A00001 V_ADD_F32_e64 v18, 0, v18, 0, 1, 0, 0 ; D2060812 02022480 V_ADD_F32_e32 v19, v18, v18 ; 06262512 V_SUB_F32_e32 v19, 3.000000e+00, v19 ; 082626FF 40400000 V_MUL_F32_e32 v19, v18, v19 ; 10262712 V_MUL_F32_e32 v20, v18, v19 ; 10282712 V_SUB_F32_e32 v20, 1.000000e+00, v20 ; 082828F2 S_BUFFER_LOAD_DWORD s4, s[16:19], 34 ; C2021122 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v21, s4, v14, 0, 0, 0, 0 ; D2100015 02021C04 S_BUFFER_LOAD_DWORD s4, s[16:19], 38 ; C2021126 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v21, s4, v13, v21, 0, 0, 0, 0 ; D2820015 04561A04 S_BUFFER_LOAD_DWORD s4, s[16:19], 42 ; C202112A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v21, s4, v15, v21, 0, 0, 0, 0 ; D2820015 04561E04 S_BUFFER_LOAD_DWORD s4, s[16:19], 46 ; C202112E S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v21, s4, v21 ; 062A2A04 V_CMP_U_F32_e64 s[4:5], v21, v21, 0, 0, 0, 0 ; D0100004 02022B15 V_CMP_GE_F32_e64 s[22:23], v21, -1.000000e+00, 0, 0, 0, 0 ; D00C0016 0201E715 S_OR_B64 s[4:5], s[22:23], s[4:5] ; 88840416 V_CNDMASK_B32_e64 v21, -1.000000e+00, v21, s[4:5], 0, 0, 0, 0 ; D2000015 00122AF3 V_CMP_U_F32_e64 s[4:5], v21, v21, 0, 0, 0, 0 ; D0100004 02022B15 V_CMP_GE_F32_e64 s[22:23], v21, 1.000000e+00, 0, 0, 0, 0 ; D00C0016 0201E515 S_OR_B64 s[4:5], s[22:23], s[4:5] ; 88840416 V_CNDMASK_B32_e64 v21, v21, 1.000000e+00, s[4:5], 0, 0, 0, 0 ; D2000015 0011E515 V_ADD_F32_e32 v21, 1.000000e+00, v21 ; 062A2AF2 S_BUFFER_LOAD_DWORD s4, s[16:19], 63 ; C202113F S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v21, s4, v21 ; 102A2A04 V_MUL_F32_e32 v21, -7.213475e-01, v21 ; 102A2AFF BF38AA3B V_EXP_F32_e32 v21, v21 ; 7E2A4B15 S_BUFFER_LOAD_DWORD s4, s[16:19], 33 ; C2021121 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v22, s4, v14, 0, 0, 0, 0 ; D2100016 02021C04 S_BUFFER_LOAD_DWORD s4, s[16:19], 37 ; C2021125 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v22, s4, v13, v22, 0, 0, 0, 0 ; D2820016 045A1A04 S_BUFFER_LOAD_DWORD s4, s[16:19], 41 ; C2021129 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v22, s4, v15, v22, 0, 0, 0, 0 ; D2820016 045A1E04 S_BUFFER_LOAD_DWORD s4, s[16:19], 45 ; C202112D S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v22, s4, v22 ; 062C2C04 V_MAD_F32 v22, v22, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0 ; D2820016 03C1E116 S_BUFFER_LOAD_DWORD s4, s[16:19], 66 ; C2021142 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v23, s4, v22 ; 102E2C04 S_BUFFER_LOAD_DWORD s5, s[16:19], 32 ; C2029120 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v24, s5, v14, 0, 0, 0, 0 ; D2100018 02021C05 S_BUFFER_LOAD_DWORD s5, s[16:19], 36 ; C2029124 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v24, s5, v13, v24, 0, 0, 0, 0 ; D2820018 04621A05 S_BUFFER_LOAD_DWORD s5, s[16:19], 40 ; C2029128 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v24, s5, v15, v24, 0, 0, 0, 0 ; D2820018 04621E05 S_BUFFER_LOAD_DWORD s5, s[16:19], 44 ; C202912C S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v24, s5, v24 ; 06303005 V_MAD_F32 v24, v24, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0 ; D2820018 03C1E118 V_MUL_F32_e32 v22, s4, v24 ; 102C3004 IMAGE_SAMPLE v22, 1, -1, 0, 0, 0, 0, 0, 0, v[22:23], s[44:51], s[24:27] ; F0801100 00CB1616 S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v21, v21, v22 ; 102A2D15 V_ADD_F32_e64 v21, 0, v21, 0, 1, 0, 0 ; D2060815 02022A80 V_MUL_F32_e32 v20, v20, v21 ; 10282B14 V_MAD_F32 v24, v18, v19, v20, 0, 0, 0, 0 ; D2820018 04522712 S_OR_B64 exec, exec, s[2:3] ; 88FE027E S_OR_SAVEEXEC_B64 s[0:1], s[0:1] ; BE802500 S_BUFFER_LOAD_DWORD s2, s[12:15], 12 ; C2010D0C S_BUFFER_LOAD_DWORD s3, s[16:19], 54 ; C2019136 S_BUFFER_LOAD_DWORD s4, s[16:19], 53 ; C2021135 S_BUFFER_LOAD_DWORD s5, s[16:19], 52 ; C2029134 S_BUFFER_LOAD_DWORD s21, s[16:19], 58 ; C20A913A S_BUFFER_LOAD_DWORD s22, s[16:19], 57 ; C20B1139 S_BUFFER_LOAD_DWORD s23, s[16:19], 56 ; C20B9138 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v23, s3 ; 7E2E0203 V_MOV_B32_e32 v20, s4 ; 7E280204 V_MOV_B32_e32 v18, s5 ; 7E240205 V_MOV_B32_e32 v25, s20 ; 7E320214 V_MOV_B32_e32 v26, s11 ; 7E34020B V_MOV_B32_e32 v27, s10 ; 7E36020A V_MOV_B32_e32 v22, s21 ; 7E2C0215 V_MOV_B32_e32 v21, s22 ; 7E2A0216 V_MOV_B32_e32 v19, s23 ; 7E260217 S_XOR_B64 exec, exec, s[0:1] ; 89FE007E S_CBRANCH_EXECZ BB0_9 ; BF880000 S_BUFFER_LOAD_DWORD s3, s[16:19], 18 ; C2019112 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v24, s3, v14, 0, 0, 0, 0 ; D2100018 02021C03 S_BUFFER_LOAD_DWORD s3, s[16:19], 22 ; C2019116 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v24, s3, v13, v24, 0, 0, 0, 0 ; D2820018 04621A03 S_BUFFER_LOAD_DWORD s3, s[16:19], 26 ; C201911A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v24, s3, v15, v24, 0, 0, 0, 0 ; D2820018 04621E03 S_BUFFER_LOAD_DWORD s3, s[16:19], 30 ; C201911E S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v24, s3, v24 ; 06303003 V_CMP_U_F32_e64 s[4:5], v24, v24, 0, 0, 0, 0 ; D0100004 02023118 V_CMP_GE_F32_e64 s[10:11], v24, -1.000000e+00, 0, 0, 0, 0 ; D00C000A 0201E718 S_OR_B64 s[4:5], s[10:11], s[4:5] ; 8884040A V_CNDMASK_B32_e64 v24, -1.000000e+00, v24, s[4:5], 0, 0, 0, 0 ; D2000018 001230F3 V_CMP_U_F32_e64 s[4:5], v24, v24, 0, 0, 0, 0 ; D0100004 02023118 V_CMP_GE_F32_e64 s[10:11], v24, 1.000000e+00, 0, 0, 0, 0 ; D00C000A 0201E518 S_OR_B64 s[4:5], s[10:11], s[4:5] ; 8884040A V_CNDMASK_B32_e64 v24, v24, 1.000000e+00, s[4:5], 0, 0, 0, 0 ; D2000018 0011E518 V_ADD_F32_e32 v24, 1.000000e+00, v24 ; 063030F2 S_BUFFER_LOAD_DWORD s3, s[16:19], 63 ; C201913F S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v24, s3, v24 ; 10303003 V_MUL_F32_e32 v24, -7.213475e-01, v24 ; 103030FF BF38AA3B V_EXP_F32_e32 v24, v24 ; 7E304B18 S_BUFFER_LOAD_DWORD s3, s[16:19], 17 ; C2019111 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v28, s3, v14, 0, 0, 0, 0 ; D210001C 02021C03 S_BUFFER_LOAD_DWORD s3, s[16:19], 21 ; C2019115 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v28, s3, v13, v28, 0, 0, 0, 0 ; D282001C 04721A03 S_BUFFER_LOAD_DWORD s3, s[16:19], 25 ; C2019119 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v28, s3, v15, v28, 0, 0, 0, 0 ; D282001C 04721E03 S_BUFFER_LOAD_DWORD s3, s[16:19], 29 ; C201911D S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v28, s3, v28 ; 06383803 V_MAD_F32 v28, v28, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0 ; D282001C 03C1E11C S_BUFFER_LOAD_DWORD s3, s[16:19], 66 ; C2019142 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v29, s3, v28 ; 103A3803 S_BUFFER_LOAD_DWORD s4, s[16:19], 16 ; C2021110 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v30, s4, v14, 0, 0, 0, 0 ; D210001E 02021C04 S_BUFFER_LOAD_DWORD s4, s[16:19], 20 ; C2021114 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v30, s4, v13, v30, 0, 0, 0, 0 ; D282001E 047A1A04 S_BUFFER_LOAD_DWORD s4, s[16:19], 24 ; C2021118 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v30, s4, v15, v30, 0, 0, 0, 0 ; D282001E 047A1E04 S_BUFFER_LOAD_DWORD s4, s[16:19], 28 ; C202111C S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v30, s4, v30 ; 063C3C04 V_MAD_F32 v30, v30, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0 ; D282001E 03C1E11E V_MUL_F32_e32 v28, s3, v30 ; 10383C03 IMAGE_SAMPLE v28, 1, -1, 0, 0, 0, 0, 0, 0, v[28:29], s[36:43], s[32:35] ; F0801100 01091C1C S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v24, v24, v28 ; 10303918 V_ADD_F32_e64 v24, 0, v24, 0, 1, 0, 0 ; D2060818 02023080 S_OR_B64 exec, exec, s[0:1] ; 88FE007E V_MUL_F32_e64 v27, v0, v27, 0, 0, 0, 0 ; D210001B 02023700 V_MAD_F32 v26, v1, v26, v27, 0, 0, 0, 0 ; D282001A 046E3501 V_MAD_F32 v25, v9, v25, v26, 0, 0, 0, 0 ; D2820019 046A3309 V_CMP_U_F32_e64 s[0:1], v25, v25, 0, 0, 0, 0 ; D0100000 02023319 V_CMP_LE_F32_e64 s[4:5], v25, 0.000000e+00, 0, 0, 0, 0 ; D0060004 02010119 S_OR_B64 s[0:1], s[4:5], s[0:1] ; 88800004 V_CNDMASK_B32_e64 v25, v25, 0.000000e+00, s[0:1], 0, 0, 0, 0 ; D2000019 00010119 V_MUL_F32_e32 v26, v23, v25 ; 10343317 V_MUL_F32_e32 v26, v2, v26 ; 10343502 V_MUL_F32_e64 v23, v16, v23, 0, 0, 0, 0 ; D2100017 02022F10 V_MAD_F32 v23, v23, s7, v26, 0, 0, 0, 0 ; D2820017 04680F17 V_MOV_B32_e32 v26, -8.000000e-01 ; 7E3402FF BF4CCCCD V_ADD_F32_e32 v24, v24, v26 ; 06303518 V_MUL_F32_e32 v24, 5.000000e+00, v24 ; 103030FF 40A00001 V_ADD_F32_e64 v24, 0, v24, 0, 1, 0, 0 ; D2060818 02023080 V_ADD_F32_e32 v26, v24, v24 ; 06343118 V_SUB_F32_e32 v26, 3.000000e+00, v26 ; 083434FF 40400000 V_MUL_F32_e32 v26, v24, v26 ; 10343518 V_MUL_F32_e32 v24, v24, v26 ; 10303518 V_MUL_F32_e32 v23, v23, v24 ; 102E3117 V_MUL_F32_e64 v22, v17, v22, 0, 0, 0, 0 ; D2100016 02022D11 V_MAD_F32 v22, v2, v22, v23, 0, 0, 0, 0 ; D2820016 045E2D02 V_MUL_F32_e32 v23, v20, v25 ; 102E3314 V_MUL_F32_e32 v23, v3, v23 ; 102E2F03 V_MUL_F32_e64 v20, v16, v20, 0, 0, 0, 0 ; D2100014 02022910 V_MAD_F32 v20, v20, s8, v23, 0, 0, 0, 0 ; D2820014 045C1114 V_MUL_F32_e32 v20, v20, v24 ; 10283114 V_MUL_F32_e64 v21, v17, v21, 0, 0, 0, 0 ; D2100015 02022B11 V_MAD_F32 v21, v3, v21, v20, 0, 0, 0, 0 ; D2820015 04522B03 V_MUL_F32_e32 v20, v18, v25 ; 10283312 V_MUL_F32_e32 v20, v4, v20 ; 10282904 V_MUL_F32_e64 v16, v16, v18, 0, 0, 0, 0 ; D2100010 02022510 V_MAD_F32 v16, v16, s9, v20, 0, 0, 0, 0 ; D2820010 04501310 V_MUL_F32_e32 v16, v16, v24 ; 10203110 V_MUL_F32_e64 v17, v17, v19, 0, 0, 0, 0 ; D2100011 02022711 V_MAD_F32 v23, v4, v17, v16, 0, 0, 0, 0 ; D2820017 04422304 V_MOV_B32_e32 v16, -2147483648 ; 7E2002FF 80000000 V_XOR_B32_e32 v15, v15, v16 ; 3A1E210F V_XOR_B32_e32 v13, v13, v16 ; 3A1A210D V_XOR_B32_e32 v14, v14, v16 ; 3A1C210E V_MOV_B32_e32 v16, 0.000000e+00 ; 7E200280 S_MOV_B64 s[0:1], 0 ; BE800480 V_MOV_B32_e32 v17, s2 ; 7E220202 V_MOV_B32_e32 v18, v23 ; 7E240317 V_MOV_B32_e32 v19, v21 ; 7E260315 V_MOV_B32_e32 v20, v22 ; 7E280316 V_CMP_GE_I32_e64 s[2:3], v16, v17, 0, 0, 0, 0 ; D10C0002 02022310 V_CNDMASK_B32_e64 v21, 0, -1, s[2:3], 0, 0, 0, 0 ; D2000015 00098280 V_CMP_EQ_I32_e64 s[2:3], v21, 0, 0, 0, 0, 0 ; D1040002 02010115 S_AND_SAVEEXEC_B64 s[2:3], s[2:3] ; BE822402 S_XOR_B64 s[2:3], exec, s[2:3] ; 8982027E S_CBRANCH_EXECZ BB0_14 ; BF880000 V_MUL_LO_I32 v21, 7, v16, 0, 0, 0, 0, 0 ; D2D60015 02022087 V_LSHLREV_B32_e32 v23, 4, v21 ; 342E2A84 V_ADD_I32_e32 v21, 80, v23 ; 4A2A2EFF 00000050 BUFFER_LOAD_DWORD v21, s[12:15] + v21 + 0, glc=0, slc=0, tfe=0 ; E0301000 80031515 S_WAITCNT vmcnt(0) expcnt(0) ; BF8C0700 V_ADD_F32_e32 v21, v13, v21 ; 062A2B0D V_ADD_I32_e32 v22, 64, v23 ; 4A2C2EC0 BUFFER_LOAD_DWORD v22, s[12:15] + v22 + 0, glc=0, slc=0, tfe=0 ; E0301000 80031616 S_WAITCNT vmcnt(0) ; BF8C0770 V_ADD_F32_e32 v22, v14, v22 ; 062C2D0E V_MUL_F32_e32 v24, v22, v22 ; 10302D16 V_MAD_F32 v24, v21, v21, v24, 0, 0, 0, 0 ; D2820018 04622B15 V_ADD_I32_e32 v25, 96, v23 ; 4A322EFF 00000060 BUFFER_LOAD_DWORD v25, s[12:15] + v25 + 0, glc=0, slc=0, tfe=0 ; E0301000 80031919 S_WAITCNT vmcnt(0) ; BF8C0770 V_ADD_F32_e32 v25, v15, v25 ; 0632330F V_MAD_F32 v24, v25, v25, v24, 0, 0, 0, 0 ; D2820018 04623319 V_RSQ_LEGACY_F32_e32 v26, v24 ; 7E345B18 V_MUL_F32_e32 v26, v26, v24 ; 1034311A V_XOR_B32_e32 v24, -2147483648, v24 ; 3A3030FF 80000000 V_CMP_GT_F32_e64 s[4:5], 0, v24, 0, 0, 0, 0 ; D0080004 02023080 V_CNDMASK_B32_e64 v24, 0.000000e+00, v26, s[4:5], 0, 0, 0, 0 ; D2000018 00123480 V_RCP_F32_e32 v26, v24 ; 7E345518 V_MUL_F32_e32 v21, v21, v26 ; 102A3515 V_MUL_F32_e32 v22, v22, v26 ; 102C3516 V_MUL_F32_e32 v27, v0, v22 ; 10362D00 V_MAD_F32 v27, v1, v21, v27, 0, 0, 0, 0 ; D282001B 046E2B01 V_MUL_F32_e32 v25, v25, v26 ; 10323519 V_MAD_F32 v26, v9, v25, v27, 0, 0, 0, 0 ; D282001A 046E3309 V_CMP_U_F32_e64 s[4:5], v26, v26, 0, 0, 0, 0 ; D0100004 0202351A V_CMP_LE_F32_e64 s[10:11], v26, 0.000000e+00, 0, 0, 0, 0 ; D006000A 0201011A S_OR_B64 s[4:5], s[10:11], s[4:5] ; 8884040A V_CNDMASK_B32_e64 v26, v26, 0.000000e+00, s[4:5], 0, 0, 0, 0 ; D200001A 0011011A V_ADD_I32_e32 v27, 144, v23 ; 4A362EFF 00000090 BUFFER_LOAD_DWORD v27, s[12:15] + v27 + 0, glc=0, slc=0, tfe=0 ; E0301000 80031B1B S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v28, v26, v27 ; 1038371A V_MUL_F32_e32 v28, v2, v28 ; 10383902 V_MUL_F32_e32 v22, v11, v22 ; 102C2D0B V_MAD_F32 v21, v10, v21, v22, 0, 0, 0, 0 ; D2820015 045A2B0A V_MAD_F32 v21, v12, v25, v21, 0, 0, 0, 0 ; D2820015 0456330C V_MOV_B32_e32 v22, 1.000000e-03 ; 7E2C02FF 3A83126F V_CMP_LE_F32_e64 s[4:5], v21, v22, 0, 0, 0, 0 ; D0060004 02022D15 V_CMP_U_F32_e64 s[10:11], v21, v21, 0, 0, 0, 0 ; D010000A 02022B15 S_OR_B64 s[4:5], s[4:5], s[10:11] ; 88840A04 V_CNDMASK_B32_e64 v21, v21, v22, s[4:5], 0, 0, 0, 0 ; D2000015 00122D15 V_LOG_F32_e32 v21, v21 ; 7E2A4F15 V_MUL_LEGACY_F32_e32 v21, s6, v21 ; 0E2A2A06 V_EXP_F32_e32 v25, v21 ; 7E324B15 V_MUL_F32_e32 v21, v25, v27 ; 102A3719 V_MAD_F32 v21, v21, s7, v28, 0, 0, 0, 0 ; D2820015 04700F15 V_ADD_I32_e32 v22, 160, v23 ; 4A2C2EFF 000000A0 BUFFER_LOAD_DWORD v22, s[12:15] + v22 + 0, glc=0, slc=0, tfe=0 ; E0301000 80031616 S_WAITCNT vmcnt(0) ; BF8C0770 V_MAD_F32 v24, v22, -5.000000e-01, v24, 0, 0, 0, 0 ; D2820018 0461E316 V_MAD_F32 v22, v22, -5.000000e-01, v22, 0, 0, 0, 0 ; D2820016 0459E316 V_RCP_F32_e32 v22, v22 ; 7E2C5516 V_MUL_F32_e32 v22, v24, v22 ; 102C2D18 V_ADD_F32_e64 v22, 0, v22, 0, 1, 0, 0 ; D2060816 02022C80 V_ADD_F32_e32 v24, v22, v22 ; 06302D16 V_SUB_F32_e32 v24, 3.000000e+00, v24 ; 083030FF 40400000 V_MUL_F32_e32 v24, v22, v24 ; 10303116 V_MUL_F32_e32 v22, v22, v24 ; 102C3116 V_SUB_F32_e32 v24, 1.000000e+00, v22 ; 08302CF2 V_MAD_F32 v22, v21, v24, v20, 0, 0, 0, 0 ; D2820016 04523115 V_ADD_I32_e32 v21, 128, v23 ; 4A2A2EFF 00000080 BUFFER_LOAD_DWORD v21, s[12:15] + v21 + 0, glc=0, slc=0, tfe=0 ; E0301000 80031515 S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v27, v26, v21 ; 10362B1A V_MUL_F32_e32 v27, v3, v27 ; 10363703 V_MUL_F32_e32 v21, v25, v21 ; 102A2B19 V_MAD_F32 v21, v21, s8, v27, 0, 0, 0, 0 ; D2820015 046C1115 V_MAD_F32 v21, v21, v24, v19, 0, 0, 0, 0 ; D2820015 044E3115 V_ADD_I32_e32 v23, 112, v23 ; 4A2E2EFF 00000070 BUFFER_LOAD_DWORD v23, s[12:15] + v23 + 0, glc=0, slc=0, tfe=0 ; E0301000 80031717 S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v26, v26, v23 ; 10342F1A V_MUL_F32_e32 v26, v4, v26 ; 10343504 V_MUL_F32_e32 v23, v25, v23 ; 102E2F19 V_MAD_F32 v23, v23, s9, v26, 0, 0, 0, 0 ; D2820017 04681317 V_MAD_F32 v23, v23, v24, v18, 0, 0, 0, 0 ; D2820017 044A3117 V_ADD_I32_e32 v16, 1, v16 ; 4A202081 S_OR_B64 exec, exec, s[2:3] ; 88FE027E S_OR_B64 s[0:1], s[2:3], s[0:1] ; 88800002 S_ANDN2_B64 exec, exec, s[0:1] ; 8AFE007E S_CBRANCH_EXECNZ BB0_13 ; BF890000 S_OR_B64 exec, exec, s[0:1] ; 88FE007E V_CVT_PKRTZ_F16_F32_e64 v0, v20, v8, 0, 0, 0, 0 ; D25E0000 02021114 V_CVT_PKRTZ_F16_F32_e64 v1, v18, v19, 0, 0, 0, 0 ; D25E0001 02022712 EXP 15, 0, 1, 1, 1, v1, v0, v1, v0 ; F8001C0F 00010001 S_ENDPGM ; BF810000 VERT DCL IN[0] DCL IN[1] DCL IN[2] DCL OUT[0], POSITION DCL OUT[1], GENERIC[20] DCL OUT[2], GENERIC[21] DCL OUT[3], GENERIC[22] DCL CONST[0..3] DCL CONST[1][0..96] DCL CONST[2][0..68] DCL TEMP[0..5], LOCAL DCL ADDR[0] IMM[0] UINT32 {0, 48, 32, 16} IMM[1] INT32 {3, 2, 1, 0} IMM[2] UINT32 {176, 160, 144, 128} IMM[3] INT32 {11, 10, 9, 8} 0: MUL TEMP[0], CONST[0], IN[0].xxxx 1: MAD TEMP[0], CONST[1], IN[0].yyyy, TEMP[0] 2: MAD TEMP[0], CONST[2], IN[0].zzzz, TEMP[0] 3: ADD TEMP[0], TEMP[0], CONST[3] 4: UARL ADDR[0].x, IMM[1].xxxx 5: MOV TEMP[1], CONST[1][ADDR[0].x] 6: UARL ADDR[0].x, IMM[1].yyyy 7: MOV TEMP[2], CONST[1][ADDR[0].x] 8: UARL ADDR[0].x, IMM[1].zzzz 9: MOV TEMP[3], CONST[1][ADDR[0].x] 10: UARL ADDR[0].x, IMM[1].wwww 11: MOV TEMP[4], CONST[1][ADDR[0].x] 12: MUL TEMP[4], TEMP[4], TEMP[0].xxxx 13: MAD TEMP[3], TEMP[3], TEMP[0].yyyy, TEMP[4] 14: MAD TEMP[2], TEMP[2], TEMP[0].zzzz, TEMP[3] 15: MAD TEMP[1].xyz, TEMP[1], TEMP[0].wwww, TEMP[2] 16: UARL ADDR[0].x, IMM[3].xxxx 17: MOV TEMP[2], CONST[1][ADDR[0].x] 18: UARL ADDR[0].x, IMM[3].yyyy 19: MOV TEMP[3], CONST[1][ADDR[0].x] 20: UARL ADDR[0].x, IMM[3].zzzz 21: MOV TEMP[4], CONST[1][ADDR[0].x] 22: UARL ADDR[0].x, IMM[3].wwww 23: MOV TEMP[5], CONST[1][ADDR[0].x] 24: MUL TEMP[5], TEMP[5], TEMP[0].xxxx 25: MAD TEMP[4], TEMP[4], TEMP[0].yyyy, TEMP[5] 26: MAD TEMP[3], TEMP[3], TEMP[0].zzzz, TEMP[4] 27: MAD TEMP[0], TEMP[2], TEMP[0].wwww, TEMP[3] 28: MOV TEMP[2].xyz, IN[2].xyzx 29: MOV TEMP[2].w, TEMP[1].xxxx 30: MOV TEMP[1].xy, TEMP[1].yzyy 31: MOV TEMP[1].zw, IN[0].yyxy 32: MOV TEMP[3].x, IN[0].zzzz 33: MOV TEMP[3].yzw, IN[1].yxyz 34: MOV OUT[3], TEMP[3] 35: MOV OUT[1], TEMP[2] 36: MOV OUT[0], TEMP[0] 37: MOV OUT[2], TEMP[1] 38: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0 %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0 %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0) %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4) %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8) %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12) %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16) %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20) %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24) %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28) %20 = call float @llvm.SI.load.const(<16 x i8> %11, i32 32) %21 = call float @llvm.SI.load.const(<16 x i8> %11, i32 36) %22 = call float @llvm.SI.load.const(<16 x i8> %11, i32 40) %23 = call float @llvm.SI.load.const(<16 x i8> %11, i32 44) %24 = call float @llvm.SI.load.const(<16 x i8> %11, i32 48) %25 = call float @llvm.SI.load.const(<16 x i8> %11, i32 52) %26 = call float @llvm.SI.load.const(<16 x i8> %11, i32 56) %27 = call float @llvm.SI.load.const(<16 x i8> %11, i32 60) %28 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 1 %29 = load <16 x i8> addrspace(2)* %28, !tbaa !0 %30 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 0 %31 = load <16 x i8> addrspace(2)* %30, !tbaa !0 %32 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %31, i32 0, i32 %6) %33 = extractelement <4 x float> %32, i32 0 %34 = extractelement <4 x float> %32, i32 1 %35 = extractelement <4 x float> %32, i32 2 %36 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 1 %37 = load <16 x i8> addrspace(2)* %36, !tbaa !0 %38 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %37, i32 0, i32 %6) %39 = extractelement <4 x float> %38, i32 0 %40 = extractelement <4 x float> %38, i32 1 %41 = extractelement <4 x float> %38, i32 2 %42 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 2 %43 = load <16 x i8> addrspace(2)* %42, !tbaa !0 %44 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %43, i32 0, i32 %6) %45 = extractelement <4 x float> %44, i32 0 %46 = extractelement <4 x float> %44, i32 1 %47 = extractelement <4 x float> %44, i32 2 %48 = fmul float %12, %33 %49 = fmul float %13, %33 %50 = fmul float %14, %33 %51 = fmul float %15, %33 %52 = fmul float %16, %34 %53 = fadd float %52, %48 %54 = fmul float %17, %34 %55 = fadd float %54, %49 %56 = fmul float %18, %34 %57 = fadd float %56, %50 %58 = fmul float %19, %34 %59 = fadd float %58, %51 %60 = fmul float %20, %35 %61 = fadd float %60, %53 %62 = fmul float %21, %35 %63 = fadd float %62, %55 %64 = fmul float %22, %35 %65 = fadd float %64, %57 %66 = fmul float %23, %35 %67 = fadd float %66, %59 %68 = fadd float %61, %24 %69 = fadd float %63, %25 %70 = fadd float %65, %26 %71 = fadd float %67, %27 %72 = shl i32 3, 4 %73 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %72) %74 = shl i32 3, 4 %75 = add i32 %74, 4 %76 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %75) %77 = shl i32 3, 4 %78 = add i32 %77, 8 %79 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %78) %80 = shl i32 2, 4 %81 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %80) %82 = shl i32 2, 4 %83 = add i32 %82, 4 %84 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %83) %85 = shl i32 2, 4 %86 = add i32 %85, 8 %87 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %86) %88 = shl i32 1, 4 %89 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %88) %90 = shl i32 1, 4 %91 = add i32 %90, 4 %92 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %91) %93 = shl i32 1, 4 %94 = add i32 %93, 8 %95 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %94) %96 = shl i32 0, 4 %97 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %96) %98 = shl i32 0, 4 %99 = add i32 %98, 4 %100 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %99) %101 = shl i32 0, 4 %102 = add i32 %101, 8 %103 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %102) %104 = fmul float %97, %68 %105 = fmul float %100, %68 %106 = fmul float %103, %68 %107 = fmul float %89, %69 %108 = fadd float %107, %104 %109 = fmul float %92, %69 %110 = fadd float %109, %105 %111 = fmul float %95, %69 %112 = fadd float %111, %106 %113 = fmul float %81, %70 %114 = fadd float %113, %108 %115 = fmul float %84, %70 %116 = fadd float %115, %110 %117 = fmul float %87, %70 %118 = fadd float %117, %112 %119 = fmul float %73, %71 %120 = fadd float %119, %114 %121 = fmul float %76, %71 %122 = fadd float %121, %116 %123 = fmul float %79, %71 %124 = fadd float %123, %118 %125 = shl i32 11, 4 %126 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %125) %127 = shl i32 11, 4 %128 = add i32 %127, 4 %129 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %128) %130 = shl i32 11, 4 %131 = add i32 %130, 8 %132 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %131) %133 = shl i32 11, 4 %134 = add i32 %133, 12 %135 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %134) %136 = shl i32 10, 4 %137 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %136) %138 = shl i32 10, 4 %139 = add i32 %138, 4 %140 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %139) %141 = shl i32 10, 4 %142 = add i32 %141, 8 %143 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %142) %144 = shl i32 10, 4 %145 = add i32 %144, 12 %146 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %145) %147 = shl i32 9, 4 %148 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %147) %149 = shl i32 9, 4 %150 = add i32 %149, 4 %151 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %150) %152 = shl i32 9, 4 %153 = add i32 %152, 8 %154 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %153) %155 = shl i32 9, 4 %156 = add i32 %155, 12 %157 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %156) %158 = shl i32 8, 4 %159 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %158) %160 = shl i32 8, 4 %161 = add i32 %160, 4 %162 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %161) %163 = shl i32 8, 4 %164 = add i32 %163, 8 %165 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %164) %166 = shl i32 8, 4 %167 = add i32 %166, 12 %168 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %167) %169 = fmul float %159, %68 %170 = fmul float %162, %68 %171 = fmul float %165, %68 %172 = fmul float %168, %68 %173 = fmul float %148, %69 %174 = fadd float %173, %169 %175 = fmul float %151, %69 %176 = fadd float %175, %170 %177 = fmul float %154, %69 %178 = fadd float %177, %171 %179 = fmul float %157, %69 %180 = fadd float %179, %172 %181 = fmul float %137, %70 %182 = fadd float %181, %174 %183 = fmul float %140, %70 %184 = fadd float %183, %176 %185 = fmul float %143, %70 %186 = fadd float %185, %178 %187 = fmul float %146, %70 %188 = fadd float %187, %180 %189 = fmul float %126, %71 %190 = fadd float %189, %182 %191 = fmul float %129, %71 %192 = fadd float %191, %184 %193 = fmul float %132, %71 %194 = fadd float %193, %186 %195 = fmul float %135, %71 %196 = fadd float %195, %188 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %45, float %46, float %47, float %120) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %122, float %124, float %33, float %34) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %35, float %39, float %40, float %41) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %190, float %192, float %194, float %196) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_LOAD_DWORDX4 s[4:7], s[8:9], 0 ; C0820900 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[1:4], s[4:7][v0] + 0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80010100 S_LOAD_DWORDX4 s[4:7], s[0:1], 0 ; C0820100 S_WAITCNT vmcnt(0) lgkmcnt(0) ; BF8C0070 S_BUFFER_LOAD_DWORD s2, s[4:7], 1 ; C2010501 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v5, s2, v1 ; 100A0202 S_BUFFER_LOAD_DWORD s2, s[4:7], 5 ; C2010505 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v5, s2, v2, v5, 0, 0, 0, 0 ; D2820005 04160402 S_BUFFER_LOAD_DWORD s2, s[4:7], 9 ; C2010509 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v5, s2, v3, v5, 0, 0, 0, 0 ; D2820005 04160602 S_BUFFER_LOAD_DWORD s2, s[4:7], 13 ; C201050D S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v5, s2, v5 ; 060A0A02 S_BUFFER_LOAD_DWORD s2, s[4:7], 0 ; C2010500 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v6, s2, v1 ; 100C0202 S_BUFFER_LOAD_DWORD s2, s[4:7], 4 ; C2010504 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v6, s2, v2, v6, 0, 0, 0, 0 ; D2820006 041A0402 S_BUFFER_LOAD_DWORD s2, s[4:7], 8 ; C2010508 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v6, s2, v3, v6, 0, 0, 0, 0 ; D2820006 041A0602 S_BUFFER_LOAD_DWORD s2, s[4:7], 12 ; C201050C S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v6, s2, v6 ; 060C0C02 S_LOAD_DWORDX4 s[0:3], s[0:1], 4 ; C0800104 S_WAITCNT lgkmcnt(0) ; BF8C007F S_BUFFER_LOAD_DWORD s10, s[0:3], 0 ; C2050100 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v7, s10, v6 ; 100E0C0A S_BUFFER_LOAD_DWORD s10, s[0:3], 4 ; C2050104 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v7, s10, v5, v7, 0, 0, 0, 0 ; D2820007 041E0A0A S_BUFFER_LOAD_DWORD s10, s[4:7], 2 ; C2050502 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v8, s10, v1 ; 1010020A S_BUFFER_LOAD_DWORD s10, s[4:7], 6 ; C2050506 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v8, s10, v2, v8, 0, 0, 0, 0 ; D2820008 0422040A S_BUFFER_LOAD_DWORD s10, s[4:7], 10 ; C205050A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v8, s10, v3, v8, 0, 0, 0, 0 ; D2820008 0422060A S_BUFFER_LOAD_DWORD s10, s[4:7], 14 ; C205050E S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v8, s10, v8 ; 0610100A S_BUFFER_LOAD_DWORD s10, s[0:3], 8 ; C2050108 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v7, s10, v8, v7, 0, 0, 0, 0 ; D2820007 041E100A S_BUFFER_LOAD_DWORD s10, s[4:7], 3 ; C2050503 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v9, s10, v1 ; 1012020A S_BUFFER_LOAD_DWORD s10, s[4:7], 7 ; C2050507 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v9, s10, v2, v9, 0, 0, 0, 0 ; D2820009 0426040A S_BUFFER_LOAD_DWORD s10, s[4:7], 11 ; C205050B S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v9, s10, v3, v9, 0, 0, 0, 0 ; D2820009 0426060A S_BUFFER_LOAD_DWORD s4, s[4:7], 15 ; C202050F S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v9, s4, v9 ; 06121204 S_BUFFER_LOAD_DWORD s4, s[0:3], 12 ; C202010C S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v7, s4, v9, v7, 0, 0, 0, 0 ; D2820007 041E1204 S_LOAD_DWORDX4 s[4:7], s[8:9], 8 ; C0820908 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[10:13], s[4:7][v0] + 0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80010A00 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 32, 0, 0, 0, v10, v11, v12, v7 ; F800020F 070C0B0A S_BUFFER_LOAD_DWORD s4, s[0:3], 2 ; C2020102 S_WAITCNT expcnt(0) lgkmcnt(0) ; BF8C000F V_MUL_F32_e32 v7, s4, v6 ; 100E0C04 S_BUFFER_LOAD_DWORD s4, s[0:3], 6 ; C2020106 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v7, s4, v5, v7, 0, 0, 0, 0 ; D2820007 041E0A04 S_BUFFER_LOAD_DWORD s4, s[0:3], 10 ; C202010A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v7, s4, v8, v7, 0, 0, 0, 0 ; D2820007 041E1004 S_BUFFER_LOAD_DWORD s4, s[0:3], 14 ; C202010E S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v7, s4, v9, v7, 0, 0, 0, 0 ; D2820007 041E1204 S_BUFFER_LOAD_DWORD s4, s[0:3], 1 ; C2020101 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v10, s4, v6 ; 10140C04 S_BUFFER_LOAD_DWORD s4, s[0:3], 5 ; C2020105 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v10, s4, v5, v10, 0, 0, 0, 0 ; D282000A 042A0A04 S_BUFFER_LOAD_DWORD s4, s[0:3], 9 ; C2020109 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v10, s4, v8, v10, 0, 0, 0, 0 ; D282000A 042A1004 S_BUFFER_LOAD_DWORD s4, s[0:3], 13 ; C202010D S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v10, s4, v9, v10, 0, 0, 0, 0 ; D282000A 042A1204 EXP 15, 33, 0, 0, 0, v10, v7, v1, v2 ; F800021F 0201070A S_LOAD_DWORDX4 s[4:7], s[8:9], 4 ; C0820904 S_WAITCNT expcnt(0) lgkmcnt(0) ; BF8C000F BUFFER_LOAD_FORMAT_XYZW v[10:13], s[4:7][v0] + 0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80010A00 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 34, 0, 0, 0, v3, v10, v11, v12 ; F800022F 0C0B0A03 S_BUFFER_LOAD_DWORD s4, s[0:3], 35 ; C2020123 S_WAITCNT expcnt(0) lgkmcnt(0) ; BF8C000F V_MUL_F32_e32 v0, s4, v6 ; 10000C04 S_BUFFER_LOAD_DWORD s4, s[0:3], 39 ; C2020127 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v0, s4, v5, v0, 0, 0, 0, 0 ; D2820000 04020A04 S_BUFFER_LOAD_DWORD s4, s[0:3], 43 ; C202012B S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v0, s4, v8, v0, 0, 0, 0, 0 ; D2820000 04021004 S_BUFFER_LOAD_DWORD s4, s[0:3], 47 ; C202012F S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v0, s4, v9, v0, 0, 0, 0, 0 ; D2820000 04021204 S_BUFFER_LOAD_DWORD s4, s[0:3], 34 ; C2020122 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v1, s4, v6 ; 10020C04 S_BUFFER_LOAD_DWORD s4, s[0:3], 38 ; C2020126 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v1, s4, v5, v1, 0, 0, 0, 0 ; D2820001 04060A04 S_BUFFER_LOAD_DWORD s4, s[0:3], 42 ; C202012A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v1, s4, v8, v1, 0, 0, 0, 0 ; D2820001 04061004 S_BUFFER_LOAD_DWORD s4, s[0:3], 46 ; C202012E S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v1, s4, v9, v1, 0, 0, 0, 0 ; D2820001 04061204 S_BUFFER_LOAD_DWORD s4, s[0:3], 33 ; C2020121 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v2, s4, v6 ; 10040C04 S_BUFFER_LOAD_DWORD s4, s[0:3], 37 ; C2020125 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v2, s4, v5, v2, 0, 0, 0, 0 ; D2820002 040A0A04 S_BUFFER_LOAD_DWORD s4, s[0:3], 41 ; C2020129 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v2, s4, v8, v2, 0, 0, 0, 0 ; D2820002 040A1004 S_BUFFER_LOAD_DWORD s4, s[0:3], 45 ; C202012D S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v2, s4, v9, v2, 0, 0, 0, 0 ; D2820002 040A1204 S_BUFFER_LOAD_DWORD s4, s[0:3], 32 ; C2020120 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v3, s4, v6 ; 10060C04 S_BUFFER_LOAD_DWORD s4, s[0:3], 36 ; C2020124 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v3, s4, v5, v3, 0, 0, 0, 0 ; D2820003 040E0A04 S_BUFFER_LOAD_DWORD s4, s[0:3], 40 ; C2020128 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v3, s4, v8, v3, 0, 0, 0, 0 ; D2820003 040E1004 S_BUFFER_LOAD_DWORD s0, s[0:3], 44 ; C200012C S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v3, s0, v9, v3, 0, 0, 0, 0 ; D2820003 040E1200 EXP 15, 12, 0, 1, 0, v3, v2, v1, v0 ; F80008CF 00010203 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[20], PERSPECTIVE DCL IN[1], GENERIC[21], PERSPECTIVE DCL IN[2], GENERIC[22], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL SAMP[1] DCL SAMP[2] DCL SAMP[3] DCL SAMP[4] DCL SAMP[5] DCL SAMP[6] DCL SAMP[7] DCL CONST[2..73] DCL CONST[80..89] DCL CONST[1][0..96] DCL CONST[2][0..68] DCL TEMP[0..41], LOCAL DCL ADDR[0] IMM[0] FLT32 { 0.0010, 0.2230, 0.5000, 2.0000} IMM[1] FLT32 { -1.0039, 1.0500, 0.0000, 0.8000} IMM[2] UINT32 {0, 224, 208, 192} IMM[3] INT32 {14, 13, 12, 15} IMM[4] UINT32 {240, 320, 1, 256} IMM[5] INT32 {20, 16, 6, 5} IMM[6] UINT32 {96, 80, 64, 112} IMM[7] INT32 {4, 7, 10, 9} IMM[8] FLT32 { 0.7213, -1.0000, 1.0000, -0.8000} IMM[9] UINT32 {252, 264, 160, 144} IMM[10] UINT32 {128, 176, 260, 0} IMM[11] INT32 {8, 11, 0, 1} IMM[12] FLT32 { 5.0000, 3.0000, 0.0000, 0.0000} IMM[13] INT32 {2, 3, 0, 0} 0: MOV TEMP[0].x, IN[0].wwww 1: MOV TEMP[0].yz, IN[1].yxyy 2: MOV TEMP[1].xy, IN[1].zwzz 3: MOV TEMP[1].z, IN[2].xxxx 4: ABS TEMP[1].xyz, TEMP[1].xyzz 5: ADD TEMP[2].xyz, TEMP[1].xyzz, IMM[0].xxxx 6: POW TEMP[3].x, TEMP[2].xxxx, CONST[84].xxxx 7: POW TEMP[3].y, TEMP[2].yyyy, CONST[84].xxxx 8: POW TEMP[3].z, TEMP[2].zzzz, CONST[84].xxxx 9: ADD TEMP[2].x, TEMP[3].xxxx, TEMP[3].yyyy 10: ADD TEMP[2].x, TEMP[2].xxxx, TEMP[3].zzzz 11: RCP TEMP[2].x, TEMP[2].xxxx 12: MUL TEMP[2].xyz, TEMP[3].xyzz, TEMP[2].xxxx 13: RCP TEMP[3].x, CONST[81].xxxx 14: MUL TEMP[3].xy, TEMP[0].xyyy, TEMP[3].xxxx 15: MUL TEMP[4].x, CONST[81].xxxx, IMM[0].yyyy 16: RCP TEMP[5].x, CONST[82].xxxx 17: MUL TEMP[5].xy, TEMP[0].xzzz, TEMP[5].xxxx 18: MUL TEMP[6].x, CONST[82].xxxx, IMM[0].yyyy 19: RCP TEMP[7].x, CONST[83].xxxx 20: MUL TEMP[7].xy, IN[1].yxxx, TEMP[7].xxxx 21: MUL TEMP[8].x, CONST[83].xxxx, IMM[0].yyyy 22: RCP TEMP[9].x, TEMP[8].xxxx 23: MUL TEMP[9].xy, IN[1].yxxx, TEMP[9].xxxx 24: MOV TEMP[9].xy, TEMP[9].xyyy 25: TEX TEMP[9], TEMP[9], SAMP[4], 2D 26: MOV TEMP[10].xy, TEMP[7].xyyy 27: TEX TEMP[10], TEMP[10], SAMP[4], 2D 28: MUL TEMP[10].xyz, IMM[0].zzzz, TEMP[10].xyzz 29: MAD TEMP[9].xyz, IMM[0].zzzz, TEMP[9].xyzz, TEMP[10].xyzz 30: RCP TEMP[10].x, TEMP[6].xxxx 31: MUL TEMP[10].xy, TEMP[0].xzzz, TEMP[10].xxxx 32: MOV TEMP[10].xy, TEMP[10].xyyy 33: TEX TEMP[10], TEMP[10], SAMP[3], 2D 34: MOV TEMP[11].xy, TEMP[5].xyyy 35: TEX TEMP[11], TEMP[11], SAMP[3], 2D 36: MUL TEMP[11].xyz, IMM[0].zzzz, TEMP[11].xyzz 37: MAD TEMP[10].xyz, IMM[0].zzzz, TEMP[10].xyzz, TEMP[11].xyzz 38: RCP TEMP[11].x, TEMP[4].xxxx 39: MUL TEMP[11].xy, TEMP[0].xyyy, TEMP[11].xxxx 40: MOV TEMP[11].xy, TEMP[11].xyyy 41: TEX TEMP[11], TEMP[11], SAMP[2], 2D 42: MOV TEMP[12].xy, TEMP[3].xyyy 43: TEX TEMP[12], TEMP[12], SAMP[2], 2D 44: MUL TEMP[12].xyz, IMM[0].zzzz, TEMP[12].xyzz 45: MAD TEMP[11].xyz, IMM[0].zzzz, TEMP[11].xyzz, TEMP[12].xyzz 46: MUL TEMP[11].xyz, TEMP[11].xyzz, TEMP[2].zzzz 47: MAD TEMP[10].xyz, TEMP[10].xyzz, TEMP[2].yyyy, TEMP[11].xyzz 48: MAD TEMP[2].xyz, TEMP[9].xyzz, TEMP[2].xxxx, TEMP[10].xyzz 49: RCP TEMP[4].x, TEMP[4].xxxx 50: MUL TEMP[4].xy, TEMP[0].xyyy, TEMP[4].xxxx 51: MOV TEMP[4].xy, TEMP[4].xyyy 52: TEX TEMP[4], TEMP[4], SAMP[5], 2D 53: MOV TEMP[3].xy, TEMP[3].xyyy 54: TEX TEMP[3], TEMP[3], SAMP[5], 2D 55: MUL TEMP[3].xyz, IMM[0].zzzz, TEMP[3].xyzz 56: MAD TEMP[3].xyz, IMM[0].zzzz, TEMP[4].xyzz, TEMP[3].xyzz 57: MAD TEMP[4].xy, TEMP[3].xyyy, IMM[0].wwww, IMM[1].xxxx 58: MOV TEMP[4].z, TEMP[3].zzzz 59: RCP TEMP[3].x, TEMP[6].xxxx 60: MUL TEMP[0].xy, TEMP[0].xzzz, TEMP[3].xxxx 61: MOV TEMP[0].xy, TEMP[0].xyyy 62: TEX TEMP[0], TEMP[0], SAMP[6], 2D 63: MOV TEMP[3].xy, TEMP[5].xyyy 64: TEX TEMP[3], TEMP[3], SAMP[6], 2D 65: MUL TEMP[3].xyz, IMM[0].zzzz, TEMP[3].xyzz 66: MAD TEMP[0].xyz, IMM[0].zzzz, TEMP[0].xyzz, TEMP[3].xyzz 67: MAD TEMP[3].xy, TEMP[0].xyyy, IMM[0].wwww, IMM[1].xxxx 68: MOV TEMP[3].z, TEMP[0].zzzz 69: RCP TEMP[0].x, TEMP[8].xxxx 70: MUL TEMP[0].xy, IN[1].yxxx, TEMP[0].xxxx 71: MOV TEMP[0].xy, TEMP[0].xyyy 72: TEX TEMP[0], TEMP[0], SAMP[7], 2D 73: MOV TEMP[5].xy, TEMP[7].xyyy 74: TEX TEMP[5], TEMP[5], SAMP[7], 2D 75: MUL TEMP[5].xyz, IMM[0].zzzz, TEMP[5].xyzz 76: MAD TEMP[0].xyz, IMM[0].zzzz, TEMP[0].xyzz, TEMP[5].xyzz 77: MAD TEMP[5].xy, TEMP[0].xyyy, IMM[0].wwww, IMM[1].xxxx 78: MOV TEMP[5].z, TEMP[0].zzzz 79: ADD TEMP[0].x, TEMP[1].xxxx, TEMP[1].yyyy 80: ADD TEMP[0].x, TEMP[0].xxxx, TEMP[1].zzzz 81: RCP TEMP[0].x, TEMP[0].xxxx 82: MUL TEMP[0].xyz, TEMP[1].xyzz, TEMP[0].xxxx 83: SSG TEMP[1].x, IN[1].zzzz 84: MUL TEMP[1].xyz, TEMP[5].zyxx, TEMP[1].xxxx 85: SSG TEMP[5].x, IN[1].wwww 86: MUL TEMP[3].xyz, TEMP[3].xzyy, TEMP[5].xxxx 87: SSG TEMP[5].x, IN[2].xxxx 88: MUL TEMP[4].xyz, TEMP[4].xyzz, TEMP[5].xxxx 89: MUL TEMP[4].xyz, TEMP[4].xyzz, TEMP[0].zzzz 90: MAD TEMP[3].xyz, TEMP[3].xyzz, TEMP[0].yyyy, TEMP[4].xyzz 91: MAD TEMP[0].xyz, TEMP[1].xyzz, TEMP[0].xxxx, TEMP[3].xyzz 92: MUL TEMP[1].xyz, CONST[86].xyzz, TEMP[0].xxxx 93: MAD TEMP[1].xyz, CONST[87].xyzz, TEMP[0].yyyy, TEMP[1].xyzz 94: MAD TEMP[0].xyz, CONST[88].xyzz, TEMP[0].zzzz, TEMP[1].xyzz 95: DP3 TEMP[1].x, TEMP[0].xyzz, TEMP[0].xyzz 96: RSQ TEMP[1].x, TEMP[1].xxxx 97: MUL TEMP[0].xyz, TEMP[0].xyzz, TEMP[1].xxxx 98: MOV TEMP[1].xyz, TEMP[0].xyzx 99: MOV TEMP[3].xyz, TEMP[2].xyzx 100: MOV TEMP[4], CONST[80] 101: UARL ADDR[0].x, IMM[3].xxxx 102: MOV TEMP[5], CONST[1][ADDR[0].x] 103: UARL ADDR[0].x, IMM[3].yyyy 104: MOV TEMP[6], CONST[1][ADDR[0].x] 105: UARL ADDR[0].x, IMM[3].zzzz 106: MOV TEMP[7], CONST[1][ADDR[0].x] 107: MUL TEMP[7], TEMP[7], IN[0].xxxx 108: MAD TEMP[6], TEMP[6], IN[0].yyyy, TEMP[7] 109: MAD TEMP[5], TEMP[5], IN[0].zzzz, TEMP[6] 110: UARL ADDR[0].x, IMM[3].wwww 111: MOV TEMP[6], CONST[1][ADDR[0].x] 112: ADD TEMP[5], TEMP[5], TEMP[6] 113: MOV TEMP[6].xyz, TEMP[5].xyzx 114: UARL ADDR[0].x, IMM[5].xxxx 115: MOV TEMP[7].xyz, CONST[1][ADDR[0].x].xyzz 116: ADD TEMP[7].xyz, TEMP[5].xyzz, -TEMP[7].xyzz 117: DP3 TEMP[8].x, TEMP[7].xyzz, TEMP[7].xyzz 118: RSQ TEMP[8].x, TEMP[8].xxxx 119: MUL TEMP[7].xyz, TEMP[7].xyzz, TEMP[8].xxxx 120: DP3 TEMP[8].x, TEMP[0].xyzz, TEMP[7].xyzz 121: MUL TEMP[8].xyz, TEMP[8].xxxx, TEMP[0].xyzz 122: MUL TEMP[8].xyz, IMM[0].wwww, TEMP[8].xyzz 123: ADD TEMP[7].xyz, TEMP[7].xyzz, -TEMP[8].xyzz 124: MOV TEMP[8].xyz, TEMP[7].xyzx 125: ADD_SAT TEMP[9].x, TEMP[0].yyyy, IMM[1].yyyy 126: UARL ADDR[0].x, IMM[3].xxxx 127: MOV TEMP[10].xyz, CONST[2][ADDR[0].x].xyzz 128: MUL TEMP[9].xyz, TEMP[9].xxxx, TEMP[10].xyzz 129: MUL TEMP[9].xyz, TEMP[2].xyzz, TEMP[9].xyzz 130: UARL ADDR[0].x, IMM[3].zzzz 131: UARL ADDR[0].x, IMM[3].zzzz 132: MOV TEMP[10].xyz, CONST[2][ADDR[0].x].xyzz 133: UARL ADDR[0].x, IMM[3].yyyy 134: UARL ADDR[0].x, IMM[3].yyyy 135: MOV TEMP[11].xyz, CONST[2][ADDR[0].x].xyzz 136: DP3 TEMP[0].x, TEMP[0].xyzz, TEMP[10].xyzz 137: MAX TEMP[0].x, IMM[1].zzzz, TEMP[0].xxxx 138: MUL TEMP[0].xyz, TEMP[0].xxxx, TEMP[11].xyzz 139: MUL TEMP[0].xyz, TEMP[0].xyzz, TEMP[2].xyzz 140: DP3 TEMP[2].x, TEMP[7].xyzz, TEMP[10].xyzz 141: MAX TEMP[2].x, IMM[0].xxxx, TEMP[2].xxxx 142: POW TEMP[2].x, TEMP[2].xxxx, CONST[80].wwww 143: MUL TEMP[2].xyz, TEMP[2].xxxx, TEMP[11].xyzz 144: MAD TEMP[0].xyz, TEMP[2].xyzz, CONST[80].xyzz, TEMP[0].xyzz 145: UARL ADDR[0].x, IMM[3].wwww 146: MOV TEMP[2].xyz, CONST[2][ADDR[0].x].xyzz 147: ADD TEMP[2].xyz, TEMP[5].xyzz, -TEMP[2].xyzz 148: DP3 TEMP[2].x, TEMP[2].xyzz, TEMP[2].xyzz 149: RSQ TEMP[7].x, TEMP[2].xxxx 150: MUL TEMP[7].x, TEMP[7].xxxx, TEMP[2].xxxx 151: CMP TEMP[2].x, -TEMP[2].xxxx, TEMP[7].xxxx, IMM[1].zzzz 152: MOV TEMP[7].x, IMM[1].zzzz 153: UARL ADDR[0].x, IMM[5].yyyy 154: UARL ADDR[0].x, IMM[5].yyyy 155: MOV TEMP[10].x, CONST[2][ADDR[0].x].xxxx 156: MUL TEMP[10].x, IMM[1].wwww, TEMP[10].xxxx 157: FSLT TEMP[10].x, TEMP[2].xxxx, TEMP[10].xxxx 158: UIF TEMP[10].xxxx :0 159: UARL ADDR[0].x, IMM[5].zzzz 160: MOV TEMP[10], CONST[2][ADDR[0].x] 161: UARL ADDR[0].x, IMM[5].wwww 162: MOV TEMP[11], CONST[2][ADDR[0].x] 163: UARL ADDR[0].x, IMM[7].xxxx 164: MOV TEMP[12], CONST[2][ADDR[0].x] 165: MUL TEMP[12], TEMP[12], TEMP[5].xxxx 166: MAD TEMP[11], TEMP[11], TEMP[5].yyyy, TEMP[12] 167: MAD TEMP[10], TEMP[10], TEMP[5].zzzz, TEMP[11] 168: UARL ADDR[0].x, IMM[7].yyyy 169: MOV TEMP[11], CONST[2][ADDR[0].x] 170: ADD TEMP[10], TEMP[10], TEMP[11] 171: UARL ADDR[0].x, IMM[3].wwww 172: MOV TEMP[11].x, CONST[2][ADDR[0].x].wwww 173: MAX TEMP[12].x, TEMP[10].zzzz, IMM[8].yyyy 174: MIN TEMP[12].x, TEMP[12].xxxx, IMM[8].zzzz 175: ADD TEMP[12].x, TEMP[12].xxxx, IMM[8].zzzz 176: MUL TEMP[11].x, -TEMP[11].xxxx, TEMP[12].xxxx 177: MUL TEMP[11].x, IMM[8].xxxx, TEMP[11].xxxx 178: EX2 TEMP[11].x, TEMP[11].xxxx 179: MAD TEMP[10].xy, TEMP[10].xyyy, IMM[0].zzzz, IMM[0].zzzz 180: UARL ADDR[0].x, IMM[5].yyyy 181: MOV TEMP[12].x, CONST[2][ADDR[0].x].zzzz 182: MUL TEMP[10].xy, TEMP[10].xyyy, TEMP[12].xxxx 183: MOV TEMP[10].xy, TEMP[10].xyyy 184: TEX TEMP[10], TEMP[10], SAMP[0], RECT 185: MUL_SAT TEMP[10].x, TEMP[11].xxxx, TEMP[10].xxxx 186: MOV TEMP[7].x, TEMP[10].xxxx 187: ELSE :0 188: UARL ADDR[0].x, IMM[5].yyyy 189: UARL ADDR[0].x, IMM[5].yyyy 190: MOV TEMP[10].x, CONST[2][ADDR[0].x].xxxx 191: FSLT TEMP[10].x, TEMP[10].xxxx, TEMP[2].xxxx 192: UIF TEMP[10].xxxx :0 193: UARL ADDR[0].x, IMM[7].zzzz 194: MOV TEMP[10], CONST[2][ADDR[0].x] 195: UARL ADDR[0].x, IMM[7].wwww 196: MOV TEMP[11], CONST[2][ADDR[0].x] 197: UARL ADDR[0].x, IMM[11].xxxx 198: MOV TEMP[12], CONST[2][ADDR[0].x] 199: MUL TEMP[12], TEMP[12], TEMP[5].xxxx 200: MAD TEMP[11], TEMP[11], TEMP[5].yyyy, TEMP[12] 201: MAD TEMP[10], TEMP[10], TEMP[5].zzzz, TEMP[11] 202: UARL ADDR[0].x, IMM[11].yyyy 203: MOV TEMP[11], CONST[2][ADDR[0].x] 204: ADD TEMP[10], TEMP[10], TEMP[11] 205: UARL ADDR[0].x, IMM[3].wwww 206: MOV TEMP[11].xyz, CONST[2][ADDR[0].x].xyzz 207: ADD TEMP[11].xyz, TEMP[5].xyzz, -TEMP[11].xyzz 208: DP3 TEMP[11].x, TEMP[11].xyzz, TEMP[11].xyzz 209: RSQ TEMP[12].x, TEMP[11].xxxx 210: MUL TEMP[12].x, TEMP[12].xxxx, TEMP[11].xxxx 211: CMP TEMP[12].x, -TEMP[11].xxxx, TEMP[12].xxxx, IMM[1].zzzz 212: UARL ADDR[0].x, IMM[5].yyyy 213: MOV TEMP[11].x, CONST[2][ADDR[0].x].yyyy 214: RCP TEMP[11].x, TEMP[11].xxxx 215: MAD TEMP[11].x, TEMP[12].xxxx, TEMP[11].xxxx, IMM[8].wwww 216: MUL_SAT TEMP[11].x, TEMP[11].xxxx, IMM[12].xxxx 217: UARL ADDR[0].x, IMM[3].wwww 218: MOV TEMP[12].x, CONST[2][ADDR[0].x].wwww 219: MAX TEMP[13].x, TEMP[10].zzzz, IMM[8].yyyy 220: MIN TEMP[13].x, TEMP[13].xxxx, IMM[8].zzzz 221: ADD TEMP[13].x, TEMP[13].xxxx, IMM[8].zzzz 222: MUL TEMP[12].x, -TEMP[12].xxxx, TEMP[13].xxxx 223: MUL TEMP[12].x, IMM[8].xxxx, TEMP[12].xxxx 224: EX2 TEMP[12].x, TEMP[12].xxxx 225: MAD TEMP[10].xy, TEMP[10].xyyy, IMM[0].zzzz, IMM[0].zzzz 226: UARL ADDR[0].x, IMM[5].yyyy 227: MOV TEMP[13].x, CONST[2][ADDR[0].x].zzzz 228: MUL TEMP[10].xy, TEMP[10].xyyy, TEMP[13].xxxx 229: MOV TEMP[10].xy, TEMP[10].xyyy 230: TEX TEMP[10], TEMP[10], SAMP[1], RECT 231: MUL_SAT TEMP[10].x, TEMP[12].xxxx, TEMP[10].xxxx 232: MUL TEMP[12].x, IMM[0].wwww, TEMP[11].xxxx 233: ADD TEMP[12].x, IMM[12].yyyy, -TEMP[12].xxxx 234: MUL TEMP[12].x, TEMP[11].xxxx, TEMP[12].xxxx 235: MUL TEMP[11].x, TEMP[11].xxxx, TEMP[12].xxxx 236: LRP TEMP[7].x, TEMP[11].xxxx, IMM[8].zzzz, TEMP[10].xxxx 237: ELSE :0 238: UARL ADDR[0].x, IMM[5].zzzz 239: MOV TEMP[10], CONST[2][ADDR[0].x] 240: UARL ADDR[0].x, IMM[5].wwww 241: MOV TEMP[11], CONST[2][ADDR[0].x] 242: UARL ADDR[0].x, IMM[7].xxxx 243: MOV TEMP[12], CONST[2][ADDR[0].x] 244: MUL TEMP[12], TEMP[12], TEMP[5].xxxx 245: MAD TEMP[11], TEMP[11], TEMP[5].yyyy, TEMP[12] 246: MAD TEMP[10], TEMP[10], TEMP[5].zzzz, TEMP[11] 247: UARL ADDR[0].x, IMM[7].yyyy 248: MOV TEMP[11], CONST[2][ADDR[0].x] 249: ADD TEMP[10], TEMP[10], TEMP[11] 250: UARL ADDR[0].x, IMM[7].zzzz 251: MOV TEMP[11], CONST[2][ADDR[0].x] 252: UARL ADDR[0].x, IMM[7].wwww 253: MOV TEMP[12], CONST[2][ADDR[0].x] 254: UARL ADDR[0].x, IMM[11].xxxx 255: MOV TEMP[13], CONST[2][ADDR[0].x] 256: MUL TEMP[13], TEMP[13], TEMP[5].xxxx 257: MAD TEMP[12], TEMP[12], TEMP[5].yyyy, TEMP[13] 258: MAD TEMP[5], TEMP[11], TEMP[5].zzzz, TEMP[12] 259: UARL ADDR[0].x, IMM[11].yyyy 260: MOV TEMP[11], CONST[2][ADDR[0].x] 261: ADD TEMP[5], TEMP[5], TEMP[11] 262: UARL ADDR[0].x, IMM[5].yyyy 263: UARL ADDR[0].x, IMM[5].yyyy 264: MOV TEMP[11].x, CONST[2][ADDR[0].x].xxxx 265: MUL TEMP[12].x, IMM[1].wwww, TEMP[11].xxxx 266: ADD TEMP[2].x, TEMP[2].xxxx, -TEMP[12].xxxx 267: ADD TEMP[11].x, TEMP[11].xxxx, -TEMP[12].xxxx 268: RCP TEMP[11].x, TEMP[11].xxxx 269: MUL_SAT TEMP[2].x, TEMP[2].xxxx, TEMP[11].xxxx 270: UARL ADDR[0].x, IMM[3].wwww 271: UARL ADDR[0].x, IMM[3].wwww 272: MOV TEMP[11].x, CONST[2][ADDR[0].x].wwww 273: UARL ADDR[0].x, IMM[5].yyyy 274: UARL ADDR[0].x, IMM[5].yyyy 275: MOV TEMP[12].x, CONST[2][ADDR[0].x].zzzz 276: MAX TEMP[13].x, TEMP[10].zzzz, IMM[8].yyyy 277: MIN TEMP[13].x, TEMP[13].xxxx, IMM[8].zzzz 278: ADD TEMP[13].x, TEMP[13].xxxx, IMM[8].zzzz 279: MUL TEMP[13].x, -TEMP[11].xxxx, TEMP[13].xxxx 280: MUL TEMP[13].x, IMM[8].xxxx, TEMP[13].xxxx 281: EX2 TEMP[13].x, TEMP[13].xxxx 282: MAD TEMP[10].xy, TEMP[10].xyyy, IMM[0].zzzz, IMM[0].zzzz 283: MUL TEMP[10].xy, TEMP[10].xyyy, TEMP[12].xxxx 284: MOV TEMP[10].xy, TEMP[10].xyyy 285: TEX TEMP[10], TEMP[10], SAMP[0], RECT 286: MUL_SAT TEMP[10].x, TEMP[13].xxxx, TEMP[10].xxxx 287: MAX TEMP[13].x, TEMP[5].zzzz, IMM[8].yyyy 288: MIN TEMP[13].x, TEMP[13].xxxx, IMM[8].zzzz 289: ADD TEMP[13].x, TEMP[13].xxxx, IMM[8].zzzz 290: MUL TEMP[11].x, -TEMP[11].xxxx, TEMP[13].xxxx 291: MUL TEMP[11].x, IMM[8].xxxx, TEMP[11].xxxx 292: EX2 TEMP[11].x, TEMP[11].xxxx 293: MAD TEMP[5].xy, TEMP[5].xyyy, IMM[0].zzzz, IMM[0].zzzz 294: MUL TEMP[5].xy, TEMP[5].xyyy, TEMP[12].xxxx 295: MOV TEMP[5].xy, TEMP[5].xyyy 296: TEX TEMP[5], TEMP[5], SAMP[1], RECT 297: MUL_SAT TEMP[5].x, TEMP[11].xxxx, TEMP[5].xxxx 298: MUL TEMP[11].x, IMM[0].wwww, TEMP[2].xxxx 299: ADD TEMP[11].x, IMM[12].yyyy, -TEMP[11].xxxx 300: MUL TEMP[11].x, TEMP[2].xxxx, TEMP[11].xxxx 301: MUL TEMP[2].x, TEMP[2].xxxx, TEMP[11].xxxx 302: LRP TEMP[7].x, TEMP[2].xxxx, TEMP[5].xxxx, TEMP[10].xxxx 303: ENDIF 304: ENDIF 305: ADD TEMP[2].x, TEMP[7].xxxx, IMM[8].wwww 306: MUL_SAT TEMP[2].x, TEMP[2].xxxx, IMM[12].xxxx 307: MUL TEMP[5].x, IMM[0].wwww, TEMP[2].xxxx 308: ADD TEMP[5].x, IMM[12].yyyy, -TEMP[5].xxxx 309: MUL TEMP[5].x, TEMP[2].xxxx, TEMP[5].xxxx 310: MUL TEMP[2].x, TEMP[2].xxxx, TEMP[5].xxxx 311: MUL TEMP[0].xyz, TEMP[0].xyzz, TEMP[2].xxxx 312: ADD TEMP[9].xyz, TEMP[9].xyzz, TEMP[0].xyzz 313: MOV TEMP[0].x, IMM[11].zzzz 314: BGNLOOP :0 315: ISGE TEMP[2].x, TEMP[0].xxxx, CONST[3].xxxx 316: UIF TEMP[2].xxxx :0 317: BRK 318: ENDIF 319: UMUL TEMP[5].x, TEMP[0].xxxx, IMM[7].yyyy 320: UARL ADDR[0].x, TEMP[5].xxxx 321: MOV TEMP[7].x, CONST[ADDR[0].x+4].xxxx 322: UADD TEMP[10].x, TEMP[5].xxxx, IMM[11].wwww 323: UARL ADDR[0].x, TEMP[10].xxxx 324: MOV TEMP[7].y, CONST[ADDR[0].x+4].xxxx 325: UADD TEMP[11].x, TEMP[5].xxxx, IMM[13].xxxx 326: UARL ADDR[0].x, TEMP[11].xxxx 327: MOV TEMP[7].z, CONST[ADDR[0].x+4].xxxx 328: UADD TEMP[12].x, TEMP[5].xxxx, IMM[13].yyyy 329: UARL ADDR[0].x, TEMP[12].xxxx 330: MOV TEMP[13].x, CONST[ADDR[0].x+4].xxxx 331: UADD TEMP[14].x, TEMP[5].xxxx, IMM[7].xxxx 332: UARL ADDR[0].x, TEMP[14].xxxx 333: MOV TEMP[13].y, CONST[ADDR[0].x+4].xxxx 334: UADD TEMP[15].x, TEMP[5].xxxx, IMM[5].wwww 335: UARL ADDR[0].x, TEMP[15].xxxx 336: MOV TEMP[13].z, CONST[ADDR[0].x+4].xxxx 337: UADD TEMP[16].x, TEMP[5].xxxx, IMM[5].zzzz 338: UARL ADDR[0].x, TEMP[16].xxxx 339: MOV TEMP[17].x, CONST[ADDR[0].x+4].xxxx 340: ADD TEMP[18].xyz, TEMP[7].xyzz, -TEMP[6].xyzz 341: DP3 TEMP[19].x, TEMP[18].xyzz, TEMP[18].xyzz 342: RSQ TEMP[20].x, TEMP[19].xxxx 343: MUL TEMP[20].x, TEMP[20].xxxx, TEMP[19].xxxx 344: CMP TEMP[21].x, -TEMP[19].xxxx, TEMP[20].xxxx, IMM[1].zzzz 345: RCP TEMP[22].x, TEMP[21].xxxx 346: MUL TEMP[23].xyz, TEMP[18].xyzz, TEMP[22].xxxx 347: DP3 TEMP[24].x, TEMP[1].xyzz, TEMP[23].xyzz 348: MAX TEMP[25].x, IMM[1].zzzz, TEMP[24].xxxx 349: MUL TEMP[26].xyz, TEMP[25].xxxx, TEMP[13].xyzz 350: MUL TEMP[27].xyz, TEMP[26].xyzz, TEMP[3].xyzz 351: DP3 TEMP[28].x, TEMP[8].xyzz, TEMP[23].xyzz 352: MAX TEMP[29].x, IMM[0].xxxx, TEMP[28].xxxx 353: POW TEMP[30].x, TEMP[29].xxxx, TEMP[4].wwww 354: MUL TEMP[31].xyz, TEMP[30].xxxx, TEMP[13].xyzz 355: MAD TEMP[27].xyz, TEMP[31].xyzz, TEMP[4].xyzz, TEMP[27].xyzz 356: MUL TEMP[32].x, TEMP[17].xxxx, IMM[0].zzzz 357: ADD TEMP[33].x, TEMP[21].xxxx, -TEMP[32].xxxx 358: ADD TEMP[34].x, TEMP[17].xxxx, -TEMP[32].xxxx 359: RCP TEMP[35].x, TEMP[34].xxxx 360: MUL_SAT TEMP[36].x, TEMP[33].xxxx, TEMP[35].xxxx 361: MUL TEMP[37].x, IMM[0].wwww, TEMP[36].xxxx 362: ADD TEMP[38].x, IMM[12].yyyy, -TEMP[37].xxxx 363: MUL TEMP[39].x, TEMP[36].xxxx, TEMP[38].xxxx 364: MUL TEMP[40].x, TEMP[36].xxxx, TEMP[39].xxxx 365: ADD TEMP[41].x, IMM[8].zzzz, -TEMP[40].xxxx 366: MUL TEMP[27].xyz, TEMP[27].xyzz, TEMP[41].xxxx 367: ADD TEMP[9].xyz, TEMP[9].xyzz, TEMP[27].xyzz 368: UADD TEMP[0].x, TEMP[0].xxxx, IMM[11].wwww 369: ENDLOOP :0 370: MUL TEMP[0].xyz, TEMP[9].xyzz, CONST[85].xxxx 371: MOV OUT[0], TEMP[0] 372: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %22 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0 %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0 %24 = call float @llvm.SI.load.const(<16 x i8> %23, i32 48) %25 = call float @llvm.SI.load.const(<16 x i8> %23, i32 1280) %26 = call float @llvm.SI.load.const(<16 x i8> %23, i32 1284) %27 = call float @llvm.SI.load.const(<16 x i8> %23, i32 1288) %28 = call float @llvm.SI.load.const(<16 x i8> %23, i32 1292) %29 = call float @llvm.SI.load.const(<16 x i8> %23, i32 1296) %30 = call float @llvm.SI.load.const(<16 x i8> %23, i32 1312) %31 = call float @llvm.SI.load.const(<16 x i8> %23, i32 1328) %32 = call float @llvm.SI.load.const(<16 x i8> %23, i32 1344) %33 = call float @llvm.SI.load.const(<16 x i8> %23, i32 1360) %34 = call float @llvm.SI.load.const(<16 x i8> %23, i32 1376) %35 = call float @llvm.SI.load.const(<16 x i8> %23, i32 1380) %36 = call float @llvm.SI.load.const(<16 x i8> %23, i32 1384) %37 = call float @llvm.SI.load.const(<16 x i8> %23, i32 1392) %38 = call float @llvm.SI.load.const(<16 x i8> %23, i32 1396) %39 = call float @llvm.SI.load.const(<16 x i8> %23, i32 1400) %40 = call float @llvm.SI.load.const(<16 x i8> %23, i32 1408) %41 = call float @llvm.SI.load.const(<16 x i8> %23, i32 1412) %42 = call float @llvm.SI.load.const(<16 x i8> %23, i32 1416) %43 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 1 %44 = load <16 x i8> addrspace(2)* %43, !tbaa !0 %45 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 2 %46 = load <16 x i8> addrspace(2)* %45, !tbaa !0 %47 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0 %48 = load <32 x i8> addrspace(2)* %47, !tbaa !0 %49 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0 %50 = load <16 x i8> addrspace(2)* %49, !tbaa !0 %51 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 1 %52 = load <32 x i8> addrspace(2)* %51, !tbaa !0 %53 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 1 %54 = load <16 x i8> addrspace(2)* %53, !tbaa !0 %55 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 2 %56 = load <32 x i8> addrspace(2)* %55, !tbaa !0 %57 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 2 %58 = load <16 x i8> addrspace(2)* %57, !tbaa !0 %59 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 3 %60 = load <32 x i8> addrspace(2)* %59, !tbaa !0 %61 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 3 %62 = load <16 x i8> addrspace(2)* %61, !tbaa !0 %63 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 4 %64 = load <32 x i8> addrspace(2)* %63, !tbaa !0 %65 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 4 %66 = load <16 x i8> addrspace(2)* %65, !tbaa !0 %67 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 5 %68 = load <32 x i8> addrspace(2)* %67, !tbaa !0 %69 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 5 %70 = load <16 x i8> addrspace(2)* %69, !tbaa !0 %71 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 6 %72 = load <32 x i8> addrspace(2)* %71, !tbaa !0 %73 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 6 %74 = load <16 x i8> addrspace(2)* %73, !tbaa !0 %75 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 7 %76 = load <32 x i8> addrspace(2)* %75, !tbaa !0 %77 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 7 %78 = load <16 x i8> addrspace(2)* %77, !tbaa !0 %79 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %7) %80 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %7) %81 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %5, <2 x i32> %7) %82 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %5, <2 x i32> %7) %83 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %5, <2 x i32> %7) %84 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %5, <2 x i32> %7) %85 = call float @llvm.SI.fs.interp(i32 2, i32 1, i32 %5, <2 x i32> %7) %86 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %5, <2 x i32> %7) %87 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %5, <2 x i32> %7) %88 = call float @fabs(float %85) %89 = call float @fabs(float %86) %90 = call float @fabs(float %87) %91 = fadd float %88, 0x3F50624DE0000000 %92 = fadd float %89, 0x3F50624DE0000000 %93 = fadd float %90, 0x3F50624DE0000000 %94 = call float @llvm.pow.f32(float %91, float %32) %95 = call float @llvm.pow.f32(float %92, float %32) %96 = call float @llvm.pow.f32(float %93, float %32) %97 = fadd float %94, %95 %98 = fadd float %97, %96 %99 = fdiv float 1.000000e+00, %98 %100 = fmul float %94, %99 %101 = fmul float %95, %99 %102 = fmul float %96, %99 %103 = fdiv float 1.000000e+00, %29 %104 = fmul float %82, %103 %105 = fmul float %83, %103 %106 = fmul float %29, 0x3FCC8B43A0000000 %107 = fdiv float 1.000000e+00, %30 %108 = fmul float %82, %107 %109 = fmul float %84, %107 %110 = fmul float %30, 0x3FCC8B43A0000000 %111 = fdiv float 1.000000e+00, %31 %112 = fmul float %84, %111 %113 = fmul float %83, %111 %114 = fmul float %31, 0x3FCC8B43A0000000 %115 = fdiv float 1.000000e+00, %114 %116 = fmul float %84, %115 %117 = fmul float %83, %115 %118 = bitcast float %116 to i32 %119 = bitcast float %117 to i32 %120 = insertelement <2 x i32> undef, i32 %118, i32 0 %121 = insertelement <2 x i32> %120, i32 %119, i32 1 %122 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %121, <32 x i8> %64, <16 x i8> %66, i32 2) %123 = extractelement <4 x float> %122, i32 0 %124 = extractelement <4 x float> %122, i32 1 %125 = extractelement <4 x float> %122, i32 2 %126 = bitcast float %112 to i32 %127 = bitcast float %113 to i32 %128 = insertelement <2 x i32> undef, i32 %126, i32 0 %129 = insertelement <2 x i32> %128, i32 %127, i32 1 %130 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %129, <32 x i8> %64, <16 x i8> %66, i32 2) %131 = extractelement <4 x float> %130, i32 0 %132 = extractelement <4 x float> %130, i32 1 %133 = extractelement <4 x float> %130, i32 2 %134 = fmul float 5.000000e-01, %131 %135 = fmul float 5.000000e-01, %132 %136 = fmul float 5.000000e-01, %133 %137 = fmul float 5.000000e-01, %123 %138 = fadd float %137, %134 %139 = fmul float 5.000000e-01, %124 %140 = fadd float %139, %135 %141 = fmul float 5.000000e-01, %125 %142 = fadd float %141, %136 %143 = fdiv float 1.000000e+00, %110 %144 = fmul float %82, %143 %145 = fmul float %84, %143 %146 = bitcast float %144 to i32 %147 = bitcast float %145 to i32 %148 = insertelement <2 x i32> undef, i32 %146, i32 0 %149 = insertelement <2 x i32> %148, i32 %147, i32 1 %150 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %149, <32 x i8> %60, <16 x i8> %62, i32 2) %151 = extractelement <4 x float> %150, i32 0 %152 = extractelement <4 x float> %150, i32 1 %153 = extractelement <4 x float> %150, i32 2 %154 = bitcast float %108 to i32 %155 = bitcast float %109 to i32 %156 = insertelement <2 x i32> undef, i32 %154, i32 0 %157 = insertelement <2 x i32> %156, i32 %155, i32 1 %158 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %157, <32 x i8> %60, <16 x i8> %62, i32 2) %159 = extractelement <4 x float> %158, i32 0 %160 = extractelement <4 x float> %158, i32 1 %161 = extractelement <4 x float> %158, i32 2 %162 = fmul float 5.000000e-01, %159 %163 = fmul float 5.000000e-01, %160 %164 = fmul float 5.000000e-01, %161 %165 = fmul float 5.000000e-01, %151 %166 = fadd float %165, %162 %167 = fmul float 5.000000e-01, %152 %168 = fadd float %167, %163 %169 = fmul float 5.000000e-01, %153 %170 = fadd float %169, %164 %171 = fdiv float 1.000000e+00, %106 %172 = fmul float %82, %171 %173 = fmul float %83, %171 %174 = bitcast float %172 to i32 %175 = bitcast float %173 to i32 %176 = insertelement <2 x i32> undef, i32 %174, i32 0 %177 = insertelement <2 x i32> %176, i32 %175, i32 1 %178 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %177, <32 x i8> %56, <16 x i8> %58, i32 2) %179 = extractelement <4 x float> %178, i32 0 %180 = extractelement <4 x float> %178, i32 1 %181 = extractelement <4 x float> %178, i32 2 %182 = bitcast float %104 to i32 %183 = bitcast float %105 to i32 %184 = insertelement <2 x i32> undef, i32 %182, i32 0 %185 = insertelement <2 x i32> %184, i32 %183, i32 1 %186 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %185, <32 x i8> %56, <16 x i8> %58, i32 2) %187 = extractelement <4 x float> %186, i32 0 %188 = extractelement <4 x float> %186, i32 1 %189 = extractelement <4 x float> %186, i32 2 %190 = fmul float 5.000000e-01, %187 %191 = fmul float 5.000000e-01, %188 %192 = fmul float 5.000000e-01, %189 %193 = fmul float 5.000000e-01, %179 %194 = fadd float %193, %190 %195 = fmul float 5.000000e-01, %180 %196 = fadd float %195, %191 %197 = fmul float 5.000000e-01, %181 %198 = fadd float %197, %192 %199 = fmul float %194, %102 %200 = fmul float %196, %102 %201 = fmul float %198, %102 %202 = fmul float %166, %101 %203 = fadd float %202, %199 %204 = fmul float %168, %101 %205 = fadd float %204, %200 %206 = fmul float %170, %101 %207 = fadd float %206, %201 %208 = fmul float %138, %100 %209 = fadd float %208, %203 %210 = fmul float %140, %100 %211 = fadd float %210, %205 %212 = fmul float %142, %100 %213 = fadd float %212, %207 %214 = fdiv float 1.000000e+00, %106 %215 = fmul float %82, %214 %216 = fmul float %83, %214 %217 = bitcast float %215 to i32 %218 = bitcast float %216 to i32 %219 = insertelement <2 x i32> undef, i32 %217, i32 0 %220 = insertelement <2 x i32> %219, i32 %218, i32 1 %221 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %220, <32 x i8> %68, <16 x i8> %70, i32 2) %222 = extractelement <4 x float> %221, i32 0 %223 = extractelement <4 x float> %221, i32 1 %224 = extractelement <4 x float> %221, i32 2 %225 = bitcast float %104 to i32 %226 = bitcast float %105 to i32 %227 = insertelement <2 x i32> undef, i32 %225, i32 0 %228 = insertelement <2 x i32> %227, i32 %226, i32 1 %229 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %228, <32 x i8> %68, <16 x i8> %70, i32 2) %230 = extractelement <4 x float> %229, i32 0 %231 = extractelement <4 x float> %229, i32 1 %232 = extractelement <4 x float> %229, i32 2 %233 = fmul float 5.000000e-01, %230 %234 = fmul float 5.000000e-01, %231 %235 = fmul float 5.000000e-01, %232 %236 = fmul float 5.000000e-01, %222 %237 = fadd float %236, %233 %238 = fmul float 5.000000e-01, %223 %239 = fadd float %238, %234 %240 = fmul float 5.000000e-01, %224 %241 = fadd float %240, %235 %242 = fmul float %237, 2.000000e+00 %243 = fadd float %242, 0xBFF0100000000000 %244 = fmul float %239, 2.000000e+00 %245 = fadd float %244, 0xBFF0100000000000 %246 = fdiv float 1.000000e+00, %110 %247 = fmul float %82, %246 %248 = fmul float %84, %246 %249 = bitcast float %247 to i32 %250 = bitcast float %248 to i32 %251 = insertelement <2 x i32> undef, i32 %249, i32 0 %252 = insertelement <2 x i32> %251, i32 %250, i32 1 %253 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %252, <32 x i8> %72, <16 x i8> %74, i32 2) %254 = extractelement <4 x float> %253, i32 0 %255 = extractelement <4 x float> %253, i32 1 %256 = extractelement <4 x float> %253, i32 2 %257 = bitcast float %108 to i32 %258 = bitcast float %109 to i32 %259 = insertelement <2 x i32> undef, i32 %257, i32 0 %260 = insertelement <2 x i32> %259, i32 %258, i32 1 %261 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %260, <32 x i8> %72, <16 x i8> %74, i32 2) %262 = extractelement <4 x float> %261, i32 0 %263 = extractelement <4 x float> %261, i32 1 %264 = extractelement <4 x float> %261, i32 2 %265 = fmul float 5.000000e-01, %262 %266 = fmul float 5.000000e-01, %263 %267 = fmul float 5.000000e-01, %264 %268 = fmul float 5.000000e-01, %254 %269 = fadd float %268, %265 %270 = fmul float 5.000000e-01, %255 %271 = fadd float %270, %266 %272 = fmul float 5.000000e-01, %256 %273 = fadd float %272, %267 %274 = fmul float %269, 2.000000e+00 %275 = fadd float %274, 0xBFF0100000000000 %276 = fmul float %271, 2.000000e+00 %277 = fadd float %276, 0xBFF0100000000000 %278 = fdiv float 1.000000e+00, %114 %279 = fmul float %84, %278 %280 = fmul float %83, %278 %281 = bitcast float %279 to i32 %282 = bitcast float %280 to i32 %283 = insertelement <2 x i32> undef, i32 %281, i32 0 %284 = insertelement <2 x i32> %283, i32 %282, i32 1 %285 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %284, <32 x i8> %76, <16 x i8> %78, i32 2) %286 = extractelement <4 x float> %285, i32 0 %287 = extractelement <4 x float> %285, i32 1 %288 = extractelement <4 x float> %285, i32 2 %289 = extractelement <4 x float> %285, i32 3 %290 = bitcast float %112 to i32 %291 = bitcast float %113 to i32 %292 = insertelement <2 x i32> undef, i32 %290, i32 0 %293 = insertelement <2 x i32> %292, i32 %291, i32 1 %294 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %293, <32 x i8> %76, <16 x i8> %78, i32 2) %295 = extractelement <4 x float> %294, i32 0 %296 = extractelement <4 x float> %294, i32 1 %297 = extractelement <4 x float> %294, i32 2 %298 = fmul float 5.000000e-01, %295 %299 = fmul float 5.000000e-01, %296 %300 = fmul float 5.000000e-01, %297 %301 = fmul float 5.000000e-01, %286 %302 = fadd float %301, %298 %303 = fmul float 5.000000e-01, %287 %304 = fadd float %303, %299 %305 = fmul float 5.000000e-01, %288 %306 = fadd float %305, %300 %307 = fmul float %302, 2.000000e+00 %308 = fadd float %307, 0xBFF0100000000000 %309 = fmul float %304, 2.000000e+00 %310 = fadd float %309, 0xBFF0100000000000 %311 = fadd float %88, %89 %312 = fadd float %311, %90 %313 = fdiv float 1.000000e+00, %312 %314 = fmul float %88, %313 %315 = fmul float %89, %313 %316 = fmul float %90, %313 %317 = fcmp ugt float %85, 0.000000e+00 %318 = select i1 %317, float 1.000000e+00, float %85 %319 = fcmp uge float %318, 0.000000e+00 %320 = select i1 %319, float %318, float -1.000000e+00 %321 = fmul float %306, %320 %322 = fmul float %310, %320 %323 = fmul float %308, %320 %324 = fcmp ugt float %86, 0.000000e+00 %325 = select i1 %324, float 1.000000e+00, float %86 %326 = fcmp uge float %325, 0.000000e+00 %327 = select i1 %326, float %325, float -1.000000e+00 %328 = fmul float %275, %327 %329 = fmul float %273, %327 %330 = fmul float %277, %327 %331 = fcmp ugt float %87, 0.000000e+00 %332 = select i1 %331, float 1.000000e+00, float %87 %333 = fcmp uge float %332, 0.000000e+00 %334 = select i1 %333, float %332, float -1.000000e+00 %335 = fmul float %243, %334 %336 = fmul float %245, %334 %337 = fmul float %241, %334 %338 = fmul float %335, %316 %339 = fmul float %336, %316 %340 = fmul float %337, %316 %341 = fmul float %328, %315 %342 = fadd float %341, %338 %343 = fmul float %329, %315 %344 = fadd float %343, %339 %345 = fmul float %330, %315 %346 = fadd float %345, %340 %347 = fmul float %321, %314 %348 = fadd float %347, %342 %349 = fmul float %322, %314 %350 = fadd float %349, %344 %351 = fmul float %323, %314 %352 = fadd float %351, %346 %353 = fmul float %34, %348 %354 = fmul float %35, %348 %355 = fmul float %36, %348 %356 = fmul float %37, %350 %357 = fadd float %356, %353 %358 = fmul float %38, %350 %359 = fadd float %358, %354 %360 = fmul float %39, %350 %361 = fadd float %360, %355 %362 = fmul float %40, %352 %363 = fadd float %362, %357 %364 = fmul float %41, %352 %365 = fadd float %364, %359 %366 = fmul float %42, %352 %367 = fadd float %366, %361 %368 = fmul float %363, %363 %369 = fmul float %365, %365 %370 = fadd float %369, %368 %371 = fmul float %367, %367 %372 = fadd float %370, %371 %373 = call float @llvm.AMDGPU.rsq(float %372) %374 = fmul float %363, %373 %375 = fmul float %365, %373 %376 = fmul float %367, %373 %377 = shl i32 14, 4 %378 = call float @llvm.SI.load.const(<16 x i8> %44, i32 %377) %379 = shl i32 14, 4 %380 = add i32 %379, 4 %381 = call float @llvm.SI.load.const(<16 x i8> %44, i32 %380) %382 = shl i32 14, 4 %383 = add i32 %382, 8 %384 = call float @llvm.SI.load.const(<16 x i8> %44, i32 %383) %385 = shl i32 13, 4 %386 = call float @llvm.SI.load.const(<16 x i8> %44, i32 %385) %387 = shl i32 13, 4 %388 = add i32 %387, 4 %389 = call float @llvm.SI.load.const(<16 x i8> %44, i32 %388) %390 = shl i32 13, 4 %391 = add i32 %390, 8 %392 = call float @llvm.SI.load.const(<16 x i8> %44, i32 %391) %393 = shl i32 12, 4 %394 = call float @llvm.SI.load.const(<16 x i8> %44, i32 %393) %395 = shl i32 12, 4 %396 = add i32 %395, 4 %397 = call float @llvm.SI.load.const(<16 x i8> %44, i32 %396) %398 = shl i32 12, 4 %399 = add i32 %398, 8 %400 = call float @llvm.SI.load.const(<16 x i8> %44, i32 %399) %401 = fmul float %394, %79 %402 = fmul float %397, %79 %403 = fmul float %400, %79 %404 = fmul float %386, %80 %405 = fadd float %404, %401 %406 = fmul float %389, %80 %407 = fadd float %406, %402 %408 = fmul float %392, %80 %409 = fadd float %408, %403 %410 = fmul float %378, %81 %411 = fadd float %410, %405 %412 = fmul float %381, %81 %413 = fadd float %412, %407 %414 = fmul float %384, %81 %415 = fadd float %414, %409 %416 = shl i32 15, 4 %417 = call float @llvm.SI.load.const(<16 x i8> %44, i32 %416) %418 = shl i32 15, 4 %419 = add i32 %418, 4 %420 = call float @llvm.SI.load.const(<16 x i8> %44, i32 %419) %421 = shl i32 15, 4 %422 = add i32 %421, 8 %423 = call float @llvm.SI.load.const(<16 x i8> %44, i32 %422) %424 = fadd float %411, %417 %425 = fadd float %413, %420 %426 = fadd float %415, %423 %427 = shl i32 20, 4 %428 = call float @llvm.SI.load.const(<16 x i8> %44, i32 %427) %429 = shl i32 20, 4 %430 = add i32 %429, 4 %431 = call float @llvm.SI.load.const(<16 x i8> %44, i32 %430) %432 = shl i32 20, 4 %433 = add i32 %432, 8 %434 = call float @llvm.SI.load.const(<16 x i8> %44, i32 %433) %435 = fsub float -0.000000e+00, %428 %436 = fadd float %424, %435 %437 = fsub float -0.000000e+00, %431 %438 = fadd float %425, %437 %439 = fsub float -0.000000e+00, %434 %440 = fadd float %426, %439 %441 = fmul float %436, %436 %442 = fmul float %438, %438 %443 = fadd float %442, %441 %444 = fmul float %440, %440 %445 = fadd float %443, %444 %446 = call float @llvm.AMDGPU.rsq(float %445) %447 = fmul float %436, %446 %448 = fmul float %438, %446 %449 = fmul float %440, %446 %450 = fmul float %374, %447 %451 = fmul float %375, %448 %452 = fadd float %451, %450 %453 = fmul float %376, %449 %454 = fadd float %452, %453 %455 = fmul float %454, %374 %456 = fmul float %454, %375 %457 = fmul float %454, %376 %458 = fmul float 2.000000e+00, %455 %459 = fmul float 2.000000e+00, %456 %460 = fmul float 2.000000e+00, %457 %461 = fsub float -0.000000e+00, %458 %462 = fadd float %447, %461 %463 = fsub float -0.000000e+00, %459 %464 = fadd float %448, %463 %465 = fsub float -0.000000e+00, %460 %466 = fadd float %449, %465 %467 = fadd float %375, 0x3FF0CCCCC0000000 %468 = call float @llvm.AMDIL.clamp.(float %467, float 0.000000e+00, float 1.000000e+00) %469 = shl i32 14, 4 %470 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %469) %471 = shl i32 14, 4 %472 = add i32 %471, 4 %473 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %472) %474 = shl i32 14, 4 %475 = add i32 %474, 8 %476 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %475) %477 = fmul float %468, %470 %478 = fmul float %468, %473 %479 = fmul float %468, %476 %480 = fmul float %209, %477 %481 = fmul float %211, %478 %482 = fmul float %213, %479 %483 = shl i32 12, 4 %484 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %483) %485 = shl i32 12, 4 %486 = add i32 %485, 4 %487 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %486) %488 = shl i32 12, 4 %489 = add i32 %488, 8 %490 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %489) %491 = shl i32 13, 4 %492 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %491) %493 = shl i32 13, 4 %494 = add i32 %493, 4 %495 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %494) %496 = shl i32 13, 4 %497 = add i32 %496, 8 %498 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %497) %499 = fmul float %374, %484 %500 = fmul float %375, %487 %501 = fadd float %500, %499 %502 = fmul float %376, %490 %503 = fadd float %501, %502 %504 = fcmp uge float 0.000000e+00, %503 %505 = select i1 %504, float 0.000000e+00, float %503 %506 = fmul float %505, %492 %507 = fmul float %505, %495 %508 = fmul float %505, %498 %509 = fmul float %506, %209 %510 = fmul float %507, %211 %511 = fmul float %508, %213 %512 = fmul float %462, %484 %513 = fmul float %464, %487 %514 = fadd float %513, %512 %515 = fmul float %466, %490 %516 = fadd float %514, %515 %517 = fcmp uge float 0x3F50624DE0000000, %516 %518 = select i1 %517, float 0x3F50624DE0000000, float %516 %519 = call float @llvm.pow.f32(float %518, float %28) %520 = fmul float %519, %492 %521 = fmul float %519, %495 %522 = fmul float %519, %498 %523 = fmul float %520, %25 %524 = fadd float %523, %509 %525 = fmul float %521, %26 %526 = fadd float %525, %510 %527 = fmul float %522, %27 %528 = fadd float %527, %511 %529 = shl i32 15, 4 %530 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %529) %531 = shl i32 15, 4 %532 = add i32 %531, 4 %533 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %532) %534 = shl i32 15, 4 %535 = add i32 %534, 8 %536 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %535) %537 = fsub float -0.000000e+00, %530 %538 = fadd float %424, %537 %539 = fsub float -0.000000e+00, %533 %540 = fadd float %425, %539 %541 = fsub float -0.000000e+00, %536 %542 = fadd float %426, %541 %543 = fmul float %538, %538 %544 = fmul float %540, %540 %545 = fadd float %544, %543 %546 = fmul float %542, %542 %547 = fadd float %545, %546 %548 = call float @llvm.AMDGPU.rsq(float %547) %549 = fmul float %548, %547 %550 = fsub float -0.000000e+00, %547 %551 = call float @llvm.AMDGPU.cndlt(float %550, float %549, float 0.000000e+00) %552 = shl i32 16, 4 %553 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %552) %554 = fmul float 0x3FE99999A0000000, %553 %555 = fcmp olt float %551, %554 %556 = sext i1 %555 to i32 %557 = bitcast i32 %556 to float %558 = bitcast float %557 to i32 %559 = icmp ne i32 %558, 0 br i1 %559, label %IF, label %ELSE IF: ; preds = %main_body %560 = shl i32 6, 4 %561 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %560) %562 = shl i32 6, 4 %563 = add i32 %562, 4 %564 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %563) %565 = shl i32 6, 4 %566 = add i32 %565, 8 %567 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %566) %568 = shl i32 5, 4 %569 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %568) %570 = shl i32 5, 4 %571 = add i32 %570, 4 %572 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %571) %573 = shl i32 5, 4 %574 = add i32 %573, 8 %575 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %574) %576 = shl i32 4, 4 %577 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %576) %578 = shl i32 4, 4 %579 = add i32 %578, 4 %580 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %579) %581 = shl i32 4, 4 %582 = add i32 %581, 8 %583 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %582) %584 = fmul float %577, %424 %585 = fmul float %580, %424 %586 = fmul float %583, %424 %587 = fmul float %569, %425 %588 = fadd float %587, %584 %589 = fmul float %572, %425 %590 = fadd float %589, %585 %591 = fmul float %575, %425 %592 = fadd float %591, %586 %593 = fmul float %561, %426 %594 = fadd float %593, %588 %595 = fmul float %564, %426 %596 = fadd float %595, %590 %597 = fmul float %567, %426 %598 = fadd float %597, %592 %599 = shl i32 7, 4 %600 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %599) %601 = shl i32 7, 4 %602 = add i32 %601, 4 %603 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %602) %604 = shl i32 7, 4 %605 = add i32 %604, 8 %606 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %605) %607 = fadd float %594, %600 %608 = fadd float %596, %603 %609 = fadd float %598, %606 %610 = shl i32 15, 4 %611 = add i32 %610, 12 %612 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %611) %613 = fcmp uge float %609, -1.000000e+00 %614 = select i1 %613, float %609, float -1.000000e+00 %615 = fcmp uge float %614, 1.000000e+00 %616 = select i1 %615, float 1.000000e+00, float %614 %617 = fadd float %616, 1.000000e+00 %618 = fsub float -0.000000e+00, %612 %619 = fmul float %618, %617 %620 = fmul float 0x3FE7154760000000, %619 %621 = call float @llvm.AMDIL.exp.(float %620) %622 = fmul float %607, 5.000000e-01 %623 = fadd float %622, 5.000000e-01 %624 = fmul float %608, 5.000000e-01 %625 = fadd float %624, 5.000000e-01 %626 = shl i32 16, 4 %627 = add i32 %626, 8 %628 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %627) %629 = fmul float %623, %628 %630 = fmul float %625, %628 %631 = bitcast float %629 to i32 %632 = bitcast float %630 to i32 %633 = insertelement <2 x i32> undef, i32 %631, i32 0 %634 = insertelement <2 x i32> %633, i32 %632, i32 1 %635 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %634, <32 x i8> %48, <16 x i8> %50, i32 5) %636 = extractelement <4 x float> %635, i32 0 %637 = fmul float %621, %636 %638 = call float @llvm.AMDIL.clamp.(float %637, float 0.000000e+00, float 1.000000e+00) br label %ENDIF ELSE: ; preds = %main_body %639 = shl i32 16, 4 %640 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %639) %641 = fcmp olt float %640, %551 %642 = sext i1 %641 to i32 %643 = bitcast i32 %642 to float %644 = bitcast float %643 to i32 %645 = icmp ne i32 %644, 0 br i1 %645, label %IF219, label %ELSE220 ENDIF: ; preds = %IF219, %ELSE220, %IF %temp28.0 = phi float [ %638, %IF ], [ %779, %IF219 ], [ %947, %ELSE220 ] %646 = fadd float %temp28.0, 0xBFE99999A0000000 %647 = fmul float %646, 0x4014000020000000 %648 = call float @llvm.AMDIL.clamp.(float %647, float 0.000000e+00, float 1.000000e+00) %649 = fmul float 2.000000e+00, %648 %650 = fsub float -0.000000e+00, %649 %651 = fadd float 3.000000e+00, %650 %652 = fmul float %648, %651 %653 = fmul float %648, %652 %654 = fmul float %524, %653 %655 = fmul float %526, %653 %656 = fmul float %528, %653 %657 = fadd float %480, %654 %658 = fadd float %481, %655 %659 = fadd float %482, %656 %660 = bitcast float %24 to i32 %661 = fsub float -0.000000e+00, %424 %662 = fsub float -0.000000e+00, %425 %663 = fsub float -0.000000e+00, %426 br label %LOOP IF219: ; preds = %ELSE %664 = shl i32 10, 4 %665 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %664) %666 = shl i32 10, 4 %667 = add i32 %666, 4 %668 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %667) %669 = shl i32 10, 4 %670 = add i32 %669, 8 %671 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %670) %672 = shl i32 9, 4 %673 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %672) %674 = shl i32 9, 4 %675 = add i32 %674, 4 %676 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %675) %677 = shl i32 9, 4 %678 = add i32 %677, 8 %679 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %678) %680 = shl i32 8, 4 %681 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %680) %682 = shl i32 8, 4 %683 = add i32 %682, 4 %684 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %683) %685 = shl i32 8, 4 %686 = add i32 %685, 8 %687 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %686) %688 = fmul float %681, %424 %689 = fmul float %684, %424 %690 = fmul float %687, %424 %691 = fmul float %673, %425 %692 = fadd float %691, %688 %693 = fmul float %676, %425 %694 = fadd float %693, %689 %695 = fmul float %679, %425 %696 = fadd float %695, %690 %697 = fmul float %665, %426 %698 = fadd float %697, %692 %699 = fmul float %668, %426 %700 = fadd float %699, %694 %701 = fmul float %671, %426 %702 = fadd float %701, %696 %703 = shl i32 11, 4 %704 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %703) %705 = shl i32 11, 4 %706 = add i32 %705, 4 %707 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %706) %708 = shl i32 11, 4 %709 = add i32 %708, 8 %710 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %709) %711 = fadd float %698, %704 %712 = fadd float %700, %707 %713 = fadd float %702, %710 %714 = shl i32 15, 4 %715 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %714) %716 = shl i32 15, 4 %717 = add i32 %716, 4 %718 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %717) %719 = shl i32 15, 4 %720 = add i32 %719, 8 %721 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %720) %722 = fsub float -0.000000e+00, %715 %723 = fadd float %424, %722 %724 = fsub float -0.000000e+00, %718 %725 = fadd float %425, %724 %726 = fsub float -0.000000e+00, %721 %727 = fadd float %426, %726 %728 = fmul float %723, %723 %729 = fmul float %725, %725 %730 = fadd float %729, %728 %731 = fmul float %727, %727 %732 = fadd float %730, %731 %733 = call float @llvm.AMDGPU.rsq(float %732) %734 = fmul float %733, %732 %735 = fsub float -0.000000e+00, %732 %736 = call float @llvm.AMDGPU.cndlt(float %735, float %734, float 0.000000e+00) %737 = shl i32 16, 4 %738 = add i32 %737, 4 %739 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %738) %740 = fdiv float 1.000000e+00, %739 %741 = fmul float %736, %740 %742 = fadd float %741, 0xBFE99999A0000000 %743 = fmul float %742, 0x4014000020000000 %744 = call float @llvm.AMDIL.clamp.(float %743, float 0.000000e+00, float 1.000000e+00) %745 = shl i32 15, 4 %746 = add i32 %745, 12 %747 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %746) %748 = fcmp uge float %713, -1.000000e+00 %749 = select i1 %748, float %713, float -1.000000e+00 %750 = fcmp uge float %749, 1.000000e+00 %751 = select i1 %750, float 1.000000e+00, float %749 %752 = fadd float %751, 1.000000e+00 %753 = fsub float -0.000000e+00, %747 %754 = fmul float %753, %752 %755 = fmul float 0x3FE7154760000000, %754 %756 = call float @llvm.AMDIL.exp.(float %755) %757 = fmul float %711, 5.000000e-01 %758 = fadd float %757, 5.000000e-01 %759 = fmul float %712, 5.000000e-01 %760 = fadd float %759, 5.000000e-01 %761 = shl i32 16, 4 %762 = add i32 %761, 8 %763 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %762) %764 = fmul float %758, %763 %765 = fmul float %760, %763 %766 = bitcast float %764 to i32 %767 = bitcast float %765 to i32 %768 = insertelement <2 x i32> undef, i32 %766, i32 0 %769 = insertelement <2 x i32> %768, i32 %767, i32 1 %770 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %769, <32 x i8> %52, <16 x i8> %54, i32 5) %771 = extractelement <4 x float> %770, i32 0 %772 = fmul float %756, %771 %773 = call float @llvm.AMDIL.clamp.(float %772, float 0.000000e+00, float 1.000000e+00) %774 = fmul float 2.000000e+00, %744 %775 = fsub float -0.000000e+00, %774 %776 = fadd float 3.000000e+00, %775 %777 = fmul float %744, %776 %778 = fmul float %744, %777 %779 = call float @llvm.AMDGPU.lrp(float %778, float 1.000000e+00, float %773) br label %ENDIF ELSE220: ; preds = %ELSE %780 = shl i32 6, 4 %781 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %780) %782 = shl i32 6, 4 %783 = add i32 %782, 4 %784 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %783) %785 = shl i32 6, 4 %786 = add i32 %785, 8 %787 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %786) %788 = shl i32 5, 4 %789 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %788) %790 = shl i32 5, 4 %791 = add i32 %790, 4 %792 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %791) %793 = shl i32 5, 4 %794 = add i32 %793, 8 %795 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %794) %796 = shl i32 4, 4 %797 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %796) %798 = shl i32 4, 4 %799 = add i32 %798, 4 %800 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %799) %801 = shl i32 4, 4 %802 = add i32 %801, 8 %803 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %802) %804 = fmul float %797, %424 %805 = fmul float %800, %424 %806 = fmul float %803, %424 %807 = fmul float %789, %425 %808 = fadd float %807, %804 %809 = fmul float %792, %425 %810 = fadd float %809, %805 %811 = fmul float %795, %425 %812 = fadd float %811, %806 %813 = fmul float %781, %426 %814 = fadd float %813, %808 %815 = fmul float %784, %426 %816 = fadd float %815, %810 %817 = fmul float %787, %426 %818 = fadd float %817, %812 %819 = shl i32 7, 4 %820 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %819) %821 = shl i32 7, 4 %822 = add i32 %821, 4 %823 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %822) %824 = shl i32 7, 4 %825 = add i32 %824, 8 %826 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %825) %827 = fadd float %814, %820 %828 = fadd float %816, %823 %829 = fadd float %818, %826 %830 = shl i32 10, 4 %831 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %830) %832 = shl i32 10, 4 %833 = add i32 %832, 4 %834 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %833) %835 = shl i32 10, 4 %836 = add i32 %835, 8 %837 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %836) %838 = shl i32 9, 4 %839 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %838) %840 = shl i32 9, 4 %841 = add i32 %840, 4 %842 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %841) %843 = shl i32 9, 4 %844 = add i32 %843, 8 %845 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %844) %846 = shl i32 8, 4 %847 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %846) %848 = shl i32 8, 4 %849 = add i32 %848, 4 %850 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %849) %851 = shl i32 8, 4 %852 = add i32 %851, 8 %853 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %852) %854 = fmul float %847, %424 %855 = fmul float %850, %424 %856 = fmul float %853, %424 %857 = fmul float %839, %425 %858 = fadd float %857, %854 %859 = fmul float %842, %425 %860 = fadd float %859, %855 %861 = fmul float %845, %425 %862 = fadd float %861, %856 %863 = fmul float %831, %426 %864 = fadd float %863, %858 %865 = fmul float %834, %426 %866 = fadd float %865, %860 %867 = fmul float %837, %426 %868 = fadd float %867, %862 %869 = shl i32 11, 4 %870 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %869) %871 = shl i32 11, 4 %872 = add i32 %871, 4 %873 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %872) %874 = shl i32 11, 4 %875 = add i32 %874, 8 %876 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %875) %877 = fadd float %864, %870 %878 = fadd float %866, %873 %879 = fadd float %868, %876 %880 = shl i32 16, 4 %881 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %880) %882 = fmul float 0x3FE99999A0000000, %881 %883 = fsub float -0.000000e+00, %882 %884 = fadd float %551, %883 %885 = fsub float -0.000000e+00, %882 %886 = fadd float %881, %885 %887 = fdiv float 1.000000e+00, %886 %888 = fmul float %884, %887 %889 = call float @llvm.AMDIL.clamp.(float %888, float 0.000000e+00, float 1.000000e+00) %890 = shl i32 15, 4 %891 = add i32 %890, 12 %892 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %891) %893 = shl i32 16, 4 %894 = add i32 %893, 8 %895 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %894) %896 = fcmp uge float %829, -1.000000e+00 %897 = select i1 %896, float %829, float -1.000000e+00 %898 = fcmp uge float %897, 1.000000e+00 %899 = select i1 %898, float 1.000000e+00, float %897 %900 = fadd float %899, 1.000000e+00 %901 = fsub float -0.000000e+00, %892 %902 = fmul float %901, %900 %903 = fmul float 0x3FE7154760000000, %902 %904 = call float @llvm.AMDIL.exp.(float %903) %905 = fmul float %827, 5.000000e-01 %906 = fadd float %905, 5.000000e-01 %907 = fmul float %828, 5.000000e-01 %908 = fadd float %907, 5.000000e-01 %909 = fmul float %906, %895 %910 = fmul float %908, %895 %911 = bitcast float %909 to i32 %912 = bitcast float %910 to i32 %913 = insertelement <2 x i32> undef, i32 %911, i32 0 %914 = insertelement <2 x i32> %913, i32 %912, i32 1 %915 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %914, <32 x i8> %48, <16 x i8> %50, i32 5) %916 = extractelement <4 x float> %915, i32 0 %917 = fmul float %904, %916 %918 = call float @llvm.AMDIL.clamp.(float %917, float 0.000000e+00, float 1.000000e+00) %919 = fcmp uge float %879, -1.000000e+00 %920 = select i1 %919, float %879, float -1.000000e+00 %921 = fcmp uge float %920, 1.000000e+00 %922 = select i1 %921, float 1.000000e+00, float %920 %923 = fadd float %922, 1.000000e+00 %924 = fsub float -0.000000e+00, %892 %925 = fmul float %924, %923 %926 = fmul float 0x3FE7154760000000, %925 %927 = call float @llvm.AMDIL.exp.(float %926) %928 = fmul float %877, 5.000000e-01 %929 = fadd float %928, 5.000000e-01 %930 = fmul float %878, 5.000000e-01 %931 = fadd float %930, 5.000000e-01 %932 = fmul float %929, %895 %933 = fmul float %931, %895 %934 = bitcast float %932 to i32 %935 = bitcast float %933 to i32 %936 = insertelement <2 x i32> undef, i32 %934, i32 0 %937 = insertelement <2 x i32> %936, i32 %935, i32 1 %938 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %937, <32 x i8> %52, <16 x i8> %54, i32 5) %939 = extractelement <4 x float> %938, i32 0 %940 = fmul float %927, %939 %941 = call float @llvm.AMDIL.clamp.(float %940, float 0.000000e+00, float 1.000000e+00) %942 = fmul float 2.000000e+00, %889 %943 = fsub float -0.000000e+00, %942 %944 = fadd float 3.000000e+00, %943 %945 = fmul float %889, %944 %946 = fmul float %889, %945 %947 = call float @llvm.AMDGPU.lrp(float %946, float %941, float %918) br label %ENDIF LOOP: ; preds = %ENDIF278, %ENDIF %temp38.0 = phi float [ %659, %ENDIF ], [ %1076, %ENDIF278 ] %temp37.0 = phi float [ %658, %ENDIF ], [ %1075, %ENDIF278 ] %temp36.0 = phi float [ %657, %ENDIF ], [ %1074, %ENDIF278 ] %temp.0 = phi float [ 0.000000e+00, %ENDIF ], [ %1079, %ENDIF278 ] %948 = bitcast float %temp.0 to i32 %949 = icmp sge i32 %948, %660 %950 = sext i1 %949 to i32 %951 = bitcast i32 %950 to float %952 = bitcast float %951 to i32 %953 = icmp ne i32 %952, 0 br i1 %953, label %IF279, label %ENDIF278 IF279: ; preds = %LOOP %temp36.0.lcssa = phi float [ %temp36.0, %LOOP ] %temp37.0.lcssa = phi float [ %temp37.0, %LOOP ] %temp38.0.lcssa = phi float [ %temp38.0, %LOOP ] %954 = fmul float %temp36.0.lcssa, %33 %955 = fmul float %temp37.0.lcssa, %33 %956 = fmul float %temp38.0.lcssa, %33 %957 = call i32 @llvm.SI.packf16(float %954, float %955) %958 = bitcast i32 %957 to float %959 = call i32 @llvm.SI.packf16(float %956, float %289) %960 = bitcast i32 %959 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %958, float %960, float %958, float %960) ret void ENDIF278: ; preds = %LOOP %961 = bitcast float %temp.0 to i32 %962 = mul i32 %961, 7 %963 = bitcast i32 %962 to float %964 = bitcast float %963 to i32 %965 = shl i32 %964, 4 %966 = add i32 %965, 64 %967 = call float @llvm.SI.load.const(<16 x i8> %23, i32 %966) %968 = bitcast float %963 to i32 %969 = add i32 %968, 1 %970 = bitcast i32 %969 to float %971 = bitcast float %970 to i32 %972 = shl i32 %971, 4 %973 = add i32 %972, 64 %974 = call float @llvm.SI.load.const(<16 x i8> %23, i32 %973) %975 = bitcast float %963 to i32 %976 = add i32 %975, 2 %977 = bitcast i32 %976 to float %978 = bitcast float %977 to i32 %979 = shl i32 %978, 4 %980 = add i32 %979, 64 %981 = call float @llvm.SI.load.const(<16 x i8> %23, i32 %980) %982 = bitcast float %963 to i32 %983 = add i32 %982, 3 %984 = bitcast i32 %983 to float %985 = bitcast float %984 to i32 %986 = shl i32 %985, 4 %987 = add i32 %986, 64 %988 = call float @llvm.SI.load.const(<16 x i8> %23, i32 %987) %989 = bitcast float %963 to i32 %990 = add i32 %989, 4 %991 = bitcast i32 %990 to float %992 = bitcast float %991 to i32 %993 = shl i32 %992, 4 %994 = add i32 %993, 64 %995 = call float @llvm.SI.load.const(<16 x i8> %23, i32 %994) %996 = bitcast float %963 to i32 %997 = add i32 %996, 5 %998 = bitcast i32 %997 to float %999 = bitcast float %998 to i32 %1000 = shl i32 %999, 4 %1001 = add i32 %1000, 64 %1002 = call float @llvm.SI.load.const(<16 x i8> %23, i32 %1001) %1003 = bitcast float %963 to i32 %1004 = add i32 %1003, 6 %1005 = bitcast i32 %1004 to float %1006 = bitcast float %1005 to i32 %1007 = shl i32 %1006, 4 %1008 = add i32 %1007, 64 %1009 = call float @llvm.SI.load.const(<16 x i8> %23, i32 %1008) %1010 = fadd float %967, %661 %1011 = fadd float %974, %662 %1012 = fadd float %981, %663 %1013 = fmul float %1010, %1010 %1014 = fmul float %1011, %1011 %1015 = fadd float %1014, %1013 %1016 = fmul float %1012, %1012 %1017 = fadd float %1015, %1016 %1018 = call float @llvm.AMDGPU.rsq(float %1017) %1019 = fmul float %1018, %1017 %1020 = fsub float -0.000000e+00, %1017 %1021 = call float @llvm.AMDGPU.cndlt(float %1020, float %1019, float 0.000000e+00) %1022 = fdiv float 1.000000e+00, %1021 %1023 = fmul float %1010, %1022 %1024 = fmul float %1011, %1022 %1025 = fmul float %1012, %1022 %1026 = fmul float %374, %1023 %1027 = fmul float %375, %1024 %1028 = fadd float %1027, %1026 %1029 = fmul float %376, %1025 %1030 = fadd float %1028, %1029 %1031 = fcmp uge float 0.000000e+00, %1030 %1032 = select i1 %1031, float 0.000000e+00, float %1030 %1033 = fmul float %1032, %988 %1034 = fmul float %1032, %995 %1035 = fmul float %1032, %1002 %1036 = fmul float %1033, %209 %1037 = fmul float %1034, %211 %1038 = fmul float %1035, %213 %1039 = fmul float %462, %1023 %1040 = fmul float %464, %1024 %1041 = fadd float %1040, %1039 %1042 = fmul float %466, %1025 %1043 = fadd float %1041, %1042 %1044 = fcmp uge float 0x3F50624DE0000000, %1043 %1045 = select i1 %1044, float 0x3F50624DE0000000, float %1043 %1046 = call float @llvm.pow.f32(float %1045, float %28) %1047 = fmul float %1046, %988 %1048 = fmul float %1046, %995 %1049 = fmul float %1046, %1002 %1050 = fmul float %1047, %25 %1051 = fadd float %1050, %1036 %1052 = fmul float %1048, %26 %1053 = fadd float %1052, %1037 %1054 = fmul float %1049, %27 %1055 = fadd float %1054, %1038 %1056 = fmul float %1009, 5.000000e-01 %1057 = fsub float -0.000000e+00, %1056 %1058 = fadd float %1021, %1057 %1059 = fsub float -0.000000e+00, %1056 %1060 = fadd float %1009, %1059 %1061 = fdiv float 1.000000e+00, %1060 %1062 = fmul float %1058, %1061 %1063 = call float @llvm.AMDIL.clamp.(float %1062, float 0.000000e+00, float 1.000000e+00) %1064 = fmul float 2.000000e+00, %1063 %1065 = fsub float -0.000000e+00, %1064 %1066 = fadd float 3.000000e+00, %1065 %1067 = fmul float %1063, %1066 %1068 = fmul float %1063, %1067 %1069 = fsub float -0.000000e+00, %1068 %1070 = fadd float 1.000000e+00, %1069 %1071 = fmul float %1051, %1070 %1072 = fmul float %1053, %1070 %1073 = fmul float %1055, %1070 %1074 = fadd float %temp36.0, %1071 %1075 = fadd float %temp37.0, %1072 %1076 = fadd float %temp38.0, %1073 %1077 = bitcast float %temp.0 to i32 %1078 = add i32 %1077, 1 %1079 = bitcast i32 %1078 to float br label %LOOP } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: readonly declare float @fabs(float) #2 ; Function Attrs: nounwind readonly declare float @llvm.pow.f32(float, float) #3 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1 ; Function Attrs: readnone declare float @llvm.AMDGPU.rsq(float) #4 ; Function Attrs: readnone declare float @llvm.AMDIL.clamp.(float, float, float) #4 ; Function Attrs: readnone declare float @llvm.AMDGPU.cndlt(float, float, float) #4 ; Function Attrs: readnone declare float @llvm.AMDIL.exp.(float) #4 ; Function Attrs: readnone declare float @llvm.AMDGPU.lrp(float, float, float) #4 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } attributes #2 = { readonly } attributes #3 = { nounwind readonly } attributes #4 = { readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s9 ; BEFC0309 V_INTERP_P1_F32 v2, v0, 3, 1, [m0] ; C8080700 V_INTERP_P2_F32 v2, [v2], v1, 3, 1, [m0] ; C8090701 V_CMP_U_F32_e64 s[6:7], v2, v2, 0, 0, 0, 0 ; D0100006 02020502 V_CMP_GT_F32_e64 s[10:11], v2, 0.000000e+00, 0, 0, 0, 0 ; D008000A 02010102 S_OR_B64 s[6:7], s[10:11], s[6:7] ; 8886060A V_CNDMASK_B32_e64 v3, v2, 1.000000e+00, s[6:7], 0, 0, 0, 0 ; D2000003 0019E502 V_CMP_U_F32_e64 s[6:7], v3, v3, 0, 0, 0, 0 ; D0100006 02020703 V_CMP_GE_F32_e64 s[10:11], v3, 0.000000e+00, 0, 0, 0, 0 ; D00C000A 02010103 S_OR_B64 s[6:7], s[10:11], s[6:7] ; 8886060A V_CNDMASK_B32_e64 v6, -1.000000e+00, v3, s[6:7], 0, 0, 0, 0 ; D2000006 001A06F3 V_INTERP_P1_F32 v7, v0, 1, 1, [m0] ; C81C0500 V_INTERP_P2_F32 v7, [v7], v1, 1, 1, [m0] ; C81D0501 S_LOAD_DWORDX4 s[12:15], s[0:1], 0 ; C0860100 S_MOV_B32 s6, 1312 ; BE8603FF 00000520 S_WAITCNT lgkmcnt(0) ; BF8C007F S_BUFFER_LOAD_DWORD s6, s[12:15], s6 ; C2030C06 V_MOV_B32_e32 v3, 2.230000e-01 ; 7E0602FF 3E645A1D S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v4, s6, v3 ; 10080606 V_RCP_F32_e32 v4, v4 ; 7E085504 V_MUL_F32_e32 v16, v7, v4 ; 10200907 V_INTERP_P1_F32 v5, v0, 3, 0, [m0] ; C8140300 V_INTERP_P2_F32 v5, [v5], v1, 3, 0, [m0] ; C8150301 V_MUL_F32_e32 v15, v5, v4 ; 101E0905 S_LOAD_DWORDX4 s[16:19], s[2:3], 24 ; C0880318 S_LOAD_DWORDX8 s[20:27], s[4:5], 48 ; C0CA0530 S_WAITCNT lgkmcnt(0) ; BF8C007F IMAGE_SAMPLE v[8:10], 7, 0, 0, 0, 0, 0, 0, 0, v[15:16], s[20:27], s[16:19] ; F0800700 0085080F V_RCP_F32_e32 v4, s6 ; 7E085406 V_MUL_F32_e32 v18, v7, v4 ; 10240907 V_MUL_F32_e32 v17, v5, v4 ; 10220905 IMAGE_SAMPLE v[11:13], 7, 0, 0, 0, 0, 0, 0, 0, v[17:18], s[20:27], s[16:19] ; F0800700 00850B11 S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e64 v4, v13, 5.000000e-01, 0, 0, 0, 0 ; D2100004 0201E10D V_MAD_F32 v4, v10, 5.000000e-01, v4, 0, 0, 0, 0 ; D2820004 0411E10A V_MUL_F32_e32 v4, v4, v6 ; 10080D04 V_INTERP_P1_F32 v14, v0, 0, 2, [m0] ; C8380800 V_INTERP_P2_F32 v14, [v14], v1, 0, 2, [m0] ; C8390801 V_CMP_U_F32_e64 s[6:7], v14, v14, 0, 0, 0, 0 ; D0100006 02021D0E V_CMP_GT_F32_e64 s[10:11], v14, 0.000000e+00, 0, 0, 0, 0 ; D008000A 0201010E S_OR_B64 s[6:7], s[10:11], s[6:7] ; 8886060A V_CNDMASK_B32_e64 v19, v14, 1.000000e+00, s[6:7], 0, 0, 0, 0 ; D2000013 0019E50E V_CMP_U_F32_e64 s[6:7], v19, v19, 0, 0, 0, 0 ; D0100006 02022713 V_CMP_GE_F32_e64 s[10:11], v19, 0.000000e+00, 0, 0, 0, 0 ; D00C000A 02010113 S_OR_B64 s[6:7], s[10:11], s[6:7] ; 8886060A V_CNDMASK_B32_e64 v19, -1.000000e+00, v19, s[6:7], 0, 0, 0, 0 ; D2000013 001A26F3 V_INTERP_P1_F32 v20, v0, 0, 1, [m0] ; C8500400 V_INTERP_P2_F32 v20, [v20], v1, 0, 1, [m0] ; C8510401 S_MOV_B32 s6, 1296 ; BE8603FF 00000510 S_BUFFER_LOAD_DWORD s6, s[12:15], s6 ; C2030C06 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v21, s6, v3 ; 102A0606 V_RCP_F32_e32 v21, v21 ; 7E2A5515 V_MUL_F32_e32 v23, v20, v21 ; 102E2B14 V_MUL_F32_e32 v22, v5, v21 ; 102C2B05 S_LOAD_DWORDX4 s[16:19], s[2:3], 20 ; C0880314 S_LOAD_DWORDX8 s[20:27], s[4:5], 40 ; C0CA0528 S_WAITCNT lgkmcnt(0) ; BF8C007F IMAGE_SAMPLE v[24:26], 7, 0, 0, 0, 0, 0, 0, 0, v[22:23], s[20:27], s[16:19] ; F0800700 00851816 V_RCP_F32_e32 v21, s6 ; 7E2A5406 V_MUL_F32_e32 v28, v20, v21 ; 10382B14 V_MUL_F32_e32 v27, v5, v21 ; 10362B05 IMAGE_SAMPLE v[29:31], 7, 0, 0, 0, 0, 0, 0, 0, v[27:28], s[20:27], s[16:19] ; F0800700 00851D1B S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e64 v5, v30, 5.000000e-01, 0, 0, 0, 0 ; D2100005 0201E11E V_MAD_F32 v5, v25, 5.000000e-01, v5, 0, 0, 0, 0 ; D2820005 0415E119 V_ADD_F32_e32 v5, v5, v5 ; 060A0B05 V_ADD_F32_e32 v5, -1.003906e+00, v5 ; 060A0AFF BF808000 V_MUL_F32_e32 v5, v5, v19 ; 100A2705 V_AND_B32_e32 v39, 2147483647, v2 ; 364E04FF 7FFFFFFF V_INTERP_P1_F32 v2, v0, 2, 1, [m0] ; C8080600 V_INTERP_P2_F32 v2, [v2], v1, 2, 1, [m0] ; C8090601 V_AND_B32_e32 v43, 2147483647, v2 ; 365604FF 7FFFFFFF V_ADD_F32_e32 v21, v43, v39 ; 062A4F2B V_AND_B32_e32 v40, 2147483647, v14 ; 36501CFF 7FFFFFFF V_ADD_F32_e32 v14, v21, v40 ; 061C5115 V_RCP_F32_e32 v14, v14 ; 7E1C550E V_MUL_F32_e32 v21, v40, v14 ; 102A1D28 V_MUL_F32_e32 v5, v5, v21 ; 100A2B05 V_MUL_F32_e32 v32, v39, v14 ; 10401D27 V_MAD_F32 v33, v4, v32, v5, 0, 0, 0, 0 ; D2820021 04164104 V_CMP_U_F32_e64 s[6:7], v2, v2, 0, 0, 0, 0 ; D0100006 02020502 V_CMP_GT_F32_e64 s[10:11], v2, 0.000000e+00, 0, 0, 0, 0 ; D008000A 02010102 S_OR_B64 s[6:7], s[10:11], s[6:7] ; 8886060A V_CNDMASK_B32_e64 v2, v2, 1.000000e+00, s[6:7], 0, 0, 0, 0 ; D2000002 0019E502 V_CMP_U_F32_e64 s[6:7], v2, v2, 0, 0, 0, 0 ; D0100006 02020502 V_CMP_GE_F32_e64 s[10:11], v2, 0.000000e+00, 0, 0, 0, 0 ; D00C000A 02010102 S_OR_B64 s[6:7], s[10:11], s[6:7] ; 8886060A V_CNDMASK_B32_e64 v34, -1.000000e+00, v2, s[6:7], 0, 0, 0, 0 ; D2000022 001A04F3 S_MOV_B32 s6, 1328 ; BE8603FF 00000530 S_BUFFER_LOAD_DWORD s6, s[12:15], s6 ; C2030C06 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v2, s6, v3 ; 10040606 V_RCP_F32_e32 v2, v2 ; 7E045502 V_MUL_F32_e32 v45, v20, v2 ; 105A0514 V_MUL_F32_e32 v44, v7, v2 ; 10580507 S_LOAD_DWORDX4 s[16:19], s[2:3], 28 ; C088031C S_LOAD_DWORDX8 s[20:27], s[4:5], 56 ; C0CA0538 S_WAITCNT lgkmcnt(0) ; BF8C007F IMAGE_SAMPLE v[2:5], 15, 0, 0, 0, 0, 0, 0, 0, v[44:45], s[20:27], s[16:19] ; F0800F00 0085022C V_RCP_F32_e32 v35, s6 ; 7E465406 V_MUL_F32_e32 v47, v20, v35 ; 105E4714 V_MUL_F32_e32 v46, v7, v35 ; 105C4707 IMAGE_SAMPLE v[35:37], 7, 0, 0, 0, 0, 0, 0, 0, v[46:47], s[20:27], s[16:19] ; F0800700 0085232E S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e64 v7, v36, 5.000000e-01, 0, 0, 0, 0 ; D2100007 0201E124 V_MAD_F32 v7, v3, 5.000000e-01, v7, 0, 0, 0, 0 ; D2820007 041DE103 V_ADD_F32_e32 v7, v7, v7 ; 060E0F07 V_ADD_F32_e32 v7, -1.003906e+00, v7 ; 060E0EFF BF808000 V_MUL_F32_e32 v7, v7, v34 ; 100E4507 V_MUL_F32_e32 v14, v43, v14 ; 101C1D2B V_MAD_F32 v7, v7, v14, v33, 0, 0, 0, 0 ; D2820007 04861D07 V_MUL_F32_e64 v20, v11, 5.000000e-01, 0, 0, 0, 0 ; D2100014 0201E10B V_MAD_F32 v20, v8, 5.000000e-01, v20, 0, 0, 0, 0 ; D2820014 0451E108 V_ADD_F32_e32 v20, v20, v20 ; 06282914 V_ADD_F32_e32 v20, -1.003906e+00, v20 ; 062828FF BF808000 V_MUL_F32_e32 v20, v20, v6 ; 10280D14 V_MUL_F32_e64 v33, v29, 5.000000e-01, 0, 0, 0, 0 ; D2100021 0201E11D V_MAD_F32 v33, v24, 5.000000e-01, v33, 0, 0, 0, 0 ; D2820021 0485E118 V_ADD_F32_e32 v33, v33, v33 ; 06424321 V_ADD_F32_e32 v33, -1.003906e+00, v33 ; 064242FF BF808000 V_MUL_F32_e32 v33, v33, v19 ; 10422721 V_MUL_F32_e32 v33, v33, v21 ; 10422B21 V_MAD_F32 v20, v20, v32, v33, 0, 0, 0, 0 ; D2820014 04864114 V_MUL_F32_e64 v33, v37, 5.000000e-01, 0, 0, 0, 0 ; D2100021 0201E125 V_MAD_F32 v33, v4, 5.000000e-01, v33, 0, 0, 0, 0 ; D2820021 0485E104 V_MUL_F32_e32 v33, v33, v34 ; 10424521 V_MAD_F32 v20, v33, v14, v20, 0, 0, 0, 0 ; D2820014 04521D21 S_MOV_B32 s6, 1380 ; BE8603FF 00000564 S_BUFFER_LOAD_DWORD s6, s[12:15], s6 ; C2030C06 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v33, s6, v20 ; 10422806 S_MOV_B32 s6, 1396 ; BE8603FF 00000574 S_BUFFER_LOAD_DWORD s6, s[12:15], s6 ; C2030C06 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v33, s6, v7, v33, 0, 0, 0, 0 ; D2820021 04860E06 V_MUL_F32_e64 v29, v31, 5.000000e-01, 0, 0, 0, 0 ; D210001D 0201E11F V_MAD_F32 v24, v26, 5.000000e-01, v29, 0, 0, 0, 0 ; D2820018 0475E11A V_MUL_F32_e32 v19, v24, v19 ; 10262718 V_MUL_F32_e32 v19, v19, v21 ; 10262B13 V_MUL_F32_e64 v11, v12, 5.000000e-01, 0, 0, 0, 0 ; D210000B 0201E10C V_MAD_F32 v8, v9, 5.000000e-01, v11, 0, 0, 0, 0 ; D2820008 042DE109 V_ADD_F32_e32 v8, v8, v8 ; 06101108 V_ADD_F32_e32 v8, -1.003906e+00, v8 ; 061010FF BF808000 V_MUL_F32_e32 v6, v8, v6 ; 100C0D08 V_MAD_F32 v6, v6, v32, v19, 0, 0, 0, 0 ; D2820006 044E4106 V_MUL_F32_e64 v8, v35, 5.000000e-01, 0, 0, 0, 0 ; D2100008 0201E123 V_MAD_F32 v8, v2, 5.000000e-01, v8, 0, 0, 0, 0 ; D2820008 0421E102 V_ADD_F32_e32 v8, v8, v8 ; 06101108 V_ADD_F32_e32 v8, -1.003906e+00, v8 ; 061010FF BF808000 V_MUL_F32_e32 v8, v8, v34 ; 10104508 V_MAD_F32 v6, v8, v14, v6, 0, 0, 0, 0 ; D2820006 041A1D08 S_MOV_B32 s6, 1412 ; BE8603FF 00000584 S_BUFFER_LOAD_DWORD s6, s[12:15], s6 ; C2030C06 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v14, s6, v6, v33, 0, 0, 0, 0 ; D282000E 04860C06 S_MOV_B32 s6, 1376 ; BE8603FF 00000560 S_BUFFER_LOAD_DWORD s6, s[12:15], s6 ; C2030C06 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v8, s6, v20 ; 10102806 S_MOV_B32 s6, 1392 ; BE8603FF 00000570 S_BUFFER_LOAD_DWORD s6, s[12:15], s6 ; C2030C06 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v8, s6, v7, v8, 0, 0, 0, 0 ; D2820008 04220E06 S_MOV_B32 s6, 1408 ; BE8603FF 00000580 S_BUFFER_LOAD_DWORD s6, s[12:15], s6 ; C2030C06 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v8, s6, v6, v8, 0, 0, 0, 0 ; D2820008 04220C06 V_MUL_F32_e32 v9, v8, v8 ; 10121108 V_MAD_F32 v9, v14, v14, v9, 0, 0, 0, 0 ; D2820009 04261D0E S_MOV_B32 s6, 1384 ; BE8603FF 00000568 S_BUFFER_LOAD_DWORD s6, s[12:15], s6 ; C2030C06 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v10, s6, v20 ; 10142806 S_MOV_B32 s6, 1400 ; BE8603FF 00000578 S_BUFFER_LOAD_DWORD s6, s[12:15], s6 ; C2030C06 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v7, s6, v7, v10, 0, 0, 0, 0 ; D2820007 042A0E06 S_MOV_B32 s6, 1416 ; BE8603FF 00000588 S_BUFFER_LOAD_DWORD s6, s[12:15], s6 ; C2030C06 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v13, s6, v6, v7, 0, 0, 0, 0 ; D282000D 041E0C06 V_MAD_F32 v6, v13, v13, v9, 0, 0, 0, 0 ; D2820006 04261B0D V_RSQ_LEGACY_F32_e32 v19, v6 ; 7E265B06 V_MUL_F32_e32 v6, v14, v19 ; 100C270E V_MUL_F32_e32 v7, v8, v19 ; 100E2708 V_INTERP_P1_F32 v8, v0, 1, 0, [m0] ; C8200100 V_INTERP_P2_F32 v8, [v8], v1, 1, 0, [m0] ; C8210101 V_INTERP_P1_F32 v9, v0, 0, 0, [m0] ; C8240000 V_INTERP_P2_F32 v9, [v9], v1, 0, 0, [m0] ; C8250001 S_LOAD_DWORDX4 s[16:19], s[0:1], 4 ; C0880104 S_WAITCNT lgkmcnt(0) ; BF8C007F S_BUFFER_LOAD_DWORD s6, s[16:19], 49 ; C2031131 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v10, s6, v9 ; 10141206 S_BUFFER_LOAD_DWORD s6, s[16:19], 53 ; C2031135 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v10, s6, v8, v10, 0, 0, 0, 0 ; D282000A 042A1006 V_INTERP_P1_F32 v12, v0, 2, 0, [m0] ; C8300200 V_INTERP_P2_F32 v12, [v12], v1, 2, 0, [m0] ; C8310201 S_BUFFER_LOAD_DWORD s6, s[16:19], 57 ; C2031139 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v0, s6, v12, v10, 0, 0, 0, 0 ; D2820000 042A1806 S_BUFFER_LOAD_DWORD s6, s[16:19], 61 ; C203113D S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v10, s6, v0 ; 06140006 S_BUFFER_LOAD_DWORD s6, s[16:19], 81 ; C2031151 S_WAITCNT lgkmcnt(0) ; BF8C007F V_SUBREV_F32_e32 v0, s6, v10 ; 0A001406 S_BUFFER_LOAD_DWORD s6, s[16:19], 48 ; C2031130 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v1, s6, v9 ; 10021206 S_BUFFER_LOAD_DWORD s6, s[16:19], 52 ; C2031134 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v1, s6, v8, v1, 0, 0, 0, 0 ; D2820001 04061006 S_BUFFER_LOAD_DWORD s6, s[16:19], 56 ; C2031138 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v1, s6, v12, v1, 0, 0, 0, 0 ; D2820001 04061806 S_BUFFER_LOAD_DWORD s6, s[16:19], 60 ; C203113C S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v11, s6, v1 ; 06160206 S_BUFFER_LOAD_DWORD s6, s[16:19], 80 ; C2031150 S_WAITCNT lgkmcnt(0) ; BF8C007F V_SUBREV_F32_e32 v1, s6, v11 ; 0A021606 V_MUL_F32_e32 v20, v1, v1 ; 10280301 V_MAD_F32 v20, v0, v0, v20, 0, 0, 0, 0 ; D2820014 04520100 S_BUFFER_LOAD_DWORD s6, s[16:19], 50 ; C2031132 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v9, s6, v9 ; 10121206 S_BUFFER_LOAD_DWORD s6, s[16:19], 54 ; C2031136 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v8, s6, v8, v9, 0, 0, 0, 0 ; D2820008 04261006 S_BUFFER_LOAD_DWORD s6, s[16:19], 58 ; C203113A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v8, s6, v12, v8, 0, 0, 0, 0 ; D2820008 04221806 S_BUFFER_LOAD_DWORD s6, s[16:19], 62 ; C203113E S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v12, s6, v8 ; 06181006 S_BUFFER_LOAD_DWORD s6, s[16:19], 82 ; C2031152 S_WAITCNT lgkmcnt(0) ; BF8C007F V_SUBREV_F32_e32 v8, s6, v12 ; 0A101806 V_MAD_F32 v9, v8, v8, v20, 0, 0, 0, 0 ; D2820009 04521108 V_RSQ_LEGACY_F32_e32 v9, v9 ; 7E125B09 V_MUL_F32_e32 v20, v1, v9 ; 10281301 V_MUL_F32_e32 v1, v7, v20 ; 10022907 V_MUL_F32_e32 v21, v0, v9 ; 102A1300 V_MAD_F32 v1, v6, v21, v1, 0, 0, 0, 0 ; D2820001 04062B06 V_MUL_F32_e32 v0, v13, v19 ; 1000270D V_MUL_F32_e32 v9, v8, v9 ; 10121308 V_MAD_F32 v13, v0, v9, v1, 0, 0, 0, 0 ; D282000D 04061300 V_MUL_F32_e32 v1, v13, v6 ; 10020D0D V_MAD_F32 v1, v13, v6, v1, 0, 0, 0, 0 ; D2820001 04060D0D V_SUB_F32_e32 v1, v21, v1 ; 08020315 V_MUL_F32_e32 v8, v13, v7 ; 10100F0D V_MAD_F32 v8, v13, v7, v8, 0, 0, 0, 0 ; D2820008 04220F0D V_SUB_F32_e32 v8, v20, v8 ; 08101114 S_LOAD_DWORDX4 s[16:19], s[0:1], 8 ; C0880108 S_WAITCNT lgkmcnt(0) ; BF8C007F S_BUFFER_LOAD_DWORD s9, s[16:19], 48 ; C2049130 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v20, s9, v8 ; 10281009 S_BUFFER_LOAD_DWORD s10, s[16:19], 49 ; C2051131 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v20, v1, s10, v20, 0, 0, 0, 0 ; D2820014 04501501 V_MUL_F32_e32 v21, v13, v0 ; 102A010D V_MAD_F32 v13, v13, v0, v21, 0, 0, 0, 0 ; D282000D 0456010D V_SUB_F32_e32 v9, v9, v13 ; 08121B09 S_BUFFER_LOAD_DWORD s11, s[16:19], 50 ; C2059132 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v13, v9, s11, v20, 0, 0, 0, 0 ; D282000D 04501709 V_MOV_B32_e32 v20, 1.000000e-03 ; 7E2802FF 3A83126F V_CMP_LE_F32_e64 s[0:1], v13, v20, 0, 0, 0, 0 ; D0060000 0202290D V_CMP_U_F32_e64 s[6:7], v13, v13, 0, 0, 0, 0 ; D0100006 02021B0D S_OR_B64 s[0:1], s[0:1], s[6:7] ; 88800600 V_CNDMASK_B32_e64 v13, v13, v20, s[0:1], 0, 0, 0, 0 ; D200000D 0002290D V_LOG_F32_e32 v13, v13 ; 7E1A4F0D S_MOV_B32 s0, 1292 ; BE8003FF 0000050C S_BUFFER_LOAD_DWORD s0, s[12:15], s0 ; C2000C00 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_LEGACY_F32_e32 v13, s0, v13 ; 0E1A1A00 V_EXP_F32_e32 v13, v13 ; 7E1A4B0D V_MOV_B32_e32 v20, 1.050000e+00 ; 7E2802FF 3F866666 V_MAD_F32 v14, v14, v19, v20, 0, 0, 0, 0 ; D282000E 0452270E V_ADD_F32_e64 v14, 0, v14, 0, 1, 0, 0 ; D206080E 02021C80 S_BUFFER_LOAD_DWORD s22, s[16:19], 61 ; C20B113D S_WAITCNT lgkmcnt(0) ; BF8C007F V_SUBREV_F32_e32 v19, s22, v10 ; 0A261416 S_BUFFER_LOAD_DWORD s23, s[16:19], 60 ; C20B913C S_WAITCNT lgkmcnt(0) ; BF8C007F V_SUBREV_F32_e32 v20, s23, v11 ; 0A281617 V_MUL_F32_e32 v20, v20, v20 ; 10282914 V_MAD_F32 v19, v19, v19, v20, 0, 0, 0, 0 ; D2820013 04522713 S_BUFFER_LOAD_DWORD s48, s[16:19], 62 ; C218113E S_WAITCNT lgkmcnt(0) ; BF8C007F V_SUBREV_F32_e32 v20, s48, v12 ; 0A281830 V_MAD_F32 v19, v20, v20, v19, 0, 0, 0, 0 ; D2820013 044E2914 V_RSQ_LEGACY_F32_e32 v20, v19 ; 7E285B13 V_MUL_F32_e32 v20, v20, v19 ; 10282714 V_XOR_B32_e32 v19, -2147483648, v19 ; 3A2626FF 80000000 V_CMP_GT_F32_e64 s[6:7], 0, v19, 0, 0, 0, 0 ; D0080006 02022680 V_CNDMASK_B32_e64 v42, 0.000000e+00, v20, s[6:7], 0, 0, 0, 0 ; D200002A 001A2880 S_BUFFER_LOAD_DWORD s49, s[16:19], 64 ; C2189140 V_MOV_B32_e32 v19, 8.000000e-01 ; 7E2602FF 3F4CCCCD S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v19, s49, v19 ; 10262631 V_CMP_LT_F32_e64 s[6:7], v42, v19, 0, 0, 0, 0 ; D0020006 0202272A V_CNDMASK_B32_e64 v19, 0, -1, s[6:7], 0, 0, 0, 0 ; D2000013 00198280 V_CMP_EQ_I32_e64 s[20:21], v19, 0, 0, 0, 0, 0 ; D1040014 02010113 S_LOAD_DWORDX4 s[24:27], s[2:3], 8 ; C08C0308 S_LOAD_DWORDX8 s[28:35], s[4:5], 16 ; C0CE0510 S_WAITCNT lgkmcnt(0) ; BF8C007F IMAGE_SAMPLE v[35:38], 15, 0, 0, 0, 0, 0, 0, 0, v[27:28], s[28:35], s[24:27] ; F0800F00 00C7231B IMAGE_SAMPLE v[31:34], 15, 0, 0, 0, 0, 0, 0, 0, v[22:23], s[28:35], s[24:27] ; F0800F00 00C71F16 S_LOAD_DWORDX4 s[24:27], s[2:3], 12 ; C08C030C S_LOAD_DWORDX8 s[28:35], s[4:5], 24 ; C0CE0518 S_WAITCNT vmcnt(0) lgkmcnt(0) ; BF8C0070 IMAGE_SAMPLE v[27:30], 15, 0, 0, 0, 0, 0, 0, 0, v[17:18], s[28:35], s[24:27] ; F0800F00 00C71B11 IMAGE_SAMPLE v[23:26], 15, 0, 0, 0, 0, 0, 0, 0, v[15:16], s[28:35], s[24:27] ; F0800F00 00C7170F S_LOAD_DWORDX4 s[24:27], s[2:3], 16 ; C08C0310 S_LOAD_DWORDX8 s[28:35], s[4:5], 32 ; C0CE0520 S_WAITCNT vmcnt(0) lgkmcnt(0) ; BF8C0070 IMAGE_SAMPLE v[19:22], 15, 0, 0, 0, 0, 0, 0, 0, v[46:47], s[28:35], s[24:27] ; F0800F00 00C7132E IMAGE_SAMPLE v[15:18], 15, 0, 0, 0, 0, 0, 0, 0, v[44:45], s[28:35], s[24:27] ; F0800F00 00C70F2C V_ADD_F32_e32 v40, 1.000000e-03, v40 ; 065050FF 3A83126F V_LOG_F32_e32 v40, v40 ; 7E504F28 S_MOV_B32 s1, 1344 ; BE8103FF 00000540 S_BUFFER_LOAD_DWORD s1, s[12:15], s1 ; C2008C01 S_WAITCNT vmcnt(0) lgkmcnt(0) ; BF8C0070 V_MUL_LEGACY_F32_e32 v40, s1, v40 ; 0E505001 V_EXP_F32_e32 v41, v40 ; 7E524B28 V_ADD_F32_e32 v39, 1.000000e-03, v39 ; 064E4EFF 3A83126F V_LOG_F32_e32 v39, v39 ; 7E4E4F27 V_MUL_LEGACY_F32_e32 v39, s1, v39 ; 0E4E4E01 V_EXP_F32_e32 v40, v39 ; 7E504B27 V_ADD_F32_e32 v39, 1.000000e-03, v43 ; 064E56FF 3A83126F V_LOG_F32_e32 v39, v39 ; 7E4E4F27 V_MUL_LEGACY_F32_e32 v39, s1, v39 ; 0E4E4E01 V_EXP_F32_e32 v39, v39 ; 7E4E4B27 S_MOV_B32 s1, 1360 ; BE8103FF 00000550 S_BUFFER_LOAD_DWORD s1, s[12:15], s1 ; C2008C01 S_MOV_B32 s6, 1288 ; BE8603FF 00000508 S_BUFFER_LOAD_DWORD s6, s[12:15], s6 ; C2030C06 S_MOV_B32 s7, 1284 ; BE8703FF 00000504 S_BUFFER_LOAD_DWORD s7, s[12:15], s7 ; C2038C07 S_MOV_B32 s8, 1280 ; BE8803FF 00000500 S_BUFFER_LOAD_DWORD s8, s[12:15], s8 ; C2040C08 S_LOAD_DWORDX4 s[24:27], s[2:3], 0 ; C08C0300 S_LOAD_DWORDX8 s[28:35], s[4:5], 0 ; C0CE0500 S_WAITCNT lgkmcnt(0) ; BF8C007F S_AND_SAVEEXEC_B64 s[20:21], s[20:21] ; BE942414 S_XOR_B64 s[20:21], exec, s[20:21] ; 8994147E S_CBRANCH_EXECZ BB0_1 ; BF880000 V_CMP_LT_F32_e64 s[36:37], s49, v42, 0, 0, 0, 0 ; D0020024 02025431 V_CNDMASK_B32_e64 v43, 0, -1, s[36:37], 0, 0, 0, 0 ; D200002B 00918280 V_CMP_EQ_I32_e64 s[50:51], v43, 0, 0, 0, 0, 0 ; D1040032 0201012B S_LOAD_DWORDX4 s[36:39], s[2:3], 4 ; C0920304 S_LOAD_DWORDX8 s[40:47], s[4:5], 8 ; C0D40508 S_WAITCNT lgkmcnt(0) ; BF8C007F S_AND_SAVEEXEC_B64 s[2:3], s[50:51] ; BE822432 S_XOR_B64 s[2:3], exec, s[2:3] ; 8982027E S_CBRANCH_EXECZ BB0_6 ; BF880000 V_MOV_B32_e32 v43, -8.000000e-01 ; 7E5602FF BF4CCCCD V_MAD_F32 v42, s49, v43, v42, 0, 0, 0, 0 ; D282002A 04AA5631 V_MOV_B32_e32 v44, s49 ; 7E580231 V_MAD_F32 v43, s49, v43, v44, 0, 0, 0, 0 ; D282002B 04B25631 V_RCP_F32_e32 v43, v43 ; 7E56552B V_MUL_F32_e32 v42, v42, v43 ; 1054572A V_ADD_F32_e64 v42, 0, v42, 0, 1, 0, 0 ; D206082A 02025480 V_ADD_F32_e32 v43, v42, v42 ; 0656552A V_SUB_F32_e32 v43, 3.000000e+00, v43 ; 085656FF 40400000 V_MUL_F32_e32 v43, v42, v43 ; 1056572A V_MUL_F32_e32 v42, v42, v43 ; 1054572A V_SUB_F32_e32 v43, 1.000000e+00, v42 ; 085654F2 S_BUFFER_LOAD_DWORD s4, s[16:19], 18 ; C2021112 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v44, s4, v11, 0, 0, 0, 0 ; D210002C 02021604 S_BUFFER_LOAD_DWORD s4, s[16:19], 22 ; C2021116 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v44, s4, v10, v44, 0, 0, 0, 0 ; D282002C 04B21404 S_BUFFER_LOAD_DWORD s4, s[16:19], 26 ; C202111A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v44, s4, v12, v44, 0, 0, 0, 0 ; D282002C 04B21804 S_BUFFER_LOAD_DWORD s4, s[16:19], 30 ; C202111E S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v44, s4, v44 ; 06585804 V_CMP_U_F32_e64 s[4:5], v44, v44, 0, 0, 0, 0 ; D0100004 0202592C V_CMP_GE_F32_e64 s[50:51], v44, -1.000000e+00, 0, 0, 0, 0 ; D00C0032 0201E72C S_OR_B64 s[4:5], s[50:51], s[4:5] ; 88840432 V_CNDMASK_B32_e64 v44, -1.000000e+00, v44, s[4:5], 0, 0, 0, 0 ; D200002C 001258F3 V_CMP_U_F32_e64 s[4:5], v44, v44, 0, 0, 0, 0 ; D0100004 0202592C V_CMP_GE_F32_e64 s[50:51], v44, 1.000000e+00, 0, 0, 0, 0 ; D00C0032 0201E52C S_OR_B64 s[4:5], s[50:51], s[4:5] ; 88840432 V_CNDMASK_B32_e64 v44, v44, 1.000000e+00, s[4:5], 0, 0, 0, 0 ; D200002C 0011E52C V_ADD_F32_e32 v44, 1.000000e+00, v44 ; 065858F2 S_BUFFER_LOAD_DWORD s4, s[16:19], 63 ; C202113F V_MOV_B32_e32 v45, -2147483648 ; 7E5A02FF 80000000 S_WAITCNT lgkmcnt(0) ; BF8C007F V_XOR_B32_e32 v45, s4, v45 ; 3A5A5A04 V_MUL_F32_e32 v44, v45, v44 ; 1058592D V_MUL_F32_e32 v44, 7.213475e-01, v44 ; 105858FF 3F38AA3B V_EXP_F32_e32 v44, v44 ; 7E584B2C S_BUFFER_LOAD_DWORD s4, s[16:19], 17 ; C2021111 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v46, s4, v11, 0, 0, 0, 0 ; D210002E 02021604 S_BUFFER_LOAD_DWORD s4, s[16:19], 21 ; C2021115 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v46, s4, v10, v46, 0, 0, 0, 0 ; D282002E 04BA1404 S_BUFFER_LOAD_DWORD s4, s[16:19], 25 ; C2021119 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v46, s4, v12, v46, 0, 0, 0, 0 ; D282002E 04BA1804 S_BUFFER_LOAD_DWORD s4, s[16:19], 29 ; C202111D S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v46, s4, v46 ; 065C5C04 V_MAD_F32 v46, v46, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0 ; D282002E 03C1E12E S_BUFFER_LOAD_DWORD s4, s[16:19], 66 ; C2021142 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v47, s4, v46 ; 105E5C04 S_BUFFER_LOAD_DWORD s5, s[16:19], 16 ; C2029110 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v48, s5, v11, 0, 0, 0, 0 ; D2100030 02021605 S_BUFFER_LOAD_DWORD s5, s[16:19], 20 ; C2029114 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v48, s5, v10, v48, 0, 0, 0, 0 ; D2820030 04C21405 S_BUFFER_LOAD_DWORD s5, s[16:19], 24 ; C2029118 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v48, s5, v12, v48, 0, 0, 0, 0 ; D2820030 04C21805 S_BUFFER_LOAD_DWORD s5, s[16:19], 28 ; C202911C S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v48, s5, v48 ; 06606005 V_MAD_F32 v48, v48, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0 ; D2820030 03C1E130 V_MUL_F32_e32 v46, s4, v48 ; 105C6004 IMAGE_SAMPLE v46, 1, -1, 0, 0, 0, 0, 0, 0, v[46:47], s[28:35], s[24:27] ; F0801100 00C72E2E S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v44, v44, v46 ; 10585D2C V_ADD_F32_e64 v44, 0, v44, 0, 1, 0, 0 ; D206082C 02025880 V_MUL_F32_e32 v43, v43, v44 ; 1056592B S_BUFFER_LOAD_DWORD s5, s[16:19], 34 ; C2029122 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v44, s5, v11, 0, 0, 0, 0 ; D210002C 02021605 S_BUFFER_LOAD_DWORD s5, s[16:19], 38 ; C2029126 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v44, s5, v10, v44, 0, 0, 0, 0 ; D282002C 04B21405 S_BUFFER_LOAD_DWORD s5, s[16:19], 42 ; C202912A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v44, s5, v12, v44, 0, 0, 0, 0 ; D282002C 04B21805 S_BUFFER_LOAD_DWORD s5, s[16:19], 46 ; C202912E S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v44, s5, v44 ; 06585805 V_CMP_U_F32_e64 s[50:51], v44, v44, 0, 0, 0, 0 ; D0100032 0202592C V_CMP_GE_F32_e64 s[52:53], v44, -1.000000e+00, 0, 0, 0, 0 ; D00C0034 0201E72C S_OR_B64 s[50:51], s[52:53], s[50:51] ; 88B23234 V_CNDMASK_B32_e64 v44, -1.000000e+00, v44, s[50:51], 0, 0, 0, 0 ; D200002C 00CA58F3 V_CMP_U_F32_e64 s[50:51], v44, v44, 0, 0, 0, 0 ; D0100032 0202592C V_CMP_GE_F32_e64 s[52:53], v44, 1.000000e+00, 0, 0, 0, 0 ; D00C0034 0201E52C S_OR_B64 s[50:51], s[52:53], s[50:51] ; 88B23234 V_CNDMASK_B32_e64 v44, v44, 1.000000e+00, s[50:51], 0, 0, 0, 0 ; D200002C 00C9E52C V_ADD_F32_e32 v44, 1.000000e+00, v44 ; 065858F2 V_MUL_F32_e32 v44, v45, v44 ; 1058592D V_MUL_F32_e32 v44, 7.213475e-01, v44 ; 105858FF 3F38AA3B V_EXP_F32_e32 v44, v44 ; 7E584B2C S_BUFFER_LOAD_DWORD s5, s[16:19], 33 ; C2029121 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v45, s5, v11, 0, 0, 0, 0 ; D210002D 02021605 S_BUFFER_LOAD_DWORD s5, s[16:19], 37 ; C2029125 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v45, s5, v10, v45, 0, 0, 0, 0 ; D282002D 04B61405 S_BUFFER_LOAD_DWORD s5, s[16:19], 41 ; C2029129 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v45, s5, v12, v45, 0, 0, 0, 0 ; D282002D 04B61805 S_BUFFER_LOAD_DWORD s5, s[16:19], 45 ; C202912D S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v45, s5, v45 ; 065A5A05 V_MAD_F32 v45, v45, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0 ; D282002D 03C1E12D V_MUL_F32_e32 v46, s4, v45 ; 105C5A04 S_BUFFER_LOAD_DWORD s5, s[16:19], 32 ; C2029120 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v47, s5, v11, 0, 0, 0, 0 ; D210002F 02021605 S_BUFFER_LOAD_DWORD s5, s[16:19], 36 ; C2029124 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v47, s5, v10, v47, 0, 0, 0, 0 ; D282002F 04BE1405 S_BUFFER_LOAD_DWORD s5, s[16:19], 40 ; C2029128 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v47, s5, v12, v47, 0, 0, 0, 0 ; D282002F 04BE1805 S_BUFFER_LOAD_DWORD s5, s[16:19], 44 ; C202912C S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v47, s5, v47 ; 065E5E05 V_MAD_F32 v47, v47, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0 ; D282002F 03C1E12F V_MUL_F32_e32 v45, s4, v47 ; 105A5E04 IMAGE_SAMPLE v45, 1, -1, 0, 0, 0, 0, 0, 0, v[45:46], s[40:47], s[36:39] ; F0801100 012A2D2D S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v44, v44, v45 ; 10585B2C V_ADD_F32_e64 v44, 0, v44, 0, 1, 0, 0 ; D206082C 02025880 V_MAD_F32 v50, v42, v44, v43, 0, 0, 0, 0 ; D2820032 04AE592A S_OR_SAVEEXEC_B64 s[2:3], s[2:3] ; BE822502 S_XOR_B64 exec, exec, s[2:3] ; 89FE027E S_CBRANCH_EXECZ BB0_4 ; BF880000 V_MOV_B32_e32 v42, s22 ; 7E540216 V_SUB_F32_e64 v42, v10, v42, 0, 0, 0, 0 ; D208002A 0202550A V_MOV_B32_e32 v43, s23 ; 7E560217 V_SUB_F32_e64 v43, v11, v43, 0, 0, 0, 0 ; D208002B 0202570B V_MUL_F32_e32 v43, v43, v43 ; 1056572B V_MAD_F32 v42, v42, v42, v43, 0, 0, 0, 0 ; D282002A 04AE552A V_MOV_B32_e32 v43, s48 ; 7E560230 V_SUB_F32_e64 v43, v12, v43, 0, 0, 0, 0 ; D208002B 0202570C V_MAD_F32 v42, v43, v43, v42, 0, 0, 0, 0 ; D282002A 04AA572B V_RSQ_LEGACY_F32_e32 v43, v42 ; 7E565B2A V_MUL_F32_e32 v43, v43, v42 ; 1056552B V_XOR_B32_e32 v42, -2147483648, v42 ; 3A5454FF 80000000 V_CMP_GT_F32_e64 s[4:5], 0, v42, 0, 0, 0, 0 ; D0080004 02025480 V_CNDMASK_B32_e64 v42, 0.000000e+00, v43, s[4:5], 0, 0, 0, 0 ; D200002A 00125680 S_BUFFER_LOAD_DWORD s4, s[16:19], 65 ; C2021141 S_WAITCNT lgkmcnt(0) ; BF8C007F V_RCP_F32_e32 v43, s4 ; 7E565404 V_MOV_B32_e32 v44, -8.000000e-01 ; 7E5802FF BF4CCCCD V_MAD_F32 v42, v42, v43, v44, 0, 0, 0, 0 ; D282002A 04B2572A V_MUL_F32_e32 v42, 5.000000e+00, v42 ; 105454FF 40A00001 V_ADD_F32_e64 v42, 0, v42, 0, 1, 0, 0 ; D206082A 02025480 V_ADD_F32_e32 v43, v42, v42 ; 0656552A V_SUB_F32_e32 v43, 3.000000e+00, v43 ; 085656FF 40400000 V_MUL_F32_e32 v43, v42, v43 ; 1056572A V_MUL_F32_e32 v44, v42, v43 ; 1058572A V_SUB_F32_e32 v44, 1.000000e+00, v44 ; 085858F2 S_BUFFER_LOAD_DWORD s4, s[16:19], 34 ; C2021122 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v45, s4, v11, 0, 0, 0, 0 ; D210002D 02021604 S_BUFFER_LOAD_DWORD s4, s[16:19], 38 ; C2021126 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v45, s4, v10, v45, 0, 0, 0, 0 ; D282002D 04B61404 S_BUFFER_LOAD_DWORD s4, s[16:19], 42 ; C202112A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v45, s4, v12, v45, 0, 0, 0, 0 ; D282002D 04B61804 S_BUFFER_LOAD_DWORD s4, s[16:19], 46 ; C202112E S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v45, s4, v45 ; 065A5A04 V_CMP_U_F32_e64 s[4:5], v45, v45, 0, 0, 0, 0 ; D0100004 02025B2D V_CMP_GE_F32_e64 s[22:23], v45, -1.000000e+00, 0, 0, 0, 0 ; D00C0016 0201E72D S_OR_B64 s[4:5], s[22:23], s[4:5] ; 88840416 V_CNDMASK_B32_e64 v45, -1.000000e+00, v45, s[4:5], 0, 0, 0, 0 ; D200002D 00125AF3 V_CMP_U_F32_e64 s[4:5], v45, v45, 0, 0, 0, 0 ; D0100004 02025B2D V_CMP_GE_F32_e64 s[22:23], v45, 1.000000e+00, 0, 0, 0, 0 ; D00C0016 0201E52D S_OR_B64 s[4:5], s[22:23], s[4:5] ; 88840416 V_CNDMASK_B32_e64 v45, v45, 1.000000e+00, s[4:5], 0, 0, 0, 0 ; D200002D 0011E52D V_ADD_F32_e32 v45, 1.000000e+00, v45 ; 065A5AF2 S_BUFFER_LOAD_DWORD s4, s[16:19], 63 ; C202113F S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v45, s4, v45 ; 105A5A04 V_MUL_F32_e32 v45, -7.213475e-01, v45 ; 105A5AFF BF38AA3B V_EXP_F32_e32 v45, v45 ; 7E5A4B2D S_BUFFER_LOAD_DWORD s4, s[16:19], 33 ; C2021121 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v46, s4, v11, 0, 0, 0, 0 ; D210002E 02021604 S_BUFFER_LOAD_DWORD s4, s[16:19], 37 ; C2021125 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v46, s4, v10, v46, 0, 0, 0, 0 ; D282002E 04BA1404 S_BUFFER_LOAD_DWORD s4, s[16:19], 41 ; C2021129 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v46, s4, v12, v46, 0, 0, 0, 0 ; D282002E 04BA1804 S_BUFFER_LOAD_DWORD s4, s[16:19], 45 ; C202112D S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v46, s4, v46 ; 065C5C04 V_MAD_F32 v46, v46, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0 ; D282002E 03C1E12E S_BUFFER_LOAD_DWORD s4, s[16:19], 66 ; C2021142 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v47, s4, v46 ; 105E5C04 S_BUFFER_LOAD_DWORD s5, s[16:19], 32 ; C2029120 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v48, s5, v11, 0, 0, 0, 0 ; D2100030 02021605 S_BUFFER_LOAD_DWORD s5, s[16:19], 36 ; C2029124 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v48, s5, v10, v48, 0, 0, 0, 0 ; D2820030 04C21405 S_BUFFER_LOAD_DWORD s5, s[16:19], 40 ; C2029128 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v48, s5, v12, v48, 0, 0, 0, 0 ; D2820030 04C21805 S_BUFFER_LOAD_DWORD s5, s[16:19], 44 ; C202912C S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v48, s5, v48 ; 06606005 V_MAD_F32 v48, v48, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0 ; D2820030 03C1E130 V_MUL_F32_e32 v46, s4, v48 ; 105C6004 IMAGE_SAMPLE v46, 1, -1, 0, 0, 0, 0, 0, 0, v[46:47], s[40:47], s[36:39] ; F0801100 012A2E2E S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v45, v45, v46 ; 105A5D2D V_ADD_F32_e64 v45, 0, v45, 0, 1, 0, 0 ; D206082D 02025A80 V_MUL_F32_e32 v44, v44, v45 ; 10585B2C V_MAD_F32 v50, v42, v43, v44, 0, 0, 0, 0 ; D2820032 04B2572A S_OR_B64 exec, exec, s[2:3] ; 88FE027E S_OR_SAVEEXEC_B64 s[20:21], s[20:21] ; BE942514 S_BUFFER_LOAD_DWORD s3, s[16:19], 54 ; C2019136 S_BUFFER_LOAD_DWORD s4, s[16:19], 53 ; C2021135 S_BUFFER_LOAD_DWORD s5, s[16:19], 52 ; C2029134 S_BUFFER_LOAD_DWORD s22, s[16:19], 58 ; C20B113A S_BUFFER_LOAD_DWORD s23, s[16:19], 57 ; C20B9139 S_BUFFER_LOAD_DWORD s36, s[16:19], 56 ; C2121138 S_BUFFER_LOAD_DWORD s2, s[12:15], 12 ; C2010D0C S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v47, s3 ; 7E5E0203 V_MOV_B32_e32 v44, s4 ; 7E580204 V_MOV_B32_e32 v42, s5 ; 7E540205 V_MOV_B32_e32 v48, s11 ; 7E60020B V_MOV_B32_e32 v49, s10 ; 7E62020A V_MOV_B32_e32 v51, s9 ; 7E660209 V_MOV_B32_e32 v46, s22 ; 7E5C0216 V_MOV_B32_e32 v45, s23 ; 7E5A0217 V_MOV_B32_e32 v43, s36 ; 7E560224 S_XOR_B64 exec, exec, s[20:21] ; 89FE147E S_CBRANCH_EXECZ BB0_5 ; BF880000 S_BUFFER_LOAD_DWORD s3, s[16:19], 18 ; C2019112 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v50, s3, v11, 0, 0, 0, 0 ; D2100032 02021603 S_BUFFER_LOAD_DWORD s3, s[16:19], 22 ; C2019116 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v50, s3, v10, v50, 0, 0, 0, 0 ; D2820032 04CA1403 S_BUFFER_LOAD_DWORD s3, s[16:19], 26 ; C201911A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v50, s3, v12, v50, 0, 0, 0, 0 ; D2820032 04CA1803 S_BUFFER_LOAD_DWORD s3, s[16:19], 30 ; C201911E S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v50, s3, v50 ; 06646403 V_CMP_U_F32_e64 s[4:5], v50, v50, 0, 0, 0, 0 ; D0100004 02026532 V_CMP_GE_F32_e64 s[10:11], v50, -1.000000e+00, 0, 0, 0, 0 ; D00C000A 0201E732 S_OR_B64 s[4:5], s[10:11], s[4:5] ; 8884040A V_CNDMASK_B32_e64 v50, -1.000000e+00, v50, s[4:5], 0, 0, 0, 0 ; D2000032 001264F3 V_CMP_U_F32_e64 s[4:5], v50, v50, 0, 0, 0, 0 ; D0100004 02026532 V_CMP_GE_F32_e64 s[10:11], v50, 1.000000e+00, 0, 0, 0, 0 ; D00C000A 0201E532 S_OR_B64 s[4:5], s[10:11], s[4:5] ; 8884040A V_CNDMASK_B32_e64 v50, v50, 1.000000e+00, s[4:5], 0, 0, 0, 0 ; D2000032 0011E532 V_ADD_F32_e32 v50, 1.000000e+00, v50 ; 066464F2 S_BUFFER_LOAD_DWORD s3, s[16:19], 63 ; C201913F S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v50, s3, v50 ; 10646403 V_MUL_F32_e32 v50, -7.213475e-01, v50 ; 106464FF BF38AA3B V_EXP_F32_e32 v50, v50 ; 7E644B32 S_BUFFER_LOAD_DWORD s3, s[16:19], 17 ; C2019111 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v52, s3, v11, 0, 0, 0, 0 ; D2100034 02021603 S_BUFFER_LOAD_DWORD s3, s[16:19], 21 ; C2019115 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v52, s3, v10, v52, 0, 0, 0, 0 ; D2820034 04D21403 S_BUFFER_LOAD_DWORD s3, s[16:19], 25 ; C2019119 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v52, s3, v12, v52, 0, 0, 0, 0 ; D2820034 04D21803 S_BUFFER_LOAD_DWORD s3, s[16:19], 29 ; C201911D S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v52, s3, v52 ; 06686803 V_MAD_F32 v52, v52, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0 ; D2820034 03C1E134 S_BUFFER_LOAD_DWORD s3, s[16:19], 66 ; C2019142 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v53, s3, v52 ; 106A6803 S_BUFFER_LOAD_DWORD s4, s[16:19], 16 ; C2021110 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v54, s4, v11, 0, 0, 0, 0 ; D2100036 02021604 S_BUFFER_LOAD_DWORD s4, s[16:19], 20 ; C2021114 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v54, s4, v10, v54, 0, 0, 0, 0 ; D2820036 04DA1404 S_BUFFER_LOAD_DWORD s4, s[16:19], 24 ; C2021118 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v54, s4, v12, v54, 0, 0, 0, 0 ; D2820036 04DA1804 S_BUFFER_LOAD_DWORD s4, s[16:19], 28 ; C202111C S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v54, s4, v54 ; 066C6C04 V_MAD_F32 v54, v54, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0 ; D2820036 03C1E136 V_MUL_F32_e32 v52, s3, v54 ; 10686C03 IMAGE_SAMPLE v52, 1, -1, 0, 0, 0, 0, 0, 0, v[52:53], s[28:35], s[24:27] ; F0801100 00C73434 S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v50, v50, v52 ; 10646932 V_ADD_F32_e64 v50, 0, v50, 0, 1, 0, 0 ; D2060832 02026480 S_OR_B64 exec, exec, s[20:21] ; 88FE147E V_MUL_F32_e64 v52, v37, 5.000000e-01, 0, 0, 0, 0 ; D2100034 0201E125 V_MAD_F32 v52, v33, 5.000000e-01, v52, 0, 0, 0, 0 ; D2820034 04D1E121 V_ADD_F32_e64 v53, v39, v40, 0, 0, 0, 0 ; D2060035 02025127 V_ADD_F32_e32 v53, v41, v53 ; 066A6B29 V_RCP_F32_e32 v53, v53 ; 7E6A5535 V_MUL_F32_e32 v54, v41, v53 ; 106C6B29 V_MUL_F32_e32 v41, v52, v54 ; 10526D34 V_MUL_F32_e64 v52, v29, 5.000000e-01, 0, 0, 0, 0 ; D2100034 0201E11D V_MAD_F32 v52, v25, 5.000000e-01, v52, 0, 0, 0, 0 ; D2820034 04D1E119 V_MUL_F32_e32 v55, v40, v53 ; 106E6B28 V_MAD_F32 v40, v52, v55, v41, 0, 0, 0, 0 ; D2820028 04A66F34 V_MUL_F32_e64 v41, v21, 5.000000e-01, 0, 0, 0, 0 ; D2100029 0201E115 V_MAD_F32 v41, v17, 5.000000e-01, v41, 0, 0, 0, 0 ; D2820029 04A5E111 V_MUL_F32_e32 v52, v39, v53 ; 10686B27 V_MAD_F32 v39, v41, v52, v40, 0, 0, 0, 0 ; D2820027 04A26929 V_MUL_F32_e64 v40, v7, v51, 0, 0, 0, 0 ; D2100028 02026707 V_MAD_F32 v40, v6, v49, v40, 0, 0, 0, 0 ; D2820028 04A26306 V_MAD_F32 v40, v0, v48, v40, 0, 0, 0, 0 ; D2820028 04A26100 V_CMP_U_F32_e64 s[4:5], v40, v40, 0, 0, 0, 0 ; D0100004 02025128 V_CMP_LE_F32_e64 s[10:11], v40, 0.000000e+00, 0, 0, 0, 0 ; D006000A 02010128 S_OR_B64 s[4:5], s[10:11], s[4:5] ; 8884040A V_CNDMASK_B32_e64 v48, v40, 0.000000e+00, s[4:5], 0, 0, 0, 0 ; D2000030 00110128 V_MUL_F32_e32 v40, v47, v48 ; 1050612F V_MUL_F32_e32 v40, v40, v39 ; 10504F28 V_MUL_F32_e64 v41, v13, v47, 0, 0, 0, 0 ; D2100029 02025F0D V_MAD_F32 v40, v41, s6, v40, 0, 0, 0, 0 ; D2820028 04A00D29 V_MOV_B32_e32 v41, -8.000000e-01 ; 7E5202FF BF4CCCCD V_ADD_F32_e32 v41, v50, v41 ; 06525332 V_MUL_F32_e32 v41, 5.000000e+00, v41 ; 105252FF 40A00001 V_ADD_F32_e64 v41, 0, v41, 0, 1, 0, 0 ; D2060829 02025280 V_ADD_F32_e32 v47, v41, v41 ; 065E5329 V_SUB_F32_e32 v47, 3.000000e+00, v47 ; 085E5EFF 40400000 V_MUL_F32_e32 v47, v41, v47 ; 105E5F29 V_MUL_F32_e32 v47, v41, v47 ; 105E5F29 V_MUL_F32_e32 v40, v40, v47 ; 10505F28 V_MUL_F32_e64 v41, v14, v46, 0, 0, 0, 0 ; D2100029 02025D0E V_MAD_F32 v41, v39, v41, v40, 0, 0, 0, 0 ; D2820029 04A25327 V_MUL_F32_e64 v40, v36, 5.000000e-01, 0, 0, 0, 0 ; D2100028 0201E124 V_MAD_F32 v40, v32, 5.000000e-01, v40, 0, 0, 0, 0 ; D2820028 04A1E120 V_MUL_F32_e32 v40, v40, v54 ; 10506D28 V_MUL_F32_e64 v46, v28, 5.000000e-01, 0, 0, 0, 0 ; D210002E 0201E11C V_MAD_F32 v46, v24, 5.000000e-01, v46, 0, 0, 0, 0 ; D282002E 04B9E118 V_MAD_F32 v40, v46, v55, v40, 0, 0, 0, 0 ; D2820028 04A26F2E V_MUL_F32_e64 v46, v20, 5.000000e-01, 0, 0, 0, 0 ; D210002E 0201E114 V_MAD_F32 v46, v16, 5.000000e-01, v46, 0, 0, 0, 0 ; D282002E 04B9E110 V_MAD_F32 v40, v46, v52, v40, 0, 0, 0, 0 ; D2820028 04A2692E V_MUL_F32_e32 v46, v44, v48 ; 105C612C V_MUL_F32_e32 v46, v46, v40 ; 105C512E V_MUL_F32_e64 v44, v13, v44, 0, 0, 0, 0 ; D210002C 0202590D V_MAD_F32 v44, v44, s7, v46, 0, 0, 0, 0 ; D282002C 04B80F2C V_MUL_F32_e32 v44, v44, v47 ; 10585F2C V_MUL_F32_e64 v45, v14, v45, 0, 0, 0, 0 ; D210002D 02025B0E V_MAD_F32 v44, v40, v45, v44, 0, 0, 0, 0 ; D282002C 04B25B28 V_MUL_F32_e64 v35, v35, 5.000000e-01, 0, 0, 0, 0 ; D2100023 0201E123 V_MAD_F32 v31, v31, 5.000000e-01, v35, 0, 0, 0, 0 ; D282001F 048DE11F V_MUL_F32_e32 v31, v31, v54 ; 103E6D1F V_MUL_F32_e64 v27, v27, 5.000000e-01, 0, 0, 0, 0 ; D210001B 0201E11B V_MAD_F32 v23, v23, 5.000000e-01, v27, 0, 0, 0, 0 ; D2820017 046DE117 V_MAD_F32 v23, v23, v55, v31, 0, 0, 0, 0 ; D2820017 047E6F17 V_MUL_F32_e64 v19, v19, 5.000000e-01, 0, 0, 0, 0 ; D2100013 0201E113 V_MAD_F32 v15, v15, 5.000000e-01, v19, 0, 0, 0, 0 ; D282000F 044DE10F V_MAD_F32 v15, v15, v52, v23, 0, 0, 0, 0 ; D282000F 045E690F V_MUL_F32_e32 v16, v42, v48 ; 1020612A V_MUL_F32_e32 v16, v16, v15 ; 10201F10 V_MUL_F32_e64 v13, v13, v42, 0, 0, 0, 0 ; D210000D 0202550D V_MAD_F32 v13, v13, s8, v16, 0, 0, 0, 0 ; D282000D 0440110D V_MUL_F32_e32 v13, v13, v47 ; 101A5F0D V_MUL_F32_e64 v14, v14, v43, 0, 0, 0, 0 ; D210000E 0202570E V_MAD_F32 v19, v15, v14, v13, 0, 0, 0, 0 ; D2820013 04361D0F V_MOV_B32_e32 v13, -2147483648 ; 7E1A02FF 80000000 V_XOR_B32_e32 v12, v12, v13 ; 3A181B0C V_XOR_B32_e32 v10, v10, v13 ; 3A141B0A V_XOR_B32_e32 v11, v11, v13 ; 3A161B0B V_MOV_B32_e32 v13, 0.000000e+00 ; 7E1A0280 S_MOV_B64 s[4:5], 0 ; BE840480 V_MOV_B32_e32 v14, s2 ; 7E1C0202 V_MOV_B32_e32 v17, v19 ; 7E220313 V_MOV_B32_e32 v18, v44 ; 7E24032C V_MOV_B32_e32 v16, v41 ; 7E200329 V_CMP_GE_I32_e64 s[2:3], v13, v14, 0, 0, 0, 0 ; D10C0002 02021D0D V_CNDMASK_B32_e64 v19, 0, -1, s[2:3], 0, 0, 0, 0 ; D2000013 00098280 V_CMP_EQ_I32_e64 s[2:3], v19, 0, 0, 0, 0, 0 ; D1040002 02010113 S_AND_SAVEEXEC_B64 s[2:3], s[2:3] ; BE822402 S_XOR_B64 s[2:3], exec, s[2:3] ; 8982027E S_CBRANCH_EXECZ BB0_10 ; BF880000 V_MUL_LO_I32 v19, 7, v13, 0, 0, 0, 0, 0 ; D2D60013 02021A87 V_LSHLREV_B32_e32 v19, 4, v19 ; 34262684 V_ADD_I32_e32 v20, 80, v19 ; 4A2826FF 00000050 BUFFER_LOAD_DWORD v20, s[12:15] + v20 + 0, glc=0, slc=0, tfe=0 ; E0301000 80031414 S_WAITCNT vmcnt(0) expcnt(0) ; BF8C0700 V_ADD_F32_e32 v20, v10, v20 ; 0628290A V_ADD_I32_e32 v21, 64, v19 ; 4A2A26C0 BUFFER_LOAD_DWORD v21, s[12:15] + v21 + 0, glc=0, slc=0, tfe=0 ; E0301000 80031515 S_WAITCNT vmcnt(0) ; BF8C0770 V_ADD_F32_e32 v21, v11, v21 ; 062A2B0B V_MUL_F32_e32 v22, v21, v21 ; 102C2B15 V_MAD_F32 v22, v20, v20, v22, 0, 0, 0, 0 ; D2820016 045A2914 V_ADD_I32_e32 v23, 96, v19 ; 4A2E26FF 00000060 BUFFER_LOAD_DWORD v23, s[12:15] + v23 + 0, glc=0, slc=0, tfe=0 ; E0301000 80031717 S_WAITCNT vmcnt(0) ; BF8C0770 V_ADD_F32_e32 v23, v12, v23 ; 062E2F0C V_MAD_F32 v22, v23, v23, v22, 0, 0, 0, 0 ; D2820016 045A2F17 V_RSQ_LEGACY_F32_e32 v24, v22 ; 7E305B16 V_MUL_F32_e32 v24, v24, v22 ; 10302D18 V_XOR_B32_e32 v22, -2147483648, v22 ; 3A2C2CFF 80000000 V_CMP_GT_F32_e64 s[10:11], 0, v22, 0, 0, 0, 0 ; D008000A 02022C80 V_CNDMASK_B32_e64 v22, 0.000000e+00, v24, s[10:11], 0, 0, 0, 0 ; D2000016 002A3080 V_RCP_F32_e32 v24, v22 ; 7E305516 V_MUL_F32_e32 v20, v20, v24 ; 10283114 V_MUL_F32_e32 v21, v21, v24 ; 102A3115 V_MUL_F32_e32 v25, v7, v21 ; 10322B07 V_MAD_F32 v25, v6, v20, v25, 0, 0, 0, 0 ; D2820019 04662906 V_MUL_F32_e32 v23, v23, v24 ; 102E3117 V_MAD_F32 v24, v0, v23, v25, 0, 0, 0, 0 ; D2820018 04662F00 V_CMP_U_F32_e64 s[10:11], v24, v24, 0, 0, 0, 0 ; D010000A 02023118 V_CMP_LE_F32_e64 s[16:17], v24, 0.000000e+00, 0, 0, 0, 0 ; D0060010 02010118 S_OR_B64 s[10:11], s[16:17], s[10:11] ; 888A0A10 V_CNDMASK_B32_e64 v24, v24, 0.000000e+00, s[10:11], 0, 0, 0, 0 ; D2000018 00290118 V_ADD_I32_e32 v25, 144, v19 ; 4A3226FF 00000090 BUFFER_LOAD_DWORD v25, s[12:15] + v25 + 0, glc=0, slc=0, tfe=0 ; E0301000 80031919 S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v26, v24, v25 ; 10343318 V_MUL_F32_e32 v26, v39, v26 ; 10343527 V_MUL_F32_e32 v21, v8, v21 ; 102A2B08 V_MAD_F32 v20, v1, v20, v21, 0, 0, 0, 0 ; D2820014 04562901 V_MAD_F32 v20, v9, v23, v20, 0, 0, 0, 0 ; D2820014 04522F09 V_MOV_B32_e32 v21, 1.000000e-03 ; 7E2A02FF 3A83126F V_CMP_LE_F32_e64 s[10:11], v20, v21, 0, 0, 0, 0 ; D006000A 02022B14 V_CMP_U_F32_e64 s[16:17], v20, v20, 0, 0, 0, 0 ; D0100010 02022914 S_OR_B64 s[10:11], s[10:11], s[16:17] ; 888A100A V_CNDMASK_B32_e64 v20, v20, v21, s[10:11], 0, 0, 0, 0 ; D2000014 002A2B14 V_LOG_F32_e32 v20, v20 ; 7E284F14 V_MUL_LEGACY_F32_e32 v20, s0, v20 ; 0E282800 V_EXP_F32_e32 v20, v20 ; 7E284B14 V_MUL_F32_e32 v21, v20, v25 ; 102A3314 V_MAD_F32 v21, v21, s6, v26, 0, 0, 0, 0 ; D2820015 04680D15 V_ADD_I32_e32 v23, 160, v19 ; 4A2E26FF 000000A0 BUFFER_LOAD_DWORD v23, s[12:15] + v23 + 0, glc=0, slc=0, tfe=0 ; E0301000 80031717 S_WAITCNT vmcnt(0) ; BF8C0770 V_MAD_F32 v22, v23, -5.000000e-01, v22, 0, 0, 0, 0 ; D2820016 0459E317 V_MAD_F32 v23, v23, -5.000000e-01, v23, 0, 0, 0, 0 ; D2820017 045DE317 V_RCP_F32_e32 v23, v23 ; 7E2E5517 V_MUL_F32_e32 v22, v22, v23 ; 102C2F16 V_ADD_F32_e64 v22, 0, v22, 0, 1, 0, 0 ; D2060816 02022C80 V_ADD_F32_e32 v23, v22, v22 ; 062E2D16 V_SUB_F32_e32 v23, 3.000000e+00, v23 ; 082E2EFF 40400000 V_MUL_F32_e32 v23, v22, v23 ; 102E2F16 V_MUL_F32_e32 v22, v22, v23 ; 102C2F16 V_SUB_F32_e32 v22, 1.000000e+00, v22 ; 082C2CF2 V_MAD_F32 v41, v21, v22, v16, 0, 0, 0, 0 ; D2820029 04422D15 V_ADD_I32_e32 v21, 128, v19 ; 4A2A26FF 00000080 BUFFER_LOAD_DWORD v21, s[12:15] + v21 + 0, glc=0, slc=0, tfe=0 ; E0301000 80031515 S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v23, v24, v21 ; 102E2B18 V_MUL_F32_e32 v23, v40, v23 ; 102E2F28 V_MUL_F32_e32 v21, v20, v21 ; 102A2B14 V_MAD_F32 v21, v21, s7, v23, 0, 0, 0, 0 ; D2820015 045C0F15 V_MAD_F32 v44, v21, v22, v18, 0, 0, 0, 0 ; D282002C 044A2D15 V_ADD_I32_e32 v19, 112, v19 ; 4A2626FF 00000070 BUFFER_LOAD_DWORD v19, s[12:15] + v19 + 0, glc=0, slc=0, tfe=0 ; E0301000 80031313 S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v21, v24, v19 ; 102A2718 V_MUL_F32_e32 v21, v15, v21 ; 102A2B0F V_MUL_F32_e32 v19, v20, v19 ; 10262714 V_MAD_F32 v19, v19, s8, v21, 0, 0, 0, 0 ; D2820013 04541113 V_MAD_F32 v19, v19, v22, v17, 0, 0, 0, 0 ; D2820013 04462D13 V_ADD_I32_e32 v13, 1, v13 ; 4A1A1A81 S_OR_B64 exec, exec, s[2:3] ; 88FE027E S_OR_B64 s[4:5], s[2:3], s[4:5] ; 88840402 S_ANDN2_B64 exec, exec, s[4:5] ; 8AFE047E S_CBRANCH_EXECNZ BB0_9 ; BF890000 S_OR_B64 exec, exec, s[4:5] ; 88FE047E V_MOV_B32_e32 v0, s1 ; 7E000201 V_MUL_F32_e64 v1, v18, v0, 0, 0, 0, 0 ; D2100001 02020112 V_MUL_F32_e64 v6, v17, v0, 0, 0, 0, 0 ; D2100006 02020111 V_CVT_PKRTZ_F16_F32_e32 v1, v6, v1 ; 5E020306 V_MUL_F32_e64 v0, v16, v0, 0, 0, 0, 0 ; D2100000 02020110 V_CVT_PKRTZ_F16_F32_e64 v0, v0, v5, 0, 0, 0, 0 ; D25E0000 02020B00 EXP 15, 0, 1, 1, 1, v1, v0, v1, v0 ; F8001C0F 00010001 S_ENDPGM ; BF810000 VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[20] DCL OUT[2], GENERIC[21] DCL OUT[3], GENERIC[22] DCL CONST[0..3] DCL CONST[1][0..96] DCL CONST[2][0..68] DCL TEMP[0..5], LOCAL DCL ADDR[0] IMM[0] UINT32 {0, 176, 160, 144} IMM[1] INT32 {11, 10, 9, 8} IMM[2] UINT32 {128, 48, 32, 16} IMM[3] INT32 {3, 2, 1, 0} 0: MUL TEMP[0], CONST[0], IN[0].xxxx 1: MAD TEMP[0], CONST[1], IN[0].yyyy, TEMP[0] 2: MAD TEMP[0], CONST[2], IN[0].zzzz, TEMP[0] 3: ADD TEMP[0], TEMP[0], CONST[3] 4: UARL ADDR[0].x, IMM[1].xxxx 5: MOV TEMP[1], CONST[1][ADDR[0].x] 6: UARL ADDR[0].x, IMM[1].yyyy 7: MOV TEMP[2], CONST[1][ADDR[0].x] 8: UARL ADDR[0].x, IMM[1].zzzz 9: MOV TEMP[3], CONST[1][ADDR[0].x] 10: UARL ADDR[0].x, IMM[1].wwww 11: MOV TEMP[4], CONST[1][ADDR[0].x] 12: MUL TEMP[4], TEMP[4], TEMP[0].xxxx 13: MAD TEMP[3], TEMP[3], TEMP[0].yyyy, TEMP[4] 14: MAD TEMP[2], TEMP[2], TEMP[0].zzzz, TEMP[3] 15: MAD TEMP[1], TEMP[1], TEMP[0].wwww, TEMP[2] 16: UARL ADDR[0].x, IMM[3].xxxx 17: MOV TEMP[2], CONST[1][ADDR[0].x] 18: UARL ADDR[0].x, IMM[3].yyyy 19: MOV TEMP[3], CONST[1][ADDR[0].x] 20: UARL ADDR[0].x, IMM[3].zzzz 21: MOV TEMP[4], CONST[1][ADDR[0].x] 22: UARL ADDR[0].x, IMM[3].wwww 23: MOV TEMP[5], CONST[1][ADDR[0].x] 24: MUL TEMP[5], TEMP[5], TEMP[0].xxxx 25: MAD TEMP[4], TEMP[4], TEMP[0].yyyy, TEMP[5] 26: MAD TEMP[3], TEMP[3], TEMP[0].zzzz, TEMP[4] 27: MAD TEMP[0].xyz, TEMP[2], TEMP[0].wwww, TEMP[3] 28: MOV TEMP[0].xyz, TEMP[0].xyzx 29: MOV TEMP[0].w, IN[0].xxxx 30: MOV TEMP[2].xy, IN[0].yzyy 31: MOV TEMP[2].zw, IN[1].yyxy 32: MOV TEMP[3].x, IN[1].zzzz 33: MOV OUT[1], TEMP[0] 34: MOV OUT[3], TEMP[3] 35: MOV OUT[2], TEMP[2] 36: MOV OUT[0], TEMP[1] 37: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0 %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0 %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0) %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4) %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8) %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12) %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16) %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20) %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24) %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28) %20 = call float @llvm.SI.load.const(<16 x i8> %11, i32 32) %21 = call float @llvm.SI.load.const(<16 x i8> %11, i32 36) %22 = call float @llvm.SI.load.const(<16 x i8> %11, i32 40) %23 = call float @llvm.SI.load.const(<16 x i8> %11, i32 44) %24 = call float @llvm.SI.load.const(<16 x i8> %11, i32 48) %25 = call float @llvm.SI.load.const(<16 x i8> %11, i32 52) %26 = call float @llvm.SI.load.const(<16 x i8> %11, i32 56) %27 = call float @llvm.SI.load.const(<16 x i8> %11, i32 60) %28 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 1 %29 = load <16 x i8> addrspace(2)* %28, !tbaa !0 %30 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 0 %31 = load <16 x i8> addrspace(2)* %30, !tbaa !0 %32 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %31, i32 0, i32 %6) %33 = extractelement <4 x float> %32, i32 0 %34 = extractelement <4 x float> %32, i32 1 %35 = extractelement <4 x float> %32, i32 2 %36 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 1 %37 = load <16 x i8> addrspace(2)* %36, !tbaa !0 %38 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %37, i32 0, i32 %6) %39 = extractelement <4 x float> %38, i32 0 %40 = extractelement <4 x float> %38, i32 1 %41 = extractelement <4 x float> %38, i32 2 %42 = fmul float %12, %33 %43 = fmul float %13, %33 %44 = fmul float %14, %33 %45 = fmul float %15, %33 %46 = fmul float %16, %34 %47 = fadd float %46, %42 %48 = fmul float %17, %34 %49 = fadd float %48, %43 %50 = fmul float %18, %34 %51 = fadd float %50, %44 %52 = fmul float %19, %34 %53 = fadd float %52, %45 %54 = fmul float %20, %35 %55 = fadd float %54, %47 %56 = fmul float %21, %35 %57 = fadd float %56, %49 %58 = fmul float %22, %35 %59 = fadd float %58, %51 %60 = fmul float %23, %35 %61 = fadd float %60, %53 %62 = fadd float %55, %24 %63 = fadd float %57, %25 %64 = fadd float %59, %26 %65 = fadd float %61, %27 %66 = shl i32 11, 4 %67 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %66) %68 = shl i32 11, 4 %69 = add i32 %68, 4 %70 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %69) %71 = shl i32 11, 4 %72 = add i32 %71, 8 %73 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %72) %74 = shl i32 11, 4 %75 = add i32 %74, 12 %76 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %75) %77 = shl i32 10, 4 %78 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %77) %79 = shl i32 10, 4 %80 = add i32 %79, 4 %81 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %80) %82 = shl i32 10, 4 %83 = add i32 %82, 8 %84 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %83) %85 = shl i32 10, 4 %86 = add i32 %85, 12 %87 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %86) %88 = shl i32 9, 4 %89 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %88) %90 = shl i32 9, 4 %91 = add i32 %90, 4 %92 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %91) %93 = shl i32 9, 4 %94 = add i32 %93, 8 %95 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %94) %96 = shl i32 9, 4 %97 = add i32 %96, 12 %98 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %97) %99 = shl i32 8, 4 %100 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %99) %101 = shl i32 8, 4 %102 = add i32 %101, 4 %103 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %102) %104 = shl i32 8, 4 %105 = add i32 %104, 8 %106 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %105) %107 = shl i32 8, 4 %108 = add i32 %107, 12 %109 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %108) %110 = fmul float %100, %62 %111 = fmul float %103, %62 %112 = fmul float %106, %62 %113 = fmul float %109, %62 %114 = fmul float %89, %63 %115 = fadd float %114, %110 %116 = fmul float %92, %63 %117 = fadd float %116, %111 %118 = fmul float %95, %63 %119 = fadd float %118, %112 %120 = fmul float %98, %63 %121 = fadd float %120, %113 %122 = fmul float %78, %64 %123 = fadd float %122, %115 %124 = fmul float %81, %64 %125 = fadd float %124, %117 %126 = fmul float %84, %64 %127 = fadd float %126, %119 %128 = fmul float %87, %64 %129 = fadd float %128, %121 %130 = fmul float %67, %65 %131 = fadd float %130, %123 %132 = fmul float %70, %65 %133 = fadd float %132, %125 %134 = fmul float %73, %65 %135 = fadd float %134, %127 %136 = fmul float %76, %65 %137 = fadd float %136, %129 %138 = shl i32 3, 4 %139 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %138) %140 = shl i32 3, 4 %141 = add i32 %140, 4 %142 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %141) %143 = shl i32 3, 4 %144 = add i32 %143, 8 %145 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %144) %146 = shl i32 2, 4 %147 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %146) %148 = shl i32 2, 4 %149 = add i32 %148, 4 %150 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %149) %151 = shl i32 2, 4 %152 = add i32 %151, 8 %153 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %152) %154 = shl i32 2, 4 %155 = add i32 %154, 12 %156 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %155) %157 = shl i32 1, 4 %158 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %157) %159 = shl i32 1, 4 %160 = add i32 %159, 4 %161 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %160) %162 = shl i32 1, 4 %163 = add i32 %162, 8 %164 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %163) %165 = shl i32 1, 4 %166 = add i32 %165, 12 %167 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %166) %168 = shl i32 0, 4 %169 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %168) %170 = shl i32 0, 4 %171 = add i32 %170, 4 %172 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %171) %173 = shl i32 0, 4 %174 = add i32 %173, 8 %175 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %174) %176 = shl i32 0, 4 %177 = add i32 %176, 12 %178 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %177) %179 = fmul float %169, %62 %180 = fmul float %172, %62 %181 = fmul float %175, %62 %182 = fmul float %178, %62 %183 = fmul float %158, %63 %184 = fadd float %183, %179 %185 = fmul float %161, %63 %186 = fadd float %185, %180 %187 = fmul float %164, %63 %188 = fadd float %187, %181 %189 = fmul float %167, %63 %190 = fadd float %189, %182 %191 = fmul float %147, %64 %192 = fadd float %191, %184 %193 = fmul float %150, %64 %194 = fadd float %193, %186 %195 = fmul float %153, %64 %196 = fadd float %195, %188 %197 = fmul float %156, %64 %198 = fadd float %197, %190 %199 = fmul float %139, %65 %200 = fadd float %199, %192 %201 = fmul float %142, %65 %202 = fadd float %201, %194 %203 = fmul float %145, %65 %204 = fadd float %203, %196 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %200, float %202, float %204, float %33) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %34, float %35, float %39, float %40) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %41, float %194, float %196, float %198) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %131, float %133, float %135, float %137) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_LOAD_DWORDX4 s[4:7], s[8:9], 0 ; C0820900 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[1:4], s[4:7][v0] + 0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80010100 S_LOAD_DWORDX4 s[4:7], s[0:1], 0 ; C0820100 S_WAITCNT vmcnt(0) lgkmcnt(0) ; BF8C0070 S_BUFFER_LOAD_DWORD s2, s[4:7], 1 ; C2010501 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v5, s2, v1 ; 100A0202 S_BUFFER_LOAD_DWORD s2, s[4:7], 5 ; C2010505 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v5, s2, v2, v5, 0, 0, 0, 0 ; D2820005 04160402 S_BUFFER_LOAD_DWORD s2, s[4:7], 9 ; C2010509 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v5, s2, v3, v5, 0, 0, 0, 0 ; D2820005 04160602 S_BUFFER_LOAD_DWORD s2, s[4:7], 13 ; C201050D S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v5, s2, v5 ; 060A0A02 S_BUFFER_LOAD_DWORD s2, s[4:7], 0 ; C2010500 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v6, s2, v1 ; 100C0202 S_BUFFER_LOAD_DWORD s2, s[4:7], 4 ; C2010504 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v6, s2, v2, v6, 0, 0, 0, 0 ; D2820006 041A0402 S_BUFFER_LOAD_DWORD s2, s[4:7], 8 ; C2010508 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v6, s2, v3, v6, 0, 0, 0, 0 ; D2820006 041A0602 S_BUFFER_LOAD_DWORD s2, s[4:7], 12 ; C201050C S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v6, s2, v6 ; 060C0C02 S_LOAD_DWORDX4 s[0:3], s[0:1], 4 ; C0800104 S_WAITCNT lgkmcnt(0) ; BF8C007F S_BUFFER_LOAD_DWORD s10, s[0:3], 2 ; C2050102 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v7, s10, v6 ; 100E0C0A S_BUFFER_LOAD_DWORD s10, s[0:3], 6 ; C2050106 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v7, s10, v5, v7, 0, 0, 0, 0 ; D2820007 041E0A0A S_BUFFER_LOAD_DWORD s10, s[4:7], 2 ; C2050502 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v8, s10, v1 ; 1010020A S_BUFFER_LOAD_DWORD s10, s[4:7], 6 ; C2050506 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v8, s10, v2, v8, 0, 0, 0, 0 ; D2820008 0422040A S_BUFFER_LOAD_DWORD s10, s[4:7], 10 ; C205050A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v8, s10, v3, v8, 0, 0, 0, 0 ; D2820008 0422060A S_BUFFER_LOAD_DWORD s10, s[4:7], 14 ; C205050E S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v8, s10, v8 ; 0610100A S_BUFFER_LOAD_DWORD s10, s[0:3], 10 ; C205010A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v7, s10, v8, v7, 0, 0, 0, 0 ; D2820007 041E100A S_BUFFER_LOAD_DWORD s10, s[4:7], 3 ; C2050503 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v9, s10, v1 ; 1012020A S_BUFFER_LOAD_DWORD s10, s[4:7], 7 ; C2050507 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v9, s10, v2, v9, 0, 0, 0, 0 ; D2820009 0426040A S_BUFFER_LOAD_DWORD s10, s[4:7], 11 ; C205050B S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v9, s10, v3, v9, 0, 0, 0, 0 ; D2820009 0426060A S_BUFFER_LOAD_DWORD s4, s[4:7], 15 ; C202050F S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v9, s4, v9 ; 06121204 S_BUFFER_LOAD_DWORD s4, s[0:3], 14 ; C202010E S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v10, s4, v9, v7, 0, 0, 0, 0 ; D282000A 041E1204 S_BUFFER_LOAD_DWORD s4, s[0:3], 1 ; C2020101 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v11, s4, v6 ; 10160C04 S_BUFFER_LOAD_DWORD s4, s[0:3], 5 ; C2020105 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v11, s4, v5, v11, 0, 0, 0, 0 ; D282000B 042E0A04 S_BUFFER_LOAD_DWORD s4, s[0:3], 9 ; C2020109 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v11, s4, v8, v11, 0, 0, 0, 0 ; D282000B 042E1004 S_BUFFER_LOAD_DWORD s4, s[0:3], 13 ; C202010D S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v12, s4, v9, v11, 0, 0, 0, 0 ; D282000C 042E1204 S_BUFFER_LOAD_DWORD s4, s[0:3], 0 ; C2020100 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v13, s4, v6 ; 101A0C04 S_BUFFER_LOAD_DWORD s4, s[0:3], 4 ; C2020104 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v13, s4, v5, v13, 0, 0, 0, 0 ; D282000D 04360A04 S_BUFFER_LOAD_DWORD s4, s[0:3], 8 ; C2020108 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v13, s4, v8, v13, 0, 0, 0, 0 ; D282000D 04361004 S_BUFFER_LOAD_DWORD s4, s[0:3], 12 ; C202010C S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v13, s4, v9, v13, 0, 0, 0, 0 ; D282000D 04361204 EXP 15, 32, 0, 0, 0, v13, v12, v10, v1 ; F800020F 010A0C0D S_LOAD_DWORDX4 s[4:7], s[8:9], 4 ; C0820904 S_WAITCNT expcnt(0) lgkmcnt(0) ; BF8C000F BUFFER_LOAD_FORMAT_XYZW v[12:15], s[4:7][v0] + 0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80010C00 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 33, 0, 0, 0, v2, v3, v12, v13 ; F800021F 0D0C0302 S_BUFFER_LOAD_DWORD s4, s[0:3], 3 ; C2020103 S_WAITCNT expcnt(0) lgkmcnt(0) ; BF8C000F V_MUL_F32_e32 v0, s4, v6 ; 10000C04 S_BUFFER_LOAD_DWORD s4, s[0:3], 7 ; C2020107 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v0, s4, v5, v0, 0, 0, 0, 0 ; D2820000 04020A04 S_BUFFER_LOAD_DWORD s4, s[0:3], 11 ; C202010B S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v0, s4, v8, v0, 0, 0, 0, 0 ; D2820000 04021004 EXP 15, 34, 0, 0, 0, v14, v11, v7, v0 ; F800022F 00070B0E S_BUFFER_LOAD_DWORD s4, s[0:3], 35 ; C2020123 S_WAITCNT expcnt(0) lgkmcnt(0) ; BF8C000F V_MUL_F32_e32 v0, s4, v6 ; 10000C04 S_BUFFER_LOAD_DWORD s4, s[0:3], 39 ; C2020127 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v0, s4, v5, v0, 0, 0, 0, 0 ; D2820000 04020A04 S_BUFFER_LOAD_DWORD s4, s[0:3], 43 ; C202012B S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v0, s4, v8, v0, 0, 0, 0, 0 ; D2820000 04021004 S_BUFFER_LOAD_DWORD s4, s[0:3], 47 ; C202012F S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v0, s4, v9, v0, 0, 0, 0, 0 ; D2820000 04021204 S_BUFFER_LOAD_DWORD s4, s[0:3], 34 ; C2020122 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v1, s4, v6 ; 10020C04 S_BUFFER_LOAD_DWORD s4, s[0:3], 38 ; C2020126 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v1, s4, v5, v1, 0, 0, 0, 0 ; D2820001 04060A04 S_BUFFER_LOAD_DWORD s4, s[0:3], 42 ; C202012A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v1, s4, v8, v1, 0, 0, 0, 0 ; D2820001 04061004 S_BUFFER_LOAD_DWORD s4, s[0:3], 46 ; C202012E S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v1, s4, v9, v1, 0, 0, 0, 0 ; D2820001 04061204 S_BUFFER_LOAD_DWORD s4, s[0:3], 33 ; C2020121 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v2, s4, v6 ; 10040C04 S_BUFFER_LOAD_DWORD s4, s[0:3], 37 ; C2020125 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v2, s4, v5, v2, 0, 0, 0, 0 ; D2820002 040A0A04 S_BUFFER_LOAD_DWORD s4, s[0:3], 41 ; C2020129 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v2, s4, v8, v2, 0, 0, 0, 0 ; D2820002 040A1004 S_BUFFER_LOAD_DWORD s4, s[0:3], 45 ; C202012D S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v2, s4, v9, v2, 0, 0, 0, 0 ; D2820002 040A1204 S_BUFFER_LOAD_DWORD s4, s[0:3], 32 ; C2020120 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v3, s4, v6 ; 10060C04 S_BUFFER_LOAD_DWORD s4, s[0:3], 36 ; C2020124 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v3, s4, v5, v3, 0, 0, 0, 0 ; D2820003 040E0A04 S_BUFFER_LOAD_DWORD s4, s[0:3], 40 ; C2020128 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v3, s4, v8, v3, 0, 0, 0, 0 ; D2820003 040E1004 S_BUFFER_LOAD_DWORD s0, s[0:3], 44 ; C200012C S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v3, s0, v9, v3, 0, 0, 0, 0 ; D2820003 040E1200 EXP 15, 12, 0, 1, 0, v3, v2, v1, v0 ; F80008CF 00010203 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[20], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL CONST[1] DCL CONST[1][0..96] DCL TEMP[0], LOCAL IMM[0] FLT32 { 1.0000, 0.0000, 0.0000, 0.0000} 0: MOV TEMP[0].xy, IN[0].xyyy 1: TEX TEMP[0].w, TEMP[0], SAMP[0], 2D 2: FSLT TEMP[0].x, TEMP[0].wwww, CONST[1].xxxx 3: UIF TEMP[0].xxxx :0 4: KILL 5: ENDIF 6: MOV TEMP[0].xyz, IMM[0].xxxx 7: MOV OUT[0], TEMP[0] 8: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %22 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0 %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0 %24 = call float @llvm.SI.load.const(<16 x i8> %23, i32 16) %25 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0 %26 = load <32 x i8> addrspace(2)* %25, !tbaa !0 %27 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0 %28 = load <16 x i8> addrspace(2)* %27, !tbaa !0 %29 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %7) %30 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %7) %31 = bitcast float %29 to i32 %32 = bitcast float %30 to i32 %33 = insertelement <2 x i32> undef, i32 %31, i32 0 %34 = insertelement <2 x i32> %33, i32 %32, i32 1 %35 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %34, <32 x i8> %26, <16 x i8> %28, i32 2) %36 = extractelement <4 x float> %35, i32 3 %37 = fcmp olt float %36, %24 %38 = sext i1 %37 to i32 %39 = bitcast i32 %38 to float %40 = bitcast float %39 to i32 %41 = icmp ne i32 %40, 0 br i1 %41, label %IF, label %ENDIF IF: ; preds = %main_body call void @llvm.AMDGPU.kilp() br label %ENDIF ENDIF: ; preds = %main_body, %IF %42 = call i32 @llvm.SI.packf16(float 1.000000e+00, float 1.000000e+00) %43 = bitcast i32 %42 to float %44 = call i32 @llvm.SI.packf16(float 1.000000e+00, float %36) %45 = bitcast i32 %44 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %43, float %45, float %43, float %45) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1 declare void @llvm.AMDGPU.kilp() ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s9 ; BEFC0309 V_INTERP_P1_F32 v3, v0, 1, 0, [m0] ; C80C0100 V_INTERP_P2_F32 v3, [v3], v1, 1, 0, [m0] ; C80D0101 V_INTERP_P1_F32 v2, v0, 0, 0, [m0] ; C8080000 V_INTERP_P2_F32 v2, [v2], v1, 0, 0, [m0] ; C8090001 S_LOAD_DWORDX4 s[8:11], s[2:3], 0 ; C0840300 S_LOAD_DWORDX8 s[12:19], s[4:5], 0 ; C0C60500 S_WAITCNT lgkmcnt(0) ; BF8C007F IMAGE_SAMPLE v0, 8, 0, 0, 0, 0, 0, 0, 0, v[2:3], s[12:19], s[8:11] ; F0800800 00430002 S_LOAD_DWORDX4 s[0:3], s[0:1], 0 ; C0800100 S_WAITCNT vmcnt(0) lgkmcnt(0) ; BF8C0070 S_BUFFER_LOAD_DWORD s0, s[0:3], 4 ; C2000104 S_WAITCNT lgkmcnt(0) ; BF8C007F V_CMP_LT_F32_e64 s[0:1], v0, s0, 0, 0, 0, 0 ; D0020000 02000100 S_AND_SAVEEXEC_B64 s[0:1], s[0:1] ; BE802400 S_XOR_B64 s[0:1], exec, s[0:1] ; 8980007E S_MOV_B64 exec, 0 ; BEFE0480 S_OR_B64 exec, exec, s[0:1] ; 88FE007E V_CVT_PKRTZ_F16_F32_e64 v0, 1.000000e+00, v0, 0, 0, 0, 0 ; D25E0000 020200F2 V_CVT_PKRTZ_F16_F32_e64 v1, 1.000000e+00, 1.000000e+00, 0, 0, 0, 0 ; D25E0001 0201E4F2 EXP 15, 0, 1, 1, 1, v1, v0, v1, v0 ; F8001C0F 00010001 S_ENDPGM ; BF810000 VERT DCL IN[0] DCL IN[1] DCL IN[2] DCL IN[3] DCL IN[4] DCL OUT[0], POSITION DCL OUT[1], GENERIC[20] DCL CONST[0..4] DCL CONST[1][0..96] DCL TEMP[0..5], LOCAL DCL ADDR[0] IMM[0] FLT32 { 0.0000, 0.8000, 1.0000, 3.0000} IMM[1] UINT32 {0, 320, 368, 176} IMM[2] INT32 {20, 23, 11, 10} IMM[3] FLT32 { 2.0000, 0.1000, 0.0000, 0.0000} IMM[4] UINT32 {160, 144, 128, 0} IMM[5] INT32 {9, 8, 0, 0} 0: DP3 TEMP[0].x, IN[4].xyzz, IN[4].xyzz 1: RSQ TEMP[1].x, TEMP[0].xxxx 2: MUL TEMP[1].x, TEMP[1].xxxx, TEMP[0].xxxx 3: CMP TEMP[0].x, -TEMP[0].xxxx, TEMP[1].xxxx, IMM[0].xxxx 4: MUL TEMP[1].xyz, IN[3].zxyy, IN[4].yzxx 5: MAD TEMP[1].xyz, IN[3].yzxx, IN[4].zxyy, -TEMP[1].xyzz 6: DP3 TEMP[2].x, TEMP[1].xyzz, TEMP[1].xyzz 7: RSQ TEMP[2].x, TEMP[2].xxxx 8: MUL TEMP[1].xyz, TEMP[1].xyzz, TEMP[2].xxxx 9: MUL TEMP[2].xyz, TEMP[1].zxyy, IN[3].yzxx 10: MAD TEMP[2].xyz, TEMP[1].yzxx, IN[3].zxyy, -TEMP[2].xyzz 11: MUL TEMP[1].xyz, TEMP[1].xyzz, TEMP[0].xxxx 12: DP3 TEMP[3].x, TEMP[2].xyzz, TEMP[2].xyzz 13: RSQ TEMP[3].x, TEMP[3].xxxx 14: MUL TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xxxx 15: MUL TEMP[0].xyz, TEMP[2].xyzz, TEMP[0].xxxx 16: UARL ADDR[0].x, IMM[2].xxxx 17: MOV TEMP[2].xyz, CONST[1][ADDR[0].x].xyzz 18: ADD TEMP[2].xyz, IN[2].xyzz, -TEMP[2].xyzz 19: MUL TEMP[3].x, CONST[4].xxxx, IMM[0].yyyy 20: DP3 TEMP[2].x, TEMP[2].xyzz, TEMP[2].xyzz 21: RSQ TEMP[4].x, TEMP[2].xxxx 22: MUL TEMP[4].x, TEMP[4].xxxx, TEMP[2].xxxx 23: CMP TEMP[4].x, -TEMP[2].xxxx, TEMP[4].xxxx, IMM[0].xxxx 24: ADD TEMP[2].x, TEMP[4].xxxx, -TEMP[3].xxxx 25: ADD TEMP[3].x, CONST[4].xxxx, -TEMP[3].xxxx 26: RCP TEMP[3].x, TEMP[3].xxxx 27: MUL_SAT TEMP[2].x, TEMP[2].xxxx, TEMP[3].xxxx 28: MUL TEMP[3].x, IMM[3].xxxx, TEMP[2].xxxx 29: ADD TEMP[3].x, IMM[0].wwww, -TEMP[3].xxxx 30: MUL TEMP[3].x, TEMP[2].xxxx, TEMP[3].xxxx 31: MUL TEMP[3].x, TEMP[2].xxxx, TEMP[3].xxxx 32: ADD TEMP[3].x, IMM[0].zzzz, -TEMP[3].xxxx 33: MUL TEMP[2].xyz, IN[0].xyzz, TEMP[3].xxxx 34: MUL TEMP[3], CONST[0], TEMP[0].xxxx 35: MAD TEMP[3], CONST[1], TEMP[0].yyyy, TEMP[3] 36: MAD TEMP[0], CONST[2], TEMP[0].zzzz, TEMP[3] 37: MUL TEMP[3], CONST[0], IN[3].xxxx 38: MAD TEMP[3], CONST[1], IN[3].yyyy, TEMP[3] 39: MAD TEMP[3], CONST[2], IN[3].zzzz, TEMP[3] 40: MUL TEMP[4], CONST[0], TEMP[1].xxxx 41: MAD TEMP[4], CONST[1], TEMP[1].yyyy, TEMP[4] 42: MAD TEMP[1], CONST[2], TEMP[1].zzzz, TEMP[4] 43: MUL TEMP[1], TEMP[1], TEMP[2].xxxx 44: MAD TEMP[1], TEMP[3], TEMP[2].yyyy, TEMP[1] 45: MAD TEMP[0], TEMP[0], TEMP[2].zzzz, TEMP[1] 46: MUL TEMP[1], CONST[0], IN[2].xxxx 47: MAD TEMP[1], CONST[1], IN[2].yyyy, TEMP[1] 48: MAD TEMP[1], CONST[2], IN[2].zzzz, TEMP[1] 49: ADD TEMP[1], TEMP[1], CONST[3] 50: ADD TEMP[0], TEMP[0], TEMP[1] 51: UARL ADDR[0].x, IMM[2].yyyy 52: MOV TEMP[2].x, CONST[1][ADDR[0].x].xxxx 53: ADD TEMP[2].x, TEMP[2].xxxx, IN[2].xxxx 54: ADD TEMP[2].x, TEMP[2].xxxx, IN[2].yyyy 55: ADD TEMP[2].x, TEMP[2].xxxx, IN[2].zzzz 56: COS TEMP[2].x, TEMP[2].xxxx 57: MOV TEMP[3].y, IMM[0].xxxx 58: ADD TEMP[4].x, IN[2].xxxx, IN[2].zzzz 59: COS TEMP[4].x, TEMP[4].xxxx 60: MUL TEMP[3].x, TEMP[2].xxxx, TEMP[4].xxxx 61: ADD TEMP[4].x, IN[2].yyyy, IN[2].zzzz 62: COS TEMP[4].x, TEMP[4].xxxx 63: MUL TEMP[2].x, TEMP[2].xxxx, TEMP[4].xxxx 64: MOV TEMP[3].z, TEMP[2].xxxx 65: MAX TEMP[2].x, IMM[0].xxxx, IN[0].yyyy 66: MUL TEMP[2].xyz, TEMP[3].xyzz, TEMP[2].xxxx 67: MAD TEMP[1].xyz, TEMP[2].xyzz, IMM[3].yyyy, TEMP[0].xyzz 68: UARL ADDR[0].x, IMM[2].zzzz 69: MOV TEMP[2], CONST[1][ADDR[0].x] 70: UARL ADDR[0].x, IMM[2].wwww 71: MOV TEMP[3], CONST[1][ADDR[0].x] 72: UARL ADDR[0].x, IMM[5].xxxx 73: MOV TEMP[4], CONST[1][ADDR[0].x] 74: UARL ADDR[0].x, IMM[5].yyyy 75: MOV TEMP[5], CONST[1][ADDR[0].x] 76: MUL TEMP[5], TEMP[5], TEMP[1].xxxx 77: MAD TEMP[4], TEMP[4], TEMP[1].yyyy, TEMP[5] 78: MAD TEMP[1], TEMP[3], TEMP[1].zzzz, TEMP[4] 79: MAD TEMP[0], TEMP[2], TEMP[0].wwww, TEMP[1] 80: MOV TEMP[1].xy, IN[1].xyxx 81: MOV OUT[1], TEMP[1] 82: MOV OUT[0], TEMP[0] 83: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0 %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0 %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0) %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4) %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8) %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12) %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16) %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20) %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24) %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28) %20 = call float @llvm.SI.load.const(<16 x i8> %11, i32 32) %21 = call float @llvm.SI.load.const(<16 x i8> %11, i32 36) %22 = call float @llvm.SI.load.const(<16 x i8> %11, i32 40) %23 = call float @llvm.SI.load.const(<16 x i8> %11, i32 44) %24 = call float @llvm.SI.load.const(<16 x i8> %11, i32 48) %25 = call float @llvm.SI.load.const(<16 x i8> %11, i32 52) %26 = call float @llvm.SI.load.const(<16 x i8> %11, i32 56) %27 = call float @llvm.SI.load.const(<16 x i8> %11, i32 60) %28 = call float @llvm.SI.load.const(<16 x i8> %11, i32 64) %29 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 1 %30 = load <16 x i8> addrspace(2)* %29, !tbaa !0 %31 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 0 %32 = load <16 x i8> addrspace(2)* %31, !tbaa !0 %33 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %32, i32 0, i32 %6) %34 = extractelement <4 x float> %33, i32 0 %35 = extractelement <4 x float> %33, i32 1 %36 = extractelement <4 x float> %33, i32 2 %37 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 1 %38 = load <16 x i8> addrspace(2)* %37, !tbaa !0 %39 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %38, i32 0, i32 %6) %40 = extractelement <4 x float> %39, i32 0 %41 = extractelement <4 x float> %39, i32 1 %42 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 2 %43 = load <16 x i8> addrspace(2)* %42, !tbaa !0 %44 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %43, i32 0, i32 %6) %45 = extractelement <4 x float> %44, i32 0 %46 = extractelement <4 x float> %44, i32 1 %47 = extractelement <4 x float> %44, i32 2 %48 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 3 %49 = load <16 x i8> addrspace(2)* %48, !tbaa !0 %50 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %49, i32 0, i32 %6) %51 = extractelement <4 x float> %50, i32 0 %52 = extractelement <4 x float> %50, i32 1 %53 = extractelement <4 x float> %50, i32 2 %54 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 4 %55 = load <16 x i8> addrspace(2)* %54, !tbaa !0 %56 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %55, i32 0, i32 %6) %57 = extractelement <4 x float> %56, i32 0 %58 = extractelement <4 x float> %56, i32 1 %59 = extractelement <4 x float> %56, i32 2 %60 = fmul float %57, %57 %61 = fmul float %58, %58 %62 = fadd float %61, %60 %63 = fmul float %59, %59 %64 = fadd float %62, %63 %65 = call float @llvm.AMDGPU.rsq(float %64) %66 = fmul float %65, %64 %67 = fsub float -0.000000e+00, %64 %68 = call float @llvm.AMDGPU.cndlt(float %67, float %66, float 0.000000e+00) %69 = fmul float %53, %58 %70 = fmul float %51, %59 %71 = fmul float %52, %57 %72 = fsub float -0.000000e+00, %69 %73 = fmul float %52, %59 %74 = fadd float %73, %72 %75 = fsub float -0.000000e+00, %70 %76 = fmul float %53, %57 %77 = fadd float %76, %75 %78 = fsub float -0.000000e+00, %71 %79 = fmul float %51, %58 %80 = fadd float %79, %78 %81 = fmul float %74, %74 %82 = fmul float %77, %77 %83 = fadd float %82, %81 %84 = fmul float %80, %80 %85 = fadd float %83, %84 %86 = call float @llvm.AMDGPU.rsq(float %85) %87 = fmul float %74, %86 %88 = fmul float %77, %86 %89 = fmul float %80, %86 %90 = fmul float %89, %52 %91 = fmul float %87, %53 %92 = fmul float %88, %51 %93 = fsub float -0.000000e+00, %90 %94 = fmul float %88, %53 %95 = fadd float %94, %93 %96 = fsub float -0.000000e+00, %91 %97 = fmul float %89, %51 %98 = fadd float %97, %96 %99 = fsub float -0.000000e+00, %92 %100 = fmul float %87, %52 %101 = fadd float %100, %99 %102 = fmul float %87, %68 %103 = fmul float %88, %68 %104 = fmul float %89, %68 %105 = fmul float %95, %95 %106 = fmul float %98, %98 %107 = fadd float %106, %105 %108 = fmul float %101, %101 %109 = fadd float %107, %108 %110 = call float @llvm.AMDGPU.rsq(float %109) %111 = fmul float %95, %110 %112 = fmul float %98, %110 %113 = fmul float %101, %110 %114 = fmul float %111, %68 %115 = fmul float %112, %68 %116 = fmul float %113, %68 %117 = shl i32 20, 4 %118 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %117) %119 = shl i32 20, 4 %120 = add i32 %119, 4 %121 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %120) %122 = shl i32 20, 4 %123 = add i32 %122, 8 %124 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %123) %125 = fsub float -0.000000e+00, %118 %126 = fadd float %45, %125 %127 = fsub float -0.000000e+00, %121 %128 = fadd float %46, %127 %129 = fsub float -0.000000e+00, %124 %130 = fadd float %47, %129 %131 = fmul float %28, 0x3FE99999A0000000 %132 = fmul float %126, %126 %133 = fmul float %128, %128 %134 = fadd float %133, %132 %135 = fmul float %130, %130 %136 = fadd float %134, %135 %137 = call float @llvm.AMDGPU.rsq(float %136) %138 = fmul float %137, %136 %139 = fsub float -0.000000e+00, %136 %140 = call float @llvm.AMDGPU.cndlt(float %139, float %138, float 0.000000e+00) %141 = fsub float -0.000000e+00, %131 %142 = fadd float %140, %141 %143 = fsub float -0.000000e+00, %131 %144 = fadd float %28, %143 %145 = fdiv float 1.000000e+00, %144 %146 = fmul float %142, %145 %147 = call float @llvm.AMDIL.clamp.(float %146, float 0.000000e+00, float 1.000000e+00) %148 = fmul float 2.000000e+00, %147 %149 = fsub float -0.000000e+00, %148 %150 = fadd float 3.000000e+00, %149 %151 = fmul float %147, %150 %152 = fmul float %147, %151 %153 = fsub float -0.000000e+00, %152 %154 = fadd float 1.000000e+00, %153 %155 = fmul float %34, %154 %156 = fmul float %35, %154 %157 = fmul float %36, %154 %158 = fmul float %12, %114 %159 = fmul float %13, %114 %160 = fmul float %14, %114 %161 = fmul float %15, %114 %162 = fmul float %16, %115 %163 = fadd float %162, %158 %164 = fmul float %17, %115 %165 = fadd float %164, %159 %166 = fmul float %18, %115 %167 = fadd float %166, %160 %168 = fmul float %19, %115 %169 = fadd float %168, %161 %170 = fmul float %20, %116 %171 = fadd float %170, %163 %172 = fmul float %21, %116 %173 = fadd float %172, %165 %174 = fmul float %22, %116 %175 = fadd float %174, %167 %176 = fmul float %23, %116 %177 = fadd float %176, %169 %178 = fmul float %12, %51 %179 = fmul float %13, %51 %180 = fmul float %14, %51 %181 = fmul float %15, %51 %182 = fmul float %16, %52 %183 = fadd float %182, %178 %184 = fmul float %17, %52 %185 = fadd float %184, %179 %186 = fmul float %18, %52 %187 = fadd float %186, %180 %188 = fmul float %19, %52 %189 = fadd float %188, %181 %190 = fmul float %20, %53 %191 = fadd float %190, %183 %192 = fmul float %21, %53 %193 = fadd float %192, %185 %194 = fmul float %22, %53 %195 = fadd float %194, %187 %196 = fmul float %23, %53 %197 = fadd float %196, %189 %198 = fmul float %12, %102 %199 = fmul float %13, %102 %200 = fmul float %14, %102 %201 = fmul float %15, %102 %202 = fmul float %16, %103 %203 = fadd float %202, %198 %204 = fmul float %17, %103 %205 = fadd float %204, %199 %206 = fmul float %18, %103 %207 = fadd float %206, %200 %208 = fmul float %19, %103 %209 = fadd float %208, %201 %210 = fmul float %20, %104 %211 = fadd float %210, %203 %212 = fmul float %21, %104 %213 = fadd float %212, %205 %214 = fmul float %22, %104 %215 = fadd float %214, %207 %216 = fmul float %23, %104 %217 = fadd float %216, %209 %218 = fmul float %211, %155 %219 = fmul float %213, %155 %220 = fmul float %215, %155 %221 = fmul float %217, %155 %222 = fmul float %191, %156 %223 = fadd float %222, %218 %224 = fmul float %193, %156 %225 = fadd float %224, %219 %226 = fmul float %195, %156 %227 = fadd float %226, %220 %228 = fmul float %197, %156 %229 = fadd float %228, %221 %230 = fmul float %171, %157 %231 = fadd float %230, %223 %232 = fmul float %173, %157 %233 = fadd float %232, %225 %234 = fmul float %175, %157 %235 = fadd float %234, %227 %236 = fmul float %177, %157 %237 = fadd float %236, %229 %238 = fmul float %12, %45 %239 = fmul float %13, %45 %240 = fmul float %14, %45 %241 = fmul float %15, %45 %242 = fmul float %16, %46 %243 = fadd float %242, %238 %244 = fmul float %17, %46 %245 = fadd float %244, %239 %246 = fmul float %18, %46 %247 = fadd float %246, %240 %248 = fmul float %19, %46 %249 = fadd float %248, %241 %250 = fmul float %20, %47 %251 = fadd float %250, %243 %252 = fmul float %21, %47 %253 = fadd float %252, %245 %254 = fmul float %22, %47 %255 = fadd float %254, %247 %256 = fmul float %23, %47 %257 = fadd float %256, %249 %258 = fadd float %251, %24 %259 = fadd float %253, %25 %260 = fadd float %255, %26 %261 = fadd float %257, %27 %262 = fadd float %231, %258 %263 = fadd float %233, %259 %264 = fadd float %235, %260 %265 = fadd float %237, %261 %266 = shl i32 23, 4 %267 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %266) %268 = fadd float %267, %45 %269 = fadd float %268, %46 %270 = fadd float %269, %47 %271 = call float @llvm.cos.f32(float %270) %272 = fadd float %45, %47 %273 = call float @llvm.cos.f32(float %272) %274 = fmul float %271, %273 %275 = fadd float %46, %47 %276 = call float @llvm.cos.f32(float %275) %277 = fmul float %271, %276 %278 = fcmp uge float 0.000000e+00, %35 %279 = select i1 %278, float 0.000000e+00, float %35 %280 = fmul float %274, %279 %281 = fmul float 0.000000e+00, %279 %282 = fmul float %277, %279 %283 = fmul float %280, 0x3FB99999A0000000 %284 = fadd float %283, %262 %285 = fmul float %281, 0x3FB99999A0000000 %286 = fadd float %285, %263 %287 = fmul float %282, 0x3FB99999A0000000 %288 = fadd float %287, %264 %289 = shl i32 11, 4 %290 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %289) %291 = shl i32 11, 4 %292 = add i32 %291, 4 %293 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %292) %294 = shl i32 11, 4 %295 = add i32 %294, 8 %296 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %295) %297 = shl i32 11, 4 %298 = add i32 %297, 12 %299 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %298) %300 = shl i32 10, 4 %301 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %300) %302 = shl i32 10, 4 %303 = add i32 %302, 4 %304 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %303) %305 = shl i32 10, 4 %306 = add i32 %305, 8 %307 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %306) %308 = shl i32 10, 4 %309 = add i32 %308, 12 %310 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %309) %311 = shl i32 9, 4 %312 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %311) %313 = shl i32 9, 4 %314 = add i32 %313, 4 %315 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %314) %316 = shl i32 9, 4 %317 = add i32 %316, 8 %318 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %317) %319 = shl i32 9, 4 %320 = add i32 %319, 12 %321 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %320) %322 = shl i32 8, 4 %323 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %322) %324 = shl i32 8, 4 %325 = add i32 %324, 4 %326 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %325) %327 = shl i32 8, 4 %328 = add i32 %327, 8 %329 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %328) %330 = shl i32 8, 4 %331 = add i32 %330, 12 %332 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %331) %333 = fmul float %323, %284 %334 = fmul float %326, %284 %335 = fmul float %329, %284 %336 = fmul float %332, %284 %337 = fmul float %312, %286 %338 = fadd float %337, %333 %339 = fmul float %315, %286 %340 = fadd float %339, %334 %341 = fmul float %318, %286 %342 = fadd float %341, %335 %343 = fmul float %321, %286 %344 = fadd float %343, %336 %345 = fmul float %301, %288 %346 = fadd float %345, %338 %347 = fmul float %304, %288 %348 = fadd float %347, %340 %349 = fmul float %307, %288 %350 = fadd float %349, %342 %351 = fmul float %310, %288 %352 = fadd float %351, %344 %353 = fmul float %290, %265 %354 = fadd float %353, %346 %355 = fmul float %293, %265 %356 = fadd float %355, %348 %357 = fmul float %296, %265 %358 = fadd float %357, %350 %359 = fmul float %299, %265 %360 = fadd float %359, %352 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %40, float %41, float %350, float %352) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %354, float %356, float %358, float %360) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 ; Function Attrs: readnone declare float @llvm.AMDGPU.rsq(float) #2 ; Function Attrs: readnone declare float @llvm.AMDGPU.cndlt(float, float, float) #2 ; Function Attrs: readnone declare float @llvm.AMDIL.clamp.(float, float, float) #2 ; Function Attrs: nounwind readonly declare float @llvm.cos.f32(float) #3 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } attributes #3 = { nounwind readonly } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_LOAD_DWORDX4 s[4:7], s[8:9], 16 ; C0820910 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[1:4], s[4:7][v0] + 0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80010100 S_LOAD_DWORDX4 s[4:7], s[8:9], 12 ; C082090C S_WAITCNT vmcnt(0) lgkmcnt(0) ; BF8C0070 BUFFER_LOAD_FORMAT_XYZW v[5:8], s[4:7][v0] + 0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80010500 S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v9, v5, v3 ; 10120705 V_MUL_F32_e32 v10, v7, v1 ; 10140307 V_SUB_F32_e32 v9, v10, v9 ; 0812130A V_MUL_F32_e32 v10, v7, v2 ; 10140507 V_MUL_F32_e32 v11, v6, v3 ; 10160706 V_SUB_F32_e32 v10, v11, v10 ; 0814150B V_MUL_F32_e32 v11, v10, v10 ; 1016150A V_MAD_F32 v11, v9, v9, v11, 0, 0, 0, 0 ; D282000B 042E1309 V_MUL_F32_e32 v12, v6, v1 ; 10180306 V_MUL_F32_e32 v13, v5, v2 ; 101A0505 V_SUB_F32_e32 v12, v13, v12 ; 0818190D V_MAD_F32 v11, v12, v12, v11, 0, 0, 0, 0 ; D282000B 042E190C V_RSQ_LEGACY_F32_e32 v11, v11 ; 7E165B0B V_MUL_F32_e32 v10, v10, v11 ; 1014170A V_MUL_F32_e32 v13, v10, v7 ; 101A0F0A V_MUL_F32_e32 v12, v12, v11 ; 1018170C V_MUL_F32_e32 v14, v12, v5 ; 101C0B0C V_SUB_F32_e32 v13, v14, v13 ; 081A1B0E V_MUL_F32_e32 v14, v12, v6 ; 101C0D0C V_MUL_F32_e32 v9, v9, v11 ; 10121709 V_MUL_F32_e32 v11, v9, v7 ; 10160F09 V_SUB_F32_e32 v11, v11, v14 ; 08161D0B V_MUL_F32_e32 v14, v11, v11 ; 101C170B V_MAD_F32 v14, v13, v13, v14, 0, 0, 0, 0 ; D282000E 043A1B0D V_MUL_F32_e32 v15, v9, v5 ; 101E0B09 V_MUL_F32_e32 v16, v10, v6 ; 10200D0A V_SUB_F32_e32 v15, v16, v15 ; 081E1F10 V_MAD_F32 v14, v15, v15, v14, 0, 0, 0, 0 ; D282000E 043A1F0F V_RSQ_LEGACY_F32_e32 v14, v14 ; 7E1C5B0E V_MUL_F32_e32 v13, v13, v14 ; 101A1D0D V_MUL_F32_e32 v16, v1, v1 ; 10200301 V_MAD_F32 v16, v2, v2, v16, 0, 0, 0, 0 ; D2820010 04420502 V_MAD_F32 v1, v3, v3, v16, 0, 0, 0, 0 ; D2820001 04420703 V_RSQ_LEGACY_F32_e32 v2, v1 ; 7E045B01 V_MUL_F32_e32 v2, v2, v1 ; 10040302 V_XOR_B32_e32 v1, -2147483648, v1 ; 3A0202FF 80000000 V_CMP_GT_F32_e64 s[2:3], 0, v1, 0, 0, 0, 0 ; D0080002 02020280 V_CNDMASK_B32_e64 v1, 0.000000e+00, v2, s[2:3], 0, 0, 0, 0 ; D2000001 000A0480 V_MUL_F32_e32 v2, v13, v1 ; 1004030D V_MUL_F32_e32 v3, v11, v14 ; 10061D0B V_MUL_F32_e32 v3, v3, v1 ; 10060303 S_LOAD_DWORDX4 s[4:7], s[0:1], 0 ; C0820100 S_WAITCNT lgkmcnt(0) ; BF8C007F S_BUFFER_LOAD_DWORD s10, s[4:7], 1 ; C2050501 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v4, s10, v3 ; 1008060A S_BUFFER_LOAD_DWORD s11, s[4:7], 5 ; C2058505 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v4, s11, v2, v4, 0, 0, 0, 0 ; D2820004 0412040B V_MUL_F32_e32 v11, v15, v14 ; 10161D0F V_MUL_F32_e32 v11, v11, v1 ; 1016030B S_BUFFER_LOAD_DWORD s12, s[4:7], 9 ; C2060509 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v4, s12, v11, v4, 0, 0, 0, 0 ; D2820004 0412160C V_MUL_F32_e32 v9, v9, v1 ; 10120309 V_MUL_F32_e32 v10, v10, v1 ; 1014030A V_MUL_F32_e32 v13, s10, v10 ; 101A140A V_MAD_F32 v13, s11, v9, v13, 0, 0, 0, 0 ; D282000D 0436120B V_MUL_F32_e32 v1, v12, v1 ; 1002030C V_MAD_F32 v12, s12, v1, v13, 0, 0, 0, 0 ; D282000C 0436020C S_LOAD_DWORDX4 s[16:19], s[8:9], 8 ; C0880908 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[13:16], s[16:19][v0] + 0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80040D00 S_LOAD_DWORDX4 s[0:3], s[0:1], 4 ; C0800104 S_WAITCNT vmcnt(0) lgkmcnt(0) ; BF8C0070 S_BUFFER_LOAD_DWORD s13, s[0:3], 81 ; C2068151 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v17, s13 ; 7E22020D V_SUB_F32_e64 v17, v14, v17, 0, 0, 0, 0 ; D2080011 0202230E S_BUFFER_LOAD_DWORD s13, s[0:3], 80 ; C2068150 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v18, s13 ; 7E24020D V_SUB_F32_e64 v18, v13, v18, 0, 0, 0, 0 ; D2080012 0202250D V_MUL_F32_e32 v18, v18, v18 ; 10242512 V_MAD_F32 v17, v17, v17, v18, 0, 0, 0, 0 ; D2820011 044A2311 S_BUFFER_LOAD_DWORD s13, s[0:3], 82 ; C2068152 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v18, s13 ; 7E24020D V_SUB_F32_e64 v18, v15, v18, 0, 0, 0, 0 ; D2080012 0202250F V_MAD_F32 v17, v18, v18, v17, 0, 0, 0, 0 ; D2820011 04462512 V_RSQ_LEGACY_F32_e32 v18, v17 ; 7E245B11 V_MUL_F32_e32 v18, v18, v17 ; 10242312 V_XOR_B32_e32 v17, -2147483648, v17 ; 3A2222FF 80000000 V_CMP_GT_F32_e64 s[14:15], 0, v17, 0, 0, 0, 0 ; D008000E 02022280 V_CNDMASK_B32_e64 v17, 0.000000e+00, v18, s[14:15], 0, 0, 0, 0 ; D2000011 003A2480 S_BUFFER_LOAD_DWORD s13, s[4:7], 16 ; C2068510 V_MOV_B32_e32 v18, -8.000000e-01 ; 7E2402FF BF4CCCCD S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v17, s13, v18, v17, 0, 0, 0, 0 ; D2820011 0446240D V_MOV_B32_e32 v19, s13 ; 7E26020D V_MAD_F32 v18, s13, v18, v19, 0, 0, 0, 0 ; D2820012 044E240D V_RCP_F32_e32 v18, v18 ; 7E245512 V_MUL_F32_e32 v17, v17, v18 ; 10222511 V_ADD_F32_e64 v17, 0, v17, 0, 1, 0, 0 ; D2060811 02022280 V_ADD_F32_e32 v18, v17, v17 ; 06242311 V_SUB_F32_e32 v18, 3.000000e+00, v18 ; 082424FF 40400000 V_MUL_F32_e32 v18, v17, v18 ; 10242511 V_MUL_F32_e32 v17, v17, v18 ; 10222511 V_SUB_F32_e32 v17, 1.000000e+00, v17 ; 082222F2 S_LOAD_DWORDX4 s[16:19], s[8:9], 0 ; C0880900 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[18:21], s[16:19][v0] + 0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80041200 S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v22, v18, v17 ; 102C2312 V_MUL_F32_e32 v12, v12, v22 ; 10182D0C V_MUL_F32_e32 v23, v19, v17 ; 102E2313 V_MUL_F32_e32 v24, s10, v5 ; 10300A0A V_MAD_F32 v24, s11, v6, v24, 0, 0, 0, 0 ; D2820018 04620C0B V_MAD_F32 v24, s12, v7, v24, 0, 0, 0, 0 ; D2820018 04620E0C V_MAD_F32 v12, v24, v23, v12, 0, 0, 0, 0 ; D282000C 04322F18 V_MUL_F32_e32 v17, v20, v17 ; 10222314 V_MAD_F32 v4, v4, v17, v12, 0, 0, 0, 0 ; D2820004 04322304 V_MUL_F32_e32 v12, s10, v13 ; 10181A0A V_MAD_F32 v12, s11, v14, v12, 0, 0, 0, 0 ; D282000C 04321C0B V_MAD_F32 v12, s12, v15, v12, 0, 0, 0, 0 ; D282000C 04321E0C S_BUFFER_LOAD_DWORD s10, s[4:7], 13 ; C205050D S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v12, s10, v12 ; 0618180A V_ADD_F32_e32 v4, v4, v12 ; 06081904 V_CMP_U_F32_e64 s[10:11], v19, v19, 0, 0, 0, 0 ; D010000A 02022713 V_CMP_LE_F32_e64 s[12:13], v19, 0.000000e+00, 0, 0, 0, 0 ; D006000C 02010113 S_OR_B64 s[10:11], s[12:13], s[10:11] ; 888A0A0C V_CNDMASK_B32_e64 v12, v19, 0.000000e+00, s[10:11], 0, 0, 0, 0 ; D200000C 00290113 V_MUL_F32_e32 v18, 0.000000e+00, v12 ; 10241880 V_MOV_B32_e32 v19, 1.000000e-01 ; 7E2602FF 3DCCCCCD V_MAD_F32 v4, v18, v19, v4, 0, 0, 0, 0 ; D2820004 04122712 S_BUFFER_LOAD_DWORD s10, s[4:7], 0 ; C2050500 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v18, s10, v3 ; 1024060A S_BUFFER_LOAD_DWORD s11, s[4:7], 4 ; C2058504 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v18, s11, v2, v18, 0, 0, 0, 0 ; D2820012 044A040B S_BUFFER_LOAD_DWORD s12, s[4:7], 8 ; C2060508 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v18, s12, v11, v18, 0, 0, 0, 0 ; D2820012 044A160C V_MUL_F32_e32 v20, s10, v10 ; 1028140A V_MAD_F32 v20, s11, v9, v20, 0, 0, 0, 0 ; D2820014 0452120B V_MAD_F32 v20, s12, v1, v20, 0, 0, 0, 0 ; D2820014 0452020C V_MUL_F32_e32 v20, v20, v22 ; 10282D14 V_MUL_F32_e32 v21, s10, v5 ; 102A0A0A V_MAD_F32 v21, s11, v6, v21, 0, 0, 0, 0 ; D2820015 04560C0B V_MAD_F32 v21, s12, v7, v21, 0, 0, 0, 0 ; D2820015 04560E0C V_MAD_F32 v20, v21, v23, v20, 0, 0, 0, 0 ; D2820014 04522F15 V_MAD_F32 v18, v18, v17, v20, 0, 0, 0, 0 ; D2820012 04522312 V_MUL_F32_e32 v20, s10, v13 ; 10281A0A V_MAD_F32 v20, s11, v14, v20, 0, 0, 0, 0 ; D2820014 04521C0B V_MAD_F32 v20, s12, v15, v20, 0, 0, 0, 0 ; D2820014 04521E0C S_BUFFER_LOAD_DWORD s10, s[4:7], 12 ; C205050C S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v20, s10, v20 ; 0628280A V_ADD_F32_e32 v18, v18, v20 ; 06242912 V_ADD_F32_e32 v20, v13, v15 ; 06281F0D V_MUL_F32_e32 v20, 1042479491, v20 ; 102828FF 3E22F983 V_COS_F32_e32 v20, v20 ; 7E286D14 S_BUFFER_LOAD_DWORD s10, s[0:3], 92 ; C205015C S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v21, s10, v13 ; 062A1A0A V_ADD_F32_e32 v21, v21, v14 ; 062A1D15 V_ADD_F32_e32 v21, v21, v15 ; 062A1F15 V_MUL_F32_e32 v21, 1042479491, v21 ; 102A2AFF 3E22F983 V_COS_F32_e32 v21, v21 ; 7E2A6D15 V_MUL_F32_e32 v20, v21, v20 ; 10282915 V_MUL_F32_e32 v20, v20, v12 ; 10281914 V_MAD_F32 v18, v20, v19, v18, 0, 0, 0, 0 ; D2820012 044A2714 S_BUFFER_LOAD_DWORD s10, s[0:3], 35 ; C2050123 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v20, s10, v18 ; 1028240A S_BUFFER_LOAD_DWORD s10, s[0:3], 39 ; C2050127 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v20, s10, v4, v20, 0, 0, 0, 0 ; D2820014 0452080A S_BUFFER_LOAD_DWORD s10, s[4:7], 2 ; C2050502 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v24, s10, v3 ; 1030060A S_BUFFER_LOAD_DWORD s11, s[4:7], 6 ; C2058506 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v24, s11, v2, v24, 0, 0, 0, 0 ; D2820018 0462040B S_BUFFER_LOAD_DWORD s12, s[4:7], 10 ; C206050A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v24, s12, v11, v24, 0, 0, 0, 0 ; D2820018 0462160C V_MUL_F32_e32 v25, s10, v10 ; 1032140A V_MAD_F32 v25, s11, v9, v25, 0, 0, 0, 0 ; D2820019 0466120B V_MAD_F32 v25, s12, v1, v25, 0, 0, 0, 0 ; D2820019 0466020C V_MUL_F32_e32 v25, v25, v22 ; 10322D19 V_MUL_F32_e32 v26, s10, v5 ; 10340A0A V_MAD_F32 v26, s11, v6, v26, 0, 0, 0, 0 ; D282001A 046A0C0B V_MAD_F32 v26, s12, v7, v26, 0, 0, 0, 0 ; D282001A 046A0E0C V_MAD_F32 v25, v26, v23, v25, 0, 0, 0, 0 ; D2820019 04662F1A V_MAD_F32 v24, v24, v17, v25, 0, 0, 0, 0 ; D2820018 04662318 V_MUL_F32_e32 v25, s10, v13 ; 10321A0A V_MAD_F32 v25, s11, v14, v25, 0, 0, 0, 0 ; D2820019 04661C0B V_MAD_F32 v25, s12, v15, v25, 0, 0, 0, 0 ; D2820019 04661E0C S_BUFFER_LOAD_DWORD s10, s[4:7], 14 ; C205050E S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v25, s10, v25 ; 0632320A V_ADD_F32_e32 v24, v24, v25 ; 06303318 V_ADD_F32_e32 v25, v14, v15 ; 06321F0E V_MUL_F32_e32 v25, 1042479491, v25 ; 103232FF 3E22F983 V_COS_F32_e32 v25, v25 ; 7E326D19 V_MUL_F32_e32 v21, v21, v25 ; 102A3315 V_MUL_F32_e32 v12, v21, v12 ; 10181915 V_MAD_F32 v12, v12, v19, v24, 0, 0, 0, 0 ; D282000C 0462270C S_BUFFER_LOAD_DWORD s10, s[0:3], 43 ; C205012B S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v19, s10, v12, v20, 0, 0, 0, 0 ; D2820013 0452180A S_BUFFER_LOAD_DWORD s10, s[0:3], 34 ; C2050122 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v20, s10, v18 ; 1028240A S_BUFFER_LOAD_DWORD s10, s[0:3], 38 ; C2050126 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v20, s10, v4, v20, 0, 0, 0, 0 ; D2820014 0452080A S_BUFFER_LOAD_DWORD s10, s[0:3], 42 ; C205012A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v20, s10, v12, v20, 0, 0, 0, 0 ; D2820014 0452180A S_LOAD_DWORDX4 s[8:11], s[8:9], 4 ; C0840904 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[24:27], s[8:11][v0] + 0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80021800 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 32, 0, 0, 0, v24, v25, v20, v19 ; F800020F 13141918 S_BUFFER_LOAD_DWORD s8, s[4:7], 3 ; C2040503 S_WAITCNT expcnt(0) lgkmcnt(0) ; BF8C000F V_MUL_F32_e32 v0, s8, v3 ; 10000608 S_BUFFER_LOAD_DWORD s9, s[4:7], 7 ; C2048507 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v0, s9, v2, v0, 0, 0, 0, 0 ; D2820000 04020409 S_BUFFER_LOAD_DWORD s10, s[4:7], 11 ; C205050B S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v0, s10, v11, v0, 0, 0, 0, 0 ; D2820000 0402160A V_MUL_F32_e32 v2, s8, v10 ; 10041408 V_MAD_F32 v2, s9, v9, v2, 0, 0, 0, 0 ; D2820002 040A1209 V_MAD_F32 v1, s10, v1, v2, 0, 0, 0, 0 ; D2820001 040A020A V_MUL_F32_e32 v1, v1, v22 ; 10022D01 V_MUL_F32_e32 v2, s8, v5 ; 10040A08 V_MAD_F32 v2, s9, v6, v2, 0, 0, 0, 0 ; D2820002 040A0C09 V_MAD_F32 v2, s10, v7, v2, 0, 0, 0, 0 ; D2820002 040A0E0A V_MAD_F32 v1, v2, v23, v1, 0, 0, 0, 0 ; D2820001 04062F02 V_MAD_F32 v0, v0, v17, v1, 0, 0, 0, 0 ; D2820000 04062300 V_MUL_F32_e32 v1, s8, v13 ; 10021A08 V_MAD_F32 v1, s9, v14, v1, 0, 0, 0, 0 ; D2820001 04061C09 V_MAD_F32 v1, s10, v15, v1, 0, 0, 0, 0 ; D2820001 04061E0A S_BUFFER_LOAD_DWORD s4, s[4:7], 15 ; C202050F S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v1, s4, v1 ; 06020204 V_ADD_F32_e32 v0, v0, v1 ; 06000300 S_BUFFER_LOAD_DWORD s4, s[0:3], 47 ; C202012F S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v1, s4, v0, v19, 0, 0, 0, 0 ; D2820001 044E0004 S_BUFFER_LOAD_DWORD s4, s[0:3], 46 ; C202012E S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v2, s4, v0, v20, 0, 0, 0, 0 ; D2820002 04520004 S_BUFFER_LOAD_DWORD s4, s[0:3], 33 ; C2020121 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v3, s4, v18 ; 10062404 S_BUFFER_LOAD_DWORD s4, s[0:3], 37 ; C2020125 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v3, s4, v4, v3, 0, 0, 0, 0 ; D2820003 040E0804 S_BUFFER_LOAD_DWORD s4, s[0:3], 41 ; C2020129 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v3, s4, v12, v3, 0, 0, 0, 0 ; D2820003 040E1804 S_BUFFER_LOAD_DWORD s4, s[0:3], 45 ; C202012D S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v3, s4, v0, v3, 0, 0, 0, 0 ; D2820003 040E0004 S_BUFFER_LOAD_DWORD s4, s[0:3], 32 ; C2020120 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v5, s4, v18 ; 100A2404 S_BUFFER_LOAD_DWORD s4, s[0:3], 36 ; C2020124 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v4, s4, v4, v5, 0, 0, 0, 0 ; D2820004 04160804 S_BUFFER_LOAD_DWORD s4, s[0:3], 40 ; C2020128 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v4, s4, v12, v4, 0, 0, 0, 0 ; D2820004 04121804 S_BUFFER_LOAD_DWORD s0, s[0:3], 44 ; C200012C S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v0, s0, v0, v4, 0, 0, 0, 0 ; D2820000 04120000 EXP 15, 12, 0, 1, 0, v0, v3, v2, v1 ; F80008CF 01020300 S_ENDPGM ; BF810000 VERT DCL IN[0] DCL IN[1] DCL IN[2] DCL IN[3] DCL IN[4] DCL OUT[0], POSITION DCL OUT[1], GENERIC[20] DCL CONST[0..4] DCL CONST[1][0..96] DCL TEMP[0..5], LOCAL DCL ADDR[0] IMM[0] FLT32 { 0.0000, 0.8000, 1.0000, 3.0000} IMM[1] UINT32 {0, 320, 368, 176} IMM[2] INT32 {20, 23, 11, 10} IMM[3] FLT32 { 2.0000, 0.1000, 0.0000, 0.0000} IMM[4] UINT32 {160, 144, 128, 0} IMM[5] INT32 {9, 8, 0, 0} 0: DP3 TEMP[0].x, IN[4].xyzz, IN[4].xyzz 1: RSQ TEMP[1].x, TEMP[0].xxxx 2: MUL TEMP[1].x, TEMP[1].xxxx, TEMP[0].xxxx 3: CMP TEMP[0].x, -TEMP[0].xxxx, TEMP[1].xxxx, IMM[0].xxxx 4: MUL TEMP[1].xyz, IN[3].zxyy, IN[4].yzxx 5: MAD TEMP[1].xyz, IN[3].yzxx, IN[4].zxyy, -TEMP[1].xyzz 6: DP3 TEMP[2].x, TEMP[1].xyzz, TEMP[1].xyzz 7: RSQ TEMP[2].x, TEMP[2].xxxx 8: MUL TEMP[1].xyz, TEMP[1].xyzz, TEMP[2].xxxx 9: MUL TEMP[2].xyz, TEMP[1].zxyy, IN[3].yzxx 10: MAD TEMP[2].xyz, TEMP[1].yzxx, IN[3].zxyy, -TEMP[2].xyzz 11: MUL TEMP[1].xyz, TEMP[1].xyzz, TEMP[0].xxxx 12: DP3 TEMP[3].x, TEMP[2].xyzz, TEMP[2].xyzz 13: RSQ TEMP[3].x, TEMP[3].xxxx 14: MUL TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xxxx 15: MUL TEMP[0].xyz, TEMP[2].xyzz, TEMP[0].xxxx 16: UARL ADDR[0].x, IMM[2].xxxx 17: MOV TEMP[2].xyz, CONST[1][ADDR[0].x].xyzz 18: ADD TEMP[2].xyz, IN[2].xyzz, -TEMP[2].xyzz 19: MUL TEMP[3].x, CONST[4].xxxx, IMM[0].yyyy 20: DP3 TEMP[2].x, TEMP[2].xyzz, TEMP[2].xyzz 21: RSQ TEMP[4].x, TEMP[2].xxxx 22: MUL TEMP[4].x, TEMP[4].xxxx, TEMP[2].xxxx 23: CMP TEMP[4].x, -TEMP[2].xxxx, TEMP[4].xxxx, IMM[0].xxxx 24: ADD TEMP[2].x, TEMP[4].xxxx, -TEMP[3].xxxx 25: ADD TEMP[3].x, CONST[4].xxxx, -TEMP[3].xxxx 26: RCP TEMP[3].x, TEMP[3].xxxx 27: MUL_SAT TEMP[2].x, TEMP[2].xxxx, TEMP[3].xxxx 28: MUL TEMP[3].x, IMM[3].xxxx, TEMP[2].xxxx 29: ADD TEMP[3].x, IMM[0].wwww, -TEMP[3].xxxx 30: MUL TEMP[3].x, TEMP[2].xxxx, TEMP[3].xxxx 31: MUL TEMP[3].x, TEMP[2].xxxx, TEMP[3].xxxx 32: ADD TEMP[3].x, IMM[0].zzzz, -TEMP[3].xxxx 33: MUL TEMP[2].xyz, IN[0].xyzz, TEMP[3].xxxx 34: MUL TEMP[3], CONST[0], TEMP[0].xxxx 35: MAD TEMP[3], CONST[1], TEMP[0].yyyy, TEMP[3] 36: MAD TEMP[0], CONST[2], TEMP[0].zzzz, TEMP[3] 37: MUL TEMP[3], CONST[0], IN[3].xxxx 38: MAD TEMP[3], CONST[1], IN[3].yyyy, TEMP[3] 39: MAD TEMP[3], CONST[2], IN[3].zzzz, TEMP[3] 40: MUL TEMP[4], CONST[0], TEMP[1].xxxx 41: MAD TEMP[4], CONST[1], TEMP[1].yyyy, TEMP[4] 42: MAD TEMP[1], CONST[2], TEMP[1].zzzz, TEMP[4] 43: MUL TEMP[1], TEMP[1], TEMP[2].xxxx 44: MAD TEMP[1], TEMP[3], TEMP[2].yyyy, TEMP[1] 45: MAD TEMP[0], TEMP[0], TEMP[2].zzzz, TEMP[1] 46: MUL TEMP[1], CONST[0], IN[2].xxxx 47: MAD TEMP[1], CONST[1], IN[2].yyyy, TEMP[1] 48: MAD TEMP[1], CONST[2], IN[2].zzzz, TEMP[1] 49: ADD TEMP[1], TEMP[1], CONST[3] 50: ADD TEMP[0], TEMP[0], TEMP[1] 51: UARL ADDR[0].x, IMM[2].yyyy 52: MOV TEMP[2].x, CONST[1][ADDR[0].x].xxxx 53: ADD TEMP[2].x, TEMP[2].xxxx, IN[2].xxxx 54: ADD TEMP[2].x, TEMP[2].xxxx, IN[2].yyyy 55: ADD TEMP[2].x, TEMP[2].xxxx, IN[2].zzzz 56: COS TEMP[2].x, TEMP[2].xxxx 57: MOV TEMP[3].y, IMM[0].xxxx 58: ADD TEMP[4].x, IN[2].xxxx, IN[2].zzzz 59: COS TEMP[4].x, TEMP[4].xxxx 60: MUL TEMP[3].x, TEMP[2].xxxx, TEMP[4].xxxx 61: ADD TEMP[4].x, IN[2].yyyy, IN[2].zzzz 62: COS TEMP[4].x, TEMP[4].xxxx 63: MUL TEMP[2].x, TEMP[2].xxxx, TEMP[4].xxxx 64: MOV TEMP[3].z, TEMP[2].xxxx 65: MAX TEMP[2].x, IMM[0].xxxx, IN[0].yyyy 66: MUL TEMP[2].xyz, TEMP[3].xyzz, TEMP[2].xxxx 67: MAD TEMP[1].xyz, TEMP[2].xyzz, IMM[3].yyyy, TEMP[0].xyzz 68: UARL ADDR[0].x, IMM[2].zzzz 69: MOV TEMP[2], CONST[1][ADDR[0].x] 70: UARL ADDR[0].x, IMM[2].wwww 71: MOV TEMP[3], CONST[1][ADDR[0].x] 72: UARL ADDR[0].x, IMM[5].xxxx 73: MOV TEMP[4], CONST[1][ADDR[0].x] 74: UARL ADDR[0].x, IMM[5].yyyy 75: MOV TEMP[5], CONST[1][ADDR[0].x] 76: MUL TEMP[5], TEMP[5], TEMP[1].xxxx 77: MAD TEMP[4], TEMP[4], TEMP[1].yyyy, TEMP[5] 78: MAD TEMP[1], TEMP[3], TEMP[1].zzzz, TEMP[4] 79: MAD TEMP[0], TEMP[2], TEMP[0].wwww, TEMP[1] 80: MOV TEMP[1].xy, IN[1].xyxx 81: MOV OUT[1], TEMP[1] 82: MOV OUT[0], TEMP[0] 83: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0 %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0 %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0) %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4) %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8) %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12) %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16) %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20) %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24) %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28) %20 = call float @llvm.SI.load.const(<16 x i8> %11, i32 32) %21 = call float @llvm.SI.load.const(<16 x i8> %11, i32 36) %22 = call float @llvm.SI.load.const(<16 x i8> %11, i32 40) %23 = call float @llvm.SI.load.const(<16 x i8> %11, i32 44) %24 = call float @llvm.SI.load.const(<16 x i8> %11, i32 48) %25 = call float @llvm.SI.load.const(<16 x i8> %11, i32 52) %26 = call float @llvm.SI.load.const(<16 x i8> %11, i32 56) %27 = call float @llvm.SI.load.const(<16 x i8> %11, i32 60) %28 = call float @llvm.SI.load.const(<16 x i8> %11, i32 64) %29 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 1 %30 = load <16 x i8> addrspace(2)* %29, !tbaa !0 %31 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 0 %32 = load <16 x i8> addrspace(2)* %31, !tbaa !0 %33 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %32, i32 0, i32 %6) %34 = extractelement <4 x float> %33, i32 0 %35 = extractelement <4 x float> %33, i32 1 %36 = extractelement <4 x float> %33, i32 2 %37 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 1 %38 = load <16 x i8> addrspace(2)* %37, !tbaa !0 %39 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %38, i32 0, i32 %6) %40 = extractelement <4 x float> %39, i32 0 %41 = extractelement <4 x float> %39, i32 1 %42 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 2 %43 = load <16 x i8> addrspace(2)* %42, !tbaa !0 %44 = add i32 %9, %5 %45 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %43, i32 0, i32 %44) %46 = extractelement <4 x float> %45, i32 0 %47 = extractelement <4 x float> %45, i32 1 %48 = extractelement <4 x float> %45, i32 2 %49 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 3 %50 = load <16 x i8> addrspace(2)* %49, !tbaa !0 %51 = add i32 %9, %5 %52 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %50, i32 0, i32 %51) %53 = extractelement <4 x float> %52, i32 0 %54 = extractelement <4 x float> %52, i32 1 %55 = extractelement <4 x float> %52, i32 2 %56 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 4 %57 = load <16 x i8> addrspace(2)* %56, !tbaa !0 %58 = add i32 %9, %5 %59 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %57, i32 0, i32 %58) %60 = extractelement <4 x float> %59, i32 0 %61 = extractelement <4 x float> %59, i32 1 %62 = extractelement <4 x float> %59, i32 2 %63 = fmul float %60, %60 %64 = fmul float %61, %61 %65 = fadd float %64, %63 %66 = fmul float %62, %62 %67 = fadd float %65, %66 %68 = call float @llvm.AMDGPU.rsq(float %67) %69 = fmul float %68, %67 %70 = fsub float -0.000000e+00, %67 %71 = call float @llvm.AMDGPU.cndlt(float %70, float %69, float 0.000000e+00) %72 = fmul float %55, %61 %73 = fmul float %53, %62 %74 = fmul float %54, %60 %75 = fsub float -0.000000e+00, %72 %76 = fmul float %54, %62 %77 = fadd float %76, %75 %78 = fsub float -0.000000e+00, %73 %79 = fmul float %55, %60 %80 = fadd float %79, %78 %81 = fsub float -0.000000e+00, %74 %82 = fmul float %53, %61 %83 = fadd float %82, %81 %84 = fmul float %77, %77 %85 = fmul float %80, %80 %86 = fadd float %85, %84 %87 = fmul float %83, %83 %88 = fadd float %86, %87 %89 = call float @llvm.AMDGPU.rsq(float %88) %90 = fmul float %77, %89 %91 = fmul float %80, %89 %92 = fmul float %83, %89 %93 = fmul float %92, %54 %94 = fmul float %90, %55 %95 = fmul float %91, %53 %96 = fsub float -0.000000e+00, %93 %97 = fmul float %91, %55 %98 = fadd float %97, %96 %99 = fsub float -0.000000e+00, %94 %100 = fmul float %92, %53 %101 = fadd float %100, %99 %102 = fsub float -0.000000e+00, %95 %103 = fmul float %90, %54 %104 = fadd float %103, %102 %105 = fmul float %90, %71 %106 = fmul float %91, %71 %107 = fmul float %92, %71 %108 = fmul float %98, %98 %109 = fmul float %101, %101 %110 = fadd float %109, %108 %111 = fmul float %104, %104 %112 = fadd float %110, %111 %113 = call float @llvm.AMDGPU.rsq(float %112) %114 = fmul float %98, %113 %115 = fmul float %101, %113 %116 = fmul float %104, %113 %117 = fmul float %114, %71 %118 = fmul float %115, %71 %119 = fmul float %116, %71 %120 = shl i32 20, 4 %121 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %120) %122 = shl i32 20, 4 %123 = add i32 %122, 4 %124 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %123) %125 = shl i32 20, 4 %126 = add i32 %125, 8 %127 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %126) %128 = fsub float -0.000000e+00, %121 %129 = fadd float %46, %128 %130 = fsub float -0.000000e+00, %124 %131 = fadd float %47, %130 %132 = fsub float -0.000000e+00, %127 %133 = fadd float %48, %132 %134 = fmul float %28, 0x3FE99999A0000000 %135 = fmul float %129, %129 %136 = fmul float %131, %131 %137 = fadd float %136, %135 %138 = fmul float %133, %133 %139 = fadd float %137, %138 %140 = call float @llvm.AMDGPU.rsq(float %139) %141 = fmul float %140, %139 %142 = fsub float -0.000000e+00, %139 %143 = call float @llvm.AMDGPU.cndlt(float %142, float %141, float 0.000000e+00) %144 = fsub float -0.000000e+00, %134 %145 = fadd float %143, %144 %146 = fsub float -0.000000e+00, %134 %147 = fadd float %28, %146 %148 = fdiv float 1.000000e+00, %147 %149 = fmul float %145, %148 %150 = call float @llvm.AMDIL.clamp.(float %149, float 0.000000e+00, float 1.000000e+00) %151 = fmul float 2.000000e+00, %150 %152 = fsub float -0.000000e+00, %151 %153 = fadd float 3.000000e+00, %152 %154 = fmul float %150, %153 %155 = fmul float %150, %154 %156 = fsub float -0.000000e+00, %155 %157 = fadd float 1.000000e+00, %156 %158 = fmul float %34, %157 %159 = fmul float %35, %157 %160 = fmul float %36, %157 %161 = fmul float %12, %117 %162 = fmul float %13, %117 %163 = fmul float %14, %117 %164 = fmul float %15, %117 %165 = fmul float %16, %118 %166 = fadd float %165, %161 %167 = fmul float %17, %118 %168 = fadd float %167, %162 %169 = fmul float %18, %118 %170 = fadd float %169, %163 %171 = fmul float %19, %118 %172 = fadd float %171, %164 %173 = fmul float %20, %119 %174 = fadd float %173, %166 %175 = fmul float %21, %119 %176 = fadd float %175, %168 %177 = fmul float %22, %119 %178 = fadd float %177, %170 %179 = fmul float %23, %119 %180 = fadd float %179, %172 %181 = fmul float %12, %53 %182 = fmul float %13, %53 %183 = fmul float %14, %53 %184 = fmul float %15, %53 %185 = fmul float %16, %54 %186 = fadd float %185, %181 %187 = fmul float %17, %54 %188 = fadd float %187, %182 %189 = fmul float %18, %54 %190 = fadd float %189, %183 %191 = fmul float %19, %54 %192 = fadd float %191, %184 %193 = fmul float %20, %55 %194 = fadd float %193, %186 %195 = fmul float %21, %55 %196 = fadd float %195, %188 %197 = fmul float %22, %55 %198 = fadd float %197, %190 %199 = fmul float %23, %55 %200 = fadd float %199, %192 %201 = fmul float %12, %105 %202 = fmul float %13, %105 %203 = fmul float %14, %105 %204 = fmul float %15, %105 %205 = fmul float %16, %106 %206 = fadd float %205, %201 %207 = fmul float %17, %106 %208 = fadd float %207, %202 %209 = fmul float %18, %106 %210 = fadd float %209, %203 %211 = fmul float %19, %106 %212 = fadd float %211, %204 %213 = fmul float %20, %107 %214 = fadd float %213, %206 %215 = fmul float %21, %107 %216 = fadd float %215, %208 %217 = fmul float %22, %107 %218 = fadd float %217, %210 %219 = fmul float %23, %107 %220 = fadd float %219, %212 %221 = fmul float %214, %158 %222 = fmul float %216, %158 %223 = fmul float %218, %158 %224 = fmul float %220, %158 %225 = fmul float %194, %159 %226 = fadd float %225, %221 %227 = fmul float %196, %159 %228 = fadd float %227, %222 %229 = fmul float %198, %159 %230 = fadd float %229, %223 %231 = fmul float %200, %159 %232 = fadd float %231, %224 %233 = fmul float %174, %160 %234 = fadd float %233, %226 %235 = fmul float %176, %160 %236 = fadd float %235, %228 %237 = fmul float %178, %160 %238 = fadd float %237, %230 %239 = fmul float %180, %160 %240 = fadd float %239, %232 %241 = fmul float %12, %46 %242 = fmul float %13, %46 %243 = fmul float %14, %46 %244 = fmul float %15, %46 %245 = fmul float %16, %47 %246 = fadd float %245, %241 %247 = fmul float %17, %47 %248 = fadd float %247, %242 %249 = fmul float %18, %47 %250 = fadd float %249, %243 %251 = fmul float %19, %47 %252 = fadd float %251, %244 %253 = fmul float %20, %48 %254 = fadd float %253, %246 %255 = fmul float %21, %48 %256 = fadd float %255, %248 %257 = fmul float %22, %48 %258 = fadd float %257, %250 %259 = fmul float %23, %48 %260 = fadd float %259, %252 %261 = fadd float %254, %24 %262 = fadd float %256, %25 %263 = fadd float %258, %26 %264 = fadd float %260, %27 %265 = fadd float %234, %261 %266 = fadd float %236, %262 %267 = fadd float %238, %263 %268 = fadd float %240, %264 %269 = shl i32 23, 4 %270 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %269) %271 = fadd float %270, %46 %272 = fadd float %271, %47 %273 = fadd float %272, %48 %274 = call float @llvm.cos.f32(float %273) %275 = fadd float %46, %48 %276 = call float @llvm.cos.f32(float %275) %277 = fmul float %274, %276 %278 = fadd float %47, %48 %279 = call float @llvm.cos.f32(float %278) %280 = fmul float %274, %279 %281 = fcmp uge float 0.000000e+00, %35 %282 = select i1 %281, float 0.000000e+00, float %35 %283 = fmul float %277, %282 %284 = fmul float 0.000000e+00, %282 %285 = fmul float %280, %282 %286 = fmul float %283, 0x3FB99999A0000000 %287 = fadd float %286, %265 %288 = fmul float %284, 0x3FB99999A0000000 %289 = fadd float %288, %266 %290 = fmul float %285, 0x3FB99999A0000000 %291 = fadd float %290, %267 %292 = shl i32 11, 4 %293 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %292) %294 = shl i32 11, 4 %295 = add i32 %294, 4 %296 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %295) %297 = shl i32 11, 4 %298 = add i32 %297, 8 %299 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %298) %300 = shl i32 11, 4 %301 = add i32 %300, 12 %302 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %301) %303 = shl i32 10, 4 %304 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %303) %305 = shl i32 10, 4 %306 = add i32 %305, 4 %307 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %306) %308 = shl i32 10, 4 %309 = add i32 %308, 8 %310 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %309) %311 = shl i32 10, 4 %312 = add i32 %311, 12 %313 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %312) %314 = shl i32 9, 4 %315 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %314) %316 = shl i32 9, 4 %317 = add i32 %316, 4 %318 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %317) %319 = shl i32 9, 4 %320 = add i32 %319, 8 %321 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %320) %322 = shl i32 9, 4 %323 = add i32 %322, 12 %324 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %323) %325 = shl i32 8, 4 %326 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %325) %327 = shl i32 8, 4 %328 = add i32 %327, 4 %329 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %328) %330 = shl i32 8, 4 %331 = add i32 %330, 8 %332 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %331) %333 = shl i32 8, 4 %334 = add i32 %333, 12 %335 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %334) %336 = fmul float %326, %287 %337 = fmul float %329, %287 %338 = fmul float %332, %287 %339 = fmul float %335, %287 %340 = fmul float %315, %289 %341 = fadd float %340, %336 %342 = fmul float %318, %289 %343 = fadd float %342, %337 %344 = fmul float %321, %289 %345 = fadd float %344, %338 %346 = fmul float %324, %289 %347 = fadd float %346, %339 %348 = fmul float %304, %291 %349 = fadd float %348, %341 %350 = fmul float %307, %291 %351 = fadd float %350, %343 %352 = fmul float %310, %291 %353 = fadd float %352, %345 %354 = fmul float %313, %291 %355 = fadd float %354, %347 %356 = fmul float %293, %268 %357 = fadd float %356, %349 %358 = fmul float %296, %268 %359 = fadd float %358, %351 %360 = fmul float %299, %268 %361 = fadd float %360, %353 %362 = fmul float %302, %268 %363 = fadd float %362, %355 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %40, float %41, float %353, float %355) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %357, float %359, float %361, float %363) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 ; Function Attrs: readnone declare float @llvm.AMDGPU.rsq(float) #2 ; Function Attrs: readnone declare float @llvm.AMDGPU.cndlt(float, float, float) #2 ; Function Attrs: readnone declare float @llvm.AMDIL.clamp.(float, float, float) #2 ; Function Attrs: nounwind readonly declare float @llvm.cos.f32(float) #3 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } attributes #3 = { nounwind readonly } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: V_ADD_I32_e32 v1, s10, v3 ; 4A02060A S_LOAD_DWORDX4 s[4:7], s[8:9], 16 ; C0820910 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[2:5], s[4:7][v1] + 0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80010201 S_LOAD_DWORDX4 s[4:7], s[8:9], 12 ; C082090C S_WAITCNT vmcnt(0) lgkmcnt(0) ; BF8C0070 BUFFER_LOAD_FORMAT_XYZW v[6:9], s[4:7][v1] + 0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80010601 S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v10, v6, v4 ; 10140906 V_MUL_F32_e32 v11, v8, v2 ; 10160508 V_SUB_F32_e32 v10, v11, v10 ; 0814150B V_MUL_F32_e32 v11, v8, v3 ; 10160708 V_MUL_F32_e32 v12, v7, v4 ; 10180907 V_SUB_F32_e32 v11, v12, v11 ; 0816170C V_MUL_F32_e32 v12, v11, v11 ; 1018170B V_MAD_F32 v12, v10, v10, v12, 0, 0, 0, 0 ; D282000C 0432150A V_MUL_F32_e32 v13, v7, v2 ; 101A0507 V_MUL_F32_e32 v14, v6, v3 ; 101C0706 V_SUB_F32_e32 v13, v14, v13 ; 081A1B0E V_MAD_F32 v12, v13, v13, v12, 0, 0, 0, 0 ; D282000C 04321B0D V_RSQ_LEGACY_F32_e32 v12, v12 ; 7E185B0C V_MUL_F32_e32 v11, v11, v12 ; 1016190B V_MUL_F32_e32 v14, v11, v8 ; 101C110B V_MUL_F32_e32 v13, v13, v12 ; 101A190D V_MUL_F32_e32 v15, v13, v6 ; 101E0D0D V_SUB_F32_e32 v14, v15, v14 ; 081C1D0F V_MUL_F32_e32 v15, v13, v7 ; 101E0F0D V_MUL_F32_e32 v10, v10, v12 ; 1014190A V_MUL_F32_e32 v12, v10, v8 ; 1018110A V_SUB_F32_e32 v12, v12, v15 ; 08181F0C V_MUL_F32_e32 v15, v12, v12 ; 101E190C V_MAD_F32 v15, v14, v14, v15, 0, 0, 0, 0 ; D282000F 043E1D0E V_MUL_F32_e32 v16, v10, v6 ; 10200D0A V_MUL_F32_e32 v17, v11, v7 ; 10220F0B V_SUB_F32_e32 v16, v17, v16 ; 08202111 V_MAD_F32 v15, v16, v16, v15, 0, 0, 0, 0 ; D282000F 043E2110 V_RSQ_LEGACY_F32_e32 v15, v15 ; 7E1E5B0F V_MUL_F32_e32 v14, v14, v15 ; 101C1F0E V_MUL_F32_e32 v17, v2, v2 ; 10220502 V_MAD_F32 v17, v3, v3, v17, 0, 0, 0, 0 ; D2820011 04460703 V_MAD_F32 v2, v4, v4, v17, 0, 0, 0, 0 ; D2820002 04460904 V_RSQ_LEGACY_F32_e32 v3, v2 ; 7E065B02 V_MUL_F32_e32 v3, v3, v2 ; 10060503 V_XOR_B32_e32 v2, -2147483648, v2 ; 3A0404FF 80000000 V_CMP_GT_F32_e64 s[2:3], 0, v2, 0, 0, 0, 0 ; D0080002 02020480 V_CNDMASK_B32_e64 v2, 0.000000e+00, v3, s[2:3], 0, 0, 0, 0 ; D2000002 000A0680 V_MUL_F32_e32 v3, v14, v2 ; 1006050E V_MUL_F32_e32 v4, v12, v15 ; 10081F0C V_MUL_F32_e32 v4, v4, v2 ; 10080504 S_LOAD_DWORDX4 s[4:7], s[0:1], 0 ; C0820100 S_WAITCNT lgkmcnt(0) ; BF8C007F S_BUFFER_LOAD_DWORD s10, s[4:7], 1 ; C2050501 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v5, s10, v4 ; 100A080A S_BUFFER_LOAD_DWORD s11, s[4:7], 5 ; C2058505 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v5, s11, v3, v5, 0, 0, 0, 0 ; D2820005 0416060B V_MUL_F32_e32 v12, v16, v15 ; 10181F10 V_MUL_F32_e32 v12, v12, v2 ; 1018050C S_BUFFER_LOAD_DWORD s12, s[4:7], 9 ; C2060509 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v5, s12, v12, v5, 0, 0, 0, 0 ; D2820005 0416180C V_MUL_F32_e32 v10, v10, v2 ; 1014050A V_MUL_F32_e32 v11, v11, v2 ; 1016050B V_MUL_F32_e32 v14, s10, v11 ; 101C160A V_MAD_F32 v14, s11, v10, v14, 0, 0, 0, 0 ; D282000E 043A140B V_MUL_F32_e32 v2, v13, v2 ; 1004050D V_MAD_F32 v13, s12, v2, v14, 0, 0, 0, 0 ; D282000D 043A040C S_LOAD_DWORDX4 s[16:19], s[8:9], 8 ; C0880908 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[14:17], s[16:19][v1] + 0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80040E01 S_LOAD_DWORDX4 s[0:3], s[0:1], 4 ; C0800104 S_WAITCNT vmcnt(0) lgkmcnt(0) ; BF8C0070 S_BUFFER_LOAD_DWORD s13, s[0:3], 81 ; C2068151 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v1, s13 ; 7E02020D V_SUB_F32_e64 v1, v15, v1, 0, 0, 0, 0 ; D2080001 0202030F S_BUFFER_LOAD_DWORD s13, s[0:3], 80 ; C2068150 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v18, s13 ; 7E24020D V_SUB_F32_e64 v18, v14, v18, 0, 0, 0, 0 ; D2080012 0202250E V_MUL_F32_e32 v18, v18, v18 ; 10242512 V_MAD_F32 v1, v1, v1, v18, 0, 0, 0, 0 ; D2820001 044A0301 S_BUFFER_LOAD_DWORD s13, s[0:3], 82 ; C2068152 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v18, s13 ; 7E24020D V_SUB_F32_e64 v18, v16, v18, 0, 0, 0, 0 ; D2080012 02022510 V_MAD_F32 v1, v18, v18, v1, 0, 0, 0, 0 ; D2820001 04062512 V_RSQ_LEGACY_F32_e32 v18, v1 ; 7E245B01 V_MUL_F32_e32 v18, v18, v1 ; 10240312 V_XOR_B32_e32 v1, -2147483648, v1 ; 3A0202FF 80000000 V_CMP_GT_F32_e64 s[14:15], 0, v1, 0, 0, 0, 0 ; D008000E 02020280 V_CNDMASK_B32_e64 v1, 0.000000e+00, v18, s[14:15], 0, 0, 0, 0 ; D2000001 003A2480 S_BUFFER_LOAD_DWORD s13, s[4:7], 16 ; C2068510 V_MOV_B32_e32 v18, -8.000000e-01 ; 7E2402FF BF4CCCCD S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v1, s13, v18, v1, 0, 0, 0, 0 ; D2820001 0406240D V_MOV_B32_e32 v19, s13 ; 7E26020D V_MAD_F32 v18, s13, v18, v19, 0, 0, 0, 0 ; D2820012 044E240D V_RCP_F32_e32 v18, v18 ; 7E245512 V_MUL_F32_e32 v1, v1, v18 ; 10022501 V_ADD_F32_e64 v1, 0, v1, 0, 1, 0, 0 ; D2060801 02020280 V_ADD_F32_e32 v18, v1, v1 ; 06240301 V_SUB_F32_e32 v18, 3.000000e+00, v18 ; 082424FF 40400000 V_MUL_F32_e32 v18, v1, v18 ; 10242501 V_MUL_F32_e32 v1, v1, v18 ; 10022501 V_SUB_F32_e32 v1, 1.000000e+00, v1 ; 080202F2 S_LOAD_DWORDX4 s[16:19], s[8:9], 0 ; C0880900 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[18:21], s[16:19][v0] + 0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80041200 S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v22, v18, v1 ; 102C0312 V_MUL_F32_e32 v13, v13, v22 ; 101A2D0D V_MUL_F32_e32 v23, v19, v1 ; 102E0313 V_MUL_F32_e32 v24, s10, v6 ; 10300C0A V_MAD_F32 v24, s11, v7, v24, 0, 0, 0, 0 ; D2820018 04620E0B V_MAD_F32 v24, s12, v8, v24, 0, 0, 0, 0 ; D2820018 0462100C V_MAD_F32 v13, v24, v23, v13, 0, 0, 0, 0 ; D282000D 04362F18 V_MUL_F32_e32 v1, v20, v1 ; 10020314 V_MAD_F32 v5, v5, v1, v13, 0, 0, 0, 0 ; D2820005 04360305 V_MUL_F32_e32 v13, s10, v14 ; 101A1C0A V_MAD_F32 v13, s11, v15, v13, 0, 0, 0, 0 ; D282000D 04361E0B V_MAD_F32 v13, s12, v16, v13, 0, 0, 0, 0 ; D282000D 0436200C S_BUFFER_LOAD_DWORD s10, s[4:7], 13 ; C205050D S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v13, s10, v13 ; 061A1A0A V_ADD_F32_e32 v5, v5, v13 ; 060A1B05 V_CMP_U_F32_e64 s[10:11], v19, v19, 0, 0, 0, 0 ; D010000A 02022713 V_CMP_LE_F32_e64 s[12:13], v19, 0.000000e+00, 0, 0, 0, 0 ; D006000C 02010113 S_OR_B64 s[10:11], s[12:13], s[10:11] ; 888A0A0C V_CNDMASK_B32_e64 v13, v19, 0.000000e+00, s[10:11], 0, 0, 0, 0 ; D200000D 00290113 V_MUL_F32_e32 v18, 0.000000e+00, v13 ; 10241A80 V_MOV_B32_e32 v19, 1.000000e-01 ; 7E2602FF 3DCCCCCD V_MAD_F32 v5, v18, v19, v5, 0, 0, 0, 0 ; D2820005 04162712 S_BUFFER_LOAD_DWORD s10, s[4:7], 0 ; C2050500 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v18, s10, v4 ; 1024080A S_BUFFER_LOAD_DWORD s11, s[4:7], 4 ; C2058504 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v18, s11, v3, v18, 0, 0, 0, 0 ; D2820012 044A060B S_BUFFER_LOAD_DWORD s12, s[4:7], 8 ; C2060508 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v18, s12, v12, v18, 0, 0, 0, 0 ; D2820012 044A180C V_MUL_F32_e32 v20, s10, v11 ; 1028160A V_MAD_F32 v20, s11, v10, v20, 0, 0, 0, 0 ; D2820014 0452140B V_MAD_F32 v20, s12, v2, v20, 0, 0, 0, 0 ; D2820014 0452040C V_MUL_F32_e32 v20, v20, v22 ; 10282D14 V_MUL_F32_e32 v21, s10, v6 ; 102A0C0A V_MAD_F32 v21, s11, v7, v21, 0, 0, 0, 0 ; D2820015 04560E0B V_MAD_F32 v21, s12, v8, v21, 0, 0, 0, 0 ; D2820015 0456100C V_MAD_F32 v20, v21, v23, v20, 0, 0, 0, 0 ; D2820014 04522F15 V_MAD_F32 v18, v18, v1, v20, 0, 0, 0, 0 ; D2820012 04520312 V_MUL_F32_e32 v20, s10, v14 ; 10281C0A V_MAD_F32 v20, s11, v15, v20, 0, 0, 0, 0 ; D2820014 04521E0B V_MAD_F32 v20, s12, v16, v20, 0, 0, 0, 0 ; D2820014 0452200C S_BUFFER_LOAD_DWORD s10, s[4:7], 12 ; C205050C S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v20, s10, v20 ; 0628280A V_ADD_F32_e32 v18, v18, v20 ; 06242912 V_ADD_F32_e32 v20, v14, v16 ; 0628210E V_MUL_F32_e32 v20, 1042479491, v20 ; 102828FF 3E22F983 V_COS_F32_e32 v20, v20 ; 7E286D14 S_BUFFER_LOAD_DWORD s10, s[0:3], 92 ; C205015C S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v21, s10, v14 ; 062A1C0A V_ADD_F32_e32 v21, v21, v15 ; 062A1F15 V_ADD_F32_e32 v21, v21, v16 ; 062A2115 V_MUL_F32_e32 v21, 1042479491, v21 ; 102A2AFF 3E22F983 V_COS_F32_e32 v21, v21 ; 7E2A6D15 V_MUL_F32_e32 v20, v21, v20 ; 10282915 V_MUL_F32_e32 v20, v20, v13 ; 10281B14 V_MAD_F32 v18, v20, v19, v18, 0, 0, 0, 0 ; D2820012 044A2714 S_BUFFER_LOAD_DWORD s10, s[0:3], 35 ; C2050123 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v20, s10, v18 ; 1028240A S_BUFFER_LOAD_DWORD s10, s[0:3], 39 ; C2050127 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v20, s10, v5, v20, 0, 0, 0, 0 ; D2820014 04520A0A S_BUFFER_LOAD_DWORD s10, s[4:7], 2 ; C2050502 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v24, s10, v4 ; 1030080A S_BUFFER_LOAD_DWORD s11, s[4:7], 6 ; C2058506 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v24, s11, v3, v24, 0, 0, 0, 0 ; D2820018 0462060B S_BUFFER_LOAD_DWORD s12, s[4:7], 10 ; C206050A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v24, s12, v12, v24, 0, 0, 0, 0 ; D2820018 0462180C V_MUL_F32_e32 v25, s10, v11 ; 1032160A V_MAD_F32 v25, s11, v10, v25, 0, 0, 0, 0 ; D2820019 0466140B V_MAD_F32 v25, s12, v2, v25, 0, 0, 0, 0 ; D2820019 0466040C V_MUL_F32_e32 v25, v25, v22 ; 10322D19 V_MUL_F32_e32 v26, s10, v6 ; 10340C0A V_MAD_F32 v26, s11, v7, v26, 0, 0, 0, 0 ; D282001A 046A0E0B V_MAD_F32 v26, s12, v8, v26, 0, 0, 0, 0 ; D282001A 046A100C V_MAD_F32 v25, v26, v23, v25, 0, 0, 0, 0 ; D2820019 04662F1A V_MAD_F32 v24, v24, v1, v25, 0, 0, 0, 0 ; D2820018 04660318 V_MUL_F32_e32 v25, s10, v14 ; 10321C0A V_MAD_F32 v25, s11, v15, v25, 0, 0, 0, 0 ; D2820019 04661E0B V_MAD_F32 v25, s12, v16, v25, 0, 0, 0, 0 ; D2820019 0466200C S_BUFFER_LOAD_DWORD s10, s[4:7], 14 ; C205050E S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v25, s10, v25 ; 0632320A V_ADD_F32_e32 v24, v24, v25 ; 06303318 V_ADD_F32_e32 v25, v15, v16 ; 0632210F V_MUL_F32_e32 v25, 1042479491, v25 ; 103232FF 3E22F983 V_COS_F32_e32 v25, v25 ; 7E326D19 V_MUL_F32_e32 v21, v21, v25 ; 102A3315 V_MUL_F32_e32 v13, v21, v13 ; 101A1B15 V_MAD_F32 v13, v13, v19, v24, 0, 0, 0, 0 ; D282000D 0462270D S_BUFFER_LOAD_DWORD s10, s[0:3], 43 ; C205012B S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v19, s10, v13, v20, 0, 0, 0, 0 ; D2820013 04521A0A S_BUFFER_LOAD_DWORD s10, s[0:3], 34 ; C2050122 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v20, s10, v18 ; 1028240A S_BUFFER_LOAD_DWORD s10, s[0:3], 38 ; C2050126 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v20, s10, v5, v20, 0, 0, 0, 0 ; D2820014 04520A0A S_BUFFER_LOAD_DWORD s10, s[0:3], 42 ; C205012A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v20, s10, v13, v20, 0, 0, 0, 0 ; D2820014 04521A0A S_LOAD_DWORDX4 s[8:11], s[8:9], 4 ; C0840904 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[24:27], s[8:11][v0] + 0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80021800 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 32, 0, 0, 0, v24, v25, v20, v19 ; F800020F 13141918 S_BUFFER_LOAD_DWORD s8, s[4:7], 3 ; C2040503 S_WAITCNT expcnt(0) lgkmcnt(0) ; BF8C000F V_MUL_F32_e32 v0, s8, v4 ; 10000808 S_BUFFER_LOAD_DWORD s9, s[4:7], 7 ; C2048507 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v0, s9, v3, v0, 0, 0, 0, 0 ; D2820000 04020609 S_BUFFER_LOAD_DWORD s10, s[4:7], 11 ; C205050B S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v0, s10, v12, v0, 0, 0, 0, 0 ; D2820000 0402180A V_MUL_F32_e32 v3, s8, v11 ; 10061608 V_MAD_F32 v3, s9, v10, v3, 0, 0, 0, 0 ; D2820003 040E1409 V_MAD_F32 v2, s10, v2, v3, 0, 0, 0, 0 ; D2820002 040E040A V_MUL_F32_e32 v2, v2, v22 ; 10042D02 V_MUL_F32_e32 v3, s8, v6 ; 10060C08 V_MAD_F32 v3, s9, v7, v3, 0, 0, 0, 0 ; D2820003 040E0E09 V_MAD_F32 v3, s10, v8, v3, 0, 0, 0, 0 ; D2820003 040E100A V_MAD_F32 v2, v3, v23, v2, 0, 0, 0, 0 ; D2820002 040A2F03 V_MAD_F32 v0, v0, v1, v2, 0, 0, 0, 0 ; D2820000 040A0300 V_MUL_F32_e32 v1, s8, v14 ; 10021C08 V_MAD_F32 v1, s9, v15, v1, 0, 0, 0, 0 ; D2820001 04061E09 V_MAD_F32 v1, s10, v16, v1, 0, 0, 0, 0 ; D2820001 0406200A S_BUFFER_LOAD_DWORD s4, s[4:7], 15 ; C202050F S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v1, s4, v1 ; 06020204 V_ADD_F32_e32 v0, v0, v1 ; 06000300 S_BUFFER_LOAD_DWORD s4, s[0:3], 47 ; C202012F S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v1, s4, v0, v19, 0, 0, 0, 0 ; D2820001 044E0004 S_BUFFER_LOAD_DWORD s4, s[0:3], 46 ; C202012E S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v2, s4, v0, v20, 0, 0, 0, 0 ; D2820002 04520004 S_BUFFER_LOAD_DWORD s4, s[0:3], 33 ; C2020121 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v3, s4, v18 ; 10062404 S_BUFFER_LOAD_DWORD s4, s[0:3], 37 ; C2020125 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v3, s4, v5, v3, 0, 0, 0, 0 ; D2820003 040E0A04 S_BUFFER_LOAD_DWORD s4, s[0:3], 41 ; C2020129 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v3, s4, v13, v3, 0, 0, 0, 0 ; D2820003 040E1A04 S_BUFFER_LOAD_DWORD s4, s[0:3], 45 ; C202012D S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v3, s4, v0, v3, 0, 0, 0, 0 ; D2820003 040E0004 S_BUFFER_LOAD_DWORD s4, s[0:3], 32 ; C2020120 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v4, s4, v18 ; 10082404 S_BUFFER_LOAD_DWORD s4, s[0:3], 36 ; C2020124 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v4, s4, v5, v4, 0, 0, 0, 0 ; D2820004 04120A04 S_BUFFER_LOAD_DWORD s4, s[0:3], 40 ; C2020128 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v4, s4, v13, v4, 0, 0, 0, 0 ; D2820004 04121A04 S_BUFFER_LOAD_DWORD s0, s[0:3], 44 ; C200012C S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v0, s0, v0, v4, 0, 0, 0, 0 ; D2820000 04120000 EXP 15, 12, 0, 1, 0, v0, v3, v2, v1 ; F80008CF 01020300 S_ENDPGM ; BF810000 FRAG DCL IN[0], GENERIC[20], PERSPECTIVE DCL IN[1], GENERIC[21], PERSPECTIVE DCL IN[2], GENERIC[22], PERSPECTIVE DCL IN[3], GENERIC[23], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL SAMP[1] DCL SAMP[2] DCL SAMP[3] DCL SAMP[4] DCL SAMP[5] DCL SAMP[6] DCL SAMP[7] DCL SAMP[8] DCL SAMP[9] DCL CONST[2..73] DCL CONST[82..94] DCL CONST[1][0..96] DCL CONST[2][0..68] DCL TEMP[0..41], LOCAL DCL ADDR[0] IMM[0] UINT32 {0, 224, 208, 192} IMM[1] INT32 {14, 13, 12, 15} IMM[2] UINT32 {240, 320, 1, 256} IMM[3] INT32 {20, 16, 6, 5} IMM[4] FLT32 { 0.0000, 1.0000, 0.6931, 0.0010} IMM[5] FLT32 { 2.0000, -1.0039, 0.5000, 3.0000} IMM[6] FLT32 { 1.0500, 0.8000, 0.7213, -1.0000} IMM[7] UINT32 {96, 80, 64, 112} IMM[8] INT32 {4, 7, 10, 9} IMM[9] UINT32 {252, 264, 160, 144} IMM[10] UINT32 {128, 176, 260, 0} IMM[11] INT32 {8, 11, 0, 1} IMM[12] FLT32 { -0.8000, 5.0000, 0.0000, 0.0000} IMM[13] INT32 {2, 3, 0, 0} 0: MOV TEMP[0].x, IN[1].wwww 1: MOV TEMP[0].yz, IN[2].yxyy 2: MOV TEMP[1].xy, IN[2].zwzz 3: MOV TEMP[1].z, IN[3].xxxx 4: UARL ADDR[0].x, IMM[1].xxxx 5: MOV TEMP[2], CONST[1][ADDR[0].x] 6: UARL ADDR[0].x, IMM[1].yyyy 7: MOV TEMP[3], CONST[1][ADDR[0].x] 8: UARL ADDR[0].x, IMM[1].zzzz 9: MOV TEMP[4], CONST[1][ADDR[0].x] 10: MUL TEMP[4], TEMP[4], IN[1].xxxx 11: MAD TEMP[3], TEMP[3], IN[1].yyyy, TEMP[4] 12: MAD TEMP[2], TEMP[2], IN[1].zzzz, TEMP[3] 13: UARL ADDR[0].x, IMM[1].wwww 14: MOV TEMP[3], CONST[1][ADDR[0].x] 15: ADD TEMP[2], TEMP[2], TEMP[3] 16: UARL ADDR[0].x, IMM[3].xxxx 17: MOV TEMP[3].xyz, CONST[1][ADDR[0].x].xyzz 18: ADD TEMP[2].xyz, TEMP[2].xyzz, -TEMP[3].xyzz 19: DP3 TEMP[2].x, TEMP[2].xyzz, TEMP[2].xyzz 20: RSQ TEMP[3].x, TEMP[2].xxxx 21: MUL TEMP[3].x, TEMP[3].xxxx, TEMP[2].xxxx 22: CMP TEMP[3].x, -TEMP[2].xxxx, TEMP[3].xxxx, IMM[4].xxxx 23: RCP TEMP[2].x, CONST[87].xxxx 24: MAD TEMP[2].x, TEMP[3].xxxx, TEMP[2].xxxx, IMM[4].yyyy 25: LG2 TEMP[2].x, TEMP[2].xxxx 26: MUL TEMP[2].x, TEMP[2].xxxx, IMM[4].zzzz 27: LG2 TEMP[3].x, CONST[88].xxxx 28: MUL TEMP[3].x, TEMP[3].xxxx, IMM[4].zzzz 29: RCP TEMP[3].x, TEMP[3].xxxx 30: MUL TEMP[2].x, TEMP[2].xxxx, TEMP[3].xxxx 31: FLR TEMP[3].x, TEMP[2].xxxx 32: EX2 TEMP[3].x, TEMP[3].xxxx 33: FRC TEMP[2].x, TEMP[2].xxxx 34: ABS TEMP[4].xyz, TEMP[1].xyzz 35: ADD TEMP[5].xyz, TEMP[4].xyzz, IMM[4].wwww 36: POW TEMP[6].x, TEMP[5].xxxx, CONST[86].xxxx 37: POW TEMP[6].y, TEMP[5].yyyy, CONST[86].xxxx 38: POW TEMP[6].z, TEMP[5].zzzz, CONST[86].xxxx 39: ADD TEMP[5].x, TEMP[6].xxxx, TEMP[6].yyyy 40: ADD TEMP[5].x, TEMP[5].xxxx, TEMP[6].zzzz 41: RCP TEMP[5].x, TEMP[5].xxxx 42: MUL TEMP[5].xyz, TEMP[6].xyzz, TEMP[5].xxxx 43: MUL TEMP[6].x, IN[0].xxxx, IMM[5].xxxx 44: MUL TEMP[7].x, CONST[85].xxxx, TEMP[3].xxxx 45: RCP TEMP[7].x, TEMP[7].xxxx 46: MUL TEMP[7].xy, IN[2].yxxx, TEMP[7].xxxx 47: MOV TEMP[7].xy, TEMP[7].xyyy 48: TEX TEMP[7], TEMP[7], SAMP[5], 2D 49: MUL TEMP[8].x, CONST[84].xxxx, TEMP[3].xxxx 50: RCP TEMP[8].x, TEMP[8].xxxx 51: MUL TEMP[8].xy, TEMP[0].xzzz, TEMP[8].xxxx 52: MOV TEMP[8].xy, TEMP[8].xyyy 53: TEX TEMP[8], TEMP[8], SAMP[4], 2D 54: MUL TEMP[9].x, CONST[84].xxxx, TEMP[3].xxxx 55: RCP TEMP[9].x, TEMP[9].xxxx 56: MUL TEMP[9].xy, TEMP[0].xzzz, TEMP[9].xxxx 57: MOV TEMP[9].xy, TEMP[9].xyyy 58: TEX TEMP[9], TEMP[9], SAMP[3], 2D 59: MIN TEMP[10].x, IMM[4].yyyy, TEMP[6].xxxx 60: LRP TEMP[8].xyz, TEMP[10].xxxx, TEMP[9].xyzz, TEMP[8].xyzz 61: MUL TEMP[9].x, CONST[83].xxxx, TEMP[3].xxxx 62: RCP TEMP[9].x, TEMP[9].xxxx 63: MUL TEMP[9].xy, TEMP[0].xyyy, TEMP[9].xxxx 64: MOV TEMP[9].xy, TEMP[9].xyyy 65: TEX TEMP[9], TEMP[9], SAMP[2], 2D 66: MUL TEMP[9].xyz, TEMP[9].xyzz, TEMP[5].zzzz 67: MAD TEMP[8].xyz, TEMP[8].xyzz, TEMP[5].yyyy, TEMP[9].xyzz 68: MAD TEMP[5].xyz, TEMP[7].xyzz, TEMP[5].xxxx, TEMP[8].xyzz 69: MUL TEMP[7].x, CONST[83].xxxx, TEMP[3].xxxx 70: RCP TEMP[7].x, TEMP[7].xxxx 71: MUL TEMP[7].xy, TEMP[0].xyyy, TEMP[7].xxxx 72: MOV TEMP[7].xy, TEMP[7].xyyy 73: TEX TEMP[7], TEMP[7], SAMP[6], 2D 74: MAD TEMP[8].xy, TEMP[7].xyyy, IMM[5].xxxx, IMM[5].yyyy 75: MOV TEMP[8].z, TEMP[7].zzzz 76: MUL TEMP[7].x, CONST[84].xxxx, TEMP[3].xxxx 77: RCP TEMP[7].x, TEMP[7].xxxx 78: MUL TEMP[7].xy, TEMP[0].xzzz, TEMP[7].xxxx 79: MOV TEMP[7].xy, TEMP[7].xyyy 80: TEX TEMP[7], TEMP[7], SAMP[7], 2D 81: MAD TEMP[9].xy, TEMP[7].xyyy, IMM[5].xxxx, IMM[5].yyyy 82: MOV TEMP[9].z, TEMP[7].zzzz 83: MUL TEMP[7].x, CONST[84].xxxx, TEMP[3].xxxx 84: RCP TEMP[7].x, TEMP[7].xxxx 85: MUL TEMP[7].xy, TEMP[0].xzzz, TEMP[7].xxxx 86: MOV TEMP[7].xy, TEMP[7].xyyy 87: TEX TEMP[7], TEMP[7], SAMP[8], 2D 88: MAD TEMP[10].xy, TEMP[7].xyyy, IMM[5].xxxx, IMM[5].yyyy 89: MOV TEMP[10].z, TEMP[7].zzzz 90: MUL TEMP[7].x, CONST[85].xxxx, TEMP[3].xxxx 91: RCP TEMP[7].x, TEMP[7].xxxx 92: MUL TEMP[7].xy, IN[2].yxxx, TEMP[7].xxxx 93: MOV TEMP[7].xy, TEMP[7].xyyy 94: TEX TEMP[7], TEMP[7], SAMP[9], 2D 95: MAD TEMP[11].xy, TEMP[7].xyyy, IMM[5].xxxx, IMM[5].yyyy 96: MOV TEMP[11].z, TEMP[7].zzzz 97: ADD TEMP[7].x, TEMP[4].xxxx, TEMP[4].yyyy 98: ADD TEMP[7].x, TEMP[7].xxxx, TEMP[4].zzzz 99: RCP TEMP[7].x, TEMP[7].xxxx 100: MUL TEMP[4].xyz, TEMP[4].xyzz, TEMP[7].xxxx 101: SSG TEMP[7].x, IN[2].zzzz 102: MUL TEMP[7].xyz, TEMP[11].zyxx, TEMP[7].xxxx 103: MIN TEMP[6].x, IMM[4].yyyy, TEMP[6].xxxx 104: LRP TEMP[6].xyz, TEMP[6].xxxx, TEMP[9].xyzz, TEMP[10].xyzz 105: SSG TEMP[9].x, IN[2].wwww 106: MUL TEMP[6].xyz, TEMP[6].xzyy, TEMP[9].xxxx 107: SSG TEMP[9].x, IN[3].xxxx 108: MUL TEMP[8].xyz, TEMP[8].xyzz, TEMP[9].xxxx 109: MUL TEMP[8].xyz, TEMP[8].xyzz, TEMP[4].zzzz 110: MAD TEMP[6].xyz, TEMP[6].xyzz, TEMP[4].yyyy, TEMP[8].xyzz 111: MAD TEMP[4].xyz, TEMP[7].xyzz, TEMP[4].xxxx, TEMP[6].xyzz 112: MOV TEMP[6].xyz, TEMP[5].xyzx 113: MOV TEMP[7].xyz, TEMP[4].xyzx 114: FSLT TEMP[8].x, TEMP[2].xxxx, CONST[89].xxxx 115: UIF TEMP[8].xxxx :0 116: MUL TEMP[3].x, TEMP[3].xxxx, IMM[5].zzzz 117: ABS TEMP[1].xyz, TEMP[1].xyzz 118: ADD TEMP[8].xyz, TEMP[1].xyzz, IMM[4].wwww 119: POW TEMP[9].x, TEMP[8].xxxx, CONST[86].xxxx 120: POW TEMP[9].y, TEMP[8].yyyy, CONST[86].xxxx 121: POW TEMP[9].z, TEMP[8].zzzz, CONST[86].xxxx 122: ADD TEMP[8].x, TEMP[9].xxxx, TEMP[9].yyyy 123: ADD TEMP[8].x, TEMP[8].xxxx, TEMP[9].zzzz 124: RCP TEMP[8].x, TEMP[8].xxxx 125: MUL TEMP[8].xyz, TEMP[9].xyzz, TEMP[8].xxxx 126: MUL TEMP[9].x, CONST[83].xxxx, TEMP[3].xxxx 127: RCP TEMP[9].x, TEMP[9].xxxx 128: MUL TEMP[9].xy, TEMP[0].xyyy, TEMP[9].xxxx 129: MOV TEMP[9].xy, TEMP[9].xyyy 130: TEX TEMP[9], TEMP[9], SAMP[6], 2D 131: MAD TEMP[10].xy, TEMP[9].xyyy, IMM[5].xxxx, IMM[5].yyyy 132: MOV TEMP[10].z, TEMP[9].zzzz 133: MUL TEMP[9].x, CONST[84].xxxx, TEMP[3].xxxx 134: RCP TEMP[9].x, TEMP[9].xxxx 135: MUL TEMP[9].xy, TEMP[0].xzzz, TEMP[9].xxxx 136: MOV TEMP[9].xy, TEMP[9].xyyy 137: TEX TEMP[9], TEMP[9], SAMP[7], 2D 138: MAD TEMP[11].xy, TEMP[9].xyyy, IMM[5].xxxx, IMM[5].yyyy 139: MOV TEMP[11].z, TEMP[9].zzzz 140: MUL TEMP[9].x, CONST[84].xxxx, TEMP[3].xxxx 141: RCP TEMP[9].x, TEMP[9].xxxx 142: MUL TEMP[9].xy, TEMP[0].xzzz, TEMP[9].xxxx 143: MOV TEMP[9].xy, TEMP[9].xyyy 144: TEX TEMP[9], TEMP[9], SAMP[8], 2D 145: MAD TEMP[12].xy, TEMP[9].xyyy, IMM[5].xxxx, IMM[5].yyyy 146: MOV TEMP[12].z, TEMP[9].zzzz 147: MUL TEMP[9].x, CONST[85].xxxx, TEMP[3].xxxx 148: RCP TEMP[9].x, TEMP[9].xxxx 149: MUL TEMP[9].xy, IN[2].yxxx, TEMP[9].xxxx 150: MOV TEMP[9].xy, TEMP[9].xyyy 151: TEX TEMP[9], TEMP[9], SAMP[9], 2D 152: MAD TEMP[13].xy, TEMP[9].xyyy, IMM[5].xxxx, IMM[5].yyyy 153: MOV TEMP[13].z, TEMP[9].zzzz 154: ADD TEMP[9].x, TEMP[1].xxxx, TEMP[1].yyyy 155: ADD TEMP[9].x, TEMP[9].xxxx, TEMP[1].zzzz 156: RCP TEMP[9].x, TEMP[9].xxxx 157: MUL TEMP[1].xyz, TEMP[1].xyzz, TEMP[9].xxxx 158: RCP TEMP[9].x, CONST[89].xxxx 159: MUL_SAT TEMP[2].x, TEMP[2].xxxx, TEMP[9].xxxx 160: MUL TEMP[9].x, IMM[5].xxxx, TEMP[2].xxxx 161: ADD TEMP[9].x, IMM[5].wwww, -TEMP[9].xxxx 162: MUL TEMP[9].x, TEMP[2].xxxx, TEMP[9].xxxx 163: MUL TEMP[2].x, TEMP[2].xxxx, TEMP[9].xxxx 164: MUL TEMP[9].x, IN[0].xxxx, IMM[5].xxxx 165: MUL TEMP[14].x, CONST[85].xxxx, TEMP[3].xxxx 166: RCP TEMP[14].x, TEMP[14].xxxx 167: MUL TEMP[14].xy, IN[2].yxxx, TEMP[14].xxxx 168: MOV TEMP[14].xy, TEMP[14].xyyy 169: TEX TEMP[14], TEMP[14], SAMP[5], 2D 170: MUL TEMP[15].x, CONST[84].xxxx, TEMP[3].xxxx 171: RCP TEMP[15].x, TEMP[15].xxxx 172: MUL TEMP[15].xy, TEMP[0].xzzz, TEMP[15].xxxx 173: MOV TEMP[15].xy, TEMP[15].xyyy 174: TEX TEMP[15], TEMP[15], SAMP[4], 2D 175: MUL TEMP[16].x, CONST[84].xxxx, TEMP[3].xxxx 176: RCP TEMP[16].x, TEMP[16].xxxx 177: MUL TEMP[16].xy, TEMP[0].xzzz, TEMP[16].xxxx 178: MOV TEMP[16].xy, TEMP[16].xyyy 179: TEX TEMP[16], TEMP[16], SAMP[3], 2D 180: MIN TEMP[17].x, IMM[4].yyyy, TEMP[9].xxxx 181: LRP TEMP[15].xyz, TEMP[17].xxxx, TEMP[16].xyzz, TEMP[15].xyzz 182: MUL TEMP[3].x, CONST[83].xxxx, TEMP[3].xxxx 183: RCP TEMP[3].x, TEMP[3].xxxx 184: MUL TEMP[0].xy, TEMP[0].xyyy, TEMP[3].xxxx 185: MOV TEMP[0].xy, TEMP[0].xyyy 186: TEX TEMP[0], TEMP[0], SAMP[2], 2D 187: MUL TEMP[0].xyz, TEMP[0].xyzz, TEMP[8].zzzz 188: MAD TEMP[0].xyz, TEMP[15].xyzz, TEMP[8].yyyy, TEMP[0].xyzz 189: MAD TEMP[0].xyz, TEMP[14].xyzz, TEMP[8].xxxx, TEMP[0].xyzz 190: LRP TEMP[6].xyz, TEMP[2].xxxx, TEMP[5].xyzz, TEMP[0].xyzz 191: SSG TEMP[0].x, IN[2].zzzz 192: MUL TEMP[0].xyz, TEMP[13].zyxx, TEMP[0].xxxx 193: MIN TEMP[3].x, IMM[4].yyyy, TEMP[9].xxxx 194: LRP TEMP[3].xyz, TEMP[3].xxxx, TEMP[11].xyzz, TEMP[12].xyzz 195: SSG TEMP[5].x, IN[2].wwww 196: MUL TEMP[3].xyz, TEMP[3].xzyy, TEMP[5].xxxx 197: SSG TEMP[5].x, IN[3].xxxx 198: MUL TEMP[5].xyz, TEMP[10].xyzz, TEMP[5].xxxx 199: MUL TEMP[5].xyz, TEMP[5].xyzz, TEMP[1].zzzz 200: MAD TEMP[3].xyz, TEMP[3].xyzz, TEMP[1].yyyy, TEMP[5].xyzz 201: MAD TEMP[0].xyz, TEMP[0].xyzz, TEMP[1].xxxx, TEMP[3].xyzz 202: LRP TEMP[7].xyz, TEMP[2].xxxx, TEMP[4].xyzz, TEMP[0].xyzz 203: ENDIF 204: MUL TEMP[6].xyz, TEMP[6].xyzz, IN[0].yzww 205: MUL TEMP[0].xyz, CONST[91].xyzz, TEMP[7].xxxx 206: MAD TEMP[0].xyz, CONST[92].xyzz, TEMP[7].yyyy, TEMP[0].xyzz 207: MAD TEMP[0].xyz, CONST[93].xyzz, TEMP[7].zzzz, TEMP[0].xyzz 208: DP3 TEMP[1].x, TEMP[0].xyzz, TEMP[0].xyzz 209: RSQ TEMP[1].x, TEMP[1].xxxx 210: MUL TEMP[0].xyz, TEMP[0].xyzz, TEMP[1].xxxx 211: MOV TEMP[1].xyz, TEMP[0].xyzx 212: MOV TEMP[2].xyz, TEMP[6].xyzx 213: MOV TEMP[3], CONST[82] 214: UARL ADDR[0].x, IMM[1].xxxx 215: MOV TEMP[4], CONST[1][ADDR[0].x] 216: UARL ADDR[0].x, IMM[1].yyyy 217: MOV TEMP[5], CONST[1][ADDR[0].x] 218: UARL ADDR[0].x, IMM[1].zzzz 219: MOV TEMP[7], CONST[1][ADDR[0].x] 220: MUL TEMP[7], TEMP[7], IN[1].xxxx 221: MAD TEMP[5], TEMP[5], IN[1].yyyy, TEMP[7] 222: MAD TEMP[4], TEMP[4], IN[1].zzzz, TEMP[5] 223: UARL ADDR[0].x, IMM[1].wwww 224: MOV TEMP[5], CONST[1][ADDR[0].x] 225: ADD TEMP[4], TEMP[4], TEMP[5] 226: MOV TEMP[5].xyz, TEMP[4].xyzx 227: UARL ADDR[0].x, IMM[3].xxxx 228: MOV TEMP[7].xyz, CONST[1][ADDR[0].x].xyzz 229: ADD TEMP[7].xyz, TEMP[4].xyzz, -TEMP[7].xyzz 230: DP3 TEMP[8].x, TEMP[7].xyzz, TEMP[7].xyzz 231: RSQ TEMP[8].x, TEMP[8].xxxx 232: MUL TEMP[7].xyz, TEMP[7].xyzz, TEMP[8].xxxx 233: DP3 TEMP[8].x, TEMP[0].xyzz, TEMP[7].xyzz 234: MUL TEMP[8].xyz, TEMP[8].xxxx, TEMP[0].xyzz 235: MUL TEMP[8].xyz, IMM[5].xxxx, TEMP[8].xyzz 236: ADD TEMP[7].xyz, TEMP[7].xyzz, -TEMP[8].xyzz 237: MOV TEMP[8].xyz, TEMP[7].xyzx 238: ADD_SAT TEMP[9].x, TEMP[0].yyyy, IMM[6].xxxx 239: UARL ADDR[0].x, IMM[1].xxxx 240: MOV TEMP[10].xyz, CONST[2][ADDR[0].x].xyzz 241: MUL TEMP[9].xyz, TEMP[9].xxxx, TEMP[10].xyzz 242: MUL TEMP[9].xyz, TEMP[6].xyzz, TEMP[9].xyzz 243: UARL ADDR[0].x, IMM[1].zzzz 244: UARL ADDR[0].x, IMM[1].zzzz 245: MOV TEMP[10].xyz, CONST[2][ADDR[0].x].xyzz 246: UARL ADDR[0].x, IMM[1].yyyy 247: UARL ADDR[0].x, IMM[1].yyyy 248: MOV TEMP[11].xyz, CONST[2][ADDR[0].x].xyzz 249: DP3 TEMP[0].x, TEMP[0].xyzz, TEMP[10].xyzz 250: MAX TEMP[0].x, IMM[4].xxxx, TEMP[0].xxxx 251: MUL TEMP[0].xyz, TEMP[0].xxxx, TEMP[11].xyzz 252: MUL TEMP[0].xyz, TEMP[0].xyzz, TEMP[6].xyzz 253: DP3 TEMP[6].x, TEMP[7].xyzz, TEMP[10].xyzz 254: MAX TEMP[6].x, IMM[4].wwww, TEMP[6].xxxx 255: POW TEMP[6].x, TEMP[6].xxxx, CONST[82].wwww 256: MUL TEMP[6].xyz, TEMP[6].xxxx, TEMP[11].xyzz 257: MAD TEMP[0].xyz, TEMP[6].xyzz, CONST[82].xyzz, TEMP[0].xyzz 258: UARL ADDR[0].x, IMM[1].wwww 259: MOV TEMP[6].xyz, CONST[2][ADDR[0].x].xyzz 260: ADD TEMP[6].xyz, TEMP[4].xyzz, -TEMP[6].xyzz 261: DP3 TEMP[6].x, TEMP[6].xyzz, TEMP[6].xyzz 262: RSQ TEMP[7].x, TEMP[6].xxxx 263: MUL TEMP[7].x, TEMP[7].xxxx, TEMP[6].xxxx 264: CMP TEMP[6].x, -TEMP[6].xxxx, TEMP[7].xxxx, IMM[4].xxxx 265: MOV TEMP[7].x, IMM[4].xxxx 266: UARL ADDR[0].x, IMM[3].yyyy 267: UARL ADDR[0].x, IMM[3].yyyy 268: MOV TEMP[10].x, CONST[2][ADDR[0].x].xxxx 269: MUL TEMP[10].x, IMM[6].yyyy, TEMP[10].xxxx 270: FSLT TEMP[10].x, TEMP[6].xxxx, TEMP[10].xxxx 271: UIF TEMP[10].xxxx :0 272: UARL ADDR[0].x, IMM[3].zzzz 273: MOV TEMP[10], CONST[2][ADDR[0].x] 274: UARL ADDR[0].x, IMM[3].wwww 275: MOV TEMP[11], CONST[2][ADDR[0].x] 276: UARL ADDR[0].x, IMM[8].xxxx 277: MOV TEMP[12], CONST[2][ADDR[0].x] 278: MUL TEMP[12], TEMP[12], TEMP[4].xxxx 279: MAD TEMP[11], TEMP[11], TEMP[4].yyyy, TEMP[12] 280: MAD TEMP[10], TEMP[10], TEMP[4].zzzz, TEMP[11] 281: UARL ADDR[0].x, IMM[8].yyyy 282: MOV TEMP[11], CONST[2][ADDR[0].x] 283: ADD TEMP[10], TEMP[10], TEMP[11] 284: UARL ADDR[0].x, IMM[1].wwww 285: MOV TEMP[11].x, CONST[2][ADDR[0].x].wwww 286: MAX TEMP[12].x, TEMP[10].zzzz, IMM[6].wwww 287: MIN TEMP[12].x, TEMP[12].xxxx, IMM[4].yyyy 288: ADD TEMP[12].x, TEMP[12].xxxx, IMM[4].yyyy 289: MUL TEMP[11].x, -TEMP[11].xxxx, TEMP[12].xxxx 290: MUL TEMP[11].x, IMM[6].zzzz, TEMP[11].xxxx 291: EX2 TEMP[11].x, TEMP[11].xxxx 292: MAD TEMP[10].xy, TEMP[10].xyyy, IMM[5].zzzz, IMM[5].zzzz 293: UARL ADDR[0].x, IMM[3].yyyy 294: MOV TEMP[12].x, CONST[2][ADDR[0].x].zzzz 295: MUL TEMP[10].xy, TEMP[10].xyyy, TEMP[12].xxxx 296: MOV TEMP[10].xy, TEMP[10].xyyy 297: TEX TEMP[10], TEMP[10], SAMP[0], RECT 298: MUL_SAT TEMP[10].x, TEMP[11].xxxx, TEMP[10].xxxx 299: MOV TEMP[7].x, TEMP[10].xxxx 300: ELSE :0 301: UARL ADDR[0].x, IMM[3].yyyy 302: UARL ADDR[0].x, IMM[3].yyyy 303: MOV TEMP[10].x, CONST[2][ADDR[0].x].xxxx 304: FSLT TEMP[10].x, TEMP[10].xxxx, TEMP[6].xxxx 305: UIF TEMP[10].xxxx :0 306: UARL ADDR[0].x, IMM[8].zzzz 307: MOV TEMP[10], CONST[2][ADDR[0].x] 308: UARL ADDR[0].x, IMM[8].wwww 309: MOV TEMP[11], CONST[2][ADDR[0].x] 310: UARL ADDR[0].x, IMM[11].xxxx 311: MOV TEMP[12], CONST[2][ADDR[0].x] 312: MUL TEMP[12], TEMP[12], TEMP[4].xxxx 313: MAD TEMP[11], TEMP[11], TEMP[4].yyyy, TEMP[12] 314: MAD TEMP[10], TEMP[10], TEMP[4].zzzz, TEMP[11] 315: UARL ADDR[0].x, IMM[11].yyyy 316: MOV TEMP[11], CONST[2][ADDR[0].x] 317: ADD TEMP[10], TEMP[10], TEMP[11] 318: UARL ADDR[0].x, IMM[1].wwww 319: MOV TEMP[11].xyz, CONST[2][ADDR[0].x].xyzz 320: ADD TEMP[11].xyz, TEMP[4].xyzz, -TEMP[11].xyzz 321: DP3 TEMP[11].x, TEMP[11].xyzz, TEMP[11].xyzz 322: RSQ TEMP[12].x, TEMP[11].xxxx 323: MUL TEMP[12].x, TEMP[12].xxxx, TEMP[11].xxxx 324: CMP TEMP[12].x, -TEMP[11].xxxx, TEMP[12].xxxx, IMM[4].xxxx 325: UARL ADDR[0].x, IMM[3].yyyy 326: MOV TEMP[11].x, CONST[2][ADDR[0].x].yyyy 327: RCP TEMP[11].x, TEMP[11].xxxx 328: MAD TEMP[11].x, TEMP[12].xxxx, TEMP[11].xxxx, IMM[12].xxxx 329: MUL_SAT TEMP[11].x, TEMP[11].xxxx, IMM[12].yyyy 330: UARL ADDR[0].x, IMM[1].wwww 331: MOV TEMP[12].x, CONST[2][ADDR[0].x].wwww 332: MAX TEMP[13].x, TEMP[10].zzzz, IMM[6].wwww 333: MIN TEMP[13].x, TEMP[13].xxxx, IMM[4].yyyy 334: ADD TEMP[13].x, TEMP[13].xxxx, IMM[4].yyyy 335: MUL TEMP[12].x, -TEMP[12].xxxx, TEMP[13].xxxx 336: MUL TEMP[12].x, IMM[6].zzzz, TEMP[12].xxxx 337: EX2 TEMP[12].x, TEMP[12].xxxx 338: MAD TEMP[10].xy, TEMP[10].xyyy, IMM[5].zzzz, IMM[5].zzzz 339: UARL ADDR[0].x, IMM[3].yyyy 340: MOV TEMP[13].x, CONST[2][ADDR[0].x].zzzz 341: MUL TEMP[10].xy, TEMP[10].xyyy, TEMP[13].xxxx 342: MOV TEMP[10].xy, TEMP[10].xyyy 343: TEX TEMP[10], TEMP[10], SAMP[1], RECT 344: MUL_SAT TEMP[10].x, TEMP[12].xxxx, TEMP[10].xxxx 345: MUL TEMP[12].x, IMM[5].xxxx, TEMP[11].xxxx 346: ADD TEMP[12].x, IMM[5].wwww, -TEMP[12].xxxx 347: MUL TEMP[12].x, TEMP[11].xxxx, TEMP[12].xxxx 348: MUL TEMP[11].x, TEMP[11].xxxx, TEMP[12].xxxx 349: LRP TEMP[7].x, TEMP[11].xxxx, IMM[4].yyyy, TEMP[10].xxxx 350: ELSE :0 351: UARL ADDR[0].x, IMM[3].zzzz 352: MOV TEMP[10], CONST[2][ADDR[0].x] 353: UARL ADDR[0].x, IMM[3].wwww 354: MOV TEMP[11], CONST[2][ADDR[0].x] 355: UARL ADDR[0].x, IMM[8].xxxx 356: MOV TEMP[12], CONST[2][ADDR[0].x] 357: MUL TEMP[12], TEMP[12], TEMP[4].xxxx 358: MAD TEMP[11], TEMP[11], TEMP[4].yyyy, TEMP[12] 359: MAD TEMP[10], TEMP[10], TEMP[4].zzzz, TEMP[11] 360: UARL ADDR[0].x, IMM[8].yyyy 361: MOV TEMP[11], CONST[2][ADDR[0].x] 362: ADD TEMP[10], TEMP[10], TEMP[11] 363: UARL ADDR[0].x, IMM[8].zzzz 364: MOV TEMP[11], CONST[2][ADDR[0].x] 365: UARL ADDR[0].x, IMM[8].wwww 366: MOV TEMP[12], CONST[2][ADDR[0].x] 367: UARL ADDR[0].x, IMM[11].xxxx 368: MOV TEMP[13], CONST[2][ADDR[0].x] 369: MUL TEMP[13], TEMP[13], TEMP[4].xxxx 370: MAD TEMP[12], TEMP[12], TEMP[4].yyyy, TEMP[13] 371: MAD TEMP[4], TEMP[11], TEMP[4].zzzz, TEMP[12] 372: UARL ADDR[0].x, IMM[11].yyyy 373: MOV TEMP[11], CONST[2][ADDR[0].x] 374: ADD TEMP[4], TEMP[4], TEMP[11] 375: UARL ADDR[0].x, IMM[3].yyyy 376: UARL ADDR[0].x, IMM[3].yyyy 377: MOV TEMP[11].x, CONST[2][ADDR[0].x].xxxx 378: MUL TEMP[12].x, IMM[6].yyyy, TEMP[11].xxxx 379: ADD TEMP[6].x, TEMP[6].xxxx, -TEMP[12].xxxx 380: ADD TEMP[11].x, TEMP[11].xxxx, -TEMP[12].xxxx 381: RCP TEMP[11].x, TEMP[11].xxxx 382: MUL_SAT TEMP[6].x, TEMP[6].xxxx, TEMP[11].xxxx 383: UARL ADDR[0].x, IMM[1].wwww 384: UARL ADDR[0].x, IMM[1].wwww 385: MOV TEMP[11].x, CONST[2][ADDR[0].x].wwww 386: UARL ADDR[0].x, IMM[3].yyyy 387: UARL ADDR[0].x, IMM[3].yyyy 388: MOV TEMP[12].x, CONST[2][ADDR[0].x].zzzz 389: MAX TEMP[13].x, TEMP[10].zzzz, IMM[6].wwww 390: MIN TEMP[13].x, TEMP[13].xxxx, IMM[4].yyyy 391: ADD TEMP[13].x, TEMP[13].xxxx, IMM[4].yyyy 392: MUL TEMP[13].x, -TEMP[11].xxxx, TEMP[13].xxxx 393: MUL TEMP[13].x, IMM[6].zzzz, TEMP[13].xxxx 394: EX2 TEMP[13].x, TEMP[13].xxxx 395: MAD TEMP[10].xy, TEMP[10].xyyy, IMM[5].zzzz, IMM[5].zzzz 396: MUL TEMP[10].xy, TEMP[10].xyyy, TEMP[12].xxxx 397: MOV TEMP[10].xy, TEMP[10].xyyy 398: TEX TEMP[10], TEMP[10], SAMP[0], RECT 399: MUL_SAT TEMP[10].x, TEMP[13].xxxx, TEMP[10].xxxx 400: MAX TEMP[13].x, TEMP[4].zzzz, IMM[6].wwww 401: MIN TEMP[13].x, TEMP[13].xxxx, IMM[4].yyyy 402: ADD TEMP[13].x, TEMP[13].xxxx, IMM[4].yyyy 403: MUL TEMP[11].x, -TEMP[11].xxxx, TEMP[13].xxxx 404: MUL TEMP[11].x, IMM[6].zzzz, TEMP[11].xxxx 405: EX2 TEMP[11].x, TEMP[11].xxxx 406: MAD TEMP[4].xy, TEMP[4].xyyy, IMM[5].zzzz, IMM[5].zzzz 407: MUL TEMP[4].xy, TEMP[4].xyyy, TEMP[12].xxxx 408: MOV TEMP[4].xy, TEMP[4].xyyy 409: TEX TEMP[4], TEMP[4], SAMP[1], RECT 410: MUL_SAT TEMP[4].x, TEMP[11].xxxx, TEMP[4].xxxx 411: MUL TEMP[11].x, IMM[5].xxxx, TEMP[6].xxxx 412: ADD TEMP[11].x, IMM[5].wwww, -TEMP[11].xxxx 413: MUL TEMP[11].x, TEMP[6].xxxx, TEMP[11].xxxx 414: MUL TEMP[6].x, TEMP[6].xxxx, TEMP[11].xxxx 415: LRP TEMP[7].x, TEMP[6].xxxx, TEMP[4].xxxx, TEMP[10].xxxx 416: ENDIF 417: ENDIF 418: ADD TEMP[4].x, TEMP[7].xxxx, IMM[12].xxxx 419: MUL_SAT TEMP[4].x, TEMP[4].xxxx, IMM[12].yyyy 420: MUL TEMP[6].x, IMM[5].xxxx, TEMP[4].xxxx 421: ADD TEMP[6].x, IMM[5].wwww, -TEMP[6].xxxx 422: MUL TEMP[6].x, TEMP[4].xxxx, TEMP[6].xxxx 423: MUL TEMP[4].x, TEMP[4].xxxx, TEMP[6].xxxx 424: MUL TEMP[0].xyz, TEMP[0].xyzz, TEMP[4].xxxx 425: ADD TEMP[9].xyz, TEMP[9].xyzz, TEMP[0].xyzz 426: MOV TEMP[0].x, IMM[11].zzzz 427: BGNLOOP :0 428: ISGE TEMP[4].x, TEMP[0].xxxx, CONST[3].xxxx 429: UIF TEMP[4].xxxx :0 430: BRK 431: ENDIF 432: UMUL TEMP[6].x, TEMP[0].xxxx, IMM[8].yyyy 433: UARL ADDR[0].x, TEMP[6].xxxx 434: MOV TEMP[7].x, CONST[ADDR[0].x+4].xxxx 435: UADD TEMP[10].x, TEMP[6].xxxx, IMM[11].wwww 436: UARL ADDR[0].x, TEMP[10].xxxx 437: MOV TEMP[7].y, CONST[ADDR[0].x+4].xxxx 438: UADD TEMP[11].x, TEMP[6].xxxx, IMM[13].xxxx 439: UARL ADDR[0].x, TEMP[11].xxxx 440: MOV TEMP[7].z, CONST[ADDR[0].x+4].xxxx 441: UADD TEMP[12].x, TEMP[6].xxxx, IMM[13].yyyy 442: UARL ADDR[0].x, TEMP[12].xxxx 443: MOV TEMP[13].x, CONST[ADDR[0].x+4].xxxx 444: UADD TEMP[14].x, TEMP[6].xxxx, IMM[8].xxxx 445: UARL ADDR[0].x, TEMP[14].xxxx 446: MOV TEMP[13].y, CONST[ADDR[0].x+4].xxxx 447: UADD TEMP[15].x, TEMP[6].xxxx, IMM[3].wwww 448: UARL ADDR[0].x, TEMP[15].xxxx 449: MOV TEMP[13].z, CONST[ADDR[0].x+4].xxxx 450: UADD TEMP[16].x, TEMP[6].xxxx, IMM[3].zzzz 451: UARL ADDR[0].x, TEMP[16].xxxx 452: MOV TEMP[17].x, CONST[ADDR[0].x+4].xxxx 453: ADD TEMP[18].xyz, TEMP[7].xyzz, -TEMP[5].xyzz 454: DP3 TEMP[19].x, TEMP[18].xyzz, TEMP[18].xyzz 455: RSQ TEMP[20].x, TEMP[19].xxxx 456: MUL TEMP[20].x, TEMP[20].xxxx, TEMP[19].xxxx 457: CMP TEMP[21].x, -TEMP[19].xxxx, TEMP[20].xxxx, IMM[4].xxxx 458: RCP TEMP[22].x, TEMP[21].xxxx 459: MUL TEMP[23].xyz, TEMP[18].xyzz, TEMP[22].xxxx 460: DP3 TEMP[24].x, TEMP[1].xyzz, TEMP[23].xyzz 461: MAX TEMP[25].x, IMM[4].xxxx, TEMP[24].xxxx 462: MUL TEMP[26].xyz, TEMP[25].xxxx, TEMP[13].xyzz 463: MUL TEMP[27].xyz, TEMP[26].xyzz, TEMP[2].xyzz 464: DP3 TEMP[28].x, TEMP[8].xyzz, TEMP[23].xyzz 465: MAX TEMP[29].x, IMM[4].wwww, TEMP[28].xxxx 466: POW TEMP[30].x, TEMP[29].xxxx, TEMP[3].wwww 467: MUL TEMP[31].xyz, TEMP[30].xxxx, TEMP[13].xyzz 468: MAD TEMP[27].xyz, TEMP[31].xyzz, TEMP[3].xyzz, TEMP[27].xyzz 469: MUL TEMP[32].x, TEMP[17].xxxx, IMM[5].zzzz 470: ADD TEMP[33].x, TEMP[21].xxxx, -TEMP[32].xxxx 471: ADD TEMP[34].x, TEMP[17].xxxx, -TEMP[32].xxxx 472: RCP TEMP[35].x, TEMP[34].xxxx 473: MUL_SAT TEMP[36].x, TEMP[33].xxxx, TEMP[35].xxxx 474: MUL TEMP[37].x, IMM[5].xxxx, TEMP[36].xxxx 475: ADD TEMP[38].x, IMM[5].wwww, -TEMP[37].xxxx 476: MUL TEMP[39].x, TEMP[36].xxxx, TEMP[38].xxxx 477: MUL TEMP[40].x, TEMP[36].xxxx, TEMP[39].xxxx 478: ADD TEMP[41].x, IMM[4].yyyy, -TEMP[40].xxxx 479: MUL TEMP[27].xyz, TEMP[27].xyzz, TEMP[41].xxxx 480: ADD TEMP[9].xyz, TEMP[9].xyzz, TEMP[27].xyzz 481: UADD TEMP[0].x, TEMP[0].xxxx, IMM[11].wwww 482: ENDLOOP :0 483: MOV TEMP[0].xyz, TEMP[9].xyzx 484: MOV OUT[0], TEMP[0] 485: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %22 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0 %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0 %24 = call float @llvm.SI.load.const(<16 x i8> %23, i32 48) %25 = call float @llvm.SI.load.const(<16 x i8> %23, i32 1312) %26 = call float @llvm.SI.load.const(<16 x i8> %23, i32 1316) %27 = call float @llvm.SI.load.const(<16 x i8> %23, i32 1320) %28 = call float @llvm.SI.load.const(<16 x i8> %23, i32 1324) %29 = call float @llvm.SI.load.const(<16 x i8> %23, i32 1328) %30 = call float @llvm.SI.load.const(<16 x i8> %23, i32 1344) %31 = call float @llvm.SI.load.const(<16 x i8> %23, i32 1360) %32 = call float @llvm.SI.load.const(<16 x i8> %23, i32 1376) %33 = call float @llvm.SI.load.const(<16 x i8> %23, i32 1392) %34 = call float @llvm.SI.load.const(<16 x i8> %23, i32 1408) %35 = call float @llvm.SI.load.const(<16 x i8> %23, i32 1424) %36 = call float @llvm.SI.load.const(<16 x i8> %23, i32 1456) %37 = call float @llvm.SI.load.const(<16 x i8> %23, i32 1460) %38 = call float @llvm.SI.load.const(<16 x i8> %23, i32 1464) %39 = call float @llvm.SI.load.const(<16 x i8> %23, i32 1472) %40 = call float @llvm.SI.load.const(<16 x i8> %23, i32 1476) %41 = call float @llvm.SI.load.const(<16 x i8> %23, i32 1480) %42 = call float @llvm.SI.load.const(<16 x i8> %23, i32 1488) %43 = call float @llvm.SI.load.const(<16 x i8> %23, i32 1492) %44 = call float @llvm.SI.load.const(<16 x i8> %23, i32 1496) %45 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 1 %46 = load <16 x i8> addrspace(2)* %45, !tbaa !0 %47 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 2 %48 = load <16 x i8> addrspace(2)* %47, !tbaa !0 %49 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0 %50 = load <32 x i8> addrspace(2)* %49, !tbaa !0 %51 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0 %52 = load <16 x i8> addrspace(2)* %51, !tbaa !0 %53 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 1 %54 = load <32 x i8> addrspace(2)* %53, !tbaa !0 %55 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 1 %56 = load <16 x i8> addrspace(2)* %55, !tbaa !0 %57 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 2 %58 = load <32 x i8> addrspace(2)* %57, !tbaa !0 %59 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 2 %60 = load <16 x i8> addrspace(2)* %59, !tbaa !0 %61 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 3 %62 = load <32 x i8> addrspace(2)* %61, !tbaa !0 %63 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 3 %64 = load <16 x i8> addrspace(2)* %63, !tbaa !0 %65 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 4 %66 = load <32 x i8> addrspace(2)* %65, !tbaa !0 %67 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 4 %68 = load <16 x i8> addrspace(2)* %67, !tbaa !0 %69 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 5 %70 = load <32 x i8> addrspace(2)* %69, !tbaa !0 %71 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 5 %72 = load <16 x i8> addrspace(2)* %71, !tbaa !0 %73 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 6 %74 = load <32 x i8> addrspace(2)* %73, !tbaa !0 %75 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 6 %76 = load <16 x i8> addrspace(2)* %75, !tbaa !0 %77 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 7 %78 = load <32 x i8> addrspace(2)* %77, !tbaa !0 %79 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 7 %80 = load <16 x i8> addrspace(2)* %79, !tbaa !0 %81 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 8 %82 = load <32 x i8> addrspace(2)* %81, !tbaa !0 %83 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 8 %84 = load <16 x i8> addrspace(2)* %83, !tbaa !0 %85 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 9 %86 = load <32 x i8> addrspace(2)* %85, !tbaa !0 %87 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 9 %88 = load <16 x i8> addrspace(2)* %87, !tbaa !0 %89 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %7) %90 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %7) %91 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %5, <2 x i32> %7) %92 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %5, <2 x i32> %7) %93 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %5, <2 x i32> %7) %94 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %5, <2 x i32> %7) %95 = call float @llvm.SI.fs.interp(i32 2, i32 1, i32 %5, <2 x i32> %7) %96 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %5, <2 x i32> %7) %97 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %5, <2 x i32> %7) %98 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %5, <2 x i32> %7) %99 = call float @llvm.SI.fs.interp(i32 2, i32 2, i32 %5, <2 x i32> %7) %100 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %5, <2 x i32> %7) %101 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %5, <2 x i32> %7) %102 = shl i32 14, 4 %103 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %102) %104 = shl i32 14, 4 %105 = add i32 %104, 4 %106 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %105) %107 = shl i32 14, 4 %108 = add i32 %107, 8 %109 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %108) %110 = shl i32 13, 4 %111 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %110) %112 = shl i32 13, 4 %113 = add i32 %112, 4 %114 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %113) %115 = shl i32 13, 4 %116 = add i32 %115, 8 %117 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %116) %118 = shl i32 12, 4 %119 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %118) %120 = shl i32 12, 4 %121 = add i32 %120, 4 %122 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %121) %123 = shl i32 12, 4 %124 = add i32 %123, 8 %125 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %124) %126 = fmul float %119, %93 %127 = fmul float %122, %93 %128 = fmul float %125, %93 %129 = fmul float %111, %94 %130 = fadd float %129, %126 %131 = fmul float %114, %94 %132 = fadd float %131, %127 %133 = fmul float %117, %94 %134 = fadd float %133, %128 %135 = fmul float %103, %95 %136 = fadd float %135, %130 %137 = fmul float %106, %95 %138 = fadd float %137, %132 %139 = fmul float %109, %95 %140 = fadd float %139, %134 %141 = shl i32 15, 4 %142 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %141) %143 = shl i32 15, 4 %144 = add i32 %143, 4 %145 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %144) %146 = shl i32 15, 4 %147 = add i32 %146, 8 %148 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %147) %149 = fadd float %136, %142 %150 = fadd float %138, %145 %151 = fadd float %140, %148 %152 = shl i32 20, 4 %153 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %152) %154 = shl i32 20, 4 %155 = add i32 %154, 4 %156 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %155) %157 = shl i32 20, 4 %158 = add i32 %157, 8 %159 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %158) %160 = fsub float -0.000000e+00, %153 %161 = fadd float %149, %160 %162 = fsub float -0.000000e+00, %156 %163 = fadd float %150, %162 %164 = fsub float -0.000000e+00, %159 %165 = fadd float %151, %164 %166 = fmul float %161, %161 %167 = fmul float %163, %163 %168 = fadd float %167, %166 %169 = fmul float %165, %165 %170 = fadd float %168, %169 %171 = call float @llvm.AMDGPU.rsq(float %170) %172 = fmul float %171, %170 %173 = fsub float -0.000000e+00, %170 %174 = call float @llvm.AMDGPU.cndlt(float %173, float %172, float 0.000000e+00) %175 = fdiv float 1.000000e+00, %33 %176 = fmul float %174, %175 %177 = fadd float %176, 1.000000e+00 %178 = call float @llvm.log2.f32(float %177) %179 = fmul float %178, 0x3FE62E4300000000 %180 = call float @llvm.log2.f32(float %34) %181 = fmul float %180, 0x3FE62E4300000000 %182 = fdiv float 1.000000e+00, %181 %183 = fmul float %179, %182 %184 = call float @floor(float %183) %185 = call float @llvm.AMDIL.exp.(float %184) %186 = call float @llvm.AMDIL.fraction.(float %183) %187 = call float @fabs(float %99) %188 = call float @fabs(float %100) %189 = call float @fabs(float %101) %190 = fadd float %187, 0x3F50624DE0000000 %191 = fadd float %188, 0x3F50624DE0000000 %192 = fadd float %189, 0x3F50624DE0000000 %193 = call float @llvm.pow.f32(float %190, float %32) %194 = call float @llvm.pow.f32(float %191, float %32) %195 = call float @llvm.pow.f32(float %192, float %32) %196 = fadd float %193, %194 %197 = fadd float %196, %195 %198 = fdiv float 1.000000e+00, %197 %199 = fmul float %193, %198 %200 = fmul float %194, %198 %201 = fmul float %195, %198 %202 = fmul float %89, 2.000000e+00 %203 = fmul float %31, %185 %204 = fdiv float 1.000000e+00, %203 %205 = fmul float %98, %204 %206 = fmul float %97, %204 %207 = bitcast float %205 to i32 %208 = bitcast float %206 to i32 %209 = insertelement <2 x i32> undef, i32 %207, i32 0 %210 = insertelement <2 x i32> %209, i32 %208, i32 1 %211 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %210, <32 x i8> %70, <16 x i8> %72, i32 2) %212 = extractelement <4 x float> %211, i32 0 %213 = extractelement <4 x float> %211, i32 1 %214 = extractelement <4 x float> %211, i32 2 %215 = fmul float %30, %185 %216 = fdiv float 1.000000e+00, %215 %217 = fmul float %96, %216 %218 = fmul float %98, %216 %219 = bitcast float %217 to i32 %220 = bitcast float %218 to i32 %221 = insertelement <2 x i32> undef, i32 %219, i32 0 %222 = insertelement <2 x i32> %221, i32 %220, i32 1 %223 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %222, <32 x i8> %66, <16 x i8> %68, i32 2) %224 = extractelement <4 x float> %223, i32 0 %225 = extractelement <4 x float> %223, i32 1 %226 = extractelement <4 x float> %223, i32 2 %227 = fmul float %30, %185 %228 = fdiv float 1.000000e+00, %227 %229 = fmul float %96, %228 %230 = fmul float %98, %228 %231 = bitcast float %229 to i32 %232 = bitcast float %230 to i32 %233 = insertelement <2 x i32> undef, i32 %231, i32 0 %234 = insertelement <2 x i32> %233, i32 %232, i32 1 %235 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %234, <32 x i8> %62, <16 x i8> %64, i32 2) %236 = extractelement <4 x float> %235, i32 0 %237 = extractelement <4 x float> %235, i32 1 %238 = extractelement <4 x float> %235, i32 2 %239 = fcmp uge float 1.000000e+00, %202 %240 = select i1 %239, float %202, float 1.000000e+00 %241 = call float @llvm.AMDGPU.lrp(float %240, float %236, float %224) %242 = call float @llvm.AMDGPU.lrp(float %240, float %237, float %225) %243 = call float @llvm.AMDGPU.lrp(float %240, float %238, float %226) %244 = fmul float %29, %185 %245 = fdiv float 1.000000e+00, %244 %246 = fmul float %96, %245 %247 = fmul float %97, %245 %248 = bitcast float %246 to i32 %249 = bitcast float %247 to i32 %250 = insertelement <2 x i32> undef, i32 %248, i32 0 %251 = insertelement <2 x i32> %250, i32 %249, i32 1 %252 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %251, <32 x i8> %58, <16 x i8> %60, i32 2) %253 = extractelement <4 x float> %252, i32 0 %254 = extractelement <4 x float> %252, i32 1 %255 = extractelement <4 x float> %252, i32 2 %256 = fmul float %253, %201 %257 = fmul float %254, %201 %258 = fmul float %255, %201 %259 = fmul float %241, %200 %260 = fadd float %259, %256 %261 = fmul float %242, %200 %262 = fadd float %261, %257 %263 = fmul float %243, %200 %264 = fadd float %263, %258 %265 = fmul float %212, %199 %266 = fadd float %265, %260 %267 = fmul float %213, %199 %268 = fadd float %267, %262 %269 = fmul float %214, %199 %270 = fadd float %269, %264 %271 = fmul float %29, %185 %272 = fdiv float 1.000000e+00, %271 %273 = fmul float %96, %272 %274 = fmul float %97, %272 %275 = bitcast float %273 to i32 %276 = bitcast float %274 to i32 %277 = insertelement <2 x i32> undef, i32 %275, i32 0 %278 = insertelement <2 x i32> %277, i32 %276, i32 1 %279 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %278, <32 x i8> %74, <16 x i8> %76, i32 2) %280 = extractelement <4 x float> %279, i32 0 %281 = extractelement <4 x float> %279, i32 1 %282 = extractelement <4 x float> %279, i32 2 %283 = fmul float %280, 2.000000e+00 %284 = fadd float %283, 0xBFF0100000000000 %285 = fmul float %281, 2.000000e+00 %286 = fadd float %285, 0xBFF0100000000000 %287 = fmul float %30, %185 %288 = fdiv float 1.000000e+00, %287 %289 = fmul float %96, %288 %290 = fmul float %98, %288 %291 = bitcast float %289 to i32 %292 = bitcast float %290 to i32 %293 = insertelement <2 x i32> undef, i32 %291, i32 0 %294 = insertelement <2 x i32> %293, i32 %292, i32 1 %295 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %294, <32 x i8> %78, <16 x i8> %80, i32 2) %296 = extractelement <4 x float> %295, i32 0 %297 = extractelement <4 x float> %295, i32 1 %298 = extractelement <4 x float> %295, i32 2 %299 = fmul float %296, 2.000000e+00 %300 = fadd float %299, 0xBFF0100000000000 %301 = fmul float %297, 2.000000e+00 %302 = fadd float %301, 0xBFF0100000000000 %303 = fmul float %30, %185 %304 = fdiv float 1.000000e+00, %303 %305 = fmul float %96, %304 %306 = fmul float %98, %304 %307 = bitcast float %305 to i32 %308 = bitcast float %306 to i32 %309 = insertelement <2 x i32> undef, i32 %307, i32 0 %310 = insertelement <2 x i32> %309, i32 %308, i32 1 %311 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %310, <32 x i8> %82, <16 x i8> %84, i32 2) %312 = extractelement <4 x float> %311, i32 0 %313 = extractelement <4 x float> %311, i32 1 %314 = extractelement <4 x float> %311, i32 2 %315 = fmul float %312, 2.000000e+00 %316 = fadd float %315, 0xBFF0100000000000 %317 = fmul float %313, 2.000000e+00 %318 = fadd float %317, 0xBFF0100000000000 %319 = fmul float %31, %185 %320 = fdiv float 1.000000e+00, %319 %321 = fmul float %98, %320 %322 = fmul float %97, %320 %323 = bitcast float %321 to i32 %324 = bitcast float %322 to i32 %325 = insertelement <2 x i32> undef, i32 %323, i32 0 %326 = insertelement <2 x i32> %325, i32 %324, i32 1 %327 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %326, <32 x i8> %86, <16 x i8> %88, i32 2) %328 = extractelement <4 x float> %327, i32 0 %329 = extractelement <4 x float> %327, i32 1 %330 = extractelement <4 x float> %327, i32 2 %331 = fmul float %328, 2.000000e+00 %332 = fadd float %331, 0xBFF0100000000000 %333 = fmul float %329, 2.000000e+00 %334 = fadd float %333, 0xBFF0100000000000 %335 = fadd float %187, %188 %336 = fadd float %335, %189 %337 = fdiv float 1.000000e+00, %336 %338 = fmul float %187, %337 %339 = fmul float %188, %337 %340 = fmul float %189, %337 %341 = fcmp ugt float %99, 0.000000e+00 %342 = select i1 %341, float 1.000000e+00, float %99 %343 = fcmp uge float %342, 0.000000e+00 %344 = select i1 %343, float %342, float -1.000000e+00 %345 = fmul float %330, %344 %346 = fmul float %334, %344 %347 = fmul float %332, %344 %348 = fcmp uge float 1.000000e+00, %202 %349 = select i1 %348, float %202, float 1.000000e+00 %350 = call float @llvm.AMDGPU.lrp(float %349, float %300, float %316) %351 = call float @llvm.AMDGPU.lrp(float %349, float %302, float %318) %352 = call float @llvm.AMDGPU.lrp(float %349, float %298, float %314) %353 = fcmp ugt float %100, 0.000000e+00 %354 = select i1 %353, float 1.000000e+00, float %100 %355 = fcmp uge float %354, 0.000000e+00 %356 = select i1 %355, float %354, float -1.000000e+00 %357 = fmul float %350, %356 %358 = fmul float %352, %356 %359 = fmul float %351, %356 %360 = fcmp ugt float %101, 0.000000e+00 %361 = select i1 %360, float 1.000000e+00, float %101 %362 = fcmp uge float %361, 0.000000e+00 %363 = select i1 %362, float %361, float -1.000000e+00 %364 = fmul float %284, %363 %365 = fmul float %286, %363 %366 = fmul float %282, %363 %367 = fmul float %364, %340 %368 = fmul float %365, %340 %369 = fmul float %366, %340 %370 = fmul float %357, %339 %371 = fadd float %370, %367 %372 = fmul float %358, %339 %373 = fadd float %372, %368 %374 = fmul float %359, %339 %375 = fadd float %374, %369 %376 = fmul float %345, %338 %377 = fadd float %376, %371 %378 = fmul float %346, %338 %379 = fadd float %378, %373 %380 = fmul float %347, %338 %381 = fadd float %380, %375 %382 = fcmp olt float %186, %35 %383 = sext i1 %382 to i32 %384 = bitcast i32 %383 to float %385 = bitcast float %384 to i32 %386 = icmp ne i32 %385, 0 br i1 %386, label %IF, label %ENDIF IF: ; preds = %main_body %387 = fmul float %185, 5.000000e-01 %388 = call float @fabs(float %99) %389 = call float @fabs(float %100) %390 = call float @fabs(float %101) %391 = fadd float %388, 0x3F50624DE0000000 %392 = fadd float %389, 0x3F50624DE0000000 %393 = fadd float %390, 0x3F50624DE0000000 %394 = call float @llvm.pow.f32(float %391, float %32) %395 = call float @llvm.pow.f32(float %392, float %32) %396 = call float @llvm.pow.f32(float %393, float %32) %397 = fadd float %394, %395 %398 = fadd float %397, %396 %399 = fdiv float 1.000000e+00, %398 %400 = fmul float %394, %399 %401 = fmul float %395, %399 %402 = fmul float %396, %399 %403 = fmul float %29, %387 %404 = fdiv float 1.000000e+00, %403 %405 = fmul float %96, %404 %406 = fmul float %97, %404 %407 = bitcast float %405 to i32 %408 = bitcast float %406 to i32 %409 = insertelement <2 x i32> undef, i32 %407, i32 0 %410 = insertelement <2 x i32> %409, i32 %408, i32 1 %411 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %410, <32 x i8> %74, <16 x i8> %76, i32 2) %412 = extractelement <4 x float> %411, i32 0 %413 = extractelement <4 x float> %411, i32 1 %414 = extractelement <4 x float> %411, i32 2 %415 = fmul float %412, 2.000000e+00 %416 = fadd float %415, 0xBFF0100000000000 %417 = fmul float %413, 2.000000e+00 %418 = fadd float %417, 0xBFF0100000000000 %419 = fmul float %30, %387 %420 = fdiv float 1.000000e+00, %419 %421 = fmul float %96, %420 %422 = fmul float %98, %420 %423 = bitcast float %421 to i32 %424 = bitcast float %422 to i32 %425 = insertelement <2 x i32> undef, i32 %423, i32 0 %426 = insertelement <2 x i32> %425, i32 %424, i32 1 %427 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %426, <32 x i8> %78, <16 x i8> %80, i32 2) %428 = extractelement <4 x float> %427, i32 0 %429 = extractelement <4 x float> %427, i32 1 %430 = extractelement <4 x float> %427, i32 2 %431 = fmul float %428, 2.000000e+00 %432 = fadd float %431, 0xBFF0100000000000 %433 = fmul float %429, 2.000000e+00 %434 = fadd float %433, 0xBFF0100000000000 %435 = fmul float %30, %387 %436 = fdiv float 1.000000e+00, %435 %437 = fmul float %96, %436 %438 = fmul float %98, %436 %439 = bitcast float %437 to i32 %440 = bitcast float %438 to i32 %441 = insertelement <2 x i32> undef, i32 %439, i32 0 %442 = insertelement <2 x i32> %441, i32 %440, i32 1 %443 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %442, <32 x i8> %82, <16 x i8> %84, i32 2) %444 = extractelement <4 x float> %443, i32 0 %445 = extractelement <4 x float> %443, i32 1 %446 = extractelement <4 x float> %443, i32 2 %447 = fmul float %444, 2.000000e+00 %448 = fadd float %447, 0xBFF0100000000000 %449 = fmul float %445, 2.000000e+00 %450 = fadd float %449, 0xBFF0100000000000 %451 = fmul float %31, %387 %452 = fdiv float 1.000000e+00, %451 %453 = fmul float %98, %452 %454 = fmul float %97, %452 %455 = bitcast float %453 to i32 %456 = bitcast float %454 to i32 %457 = insertelement <2 x i32> undef, i32 %455, i32 0 %458 = insertelement <2 x i32> %457, i32 %456, i32 1 %459 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %458, <32 x i8> %86, <16 x i8> %88, i32 2) %460 = extractelement <4 x float> %459, i32 0 %461 = extractelement <4 x float> %459, i32 1 %462 = extractelement <4 x float> %459, i32 2 %463 = fmul float %460, 2.000000e+00 %464 = fadd float %463, 0xBFF0100000000000 %465 = fmul float %461, 2.000000e+00 %466 = fadd float %465, 0xBFF0100000000000 %467 = fadd float %388, %389 %468 = fadd float %467, %390 %469 = fdiv float 1.000000e+00, %468 %470 = fmul float %388, %469 %471 = fmul float %389, %469 %472 = fmul float %390, %469 %473 = fdiv float 1.000000e+00, %35 %474 = fmul float %186, %473 %475 = call float @llvm.AMDIL.clamp.(float %474, float 0.000000e+00, float 1.000000e+00) %476 = fmul float 2.000000e+00, %475 %477 = fsub float -0.000000e+00, %476 %478 = fadd float 3.000000e+00, %477 %479 = fmul float %475, %478 %480 = fmul float %475, %479 %481 = fmul float %89, 2.000000e+00 %482 = fmul float %31, %387 %483 = fdiv float 1.000000e+00, %482 %484 = fmul float %98, %483 %485 = fmul float %97, %483 %486 = bitcast float %484 to i32 %487 = bitcast float %485 to i32 %488 = insertelement <2 x i32> undef, i32 %486, i32 0 %489 = insertelement <2 x i32> %488, i32 %487, i32 1 %490 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %489, <32 x i8> %70, <16 x i8> %72, i32 2) %491 = extractelement <4 x float> %490, i32 0 %492 = extractelement <4 x float> %490, i32 1 %493 = extractelement <4 x float> %490, i32 2 %494 = fmul float %30, %387 %495 = fdiv float 1.000000e+00, %494 %496 = fmul float %96, %495 %497 = fmul float %98, %495 %498 = bitcast float %496 to i32 %499 = bitcast float %497 to i32 %500 = insertelement <2 x i32> undef, i32 %498, i32 0 %501 = insertelement <2 x i32> %500, i32 %499, i32 1 %502 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %501, <32 x i8> %66, <16 x i8> %68, i32 2) %503 = extractelement <4 x float> %502, i32 0 %504 = extractelement <4 x float> %502, i32 1 %505 = extractelement <4 x float> %502, i32 2 %506 = fmul float %30, %387 %507 = fdiv float 1.000000e+00, %506 %508 = fmul float %96, %507 %509 = fmul float %98, %507 %510 = bitcast float %508 to i32 %511 = bitcast float %509 to i32 %512 = insertelement <2 x i32> undef, i32 %510, i32 0 %513 = insertelement <2 x i32> %512, i32 %511, i32 1 %514 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %513, <32 x i8> %62, <16 x i8> %64, i32 2) %515 = extractelement <4 x float> %514, i32 0 %516 = extractelement <4 x float> %514, i32 1 %517 = extractelement <4 x float> %514, i32 2 %518 = fcmp uge float 1.000000e+00, %481 %519 = select i1 %518, float %481, float 1.000000e+00 %520 = call float @llvm.AMDGPU.lrp(float %519, float %515, float %503) %521 = call float @llvm.AMDGPU.lrp(float %519, float %516, float %504) %522 = call float @llvm.AMDGPU.lrp(float %519, float %517, float %505) %523 = fmul float %29, %387 %524 = fdiv float 1.000000e+00, %523 %525 = fmul float %96, %524 %526 = fmul float %97, %524 %527 = bitcast float %525 to i32 %528 = bitcast float %526 to i32 %529 = insertelement <2 x i32> undef, i32 %527, i32 0 %530 = insertelement <2 x i32> %529, i32 %528, i32 1 %531 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %530, <32 x i8> %58, <16 x i8> %60, i32 2) %532 = extractelement <4 x float> %531, i32 0 %533 = extractelement <4 x float> %531, i32 1 %534 = extractelement <4 x float> %531, i32 2 %535 = extractelement <4 x float> %531, i32 3 %536 = fmul float %532, %402 %537 = fmul float %533, %402 %538 = fmul float %534, %402 %539 = fmul float %520, %401 %540 = fadd float %539, %536 %541 = fmul float %521, %401 %542 = fadd float %541, %537 %543 = fmul float %522, %401 %544 = fadd float %543, %538 %545 = fmul float %491, %400 %546 = fadd float %545, %540 %547 = fmul float %492, %400 %548 = fadd float %547, %542 %549 = fmul float %493, %400 %550 = fadd float %549, %544 %551 = call float @llvm.AMDGPU.lrp(float %480, float %266, float %546) %552 = call float @llvm.AMDGPU.lrp(float %480, float %268, float %548) %553 = call float @llvm.AMDGPU.lrp(float %480, float %270, float %550) %554 = fcmp ugt float %99, 0.000000e+00 %555 = select i1 %554, float 1.000000e+00, float %99 %556 = fcmp uge float %555, 0.000000e+00 %557 = select i1 %556, float %555, float -1.000000e+00 %558 = fmul float %462, %557 %559 = fmul float %466, %557 %560 = fmul float %464, %557 %561 = fcmp uge float 1.000000e+00, %481 %562 = select i1 %561, float %481, float 1.000000e+00 %563 = call float @llvm.AMDGPU.lrp(float %562, float %432, float %448) %564 = call float @llvm.AMDGPU.lrp(float %562, float %434, float %450) %565 = call float @llvm.AMDGPU.lrp(float %562, float %430, float %446) %566 = fcmp ugt float %100, 0.000000e+00 %567 = select i1 %566, float 1.000000e+00, float %100 %568 = fcmp uge float %567, 0.000000e+00 %569 = select i1 %568, float %567, float -1.000000e+00 %570 = fmul float %563, %569 %571 = fmul float %565, %569 %572 = fmul float %564, %569 %573 = fcmp ugt float %101, 0.000000e+00 %574 = select i1 %573, float 1.000000e+00, float %101 %575 = fcmp uge float %574, 0.000000e+00 %576 = select i1 %575, float %574, float -1.000000e+00 %577 = fmul float %416, %576 %578 = fmul float %418, %576 %579 = fmul float %414, %576 %580 = fmul float %577, %472 %581 = fmul float %578, %472 %582 = fmul float %579, %472 %583 = fmul float %570, %471 %584 = fadd float %583, %580 %585 = fmul float %571, %471 %586 = fadd float %585, %581 %587 = fmul float %572, %471 %588 = fadd float %587, %582 %589 = fmul float %558, %470 %590 = fadd float %589, %584 %591 = fmul float %559, %470 %592 = fadd float %591, %586 %593 = fmul float %560, %470 %594 = fadd float %593, %588 %595 = call float @llvm.AMDGPU.lrp(float %480, float %377, float %590) %596 = call float @llvm.AMDGPU.lrp(float %480, float %379, float %592) %597 = call float @llvm.AMDGPU.lrp(float %480, float %381, float %594) br label %ENDIF ENDIF: ; preds = %main_body, %IF %temp30.0 = phi float [ %597, %IF ], [ %381, %main_body ] %temp29.0 = phi float [ %596, %IF ], [ %379, %main_body ] %temp28.0 = phi float [ %595, %IF ], [ %377, %main_body ] %temp26.0 = phi float [ %553, %IF ], [ %270, %main_body ] %temp25.0 = phi float [ %552, %IF ], [ %268, %main_body ] %temp24.0 = phi float [ %551, %IF ], [ %266, %main_body ] %temp3.0 = phi float [ %535, %IF ], [ 0.000000e+00, %main_body ] %598 = fmul float %temp24.0, %90 %599 = fmul float %temp25.0, %91 %600 = fmul float %temp26.0, %92 %601 = fmul float %36, %temp28.0 %602 = fmul float %37, %temp28.0 %603 = fmul float %38, %temp28.0 %604 = fmul float %39, %temp29.0 %605 = fadd float %604, %601 %606 = fmul float %40, %temp29.0 %607 = fadd float %606, %602 %608 = fmul float %41, %temp29.0 %609 = fadd float %608, %603 %610 = fmul float %42, %temp30.0 %611 = fadd float %610, %605 %612 = fmul float %43, %temp30.0 %613 = fadd float %612, %607 %614 = fmul float %44, %temp30.0 %615 = fadd float %614, %609 %616 = fmul float %611, %611 %617 = fmul float %613, %613 %618 = fadd float %617, %616 %619 = fmul float %615, %615 %620 = fadd float %618, %619 %621 = call float @llvm.AMDGPU.rsq(float %620) %622 = fmul float %611, %621 %623 = fmul float %613, %621 %624 = fmul float %615, %621 %625 = shl i32 14, 4 %626 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %625) %627 = shl i32 14, 4 %628 = add i32 %627, 4 %629 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %628) %630 = shl i32 14, 4 %631 = add i32 %630, 8 %632 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %631) %633 = shl i32 13, 4 %634 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %633) %635 = shl i32 13, 4 %636 = add i32 %635, 4 %637 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %636) %638 = shl i32 13, 4 %639 = add i32 %638, 8 %640 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %639) %641 = shl i32 12, 4 %642 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %641) %643 = shl i32 12, 4 %644 = add i32 %643, 4 %645 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %644) %646 = shl i32 12, 4 %647 = add i32 %646, 8 %648 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %647) %649 = fmul float %642, %93 %650 = fmul float %645, %93 %651 = fmul float %648, %93 %652 = fmul float %634, %94 %653 = fadd float %652, %649 %654 = fmul float %637, %94 %655 = fadd float %654, %650 %656 = fmul float %640, %94 %657 = fadd float %656, %651 %658 = fmul float %626, %95 %659 = fadd float %658, %653 %660 = fmul float %629, %95 %661 = fadd float %660, %655 %662 = fmul float %632, %95 %663 = fadd float %662, %657 %664 = shl i32 15, 4 %665 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %664) %666 = shl i32 15, 4 %667 = add i32 %666, 4 %668 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %667) %669 = shl i32 15, 4 %670 = add i32 %669, 8 %671 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %670) %672 = fadd float %659, %665 %673 = fadd float %661, %668 %674 = fadd float %663, %671 %675 = shl i32 20, 4 %676 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %675) %677 = shl i32 20, 4 %678 = add i32 %677, 4 %679 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %678) %680 = shl i32 20, 4 %681 = add i32 %680, 8 %682 = call float @llvm.SI.load.const(<16 x i8> %46, i32 %681) %683 = fsub float -0.000000e+00, %676 %684 = fadd float %672, %683 %685 = fsub float -0.000000e+00, %679 %686 = fadd float %673, %685 %687 = fsub float -0.000000e+00, %682 %688 = fadd float %674, %687 %689 = fmul float %684, %684 %690 = fmul float %686, %686 %691 = fadd float %690, %689 %692 = fmul float %688, %688 %693 = fadd float %691, %692 %694 = call float @llvm.AMDGPU.rsq(float %693) %695 = fmul float %684, %694 %696 = fmul float %686, %694 %697 = fmul float %688, %694 %698 = fmul float %622, %695 %699 = fmul float %623, %696 %700 = fadd float %699, %698 %701 = fmul float %624, %697 %702 = fadd float %700, %701 %703 = fmul float %702, %622 %704 = fmul float %702, %623 %705 = fmul float %702, %624 %706 = fmul float 2.000000e+00, %703 %707 = fmul float 2.000000e+00, %704 %708 = fmul float 2.000000e+00, %705 %709 = fsub float -0.000000e+00, %706 %710 = fadd float %695, %709 %711 = fsub float -0.000000e+00, %707 %712 = fadd float %696, %711 %713 = fsub float -0.000000e+00, %708 %714 = fadd float %697, %713 %715 = fadd float %623, 0x3FF0CCCCC0000000 %716 = call float @llvm.AMDIL.clamp.(float %715, float 0.000000e+00, float 1.000000e+00) %717 = shl i32 14, 4 %718 = call float @llvm.SI.load.const(<16 x i8> %48, i32 %717) %719 = shl i32 14, 4 %720 = add i32 %719, 4 %721 = call float @llvm.SI.load.const(<16 x i8> %48, i32 %720) %722 = shl i32 14, 4 %723 = add i32 %722, 8 %724 = call float @llvm.SI.load.const(<16 x i8> %48, i32 %723) %725 = fmul float %716, %718 %726 = fmul float %716, %721 %727 = fmul float %716, %724 %728 = fmul float %598, %725 %729 = fmul float %599, %726 %730 = fmul float %600, %727 %731 = shl i32 12, 4 %732 = call float @llvm.SI.load.const(<16 x i8> %48, i32 %731) %733 = shl i32 12, 4 %734 = add i32 %733, 4 %735 = call float @llvm.SI.load.const(<16 x i8> %48, i32 %734) %736 = shl i32 12, 4 %737 = add i32 %736, 8 %738 = call float @llvm.SI.load.const(<16 x i8> %48, i32 %737) %739 = shl i32 13, 4 %740 = call float @llvm.SI.load.const(<16 x i8> %48, i32 %739) %741 = shl i32 13, 4 %742 = add i32 %741, 4 %743 = call float @llvm.SI.load.const(<16 x i8> %48, i32 %742) %744 = shl i32 13, 4 %745 = add i32 %744, 8 %746 = call float @llvm.SI.load.const(<16 x i8> %48, i32 %745) %747 = fmul float %622, %732 %748 = fmul float %623, %735 %749 = fadd float %748, %747 %750 = fmul float %624, %738 %751 = fadd float %749, %750 %752 = fcmp uge float 0.000000e+00, %751 %753 = select i1 %752, float 0.000000e+00, float %751 %754 = fmul float %753, %740 %755 = fmul float %753, %743 %756 = fmul float %753, %746 %757 = fmul float %754, %598 %758 = fmul float %755, %599 %759 = fmul float %756, %600 %760 = fmul float %710, %732 %761 = fmul float %712, %735 %762 = fadd float %761, %760 %763 = fmul float %714, %738 %764 = fadd float %762, %763 %765 = fcmp uge float 0x3F50624DE0000000, %764 %766 = select i1 %765, float 0x3F50624DE0000000, float %764 %767 = call float @llvm.pow.f32(float %766, float %28) %768 = fmul float %767, %740 %769 = fmul float %767, %743 %770 = fmul float %767, %746 %771 = fmul float %768, %25 %772 = fadd float %771, %757 %773 = fmul float %769, %26 %774 = fadd float %773, %758 %775 = fmul float %770, %27 %776 = fadd float %775, %759 %777 = shl i32 15, 4 %778 = call float @llvm.SI.load.const(<16 x i8> %48, i32 %777) %779 = shl i32 15, 4 %780 = add i32 %779, 4 %781 = call float @llvm.SI.load.const(<16 x i8> %48, i32 %780) %782 = shl i32 15, 4 %783 = add i32 %782, 8 %784 = call float @llvm.SI.load.const(<16 x i8> %48, i32 %783) %785 = fsub float -0.000000e+00, %778 %786 = fadd float %672, %785 %787 = fsub float -0.000000e+00, %781 %788 = fadd float %673, %787 %789 = fsub float -0.000000e+00, %784 %790 = fadd float %674, %789 %791 = fmul float %786, %786 %792 = fmul float %788, %788 %793 = fadd float %792, %791 %794 = fmul float %790, %790 %795 = fadd float %793, %794 %796 = call float @llvm.AMDGPU.rsq(float %795) %797 = fmul float %796, %795 %798 = fsub float -0.000000e+00, %795 %799 = call float @llvm.AMDGPU.cndlt(float %798, float %797, float 0.000000e+00) %800 = shl i32 16, 4 %801 = call float @llvm.SI.load.const(<16 x i8> %48, i32 %800) %802 = fmul float 0x3FE99999A0000000, %801 %803 = fcmp olt float %799, %802 %804 = sext i1 %803 to i32 %805 = bitcast i32 %804 to float %806 = bitcast float %805 to i32 %807 = icmp ne i32 %806, 0 br i1 %807, label %IF219, label %ELSE220 IF219: ; preds = %ENDIF %808 = shl i32 6, 4 %809 = call float @llvm.SI.load.const(<16 x i8> %48, i32 %808) %810 = shl i32 6, 4 %811 = add i32 %810, 4 %812 = call float @llvm.SI.load.const(<16 x i8> %48, i32 %811) %813 = shl i32 6, 4 %814 = add i32 %813, 8 %815 = call float @llvm.SI.load.const(<16 x i8> %48, i32 %814) %816 = shl i32 5, 4 %817 = call float @llvm.SI.load.const(<16 x i8> %48, i32 %816) %818 = shl i32 5, 4 %819 = add i32 %818, 4 %820 = call float @llvm.SI.load.const(<16 x i8> %48, i32 %819) %821 = shl i32 5, 4 %822 = add i32 %821, 8 %823 = call float @llvm.SI.load.const(<16 x i8> %48, i32 %822) %824 = shl i32 4, 4 %825 = call float @llvm.SI.load.const(<16 x i8> %48, i32 %824) %826 = shl i32 4, 4 %827 = add i32 %826, 4 %828 = call float @llvm.SI.load.const(<16 x i8> %48, i32 %827) %829 = shl i32 4, 4 %830 = add i32 %829, 8 %831 = call float @llvm.SI.load.const(<16 x i8> %48, i32 %830) %832 = fmul float %825, %672 %833 = fmul float %828, %672 %834 = fmul float %831, %672 %835 = fmul float %817, %673 %836 = fadd float %835, %832 %837 = fmul float %820, %673 %838 = fadd float %837, %833 %839 = fmul float %823, %673 %840 = fadd float %839, %834 %841 = fmul float %809, %674 %842 = fadd float %841, %836 %843 = fmul float %812, %674 %844 = fadd float %843, %838 %845 = fmul float %815, %674 %846 = fadd float %845, %840 %847 = shl i32 7, 4 %848 = call float @llvm.SI.load.const(<16 x i8> %48, i32 %847) %849 = shl i32 7, 4 %850 = add i32 %849, 4 %851 = call float @llvm.SI.load.const(<16 x i8> %48, i32 %850) %852 = shl i32 7, 4 %853 = add i32 %852, 8 %854 = call float @llvm.SI.load.const(<16 x i8> %48, i32 %853) %855 = fadd float %842, %848 %856 = fadd float %844, %851 %857 = fadd float %846, %854 %858 = shl i32 15, 4 %859 = add i32 %858, 12 %860 = call float @llvm.SI.load.const(<16 x i8> %48, i32 %859) %861 = fcmp uge float %857, -1.000000e+00 %862 = select i1 %861, float %857, float -1.000000e+00 %863 = fcmp uge float %862, 1.000000e+00 %864 = select i1 %863, float 1.000000e+00, float %862 %865 = fadd float %864, 1.000000e+00 %866 = fsub float -0.000000e+00, %860 %867 = fmul float %866, %865 %868 = fmul float 0x3FE7154760000000, %867 %869 = call float @llvm.AMDIL.exp.(float %868) %870 = fmul float %855, 5.000000e-01 %871 = fadd float %870, 5.000000e-01 %872 = fmul float %856, 5.000000e-01 %873 = fadd float %872, 5.000000e-01 %874 = shl i32 16, 4 %875 = add i32 %874, 8 %876 = call float @llvm.SI.load.const(<16 x i8> %48, i32 %875) %877 = fmul float %871, %876 %878 = fmul float %873, %876 %879 = bitcast float %877 to i32 %880 = bitcast float %878 to i32 %881 = insertelement <2 x i32> undef, i32 %879, i32 0 %882 = insertelement <2 x i32> %881, i32 %880, i32 1 %883 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %882, <32 x i8> %50, <16 x i8> %52, i32 5) %884 = extractelement <4 x float> %883, i32 0 %885 = fmul float %869, %884 %886 = call float @llvm.AMDIL.clamp.(float %885, float 0.000000e+00, float 1.000000e+00) br label %ENDIF218 ELSE220: ; preds = %ENDIF %887 = shl i32 16, 4 %888 = call float @llvm.SI.load.const(<16 x i8> %48, i32 %887) %889 = fcmp olt float %888, %799 %890 = sext i1 %889 to i32 %891 = bitcast i32 %890 to float %892 = bitcast float %891 to i32 %893 = icmp ne i32 %892, 0 br i1 %893, label %IF241, label %ELSE242 ENDIF218: ; preds = %IF241, %ELSE242, %IF219 %temp28.1 = phi float [ %886, %IF219 ], [ %1027, %IF241 ], [ %1195, %ELSE242 ] %894 = fadd float %temp28.1, 0xBFE99999A0000000 %895 = fmul float %894, 0x4014000020000000 %896 = call float @llvm.AMDIL.clamp.(float %895, float 0.000000e+00, float 1.000000e+00) %897 = fmul float 2.000000e+00, %896 %898 = fsub float -0.000000e+00, %897 %899 = fadd float 3.000000e+00, %898 %900 = fmul float %896, %899 %901 = fmul float %896, %900 %902 = fmul float %772, %901 %903 = fmul float %774, %901 %904 = fmul float %776, %901 %905 = fadd float %728, %902 %906 = fadd float %729, %903 %907 = fadd float %730, %904 %908 = bitcast float %24 to i32 %909 = fsub float -0.000000e+00, %672 %910 = fsub float -0.000000e+00, %673 %911 = fsub float -0.000000e+00, %674 br label %LOOP IF241: ; preds = %ELSE220 %912 = shl i32 10, 4 %913 = call float @llvm.SI.load.const(<16 x i8> %48, i32 %912) %914 = shl i32 10, 4 %915 = add i32 %914, 4 %916 = call float @llvm.SI.load.const(<16 x i8> %48, i32 %915) %917 = shl i32 10, 4 %918 = add i32 %917, 8 %919 = call float @llvm.SI.load.const(<16 x i8> %48, i32 %918) %920 = shl i32 9, 4 %921 = call float @llvm.SI.load.const(<16 x i8> %48, i32 %920) %922 = shl i32 9, 4 %923 = add i32 %922, 4 %924 = call float @llvm.SI.load.const(<16 x i8> %48, i32 %923) %925 = shl i32 9, 4 %926 = add i32 %925, 8 %927 = call float @llvm.SI.load.const(<16 x i8> %48, i32 %926) %928 = shl i32 8, 4 %929 = call float @llvm.SI.load.const(<16 x i8> %48, i32 %928) %930 = shl i32 8, 4 %931 = add i32 %930, 4 %932 = call float @llvm.SI.load.const(<16 x i8> %48, i32 %931) %933 = shl i32 8, 4 %934 = add i32 %933, 8 %935 = call float @llvm.SI.load.const(<16 x i8> %48, i32 %934) %936 = fmul float %929, %672 %937 = fmul float %932, %672 %938 = fmul float %935, %672 %939 = fmul float %921, %673 %940 = fadd float %939, %936 %941 = fmul float %924, %673 %942 = fadd float %941, %937 %943 = fmul float %927, %673 %944 = fadd float %943, %938 %945 = fmul float %913, %674 %946 = fadd float %945, %940 %947 = fmul float %916, %674 %948 = fadd float %947, %942 %949 = fmul float %919, %674 %950 = fadd float %949, %944 %951 = shl i32 11, 4 %952 = call float @llvm.SI.load.const(<16 x i8> %48, i32 %951) %953 = shl i32 11, 4 %954 = add i32 %953, 4 %955 = call float @llvm.SI.load.const(<16 x i8> %48, i32 %954) %956 = shl i32 11, 4 %957 = add i32 %956, 8 %958 = call float @llvm.SI.load.const(<16 x i8> %48, i32 %957) %959 = fadd float %946, %952 %960 = fadd float %948, %955 %961 = fadd float %950, %958 %962 = shl i32 15, 4 %963 = call float @llvm.SI.load.const(<16 x i8> %48, i32 %962) %964 = shl i32 15, 4 %965 = add i32 %964, 4 %966 = call float @llvm.SI.load.const(<16 x i8> %48, i32 %965) %967 = shl i32 15, 4 %968 = add i32 %967, 8 %969 = call float @llvm.SI.load.const(<16 x i8> %48, i32 %968) %970 = fsub float -0.000000e+00, %963 %971 = fadd float %672, %970 %972 = fsub float -0.000000e+00, %966 %973 = fadd float %673, %972 %974 = fsub float -0.000000e+00, %969 %975 = fadd float %674, %974 %976 = fmul float %971, %971 %977 = fmul float %973, %973 %978 = fadd float %977, %976 %979 = fmul float %975, %975 %980 = fadd float %978, %979 %981 = call float @llvm.AMDGPU.rsq(float %980) %982 = fmul float %981, %980 %983 = fsub float -0.000000e+00, %980 %984 = call float @llvm.AMDGPU.cndlt(float %983, float %982, float 0.000000e+00) %985 = shl i32 16, 4 %986 = add i32 %985, 4 %987 = call float @llvm.SI.load.const(<16 x i8> %48, i32 %986) %988 = fdiv float 1.000000e+00, %987 %989 = fmul float %984, %988 %990 = fadd float %989, 0xBFE99999A0000000 %991 = fmul float %990, 0x4014000020000000 %992 = call float @llvm.AMDIL.clamp.(float %991, float 0.000000e+00, float 1.000000e+00) %993 = shl i32 15, 4 %994 = add i32 %993, 12 %995 = call float @llvm.SI.load.const(<16 x i8> %48, i32 %994) %996 = fcmp uge float %961, -1.000000e+00 %997 = select i1 %996, float %961, float -1.000000e+00 %998 = fcmp uge float %997, 1.000000e+00 %999 = select i1 %998, float 1.000000e+00, float %997 %1000 = fadd float %999, 1.000000e+00 %1001 = fsub float -0.000000e+00, %995 %1002 = fmul float %1001, %1000 %1003 = fmul float 0x3FE7154760000000, %1002 %1004 = call float @llvm.AMDIL.exp.(float %1003) %1005 = fmul float %959, 5.000000e-01 %1006 = fadd float %1005, 5.000000e-01 %1007 = fmul float %960, 5.000000e-01 %1008 = fadd float %1007, 5.000000e-01 %1009 = shl i32 16, 4 %1010 = add i32 %1009, 8 %1011 = call float @llvm.SI.load.const(<16 x i8> %48, i32 %1010) %1012 = fmul float %1006, %1011 %1013 = fmul float %1008, %1011 %1014 = bitcast float %1012 to i32 %1015 = bitcast float %1013 to i32 %1016 = insertelement <2 x i32> undef, i32 %1014, i32 0 %1017 = insertelement <2 x i32> %1016, i32 %1015, i32 1 %1018 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1017, <32 x i8> %54, <16 x i8> %56, i32 5) %1019 = extractelement <4 x float> %1018, i32 0 %1020 = fmul float %1004, %1019 %1021 = call float @llvm.AMDIL.clamp.(float %1020, float 0.000000e+00, float 1.000000e+00) %1022 = fmul float 2.000000e+00, %992 %1023 = fsub float -0.000000e+00, %1022 %1024 = fadd float 3.000000e+00, %1023 %1025 = fmul float %992, %1024 %1026 = fmul float %992, %1025 %1027 = call float @llvm.AMDGPU.lrp(float %1026, float 1.000000e+00, float %1021) br label %ENDIF218 ELSE242: ; preds = %ELSE220 %1028 = shl i32 6, 4 %1029 = call float @llvm.SI.load.const(<16 x i8> %48, i32 %1028) %1030 = shl i32 6, 4 %1031 = add i32 %1030, 4 %1032 = call float @llvm.SI.load.const(<16 x i8> %48, i32 %1031) %1033 = shl i32 6, 4 %1034 = add i32 %1033, 8 %1035 = call float @llvm.SI.load.const(<16 x i8> %48, i32 %1034) %1036 = shl i32 5, 4 %1037 = call float @llvm.SI.load.const(<16 x i8> %48, i32 %1036) %1038 = shl i32 5, 4 %1039 = add i32 %1038, 4 %1040 = call float @llvm.SI.load.const(<16 x i8> %48, i32 %1039) %1041 = shl i32 5, 4 %1042 = add i32 %1041, 8 %1043 = call float @llvm.SI.load.const(<16 x i8> %48, i32 %1042) %1044 = shl i32 4, 4 %1045 = call float @llvm.SI.load.const(<16 x i8> %48, i32 %1044) %1046 = shl i32 4, 4 %1047 = add i32 %1046, 4 %1048 = call float @llvm.SI.load.const(<16 x i8> %48, i32 %1047) %1049 = shl i32 4, 4 %1050 = add i32 %1049, 8 %1051 = call float @llvm.SI.load.const(<16 x i8> %48, i32 %1050) %1052 = fmul float %1045, %672 %1053 = fmul float %1048, %672 %1054 = fmul float %1051, %672 %1055 = fmul float %1037, %673 %1056 = fadd float %1055, %1052 %1057 = fmul float %1040, %673 %1058 = fadd float %1057, %1053 %1059 = fmul float %1043, %673 %1060 = fadd float %1059, %1054 %1061 = fmul float %1029, %674 %1062 = fadd float %1061, %1056 %1063 = fmul float %1032, %674 %1064 = fadd float %1063, %1058 %1065 = fmul float %1035, %674 %1066 = fadd float %1065, %1060 %1067 = shl i32 7, 4 %1068 = call float @llvm.SI.load.const(<16 x i8> %48, i32 %1067) %1069 = shl i32 7, 4 %1070 = add i32 %1069, 4 %1071 = call float @llvm.SI.load.const(<16 x i8> %48, i32 %1070) %1072 = shl i32 7, 4 %1073 = add i32 %1072, 8 %1074 = call float @llvm.SI.load.const(<16 x i8> %48, i32 %1073) %1075 = fadd float %1062, %1068 %1076 = fadd float %1064, %1071 %1077 = fadd float %1066, %1074 %1078 = shl i32 10, 4 %1079 = call float @llvm.SI.load.const(<16 x i8> %48, i32 %1078) %1080 = shl i32 10, 4 %1081 = add i32 %1080, 4 %1082 = call float @llvm.SI.load.const(<16 x i8> %48, i32 %1081) %1083 = shl i32 10, 4 %1084 = add i32 %1083, 8 %1085 = call float @llvm.SI.load.const(<16 x i8> %48, i32 %1084) %1086 = shl i32 9, 4 %1087 = call float @llvm.SI.load.const(<16 x i8> %48, i32 %1086) %1088 = shl i32 9, 4 %1089 = add i32 %1088, 4 %1090 = call float @llvm.SI.load.const(<16 x i8> %48, i32 %1089) %1091 = shl i32 9, 4 %1092 = add i32 %1091, 8 %1093 = call float @llvm.SI.load.const(<16 x i8> %48, i32 %1092) %1094 = shl i32 8, 4 %1095 = call float @llvm.SI.load.const(<16 x i8> %48, i32 %1094) %1096 = shl i32 8, 4 %1097 = add i32 %1096, 4 %1098 = call float @llvm.SI.load.const(<16 x i8> %48, i32 %1097) %1099 = shl i32 8, 4 %1100 = add i32 %1099, 8 %1101 = call float @llvm.SI.load.const(<16 x i8> %48, i32 %1100) %1102 = fmul float %1095, %672 %1103 = fmul float %1098, %672 %1104 = fmul float %1101, %672 %1105 = fmul float %1087, %673 %1106 = fadd float %1105, %1102 %1107 = fmul float %1090, %673 %1108 = fadd float %1107, %1103 %1109 = fmul float %1093, %673 %1110 = fadd float %1109, %1104 %1111 = fmul float %1079, %674 %1112 = fadd float %1111, %1106 %1113 = fmul float %1082, %674 %1114 = fadd float %1113, %1108 %1115 = fmul float %1085, %674 %1116 = fadd float %1115, %1110 %1117 = shl i32 11, 4 %1118 = call float @llvm.SI.load.const(<16 x i8> %48, i32 %1117) %1119 = shl i32 11, 4 %1120 = add i32 %1119, 4 %1121 = call float @llvm.SI.load.const(<16 x i8> %48, i32 %1120) %1122 = shl i32 11, 4 %1123 = add i32 %1122, 8 %1124 = call float @llvm.SI.load.const(<16 x i8> %48, i32 %1123) %1125 = fadd float %1112, %1118 %1126 = fadd float %1114, %1121 %1127 = fadd float %1116, %1124 %1128 = shl i32 16, 4 %1129 = call float @llvm.SI.load.const(<16 x i8> %48, i32 %1128) %1130 = fmul float 0x3FE99999A0000000, %1129 %1131 = fsub float -0.000000e+00, %1130 %1132 = fadd float %799, %1131 %1133 = fsub float -0.000000e+00, %1130 %1134 = fadd float %1129, %1133 %1135 = fdiv float 1.000000e+00, %1134 %1136 = fmul float %1132, %1135 %1137 = call float @llvm.AMDIL.clamp.(float %1136, float 0.000000e+00, float 1.000000e+00) %1138 = shl i32 15, 4 %1139 = add i32 %1138, 12 %1140 = call float @llvm.SI.load.const(<16 x i8> %48, i32 %1139) %1141 = shl i32 16, 4 %1142 = add i32 %1141, 8 %1143 = call float @llvm.SI.load.const(<16 x i8> %48, i32 %1142) %1144 = fcmp uge float %1077, -1.000000e+00 %1145 = select i1 %1144, float %1077, float -1.000000e+00 %1146 = fcmp uge float %1145, 1.000000e+00 %1147 = select i1 %1146, float 1.000000e+00, float %1145 %1148 = fadd float %1147, 1.000000e+00 %1149 = fsub float -0.000000e+00, %1140 %1150 = fmul float %1149, %1148 %1151 = fmul float 0x3FE7154760000000, %1150 %1152 = call float @llvm.AMDIL.exp.(float %1151) %1153 = fmul float %1075, 5.000000e-01 %1154 = fadd float %1153, 5.000000e-01 %1155 = fmul float %1076, 5.000000e-01 %1156 = fadd float %1155, 5.000000e-01 %1157 = fmul float %1154, %1143 %1158 = fmul float %1156, %1143 %1159 = bitcast float %1157 to i32 %1160 = bitcast float %1158 to i32 %1161 = insertelement <2 x i32> undef, i32 %1159, i32 0 %1162 = insertelement <2 x i32> %1161, i32 %1160, i32 1 %1163 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1162, <32 x i8> %50, <16 x i8> %52, i32 5) %1164 = extractelement <4 x float> %1163, i32 0 %1165 = fmul float %1152, %1164 %1166 = call float @llvm.AMDIL.clamp.(float %1165, float 0.000000e+00, float 1.000000e+00) %1167 = fcmp uge float %1127, -1.000000e+00 %1168 = select i1 %1167, float %1127, float -1.000000e+00 %1169 = fcmp uge float %1168, 1.000000e+00 %1170 = select i1 %1169, float 1.000000e+00, float %1168 %1171 = fadd float %1170, 1.000000e+00 %1172 = fsub float -0.000000e+00, %1140 %1173 = fmul float %1172, %1171 %1174 = fmul float 0x3FE7154760000000, %1173 %1175 = call float @llvm.AMDIL.exp.(float %1174) %1176 = fmul float %1125, 5.000000e-01 %1177 = fadd float %1176, 5.000000e-01 %1178 = fmul float %1126, 5.000000e-01 %1179 = fadd float %1178, 5.000000e-01 %1180 = fmul float %1177, %1143 %1181 = fmul float %1179, %1143 %1182 = bitcast float %1180 to i32 %1183 = bitcast float %1181 to i32 %1184 = insertelement <2 x i32> undef, i32 %1182, i32 0 %1185 = insertelement <2 x i32> %1184, i32 %1183, i32 1 %1186 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1185, <32 x i8> %54, <16 x i8> %56, i32 5) %1187 = extractelement <4 x float> %1186, i32 0 %1188 = fmul float %1175, %1187 %1189 = call float @llvm.AMDIL.clamp.(float %1188, float 0.000000e+00, float 1.000000e+00) %1190 = fmul float 2.000000e+00, %1137 %1191 = fsub float -0.000000e+00, %1190 %1192 = fadd float 3.000000e+00, %1191 %1193 = fmul float %1137, %1192 %1194 = fmul float %1137, %1193 %1195 = call float @llvm.AMDGPU.lrp(float %1194, float %1189, float %1166) br label %ENDIF218 LOOP: ; preds = %ENDIF300, %ENDIF218 %temp38.0 = phi float [ %907, %ENDIF218 ], [ %1321, %ENDIF300 ] %temp37.0 = phi float [ %906, %ENDIF218 ], [ %1320, %ENDIF300 ] %temp36.0 = phi float [ %905, %ENDIF218 ], [ %1319, %ENDIF300 ] %temp.0 = phi float [ 0.000000e+00, %ENDIF218 ], [ %1324, %ENDIF300 ] %1196 = bitcast float %temp.0 to i32 %1197 = icmp sge i32 %1196, %908 %1198 = sext i1 %1197 to i32 %1199 = bitcast i32 %1198 to float %1200 = bitcast float %1199 to i32 %1201 = icmp ne i32 %1200, 0 br i1 %1201, label %IF301, label %ENDIF300 IF301: ; preds = %LOOP %temp36.0.lcssa = phi float [ %temp36.0, %LOOP ] %temp37.0.lcssa = phi float [ %temp37.0, %LOOP ] %temp38.0.lcssa = phi float [ %temp38.0, %LOOP ] %1202 = call i32 @llvm.SI.packf16(float %temp36.0.lcssa, float %temp37.0.lcssa) %1203 = bitcast i32 %1202 to float %1204 = call i32 @llvm.SI.packf16(float %temp38.0.lcssa, float %temp3.0) %1205 = bitcast i32 %1204 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %1203, float %1205, float %1203, float %1205) ret void ENDIF300: ; preds = %LOOP %1206 = bitcast float %temp.0 to i32 %1207 = mul i32 %1206, 7 %1208 = bitcast i32 %1207 to float %1209 = bitcast float %1208 to i32 %1210 = shl i32 %1209, 4 %1211 = add i32 %1210, 64 %1212 = call float @llvm.SI.load.const(<16 x i8> %23, i32 %1211) %1213 = bitcast float %1208 to i32 %1214 = add i32 %1213, 1 %1215 = bitcast i32 %1214 to float %1216 = bitcast float %1215 to i32 %1217 = shl i32 %1216, 4 %1218 = add i32 %1217, 64 %1219 = call float @llvm.SI.load.const(<16 x i8> %23, i32 %1218) %1220 = bitcast float %1208 to i32 %1221 = add i32 %1220, 2 %1222 = bitcast i32 %1221 to float %1223 = bitcast float %1222 to i32 %1224 = shl i32 %1223, 4 %1225 = add i32 %1224, 64 %1226 = call float @llvm.SI.load.const(<16 x i8> %23, i32 %1225) %1227 = bitcast float %1208 to i32 %1228 = add i32 %1227, 3 %1229 = bitcast i32 %1228 to float %1230 = bitcast float %1229 to i32 %1231 = shl i32 %1230, 4 %1232 = add i32 %1231, 64 %1233 = call float @llvm.SI.load.const(<16 x i8> %23, i32 %1232) %1234 = bitcast float %1208 to i32 %1235 = add i32 %1234, 4 %1236 = bitcast i32 %1235 to float %1237 = bitcast float %1236 to i32 %1238 = shl i32 %1237, 4 %1239 = add i32 %1238, 64 %1240 = call float @llvm.SI.load.const(<16 x i8> %23, i32 %1239) %1241 = bitcast float %1208 to i32 %1242 = add i32 %1241, 5 %1243 = bitcast i32 %1242 to float %1244 = bitcast float %1243 to i32 %1245 = shl i32 %1244, 4 %1246 = add i32 %1245, 64 %1247 = call float @llvm.SI.load.const(<16 x i8> %23, i32 %1246) %1248 = bitcast float %1208 to i32 %1249 = add i32 %1248, 6 %1250 = bitcast i32 %1249 to float %1251 = bitcast float %1250 to i32 %1252 = shl i32 %1251, 4 %1253 = add i32 %1252, 64 %1254 = call float @llvm.SI.load.const(<16 x i8> %23, i32 %1253) %1255 = fadd float %1212, %909 %1256 = fadd float %1219, %910 %1257 = fadd float %1226, %911 %1258 = fmul float %1255, %1255 %1259 = fmul float %1256, %1256 %1260 = fadd float %1259, %1258 %1261 = fmul float %1257, %1257 %1262 = fadd float %1260, %1261 %1263 = call float @llvm.AMDGPU.rsq(float %1262) %1264 = fmul float %1263, %1262 %1265 = fsub float -0.000000e+00, %1262 %1266 = call float @llvm.AMDGPU.cndlt(float %1265, float %1264, float 0.000000e+00) %1267 = fdiv float 1.000000e+00, %1266 %1268 = fmul float %1255, %1267 %1269 = fmul float %1256, %1267 %1270 = fmul float %1257, %1267 %1271 = fmul float %622, %1268 %1272 = fmul float %623, %1269 %1273 = fadd float %1272, %1271 %1274 = fmul float %624, %1270 %1275 = fadd float %1273, %1274 %1276 = fcmp uge float 0.000000e+00, %1275 %1277 = select i1 %1276, float 0.000000e+00, float %1275 %1278 = fmul float %1277, %1233 %1279 = fmul float %1277, %1240 %1280 = fmul float %1277, %1247 %1281 = fmul float %1278, %598 %1282 = fmul float %1279, %599 %1283 = fmul float %1280, %600 %1284 = fmul float %710, %1268 %1285 = fmul float %712, %1269 %1286 = fadd float %1285, %1284 %1287 = fmul float %714, %1270 %1288 = fadd float %1286, %1287 %1289 = fcmp uge float 0x3F50624DE0000000, %1288 %1290 = select i1 %1289, float 0x3F50624DE0000000, float %1288 %1291 = call float @llvm.pow.f32(float %1290, float %28) %1292 = fmul float %1291, %1233 %1293 = fmul float %1291, %1240 %1294 = fmul float %1291, %1247 %1295 = fmul float %1292, %25 %1296 = fadd float %1295, %1281 %1297 = fmul float %1293, %26 %1298 = fadd float %1297, %1282 %1299 = fmul float %1294, %27 %1300 = fadd float %1299, %1283 %1301 = fmul float %1254, 5.000000e-01 %1302 = fsub float -0.000000e+00, %1301 %1303 = fadd float %1266, %1302 %1304 = fsub float -0.000000e+00, %1301 %1305 = fadd float %1254, %1304 %1306 = fdiv float 1.000000e+00, %1305 %1307 = fmul float %1303, %1306 %1308 = call float @llvm.AMDIL.clamp.(float %1307, float 0.000000e+00, float 1.000000e+00) %1309 = fmul float 2.000000e+00, %1308 %1310 = fsub float -0.000000e+00, %1309 %1311 = fadd float 3.000000e+00, %1310 %1312 = fmul float %1308, %1311 %1313 = fmul float %1308, %1312 %1314 = fsub float -0.000000e+00, %1313 %1315 = fadd float 1.000000e+00, %1314 %1316 = fmul float %1296, %1315 %1317 = fmul float %1298, %1315 %1318 = fmul float %1300, %1315 %1319 = fadd float %temp36.0, %1316 %1320 = fadd float %temp37.0, %1317 %1321 = fadd float %temp38.0, %1318 %1322 = bitcast float %temp.0 to i32 %1323 = add i32 %1322, 1 %1324 = bitcast i32 %1323 to float br label %LOOP } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: readnone declare float @llvm.AMDGPU.rsq(float) #2 ; Function Attrs: readnone declare float @llvm.AMDGPU.cndlt(float, float, float) #2 ; Function Attrs: nounwind readonly declare float @llvm.log2.f32(float) #3 ; Function Attrs: readonly declare float @floor(float) #4 ; Function Attrs: readnone declare float @llvm.AMDIL.exp.(float) #2 ; Function Attrs: readnone declare float @llvm.AMDIL.fraction.(float) #2 ; Function Attrs: readonly declare float @fabs(float) #4 ; Function Attrs: nounwind readonly declare float @llvm.pow.f32(float, float) #3 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1 ; Function Attrs: readnone declare float @llvm.AMDGPU.lrp(float, float, float) #2 ; Function Attrs: readnone declare float @llvm.AMDIL.clamp.(float, float, float) #2 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } attributes #3 = { nounwind readonly } attributes #4 = { readonly } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B64 s[10:11], s[0:1] ; BE8A0400 S_MOV_B32 m0, s9 ; BEFC0309 V_INTERP_P1_F32 v12, v0, 1, 1, [m0] ; C8300500 V_INTERP_P2_F32 v12, [v12], v1, 1, 1, [m0] ; C8310501 V_INTERP_P1_F32 v13, v0, 0, 1, [m0] ; C8340400 V_INTERP_P2_F32 v13, [v13], v1, 0, 1, [m0] ; C8350401 S_LOAD_DWORDX4 s[12:15], s[10:11], 4 ; C0860B04 S_WAITCNT lgkmcnt(0) ; BF8C007F S_BUFFER_LOAD_DWORD s90, s[12:15], 49 ; C22D0D31 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v2, s90, v13 ; 10041A5A S_BUFFER_LOAD_DWORD s91, s[12:15], 53 ; C22D8D35 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v2, s91, v12, v2, 0, 0, 0, 0 ; D2820002 040A185B V_INTERP_P1_F32 v14, v0, 2, 1, [m0] ; C8380600 V_INTERP_P2_F32 v14, [v14], v1, 2, 1, [m0] ; C8390601 S_BUFFER_LOAD_DWORD s0, s[12:15], 57 ; C2000D39 S_WAITCNT lgkmcnt(0) ; BF8C007F V_WRITELANE_B32 v49, s0, 1 ; 04630200 V_MAD_F32 v2, s0, v14, v2, 0, 0, 0, 0 ; D2820002 040A1C00 S_BUFFER_LOAD_DWORD s0, s[12:15], 61 ; C2000D3D S_WAITCNT lgkmcnt(0) ; BF8C007F V_WRITELANE_B32 v49, s0, 2 ; 04630400 V_ADD_F32_e32 v2, s0, v2 ; 06040400 S_BUFFER_LOAD_DWORD s0, s[12:15], 81 ; C2000D51 S_WAITCNT lgkmcnt(0) ; BF8C007F V_WRITELANE_B32 v49, s0, 3 ; 04630600 V_SUBREV_F32_e32 v2, s0, v2 ; 0A040400 S_BUFFER_LOAD_DWORD s0, s[12:15], 48 ; C2000D30 S_WAITCNT lgkmcnt(0) ; BF8C007F V_WRITELANE_B32 v49, s0, 4 ; 04630800 V_MUL_F32_e32 v3, s0, v13 ; 10061A00 S_BUFFER_LOAD_DWORD s0, s[12:15], 52 ; C2000D34 S_WAITCNT lgkmcnt(0) ; BF8C007F V_WRITELANE_B32 v49, s0, 5 ; 04630A00 V_MAD_F32 v3, s0, v12, v3, 0, 0, 0, 0 ; D2820003 040E1800 S_BUFFER_LOAD_DWORD s0, s[12:15], 56 ; C2000D38 S_WAITCNT lgkmcnt(0) ; BF8C007F V_WRITELANE_B32 v49, s0, 6 ; 04630C00 V_MAD_F32 v3, s0, v14, v3, 0, 0, 0, 0 ; D2820003 040E1C00 S_BUFFER_LOAD_DWORD s0, s[12:15], 60 ; C2000D3C S_WAITCNT lgkmcnt(0) ; BF8C007F V_WRITELANE_B32 v49, s0, 7 ; 04630E00 V_ADD_F32_e32 v3, s0, v3 ; 06060600 S_BUFFER_LOAD_DWORD s0, s[12:15], 80 ; C2000D50 S_WAITCNT lgkmcnt(0) ; BF8C007F V_WRITELANE_B32 v49, s0, 8 ; 04631000 V_SUBREV_F32_e32 v3, s0, v3 ; 0A060600 V_MUL_F32_e32 v3, v3, v3 ; 10060703 V_MAD_F32 v2, v2, v2, v3, 0, 0, 0, 0 ; D2820002 040E0502 S_BUFFER_LOAD_DWORD s0, s[12:15], 50 ; C2000D32 S_WAITCNT lgkmcnt(0) ; BF8C007F V_WRITELANE_B32 v49, s0, 9 ; 04631200 V_MUL_F32_e32 v3, s0, v13 ; 10061A00 S_BUFFER_LOAD_DWORD s0, s[12:15], 54 ; C2000D36 S_WAITCNT lgkmcnt(0) ; BF8C007F V_WRITELANE_B32 v49, s0, 10 ; 04631400 V_MAD_F32 v3, s0, v12, v3, 0, 0, 0, 0 ; D2820003 040E1800 S_BUFFER_LOAD_DWORD s0, s[12:15], 58 ; C2000D3A S_WAITCNT lgkmcnt(0) ; BF8C007F V_WRITELANE_B32 v49, s0, 11 ; 04631600 V_MAD_F32 v3, s0, v14, v3, 0, 0, 0, 0 ; D2820003 040E1C00 S_BUFFER_LOAD_DWORD s0, s[12:15], 62 ; C2000D3E S_WAITCNT lgkmcnt(0) ; BF8C007F V_WRITELANE_B32 v49, s0, 12 ; 04631800 V_ADD_F32_e32 v3, s0, v3 ; 06060600 S_BUFFER_LOAD_DWORD s0, s[12:15], 82 ; C2000D52 S_WAITCNT lgkmcnt(0) ; BF8C007F V_WRITELANE_B32 v49, s0, 13 ; 04631A00 V_SUBREV_F32_e32 v3, s0, v3 ; 0A060600 V_MAD_F32 v2, v3, v3, v2, 0, 0, 0, 0 ; D2820002 040A0703 V_RSQ_LEGACY_F32_e32 v3, v2 ; 7E065B02 V_MUL_F32_e32 v3, v3, v2 ; 10060503 V_XOR_B32_e32 v2, -2147483648, v2 ; 3A0404FF 80000000 V_CMP_GT_F32_e64 s[0:1], 0, v2, 0, 0, 0, 0 ; D0080000 02020480 V_CNDMASK_B32_e64 v2, 0.000000e+00, v3, s[0:1], 0, 0, 0, 0 ; D2000002 00020680 S_LOAD_DWORDX4 s[12:15], s[10:11], 0 ; C0860B00 S_MOV_B32 s0, 1392 ; BE8003FF 00000570 S_WAITCNT lgkmcnt(0) ; BF8C007F S_BUFFER_LOAD_DWORD s0, s[12:15], s0 ; C2000C00 S_WAITCNT lgkmcnt(0) ; BF8C007F V_RCP_F32_e32 v3, s0 ; 7E065400 V_MAD_F32 v2, v2, v3, 1.000000e+00, 0, 0, 0, 0 ; D2820002 03CA0702 V_LOG_F32_e32 v2, v2 ; 7E044F02 V_MUL_F32_e32 v2, 6.931472e-01, v2 ; 100404FF 3F317218 S_MOV_B32 s0, 1408 ; BE8003FF 00000580 S_BUFFER_LOAD_DWORD s0, s[12:15], s0 ; C2000C00 S_WAITCNT lgkmcnt(0) ; BF8C007F V_LOG_F32_e32 v3, s0 ; 7E064E00 V_MUL_F32_e32 v3, 6.931472e-01, v3 ; 100606FF 3F317218 V_RCP_F32_e32 v3, v3 ; 7E065503 V_MUL_F32_e32 v5, v2, v3 ; 100A0702 V_FLOOR_F32_e32 v2, v5 ; 7E044905 V_EXP_F32_e32 v23, v2 ; 7E2E4B02 S_MOV_B32 s0, 1344 ; BE8003FF 00000540 S_BUFFER_LOAD_DWORD s0, s[12:15], s0 ; C2000C00 S_WAITCNT lgkmcnt(0) ; BF8C007F V_WRITELANE_B32 v49, s0, 14 ; 04631C00 V_MUL_F32_e32 v2, s0, v23 ; 10042E00 V_RCP_F32_e32 v2, v2 ; 7E045502 V_INTERP_P1_F32 v16, v0, 1, 2, [m0] ; C8400900 V_INTERP_P2_F32 v16, [v16], v1, 1, 2, [m0] ; C8410901 V_MUL_F32_e32 v7, v16, v2 ; 100E0510 V_INTERP_P1_F32 v20, v0, 3, 1, [m0] ; C8500700 V_INTERP_P2_F32 v20, [v20], v1, 3, 1, [m0] ; C8510701 V_MUL_F32_e32 v6, v20, v2 ; 100C0514 S_LOAD_DWORDX4 s[16:19], s[2:3], 16 ; C0880310 S_WAITCNT lgkmcnt(0) ; BF8C007F V_WRITELANE_B32 v49, s16, 15 ; 04631E10 V_WRITELANE_B32 v49, s17, 16 ; 04632011 V_WRITELANE_B32 v49, s18, 17 ; 04632212 V_WRITELANE_B32 v49, s19, 18 ; 04632413 S_LOAD_DWORDX8 s[48:55], s[4:5], 32 ; C0D80520 S_WAITCNT lgkmcnt(0) ; BF8C007F IMAGE_SAMPLE v[8:10], 7, 0, 0, 0, 0, 0, 0, 0, v[6:7], s[48:55], s[16:19] ; F0800700 008C0806 V_INTERP_P1_F32 v25, v0, 0, 0, [m0] ; C8640000 V_INTERP_P2_F32 v25, [v25], v1, 0, 0, [m0] ; C8650001 V_ADD_F32_e32 v2, v25, v25 ; 06043319 V_CMP_U_F32_e64 s[0:1], v2, v2, 0, 0, 0, 0 ; D0100000 02020502 V_CMP_LE_F32_e64 s[6:7], v2, 1.000000e+00, 0, 0, 0, 0 ; D0060006 0201E502 S_OR_B64 s[0:1], s[6:7], s[0:1] ; 88800006 V_CNDMASK_B32_e64 v11, 1.000000e+00, v2, s[0:1], 0, 0, 0, 0 ; D200000B 000204F2 V_SUB_F32_e32 v24, 1.000000e+00, v11 ; 083016F2 S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v2, v24, v10 ; 10041518 S_LOAD_DWORDX4 s[76:79], s[2:3], 12 ; C0A6030C S_LOAD_DWORDX8 s[16:23], s[4:5], 24 ; C0C80518 S_WAITCNT lgkmcnt(0) ; BF8C007F V_WRITELANE_B32 v49, s16, 19 ; 04632610 V_WRITELANE_B32 v49, s17, 20 ; 04632811 V_WRITELANE_B32 v49, s18, 21 ; 04632A12 V_WRITELANE_B32 v49, s19, 22 ; 04632C13 V_WRITELANE_B32 v49, s20, 23 ; 04632E14 V_WRITELANE_B32 v49, s21, 24 ; 04633015 V_WRITELANE_B32 v49, s22, 25 ; 04633216 V_WRITELANE_B32 v49, s23, 26 ; 04633417 IMAGE_SAMPLE v[26:28], 7, 0, 0, 0, 0, 0, 0, 0, v[6:7], s[16:23], s[76:79] ; F0800700 02641A06 S_WAITCNT vmcnt(0) ; BF8C0770 V_MAD_F32 v2, v11, v28, v2, 0, 0, 0, 0 ; D2820002 040A390B S_MOV_B32 s0, 1328 ; BE8003FF 00000530 S_BUFFER_LOAD_DWORD s89, s[12:15], s0 ; C22C8C00 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v3, s89, v23 ; 10062E59 V_RCP_F32_e32 v3, v3 ; 7E065503 V_INTERP_P1_F32 v22, v0, 0, 2, [m0] ; C8580800 V_INTERP_P2_F32 v22, [v22], v1, 0, 2, [m0] ; C8590801 V_MUL_F32_e32 v30, v22, v3 ; 103C0716 V_MUL_F32_e32 v29, v20, v3 ; 103A0714 S_LOAD_DWORDX4 s[56:59], s[2:3], 8 ; C09C0308 S_LOAD_DWORDX8 s[60:67], s[4:5], 16 ; C0DE0510 S_WAITCNT lgkmcnt(0) ; BF8C007F IMAGE_SAMPLE v[31:33], 7, 0, 0, 0, 0, 0, 0, 0, v[29:30], s[60:67], s[56:59] ; F0800700 01CF1F1D V_INTERP_P1_F32 v17, v0, 3, 2, [m0] ; C8440B00 V_INTERP_P2_F32 v17, [v17], v1, 3, 2, [m0] ; C8450B01 V_AND_B32_e32 v18, 2147483647, v17 ; 362422FF 7FFFFFFF V_ADD_F32_e32 v3, 1.000000e-03, v18 ; 060624FF 3A83126F V_LOG_F32_e32 v3, v3 ; 7E064F03 S_MOV_B32 s0, 1376 ; BE8003FF 00000560 S_BUFFER_LOAD_DWORD s88, s[12:15], s0 ; C22C0C00 S_WAITCNT vmcnt(0) lgkmcnt(0) ; BF8C0070 V_MUL_LEGACY_F32_e32 v3, s88, v3 ; 0E060658 V_EXP_F32_e32 v3, v3 ; 7E064B03 V_INTERP_P1_F32 v15, v0, 2, 2, [m0] ; C83C0A00 V_INTERP_P2_F32 v15, [v15], v1, 2, 2, [m0] ; C83D0A01 V_AND_B32_e32 v21, 2147483647, v15 ; 362A1EFF 7FFFFFFF V_ADD_F32_e32 v4, 1.000000e-03, v21 ; 06082AFF 3A83126F V_LOG_F32_e32 v4, v4 ; 7E084F04 V_MUL_LEGACY_F32_e32 v4, s88, v4 ; 0E080858 V_EXP_F32_e32 v4, v4 ; 7E084B04 V_ADD_F32_e32 v34, v4, v3 ; 06440704 V_INTERP_P1_F32 v19, v0, 0, 3, [m0] ; C84C0C00 V_INTERP_P2_F32 v19, [v19], v1, 0, 3, [m0] ; C84D0C01 V_AND_B32_e32 v35, 2147483647, v19 ; 364626FF 7FFFFFFF V_ADD_F32_e32 v36, 1.000000e-03, v35 ; 064846FF 3A83126F V_LOG_F32_e32 v36, v36 ; 7E484F24 V_MUL_LEGACY_F32_e32 v36, s88, v36 ; 0E484858 V_EXP_F32_e32 v36, v36 ; 7E484B24 V_ADD_F32_e32 v34, v34, v36 ; 06444922 V_RCP_F32_e32 v34, v34 ; 7E445522 V_MUL_F32_e32 v36, v36, v34 ; 10484524 V_MUL_F32_e32 v37, v33, v36 ; 104A4921 V_MUL_F32_e32 v3, v3, v34 ; 10064503 V_MAD_F32 v2, v2, v3, v37, 0, 0, 0, 0 ; D2820002 04960702 S_MOV_B32 s0, 1360 ; BE8003FF 00000550 S_BUFFER_LOAD_DWORD s1, s[12:15], s0 ; C2008C00 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v37, s1, v23 ; 104A2E01 V_RCP_F32_e32 v37, v37 ; 7E4A5525 V_MUL_F32_e32 v39, v22, v37 ; 104E4B16 V_MUL_F32_e32 v38, v16, v37 ; 104C4B10 S_LOAD_DWORDX4 s[36:39], s[2:3], 20 ; C0920314 S_LOAD_DWORDX8 s[40:47], s[4:5], 40 ; C0D40528 S_WAITCNT lgkmcnt(0) ; BF8C007F IMAGE_SAMPLE v[40:42], 7, 0, 0, 0, 0, 0, 0, 0, v[38:39], s[40:47], s[36:39] ; F0800700 012A2826 V_MUL_F32_e32 v34, v4, v34 ; 10444504 S_WAITCNT vmcnt(0) ; BF8C0770 V_MAD_F32 v4, v42, v34, v2, 0, 0, 0, 0 ; D2820004 040A452A V_MUL_F32_e32 v2, v24, v9 ; 10041318 V_MAD_F32 v2, v11, v27, v2, 0, 0, 0, 0 ; D2820002 040A370B V_MUL_F32_e32 v37, v32, v36 ; 104A4920 V_MAD_F32 v2, v2, v3, v37, 0, 0, 0, 0 ; D2820002 04960702 V_MAD_F32 v2, v41, v34, v2, 0, 0, 0, 0 ; D2820002 040A4529 V_MUL_F32_e32 v8, v24, v8 ; 10101118 V_MAD_F32 v8, v11, v26, v8, 0, 0, 0, 0 ; D2820008 0422350B V_MUL_F32_e32 v9, v31, v36 ; 1012491F V_MAD_F32 v3, v8, v3, v9, 0, 0, 0, 0 ; D2820003 04260708 V_MAD_F32 v3, v40, v34, v3, 0, 0, 0, 0 ; D2820003 040E4528 S_LOAD_DWORDX4 s[16:19], s[2:3], 32 ; C0880320 S_LOAD_DWORDX8 s[20:27], s[4:5], 64 ; C0CA0540 S_WAITCNT lgkmcnt(0) ; BF8C007F IMAGE_SAMPLE v[8:10], 7, 0, 0, 0, 0, 0, 0, 0, v[6:7], s[20:27], s[16:19] ; F0800700 00850806 S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v26, v24, v10 ; 10341518 S_LOAD_DWORDX4 s[68:71], s[2:3], 28 ; C0A2031C S_LOAD_DWORDX8 s[28:35], s[4:5], 56 ; C0CE0538 S_WAITCNT lgkmcnt(0) ; BF8C007F IMAGE_SAMPLE v[31:33], 7, 0, 0, 0, 0, 0, 0, 0, v[6:7], s[28:35], s[68:71] ; F0800700 02271F06 S_WAITCNT vmcnt(0) ; BF8C0770 V_MAD_F32 v6, v11, v33, v26, 0, 0, 0, 0 ; D2820006 046A430B V_CMP_U_F32_e64 s[6:7], v17, v17, 0, 0, 0, 0 ; D0100006 02022311 V_CMP_GT_F32_e64 s[72:73], v17, 0.000000e+00, 0, 0, 0, 0 ; D0080048 02010111 S_OR_B64 s[6:7], s[72:73], s[6:7] ; 88860648 V_CNDMASK_B32_e64 v7, v17, 1.000000e+00, s[6:7], 0, 0, 0, 0 ; D2000007 0019E511 V_CMP_U_F32_e64 s[6:7], v7, v7, 0, 0, 0, 0 ; D0100006 02020F07 V_CMP_GE_F32_e64 s[72:73], v7, 0.000000e+00, 0, 0, 0, 0 ; D00C0048 02010107 S_OR_B64 s[6:7], s[72:73], s[6:7] ; 88860648 V_CNDMASK_B32_e64 v7, -1.000000e+00, v7, s[6:7], 0, 0, 0, 0 ; D2000007 001A0EF3 V_MUL_F32_e32 v6, v6, v7 ; 100C0F06 S_LOAD_DWORDX4 s[80:83], s[2:3], 24 ; C0A80318 S_LOAD_DWORDX8 s[92:99], s[4:5], 48 ; C0EE0530 S_WAITCNT lgkmcnt(0) ; BF8C007F V_WRITELANE_B32 v49, s92, 27 ; 0463365C V_WRITELANE_B32 v49, s93, 28 ; 0463385D V_WRITELANE_B32 v49, s94, 29 ; 04633A5E V_WRITELANE_B32 v49, s95, 30 ; 04633C5F V_WRITELANE_B32 v49, s96, 31 ; 04633E60 V_WRITELANE_B32 v49, s97, 32 ; 04634061 V_WRITELANE_B32 v49, s98, 33 ; 04634262 V_WRITELANE_B32 v49, s99, 34 ; 04634463 IMAGE_SAMPLE v[26:28], 7, 0, 0, 0, 0, 0, 0, 0, v[29:30], s[92:99], s[80:83] ; F0800700 02971A1D S_WAITCNT vmcnt(0) ; BF8C0770 V_ADD_F32_e32 v29, v27, v27 ; 063A371B V_ADD_F32_e32 v29, -1.003906e+00, v29 ; 063A3AFF BF808000 V_CMP_U_F32_e64 s[6:7], v19, v19, 0, 0, 0, 0 ; D0100006 02022713 V_CMP_GT_F32_e64 s[84:85], v19, 0.000000e+00, 0, 0, 0, 0 ; D0080054 02010113 S_OR_B64 s[6:7], s[84:85], s[6:7] ; 88860654 V_CNDMASK_B32_e64 v30, v19, 1.000000e+00, s[6:7], 0, 0, 0, 0 ; D200001E 0019E513 V_CMP_U_F32_e64 s[6:7], v30, v30, 0, 0, 0, 0 ; D0100006 02023D1E V_CMP_GE_F32_e64 s[84:85], v30, 0.000000e+00, 0, 0, 0, 0 ; D00C0054 0201011E S_OR_B64 s[6:7], s[84:85], s[6:7] ; 88860654 V_CNDMASK_B32_e64 v30, -1.000000e+00, v30, s[6:7], 0, 0, 0, 0 ; D200001E 001A3CF3 V_MUL_F32_e32 v29, v29, v30 ; 103A3D1D V_ADD_F32_e32 v34, v21, v18 ; 06442515 V_ADD_F32_e32 v34, v34, v35 ; 06444722 V_RCP_F32_e32 v34, v34 ; 7E445522 V_MUL_F32_e32 v35, v35, v34 ; 10464523 V_MUL_F32_e32 v29, v29, v35 ; 103A471D V_MUL_F32_e32 v36, v18, v34 ; 10484512 V_MAD_F32 v6, v6, v36, v29, 0, 0, 0, 0 ; D2820006 04764906 S_LOAD_DWORDX4 s[84:87], s[2:3], 36 ; C0AA0324 S_LOAD_DWORDX8 s[92:99], s[4:5], 72 ; C0EE0548 S_WAITCNT lgkmcnt(0) ; BF8C007F IMAGE_SAMPLE v[37:39], 7, 0, 0, 0, 0, 0, 0, 0, v[38:39], s[92:99], s[84:87] ; F0800700 02B72526 S_WAITCNT vmcnt(0) ; BF8C0770 V_ADD_F32_e32 v18, v38, v38 ; 06244D26 V_ADD_F32_e32 v18, -1.003906e+00, v18 ; 062424FF BF808000 V_CMP_U_F32_e64 s[6:7], v15, v15, 0, 0, 0, 0 ; D0100006 02021F0F V_CMP_GT_F32_e64 s[100:101], v15, 0.000000e+00, 0, 0, 0, 0 ; D0080064 0201010F S_OR_B64 s[6:7], s[100:101], s[6:7] ; 88860664 V_CNDMASK_B32_e64 v29, v15, 1.000000e+00, s[6:7], 0, 0, 0, 0 ; D200001D 0019E50F V_CMP_U_F32_e64 s[6:7], v29, v29, 0, 0, 0, 0 ; D0100006 02023B1D V_CMP_GE_F32_e64 s[100:101], v29, 0.000000e+00, 0, 0, 0, 0 ; D00C0064 0201011D S_OR_B64 s[6:7], s[100:101], s[6:7] ; 88860664 V_CNDMASK_B32_e64 v29, -1.000000e+00, v29, s[6:7], 0, 0, 0, 0 ; D200001D 001A3AF3 V_MUL_F32_e32 v18, v18, v29 ; 10243B12 V_MUL_F32_e32 v34, v21, v34 ; 10444515 V_MAD_F32 v18, v18, v34, v6, 0, 0, 0, 0 ; D2820012 041A4512 V_ADD_F32_e32 v6, v9, v9 ; 060C1309 V_ADD_F32_e32 v6, -1.003906e+00, v6 ; 060C0CFF BF808000 V_MUL_F32_e32 v6, v24, v6 ; 100C0D18 V_ADD_F32_e32 v21, v32, v32 ; 062A4120 V_ADD_F32_e32 v21, -1.003906e+00, v21 ; 062A2AFF BF808000 V_MAD_F32 v6, v11, v21, v6, 0, 0, 0, 0 ; D2820006 041A2B0B V_MUL_F32_e32 v6, v6, v7 ; 100C0F06 V_MUL_F32_e32 v21, v28, v30 ; 102A3D1C V_MUL_F32_e32 v21, v21, v35 ; 102A4715 V_MAD_F32 v6, v6, v36, v21, 0, 0, 0, 0 ; D2820006 04564906 V_ADD_F32_e32 v21, v37, v37 ; 062A4B25 V_ADD_F32_e32 v21, -1.003906e+00, v21 ; 062A2AFF BF808000 V_MUL_F32_e32 v21, v21, v29 ; 102A3B15 V_MAD_F32 v21, v21, v34, v6, 0, 0, 0, 0 ; D2820015 041A4515 V_ADD_F32_e32 v6, v8, v8 ; 060C1108 V_ADD_F32_e32 v6, -1.003906e+00, v6 ; 060C0CFF BF808000 V_MUL_F32_e32 v6, v24, v6 ; 100C0D18 V_ADD_F32_e32 v8, v31, v31 ; 06103F1F V_ADD_F32_e32 v8, -1.003906e+00, v8 ; 061010FF BF808000 V_MAD_F32 v6, v11, v8, v6, 0, 0, 0, 0 ; D2820006 041A110B V_MUL_F32_e32 v6, v6, v7 ; 100C0F06 V_ADD_F32_e32 v7, v26, v26 ; 060E351A V_ADD_F32_e32 v7, -1.003906e+00, v7 ; 060E0EFF BF808000 V_MUL_F32_e32 v7, v7, v30 ; 100E3D07 V_MUL_F32_e32 v7, v7, v35 ; 100E4707 V_MAD_F32 v6, v6, v36, v7, 0, 0, 0, 0 ; D2820006 041E4906 V_MUL_F32_e32 v7, v39, v29 ; 100E3B27 V_MAD_F32 v24, v7, v34, v6, 0, 0, 0, 0 ; D2820018 041A4507 V_FRACT_F32_e32 v26, v5 ; 7E344105 S_MOV_B32 s0, 1424 ; BE8003FF 00000590 S_BUFFER_LOAD_DWORD s100, s[12:15], s0 ; C2320C00 S_WAITCNT lgkmcnt(0) ; BF8C007F V_CMP_LT_F32_e64 vcc, v26, s100, 0, 0, 0, 0 ; D002006A 0200C91A V_INTERP_P1_F32 v11, v0, 3, 0, [m0] ; C82C0300 V_INTERP_P2_F32 v11, [v11], v1, 3, 0, [m0] ; C82D0301 V_INTERP_P1_F32 v10, v0, 2, 0, [m0] ; C8280200 V_INTERP_P2_F32 v10, [v10], v1, 2, 0, [m0] ; C8290201 V_INTERP_P1_F32 v9, v0, 1, 0, [m0] ; C8240100 V_INTERP_P2_F32 v9, [v9], v1, 1, 0, [m0] ; C8250101 S_MOV_B32 s0, 1496 ; BE8003FF 000005D8 S_BUFFER_LOAD_DWORD s72, s[12:15], s0 ; C2240C00 S_MOV_B32 s0, 1492 ; BE8003FF 000005D4 S_BUFFER_LOAD_DWORD s75, s[12:15], s0 ; C2258C00 S_MOV_B32 s0, 1488 ; BE8003FF 000005D0 S_BUFFER_LOAD_DWORD s74, s[12:15], s0 ; C2250C00 S_MOV_B32 s0, 1480 ; BE8003FF 000005C8 S_BUFFER_LOAD_DWORD s73, s[12:15], s0 ; C2248C00 S_MOV_B32 s0, 1476 ; BE8003FF 000005C4 S_BUFFER_LOAD_DWORD s0, s[12:15], s0 ; C2000C00 S_WAITCNT lgkmcnt(0) ; BF8C007F V_WRITELANE_B32 v49, s0, 36 ; 04634800 S_MOV_B32 s0, 1472 ; BE8003FF 000005C0 S_BUFFER_LOAD_DWORD s0, s[12:15], s0 ; C2000C00 S_WAITCNT lgkmcnt(0) ; BF8C007F V_WRITELANE_B32 v49, s0, 35 ; 04634600 S_MOV_B32 s0, 1464 ; BE8003FF 000005B8 S_BUFFER_LOAD_DWORD s101, s[12:15], s0 ; C2328C00 S_MOV_B32 s0, 1460 ; BE8003FF 000005B4 S_BUFFER_LOAD_DWORD s0, s[12:15], s0 ; C2000C00 S_WAITCNT lgkmcnt(0) ; BF8C007F V_WRITELANE_B32 v49, s0, 38 ; 04634C00 S_MOV_B32 s6, 1456 ; BE8603FF 000005B0 S_BUFFER_LOAD_DWORD s0, s[12:15], s6 ; C2000C06 S_WAITCNT lgkmcnt(0) ; BF8C007F V_WRITELANE_B32 v49, s0, 37 ; 04634A00 S_MOV_B32 s6, 1324 ; BE8603FF 0000052C S_BUFFER_LOAD_DWORD s6, s[12:15], s6 ; C2030C06 S_MOV_B32 s7, 1320 ; BE8703FF 00000528 S_BUFFER_LOAD_DWORD s7, s[12:15], s7 ; C2038C07 S_MOV_B32 s8, 1316 ; BE8803FF 00000524 S_BUFFER_LOAD_DWORD s8, s[12:15], s8 ; C2040C08 S_MOV_B32 s9, 1312 ; BE8903FF 00000520 S_BUFFER_LOAD_DWORD s9, s[12:15], s9 ; C2048C09 V_MOV_B32_e32 v8, 0.000000e+00 ; 7E100280 S_WAITCNT lgkmcnt(0) ; BF8C007F S_AND_SAVEEXEC_B64 vcc, vcc ; BEEA246A S_XOR_B64 vcc, exec, vcc ; 89EA6A7E S_CBRANCH_EXECZ BB0_2 ; BF880000 V_ADD_F32_e64 v0, v25, v25, 0, 0, 0, 0 ; D2060000 02023319 V_WRITELANE_B32 v49, s10, 0 ; 0463000A V_WRITELANE_B32 v49, s11, 1 ; 0463020B V_CMP_U_F32_e64 s[10:11], v0, v0, 0, 0, 0, 0 ; D010000A 02020100 V_WRITELANE_B32 v49, s92, 39 ; 04634E5C V_WRITELANE_B32 v49, s93, 40 ; 0463505D V_WRITELANE_B32 v49, s94, 41 ; 0463525E V_WRITELANE_B32 v49, s95, 42 ; 0463545F V_WRITELANE_B32 v49, s96, 43 ; 04635660 V_WRITELANE_B32 v49, s97, 44 ; 04635861 V_WRITELANE_B32 v49, s98, 45 ; 04635A62 V_WRITELANE_B32 v49, s99, 46 ; 04635C63 S_MOV_B32 s92, s89 ; BEDC0359 S_MOV_B32 s89, s75 ; BED9034B S_MOV_B32 s75, s74 ; BECB034A S_MOV_B32 s74, s73 ; BECA0349 S_MOV_B32 s73, s101 ; BEC90365 S_MOV_B32 s101, s90 ; BEE5035A S_MOV_B32 s0, s91 ; BE80035B V_CMP_LE_F32_e64 s[90:91], v0, 1.000000e+00, 0, 0, 0, 0 ; D006005A 0201E500 S_OR_B64 s[10:11], s[90:91], s[10:11] ; 888A0A5A S_MOV_B32 s91, s0 ; BEDB0300 S_MOV_B32 s90, s101 ; BEDA0365 S_MOV_B32 s101, s73 ; BEE50349 S_MOV_B32 s73, s74 ; BEC9034A S_MOV_B32 s74, s75 ; BECA034B S_MOV_B32 s75, s89 ; BECB0359 V_CNDMASK_B32_e64 v0, 1.000000e+00, v0, s[10:11], 0, 0, 0, 0 ; D2000000 002A00F2 V_SUB_F32_e32 v1, 1.000000e+00, v0 ; 080200F2 V_MUL_F32_e64 v23, v23, 5.000000e-01, 0, 0, 0, 0 ; D2100017 0201E117 V_READLANE_B32 s0, v49, 14 ; 02011D31 V_MUL_F32_e32 v5, s0, v23 ; 100A2E00 V_RCP_F32_e32 v5, v5 ; 7E0A5505 V_MUL_F32_e32 v28, v16, v5 ; 10380B10 V_MUL_F32_e32 v27, v20, v5 ; 10360B14 S_MOV_B32 s0, s72 ; BE800348 V_WRITELANE_B32 v49, s80, 47 ; 04635E50 V_WRITELANE_B32 v49, s81, 48 ; 04636051 V_WRITELANE_B32 v49, s82, 49 ; 04636252 V_WRITELANE_B32 v49, s83, 50 ; 04636453 S_MOV_B32 s96, s84 ; BEE00354 S_MOV_B32 s97, s85 ; BEE10355 S_MOV_B32 s98, s86 ; BEE20356 S_MOV_B32 s99, s87 ; BEE30357 S_MOV_B32 s80, s60 ; BED0033C S_MOV_B32 s81, s61 ; BED1033D S_MOV_B32 s82, s62 ; BED2033E S_MOV_B32 s83, s63 ; BED3033F S_MOV_B32 s84, s64 ; BED40340 S_MOV_B32 s85, s65 ; BED50341 S_MOV_B32 s86, s66 ; BED60342 S_MOV_B32 s87, s67 ; BED70343 S_MOV_B32 s60, s56 ; BEBC0338 S_MOV_B32 s61, s57 ; BEBD0339 S_MOV_B32 s62, s58 ; BEBE033A S_MOV_B32 s63, s59 ; BEBF033B S_MOV_B32 s52, s48 ; BEB40330 S_MOV_B32 s53, s49 ; BEB50331 S_MOV_B32 s54, s50 ; BEB60332 S_MOV_B32 s55, s51 ; BEB70333 S_MOV_B32 s56, s52 ; BEB80334 S_MOV_B32 s57, s53 ; BEB90335 S_MOV_B32 s58, s54 ; BEBA0336 S_MOV_B32 s59, s55 ; BEBB0337 V_READLANE_B32 s48, v49, 15 ; 02611F31 V_READLANE_B32 s49, v49, 16 ; 02632131 V_READLANE_B32 s50, v49, 17 ; 02652331 V_READLANE_B32 s51, v49, 18 ; 02672531 IMAGE_SAMPLE v[29:31], 7, 0, 0, 0, 0, 0, 0, 0, v[27:28], s[52:59], s[48:51] ; F0800700 018D1D1B S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v5, v1, v31 ; 100A3F01 V_READLANE_B32 s48, v49, 19 ; 02612731 V_READLANE_B32 s49, v49, 20 ; 02632931 V_READLANE_B32 s50, v49, 21 ; 02652B31 V_READLANE_B32 s51, v49, 22 ; 02672D31 V_READLANE_B32 s52, v49, 23 ; 02692F31 V_READLANE_B32 s53, v49, 24 ; 026B3131 V_READLANE_B32 s54, v49, 25 ; 026D3331 V_READLANE_B32 s55, v49, 26 ; 026F3531 IMAGE_SAMPLE v[32:34], 7, 0, 0, 0, 0, 0, 0, 0, v[27:28], s[48:55], s[76:79] ; F0800700 026C201B S_WAITCNT vmcnt(0) ; BF8C0770 V_MAD_F32 v25, v0, v34, v5, 0, 0, 0, 0 ; D2820019 04164500 V_MOV_B32_e32 v5, 2147483647 ; 7E0A02FF 7FFFFFFF V_AND_B32_e32 v35, v17, v5 ; 36460B11 V_ADD_F32_e32 v6, 1.000000e-03, v35 ; 060C46FF 3A83126F V_LOG_F32_e32 v6, v6 ; 7E0C4F06 V_MUL_LEGACY_F32_e32 v6, s88, v6 ; 0E0C0C58 V_EXP_F32_e32 v36, v6 ; 7E484B06 V_AND_B32_e32 v37, v15, v5 ; 364A0B0F V_ADD_F32_e32 v6, 1.000000e-03, v37 ; 060C4AFF 3A83126F V_LOG_F32_e32 v6, v6 ; 7E0C4F06 V_MUL_LEGACY_F32_e32 v6, s88, v6 ; 0E0C0C58 V_EXP_F32_e32 v38, v6 ; 7E4C4B06 V_ADD_F32_e32 v6, v38, v36 ; 060C4926 V_AND_B32_e32 v39, v19, v5 ; 364E0B13 V_ADD_F32_e32 v5, 1.000000e-03, v39 ; 060A4EFF 3A83126F V_LOG_F32_e32 v5, v5 ; 7E0A4F05 V_MUL_LEGACY_F32_e32 v5, s88, v5 ; 0E0A0A58 V_EXP_F32_e32 v5, v5 ; 7E0A4B05 V_ADD_F32_e32 v6, v6, v5 ; 060C0B06 V_RCP_F32_e32 v40, v6 ; 7E505506 V_MUL_F32_e32 v41, v5, v40 ; 10525105 V_MUL_F32_e32 v5, s92, v23 ; 100A2E5C V_RCP_F32_e32 v5, v5 ; 7E0A5505 V_MUL_F32_e32 v43, v22, v5 ; 10560B16 V_MUL_F32_e32 v42, v20, v5 ; 10540B14 IMAGE_SAMPLE v[5:8], 15, 0, 0, 0, 0, 0, 0, 0, v[42:43], s[80:87], s[60:63] ; F0800F00 01F4052A S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v20, v7, v41 ; 10285307 V_MUL_F32_e32 v36, v36, v40 ; 10485124 V_MAD_F32 v20, v25, v36, v20, 0, 0, 0, 0 ; D2820014 04524919 V_MUL_F32_e32 v25, v38, v40 ; 10325126 V_MUL_F32_e32 v23, s1, v23 ; 102E2E01 V_RCP_F32_e32 v23, v23 ; 7E2E5517 V_MUL_F32_e32 v45, v22, v23 ; 105A2F16 V_MUL_F32_e32 v44, v16, v23 ; 10582F10 IMAGE_SAMPLE v[46:48], 7, 0, 0, 0, 0, 0, 0, 0, v[44:45], s[40:47], s[36:39] ; F0800700 012A2E2C S_WAITCNT vmcnt(0) ; BF8C0770 V_MAD_F32 v16, v48, v25, v20, 0, 0, 0, 0 ; D2820010 04523330 V_RCP_F32_e32 v20, s100 ; 7E285464 V_MUL_F32_e32 v20, v26, v20 ; 1028291A V_ADD_F32_e64 v20, 0, v20, 0, 1, 0, 0 ; D2060814 02022880 V_ADD_F32_e32 v22, v20, v20 ; 062C2914 V_SUB_F32_e32 v22, 3.000000e+00, v22 ; 082C2CFF 40400000 V_MUL_F32_e32 v22, v20, v22 ; 102C2D14 V_MUL_F32_e32 v20, v20, v22 ; 10282D14 V_SUB_F32_e32 v22, 1.000000e+00, v20 ; 082C28F2 V_MUL_F32_e32 v16, v22, v16 ; 10202116 V_MAD_F32 v4, v20, v4, v16, 0, 0, 0, 0 ; D2820004 04420914 V_MUL_F32_e32 v16, v1, v30 ; 10203D01 V_MAD_F32 v16, v0, v33, v16, 0, 0, 0, 0 ; D2820010 04424300 V_MUL_F32_e32 v23, v6, v41 ; 102E5306 V_MAD_F32 v16, v16, v36, v23, 0, 0, 0, 0 ; D2820010 045E4910 V_MAD_F32 v16, v47, v25, v16, 0, 0, 0, 0 ; D2820010 0442332F V_MUL_F32_e32 v16, v22, v16 ; 10202116 V_MAD_F32 v2, v20, v2, v16, 0, 0, 0, 0 ; D2820002 04420514 V_MUL_F32_e32 v16, v1, v29 ; 10203B01 V_MAD_F32 v16, v0, v32, v16, 0, 0, 0, 0 ; D2820010 04424100 V_MUL_F32_e32 v23, v5, v41 ; 102E5305 V_MAD_F32 v16, v16, v36, v23, 0, 0, 0, 0 ; D2820010 045E4910 V_MAD_F32 v16, v46, v25, v16, 0, 0, 0, 0 ; D2820010 0442332E V_MUL_F32_e32 v16, v22, v16 ; 10202116 V_MAD_F32 v3, v20, v3, v16, 0, 0, 0, 0 ; D2820003 04420714 IMAGE_SAMPLE v[29:31], 7, 0, 0, 0, 0, 0, 0, 0, v[27:28], s[20:27], s[16:19] ; F0800700 00851D1B S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v16, v1, v31 ; 10203F01 IMAGE_SAMPLE v[25:27], 7, 0, 0, 0, 0, 0, 0, 0, v[27:28], s[28:35], s[68:71] ; F0800700 0227191B S_WAITCNT vmcnt(0) ; BF8C0770 V_MAD_F32 v16, v0, v27, v16, 0, 0, 0, 0 ; D2820010 04423700 V_CMP_U_F32_e64 s[10:11], v17, v17, 0, 0, 0, 0 ; D010000A 02022311 V_CMP_GT_F32_e64 s[16:17], v17, 0.000000e+00, 0, 0, 0, 0 ; D0080010 02010111 S_OR_B64 s[10:11], s[16:17], s[10:11] ; 888A0A10 V_CNDMASK_B32_e64 v17, v17, 1.000000e+00, s[10:11], 0, 0, 0, 0 ; D2000011 0029E511 V_CMP_U_F32_e64 s[10:11], v17, v17, 0, 0, 0, 0 ; D010000A 02022311 V_CMP_GE_F32_e64 s[16:17], v17, 0.000000e+00, 0, 0, 0, 0 ; D00C0010 02010111 S_OR_B64 s[10:11], s[16:17], s[10:11] ; 888A0A10 V_CNDMASK_B32_e64 v17, -1.000000e+00, v17, s[10:11], 0, 0, 0, 0 ; D2000011 002A22F3 V_MUL_F32_e32 v16, v16, v17 ; 10202310 V_CMP_U_F32_e64 s[10:11], v19, v19, 0, 0, 0, 0 ; D010000A 02022713 V_CMP_GT_F32_e64 s[16:17], v19, 0.000000e+00, 0, 0, 0, 0 ; D0080010 02010113 S_OR_B64 s[10:11], s[16:17], s[10:11] ; 888A0A10 V_CNDMASK_B32_e64 v19, v19, 1.000000e+00, s[10:11], 0, 0, 0, 0 ; D2000013 0029E513 V_CMP_U_F32_e64 s[10:11], v19, v19, 0, 0, 0, 0 ; D010000A 02022713 V_CMP_GE_F32_e64 s[16:17], v19, 0.000000e+00, 0, 0, 0, 0 ; D00C0010 02010113 S_OR_B64 s[10:11], s[16:17], s[10:11] ; 888A0A10 V_CNDMASK_B32_e64 v19, -1.000000e+00, v19, s[10:11], 0, 0, 0, 0 ; D2000013 002A26F3 V_READLANE_B32 s16, v49, 27 ; 02213731 V_READLANE_B32 s17, v49, 28 ; 02233931 V_READLANE_B32 s18, v49, 29 ; 02253B31 V_READLANE_B32 s19, v49, 30 ; 02273D31 V_READLANE_B32 s20, v49, 31 ; 02293F31 V_READLANE_B32 s21, v49, 32 ; 022B4131 V_READLANE_B32 s22, v49, 33 ; 022D4331 V_READLANE_B32 s23, v49, 34 ; 022F4531 V_READLANE_B32 s24, v49, 47 ; 02315F31 V_READLANE_B32 s25, v49, 48 ; 02336131 V_READLANE_B32 s26, v49, 49 ; 02356331 V_READLANE_B32 s27, v49, 50 ; 02376531 IMAGE_SAMPLE v[32:34], 7, 0, 0, 0, 0, 0, 0, 0, v[42:43], s[16:23], s[24:27] ; F0800700 00C4202A S_WAITCNT vmcnt(0) ; BF8C0770 V_ADD_F32_e32 v23, v33, v33 ; 062E4321 V_ADD_F32_e32 v23, -1.003906e+00, v23 ; 062E2EFF BF808000 V_MUL_F32_e32 v23, v23, v19 ; 102E2717 V_ADD_F32_e32 v28, v37, v35 ; 06384725 V_ADD_F32_e32 v28, v28, v39 ; 06384F1C V_RCP_F32_e32 v28, v28 ; 7E38551C V_MUL_F32_e32 v36, v39, v28 ; 10483927 V_MUL_F32_e32 v23, v23, v36 ; 102E4917 V_MUL_F32_e32 v35, v35, v28 ; 10463923 V_MAD_F32 v16, v16, v35, v23, 0, 0, 0, 0 ; D2820010 045E4710 V_CMP_U_F32_e64 s[10:11], v15, v15, 0, 0, 0, 0 ; D010000A 02021F0F V_CMP_GT_F32_e64 s[16:17], v15, 0.000000e+00, 0, 0, 0, 0 ; D0080010 0201010F S_OR_B64 s[10:11], s[16:17], s[10:11] ; 888A0A10 V_CNDMASK_B32_e64 v15, v15, 1.000000e+00, s[10:11], 0, 0, 0, 0 ; D200000F 0029E50F V_CMP_U_F32_e64 s[10:11], v15, v15, 0, 0, 0, 0 ; D010000A 02021F0F V_CMP_GE_F32_e64 s[16:17], v15, 0.000000e+00, 0, 0, 0, 0 ; D00C0010 0201010F S_OR_B64 s[10:11], s[16:17], s[10:11] ; 888A0A10 V_CNDMASK_B32_e64 v15, -1.000000e+00, v15, s[10:11], 0, 0, 0, 0 ; D200000F 002A1EF3 V_READLANE_B32 s10, v49, 0 ; 02150131 V_READLANE_B32 s11, v49, 1 ; 02170331 V_READLANE_B32 s16, v49, 39 ; 02214F31 V_READLANE_B32 s17, v49, 40 ; 02235131 V_READLANE_B32 s18, v49, 41 ; 02255331 V_READLANE_B32 s19, v49, 42 ; 02275531 V_READLANE_B32 s20, v49, 43 ; 02295731 V_READLANE_B32 s21, v49, 44 ; 022B5931 V_READLANE_B32 s22, v49, 45 ; 022D5B31 V_READLANE_B32 s23, v49, 46 ; 022F5D31 IMAGE_SAMPLE v[38:40], 7, 0, 0, 0, 0, 0, 0, 0, v[44:45], s[16:23], s[96:99] ; F0800700 0304262C S_WAITCNT vmcnt(0) ; BF8C0770 V_ADD_F32_e32 v23, v39, v39 ; 062E4F27 V_ADD_F32_e32 v23, -1.003906e+00, v23 ; 062E2EFF BF808000 V_MUL_F32_e32 v23, v23, v15 ; 102E1F17 V_MUL_F32_e32 v28, v37, v28 ; 10383925 V_MAD_F32 v16, v23, v28, v16, 0, 0, 0, 0 ; D2820010 04423917 V_MUL_F32_e32 v16, v22, v16 ; 10202116 V_MAD_F32 v18, v20, v18, v16, 0, 0, 0, 0 ; D2820012 04422514 V_MUL_F32_e32 v16, v34, v19 ; 10202722 V_MUL_F32_e32 v16, v16, v36 ; 10204910 V_ADD_F32_e32 v23, v30, v30 ; 062E3D1E V_ADD_F32_e32 v23, -1.003906e+00, v23 ; 062E2EFF BF808000 V_MUL_F32_e32 v23, v1, v23 ; 102E2F01 V_ADD_F32_e32 v37, v26, v26 ; 064A351A V_ADD_F32_e32 v37, -1.003906e+00, v37 ; 064A4AFF BF808000 V_MAD_F32 v23, v0, v37, v23, 0, 0, 0, 0 ; D2820017 045E4B00 V_MUL_F32_e32 v23, v23, v17 ; 102E2317 V_MAD_F32 v16, v23, v35, v16, 0, 0, 0, 0 ; D2820010 04424717 V_ADD_F32_e32 v23, v38, v38 ; 062E4D26 V_ADD_F32_e32 v23, -1.003906e+00, v23 ; 062E2EFF BF808000 V_MUL_F32_e32 v23, v23, v15 ; 102E1F17 V_MAD_F32 v16, v23, v28, v16, 0, 0, 0, 0 ; D2820010 04423917 V_MUL_F32_e32 v16, v22, v16 ; 10202116 V_MAD_F32 v21, v20, v21, v16, 0, 0, 0, 0 ; D2820015 04422B14 V_ADD_F32_e32 v16, v32, v32 ; 06204120 V_ADD_F32_e32 v16, -1.003906e+00, v16 ; 062020FF BF808000 V_MUL_F32_e32 v16, v16, v19 ; 10202710 V_MUL_F32_e32 v16, v16, v36 ; 10204910 V_ADD_F32_e32 v19, v29, v29 ; 06263B1D V_ADD_F32_e32 v19, -1.003906e+00, v19 ; 062626FF BF808000 V_MUL_F32_e32 v1, v1, v19 ; 10022701 V_ADD_F32_e32 v19, v25, v25 ; 06263319 V_ADD_F32_e32 v19, -1.003906e+00, v19 ; 062626FF BF808000 V_MAD_F32 v0, v0, v19, v1, 0, 0, 0, 0 ; D2820000 04062700 V_MUL_F32_e32 v0, v0, v17 ; 10002300 V_MAD_F32 v0, v0, v35, v16, 0, 0, 0, 0 ; D2820000 04424700 V_MUL_F32_e32 v1, v40, v15 ; 10021F28 V_MAD_F32 v0, v1, v28, v0, 0, 0, 0, 0 ; D2820000 04023901 V_MUL_F32_e32 v0, v22, v0 ; 10000116 V_MAD_F32 v24, v20, v24, v0, 0, 0, 0, 0 ; D2820018 04023114 S_OR_B64 exec, exec, vcc ; 88FE6A7E S_LOAD_DWORDX4 s[32:35], s[2:3], 0 ; C0900300 S_LOAD_DWORDX8 s[36:43], s[4:5], 0 ; C0D20500 V_READLANE_B32 s0, v49, 38 ; 02014D31 V_MUL_F32_e64 v0, s0, v24, 0, 0, 0, 0 ; D2100000 02023000 V_READLANE_B32 s0, v49, 36 ; 02014931 V_MAD_F32 v0, s0, v18, v0, 0, 0, 0, 0 ; D2820000 04022400 V_MAD_F32 v20, s75, v21, v0, 0, 0, 0, 0 ; D2820014 04022A4B V_READLANE_B32 s0, v49, 37 ; 02014B31 V_MUL_F32_e64 v0, s0, v24, 0, 0, 0, 0 ; D2100000 02023000 V_READLANE_B32 s0, v49, 35 ; 02014731 V_MAD_F32 v0, s0, v18, v0, 0, 0, 0, 0 ; D2820000 04022400 V_MAD_F32 v0, s74, v21, v0, 0, 0, 0, 0 ; D2820000 04022A4A V_MUL_F32_e32 v1, v0, v0 ; 10020100 V_MAD_F32 v1, v20, v20, v1, 0, 0, 0, 0 ; D2820001 04062914 V_MUL_F32_e64 v15, s101, v24, 0, 0, 0, 0 ; D210000F 02023065 V_MAD_F32 v15, s73, v18, v15, 0, 0, 0, 0 ; D282000F 043E2449 V_MAD_F32 v15, s72, v21, v15, 0, 0, 0, 0 ; D282000F 043E2A48 V_MAD_F32 v1, v15, v15, v1, 0, 0, 0, 0 ; D2820001 04061F0F V_RSQ_LEGACY_F32_e32 v22, v1 ; 7E2C5B01 V_MUL_F32_e32 v0, v0, v22 ; 10002D00 V_MUL_F32_e64 v1, s90, v13, 0, 0, 0, 0 ; D2100001 02021A5A V_MAD_F32 v1, s91, v12, v1, 0, 0, 0, 0 ; D2820001 0406185B V_READLANE_B32 s0, v49, 1 ; 02010331 V_MAD_F32 v1, s0, v14, v1, 0, 0, 0, 0 ; D2820001 04061C00 V_READLANE_B32 s0, v49, 2 ; 02010531 V_ADD_F32_e32 v16, s0, v1 ; 06200200 V_READLANE_B32 s0, v49, 3 ; 02010731 V_SUBREV_F32_e32 v19, s0, v16 ; 0A262000 V_READLANE_B32 s0, v49, 4 ; 02010931 V_MUL_F32_e64 v1, s0, v13, 0, 0, 0, 0 ; D2100001 02021A00 V_READLANE_B32 s0, v49, 5 ; 02010B31 V_MAD_F32 v1, s0, v12, v1, 0, 0, 0, 0 ; D2820001 04061800 V_READLANE_B32 s0, v49, 6 ; 02010D31 V_MAD_F32 v1, s0, v14, v1, 0, 0, 0, 0 ; D2820001 04061C00 V_READLANE_B32 s0, v49, 7 ; 02010F31 V_ADD_F32_e32 v17, s0, v1 ; 06220200 V_READLANE_B32 s0, v49, 8 ; 02011131 V_SUBREV_F32_e32 v1, s0, v17 ; 0A022200 V_MUL_F32_e32 v18, v1, v1 ; 10240301 V_MAD_F32 v21, v19, v19, v18, 0, 0, 0, 0 ; D2820015 044A2713 V_READLANE_B32 s0, v49, 9 ; 02011331 V_MUL_F32_e64 v13, s0, v13, 0, 0, 0, 0 ; D210000D 02021A00 V_READLANE_B32 s0, v49, 10 ; 02011531 V_MAD_F32 v12, s0, v12, v13, 0, 0, 0, 0 ; D282000C 04361800 V_READLANE_B32 s0, v49, 11 ; 02011731 V_MAD_F32 v12, s0, v14, v12, 0, 0, 0, 0 ; D282000C 04321C00 V_READLANE_B32 s0, v49, 12 ; 02011931 V_ADD_F32_e32 v18, s0, v12 ; 06241800 V_READLANE_B32 s0, v49, 13 ; 02011B31 V_SUBREV_F32_e32 v13, s0, v18 ; 0A1A2400 V_MAD_F32 v12, v13, v13, v21, 0, 0, 0, 0 ; D282000C 04561B0D V_RSQ_LEGACY_F32_e32 v14, v12 ; 7E1C5B0C V_MUL_F32_e32 v21, v1, v14 ; 102A1D01 V_MUL_F32_e32 v12, v0, v21 ; 10182B00 V_MUL_F32_e32 v1, v20, v22 ; 10022D14 V_MUL_F32_e32 v19, v19, v14 ; 10261D13 V_MAD_F32 v23, v1, v19, v12, 0, 0, 0, 0 ; D2820017 04322701 V_MUL_F32_e32 v12, v15, v22 ; 10182D0F V_MUL_F32_e32 v15, v13, v14 ; 101E1D0D V_MAD_F32 v23, v12, v15, v23, 0, 0, 0, 0 ; D2820017 045E1F0C V_MUL_F32_e32 v13, v23, v1 ; 101A0317 V_MAD_F32 v13, v23, v1, v13, 0, 0, 0, 0 ; D282000D 04360317 V_SUB_F32_e32 v13, v19, v13 ; 081A1B13 V_MUL_F32_e32 v14, v23, v0 ; 101C0117 V_MAD_F32 v14, v23, v0, v14, 0, 0, 0, 0 ; D282000E 043A0117 V_SUB_F32_e32 v14, v21, v14 ; 081C1D15 S_LOAD_DWORDX4 s[16:19], s[10:11], 8 ; C0880B08 S_WAITCNT lgkmcnt(0) ; BF8C007F S_BUFFER_LOAD_DWORD s10, s[16:19], 48 ; C2051130 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v19, s10, v14 ; 10261C0A S_BUFFER_LOAD_DWORD s11, s[16:19], 49 ; C2059131 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v19, v13, s11, v19, 0, 0, 0, 0 ; D2820013 044C170D V_MUL_F32_e32 v21, v23, v12 ; 102A1917 V_MAD_F32 v21, v23, v12, v21, 0, 0, 0, 0 ; D2820015 04561917 V_SUB_F32_e32 v15, v15, v21 ; 081E2B0F S_BUFFER_LOAD_DWORD s20, s[16:19], 50 ; C20A1132 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v19, v15, s20, v19, 0, 0, 0, 0 ; D2820013 044C290F V_MOV_B32_e32 v21, 1.000000e-03 ; 7E2A02FF 3A83126F V_CMP_LE_F32_e64 s[0:1], v19, v21, 0, 0, 0, 0 ; D0060000 02022B13 V_CMP_U_F32_e64 s[22:23], v19, v19, 0, 0, 0, 0 ; D0100016 02022713 S_OR_B64 s[0:1], s[0:1], s[22:23] ; 88801600 V_CNDMASK_B32_e64 v19, v19, v21, s[0:1], 0, 0, 0, 0 ; D2000013 00022B13 V_LOG_F32_e32 v19, v19 ; 7E264F13 V_MUL_LEGACY_F32_e32 v19, s6, v19 ; 0E262606 V_EXP_F32_e32 v19, v19 ; 7E264B13 S_BUFFER_LOAD_DWORD s21, s[16:19], 61 ; C20A913D S_WAITCNT lgkmcnt(0) ; BF8C007F V_SUBREV_F32_e32 v21, s21, v16 ; 0A2A2015 S_BUFFER_LOAD_DWORD s22, s[16:19], 60 ; C20B113C S_WAITCNT lgkmcnt(0) ; BF8C007F V_SUBREV_F32_e32 v23, s22, v17 ; 0A2E2216 V_MUL_F32_e32 v23, v23, v23 ; 102E2F17 V_MAD_F32 v21, v21, v21, v23, 0, 0, 0, 0 ; D2820015 045E2B15 S_BUFFER_LOAD_DWORD s23, s[16:19], 62 ; C20B913E S_WAITCNT lgkmcnt(0) ; BF8C007F V_SUBREV_F32_e32 v23, s23, v18 ; 0A2E2417 V_MAD_F32 v21, v23, v23, v21, 0, 0, 0, 0 ; D2820015 04562F17 V_RSQ_LEGACY_F32_e32 v23, v21 ; 7E2E5B15 V_MUL_F32_e32 v23, v23, v21 ; 102E2B17 V_XOR_B32_e32 v21, -2147483648, v21 ; 3A2A2AFF 80000000 V_CMP_GT_F32_e64 s[0:1], 0, v21, 0, 0, 0, 0 ; D0080000 02022A80 V_CNDMASK_B32_e64 v21, 0.000000e+00, v23, s[0:1], 0, 0, 0, 0 ; D2000015 00022E80 S_BUFFER_LOAD_DWORD s28, s[16:19], 64 ; C20E1140 V_MOV_B32_e32 v23, 8.000000e-01 ; 7E2E02FF 3F4CCCCD S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v23, s28, v23 ; 102E2E1C V_CMP_LT_F32_e64 s[0:1], v21, v23, 0, 0, 0, 0 ; D0020000 02022F15 V_CNDMASK_B32_e64 v23, 0, -1, s[0:1], 0, 0, 0, 0 ; D2000017 00018280 V_CMP_EQ_I32_e64 s[0:1], v23, 0, 0, 0, 0, 0 ; D1040000 02010117 V_MOV_B32_e32 v23, 1.050000e+00 ; 7E2E02FF 3F866666 V_MAD_F32 v20, v20, v22, v23, 0, 0, 0, 0 ; D2820014 045E2D14 V_ADD_F32_e64 v20, 0, v20, 0, 1, 0, 0 ; D2060814 02022880 S_AND_SAVEEXEC_B64 s[0:1], s[0:1] ; BE802400 S_XOR_B64 s[0:1], exec, s[0:1] ; 8980007E S_CBRANCH_EXECZ BB0_3 ; BF880000 V_CMP_LT_F32_e64 s[24:25], s28, v21, 0, 0, 0, 0 ; D0020018 02022A1C V_CNDMASK_B32_e64 v22, 0, -1, s[24:25], 0, 0, 0, 0 ; D2000016 00618280 V_CMP_EQ_I32_e64 s[30:31], v22, 0, 0, 0, 0, 0 ; D104001E 02010116 S_LOAD_DWORDX4 s[24:27], s[2:3], 4 ; C08C0304 S_LOAD_DWORDX8 s[44:51], s[4:5], 8 ; C0D60508 S_WAITCNT lgkmcnt(0) ; BF8C007F S_AND_SAVEEXEC_B64 s[2:3], s[30:31] ; BE82241E S_XOR_B64 s[2:3], exec, s[2:3] ; 8982027E S_CBRANCH_EXECZ BB0_8 ; BF880000 V_MOV_B32_e32 v22, -8.000000e-01 ; 7E2C02FF BF4CCCCD V_MAD_F32 v21, s28, v22, v21, 0, 0, 0, 0 ; D2820015 04562C1C V_MOV_B32_e32 v23, s28 ; 7E2E021C V_MAD_F32 v22, s28, v22, v23, 0, 0, 0, 0 ; D2820016 045E2C1C V_RCP_F32_e32 v22, v22 ; 7E2C5516 V_MUL_F32_e32 v21, v21, v22 ; 102A2D15 V_ADD_F32_e64 v21, 0, v21, 0, 1, 0, 0 ; D2060815 02022A80 V_ADD_F32_e32 v22, v21, v21 ; 062C2B15 V_SUB_F32_e32 v22, 3.000000e+00, v22 ; 082C2CFF 40400000 V_MUL_F32_e32 v22, v21, v22 ; 102C2D15 V_MUL_F32_e32 v21, v21, v22 ; 102A2D15 V_SUB_F32_e32 v22, 1.000000e+00, v21 ; 082C2AF2 S_BUFFER_LOAD_DWORD s4, s[16:19], 18 ; C2021112 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v23, s4, v17, 0, 0, 0, 0 ; D2100017 02022204 S_BUFFER_LOAD_DWORD s4, s[16:19], 22 ; C2021116 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v23, s4, v16, v23, 0, 0, 0, 0 ; D2820017 045E2004 S_BUFFER_LOAD_DWORD s4, s[16:19], 26 ; C202111A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v23, s4, v18, v23, 0, 0, 0, 0 ; D2820017 045E2404 S_BUFFER_LOAD_DWORD s4, s[16:19], 30 ; C202111E S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v23, s4, v23 ; 062E2E04 V_CMP_U_F32_e64 s[4:5], v23, v23, 0, 0, 0, 0 ; D0100004 02022F17 V_CMP_GE_F32_e64 s[28:29], v23, -1.000000e+00, 0, 0, 0, 0 ; D00C001C 0201E717 S_OR_B64 s[4:5], s[28:29], s[4:5] ; 8884041C V_CNDMASK_B32_e64 v23, -1.000000e+00, v23, s[4:5], 0, 0, 0, 0 ; D2000017 00122EF3 V_CMP_U_F32_e64 s[4:5], v23, v23, 0, 0, 0, 0 ; D0100004 02022F17 V_CMP_GE_F32_e64 s[28:29], v23, 1.000000e+00, 0, 0, 0, 0 ; D00C001C 0201E517 S_OR_B64 s[4:5], s[28:29], s[4:5] ; 8884041C V_CNDMASK_B32_e64 v23, v23, 1.000000e+00, s[4:5], 0, 0, 0, 0 ; D2000017 0011E517 V_ADD_F32_e32 v23, 1.000000e+00, v23 ; 062E2EF2 S_BUFFER_LOAD_DWORD s4, s[16:19], 63 ; C202113F V_MOV_B32_e32 v24, -2147483648 ; 7E3002FF 80000000 S_WAITCNT lgkmcnt(0) ; BF8C007F V_XOR_B32_e32 v24, s4, v24 ; 3A303004 V_MUL_F32_e32 v23, v24, v23 ; 102E2F18 V_MUL_F32_e32 v23, 7.213475e-01, v23 ; 102E2EFF 3F38AA3B V_EXP_F32_e32 v23, v23 ; 7E2E4B17 S_BUFFER_LOAD_DWORD s4, s[16:19], 17 ; C2021111 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v25, s4, v17, 0, 0, 0, 0 ; D2100019 02022204 S_BUFFER_LOAD_DWORD s4, s[16:19], 21 ; C2021115 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v25, s4, v16, v25, 0, 0, 0, 0 ; D2820019 04662004 S_BUFFER_LOAD_DWORD s4, s[16:19], 25 ; C2021119 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v25, s4, v18, v25, 0, 0, 0, 0 ; D2820019 04662404 S_BUFFER_LOAD_DWORD s4, s[16:19], 29 ; C202111D S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v25, s4, v25 ; 06323204 V_MAD_F32 v25, v25, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0 ; D2820019 03C1E119 S_BUFFER_LOAD_DWORD s4, s[16:19], 66 ; C2021142 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v26, s4, v25 ; 10343204 S_BUFFER_LOAD_DWORD s5, s[16:19], 16 ; C2029110 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v27, s5, v17, 0, 0, 0, 0 ; D210001B 02022205 S_BUFFER_LOAD_DWORD s5, s[16:19], 20 ; C2029114 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v27, s5, v16, v27, 0, 0, 0, 0 ; D282001B 046E2005 S_BUFFER_LOAD_DWORD s5, s[16:19], 24 ; C2029118 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v27, s5, v18, v27, 0, 0, 0, 0 ; D282001B 046E2405 S_BUFFER_LOAD_DWORD s5, s[16:19], 28 ; C202911C S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v27, s5, v27 ; 06363605 V_MAD_F32 v27, v27, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0 ; D282001B 03C1E11B V_MUL_F32_e32 v25, s4, v27 ; 10323604 IMAGE_SAMPLE v25, 1, -1, 0, 0, 0, 0, 0, 0, v[25:26], s[36:43], s[32:35] ; F0801100 01091919 S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v23, v23, v25 ; 102E3317 V_ADD_F32_e64 v23, 0, v23, 0, 1, 0, 0 ; D2060817 02022E80 V_MUL_F32_e32 v22, v22, v23 ; 102C2F16 S_BUFFER_LOAD_DWORD s5, s[16:19], 34 ; C2029122 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v23, s5, v17, 0, 0, 0, 0 ; D2100017 02022205 S_BUFFER_LOAD_DWORD s5, s[16:19], 38 ; C2029126 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v23, s5, v16, v23, 0, 0, 0, 0 ; D2820017 045E2005 S_BUFFER_LOAD_DWORD s5, s[16:19], 42 ; C202912A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v23, s5, v18, v23, 0, 0, 0, 0 ; D2820017 045E2405 S_BUFFER_LOAD_DWORD s5, s[16:19], 46 ; C202912E S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v23, s5, v23 ; 062E2E05 V_CMP_U_F32_e64 s[28:29], v23, v23, 0, 0, 0, 0 ; D010001C 02022F17 V_CMP_GE_F32_e64 s[30:31], v23, -1.000000e+00, 0, 0, 0, 0 ; D00C001E 0201E717 S_OR_B64 s[28:29], s[30:31], s[28:29] ; 889C1C1E V_CNDMASK_B32_e64 v23, -1.000000e+00, v23, s[28:29], 0, 0, 0, 0 ; D2000017 00722EF3 V_CMP_U_F32_e64 s[28:29], v23, v23, 0, 0, 0, 0 ; D010001C 02022F17 V_CMP_GE_F32_e64 s[30:31], v23, 1.000000e+00, 0, 0, 0, 0 ; D00C001E 0201E517 S_OR_B64 s[28:29], s[30:31], s[28:29] ; 889C1C1E V_CNDMASK_B32_e64 v23, v23, 1.000000e+00, s[28:29], 0, 0, 0, 0 ; D2000017 0071E517 V_ADD_F32_e32 v23, 1.000000e+00, v23 ; 062E2EF2 V_MUL_F32_e32 v23, v24, v23 ; 102E2F18 V_MUL_F32_e32 v23, 7.213475e-01, v23 ; 102E2EFF 3F38AA3B V_EXP_F32_e32 v23, v23 ; 7E2E4B17 S_BUFFER_LOAD_DWORD s5, s[16:19], 33 ; C2029121 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v24, s5, v17, 0, 0, 0, 0 ; D2100018 02022205 S_BUFFER_LOAD_DWORD s5, s[16:19], 37 ; C2029125 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v24, s5, v16, v24, 0, 0, 0, 0 ; D2820018 04622005 S_BUFFER_LOAD_DWORD s5, s[16:19], 41 ; C2029129 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v24, s5, v18, v24, 0, 0, 0, 0 ; D2820018 04622405 S_BUFFER_LOAD_DWORD s5, s[16:19], 45 ; C202912D S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v24, s5, v24 ; 06303005 V_MAD_F32 v24, v24, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0 ; D2820018 03C1E118 V_MUL_F32_e32 v25, s4, v24 ; 10323004 S_BUFFER_LOAD_DWORD s5, s[16:19], 32 ; C2029120 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v26, s5, v17, 0, 0, 0, 0 ; D210001A 02022205 S_BUFFER_LOAD_DWORD s5, s[16:19], 36 ; C2029124 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v26, s5, v16, v26, 0, 0, 0, 0 ; D282001A 046A2005 S_BUFFER_LOAD_DWORD s5, s[16:19], 40 ; C2029128 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v26, s5, v18, v26, 0, 0, 0, 0 ; D282001A 046A2405 S_BUFFER_LOAD_DWORD s5, s[16:19], 44 ; C202912C S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v26, s5, v26 ; 06343405 V_MAD_F32 v26, v26, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0 ; D282001A 03C1E11A V_MUL_F32_e32 v24, s4, v26 ; 10303404 IMAGE_SAMPLE v24, 1, -1, 0, 0, 0, 0, 0, 0, v[24:25], s[44:51], s[24:27] ; F0801100 00CB1818 S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v23, v23, v24 ; 102E3117 V_ADD_F32_e64 v23, 0, v23, 0, 1, 0, 0 ; D2060817 02022E80 V_MAD_F32 v27, v21, v23, v22, 0, 0, 0, 0 ; D282001B 045A2F15 S_OR_SAVEEXEC_B64 s[2:3], s[2:3] ; BE822502 S_XOR_B64 exec, exec, s[2:3] ; 89FE027E S_CBRANCH_EXECZ BB0_6 ; BF880000 V_MOV_B32_e32 v21, s21 ; 7E2A0215 V_SUB_F32_e64 v21, v16, v21, 0, 0, 0, 0 ; D2080015 02022B10 V_MOV_B32_e32 v22, s22 ; 7E2C0216 V_SUB_F32_e64 v22, v17, v22, 0, 0, 0, 0 ; D2080016 02022D11 V_MUL_F32_e32 v22, v22, v22 ; 102C2D16 V_MAD_F32 v21, v21, v21, v22, 0, 0, 0, 0 ; D2820015 045A2B15 V_MOV_B32_e32 v22, s23 ; 7E2C0217 V_SUB_F32_e64 v22, v18, v22, 0, 0, 0, 0 ; D2080016 02022D12 V_MAD_F32 v21, v22, v22, v21, 0, 0, 0, 0 ; D2820015 04562D16 V_RSQ_LEGACY_F32_e32 v22, v21 ; 7E2C5B15 V_MUL_F32_e32 v22, v22, v21 ; 102C2B16 V_XOR_B32_e32 v21, -2147483648, v21 ; 3A2A2AFF 80000000 V_CMP_GT_F32_e64 s[4:5], 0, v21, 0, 0, 0, 0 ; D0080004 02022A80 V_CNDMASK_B32_e64 v21, 0.000000e+00, v22, s[4:5], 0, 0, 0, 0 ; D2000015 00122C80 S_BUFFER_LOAD_DWORD s4, s[16:19], 65 ; C2021141 S_WAITCNT lgkmcnt(0) ; BF8C007F V_RCP_F32_e32 v22, s4 ; 7E2C5404 V_MOV_B32_e32 v23, -8.000000e-01 ; 7E2E02FF BF4CCCCD V_MAD_F32 v21, v21, v22, v23, 0, 0, 0, 0 ; D2820015 045E2D15 V_MUL_F32_e32 v21, 5.000000e+00, v21 ; 102A2AFF 40A00001 V_ADD_F32_e64 v21, 0, v21, 0, 1, 0, 0 ; D2060815 02022A80 V_ADD_F32_e32 v22, v21, v21 ; 062C2B15 V_SUB_F32_e32 v22, 3.000000e+00, v22 ; 082C2CFF 40400000 V_MUL_F32_e32 v22, v21, v22 ; 102C2D15 V_MUL_F32_e32 v23, v21, v22 ; 102E2D15 V_SUB_F32_e32 v23, 1.000000e+00, v23 ; 082E2EF2 S_BUFFER_LOAD_DWORD s4, s[16:19], 34 ; C2021122 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v24, s4, v17, 0, 0, 0, 0 ; D2100018 02022204 S_BUFFER_LOAD_DWORD s4, s[16:19], 38 ; C2021126 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v24, s4, v16, v24, 0, 0, 0, 0 ; D2820018 04622004 S_BUFFER_LOAD_DWORD s4, s[16:19], 42 ; C202112A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v24, s4, v18, v24, 0, 0, 0, 0 ; D2820018 04622404 S_BUFFER_LOAD_DWORD s4, s[16:19], 46 ; C202112E S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v24, s4, v24 ; 06303004 V_CMP_U_F32_e64 s[4:5], v24, v24, 0, 0, 0, 0 ; D0100004 02023118 V_CMP_GE_F32_e64 s[22:23], v24, -1.000000e+00, 0, 0, 0, 0 ; D00C0016 0201E718 S_OR_B64 s[4:5], s[22:23], s[4:5] ; 88840416 V_CNDMASK_B32_e64 v24, -1.000000e+00, v24, s[4:5], 0, 0, 0, 0 ; D2000018 001230F3 V_CMP_U_F32_e64 s[4:5], v24, v24, 0, 0, 0, 0 ; D0100004 02023118 V_CMP_GE_F32_e64 s[22:23], v24, 1.000000e+00, 0, 0, 0, 0 ; D00C0016 0201E518 S_OR_B64 s[4:5], s[22:23], s[4:5] ; 88840416 V_CNDMASK_B32_e64 v24, v24, 1.000000e+00, s[4:5], 0, 0, 0, 0 ; D2000018 0011E518 V_ADD_F32_e32 v24, 1.000000e+00, v24 ; 063030F2 S_BUFFER_LOAD_DWORD s4, s[16:19], 63 ; C202113F S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v24, s4, v24 ; 10303004 V_MUL_F32_e32 v24, -7.213475e-01, v24 ; 103030FF BF38AA3B V_EXP_F32_e32 v24, v24 ; 7E304B18 S_BUFFER_LOAD_DWORD s4, s[16:19], 33 ; C2021121 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v25, s4, v17, 0, 0, 0, 0 ; D2100019 02022204 S_BUFFER_LOAD_DWORD s4, s[16:19], 37 ; C2021125 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v25, s4, v16, v25, 0, 0, 0, 0 ; D2820019 04662004 S_BUFFER_LOAD_DWORD s4, s[16:19], 41 ; C2021129 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v25, s4, v18, v25, 0, 0, 0, 0 ; D2820019 04662404 S_BUFFER_LOAD_DWORD s4, s[16:19], 45 ; C202112D S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v25, s4, v25 ; 06323204 V_MAD_F32 v25, v25, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0 ; D2820019 03C1E119 S_BUFFER_LOAD_DWORD s4, s[16:19], 66 ; C2021142 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v26, s4, v25 ; 10343204 S_BUFFER_LOAD_DWORD s5, s[16:19], 32 ; C2029120 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v27, s5, v17, 0, 0, 0, 0 ; D210001B 02022205 S_BUFFER_LOAD_DWORD s5, s[16:19], 36 ; C2029124 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v27, s5, v16, v27, 0, 0, 0, 0 ; D282001B 046E2005 S_BUFFER_LOAD_DWORD s5, s[16:19], 40 ; C2029128 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v27, s5, v18, v27, 0, 0, 0, 0 ; D282001B 046E2405 S_BUFFER_LOAD_DWORD s5, s[16:19], 44 ; C202912C S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v27, s5, v27 ; 06363605 V_MAD_F32 v27, v27, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0 ; D282001B 03C1E11B V_MUL_F32_e32 v25, s4, v27 ; 10323604 IMAGE_SAMPLE v25, 1, -1, 0, 0, 0, 0, 0, 0, v[25:26], s[44:51], s[24:27] ; F0801100 00CB1919 S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v24, v24, v25 ; 10303318 V_ADD_F32_e64 v24, 0, v24, 0, 1, 0, 0 ; D2060818 02023080 V_MUL_F32_e32 v23, v23, v24 ; 102E3117 V_MAD_F32 v27, v21, v22, v23, 0, 0, 0, 0 ; D282001B 045E2D15 S_OR_B64 exec, exec, s[2:3] ; 88FE027E S_OR_SAVEEXEC_B64 s[0:1], s[0:1] ; BE802500 S_BUFFER_LOAD_DWORD s2, s[12:15], 12 ; C2010D0C S_BUFFER_LOAD_DWORD s3, s[16:19], 54 ; C2019136 S_BUFFER_LOAD_DWORD s4, s[16:19], 53 ; C2021135 S_BUFFER_LOAD_DWORD s5, s[16:19], 52 ; C2029134 S_BUFFER_LOAD_DWORD s21, s[16:19], 58 ; C20A913A S_BUFFER_LOAD_DWORD s22, s[16:19], 57 ; C20B1139 S_BUFFER_LOAD_DWORD s23, s[16:19], 56 ; C20B9138 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v26, s3 ; 7E340203 V_MOV_B32_e32 v23, s4 ; 7E2E0204 V_MOV_B32_e32 v21, s5 ; 7E2A0205 V_MOV_B32_e32 v28, s20 ; 7E380214 V_MOV_B32_e32 v29, s11 ; 7E3A020B V_MOV_B32_e32 v30, s10 ; 7E3C020A V_MOV_B32_e32 v25, s21 ; 7E320215 V_MOV_B32_e32 v24, s22 ; 7E300216 V_MOV_B32_e32 v22, s23 ; 7E2C0217 S_XOR_B64 exec, exec, s[0:1] ; 89FE007E S_CBRANCH_EXECZ BB0_7 ; BF880000 S_BUFFER_LOAD_DWORD s3, s[16:19], 18 ; C2019112 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v27, s3, v17, 0, 0, 0, 0 ; D210001B 02022203 S_BUFFER_LOAD_DWORD s3, s[16:19], 22 ; C2019116 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v27, s3, v16, v27, 0, 0, 0, 0 ; D282001B 046E2003 S_BUFFER_LOAD_DWORD s3, s[16:19], 26 ; C201911A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v27, s3, v18, v27, 0, 0, 0, 0 ; D282001B 046E2403 S_BUFFER_LOAD_DWORD s3, s[16:19], 30 ; C201911E S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v27, s3, v27 ; 06363603 V_CMP_U_F32_e64 s[4:5], v27, v27, 0, 0, 0, 0 ; D0100004 0202371B V_CMP_GE_F32_e64 s[10:11], v27, -1.000000e+00, 0, 0, 0, 0 ; D00C000A 0201E71B S_OR_B64 s[4:5], s[10:11], s[4:5] ; 8884040A V_CNDMASK_B32_e64 v27, -1.000000e+00, v27, s[4:5], 0, 0, 0, 0 ; D200001B 001236F3 V_CMP_U_F32_e64 s[4:5], v27, v27, 0, 0, 0, 0 ; D0100004 0202371B V_CMP_GE_F32_e64 s[10:11], v27, 1.000000e+00, 0, 0, 0, 0 ; D00C000A 0201E51B S_OR_B64 s[4:5], s[10:11], s[4:5] ; 8884040A V_CNDMASK_B32_e64 v27, v27, 1.000000e+00, s[4:5], 0, 0, 0, 0 ; D200001B 0011E51B V_ADD_F32_e32 v27, 1.000000e+00, v27 ; 063636F2 S_BUFFER_LOAD_DWORD s3, s[16:19], 63 ; C201913F S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v27, s3, v27 ; 10363603 V_MUL_F32_e32 v27, -7.213475e-01, v27 ; 103636FF BF38AA3B V_EXP_F32_e32 v27, v27 ; 7E364B1B S_BUFFER_LOAD_DWORD s3, s[16:19], 17 ; C2019111 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v31, s3, v17, 0, 0, 0, 0 ; D210001F 02022203 S_BUFFER_LOAD_DWORD s3, s[16:19], 21 ; C2019115 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v31, s3, v16, v31, 0, 0, 0, 0 ; D282001F 047E2003 S_BUFFER_LOAD_DWORD s3, s[16:19], 25 ; C2019119 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v31, s3, v18, v31, 0, 0, 0, 0 ; D282001F 047E2403 S_BUFFER_LOAD_DWORD s3, s[16:19], 29 ; C201911D S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v31, s3, v31 ; 063E3E03 V_MAD_F32 v31, v31, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0 ; D282001F 03C1E11F S_BUFFER_LOAD_DWORD s3, s[16:19], 66 ; C2019142 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v32, s3, v31 ; 10403E03 S_BUFFER_LOAD_DWORD s4, s[16:19], 16 ; C2021110 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v33, s4, v17, 0, 0, 0, 0 ; D2100021 02022204 S_BUFFER_LOAD_DWORD s4, s[16:19], 20 ; C2021114 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v33, s4, v16, v33, 0, 0, 0, 0 ; D2820021 04862004 S_BUFFER_LOAD_DWORD s4, s[16:19], 24 ; C2021118 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v33, s4, v18, v33, 0, 0, 0, 0 ; D2820021 04862404 S_BUFFER_LOAD_DWORD s4, s[16:19], 28 ; C202111C S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v33, s4, v33 ; 06424204 V_MAD_F32 v33, v33, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0 ; D2820021 03C1E121 V_MUL_F32_e32 v31, s3, v33 ; 103E4203 IMAGE_SAMPLE v31, 1, -1, 0, 0, 0, 0, 0, 0, v[31:32], s[36:43], s[32:35] ; F0801100 01091F1F S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v27, v27, v31 ; 10363F1B V_ADD_F32_e64 v27, 0, v27, 0, 1, 0, 0 ; D206081B 02023680 S_OR_B64 exec, exec, s[0:1] ; 88FE007E V_MUL_F32_e64 v30, v0, v30, 0, 0, 0, 0 ; D210001E 02023D00 V_MAD_F32 v29, v1, v29, v30, 0, 0, 0, 0 ; D282001D 047A3B01 V_MAD_F32 v28, v12, v28, v29, 0, 0, 0, 0 ; D282001C 0476390C V_CMP_U_F32_e64 s[0:1], v28, v28, 0, 0, 0, 0 ; D0100000 0202391C V_CMP_LE_F32_e64 s[4:5], v28, 0.000000e+00, 0, 0, 0, 0 ; D0060004 0201011C S_OR_B64 s[0:1], s[4:5], s[0:1] ; 88800004 V_CNDMASK_B32_e64 v28, v28, 0.000000e+00, s[0:1], 0, 0, 0, 0 ; D200001C 0001011C V_MUL_F32_e32 v29, v26, v28 ; 103A391A V_MUL_F32_e64 v4, v4, v11, 0, 0, 0, 0 ; D2100004 02021704 V_MUL_F32_e32 v11, v29, v4 ; 1016091D V_MUL_F32_e64 v26, v19, v26, 0, 0, 0, 0 ; D210001A 02023513 V_MAD_F32 v11, v26, s7, v11, 0, 0, 0, 0 ; D282000B 042C0F1A V_MOV_B32_e32 v26, -8.000000e-01 ; 7E3402FF BF4CCCCD V_ADD_F32_e32 v26, v27, v26 ; 0634351B V_MUL_F32_e32 v26, 5.000000e+00, v26 ; 103434FF 40A00001 V_ADD_F32_e64 v26, 0, v26, 0, 1, 0, 0 ; D206081A 02023480 V_ADD_F32_e32 v27, v26, v26 ; 0636351A V_SUB_F32_e32 v27, 3.000000e+00, v27 ; 083636FF 40400000 V_MUL_F32_e32 v27, v26, v27 ; 1036371A V_MUL_F32_e32 v26, v26, v27 ; 1034371A V_MUL_F32_e32 v11, v11, v26 ; 1016350B V_MUL_F32_e64 v25, v20, v25, 0, 0, 0, 0 ; D2100019 02023314 V_MAD_F32 v25, v4, v25, v11, 0, 0, 0, 0 ; D2820019 042E3304 V_MUL_F32_e32 v11, v23, v28 ; 10163917 V_MUL_F32_e64 v2, v2, v10, 0, 0, 0, 0 ; D2100002 02021502 V_MUL_F32_e32 v10, v11, v2 ; 1014050B V_MUL_F32_e64 v11, v19, v23, 0, 0, 0, 0 ; D210000B 02022F13 V_MAD_F32 v10, v11, s8, v10, 0, 0, 0, 0 ; D282000A 0428110B V_MUL_F32_e32 v10, v10, v26 ; 1014350A V_MUL_F32_e64 v11, v20, v24, 0, 0, 0, 0 ; D210000B 02023114 V_MAD_F32 v23, v2, v11, v10, 0, 0, 0, 0 ; D2820017 042A1702 V_MUL_F32_e32 v10, v21, v28 ; 10143915 V_MUL_F32_e64 v3, v3, v9, 0, 0, 0, 0 ; D2100003 02021303 V_MUL_F32_e32 v9, v10, v3 ; 1012070A V_MUL_F32_e64 v10, v19, v21, 0, 0, 0, 0 ; D210000A 02022B13 V_MAD_F32 v9, v10, s9, v9, 0, 0, 0, 0 ; D2820009 0424130A V_MUL_F32_e32 v9, v9, v26 ; 10123509 V_MUL_F32_e64 v10, v20, v22, 0, 0, 0, 0 ; D210000A 02022D14 V_MAD_F32 v21, v3, v10, v9, 0, 0, 0, 0 ; D2820015 04261503 V_MOV_B32_e32 v11, -2147483648 ; 7E1602FF 80000000 V_XOR_B32_e32 v9, v18, v11 ; 3A121712 V_XOR_B32_e32 v10, v16, v11 ; 3A141710 V_XOR_B32_e32 v11, v17, v11 ; 3A161711 V_MOV_B32_e32 v16, 0.000000e+00 ; 7E200280 S_MOV_B64 s[0:1], 0 ; BE800480 V_MOV_B32_e32 v17, s2 ; 7E220202 V_MOV_B32_e32 v18, v21 ; 7E240315 V_MOV_B32_e32 v19, v23 ; 7E260317 V_MOV_B32_e32 v20, v25 ; 7E280319 V_CMP_GE_I32_e64 s[2:3], v16, v17, 0, 0, 0, 0 ; D10C0002 02022310 V_CNDMASK_B32_e64 v21, 0, -1, s[2:3], 0, 0, 0, 0 ; D2000015 00098280 V_CMP_EQ_I32_e64 s[2:3], v21, 0, 0, 0, 0, 0 ; D1040002 02010115 S_AND_SAVEEXEC_B64 s[2:3], s[2:3] ; BE822402 S_XOR_B64 s[2:3], exec, s[2:3] ; 8982027E S_CBRANCH_EXECZ BB0_12 ; BF880000 V_MUL_LO_I32 v21, 7, v16, 0, 0, 0, 0, 0 ; D2D60015 02022087 V_LSHLREV_B32_e32 v21, 4, v21 ; 342A2A84 V_ADD_I32_e32 v22, 80, v21 ; 4A2C2AFF 00000050 BUFFER_LOAD_DWORD v22, s[12:15] + v22 + 0, glc=0, slc=0, tfe=0 ; E0301000 80031616 S_WAITCNT vmcnt(0) expcnt(0) ; BF8C0700 V_ADD_F32_e32 v22, v10, v22 ; 062C2D0A V_ADD_I32_e32 v23, 64, v21 ; 4A2E2AC0 BUFFER_LOAD_DWORD v23, s[12:15] + v23 + 0, glc=0, slc=0, tfe=0 ; E0301000 80031717 S_WAITCNT vmcnt(0) ; BF8C0770 V_ADD_F32_e32 v23, v11, v23 ; 062E2F0B V_MUL_F32_e32 v24, v23, v23 ; 10302F17 V_MAD_F32 v24, v22, v22, v24, 0, 0, 0, 0 ; D2820018 04622D16 V_ADD_I32_e32 v25, 96, v21 ; 4A322AFF 00000060 BUFFER_LOAD_DWORD v25, s[12:15] + v25 + 0, glc=0, slc=0, tfe=0 ; E0301000 80031919 S_WAITCNT vmcnt(0) ; BF8C0770 V_ADD_F32_e32 v25, v9, v25 ; 06323309 V_MAD_F32 v24, v25, v25, v24, 0, 0, 0, 0 ; D2820018 04623319 V_RSQ_LEGACY_F32_e32 v26, v24 ; 7E345B18 V_MUL_F32_e32 v26, v26, v24 ; 1034311A V_XOR_B32_e32 v24, -2147483648, v24 ; 3A3030FF 80000000 V_CMP_GT_F32_e64 s[4:5], 0, v24, 0, 0, 0, 0 ; D0080004 02023080 V_CNDMASK_B32_e64 v24, 0.000000e+00, v26, s[4:5], 0, 0, 0, 0 ; D2000018 00123480 V_RCP_F32_e32 v26, v24 ; 7E345518 V_MUL_F32_e32 v22, v22, v26 ; 102C3516 V_MUL_F32_e32 v23, v23, v26 ; 102E3517 V_MUL_F32_e32 v27, v0, v23 ; 10362F00 V_MAD_F32 v27, v1, v22, v27, 0, 0, 0, 0 ; D282001B 046E2D01 V_MUL_F32_e32 v25, v25, v26 ; 10323519 V_MAD_F32 v26, v12, v25, v27, 0, 0, 0, 0 ; D282001A 046E330C V_CMP_U_F32_e64 s[4:5], v26, v26, 0, 0, 0, 0 ; D0100004 0202351A V_CMP_LE_F32_e64 s[10:11], v26, 0.000000e+00, 0, 0, 0, 0 ; D006000A 0201011A S_OR_B64 s[4:5], s[10:11], s[4:5] ; 8884040A V_CNDMASK_B32_e64 v26, v26, 0.000000e+00, s[4:5], 0, 0, 0, 0 ; D200001A 0011011A V_ADD_I32_e32 v27, 144, v21 ; 4A362AFF 00000090 BUFFER_LOAD_DWORD v27, s[12:15] + v27 + 0, glc=0, slc=0, tfe=0 ; E0301000 80031B1B S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v28, v26, v27 ; 1038371A V_MUL_F32_e32 v28, v4, v28 ; 10383904 V_MUL_F32_e32 v23, v14, v23 ; 102E2F0E V_MAD_F32 v22, v13, v22, v23, 0, 0, 0, 0 ; D2820016 045E2D0D V_MAD_F32 v22, v15, v25, v22, 0, 0, 0, 0 ; D2820016 045A330F V_MOV_B32_e32 v23, 1.000000e-03 ; 7E2E02FF 3A83126F V_CMP_LE_F32_e64 s[4:5], v22, v23, 0, 0, 0, 0 ; D0060004 02022F16 V_CMP_U_F32_e64 s[10:11], v22, v22, 0, 0, 0, 0 ; D010000A 02022D16 S_OR_B64 s[4:5], s[4:5], s[10:11] ; 88840A04 V_CNDMASK_B32_e64 v22, v22, v23, s[4:5], 0, 0, 0, 0 ; D2000016 00122F16 V_LOG_F32_e32 v22, v22 ; 7E2C4F16 V_MUL_LEGACY_F32_e32 v22, s6, v22 ; 0E2C2C06 V_EXP_F32_e32 v22, v22 ; 7E2C4B16 V_MUL_F32_e32 v23, v22, v27 ; 102E3716 V_MAD_F32 v23, v23, s7, v28, 0, 0, 0, 0 ; D2820017 04700F17 V_ADD_I32_e32 v25, 160, v21 ; 4A322AFF 000000A0 BUFFER_LOAD_DWORD v25, s[12:15] + v25 + 0, glc=0, slc=0, tfe=0 ; E0301000 80031919 S_WAITCNT vmcnt(0) ; BF8C0770 V_MAD_F32 v24, v25, -5.000000e-01, v24, 0, 0, 0, 0 ; D2820018 0461E319 V_MAD_F32 v25, v25, -5.000000e-01, v25, 0, 0, 0, 0 ; D2820019 0465E319 V_RCP_F32_e32 v25, v25 ; 7E325519 V_MUL_F32_e32 v24, v24, v25 ; 10303318 V_ADD_F32_e64 v24, 0, v24, 0, 1, 0, 0 ; D2060818 02023080 V_ADD_F32_e32 v25, v24, v24 ; 06323118 V_SUB_F32_e32 v25, 3.000000e+00, v25 ; 083232FF 40400000 V_MUL_F32_e32 v25, v24, v25 ; 10323318 V_MUL_F32_e32 v24, v24, v25 ; 10303318 V_SUB_F32_e32 v24, 1.000000e+00, v24 ; 083030F2 V_MAD_F32 v25, v23, v24, v20, 0, 0, 0, 0 ; D2820019 04523117 V_ADD_I32_e32 v23, 128, v21 ; 4A2E2AFF 00000080 BUFFER_LOAD_DWORD v23, s[12:15] + v23 + 0, glc=0, slc=0, tfe=0 ; E0301000 80031717 S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v27, v26, v23 ; 10362F1A V_MUL_F32_e32 v27, v2, v27 ; 10363702 V_MUL_F32_e32 v23, v22, v23 ; 102E2F16 V_MAD_F32 v23, v23, s8, v27, 0, 0, 0, 0 ; D2820017 046C1117 V_MAD_F32 v23, v23, v24, v19, 0, 0, 0, 0 ; D2820017 044E3117 V_ADD_I32_e32 v21, 112, v21 ; 4A2A2AFF 00000070 BUFFER_LOAD_DWORD v21, s[12:15] + v21 + 0, glc=0, slc=0, tfe=0 ; E0301000 80031515 S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v26, v26, v21 ; 10342B1A V_MUL_F32_e32 v26, v3, v26 ; 10343503 V_MUL_F32_e32 v21, v22, v21 ; 102A2B16 V_MAD_F32 v21, v21, s9, v26, 0, 0, 0, 0 ; D2820015 04681315 V_MAD_F32 v21, v21, v24, v18, 0, 0, 0, 0 ; D2820015 044A3115 V_ADD_I32_e32 v16, 1, v16 ; 4A202081 S_OR_B64 exec, exec, s[2:3] ; 88FE027E S_OR_B64 s[0:1], s[2:3], s[0:1] ; 88800002 S_ANDN2_B64 exec, exec, s[0:1] ; 8AFE007E S_CBRANCH_EXECNZ BB0_11 ; BF890000 S_OR_B64 exec, exec, s[0:1] ; 88FE007E V_CVT_PKRTZ_F16_F32_e64 v0, v20, v8, 0, 0, 0, 0 ; D25E0000 02021114 V_CVT_PKRTZ_F16_F32_e64 v1, v18, v19, 0, 0, 0, 0 ; D25E0001 02022712 EXP 15, 0, 1, 1, 1, v1, v0, v1, v0 ; F8001C0F 00010001 S_ENDPGM ; BF810000 VERT DCL IN[0] DCL IN[1] DCL IN[2] DCL IN[3] DCL OUT[0], POSITION DCL OUT[1], GENERIC[20] DCL OUT[2], GENERIC[21] DCL OUT[3], GENERIC[22] DCL OUT[4], GENERIC[23] DCL CONST[0..3] DCL CONST[1][0..96] DCL CONST[2][0..68] DCL TEMP[0..6], LOCAL DCL ADDR[0] IMM[0] UINT32 {0, 176, 160, 144} IMM[1] INT32 {11, 10, 9, 8} IMM[2] UINT32 {128, 48, 32, 16} IMM[3] INT32 {3, 2, 1, 0} 0: MUL TEMP[0], CONST[0], IN[0].xxxx 1: MAD TEMP[0], CONST[1], IN[0].yyyy, TEMP[0] 2: MAD TEMP[0], CONST[2], IN[0].zzzz, TEMP[0] 3: ADD TEMP[0], TEMP[0], CONST[3] 4: UARL ADDR[0].x, IMM[1].xxxx 5: MOV TEMP[1], CONST[1][ADDR[0].x] 6: UARL ADDR[0].x, IMM[1].yyyy 7: MOV TEMP[2], CONST[1][ADDR[0].x] 8: UARL ADDR[0].x, IMM[1].zzzz 9: MOV TEMP[3], CONST[1][ADDR[0].x] 10: UARL ADDR[0].x, IMM[1].wwww 11: MOV TEMP[4], CONST[1][ADDR[0].x] 12: MUL TEMP[4], TEMP[4], TEMP[0].xxxx 13: MAD TEMP[3], TEMP[3], TEMP[0].yyyy, TEMP[4] 14: MAD TEMP[2], TEMP[2], TEMP[0].zzzz, TEMP[3] 15: MAD TEMP[1], TEMP[1], TEMP[0].wwww, TEMP[2] 16: MOV TEMP[2].x, IN[3].xxxx 17: MOV TEMP[2].yzw, IN[2].yxyz 18: UARL ADDR[0].x, IMM[3].xxxx 19: MOV TEMP[3], CONST[1][ADDR[0].x] 20: UARL ADDR[0].x, IMM[3].yyyy 21: MOV TEMP[4], CONST[1][ADDR[0].x] 22: UARL ADDR[0].x, IMM[3].zzzz 23: MOV TEMP[5], CONST[1][ADDR[0].x] 24: UARL ADDR[0].x, IMM[3].wwww 25: MOV TEMP[6], CONST[1][ADDR[0].x] 26: MUL TEMP[6], TEMP[6], TEMP[0].xxxx 27: MAD TEMP[5], TEMP[5], TEMP[0].yyyy, TEMP[6] 28: MAD TEMP[4], TEMP[4], TEMP[0].zzzz, TEMP[5] 29: MAD TEMP[0].xyz, TEMP[3], TEMP[0].wwww, TEMP[4] 30: MOV TEMP[0].xyz, TEMP[0].xyzx 31: MOV TEMP[0].w, IN[0].xxxx 32: MOV TEMP[3].xy, IN[0].yzyy 33: MOV TEMP[3].zw, IN[1].yyxy 34: MOV TEMP[4].x, IN[1].zzzz 35: MOV OUT[2], TEMP[0] 36: MOV OUT[4], TEMP[4] 37: MOV OUT[3], TEMP[3] 38: MOV OUT[0], TEMP[1] 39: MOV OUT[1], TEMP[2] 40: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0 %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0 %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0) %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4) %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8) %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12) %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16) %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20) %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24) %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28) %20 = call float @llvm.SI.load.const(<16 x i8> %11, i32 32) %21 = call float @llvm.SI.load.const(<16 x i8> %11, i32 36) %22 = call float @llvm.SI.load.const(<16 x i8> %11, i32 40) %23 = call float @llvm.SI.load.const(<16 x i8> %11, i32 44) %24 = call float @llvm.SI.load.const(<16 x i8> %11, i32 48) %25 = call float @llvm.SI.load.const(<16 x i8> %11, i32 52) %26 = call float @llvm.SI.load.const(<16 x i8> %11, i32 56) %27 = call float @llvm.SI.load.const(<16 x i8> %11, i32 60) %28 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 1 %29 = load <16 x i8> addrspace(2)* %28, !tbaa !0 %30 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 0 %31 = load <16 x i8> addrspace(2)* %30, !tbaa !0 %32 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %31, i32 0, i32 %6) %33 = extractelement <4 x float> %32, i32 0 %34 = extractelement <4 x float> %32, i32 1 %35 = extractelement <4 x float> %32, i32 2 %36 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 1 %37 = load <16 x i8> addrspace(2)* %36, !tbaa !0 %38 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %37, i32 0, i32 %6) %39 = extractelement <4 x float> %38, i32 0 %40 = extractelement <4 x float> %38, i32 1 %41 = extractelement <4 x float> %38, i32 2 %42 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 2 %43 = load <16 x i8> addrspace(2)* %42, !tbaa !0 %44 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %43, i32 0, i32 %6) %45 = extractelement <4 x float> %44, i32 0 %46 = extractelement <4 x float> %44, i32 1 %47 = extractelement <4 x float> %44, i32 2 %48 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 3 %49 = load <16 x i8> addrspace(2)* %48, !tbaa !0 %50 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %49, i32 0, i32 %6) %51 = extractelement <4 x float> %50, i32 0 %52 = fmul float %12, %33 %53 = fmul float %13, %33 %54 = fmul float %14, %33 %55 = fmul float %15, %33 %56 = fmul float %16, %34 %57 = fadd float %56, %52 %58 = fmul float %17, %34 %59 = fadd float %58, %53 %60 = fmul float %18, %34 %61 = fadd float %60, %54 %62 = fmul float %19, %34 %63 = fadd float %62, %55 %64 = fmul float %20, %35 %65 = fadd float %64, %57 %66 = fmul float %21, %35 %67 = fadd float %66, %59 %68 = fmul float %22, %35 %69 = fadd float %68, %61 %70 = fmul float %23, %35 %71 = fadd float %70, %63 %72 = fadd float %65, %24 %73 = fadd float %67, %25 %74 = fadd float %69, %26 %75 = fadd float %71, %27 %76 = shl i32 11, 4 %77 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %76) %78 = shl i32 11, 4 %79 = add i32 %78, 4 %80 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %79) %81 = shl i32 11, 4 %82 = add i32 %81, 8 %83 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %82) %84 = shl i32 11, 4 %85 = add i32 %84, 12 %86 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %85) %87 = shl i32 10, 4 %88 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %87) %89 = shl i32 10, 4 %90 = add i32 %89, 4 %91 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %90) %92 = shl i32 10, 4 %93 = add i32 %92, 8 %94 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %93) %95 = shl i32 10, 4 %96 = add i32 %95, 12 %97 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %96) %98 = shl i32 9, 4 %99 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %98) %100 = shl i32 9, 4 %101 = add i32 %100, 4 %102 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %101) %103 = shl i32 9, 4 %104 = add i32 %103, 8 %105 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %104) %106 = shl i32 9, 4 %107 = add i32 %106, 12 %108 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %107) %109 = shl i32 8, 4 %110 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %109) %111 = shl i32 8, 4 %112 = add i32 %111, 4 %113 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %112) %114 = shl i32 8, 4 %115 = add i32 %114, 8 %116 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %115) %117 = shl i32 8, 4 %118 = add i32 %117, 12 %119 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %118) %120 = fmul float %110, %72 %121 = fmul float %113, %72 %122 = fmul float %116, %72 %123 = fmul float %119, %72 %124 = fmul float %99, %73 %125 = fadd float %124, %120 %126 = fmul float %102, %73 %127 = fadd float %126, %121 %128 = fmul float %105, %73 %129 = fadd float %128, %122 %130 = fmul float %108, %73 %131 = fadd float %130, %123 %132 = fmul float %88, %74 %133 = fadd float %132, %125 %134 = fmul float %91, %74 %135 = fadd float %134, %127 %136 = fmul float %94, %74 %137 = fadd float %136, %129 %138 = fmul float %97, %74 %139 = fadd float %138, %131 %140 = fmul float %77, %75 %141 = fadd float %140, %133 %142 = fmul float %80, %75 %143 = fadd float %142, %135 %144 = fmul float %83, %75 %145 = fadd float %144, %137 %146 = fmul float %86, %75 %147 = fadd float %146, %139 %148 = shl i32 3, 4 %149 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %148) %150 = shl i32 3, 4 %151 = add i32 %150, 4 %152 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %151) %153 = shl i32 3, 4 %154 = add i32 %153, 8 %155 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %154) %156 = shl i32 2, 4 %157 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %156) %158 = shl i32 2, 4 %159 = add i32 %158, 4 %160 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %159) %161 = shl i32 2, 4 %162 = add i32 %161, 8 %163 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %162) %164 = shl i32 2, 4 %165 = add i32 %164, 12 %166 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %165) %167 = shl i32 1, 4 %168 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %167) %169 = shl i32 1, 4 %170 = add i32 %169, 4 %171 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %170) %172 = shl i32 1, 4 %173 = add i32 %172, 8 %174 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %173) %175 = shl i32 1, 4 %176 = add i32 %175, 12 %177 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %176) %178 = shl i32 0, 4 %179 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %178) %180 = shl i32 0, 4 %181 = add i32 %180, 4 %182 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %181) %183 = shl i32 0, 4 %184 = add i32 %183, 8 %185 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %184) %186 = shl i32 0, 4 %187 = add i32 %186, 12 %188 = call float @llvm.SI.load.const(<16 x i8> %29, i32 %187) %189 = fmul float %179, %72 %190 = fmul float %182, %72 %191 = fmul float %185, %72 %192 = fmul float %188, %72 %193 = fmul float %168, %73 %194 = fadd float %193, %189 %195 = fmul float %171, %73 %196 = fadd float %195, %190 %197 = fmul float %174, %73 %198 = fadd float %197, %191 %199 = fmul float %177, %73 %200 = fadd float %199, %192 %201 = fmul float %157, %74 %202 = fadd float %201, %194 %203 = fmul float %160, %74 %204 = fadd float %203, %196 %205 = fmul float %163, %74 %206 = fadd float %205, %198 %207 = fmul float %166, %74 %208 = fadd float %207, %200 %209 = fmul float %149, %75 %210 = fadd float %209, %202 %211 = fmul float %152, %75 %212 = fadd float %211, %204 %213 = fmul float %155, %75 %214 = fadd float %213, %206 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %51, float %45, float %46, float %47) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %210, float %212, float %214, float %33) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %34, float %35, float %39, float %40) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 35, i32 0, float %41, float %204, float %206, float %208) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %141, float %143, float %145, float %147) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" } attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_LOAD_DWORDX4 s[4:7], s[8:9], 8 ; C0820908 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[1:4], s[4:7][v0] + 0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80010100 S_LOAD_DWORDX4 s[4:7], s[8:9], 12 ; C082090C S_WAITCNT vmcnt(0) lgkmcnt(0) ; BF8C0070 BUFFER_LOAD_FORMAT_XYZW v[5:8], s[4:7][v0] + 0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80010500 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 32, 0, 0, 0, v5, v1, v2, v3 ; F800020F 03020105 S_LOAD_DWORDX4 s[4:7], s[8:9], 0 ; C0820900 S_WAITCNT expcnt(0) lgkmcnt(0) ; BF8C000F BUFFER_LOAD_FORMAT_XYZW v[1:4], s[4:7][v0] + 0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80010100 S_LOAD_DWORDX4 s[4:7], s[0:1], 0 ; C0820100 S_WAITCNT vmcnt(0) lgkmcnt(0) ; BF8C0070 S_BUFFER_LOAD_DWORD s2, s[4:7], 1 ; C2010501 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v5, s2, v1 ; 100A0202 S_BUFFER_LOAD_DWORD s2, s[4:7], 5 ; C2010505 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v5, s2, v2, v5, 0, 0, 0, 0 ; D2820005 04160402 S_BUFFER_LOAD_DWORD s2, s[4:7], 9 ; C2010509 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v5, s2, v3, v5, 0, 0, 0, 0 ; D2820005 04160602 S_BUFFER_LOAD_DWORD s2, s[4:7], 13 ; C201050D S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v5, s2, v5 ; 060A0A02 S_BUFFER_LOAD_DWORD s2, s[4:7], 0 ; C2010500 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v6, s2, v1 ; 100C0202 S_BUFFER_LOAD_DWORD s2, s[4:7], 4 ; C2010504 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v6, s2, v2, v6, 0, 0, 0, 0 ; D2820006 041A0402 S_BUFFER_LOAD_DWORD s2, s[4:7], 8 ; C2010508 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v6, s2, v3, v6, 0, 0, 0, 0 ; D2820006 041A0602 S_BUFFER_LOAD_DWORD s2, s[4:7], 12 ; C201050C S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v6, s2, v6 ; 060C0C02 S_LOAD_DWORDX4 s[0:3], s[0:1], 4 ; C0800104 S_WAITCNT lgkmcnt(0) ; BF8C007F S_BUFFER_LOAD_DWORD s10, s[0:3], 2 ; C2050102 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v7, s10, v6 ; 100E0C0A S_BUFFER_LOAD_DWORD s10, s[0:3], 6 ; C2050106 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v7, s10, v5, v7, 0, 0, 0, 0 ; D2820007 041E0A0A S_BUFFER_LOAD_DWORD s10, s[4:7], 2 ; C2050502 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v8, s10, v1 ; 1010020A S_BUFFER_LOAD_DWORD s10, s[4:7], 6 ; C2050506 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v8, s10, v2, v8, 0, 0, 0, 0 ; D2820008 0422040A S_BUFFER_LOAD_DWORD s10, s[4:7], 10 ; C205050A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v8, s10, v3, v8, 0, 0, 0, 0 ; D2820008 0422060A S_BUFFER_LOAD_DWORD s10, s[4:7], 14 ; C205050E S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v8, s10, v8 ; 0610100A S_BUFFER_LOAD_DWORD s10, s[0:3], 10 ; C205010A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v7, s10, v8, v7, 0, 0, 0, 0 ; D2820007 041E100A S_BUFFER_LOAD_DWORD s10, s[4:7], 3 ; C2050503 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v9, s10, v1 ; 1012020A S_BUFFER_LOAD_DWORD s10, s[4:7], 7 ; C2050507 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v9, s10, v2, v9, 0, 0, 0, 0 ; D2820009 0426040A S_BUFFER_LOAD_DWORD s10, s[4:7], 11 ; C205050B S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v9, s10, v3, v9, 0, 0, 0, 0 ; D2820009 0426060A S_BUFFER_LOAD_DWORD s4, s[4:7], 15 ; C202050F S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v9, s4, v9 ; 06121204 S_BUFFER_LOAD_DWORD s4, s[0:3], 14 ; C202010E S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v10, s4, v9, v7, 0, 0, 0, 0 ; D282000A 041E1204 S_BUFFER_LOAD_DWORD s4, s[0:3], 1 ; C2020101 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v11, s4, v6 ; 10160C04 S_BUFFER_LOAD_DWORD s4, s[0:3], 5 ; C2020105 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v11, s4, v5, v11, 0, 0, 0, 0 ; D282000B 042E0A04 S_BUFFER_LOAD_DWORD s4, s[0:3], 9 ; C2020109 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v11, s4, v8, v11, 0, 0, 0, 0 ; D282000B 042E1004 S_BUFFER_LOAD_DWORD s4, s[0:3], 13 ; C202010D S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v12, s4, v9, v11, 0, 0, 0, 0 ; D282000C 042E1204 S_BUFFER_LOAD_DWORD s4, s[0:3], 0 ; C2020100 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v13, s4, v6 ; 101A0C04 S_BUFFER_LOAD_DWORD s4, s[0:3], 4 ; C2020104 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v13, s4, v5, v13, 0, 0, 0, 0 ; D282000D 04360A04 S_BUFFER_LOAD_DWORD s4, s[0:3], 8 ; C2020108 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v13, s4, v8, v13, 0, 0, 0, 0 ; D282000D 04361004 S_BUFFER_LOAD_DWORD s4, s[0:3], 12 ; C202010C S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v13, s4, v9, v13, 0, 0, 0, 0 ; D282000D 04361204 EXP 15, 33, 0, 0, 0, v13, v12, v10, v1 ; F800021F 010A0C0D S_LOAD_DWORDX4 s[4:7], s[8:9], 4 ; C0820904 S_WAITCNT expcnt(0) lgkmcnt(0) ; BF8C000F BUFFER_LOAD_FORMAT_XYZW v[12:15], s[4:7][v0] + 0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80010C00 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 34, 0, 0, 0, v2, v3, v12, v13 ; F800022F 0D0C0302 S_BUFFER_LOAD_DWORD s4, s[0:3], 3 ; C2020103 S_WAITCNT expcnt(0) lgkmcnt(0) ; BF8C000F V_MUL_F32_e32 v0, s4, v6 ; 10000C04 S_BUFFER_LOAD_DWORD s4, s[0:3], 7 ; C2020107 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v0, s4, v5, v0, 0, 0, 0, 0 ; D2820000 04020A04 S_BUFFER_LOAD_DWORD s4, s[0:3], 11 ; C202010B S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v0, s4, v8, v0, 0, 0, 0, 0 ; D2820000 04021004 EXP 15, 35, 0, 0, 0, v14, v11, v7, v0 ; F800023F 00070B0E S_BUFFER_LOAD_DWORD s4, s[0:3], 35 ; C2020123 S_WAITCNT expcnt(0) lgkmcnt(0) ; BF8C000F V_MUL_F32_e32 v0, s4, v6 ; 10000C04 S_BUFFER_LOAD_DWORD s4, s[0:3], 39 ; C2020127 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v0, s4, v5, v0, 0, 0, 0, 0 ; D2820000 04020A04 S_BUFFER_LOAD_DWORD s4, s[0:3], 43 ; C202012B S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v0, s4, v8, v0, 0, 0, 0, 0 ; D2820000 04021004 S_BUFFER_LOAD_DWORD s4, s[0:3], 47 ; C202012F S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v0, s4, v9, v0, 0, 0, 0, 0 ; D2820000 04021204 S_BUFFER_LOAD_DWORD s4, s[0:3], 34 ; C2020122 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v1, s4, v6 ; 10020C04 S_BUFFER_LOAD_DWORD s4, s[0:3], 38 ; C2020126 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v1, s4, v5, v1, 0, 0, 0, 0 ; D2820001 04060A04 S_BUFFER_LOAD_DWORD s4, s[0:3], 42 ; C202012A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v1, s4, v8, v1, 0, 0, 0, 0 ; D2820001 04061004 S_BUFFER_LOAD_DWORD s4, s[0:3], 46 ; C202012E S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v1, s4, v9, v1, 0, 0, 0, 0 ; D2820001 04061204 S_BUFFER_LOAD_DWORD s4, s[0:3], 33 ; C2020121 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v2, s4, v6 ; 10040C04 S_BUFFER_LOAD_DWORD s4, s[0:3], 37 ; C2020125 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v2, s4, v5, v2, 0, 0, 0, 0 ; D2820002 040A0A04 S_BUFFER_LOAD_DWORD s4, s[0:3], 41 ; C2020129 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v2, s4, v8, v2, 0, 0, 0, 0 ; D2820002 040A1004 S_BUFFER_LOAD_DWORD s4, s[0:3], 45 ; C202012D S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v2, s4, v9, v2, 0, 0, 0, 0 ; D2820002 040A1204 S_BUFFER_LOAD_DWORD s4, s[0:3], 32 ; C2020120 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v3, s4, v6 ; 10060C04 S_BUFFER_LOAD_DWORD s4, s[0:3], 36 ; C2020124 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v3, s4, v5, v3, 0, 0, 0, 0 ; D2820003 040E0A04 S_BUFFER_LOAD_DWORD s4, s[0:3], 40 ; C2020128 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v3, s4, v8, v3, 0, 0, 0, 0 ; D2820003 040E1004 S_BUFFER_LOAD_DWORD s0, s[0:3], 44 ; C200012C S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v3, s0, v9, v3, 0, 0, 0, 0 ; D2820003 040E1200 EXP 15, 12, 0, 1, 0, v3, v2, v1, v0 ; F80008CF 00010203 S_ENDPGM ; BF810000 FRAG DCL IN[0], FACE, CONSTANT DCL IN[1], GENERIC[20], PERSPECTIVE DCL IN[2], GENERIC[21], PERSPECTIVE DCL IN[3], GENERIC[22], PERSPECTIVE DCL OUT[0], COLOR DCL SAMP[0] DCL SAMP[1] DCL SAMP[2] DCL CONST[2..73] DCL CONST[75] DCL CONST[1][0..96] DCL CONST[2][0..68] DCL TEMP[0] DCL TEMP[1..39], LOCAL DCL ADDR[0] IMM[0] UINT32 {0, 4294967295, 224, 208} IMM[1] FLT32 { 0.9010, 0.0100, 0.0000, 0.9000} IMM[2] FLT32 { 0.0010, 1.0000, 1.0500, 0.8000} IMM[3] INT32 {14, 13, 12, 15} IMM[4] UINT32 {192, 240, 1, 256} IMM[5] INT32 {16, 6, 5, 4} IMM[6] UINT32 {96, 80, 64, 112} IMM[7] INT32 {7, 10, 9, 8} IMM[8] FLT32 { 0.7213, -1.0000, 0.5000, -0.8000} IMM[9] UINT32 {252, 264, 160, 144} IMM[10] UINT32 {128, 176, 260, 0} IMM[11] INT32 {11, 0, 1, 2} IMM[12] FLT32 { 5.0000, 3.0000, 2.0000, 0.0000} IMM[13] INT32 {3, 0, 0, 0} 0: MOV_SAT TEMP[0], IN[0] 1: MOV TEMP[1].xy, IN[1].zwzz 2: MOV TEMP[1].z, IN[2].xxxx 3: MOV TEMP[2].x, IMM[0].xxxx 4: MOV TEMP[3].xy, IN[1].xyyy 5: TEX TEMP[3], TEMP[3], SAMP[2], 2D 6: MOV TEMP[4].w, TEMP[3] 7: MOV TEMP[5].x, -IN[3].zzzz 8: MUL TEMP[6].x, TEMP[5].xxxx, IMM[1].yyyy 9: MAX TEMP[6].x, TEMP[6].xxxx, IMM[1].zzzz 10: MIN TEMP[6].x, TEMP[6].xxxx, IMM[1].wwww 11: ADD TEMP[5].x, IMM[1].xxxx, -TEMP[6].xxxx 12: FSLT TEMP[5].x, TEMP[3].wwww, TEMP[5].xxxx 13: UIF TEMP[5].xxxx :1 14: MOV TEMP[2].x, IMM[0].yyyy 15: KILL 16: ENDIF 17: ADD TEMP[5].x, TEMP[3].wwww, IMM[2].xxxx 18: RCP TEMP[5].x, TEMP[5].xxxx 19: MUL TEMP[4].xyz, TEMP[3].xyzz, TEMP[5].xxxx 20: MUL TEMP[4].xyz, TEMP[4].xyzz, IN[2].yzww 21: NOT TEMP[3].x, TEMP[0].xxxx 22: AND TEMP[3].x, TEMP[3].xxxx, IMM[2].yyyy 23: LRP TEMP[1].xyz, TEMP[3].xxxx, -TEMP[1].xyzz, TEMP[1].xyzz 24: MOV TEMP[3].xyz, TEMP[1].xyzx 25: MOV TEMP[5].xyz, TEMP[4].xyzx 26: UARL ADDR[0].x, IMM[3].xxxx 27: MOV TEMP[6], CONST[1][ADDR[0].x] 28: UARL ADDR[0].x, IMM[3].yyyy 29: MOV TEMP[7], CONST[1][ADDR[0].x] 30: UARL ADDR[0].x, IMM[3].zzzz 31: MOV TEMP[8], CONST[1][ADDR[0].x] 32: MUL TEMP[8], TEMP[8], IN[3].xxxx 33: MAD TEMP[7], TEMP[7], IN[3].yyyy, TEMP[8] 34: MAD TEMP[6], TEMP[6], IN[3].zzzz, TEMP[7] 35: UARL ADDR[0].x, IMM[3].wwww 36: MOV TEMP[7], CONST[1][ADDR[0].x] 37: ADD TEMP[6], TEMP[6], TEMP[7] 38: MOV TEMP[7].xyz, TEMP[6].xyzx 39: ADD_SAT TEMP[8].x, TEMP[1].yyyy, IMM[2].zzzz 40: UARL ADDR[0].x, IMM[3].xxxx 41: MOV TEMP[9].xyz, CONST[2][ADDR[0].x].xyzz 42: MUL TEMP[8].xyz, TEMP[8].xxxx, TEMP[9].xyzz 43: MUL TEMP[8].xyz, TEMP[4].xyzz, TEMP[8].xyzz 44: UARL ADDR[0].x, IMM[3].zzzz 45: MOV TEMP[9].xyz, CONST[2][ADDR[0].x].xyzz 46: DP3 TEMP[9].x, TEMP[1].xyzz, TEMP[9].xyzz 47: MAX TEMP[9].x, IMM[1].zzzz, TEMP[9].xxxx 48: UARL ADDR[0].x, IMM[3].yyyy 49: MOV TEMP[10].xyz, CONST[2][ADDR[0].x].xyzz 50: MUL TEMP[9].xyz, TEMP[9].xxxx, TEMP[10].xyzz 51: MUL TEMP[9].xyz, TEMP[9].xyzz, TEMP[4].xyzz 52: UARL ADDR[0].x, IMM[3].wwww 53: MOV TEMP[10].xyz, CONST[2][ADDR[0].x].xyzz 54: ADD TEMP[10].xyz, TEMP[6].xyzz, -TEMP[10].xyzz 55: DP3 TEMP[10].x, TEMP[10].xyzz, TEMP[10].xyzz 56: RSQ TEMP[11].x, TEMP[10].xxxx 57: MUL TEMP[11].x, TEMP[11].xxxx, TEMP[10].xxxx 58: CMP TEMP[10].x, -TEMP[10].xxxx, TEMP[11].xxxx, IMM[1].zzzz 59: MOV TEMP[11].x, IMM[1].zzzz 60: UARL ADDR[0].x, IMM[5].xxxx 61: UARL ADDR[0].x, IMM[5].xxxx 62: MOV TEMP[12].x, CONST[2][ADDR[0].x].xxxx 63: MUL TEMP[12].x, IMM[2].wwww, TEMP[12].xxxx 64: FSLT TEMP[12].x, TEMP[10].xxxx, TEMP[12].xxxx 65: UIF TEMP[12].xxxx :1 66: UARL ADDR[0].x, IMM[5].yyyy 67: MOV TEMP[12], CONST[2][ADDR[0].x] 68: UARL ADDR[0].x, IMM[5].zzzz 69: MOV TEMP[13], CONST[2][ADDR[0].x] 70: UARL ADDR[0].x, IMM[5].wwww 71: MOV TEMP[14], CONST[2][ADDR[0].x] 72: MUL TEMP[14], TEMP[14], TEMP[6].xxxx 73: MAD TEMP[13], TEMP[13], TEMP[6].yyyy, TEMP[14] 74: MAD TEMP[12], TEMP[12], TEMP[6].zzzz, TEMP[13] 75: UARL ADDR[0].x, IMM[7].xxxx 76: MOV TEMP[13], CONST[2][ADDR[0].x] 77: ADD TEMP[12], TEMP[12], TEMP[13] 78: UARL ADDR[0].x, IMM[3].wwww 79: MOV TEMP[13].x, CONST[2][ADDR[0].x].wwww 80: MAX TEMP[14].x, TEMP[12].zzzz, IMM[8].yyyy 81: MIN TEMP[14].x, TEMP[14].xxxx, IMM[2].yyyy 82: ADD TEMP[14].x, TEMP[14].xxxx, IMM[2].yyyy 83: MUL TEMP[13].x, -TEMP[13].xxxx, TEMP[14].xxxx 84: MUL TEMP[13].x, IMM[8].xxxx, TEMP[13].xxxx 85: EX2 TEMP[13].x, TEMP[13].xxxx 86: MAD TEMP[12].xy, TEMP[12].xyyy, IMM[8].zzzz, IMM[8].zzzz 87: UARL ADDR[0].x, IMM[5].xxxx 88: MOV TEMP[14].x, CONST[2][ADDR[0].x].zzzz 89: MUL TEMP[12].xy, TEMP[12].xyyy, TEMP[14].xxxx 90: MOV TEMP[12].xy, TEMP[12].xyyy 91: TEX TEMP[12], TEMP[12], SAMP[0], RECT 92: MUL_SAT TEMP[12].x, TEMP[13].xxxx, TEMP[12].xxxx 93: MOV TEMP[11].x, TEMP[12].xxxx 94: ELSE :1 95: UARL ADDR[0].x, IMM[5].xxxx 96: UARL ADDR[0].x, IMM[5].xxxx 97: MOV TEMP[12].x, CONST[2][ADDR[0].x].xxxx 98: FSLT TEMP[12].x, TEMP[12].xxxx, TEMP[10].xxxx 99: UIF TEMP[12].xxxx :1 100: UARL ADDR[0].x, IMM[7].yyyy 101: MOV TEMP[12], CONST[2][ADDR[0].x] 102: UARL ADDR[0].x, IMM[7].zzzz 103: MOV TEMP[13], CONST[2][ADDR[0].x] 104: UARL ADDR[0].x, IMM[7].wwww 105: MOV TEMP[14], CONST[2][ADDR[0].x] 106: MUL TEMP[14], TEMP[14], TEMP[6].xxxx 107: MAD TEMP[13], TEMP[13], TEMP[6].yyyy, TEMP[14] 108: MAD TEMP[12], TEMP[12], TEMP[6].zzzz, TEMP[13] 109: UARL ADDR[0].x, IMM[11].xxxx 110: MOV TEMP[13], CONST[2][ADDR[0].x] 111: ADD TEMP[12], TEMP[12], TEMP[13] 112: UARL ADDR[0].x, IMM[3].wwww 113: MOV TEMP[13].xyz, CONST[2][ADDR[0].x].xyzz 114: ADD TEMP[13].xyz, TEMP[6].xyzz, -TEMP[13].xyzz 115: DP3 TEMP[13].x, TEMP[13].xyzz, TEMP[13].xyzz 116: RSQ TEMP[14].x, TEMP[13].xxxx 117: MUL TEMP[14].x, TEMP[14].xxxx, TEMP[13].xxxx 118: CMP TEMP[14].x, -TEMP[13].xxxx, TEMP[14].xxxx, IMM[1].zzzz 119: UARL ADDR[0].x, IMM[5].xxxx 120: MOV TEMP[13].x, CONST[2][ADDR[0].x].yyyy 121: RCP TEMP[13].x, TEMP[13].xxxx 122: MAD TEMP[13].x, TEMP[14].xxxx, TEMP[13].xxxx, IMM[8].wwww 123: MUL_SAT TEMP[13].x, TEMP[13].xxxx, IMM[12].xxxx 124: UARL ADDR[0].x, IMM[3].wwww 125: MOV TEMP[14].x, CONST[2][ADDR[0].x].wwww 126: MAX TEMP[15].x, TEMP[12].zzzz, IMM[8].yyyy 127: MIN TEMP[15].x, TEMP[15].xxxx, IMM[2].yyyy 128: ADD TEMP[15].x, TEMP[15].xxxx, IMM[2].yyyy 129: MUL TEMP[14].x, -TEMP[14].xxxx, TEMP[15].xxxx 130: MUL TEMP[14].x, IMM[8].xxxx, TEMP[14].xxxx 131: EX2 TEMP[14].x, TEMP[14].xxxx 132: MAD TEMP[12].xy, TEMP[12].xyyy, IMM[8].zzzz, IMM[8].zzzz 133: UARL ADDR[0].x, IMM[5].xxxx 134: MOV TEMP[15].x, CONST[2][ADDR[0].x].zzzz 135: MUL TEMP[12].xy, TEMP[12].xyyy, TEMP[15].xxxx 136: MOV TEMP[12].xy, TEMP[12].xyyy 137: TEX TEMP[12], TEMP[12], SAMP[1], RECT 138: MUL_SAT TEMP[12].x, TEMP[14].xxxx, TEMP[12].xxxx 139: MUL TEMP[14].x, IMM[12].zzzz, TEMP[13].xxxx 140: ADD TEMP[14].x, IMM[12].yyyy, -TEMP[14].xxxx 141: MUL TEMP[14].x, TEMP[13].xxxx, TEMP[14].xxxx 142: MUL TEMP[13].x, TEMP[13].xxxx, TEMP[14].xxxx 143: LRP TEMP[11].x, TEMP[13].xxxx, IMM[2].yyyy, TEMP[12].xxxx 144: ELSE :1 145: UARL ADDR[0].x, IMM[5].yyyy 146: MOV TEMP[12], CONST[2][ADDR[0].x] 147: UARL ADDR[0].x, IMM[5].zzzz 148: MOV TEMP[13], CONST[2][ADDR[0].x] 149: UARL ADDR[0].x, IMM[5].wwww 150: MOV TEMP[14], CONST[2][ADDR[0].x] 151: MUL TEMP[14], TEMP[14], TEMP[6].xxxx 152: MAD TEMP[13], TEMP[13], TEMP[6].yyyy, TEMP[14] 153: MAD TEMP[12], TEMP[12], TEMP[6].zzzz, TEMP[13] 154: UARL ADDR[0].x, IMM[7].xxxx 155: MOV TEMP[13], CONST[2][ADDR[0].x] 156: ADD TEMP[12], TEMP[12], TEMP[13] 157: UARL ADDR[0].x, IMM[7].yyyy 158: MOV TEMP[13], CONST[2][ADDR[0].x] 159: UARL ADDR[0].x, IMM[7].zzzz 160: MOV TEMP[14], CONST[2][ADDR[0].x] 161: UARL ADDR[0].x, IMM[7].wwww 162: MOV TEMP[15], CONST[2][ADDR[0].x] 163: MUL TEMP[15], TEMP[15], TEMP[6].xxxx 164: MAD TEMP[14], TEMP[14], TEMP[6].yyyy, TEMP[15] 165: MAD TEMP[6], TEMP[13], TEMP[6].zzzz, TEMP[14] 166: UARL ADDR[0].x, IMM[11].xxxx 167: MOV TEMP[13], CONST[2][ADDR[0].x] 168: ADD TEMP[6], TEMP[6], TEMP[13] 169: UARL ADDR[0].x, IMM[5].xxxx 170: UARL ADDR[0].x, IMM[5].xxxx 171: MOV TEMP[13].x, CONST[2][ADDR[0].x].xxxx 172: MUL TEMP[14].x, IMM[2].wwww, TEMP[13].xxxx 173: ADD TEMP[10].x, TEMP[10].xxxx, -TEMP[14].xxxx 174: ADD TEMP[13].x, TEMP[13].xxxx, -TEMP[14].xxxx 175: RCP TEMP[13].x, TEMP[13].xxxx 176: MUL_SAT TEMP[10].x, TEMP[10].xxxx, TEMP[13].xxxx 177: UARL ADDR[0].x, IMM[3].wwww 178: UARL ADDR[0].x, IMM[3].wwww 179: MOV TEMP[13].x, CONST[2][ADDR[0].x].wwww 180: UARL ADDR[0].x, IMM[5].xxxx 181: UARL ADDR[0].x, IMM[5].xxxx 182: MOV TEMP[14].x, CONST[2][ADDR[0].x].zzzz 183: MAX TEMP[15].x, TEMP[12].zzzz, IMM[8].yyyy 184: MIN TEMP[15].x, TEMP[15].xxxx, IMM[2].yyyy 185: ADD TEMP[15].x, TEMP[15].xxxx, IMM[2].yyyy 186: MUL TEMP[15].x, -TEMP[13].xxxx, TEMP[15].xxxx 187: MUL TEMP[15].x, IMM[8].xxxx, TEMP[15].xxxx 188: EX2 TEMP[15].x, TEMP[15].xxxx 189: MAD TEMP[12].xy, TEMP[12].xyyy, IMM[8].zzzz, IMM[8].zzzz 190: MUL TEMP[12].xy, TEMP[12].xyyy, TEMP[14].xxxx 191: MOV TEMP[12].xy, TEMP[12].xyyy 192: TEX TEMP[12], TEMP[12], SAMP[0], RECT 193: MUL_SAT TEMP[12].x, TEMP[15].xxxx, TEMP[12].xxxx 194: MAX TEMP[15].x, TEMP[6].zzzz, IMM[8].yyyy 195: MIN TEMP[15].x, TEMP[15].xxxx, IMM[2].yyyy 196: ADD TEMP[15].x, TEMP[15].xxxx, IMM[2].yyyy 197: MUL TEMP[13].x, -TEMP[13].xxxx, TEMP[15].xxxx 198: MUL TEMP[13].x, IMM[8].xxxx, TEMP[13].xxxx 199: EX2 TEMP[13].x, TEMP[13].xxxx 200: MAD TEMP[6].xy, TEMP[6].xyyy, IMM[8].zzzz, IMM[8].zzzz 201: MUL TEMP[6].xy, TEMP[6].xyyy, TEMP[14].xxxx 202: MOV TEMP[6].xy, TEMP[6].xyyy 203: TEX TEMP[6], TEMP[6], SAMP[1], RECT 204: MUL_SAT TEMP[6].x, TEMP[13].xxxx, TEMP[6].xxxx 205: MUL TEMP[13].x, IMM[12].zzzz, TEMP[10].xxxx 206: ADD TEMP[13].x, IMM[12].yyyy, -TEMP[13].xxxx 207: MUL TEMP[13].x, TEMP[10].xxxx, TEMP[13].xxxx 208: MUL TEMP[10].x, TEMP[10].xxxx, TEMP[13].xxxx 209: LRP TEMP[11].x, TEMP[10].xxxx, TEMP[6].xxxx, TEMP[12].xxxx 210: ENDIF 211: ENDIF 212: ADD TEMP[6].x, TEMP[11].xxxx, IMM[8].wwww 213: MUL_SAT TEMP[6].x, TEMP[6].xxxx, IMM[12].xxxx 214: MUL TEMP[10].x, IMM[12].zzzz, TEMP[6].xxxx 215: ADD TEMP[10].x, IMM[12].yyyy, -TEMP[10].xxxx 216: MUL TEMP[10].x, TEMP[6].xxxx, TEMP[10].xxxx 217: MUL TEMP[6].x, TEMP[6].xxxx, TEMP[10].xxxx 218: MUL TEMP[9].xyz, TEMP[9].xyzz, TEMP[6].xxxx 219: ADD TEMP[8].xyz, TEMP[8].xyzz, TEMP[9].xyzz 220: MOV TEMP[6].x, IMM[11].yyyy 221: BGNLOOP :1 222: ISGE TEMP[9].x, TEMP[6].xxxx, CONST[3].xxxx 223: UIF TEMP[9].xxxx :1 224: BRK 225: ENDIF 226: UMUL TEMP[10].x, TEMP[6].xxxx, IMM[7].xxxx 227: UARL ADDR[0].x, TEMP[10].xxxx 228: MOV TEMP[11].x, CONST[ADDR[0].x+4].xxxx 229: UADD TEMP[12].x, TEMP[10].xxxx, IMM[11].zzzz 230: UARL ADDR[0].x, TEMP[12].xxxx 231: MOV TEMP[11].y, CONST[ADDR[0].x+4].xxxx 232: UADD TEMP[13].x, TEMP[10].xxxx, IMM[11].wwww 233: UARL ADDR[0].x, TEMP[13].xxxx 234: MOV TEMP[11].z, CONST[ADDR[0].x+4].xxxx 235: UADD TEMP[14].x, TEMP[10].xxxx, IMM[13].xxxx 236: UARL ADDR[0].x, TEMP[14].xxxx 237: MOV TEMP[15].x, CONST[ADDR[0].x+4].xxxx 238: UADD TEMP[16].x, TEMP[10].xxxx, IMM[5].wwww 239: UARL ADDR[0].x, TEMP[16].xxxx 240: MOV TEMP[15].y, CONST[ADDR[0].x+4].xxxx 241: UADD TEMP[17].x, TEMP[10].xxxx, IMM[5].zzzz 242: UARL ADDR[0].x, TEMP[17].xxxx 243: MOV TEMP[15].z, CONST[ADDR[0].x+4].xxxx 244: UADD TEMP[18].x, TEMP[10].xxxx, IMM[5].yyyy 245: UARL ADDR[0].x, TEMP[18].xxxx 246: MOV TEMP[19].x, CONST[ADDR[0].x+4].xxxx 247: ADD TEMP[20].xyz, TEMP[11].xyzz, -TEMP[7].xyzz 248: DP3 TEMP[21].x, TEMP[20].xyzz, TEMP[20].xyzz 249: RSQ TEMP[22].x, TEMP[21].xxxx 250: MUL TEMP[22].x, TEMP[22].xxxx, TEMP[21].xxxx 251: CMP TEMP[23].x, -TEMP[21].xxxx, TEMP[22].xxxx, IMM[1].zzzz 252: RCP TEMP[24].x, TEMP[23].xxxx 253: MUL TEMP[25].xyz, TEMP[20].xyzz, TEMP[24].xxxx 254: DP3 TEMP[26].x, TEMP[3].xyzz, TEMP[25].xyzz 255: MAX TEMP[27].x, IMM[1].zzzz, TEMP[26].xxxx 256: MUL TEMP[28].xyz, TEMP[27].xxxx, TEMP[15].xyzz 257: MUL TEMP[29].xyz, TEMP[28].xyzz, TEMP[5].xyzz 258: MUL TEMP[30].x, TEMP[19].xxxx, IMM[8].zzzz 259: ADD TEMP[31].x, TEMP[23].xxxx, -TEMP[30].xxxx 260: ADD TEMP[32].x, TEMP[19].xxxx, -TEMP[30].xxxx 261: RCP TEMP[33].x, TEMP[32].xxxx 262: MUL_SAT TEMP[34].x, TEMP[31].xxxx, TEMP[33].xxxx 263: MUL TEMP[35].x, IMM[12].zzzz, TEMP[34].xxxx 264: ADD TEMP[36].x, IMM[12].yyyy, -TEMP[35].xxxx 265: MUL TEMP[37].x, TEMP[34].xxxx, TEMP[36].xxxx 266: MUL TEMP[38].x, TEMP[34].xxxx, TEMP[37].xxxx 267: ADD TEMP[39].x, IMM[2].yyyy, -TEMP[38].xxxx 268: MUL TEMP[29].xyz, TEMP[29].xyzz, TEMP[39].xxxx 269: ADD TEMP[8].xyz, TEMP[8].xyzz, TEMP[29].xyzz 270: UADD TEMP[6].x, TEMP[6].xxxx, IMM[11].zzzz 271: UIF TEMP[2].xxxx :1 272: BRK 273: ENDIF 274: ENDLOOP :1 275: MOV TEMP[1].xyz, -TEMP[1].xyzx 276: MOV TEMP[3].xyz, TEMP[4].xyzx 277: UARL ADDR[0].x, IMM[3].xxxx 278: MOV TEMP[5], CONST[1][ADDR[0].x] 279: UARL ADDR[0].x, IMM[3].yyyy 280: MOV TEMP[6], CONST[1][ADDR[0].x] 281: UARL ADDR[0].x, IMM[3].zzzz 282: MOV TEMP[7], CONST[1][ADDR[0].x] 283: MUL TEMP[7], TEMP[7], IN[3].xxxx 284: MAD TEMP[6], TEMP[6], IN[3].yyyy, TEMP[7] 285: MAD TEMP[5], TEMP[5], IN[3].zzzz, TEMP[6] 286: UARL ADDR[0].x, IMM[3].wwww 287: MOV TEMP[6], CONST[1][ADDR[0].x] 288: ADD TEMP[5], TEMP[5], TEMP[6] 289: MOV TEMP[6].xyz, TEMP[5].xyzx 290: ADD_SAT TEMP[7].x, TEMP[1].yyyy, IMM[2].zzzz 291: UARL ADDR[0].x, IMM[3].xxxx 292: MOV TEMP[9].xyz, CONST[2][ADDR[0].x].xyzz 293: MUL TEMP[7].xyz, TEMP[7].xxxx, TEMP[9].xyzz 294: MUL TEMP[7].xyz, TEMP[4].xyzz, TEMP[7].xyzz 295: UARL ADDR[0].x, IMM[3].zzzz 296: MOV TEMP[9].xyz, CONST[2][ADDR[0].x].xyzz 297: DP3 TEMP[9].x, TEMP[1].xyzz, TEMP[9].xyzz 298: MAX TEMP[9].x, IMM[1].zzzz, TEMP[9].xxxx 299: UARL ADDR[0].x, IMM[3].yyyy 300: MOV TEMP[10].xyz, CONST[2][ADDR[0].x].xyzz 301: MUL TEMP[9].xyz, TEMP[9].xxxx, TEMP[10].xyzz 302: MUL TEMP[4].xyz, TEMP[9].xyzz, TEMP[4].xyzz 303: UARL ADDR[0].x, IMM[3].wwww 304: MOV TEMP[9].xyz, CONST[2][ADDR[0].x].xyzz 305: ADD TEMP[9].xyz, TEMP[5].xyzz, -TEMP[9].xyzz 306: DP3 TEMP[9].x, TEMP[9].xyzz, TEMP[9].xyzz 307: RSQ TEMP[10].x, TEMP[9].xxxx 308: MUL TEMP[10].x, TEMP[10].xxxx, TEMP[9].xxxx 309: CMP TEMP[9].x, -TEMP[9].xxxx, TEMP[10].xxxx, IMM[1].zzzz 310: MOV TEMP[10].x, IMM[1].zzzz 311: UARL ADDR[0].x, IMM[5].xxxx 312: UARL ADDR[0].x, IMM[5].xxxx 313: MOV TEMP[11].x, CONST[2][ADDR[0].x].xxxx 314: MUL TEMP[11].x, IMM[2].wwww, TEMP[11].xxxx 315: FSLT TEMP[11].x, TEMP[9].xxxx, TEMP[11].xxxx 316: UIF TEMP[11].xxxx :1 317: UARL ADDR[0].x, IMM[5].yyyy 318: MOV TEMP[11], CONST[2][ADDR[0].x] 319: UARL ADDR[0].x, IMM[5].zzzz 320: MOV TEMP[12], CONST[2][ADDR[0].x] 321: UARL ADDR[0].x, IMM[5].wwww 322: MOV TEMP[13], CONST[2][ADDR[0].x] 323: MUL TEMP[13], TEMP[13], TEMP[5].xxxx 324: MAD TEMP[12], TEMP[12], TEMP[5].yyyy, TEMP[13] 325: MAD TEMP[11], TEMP[11], TEMP[5].zzzz, TEMP[12] 326: UARL ADDR[0].x, IMM[7].xxxx 327: MOV TEMP[12], CONST[2][ADDR[0].x] 328: ADD TEMP[11], TEMP[11], TEMP[12] 329: UARL ADDR[0].x, IMM[3].wwww 330: MOV TEMP[12].x, CONST[2][ADDR[0].x].wwww 331: MAX TEMP[13].x, TEMP[11].zzzz, IMM[8].yyyy 332: MIN TEMP[13].x, TEMP[13].xxxx, IMM[2].yyyy 333: ADD TEMP[13].x, TEMP[13].xxxx, IMM[2].yyyy 334: MUL TEMP[12].x, -TEMP[12].xxxx, TEMP[13].xxxx 335: MUL TEMP[12].x, IMM[8].xxxx, TEMP[12].xxxx 336: EX2 TEMP[12].x, TEMP[12].xxxx 337: MAD TEMP[11].xy, TEMP[11].xyyy, IMM[8].zzzz, IMM[8].zzzz 338: UARL ADDR[0].x, IMM[5].xxxx 339: MOV TEMP[13].x, CONST[2][ADDR[0].x].zzzz 340: MUL TEMP[11].xy, TEMP[11].xyyy, TEMP[13].xxxx 341: MOV TEMP[11].xy, TEMP[11].xyyy 342: TEX TEMP[11], TEMP[11], SAMP[0], RECT 343: MUL_SAT TEMP[11].x, TEMP[12].xxxx, TEMP[11].xxxx 344: MOV TEMP[10].x, TEMP[11].xxxx 345: ELSE :1 346: UARL ADDR[0].x, IMM[5].xxxx 347: UARL ADDR[0].x, IMM[5].xxxx 348: MOV TEMP[11].x, CONST[2][ADDR[0].x].xxxx 349: FSLT TEMP[11].x, TEMP[11].xxxx, TEMP[9].xxxx 350: UIF TEMP[11].xxxx :1 351: UARL ADDR[0].x, IMM[7].yyyy 352: MOV TEMP[11], CONST[2][ADDR[0].x] 353: UARL ADDR[0].x, IMM[7].zzzz 354: MOV TEMP[12], CONST[2][ADDR[0].x] 355: UARL ADDR[0].x, IMM[7].wwww 356: MOV TEMP[13], CONST[2][ADDR[0].x] 357: MUL TEMP[13], TEMP[13], TEMP[5].xxxx 358: MAD TEMP[12], TEMP[12], TEMP[5].yyyy, TEMP[13] 359: MAD TEMP[11], TEMP[11], TEMP[5].zzzz, TEMP[12] 360: UARL ADDR[0].x, IMM[11].xxxx 361: MOV TEMP[12], CONST[2][ADDR[0].x] 362: ADD TEMP[11], TEMP[11], TEMP[12] 363: UARL ADDR[0].x, IMM[3].wwww 364: MOV TEMP[12].xyz, CONST[2][ADDR[0].x].xyzz 365: ADD TEMP[12].xyz, TEMP[5].xyzz, -TEMP[12].xyzz 366: DP3 TEMP[12].x, TEMP[12].xyzz, TEMP[12].xyzz 367: RSQ TEMP[13].x, TEMP[12].xxxx 368: MUL TEMP[13].x, TEMP[13].xxxx, TEMP[12].xxxx 369: CMP TEMP[13].x, -TEMP[12].xxxx, TEMP[13].xxxx, IMM[1].zzzz 370: UARL ADDR[0].x, IMM[5].xxxx 371: MOV TEMP[12].x, CONST[2][ADDR[0].x].yyyy 372: RCP TEMP[12].x, TEMP[12].xxxx 373: MAD TEMP[12].x, TEMP[13].xxxx, TEMP[12].xxxx, IMM[8].wwww 374: MUL_SAT TEMP[12].x, TEMP[12].xxxx, IMM[12].xxxx 375: UARL ADDR[0].x, IMM[3].wwww 376: MOV TEMP[13].x, CONST[2][ADDR[0].x].wwww 377: MAX TEMP[14].x, TEMP[11].zzzz, IMM[8].yyyy 378: MIN TEMP[14].x, TEMP[14].xxxx, IMM[2].yyyy 379: ADD TEMP[14].x, TEMP[14].xxxx, IMM[2].yyyy 380: MUL TEMP[13].x, -TEMP[13].xxxx, TEMP[14].xxxx 381: MUL TEMP[13].x, IMM[8].xxxx, TEMP[13].xxxx 382: EX2 TEMP[13].x, TEMP[13].xxxx 383: MAD TEMP[11].xy, TEMP[11].xyyy, IMM[8].zzzz, IMM[8].zzzz 384: UARL ADDR[0].x, IMM[5].xxxx 385: MOV TEMP[14].x, CONST[2][ADDR[0].x].zzzz 386: MUL TEMP[11].xy, TEMP[11].xyyy, TEMP[14].xxxx 387: MOV TEMP[11].xy, TEMP[11].xyyy 388: TEX TEMP[11], TEMP[11], SAMP[1], RECT 389: MUL_SAT TEMP[11].x, TEMP[13].xxxx, TEMP[11].xxxx 390: MUL TEMP[13].x, IMM[12].zzzz, TEMP[12].xxxx 391: ADD TEMP[13].x, IMM[12].yyyy, -TEMP[13].xxxx 392: MUL TEMP[13].x, TEMP[12].xxxx, TEMP[13].xxxx 393: MUL TEMP[12].x, TEMP[12].xxxx, TEMP[13].xxxx 394: LRP TEMP[10].x, TEMP[12].xxxx, IMM[2].yyyy, TEMP[11].xxxx 395: ELSE :1 396: UARL ADDR[0].x, IMM[5].yyyy 397: MOV TEMP[11], CONST[2][ADDR[0].x] 398: UARL ADDR[0].x, IMM[5].zzzz 399: MOV TEMP[12], CONST[2][ADDR[0].x] 400: UARL ADDR[0].x, IMM[5].wwww 401: MOV TEMP[13], CONST[2][ADDR[0].x] 402: MUL TEMP[13], TEMP[13], TEMP[5].xxxx 403: MAD TEMP[12], TEMP[12], TEMP[5].yyyy, TEMP[13] 404: MAD TEMP[11], TEMP[11], TEMP[5].zzzz, TEMP[12] 405: UARL ADDR[0].x, IMM[7].xxxx 406: MOV TEMP[12], CONST[2][ADDR[0].x] 407: ADD TEMP[11], TEMP[11], TEMP[12] 408: UARL ADDR[0].x, IMM[7].yyyy 409: MOV TEMP[12], CONST[2][ADDR[0].x] 410: UARL ADDR[0].x, IMM[7].zzzz 411: MOV TEMP[13], CONST[2][ADDR[0].x] 412: UARL ADDR[0].x, IMM[7].wwww 413: MOV TEMP[14], CONST[2][ADDR[0].x] 414: MUL TEMP[14], TEMP[14], TEMP[5].xxxx 415: MAD TEMP[13], TEMP[13], TEMP[5].yyyy, TEMP[14] 416: MAD TEMP[5], TEMP[12], TEMP[5].zzzz, TEMP[13] 417: UARL ADDR[0].x, IMM[11].xxxx 418: MOV TEMP[12], CONST[2][ADDR[0].x] 419: ADD TEMP[5], TEMP[5], TEMP[12] 420: UARL ADDR[0].x, IMM[5].xxxx 421: UARL ADDR[0].x, IMM[5].xxxx 422: MOV TEMP[12].x, CONST[2][ADDR[0].x].xxxx 423: MUL TEMP[13].x, IMM[2].wwww, TEMP[12].xxxx 424: ADD TEMP[9].x, TEMP[9].xxxx, -TEMP[13].xxxx 425: ADD TEMP[12].x, TEMP[12].xxxx, -TEMP[13].xxxx 426: RCP TEMP[12].x, TEMP[12].xxxx 427: MUL_SAT TEMP[9].x, TEMP[9].xxxx, TEMP[12].xxxx 428: UARL ADDR[0].x, IMM[3].wwww 429: UARL ADDR[0].x, IMM[3].wwww 430: MOV TEMP[12].x, CONST[2][ADDR[0].x].wwww 431: UARL ADDR[0].x, IMM[5].xxxx 432: UARL ADDR[0].x, IMM[5].xxxx 433: MOV TEMP[13].x, CONST[2][ADDR[0].x].zzzz 434: MAX TEMP[14].x, TEMP[11].zzzz, IMM[8].yyyy 435: MIN TEMP[14].x, TEMP[14].xxxx, IMM[2].yyyy 436: ADD TEMP[14].x, TEMP[14].xxxx, IMM[2].yyyy 437: MUL TEMP[14].x, -TEMP[12].xxxx, TEMP[14].xxxx 438: MUL TEMP[14].x, IMM[8].xxxx, TEMP[14].xxxx 439: EX2 TEMP[14].x, TEMP[14].xxxx 440: MAD TEMP[11].xy, TEMP[11].xyyy, IMM[8].zzzz, IMM[8].zzzz 441: MUL TEMP[11].xy, TEMP[11].xyyy, TEMP[13].xxxx 442: MOV TEMP[11].xy, TEMP[11].xyyy 443: TEX TEMP[11], TEMP[11], SAMP[0], RECT 444: MUL_SAT TEMP[11].x, TEMP[14].xxxx, TEMP[11].xxxx 445: MAX TEMP[14].x, TEMP[5].zzzz, IMM[8].yyyy 446: MIN TEMP[14].x, TEMP[14].xxxx, IMM[2].yyyy 447: ADD TEMP[14].x, TEMP[14].xxxx, IMM[2].yyyy 448: MUL TEMP[12].x, -TEMP[12].xxxx, TEMP[14].xxxx 449: MUL TEMP[12].x, IMM[8].xxxx, TEMP[12].xxxx 450: EX2 TEMP[12].x, TEMP[12].xxxx 451: MAD TEMP[5].xy, TEMP[5].xyyy, IMM[8].zzzz, IMM[8].zzzz 452: MUL TEMP[5].xy, TEMP[5].xyyy, TEMP[13].xxxx 453: MOV TEMP[5].xy, TEMP[5].xyyy 454: TEX TEMP[5], TEMP[5], SAMP[1], RECT 455: MUL_SAT TEMP[5].x, TEMP[12].xxxx, TEMP[5].xxxx 456: MUL TEMP[12].x, IMM[12].zzzz, TEMP[9].xxxx 457: ADD TEMP[12].x, IMM[12].yyyy, -TEMP[12].xxxx 458: MUL TEMP[12].x, TEMP[9].xxxx, TEMP[12].xxxx 459: MUL TEMP[9].x, TEMP[9].xxxx, TEMP[12].xxxx 460: LRP TEMP[10].x, TEMP[9].xxxx, TEMP[5].xxxx, TEMP[11].xxxx 461: ENDIF 462: ENDIF 463: ADD TEMP[5].x, TEMP[10].xxxx, IMM[8].wwww 464: MUL_SAT TEMP[5].x, TEMP[5].xxxx, IMM[12].xxxx 465: MUL TEMP[9].x, IMM[12].zzzz, TEMP[5].xxxx 466: ADD TEMP[9].x, IMM[12].yyyy, -TEMP[9].xxxx 467: MUL TEMP[9].x, TEMP[5].xxxx, TEMP[9].xxxx 468: MUL TEMP[5].x, TEMP[5].xxxx, TEMP[9].xxxx 469: MUL TEMP[4].xyz, TEMP[4].xyzz, TEMP[5].xxxx 470: ADD TEMP[7].xyz, TEMP[7].xyzz, TEMP[4].xyzz 471: MOV TEMP[4].x, IMM[11].yyyy 472: BGNLOOP :1 473: ISGE TEMP[5].x, TEMP[4].xxxx, CONST[3].xxxx 474: UIF TEMP[5].xxxx :1 475: BRK 476: ENDIF 477: UMUL TEMP[9].x, TEMP[4].xxxx, IMM[7].xxxx 478: UARL ADDR[0].x, TEMP[9].xxxx 479: MOV TEMP[10].x, CONST[ADDR[0].x+4].xxxx 480: UADD TEMP[11].x, TEMP[9].xxxx, IMM[11].zzzz 481: UARL ADDR[0].x, TEMP[11].xxxx 482: MOV TEMP[10].y, CONST[ADDR[0].x+4].xxxx 483: UADD TEMP[12].x, TEMP[9].xxxx, IMM[11].wwww 484: UARL ADDR[0].x, TEMP[12].xxxx 485: MOV TEMP[10].z, CONST[ADDR[0].x+4].xxxx 486: UADD TEMP[13].x, TEMP[9].xxxx, IMM[13].xxxx 487: UARL ADDR[0].x, TEMP[13].xxxx 488: MOV TEMP[14].x, CONST[ADDR[0].x+4].xxxx 489: UADD TEMP[15].x, TEMP[9].xxxx, IMM[5].wwww 490: UARL ADDR[0].x, TEMP[15].xxxx 491: MOV TEMP[14].y, CONST[ADDR[0].x+4].xxxx 492: UADD TEMP[16].x, TEMP[9].xxxx, IMM[5].zzzz 493: UARL ADDR[0].x, TEMP[16].xxxx 494: MOV TEMP[14].z, CONST[ADDR[0].x+4].xxxx 495: UADD TEMP[17].x, TEMP[9].xxxx, IMM[5].yyyy 496: UARL ADDR[0].x, TEMP[17].xxxx 497: MOV TEMP[18].x, CONST[ADDR[0].x+4].xxxx 498: ADD TEMP[19].xyz, TEMP[10].xyzz, -TEMP[6].xyzz 499: DP3 TEMP[20].x, TEMP[19].xyzz, TEMP[19].xyzz 500: RSQ TEMP[21].x, TEMP[20].xxxx 501: MUL TEMP[21].x, TEMP[21].xxxx, TEMP[20].xxxx 502: CMP TEMP[22].x, -TEMP[20].xxxx, TEMP[21].xxxx, IMM[1].zzzz 503: RCP TEMP[23].x, TEMP[22].xxxx 504: MUL TEMP[24].xyz, TEMP[19].xyzz, TEMP[23].xxxx 505: DP3 TEMP[25].x, TEMP[1].xyzz, TEMP[24].xyzz 506: MAX TEMP[26].x, IMM[1].zzzz, TEMP[25].xxxx 507: MUL TEMP[27].xyz, TEMP[26].xxxx, TEMP[14].xyzz 508: MUL TEMP[28].xyz, TEMP[27].xyzz, TEMP[3].xyzz 509: MUL TEMP[29].x, TEMP[18].xxxx, IMM[8].zzzz 510: ADD TEMP[30].x, TEMP[22].xxxx, -TEMP[29].xxxx 511: ADD TEMP[31].x, TEMP[18].xxxx, -TEMP[29].xxxx 512: RCP TEMP[32].x, TEMP[31].xxxx 513: MUL_SAT TEMP[33].x, TEMP[30].xxxx, TEMP[32].xxxx 514: MUL TEMP[34].x, IMM[12].zzzz, TEMP[33].xxxx 515: ADD TEMP[35].x, IMM[12].yyyy, -TEMP[34].xxxx 516: MUL TEMP[36].x, TEMP[33].xxxx, TEMP[35].xxxx 517: MUL TEMP[37].x, TEMP[33].xxxx, TEMP[36].xxxx 518: ADD TEMP[38].x, IMM[2].yyyy, -TEMP[37].xxxx 519: MUL TEMP[28].xyz, TEMP[28].xyzz, TEMP[38].xxxx 520: ADD TEMP[7].xyz, TEMP[7].xyzz, TEMP[28].xyzz 521: UADD TEMP[4].x, TEMP[4].xxxx, IMM[11].zzzz 522: UIF TEMP[2].xxxx :1 523: BRK 524: ENDIF 525: ENDLOOP :1 526: ADD TEMP[1].xyz, TEMP[8].xyzz, TEMP[7].xyzz 527: MOV OUT[0], TEMP[1] 528: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { main_body: %22 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0 %23 = load <16 x i8> addrspace(2)* %22, !tbaa !0 %24 = call float @llvm.SI.load.const(<16 x i8> %23, i32 48) %25 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 1 %26 = load <16 x i8> addrspace(2)* %25, !tbaa !0 %27 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 2 %28 = load <16 x i8> addrspace(2)* %27, !tbaa !0 %29 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0 %30 = load <32 x i8> addrspace(2)* %29, !tbaa !0 %31 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0 %32 = load <16 x i8> addrspace(2)* %31, !tbaa !0 %33 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 1 %34 = load <32 x i8> addrspace(2)* %33, !tbaa !0 %35 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 1 %36 = load <16 x i8> addrspace(2)* %35, !tbaa !0 %37 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 2 %38 = load <32 x i8> addrspace(2)* %37, !tbaa !0 %39 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 2 %40 = load <16 x i8> addrspace(2)* %39, !tbaa !0 %41 = fcmp ugt float %18, 0.000000e+00 %42 = select i1 %41, float 1.000000e+00, float 0.000000e+00 %43 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %7) %44 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %7) %45 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %5, <2 x i32> %7) %46 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %5, <2 x i32> %7) %47 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %5, <2 x i32> %7) %48 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %5, <2 x i32> %7) %49 = call float @llvm.SI.fs.interp(i32 2, i32 1, i32 %5, <2 x i32> %7) %50 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %5, <2 x i32> %7) %51 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %5, <2 x i32> %7) %52 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %5, <2 x i32> %7) %53 = call float @llvm.SI.fs.interp(i32 2, i32 2, i32 %5, <2 x i32> %7) %54 = call float @llvm.AMDIL.clamp.(float %42, float 0.000000e+00, float 1.000000e+00) %55 = call float @llvm.AMDIL.clamp.(float 0.000000e+00, float 0.000000e+00, float 1.000000e+00) %56 = call float @llvm.AMDIL.clamp.(float 0.000000e+00, float 0.000000e+00, float 1.000000e+00) %57 = call float @llvm.AMDIL.clamp.(float 1.000000e+00, float 0.000000e+00, float 1.000000e+00) %58 = bitcast float %43 to i32 %59 = bitcast float %44 to i32 %60 = insertelement <2 x i32> undef, i32 %58, i32 0 %61 = insertelement <2 x i32> %60, i32 %59, i32 1 %62 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %61, <32 x i8> %38, <16 x i8> %40, i32 2) %63 = extractelement <4 x float> %62, i32 0 %64 = extractelement <4 x float> %62, i32 1 %65 = extractelement <4 x float> %62, i32 2 %66 = extractelement <4 x float> %62, i32 3 %67 = fsub float -0.000000e+00, %53 %68 = fmul float %67, 0x3F847AE140000000 %69 = fcmp uge float %68, 0.000000e+00 %70 = select i1 %69, float %68, float 0.000000e+00 %71 = fcmp uge float %70, 0x3FECCCCCC0000000 %72 = select i1 %71, float 0x3FECCCCCC0000000, float %70 %73 = fsub float -0.000000e+00, %72 %74 = fadd float 0x3FECD4FE00000000, %73 %75 = fcmp olt float %66, %74 %76 = sext i1 %75 to i32 %77 = bitcast i32 %76 to float %78 = bitcast float %77 to i32 %79 = icmp ne i32 %78, 0 br i1 %79, label %IF, label %ENDIF IF: ; preds = %main_body call void @llvm.AMDGPU.kilp() br label %ENDIF ENDIF: ; preds = %main_body, %IF %temp8.0 = phi float [ 0xFFFFFFFFE0000000, %IF ], [ 0.000000e+00, %main_body ] %80 = fadd float %66, 0x3F50624DE0000000 %81 = fdiv float 1.000000e+00, %80 %82 = fmul float %63, %81 %83 = fmul float %64, %81 %84 = fmul float %65, %81 %85 = fmul float %82, %48 %86 = fmul float %83, %49 %87 = fmul float %84, %50 %88 = bitcast float %54 to i32 %89 = xor i32 %88, -1 %90 = bitcast i32 %89 to float %91 = bitcast float %90 to i32 %92 = and i32 %91, 1065353216 %93 = bitcast i32 %92 to float %94 = fsub float -0.000000e+00, %45 %95 = call float @llvm.AMDGPU.lrp(float %93, float %94, float %45) %96 = fsub float -0.000000e+00, %46 %97 = call float @llvm.AMDGPU.lrp(float %93, float %96, float %46) %98 = fsub float -0.000000e+00, %47 %99 = call float @llvm.AMDGPU.lrp(float %93, float %98, float %47) %100 = shl i32 14, 4 %101 = call float @llvm.SI.load.const(<16 x i8> %26, i32 %100) %102 = shl i32 14, 4 %103 = add i32 %102, 4 %104 = call float @llvm.SI.load.const(<16 x i8> %26, i32 %103) %105 = shl i32 14, 4 %106 = add i32 %105, 8 %107 = call float @llvm.SI.load.const(<16 x i8> %26, i32 %106) %108 = shl i32 13, 4 %109 = call float @llvm.SI.load.const(<16 x i8> %26, i32 %108) %110 = shl i32 13, 4 %111 = add i32 %110, 4 %112 = call float @llvm.SI.load.const(<16 x i8> %26, i32 %111) %113 = shl i32 13, 4 %114 = add i32 %113, 8 %115 = call float @llvm.SI.load.const(<16 x i8> %26, i32 %114) %116 = shl i32 12, 4 %117 = call float @llvm.SI.load.const(<16 x i8> %26, i32 %116) %118 = shl i32 12, 4 %119 = add i32 %118, 4 %120 = call float @llvm.SI.load.const(<16 x i8> %26, i32 %119) %121 = shl i32 12, 4 %122 = add i32 %121, 8 %123 = call float @llvm.SI.load.const(<16 x i8> %26, i32 %122) %124 = fmul float %117, %51 %125 = fmul float %120, %51 %126 = fmul float %123, %51 %127 = fmul float %109, %52 %128 = fadd float %127, %124 %129 = fmul float %112, %52 %130 = fadd float %129, %125 %131 = fmul float %115, %52 %132 = fadd float %131, %126 %133 = fmul float %101, %53 %134 = fadd float %133, %128 %135 = fmul float %104, %53 %136 = fadd float %135, %130 %137 = fmul float %107, %53 %138 = fadd float %137, %132 %139 = shl i32 15, 4 %140 = call float @llvm.SI.load.const(<16 x i8> %26, i32 %139) %141 = shl i32 15, 4 %142 = add i32 %141, 4 %143 = call float @llvm.SI.load.const(<16 x i8> %26, i32 %142) %144 = shl i32 15, 4 %145 = add i32 %144, 8 %146 = call float @llvm.SI.load.const(<16 x i8> %26, i32 %145) %147 = fadd float %134, %140 %148 = fadd float %136, %143 %149 = fadd float %138, %146 %150 = fadd float %97, 0x3FF0CCCCC0000000 %151 = call float @llvm.AMDIL.clamp.(float %150, float 0.000000e+00, float 1.000000e+00) %152 = shl i32 14, 4 %153 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %152) %154 = shl i32 14, 4 %155 = add i32 %154, 4 %156 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %155) %157 = shl i32 14, 4 %158 = add i32 %157, 8 %159 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %158) %160 = fmul float %151, %153 %161 = fmul float %151, %156 %162 = fmul float %151, %159 %163 = fmul float %85, %160 %164 = fmul float %86, %161 %165 = fmul float %87, %162 %166 = shl i32 12, 4 %167 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %166) %168 = shl i32 12, 4 %169 = add i32 %168, 4 %170 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %169) %171 = shl i32 12, 4 %172 = add i32 %171, 8 %173 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %172) %174 = fmul float %95, %167 %175 = fmul float %97, %170 %176 = fadd float %175, %174 %177 = fmul float %99, %173 %178 = fadd float %176, %177 %179 = fcmp uge float 0.000000e+00, %178 %180 = select i1 %179, float 0.000000e+00, float %178 %181 = shl i32 13, 4 %182 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %181) %183 = shl i32 13, 4 %184 = add i32 %183, 4 %185 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %184) %186 = shl i32 13, 4 %187 = add i32 %186, 8 %188 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %187) %189 = fmul float %180, %182 %190 = fmul float %180, %185 %191 = fmul float %180, %188 %192 = fmul float %189, %85 %193 = fmul float %190, %86 %194 = fmul float %191, %87 %195 = shl i32 15, 4 %196 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %195) %197 = shl i32 15, 4 %198 = add i32 %197, 4 %199 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %198) %200 = shl i32 15, 4 %201 = add i32 %200, 8 %202 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %201) %203 = fsub float -0.000000e+00, %196 %204 = fadd float %147, %203 %205 = fsub float -0.000000e+00, %199 %206 = fadd float %148, %205 %207 = fsub float -0.000000e+00, %202 %208 = fadd float %149, %207 %209 = fmul float %204, %204 %210 = fmul float %206, %206 %211 = fadd float %210, %209 %212 = fmul float %208, %208 %213 = fadd float %211, %212 %214 = call float @llvm.AMDGPU.rsq(float %213) %215 = fmul float %214, %213 %216 = fsub float -0.000000e+00, %213 %217 = call float @llvm.AMDGPU.cndlt(float %216, float %215, float 0.000000e+00) %218 = shl i32 16, 4 %219 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %218) %220 = fmul float 0x3FE99999A0000000, %219 %221 = fcmp olt float %217, %220 %222 = sext i1 %221 to i32 %223 = bitcast i32 %222 to float %224 = bitcast float %223 to i32 %225 = icmp ne i32 %224, 0 br i1 %225, label %IF189, label %ELSE190 IF189: ; preds = %ENDIF %226 = shl i32 6, 4 %227 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %226) %228 = shl i32 6, 4 %229 = add i32 %228, 4 %230 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %229) %231 = shl i32 6, 4 %232 = add i32 %231, 8 %233 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %232) %234 = shl i32 5, 4 %235 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %234) %236 = shl i32 5, 4 %237 = add i32 %236, 4 %238 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %237) %239 = shl i32 5, 4 %240 = add i32 %239, 8 %241 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %240) %242 = shl i32 4, 4 %243 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %242) %244 = shl i32 4, 4 %245 = add i32 %244, 4 %246 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %245) %247 = shl i32 4, 4 %248 = add i32 %247, 8 %249 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %248) %250 = fmul float %243, %147 %251 = fmul float %246, %147 %252 = fmul float %249, %147 %253 = fmul float %235, %148 %254 = fadd float %253, %250 %255 = fmul float %238, %148 %256 = fadd float %255, %251 %257 = fmul float %241, %148 %258 = fadd float %257, %252 %259 = fmul float %227, %149 %260 = fadd float %259, %254 %261 = fmul float %230, %149 %262 = fadd float %261, %256 %263 = fmul float %233, %149 %264 = fadd float %263, %258 %265 = shl i32 7, 4 %266 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %265) %267 = shl i32 7, 4 %268 = add i32 %267, 4 %269 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %268) %270 = shl i32 7, 4 %271 = add i32 %270, 8 %272 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %271) %273 = fadd float %260, %266 %274 = fadd float %262, %269 %275 = fadd float %264, %272 %276 = shl i32 15, 4 %277 = add i32 %276, 12 %278 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %277) %279 = fcmp uge float %275, -1.000000e+00 %280 = select i1 %279, float %275, float -1.000000e+00 %281 = fcmp uge float %280, 1.000000e+00 %282 = select i1 %281, float 1.000000e+00, float %280 %283 = fadd float %282, 1.000000e+00 %284 = fsub float -0.000000e+00, %278 %285 = fmul float %284, %283 %286 = fmul float 0x3FE7154760000000, %285 %287 = call float @llvm.AMDIL.exp.(float %286) %288 = fmul float %273, 5.000000e-01 %289 = fadd float %288, 5.000000e-01 %290 = fmul float %274, 5.000000e-01 %291 = fadd float %290, 5.000000e-01 %292 = shl i32 16, 4 %293 = add i32 %292, 8 %294 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %293) %295 = fmul float %289, %294 %296 = fmul float %291, %294 %297 = bitcast float %295 to i32 %298 = bitcast float %296 to i32 %299 = insertelement <2 x i32> undef, i32 %297, i32 0 %300 = insertelement <2 x i32> %299, i32 %298, i32 1 %301 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %300, <32 x i8> %30, <16 x i8> %32, i32 5) %302 = extractelement <4 x float> %301, i32 0 %303 = fmul float %287, %302 %304 = call float @llvm.AMDIL.clamp.(float %303, float 0.000000e+00, float 1.000000e+00) br label %ENDIF188 ELSE190: ; preds = %ENDIF %305 = shl i32 16, 4 %306 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %305) %307 = fcmp olt float %306, %217 %308 = sext i1 %307 to i32 %309 = bitcast i32 %308 to float %310 = bitcast float %309 to i32 %311 = icmp ne i32 %310, 0 br i1 %311, label %IF211, label %ELSE212 ENDIF188: ; preds = %IF211, %ELSE212, %IF189 %temp44.0 = phi float [ %304, %IF189 ], [ %447, %IF211 ], [ %615, %ELSE212 ] %312 = fadd float %temp44.0, 0xBFE99999A0000000 %313 = fmul float %312, 0x4014000020000000 %314 = call float @llvm.AMDIL.clamp.(float %313, float 0.000000e+00, float 1.000000e+00) %315 = fmul float 2.000000e+00, %314 %316 = fsub float -0.000000e+00, %315 %317 = fadd float 3.000000e+00, %316 %318 = fmul float %314, %317 %319 = fmul float %314, %318 %320 = fmul float %192, %319 %321 = fmul float %193, %319 %322 = fmul float %194, %319 %323 = fadd float %163, %320 %324 = fadd float %164, %321 %325 = fadd float %165, %322 %326 = bitcast float %24 to i32 %327 = fsub float -0.000000e+00, %147 %328 = fsub float -0.000000e+00, %148 %329 = fsub float -0.000000e+00, %149 %330 = bitcast float %temp8.0 to i32 %331 = icmp ne i32 %330, 0 br label %LOOP IF211: ; preds = %ELSE190 %332 = shl i32 10, 4 %333 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %332) %334 = shl i32 10, 4 %335 = add i32 %334, 4 %336 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %335) %337 = shl i32 10, 4 %338 = add i32 %337, 8 %339 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %338) %340 = shl i32 9, 4 %341 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %340) %342 = shl i32 9, 4 %343 = add i32 %342, 4 %344 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %343) %345 = shl i32 9, 4 %346 = add i32 %345, 8 %347 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %346) %348 = shl i32 8, 4 %349 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %348) %350 = shl i32 8, 4 %351 = add i32 %350, 4 %352 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %351) %353 = shl i32 8, 4 %354 = add i32 %353, 8 %355 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %354) %356 = fmul float %349, %147 %357 = fmul float %352, %147 %358 = fmul float %355, %147 %359 = fmul float %341, %148 %360 = fadd float %359, %356 %361 = fmul float %344, %148 %362 = fadd float %361, %357 %363 = fmul float %347, %148 %364 = fadd float %363, %358 %365 = fmul float %333, %149 %366 = fadd float %365, %360 %367 = fmul float %336, %149 %368 = fadd float %367, %362 %369 = fmul float %339, %149 %370 = fadd float %369, %364 %371 = shl i32 11, 4 %372 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %371) %373 = shl i32 11, 4 %374 = add i32 %373, 4 %375 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %374) %376 = shl i32 11, 4 %377 = add i32 %376, 8 %378 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %377) %379 = fadd float %366, %372 %380 = fadd float %368, %375 %381 = fadd float %370, %378 %382 = shl i32 15, 4 %383 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %382) %384 = shl i32 15, 4 %385 = add i32 %384, 4 %386 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %385) %387 = shl i32 15, 4 %388 = add i32 %387, 8 %389 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %388) %390 = fsub float -0.000000e+00, %383 %391 = fadd float %147, %390 %392 = fsub float -0.000000e+00, %386 %393 = fadd float %148, %392 %394 = fsub float -0.000000e+00, %389 %395 = fadd float %149, %394 %396 = fmul float %391, %391 %397 = fmul float %393, %393 %398 = fadd float %397, %396 %399 = fmul float %395, %395 %400 = fadd float %398, %399 %401 = call float @llvm.AMDGPU.rsq(float %400) %402 = fmul float %401, %400 %403 = fsub float -0.000000e+00, %400 %404 = call float @llvm.AMDGPU.cndlt(float %403, float %402, float 0.000000e+00) %405 = shl i32 16, 4 %406 = add i32 %405, 4 %407 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %406) %408 = fdiv float 1.000000e+00, %407 %409 = fmul float %404, %408 %410 = fadd float %409, 0xBFE99999A0000000 %411 = fmul float %410, 0x4014000020000000 %412 = call float @llvm.AMDIL.clamp.(float %411, float 0.000000e+00, float 1.000000e+00) %413 = shl i32 15, 4 %414 = add i32 %413, 12 %415 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %414) %416 = fcmp uge float %381, -1.000000e+00 %417 = select i1 %416, float %381, float -1.000000e+00 %418 = fcmp uge float %417, 1.000000e+00 %419 = select i1 %418, float 1.000000e+00, float %417 %420 = fadd float %419, 1.000000e+00 %421 = fsub float -0.000000e+00, %415 %422 = fmul float %421, %420 %423 = fmul float 0x3FE7154760000000, %422 %424 = call float @llvm.AMDIL.exp.(float %423) %425 = fmul float %379, 5.000000e-01 %426 = fadd float %425, 5.000000e-01 %427 = fmul float %380, 5.000000e-01 %428 = fadd float %427, 5.000000e-01 %429 = shl i32 16, 4 %430 = add i32 %429, 8 %431 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %430) %432 = fmul float %426, %431 %433 = fmul float %428, %431 %434 = bitcast float %432 to i32 %435 = bitcast float %433 to i32 %436 = insertelement <2 x i32> undef, i32 %434, i32 0 %437 = insertelement <2 x i32> %436, i32 %435, i32 1 %438 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %437, <32 x i8> %34, <16 x i8> %36, i32 5) %439 = extractelement <4 x float> %438, i32 0 %440 = fmul float %424, %439 %441 = call float @llvm.AMDIL.clamp.(float %440, float 0.000000e+00, float 1.000000e+00) %442 = fmul float 2.000000e+00, %412 %443 = fsub float -0.000000e+00, %442 %444 = fadd float 3.000000e+00, %443 %445 = fmul float %412, %444 %446 = fmul float %412, %445 %447 = call float @llvm.AMDGPU.lrp(float %446, float 1.000000e+00, float %441) br label %ENDIF188 ELSE212: ; preds = %ELSE190 %448 = shl i32 6, 4 %449 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %448) %450 = shl i32 6, 4 %451 = add i32 %450, 4 %452 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %451) %453 = shl i32 6, 4 %454 = add i32 %453, 8 %455 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %454) %456 = shl i32 5, 4 %457 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %456) %458 = shl i32 5, 4 %459 = add i32 %458, 4 %460 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %459) %461 = shl i32 5, 4 %462 = add i32 %461, 8 %463 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %462) %464 = shl i32 4, 4 %465 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %464) %466 = shl i32 4, 4 %467 = add i32 %466, 4 %468 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %467) %469 = shl i32 4, 4 %470 = add i32 %469, 8 %471 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %470) %472 = fmul float %465, %147 %473 = fmul float %468, %147 %474 = fmul float %471, %147 %475 = fmul float %457, %148 %476 = fadd float %475, %472 %477 = fmul float %460, %148 %478 = fadd float %477, %473 %479 = fmul float %463, %148 %480 = fadd float %479, %474 %481 = fmul float %449, %149 %482 = fadd float %481, %476 %483 = fmul float %452, %149 %484 = fadd float %483, %478 %485 = fmul float %455, %149 %486 = fadd float %485, %480 %487 = shl i32 7, 4 %488 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %487) %489 = shl i32 7, 4 %490 = add i32 %489, 4 %491 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %490) %492 = shl i32 7, 4 %493 = add i32 %492, 8 %494 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %493) %495 = fadd float %482, %488 %496 = fadd float %484, %491 %497 = fadd float %486, %494 %498 = shl i32 10, 4 %499 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %498) %500 = shl i32 10, 4 %501 = add i32 %500, 4 %502 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %501) %503 = shl i32 10, 4 %504 = add i32 %503, 8 %505 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %504) %506 = shl i32 9, 4 %507 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %506) %508 = shl i32 9, 4 %509 = add i32 %508, 4 %510 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %509) %511 = shl i32 9, 4 %512 = add i32 %511, 8 %513 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %512) %514 = shl i32 8, 4 %515 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %514) %516 = shl i32 8, 4 %517 = add i32 %516, 4 %518 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %517) %519 = shl i32 8, 4 %520 = add i32 %519, 8 %521 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %520) %522 = fmul float %515, %147 %523 = fmul float %518, %147 %524 = fmul float %521, %147 %525 = fmul float %507, %148 %526 = fadd float %525, %522 %527 = fmul float %510, %148 %528 = fadd float %527, %523 %529 = fmul float %513, %148 %530 = fadd float %529, %524 %531 = fmul float %499, %149 %532 = fadd float %531, %526 %533 = fmul float %502, %149 %534 = fadd float %533, %528 %535 = fmul float %505, %149 %536 = fadd float %535, %530 %537 = shl i32 11, 4 %538 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %537) %539 = shl i32 11, 4 %540 = add i32 %539, 4 %541 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %540) %542 = shl i32 11, 4 %543 = add i32 %542, 8 %544 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %543) %545 = fadd float %532, %538 %546 = fadd float %534, %541 %547 = fadd float %536, %544 %548 = shl i32 16, 4 %549 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %548) %550 = fmul float 0x3FE99999A0000000, %549 %551 = fsub float -0.000000e+00, %550 %552 = fadd float %217, %551 %553 = fsub float -0.000000e+00, %550 %554 = fadd float %549, %553 %555 = fdiv float 1.000000e+00, %554 %556 = fmul float %552, %555 %557 = call float @llvm.AMDIL.clamp.(float %556, float 0.000000e+00, float 1.000000e+00) %558 = shl i32 15, 4 %559 = add i32 %558, 12 %560 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %559) %561 = shl i32 16, 4 %562 = add i32 %561, 8 %563 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %562) %564 = fcmp uge float %497, -1.000000e+00 %565 = select i1 %564, float %497, float -1.000000e+00 %566 = fcmp uge float %565, 1.000000e+00 %567 = select i1 %566, float 1.000000e+00, float %565 %568 = fadd float %567, 1.000000e+00 %569 = fsub float -0.000000e+00, %560 %570 = fmul float %569, %568 %571 = fmul float 0x3FE7154760000000, %570 %572 = call float @llvm.AMDIL.exp.(float %571) %573 = fmul float %495, 5.000000e-01 %574 = fadd float %573, 5.000000e-01 %575 = fmul float %496, 5.000000e-01 %576 = fadd float %575, 5.000000e-01 %577 = fmul float %574, %563 %578 = fmul float %576, %563 %579 = bitcast float %577 to i32 %580 = bitcast float %578 to i32 %581 = insertelement <2 x i32> undef, i32 %579, i32 0 %582 = insertelement <2 x i32> %581, i32 %580, i32 1 %583 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %582, <32 x i8> %30, <16 x i8> %32, i32 5) %584 = extractelement <4 x float> %583, i32 0 %585 = fmul float %572, %584 %586 = call float @llvm.AMDIL.clamp.(float %585, float 0.000000e+00, float 1.000000e+00) %587 = fcmp uge float %547, -1.000000e+00 %588 = select i1 %587, float %547, float -1.000000e+00 %589 = fcmp uge float %588, 1.000000e+00 %590 = select i1 %589, float 1.000000e+00, float %588 %591 = fadd float %590, 1.000000e+00 %592 = fsub float -0.000000e+00, %560 %593 = fmul float %592, %591 %594 = fmul float 0x3FE7154760000000, %593 %595 = call float @llvm.AMDIL.exp.(float %594) %596 = fmul float %545, 5.000000e-01 %597 = fadd float %596, 5.000000e-01 %598 = fmul float %546, 5.000000e-01 %599 = fadd float %598, 5.000000e-01 %600 = fmul float %597, %563 %601 = fmul float %599, %563 %602 = bitcast float %600 to i32 %603 = bitcast float %601 to i32 %604 = insertelement <2 x i32> undef, i32 %602, i32 0 %605 = insertelement <2 x i32> %604, i32 %603, i32 1 %606 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %605, <32 x i8> %34, <16 x i8> %36, i32 5) %607 = extractelement <4 x float> %606, i32 0 %608 = fmul float %595, %607 %609 = call float @llvm.AMDIL.clamp.(float %608, float 0.000000e+00, float 1.000000e+00) %610 = fmul float 2.000000e+00, %557 %611 = fsub float -0.000000e+00, %610 %612 = fadd float 3.000000e+00, %611 %613 = fmul float %557, %612 %614 = fmul float %557, %613 %615 = call float @llvm.AMDGPU.lrp(float %614, float %609, float %586) br label %ENDIF188 LOOP: ; preds = %ENDIF270, %ENDIF188 %temp34.0 = phi float [ %325, %ENDIF188 ], [ %849, %ENDIF270 ] %temp33.0 = phi float [ %324, %ENDIF188 ], [ %848, %ENDIF270 ] %temp32.0 = phi float [ %323, %ENDIF188 ], [ %847, %ENDIF270 ] %temp24.0 = phi float [ 0.000000e+00, %ENDIF188 ], [ %852, %ENDIF270 ] %616 = bitcast float %temp24.0 to i32 %617 = icmp sge i32 %616, %326 %618 = sext i1 %617 to i32 %619 = bitcast i32 %618 to float %620 = bitcast float %619 to i32 %621 = icmp ne i32 %620, 0 br i1 %621, label %ENDLOOP, label %ENDIF270 ENDLOOP: ; preds = %ENDIF270, %LOOP %temp34.1 = phi float [ %temp34.0, %LOOP ], [ %849, %ENDIF270 ] %temp33.1 = phi float [ %temp33.0, %LOOP ], [ %848, %ENDIF270 ] %temp32.1 = phi float [ %temp32.0, %LOOP ], [ %847, %ENDIF270 ] %622 = fsub float -0.000000e+00, %95 %623 = fsub float -0.000000e+00, %97 %624 = fsub float -0.000000e+00, %99 %625 = shl i32 14, 4 %626 = call float @llvm.SI.load.const(<16 x i8> %26, i32 %625) %627 = shl i32 14, 4 %628 = add i32 %627, 4 %629 = call float @llvm.SI.load.const(<16 x i8> %26, i32 %628) %630 = shl i32 14, 4 %631 = add i32 %630, 8 %632 = call float @llvm.SI.load.const(<16 x i8> %26, i32 %631) %633 = shl i32 13, 4 %634 = call float @llvm.SI.load.const(<16 x i8> %26, i32 %633) %635 = shl i32 13, 4 %636 = add i32 %635, 4 %637 = call float @llvm.SI.load.const(<16 x i8> %26, i32 %636) %638 = shl i32 13, 4 %639 = add i32 %638, 8 %640 = call float @llvm.SI.load.const(<16 x i8> %26, i32 %639) %641 = shl i32 12, 4 %642 = call float @llvm.SI.load.const(<16 x i8> %26, i32 %641) %643 = shl i32 12, 4 %644 = add i32 %643, 4 %645 = call float @llvm.SI.load.const(<16 x i8> %26, i32 %644) %646 = shl i32 12, 4 %647 = add i32 %646, 8 %648 = call float @llvm.SI.load.const(<16 x i8> %26, i32 %647) %649 = fmul float %642, %51 %650 = fmul float %645, %51 %651 = fmul float %648, %51 %652 = fmul float %634, %52 %653 = fadd float %652, %649 %654 = fmul float %637, %52 %655 = fadd float %654, %650 %656 = fmul float %640, %52 %657 = fadd float %656, %651 %658 = fmul float %626, %53 %659 = fadd float %658, %653 %660 = fmul float %629, %53 %661 = fadd float %660, %655 %662 = fmul float %632, %53 %663 = fadd float %662, %657 %664 = shl i32 15, 4 %665 = call float @llvm.SI.load.const(<16 x i8> %26, i32 %664) %666 = shl i32 15, 4 %667 = add i32 %666, 4 %668 = call float @llvm.SI.load.const(<16 x i8> %26, i32 %667) %669 = shl i32 15, 4 %670 = add i32 %669, 8 %671 = call float @llvm.SI.load.const(<16 x i8> %26, i32 %670) %672 = fadd float %659, %665 %673 = fadd float %661, %668 %674 = fadd float %663, %671 %675 = fadd float %623, 0x3FF0CCCCC0000000 %676 = call float @llvm.AMDIL.clamp.(float %675, float 0.000000e+00, float 1.000000e+00) %677 = shl i32 14, 4 %678 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %677) %679 = shl i32 14, 4 %680 = add i32 %679, 4 %681 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %680) %682 = shl i32 14, 4 %683 = add i32 %682, 8 %684 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %683) %685 = fmul float %676, %678 %686 = fmul float %676, %681 %687 = fmul float %676, %684 %688 = fmul float %85, %685 %689 = fmul float %86, %686 %690 = fmul float %87, %687 %691 = shl i32 12, 4 %692 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %691) %693 = shl i32 12, 4 %694 = add i32 %693, 4 %695 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %694) %696 = shl i32 12, 4 %697 = add i32 %696, 8 %698 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %697) %699 = fmul float %622, %692 %700 = fmul float %623, %695 %701 = fadd float %700, %699 %702 = fmul float %624, %698 %703 = fadd float %701, %702 %704 = fcmp uge float 0.000000e+00, %703 %705 = select i1 %704, float 0.000000e+00, float %703 %706 = shl i32 13, 4 %707 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %706) %708 = shl i32 13, 4 %709 = add i32 %708, 4 %710 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %709) %711 = shl i32 13, 4 %712 = add i32 %711, 8 %713 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %712) %714 = fmul float %705, %707 %715 = fmul float %705, %710 %716 = fmul float %705, %713 %717 = fmul float %714, %85 %718 = fmul float %715, %86 %719 = fmul float %716, %87 %720 = shl i32 15, 4 %721 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %720) %722 = shl i32 15, 4 %723 = add i32 %722, 4 %724 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %723) %725 = shl i32 15, 4 %726 = add i32 %725, 8 %727 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %726) %728 = fsub float -0.000000e+00, %721 %729 = fadd float %672, %728 %730 = fsub float -0.000000e+00, %724 %731 = fadd float %673, %730 %732 = fsub float -0.000000e+00, %727 %733 = fadd float %674, %732 %734 = fmul float %729, %729 %735 = fmul float %731, %731 %736 = fadd float %735, %734 %737 = fmul float %733, %733 %738 = fadd float %736, %737 %739 = call float @llvm.AMDGPU.rsq(float %738) %740 = fmul float %739, %738 %741 = fsub float -0.000000e+00, %738 %742 = call float @llvm.AMDGPU.cndlt(float %741, float %740, float 0.000000e+00) %743 = shl i32 16, 4 %744 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %743) %745 = fmul float 0x3FE99999A0000000, %744 %746 = fcmp olt float %742, %745 %747 = sext i1 %746 to i32 %748 = bitcast i32 %747 to float %749 = bitcast float %748 to i32 %750 = icmp ne i32 %749, 0 br i1 %750, label %IF313, label %ELSE314 ENDIF270: ; preds = %LOOP %751 = bitcast float %temp24.0 to i32 %752 = mul i32 %751, 7 %753 = bitcast i32 %752 to float %754 = bitcast float %753 to i32 %755 = shl i32 %754, 4 %756 = add i32 %755, 64 %757 = call float @llvm.SI.load.const(<16 x i8> %23, i32 %756) %758 = bitcast float %753 to i32 %759 = add i32 %758, 1 %760 = bitcast i32 %759 to float %761 = bitcast float %760 to i32 %762 = shl i32 %761, 4 %763 = add i32 %762, 64 %764 = call float @llvm.SI.load.const(<16 x i8> %23, i32 %763) %765 = bitcast float %753 to i32 %766 = add i32 %765, 2 %767 = bitcast i32 %766 to float %768 = bitcast float %767 to i32 %769 = shl i32 %768, 4 %770 = add i32 %769, 64 %771 = call float @llvm.SI.load.const(<16 x i8> %23, i32 %770) %772 = bitcast float %753 to i32 %773 = add i32 %772, 3 %774 = bitcast i32 %773 to float %775 = bitcast float %774 to i32 %776 = shl i32 %775, 4 %777 = add i32 %776, 64 %778 = call float @llvm.SI.load.const(<16 x i8> %23, i32 %777) %779 = bitcast float %753 to i32 %780 = add i32 %779, 4 %781 = bitcast i32 %780 to float %782 = bitcast float %781 to i32 %783 = shl i32 %782, 4 %784 = add i32 %783, 64 %785 = call float @llvm.SI.load.const(<16 x i8> %23, i32 %784) %786 = bitcast float %753 to i32 %787 = add i32 %786, 5 %788 = bitcast i32 %787 to float %789 = bitcast float %788 to i32 %790 = shl i32 %789, 4 %791 = add i32 %790, 64 %792 = call float @llvm.SI.load.const(<16 x i8> %23, i32 %791) %793 = bitcast float %753 to i32 %794 = add i32 %793, 6 %795 = bitcast i32 %794 to float %796 = bitcast float %795 to i32 %797 = shl i32 %796, 4 %798 = add i32 %797, 64 %799 = call float @llvm.SI.load.const(<16 x i8> %23, i32 %798) %800 = fadd float %757, %327 %801 = fadd float %764, %328 %802 = fadd float %771, %329 %803 = fmul float %800, %800 %804 = fmul float %801, %801 %805 = fadd float %804, %803 %806 = fmul float %802, %802 %807 = fadd float %805, %806 %808 = call float @llvm.AMDGPU.rsq(float %807) %809 = fmul float %808, %807 %810 = fsub float -0.000000e+00, %807 %811 = call float @llvm.AMDGPU.cndlt(float %810, float %809, float 0.000000e+00) %812 = fdiv float 1.000000e+00, %811 %813 = fmul float %800, %812 %814 = fmul float %801, %812 %815 = fmul float %802, %812 %816 = fmul float %95, %813 %817 = fmul float %97, %814 %818 = fadd float %817, %816 %819 = fmul float %99, %815 %820 = fadd float %818, %819 %821 = fcmp uge float 0.000000e+00, %820 %822 = select i1 %821, float 0.000000e+00, float %820 %823 = fmul float %822, %778 %824 = fmul float %822, %785 %825 = fmul float %822, %792 %826 = fmul float %823, %85 %827 = fmul float %824, %86 %828 = fmul float %825, %87 %829 = fmul float %799, 5.000000e-01 %830 = fsub float -0.000000e+00, %829 %831 = fadd float %811, %830 %832 = fsub float -0.000000e+00, %829 %833 = fadd float %799, %832 %834 = fdiv float 1.000000e+00, %833 %835 = fmul float %831, %834 %836 = call float @llvm.AMDIL.clamp.(float %835, float 0.000000e+00, float 1.000000e+00) %837 = fmul float 2.000000e+00, %836 %838 = fsub float -0.000000e+00, %837 %839 = fadd float 3.000000e+00, %838 %840 = fmul float %836, %839 %841 = fmul float %836, %840 %842 = fsub float -0.000000e+00, %841 %843 = fadd float 1.000000e+00, %842 %844 = fmul float %826, %843 %845 = fmul float %827, %843 %846 = fmul float %828, %843 %847 = fadd float %temp32.0, %844 %848 = fadd float %temp33.0, %845 %849 = fadd float %temp34.0, %846 %850 = bitcast float %temp24.0 to i32 %851 = add i32 %850, 1 %852 = bitcast i32 %851 to float br i1 %331, label %ENDLOOP, label %LOOP IF313: ; preds = %ENDLOOP %853 = shl i32 6, 4 %854 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %853) %855 = shl i32 6, 4 %856 = add i32 %855, 4 %857 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %856) %858 = shl i32 6, 4 %859 = add i32 %858, 8 %860 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %859) %861 = shl i32 5, 4 %862 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %861) %863 = shl i32 5, 4 %864 = add i32 %863, 4 %865 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %864) %866 = shl i32 5, 4 %867 = add i32 %866, 8 %868 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %867) %869 = shl i32 4, 4 %870 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %869) %871 = shl i32 4, 4 %872 = add i32 %871, 4 %873 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %872) %874 = shl i32 4, 4 %875 = add i32 %874, 8 %876 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %875) %877 = fmul float %870, %672 %878 = fmul float %873, %672 %879 = fmul float %876, %672 %880 = fmul float %862, %673 %881 = fadd float %880, %877 %882 = fmul float %865, %673 %883 = fadd float %882, %878 %884 = fmul float %868, %673 %885 = fadd float %884, %879 %886 = fmul float %854, %674 %887 = fadd float %886, %881 %888 = fmul float %857, %674 %889 = fadd float %888, %883 %890 = fmul float %860, %674 %891 = fadd float %890, %885 %892 = shl i32 7, 4 %893 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %892) %894 = shl i32 7, 4 %895 = add i32 %894, 4 %896 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %895) %897 = shl i32 7, 4 %898 = add i32 %897, 8 %899 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %898) %900 = fadd float %887, %893 %901 = fadd float %889, %896 %902 = fadd float %891, %899 %903 = shl i32 15, 4 %904 = add i32 %903, 12 %905 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %904) %906 = fcmp uge float %902, -1.000000e+00 %907 = select i1 %906, float %902, float -1.000000e+00 %908 = fcmp uge float %907, 1.000000e+00 %909 = select i1 %908, float 1.000000e+00, float %907 %910 = fadd float %909, 1.000000e+00 %911 = fsub float -0.000000e+00, %905 %912 = fmul float %911, %910 %913 = fmul float 0x3FE7154760000000, %912 %914 = call float @llvm.AMDIL.exp.(float %913) %915 = fmul float %900, 5.000000e-01 %916 = fadd float %915, 5.000000e-01 %917 = fmul float %901, 5.000000e-01 %918 = fadd float %917, 5.000000e-01 %919 = shl i32 16, 4 %920 = add i32 %919, 8 %921 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %920) %922 = fmul float %916, %921 %923 = fmul float %918, %921 %924 = bitcast float %922 to i32 %925 = bitcast float %923 to i32 %926 = insertelement <2 x i32> undef, i32 %924, i32 0 %927 = insertelement <2 x i32> %926, i32 %925, i32 1 %928 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %927, <32 x i8> %30, <16 x i8> %32, i32 5) %929 = extractelement <4 x float> %928, i32 0 %930 = fmul float %914, %929 %931 = call float @llvm.AMDIL.clamp.(float %930, float 0.000000e+00, float 1.000000e+00) br label %ENDIF312 ELSE314: ; preds = %ENDLOOP %932 = shl i32 16, 4 %933 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %932) %934 = fcmp olt float %933, %742 %935 = sext i1 %934 to i32 %936 = bitcast i32 %935 to float %937 = bitcast float %936 to i32 %938 = icmp ne i32 %937, 0 br i1 %938, label %IF335, label %ELSE336 ENDIF312: ; preds = %IF335, %ELSE336, %IF313 %temp40.0 = phi float [ %931, %IF313 ], [ %1074, %IF335 ], [ %1242, %ELSE336 ] %939 = fadd float %temp40.0, 0xBFE99999A0000000 %940 = fmul float %939, 0x4014000020000000 %941 = call float @llvm.AMDIL.clamp.(float %940, float 0.000000e+00, float 1.000000e+00) %942 = fmul float 2.000000e+00, %941 %943 = fsub float -0.000000e+00, %942 %944 = fadd float 3.000000e+00, %943 %945 = fmul float %941, %944 %946 = fmul float %941, %945 %947 = fmul float %717, %946 %948 = fmul float %718, %946 %949 = fmul float %719, %946 %950 = fadd float %688, %947 %951 = fadd float %689, %948 %952 = fadd float %690, %949 %953 = bitcast float %24 to i32 %954 = fsub float -0.000000e+00, %672 %955 = fsub float -0.000000e+00, %673 %956 = fsub float -0.000000e+00, %674 %957 = bitcast float %temp8.0 to i32 %958 = icmp ne i32 %957, 0 br label %LOOP395 IF335: ; preds = %ELSE314 %959 = shl i32 10, 4 %960 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %959) %961 = shl i32 10, 4 %962 = add i32 %961, 4 %963 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %962) %964 = shl i32 10, 4 %965 = add i32 %964, 8 %966 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %965) %967 = shl i32 9, 4 %968 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %967) %969 = shl i32 9, 4 %970 = add i32 %969, 4 %971 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %970) %972 = shl i32 9, 4 %973 = add i32 %972, 8 %974 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %973) %975 = shl i32 8, 4 %976 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %975) %977 = shl i32 8, 4 %978 = add i32 %977, 4 %979 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %978) %980 = shl i32 8, 4 %981 = add i32 %980, 8 %982 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %981) %983 = fmul float %976, %672 %984 = fmul float %979, %672 %985 = fmul float %982, %672 %986 = fmul float %968, %673 %987 = fadd float %986, %983 %988 = fmul float %971, %673 %989 = fadd float %988, %984 %990 = fmul float %974, %673 %991 = fadd float %990, %985 %992 = fmul float %960, %674 %993 = fadd float %992, %987 %994 = fmul float %963, %674 %995 = fadd float %994, %989 %996 = fmul float %966, %674 %997 = fadd float %996, %991 %998 = shl i32 11, 4 %999 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %998) %1000 = shl i32 11, 4 %1001 = add i32 %1000, 4 %1002 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %1001) %1003 = shl i32 11, 4 %1004 = add i32 %1003, 8 %1005 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %1004) %1006 = fadd float %993, %999 %1007 = fadd float %995, %1002 %1008 = fadd float %997, %1005 %1009 = shl i32 15, 4 %1010 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %1009) %1011 = shl i32 15, 4 %1012 = add i32 %1011, 4 %1013 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %1012) %1014 = shl i32 15, 4 %1015 = add i32 %1014, 8 %1016 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %1015) %1017 = fsub float -0.000000e+00, %1010 %1018 = fadd float %672, %1017 %1019 = fsub float -0.000000e+00, %1013 %1020 = fadd float %673, %1019 %1021 = fsub float -0.000000e+00, %1016 %1022 = fadd float %674, %1021 %1023 = fmul float %1018, %1018 %1024 = fmul float %1020, %1020 %1025 = fadd float %1024, %1023 %1026 = fmul float %1022, %1022 %1027 = fadd float %1025, %1026 %1028 = call float @llvm.AMDGPU.rsq(float %1027) %1029 = fmul float %1028, %1027 %1030 = fsub float -0.000000e+00, %1027 %1031 = call float @llvm.AMDGPU.cndlt(float %1030, float %1029, float 0.000000e+00) %1032 = shl i32 16, 4 %1033 = add i32 %1032, 4 %1034 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %1033) %1035 = fdiv float 1.000000e+00, %1034 %1036 = fmul float %1031, %1035 %1037 = fadd float %1036, 0xBFE99999A0000000 %1038 = fmul float %1037, 0x4014000020000000 %1039 = call float @llvm.AMDIL.clamp.(float %1038, float 0.000000e+00, float 1.000000e+00) %1040 = shl i32 15, 4 %1041 = add i32 %1040, 12 %1042 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %1041) %1043 = fcmp uge float %1008, -1.000000e+00 %1044 = select i1 %1043, float %1008, float -1.000000e+00 %1045 = fcmp uge float %1044, 1.000000e+00 %1046 = select i1 %1045, float 1.000000e+00, float %1044 %1047 = fadd float %1046, 1.000000e+00 %1048 = fsub float -0.000000e+00, %1042 %1049 = fmul float %1048, %1047 %1050 = fmul float 0x3FE7154760000000, %1049 %1051 = call float @llvm.AMDIL.exp.(float %1050) %1052 = fmul float %1006, 5.000000e-01 %1053 = fadd float %1052, 5.000000e-01 %1054 = fmul float %1007, 5.000000e-01 %1055 = fadd float %1054, 5.000000e-01 %1056 = shl i32 16, 4 %1057 = add i32 %1056, 8 %1058 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %1057) %1059 = fmul float %1053, %1058 %1060 = fmul float %1055, %1058 %1061 = bitcast float %1059 to i32 %1062 = bitcast float %1060 to i32 %1063 = insertelement <2 x i32> undef, i32 %1061, i32 0 %1064 = insertelement <2 x i32> %1063, i32 %1062, i32 1 %1065 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1064, <32 x i8> %34, <16 x i8> %36, i32 5) %1066 = extractelement <4 x float> %1065, i32 0 %1067 = fmul float %1051, %1066 %1068 = call float @llvm.AMDIL.clamp.(float %1067, float 0.000000e+00, float 1.000000e+00) %1069 = fmul float 2.000000e+00, %1039 %1070 = fsub float -0.000000e+00, %1069 %1071 = fadd float 3.000000e+00, %1070 %1072 = fmul float %1039, %1071 %1073 = fmul float %1039, %1072 %1074 = call float @llvm.AMDGPU.lrp(float %1073, float 1.000000e+00, float %1068) br label %ENDIF312 ELSE336: ; preds = %ELSE314 %1075 = shl i32 6, 4 %1076 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %1075) %1077 = shl i32 6, 4 %1078 = add i32 %1077, 4 %1079 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %1078) %1080 = shl i32 6, 4 %1081 = add i32 %1080, 8 %1082 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %1081) %1083 = shl i32 5, 4 %1084 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %1083) %1085 = shl i32 5, 4 %1086 = add i32 %1085, 4 %1087 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %1086) %1088 = shl i32 5, 4 %1089 = add i32 %1088, 8 %1090 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %1089) %1091 = shl i32 4, 4 %1092 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %1091) %1093 = shl i32 4, 4 %1094 = add i32 %1093, 4 %1095 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %1094) %1096 = shl i32 4, 4 %1097 = add i32 %1096, 8 %1098 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %1097) %1099 = fmul float %1092, %672 %1100 = fmul float %1095, %672 %1101 = fmul float %1098, %672 %1102 = fmul float %1084, %673 %1103 = fadd float %1102, %1099 %1104 = fmul float %1087, %673 %1105 = fadd float %1104, %1100 %1106 = fmul float %1090, %673 %1107 = fadd float %1106, %1101 %1108 = fmul float %1076, %674 %1109 = fadd float %1108, %1103 %1110 = fmul float %1079, %674 %1111 = fadd float %1110, %1105 %1112 = fmul float %1082, %674 %1113 = fadd float %1112, %1107 %1114 = shl i32 7, 4 %1115 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %1114) %1116 = shl i32 7, 4 %1117 = add i32 %1116, 4 %1118 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %1117) %1119 = shl i32 7, 4 %1120 = add i32 %1119, 8 %1121 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %1120) %1122 = fadd float %1109, %1115 %1123 = fadd float %1111, %1118 %1124 = fadd float %1113, %1121 %1125 = shl i32 10, 4 %1126 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %1125) %1127 = shl i32 10, 4 %1128 = add i32 %1127, 4 %1129 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %1128) %1130 = shl i32 10, 4 %1131 = add i32 %1130, 8 %1132 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %1131) %1133 = shl i32 9, 4 %1134 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %1133) %1135 = shl i32 9, 4 %1136 = add i32 %1135, 4 %1137 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %1136) %1138 = shl i32 9, 4 %1139 = add i32 %1138, 8 %1140 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %1139) %1141 = shl i32 8, 4 %1142 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %1141) %1143 = shl i32 8, 4 %1144 = add i32 %1143, 4 %1145 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %1144) %1146 = shl i32 8, 4 %1147 = add i32 %1146, 8 %1148 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %1147) %1149 = fmul float %1142, %672 %1150 = fmul float %1145, %672 %1151 = fmul float %1148, %672 %1152 = fmul float %1134, %673 %1153 = fadd float %1152, %1149 %1154 = fmul float %1137, %673 %1155 = fadd float %1154, %1150 %1156 = fmul float %1140, %673 %1157 = fadd float %1156, %1151 %1158 = fmul float %1126, %674 %1159 = fadd float %1158, %1153 %1160 = fmul float %1129, %674 %1161 = fadd float %1160, %1155 %1162 = fmul float %1132, %674 %1163 = fadd float %1162, %1157 %1164 = shl i32 11, 4 %1165 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %1164) %1166 = shl i32 11, 4 %1167 = add i32 %1166, 4 %1168 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %1167) %1169 = shl i32 11, 4 %1170 = add i32 %1169, 8 %1171 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %1170) %1172 = fadd float %1159, %1165 %1173 = fadd float %1161, %1168 %1174 = fadd float %1163, %1171 %1175 = shl i32 16, 4 %1176 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %1175) %1177 = fmul float 0x3FE99999A0000000, %1176 %1178 = fsub float -0.000000e+00, %1177 %1179 = fadd float %742, %1178 %1180 = fsub float -0.000000e+00, %1177 %1181 = fadd float %1176, %1180 %1182 = fdiv float 1.000000e+00, %1181 %1183 = fmul float %1179, %1182 %1184 = call float @llvm.AMDIL.clamp.(float %1183, float 0.000000e+00, float 1.000000e+00) %1185 = shl i32 15, 4 %1186 = add i32 %1185, 12 %1187 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %1186) %1188 = shl i32 16, 4 %1189 = add i32 %1188, 8 %1190 = call float @llvm.SI.load.const(<16 x i8> %28, i32 %1189) %1191 = fcmp uge float %1124, -1.000000e+00 %1192 = select i1 %1191, float %1124, float -1.000000e+00 %1193 = fcmp uge float %1192, 1.000000e+00 %1194 = select i1 %1193, float 1.000000e+00, float %1192 %1195 = fadd float %1194, 1.000000e+00 %1196 = fsub float -0.000000e+00, %1187 %1197 = fmul float %1196, %1195 %1198 = fmul float 0x3FE7154760000000, %1197 %1199 = call float @llvm.AMDIL.exp.(float %1198) %1200 = fmul float %1122, 5.000000e-01 %1201 = fadd float %1200, 5.000000e-01 %1202 = fmul float %1123, 5.000000e-01 %1203 = fadd float %1202, 5.000000e-01 %1204 = fmul float %1201, %1190 %1205 = fmul float %1203, %1190 %1206 = bitcast float %1204 to i32 %1207 = bitcast float %1205 to i32 %1208 = insertelement <2 x i32> undef, i32 %1206, i32 0 %1209 = insertelement <2 x i32> %1208, i32 %1207, i32 1 %1210 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1209, <32 x i8> %30, <16 x i8> %32, i32 5) %1211 = extractelement <4 x float> %1210, i32 0 %1212 = fmul float %1199, %1211 %1213 = call float @llvm.AMDIL.clamp.(float %1212, float 0.000000e+00, float 1.000000e+00) %1214 = fcmp uge float %1174, -1.000000e+00 %1215 = select i1 %1214, float %1174, float -1.000000e+00 %1216 = fcmp uge float %1215, 1.000000e+00 %1217 = select i1 %1216, float 1.000000e+00, float %1215 %1218 = fadd float %1217, 1.000000e+00 %1219 = fsub float -0.000000e+00, %1187 %1220 = fmul float %1219, %1218 %1221 = fmul float 0x3FE7154760000000, %1220 %1222 = call float @llvm.AMDIL.exp.(float %1221) %1223 = fmul float %1172, 5.000000e-01 %1224 = fadd float %1223, 5.000000e-01 %1225 = fmul float %1173, 5.000000e-01 %1226 = fadd float %1225, 5.000000e-01 %1227 = fmul float %1224, %1190 %1228 = fmul float %1226, %1190 %1229 = bitcast float %1227 to i32 %1230 = bitcast float %1228 to i32 %1231 = insertelement <2 x i32> undef, i32 %1229, i32 0 %1232 = insertelement <2 x i32> %1231, i32 %1230, i32 1 %1233 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %1232, <32 x i8> %34, <16 x i8> %36, i32 5) %1234 = extractelement <4 x float> %1233, i32 0 %1235 = fmul float %1222, %1234 %1236 = call float @llvm.AMDIL.clamp.(float %1235, float 0.000000e+00, float 1.000000e+00) %1237 = fmul float 2.000000e+00, %1184 %1238 = fsub float -0.000000e+00, %1237 %1239 = fadd float 3.000000e+00, %1238 %1240 = fmul float %1184, %1239 %1241 = fmul float %1184, %1240 %1242 = call float @llvm.AMDGPU.lrp(float %1241, float %1236, float %1213) br label %ENDIF312 LOOP395: ; preds = %ENDIF396, %ENDIF312 %temp30.0 = phi float [ %952, %ENDIF312 ], [ %1354, %ENDIF396 ] %temp29.0 = phi float [ %951, %ENDIF312 ], [ %1353, %ENDIF396 ] %temp28.0 = phi float [ %950, %ENDIF312 ], [ %1352, %ENDIF396 ] %temp16.0 = phi float [ 0.000000e+00, %ENDIF312 ], [ %1357, %ENDIF396 ] %1243 = bitcast float %temp16.0 to i32 %1244 = icmp sge i32 %1243, %953 %1245 = sext i1 %1244 to i32 %1246 = bitcast i32 %1245 to float %1247 = bitcast float %1246 to i32 %1248 = icmp ne i32 %1247, 0 br i1 %1248, label %ENDLOOP394, label %ENDIF396 ENDLOOP394: ; preds = %ENDIF396, %LOOP395 %temp30.1 = phi float [ %temp30.0, %LOOP395 ], [ %1354, %ENDIF396 ] %temp29.1 = phi float [ %temp29.0, %LOOP395 ], [ %1353, %ENDIF396 ] %temp28.1 = phi float [ %temp28.0, %LOOP395 ], [ %1352, %ENDIF396 ] %1249 = fadd float %temp32.1, %temp28.1 %1250 = fadd float %temp33.1, %temp29.1 %1251 = fadd float %temp34.1, %temp30.1 %1252 = call i32 @llvm.SI.packf16(float %1249, float %1250) %1253 = bitcast i32 %1252 to float %1254 = call i32 @llvm.SI.packf16(float %1251, float 0.000000e+00) %1255 = bitcast i32 %1254 to float call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %1253, float %1255, float %1253, float %1255) ret void ENDIF396: ; preds = %LOOP395 %1256 = bitcast float %temp16.0 to i32 %1257 = mul i32 %1256, 7 %1258 = bitcast i32 %1257 to float %1259 = bitcast float %1258 to i32 %1260 = shl i32 %1259, 4 %1261 = add i32 %1260, 64 %1262 = call float @llvm.SI.load.const(<16 x i8> %23, i32 %1261) %1263 = bitcast float %1258 to i32 %1264 = add i32 %1263, 1 %1265 = bitcast i32 %1264 to float %1266 = bitcast float %1265 to i32 %1267 = shl i32 %1266, 4 %1268 = add i32 %1267, 64 %1269 = call float @llvm.SI.load.const(<16 x i8> %23, i32 %1268) %1270 = bitcast float %1258 to i32 %1271 = add i32 %1270, 2 %1272 = bitcast i32 %1271 to float %1273 = bitcast float %1272 to i32 %1274 = shl i32 %1273, 4 %1275 = add i32 %1274, 64 %1276 = call float @llvm.SI.load.const(<16 x i8> %23, i32 %1275) %1277 = bitcast float %1258 to i32 %1278 = add i32 %1277, 3 %1279 = bitcast i32 %1278 to float %1280 = bitcast float %1279 to i32 %1281 = shl i32 %1280, 4 %1282 = add i32 %1281, 64 %1283 = call float @llvm.SI.load.const(<16 x i8> %23, i32 %1282) %1284 = bitcast float %1258 to i32 %1285 = add i32 %1284, 4 %1286 = bitcast i32 %1285 to float %1287 = bitcast float %1286 to i32 %1288 = shl i32 %1287, 4 %1289 = add i32 %1288, 64 %1290 = call float @llvm.SI.load.const(<16 x i8> %23, i32 %1289) %1291 = bitcast float %1258 to i32 %1292 = add i32 %1291, 5 %1293 = bitcast i32 %1292 to float %1294 = bitcast float %1293 to i32 %1295 = shl i32 %1294, 4 %1296 = add i32 %1295, 64 %1297 = call float @llvm.SI.load.const(<16 x i8> %23, i32 %1296) %1298 = bitcast float %1258 to i32 %1299 = add i32 %1298, 6 %1300 = bitcast i32 %1299 to float %1301 = bitcast float %1300 to i32 %1302 = shl i32 %1301, 4 %1303 = add i32 %1302, 64 %1304 = call float @llvm.SI.load.const(<16 x i8> %23, i32 %1303) %1305 = fadd float %1262, %954 %1306 = fadd float %1269, %955 %1307 = fadd float %1276, %956 %1308 = fmul float %1305, %1305 %1309 = fmul float %1306, %1306 %1310 = fadd float %1309, %1308 %1311 = fmul float %1307, %1307 %1312 = fadd float %1310, %1311 %1313 = call float @llvm.AMDGPU.rsq(float %1312) %1314 = fmul float %1313, %1312 %1315 = fsub float -0.000000e+00, %1312 %1316 = call float @llvm.AMDGPU.cndlt(float %1315, float %1314, float 0.000000e+00) %1317 = fdiv float 1.000000e+00, %1316 %1318 = fmul float %1305, %1317 %1319 = fmul float %1306, %1317 %1320 = fmul float %1307, %1317 %1321 = fmul float %622, %1318 %1322 = fmul float %623, %1319 %1323 = fadd float %1322, %1321 %1324 = fmul float %624, %1320 %1325 = fadd float %1323, %1324 %1326 = fcmp uge float 0.000000e+00, %1325 %1327 = select i1 %1326, float 0.000000e+00, float %1325 %1328 = fmul float %1327, %1283 %1329 = fmul float %1327, %1290 %1330 = fmul float %1327, %1297 %1331 = fmul float %1328, %85 %1332 = fmul float %1329, %86 %1333 = fmul float %1330, %87 %1334 = fmul float %1304, 5.000000e-01 %1335 = fsub float -0.000000e+00, %1334 %1336 = fadd float %1316, %1335 %1337 = fsub float -0.000000e+00, %1334 %1338 = fadd float %1304, %1337 %1339 = fdiv float 1.000000e+00, %1338 %1340 = fmul float %1336, %1339 %1341 = call float @llvm.AMDIL.clamp.(float %1340, float 0.000000e+00, float 1.000000e+00) %1342 = fmul float 2.000000e+00, %1341 %1343 = fsub float -0.000000e+00, %1342 %1344 = fadd float 3.000000e+00, %1343 %1345 = fmul float %1341, %1344 %1346 = fmul float %1341, %1345 %1347 = fsub float -0.000000e+00, %1346 %1348 = fadd float 1.000000e+00, %1347 %1349 = fmul float %1331, %1348 %1350 = fmul float %1332, %1348 %1351 = fmul float %1333, %1348 %1352 = fadd float %temp28.0, %1349 %1353 = fadd float %temp29.0, %1350 %1354 = fadd float %temp30.0, %1351 %1355 = bitcast float %temp16.0 to i32 %1356 = add i32 %1355, 1 %1357 = bitcast i32 %1356 to float br i1 %958, label %ENDLOOP394, label %LOOP395 } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: readnone declare float @llvm.AMDIL.clamp.(float, float, float) #2 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1 declare void @llvm.AMDGPU.kilp() ; Function Attrs: readnone declare float @llvm.AMDGPU.lrp(float, float, float) #2 ; Function Attrs: readnone declare float @llvm.AMDGPU.rsq(float) #2 ; Function Attrs: readnone declare float @llvm.AMDGPU.cndlt(float, float, float) #2 ; Function Attrs: readnone declare float @llvm.AMDIL.exp.(float) #2 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="0" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_WQM_B64 exec, exec ; BEFE0A7E S_MOV_B32 m0, s9 ; BEFC0309 V_INTERP_P1_F32 v3, v0, 2, 2, [m0] ; C80C0A00 V_INTERP_P2_F32 v3, [v3], v1, 2, 2, [m0] ; C80D0A01 V_MUL_F32_e32 v4, -1.000000e-02, v3 ; 100806FF BC23D70A V_CMP_U_F32_e64 s[6:7], v4, v4, 0, 0, 0, 0 ; D0100006 02020904 V_CMP_GE_F32_e64 s[10:11], v4, 0.000000e+00, 0, 0, 0, 0 ; D00C000A 02010104 S_OR_B64 s[6:7], s[10:11], s[6:7] ; 8886060A V_CNDMASK_B32_e64 v4, 0.000000e+00, v4, s[6:7], 0, 0, 0, 0 ; D2000004 001A0880 V_MOV_B32_e32 v5, 9.000000e-01 ; 7E0A02FF 3F666666 V_CMP_GE_F32_e64 s[6:7], v4, v5, 0, 0, 0, 0 ; D00C0006 02020B04 V_CMP_U_F32_e64 s[10:11], v4, v4, 0, 0, 0, 0 ; D010000A 02020904 S_OR_B64 s[6:7], s[6:7], s[10:11] ; 88860A06 V_CNDMASK_B32_e64 v4, v4, v5, s[6:7], 0, 0, 0, 0 ; D2000004 001A0B04 V_SUB_F32_e32 v4, 9.010000e-01, v4 ; 080808FF 3F66A7F0 V_INTERP_P1_F32 v6, v0, 1, 0, [m0] ; C8180100 V_INTERP_P2_F32 v6, [v6], v1, 1, 0, [m0] ; C8190101 V_INTERP_P1_F32 v5, v0, 0, 0, [m0] ; C8140000 V_INTERP_P2_F32 v5, [v5], v1, 0, 0, [m0] ; C8150001 S_LOAD_DWORDX4 s[12:15], s[2:3], 8 ; C0860308 S_LOAD_DWORDX8 s[16:23], s[4:5], 16 ; C0C80510 S_WAITCNT lgkmcnt(0) ; BF8C007F IMAGE_SAMPLE v[13:16], 15, 0, 0, 0, 0, 0, 0, 0, v[5:6], s[16:23], s[12:15] ; F0800F00 00640D05 S_WAITCNT vmcnt(0) ; BF8C0770 V_CMP_LT_F32_e64 s[6:7], v16, v4, 0, 0, 0, 0 ; D0020006 02020910 V_INTERP_P1_F32 v10, v0, 1, 2, [m0] ; C8280900 V_INTERP_P2_F32 v10, [v10], v1, 1, 2, [m0] ; C8290901 V_INTERP_P1_F32 v11, v0, 0, 2, [m0] ; C82C0800 V_INTERP_P2_F32 v11, [v11], v1, 0, 2, [m0] ; C82D0801 V_INTERP_P1_F32 v4, v0, 3, 1, [m0] ; C8100700 V_INTERP_P2_F32 v4, [v4], v1, 3, 1, [m0] ; C8110701 V_INTERP_P1_F32 v6, v0, 2, 1, [m0] ; C8180600 V_INTERP_P2_F32 v6, [v6], v1, 2, 1, [m0] ; C8190601 V_INTERP_P1_F32 v8, v0, 1, 1, [m0] ; C8200500 V_INTERP_P2_F32 v8, [v8], v1, 1, 1, [m0] ; C8210501 V_INTERP_P1_F32 v7, v0, 0, 1, [m0] ; C81C0400 V_INTERP_P2_F32 v7, [v7], v1, 0, 1, [m0] ; C81D0401 V_INTERP_P1_F32 v5, v0, 3, 0, [m0] ; C8140300 V_INTERP_P2_F32 v5, [v5], v1, 3, 0, [m0] ; C8150301 V_INTERP_P1_F32 v9, v0, 2, 0, [m0] ; C8240200 V_INTERP_P2_F32 v9, [v9], v1, 2, 0, [m0] ; C8250201 V_CMP_U_F32_e64 s[8:9], v2, v2, 0, 0, 0, 0 ; D0100008 02020502 V_CMP_GT_F32_e64 s[10:11], v2, 0.000000e+00, 0, 0, 0, 0 ; D008000A 02010102 S_OR_B64 s[8:9], s[10:11], s[8:9] ; 8888080A V_CNDMASK_B32_e64 v0, 0.000000e+00, 1.000000e+00, s[8:9], 0, 0, 0, 0 ; D2000000 0021E480 V_ADD_F32_e64 v1, 0, v0, 0, 1, 0, 0 ; D2060801 02020080 V_MOV_B32_e32 v0, 0.000000e+00 ; 7E000280 S_AND_SAVEEXEC_B64 s[6:7], s[6:7] ; BE862406 S_XOR_B64 s[6:7], exec, s[6:7] ; 8986067E S_MOV_B64 exec, 0 ; BEFE0480 V_MOV_B32_e32 v0, -nan ; 7E0002C1 S_OR_B64 exec, exec, s[6:7] ; 88FE067E S_LOAD_DWORDX4 s[8:11], s[2:3], 0 ; C0840300 S_LOAD_DWORDX8 s[12:19], s[4:5], 0 ; C0C60500 S_CBRANCH_EXECNZ 3 ; BF890003 EXP 0, 9, 0, 1, 1, v0, v0, v0, v0 ; F8001890 00000000 S_ENDPGM ; BF810000 S_LOAD_DWORDX4 s[24:27], s[0:1], 4 ; C08C0104 S_WAITCNT lgkmcnt(0) ; BF8C007F S_BUFFER_LOAD_DWORD s40, s[24:27], 49 ; C2141931 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v2, s40, v11, 0, 0, 0, 0 ; D2100002 02021628 S_BUFFER_LOAD_DWORD s41, s[24:27], 53 ; C2149935 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v2, s41, v10, v2, 0, 0, 0, 0 ; D2820002 040A1429 S_BUFFER_LOAD_DWORD s42, s[24:27], 57 ; C2151939 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v2, s42, v3, v2, 0, 0, 0, 0 ; D2820002 040A062A S_BUFFER_LOAD_DWORD s43, s[24:27], 61 ; C215993D S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v17, s43, v2 ; 0622042B S_LOAD_DWORDX4 s[20:23], s[0:1], 8 ; C08A0108 S_WAITCNT lgkmcnt(0) ; BF8C007F S_BUFFER_LOAD_DWORD s6, s[20:23], 61 ; C203153D S_WAITCNT lgkmcnt(0) ; BF8C007F V_SUBREV_F32_e32 v2, s6, v17 ; 0A042206 S_BUFFER_LOAD_DWORD s44, s[24:27], 48 ; C2161930 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v12, s44, v11, 0, 0, 0, 0 ; D210000C 0202162C S_BUFFER_LOAD_DWORD s45, s[24:27], 52 ; C2169934 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v12, s45, v10, v12, 0, 0, 0, 0 ; D282000C 0432142D S_BUFFER_LOAD_DWORD s46, s[24:27], 56 ; C2171938 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v12, s46, v3, v12, 0, 0, 0, 0 ; D282000C 0432062E S_BUFFER_LOAD_DWORD s47, s[24:27], 60 ; C217993C S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v18, s47, v12 ; 0624182F S_BUFFER_LOAD_DWORD s7, s[20:23], 60 ; C203953C S_WAITCNT lgkmcnt(0) ; BF8C007F V_SUBREV_F32_e32 v12, s7, v18 ; 0A182407 V_MUL_F32_e32 v12, v12, v12 ; 1018190C V_MAD_F32 v2, v2, v2, v12, 0, 0, 0, 0 ; D2820002 04320502 S_BUFFER_LOAD_DWORD s48, s[24:27], 50 ; C2181932 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v12, s48, v11, 0, 0, 0, 0 ; D210000C 02021630 S_BUFFER_LOAD_DWORD s49, s[24:27], 54 ; C2189936 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v12, s49, v10, v12, 0, 0, 0, 0 ; D282000C 04321431 S_BUFFER_LOAD_DWORD s50, s[24:27], 58 ; C219193A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v12, s50, v3, v12, 0, 0, 0, 0 ; D282000C 04320632 S_BUFFER_LOAD_DWORD s51, s[24:27], 62 ; C219993E S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v19, s51, v12 ; 06261833 S_BUFFER_LOAD_DWORD s36, s[20:23], 62 ; C212153E S_WAITCNT lgkmcnt(0) ; BF8C007F V_SUBREV_F32_e32 v12, s36, v19 ; 0A182624 V_MAD_F32 v2, v12, v12, v2, 0, 0, 0, 0 ; D2820002 040A190C V_RSQ_LEGACY_F32_e32 v12, v2 ; 7E185B02 V_MUL_F32_e32 v12, v12, v2 ; 1018050C V_XOR_B32_e32 v2, -2147483648, v2 ; 3A0404FF 80000000 V_CMP_GT_F32_e64 s[24:25], 0, v2, 0, 0, 0, 0 ; D0080018 02020480 V_CNDMASK_B32_e64 v20, 0.000000e+00, v12, s[24:25], 0, 0, 0, 0 ; D2000014 00621880 S_BUFFER_LOAD_DWORD s39, s[20:23], 64 ; C2139540 V_MOV_B32_e32 v2, 8.000000e-01 ; 7E0402FF 3F4CCCCD S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v2, s39, v2 ; 10040427 V_CMP_LT_F32_e64 s[24:25], v20, v2, 0, 0, 0, 0 ; D0020018 02020514 V_CNDMASK_B32_e64 v2, 0, -1, s[24:25], 0, 0, 0, 0 ; D2000002 00618280 V_CMP_EQ_I32_e64 s[52:53], v2, 0, 0, 0, 0, 0 ; D1040034 02010102 V_XOR_B32_e64 v1, -1, v1, 0, 0, 0, 0 ; D23A0001 020202C1 V_AND_B32_e32 v12, 1065353216, v1 ; 361802F2 V_MUL_F32_e32 v1, v7, v12 ; 10021907 V_SUB_F32_e32 v21, 1.000000e+00, v12 ; 082A18F2 V_MUL_F32_e32 v2, v7, v21 ; 10042B07 V_SUB_F32_e32 v1, v2, v1 ; 08020302 V_MUL_F32_e32 v2, v9, v12 ; 10041909 V_MUL_F32_e32 v7, v9, v21 ; 100E2B09 V_SUB_F32_e32 v2, v7, v2 ; 08040507 V_MUL_F32_e32 v7, v5, v12 ; 100E1905 V_MUL_F32_e32 v5, v5, v21 ; 100A2B05 V_SUB_F32_e32 v12, v5, v7 ; 08180F05 V_ADD_F32_e32 v5, 1.050000e+00, v12 ; 060A18FF 3F866666 V_ADD_F32_e64 v9, 0, v5, 0, 1, 0, 0 ; D2060809 02020A80 S_LOAD_DWORDX4 s[24:27], s[2:3], 4 ; C08C0304 S_LOAD_DWORDX8 s[28:35], s[4:5], 8 ; C0CE0508 S_WAITCNT lgkmcnt(0) ; BF8C007F S_AND_SAVEEXEC_B64 s[58:59], s[52:53] ; BEBA2434 S_XOR_B64 s[58:59], exec, s[58:59] ; 89BA3A7E S_CBRANCH_EXECZ BB0_3 ; BF880000 V_CMP_LT_F32_e64 s[2:3], s39, v20, 0, 0, 0, 0 ; D0020002 02022827 V_CNDMASK_B32_e64 v5, 0, -1, s[2:3], 0, 0, 0, 0 ; D2000005 00098280 V_CMP_EQ_I32_e64 s[2:3], v5, 0, 0, 0, 0, 0 ; D1040002 02010105 S_AND_SAVEEXEC_B64 s[2:3], s[2:3] ; BE822402 S_XOR_B64 s[2:3], exec, s[2:3] ; 8982027E S_CBRANCH_EXECZ BB0_8 ; BF880000 V_MOV_B32_e32 v5, -8.000000e-01 ; 7E0A02FF BF4CCCCD V_MAD_F32 v7, s39, v5, v20, 0, 0, 0, 0 ; D2820007 04520A27 V_MOV_B32_e32 v20, s39 ; 7E280227 V_MAD_F32 v5, s39, v5, v20, 0, 0, 0, 0 ; D2820005 04520A27 V_RCP_F32_e32 v5, v5 ; 7E0A5505 V_MUL_F32_e32 v5, v7, v5 ; 100A0B07 V_ADD_F32_e64 v5, 0, v5, 0, 1, 0, 0 ; D2060805 02020A80 V_ADD_F32_e32 v7, v5, v5 ; 060E0B05 V_SUB_F32_e32 v7, 3.000000e+00, v7 ; 080E0EFF 40400000 V_MUL_F32_e32 v7, v5, v7 ; 100E0F05 V_MUL_F32_e32 v5, v5, v7 ; 100A0F05 V_SUB_F32_e32 v7, 1.000000e+00, v5 ; 080E0AF2 S_BUFFER_LOAD_DWORD s4, s[20:23], 18 ; C2021512 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v20, s4, v18, 0, 0, 0, 0 ; D2100014 02022404 S_BUFFER_LOAD_DWORD s4, s[20:23], 22 ; C2021516 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v20, s4, v17, v20, 0, 0, 0, 0 ; D2820014 04522204 S_BUFFER_LOAD_DWORD s4, s[20:23], 26 ; C202151A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v20, s4, v19, v20, 0, 0, 0, 0 ; D2820014 04522604 S_BUFFER_LOAD_DWORD s4, s[20:23], 30 ; C202151E S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v20, s4, v20 ; 06282804 V_CMP_U_F32_e64 s[4:5], v20, v20, 0, 0, 0, 0 ; D0100004 02022914 V_CMP_GE_F32_e64 s[52:53], v20, -1.000000e+00, 0, 0, 0, 0 ; D00C0034 0201E714 S_OR_B64 s[4:5], s[52:53], s[4:5] ; 88840434 V_CNDMASK_B32_e64 v20, -1.000000e+00, v20, s[4:5], 0, 0, 0, 0 ; D2000014 001228F3 V_CMP_U_F32_e64 s[4:5], v20, v20, 0, 0, 0, 0 ; D0100004 02022914 V_CMP_GE_F32_e64 s[52:53], v20, 1.000000e+00, 0, 0, 0, 0 ; D00C0034 0201E514 S_OR_B64 s[4:5], s[52:53], s[4:5] ; 88840434 V_CNDMASK_B32_e64 v20, v20, 1.000000e+00, s[4:5], 0, 0, 0, 0 ; D2000014 0011E514 V_ADD_F32_e32 v20, 1.000000e+00, v20 ; 062828F2 S_BUFFER_LOAD_DWORD s4, s[20:23], 63 ; C202153F V_MOV_B32_e32 v21, -2147483648 ; 7E2A02FF 80000000 S_WAITCNT lgkmcnt(0) ; BF8C007F V_XOR_B32_e32 v21, s4, v21 ; 3A2A2A04 V_MUL_F32_e32 v20, v21, v20 ; 10282915 V_MUL_F32_e32 v20, 7.213475e-01, v20 ; 102828FF 3F38AA3B V_EXP_F32_e32 v20, v20 ; 7E284B14 S_BUFFER_LOAD_DWORD s4, s[20:23], 17 ; C2021511 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v22, s4, v18, 0, 0, 0, 0 ; D2100016 02022404 S_BUFFER_LOAD_DWORD s4, s[20:23], 21 ; C2021515 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v22, s4, v17, v22, 0, 0, 0, 0 ; D2820016 045A2204 S_BUFFER_LOAD_DWORD s4, s[20:23], 25 ; C2021519 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v22, s4, v19, v22, 0, 0, 0, 0 ; D2820016 045A2604 S_BUFFER_LOAD_DWORD s4, s[20:23], 29 ; C202151D S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v22, s4, v22 ; 062C2C04 V_MAD_F32 v22, v22, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0 ; D2820016 03C1E116 S_BUFFER_LOAD_DWORD s4, s[20:23], 66 ; C2021542 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v23, s4, v22 ; 102E2C04 S_BUFFER_LOAD_DWORD s5, s[20:23], 16 ; C2029510 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v24, s5, v18, 0, 0, 0, 0 ; D2100018 02022405 S_BUFFER_LOAD_DWORD s5, s[20:23], 20 ; C2029514 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v24, s5, v17, v24, 0, 0, 0, 0 ; D2820018 04622205 S_BUFFER_LOAD_DWORD s5, s[20:23], 24 ; C2029518 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v24, s5, v19, v24, 0, 0, 0, 0 ; D2820018 04622605 S_BUFFER_LOAD_DWORD s5, s[20:23], 28 ; C202951C S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v24, s5, v24 ; 06303005 V_MAD_F32 v24, v24, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0 ; D2820018 03C1E118 V_MUL_F32_e32 v22, s4, v24 ; 102C3004 IMAGE_SAMPLE v22, 1, -1, 0, 0, 0, 0, 0, 0, v[22:23], s[12:19], s[8:11] ; F0801100 00431616 S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v20, v20, v22 ; 10282D14 V_ADD_F32_e64 v20, 0, v20, 0, 1, 0, 0 ; D2060814 02022880 V_MUL_F32_e32 v7, v7, v20 ; 100E2907 S_BUFFER_LOAD_DWORD s5, s[20:23], 34 ; C2029522 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v20, s5, v18, 0, 0, 0, 0 ; D2100014 02022405 S_BUFFER_LOAD_DWORD s5, s[20:23], 38 ; C2029526 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v20, s5, v17, v20, 0, 0, 0, 0 ; D2820014 04522205 S_BUFFER_LOAD_DWORD s5, s[20:23], 42 ; C202952A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v20, s5, v19, v20, 0, 0, 0, 0 ; D2820014 04522605 S_BUFFER_LOAD_DWORD s5, s[20:23], 46 ; C202952E S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v20, s5, v20 ; 06282805 V_CMP_U_F32_e64 s[52:53], v20, v20, 0, 0, 0, 0 ; D0100034 02022914 V_CMP_GE_F32_e64 s[54:55], v20, -1.000000e+00, 0, 0, 0, 0 ; D00C0036 0201E714 S_OR_B64 s[52:53], s[54:55], s[52:53] ; 88B43436 V_CNDMASK_B32_e64 v20, -1.000000e+00, v20, s[52:53], 0, 0, 0, 0 ; D2000014 00D228F3 V_CMP_U_F32_e64 s[52:53], v20, v20, 0, 0, 0, 0 ; D0100034 02022914 V_CMP_GE_F32_e64 s[54:55], v20, 1.000000e+00, 0, 0, 0, 0 ; D00C0036 0201E514 S_OR_B64 s[52:53], s[54:55], s[52:53] ; 88B43436 V_CNDMASK_B32_e64 v20, v20, 1.000000e+00, s[52:53], 0, 0, 0, 0 ; D2000014 00D1E514 V_ADD_F32_e32 v20, 1.000000e+00, v20 ; 062828F2 V_MUL_F32_e32 v20, v21, v20 ; 10282915 V_MUL_F32_e32 v20, 7.213475e-01, v20 ; 102828FF 3F38AA3B V_EXP_F32_e32 v20, v20 ; 7E284B14 S_BUFFER_LOAD_DWORD s5, s[20:23], 33 ; C2029521 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v21, s5, v18, 0, 0, 0, 0 ; D2100015 02022405 S_BUFFER_LOAD_DWORD s5, s[20:23], 37 ; C2029525 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v21, s5, v17, v21, 0, 0, 0, 0 ; D2820015 04562205 S_BUFFER_LOAD_DWORD s5, s[20:23], 41 ; C2029529 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v21, s5, v19, v21, 0, 0, 0, 0 ; D2820015 04562605 S_BUFFER_LOAD_DWORD s5, s[20:23], 45 ; C202952D S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v21, s5, v21 ; 062A2A05 V_MAD_F32 v21, v21, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0 ; D2820015 03C1E115 V_MUL_F32_e32 v22, s4, v21 ; 102C2A04 S_BUFFER_LOAD_DWORD s5, s[20:23], 32 ; C2029520 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v23, s5, v18, 0, 0, 0, 0 ; D2100017 02022405 S_BUFFER_LOAD_DWORD s5, s[20:23], 36 ; C2029524 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v23, s5, v17, v23, 0, 0, 0, 0 ; D2820017 045E2205 S_BUFFER_LOAD_DWORD s5, s[20:23], 40 ; C2029528 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v23, s5, v19, v23, 0, 0, 0, 0 ; D2820017 045E2605 S_BUFFER_LOAD_DWORD s5, s[20:23], 44 ; C202952C S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v23, s5, v23 ; 062E2E05 V_MAD_F32 v23, v23, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0 ; D2820017 03C1E117 V_MUL_F32_e32 v21, s4, v23 ; 102A2E04 IMAGE_SAMPLE v21, 1, -1, 0, 0, 0, 0, 0, 0, v[21:22], s[28:35], s[24:27] ; F0801100 00C71515 S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v20, v20, v21 ; 10282B14 V_ADD_F32_e64 v20, 0, v20, 0, 1, 0, 0 ; D2060814 02022880 V_MAD_F32 v24, v5, v20, v7, 0, 0, 0, 0 ; D2820018 041E2905 S_OR_SAVEEXEC_B64 s[2:3], s[2:3] ; BE822502 S_XOR_B64 exec, exec, s[2:3] ; 89FE027E S_CBRANCH_EXECZ BB0_6 ; BF880000 V_MOV_B32_e32 v5, s6 ; 7E0A0206 V_SUB_F32_e64 v5, v17, v5, 0, 0, 0, 0 ; D2080005 02020B11 V_MOV_B32_e32 v7, s7 ; 7E0E0207 V_SUB_F32_e64 v7, v18, v7, 0, 0, 0, 0 ; D2080007 02020F12 V_MUL_F32_e32 v7, v7, v7 ; 100E0F07 V_MAD_F32 v5, v5, v5, v7, 0, 0, 0, 0 ; D2820005 041E0B05 V_MOV_B32_e32 v7, s36 ; 7E0E0224 V_SUB_F32_e64 v7, v19, v7, 0, 0, 0, 0 ; D2080007 02020F13 V_MAD_F32 v5, v7, v7, v5, 0, 0, 0, 0 ; D2820005 04160F07 V_RSQ_LEGACY_F32_e32 v7, v5 ; 7E0E5B05 V_MUL_F32_e32 v7, v7, v5 ; 100E0B07 V_XOR_B32_e32 v5, -2147483648, v5 ; 3A0A0AFF 80000000 V_CMP_GT_F32_e64 s[4:5], 0, v5, 0, 0, 0, 0 ; D0080004 02020A80 V_CNDMASK_B32_e64 v5, 0.000000e+00, v7, s[4:5], 0, 0, 0, 0 ; D2000005 00120E80 S_BUFFER_LOAD_DWORD s4, s[20:23], 65 ; C2021541 S_WAITCNT lgkmcnt(0) ; BF8C007F V_RCP_F32_e32 v7, s4 ; 7E0E5404 V_MOV_B32_e32 v20, -8.000000e-01 ; 7E2802FF BF4CCCCD V_MAD_F32 v5, v5, v7, v20, 0, 0, 0, 0 ; D2820005 04520F05 V_MUL_F32_e32 v5, 5.000000e+00, v5 ; 100A0AFF 40A00001 V_ADD_F32_e64 v5, 0, v5, 0, 1, 0, 0 ; D2060805 02020A80 V_ADD_F32_e32 v7, v5, v5 ; 060E0B05 V_SUB_F32_e32 v7, 3.000000e+00, v7 ; 080E0EFF 40400000 V_MUL_F32_e32 v7, v5, v7 ; 100E0F05 V_MUL_F32_e32 v20, v5, v7 ; 10280F05 V_SUB_F32_e32 v20, 1.000000e+00, v20 ; 082828F2 S_BUFFER_LOAD_DWORD s4, s[20:23], 34 ; C2021522 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v21, s4, v18, 0, 0, 0, 0 ; D2100015 02022404 S_BUFFER_LOAD_DWORD s4, s[20:23], 38 ; C2021526 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v21, s4, v17, v21, 0, 0, 0, 0 ; D2820015 04562204 S_BUFFER_LOAD_DWORD s4, s[20:23], 42 ; C202152A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v21, s4, v19, v21, 0, 0, 0, 0 ; D2820015 04562604 S_BUFFER_LOAD_DWORD s4, s[20:23], 46 ; C202152E S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v21, s4, v21 ; 062A2A04 V_CMP_U_F32_e64 s[4:5], v21, v21, 0, 0, 0, 0 ; D0100004 02022B15 V_CMP_GE_F32_e64 s[52:53], v21, -1.000000e+00, 0, 0, 0, 0 ; D00C0034 0201E715 S_OR_B64 s[4:5], s[52:53], s[4:5] ; 88840434 V_CNDMASK_B32_e64 v21, -1.000000e+00, v21, s[4:5], 0, 0, 0, 0 ; D2000015 00122AF3 V_CMP_U_F32_e64 s[4:5], v21, v21, 0, 0, 0, 0 ; D0100004 02022B15 V_CMP_GE_F32_e64 s[52:53], v21, 1.000000e+00, 0, 0, 0, 0 ; D00C0034 0201E515 S_OR_B64 s[4:5], s[52:53], s[4:5] ; 88840434 V_CNDMASK_B32_e64 v21, v21, 1.000000e+00, s[4:5], 0, 0, 0, 0 ; D2000015 0011E515 V_ADD_F32_e32 v21, 1.000000e+00, v21 ; 062A2AF2 S_BUFFER_LOAD_DWORD s4, s[20:23], 63 ; C202153F S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v21, s4, v21 ; 102A2A04 V_MUL_F32_e32 v21, -7.213475e-01, v21 ; 102A2AFF BF38AA3B V_EXP_F32_e32 v21, v21 ; 7E2A4B15 S_BUFFER_LOAD_DWORD s4, s[20:23], 33 ; C2021521 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v22, s4, v18, 0, 0, 0, 0 ; D2100016 02022404 S_BUFFER_LOAD_DWORD s4, s[20:23], 37 ; C2021525 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v22, s4, v17, v22, 0, 0, 0, 0 ; D2820016 045A2204 S_BUFFER_LOAD_DWORD s4, s[20:23], 41 ; C2021529 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v22, s4, v19, v22, 0, 0, 0, 0 ; D2820016 045A2604 S_BUFFER_LOAD_DWORD s4, s[20:23], 45 ; C202152D S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v22, s4, v22 ; 062C2C04 V_MAD_F32 v22, v22, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0 ; D2820016 03C1E116 S_BUFFER_LOAD_DWORD s4, s[20:23], 66 ; C2021542 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v23, s4, v22 ; 102E2C04 S_BUFFER_LOAD_DWORD s5, s[20:23], 32 ; C2029520 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v24, s5, v18, 0, 0, 0, 0 ; D2100018 02022405 S_BUFFER_LOAD_DWORD s5, s[20:23], 36 ; C2029524 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v24, s5, v17, v24, 0, 0, 0, 0 ; D2820018 04622205 S_BUFFER_LOAD_DWORD s5, s[20:23], 40 ; C2029528 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v24, s5, v19, v24, 0, 0, 0, 0 ; D2820018 04622605 S_BUFFER_LOAD_DWORD s5, s[20:23], 44 ; C202952C S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v24, s5, v24 ; 06303005 V_MAD_F32 v24, v24, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0 ; D2820018 03C1E118 V_MUL_F32_e32 v22, s4, v24 ; 102C3004 IMAGE_SAMPLE v22, 1, -1, 0, 0, 0, 0, 0, 0, v[22:23], s[28:35], s[24:27] ; F0801100 00C71616 S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v21, v21, v22 ; 102A2D15 V_ADD_F32_e64 v21, 0, v21, 0, 1, 0, 0 ; D2060815 02022A80 V_MUL_F32_e32 v20, v20, v21 ; 10282B14 V_MAD_F32 v24, v5, v7, v20, 0, 0, 0, 0 ; D2820018 04520F05 S_OR_B64 exec, exec, s[2:3] ; 88FE027E S_OR_SAVEEXEC_B64 s[58:59], s[58:59] ; BEBA253A S_LOAD_DWORDX4 s[0:3], s[0:1], 0 ; C0800100 S_WAITCNT lgkmcnt(0) ; BF8C007F S_BUFFER_LOAD_DWORD s4, s[0:3], 12 ; C202010C S_BUFFER_LOAD_DWORD s38, s[20:23], 54 ; C2131536 S_BUFFER_LOAD_DWORD s37, s[20:23], 53 ; C2129535 S_BUFFER_LOAD_DWORD s5, s[20:23], 52 ; C2029534 S_BUFFER_LOAD_DWORD s52, s[20:23], 50 ; C21A1532 S_BUFFER_LOAD_DWORD s53, s[20:23], 49 ; C21A9531 S_BUFFER_LOAD_DWORD s54, s[20:23], 48 ; C21B1530 S_BUFFER_LOAD_DWORD s55, s[20:23], 58 ; C21B953A S_BUFFER_LOAD_DWORD s56, s[20:23], 57 ; C21C1539 S_BUFFER_LOAD_DWORD s57, s[20:23], 56 ; C21C9538 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v5, s52 ; 7E0A0234 V_MOV_B32_e32 v22, s53 ; 7E2C0235 V_MOV_B32_e32 v23, s54 ; 7E2E0236 V_MOV_B32_e32 v21, s55 ; 7E2A0237 V_MOV_B32_e32 v7, s56 ; 7E0E0238 V_MOV_B32_e32 v20, s57 ; 7E280239 S_XOR_B64 exec, exec, s[58:59] ; 89FE3A7E S_CBRANCH_EXECZ BB0_7 ; BF880000 S_BUFFER_LOAD_DWORD s60, s[20:23], 18 ; C21E1512 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v24, s60, v18, 0, 0, 0, 0 ; D2100018 0202243C S_BUFFER_LOAD_DWORD s60, s[20:23], 22 ; C21E1516 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v24, s60, v17, v24, 0, 0, 0, 0 ; D2820018 0462223C S_BUFFER_LOAD_DWORD s60, s[20:23], 26 ; C21E151A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v24, s60, v19, v24, 0, 0, 0, 0 ; D2820018 0462263C S_BUFFER_LOAD_DWORD s60, s[20:23], 30 ; C21E151E S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v24, s60, v24 ; 0630303C V_CMP_U_F32_e64 s[60:61], v24, v24, 0, 0, 0, 0 ; D010003C 02023118 V_CMP_GE_F32_e64 s[62:63], v24, -1.000000e+00, 0, 0, 0, 0 ; D00C003E 0201E718 S_OR_B64 s[60:61], s[62:63], s[60:61] ; 88BC3C3E V_CNDMASK_B32_e64 v24, -1.000000e+00, v24, s[60:61], 0, 0, 0, 0 ; D2000018 00F230F3 V_CMP_U_F32_e64 s[60:61], v24, v24, 0, 0, 0, 0 ; D010003C 02023118 V_CMP_GE_F32_e64 s[62:63], v24, 1.000000e+00, 0, 0, 0, 0 ; D00C003E 0201E518 S_OR_B64 s[60:61], s[62:63], s[60:61] ; 88BC3C3E V_CNDMASK_B32_e64 v24, v24, 1.000000e+00, s[60:61], 0, 0, 0, 0 ; D2000018 00F1E518 V_ADD_F32_e32 v24, 1.000000e+00, v24 ; 063030F2 S_BUFFER_LOAD_DWORD s60, s[20:23], 63 ; C21E153F S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v24, s60, v24 ; 1030303C V_MUL_F32_e32 v24, -7.213475e-01, v24 ; 103030FF BF38AA3B V_EXP_F32_e32 v24, v24 ; 7E304B18 S_BUFFER_LOAD_DWORD s60, s[20:23], 17 ; C21E1511 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v25, s60, v18, 0, 0, 0, 0 ; D2100019 0202243C S_BUFFER_LOAD_DWORD s60, s[20:23], 21 ; C21E1515 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v25, s60, v17, v25, 0, 0, 0, 0 ; D2820019 0466223C S_BUFFER_LOAD_DWORD s60, s[20:23], 25 ; C21E1519 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v25, s60, v19, v25, 0, 0, 0, 0 ; D2820019 0466263C S_BUFFER_LOAD_DWORD s60, s[20:23], 29 ; C21E151D S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v25, s60, v25 ; 0632323C V_MAD_F32 v25, v25, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0 ; D2820019 03C1E119 S_BUFFER_LOAD_DWORD s60, s[20:23], 66 ; C21E1542 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v26, s60, v25 ; 1034323C S_BUFFER_LOAD_DWORD s61, s[20:23], 16 ; C21E9510 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v27, s61, v18, 0, 0, 0, 0 ; D210001B 0202243D S_BUFFER_LOAD_DWORD s61, s[20:23], 20 ; C21E9514 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v27, s61, v17, v27, 0, 0, 0, 0 ; D282001B 046E223D S_BUFFER_LOAD_DWORD s61, s[20:23], 24 ; C21E9518 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v27, s61, v19, v27, 0, 0, 0, 0 ; D282001B 046E263D S_BUFFER_LOAD_DWORD s61, s[20:23], 28 ; C21E951C S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v27, s61, v27 ; 0636363D V_MAD_F32 v27, v27, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0 ; D282001B 03C1E11B V_MUL_F32_e32 v25, s60, v27 ; 1032363C IMAGE_SAMPLE v25, 1, -1, 0, 0, 0, 0, 0, 0, v[25:26], s[12:19], s[8:11] ; F0801100 00431919 S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v24, v24, v25 ; 10303318 V_ADD_F32_e64 v24, 0, v24, 0, 1, 0, 0 ; D2060818 02023080 S_OR_B64 exec, exec, s[58:59] ; 88FE3A7E V_MOV_B32_e32 v25, -8.000000e-01 ; 7E3202FF BF4CCCCD V_ADD_F32_e32 v24, v24, v25 ; 06303318 V_MUL_F32_e32 v24, 5.000000e+00, v24 ; 103030FF 40A00001 V_ADD_F32_e64 v24, 0, v24, 0, 1, 0, 0 ; D2060818 02023080 V_ADD_F32_e32 v25, v24, v24 ; 06323118 V_SUB_F32_e32 v25, 3.000000e+00, v25 ; 083232FF 40400000 V_MUL_F32_e32 v25, v24, v25 ; 10323318 V_MUL_F32_e32 v24, v24, v25 ; 10303318 V_MUL_F32_e64 v23, v2, v23, 0, 0, 0, 0 ; D2100017 02022F02 V_MAD_F32 v22, v12, v22, v23, 0, 0, 0, 0 ; D2820016 045E2D0C V_MAD_F32 v5, v1, v5, v22, 0, 0, 0, 0 ; D2820005 045A0B01 V_CMP_U_F32_e64 s[58:59], v5, v5, 0, 0, 0, 0 ; D010003A 02020B05 V_CMP_LE_F32_e64 s[60:61], v5, 0.000000e+00, 0, 0, 0, 0 ; D006003C 02010105 S_OR_B64 s[58:59], s[60:61], s[58:59] ; 88BA3A3C V_CNDMASK_B32_e64 v22, v5, 0.000000e+00, s[58:59], 0, 0, 0, 0 ; D2000016 00E90105 V_MUL_F32_e32 v23, s38, v22 ; 102E2C26 V_MOV_B32_e32 v5, 1.000000e-03 ; 7E0A02FF 3A83126F V_ADD_F32_e32 v5, v16, v5 ; 060A0B10 V_RCP_F32_e32 v25, v5 ; 7E325505 V_MUL_F32_e32 v5, v15, v25 ; 100A330F V_MUL_F32_e32 v5, v4, v5 ; 100A0B04 V_MUL_F32_e32 v4, v23, v5 ; 10080B17 V_MUL_F32_e32 v4, v4, v24 ; 10083104 V_MUL_F32_e64 v21, v9, v21, 0, 0, 0, 0 ; D2100015 02022B09 V_MAD_F32 v4, v5, v21, v4, 0, 0, 0, 0 ; D2820004 04122B05 V_MUL_F32_e32 v21, s37, v22 ; 102A2C25 V_MUL_F32_e32 v23, v14, v25 ; 102E330E V_MUL_F32_e32 v6, v6, v23 ; 100C2F06 V_MUL_F32_e32 v21, v21, v6 ; 102A0D15 V_MUL_F32_e32 v21, v21, v24 ; 102A3115 V_MUL_F32_e64 v7, v9, v7, 0, 0, 0, 0 ; D2100007 02020F09 V_MAD_F32 v7, v6, v7, v21, 0, 0, 0, 0 ; D2820007 04560F06 V_MUL_F32_e32 v21, s5, v22 ; 102A2C05 V_MUL_F32_e32 v13, v13, v25 ; 101A330D V_MUL_F32_e32 v8, v8, v13 ; 10101B08 V_MUL_F32_e32 v13, v21, v8 ; 101A1115 V_MUL_F32_e32 v13, v13, v24 ; 101A310D V_MUL_F32_e64 v9, v9, v20, 0, 0, 0, 0 ; D2100009 02022909 V_MAD_F32 v9, v8, v9, v13, 0, 0, 0, 0 ; D2820009 04361308 V_MOV_B32_e32 v15, -2147483648 ; 7E1E02FF 80000000 V_XOR_B32_e32 v13, v19, v15 ; 3A1A1F13 V_XOR_B32_e32 v14, v17, v15 ; 3A1C1F11 V_XOR_B32_e32 v15, v18, v15 ; 3A1E1F12 V_MOV_B32_e32 v16, 0.000000e+00 ; 7E200280 S_MOV_B64 s[58:59], 0 ; BEBA0480 V_MOV_B32_e32 v17, s4 ; 7E220204 V_CMP_GE_I32_e64 s[60:61], v16, v17, 0, 0, 0, 0 ; D10C003C 02022310 V_CNDMASK_B32_e64 v18, 0, -1, s[60:61], 0, 0, 0, 0 ; D2000012 00F18280 V_CMP_EQ_I32_e64 s[60:61], v18, 0, 0, 0, 0, 0 ; D104003C 02010112 S_AND_SAVEEXEC_B64 s[60:61], s[60:61] ; BEBC243C S_XOR_B64 s[60:61], exec, s[60:61] ; 89BC3C7E S_CBRANCH_EXECZ BB0_12 ; BF880000 V_MUL_LO_I32 v18, 7, v16, 0, 0, 0, 0, 0 ; D2D60012 02022087 V_LSHLREV_B32_e32 v18, 4, v18 ; 34242484 V_ADD_I32_e32 v19, 80, v18 ; 4A2624FF 00000050 BUFFER_LOAD_DWORD v19, s[0:3] + v19 + 0, glc=0, slc=0, tfe=0 ; E0301000 80001313 S_WAITCNT vmcnt(0) ; BF8C0770 V_ADD_F32_e32 v19, v14, v19 ; 0626270E V_ADD_I32_e32 v20, 64, v18 ; 4A2824C0 BUFFER_LOAD_DWORD v20, s[0:3] + v20 + 0, glc=0, slc=0, tfe=0 ; E0301000 80001414 S_WAITCNT vmcnt(0) ; BF8C0770 V_ADD_F32_e32 v20, v15, v20 ; 0628290F V_MUL_F32_e32 v21, v20, v20 ; 102A2914 V_MAD_F32 v21, v19, v19, v21, 0, 0, 0, 0 ; D2820015 04562713 V_ADD_I32_e32 v22, 96, v18 ; 4A2C24FF 00000060 BUFFER_LOAD_DWORD v22, s[0:3] + v22 + 0, glc=0, slc=0, tfe=0 ; E0301000 80001616 S_WAITCNT vmcnt(0) ; BF8C0770 V_ADD_F32_e32 v22, v13, v22 ; 062C2D0D V_MAD_F32 v21, v22, v22, v21, 0, 0, 0, 0 ; D2820015 04562D16 V_RSQ_LEGACY_F32_e32 v23, v21 ; 7E2E5B15 V_MUL_F32_e32 v23, v23, v21 ; 102E2B17 V_XOR_B32_e32 v21, -2147483648, v21 ; 3A2A2AFF 80000000 V_CMP_GT_F32_e64 s[62:63], 0, v21, 0, 0, 0, 0 ; D008003E 02022A80 V_CNDMASK_B32_e64 v21, 0.000000e+00, v23, s[62:63], 0, 0, 0, 0 ; D2000015 00FA2E80 V_RCP_F32_e32 v23, v21 ; 7E2E5515 V_MUL_F32_e32 v19, v19, v23 ; 10262F13 V_MUL_F32_e32 v20, v20, v23 ; 10282F14 V_MUL_F32_e32 v20, v2, v20 ; 10282902 V_MAD_F32 v19, v12, v19, v20, 0, 0, 0, 0 ; D2820013 0452270C V_MUL_F32_e32 v20, v22, v23 ; 10282F16 V_MAD_F32 v19, v1, v20, v19, 0, 0, 0, 0 ; D2820013 044E2901 V_CMP_U_F32_e64 s[62:63], v19, v19, 0, 0, 0, 0 ; D010003E 02022713 V_CMP_LE_F32_e64 s[64:65], v19, 0.000000e+00, 0, 0, 0, 0 ; D0060040 02010113 S_OR_B64 s[62:63], s[64:65], s[62:63] ; 88BE3E40 V_CNDMASK_B32_e64 v19, v19, 0.000000e+00, s[62:63], 0, 0, 0, 0 ; D2000013 00F90113 V_ADD_I32_e32 v20, 144, v18 ; 4A2824FF 00000090 BUFFER_LOAD_DWORD v20, s[0:3] + v20 + 0, glc=0, slc=0, tfe=0 ; E0301000 80001414 S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v20, v19, v20 ; 10282913 V_MUL_F32_e32 v20, v5, v20 ; 10282905 V_ADD_I32_e32 v22, 160, v18 ; 4A2C24FF 000000A0 BUFFER_LOAD_DWORD v22, s[0:3] + v22 + 0, glc=0, slc=0, tfe=0 ; E0301000 80001616 S_WAITCNT vmcnt(0) ; BF8C0770 V_MAD_F32 v21, v22, -5.000000e-01, v21, 0, 0, 0, 0 ; D2820015 0455E316 V_MAD_F32 v22, v22, -5.000000e-01, v22, 0, 0, 0, 0 ; D2820016 0459E316 V_RCP_F32_e32 v22, v22 ; 7E2C5516 V_MUL_F32_e32 v21, v21, v22 ; 102A2D15 V_ADD_F32_e64 v21, 0, v21, 0, 1, 0, 0 ; D2060815 02022A80 V_ADD_F32_e32 v22, v21, v21 ; 062C2B15 V_SUB_F32_e32 v22, 3.000000e+00, v22 ; 082C2CFF 40400000 V_MUL_F32_e32 v22, v21, v22 ; 102C2D15 V_MUL_F32_e32 v21, v21, v22 ; 102A2D15 V_SUB_F32_e32 v21, 1.000000e+00, v21 ; 082A2AF2 V_MAD_F32 v4, v20, v21, v4, 0, 0, 0, 0 ; D2820004 04122B14 V_ADD_I32_e32 v20, 128, v18 ; 4A2824FF 00000080 BUFFER_LOAD_DWORD v20, s[0:3] + v20 + 0, glc=0, slc=0, tfe=0 ; E0301000 80001414 S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v20, v19, v20 ; 10282913 V_MUL_F32_e32 v20, v6, v20 ; 10282906 V_MAD_F32 v7, v20, v21, v7, 0, 0, 0, 0 ; D2820007 041E2B14 V_ADD_I32_e32 v18, 112, v18 ; 4A2424FF 00000070 BUFFER_LOAD_DWORD v18, s[0:3] + v18 + 0, glc=0, slc=0, tfe=0 ; E0301000 80001212 S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v18, v19, v18 ; 10242513 V_MUL_F32_e32 v18, v8, v18 ; 10242508 V_MAD_F32 v9, v18, v21, v9, 0, 0, 0, 0 ; D2820009 04262B12 V_CMP_NE_I32_e64 s[62:63], v0, 0, 0, 0, 0, 0 ; D10A003E 02010100 S_OR_B64 s[58:59], s[62:63], s[58:59] ; 88BA3A3E V_ADD_I32_e32 v16, 1, v16 ; 4A202081 S_OR_B64 exec, exec, s[60:61] ; 88FE3C7E S_OR_B64 s[58:59], s[60:61], s[58:59] ; 88BA3A3C S_ANDN2_B64 exec, exec, s[58:59] ; 8AFE3A7E S_CBRANCH_EXECNZ BB0_11 ; BF890000 S_OR_B64 exec, exec, s[58:59] ; 88FE3A7E V_MUL_F32_e64 v13, s40, v11, 0, 0, 0, 0 ; D210000D 02021628 V_MAD_F32 v13, s41, v10, v13, 0, 0, 0, 0 ; D282000D 04361429 V_MAD_F32 v13, s42, v3, v13, 0, 0, 0, 0 ; D282000D 0436062A V_ADD_F32_e32 v13, s43, v13 ; 061A1A2B V_SUBREV_F32_e32 v15, s6, v13 ; 0A1E1A06 V_MUL_F32_e64 v14, s44, v11, 0, 0, 0, 0 ; D210000E 0202162C V_MAD_F32 v14, s45, v10, v14, 0, 0, 0, 0 ; D282000E 043A142D V_MAD_F32 v14, s46, v3, v14, 0, 0, 0, 0 ; D282000E 043A062E V_ADD_F32_e32 v14, s47, v14 ; 061C1C2F V_SUBREV_F32_e32 v16, s7, v14 ; 0A201C07 V_MUL_F32_e32 v16, v16, v16 ; 10202110 V_MAD_F32 v15, v15, v15, v16, 0, 0, 0, 0 ; D282000F 04421F0F V_MUL_F32_e64 v11, s48, v11, 0, 0, 0, 0 ; D210000B 02021630 V_MAD_F32 v10, s49, v10, v11, 0, 0, 0, 0 ; D282000A 042E1431 V_MAD_F32 v3, s50, v3, v10, 0, 0, 0, 0 ; D2820003 042A0632 V_ADD_F32_e32 v10, s51, v3 ; 06140633 V_SUBREV_F32_e32 v3, s36, v10 ; 0A061424 V_MAD_F32 v3, v3, v3, v15, 0, 0, 0, 0 ; D2820003 043E0703 V_RSQ_LEGACY_F32_e32 v11, v3 ; 7E165B03 V_MUL_F32_e32 v11, v11, v3 ; 1016070B V_XOR_B32_e32 v3, -2147483648, v3 ; 3A0606FF 80000000 V_CMP_GT_F32_e64 s[40:41], 0, v3, 0, 0, 0, 0 ; D0080028 02020680 V_CNDMASK_B32_e64 v15, 0.000000e+00, v11, s[40:41], 0, 0, 0, 0 ; D200000F 00A21680 V_MOV_B32_e32 v3, 8.000000e-01 ; 7E0602FF 3F4CCCCD V_MUL_F32_e32 v3, s39, v3 ; 10060627 V_CMP_LT_F32_e64 s[40:41], v15, v3, 0, 0, 0, 0 ; D0020028 0202070F V_CNDMASK_B32_e64 v3, 0, -1, s[40:41], 0, 0, 0, 0 ; D2000003 00A18280 V_CMP_EQ_I32_e64 s[40:41], v3, 0, 0, 0, 0, 0 ; D1040028 02010103 V_MOV_B32_e32 v3, -2147483648 ; 7E0602FF 80000000 V_XOR_B32_e32 v3, v12, v3 ; 3A06070C V_SUB_F32_e32 v11, 1.050000e+00, v12 ; 081618FF 3F866666 V_ADD_F32_e64 v11, 0, v11, 0, 1, 0, 0 ; D206080B 02021680 S_AND_SAVEEXEC_B64 s[40:41], s[40:41] ; BEA82428 S_XOR_B64 s[40:41], exec, s[40:41] ; 89A8287E S_CBRANCH_EXECZ BB0_15 ; BF880000 V_CMP_LT_F32_e64 s[42:43], s39, v15, 0, 0, 0, 0 ; D002002A 02021E27 V_CNDMASK_B32_e64 v12, 0, -1, s[42:43], 0, 0, 0, 0 ; D200000C 00A98280 V_CMP_EQ_I32_e64 s[42:43], v12, 0, 0, 0, 0, 0 ; D104002A 0201010C S_AND_SAVEEXEC_B64 s[42:43], s[42:43] ; BEAA242A S_XOR_B64 s[42:43], exec, s[42:43] ; 89AA2A7E S_CBRANCH_EXECZ BB0_20 ; BF880000 V_MOV_B32_e32 v12, -8.000000e-01 ; 7E1802FF BF4CCCCD V_MAD_F32 v15, s39, v12, v15, 0, 0, 0, 0 ; D282000F 043E1827 V_MOV_B32_e32 v16, s39 ; 7E200227 V_MAD_F32 v12, s39, v12, v16, 0, 0, 0, 0 ; D282000C 04421827 V_RCP_F32_e32 v12, v12 ; 7E18550C V_MUL_F32_e32 v12, v15, v12 ; 1018190F V_ADD_F32_e64 v12, 0, v12, 0, 1, 0, 0 ; D206080C 02021880 V_ADD_F32_e32 v15, v12, v12 ; 061E190C V_SUB_F32_e32 v15, 3.000000e+00, v15 ; 081E1EFF 40400000 V_MUL_F32_e32 v15, v12, v15 ; 101E1F0C V_MUL_F32_e32 v12, v12, v15 ; 10181F0C V_SUB_F32_e32 v15, 1.000000e+00, v12 ; 081E18F2 S_BUFFER_LOAD_DWORD s39, s[20:23], 18 ; C2139512 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v16, s39, v14, 0, 0, 0, 0 ; D2100010 02021C27 S_BUFFER_LOAD_DWORD s39, s[20:23], 22 ; C2139516 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v16, s39, v13, v16, 0, 0, 0, 0 ; D2820010 04421A27 S_BUFFER_LOAD_DWORD s39, s[20:23], 26 ; C213951A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v16, s39, v10, v16, 0, 0, 0, 0 ; D2820010 04421427 S_BUFFER_LOAD_DWORD s39, s[20:23], 30 ; C213951E S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v16, s39, v16 ; 06202027 V_CMP_U_F32_e64 s[44:45], v16, v16, 0, 0, 0, 0 ; D010002C 02022110 V_CMP_GE_F32_e64 s[46:47], v16, -1.000000e+00, 0, 0, 0, 0 ; D00C002E 0201E710 S_OR_B64 s[44:45], s[46:47], s[44:45] ; 88AC2C2E V_CNDMASK_B32_e64 v16, -1.000000e+00, v16, s[44:45], 0, 0, 0, 0 ; D2000010 00B220F3 V_CMP_U_F32_e64 s[44:45], v16, v16, 0, 0, 0, 0 ; D010002C 02022110 V_CMP_GE_F32_e64 s[46:47], v16, 1.000000e+00, 0, 0, 0, 0 ; D00C002E 0201E510 S_OR_B64 s[44:45], s[46:47], s[44:45] ; 88AC2C2E V_CNDMASK_B32_e64 v16, v16, 1.000000e+00, s[44:45], 0, 0, 0, 0 ; D2000010 00B1E510 V_ADD_F32_e32 v16, 1.000000e+00, v16 ; 062020F2 S_BUFFER_LOAD_DWORD s39, s[20:23], 63 ; C213953F V_MOV_B32_e32 v17, -2147483648 ; 7E2202FF 80000000 S_WAITCNT lgkmcnt(0) ; BF8C007F V_XOR_B32_e32 v17, s39, v17 ; 3A222227 V_MUL_F32_e32 v16, v17, v16 ; 10202111 V_MUL_F32_e32 v16, 7.213475e-01, v16 ; 102020FF 3F38AA3B V_EXP_F32_e32 v16, v16 ; 7E204B10 S_BUFFER_LOAD_DWORD s39, s[20:23], 17 ; C2139511 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v18, s39, v14, 0, 0, 0, 0 ; D2100012 02021C27 S_BUFFER_LOAD_DWORD s39, s[20:23], 21 ; C2139515 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v18, s39, v13, v18, 0, 0, 0, 0 ; D2820012 044A1A27 S_BUFFER_LOAD_DWORD s39, s[20:23], 25 ; C2139519 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v18, s39, v10, v18, 0, 0, 0, 0 ; D2820012 044A1427 S_BUFFER_LOAD_DWORD s39, s[20:23], 29 ; C213951D S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v18, s39, v18 ; 06242427 V_MAD_F32 v18, v18, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0 ; D2820012 03C1E112 S_BUFFER_LOAD_DWORD s39, s[20:23], 66 ; C2139542 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v19, s39, v18 ; 10262427 S_BUFFER_LOAD_DWORD s44, s[20:23], 16 ; C2161510 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v20, s44, v14, 0, 0, 0, 0 ; D2100014 02021C2C S_BUFFER_LOAD_DWORD s44, s[20:23], 20 ; C2161514 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v20, s44, v13, v20, 0, 0, 0, 0 ; D2820014 04521A2C S_BUFFER_LOAD_DWORD s44, s[20:23], 24 ; C2161518 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v20, s44, v10, v20, 0, 0, 0, 0 ; D2820014 0452142C S_BUFFER_LOAD_DWORD s44, s[20:23], 28 ; C216151C S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v20, s44, v20 ; 0628282C V_MAD_F32 v20, v20, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0 ; D2820014 03C1E114 V_MUL_F32_e32 v18, s39, v20 ; 10242827 IMAGE_SAMPLE v18, 1, -1, 0, 0, 0, 0, 0, 0, v[18:19], s[12:19], s[8:11] ; F0801100 00431212 S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v16, v16, v18 ; 10202510 V_ADD_F32_e64 v16, 0, v16, 0, 1, 0, 0 ; D2060810 02022080 V_MUL_F32_e32 v15, v15, v16 ; 101E210F S_BUFFER_LOAD_DWORD s44, s[20:23], 34 ; C2161522 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v16, s44, v14, 0, 0, 0, 0 ; D2100010 02021C2C S_BUFFER_LOAD_DWORD s44, s[20:23], 38 ; C2161526 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v16, s44, v13, v16, 0, 0, 0, 0 ; D2820010 04421A2C S_BUFFER_LOAD_DWORD s44, s[20:23], 42 ; C216152A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v16, s44, v10, v16, 0, 0, 0, 0 ; D2820010 0442142C S_BUFFER_LOAD_DWORD s44, s[20:23], 46 ; C216152E S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v16, s44, v16 ; 0620202C V_CMP_U_F32_e64 s[44:45], v16, v16, 0, 0, 0, 0 ; D010002C 02022110 V_CMP_GE_F32_e64 s[46:47], v16, -1.000000e+00, 0, 0, 0, 0 ; D00C002E 0201E710 S_OR_B64 s[44:45], s[46:47], s[44:45] ; 88AC2C2E V_CNDMASK_B32_e64 v16, -1.000000e+00, v16, s[44:45], 0, 0, 0, 0 ; D2000010 00B220F3 V_CMP_U_F32_e64 s[44:45], v16, v16, 0, 0, 0, 0 ; D010002C 02022110 V_CMP_GE_F32_e64 s[46:47], v16, 1.000000e+00, 0, 0, 0, 0 ; D00C002E 0201E510 S_OR_B64 s[44:45], s[46:47], s[44:45] ; 88AC2C2E V_CNDMASK_B32_e64 v16, v16, 1.000000e+00, s[44:45], 0, 0, 0, 0 ; D2000010 00B1E510 V_ADD_F32_e32 v16, 1.000000e+00, v16 ; 062020F2 V_MUL_F32_e32 v16, v17, v16 ; 10202111 V_MUL_F32_e32 v16, 7.213475e-01, v16 ; 102020FF 3F38AA3B V_EXP_F32_e32 v16, v16 ; 7E204B10 S_BUFFER_LOAD_DWORD s44, s[20:23], 33 ; C2161521 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v17, s44, v14, 0, 0, 0, 0 ; D2100011 02021C2C S_BUFFER_LOAD_DWORD s44, s[20:23], 37 ; C2161525 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v17, s44, v13, v17, 0, 0, 0, 0 ; D2820011 04461A2C S_BUFFER_LOAD_DWORD s44, s[20:23], 41 ; C2161529 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v17, s44, v10, v17, 0, 0, 0, 0 ; D2820011 0446142C S_BUFFER_LOAD_DWORD s44, s[20:23], 45 ; C216152D S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v17, s44, v17 ; 0622222C V_MAD_F32 v17, v17, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0 ; D2820011 03C1E111 V_MUL_F32_e32 v18, s39, v17 ; 10242227 S_BUFFER_LOAD_DWORD s44, s[20:23], 32 ; C2161520 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v19, s44, v14, 0, 0, 0, 0 ; D2100013 02021C2C S_BUFFER_LOAD_DWORD s44, s[20:23], 36 ; C2161524 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v19, s44, v13, v19, 0, 0, 0, 0 ; D2820013 044E1A2C S_BUFFER_LOAD_DWORD s44, s[20:23], 40 ; C2161528 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v19, s44, v10, v19, 0, 0, 0, 0 ; D2820013 044E142C S_BUFFER_LOAD_DWORD s44, s[20:23], 44 ; C216152C S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v19, s44, v19 ; 0626262C V_MAD_F32 v19, v19, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0 ; D2820013 03C1E113 V_MUL_F32_e32 v17, s39, v19 ; 10222627 IMAGE_SAMPLE v17, 1, -1, 0, 0, 0, 0, 0, 0, v[17:18], s[28:35], s[24:27] ; F0801100 00C71111 S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v16, v16, v17 ; 10202310 V_ADD_F32_e64 v16, 0, v16, 0, 1, 0, 0 ; D2060810 02022080 V_MAD_F32 v20, v12, v16, v15, 0, 0, 0, 0 ; D2820014 043E210C S_OR_SAVEEXEC_B64 s[42:43], s[42:43] ; BEAA252A S_XOR_B64 exec, exec, s[42:43] ; 89FE2A7E S_CBRANCH_EXECZ BB0_18 ; BF880000 V_MOV_B32_e32 v12, s6 ; 7E180206 V_SUB_F32_e64 v12, v13, v12, 0, 0, 0, 0 ; D208000C 0202190D V_MOV_B32_e32 v15, s7 ; 7E1E0207 V_SUB_F32_e64 v15, v14, v15, 0, 0, 0, 0 ; D208000F 02021F0E V_MUL_F32_e32 v15, v15, v15 ; 101E1F0F V_MAD_F32 v12, v12, v12, v15, 0, 0, 0, 0 ; D282000C 043E190C V_MOV_B32_e32 v15, s36 ; 7E1E0224 V_SUB_F32_e64 v15, v10, v15, 0, 0, 0, 0 ; D208000F 02021F0A V_MAD_F32 v12, v15, v15, v12, 0, 0, 0, 0 ; D282000C 04321F0F V_RSQ_LEGACY_F32_e32 v15, v12 ; 7E1E5B0C V_MUL_F32_e32 v15, v15, v12 ; 101E190F V_XOR_B32_e32 v12, -2147483648, v12 ; 3A1818FF 80000000 V_CMP_GT_F32_e64 s[6:7], 0, v12, 0, 0, 0, 0 ; D0080006 02021880 V_CNDMASK_B32_e64 v12, 0.000000e+00, v15, s[6:7], 0, 0, 0, 0 ; D200000C 001A1E80 S_BUFFER_LOAD_DWORD s6, s[20:23], 65 ; C2031541 S_WAITCNT lgkmcnt(0) ; BF8C007F V_RCP_F32_e32 v15, s6 ; 7E1E5406 V_MOV_B32_e32 v16, -8.000000e-01 ; 7E2002FF BF4CCCCD V_MAD_F32 v12, v12, v15, v16, 0, 0, 0, 0 ; D282000C 04421F0C V_MUL_F32_e32 v12, 5.000000e+00, v12 ; 101818FF 40A00001 V_ADD_F32_e64 v12, 0, v12, 0, 1, 0, 0 ; D206080C 02021880 V_ADD_F32_e32 v15, v12, v12 ; 061E190C V_SUB_F32_e32 v15, 3.000000e+00, v15 ; 081E1EFF 40400000 V_MUL_F32_e32 v15, v12, v15 ; 101E1F0C V_MUL_F32_e32 v16, v12, v15 ; 10201F0C V_SUB_F32_e32 v16, 1.000000e+00, v16 ; 082020F2 S_BUFFER_LOAD_DWORD s6, s[20:23], 34 ; C2031522 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v17, s6, v14, 0, 0, 0, 0 ; D2100011 02021C06 S_BUFFER_LOAD_DWORD s6, s[20:23], 38 ; C2031526 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v17, s6, v13, v17, 0, 0, 0, 0 ; D2820011 04461A06 S_BUFFER_LOAD_DWORD s6, s[20:23], 42 ; C203152A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v17, s6, v10, v17, 0, 0, 0, 0 ; D2820011 04461406 S_BUFFER_LOAD_DWORD s6, s[20:23], 46 ; C203152E S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v17, s6, v17 ; 06222206 V_CMP_U_F32_e64 s[6:7], v17, v17, 0, 0, 0, 0 ; D0100006 02022311 V_CMP_GE_F32_e64 s[44:45], v17, -1.000000e+00, 0, 0, 0, 0 ; D00C002C 0201E711 S_OR_B64 s[6:7], s[44:45], s[6:7] ; 8886062C V_CNDMASK_B32_e64 v17, -1.000000e+00, v17, s[6:7], 0, 0, 0, 0 ; D2000011 001A22F3 V_CMP_U_F32_e64 s[6:7], v17, v17, 0, 0, 0, 0 ; D0100006 02022311 V_CMP_GE_F32_e64 s[44:45], v17, 1.000000e+00, 0, 0, 0, 0 ; D00C002C 0201E511 S_OR_B64 s[6:7], s[44:45], s[6:7] ; 8886062C V_CNDMASK_B32_e64 v17, v17, 1.000000e+00, s[6:7], 0, 0, 0, 0 ; D2000011 0019E511 V_ADD_F32_e32 v17, 1.000000e+00, v17 ; 062222F2 S_BUFFER_LOAD_DWORD s6, s[20:23], 63 ; C203153F S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v17, s6, v17 ; 10222206 V_MUL_F32_e32 v17, -7.213475e-01, v17 ; 102222FF BF38AA3B V_EXP_F32_e32 v17, v17 ; 7E224B11 S_BUFFER_LOAD_DWORD s6, s[20:23], 33 ; C2031521 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v18, s6, v14, 0, 0, 0, 0 ; D2100012 02021C06 S_BUFFER_LOAD_DWORD s6, s[20:23], 37 ; C2031525 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v18, s6, v13, v18, 0, 0, 0, 0 ; D2820012 044A1A06 S_BUFFER_LOAD_DWORD s6, s[20:23], 41 ; C2031529 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v18, s6, v10, v18, 0, 0, 0, 0 ; D2820012 044A1406 S_BUFFER_LOAD_DWORD s6, s[20:23], 45 ; C203152D S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v18, s6, v18 ; 06242406 V_MAD_F32 v18, v18, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0 ; D2820012 03C1E112 S_BUFFER_LOAD_DWORD s6, s[20:23], 66 ; C2031542 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v19, s6, v18 ; 10262406 S_BUFFER_LOAD_DWORD s7, s[20:23], 32 ; C2039520 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v20, s7, v14, 0, 0, 0, 0 ; D2100014 02021C07 S_BUFFER_LOAD_DWORD s7, s[20:23], 36 ; C2039524 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v20, s7, v13, v20, 0, 0, 0, 0 ; D2820014 04521A07 S_BUFFER_LOAD_DWORD s7, s[20:23], 40 ; C2039528 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v20, s7, v10, v20, 0, 0, 0, 0 ; D2820014 04521407 S_BUFFER_LOAD_DWORD s7, s[20:23], 44 ; C203952C S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v20, s7, v20 ; 06282807 V_MAD_F32 v20, v20, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0 ; D2820014 03C1E114 V_MUL_F32_e32 v18, s6, v20 ; 10242806 IMAGE_SAMPLE v18, 1, -1, 0, 0, 0, 0, 0, 0, v[18:19], s[28:35], s[24:27] ; F0801100 00C71212 S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v17, v17, v18 ; 10222511 V_ADD_F32_e64 v17, 0, v17, 0, 1, 0, 0 ; D2060811 02022280 V_MUL_F32_e32 v16, v16, v17 ; 10202310 V_MAD_F32 v20, v12, v15, v16, 0, 0, 0, 0 ; D2820014 04421F0C S_OR_B64 exec, exec, s[42:43] ; 88FE2A7E S_OR_SAVEEXEC_B64 s[40:41], s[40:41] ; BEA82528 V_MOV_B32_e32 v17, s52 ; 7E220234 V_MOV_B32_e32 v18, s53 ; 7E240235 V_MOV_B32_e32 v19, s54 ; 7E260236 V_MOV_B32_e32 v12, s55 ; 7E180237 V_MOV_B32_e32 v15, s56 ; 7E1E0238 V_MOV_B32_e32 v16, s57 ; 7E200239 S_XOR_B64 exec, exec, s[40:41] ; 89FE287E S_CBRANCH_EXECZ BB0_19 ; BF880000 S_BUFFER_LOAD_DWORD s6, s[20:23], 18 ; C2031512 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v20, s6, v14, 0, 0, 0, 0 ; D2100014 02021C06 S_BUFFER_LOAD_DWORD s6, s[20:23], 22 ; C2031516 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v20, s6, v13, v20, 0, 0, 0, 0 ; D2820014 04521A06 S_BUFFER_LOAD_DWORD s6, s[20:23], 26 ; C203151A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v20, s6, v10, v20, 0, 0, 0, 0 ; D2820014 04521406 S_BUFFER_LOAD_DWORD s6, s[20:23], 30 ; C203151E S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v20, s6, v20 ; 06282806 V_CMP_U_F32_e64 s[6:7], v20, v20, 0, 0, 0, 0 ; D0100006 02022914 V_CMP_GE_F32_e64 s[24:25], v20, -1.000000e+00, 0, 0, 0, 0 ; D00C0018 0201E714 S_OR_B64 s[6:7], s[24:25], s[6:7] ; 88860618 V_CNDMASK_B32_e64 v20, -1.000000e+00, v20, s[6:7], 0, 0, 0, 0 ; D2000014 001A28F3 V_CMP_U_F32_e64 s[6:7], v20, v20, 0, 0, 0, 0 ; D0100006 02022914 V_CMP_GE_F32_e64 s[24:25], v20, 1.000000e+00, 0, 0, 0, 0 ; D00C0018 0201E514 S_OR_B64 s[6:7], s[24:25], s[6:7] ; 88860618 V_CNDMASK_B32_e64 v20, v20, 1.000000e+00, s[6:7], 0, 0, 0, 0 ; D2000014 0019E514 V_ADD_F32_e32 v20, 1.000000e+00, v20 ; 062828F2 S_BUFFER_LOAD_DWORD s6, s[20:23], 63 ; C203153F S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v20, s6, v20 ; 10282806 V_MUL_F32_e32 v20, -7.213475e-01, v20 ; 102828FF BF38AA3B V_EXP_F32_e32 v20, v20 ; 7E284B14 S_BUFFER_LOAD_DWORD s6, s[20:23], 17 ; C2031511 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v21, s6, v14, 0, 0, 0, 0 ; D2100015 02021C06 S_BUFFER_LOAD_DWORD s6, s[20:23], 21 ; C2031515 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v21, s6, v13, v21, 0, 0, 0, 0 ; D2820015 04561A06 S_BUFFER_LOAD_DWORD s6, s[20:23], 25 ; C2031519 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v21, s6, v10, v21, 0, 0, 0, 0 ; D2820015 04561406 S_BUFFER_LOAD_DWORD s6, s[20:23], 29 ; C203151D S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v21, s6, v21 ; 062A2A06 V_MAD_F32 v21, v21, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0 ; D2820015 03C1E115 S_BUFFER_LOAD_DWORD s6, s[20:23], 66 ; C2031542 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v22, s6, v21 ; 102C2A06 S_BUFFER_LOAD_DWORD s7, s[20:23], 16 ; C2039510 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e64 v23, s7, v14, 0, 0, 0, 0 ; D2100017 02021C07 S_BUFFER_LOAD_DWORD s7, s[20:23], 20 ; C2039514 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v23, s7, v13, v23, 0, 0, 0, 0 ; D2820017 045E1A07 S_BUFFER_LOAD_DWORD s7, s[20:23], 24 ; C2039518 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v23, s7, v10, v23, 0, 0, 0, 0 ; D2820017 045E1407 S_BUFFER_LOAD_DWORD s7, s[20:23], 28 ; C203951C S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v23, s7, v23 ; 062E2E07 V_MAD_F32 v23, v23, 5.000000e-01, 5.000000e-01, 0, 0, 0, 0 ; D2820017 03C1E117 V_MUL_F32_e32 v21, s6, v23 ; 102A2E06 IMAGE_SAMPLE v21, 1, -1, 0, 0, 0, 0, 0, 0, v[21:22], s[12:19], s[8:11] ; F0801100 00431515 S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v20, v20, v21 ; 10282B14 V_ADD_F32_e64 v20, 0, v20, 0, 1, 0, 0 ; D2060814 02022880 S_OR_B64 exec, exec, s[40:41] ; 88FE287E V_MUL_F32_e64 v19, v2, v19, 0, 0, 0, 0 ; D2100013 02022702 V_MUL_F32_e64 v18, v3, v18, 0, 0, 0, 0 ; D2100012 02022503 V_SUB_F32_e32 v18, v18, v19 ; 08242712 V_MUL_F32_e64 v17, v1, v17, 0, 0, 0, 0 ; D2100011 02022301 V_SUB_F32_e32 v17, v18, v17 ; 08222312 V_CMP_U_F32_e64 s[6:7], v17, v17, 0, 0, 0, 0 ; D0100006 02022311 V_CMP_LE_F32_e64 s[8:9], v17, 0.000000e+00, 0, 0, 0, 0 ; D0060008 02010111 S_OR_B64 s[6:7], s[8:9], s[6:7] ; 88860608 V_CNDMASK_B32_e64 v17, v17, 0.000000e+00, s[6:7], 0, 0, 0, 0 ; D2000011 00190111 V_MUL_F32_e32 v18, s38, v17 ; 10242226 V_MUL_F32_e32 v18, v5, v18 ; 10242505 V_MOV_B32_e32 v19, -8.000000e-01 ; 7E2602FF BF4CCCCD V_ADD_F32_e32 v19, v20, v19 ; 06262714 V_MUL_F32_e32 v19, 5.000000e+00, v19 ; 102626FF 40A00001 V_ADD_F32_e64 v19, 0, v19, 0, 1, 0, 0 ; D2060813 02022680 V_ADD_F32_e32 v20, v19, v19 ; 06282713 V_SUB_F32_e32 v20, 3.000000e+00, v20 ; 082828FF 40400000 V_MUL_F32_e32 v20, v19, v20 ; 10282913 V_MUL_F32_e32 v19, v19, v20 ; 10262913 V_MUL_F32_e32 v18, v18, v19 ; 10242712 V_MUL_F32_e64 v12, v11, v12, 0, 0, 0, 0 ; D210000C 0202190B V_MAD_F32 v12, v5, v12, v18, 0, 0, 0, 0 ; D282000C 044A1905 V_MUL_F32_e32 v18, s37, v17 ; 10242225 V_MUL_F32_e32 v18, v6, v18 ; 10242506 V_MUL_F32_e32 v18, v18, v19 ; 10242712 V_MUL_F32_e64 v15, v11, v15, 0, 0, 0, 0 ; D210000F 02021F0B V_MAD_F32 v15, v6, v15, v18, 0, 0, 0, 0 ; D282000F 044A1F06 V_MUL_F32_e32 v17, s5, v17 ; 10222205 V_MUL_F32_e32 v17, v8, v17 ; 10222308 V_MUL_F32_e32 v17, v17, v19 ; 10222711 V_MUL_F32_e64 v11, v11, v16, 0, 0, 0, 0 ; D210000B 0202210B V_MAD_F32 v11, v8, v11, v17, 0, 0, 0, 0 ; D282000B 04461708 V_MOV_B32_e32 v16, -2147483648 ; 7E2002FF 80000000 V_XOR_B32_e32 v10, v10, v16 ; 3A14210A V_XOR_B32_e32 v13, v13, v16 ; 3A1A210D V_XOR_B32_e32 v14, v14, v16 ; 3A1C210E V_XOR_B32_e32 v1, v1, v16 ; 3A022101 V_XOR_B32_e32 v2, v2, v16 ; 3A042102 V_MOV_B32_e32 v16, 0.000000e+00 ; 7E200280 S_MOV_B64 s[6:7], 0 ; BE860480 V_MOV_B32_e32 v17, s4 ; 7E220204 V_CMP_GE_I32_e64 s[4:5], v16, v17, 0, 0, 0, 0 ; D10C0004 02022310 V_CNDMASK_B32_e64 v18, 0, -1, s[4:5], 0, 0, 0, 0 ; D2000012 00118280 V_CMP_EQ_I32_e64 s[4:5], v18, 0, 0, 0, 0, 0 ; D1040004 02010112 S_AND_SAVEEXEC_B64 s[4:5], s[4:5] ; BE842404 S_XOR_B64 s[4:5], exec, s[4:5] ; 8984047E S_CBRANCH_EXECZ BB0_24 ; BF880000 V_MUL_LO_I32 v18, 7, v16, 0, 0, 0, 0, 0 ; D2D60012 02022087 V_LSHLREV_B32_e32 v18, 4, v18 ; 34242484 V_ADD_I32_e32 v19, 80, v18 ; 4A2624FF 00000050 BUFFER_LOAD_DWORD v19, s[0:3] + v19 + 0, glc=0, slc=0, tfe=0 ; E0301000 80001313 S_WAITCNT vmcnt(0) expcnt(0) ; BF8C0700 V_ADD_F32_e32 v19, v13, v19 ; 0626270D V_ADD_I32_e32 v20, 64, v18 ; 4A2824C0 BUFFER_LOAD_DWORD v20, s[0:3] + v20 + 0, glc=0, slc=0, tfe=0 ; E0301000 80001414 S_WAITCNT vmcnt(0) ; BF8C0770 V_ADD_F32_e32 v20, v14, v20 ; 0628290E V_MUL_F32_e32 v21, v20, v20 ; 102A2914 V_MAD_F32 v21, v19, v19, v21, 0, 0, 0, 0 ; D2820015 04562713 V_ADD_I32_e32 v22, 96, v18 ; 4A2C24FF 00000060 BUFFER_LOAD_DWORD v22, s[0:3] + v22 + 0, glc=0, slc=0, tfe=0 ; E0301000 80001616 S_WAITCNT vmcnt(0) ; BF8C0770 V_ADD_F32_e32 v22, v10, v22 ; 062C2D0A V_MAD_F32 v21, v22, v22, v21, 0, 0, 0, 0 ; D2820015 04562D16 V_RSQ_LEGACY_F32_e32 v23, v21 ; 7E2E5B15 V_MUL_F32_e32 v23, v23, v21 ; 102E2B17 V_XOR_B32_e32 v21, -2147483648, v21 ; 3A2A2AFF 80000000 V_CMP_GT_F32_e64 s[8:9], 0, v21, 0, 0, 0, 0 ; D0080008 02022A80 V_CNDMASK_B32_e64 v21, 0.000000e+00, v23, s[8:9], 0, 0, 0, 0 ; D2000015 00222E80 V_RCP_F32_e32 v23, v21 ; 7E2E5515 V_MUL_F32_e32 v19, v19, v23 ; 10262F13 V_MUL_F32_e32 v20, v20, v23 ; 10282F14 V_MUL_F32_e32 v20, v2, v20 ; 10282902 V_MAD_F32 v19, v3, v19, v20, 0, 0, 0, 0 ; D2820013 04522703 V_MUL_F32_e32 v20, v22, v23 ; 10282F16 V_MAD_F32 v19, v1, v20, v19, 0, 0, 0, 0 ; D2820013 044E2901 V_CMP_U_F32_e64 s[8:9], v19, v19, 0, 0, 0, 0 ; D0100008 02022713 V_CMP_LE_F32_e64 s[10:11], v19, 0.000000e+00, 0, 0, 0, 0 ; D006000A 02010113 S_OR_B64 s[8:9], s[10:11], s[8:9] ; 8888080A V_CNDMASK_B32_e64 v19, v19, 0.000000e+00, s[8:9], 0, 0, 0, 0 ; D2000013 00210113 V_ADD_I32_e32 v20, 144, v18 ; 4A2824FF 00000090 BUFFER_LOAD_DWORD v20, s[0:3] + v20 + 0, glc=0, slc=0, tfe=0 ; E0301000 80001414 S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v20, v19, v20 ; 10282913 V_MUL_F32_e32 v20, v5, v20 ; 10282905 V_ADD_I32_e32 v22, 160, v18 ; 4A2C24FF 000000A0 BUFFER_LOAD_DWORD v22, s[0:3] + v22 + 0, glc=0, slc=0, tfe=0 ; E0301000 80001616 S_WAITCNT vmcnt(0) ; BF8C0770 V_MAD_F32 v21, v22, -5.000000e-01, v21, 0, 0, 0, 0 ; D2820015 0455E316 V_MAD_F32 v22, v22, -5.000000e-01, v22, 0, 0, 0, 0 ; D2820016 0459E316 V_RCP_F32_e32 v22, v22 ; 7E2C5516 V_MUL_F32_e32 v21, v21, v22 ; 102A2D15 V_ADD_F32_e64 v21, 0, v21, 0, 1, 0, 0 ; D2060815 02022A80 V_ADD_F32_e32 v22, v21, v21 ; 062C2B15 V_SUB_F32_e32 v22, 3.000000e+00, v22 ; 082C2CFF 40400000 V_MUL_F32_e32 v22, v21, v22 ; 102C2D15 V_MUL_F32_e32 v21, v21, v22 ; 102A2D15 V_SUB_F32_e32 v21, 1.000000e+00, v21 ; 082A2AF2 V_MAD_F32 v12, v20, v21, v12, 0, 0, 0, 0 ; D282000C 04322B14 V_ADD_I32_e32 v20, 128, v18 ; 4A2824FF 00000080 BUFFER_LOAD_DWORD v20, s[0:3] + v20 + 0, glc=0, slc=0, tfe=0 ; E0301000 80001414 S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v20, v19, v20 ; 10282913 V_MUL_F32_e32 v20, v6, v20 ; 10282906 V_MAD_F32 v15, v20, v21, v15, 0, 0, 0, 0 ; D282000F 043E2B14 V_ADD_I32_e32 v18, 112, v18 ; 4A2424FF 00000070 BUFFER_LOAD_DWORD v18, s[0:3] + v18 + 0, glc=0, slc=0, tfe=0 ; E0301000 80001212 S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v18, v19, v18 ; 10242513 V_MUL_F32_e32 v18, v8, v18 ; 10242508 V_MAD_F32 v11, v18, v21, v11, 0, 0, 0, 0 ; D282000B 042E2B12 V_CMP_NE_I32_e64 s[8:9], v0, 0, 0, 0, 0, 0 ; D10A0008 02010100 S_OR_B64 s[6:7], s[8:9], s[6:7] ; 88860608 V_ADD_I32_e32 v16, 1, v16 ; 4A202081 S_OR_B64 exec, exec, s[4:5] ; 88FE047E S_OR_B64 s[6:7], s[4:5], s[6:7] ; 88860604 S_ANDN2_B64 exec, exec, s[6:7] ; 8AFE067E S_CBRANCH_EXECNZ BB0_23 ; BF890000 S_OR_B64 exec, exec, s[6:7] ; 88FE067E V_ADD_F32_e64 v0, v7, v15, 0, 0, 0, 0 ; D2060000 02021F07 V_ADD_F32_e64 v1, v9, v11, 0, 0, 0, 0 ; D2060001 02021709 V_CVT_PKRTZ_F16_F32_e32 v0, v1, v0 ; 5E000101 V_ADD_F32_e64 v1, v4, v12, 0, 0, 0, 0 ; D2060001 02021904 V_CVT_PKRTZ_F16_F32_e64 v1, v1, 0.000000e+00, 0, 0, 0, 0 ; D25E0001 02010101 EXP 15, 0, 1, 1, 1, v0, v1, v0, v1 ; F8001C0F 01000100 S_ENDPGM ; BF810000 VERT DCL IN[0] DCL IN[1] DCL IN[2] DCL IN[3] DCL IN[4] DCL IN[5] DCL IN[6] DCL OUT[0], POSITION DCL OUT[1], GENERIC[20] DCL OUT[2], GENERIC[21] DCL OUT[3], GENERIC[22] DCL CONST[0..4] DCL CONST[1][0..96] DCL CONST[2][0..68] DCL TEMP[0..8], LOCAL DCL ADDR[0] IMM[0] FLT32 { 0.0000, 0.8000, 1.0000, 3.0000} IMM[1] UINT32 {0, 320, 368, 176} IMM[2] INT32 {20, 23, 11, 10} IMM[3] FLT32 { 2.0000, 0.1000, 0.0000, 0.0000} IMM[4] UINT32 {160, 144, 128, 48} IMM[5] INT32 {9, 8, 3, 2} IMM[6] UINT32 {32, 16, 0, 0} IMM[7] INT32 {1, 0, 0, 0} 0: DP3 TEMP[0].x, IN[5].xyzz, IN[5].xyzz 1: RSQ TEMP[1].x, TEMP[0].xxxx 2: MUL TEMP[1].x, TEMP[1].xxxx, TEMP[0].xxxx 3: CMP TEMP[0].x, -TEMP[0].xxxx, TEMP[1].xxxx, IMM[0].xxxx 4: MUL TEMP[1].xyz, IN[4].zxyy, IN[5].yzxx 5: MAD TEMP[1].xyz, IN[4].yzxx, IN[5].zxyy, -TEMP[1].xyzz 6: DP3 TEMP[2].x, TEMP[1].xyzz, TEMP[1].xyzz 7: RSQ TEMP[2].x, TEMP[2].xxxx 8: MUL TEMP[1].xyz, TEMP[1].xyzz, TEMP[2].xxxx 9: MUL TEMP[2].xyz, TEMP[1].zxyy, IN[4].yzxx 10: MAD TEMP[2].xyz, TEMP[1].yzxx, IN[4].zxyy, -TEMP[2].xyzz 11: DP3 TEMP[3].x, TEMP[2].xyzz, TEMP[2].xyzz 12: RSQ TEMP[3].x, TEMP[3].xxxx 13: MUL TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xxxx 14: DP3 TEMP[3].x, IN[4].xyzz, IN[4].xyzz 15: RSQ TEMP[3].x, TEMP[3].xxxx 16: MUL TEMP[3].xyz, IN[4].xyzz, TEMP[3].xxxx 17: MUL TEMP[4].xyz, TEMP[1].xyzz, TEMP[0].xxxx 18: MUL TEMP[0].xyz, TEMP[2].xyzz, TEMP[0].xxxx 19: MUL TEMP[5].xyz, CONST[0].xyzz, TEMP[2].xxxx 20: MAD TEMP[5].xyz, CONST[1].xyzz, TEMP[2].yyyy, TEMP[5].xyzz 21: MAD TEMP[2].xyz, CONST[2].xyzz, TEMP[2].zzzz, TEMP[5].xyzz 22: MUL TEMP[5].xyz, CONST[0].xyzz, TEMP[3].xxxx 23: MAD TEMP[5].xyz, CONST[1].xyzz, TEMP[3].yyyy, TEMP[5].xyzz 24: MAD TEMP[3].xyz, CONST[2].xyzz, TEMP[3].zzzz, TEMP[5].xyzz 25: MUL TEMP[5].xyz, CONST[0].xyzz, TEMP[1].xxxx 26: MAD TEMP[5].xyz, CONST[1].xyzz, TEMP[1].yyyy, TEMP[5].xyzz 27: MAD TEMP[1].xyz, CONST[2].xyzz, TEMP[1].zzzz, TEMP[5].xyzz 28: MUL TEMP[1].xyz, TEMP[1].xyzz, IN[2].xxxx 29: MAD TEMP[1].xyz, TEMP[3].xyzz, IN[2].yyyy, TEMP[1].xyzz 30: MAD TEMP[1].xyz, TEMP[2].xyzz, IN[2].zzzz, TEMP[1].xyzz 31: UARL ADDR[0].x, IMM[2].xxxx 32: MOV TEMP[2].xyz, CONST[1][ADDR[0].x].xyzz 33: ADD TEMP[2].xyz, IN[3].xyzz, -TEMP[2].xyzz 34: MUL TEMP[3].x, CONST[4].xxxx, IMM[0].yyyy 35: DP3 TEMP[2].x, TEMP[2].xyzz, TEMP[2].xyzz 36: RSQ TEMP[5].x, TEMP[2].xxxx 37: MUL TEMP[5].x, TEMP[5].xxxx, TEMP[2].xxxx 38: CMP TEMP[5].x, -TEMP[2].xxxx, TEMP[5].xxxx, IMM[0].xxxx 39: ADD TEMP[2].x, TEMP[5].xxxx, -TEMP[3].xxxx 40: ADD TEMP[3].x, CONST[4].xxxx, -TEMP[3].xxxx 41: RCP TEMP[3].x, TEMP[3].xxxx 42: MUL_SAT TEMP[2].x, TEMP[2].xxxx, TEMP[3].xxxx 43: MUL TEMP[3].x, IMM[3].xxxx, TEMP[2].xxxx 44: ADD TEMP[3].x, IMM[0].wwww, -TEMP[3].xxxx 45: MUL TEMP[3].x, TEMP[2].xxxx, TEMP[3].xxxx 46: MUL TEMP[3].x, TEMP[2].xxxx, TEMP[3].xxxx 47: ADD TEMP[3].x, IMM[0].zzzz, -TEMP[3].xxxx 48: MUL TEMP[2].xyz, IN[0].xyzz, TEMP[3].xxxx 49: MUL TEMP[3], CONST[0], TEMP[0].xxxx 50: MAD TEMP[3], CONST[1], TEMP[0].yyyy, TEMP[3] 51: MAD TEMP[0], CONST[2], TEMP[0].zzzz, TEMP[3] 52: MUL TEMP[3], CONST[0], IN[4].xxxx 53: MAD TEMP[3], CONST[1], IN[4].yyyy, TEMP[3] 54: MAD TEMP[3], CONST[2], IN[4].zzzz, TEMP[3] 55: MUL TEMP[5], CONST[0], TEMP[4].xxxx 56: MAD TEMP[5], CONST[1], TEMP[4].yyyy, TEMP[5] 57: MAD TEMP[4], CONST[2], TEMP[4].zzzz, TEMP[5] 58: MUL TEMP[4], TEMP[4], TEMP[2].xxxx 59: MAD TEMP[3], TEMP[3], TEMP[2].yyyy, TEMP[4] 60: MAD TEMP[0], TEMP[0], TEMP[2].zzzz, TEMP[3] 61: MUL TEMP[2], CONST[0], IN[3].xxxx 62: MAD TEMP[2], CONST[1], IN[3].yyyy, TEMP[2] 63: MAD TEMP[2], CONST[2], IN[3].zzzz, TEMP[2] 64: ADD TEMP[2], TEMP[2], CONST[3] 65: ADD TEMP[0], TEMP[0], TEMP[2] 66: UARL ADDR[0].x, IMM[2].yyyy 67: MOV TEMP[3].x, CONST[1][ADDR[0].x].xxxx 68: ADD TEMP[3].x, TEMP[3].xxxx, IN[3].xxxx 69: ADD TEMP[3].x, TEMP[3].xxxx, IN[3].yyyy 70: ADD TEMP[3].x, TEMP[3].xxxx, IN[3].zzzz 71: COS TEMP[3].x, TEMP[3].xxxx 72: MOV TEMP[4].y, IMM[0].xxxx 73: ADD TEMP[5].x, IN[3].xxxx, IN[3].zzzz 74: COS TEMP[5].x, TEMP[5].xxxx 75: MUL TEMP[4].x, TEMP[3].xxxx, TEMP[5].xxxx 76: ADD TEMP[5].x, IN[3].yyyy, IN[3].zzzz 77: COS TEMP[5].x, TEMP[5].xxxx 78: MUL TEMP[3].x, TEMP[3].xxxx, TEMP[5].xxxx 79: MOV TEMP[4].z, TEMP[3].xxxx 80: MAX TEMP[3].x, IMM[0].xxxx, IN[0].yyyy 81: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[3].xxxx 82: MAD TEMP[2].xyz, TEMP[3].xyzz, IMM[3].yyyy, TEMP[0].xyzz 83: UARL ADDR[0].x, IMM[2].zzzz 84: MOV TEMP[3], CONST[1][ADDR[0].x] 85: UARL ADDR[0].x, IMM[2].wwww 86: MOV TEMP[4], CONST[1][ADDR[0].x] 87: UARL ADDR[0].x, IMM[5].xxxx 88: MOV TEMP[5], CONST[1][ADDR[0].x] 89: UARL ADDR[0].x, IMM[5].yyyy 90: MOV TEMP[6], CONST[1][ADDR[0].x] 91: MUL TEMP[6], TEMP[6], TEMP[2].xxxx 92: MAD TEMP[5], TEMP[5], TEMP[2].yyyy, TEMP[6] 93: MAD TEMP[4], TEMP[4], TEMP[2].zzzz, TEMP[5] 94: MAD TEMP[3], TEMP[3], TEMP[0].wwww, TEMP[4] 95: MOV TEMP[4].zw, TEMP[1].yyxy 96: MOV TEMP[1].x, TEMP[1].zzzz 97: MOV TEMP[1].yzw, IN[6].yxyz 98: UARL ADDR[0].x, IMM[5].zzzz 99: MOV TEMP[5], CONST[1][ADDR[0].x] 100: UARL ADDR[0].x, IMM[5].wwww 101: MOV TEMP[6], CONST[1][ADDR[0].x] 102: UARL ADDR[0].x, IMM[7].xxxx 103: MOV TEMP[7], CONST[1][ADDR[0].x] 104: UARL ADDR[0].x, IMM[7].yyyy 105: MOV TEMP[8], CONST[1][ADDR[0].x] 106: MUL TEMP[8], TEMP[8], TEMP[2].xxxx 107: MAD TEMP[7], TEMP[7], TEMP[2].yyyy, TEMP[8] 108: MAD TEMP[2], TEMP[6], TEMP[2].zzzz, TEMP[7] 109: MAD TEMP[0].xyz, TEMP[5], TEMP[0].wwww, TEMP[2] 110: MOV TEMP[0].xyz, TEMP[0].xyzx 111: MOV TEMP[4].xy, IN[1].xyxx 112: MOV OUT[3], TEMP[0] 113: MOV OUT[0], TEMP[3] 114: MOV OUT[2], TEMP[1] 115: MOV OUT[1], TEMP[4] 116: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0 %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0 %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0) %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4) %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8) %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12) %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16) %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20) %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24) %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28) %20 = call float @llvm.SI.load.const(<16 x i8> %11, i32 32) %21 = call float @llvm.SI.load.const(<16 x i8> %11, i32 36) %22 = call float @llvm.SI.load.const(<16 x i8> %11, i32 40) %23 = call float @llvm.SI.load.const(<16 x i8> %11, i32 44) %24 = call float @llvm.SI.load.const(<16 x i8> %11, i32 48) %25 = call float @llvm.SI.load.const(<16 x i8> %11, i32 52) %26 = call float @llvm.SI.load.const(<16 x i8> %11, i32 56) %27 = call float @llvm.SI.load.const(<16 x i8> %11, i32 60) %28 = call float @llvm.SI.load.const(<16 x i8> %11, i32 64) %29 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 1 %30 = load <16 x i8> addrspace(2)* %29, !tbaa !0 %31 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 0 %32 = load <16 x i8> addrspace(2)* %31, !tbaa !0 %33 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %32, i32 0, i32 %6) %34 = extractelement <4 x float> %33, i32 0 %35 = extractelement <4 x float> %33, i32 1 %36 = extractelement <4 x float> %33, i32 2 %37 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 1 %38 = load <16 x i8> addrspace(2)* %37, !tbaa !0 %39 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %38, i32 0, i32 %6) %40 = extractelement <4 x float> %39, i32 0 %41 = extractelement <4 x float> %39, i32 1 %42 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 2 %43 = load <16 x i8> addrspace(2)* %42, !tbaa !0 %44 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %43, i32 0, i32 %6) %45 = extractelement <4 x float> %44, i32 0 %46 = extractelement <4 x float> %44, i32 1 %47 = extractelement <4 x float> %44, i32 2 %48 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 3 %49 = load <16 x i8> addrspace(2)* %48, !tbaa !0 %50 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %49, i32 0, i32 %6) %51 = extractelement <4 x float> %50, i32 0 %52 = extractelement <4 x float> %50, i32 1 %53 = extractelement <4 x float> %50, i32 2 %54 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 4 %55 = load <16 x i8> addrspace(2)* %54, !tbaa !0 %56 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %55, i32 0, i32 %6) %57 = extractelement <4 x float> %56, i32 0 %58 = extractelement <4 x float> %56, i32 1 %59 = extractelement <4 x float> %56, i32 2 %60 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 5 %61 = load <16 x i8> addrspace(2)* %60, !tbaa !0 %62 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %61, i32 0, i32 %6) %63 = extractelement <4 x float> %62, i32 0 %64 = extractelement <4 x float> %62, i32 1 %65 = extractelement <4 x float> %62, i32 2 %66 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 6 %67 = load <16 x i8> addrspace(2)* %66, !tbaa !0 %68 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %67, i32 0, i32 %6) %69 = extractelement <4 x float> %68, i32 0 %70 = extractelement <4 x float> %68, i32 1 %71 = extractelement <4 x float> %68, i32 2 %72 = fmul float %63, %63 %73 = fmul float %64, %64 %74 = fadd float %73, %72 %75 = fmul float %65, %65 %76 = fadd float %74, %75 %77 = call float @llvm.AMDGPU.rsq(float %76) %78 = fmul float %77, %76 %79 = fsub float -0.000000e+00, %76 %80 = call float @llvm.AMDGPU.cndlt(float %79, float %78, float 0.000000e+00) %81 = fmul float %59, %64 %82 = fmul float %57, %65 %83 = fmul float %58, %63 %84 = fsub float -0.000000e+00, %81 %85 = fmul float %58, %65 %86 = fadd float %85, %84 %87 = fsub float -0.000000e+00, %82 %88 = fmul float %59, %63 %89 = fadd float %88, %87 %90 = fsub float -0.000000e+00, %83 %91 = fmul float %57, %64 %92 = fadd float %91, %90 %93 = fmul float %86, %86 %94 = fmul float %89, %89 %95 = fadd float %94, %93 %96 = fmul float %92, %92 %97 = fadd float %95, %96 %98 = call float @llvm.AMDGPU.rsq(float %97) %99 = fmul float %86, %98 %100 = fmul float %89, %98 %101 = fmul float %92, %98 %102 = fmul float %101, %58 %103 = fmul float %99, %59 %104 = fmul float %100, %57 %105 = fsub float -0.000000e+00, %102 %106 = fmul float %100, %59 %107 = fadd float %106, %105 %108 = fsub float -0.000000e+00, %103 %109 = fmul float %101, %57 %110 = fadd float %109, %108 %111 = fsub float -0.000000e+00, %104 %112 = fmul float %99, %58 %113 = fadd float %112, %111 %114 = fmul float %107, %107 %115 = fmul float %110, %110 %116 = fadd float %115, %114 %117 = fmul float %113, %113 %118 = fadd float %116, %117 %119 = call float @llvm.AMDGPU.rsq(float %118) %120 = fmul float %107, %119 %121 = fmul float %110, %119 %122 = fmul float %113, %119 %123 = fmul float %57, %57 %124 = fmul float %58, %58 %125 = fadd float %124, %123 %126 = fmul float %59, %59 %127 = fadd float %125, %126 %128 = call float @llvm.AMDGPU.rsq(float %127) %129 = fmul float %57, %128 %130 = fmul float %58, %128 %131 = fmul float %59, %128 %132 = fmul float %99, %80 %133 = fmul float %100, %80 %134 = fmul float %101, %80 %135 = fmul float %120, %80 %136 = fmul float %121, %80 %137 = fmul float %122, %80 %138 = fmul float %12, %120 %139 = fmul float %13, %120 %140 = fmul float %14, %120 %141 = fmul float %16, %121 %142 = fadd float %141, %138 %143 = fmul float %17, %121 %144 = fadd float %143, %139 %145 = fmul float %18, %121 %146 = fadd float %145, %140 %147 = fmul float %20, %122 %148 = fadd float %147, %142 %149 = fmul float %21, %122 %150 = fadd float %149, %144 %151 = fmul float %22, %122 %152 = fadd float %151, %146 %153 = fmul float %12, %129 %154 = fmul float %13, %129 %155 = fmul float %14, %129 %156 = fmul float %16, %130 %157 = fadd float %156, %153 %158 = fmul float %17, %130 %159 = fadd float %158, %154 %160 = fmul float %18, %130 %161 = fadd float %160, %155 %162 = fmul float %20, %131 %163 = fadd float %162, %157 %164 = fmul float %21, %131 %165 = fadd float %164, %159 %166 = fmul float %22, %131 %167 = fadd float %166, %161 %168 = fmul float %12, %99 %169 = fmul float %13, %99 %170 = fmul float %14, %99 %171 = fmul float %16, %100 %172 = fadd float %171, %168 %173 = fmul float %17, %100 %174 = fadd float %173, %169 %175 = fmul float %18, %100 %176 = fadd float %175, %170 %177 = fmul float %20, %101 %178 = fadd float %177, %172 %179 = fmul float %21, %101 %180 = fadd float %179, %174 %181 = fmul float %22, %101 %182 = fadd float %181, %176 %183 = fmul float %178, %45 %184 = fmul float %180, %45 %185 = fmul float %182, %45 %186 = fmul float %163, %46 %187 = fadd float %186, %183 %188 = fmul float %165, %46 %189 = fadd float %188, %184 %190 = fmul float %167, %46 %191 = fadd float %190, %185 %192 = fmul float %148, %47 %193 = fadd float %192, %187 %194 = fmul float %150, %47 %195 = fadd float %194, %189 %196 = fmul float %152, %47 %197 = fadd float %196, %191 %198 = shl i32 20, 4 %199 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %198) %200 = shl i32 20, 4 %201 = add i32 %200, 4 %202 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %201) %203 = shl i32 20, 4 %204 = add i32 %203, 8 %205 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %204) %206 = fsub float -0.000000e+00, %199 %207 = fadd float %51, %206 %208 = fsub float -0.000000e+00, %202 %209 = fadd float %52, %208 %210 = fsub float -0.000000e+00, %205 %211 = fadd float %53, %210 %212 = fmul float %28, 0x3FE99999A0000000 %213 = fmul float %207, %207 %214 = fmul float %209, %209 %215 = fadd float %214, %213 %216 = fmul float %211, %211 %217 = fadd float %215, %216 %218 = call float @llvm.AMDGPU.rsq(float %217) %219 = fmul float %218, %217 %220 = fsub float -0.000000e+00, %217 %221 = call float @llvm.AMDGPU.cndlt(float %220, float %219, float 0.000000e+00) %222 = fsub float -0.000000e+00, %212 %223 = fadd float %221, %222 %224 = fsub float -0.000000e+00, %212 %225 = fadd float %28, %224 %226 = fdiv float 1.000000e+00, %225 %227 = fmul float %223, %226 %228 = call float @llvm.AMDIL.clamp.(float %227, float 0.000000e+00, float 1.000000e+00) %229 = fmul float 2.000000e+00, %228 %230 = fsub float -0.000000e+00, %229 %231 = fadd float 3.000000e+00, %230 %232 = fmul float %228, %231 %233 = fmul float %228, %232 %234 = fsub float -0.000000e+00, %233 %235 = fadd float 1.000000e+00, %234 %236 = fmul float %34, %235 %237 = fmul float %35, %235 %238 = fmul float %36, %235 %239 = fmul float %12, %135 %240 = fmul float %13, %135 %241 = fmul float %14, %135 %242 = fmul float %15, %135 %243 = fmul float %16, %136 %244 = fadd float %243, %239 %245 = fmul float %17, %136 %246 = fadd float %245, %240 %247 = fmul float %18, %136 %248 = fadd float %247, %241 %249 = fmul float %19, %136 %250 = fadd float %249, %242 %251 = fmul float %20, %137 %252 = fadd float %251, %244 %253 = fmul float %21, %137 %254 = fadd float %253, %246 %255 = fmul float %22, %137 %256 = fadd float %255, %248 %257 = fmul float %23, %137 %258 = fadd float %257, %250 %259 = fmul float %12, %57 %260 = fmul float %13, %57 %261 = fmul float %14, %57 %262 = fmul float %15, %57 %263 = fmul float %16, %58 %264 = fadd float %263, %259 %265 = fmul float %17, %58 %266 = fadd float %265, %260 %267 = fmul float %18, %58 %268 = fadd float %267, %261 %269 = fmul float %19, %58 %270 = fadd float %269, %262 %271 = fmul float %20, %59 %272 = fadd float %271, %264 %273 = fmul float %21, %59 %274 = fadd float %273, %266 %275 = fmul float %22, %59 %276 = fadd float %275, %268 %277 = fmul float %23, %59 %278 = fadd float %277, %270 %279 = fmul float %12, %132 %280 = fmul float %13, %132 %281 = fmul float %14, %132 %282 = fmul float %15, %132 %283 = fmul float %16, %133 %284 = fadd float %283, %279 %285 = fmul float %17, %133 %286 = fadd float %285, %280 %287 = fmul float %18, %133 %288 = fadd float %287, %281 %289 = fmul float %19, %133 %290 = fadd float %289, %282 %291 = fmul float %20, %134 %292 = fadd float %291, %284 %293 = fmul float %21, %134 %294 = fadd float %293, %286 %295 = fmul float %22, %134 %296 = fadd float %295, %288 %297 = fmul float %23, %134 %298 = fadd float %297, %290 %299 = fmul float %292, %236 %300 = fmul float %294, %236 %301 = fmul float %296, %236 %302 = fmul float %298, %236 %303 = fmul float %272, %237 %304 = fadd float %303, %299 %305 = fmul float %274, %237 %306 = fadd float %305, %300 %307 = fmul float %276, %237 %308 = fadd float %307, %301 %309 = fmul float %278, %237 %310 = fadd float %309, %302 %311 = fmul float %252, %238 %312 = fadd float %311, %304 %313 = fmul float %254, %238 %314 = fadd float %313, %306 %315 = fmul float %256, %238 %316 = fadd float %315, %308 %317 = fmul float %258, %238 %318 = fadd float %317, %310 %319 = fmul float %12, %51 %320 = fmul float %13, %51 %321 = fmul float %14, %51 %322 = fmul float %15, %51 %323 = fmul float %16, %52 %324 = fadd float %323, %319 %325 = fmul float %17, %52 %326 = fadd float %325, %320 %327 = fmul float %18, %52 %328 = fadd float %327, %321 %329 = fmul float %19, %52 %330 = fadd float %329, %322 %331 = fmul float %20, %53 %332 = fadd float %331, %324 %333 = fmul float %21, %53 %334 = fadd float %333, %326 %335 = fmul float %22, %53 %336 = fadd float %335, %328 %337 = fmul float %23, %53 %338 = fadd float %337, %330 %339 = fadd float %332, %24 %340 = fadd float %334, %25 %341 = fadd float %336, %26 %342 = fadd float %338, %27 %343 = fadd float %312, %339 %344 = fadd float %314, %340 %345 = fadd float %316, %341 %346 = fadd float %318, %342 %347 = shl i32 23, 4 %348 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %347) %349 = fadd float %348, %51 %350 = fadd float %349, %52 %351 = fadd float %350, %53 %352 = call float @llvm.cos.f32(float %351) %353 = fadd float %51, %53 %354 = call float @llvm.cos.f32(float %353) %355 = fmul float %352, %354 %356 = fadd float %52, %53 %357 = call float @llvm.cos.f32(float %356) %358 = fmul float %352, %357 %359 = fcmp uge float 0.000000e+00, %35 %360 = select i1 %359, float 0.000000e+00, float %35 %361 = fmul float %355, %360 %362 = fmul float 0.000000e+00, %360 %363 = fmul float %358, %360 %364 = fmul float %361, 0x3FB99999A0000000 %365 = fadd float %364, %343 %366 = fmul float %362, 0x3FB99999A0000000 %367 = fadd float %366, %344 %368 = fmul float %363, 0x3FB99999A0000000 %369 = fadd float %368, %345 %370 = shl i32 11, 4 %371 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %370) %372 = shl i32 11, 4 %373 = add i32 %372, 4 %374 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %373) %375 = shl i32 11, 4 %376 = add i32 %375, 8 %377 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %376) %378 = shl i32 11, 4 %379 = add i32 %378, 12 %380 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %379) %381 = shl i32 10, 4 %382 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %381) %383 = shl i32 10, 4 %384 = add i32 %383, 4 %385 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %384) %386 = shl i32 10, 4 %387 = add i32 %386, 8 %388 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %387) %389 = shl i32 10, 4 %390 = add i32 %389, 12 %391 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %390) %392 = shl i32 9, 4 %393 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %392) %394 = shl i32 9, 4 %395 = add i32 %394, 4 %396 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %395) %397 = shl i32 9, 4 %398 = add i32 %397, 8 %399 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %398) %400 = shl i32 9, 4 %401 = add i32 %400, 12 %402 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %401) %403 = shl i32 8, 4 %404 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %403) %405 = shl i32 8, 4 %406 = add i32 %405, 4 %407 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %406) %408 = shl i32 8, 4 %409 = add i32 %408, 8 %410 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %409) %411 = shl i32 8, 4 %412 = add i32 %411, 12 %413 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %412) %414 = fmul float %404, %365 %415 = fmul float %407, %365 %416 = fmul float %410, %365 %417 = fmul float %413, %365 %418 = fmul float %393, %367 %419 = fadd float %418, %414 %420 = fmul float %396, %367 %421 = fadd float %420, %415 %422 = fmul float %399, %367 %423 = fadd float %422, %416 %424 = fmul float %402, %367 %425 = fadd float %424, %417 %426 = fmul float %382, %369 %427 = fadd float %426, %419 %428 = fmul float %385, %369 %429 = fadd float %428, %421 %430 = fmul float %388, %369 %431 = fadd float %430, %423 %432 = fmul float %391, %369 %433 = fadd float %432, %425 %434 = fmul float %371, %346 %435 = fadd float %434, %427 %436 = fmul float %374, %346 %437 = fadd float %436, %429 %438 = fmul float %377, %346 %439 = fadd float %438, %431 %440 = fmul float %380, %346 %441 = fadd float %440, %433 %442 = shl i32 3, 4 %443 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %442) %444 = shl i32 3, 4 %445 = add i32 %444, 4 %446 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %445) %447 = shl i32 3, 4 %448 = add i32 %447, 8 %449 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %448) %450 = shl i32 2, 4 %451 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %450) %452 = shl i32 2, 4 %453 = add i32 %452, 4 %454 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %453) %455 = shl i32 2, 4 %456 = add i32 %455, 8 %457 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %456) %458 = shl i32 1, 4 %459 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %458) %460 = shl i32 1, 4 %461 = add i32 %460, 4 %462 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %461) %463 = shl i32 1, 4 %464 = add i32 %463, 8 %465 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %464) %466 = shl i32 0, 4 %467 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %466) %468 = shl i32 0, 4 %469 = add i32 %468, 4 %470 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %469) %471 = shl i32 0, 4 %472 = add i32 %471, 8 %473 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %472) %474 = fmul float %467, %365 %475 = fmul float %470, %365 %476 = fmul float %473, %365 %477 = fmul float %459, %367 %478 = fadd float %477, %474 %479 = fmul float %462, %367 %480 = fadd float %479, %475 %481 = fmul float %465, %367 %482 = fadd float %481, %476 %483 = fmul float %451, %369 %484 = fadd float %483, %478 %485 = fmul float %454, %369 %486 = fadd float %485, %480 %487 = fmul float %457, %369 %488 = fadd float %487, %482 %489 = fmul float %443, %346 %490 = fadd float %489, %484 %491 = fmul float %446, %346 %492 = fadd float %491, %486 %493 = fmul float %449, %346 %494 = fadd float %493, %488 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %40, float %41, float %193, float %195) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %197, float %69, float %70, float %71) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %490, float %492, float %494, float %346) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %435, float %437, float %439, float %441) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 ; Function Attrs: readnone declare float @llvm.AMDGPU.rsq(float) #2 ; Function Attrs: readnone declare float @llvm.AMDGPU.cndlt(float, float, float) #2 ; Function Attrs: readnone declare float @llvm.AMDIL.clamp.(float, float, float) #2 ; Function Attrs: nounwind readonly declare float @llvm.cos.f32(float) #3 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } attributes #3 = { nounwind readonly } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: S_LOAD_DWORDX4 s[4:7], s[8:9], 20 ; C0820914 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[1:4], s[4:7][v0] + 0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80010100 S_LOAD_DWORDX4 s[4:7], s[8:9], 16 ; C0820910 S_WAITCNT vmcnt(0) lgkmcnt(0) ; BF8C0070 BUFFER_LOAD_FORMAT_XYZW v[5:8], s[4:7][v0] + 0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80010500 S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v9, v5, v3 ; 10120705 V_MUL_F32_e32 v10, v7, v1 ; 10140307 V_SUB_F32_e32 v9, v10, v9 ; 0812130A V_MUL_F32_e32 v10, v7, v2 ; 10140507 V_MUL_F32_e32 v11, v6, v3 ; 10160706 V_SUB_F32_e32 v10, v11, v10 ; 0814150B V_MUL_F32_e32 v11, v10, v10 ; 1016150A V_MAD_F32 v11, v9, v9, v11, 0, 0, 0, 0 ; D282000B 042E1309 V_MUL_F32_e32 v12, v6, v1 ; 10180306 V_MUL_F32_e32 v13, v5, v2 ; 101A0505 V_SUB_F32_e32 v12, v13, v12 ; 0818190D V_MAD_F32 v11, v12, v12, v11, 0, 0, 0, 0 ; D282000B 042E190C V_RSQ_LEGACY_F32_e32 v11, v11 ; 7E165B0B V_MUL_F32_e32 v10, v10, v11 ; 1014170A V_MUL_F32_e32 v13, v10, v7 ; 101A0F0A V_MUL_F32_e32 v12, v12, v11 ; 1018170C V_MUL_F32_e32 v14, v12, v5 ; 101C0B0C V_SUB_F32_e32 v13, v14, v13 ; 081A1B0E V_MUL_F32_e32 v14, v12, v6 ; 101C0D0C V_MUL_F32_e32 v9, v9, v11 ; 10121709 V_MUL_F32_e32 v11, v9, v7 ; 10160F09 V_SUB_F32_e32 v11, v11, v14 ; 08161D0B V_MUL_F32_e32 v14, v11, v11 ; 101C170B V_MAD_F32 v14, v13, v13, v14, 0, 0, 0, 0 ; D282000E 043A1B0D V_MUL_F32_e32 v15, v9, v5 ; 101E0B09 V_MUL_F32_e32 v16, v10, v6 ; 10200D0A V_SUB_F32_e32 v15, v16, v15 ; 081E1F10 V_MAD_F32 v14, v15, v15, v14, 0, 0, 0, 0 ; D282000E 043A1F0F V_RSQ_LEGACY_F32_e32 v14, v14 ; 7E1C5B0E V_MUL_F32_e32 v13, v13, v14 ; 101A1D0D V_MUL_F32_e32 v11, v11, v14 ; 10161D0B S_LOAD_DWORDX4 s[4:7], s[0:1], 0 ; C0820100 S_WAITCNT lgkmcnt(0) ; BF8C007F S_BUFFER_LOAD_DWORD s10, s[4:7], 1 ; C2050501 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v16, s10, v11 ; 1020160A S_BUFFER_LOAD_DWORD s11, s[4:7], 5 ; C2058505 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v16, s11, v13, v16, 0, 0, 0, 0 ; D2820010 04421A0B V_MUL_F32_e32 v14, v15, v14 ; 101C1D0F S_BUFFER_LOAD_DWORD s12, s[4:7], 9 ; C2060509 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v15, s12, v14, v16, 0, 0, 0, 0 ; D282000F 04421C0C V_MUL_F32_e32 v16, s10, v10 ; 1020140A V_MAD_F32 v16, s11, v9, v16, 0, 0, 0, 0 ; D2820010 0442120B V_MAD_F32 v16, s12, v12, v16, 0, 0, 0, 0 ; D2820010 0442180C S_LOAD_DWORDX4 s[16:19], s[8:9], 8 ; C0880908 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[17:20], s[16:19][v0] + 0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80041100 S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v16, v16, v17 ; 10202310 V_MUL_F32_e32 v21, v5, v5 ; 102A0B05 V_MAD_F32 v21, v6, v6, v21, 0, 0, 0, 0 ; D2820015 04560D06 V_MAD_F32 v21, v7, v7, v21, 0, 0, 0, 0 ; D2820015 04560F07 V_RSQ_LEGACY_F32_e32 v21, v21 ; 7E2A5B15 V_MUL_F32_e32 v22, v6, v21 ; 102C2B06 V_MUL_F32_e32 v23, v5, v21 ; 102E2B05 V_MUL_F32_e32 v24, s10, v23 ; 10302E0A V_MAD_F32 v24, s11, v22, v24, 0, 0, 0, 0 ; D2820018 04622C0B V_MUL_F32_e32 v21, v7, v21 ; 102A2B07 V_MAD_F32 v24, s12, v21, v24, 0, 0, 0, 0 ; D2820018 04622A0C V_MAD_F32 v16, v24, v18, v16, 0, 0, 0, 0 ; D2820010 04422518 V_MAD_F32 v15, v15, v19, v16, 0, 0, 0, 0 ; D282000F 0442270F S_BUFFER_LOAD_DWORD s13, s[4:7], 0 ; C2068500 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v16, s13, v11 ; 1020160D S_BUFFER_LOAD_DWORD s14, s[4:7], 4 ; C2070504 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v16, s14, v13, v16, 0, 0, 0, 0 ; D2820010 04421A0E S_BUFFER_LOAD_DWORD s15, s[4:7], 8 ; C2078508 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v16, s15, v14, v16, 0, 0, 0, 0 ; D2820010 04421C0F V_MUL_F32_e32 v24, s13, v10 ; 1030140D V_MAD_F32 v24, s14, v9, v24, 0, 0, 0, 0 ; D2820018 0462120E V_MAD_F32 v24, s15, v12, v24, 0, 0, 0, 0 ; D2820018 0462180F V_MUL_F32_e32 v24, v24, v17 ; 10302318 V_MUL_F32_e32 v25, s13, v23 ; 10322E0D V_MAD_F32 v25, s14, v22, v25, 0, 0, 0, 0 ; D2820019 04662C0E V_MAD_F32 v25, s15, v21, v25, 0, 0, 0, 0 ; D2820019 04662A0F V_MAD_F32 v24, v25, v18, v24, 0, 0, 0, 0 ; D2820018 04622519 V_MAD_F32 v16, v16, v19, v24, 0, 0, 0, 0 ; D2820010 04622710 S_LOAD_DWORDX4 s[16:19], s[8:9], 4 ; C0880904 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[24:27], s[16:19][v0] + 0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80041800 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 32, 0, 0, 0, v24, v25, v16, v15 ; F800020F 0F101918 S_BUFFER_LOAD_DWORD s16, s[4:7], 2 ; C2080502 S_WAITCNT expcnt(0) lgkmcnt(0) ; BF8C000F V_MUL_F32_e32 v15, s16, v11 ; 101E1610 S_BUFFER_LOAD_DWORD s17, s[4:7], 6 ; C2088506 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v15, s17, v13, v15, 0, 0, 0, 0 ; D282000F 043E1A11 S_BUFFER_LOAD_DWORD s18, s[4:7], 10 ; C209050A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v15, s18, v14, v15, 0, 0, 0, 0 ; D282000F 043E1C12 V_MUL_F32_e32 v16, s16, v10 ; 10201410 V_MAD_F32 v16, s17, v9, v16, 0, 0, 0, 0 ; D2820010 04421211 V_MAD_F32 v16, s18, v12, v16, 0, 0, 0, 0 ; D2820010 04421812 V_MUL_F32_e32 v16, v16, v17 ; 10202310 V_MUL_F32_e32 v23, s16, v23 ; 102E2E10 V_MAD_F32 v22, s17, v22, v23, 0, 0, 0, 0 ; D2820016 045E2C11 V_MAD_F32 v21, s18, v21, v22, 0, 0, 0, 0 ; D2820015 045A2A12 V_MAD_F32 v16, v21, v18, v16, 0, 0, 0, 0 ; D2820010 04422515 V_MAD_F32 v15, v15, v19, v16, 0, 0, 0, 0 ; D282000F 0442270F S_LOAD_DWORDX4 s[20:23], s[8:9], 24 ; C08A0918 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[16:19], s[20:23][v0] + 0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80051000 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 33, 0, 0, 0, v15, v16, v17, v18 ; F800021F 1211100F S_WAITCNT expcnt(0) ; BF8C070F V_MUL_F32_e32 v15, v1, v1 ; 101E0301 V_MAD_F32 v15, v2, v2, v15, 0, 0, 0, 0 ; D282000F 043E0502 V_MAD_F32 v1, v3, v3, v15, 0, 0, 0, 0 ; D2820001 043E0703 V_RSQ_LEGACY_F32_e32 v2, v1 ; 7E045B01 V_MUL_F32_e32 v2, v2, v1 ; 10040302 V_XOR_B32_e32 v1, -2147483648, v1 ; 3A0202FF 80000000 V_CMP_GT_F32_e64 s[2:3], 0, v1, 0, 0, 0, 0 ; D0080002 02020280 V_CNDMASK_B32_e64 v1, 0.000000e+00, v2, s[2:3], 0, 0, 0, 0 ; D2000001 000A0480 V_MUL_F32_e32 v2, v13, v1 ; 1004030D V_MUL_F32_e32 v3, v11, v1 ; 1006030B V_MUL_F32_e32 v4, s10, v3 ; 1008060A V_MAD_F32 v4, s11, v2, v4, 0, 0, 0, 0 ; D2820004 0412040B V_MUL_F32_e32 v11, v14, v1 ; 1016030E V_MAD_F32 v4, s12, v11, v4, 0, 0, 0, 0 ; D2820004 0412160C V_MUL_F32_e32 v9, v9, v1 ; 10120309 V_MUL_F32_e32 v10, v10, v1 ; 1014030A V_MUL_F32_e32 v13, s10, v10 ; 101A140A V_MAD_F32 v13, s11, v9, v13, 0, 0, 0, 0 ; D282000D 0436120B V_MUL_F32_e32 v1, v12, v1 ; 1002030C V_MAD_F32 v12, s12, v1, v13, 0, 0, 0, 0 ; D282000C 0436020C S_LOAD_DWORDX4 s[20:23], s[8:9], 12 ; C08A090C S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[13:16], s[20:23][v0] + 0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80050D00 S_LOAD_DWORDX4 s[0:3], s[0:1], 4 ; C0800104 S_WAITCNT vmcnt(0) lgkmcnt(0) ; BF8C0070 S_BUFFER_LOAD_DWORD s19, s[0:3], 81 ; C2098151 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v17, s19 ; 7E220213 V_SUB_F32_e64 v17, v14, v17, 0, 0, 0, 0 ; D2080011 0202230E S_BUFFER_LOAD_DWORD s19, s[0:3], 80 ; C2098150 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v18, s19 ; 7E240213 V_SUB_F32_e64 v18, v13, v18, 0, 0, 0, 0 ; D2080012 0202250D V_MUL_F32_e32 v18, v18, v18 ; 10242512 V_MAD_F32 v17, v17, v17, v18, 0, 0, 0, 0 ; D2820011 044A2311 S_BUFFER_LOAD_DWORD s19, s[0:3], 82 ; C2098152 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v18, s19 ; 7E240213 V_SUB_F32_e64 v18, v15, v18, 0, 0, 0, 0 ; D2080012 0202250F V_MAD_F32 v17, v18, v18, v17, 0, 0, 0, 0 ; D2820011 04462512 V_RSQ_LEGACY_F32_e32 v18, v17 ; 7E245B11 V_MUL_F32_e32 v18, v18, v17 ; 10242312 V_XOR_B32_e32 v17, -2147483648, v17 ; 3A2222FF 80000000 V_CMP_GT_F32_e64 s[20:21], 0, v17, 0, 0, 0, 0 ; D0080014 02022280 V_CNDMASK_B32_e64 v17, 0.000000e+00, v18, s[20:21], 0, 0, 0, 0 ; D2000011 00522480 S_BUFFER_LOAD_DWORD s19, s[4:7], 16 ; C2098510 V_MOV_B32_e32 v18, -8.000000e-01 ; 7E2402FF BF4CCCCD S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v17, s19, v18, v17, 0, 0, 0, 0 ; D2820011 04462413 V_MOV_B32_e32 v19, s19 ; 7E260213 V_MAD_F32 v18, s19, v18, v19, 0, 0, 0, 0 ; D2820012 044E2413 V_RCP_F32_e32 v18, v18 ; 7E245512 V_MUL_F32_e32 v17, v17, v18 ; 10222511 V_ADD_F32_e64 v17, 0, v17, 0, 1, 0, 0 ; D2060811 02022280 V_ADD_F32_e32 v18, v17, v17 ; 06242311 V_SUB_F32_e32 v18, 3.000000e+00, v18 ; 082424FF 40400000 V_MUL_F32_e32 v18, v17, v18 ; 10242511 V_MUL_F32_e32 v17, v17, v18 ; 10222511 V_SUB_F32_e32 v17, 1.000000e+00, v17 ; 082222F2 S_LOAD_DWORDX4 s[20:23], s[8:9], 0 ; C08A0900 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[18:21], s[20:23][v0] + 0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80051200 S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v0, v18, v17 ; 10002312 V_MUL_F32_e32 v12, v12, v0 ; 1018010C V_MUL_F32_e32 v22, v19, v17 ; 102C2313 V_MUL_F32_e32 v23, s10, v5 ; 102E0A0A V_MAD_F32 v23, s11, v6, v23, 0, 0, 0, 0 ; D2820017 045E0C0B V_MAD_F32 v23, s12, v7, v23, 0, 0, 0, 0 ; D2820017 045E0E0C V_MAD_F32 v12, v23, v22, v12, 0, 0, 0, 0 ; D282000C 04322D17 V_MUL_F32_e32 v17, v20, v17 ; 10222314 V_MAD_F32 v4, v4, v17, v12, 0, 0, 0, 0 ; D2820004 04322304 V_MUL_F32_e32 v12, s10, v13 ; 10181A0A V_MAD_F32 v12, s11, v14, v12, 0, 0, 0, 0 ; D282000C 04321C0B V_MAD_F32 v12, s12, v15, v12, 0, 0, 0, 0 ; D282000C 04321E0C S_BUFFER_LOAD_DWORD s8, s[4:7], 13 ; C204050D S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v12, s8, v12 ; 06181808 V_ADD_F32_e32 v4, v4, v12 ; 06081904 V_CMP_U_F32_e64 s[8:9], v19, v19, 0, 0, 0, 0 ; D0100008 02022713 V_CMP_LE_F32_e64 s[10:11], v19, 0.000000e+00, 0, 0, 0, 0 ; D006000A 02010113 S_OR_B64 s[8:9], s[10:11], s[8:9] ; 8888080A V_CNDMASK_B32_e64 v12, v19, 0.000000e+00, s[8:9], 0, 0, 0, 0 ; D200000C 00210113 V_MUL_F32_e32 v18, 0.000000e+00, v12 ; 10241880 V_MOV_B32_e32 v19, 1.000000e-01 ; 7E2602FF 3DCCCCCD V_MAD_F32 v4, v18, v19, v4, 0, 0, 0, 0 ; D2820004 04122712 V_MUL_F32_e32 v18, s13, v3 ; 1024060D V_MAD_F32 v18, s14, v2, v18, 0, 0, 0, 0 ; D2820012 044A040E V_MAD_F32 v18, s15, v11, v18, 0, 0, 0, 0 ; D2820012 044A160F V_MUL_F32_e32 v20, s13, v10 ; 1028140D V_MAD_F32 v20, s14, v9, v20, 0, 0, 0, 0 ; D2820014 0452120E V_MAD_F32 v20, s15, v1, v20, 0, 0, 0, 0 ; D2820014 0452020F V_MUL_F32_e32 v20, v20, v0 ; 10280114 V_MUL_F32_e32 v21, s13, v5 ; 102A0A0D V_MAD_F32 v21, s14, v6, v21, 0, 0, 0, 0 ; D2820015 04560C0E V_MAD_F32 v21, s15, v7, v21, 0, 0, 0, 0 ; D2820015 04560E0F V_MAD_F32 v20, v21, v22, v20, 0, 0, 0, 0 ; D2820014 04522D15 V_MAD_F32 v18, v18, v17, v20, 0, 0, 0, 0 ; D2820012 04522312 V_MUL_F32_e32 v20, s13, v13 ; 10281A0D V_MAD_F32 v20, s14, v14, v20, 0, 0, 0, 0 ; D2820014 04521C0E V_MAD_F32 v20, s15, v15, v20, 0, 0, 0, 0 ; D2820014 04521E0F S_BUFFER_LOAD_DWORD s8, s[4:7], 12 ; C204050C S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v20, s8, v20 ; 06282808 V_ADD_F32_e32 v18, v18, v20 ; 06242912 V_ADD_F32_e32 v20, v13, v15 ; 06281F0D V_MUL_F32_e32 v20, 1042479491, v20 ; 102828FF 3E22F983 V_COS_F32_e32 v20, v20 ; 7E286D14 S_BUFFER_LOAD_DWORD s8, s[0:3], 92 ; C204015C S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v21, s8, v13 ; 062A1A08 V_ADD_F32_e32 v21, v21, v14 ; 062A1D15 V_ADD_F32_e32 v21, v21, v15 ; 062A1F15 V_MUL_F32_e32 v21, 1042479491, v21 ; 102A2AFF 3E22F983 V_COS_F32_e32 v21, v21 ; 7E2A6D15 V_MUL_F32_e32 v20, v21, v20 ; 10282915 V_MUL_F32_e32 v20, v20, v12 ; 10281914 V_MAD_F32 v18, v20, v19, v18, 0, 0, 0, 0 ; D2820012 044A2714 S_BUFFER_LOAD_DWORD s8, s[0:3], 2 ; C2040102 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v20, s8, v18 ; 10282408 S_BUFFER_LOAD_DWORD s8, s[0:3], 6 ; C2040106 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v20, s8, v4, v20, 0, 0, 0, 0 ; D2820014 04520808 V_MUL_F32_e32 v23, s16, v3 ; 102E0610 V_MAD_F32 v23, s17, v2, v23, 0, 0, 0, 0 ; D2820017 045E0411 V_MAD_F32 v23, s18, v11, v23, 0, 0, 0, 0 ; D2820017 045E1612 V_MUL_F32_e32 v24, s16, v10 ; 10301410 V_MAD_F32 v24, s17, v9, v24, 0, 0, 0, 0 ; D2820018 04621211 V_MAD_F32 v24, s18, v1, v24, 0, 0, 0, 0 ; D2820018 04620212 V_MUL_F32_e32 v24, v24, v0 ; 10300118 V_MUL_F32_e32 v25, s16, v5 ; 10320A10 V_MAD_F32 v25, s17, v6, v25, 0, 0, 0, 0 ; D2820019 04660C11 V_MAD_F32 v25, s18, v7, v25, 0, 0, 0, 0 ; D2820019 04660E12 V_MAD_F32 v24, v25, v22, v24, 0, 0, 0, 0 ; D2820018 04622D19 V_MAD_F32 v23, v23, v17, v24, 0, 0, 0, 0 ; D2820017 04622317 V_MUL_F32_e32 v24, s16, v13 ; 10301A10 V_MAD_F32 v24, s17, v14, v24, 0, 0, 0, 0 ; D2820018 04621C11 V_MAD_F32 v24, s18, v15, v24, 0, 0, 0, 0 ; D2820018 04621E12 S_BUFFER_LOAD_DWORD s8, s[4:7], 14 ; C204050E S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v24, s8, v24 ; 06303008 V_ADD_F32_e32 v23, v23, v24 ; 062E3117 V_ADD_F32_e32 v24, v14, v15 ; 06301F0E V_MUL_F32_e32 v24, 1042479491, v24 ; 103030FF 3E22F983 V_COS_F32_e32 v24, v24 ; 7E306D18 V_MUL_F32_e32 v21, v21, v24 ; 102A3115 V_MUL_F32_e32 v12, v21, v12 ; 10181915 V_MAD_F32 v12, v12, v19, v23, 0, 0, 0, 0 ; D282000C 045E270C S_BUFFER_LOAD_DWORD s8, s[0:3], 10 ; C204010A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v19, s8, v12, v20, 0, 0, 0, 0 ; D2820013 04521808 S_BUFFER_LOAD_DWORD s8, s[4:7], 3 ; C2040503 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v3, s8, v3 ; 10060608 S_BUFFER_LOAD_DWORD s9, s[4:7], 7 ; C2048507 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v2, s9, v2, v3, 0, 0, 0, 0 ; D2820002 040E0409 S_BUFFER_LOAD_DWORD s10, s[4:7], 11 ; C205050B S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v2, s10, v11, v2, 0, 0, 0, 0 ; D2820002 040A160A V_MUL_F32_e32 v3, s8, v10 ; 10061408 V_MAD_F32 v3, s9, v9, v3, 0, 0, 0, 0 ; D2820003 040E1209 V_MAD_F32 v1, s10, v1, v3, 0, 0, 0, 0 ; D2820001 040E020A V_MUL_F32_e32 v0, v1, v0 ; 10000101 V_MUL_F32_e32 v1, s8, v5 ; 10020A08 V_MAD_F32 v1, s9, v6, v1, 0, 0, 0, 0 ; D2820001 04060C09 V_MAD_F32 v1, s10, v7, v1, 0, 0, 0, 0 ; D2820001 04060E0A V_MAD_F32 v0, v1, v22, v0, 0, 0, 0, 0 ; D2820000 04022D01 V_MAD_F32 v0, v2, v17, v0, 0, 0, 0, 0 ; D2820000 04022302 V_MUL_F32_e32 v1, s8, v13 ; 10021A08 V_MAD_F32 v1, s9, v14, v1, 0, 0, 0, 0 ; D2820001 04061C09 V_MAD_F32 v1, s10, v15, v1, 0, 0, 0, 0 ; D2820001 04061E0A S_BUFFER_LOAD_DWORD s4, s[4:7], 15 ; C202050F S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v1, s4, v1 ; 06020204 V_ADD_F32_e32 v0, v0, v1 ; 06000300 S_BUFFER_LOAD_DWORD s4, s[0:3], 14 ; C202010E S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v1, s4, v0, v19, 0, 0, 0, 0 ; D2820001 044E0004 S_BUFFER_LOAD_DWORD s4, s[0:3], 1 ; C2020101 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v2, s4, v18 ; 10042404 S_BUFFER_LOAD_DWORD s4, s[0:3], 5 ; C2020105 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v2, s4, v4, v2, 0, 0, 0, 0 ; D2820002 040A0804 S_BUFFER_LOAD_DWORD s4, s[0:3], 9 ; C2020109 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v2, s4, v12, v2, 0, 0, 0, 0 ; D2820002 040A1804 S_BUFFER_LOAD_DWORD s4, s[0:3], 13 ; C202010D S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v2, s4, v0, v2, 0, 0, 0, 0 ; D2820002 040A0004 S_BUFFER_LOAD_DWORD s4, s[0:3], 0 ; C2020100 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v3, s4, v18 ; 10062404 S_BUFFER_LOAD_DWORD s4, s[0:3], 4 ; C2020104 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v3, s4, v4, v3, 0, 0, 0, 0 ; D2820003 040E0804 S_BUFFER_LOAD_DWORD s4, s[0:3], 8 ; C2020108 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v3, s4, v12, v3, 0, 0, 0, 0 ; D2820003 040E1804 S_BUFFER_LOAD_DWORD s4, s[0:3], 12 ; C202010C S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v3, s4, v0, v3, 0, 0, 0, 0 ; D2820003 040E0004 EXP 15, 34, 0, 0, 0, v3, v2, v1, v0 ; F800022F 00010203 S_BUFFER_LOAD_DWORD s4, s[0:3], 35 ; C2020123 S_WAITCNT expcnt(0) lgkmcnt(0) ; BF8C000F V_MUL_F32_e32 v1, s4, v18 ; 10022404 S_BUFFER_LOAD_DWORD s4, s[0:3], 39 ; C2020127 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v1, s4, v4, v1, 0, 0, 0, 0 ; D2820001 04060804 S_BUFFER_LOAD_DWORD s4, s[0:3], 43 ; C202012B S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v1, s4, v12, v1, 0, 0, 0, 0 ; D2820001 04061804 S_BUFFER_LOAD_DWORD s4, s[0:3], 47 ; C202012F S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v1, s4, v0, v1, 0, 0, 0, 0 ; D2820001 04060004 S_BUFFER_LOAD_DWORD s4, s[0:3], 34 ; C2020122 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v2, s4, v18 ; 10042404 S_BUFFER_LOAD_DWORD s4, s[0:3], 38 ; C2020126 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v2, s4, v4, v2, 0, 0, 0, 0 ; D2820002 040A0804 S_BUFFER_LOAD_DWORD s4, s[0:3], 42 ; C202012A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v2, s4, v12, v2, 0, 0, 0, 0 ; D2820002 040A1804 S_BUFFER_LOAD_DWORD s4, s[0:3], 46 ; C202012E S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v2, s4, v0, v2, 0, 0, 0, 0 ; D2820002 040A0004 S_BUFFER_LOAD_DWORD s4, s[0:3], 33 ; C2020121 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v3, s4, v18 ; 10062404 S_BUFFER_LOAD_DWORD s4, s[0:3], 37 ; C2020125 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v3, s4, v4, v3, 0, 0, 0, 0 ; D2820003 040E0804 S_BUFFER_LOAD_DWORD s4, s[0:3], 41 ; C2020129 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v3, s4, v12, v3, 0, 0, 0, 0 ; D2820003 040E1804 S_BUFFER_LOAD_DWORD s4, s[0:3], 45 ; C202012D S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v3, s4, v0, v3, 0, 0, 0, 0 ; D2820003 040E0004 S_BUFFER_LOAD_DWORD s4, s[0:3], 32 ; C2020120 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v5, s4, v18 ; 100A2404 S_BUFFER_LOAD_DWORD s4, s[0:3], 36 ; C2020124 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v4, s4, v4, v5, 0, 0, 0, 0 ; D2820004 04160804 S_BUFFER_LOAD_DWORD s4, s[0:3], 40 ; C2020128 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v4, s4, v12, v4, 0, 0, 0, 0 ; D2820004 04121804 S_BUFFER_LOAD_DWORD s0, s[0:3], 44 ; C200012C S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v0, s0, v0, v4, 0, 0, 0, 0 ; D2820000 04120000 EXP 15, 12, 0, 1, 0, v0, v3, v2, v1 ; F80008CF 01020300 S_ENDPGM ; BF810000 VERT DCL IN[0] DCL IN[1] DCL IN[2] DCL IN[3] DCL IN[4] DCL IN[5] DCL IN[6] DCL OUT[0], POSITION DCL OUT[1], GENERIC[20] DCL OUT[2], GENERIC[21] DCL OUT[3], GENERIC[22] DCL CONST[0..4] DCL CONST[1][0..96] DCL CONST[2][0..68] DCL TEMP[0..8], LOCAL DCL ADDR[0] IMM[0] FLT32 { 0.0000, 0.8000, 1.0000, 3.0000} IMM[1] UINT32 {0, 320, 368, 176} IMM[2] INT32 {20, 23, 11, 10} IMM[3] FLT32 { 2.0000, 0.1000, 0.0000, 0.0000} IMM[4] UINT32 {160, 144, 128, 48} IMM[5] INT32 {9, 8, 3, 2} IMM[6] UINT32 {32, 16, 0, 0} IMM[7] INT32 {1, 0, 0, 0} 0: DP3 TEMP[0].x, IN[5].xyzz, IN[5].xyzz 1: RSQ TEMP[1].x, TEMP[0].xxxx 2: MUL TEMP[1].x, TEMP[1].xxxx, TEMP[0].xxxx 3: CMP TEMP[0].x, -TEMP[0].xxxx, TEMP[1].xxxx, IMM[0].xxxx 4: MUL TEMP[1].xyz, IN[4].zxyy, IN[5].yzxx 5: MAD TEMP[1].xyz, IN[4].yzxx, IN[5].zxyy, -TEMP[1].xyzz 6: DP3 TEMP[2].x, TEMP[1].xyzz, TEMP[1].xyzz 7: RSQ TEMP[2].x, TEMP[2].xxxx 8: MUL TEMP[1].xyz, TEMP[1].xyzz, TEMP[2].xxxx 9: MUL TEMP[2].xyz, TEMP[1].zxyy, IN[4].yzxx 10: MAD TEMP[2].xyz, TEMP[1].yzxx, IN[4].zxyy, -TEMP[2].xyzz 11: DP3 TEMP[3].x, TEMP[2].xyzz, TEMP[2].xyzz 12: RSQ TEMP[3].x, TEMP[3].xxxx 13: MUL TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xxxx 14: DP3 TEMP[3].x, IN[4].xyzz, IN[4].xyzz 15: RSQ TEMP[3].x, TEMP[3].xxxx 16: MUL TEMP[3].xyz, IN[4].xyzz, TEMP[3].xxxx 17: MUL TEMP[4].xyz, TEMP[1].xyzz, TEMP[0].xxxx 18: MUL TEMP[0].xyz, TEMP[2].xyzz, TEMP[0].xxxx 19: MUL TEMP[5].xyz, CONST[0].xyzz, TEMP[2].xxxx 20: MAD TEMP[5].xyz, CONST[1].xyzz, TEMP[2].yyyy, TEMP[5].xyzz 21: MAD TEMP[2].xyz, CONST[2].xyzz, TEMP[2].zzzz, TEMP[5].xyzz 22: MUL TEMP[5].xyz, CONST[0].xyzz, TEMP[3].xxxx 23: MAD TEMP[5].xyz, CONST[1].xyzz, TEMP[3].yyyy, TEMP[5].xyzz 24: MAD TEMP[3].xyz, CONST[2].xyzz, TEMP[3].zzzz, TEMP[5].xyzz 25: MUL TEMP[5].xyz, CONST[0].xyzz, TEMP[1].xxxx 26: MAD TEMP[5].xyz, CONST[1].xyzz, TEMP[1].yyyy, TEMP[5].xyzz 27: MAD TEMP[1].xyz, CONST[2].xyzz, TEMP[1].zzzz, TEMP[5].xyzz 28: MUL TEMP[1].xyz, TEMP[1].xyzz, IN[2].xxxx 29: MAD TEMP[1].xyz, TEMP[3].xyzz, IN[2].yyyy, TEMP[1].xyzz 30: MAD TEMP[1].xyz, TEMP[2].xyzz, IN[2].zzzz, TEMP[1].xyzz 31: UARL ADDR[0].x, IMM[2].xxxx 32: MOV TEMP[2].xyz, CONST[1][ADDR[0].x].xyzz 33: ADD TEMP[2].xyz, IN[3].xyzz, -TEMP[2].xyzz 34: MUL TEMP[3].x, CONST[4].xxxx, IMM[0].yyyy 35: DP3 TEMP[2].x, TEMP[2].xyzz, TEMP[2].xyzz 36: RSQ TEMP[5].x, TEMP[2].xxxx 37: MUL TEMP[5].x, TEMP[5].xxxx, TEMP[2].xxxx 38: CMP TEMP[5].x, -TEMP[2].xxxx, TEMP[5].xxxx, IMM[0].xxxx 39: ADD TEMP[2].x, TEMP[5].xxxx, -TEMP[3].xxxx 40: ADD TEMP[3].x, CONST[4].xxxx, -TEMP[3].xxxx 41: RCP TEMP[3].x, TEMP[3].xxxx 42: MUL_SAT TEMP[2].x, TEMP[2].xxxx, TEMP[3].xxxx 43: MUL TEMP[3].x, IMM[3].xxxx, TEMP[2].xxxx 44: ADD TEMP[3].x, IMM[0].wwww, -TEMP[3].xxxx 45: MUL TEMP[3].x, TEMP[2].xxxx, TEMP[3].xxxx 46: MUL TEMP[3].x, TEMP[2].xxxx, TEMP[3].xxxx 47: ADD TEMP[3].x, IMM[0].zzzz, -TEMP[3].xxxx 48: MUL TEMP[2].xyz, IN[0].xyzz, TEMP[3].xxxx 49: MUL TEMP[3], CONST[0], TEMP[0].xxxx 50: MAD TEMP[3], CONST[1], TEMP[0].yyyy, TEMP[3] 51: MAD TEMP[0], CONST[2], TEMP[0].zzzz, TEMP[3] 52: MUL TEMP[3], CONST[0], IN[4].xxxx 53: MAD TEMP[3], CONST[1], IN[4].yyyy, TEMP[3] 54: MAD TEMP[3], CONST[2], IN[4].zzzz, TEMP[3] 55: MUL TEMP[5], CONST[0], TEMP[4].xxxx 56: MAD TEMP[5], CONST[1], TEMP[4].yyyy, TEMP[5] 57: MAD TEMP[4], CONST[2], TEMP[4].zzzz, TEMP[5] 58: MUL TEMP[4], TEMP[4], TEMP[2].xxxx 59: MAD TEMP[3], TEMP[3], TEMP[2].yyyy, TEMP[4] 60: MAD TEMP[0], TEMP[0], TEMP[2].zzzz, TEMP[3] 61: MUL TEMP[2], CONST[0], IN[3].xxxx 62: MAD TEMP[2], CONST[1], IN[3].yyyy, TEMP[2] 63: MAD TEMP[2], CONST[2], IN[3].zzzz, TEMP[2] 64: ADD TEMP[2], TEMP[2], CONST[3] 65: ADD TEMP[0], TEMP[0], TEMP[2] 66: UARL ADDR[0].x, IMM[2].yyyy 67: MOV TEMP[3].x, CONST[1][ADDR[0].x].xxxx 68: ADD TEMP[3].x, TEMP[3].xxxx, IN[3].xxxx 69: ADD TEMP[3].x, TEMP[3].xxxx, IN[3].yyyy 70: ADD TEMP[3].x, TEMP[3].xxxx, IN[3].zzzz 71: COS TEMP[3].x, TEMP[3].xxxx 72: MOV TEMP[4].y, IMM[0].xxxx 73: ADD TEMP[5].x, IN[3].xxxx, IN[3].zzzz 74: COS TEMP[5].x, TEMP[5].xxxx 75: MUL TEMP[4].x, TEMP[3].xxxx, TEMP[5].xxxx 76: ADD TEMP[5].x, IN[3].yyyy, IN[3].zzzz 77: COS TEMP[5].x, TEMP[5].xxxx 78: MUL TEMP[3].x, TEMP[3].xxxx, TEMP[5].xxxx 79: MOV TEMP[4].z, TEMP[3].xxxx 80: MAX TEMP[3].x, IMM[0].xxxx, IN[0].yyyy 81: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[3].xxxx 82: MAD TEMP[2].xyz, TEMP[3].xyzz, IMM[3].yyyy, TEMP[0].xyzz 83: UARL ADDR[0].x, IMM[2].zzzz 84: MOV TEMP[3], CONST[1][ADDR[0].x] 85: UARL ADDR[0].x, IMM[2].wwww 86: MOV TEMP[4], CONST[1][ADDR[0].x] 87: UARL ADDR[0].x, IMM[5].xxxx 88: MOV TEMP[5], CONST[1][ADDR[0].x] 89: UARL ADDR[0].x, IMM[5].yyyy 90: MOV TEMP[6], CONST[1][ADDR[0].x] 91: MUL TEMP[6], TEMP[6], TEMP[2].xxxx 92: MAD TEMP[5], TEMP[5], TEMP[2].yyyy, TEMP[6] 93: MAD TEMP[4], TEMP[4], TEMP[2].zzzz, TEMP[5] 94: MAD TEMP[3], TEMP[3], TEMP[0].wwww, TEMP[4] 95: MOV TEMP[4].zw, TEMP[1].yyxy 96: MOV TEMP[1].x, TEMP[1].zzzz 97: MOV TEMP[1].yzw, IN[6].yxyz 98: UARL ADDR[0].x, IMM[5].zzzz 99: MOV TEMP[5], CONST[1][ADDR[0].x] 100: UARL ADDR[0].x, IMM[5].wwww 101: MOV TEMP[6], CONST[1][ADDR[0].x] 102: UARL ADDR[0].x, IMM[7].xxxx 103: MOV TEMP[7], CONST[1][ADDR[0].x] 104: UARL ADDR[0].x, IMM[7].yyyy 105: MOV TEMP[8], CONST[1][ADDR[0].x] 106: MUL TEMP[8], TEMP[8], TEMP[2].xxxx 107: MAD TEMP[7], TEMP[7], TEMP[2].yyyy, TEMP[8] 108: MAD TEMP[2], TEMP[6], TEMP[2].zzzz, TEMP[7] 109: MAD TEMP[0].xyz, TEMP[5], TEMP[0].wwww, TEMP[2] 110: MOV TEMP[0].xyz, TEMP[0].xyzx 111: MOV TEMP[4].xy, IN[1].xyxx 112: MOV OUT[3], TEMP[0] 113: MOV OUT[0], TEMP[3] 114: MOV OUT[2], TEMP[1] 115: MOV OUT[1], TEMP[4] 116: END ; ModuleID = 'tgsi' define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* inreg, [17 x <16 x i8>] addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 { main_body: %10 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0 %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0 %12 = call float @llvm.SI.load.const(<16 x i8> %11, i32 0) %13 = call float @llvm.SI.load.const(<16 x i8> %11, i32 4) %14 = call float @llvm.SI.load.const(<16 x i8> %11, i32 8) %15 = call float @llvm.SI.load.const(<16 x i8> %11, i32 12) %16 = call float @llvm.SI.load.const(<16 x i8> %11, i32 16) %17 = call float @llvm.SI.load.const(<16 x i8> %11, i32 20) %18 = call float @llvm.SI.load.const(<16 x i8> %11, i32 24) %19 = call float @llvm.SI.load.const(<16 x i8> %11, i32 28) %20 = call float @llvm.SI.load.const(<16 x i8> %11, i32 32) %21 = call float @llvm.SI.load.const(<16 x i8> %11, i32 36) %22 = call float @llvm.SI.load.const(<16 x i8> %11, i32 40) %23 = call float @llvm.SI.load.const(<16 x i8> %11, i32 44) %24 = call float @llvm.SI.load.const(<16 x i8> %11, i32 48) %25 = call float @llvm.SI.load.const(<16 x i8> %11, i32 52) %26 = call float @llvm.SI.load.const(<16 x i8> %11, i32 56) %27 = call float @llvm.SI.load.const(<16 x i8> %11, i32 60) %28 = call float @llvm.SI.load.const(<16 x i8> %11, i32 64) %29 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 1 %30 = load <16 x i8> addrspace(2)* %29, !tbaa !0 %31 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 0 %32 = load <16 x i8> addrspace(2)* %31, !tbaa !0 %33 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %32, i32 0, i32 %6) %34 = extractelement <4 x float> %33, i32 0 %35 = extractelement <4 x float> %33, i32 1 %36 = extractelement <4 x float> %33, i32 2 %37 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 1 %38 = load <16 x i8> addrspace(2)* %37, !tbaa !0 %39 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %38, i32 0, i32 %6) %40 = extractelement <4 x float> %39, i32 0 %41 = extractelement <4 x float> %39, i32 1 %42 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 2 %43 = load <16 x i8> addrspace(2)* %42, !tbaa !0 %44 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %43, i32 0, i32 %6) %45 = extractelement <4 x float> %44, i32 0 %46 = extractelement <4 x float> %44, i32 1 %47 = extractelement <4 x float> %44, i32 2 %48 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 3 %49 = load <16 x i8> addrspace(2)* %48, !tbaa !0 %50 = add i32 %9, %5 %51 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %49, i32 0, i32 %50) %52 = extractelement <4 x float> %51, i32 0 %53 = extractelement <4 x float> %51, i32 1 %54 = extractelement <4 x float> %51, i32 2 %55 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 4 %56 = load <16 x i8> addrspace(2)* %55, !tbaa !0 %57 = add i32 %9, %5 %58 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %56, i32 0, i32 %57) %59 = extractelement <4 x float> %58, i32 0 %60 = extractelement <4 x float> %58, i32 1 %61 = extractelement <4 x float> %58, i32 2 %62 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 5 %63 = load <16 x i8> addrspace(2)* %62, !tbaa !0 %64 = add i32 %9, %5 %65 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %63, i32 0, i32 %64) %66 = extractelement <4 x float> %65, i32 0 %67 = extractelement <4 x float> %65, i32 1 %68 = extractelement <4 x float> %65, i32 2 %69 = getelementptr [17 x <16 x i8>] addrspace(2)* %4, i64 0, i32 6 %70 = load <16 x i8> addrspace(2)* %69, !tbaa !0 %71 = add i32 %9, %5 %72 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %70, i32 0, i32 %71) %73 = extractelement <4 x float> %72, i32 0 %74 = extractelement <4 x float> %72, i32 1 %75 = extractelement <4 x float> %72, i32 2 %76 = fmul float %66, %66 %77 = fmul float %67, %67 %78 = fadd float %77, %76 %79 = fmul float %68, %68 %80 = fadd float %78, %79 %81 = call float @llvm.AMDGPU.rsq(float %80) %82 = fmul float %81, %80 %83 = fsub float -0.000000e+00, %80 %84 = call float @llvm.AMDGPU.cndlt(float %83, float %82, float 0.000000e+00) %85 = fmul float %61, %67 %86 = fmul float %59, %68 %87 = fmul float %60, %66 %88 = fsub float -0.000000e+00, %85 %89 = fmul float %60, %68 %90 = fadd float %89, %88 %91 = fsub float -0.000000e+00, %86 %92 = fmul float %61, %66 %93 = fadd float %92, %91 %94 = fsub float -0.000000e+00, %87 %95 = fmul float %59, %67 %96 = fadd float %95, %94 %97 = fmul float %90, %90 %98 = fmul float %93, %93 %99 = fadd float %98, %97 %100 = fmul float %96, %96 %101 = fadd float %99, %100 %102 = call float @llvm.AMDGPU.rsq(float %101) %103 = fmul float %90, %102 %104 = fmul float %93, %102 %105 = fmul float %96, %102 %106 = fmul float %105, %60 %107 = fmul float %103, %61 %108 = fmul float %104, %59 %109 = fsub float -0.000000e+00, %106 %110 = fmul float %104, %61 %111 = fadd float %110, %109 %112 = fsub float -0.000000e+00, %107 %113 = fmul float %105, %59 %114 = fadd float %113, %112 %115 = fsub float -0.000000e+00, %108 %116 = fmul float %103, %60 %117 = fadd float %116, %115 %118 = fmul float %111, %111 %119 = fmul float %114, %114 %120 = fadd float %119, %118 %121 = fmul float %117, %117 %122 = fadd float %120, %121 %123 = call float @llvm.AMDGPU.rsq(float %122) %124 = fmul float %111, %123 %125 = fmul float %114, %123 %126 = fmul float %117, %123 %127 = fmul float %59, %59 %128 = fmul float %60, %60 %129 = fadd float %128, %127 %130 = fmul float %61, %61 %131 = fadd float %129, %130 %132 = call float @llvm.AMDGPU.rsq(float %131) %133 = fmul float %59, %132 %134 = fmul float %60, %132 %135 = fmul float %61, %132 %136 = fmul float %103, %84 %137 = fmul float %104, %84 %138 = fmul float %105, %84 %139 = fmul float %124, %84 %140 = fmul float %125, %84 %141 = fmul float %126, %84 %142 = fmul float %12, %124 %143 = fmul float %13, %124 %144 = fmul float %14, %124 %145 = fmul float %16, %125 %146 = fadd float %145, %142 %147 = fmul float %17, %125 %148 = fadd float %147, %143 %149 = fmul float %18, %125 %150 = fadd float %149, %144 %151 = fmul float %20, %126 %152 = fadd float %151, %146 %153 = fmul float %21, %126 %154 = fadd float %153, %148 %155 = fmul float %22, %126 %156 = fadd float %155, %150 %157 = fmul float %12, %133 %158 = fmul float %13, %133 %159 = fmul float %14, %133 %160 = fmul float %16, %134 %161 = fadd float %160, %157 %162 = fmul float %17, %134 %163 = fadd float %162, %158 %164 = fmul float %18, %134 %165 = fadd float %164, %159 %166 = fmul float %20, %135 %167 = fadd float %166, %161 %168 = fmul float %21, %135 %169 = fadd float %168, %163 %170 = fmul float %22, %135 %171 = fadd float %170, %165 %172 = fmul float %12, %103 %173 = fmul float %13, %103 %174 = fmul float %14, %103 %175 = fmul float %16, %104 %176 = fadd float %175, %172 %177 = fmul float %17, %104 %178 = fadd float %177, %173 %179 = fmul float %18, %104 %180 = fadd float %179, %174 %181 = fmul float %20, %105 %182 = fadd float %181, %176 %183 = fmul float %21, %105 %184 = fadd float %183, %178 %185 = fmul float %22, %105 %186 = fadd float %185, %180 %187 = fmul float %182, %45 %188 = fmul float %184, %45 %189 = fmul float %186, %45 %190 = fmul float %167, %46 %191 = fadd float %190, %187 %192 = fmul float %169, %46 %193 = fadd float %192, %188 %194 = fmul float %171, %46 %195 = fadd float %194, %189 %196 = fmul float %152, %47 %197 = fadd float %196, %191 %198 = fmul float %154, %47 %199 = fadd float %198, %193 %200 = fmul float %156, %47 %201 = fadd float %200, %195 %202 = shl i32 20, 4 %203 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %202) %204 = shl i32 20, 4 %205 = add i32 %204, 4 %206 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %205) %207 = shl i32 20, 4 %208 = add i32 %207, 8 %209 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %208) %210 = fsub float -0.000000e+00, %203 %211 = fadd float %52, %210 %212 = fsub float -0.000000e+00, %206 %213 = fadd float %53, %212 %214 = fsub float -0.000000e+00, %209 %215 = fadd float %54, %214 %216 = fmul float %28, 0x3FE99999A0000000 %217 = fmul float %211, %211 %218 = fmul float %213, %213 %219 = fadd float %218, %217 %220 = fmul float %215, %215 %221 = fadd float %219, %220 %222 = call float @llvm.AMDGPU.rsq(float %221) %223 = fmul float %222, %221 %224 = fsub float -0.000000e+00, %221 %225 = call float @llvm.AMDGPU.cndlt(float %224, float %223, float 0.000000e+00) %226 = fsub float -0.000000e+00, %216 %227 = fadd float %225, %226 %228 = fsub float -0.000000e+00, %216 %229 = fadd float %28, %228 %230 = fdiv float 1.000000e+00, %229 %231 = fmul float %227, %230 %232 = call float @llvm.AMDIL.clamp.(float %231, float 0.000000e+00, float 1.000000e+00) %233 = fmul float 2.000000e+00, %232 %234 = fsub float -0.000000e+00, %233 %235 = fadd float 3.000000e+00, %234 %236 = fmul float %232, %235 %237 = fmul float %232, %236 %238 = fsub float -0.000000e+00, %237 %239 = fadd float 1.000000e+00, %238 %240 = fmul float %34, %239 %241 = fmul float %35, %239 %242 = fmul float %36, %239 %243 = fmul float %12, %139 %244 = fmul float %13, %139 %245 = fmul float %14, %139 %246 = fmul float %15, %139 %247 = fmul float %16, %140 %248 = fadd float %247, %243 %249 = fmul float %17, %140 %250 = fadd float %249, %244 %251 = fmul float %18, %140 %252 = fadd float %251, %245 %253 = fmul float %19, %140 %254 = fadd float %253, %246 %255 = fmul float %20, %141 %256 = fadd float %255, %248 %257 = fmul float %21, %141 %258 = fadd float %257, %250 %259 = fmul float %22, %141 %260 = fadd float %259, %252 %261 = fmul float %23, %141 %262 = fadd float %261, %254 %263 = fmul float %12, %59 %264 = fmul float %13, %59 %265 = fmul float %14, %59 %266 = fmul float %15, %59 %267 = fmul float %16, %60 %268 = fadd float %267, %263 %269 = fmul float %17, %60 %270 = fadd float %269, %264 %271 = fmul float %18, %60 %272 = fadd float %271, %265 %273 = fmul float %19, %60 %274 = fadd float %273, %266 %275 = fmul float %20, %61 %276 = fadd float %275, %268 %277 = fmul float %21, %61 %278 = fadd float %277, %270 %279 = fmul float %22, %61 %280 = fadd float %279, %272 %281 = fmul float %23, %61 %282 = fadd float %281, %274 %283 = fmul float %12, %136 %284 = fmul float %13, %136 %285 = fmul float %14, %136 %286 = fmul float %15, %136 %287 = fmul float %16, %137 %288 = fadd float %287, %283 %289 = fmul float %17, %137 %290 = fadd float %289, %284 %291 = fmul float %18, %137 %292 = fadd float %291, %285 %293 = fmul float %19, %137 %294 = fadd float %293, %286 %295 = fmul float %20, %138 %296 = fadd float %295, %288 %297 = fmul float %21, %138 %298 = fadd float %297, %290 %299 = fmul float %22, %138 %300 = fadd float %299, %292 %301 = fmul float %23, %138 %302 = fadd float %301, %294 %303 = fmul float %296, %240 %304 = fmul float %298, %240 %305 = fmul float %300, %240 %306 = fmul float %302, %240 %307 = fmul float %276, %241 %308 = fadd float %307, %303 %309 = fmul float %278, %241 %310 = fadd float %309, %304 %311 = fmul float %280, %241 %312 = fadd float %311, %305 %313 = fmul float %282, %241 %314 = fadd float %313, %306 %315 = fmul float %256, %242 %316 = fadd float %315, %308 %317 = fmul float %258, %242 %318 = fadd float %317, %310 %319 = fmul float %260, %242 %320 = fadd float %319, %312 %321 = fmul float %262, %242 %322 = fadd float %321, %314 %323 = fmul float %12, %52 %324 = fmul float %13, %52 %325 = fmul float %14, %52 %326 = fmul float %15, %52 %327 = fmul float %16, %53 %328 = fadd float %327, %323 %329 = fmul float %17, %53 %330 = fadd float %329, %324 %331 = fmul float %18, %53 %332 = fadd float %331, %325 %333 = fmul float %19, %53 %334 = fadd float %333, %326 %335 = fmul float %20, %54 %336 = fadd float %335, %328 %337 = fmul float %21, %54 %338 = fadd float %337, %330 %339 = fmul float %22, %54 %340 = fadd float %339, %332 %341 = fmul float %23, %54 %342 = fadd float %341, %334 %343 = fadd float %336, %24 %344 = fadd float %338, %25 %345 = fadd float %340, %26 %346 = fadd float %342, %27 %347 = fadd float %316, %343 %348 = fadd float %318, %344 %349 = fadd float %320, %345 %350 = fadd float %322, %346 %351 = shl i32 23, 4 %352 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %351) %353 = fadd float %352, %52 %354 = fadd float %353, %53 %355 = fadd float %354, %54 %356 = call float @llvm.cos.f32(float %355) %357 = fadd float %52, %54 %358 = call float @llvm.cos.f32(float %357) %359 = fmul float %356, %358 %360 = fadd float %53, %54 %361 = call float @llvm.cos.f32(float %360) %362 = fmul float %356, %361 %363 = fcmp uge float 0.000000e+00, %35 %364 = select i1 %363, float 0.000000e+00, float %35 %365 = fmul float %359, %364 %366 = fmul float 0.000000e+00, %364 %367 = fmul float %362, %364 %368 = fmul float %365, 0x3FB99999A0000000 %369 = fadd float %368, %347 %370 = fmul float %366, 0x3FB99999A0000000 %371 = fadd float %370, %348 %372 = fmul float %367, 0x3FB99999A0000000 %373 = fadd float %372, %349 %374 = shl i32 11, 4 %375 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %374) %376 = shl i32 11, 4 %377 = add i32 %376, 4 %378 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %377) %379 = shl i32 11, 4 %380 = add i32 %379, 8 %381 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %380) %382 = shl i32 11, 4 %383 = add i32 %382, 12 %384 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %383) %385 = shl i32 10, 4 %386 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %385) %387 = shl i32 10, 4 %388 = add i32 %387, 4 %389 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %388) %390 = shl i32 10, 4 %391 = add i32 %390, 8 %392 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %391) %393 = shl i32 10, 4 %394 = add i32 %393, 12 %395 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %394) %396 = shl i32 9, 4 %397 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %396) %398 = shl i32 9, 4 %399 = add i32 %398, 4 %400 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %399) %401 = shl i32 9, 4 %402 = add i32 %401, 8 %403 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %402) %404 = shl i32 9, 4 %405 = add i32 %404, 12 %406 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %405) %407 = shl i32 8, 4 %408 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %407) %409 = shl i32 8, 4 %410 = add i32 %409, 4 %411 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %410) %412 = shl i32 8, 4 %413 = add i32 %412, 8 %414 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %413) %415 = shl i32 8, 4 %416 = add i32 %415, 12 %417 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %416) %418 = fmul float %408, %369 %419 = fmul float %411, %369 %420 = fmul float %414, %369 %421 = fmul float %417, %369 %422 = fmul float %397, %371 %423 = fadd float %422, %418 %424 = fmul float %400, %371 %425 = fadd float %424, %419 %426 = fmul float %403, %371 %427 = fadd float %426, %420 %428 = fmul float %406, %371 %429 = fadd float %428, %421 %430 = fmul float %386, %373 %431 = fadd float %430, %423 %432 = fmul float %389, %373 %433 = fadd float %432, %425 %434 = fmul float %392, %373 %435 = fadd float %434, %427 %436 = fmul float %395, %373 %437 = fadd float %436, %429 %438 = fmul float %375, %350 %439 = fadd float %438, %431 %440 = fmul float %378, %350 %441 = fadd float %440, %433 %442 = fmul float %381, %350 %443 = fadd float %442, %435 %444 = fmul float %384, %350 %445 = fadd float %444, %437 %446 = shl i32 3, 4 %447 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %446) %448 = shl i32 3, 4 %449 = add i32 %448, 4 %450 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %449) %451 = shl i32 3, 4 %452 = add i32 %451, 8 %453 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %452) %454 = shl i32 2, 4 %455 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %454) %456 = shl i32 2, 4 %457 = add i32 %456, 4 %458 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %457) %459 = shl i32 2, 4 %460 = add i32 %459, 8 %461 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %460) %462 = shl i32 1, 4 %463 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %462) %464 = shl i32 1, 4 %465 = add i32 %464, 4 %466 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %465) %467 = shl i32 1, 4 %468 = add i32 %467, 8 %469 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %468) %470 = shl i32 0, 4 %471 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %470) %472 = shl i32 0, 4 %473 = add i32 %472, 4 %474 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %473) %475 = shl i32 0, 4 %476 = add i32 %475, 8 %477 = call float @llvm.SI.load.const(<16 x i8> %30, i32 %476) %478 = fmul float %471, %369 %479 = fmul float %474, %369 %480 = fmul float %477, %369 %481 = fmul float %463, %371 %482 = fadd float %481, %478 %483 = fmul float %466, %371 %484 = fadd float %483, %479 %485 = fmul float %469, %371 %486 = fadd float %485, %480 %487 = fmul float %455, %373 %488 = fadd float %487, %482 %489 = fmul float %458, %373 %490 = fadd float %489, %484 %491 = fmul float %461, %373 %492 = fadd float %491, %486 %493 = fmul float %447, %350 %494 = fadd float %493, %488 %495 = fmul float %450, %350 %496 = fadd float %495, %490 %497 = fmul float %453, %350 %498 = fadd float %497, %492 call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %40, float %41, float %197, float %199) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %201, float %73, float %74, float %75) call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %494, float %496, float %498, float %350) call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %439, float %441, float %443, float %445) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 ; Function Attrs: readnone declare float @llvm.AMDGPU.rsq(float) #2 ; Function Attrs: readnone declare float @llvm.AMDGPU.cndlt(float, float, float) #2 ; Function Attrs: readnone declare float @llvm.AMDIL.clamp.(float, float, float) #2 ; Function Attrs: nounwind readonly declare float @llvm.cos.f32(float) #3 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" } attributes #1 = { nounwind readnone } attributes #2 = { readnone } attributes #3 = { nounwind readonly } !0 = metadata !{metadata !"const", null, i32 1} Shader Disassembly: V_ADD_I32_e32 v1, s10, v3 ; 4A02060A S_LOAD_DWORDX4 s[4:7], s[8:9], 20 ; C0820914 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[2:5], s[4:7][v1] + 0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80010201 S_LOAD_DWORDX4 s[4:7], s[8:9], 16 ; C0820910 S_WAITCNT vmcnt(0) lgkmcnt(0) ; BF8C0070 BUFFER_LOAD_FORMAT_XYZW v[6:9], s[4:7][v1] + 0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80010601 S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v10, v6, v4 ; 10140906 V_MUL_F32_e32 v11, v8, v2 ; 10160508 V_SUB_F32_e32 v10, v11, v10 ; 0814150B V_MUL_F32_e32 v11, v8, v3 ; 10160708 V_MUL_F32_e32 v12, v7, v4 ; 10180907 V_SUB_F32_e32 v11, v12, v11 ; 0816170C V_MUL_F32_e32 v12, v11, v11 ; 1018170B V_MAD_F32 v12, v10, v10, v12, 0, 0, 0, 0 ; D282000C 0432150A V_MUL_F32_e32 v13, v7, v2 ; 101A0507 V_MUL_F32_e32 v14, v6, v3 ; 101C0706 V_SUB_F32_e32 v13, v14, v13 ; 081A1B0E V_MAD_F32 v12, v13, v13, v12, 0, 0, 0, 0 ; D282000C 04321B0D V_RSQ_LEGACY_F32_e32 v12, v12 ; 7E185B0C V_MUL_F32_e32 v11, v11, v12 ; 1016190B V_MUL_F32_e32 v14, v11, v8 ; 101C110B V_MUL_F32_e32 v13, v13, v12 ; 101A190D V_MUL_F32_e32 v15, v13, v6 ; 101E0D0D V_SUB_F32_e32 v14, v15, v14 ; 081C1D0F V_MUL_F32_e32 v15, v13, v7 ; 101E0F0D V_MUL_F32_e32 v10, v10, v12 ; 1014190A V_MUL_F32_e32 v12, v10, v8 ; 1018110A V_SUB_F32_e32 v12, v12, v15 ; 08181F0C V_MUL_F32_e32 v15, v12, v12 ; 101E190C V_MAD_F32 v15, v14, v14, v15, 0, 0, 0, 0 ; D282000F 043E1D0E V_MUL_F32_e32 v16, v10, v6 ; 10200D0A V_MUL_F32_e32 v17, v11, v7 ; 10220F0B V_SUB_F32_e32 v16, v17, v16 ; 08202111 V_MAD_F32 v15, v16, v16, v15, 0, 0, 0, 0 ; D282000F 043E2110 V_RSQ_LEGACY_F32_e32 v15, v15 ; 7E1E5B0F V_MUL_F32_e32 v14, v14, v15 ; 101C1F0E V_MUL_F32_e32 v12, v12, v15 ; 10181F0C S_LOAD_DWORDX4 s[4:7], s[0:1], 0 ; C0820100 S_WAITCNT lgkmcnt(0) ; BF8C007F S_BUFFER_LOAD_DWORD s10, s[4:7], 1 ; C2050501 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v17, s10, v12 ; 1022180A S_BUFFER_LOAD_DWORD s11, s[4:7], 5 ; C2058505 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v17, s11, v14, v17, 0, 0, 0, 0 ; D2820011 04461C0B V_MUL_F32_e32 v15, v16, v15 ; 101E1F10 S_BUFFER_LOAD_DWORD s12, s[4:7], 9 ; C2060509 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v16, s12, v15, v17, 0, 0, 0, 0 ; D2820010 04461E0C V_MUL_F32_e32 v17, s10, v11 ; 1022160A V_MAD_F32 v17, s11, v10, v17, 0, 0, 0, 0 ; D2820011 0446140B V_MAD_F32 v17, s12, v13, v17, 0, 0, 0, 0 ; D2820011 04461A0C S_LOAD_DWORDX4 s[16:19], s[8:9], 8 ; C0880908 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[18:21], s[16:19][v0] + 0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80041200 S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v17, v17, v18 ; 10222511 V_MUL_F32_e32 v22, v6, v6 ; 102C0D06 V_MAD_F32 v22, v7, v7, v22, 0, 0, 0, 0 ; D2820016 045A0F07 V_MAD_F32 v22, v8, v8, v22, 0, 0, 0, 0 ; D2820016 045A1108 V_RSQ_LEGACY_F32_e32 v22, v22 ; 7E2C5B16 V_MUL_F32_e32 v23, v7, v22 ; 102E2D07 V_MUL_F32_e32 v24, v6, v22 ; 10302D06 V_MUL_F32_e32 v25, s10, v24 ; 1032300A V_MAD_F32 v25, s11, v23, v25, 0, 0, 0, 0 ; D2820019 04662E0B V_MUL_F32_e32 v22, v8, v22 ; 102C2D08 V_MAD_F32 v25, s12, v22, v25, 0, 0, 0, 0 ; D2820019 04662C0C V_MAD_F32 v17, v25, v19, v17, 0, 0, 0, 0 ; D2820011 04462719 V_MAD_F32 v16, v16, v20, v17, 0, 0, 0, 0 ; D2820010 04462910 S_BUFFER_LOAD_DWORD s13, s[4:7], 0 ; C2068500 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v17, s13, v12 ; 1022180D S_BUFFER_LOAD_DWORD s14, s[4:7], 4 ; C2070504 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v17, s14, v14, v17, 0, 0, 0, 0 ; D2820011 04461C0E S_BUFFER_LOAD_DWORD s15, s[4:7], 8 ; C2078508 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v17, s15, v15, v17, 0, 0, 0, 0 ; D2820011 04461E0F V_MUL_F32_e32 v25, s13, v11 ; 1032160D V_MAD_F32 v25, s14, v10, v25, 0, 0, 0, 0 ; D2820019 0466140E V_MAD_F32 v25, s15, v13, v25, 0, 0, 0, 0 ; D2820019 04661A0F V_MUL_F32_e32 v25, v25, v18 ; 10322519 V_MUL_F32_e32 v26, s13, v24 ; 1034300D V_MAD_F32 v26, s14, v23, v26, 0, 0, 0, 0 ; D282001A 046A2E0E V_MAD_F32 v26, s15, v22, v26, 0, 0, 0, 0 ; D282001A 046A2C0F V_MAD_F32 v25, v26, v19, v25, 0, 0, 0, 0 ; D2820019 0466271A V_MAD_F32 v17, v17, v20, v25, 0, 0, 0, 0 ; D2820011 04662911 S_LOAD_DWORDX4 s[16:19], s[8:9], 4 ; C0880904 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[25:28], s[16:19][v0] + 0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80041900 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 32, 0, 0, 0, v25, v26, v17, v16 ; F800020F 10111A19 S_BUFFER_LOAD_DWORD s16, s[4:7], 2 ; C2080502 S_WAITCNT expcnt(0) lgkmcnt(0) ; BF8C000F V_MUL_F32_e32 v16, s16, v12 ; 10201810 S_BUFFER_LOAD_DWORD s17, s[4:7], 6 ; C2088506 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v16, s17, v14, v16, 0, 0, 0, 0 ; D2820010 04421C11 S_BUFFER_LOAD_DWORD s18, s[4:7], 10 ; C209050A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v16, s18, v15, v16, 0, 0, 0, 0 ; D2820010 04421E12 V_MUL_F32_e32 v17, s16, v11 ; 10221610 V_MAD_F32 v17, s17, v10, v17, 0, 0, 0, 0 ; D2820011 04461411 V_MAD_F32 v17, s18, v13, v17, 0, 0, 0, 0 ; D2820011 04461A12 V_MUL_F32_e32 v17, v17, v18 ; 10222511 V_MUL_F32_e32 v24, s16, v24 ; 10303010 V_MAD_F32 v23, s17, v23, v24, 0, 0, 0, 0 ; D2820017 04622E11 V_MAD_F32 v22, s18, v22, v23, 0, 0, 0, 0 ; D2820016 045E2C12 V_MAD_F32 v17, v22, v19, v17, 0, 0, 0, 0 ; D2820011 04462716 V_MAD_F32 v16, v16, v20, v17, 0, 0, 0, 0 ; D2820010 04462910 S_LOAD_DWORDX4 s[20:23], s[8:9], 24 ; C08A0918 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[17:20], s[20:23][v1] + 0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80051101 S_WAITCNT vmcnt(0) ; BF8C0770 EXP 15, 33, 0, 0, 0, v16, v17, v18, v19 ; F800021F 13121110 S_WAITCNT expcnt(0) ; BF8C070F V_MUL_F32_e32 v16, v2, v2 ; 10200502 V_MAD_F32 v16, v3, v3, v16, 0, 0, 0, 0 ; D2820010 04420703 V_MAD_F32 v2, v4, v4, v16, 0, 0, 0, 0 ; D2820002 04420904 V_RSQ_LEGACY_F32_e32 v3, v2 ; 7E065B02 V_MUL_F32_e32 v3, v3, v2 ; 10060503 V_XOR_B32_e32 v2, -2147483648, v2 ; 3A0404FF 80000000 V_CMP_GT_F32_e64 s[2:3], 0, v2, 0, 0, 0, 0 ; D0080002 02020480 V_CNDMASK_B32_e64 v2, 0.000000e+00, v3, s[2:3], 0, 0, 0, 0 ; D2000002 000A0680 V_MUL_F32_e32 v3, v14, v2 ; 1006050E V_MUL_F32_e32 v4, v12, v2 ; 1008050C V_MUL_F32_e32 v5, s10, v4 ; 100A080A V_MAD_F32 v5, s11, v3, v5, 0, 0, 0, 0 ; D2820005 0416060B V_MUL_F32_e32 v12, v15, v2 ; 1018050F V_MAD_F32 v5, s12, v12, v5, 0, 0, 0, 0 ; D2820005 0416180C V_MUL_F32_e32 v10, v10, v2 ; 1014050A V_MUL_F32_e32 v11, v11, v2 ; 1016050B V_MUL_F32_e32 v14, s10, v11 ; 101C160A V_MAD_F32 v14, s11, v10, v14, 0, 0, 0, 0 ; D282000E 043A140B V_MUL_F32_e32 v2, v13, v2 ; 1004050D V_MAD_F32 v13, s12, v2, v14, 0, 0, 0, 0 ; D282000D 043A040C S_LOAD_DWORDX4 s[20:23], s[8:9], 12 ; C08A090C S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[14:17], s[20:23][v1] + 0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80050E01 S_LOAD_DWORDX4 s[0:3], s[0:1], 4 ; C0800104 S_WAITCNT vmcnt(0) lgkmcnt(0) ; BF8C0070 S_BUFFER_LOAD_DWORD s19, s[0:3], 81 ; C2098151 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v1, s19 ; 7E020213 V_SUB_F32_e64 v1, v15, v1, 0, 0, 0, 0 ; D2080001 0202030F S_BUFFER_LOAD_DWORD s19, s[0:3], 80 ; C2098150 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v18, s19 ; 7E240213 V_SUB_F32_e64 v18, v14, v18, 0, 0, 0, 0 ; D2080012 0202250E V_MUL_F32_e32 v18, v18, v18 ; 10242512 V_MAD_F32 v1, v1, v1, v18, 0, 0, 0, 0 ; D2820001 044A0301 S_BUFFER_LOAD_DWORD s19, s[0:3], 82 ; C2098152 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MOV_B32_e32 v18, s19 ; 7E240213 V_SUB_F32_e64 v18, v16, v18, 0, 0, 0, 0 ; D2080012 02022510 V_MAD_F32 v1, v18, v18, v1, 0, 0, 0, 0 ; D2820001 04062512 V_RSQ_LEGACY_F32_e32 v18, v1 ; 7E245B01 V_MUL_F32_e32 v18, v18, v1 ; 10240312 V_XOR_B32_e32 v1, -2147483648, v1 ; 3A0202FF 80000000 V_CMP_GT_F32_e64 s[20:21], 0, v1, 0, 0, 0, 0 ; D0080014 02020280 V_CNDMASK_B32_e64 v1, 0.000000e+00, v18, s[20:21], 0, 0, 0, 0 ; D2000001 00522480 S_BUFFER_LOAD_DWORD s19, s[4:7], 16 ; C2098510 V_MOV_B32_e32 v18, -8.000000e-01 ; 7E2402FF BF4CCCCD S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v1, s19, v18, v1, 0, 0, 0, 0 ; D2820001 04062413 V_MOV_B32_e32 v19, s19 ; 7E260213 V_MAD_F32 v18, s19, v18, v19, 0, 0, 0, 0 ; D2820012 044E2413 V_RCP_F32_e32 v18, v18 ; 7E245512 V_MUL_F32_e32 v1, v1, v18 ; 10022501 V_ADD_F32_e64 v1, 0, v1, 0, 1, 0, 0 ; D2060801 02020280 V_ADD_F32_e32 v18, v1, v1 ; 06240301 V_SUB_F32_e32 v18, 3.000000e+00, v18 ; 082424FF 40400000 V_MUL_F32_e32 v18, v1, v18 ; 10242501 V_MUL_F32_e32 v1, v1, v18 ; 10022501 V_SUB_F32_e32 v1, 1.000000e+00, v1 ; 080202F2 S_LOAD_DWORDX4 s[20:23], s[8:9], 0 ; C08A0900 S_WAITCNT lgkmcnt(0) ; BF8C007F BUFFER_LOAD_FORMAT_XYZW v[18:21], s[20:23][v0] + 0 + 0, glc=0, slc=0, tfe=0 ; E00C2000 80051200 S_WAITCNT vmcnt(0) ; BF8C0770 V_MUL_F32_e32 v0, v18, v1 ; 10000312 V_MUL_F32_e32 v13, v13, v0 ; 101A010D V_MUL_F32_e32 v22, v19, v1 ; 102C0313 V_MUL_F32_e32 v23, s10, v6 ; 102E0C0A V_MAD_F32 v23, s11, v7, v23, 0, 0, 0, 0 ; D2820017 045E0E0B V_MAD_F32 v23, s12, v8, v23, 0, 0, 0, 0 ; D2820017 045E100C V_MAD_F32 v13, v23, v22, v13, 0, 0, 0, 0 ; D282000D 04362D17 V_MUL_F32_e32 v1, v20, v1 ; 10020314 V_MAD_F32 v5, v5, v1, v13, 0, 0, 0, 0 ; D2820005 04360305 V_MUL_F32_e32 v13, s10, v14 ; 101A1C0A V_MAD_F32 v13, s11, v15, v13, 0, 0, 0, 0 ; D282000D 04361E0B V_MAD_F32 v13, s12, v16, v13, 0, 0, 0, 0 ; D282000D 0436200C S_BUFFER_LOAD_DWORD s8, s[4:7], 13 ; C204050D S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v13, s8, v13 ; 061A1A08 V_ADD_F32_e32 v5, v5, v13 ; 060A1B05 V_CMP_U_F32_e64 s[8:9], v19, v19, 0, 0, 0, 0 ; D0100008 02022713 V_CMP_LE_F32_e64 s[10:11], v19, 0.000000e+00, 0, 0, 0, 0 ; D006000A 02010113 S_OR_B64 s[8:9], s[10:11], s[8:9] ; 8888080A V_CNDMASK_B32_e64 v13, v19, 0.000000e+00, s[8:9], 0, 0, 0, 0 ; D200000D 00210113 V_MUL_F32_e32 v18, 0.000000e+00, v13 ; 10241A80 V_MOV_B32_e32 v19, 1.000000e-01 ; 7E2602FF 3DCCCCCD V_MAD_F32 v5, v18, v19, v5, 0, 0, 0, 0 ; D2820005 04162712 V_MUL_F32_e32 v18, s13, v4 ; 1024080D V_MAD_F32 v18, s14, v3, v18, 0, 0, 0, 0 ; D2820012 044A060E V_MAD_F32 v18, s15, v12, v18, 0, 0, 0, 0 ; D2820012 044A180F V_MUL_F32_e32 v20, s13, v11 ; 1028160D V_MAD_F32 v20, s14, v10, v20, 0, 0, 0, 0 ; D2820014 0452140E V_MAD_F32 v20, s15, v2, v20, 0, 0, 0, 0 ; D2820014 0452040F V_MUL_F32_e32 v20, v20, v0 ; 10280114 V_MUL_F32_e32 v21, s13, v6 ; 102A0C0D V_MAD_F32 v21, s14, v7, v21, 0, 0, 0, 0 ; D2820015 04560E0E V_MAD_F32 v21, s15, v8, v21, 0, 0, 0, 0 ; D2820015 0456100F V_MAD_F32 v20, v21, v22, v20, 0, 0, 0, 0 ; D2820014 04522D15 V_MAD_F32 v18, v18, v1, v20, 0, 0, 0, 0 ; D2820012 04520312 V_MUL_F32_e32 v20, s13, v14 ; 10281C0D V_MAD_F32 v20, s14, v15, v20, 0, 0, 0, 0 ; D2820014 04521E0E V_MAD_F32 v20, s15, v16, v20, 0, 0, 0, 0 ; D2820014 0452200F S_BUFFER_LOAD_DWORD s8, s[4:7], 12 ; C204050C S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v20, s8, v20 ; 06282808 V_ADD_F32_e32 v18, v18, v20 ; 06242912 V_ADD_F32_e32 v20, v14, v16 ; 0628210E V_MUL_F32_e32 v20, 1042479491, v20 ; 102828FF 3E22F983 V_COS_F32_e32 v20, v20 ; 7E286D14 S_BUFFER_LOAD_DWORD s8, s[0:3], 92 ; C204015C S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v21, s8, v14 ; 062A1C08 V_ADD_F32_e32 v21, v21, v15 ; 062A1F15 V_ADD_F32_e32 v21, v21, v16 ; 062A2115 V_MUL_F32_e32 v21, 1042479491, v21 ; 102A2AFF 3E22F983 V_COS_F32_e32 v21, v21 ; 7E2A6D15 V_MUL_F32_e32 v20, v21, v20 ; 10282915 V_MUL_F32_e32 v20, v20, v13 ; 10281B14 V_MAD_F32 v18, v20, v19, v18, 0, 0, 0, 0 ; D2820012 044A2714 S_BUFFER_LOAD_DWORD s8, s[0:3], 2 ; C2040102 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v20, s8, v18 ; 10282408 S_BUFFER_LOAD_DWORD s8, s[0:3], 6 ; C2040106 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v20, s8, v5, v20, 0, 0, 0, 0 ; D2820014 04520A08 V_MUL_F32_e32 v23, s16, v4 ; 102E0810 V_MAD_F32 v23, s17, v3, v23, 0, 0, 0, 0 ; D2820017 045E0611 V_MAD_F32 v23, s18, v12, v23, 0, 0, 0, 0 ; D2820017 045E1812 V_MUL_F32_e32 v24, s16, v11 ; 10301610 V_MAD_F32 v24, s17, v10, v24, 0, 0, 0, 0 ; D2820018 04621411 V_MAD_F32 v24, s18, v2, v24, 0, 0, 0, 0 ; D2820018 04620412 V_MUL_F32_e32 v24, v24, v0 ; 10300118 V_MUL_F32_e32 v25, s16, v6 ; 10320C10 V_MAD_F32 v25, s17, v7, v25, 0, 0, 0, 0 ; D2820019 04660E11 V_MAD_F32 v25, s18, v8, v25, 0, 0, 0, 0 ; D2820019 04661012 V_MAD_F32 v24, v25, v22, v24, 0, 0, 0, 0 ; D2820018 04622D19 V_MAD_F32 v23, v23, v1, v24, 0, 0, 0, 0 ; D2820017 04620317 V_MUL_F32_e32 v24, s16, v14 ; 10301C10 V_MAD_F32 v24, s17, v15, v24, 0, 0, 0, 0 ; D2820018 04621E11 V_MAD_F32 v24, s18, v16, v24, 0, 0, 0, 0 ; D2820018 04622012 S_BUFFER_LOAD_DWORD s8, s[4:7], 14 ; C204050E S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v24, s8, v24 ; 06303008 V_ADD_F32_e32 v23, v23, v24 ; 062E3117 V_ADD_F32_e32 v24, v15, v16 ; 0630210F V_MUL_F32_e32 v24, 1042479491, v24 ; 103030FF 3E22F983 V_COS_F32_e32 v24, v24 ; 7E306D18 V_MUL_F32_e32 v21, v21, v24 ; 102A3115 V_MUL_F32_e32 v13, v21, v13 ; 101A1B15 V_MAD_F32 v13, v13, v19, v23, 0, 0, 0, 0 ; D282000D 045E270D S_BUFFER_LOAD_DWORD s8, s[0:3], 10 ; C204010A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v19, s8, v13, v20, 0, 0, 0, 0 ; D2820013 04521A08 S_BUFFER_LOAD_DWORD s8, s[4:7], 3 ; C2040503 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v4, s8, v4 ; 10080808 S_BUFFER_LOAD_DWORD s9, s[4:7], 7 ; C2048507 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v3, s9, v3, v4, 0, 0, 0, 0 ; D2820003 04120609 S_BUFFER_LOAD_DWORD s10, s[4:7], 11 ; C205050B S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v3, s10, v12, v3, 0, 0, 0, 0 ; D2820003 040E180A V_MUL_F32_e32 v4, s8, v11 ; 10081608 V_MAD_F32 v4, s9, v10, v4, 0, 0, 0, 0 ; D2820004 04121409 V_MAD_F32 v2, s10, v2, v4, 0, 0, 0, 0 ; D2820002 0412040A V_MUL_F32_e32 v0, v2, v0 ; 10000102 V_MUL_F32_e32 v2, s8, v6 ; 10040C08 V_MAD_F32 v2, s9, v7, v2, 0, 0, 0, 0 ; D2820002 040A0E09 V_MAD_F32 v2, s10, v8, v2, 0, 0, 0, 0 ; D2820002 040A100A V_MAD_F32 v0, v2, v22, v0, 0, 0, 0, 0 ; D2820000 04022D02 V_MAD_F32 v0, v3, v1, v0, 0, 0, 0, 0 ; D2820000 04020303 V_MUL_F32_e32 v1, s8, v14 ; 10021C08 V_MAD_F32 v1, s9, v15, v1, 0, 0, 0, 0 ; D2820001 04061E09 V_MAD_F32 v1, s10, v16, v1, 0, 0, 0, 0 ; D2820001 0406200A S_BUFFER_LOAD_DWORD s4, s[4:7], 15 ; C202050F S_WAITCNT lgkmcnt(0) ; BF8C007F V_ADD_F32_e32 v1, s4, v1 ; 06020204 V_ADD_F32_e32 v0, v0, v1 ; 06000300 S_BUFFER_LOAD_DWORD s4, s[0:3], 14 ; C202010E S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v1, s4, v0, v19, 0, 0, 0, 0 ; D2820001 044E0004 S_BUFFER_LOAD_DWORD s4, s[0:3], 1 ; C2020101 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v2, s4, v18 ; 10042404 S_BUFFER_LOAD_DWORD s4, s[0:3], 5 ; C2020105 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v2, s4, v5, v2, 0, 0, 0, 0 ; D2820002 040A0A04 S_BUFFER_LOAD_DWORD s4, s[0:3], 9 ; C2020109 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v2, s4, v13, v2, 0, 0, 0, 0 ; D2820002 040A1A04 S_BUFFER_LOAD_DWORD s4, s[0:3], 13 ; C202010D S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v2, s4, v0, v2, 0, 0, 0, 0 ; D2820002 040A0004 S_BUFFER_LOAD_DWORD s4, s[0:3], 0 ; C2020100 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v3, s4, v18 ; 10062404 S_BUFFER_LOAD_DWORD s4, s[0:3], 4 ; C2020104 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v3, s4, v5, v3, 0, 0, 0, 0 ; D2820003 040E0A04 S_BUFFER_LOAD_DWORD s4, s[0:3], 8 ; C2020108 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v3, s4, v13, v3, 0, 0, 0, 0 ; D2820003 040E1A04 S_BUFFER_LOAD_DWORD s4, s[0:3], 12 ; C202010C S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v3, s4, v0, v3, 0, 0, 0, 0 ; D2820003 040E0004 EXP 15, 34, 0, 0, 0, v3, v2, v1, v0 ; F800022F 00010203 S_BUFFER_LOAD_DWORD s4, s[0:3], 35 ; C2020123 S_WAITCNT expcnt(0) lgkmcnt(0) ; BF8C000F V_MUL_F32_e32 v1, s4, v18 ; 10022404 S_BUFFER_LOAD_DWORD s4, s[0:3], 39 ; C2020127 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v1, s4, v5, v1, 0, 0, 0, 0 ; D2820001 04060A04 S_BUFFER_LOAD_DWORD s4, s[0:3], 43 ; C202012B S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v1, s4, v13, v1, 0, 0, 0, 0 ; D2820001 04061A04 S_BUFFER_LOAD_DWORD s4, s[0:3], 47 ; C202012F S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v1, s4, v0, v1, 0, 0, 0, 0 ; D2820001 04060004 S_BUFFER_LOAD_DWORD s4, s[0:3], 34 ; C2020122 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v2, s4, v18 ; 10042404 S_BUFFER_LOAD_DWORD s4, s[0:3], 38 ; C2020126 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v2, s4, v5, v2, 0, 0, 0, 0 ; D2820002 040A0A04 S_BUFFER_LOAD_DWORD s4, s[0:3], 42 ; C202012A S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v2, s4, v13, v2, 0, 0, 0, 0 ; D2820002 040A1A04 S_BUFFER_LOAD_DWORD s4, s[0:3], 46 ; C202012E S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v2, s4, v0, v2, 0, 0, 0, 0 ; D2820002 040A0004 S_BUFFER_LOAD_DWORD s4, s[0:3], 33 ; C2020121 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v3, s4, v18 ; 10062404 S_BUFFER_LOAD_DWORD s4, s[0:3], 37 ; C2020125 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v3, s4, v5, v3, 0, 0, 0, 0 ; D2820003 040E0A04 S_BUFFER_LOAD_DWORD s4, s[0:3], 41 ; C2020129 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v3, s4, v13, v3, 0, 0, 0, 0 ; D2820003 040E1A04 S_BUFFER_LOAD_DWORD s4, s[0:3], 45 ; C202012D S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v3, s4, v0, v3, 0, 0, 0, 0 ; D2820003 040E0004 S_BUFFER_LOAD_DWORD s4, s[0:3], 32 ; C2020120 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MUL_F32_e32 v4, s4, v18 ; 10082404 S_BUFFER_LOAD_DWORD s4, s[0:3], 36 ; C2020124 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v4, s4, v5, v4, 0, 0, 0, 0 ; D2820004 04120A04 S_BUFFER_LOAD_DWORD s4, s[0:3], 40 ; C2020128 S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v4, s4, v13, v4, 0, 0, 0, 0 ; D2820004 04121A04 S_BUFFER_LOAD_DWORD s0, s[0:3], 44 ; C200012C S_WAITCNT lgkmcnt(0) ; BF8C007F V_MAD_F32 v0, s0, v0, v4, 0, 0, 0, 0 ; D2820000 04120000 EXP 15, 12, 0, 1, 0, v0, v3, v2, v1 ; F80008CF 01020300 S_ENDPGM ; BF810000