From d3243936674e8cee79f849c459e502f8cc9031fe Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Wed, 30 Apr 2014 09:28:34 +0100 Subject: [PATCH] drm/i915/dp: Add in a few more failure messages Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/intel_dp.c | 47 +++++++++++++++++++++++++------------- drivers/gpu/drm/i915/intel_drv.h | 6 ++--- 2 files changed, 34 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 8180569..f179286 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -2568,7 +2568,7 @@ static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp) } /* Enable corresponding port and start training pattern 1 */ -void +bool intel_dp_start_link_train(struct intel_dp *intel_dp) { struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base; @@ -2587,11 +2587,16 @@ intel_dp_start_link_train(struct intel_dp *intel_dp) link_config[1] = intel_dp->lane_count; if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; - drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2); + if (drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2) != 2) { + DRM_ERROR("failed to setup link config(bw=%d, lane_count=%d)\n", + intel_dp->link_bw, intel_dp->lane_count); + return false; + } link_config[0] = 0; link_config[1] = DP_SET_ANSI_8B10B; - drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2); + if (drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2) != 2) + DRM_ERROR("failed to disable downspread control, ignoring\n"); DP |= DP_PORT_EN; @@ -2600,7 +2605,7 @@ intel_dp_start_link_train(struct intel_dp *intel_dp) DP_TRAINING_PATTERN_1 | DP_LINK_SCRAMBLING_DISABLE)) { DRM_ERROR("failed to enable link training\n"); - return; + return false; } voltage = 0xff; @@ -2612,7 +2617,7 @@ intel_dp_start_link_train(struct intel_dp *intel_dp) drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd); if (!intel_dp_get_link_status(intel_dp, link_status)) { DRM_ERROR("failed to get link status\n"); - break; + return false; } if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { @@ -2628,7 +2633,7 @@ intel_dp_start_link_train(struct intel_dp *intel_dp) ++loop_tries; if (loop_tries == 5) { DRM_ERROR("too many full retries, give up\n"); - break; + return false; } intel_dp_reset_link_train(intel_dp, &DP, DP_TRAINING_PATTERN_1 | @@ -2642,7 +2647,7 @@ intel_dp_start_link_train(struct intel_dp *intel_dp) ++voltage_tries; if (voltage_tries == 5) { DRM_ERROR("too many voltage retries, give up\n"); - break; + return false; } } else voltage_tries = 0; @@ -2651,14 +2656,15 @@ intel_dp_start_link_train(struct intel_dp *intel_dp) /* Update training set as requested by target */ if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) { DRM_ERROR("failed to update link training\n"); - break; + return false; } } intel_dp->DP = DP; + return true; } -void +bool intel_dp_complete_link_train(struct intel_dp *intel_dp) { bool channel_eq = false; @@ -2675,7 +2681,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp) training_pattern | DP_LINK_SCRAMBLING_DISABLE)) { DRM_ERROR("failed to start channel equalization\n"); - return; + return false; } tries = 0; @@ -2697,7 +2703,11 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp) /* Make sure clock is still ok */ if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { - intel_dp_start_link_train(intel_dp); + if (!intel_dp_start_link_train(intel_dp)) { + DRM_ERROR("failed to start link training, aborting\n"); + break; + } + intel_dp_set_link_train(intel_dp, &DP, training_pattern | DP_LINK_SCRAMBLING_DISABLE); @@ -2713,7 +2723,12 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp) /* Try 5 times, then try clock recovery if that fails */ if (tries > 5) { intel_dp_link_down(intel_dp); - intel_dp_start_link_train(intel_dp); + + if (!intel_dp_start_link_train(intel_dp)) { + DRM_ERROR("failed to start link training, aborting\n"); + break; + } + intel_dp_set_link_train(intel_dp, &DP, training_pattern | DP_LINK_SCRAMBLING_DISABLE); @@ -2736,13 +2751,13 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp) if (channel_eq) DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n"); - + return channel_eq; } -void intel_dp_stop_link_train(struct intel_dp *intel_dp) +bool intel_dp_stop_link_train(struct intel_dp *intel_dp) { - intel_dp_set_link_train(intel_dp, &intel_dp->DP, - DP_TRAINING_PATTERN_DISABLE); + return intel_dp_set_link_train(intel_dp, &intel_dp->DP, + DP_TRAINING_PATTERN_DISABLE); } static void diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index c666e1d..5b78203 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -785,9 +785,9 @@ int intel_format_to_fourcc(int format); void intel_dp_init(struct drm_device *dev, int output_reg, enum port port); bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port, struct intel_connector *intel_connector); -void intel_dp_start_link_train(struct intel_dp *intel_dp); -void intel_dp_complete_link_train(struct intel_dp *intel_dp); -void intel_dp_stop_link_train(struct intel_dp *intel_dp); +bool intel_dp_start_link_train(struct intel_dp *intel_dp); +bool intel_dp_complete_link_train(struct intel_dp *intel_dp); +bool intel_dp_stop_link_train(struct intel_dp *intel_dp); void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode); void intel_dp_encoder_destroy(struct drm_encoder *encoder); void intel_dp_check_link_status(struct intel_dp *intel_dp); -- 1.7.9.5