From 1c90e04a3836813b48f225efe5dfa23abe286200 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Fri, 16 May 2014 20:31:45 +0100 Subject: [PATCH] drm/i915: Prevent updating the HWS register while it is being read " bit 0 of HWS_PGA [0x2080] [g4x/ilk] This field indicates that the translation for the hardware status page from the graphics virtual address to the physical address is pending. Software can use this indicator to prevent updating the status page when there is a pending cycle for translation." Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/intel_ringbuffer.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index f382efc..cb6d510 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -1057,6 +1057,12 @@ void intel_ring_setup_status_page(struct intel_ring_buffer *ring) } } + if (IS_GEN5(dev) || IS_G4X(dev)) { + if (wait_for((I915_READ(mmio) & 1) == 0, 1000)) + DRM_ERROR("%s: wait for Translation-in-Progress to complete for HWS timed out\n", + ring->name); + } + I915_WRITE(mmio, addr); POSTING_READ(mmio); -- 1.7.9.5