[ 298.702336] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 298.702337] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 298.702338] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch [ 298.702339] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1 [ 298.702354] [drm:intel_update_fbc] no output, disabling [ 298.736119] [drm:intel_disable_shared_dpll] disable PCH DPLL A (active 1, on? 1) for crtc 5 [ 298.736129] [drm:intel_disable_shared_dpll] disabling PCH DPLL A [ 298.736554] [drm:ivb_modeset_global_resources] disabling fdi C rx [ 298.736559] [drm:check_encoder_state] [ENCODER:14:DAC-14] [ 298.736562] [drm:check_encoder_state] [ENCODER:15:TMDS-15] [ 298.736564] [drm:check_encoder_state] [ENCODER:19:TMDS-19] [ 298.736567] [drm:check_encoder_state] [ENCODER:21:TMDS-21] [ 298.736569] [drm:check_encoder_state] [ENCODER:23:TMDS-23] [ 298.736572] [drm:check_crtc_state] [CRTC:5] [ 298.736573] [drm:check_crtc_state] [CRTC:8] [ 298.736574] [drm:check_crtc_state] [CRTC:11] [ 298.736575] [drm:check_shared_dpll_state] PCH DPLL A [ 298.736580] [drm:check_shared_dpll_state] PCH DPLL B [ 298.736588] [drm:drm_mode_setcrtc] [CRTC:5] [ 298.736590] [drm:drm_mode_setcrtc] [CONNECTOR:13:VGA-1] [ 298.736592] [drm:intel_crtc_set_config] [CRTC:5] [FB:37] #connectors=1 (x y) (0 0) [ 298.736593] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set [ 298.736594] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:5], mode_changed=1, fb_changed=0 [ 298.736595] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 298.736597] [drm:intel_modeset_stage_output_state] [CONNECTOR:13:VGA-1] to [CRTC:5] [ 298.736598] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 298.736599] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch [ 298.736600] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 298.736602] [drm:connected_sink_compute_bpp] [CONNECTOR:13:VGA-1] checking for sink bpp constrains [ 298.736603] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1 [ 298.736604] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0 [ 298.736605] [drm:intel_dump_pipe_config] [CRTC:5][modeset] config for pipe A [ 298.736606] [drm:intel_dump_pipe_config] cpu_transcoder: A [ 298.736607] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 298.736609] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 3029219, gmch_n: 4194304, link_m: 126217, link_n: 524288, tu: 64 [ 298.736610] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 298.736611] [drm:intel_dump_pipe_config] requested mode: [ 298.736613] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x48 0xa [ 298.736614] [drm:intel_dump_pipe_config] adjusted mode: [ 298.736616] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x48 0xa [ 298.736617] [drm:intel_dump_crtc_timings] crtc timings: 65000 1024 1048 1184 1344 768 771 777 806, type: 0x48 flags: 0xa [ 298.736618] [drm:intel_dump_pipe_config] port clock: 65000 [ 298.736619] [drm:intel_dump_pipe_config] pipe src size: 1024x768 [ 298.736621] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 298.736622] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 298.736623] [drm:intel_dump_pipe_config] ips: 0 [ 298.736624] [drm:intel_dump_pipe_config] double wide: 0 [ 298.736630] [drm:ivb_modeset_global_resources] disabling fdi C rx [ 298.736642] [drm:intel_get_shared_dpll] CRTC:5 allocated PCH DPLL A [ 298.736643] [drm:intel_get_shared_dpll] using PCH DPLL A for pipe A [ 298.736644] [drm:intel_prepare_shared_dpll] setting up PCH DPLL A [ 298.736654] [drm:ironlake_update_primary_plane] Writing base 007A2000 00000000 0 0 4096 [ 298.737352] [drm:ivb_manual_fdi_link_train] FDI_RX_IIR before link train 0x0 [ 298.737361] [drm:ivb_manual_fdi_link_train] FDI_RX_IIR 0x100 [ 298.737363] [drm:ivb_manual_fdi_link_train] FDI train 1 done, level 0. [ 298.737371] [drm:ivb_manual_fdi_link_train] FDI_RX_IIR 0x600 [ 298.737373] [drm:ivb_manual_fdi_link_train] FDI train 2 done, level 0. [ 298.737374] [drm:ivb_manual_fdi_link_train] FDI train done. [ 298.737377] [drm:intel_enable_shared_dpll] enable PCH DPLL A (active 0, on? 0)for crtc 5 [ 298.737378] [drm:intel_enable_shared_dpll] enabling PCH DPLL A [ 298.739259] [drm:intel_update_fbc] disabled per chip default [ 298.739265] [drm:intel_connector_check_state] [CONNECTOR:13:VGA-1] [ 298.739271] [drm:check_encoder_state] [ENCODER:14:DAC-14] [ 298.739274] [drm:check_encoder_state] [ENCODER:15:TMDS-15] [ 298.739276] [drm:check_encoder_state] [ENCODER:19:TMDS-19] [ 298.739279] [drm:check_encoder_state] [ENCODER:21:TMDS-21] [ 298.739281] [drm:check_encoder_state] [ENCODER:23:TMDS-23] [ 298.739284] [drm:check_crtc_state] [CRTC:5] [ 298.739295] [drm:check_crtc_state] [CRTC:8] [ 298.739296] [drm:check_crtc_state] [CRTC:11] [ 298.739297] [drm:check_shared_dpll_state] PCH DPLL A [ 298.739301] [drm:check_shared_dpll_state] PCH DPLL B [ 298.739317] [drm:intel_crtc_page_flip] flip queue: crtc already busy [ 298.739332] [drm:drm_mode_addfb] [FB:36] [ 298.739334] [drm:intel_crtc_set_config] [CRTC:5] [NOFB] [ 298.739335] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:5], mode_changed=1, fb_changed=0 [ 298.739337] [drm:intel_modeset_stage_output_state] [CONNECTOR:13:VGA-1] to [NOCRTC] [ 298.739338] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 298.739339] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 298.739340] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch [ 298.739341] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1 [ 298.739349] [drm:intel_update_fbc] no output, disabling [ 298.773120] [drm:intel_disable_shared_dpll] disable PCH DPLL A (active 1, on? 1) for crtc 5 [ 298.773128] [drm:intel_disable_shared_dpll] disabling PCH DPLL A [ 298.773552] [drm:ivb_modeset_global_resources] disabling fdi C rx [ 298.773559] [drm:check_encoder_state] [ENCODER:14:DAC-14] [ 298.773561] [drm:check_encoder_state] [ENCODER:15:TMDS-15] [ 298.773563] [drm:check_encoder_state] [ENCODER:19:TMDS-19] [ 298.773566] [drm:check_encoder_state] [ENCODER:21:TMDS-21] [ 298.773568] [drm:check_encoder_state] [ENCODER:23:TMDS-23] [ 298.773571] [drm:check_crtc_state] [CRTC:5] [ 298.773572] [drm:check_crtc_state] [CRTC:8] [ 298.773573] [drm:check_crtc_state] [CRTC:11] [ 298.773574] [drm:check_shared_dpll_state] PCH DPLL A [ 298.773578] [drm:check_shared_dpll_state] PCH DPLL B [ 298.773587] [drm:drm_mode_setcrtc] [CRTC:5] [ 298.773589] [drm:drm_mode_setcrtc] [CONNECTOR:13:VGA-1] [ 298.773591] [drm:intel_crtc_set_config] [CRTC:5] [FB:39] #connectors=1 (x y) (0 0) [ 298.773592] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set [ 298.773593] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:5], mode_changed=1, fb_changed=0 [ 298.773594] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 298.773595] [drm:intel_modeset_stage_output_state] [CONNECTOR:13:VGA-1] to [CRTC:5] [ 298.773596] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 298.773597] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch [ 298.773599] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 298.773600] [drm:connected_sink_compute_bpp] [CONNECTOR:13:VGA-1] checking for sink bpp constrains [ 298.773602] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1 [ 298.773603] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0 [ 298.773604] [drm:intel_dump_pipe_config] [CRTC:5][modeset] config for pipe A [ 298.773605] [drm:intel_dump_pipe_config] cpu_transcoder: A [ 298.773606] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 298.773608] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 3029219, gmch_n: 4194304, link_m: 126217, link_n: 524288, tu: 64 [ 298.773609] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 298.773610] [drm:intel_dump_pipe_config] requested mode: [ 298.773612] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x48 0xa [ 298.773613] [drm:intel_dump_pipe_config] adjusted mode: [ 298.773614] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x48 0xa [ 298.773616] [drm:intel_dump_crtc_timings] crtc timings: 65000 1024 1048 1184 1344 768 771 777 806, type: 0x48 flags: 0xa [ 298.773617] [drm:intel_dump_pipe_config] port clock: 65000 [ 298.773618] [drm:intel_dump_pipe_config] pipe src size: 1024x768 [ 298.773619] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 298.773620] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 298.773621] [drm:intel_dump_pipe_config] ips: 0 [ 298.773622] [drm:intel_dump_pipe_config] double wide: 0 [ 298.773628] [drm:ivb_modeset_global_resources] disabling fdi C rx [ 298.773641] [drm:intel_get_shared_dpll] CRTC:5 allocated PCH DPLL A [ 298.773642] [drm:intel_get_shared_dpll] using PCH DPLL A for pipe A [ 298.773643] [drm:intel_prepare_shared_dpll] setting up PCH DPLL A [ 298.773651] [drm:ironlake_update_primary_plane] Writing base 004A2000 00000000 0 0 4096 [ 298.774341] [drm:ivb_manual_fdi_link_train] FDI_RX_IIR before link train 0x0 [ 298.774349] [drm:ivb_manual_fdi_link_train] FDI_RX_IIR 0x100 [ 298.774351] [drm:ivb_manual_fdi_link_train] FDI train 1 done, level 0. [ 298.774358] [drm:ivb_manual_fdi_link_train] FDI_RX_IIR 0x600 [ 298.774360] [drm:ivb_manual_fdi_link_train] FDI train 2 done, level 0. [ 298.774361] [drm:ivb_manual_fdi_link_train] FDI train done. [ 298.774365] [drm:intel_enable_shared_dpll] enable PCH DPLL A (active 0, on? 0)for crtc 5 [ 298.774366] [drm:intel_enable_shared_dpll] enabling PCH DPLL A [ 298.776248] [drm:intel_update_fbc] disabled per chip default [ 298.776254] [drm:intel_connector_check_state] [CONNECTOR:13:VGA-1] [ 298.776259] [drm:check_encoder_state] [ENCODER:14:DAC-14] [ 298.776262] [drm:check_encoder_state] [ENCODER:15:TMDS-15] [ 298.776265] [drm:check_encoder_state] [ENCODER:19:TMDS-19] [ 298.776267] [drm:check_encoder_state] [ENCODER:21:TMDS-21] [ 298.776270] [drm:check_encoder_state] [ENCODER:23:TMDS-23] [ 298.776272] [drm:check_crtc_state] [CRTC:5] [ 298.776284] [drm:check_crtc_state] [CRTC:8] [ 298.776285] [drm:check_crtc_state] [CRTC:11] [ 298.776286] [drm:check_shared_dpll_state] PCH DPLL A [ 298.776290] [drm:check_shared_dpll_state] PCH DPLL B [ 298.776306] [drm:intel_crtc_page_flip] flip queue: crtc already busy [ 298.776321] [drm:drm_mode_addfb] [FB:37] [ 298.776323] [drm:intel_crtc_set_config] [CRTC:5] [NOFB] [ 298.776324] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:5], mode_changed=1, fb_changed=0 [ 298.776326] [drm:intel_modeset_stage_output_state] [CONNECTOR:13:VGA-1] to [NOCRTC] [ 298.776327] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 298.776327] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 298.776328] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch [ 298.776330] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1 [ 298.776339] [drm:intel_update_fbc] no output, disabling [ 298.810117] [drm:intel_disable_shared_dpll] disable PCH DPLL A (active 1, on? 1) for crtc 5 [ 298.810126] [drm:intel_disable_shared_dpll] disabling PCH DPLL A [ 298.810552] [drm:ivb_modeset_global_resources] disabling fdi C rx [ 298.810560] [drm:check_encoder_state] [ENCODER:14:DAC-14] [ 298.810563] [drm:check_encoder_state] [ENCODER:15:TMDS-15] [ 298.810565] [drm:check_encoder_state] [ENCODER:19:TMDS-19] [ 298.810568] [drm:check_encoder_state] [ENCODER:21:TMDS-21] [ 298.810570] [drm:check_encoder_state] [ENCODER:23:TMDS-23] [ 298.810572] [drm:check_crtc_state] [CRTC:5] [ 298.810573] [drm:check_crtc_state] [CRTC:8] [ 298.810574] [drm:check_crtc_state] [CRTC:11] [ 298.810575] [drm:check_shared_dpll_state] PCH DPLL A [ 298.810580] [drm:check_shared_dpll_state] PCH DPLL B [ 298.810588] [drm:drm_mode_setcrtc] [CRTC:5] [ 298.810591] [drm:drm_mode_setcrtc] [CONNECTOR:13:VGA-1] [ 298.810592] [drm:intel_crtc_set_config] [CRTC:5] [FB:36] #connectors=1 (x y) (0 0) [ 298.810593] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set [ 298.810595] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:5], mode_changed=1, fb_changed=0 [ 298.810596] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 298.810597] [drm:intel_modeset_stage_output_state] [CONNECTOR:13:VGA-1] to [CRTC:5] [ 298.810598] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 298.810599] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch [ 298.810600] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 298.810602] [drm:connected_sink_compute_bpp] [CONNECTOR:13:VGA-1] checking for sink bpp constrains [ 298.810603] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1 [ 298.810604] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0 [ 298.810606] [drm:intel_dump_pipe_config] [CRTC:5][modeset] config for pipe A [ 298.810606] [drm:intel_dump_pipe_config] cpu_transcoder: A [ 298.810607] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 298.810609] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 3029219, gmch_n: 4194304, link_m: 126217, link_n: 524288, tu: 64 [ 298.810610] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 298.810611] [drm:intel_dump_pipe_config] requested mode: [ 298.810613] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x48 0xa [ 298.810614] [drm:intel_dump_pipe_config] adjusted mode: [ 298.810616] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x48 0xa [ 298.810617] [drm:intel_dump_crtc_timings] crtc timings: 65000 1024 1048 1184 1344 768 771 777 806, type: 0x48 flags: 0xa [ 298.810618] [drm:intel_dump_pipe_config] port clock: 65000 [ 298.810619] [drm:intel_dump_pipe_config] pipe src size: 1024x768 [ 298.810620] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 298.810622] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 298.810622] [drm:intel_dump_pipe_config] ips: 0 [ 298.810623] [drm:intel_dump_pipe_config] double wide: 0 [ 298.810631] [drm:ivb_modeset_global_resources] disabling fdi C rx [ 298.810642] [drm:intel_get_shared_dpll] CRTC:5 allocated PCH DPLL A [ 298.810643] [drm:intel_get_shared_dpll] using PCH DPLL A for pipe A [ 298.810644] [drm:intel_prepare_shared_dpll] setting up PCH DPLL A [ 298.810654] [drm:ironlake_update_primary_plane] Writing base 007A2000 00000000 0 0 4096 [ 298.811350] [drm:ivb_manual_fdi_link_train] FDI_RX_IIR before link train 0x0 [ 298.811358] [drm:ivb_manual_fdi_link_train] FDI_RX_IIR 0x100 [ 298.811360] [drm:ivb_manual_fdi_link_train] FDI train 1 done, level 0. [ 298.811368] [drm:ivb_manual_fdi_link_train] FDI_RX_IIR 0x600 [ 298.811370] [drm:ivb_manual_fdi_link_train] FDI train 2 done, level 0. [ 298.811371] [drm:ivb_manual_fdi_link_train] FDI train done. [ 298.811374] [drm:intel_enable_shared_dpll] enable PCH DPLL A (active 0, on? 0)for crtc 5 [ 298.811375] [drm:intel_enable_shared_dpll] enabling PCH DPLL A [ 298.813253] [drm:intel_update_fbc] disabled per chip default [ 298.813259] [drm:intel_connector_check_state] [CONNECTOR:13:VGA-1] [ 298.813264] [drm:check_encoder_state] [ENCODER:14:DAC-14] [ 298.813267] [drm:check_encoder_state] [ENCODER:15:TMDS-15] [ 298.813269] [drm:check_encoder_state] [ENCODER:19:TMDS-19] [ 298.813272] [drm:check_encoder_state] [ENCODER:21:TMDS-21] [ 298.813275] [drm:check_encoder_state] [ENCODER:23:TMDS-23] [ 298.813277] [drm:check_crtc_state] [CRTC:5] [ 298.813289] [drm:check_crtc_state] [CRTC:8] [ 298.813290] [drm:check_crtc_state] [CRTC:11] [ 298.813291] [drm:check_shared_dpll_state] PCH DPLL A [ 298.813295] [drm:check_shared_dpll_state] PCH DPLL B [ 298.813310] [drm:intel_crtc_page_flip] flip queue: crtc already busy [ 298.813324] [drm:drm_mode_addfb] [FB:39] [ 298.813326] [drm:intel_crtc_set_config] [CRTC:5] [NOFB] [ 298.813328] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:5], mode_changed=1, fb_changed=0 [ 298.813329] [drm:intel_modeset_stage_output_state] [CONNECTOR:13:VGA-1] to [NOCRTC] [ 298.813330] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 298.813331] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 298.813332] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch [ 298.813333] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1 [ 298.813342] [drm:intel_update_fbc] no output, disabling [ 298.847119] [drm:intel_disable_shared_dpll] disable PCH DPLL A (active 1, on? 1) for crtc 5 [ 298.847130] [drm:intel_disable_shared_dpll] disabling PCH DPLL A [ 298.847552] [drm:ivb_modeset_global_resources] disabling fdi C rx [ 298.847561] [drm:check_encoder_state] [ENCODER:14:DAC-14] [ 298.847563] [drm:check_encoder_state] [ENCODER:15:TMDS-15] [ 298.847566] [drm:check_encoder_state] [ENCODER:19:TMDS-19] [ 298.847569] [drm:check_encoder_state] [ENCODER:21:TMDS-21] [ 298.847571] [drm:check_encoder_state] [ENCODER:23:TMDS-23] [ 298.847574] [drm:check_crtc_state] [CRTC:5] [ 298.847575] [drm:check_crtc_state] [CRTC:8] [ 298.847576] [drm:check_crtc_state] [CRTC:11] [ 298.847577] [drm:check_shared_dpll_state] PCH DPLL A [ 298.847581] [drm:check_shared_dpll_state] PCH DPLL B [ 298.847590] [drm:drm_mode_setcrtc] [CRTC:5] [ 298.847592] [drm:drm_mode_setcrtc] [CONNECTOR:13:VGA-1] [ 298.847593] [drm:intel_crtc_set_config] [CRTC:5] [FB:37] #connectors=1 (x y) (0 0) [ 298.847595] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set [ 298.847596] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:5], mode_changed=1, fb_changed=0 [ 298.847597] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 298.847598] [drm:intel_modeset_stage_output_state] [CONNECTOR:13:VGA-1] to [CRTC:5] [ 298.847599] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 298.847600] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch [ 298.847602] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 298.847603] [drm:connected_sink_compute_bpp] [CONNECTOR:13:VGA-1] checking for sink bpp constrains [ 298.847605] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1 [ 298.847606] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0 [ 298.847607] [drm:intel_dump_pipe_config] [CRTC:5][modeset] config for pipe A [ 298.847608] [drm:intel_dump_pipe_config] cpu_transcoder: A [ 298.847609] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 298.847611] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 3029219, gmch_n: 4194304, link_m: 126217, link_n: 524288, tu: 64 [ 298.847612] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 298.847613] [drm:intel_dump_pipe_config] requested mode: [ 298.847615] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x48 0xa [ 298.847616] [drm:intel_dump_pipe_config] adjusted mode: [ 298.847617] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x48 0xa [ 298.847619] [drm:intel_dump_crtc_timings] crtc timings: 65000 1024 1048 1184 1344 768 771 777 806, type: 0x48 flags: 0xa [ 298.847620] [drm:intel_dump_pipe_config] port clock: 65000 [ 298.847621] [drm:intel_dump_pipe_config] pipe src size: 1024x768 [ 298.847622] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 298.847623] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 298.847624] [drm:intel_dump_pipe_config] ips: 0 [ 298.847625] [drm:intel_dump_pipe_config] double wide: 0 [ 298.847633] [drm:ivb_modeset_global_resources] disabling fdi C rx [ 298.847644] [drm:intel_get_shared_dpll] CRTC:5 allocated PCH DPLL A [ 298.847645] [drm:intel_get_shared_dpll] using PCH DPLL A for pipe A [ 298.847646] [drm:intel_prepare_shared_dpll] setting up PCH DPLL A [ 298.847656] [drm:ironlake_update_primary_plane] Writing base 004A2000 00000000 0 0 4096 [ 298.848353] [drm:ivb_manual_fdi_link_train] FDI_RX_IIR before link train 0x0 [ 298.848362] [drm:ivb_manual_fdi_link_train] FDI_RX_IIR 0x100 [ 298.848365] [drm:ivb_manual_fdi_link_train] FDI train 1 done, level 0. [ 298.848372] [drm:ivb_manual_fdi_link_train] FDI_RX_IIR 0x600 [ 298.848374] [drm:ivb_manual_fdi_link_train] FDI train 2 done, level 0. [ 298.848375] [drm:ivb_manual_fdi_link_train] FDI train done. [ 298.848378] [drm:intel_enable_shared_dpll] enable PCH DPLL A (active 0, on? 0)for crtc 5 [ 298.848379] [drm:intel_enable_shared_dpll] enabling PCH DPLL A [ 298.850261] [drm:intel_update_fbc] disabled per chip default [ 298.850267] [drm:intel_connector_check_state] [CONNECTOR:13:VGA-1] [ 298.850272] [drm:check_encoder_state] [ENCODER:14:DAC-14] [ 298.850275] [drm:check_encoder_state] [ENCODER:15:TMDS-15] [ 298.850278] [drm:check_encoder_state] [ENCODER:19:TMDS-19] [ 298.850280] [drm:check_encoder_state] [ENCODER:21:TMDS-21] [ 298.850283] [drm:check_encoder_state] [ENCODER:23:TMDS-23] [ 298.850285] [drm:check_crtc_state] [CRTC:5] [ 298.850297] [drm:check_crtc_state] [CRTC:8] [ 298.850298] [drm:check_crtc_state] [CRTC:11] [ 298.850299] [drm:check_shared_dpll_state] PCH DPLL A [ 298.850303] [drm:check_shared_dpll_state] PCH DPLL B [ 298.850318] [drm:intel_crtc_page_flip] flip queue: crtc already busy [ 298.850333] [drm:drm_mode_addfb] [FB:36] [ 298.850335] [drm:intel_crtc_set_config] [CRTC:5] [NOFB] [ 298.850337] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:5], mode_changed=1, fb_changed=0 [ 298.850338] [drm:intel_modeset_stage_output_state] [CONNECTOR:13:VGA-1] to [NOCRTC] [ 298.850339] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 298.850340] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 298.850341] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch [ 298.850342] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1 [ 298.850351] [drm:intel_update_fbc] no output, disabling [ 298.884115] [drm:intel_disable_shared_dpll] disable PCH DPLL A (active 1, on? 1) for crtc 5 [ 298.884124] [drm:intel_disable_shared_dpll] disabling PCH DPLL A [ 298.884549] [drm:ivb_modeset_global_resources] disabling fdi C rx [ 298.884556] [drm:check_encoder_state] [ENCODER:14:DAC-14] [ 298.884559] [drm:check_encoder_state] [ENCODER:15:TMDS-15] [ 298.884561] [drm:check_encoder_state] [ENCODER:19:TMDS-19] [ 298.884564] [drm:check_encoder_state] [ENCODER:21:TMDS-21] [ 298.884566] [drm:check_encoder_state] [ENCODER:23:TMDS-23] [ 298.884569] [drm:check_crtc_state] [CRTC:5] [ 298.884570] [drm:check_crtc_state] [CRTC:8] [ 298.884571] [drm:check_crtc_state] [CRTC:11] [ 298.884572] [drm:check_shared_dpll_state] PCH DPLL A [ 298.884576] [drm:check_shared_dpll_state] PCH DPLL B [ 298.884585] [drm:drm_mode_setcrtc] [CRTC:5] [ 298.884587] [drm:drm_mode_setcrtc] [CONNECTOR:13:VGA-1] [ 298.884588] [drm:intel_crtc_set_config] [CRTC:5] [FB:39] #connectors=1 (x y) (0 0) [ 298.884590] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set [ 298.884591] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:5], mode_changed=1, fb_changed=0 [ 298.884592] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 298.884593] [drm:intel_modeset_stage_output_state] [CONNECTOR:13:VGA-1] to [CRTC:5] [ 298.884594] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 298.884595] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch [ 298.884597] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 298.884598] [drm:connected_sink_compute_bpp] [CONNECTOR:13:VGA-1] checking for sink bpp constrains [ 298.884600] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1 [ 298.884601] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0 [ 298.884602] [drm:intel_dump_pipe_config] [CRTC:5][modeset] config for pipe A [ 298.884603] [drm:intel_dump_pipe_config] cpu_transcoder: A [ 298.884604] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 298.884605] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 3029219, gmch_n: 4194304, link_m: 126217, link_n: 524288, tu: 64 [ 298.884607] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 298.884608] [drm:intel_dump_pipe_config] requested mode: [ 298.884610] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x48 0xa [ 298.884610] [drm:intel_dump_pipe_config] adjusted mode: [ 298.884612] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x48 0xa [ 298.884614] [drm:intel_dump_crtc_timings] crtc timings: 65000 1024 1048 1184 1344 768 771 777 806, type: 0x48 flags: 0xa [ 298.884615] [drm:intel_dump_pipe_config] port clock: 65000 [ 298.884616] [drm:intel_dump_pipe_config] pipe src size: 1024x768 [ 298.884617] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 298.884618] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 298.884619] [drm:intel_dump_pipe_config] ips: 0 [ 298.884620] [drm:intel_dump_pipe_config] double wide: 0 [ 298.884627] [drm:ivb_modeset_global_resources] disabling fdi C rx [ 298.884638] [drm:intel_get_shared_dpll] CRTC:5 allocated PCH DPLL A [ 298.884639] [drm:intel_get_shared_dpll] using PCH DPLL A for pipe A [ 298.884640] [drm:intel_prepare_shared_dpll] setting up PCH DPLL A [ 298.884650] [drm:ironlake_update_primary_plane] Writing base 007A2000 00000000 0 0 4096 [ 298.885347] [drm:ivb_manual_fdi_link_train] FDI_RX_IIR before link train 0x0 [ 298.885356] [drm:ivb_manual_fdi_link_train] FDI_RX_IIR 0x100 [ 298.885359] [drm:ivb_manual_fdi_link_train] FDI train 1 done, level 0. [ 298.885366] [drm:ivb_manual_fdi_link_train] FDI_RX_IIR 0x600 [ 298.885368] [drm:ivb_manual_fdi_link_train] FDI train 2 done, level 0. [ 298.885369] [drm:ivb_manual_fdi_link_train] FDI train done. [ 298.885372] [drm:intel_enable_shared_dpll] enable PCH DPLL A (active 0, on? 0)for crtc 5 [ 298.885373] [drm:intel_enable_shared_dpll] enabling PCH DPLL A [ 298.887254] [drm:intel_update_fbc] disabled per chip default [ 298.887260] [drm:intel_connector_check_state] [CONNECTOR:13:VGA-1] [ 298.887265] [drm:check_encoder_state] [ENCODER:14:DAC-14] [ 298.887268] [drm:check_encoder_state] [ENCODER:15:TMDS-15] [ 298.887270] [drm:check_encoder_state] [ENCODER:19:TMDS-19] [ 298.887273] [drm:check_encoder_state] [ENCODER:21:TMDS-21] [ 298.887275] [drm:check_encoder_state] [ENCODER:23:TMDS-23] [ 298.887277] [drm:check_crtc_state] [CRTC:5] [ 298.887289] [drm:check_crtc_state] [CRTC:8] [ 298.887290] [drm:check_crtc_state] [CRTC:11] [ 298.887291] [drm:check_shared_dpll_state] PCH DPLL A [ 298.887295] [drm:check_shared_dpll_state] PCH DPLL B [ 298.887310] [drm:intel_crtc_page_flip] flip queue: crtc already busy [ 298.887324] [drm:drm_mode_addfb] [FB:37] [ 298.887326] [drm:intel_crtc_set_config] [CRTC:5] [NOFB] [ 298.887328] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:5], mode_changed=1, fb_changed=0 [ 298.887329] [drm:intel_modeset_stage_output_state] [CONNECTOR:13:VGA-1] to [NOCRTC] [ 298.887330] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 298.887331] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 298.887332] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch [ 298.887333] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1 [ 298.887342] [drm:intel_update_fbc] no output, disabling [ 298.921117] [drm:intel_disable_shared_dpll] disable PCH DPLL A (active 1, on? 1) for crtc 5 [ 298.921127] [drm:intel_disable_shared_dpll] disabling PCH DPLL A [ 298.921550] [drm:ivb_modeset_global_resources] disabling fdi C rx [ 298.921558] [drm:check_encoder_state] [ENCODER:14:DAC-14] [ 298.921561] [drm:check_encoder_state] [ENCODER:15:TMDS-15] [ 298.921563] [drm:check_encoder_state] [ENCODER:19:TMDS-19] [ 298.921565] [drm:check_encoder_state] [ENCODER:21:TMDS-21] [ 298.921568] [drm:check_encoder_state] [ENCODER:23:TMDS-23] [ 298.921570] [drm:check_crtc_state] [CRTC:5] [ 298.921571] [drm:check_crtc_state] [CRTC:8] [ 298.921572] [drm:check_crtc_state] [CRTC:11] [ 298.921573] [drm:check_shared_dpll_state] PCH DPLL A [ 298.921578] [drm:check_shared_dpll_state] PCH DPLL B [ 298.921586] [drm:drm_mode_setcrtc] [CRTC:5] [ 298.921588] [drm:drm_mode_setcrtc] [CONNECTOR:13:VGA-1] [ 298.921590] [drm:intel_crtc_set_config] [CRTC:5] [FB:36] #connectors=1 (x y) (0 0) [ 298.921591] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set [ 298.921592] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:5], mode_changed=1, fb_changed=0 [ 298.921593] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 298.921595] [drm:intel_modeset_stage_output_state] [CONNECTOR:13:VGA-1] to [CRTC:5] [ 298.921596] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 298.921597] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch [ 298.921598] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 298.921600] [drm:connected_sink_compute_bpp] [CONNECTOR:13:VGA-1] checking for sink bpp constrains [ 298.921601] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1 [ 298.921602] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0 [ 298.921604] [drm:intel_dump_pipe_config] [CRTC:5][modeset] config for pipe A [ 298.921604] [drm:intel_dump_pipe_config] cpu_transcoder: A [ 298.921605] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 298.921607] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 3029219, gmch_n: 4194304, link_m: 126217, link_n: 524288, tu: 64 [ 298.921608] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 298.921609] [drm:intel_dump_pipe_config] requested mode: [ 298.921611] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x48 0xa [ 298.921612] [drm:intel_dump_pipe_config] adjusted mode: [ 298.921614] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x48 0xa [ 298.921616] [drm:intel_dump_crtc_timings] crtc timings: 65000 1024 1048 1184 1344 768 771 777 806, type: 0x48 flags: 0xa [ 298.921616] [drm:intel_dump_pipe_config] port clock: 65000 [ 298.921617] [drm:intel_dump_pipe_config] pipe src size: 1024x768 [ 298.921619] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 298.921620] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 298.921621] [drm:intel_dump_pipe_config] ips: 0 [ 298.921622] [drm:intel_dump_pipe_config] double wide: 0 [ 298.921629] [drm:ivb_modeset_global_resources] disabling fdi C rx [ 298.921640] [drm:intel_get_shared_dpll] CRTC:5 allocated PCH DPLL A [ 298.921641] [drm:intel_get_shared_dpll] using PCH DPLL A for pipe A [ 298.921642] [drm:intel_prepare_shared_dpll] setting up PCH DPLL A [ 298.921652] [drm:ironlake_update_primary_plane] Writing base 004A2000 00000000 0 0 4096 [ 298.922350] [drm:ivb_manual_fdi_link_train] FDI_RX_IIR before link train 0x0 [ 298.922359] [drm:ivb_manual_fdi_link_train] FDI_RX_IIR 0x100 [ 298.922361] [drm:ivb_manual_fdi_link_train] FDI train 1 done, level 0. [ 298.922369] [drm:ivb_manual_fdi_link_train] FDI_RX_IIR 0x600 [ 298.922371] [drm:ivb_manual_fdi_link_train] FDI train 2 done, level 0. [ 298.922372] [drm:ivb_manual_fdi_link_train] FDI train done. [ 298.922375] [drm:intel_enable_shared_dpll] enable PCH DPLL A (active 0, on? 0)for crtc 5 [ 298.922376] [drm:intel_enable_shared_dpll] enabling PCH DPLL A [ 298.924257] [drm:intel_update_fbc] disabled per chip default [ 298.924263] [drm:intel_connector_check_state] [CONNECTOR:13:VGA-1] [ 298.924269] [drm:check_encoder_state] [ENCODER:14:DAC-14] [ 298.924271] [drm:check_encoder_state] [ENCODER:15:TMDS-15] [ 298.924274] [drm:check_encoder_state] [ENCODER:19:TMDS-19] [ 298.924277] [drm:check_encoder_state] [ENCODER:21:TMDS-21] [ 298.924279] [drm:check_encoder_state] [ENCODER:23:TMDS-23] [ 298.924281] [drm:check_crtc_state] [CRTC:5] [ 298.924293] [drm:check_crtc_state] [CRTC:8] [ 298.924294] [drm:check_crtc_state] [CRTC:11] [ 298.924295] [drm:check_shared_dpll_state] PCH DPLL A [ 298.924299] [drm:check_shared_dpll_state] PCH DPLL B [ 298.924314] [drm:intel_crtc_page_flip] flip queue: crtc already busy [ 298.924328] [drm:drm_mode_addfb] [FB:39] [ 298.924330] [drm:intel_crtc_set_config] [CRTC:5] [NOFB] [ 298.924332] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:5], mode_changed=1, fb_changed=0 [ 298.924333] [drm:intel_modeset_stage_output_state] [CONNECTOR:13:VGA-1] to [NOCRTC] [ 298.924334] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 298.924335] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 298.924336] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch [ 298.924337] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1 [ 298.924346] [drm:intel_update_fbc] no output, disabling [ 298.958113] [drm:intel_disable_shared_dpll] disable PCH DPLL A (active 1, on? 1) for crtc 5 [ 298.958124] [drm:intel_disable_shared_dpll] disabling PCH DPLL A [ 298.958547] [drm:ivb_modeset_global_resources] disabling fdi C rx [ 298.958554] [drm:check_encoder_state] [ENCODER:14:DAC-14] [ 298.958557] [drm:check_encoder_state] [ENCODER:15:TMDS-15] [ 298.958559] [drm:check_encoder_state] [ENCODER:19:TMDS-19] [ 298.958562] [drm:check_encoder_state] [ENCODER:21:TMDS-21] [ 298.958565] [drm:check_encoder_state] [ENCODER:23:TMDS-23] [ 298.958567] [drm:check_crtc_state] [CRTC:5] [ 298.958568] [drm:check_crtc_state] [CRTC:8] [ 298.958569] [drm:check_crtc_state] [CRTC:11] [ 298.958570] [drm:check_shared_dpll_state] PCH DPLL A [ 298.958575] [drm:check_shared_dpll_state] PCH DPLL B [ 298.958583] [drm:drm_mode_setcrtc] [CRTC:5] [ 298.958585] [drm:drm_mode_setcrtc] [CONNECTOR:13:VGA-1] [ 298.958587] [drm:intel_crtc_set_config] [CRTC:5] [FB:37] #connectors=1 (x y) (0 0) [ 298.958588] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set [ 298.958589] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:5], mode_changed=1, fb_changed=0 [ 298.958590] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 298.958592] [drm:intel_modeset_stage_output_state] [CONNECTOR:13:VGA-1] to [CRTC:5] [ 298.958593] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 298.958594] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch [ 298.958595] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 298.958597] [drm:connected_sink_compute_bpp] [CONNECTOR:13:VGA-1] checking for sink bpp constrains [ 298.958598] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1 [ 298.958599] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0 [ 298.958601] [drm:intel_dump_pipe_config] [CRTC:5][modeset] config for pipe A [ 298.958601] [drm:intel_dump_pipe_config] cpu_transcoder: A [ 298.958602] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 298.958604] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 3029219, gmch_n: 4194304, link_m: 126217, link_n: 524288, tu: 64 [ 298.958605] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 298.958606] [drm:intel_dump_pipe_config] requested mode: [ 298.958608] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x48 0xa [ 298.958609] [drm:intel_dump_pipe_config] adjusted mode: [ 298.958611] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x48 0xa [ 298.958612] [drm:intel_dump_crtc_timings] crtc timings: 65000 1024 1048 1184 1344 768 771 777 806, type: 0x48 flags: 0xa [ 298.958613] [drm:intel_dump_pipe_config] port clock: 65000 [ 298.958614] [drm:intel_dump_pipe_config] pipe src size: 1024x768 [ 298.958616] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 298.958617] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 298.958618] [drm:intel_dump_pipe_config] ips: 0 [ 298.958619] [drm:intel_dump_pipe_config] double wide: 0 [ 298.958625] [drm:ivb_modeset_global_resources] disabling fdi C rx [ 298.958637] [drm:intel_get_shared_dpll] CRTC:5 allocated PCH DPLL A [ 298.958638] [drm:intel_get_shared_dpll] using PCH DPLL A for pipe A [ 298.958639] [drm:intel_prepare_shared_dpll] setting up PCH DPLL A [ 298.958650] [drm:ironlake_update_primary_plane] Writing base 007A2000 00000000 0 0 4096 [ 298.959347] [drm:ivb_manual_fdi_link_train] FDI_RX_IIR before link train 0x0 [ 298.959355] [drm:ivb_manual_fdi_link_train] FDI_RX_IIR 0x100 [ 298.959358] [drm:ivb_manual_fdi_link_train] FDI train 1 done, level 0. [ 298.959365] [drm:ivb_manual_fdi_link_train] FDI_RX_IIR 0x600 [ 298.959367] [drm:ivb_manual_fdi_link_train] FDI train 2 done, level 0. [ 298.959368] [drm:ivb_manual_fdi_link_train] FDI train done. [ 298.959371] [drm:intel_enable_shared_dpll] enable PCH DPLL A (active 0, on? 0)for crtc 5 [ 298.959372] [drm:intel_enable_shared_dpll] enabling PCH DPLL A [ 298.961253] [drm:intel_update_fbc] disabled per chip default [ 298.961258] [drm:intel_connector_check_state] [CONNECTOR:13:VGA-1] [ 298.961264] [drm:check_encoder_state] [ENCODER:14:DAC-14] [ 298.961266] [drm:check_encoder_state] [ENCODER:15:TMDS-15] [ 298.961269] [drm:check_encoder_state] [ENCODER:19:TMDS-19] [ 298.961271] [drm:check_encoder_state] [ENCODER:21:TMDS-21] [ 298.961274] [drm:check_encoder_state] [ENCODER:23:TMDS-23] [ 298.961276] [drm:check_crtc_state] [CRTC:5] [ 298.961288] [drm:check_crtc_state] [CRTC:8] [ 298.961289] [drm:check_crtc_state] [CRTC:11] [ 298.961290] [drm:check_shared_dpll_state] PCH DPLL A [ 298.961294] [drm:check_shared_dpll_state] PCH DPLL B [ 298.961310] [drm:intel_crtc_page_flip] flip queue: crtc already busy [ 298.961323] [drm:drm_mode_addfb] [FB:36] [ 298.961325] [drm:intel_crtc_set_config] [CRTC:5] [NOFB] [ 298.961327] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:5], mode_changed=1, fb_changed=0 [ 298.961328] [drm:intel_modeset_stage_output_state] [CONNECTOR:13:VGA-1] to [NOCRTC] [ 298.961329] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 298.961330] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 298.961331] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch [ 298.961332] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1 [ 298.961342] [drm:intel_update_fbc] no output, disabling [ 298.995115] [drm:intel_disable_shared_dpll] disable PCH DPLL A (active 1, on? 1) for crtc 5 [ 298.995124] [drm:intel_disable_shared_dpll] disabling PCH DPLL A [ 298.995547] [drm:ivb_modeset_global_resources] disabling fdi C rx [ 298.995554] [drm:check_encoder_state] [ENCODER:14:DAC-14] [ 298.995557] [drm:check_encoder_state] [ENCODER:15:TMDS-15] [ 298.995559] [drm:check_encoder_state] [ENCODER:19:TMDS-19] [ 298.995562] [drm:check_encoder_state] [ENCODER:21:TMDS-21] [ 298.995564] [drm:check_encoder_state] [ENCODER:23:TMDS-23] [ 298.995567] [drm:check_crtc_state] [CRTC:5] [ 298.995568] [drm:check_crtc_state] [CRTC:8] [ 298.995569] [drm:check_crtc_state] [CRTC:11] [ 298.995570] [drm:check_shared_dpll_state] PCH DPLL A [ 298.995574] [drm:check_shared_dpll_state] PCH DPLL B [ 298.995583] [drm:drm_mode_setcrtc] [CRTC:5] [ 298.995585] [drm:drm_mode_setcrtc] [CONNECTOR:13:VGA-1] [ 298.995587] [drm:intel_crtc_set_config] [CRTC:5] [FB:39] #connectors=1 (x y) (0 0) [ 298.995588] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set [ 298.995589] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:5], mode_changed=1, fb_changed=0 [ 298.995590] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 298.995592] [drm:intel_modeset_stage_output_state] [CONNECTOR:13:VGA-1] to [CRTC:5] [ 298.995592] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 298.995594] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch [ 298.995595] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 298.995597] [drm:connected_sink_compute_bpp] [CONNECTOR:13:VGA-1] checking for sink bpp constrains [ 298.995598] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1 [ 298.995599] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0 [ 298.995600] [drm:intel_dump_pipe_config] [CRTC:5][modeset] config for pipe A [ 298.995601] [drm:intel_dump_pipe_config] cpu_transcoder: A [ 298.995602] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 298.995604] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 3029219, gmch_n: 4194304, link_m: 126217, link_n: 524288, tu: 64 [ 298.995605] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 298.995606] [drm:intel_dump_pipe_config] requested mode: [ 298.995608] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x48 0xa [ 298.995609] [drm:intel_dump_pipe_config] adjusted mode: [ 298.995611] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x48 0xa [ 298.995612] [drm:intel_dump_crtc_timings] crtc timings: 65000 1024 1048 1184 1344 768 771 777 806, type: 0x48 flags: 0xa [ 298.995613] [drm:intel_dump_pipe_config] port clock: 65000 [ 298.995614] [drm:intel_dump_pipe_config] pipe src size: 1024x768 [ 298.995615] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 298.995617] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 298.995617] [drm:intel_dump_pipe_config] ips: 0 [ 298.995618] [drm:intel_dump_pipe_config] double wide: 0 [ 298.995626] [drm:ivb_modeset_global_resources] disabling fdi C rx [ 298.995637] [drm:intel_get_shared_dpll] CRTC:5 allocated PCH DPLL A [ 298.995638] [drm:intel_get_shared_dpll] using PCH DPLL A for pipe A [ 298.995639] [drm:intel_prepare_shared_dpll] setting up PCH DPLL A [ 298.995649] [drm:ironlake_update_primary_plane] Writing base 004A2000 00000000 0 0 4096 [ 298.996346] [drm:ivb_manual_fdi_link_train] FDI_RX_IIR before link train 0x0 [ 298.996355] [drm:ivb_manual_fdi_link_train] FDI_RX_IIR 0x100 [ 298.996358] [drm:ivb_manual_fdi_link_train] FDI train 1 done, level 0. [ 298.996366] [drm:ivb_manual_fdi_link_train] FDI_RX_IIR 0x600 [ 298.996368] [drm:ivb_manual_fdi_link_train] FDI train 2 done, level 0. [ 298.996369] [drm:ivb_manual_fdi_link_train] FDI train done. [ 298.996372] [drm:intel_enable_shared_dpll] enable PCH DPLL A (active 0, on? 0)for crtc 5 [ 298.996373] [drm:intel_enable_shared_dpll] enabling PCH DPLL A [ 298.998253] [drm:intel_update_fbc] disabled per chip default [ 298.998259] [drm:intel_connector_check_state] [CONNECTOR:13:VGA-1] [ 298.998264] [drm:check_encoder_state] [ENCODER:14:DAC-14] [ 298.998267] [drm:check_encoder_state] [ENCODER:15:TMDS-15] [ 298.998269] [drm:check_encoder_state] [ENCODER:19:TMDS-19] [ 298.998272] [drm:check_encoder_state] [ENCODER:21:TMDS-21] [ 298.998275] [drm:check_encoder_state] [ENCODER:23:TMDS-23] [ 298.998277] [drm:check_crtc_state] [CRTC:5] [ 298.998289] [drm:check_crtc_state] [CRTC:8] [ 298.998290] [drm:check_crtc_state] [CRTC:11] [ 298.998291] [drm:check_shared_dpll_state] PCH DPLL A [ 298.998295] [drm:check_shared_dpll_state] PCH DPLL B [ 298.998310] [drm:intel_crtc_page_flip] flip queue: crtc already busy [ 298.998325] [drm:drm_mode_addfb] [FB:37] [ 298.998327] [drm:intel_crtc_set_config] [CRTC:5] [NOFB] [ 298.998329] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:5], mode_changed=1, fb_changed=0 [ 298.998330] [drm:intel_modeset_stage_output_state] [CONNECTOR:13:VGA-1] to [NOCRTC] [ 298.998331] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 298.998332] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 298.998333] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch [ 298.998334] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1 [ 298.998343] [drm:intel_update_fbc] no output, disabling [ 299.032111] [drm:intel_disable_shared_dpll] disable PCH DPLL A (active 1, on? 1) for crtc 5 [ 299.032121] [drm:intel_disable_shared_dpll] disabling PCH DPLL A [ 299.032546] [drm:ivb_modeset_global_resources] disabling fdi C rx [ 299.032553] [drm:check_encoder_state] [ENCODER:14:DAC-14] [ 299.032556] [drm:check_encoder_state] [ENCODER:15:TMDS-15] [ 299.032558] [drm:check_encoder_state] [ENCODER:19:TMDS-19] [ 299.032561] [drm:check_encoder_state] [ENCODER:21:TMDS-21] [ 299.032563] [drm:check_encoder_state] [ENCODER:23:TMDS-23] [ 299.032566] [drm:check_crtc_state] [CRTC:5] [ 299.032567] [drm:check_crtc_state] [CRTC:8] [ 299.032568] [drm:check_crtc_state] [CRTC:11] [ 299.032569] [drm:check_shared_dpll_state] PCH DPLL A [ 299.032573] [drm:check_shared_dpll_state] PCH DPLL B [ 299.032582] [drm:drm_mode_setcrtc] [CRTC:5] [ 299.032584] [drm:drm_mode_setcrtc] [CONNECTOR:13:VGA-1] [ 299.032586] [drm:intel_crtc_set_config] [CRTC:5] [FB:36] #connectors=1 (x y) (0 0) [ 299.032587] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set [ 299.032588] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:5], mode_changed=1, fb_changed=0 [ 299.032589] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 299.032590] [drm:intel_modeset_stage_output_state] [CONNECTOR:13:VGA-1] to [CRTC:5] [ 299.032591] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 299.032592] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch [ 299.032594] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 299.032596] [drm:connected_sink_compute_bpp] [CONNECTOR:13:VGA-1] checking for sink bpp constrains [ 299.032597] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1 [ 299.032598] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0 [ 299.032599] [drm:intel_dump_pipe_config] [CRTC:5][modeset] config for pipe A [ 299.032600] [drm:intel_dump_pipe_config] cpu_transcoder: A [ 299.032601] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 299.032603] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 3029219, gmch_n: 4194304, link_m: 126217, link_n: 524288, tu: 64 [ 299.032604] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 299.032605] [drm:intel_dump_pipe_config] requested mode: [ 299.032607] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x48 0xa [ 299.032608] [drm:intel_dump_pipe_config] adjusted mode: [ 299.032610] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x48 0xa [ 299.032611] [drm:intel_dump_crtc_timings] crtc timings: 65000 1024 1048 1184 1344 768 771 777 806, type: 0x48 flags: 0xa [ 299.032612] [drm:intel_dump_pipe_config] port clock: 65000 [ 299.032613] [drm:intel_dump_pipe_config] pipe src size: 1024x768 [ 299.032614] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 299.032616] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 299.032616] [drm:intel_dump_pipe_config] ips: 0 [ 299.032617] [drm:intel_dump_pipe_config] double wide: 0 [ 299.032624] [drm:ivb_modeset_global_resources] disabling fdi C rx [ 299.032636] [drm:intel_get_shared_dpll] CRTC:5 allocated PCH DPLL A [ 299.032637] [drm:intel_get_shared_dpll] using PCH DPLL A for pipe A [ 299.032638] [drm:intel_prepare_shared_dpll] setting up PCH DPLL A [ 299.032648] [drm:ironlake_update_primary_plane] Writing base 007A2000 00000000 0 0 4096 [ 299.033345] [drm:ivb_manual_fdi_link_train] FDI_RX_IIR before link train 0x0 [ 299.033354] [drm:ivb_manual_fdi_link_train] FDI_RX_IIR 0x100 [ 299.033357] [drm:ivb_manual_fdi_link_train] FDI train 1 done, level 0. [ 299.033364] [drm:ivb_manual_fdi_link_train] FDI_RX_IIR 0x600 [ 299.033366] [drm:ivb_manual_fdi_link_train] FDI train 2 done, level 0. [ 299.033367] [drm:ivb_manual_fdi_link_train] FDI train done. [ 299.033371] [drm:intel_enable_shared_dpll] enable PCH DPLL A (active 0, on? 0)for crtc 5 [ 299.033372] [drm:intel_enable_shared_dpll] enabling PCH DPLL A [ 299.035253] [drm:intel_update_fbc] disabled per chip default [ 299.035258] [drm:intel_connector_check_state] [CONNECTOR:13:VGA-1] [ 299.035264] [drm:check_encoder_state] [ENCODER:14:DAC-14] [ 299.035266] [drm:check_encoder_state] [ENCODER:15:TMDS-15] [ 299.035269] [drm:check_encoder_state] [ENCODER:19:TMDS-19] [ 299.035272] [drm:check_encoder_state] [ENCODER:21:TMDS-21] [ 299.035274] [drm:check_encoder_state] [ENCODER:23:TMDS-23] [ 299.035276] [drm:check_crtc_state] [CRTC:5] [ 299.035287] [drm:check_crtc_state] [CRTC:8] [ 299.035288] [drm:check_crtc_state] [CRTC:11] [ 299.035289] [drm:check_shared_dpll_state] PCH DPLL A [ 299.035293] [drm:check_shared_dpll_state] PCH DPLL B [ 299.035309] [drm:intel_crtc_page_flip] flip queue: crtc already busy [ 299.035322] [drm:drm_mode_addfb] [FB:39] [ 299.035324] [drm:intel_crtc_set_config] [CRTC:5] [NOFB] [ 299.035326] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:5], mode_changed=1, fb_changed=0 [ 299.035327] [drm:intel_modeset_stage_output_state] [CONNECTOR:13:VGA-1] to [NOCRTC] [ 299.035328] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 299.035329] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 299.035330] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch [ 299.035331] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1 [ 299.035341] [drm:intel_update_fbc] no output, disabling [ 299.069113] [drm:intel_disable_shared_dpll] disable PCH DPLL A (active 1, on? 1) for crtc 5 [ 299.069123] [drm:intel_disable_shared_dpll] disabling PCH DPLL A [ 299.069546] [drm:ivb_modeset_global_resources] disabling fdi C rx [ 299.069554] [drm:check_encoder_state] [ENCODER:14:DAC-14] [ 299.069557] [drm:check_encoder_state] [ENCODER:15:TMDS-15] [ 299.069560] [drm:check_encoder_state] [ENCODER:19:TMDS-19] [ 299.069562] [drm:check_encoder_state] [ENCODER:21:TMDS-21] [ 299.069565] [drm:check_encoder_state] [ENCODER:23:TMDS-23] [ 299.069567] [drm:check_crtc_state] [CRTC:5] [ 299.069568] [drm:check_crtc_state] [CRTC:8] [ 299.069569] [drm:check_crtc_state] [CRTC:11] [ 299.069570] [drm:check_shared_dpll_state] PCH DPLL A [ 299.069575] [drm:check_shared_dpll_state] PCH DPLL B [ 299.069583] [drm:drm_mode_setcrtc] [CRTC:5] [ 299.069586] [drm:drm_mode_setcrtc] [CONNECTOR:13:VGA-1] [ 299.069587] [drm:intel_crtc_set_config] [CRTC:5] [FB:37] #connectors=1 (x y) (0 0) [ 299.069588] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set [ 299.069590] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:5], mode_changed=1, fb_changed=0 [ 299.069591] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 299.069592] [drm:intel_modeset_stage_output_state] [CONNECTOR:13:VGA-1] to [CRTC:5] [ 299.069593] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 299.069594] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch [ 299.069595] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 299.069597] [drm:connected_sink_compute_bpp] [CONNECTOR:13:VGA-1] checking for sink bpp constrains [ 299.069598] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1 [ 299.069600] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0 [ 299.069601] [drm:intel_dump_pipe_config] [CRTC:5][modeset] config for pipe A [ 299.069601] [drm:intel_dump_pipe_config] cpu_transcoder: A [ 299.069602] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 299.069604] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 3029219, gmch_n: 4194304, link_m: 126217, link_n: 524288, tu: 64 [ 299.069605] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 299.069606] [drm:intel_dump_pipe_config] requested mode: [ 299.069608] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x48 0xa [ 299.069609] [drm:intel_dump_pipe_config] adjusted mode: [ 299.069611] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x48 0xa [ 299.069613] [drm:intel_dump_crtc_timings] crtc timings: 65000 1024 1048 1184 1344 768 771 777 806, type: 0x48 flags: 0xa [ 299.069613] [drm:intel_dump_pipe_config] port clock: 65000 [ 299.069614] [drm:intel_dump_pipe_config] pipe src size: 1024x768 [ 299.069616] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 299.069617] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 299.069618] [drm:intel_dump_pipe_config] ips: 0 [ 299.069619] [drm:intel_dump_pipe_config] double wide: 0 [ 299.069626] [drm:ivb_modeset_global_resources] disabling fdi C rx [ 299.069637] [drm:intel_get_shared_dpll] CRTC:5 allocated PCH DPLL A [ 299.069638] [drm:intel_get_shared_dpll] using PCH DPLL A for pipe A [ 299.069639] [drm:intel_prepare_shared_dpll] setting up PCH DPLL A [ 299.069649] [drm:ironlake_update_primary_plane] Writing base 004A2000 00000000 0 0 4096 [ 299.070346] [drm:ivb_manual_fdi_link_train] FDI_RX_IIR before link train 0x0 [ 299.070355] [drm:ivb_manual_fdi_link_train] FDI_RX_IIR 0x100 [ 299.070358] [drm:ivb_manual_fdi_link_train] FDI train 1 done, level 0. [ 299.070365] [drm:ivb_manual_fdi_link_train] FDI_RX_IIR 0x600 [ 299.070367] [drm:ivb_manual_fdi_link_train] FDI train 2 done, level 0. [ 299.070368] [drm:ivb_manual_fdi_link_train] FDI train done. [ 299.070371] [drm:intel_enable_shared_dpll] enable PCH DPLL A (active 0, on? 0)for crtc 5 [ 299.070373] [drm:intel_enable_shared_dpll] enabling PCH DPLL A [ 299.072255] [drm:intel_update_fbc] disabled per chip default [ 299.072260] [drm:intel_connector_check_state] [CONNECTOR:13:VGA-1] [ 299.072266] [drm:check_encoder_state] [ENCODER:14:DAC-14] [ 299.072268] [drm:check_encoder_state] [ENCODER:15:TMDS-15] [ 299.072271] [drm:check_encoder_state] [ENCODER:19:TMDS-19] [ 299.072273] [drm:check_encoder_state] [ENCODER:21:TMDS-21] [ 299.072276] [drm:check_encoder_state] [ENCODER:23:TMDS-23] [ 299.072278] [drm:check_crtc_state] [CRTC:5] [ 299.072289] [drm:check_crtc_state] [CRTC:8] [ 299.072290] [drm:check_crtc_state] [CRTC:11] [ 299.072291] [drm:check_shared_dpll_state] PCH DPLL A [ 299.072295] [drm:check_shared_dpll_state] PCH DPLL B [ 299.072311] [drm:intel_crtc_page_flip] flip queue: crtc already busy [ 299.072325] [drm:drm_mode_addfb] [FB:36] [ 299.072328] [drm:intel_crtc_set_config] [CRTC:5] [NOFB] [ 299.072329] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:5], mode_changed=1, fb_changed=0 [ 299.072330] [drm:intel_modeset_stage_output_state] [CONNECTOR:13:VGA-1] to [NOCRTC] [ 299.072331] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 299.072332] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 299.072333] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch [ 299.072335] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1 [ 299.072343] [drm:intel_update_fbc] no output, disabling [ 299.106110] [drm:intel_disable_shared_dpll] disable PCH DPLL A (active 1, on? 1) for crtc 5 [ 299.106120] [drm:intel_disable_shared_dpll] disabling PCH DPLL A [ 299.106544] [drm:ivb_modeset_global_resources] disabling fdi C rx [ 299.106551] [drm:check_encoder_state] [ENCODER:14:DAC-14] [ 299.106554] [drm:check_encoder_state] [ENCODER:15:TMDS-15] [ 299.106557] [drm:check_encoder_state] [ENCODER:19:TMDS-19] [ 299.106559] [drm:check_encoder_state] [ENCODER:21:TMDS-21] [ 299.106562] [drm:check_encoder_state] [ENCODER:23:TMDS-23] [ 299.106564] [drm:check_crtc_state] [CRTC:5] [ 299.106565] [drm:check_crtc_state] [CRTC:8] [ 299.106566] [drm:check_crtc_state] [CRTC:11] [ 299.106567] [drm:check_shared_dpll_state] PCH DPLL A [ 299.106571] [drm:check_shared_dpll_state] PCH DPLL B [ 299.106581] [drm:drm_mode_setcrtc] [CRTC:5] [ 299.106584] [drm:drm_mode_setcrtc] [CONNECTOR:13:VGA-1] [ 299.106585] [drm:intel_crtc_set_config] [CRTC:5] [FB:39] #connectors=1 (x y) (0 0) [ 299.106586] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set [ 299.106588] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:5], mode_changed=1, fb_changed=0 [ 299.106589] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 299.106590] [drm:intel_modeset_stage_output_state] [CONNECTOR:13:VGA-1] to [CRTC:5] [ 299.106591] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 299.106592] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch [ 299.106593] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 299.106595] [drm:connected_sink_compute_bpp] [CONNECTOR:13:VGA-1] checking for sink bpp constrains [ 299.106596] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1 [ 299.106598] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0 [ 299.106599] [drm:intel_dump_pipe_config] [CRTC:5][modeset] config for pipe A [ 299.106600] [drm:intel_dump_pipe_config] cpu_transcoder: A [ 299.106601] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 299.106602] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 3029219, gmch_n: 4194304, link_m: 126217, link_n: 524288, tu: 64 [ 299.106603] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 299.106604] [drm:intel_dump_pipe_config] requested mode: [ 299.106606] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x48 0xa [ 299.106607] [drm:intel_dump_pipe_config] adjusted mode: [ 299.106609] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x48 0xa [ 299.106611] [drm:intel_dump_crtc_timings] crtc timings: 65000 1024 1048 1184 1344 768 771 777 806, type: 0x48 flags: 0xa [ 299.106612] [drm:intel_dump_pipe_config] port clock: 65000 [ 299.106613] [drm:intel_dump_pipe_config] pipe src size: 1024x768 [ 299.106614] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 299.106615] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 299.106616] [drm:intel_dump_pipe_config] ips: 0 [ 299.106617] [drm:intel_dump_pipe_config] double wide: 0 [ 299.106624] [drm:ivb_modeset_global_resources] disabling fdi C rx [ 299.106635] [drm:intel_get_shared_dpll] CRTC:5 allocated PCH DPLL A [ 299.106636] [drm:intel_get_shared_dpll] using PCH DPLL A for pipe A [ 299.106637] [drm:intel_prepare_shared_dpll] setting up PCH DPLL A [ 299.106644] [drm:ironlake_update_primary_plane] Writing base 007A2000 00000000 0 0 4096 [ 299.107340] [drm:ivb_manual_fdi_link_train] FDI_RX_IIR before link train 0x0 [ 299.107349] [drm:ivb_manual_fdi_link_train] FDI_RX_IIR 0x100 [ 299.107352] [drm:ivb_manual_fdi_link_train] FDI train 1 done, level 0. [ 299.107359] [drm:ivb_manual_fdi_link_train] FDI_RX_IIR 0x600 [ 299.107361] [drm:ivb_manual_fdi_link_train] FDI train 2 done, level 0. [ 299.107362] [drm:ivb_manual_fdi_link_train] FDI train done. [ 299.107366] [drm:intel_enable_shared_dpll] enable PCH DPLL A (active 0, on? 0)for crtc 5 [ 299.107367] [drm:intel_enable_shared_dpll] enabling PCH DPLL A [ 299.109247] [drm:intel_update_fbc] disabled per chip default [ 299.109252] [drm:intel_connector_check_state] [CONNECTOR:13:VGA-1] [ 299.109258] [drm:check_encoder_state] [ENCODER:14:DAC-14] [ 299.109261] [drm:check_encoder_state] [ENCODER:15:TMDS-15] [ 299.109263] [drm:check_encoder_state] [ENCODER:19:TMDS-19] [ 299.109265] [drm:check_encoder_state] [ENCODER:21:TMDS-21] [ 299.109268] [drm:check_encoder_state] [ENCODER:23:TMDS-23] [ 299.109270] [drm:check_crtc_state] [CRTC:5] [ 299.109281] [drm:check_crtc_state] [CRTC:8] [ 299.109282] [drm:check_crtc_state] [CRTC:11] [ 299.109283] [drm:check_shared_dpll_state] PCH DPLL A [ 299.109287] [drm:check_shared_dpll_state] PCH DPLL B [ 299.109303] [drm:intel_crtc_page_flip] flip queue: crtc already busy [ 299.109317] [drm:drm_mode_addfb] [FB:37] [ 299.109319] [drm:intel_crtc_set_config] [CRTC:5] [NOFB] [ 299.109320] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:5], mode_changed=1, fb_changed=0 [ 299.109322] [drm:intel_modeset_stage_output_state] [CONNECTOR:13:VGA-1] to [NOCRTC] [ 299.109322] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 299.109323] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 299.109324] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch [ 299.109326] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1 [ 299.109335] [drm:intel_update_fbc] no output, disabling [ 299.143112] [drm:intel_disable_shared_dpll] disable PCH DPLL A (active 1, on? 1) for crtc 5 [ 299.143121] [drm:intel_disable_shared_dpll] disabling PCH DPLL A [ 299.143543] [drm:ivb_modeset_global_resources] disabling fdi C rx [ 299.143551] [drm:check_encoder_state] [ENCODER:14:DAC-14] [ 299.143554] [drm:check_encoder_state] [ENCODER:15:TMDS-15] [ 299.143556] [drm:check_encoder_state] [ENCODER:19:TMDS-19] [ 299.143559] [drm:check_encoder_state] [ENCODER:21:TMDS-21] [ 299.143561] [drm:check_encoder_state] [ENCODER:23:TMDS-23] [ 299.143564] [drm:check_crtc_state] [CRTC:5] [ 299.143565] [drm:check_crtc_state] [CRTC:8] [ 299.143566] [drm:check_crtc_state] [CRTC:11] [ 299.143567] [drm:check_shared_dpll_state] PCH DPLL A [ 299.143571] [drm:check_shared_dpll_state] PCH DPLL B [ 299.143580] [drm:drm_mode_setcrtc] [CRTC:5] [ 299.143582] [drm:drm_mode_setcrtc] [CONNECTOR:13:VGA-1] [ 299.143584] [drm:intel_crtc_set_config] [CRTC:5] [FB:36] #connectors=1 (x y) (0 0) [ 299.143585] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set [ 299.143586] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:5], mode_changed=1, fb_changed=0 [ 299.143587] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 299.143589] [drm:intel_modeset_stage_output_state] [CONNECTOR:13:VGA-1] to [CRTC:5] [ 299.143590] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 299.143591] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch [ 299.143592] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 299.143594] [drm:connected_sink_compute_bpp] [CONNECTOR:13:VGA-1] checking for sink bpp constrains [ 299.143595] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1 [ 299.143596] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0 [ 299.143597] [drm:intel_dump_pipe_config] [CRTC:5][modeset] config for pipe A [ 299.143598] [drm:intel_dump_pipe_config] cpu_transcoder: A [ 299.143599] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 299.143601] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 3029219, gmch_n: 4194304, link_m: 126217, link_n: 524288, tu: 64 [ 299.143602] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 299.143603] [drm:intel_dump_pipe_config] requested mode: [ 299.143605] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x48 0xa [ 299.143606] [drm:intel_dump_pipe_config] adjusted mode: [ 299.143608] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x48 0xa [ 299.143609] [drm:intel_dump_crtc_timings] crtc timings: 65000 1024 1048 1184 1344 768 771 777 806, type: 0x48 flags: 0xa [ 299.143610] [drm:intel_dump_pipe_config] port clock: 65000 [ 299.143611] [drm:intel_dump_pipe_config] pipe src size: 1024x768 [ 299.143612] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 299.143614] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 299.143615] [drm:intel_dump_pipe_config] ips: 0 [ 299.143615] [drm:intel_dump_pipe_config] double wide: 0 [ 299.143623] [drm:ivb_modeset_global_resources] disabling fdi C rx [ 299.143635] [drm:intel_get_shared_dpll] CRTC:5 allocated PCH DPLL A [ 299.143636] [drm:intel_get_shared_dpll] using PCH DPLL A for pipe A [ 299.143637] [drm:intel_prepare_shared_dpll] setting up PCH DPLL A [ 299.143648] [drm:ironlake_update_primary_plane] Writing base 004A2000 00000000 0 0 4096 [ 299.144345] [drm:ivb_manual_fdi_link_train] FDI_RX_IIR before link train 0x0 [ 299.144354] [drm:ivb_manual_fdi_link_train] FDI_RX_IIR 0x100 [ 299.144356] [drm:ivb_manual_fdi_link_train] FDI train 1 done, level 0. [ 299.144364] [drm:ivb_manual_fdi_link_train] FDI_RX_IIR 0x600 [ 299.144366] [drm:ivb_manual_fdi_link_train] FDI train 2 done, level 0. [ 299.144367] [drm:ivb_manual_fdi_link_train] FDI train done. [ 299.144370] [drm:intel_enable_shared_dpll] enable PCH DPLL A (active 0, on? 0)for crtc 5 [ 299.144372] [drm:intel_enable_shared_dpll] enabling PCH DPLL A [ 299.146252] [drm:intel_update_fbc] disabled per chip default [ 299.146258] [drm:intel_connector_check_state] [CONNECTOR:13:VGA-1] [ 299.146263] [drm:check_encoder_state] [ENCODER:14:DAC-14] [ 299.146266] [drm:check_encoder_state] [ENCODER:15:TMDS-15] [ 299.146268] [drm:check_encoder_state] [ENCODER:19:TMDS-19] [ 299.146271] [drm:check_encoder_state] [ENCODER:21:TMDS-21] [ 299.146274] [drm:check_encoder_state] [ENCODER:23:TMDS-23] [ 299.146276] [drm:check_crtc_state] [CRTC:5] [ 299.146288] [drm:check_crtc_state] [CRTC:8] [ 299.146289] [drm:check_crtc_state] [CRTC:11] [ 299.146290] [drm:check_shared_dpll_state] PCH DPLL A [ 299.146294] [drm:check_shared_dpll_state] PCH DPLL B [ 299.146309] [drm:intel_crtc_page_flip] flip queue: crtc already busy [ 299.146324] [drm:drm_mode_addfb] [FB:39] [ 299.146326] [drm:intel_crtc_set_config] [CRTC:5] [NOFB] [ 299.146328] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:5], mode_changed=1, fb_changed=0 [ 299.146329] [drm:intel_modeset_stage_output_state] [CONNECTOR:13:VGA-1] to [NOCRTC] [ 299.146330] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 299.146331] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 299.146332] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch [ 299.146333] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1 [ 299.146342] [drm:intel_update_fbc] no output, disabling [ 299.180107] [drm:intel_disable_shared_dpll] disable PCH DPLL A (active 1, on? 1) for crtc 5 [ 299.180117] [drm:intel_disable_shared_dpll] disabling PCH DPLL A [ 299.180541] [drm:ivb_modeset_global_resources] disabling fdi C rx [ 299.180549] [drm:check_encoder_state] [ENCODER:14:DAC-14] [ 299.180552] [drm:check_encoder_state] [ENCODER:15:TMDS-15] [ 299.180555] [drm:check_encoder_state] [ENCODER:19:TMDS-19] [ 299.180557] [drm:check_encoder_state] [ENCODER:21:TMDS-21] [ 299.180560] [drm:check_encoder_state] [ENCODER:23:TMDS-23] [ 299.180562] [drm:check_crtc_state] [CRTC:5] [ 299.180563] [drm:check_crtc_state] [CRTC:8] [ 299.180564] [drm:check_crtc_state] [CRTC:11] [ 299.180565] [drm:check_shared_dpll_state] PCH DPLL A [ 299.180569] [drm:check_shared_dpll_state] PCH DPLL B [ 299.180578] [drm:drm_mode_setcrtc] [CRTC:5] [ 299.180580] [drm:drm_mode_setcrtc] [CONNECTOR:13:VGA-1] [ 299.180581] [drm:intel_crtc_set_config] [CRTC:5] [FB:37] #connectors=1 (x y) (0 0) [ 299.180582] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set [ 299.180584] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:5], mode_changed=1, fb_changed=0 [ 299.180585] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 299.180586] [drm:intel_modeset_stage_output_state] [CONNECTOR:13:VGA-1] to [CRTC:5] [ 299.180587] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 299.180588] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch [ 299.180590] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 299.180591] [drm:connected_sink_compute_bpp] [CONNECTOR:13:VGA-1] checking for sink bpp constrains [ 299.180593] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1 [ 299.180594] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0 [ 299.180595] [drm:intel_dump_pipe_config] [CRTC:5][modeset] config for pipe A [ 299.180596] [drm:intel_dump_pipe_config] cpu_transcoder: A [ 299.180597] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 299.180598] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 3029219, gmch_n: 4194304, link_m: 126217, link_n: 524288, tu: 64 [ 299.180600] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 299.180601] [drm:intel_dump_pipe_config] requested mode: [ 299.180603] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x48 0xa [ 299.180603] [drm:intel_dump_pipe_config] adjusted mode: [ 299.180605] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x48 0xa [ 299.180607] [drm:intel_dump_crtc_timings] crtc timings: 65000 1024 1048 1184 1344 768 771 777 806, type: 0x48 flags: 0xa [ 299.180608] [drm:intel_dump_pipe_config] port clock: 65000 [ 299.180609] [drm:intel_dump_pipe_config] pipe src size: 1024x768 [ 299.180610] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 299.180611] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 299.180612] [drm:intel_dump_pipe_config] ips: 0 [ 299.180613] [drm:intel_dump_pipe_config] double wide: 0 [ 299.180620] [drm:ivb_modeset_global_resources] disabling fdi C rx [ 299.180632] [drm:intel_get_shared_dpll] CRTC:5 allocated PCH DPLL A [ 299.180633] [drm:intel_get_shared_dpll] using PCH DPLL A for pipe A [ 299.180634] [drm:intel_prepare_shared_dpll] setting up PCH DPLL A [ 299.180641] [drm:ironlake_update_primary_plane] Writing base 007A2000 00000000 0 0 4096 [ 299.181339] [drm:ivb_manual_fdi_link_train] FDI_RX_IIR before link train 0x0 [ 299.181347] [drm:ivb_manual_fdi_link_train] FDI_RX_IIR 0x100 [ 299.181350] [drm:ivb_manual_fdi_link_train] FDI train 1 done, level 0. [ 299.181357] [drm:ivb_manual_fdi_link_train] FDI_RX_IIR 0x600 [ 299.181359] [drm:ivb_manual_fdi_link_train] FDI train 2 done, level 0. [ 299.181360] [drm:ivb_manual_fdi_link_train] FDI train done. [ 299.181363] [drm:intel_enable_shared_dpll] enable PCH DPLL A (active 0, on? 0)for crtc 5 [ 299.181364] [drm:intel_enable_shared_dpll] enabling PCH DPLL A [ 299.183245] [drm:intel_update_fbc] disabled per chip default [ 299.183250] [drm:intel_connector_check_state] [CONNECTOR:13:VGA-1] [ 299.183256] [drm:check_encoder_state] [ENCODER:14:DAC-14] [ 299.183258] [drm:check_encoder_state] [ENCODER:15:TMDS-15] [ 299.183261] [drm:check_encoder_state] [ENCODER:19:TMDS-19] [ 299.183263] [drm:check_encoder_state] [ENCODER:21:TMDS-21] [ 299.183266] [drm:check_encoder_state] [ENCODER:23:TMDS-23] [ 299.183268] [drm:check_crtc_state] [CRTC:5] [ 299.183280] [drm:check_crtc_state] [CRTC:8] [ 299.183281] [drm:check_crtc_state] [CRTC:11] [ 299.183282] [drm:check_shared_dpll_state] PCH DPLL A [ 299.183286] [drm:check_shared_dpll_state] PCH DPLL B [ 299.183301] [drm:intel_crtc_page_flip] flip queue: crtc already busy [ 299.183316] [drm:drm_mode_addfb] [FB:36] [ 299.183318] [drm:intel_crtc_set_config] [CRTC:5] [NOFB] [ 299.183320] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:5], mode_changed=1, fb_changed=0 [ 299.183321] [drm:intel_modeset_stage_output_state] [CONNECTOR:13:VGA-1] to [NOCRTC] [ 299.183322] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 299.183323] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 299.183324] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch [ 299.183325] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1 [ 299.183334] [drm:intel_update_fbc] no output, disabling [ 299.217110] [drm:intel_disable_shared_dpll] disable PCH DPLL A (active 1, on? 1) for crtc 5 [ 299.217120] [drm:intel_disable_shared_dpll] disabling PCH DPLL A [ 299.217541] [drm:ivb_modeset_global_resources] disabling fdi C rx [ 299.217549] [drm:check_encoder_state] [ENCODER:14:DAC-14] [ 299.217552] [drm:check_encoder_state] [ENCODER:15:TMDS-15] [ 299.217554] [drm:check_encoder_state] [ENCODER:19:TMDS-19] [ 299.217557] [drm:check_encoder_state] [ENCODER:21:TMDS-21] [ 299.217559] [drm:check_encoder_state] [ENCODER:23:TMDS-23] [ 299.217562] [drm:check_crtc_state] [CRTC:5] [ 299.217563] [drm:check_crtc_state] [CRTC:8] [ 299.217564] [drm:check_crtc_state] [CRTC:11] [ 299.217565] [drm:check_shared_dpll_state] PCH DPLL A [ 299.217569] [drm:check_shared_dpll_state] PCH DPLL B [ 299.217578] [drm:drm_mode_setcrtc] [CRTC:5] [ 299.217580] [drm:drm_mode_setcrtc] [CONNECTOR:13:VGA-1] [ 299.217581] [drm:intel_crtc_set_config] [CRTC:5] [FB:39] #connectors=1 (x y) (0 0) [ 299.217583] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set [ 299.217584] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:5], mode_changed=1, fb_changed=0 [ 299.217585] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 299.217586] [drm:intel_modeset_stage_output_state] [CONNECTOR:13:VGA-1] to [CRTC:5] [ 299.217587] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 299.217588] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch [ 299.217590] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 299.217591] [drm:connected_sink_compute_bpp] [CONNECTOR:13:VGA-1] checking for sink bpp constrains [ 299.217593] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1 [ 299.217594] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0 [ 299.217595] [drm:intel_dump_pipe_config] [CRTC:5][modeset] config for pipe A [ 299.217596] [drm:intel_dump_pipe_config] cpu_transcoder: A [ 299.217597] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 299.217599] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 3029219, gmch_n: 4194304, link_m: 126217, link_n: 524288, tu: 64 [ 299.217600] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 299.217601] [drm:intel_dump_pipe_config] requested mode: [ 299.217603] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x48 0xa [ 299.217604] [drm:intel_dump_pipe_config] adjusted mode: [ 299.217606] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x48 0xa [ 299.217607] [drm:intel_dump_crtc_timings] crtc timings: 65000 1024 1048 1184 1344 768 771 777 806, type: 0x48 flags: 0xa [ 299.217608] [drm:intel_dump_pipe_config] port clock: 65000 [ 299.217609] [drm:intel_dump_pipe_config] pipe src size: 1024x768 [ 299.217610] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 299.217612] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 299.217612] [drm:intel_dump_pipe_config] ips: 0 [ 299.217613] [drm:intel_dump_pipe_config] double wide: 0 [ 299.217620] [drm:ivb_modeset_global_resources] disabling fdi C rx [ 299.217632] [drm:intel_get_shared_dpll] CRTC:5 allocated PCH DPLL A [ 299.217633] [drm:intel_get_shared_dpll] using PCH DPLL A for pipe A [ 299.217634] [drm:intel_prepare_shared_dpll] setting up PCH DPLL A [ 299.217644] [drm:ironlake_update_primary_plane] Writing base 004A2000 00000000 0 0 4096 [ 299.218338] [drm:ivb_manual_fdi_link_train] FDI_RX_IIR before link train 0x0 [ 299.218347] [drm:ivb_manual_fdi_link_train] FDI_RX_IIR 0x100 [ 299.218350] [drm:ivb_manual_fdi_link_train] FDI train 1 done, level 0. [ 299.218357] [drm:ivb_manual_fdi_link_train] FDI_RX_IIR 0x600 [ 299.218359] [drm:ivb_manual_fdi_link_train] FDI train 2 done, level 0. [ 299.218360] [drm:ivb_manual_fdi_link_train] FDI train done. [ 299.218364] [drm:intel_enable_shared_dpll] enable PCH DPLL A (active 0, on? 0)for crtc 5 [ 299.218364] [drm:intel_enable_shared_dpll] enabling PCH DPLL A [ 299.220247] [drm:intel_update_fbc] disabled per chip default [ 299.220252] [drm:intel_connector_check_state] [CONNECTOR:13:VGA-1] [ 299.220258] [drm:check_encoder_state] [ENCODER:14:DAC-14] [ 299.220260] [drm:check_encoder_state] [ENCODER:15:TMDS-15] [ 299.220263] [drm:check_encoder_state] [ENCODER:19:TMDS-19] [ 299.220265] [drm:check_encoder_state] [ENCODER:21:TMDS-21] [ 299.220268] [drm:check_encoder_state] [ENCODER:23:TMDS-23] [ 299.220270] [drm:check_crtc_state] [CRTC:5] [ 299.220282] [drm:check_crtc_state] [CRTC:8] [ 299.220283] [drm:check_crtc_state] [CRTC:11] [ 299.220284] [drm:check_shared_dpll_state] PCH DPLL A [ 299.220288] [drm:check_shared_dpll_state] PCH DPLL B [ 299.220303] [drm:intel_crtc_page_flip] flip queue: crtc already busy [ 299.220318] [drm:drm_mode_addfb] [FB:37] [ 299.220320] [drm:intel_crtc_set_config] [CRTC:5] [NOFB] [ 299.220322] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:5], mode_changed=1, fb_changed=0 [ 299.220323] [drm:intel_modeset_stage_output_state] [CONNECTOR:13:VGA-1] to [NOCRTC] [ 299.220324] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 299.220325] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 299.220326] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch [ 299.220327] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1 [ 299.220336] [drm:intel_update_fbc] no output, disabling [ 299.254106] [drm:intel_disable_shared_dpll] disable PCH DPLL A (active 1, on? 1) for crtc 5 [ 299.254115] [drm:intel_disable_shared_dpll] disabling PCH DPLL A [ 299.254540] [drm:ivb_modeset_global_resources] disabling fdi C rx [ 299.254546] [drm:check_encoder_state] [ENCODER:14:DAC-14] [ 299.254549] [drm:check_encoder_state] [ENCODER:15:TMDS-15] [ 299.254552] [drm:check_encoder_state] [ENCODER:19:TMDS-19] [ 299.254554] [drm:check_encoder_state] [ENCODER:21:TMDS-21] [ 299.254557] [drm:check_encoder_state] [ENCODER:23:TMDS-23] [ 299.254559] [drm:check_crtc_state] [CRTC:5] [ 299.254560] [drm:check_crtc_state] [CRTC:8] [ 299.254561] [drm:check_crtc_state] [CRTC:11] [ 299.254562] [drm:check_shared_dpll_state] PCH DPLL A [ 299.254567] [drm:check_shared_dpll_state] PCH DPLL B [ 299.254575] [drm:drm_mode_setcrtc] [CRTC:5] [ 299.254578] [drm:drm_mode_setcrtc] [CONNECTOR:13:VGA-1] [ 299.254579] [drm:intel_crtc_set_config] [CRTC:5] [FB:36] #connectors=1 (x y) (0 0) [ 299.254580] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set [ 299.254581] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:5], mode_changed=1, fb_changed=0 [ 299.254582] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 299.254584] [drm:intel_modeset_stage_output_state] [CONNECTOR:13:VGA-1] to [CRTC:5] [ 299.254585] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 299.254586] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch [ 299.254587] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 299.254589] [drm:connected_sink_compute_bpp] [CONNECTOR:13:VGA-1] checking for sink bpp constrains [ 299.254590] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1 [ 299.254591] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0 [ 299.254593] [drm:intel_dump_pipe_config] [CRTC:5][modeset] config for pipe A [ 299.254593] [drm:intel_dump_pipe_config] cpu_transcoder: A [ 299.254594] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 299.254596] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 3029219, gmch_n: 4194304, link_m: 126217, link_n: 524288, tu: 64 [ 299.254597] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 299.254598] [drm:intel_dump_pipe_config] requested mode: [ 299.254600] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x48 0xa [ 299.254601] [drm:intel_dump_pipe_config] adjusted mode: [ 299.254603] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x48 0xa [ 299.254605] [drm:intel_dump_crtc_timings] crtc timings: 65000 1024 1048 1184 1344 768 771 777 806, type: 0x48 flags: 0xa [ 299.254605] [drm:intel_dump_pipe_config] port clock: 65000 [ 299.254606] [drm:intel_dump_pipe_config] pipe src size: 1024x768 [ 299.254608] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 299.254609] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 299.254610] [drm:intel_dump_pipe_config] ips: 0 [ 299.254611] [drm:intel_dump_pipe_config] double wide: 0 [ 299.254618] [drm:ivb_modeset_global_resources] disabling fdi C rx [ 299.254630] [drm:intel_get_shared_dpll] CRTC:5 allocated PCH DPLL A [ 299.254631] [drm:intel_get_shared_dpll] using PCH DPLL A for pipe A [ 299.254632] [drm:intel_prepare_shared_dpll] setting up PCH DPLL A [ 299.254642] [drm:ironlake_update_primary_plane] Writing base 007A2000 00000000 0 0 4096 [ 299.255340] [drm:ivb_manual_fdi_link_train] FDI_RX_IIR before link train 0x0 [ 299.255349] [drm:ivb_manual_fdi_link_train] FDI_RX_IIR 0x100 [ 299.255352] [drm:ivb_manual_fdi_link_train] FDI train 1 done, level 0. [ 299.255359] [drm:ivb_manual_fdi_link_train] FDI_RX_IIR 0x600 [ 299.255361] [drm:ivb_manual_fdi_link_train] FDI train 2 done, level 0. [ 299.255362] [drm:ivb_manual_fdi_link_train] FDI train done. [ 299.255366] [drm:intel_enable_shared_dpll] enable PCH DPLL A (active 0, on? 0)for crtc 5 [ 299.255367] [drm:intel_enable_shared_dpll] enabling PCH DPLL A [ 299.257248] [drm:intel_update_fbc] disabled per chip default [ 299.257253] [drm:intel_connector_check_state] [CONNECTOR:13:VGA-1] [ 299.257259] [drm:check_encoder_state] [ENCODER:14:DAC-14] [ 299.257262] [drm:check_encoder_state] [ENCODER:15:TMDS-15] [ 299.257264] [drm:check_encoder_state] [ENCODER:19:TMDS-19] [ 299.257267] [drm:check_encoder_state] [ENCODER:21:TMDS-21] [ 299.257269] [drm:check_encoder_state] [ENCODER:23:TMDS-23] [ 299.257272] [drm:check_crtc_state] [CRTC:5] [ 299.257283] [drm:check_crtc_state] [CRTC:8] [ 299.257284] [drm:check_crtc_state] [CRTC:11] [ 299.257285] [drm:check_shared_dpll_state] PCH DPLL A [ 299.257289] [drm:check_shared_dpll_state] PCH DPLL B [ 299.257305] [drm:intel_crtc_page_flip] flip queue: crtc already busy [ 299.257316] [drm:drm_mode_addfb] [FB:39] [ 299.257319] [drm:intel_crtc_set_config] [CRTC:5] [NOFB] [ 299.257320] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:5], mode_changed=1, fb_changed=0 [ 299.257321] [drm:intel_modeset_stage_output_state] [CONNECTOR:13:VGA-1] to [NOCRTC] [ 299.257322] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 299.257323] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 299.257324] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch [ 299.257325] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1 [ 299.257337] [drm:intel_update_fbc] no output, disabling [ 299.291108] [drm:intel_disable_shared_dpll] disable PCH DPLL A (active 1, on? 1) for crtc 5 [ 299.291117] [drm:intel_disable_shared_dpll] disabling PCH DPLL A [ 299.291539] [drm:ivb_modeset_global_resources] disabling fdi C rx [ 299.291547] [drm:check_encoder_state] [ENCODER:14:DAC-14] [ 299.291550] [drm:check_encoder_state] [ENCODER:15:TMDS-15] [ 299.291552] [drm:check_encoder_state] [ENCODER:19:TMDS-19] [ 299.291555] [drm:check_encoder_state] [ENCODER:21:TMDS-21] [ 299.291557] [drm:check_encoder_state] [ENCODER:23:TMDS-23] [ 299.291560] [drm:check_crtc_state] [CRTC:5] [ 299.291561] [drm:check_crtc_state] [CRTC:8] [ 299.291562] [drm:check_crtc_state] [CRTC:11] [ 299.291563] [drm:check_shared_dpll_state] PCH DPLL A [ 299.291567] [drm:check_shared_dpll_state] PCH DPLL B [ 299.291576] [drm:drm_mode_setcrtc] [CRTC:5] [ 299.291578] [drm:drm_mode_setcrtc] [CONNECTOR:13:VGA-1] [ 299.291580] [drm:intel_crtc_set_config] [CRTC:5] [FB:37] #connectors=1 (x y) (0 0) [ 299.291581] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set [ 299.291582] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:5], mode_changed=1, fb_changed=0 [ 299.291583] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 299.291584] [drm:intel_modeset_stage_output_state] [CONNECTOR:13:VGA-1] to [CRTC:5] [ 299.291585] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 299.291586] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch [ 299.291588] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 299.291589] [drm:connected_sink_compute_bpp] [CONNECTOR:13:VGA-1] checking for sink bpp constrains [ 299.291591] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1 [ 299.291592] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0 [ 299.291593] [drm:intel_dump_pipe_config] [CRTC:5][modeset] config for pipe A [ 299.291594] [drm:intel_dump_pipe_config] cpu_transcoder: A [ 299.291595] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 299.291597] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 3029219, gmch_n: 4194304, link_m: 126217, link_n: 524288, tu: 64 [ 299.291598] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 299.291599] [drm:intel_dump_pipe_config] requested mode: [ 299.291601] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x48 0xa [ 299.291602] [drm:intel_dump_pipe_config] adjusted mode: [ 299.291603] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x48 0xa [ 299.291605] [drm:intel_dump_crtc_timings] crtc timings: 65000 1024 1048 1184 1344 768 771 777 806, type: 0x48 flags: 0xa [ 299.291606] [drm:intel_dump_pipe_config] port clock: 65000 [ 299.291607] [drm:intel_dump_pipe_config] pipe src size: 1024x768 [ 299.291608] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 299.291609] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 299.291610] [drm:intel_dump_pipe_config] ips: 0 [ 299.291611] [drm:intel_dump_pipe_config] double wide: 0 [ 299.291618] [drm:ivb_modeset_global_resources] disabling fdi C rx [ 299.291630] [drm:intel_get_shared_dpll] CRTC:5 allocated PCH DPLL A [ 299.291631] [drm:intel_get_shared_dpll] using PCH DPLL A for pipe A [ 299.291632] [drm:intel_prepare_shared_dpll] setting up PCH DPLL A [ 299.291643] [drm:ironlake_update_primary_plane] Writing base 004A2000 00000000 0 0 4096 [ 299.292336] [drm:ivb_manual_fdi_link_train] FDI_RX_IIR before link train 0x0 [ 299.292345] [drm:ivb_manual_fdi_link_train] FDI_RX_IIR 0x100 [ 299.292347] [drm:ivb_manual_fdi_link_train] FDI train 1 done, level 0. [ 299.292355] [drm:ivb_manual_fdi_link_train] FDI_RX_IIR 0x600 [ 299.292357] [drm:ivb_manual_fdi_link_train] FDI train 2 done, level 0. [ 299.292358] [drm:ivb_manual_fdi_link_train] FDI train done. [ 299.292361] [drm:intel_enable_shared_dpll] enable PCH DPLL A (active 0, on? 0)for crtc 5 [ 299.292362] [drm:intel_enable_shared_dpll] enabling PCH DPLL A [ 299.294243] [drm:intel_update_fbc] disabled per chip default [ 299.294249] [drm:intel_connector_check_state] [CONNECTOR:13:VGA-1] [ 299.294253] [drm:check_encoder_state] [ENCODER:14:DAC-14] [ 299.294256] [drm:check_encoder_state] [ENCODER:15:TMDS-15] [ 299.294259] [drm:check_encoder_state] [ENCODER:19:TMDS-19] [ 299.294261] [drm:check_encoder_state] [ENCODER:21:TMDS-21] [ 299.294264] [drm:check_encoder_state] [ENCODER:23:TMDS-23] [ 299.294266] [drm:check_crtc_state] [CRTC:5] [ 299.294278] [drm:check_crtc_state] [CRTC:8] [ 299.294279] [drm:check_crtc_state] [CRTC:11] [ 299.294280] [drm:check_shared_dpll_state] PCH DPLL A [ 299.294284] [drm:check_shared_dpll_state] PCH DPLL B [ 299.294299] [drm:intel_crtc_page_flip] flip queue: crtc already busy [ 299.294313] [drm:drm_mode_addfb] [FB:36] [ 299.294315] [drm:intel_crtc_set_config] [CRTC:5] [NOFB] [ 299.294317] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:5], mode_changed=1, fb_changed=0 [ 299.294318] [drm:intel_modeset_stage_output_state] [CONNECTOR:13:VGA-1] to [NOCRTC] [ 299.294319] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 299.294320] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 299.294321] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch [ 299.294322] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1 [ 299.294331] [drm:intel_update_fbc] no output, disabling [ 299.328103] [drm:intel_disable_shared_dpll] disable PCH DPLL A (active 1, on? 1) for crtc 5 [ 299.328111] [drm:intel_disable_shared_dpll] disabling PCH DPLL A [ 299.328536] [drm:ivb_modeset_global_resources] disabling fdi C rx [ 299.328542] [drm:check_encoder_state] [ENCODER:14:DAC-14] [ 299.328545] [drm:check_encoder_state] [ENCODER:15:TMDS-15] [ 299.328548] [drm:check_encoder_state] [ENCODER:19:TMDS-19] [ 299.328550] [drm:check_encoder_state] [ENCODER:21:TMDS-21] [ 299.328553] [drm:check_encoder_state] [ENCODER:23:TMDS-23] [ 299.328555] [drm:check_crtc_state] [CRTC:5] [ 299.328556] [drm:check_crtc_state] [CRTC:8] [ 299.328557] [drm:check_crtc_state] [CRTC:11] [ 299.328558] [drm:check_shared_dpll_state] PCH DPLL A [ 299.328563] [drm:check_shared_dpll_state] PCH DPLL B [ 299.328571] [drm:drm_mode_setcrtc] [CRTC:5] [ 299.328574] [drm:drm_mode_setcrtc] [CONNECTOR:13:VGA-1] [ 299.328575] [drm:intel_crtc_set_config] [CRTC:5] [FB:39] #connectors=1 (x y) (0 0) [ 299.328576] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set [ 299.328578] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:5], mode_changed=1, fb_changed=0 [ 299.328579] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 299.328580] [drm:intel_modeset_stage_output_state] [CONNECTOR:13:VGA-1] to [CRTC:5] [ 299.328581] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 299.328582] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch [ 299.328583] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 299.328585] [drm:connected_sink_compute_bpp] [CONNECTOR:13:VGA-1] checking for sink bpp constrains [ 299.328586] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1 [ 299.328588] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0 [ 299.328589] [drm:intel_dump_pipe_config] [CRTC:5][modeset] config for pipe A [ 299.328590] [drm:intel_dump_pipe_config] cpu_transcoder: A [ 299.328590] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 299.328592] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 3029219, gmch_n: 4194304, link_m: 126217, link_n: 524288, tu: 64 [ 299.328593] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 299.328594] [drm:intel_dump_pipe_config] requested mode: [ 299.328596] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x48 0xa [ 299.328597] [drm:intel_dump_pipe_config] adjusted mode: [ 299.328599] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x48 0xa [ 299.328601] [drm:intel_dump_crtc_timings] crtc timings: 65000 1024 1048 1184 1344 768 771 777 806, type: 0x48 flags: 0xa [ 299.328602] [drm:intel_dump_pipe_config] port clock: 65000 [ 299.328603] [drm:intel_dump_pipe_config] pipe src size: 1024x768 [ 299.328604] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 299.328605] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 299.328606] [drm:intel_dump_pipe_config] ips: 0 [ 299.328607] [drm:intel_dump_pipe_config] double wide: 0 [ 299.328614] [drm:ivb_modeset_global_resources] disabling fdi C rx [ 299.328627] [drm:intel_get_shared_dpll] CRTC:5 allocated PCH DPLL A [ 299.328628] [drm:intel_get_shared_dpll] using PCH DPLL A for pipe A [ 299.328629] [drm:intel_prepare_shared_dpll] setting up PCH DPLL A [ 299.328640] [drm:ironlake_update_primary_plane] Writing base 007A2000 00000000 0 0 4096 [ 299.329337] [drm:ivb_manual_fdi_link_train] FDI_RX_IIR before link train 0x0 [ 299.329345] [drm:ivb_manual_fdi_link_train] FDI_RX_IIR 0x100 [ 299.329348] [drm:ivb_manual_fdi_link_train] FDI train 1 done, level 0. [ 299.329356] [drm:ivb_manual_fdi_link_train] FDI_RX_IIR 0x600 [ 299.329358] [drm:ivb_manual_fdi_link_train] FDI train 2 done, level 0. [ 299.329358] [drm:ivb_manual_fdi_link_train] FDI train done. [ 299.329362] [drm:intel_enable_shared_dpll] enable PCH DPLL A (active 0, on? 0)for crtc 5 [ 299.329363] [drm:intel_enable_shared_dpll] enabling PCH DPLL A [ 299.331243] [drm:intel_update_fbc] disabled per chip default [ 299.331249] [drm:intel_connector_check_state] [CONNECTOR:13:VGA-1] [ 299.331255] [drm:check_encoder_state] [ENCODER:14:DAC-14] [ 299.331257] [drm:check_encoder_state] [ENCODER:15:TMDS-15] [ 299.331259] [drm:check_encoder_state] [ENCODER:19:TMDS-19] [ 299.331262] [drm:check_encoder_state] [ENCODER:21:TMDS-21] [ 299.331264] [drm:check_encoder_state] [ENCODER:23:TMDS-23] [ 299.331267] [drm:check_crtc_state] [CRTC:5] [ 299.331279] [drm:check_crtc_state] [CRTC:8] [ 299.331280] [drm:check_crtc_state] [CRTC:11] [ 299.331281] [drm:check_shared_dpll_state] PCH DPLL A [ 299.331285] [drm:check_shared_dpll_state] PCH DPLL B [ 299.331300] [drm:intel_crtc_page_flip] flip queue: crtc already busy [ 299.331314] [drm:drm_mode_addfb] [FB:37] [ 299.331317] [drm:intel_crtc_set_config] [CRTC:5] [NOFB] [ 299.331318] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:5], mode_changed=1, fb_changed=0 [ 299.331319] [drm:intel_modeset_stage_output_state] [CONNECTOR:13:VGA-1] to [NOCRTC] [ 299.331320] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 299.331321] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 299.331322] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch [ 299.331323] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1 [ 299.331333] [drm:intel_update_fbc] no output, disabling [ 299.365106] [drm:intel_disable_shared_dpll] disable PCH DPLL A (active 1, on? 1) for crtc 5 [ 299.365116] [drm:intel_disable_shared_dpll] disabling PCH DPLL A [ 299.365539] [drm:ivb_modeset_global_resources] disabling fdi C rx [ 299.365546] [drm:check_encoder_state] [ENCODER:14:DAC-14] [ 299.365548] [drm:check_encoder_state] [ENCODER:15:TMDS-15] [ 299.365551] [drm:check_encoder_state] [ENCODER:19:TMDS-19] [ 299.365553] [drm:check_encoder_state] [ENCODER:21:TMDS-21] [ 299.365556] [drm:check_encoder_state] [ENCODER:23:TMDS-23] [ 299.365559] [drm:check_crtc_state] [CRTC:5] [ 299.365560] [drm:check_crtc_state] [CRTC:8] [ 299.365561] [drm:check_crtc_state] [CRTC:11] [ 299.365562] [drm:check_shared_dpll_state] PCH DPLL A [ 299.365566] [drm:check_shared_dpll_state] PCH DPLL B [ 299.365575] [drm:drm_mode_setcrtc] [CRTC:5] [ 299.365577] [drm:drm_mode_setcrtc] [CONNECTOR:13:VGA-1] [ 299.365578] [drm:intel_crtc_set_config] [CRTC:5] [FB:36] #connectors=1 (x y) (0 0) [ 299.365579] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set [ 299.365581] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:5], mode_changed=1, fb_changed=0 [ 299.365582] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 299.365583] [drm:intel_modeset_stage_output_state] [CONNECTOR:13:VGA-1] to [CRTC:5] [ 299.365584] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 299.365585] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch [ 299.365587] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 299.365588] [drm:connected_sink_compute_bpp] [CONNECTOR:13:VGA-1] checking for sink bpp constrains [ 299.365590] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1 [ 299.365591] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0 [ 299.365592] [drm:intel_dump_pipe_config] [CRTC:5][modeset] config for pipe A [ 299.365593] [drm:intel_dump_pipe_config] cpu_transcoder: A [ 299.365594] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 299.365595] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 3029219, gmch_n: 4194304, link_m: 126217, link_n: 524288, tu: 64 [ 299.365597] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 299.365597] [drm:intel_dump_pipe_config] requested mode: [ 299.365599] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x48 0xa [ 299.365600] [drm:intel_dump_pipe_config] adjusted mode: [ 299.365602] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x48 0xa [ 299.365604] [drm:intel_dump_crtc_timings] crtc timings: 65000 1024 1048 1184 1344 768 771 777 806, type: 0x48 flags: 0xa [ 299.365605] [drm:intel_dump_pipe_config] port clock: 65000 [ 299.365606] [drm:intel_dump_pipe_config] pipe src size: 1024x768 [ 299.365607] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 299.365608] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 299.365609] [drm:intel_dump_pipe_config] ips: 0 [ 299.365610] [drm:intel_dump_pipe_config] double wide: 0 [ 299.365618] [drm:ivb_modeset_global_resources] disabling fdi C rx [ 299.365629] [drm:intel_get_shared_dpll] CRTC:5 allocated PCH DPLL A [ 299.365630] [drm:intel_get_shared_dpll] using PCH DPLL A for pipe A [ 299.365631] [drm:intel_prepare_shared_dpll] setting up PCH DPLL A [ 299.365641] [drm:ironlake_update_primary_plane] Writing base 004A2000 00000000 0 0 4096 [ 299.366339] [drm:ivb_manual_fdi_link_train] FDI_RX_IIR before link train 0x0 [ 299.366348] [drm:ivb_manual_fdi_link_train] FDI_RX_IIR 0x100 [ 299.366350] [drm:ivb_manual_fdi_link_train] FDI train 1 done, level 0. [ 299.366356] [drm:ivb_manual_fdi_link_train] FDI_RX_IIR 0x600 [ 299.366358] [drm:ivb_manual_fdi_link_train] FDI train 2 done, level 0. [ 299.366359] [drm:ivb_manual_fdi_link_train] FDI train done. [ 299.366363] [drm:intel_enable_shared_dpll] enable PCH DPLL A (active 0, on? 0)for crtc 5 [ 299.366364] [drm:intel_enable_shared_dpll] enabling PCH DPLL A [ 299.368245] [drm:intel_update_fbc] disabled per chip default [ 299.368251] [drm:intel_connector_check_state] [CONNECTOR:13:VGA-1] [ 299.368256] [drm:check_encoder_state] [ENCODER:14:DAC-14] [ 299.368259] [drm:check_encoder_state] [ENCODER:15:TMDS-15] [ 299.368262] [drm:check_encoder_state] [ENCODER:19:TMDS-19] [ 299.368264] [drm:check_encoder_state] [ENCODER:21:TMDS-21] [ 299.368267] [drm:check_encoder_state] [ENCODER:23:TMDS-23] [ 299.368269] [drm:check_crtc_state] [CRTC:5] [ 299.368281] [drm:check_crtc_state] [CRTC:8] [ 299.368282] [drm:check_crtc_state] [CRTC:11] [ 299.368282] [drm:check_shared_dpll_state] PCH DPLL A [ 299.368286] [drm:check_shared_dpll_state] PCH DPLL B [ 299.368302] [drm:intel_crtc_page_flip] flip queue: crtc already busy [ 299.368316] [drm:drm_mode_addfb] [FB:39] [ 299.368318] [drm:intel_crtc_set_config] [CRTC:5] [NOFB] [ 299.368320] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:5], mode_changed=1, fb_changed=0 [ 299.368321] [drm:intel_modeset_stage_output_state] [CONNECTOR:13:VGA-1] to [NOCRTC] [ 299.368322] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 299.368323] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 299.368324] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch [ 299.368325] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1 [ 299.368334] [drm:intel_update_fbc] no output, disabling [ 299.402102] [drm:intel_disable_shared_dpll] disable PCH DPLL A (active 1, on? 1) for crtc 5 [ 299.402110] [drm:intel_disable_shared_dpll] disabling PCH DPLL A [ 299.402534] [drm:ivb_modeset_global_resources] disabling fdi C rx [ 299.402542] [drm:check_encoder_state] [ENCODER:14:DAC-14] [ 299.402545] [drm:check_encoder_state] [ENCODER:15:TMDS-15] [ 299.402547] [drm:check_encoder_state] [ENCODER:19:TMDS-19] [ 299.402550] [drm:check_encoder_state] [ENCODER:21:TMDS-21] [ 299.402552] [drm:check_encoder_state] [ENCODER:23:TMDS-23] [ 299.402555] [drm:check_crtc_state] [CRTC:5] [ 299.402556] [drm:check_crtc_state] [CRTC:8] [ 299.402557] [drm:check_crtc_state] [CRTC:11] [ 299.402558] [drm:check_shared_dpll_state] PCH DPLL A [ 299.402562] [drm:check_shared_dpll_state] PCH DPLL B [ 299.402571] [drm:drm_mode_setcrtc] [CRTC:5] [ 299.402573] [drm:drm_mode_setcrtc] [CONNECTOR:13:VGA-1] [ 299.402575] [drm:intel_crtc_set_config] [CRTC:5] [FB:37] #connectors=1 (x y) (0 0) [ 299.402576] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set [ 299.402577] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:5], mode_changed=1, fb_changed=0 [ 299.402578] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 299.402579] [drm:intel_modeset_stage_output_state] [CONNECTOR:13:VGA-1] to [CRTC:5] [ 299.402580] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 299.402582] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch [ 299.402583] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 299.402584] [drm:connected_sink_compute_bpp] [CONNECTOR:13:VGA-1] checking for sink bpp constrains [ 299.402586] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1 [ 299.402587] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0 [ 299.402588] [drm:intel_dump_pipe_config] [CRTC:5][modeset] config for pipe A [ 299.402589] [drm:intel_dump_pipe_config] cpu_transcoder: A [ 299.402590] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 299.402592] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 3029219, gmch_n: 4194304, link_m: 126217, link_n: 524288, tu: 64 [ 299.402593] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 299.402594] [drm:intel_dump_pipe_config] requested mode: [ 299.402596] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x48 0xa [ 299.402597] [drm:intel_dump_pipe_config] adjusted mode: [ 299.402598] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x48 0xa [ 299.402600] [drm:intel_dump_crtc_timings] crtc timings: 65000 1024 1048 1184 1344 768 771 777 806, type: 0x48 flags: 0xa [ 299.402601] [drm:intel_dump_pipe_config] port clock: 65000 [ 299.402602] [drm:intel_dump_pipe_config] pipe src size: 1024x768 [ 299.402603] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 299.402604] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 299.402605] [drm:intel_dump_pipe_config] ips: 0 [ 299.402606] [drm:intel_dump_pipe_config] double wide: 0 [ 299.402614] [drm:ivb_modeset_global_resources] disabling fdi C rx [ 299.402625] [drm:intel_get_shared_dpll] CRTC:5 allocated PCH DPLL A [ 299.402626] [drm:intel_get_shared_dpll] using PCH DPLL A for pipe A [ 299.402627] [drm:intel_prepare_shared_dpll] setting up PCH DPLL A [ 299.402637] [drm:ironlake_update_primary_plane] Writing base 007A2000 00000000 0 0 4096 [ 299.403335] [drm:ivb_manual_fdi_link_train] FDI_RX_IIR before link train 0x0 [ 299.403344] [drm:ivb_manual_fdi_link_train] FDI_RX_IIR 0x100 [ 299.403347] [drm:ivb_manual_fdi_link_train] FDI train 1 done, level 0. [ 299.403354] [drm:ivb_manual_fdi_link_train] FDI_RX_IIR 0x600 [ 299.403356] [drm:ivb_manual_fdi_link_train] FDI train 2 done, level 0. [ 299.403357] [drm:ivb_manual_fdi_link_train] FDI train done. [ 299.403361] [drm:intel_enable_shared_dpll] enable PCH DPLL A (active 0, on? 0)for crtc 5 [ 299.403362] [drm:intel_enable_shared_dpll] enabling PCH DPLL A [ 299.405243] [drm:intel_update_fbc] disabled per chip default [ 299.405249] [drm:intel_connector_check_state] [CONNECTOR:13:VGA-1] [ 299.405255] [drm:check_encoder_state] [ENCODER:14:DAC-14] [ 299.405257] [drm:check_encoder_state] [ENCODER:15:TMDS-15] [ 299.405259] [drm:check_encoder_state] [ENCODER:19:TMDS-19] [ 299.405262] [drm:check_encoder_state] [ENCODER:21:TMDS-21] [ 299.405264] [drm:check_encoder_state] [ENCODER:23:TMDS-23] [ 299.405267] [drm:check_crtc_state] [CRTC:5] [ 299.405279] [drm:check_crtc_state] [CRTC:8] [ 299.405279] [drm:check_crtc_state] [CRTC:11] [ 299.405280] [drm:check_shared_dpll_state] PCH DPLL A [ 299.405284] [drm:check_shared_dpll_state] PCH DPLL B [ 299.405300] [drm:intel_crtc_page_flip] flip queue: crtc already busy [ 299.405314] [drm:drm_mode_addfb] [FB:36] [ 299.405316] [drm:intel_crtc_set_config] [CRTC:5] [NOFB] [ 299.405318] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:5], mode_changed=1, fb_changed=0 [ 299.405319] [drm:intel_modeset_stage_output_state] [CONNECTOR:13:VGA-1] to [NOCRTC] [ 299.405320] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 299.405321] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 299.405322] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch [ 299.405323] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1 [ 299.405332] [drm:intel_update_fbc] no output, disabling [ 299.439104] [drm:intel_disable_shared_dpll] disable PCH DPLL A (active 1, on? 1) for crtc 5 [ 299.439113] [drm:intel_disable_shared_dpll] disabling PCH DPLL A [ 299.439536] [drm:ivb_modeset_global_resources] disabling fdi C rx [ 299.439544] [drm:check_encoder_state] [ENCODER:14:DAC-14] [ 299.439547] [drm:check_encoder_state] [ENCODER:15:TMDS-15] [ 299.439549] [drm:check_encoder_state] [ENCODER:19:TMDS-19] [ 299.439552] [drm:check_encoder_state] [ENCODER:21:TMDS-21] [ 299.439554] [drm:check_encoder_state] [ENCODER:23:TMDS-23] [ 299.439557] [drm:check_crtc_state] [CRTC:5] [ 299.439558] [drm:check_crtc_state] [CRTC:8] [ 299.439559] [drm:check_crtc_state] [CRTC:11] [ 299.439560] [drm:check_shared_dpll_state] PCH DPLL A [ 299.439564] [drm:check_shared_dpll_state] PCH DPLL B [ 299.439573] [drm:drm_mode_setcrtc] [CRTC:5] [ 299.439575] [drm:drm_mode_setcrtc] [CONNECTOR:13:VGA-1] [ 299.439576] [drm:intel_crtc_set_config] [CRTC:5] [FB:39] #connectors=1 (x y) (0 0) [ 299.439578] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set [ 299.439579] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:5], mode_changed=1, fb_changed=0 [ 299.439580] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 299.439581] [drm:intel_modeset_stage_output_state] [CONNECTOR:13:VGA-1] to [CRTC:5] [ 299.439582] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 299.439583] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch [ 299.439585] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 299.439586] [drm:connected_sink_compute_bpp] [CONNECTOR:13:VGA-1] checking for sink bpp constrains [ 299.439588] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1 [ 299.439589] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0 [ 299.439590] [drm:intel_dump_pipe_config] [CRTC:5][modeset] config for pipe A [ 299.439591] [drm:intel_dump_pipe_config] cpu_transcoder: A [ 299.439592] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 299.439593] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 3029219, gmch_n: 4194304, link_m: 126217, link_n: 524288, tu: 64 [ 299.439595] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 299.439595] [drm:intel_dump_pipe_config] requested mode: [ 299.439598] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x48 0xa [ 299.439598] [drm:intel_dump_pipe_config] adjusted mode: [ 299.439600] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x48 0xa [ 299.439602] [drm:intel_dump_crtc_timings] crtc timings: 65000 1024 1048 1184 1344 768 771 777 806, type: 0x48 flags: 0xa [ 299.439603] [drm:intel_dump_pipe_config] port clock: 65000 [ 299.439604] [drm:intel_dump_pipe_config] pipe src size: 1024x768 [ 299.439605] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 299.439606] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 299.439607] [drm:intel_dump_pipe_config] ips: 0 [ 299.439608] [drm:intel_dump_pipe_config] double wide: 0 [ 299.439615] [drm:ivb_modeset_global_resources] disabling fdi C rx [ 299.439627] [drm:intel_get_shared_dpll] CRTC:5 allocated PCH DPLL A [ 299.439628] [drm:intel_get_shared_dpll] using PCH DPLL A for pipe A [ 299.439629] [drm:intel_prepare_shared_dpll] setting up PCH DPLL A [ 299.439639] [drm:ironlake_update_primary_plane] Writing base 004A2000 00000000 0 0 4096 [ 299.440336] [drm:ivb_manual_fdi_link_train] FDI_RX_IIR before link train 0x0 [ 299.440345] [drm:ivb_manual_fdi_link_train] FDI_RX_IIR 0x100 [ 299.440348] [drm:ivb_manual_fdi_link_train] FDI train 1 done, level 0. [ 299.440355] [drm:ivb_manual_fdi_link_train] FDI_RX_IIR 0x600 [ 299.440357] [drm:ivb_manual_fdi_link_train] FDI train 2 done, level 0. [ 299.440358] [drm:ivb_manual_fdi_link_train] FDI train done. [ 299.440362] [drm:intel_enable_shared_dpll] enable PCH DPLL A (active 0, on? 0)for crtc 5 [ 299.440362] [drm:intel_enable_shared_dpll] enabling PCH DPLL A [ 299.442244] [drm:intel_update_fbc] disabled per chip default [ 299.442249] [drm:intel_connector_check_state] [CONNECTOR:13:VGA-1] [ 299.442255] [drm:check_encoder_state] [ENCODER:14:DAC-14] [ 299.442257] [drm:check_encoder_state] [ENCODER:15:TMDS-15] [ 299.442260] [drm:check_encoder_state] [ENCODER:19:TMDS-19] [ 299.442263] [drm:check_encoder_state] [ENCODER:21:TMDS-21] [ 299.442265] [drm:check_encoder_state] [ENCODER:23:TMDS-23] [ 299.442267] [drm:check_crtc_state] [CRTC:5] [ 299.442279] [drm:check_crtc_state] [CRTC:8] [ 299.442280] [drm:check_crtc_state] [CRTC:11] [ 299.442281] [drm:check_shared_dpll_state] PCH DPLL A [ 299.442285] [drm:check_shared_dpll_state] PCH DPLL B [ 299.442301] [drm:intel_crtc_page_flip] flip queue: crtc already busy [ 299.442316] [drm:drm_mode_addfb] [FB:37] [ 299.442318] [drm:intel_crtc_set_config] [CRTC:5] [NOFB] [ 299.442319] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:5], mode_changed=1, fb_changed=0 [ 299.442320] [drm:intel_modeset_stage_output_state] [CONNECTOR:13:VGA-1] to [NOCRTC] [ 299.442321] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 299.442322] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 299.442323] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch [ 299.442325] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1 [ 299.442333] [drm:intel_update_fbc] no output, disabling [ 299.476100] [drm:intel_disable_shared_dpll] disable PCH DPLL A (active 1, on? 1) for crtc 5 [ 299.476109] [drm:intel_disable_shared_dpll] disabling PCH DPLL A [ 299.476532] [drm:ivb_modeset_global_resources] disabling fdi C rx [ 299.476541] [drm:check_encoder_state] [ENCODER:14:DAC-14] [ 299.476543] [drm:check_encoder_state] [ENCODER:15:TMDS-15] [ 299.476546] [drm:check_encoder_state] [ENCODER:19:TMDS-19] [ 299.476548] [drm:check_encoder_state] [ENCODER:21:TMDS-21] [ 299.476551] [drm:check_encoder_state] [ENCODER:23:TMDS-23] [ 299.476553] [drm:check_crtc_state] [CRTC:5] [ 299.476555] [drm:check_crtc_state] [CRTC:8] [ 299.476555] [drm:check_crtc_state] [CRTC:11] [ 299.476557] [drm:check_shared_dpll_state] PCH DPLL A [ 299.476561] [drm:check_shared_dpll_state] PCH DPLL B [ 299.476569] [drm:drm_mode_setcrtc] [CRTC:5] [ 299.476572] [drm:drm_mode_setcrtc] [CONNECTOR:13:VGA-1] [ 299.476573] [drm:intel_crtc_set_config] [CRTC:5] [FB:36] #connectors=1 (x y) (0 0) [ 299.476574] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set [ 299.476576] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:5], mode_changed=1, fb_changed=0 [ 299.476577] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 299.476578] [drm:intel_modeset_stage_output_state] [CONNECTOR:13:VGA-1] to [CRTC:5] [ 299.476579] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 299.476580] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch [ 299.476581] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 299.476583] [drm:connected_sink_compute_bpp] [CONNECTOR:13:VGA-1] checking for sink bpp constrains [ 299.476584] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1 [ 299.476586] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0 [ 299.476587] [drm:intel_dump_pipe_config] [CRTC:5][modeset] config for pipe A [ 299.476588] [drm:intel_dump_pipe_config] cpu_transcoder: A [ 299.476589] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 299.476590] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 3029219, gmch_n: 4194304, link_m: 126217, link_n: 524288, tu: 64 [ 299.476591] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 299.476592] [drm:intel_dump_pipe_config] requested mode: [ 299.476594] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x48 0xa [ 299.476595] [drm:intel_dump_pipe_config] adjusted mode: [ 299.476597] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x48 0xa [ 299.476599] [drm:intel_dump_crtc_timings] crtc timings: 65000 1024 1048 1184 1344 768 771 777 806, type: 0x48 flags: 0xa [ 299.476600] [drm:intel_dump_pipe_config] port clock: 65000 [ 299.476600] [drm:intel_dump_pipe_config] pipe src size: 1024x768 [ 299.476602] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 299.476603] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 299.476604] [drm:intel_dump_pipe_config] ips: 0 [ 299.476605] [drm:intel_dump_pipe_config] double wide: 0 [ 299.476612] [drm:ivb_modeset_global_resources] disabling fdi C rx [ 299.476624] [drm:intel_get_shared_dpll] CRTC:5 allocated PCH DPLL A [ 299.476625] [drm:intel_get_shared_dpll] using PCH DPLL A for pipe A [ 299.476626] [drm:intel_prepare_shared_dpll] setting up PCH DPLL A [ 299.476635] [drm:ironlake_update_primary_plane] Writing base 007A2000 00000000 0 0 4096 [ 299.477331] [drm:ivb_manual_fdi_link_train] FDI_RX_IIR before link train 0x0 [ 299.477340] [drm:ivb_manual_fdi_link_train] FDI_RX_IIR 0x100 [ 299.477342] [drm:ivb_manual_fdi_link_train] FDI train 1 done, level 0. [ 299.477350] [drm:ivb_manual_fdi_link_train] FDI_RX_IIR 0x600 [ 299.477352] [drm:ivb_manual_fdi_link_train] FDI train 2 done, level 0. [ 299.477352] [drm:ivb_manual_fdi_link_train] FDI train done. [ 299.477356] [drm:intel_enable_shared_dpll] enable PCH DPLL A (active 0, on? 0)for crtc 5 [ 299.477357] [drm:intel_enable_shared_dpll] enabling PCH DPLL A [ 299.479238] [drm:intel_update_fbc] disabled per chip default [ 299.479244] [drm:intel_connector_check_state] [CONNECTOR:13:VGA-1] [ 299.479249] [drm:check_encoder_state] [ENCODER:14:DAC-14] [ 299.479252] [drm:check_encoder_state] [ENCODER:15:TMDS-15] [ 299.479254] [drm:check_encoder_state] [ENCODER:19:TMDS-19] [ 299.479257] [drm:check_encoder_state] [ENCODER:21:TMDS-21] [ 299.479260] [drm:check_encoder_state] [ENCODER:23:TMDS-23] [ 299.479262] [drm:check_crtc_state] [CRTC:5] [ 299.479273] [drm:check_crtc_state] [CRTC:8] [ 299.479274] [drm:check_crtc_state] [CRTC:11] [ 299.479275] [drm:check_shared_dpll_state] PCH DPLL A [ 299.479279] [drm:check_shared_dpll_state] PCH DPLL B [ 299.479295] [drm:intel_crtc_page_flip] flip queue: crtc already busy [ 299.479309] [drm:drm_mode_addfb] [FB:39] [ 299.479311] [drm:intel_crtc_set_config] [CRTC:5] [NOFB] [ 299.479312] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:5], mode_changed=1, fb_changed=0 [ 299.479314] [drm:intel_modeset_stage_output_state] [CONNECTOR:13:VGA-1] to [NOCRTC] [ 299.479314] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 299.479315] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 299.479316] [drm:intel_modeset_stage_output_state] crtc disabled, full mode switch [ 299.479318] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1 [ 299.479330] [drm:intel_update_fbc] no output, disabling [ 299.513102] [drm:intel_disable_shared_dpll] disable PCH DPLL A (active 1, on? 1) for crtc 5 [ 299.513111] [drm:intel_disable_shared_dpll] disabling PCH DPLL A [ 299.513533] [drm:ivb_modeset_global_resources] disabling fdi C rx [ 299.513542] [drm:check_encoder_state] [ENCODER:14:DAC-14] [ 299.513544] [drm:check_encoder_state] [ENCODER:15:TMDS-15] [ 299.513547] [drm:check_encoder_state] [ENCODER:19:TMDS-19] [ 299.513549] [drm:check_encoder_state] [ENCODER:21:TMDS-21] [ 299.513552] [drm:check_encoder_state] [ENCODER:23:TMDS-23] [ 299.513554] [drm:check_crtc_state] [CRTC:5] [ 299.513555] [drm:check_crtc_state] [CRTC:8] [ 299.513556] [drm:check_crtc_state] [CRTC:11] [ 299.513557] [drm:check_shared_dpll_state] PCH DPLL A [ 299.513562] [drm:check_shared_dpll_state] PCH DPLL B [ 299.513570] [drm:drm_mode_setcrtc] [CRTC:5] [ 299.513573] [drm:drm_mode_setcrtc] [CONNECTOR:13:VGA-1] [ 299.513574] [drm:intel_crtc_set_config] [CRTC:5] [FB:37] #connectors=1 (x y) (0 0) [ 299.513575] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set [ 299.513577] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:5], mode_changed=1, fb_changed=0 [ 299.513578] [drm:intel_modeset_stage_output_state] encoder changed, full mode switch [ 299.513579] [drm:intel_modeset_stage_output_state] [CONNECTOR:13:VGA-1] to [CRTC:5] [ 299.513580] [drm:intel_modeset_stage_output_state] crtc changed, full mode switch [ 299.513581] [drm:intel_modeset_stage_output_state] crtc enabled, full mode switch [ 299.513582] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0 [ 299.513584] [drm:connected_sink_compute_bpp] [CONNECTOR:13:VGA-1] checking for sink bpp constrains [ 299.513585] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 1 [ 299.513587] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0 [ 299.513588] [drm:intel_dump_pipe_config] [CRTC:5][modeset] config for pipe A [ 299.513588] [drm:intel_dump_pipe_config] cpu_transcoder: A [ 299.513589] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0 [ 299.513591] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 1, gmch_m: 3029219, gmch_n: 4194304, link_m: 126217, link_n: 524288, tu: 64 [ 299.513592] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 [ 299.513593] [drm:intel_dump_pipe_config] requested mode: [ 299.513595] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x48 0xa [ 299.513596] [drm:intel_dump_pipe_config] adjusted mode: [ 299.513598] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x48 0xa [ 299.513600] [drm:intel_dump_crtc_timings] crtc timings: 65000 1024 1048 1184 1344 768 771 777 806, type: 0x48 flags: 0xa [ 299.513601] [drm:intel_dump_pipe_config] port clock: 65000 [ 299.513602] [drm:intel_dump_pipe_config] pipe src size: 1024x768 [ 299.513603] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 [ 299.513604] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [ 299.513605] [drm:intel_dump_pipe_config] ips: 0 [ 299.513606] [drm:intel_dump_pipe_config] double wide: 0 [ 299.513613] [drm:ivb_modeset_global_resources] disabling fdi C rx [ 299.513625] [drm:intel_get_shared_dpll] CRTC:5 allocated PCH DPLL A [ 299.513626] [drm:intel_get_shared_dpll] using PCH DPLL A for pipe A [ 299.513627] [drm:intel_prepare_shared_dpll] setting up PCH DPLL A [ 299.513637] [drm:ironlake_update_primary_plane] Writing base 004A2000 00000000 0 0 4096 [ 299.514335] [drm:ivb_manual_fdi_link_train] FDI_RX_IIR before link train 0x0 [ 299.514344] [drm:ivb_manual_fdi_link_train] FDI_RX_IIR 0x100 [ 299.514346] [drm:ivb_manual_fdi_link_train] FDI train 1 done, level 0. [ 299.514354] [drm:ivb_manual_fdi_link_train] FDI_RX_IIR 0x600 [ 299.514356] [drm:ivb_manual_fdi_link_train] FDI train 2 done, level 0. [ 299.514357] [drm:ivb_manual_fdi_link_train] FDI train done. [ 299.514360] [drm:intel_enable_shared_dpll] enable PCH DPLL A (active 0, on? 0)for crtc 5 [ 299.514361] [drm:intel_enable_shared_dpll] enabling PCH DPLL A [ 299.516242] [drm:intel_update_fbc] disabled per chip default [ 299.516247] [drm:intel_connector_check_state] [CONNECTOR:13:VGA-1] [ 299.516253] [drm:check_encoder_state] [ENCODER:14:DAC-14] [ 299.516256] [drm:check_encoder_state] [ENCODER:15:TMDS-15] [ 299.516258] [drm:check_encoder_state] [ENCODER:19:TMDS-19] [ 299.516261] [drm:check_encoder_state] [ENCODER:21:TMDS-21] [ 299.516263] [drm:check_encoder_state] [ENCODER:23:TMDS-23] [ 299.516266] [drm:check_crtc_state] [CRTC:5] [ 299.516278] [drm:check_crtc_state] [CRTC:8] [ 299.516279] [drm:check_crtc_state] [CRTC:11] [ 299.516279] [drm:check_shared_dpll_state] PCH DPLL A [ 299.516284] [drm:check_shared_dpll_state] PCH DPLL B [ 299.516569] [drm:intel_crtc_cursor_set] cursor off [ 299.516570] [drm:intel_crtc_set_config] [CRTC:5] [FB:35] #connectors=1 (x y) (0 0) [ 299.516572] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:5], mode_changed=0, fb_changed=1 [ 299.516573] [drm:intel_modeset_stage_output_state] [CONNECTOR:13:VGA-1] to [CRTC:5] [ 299.516576] [drm:ironlake_update_primary_plane] Writing base 0019F000 00000000 0 0 4096 [ 299.534094] [drm:intel_crtc_cursor_set] cursor off [ 299.534096] [drm:intel_crtc_set_config] [CRTC:8] [NOFB] [ 299.534098] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=0 [ 299.534101] [drm:intel_modeset_stage_output_state] [CONNECTOR:13:VGA-1] to [CRTC:5] [ 299.534102] [drm:intel_crtc_cursor_set] cursor off [ 299.534103] [drm:intel_crtc_set_config] [CRTC:11] [NOFB] [ 299.534105] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:11], mode_changed=0, fb_changed=0 [ 299.534106] [drm:intel_modeset_stage_output_state] [CONNECTOR:13:VGA-1] to [CRTC:5] [ 299.537978] [drm:intel_crtc_cursor_set] cursor off [ 299.537981] [drm:intel_crtc_set_config] [CRTC:5] [FB:35] #connectors=1 (x y) (0 0) [ 299.537984] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:5], mode_changed=0, fb_changed=0 [ 299.537985] [drm:intel_modeset_stage_output_state] [CONNECTOR:13:VGA-1] to [CRTC:5] [ 299.537987] [drm:intel_crtc_cursor_set] cursor off [ 299.537988] [drm:intel_crtc_set_config] [CRTC:8] [NOFB] [ 299.537989] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:8], mode_changed=0, fb_changed=0 [ 299.537990] [drm:intel_modeset_stage_output_state] [CONNECTOR:13:VGA-1] to [CRTC:5] [ 299.537992] [drm:intel_crtc_cursor_set] cursor off [ 299.537992] [drm:intel_crtc_set_config] [CRTC:11] [NOFB] [ 299.537994] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:11], mode_changed=0, fb_changed=0 [ 299.537995] [drm:intel_modeset_stage_output_state] [CONNECTOR:13:VGA-1] to [CRTC:5]