diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp b/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp index 33fa606..a2e008b 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp +++ b/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp @@ -31,7 +31,7 @@ brw_blorp_eu_emitter::brw_blorp_eu_emitter(struct brw_context *brw, generator(brw, mem_ctx, rzalloc(mem_ctx, struct brw_wm_prog_key), rzalloc(mem_ctx, struct brw_wm_prog_data), - NULL, NULL, false, debug_flag) + NULL, NULL, false, false, debug_flag) { } diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index 5605db3..08db394 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp @@ -3167,7 +3167,7 @@ brw_wm_fs_emit(struct brw_context *brw, final_assembly_size); } else { fs_generator g(brw, mem_ctx, key, prog_data, prog, fp, v.do_dual_src, - INTEL_DEBUG & DEBUG_WM); + v.runtime_check_aads_emit, INTEL_DEBUG & DEBUG_WM); assembly = g.generate_assembly(&v.instructions, simd16_instructions, final_assembly_size); } diff --git a/src/mesa/drivers/dri/i965/brw_fs.h b/src/mesa/drivers/dri/i965/brw_fs.h index 60a4906..f4eb9b0 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.h +++ b/src/mesa/drivers/dri/i965/brw_fs.h @@ -597,6 +597,7 @@ public: struct gl_shader_program *prog, struct gl_fragment_program *fp, bool dual_source_output, + bool runtime_check_aads_emit, bool debug_flag); ~fs_generator(); @@ -607,6 +608,10 @@ public: private: void generate_code(exec_list *instructions, struct annotation_info *annotation); + void fire_fb_write(fs_inst *inst, + GLuint base_reg, + struct brw_reg implied_header, + GLuint nr); void generate_fb_write(fs_inst *inst); void generate_blorp_fb_write(fs_inst *inst); void generate_pixel_xy(struct brw_reg dst, bool is_x); @@ -707,6 +712,7 @@ private: exec_list discard_halt_patches; bool dual_source_output; + bool runtime_check_aads_emit; const bool debug_flag; void *mem_ctx; }; diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp index 6ba8bb9..2379754 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp @@ -43,10 +43,12 @@ fs_generator::fs_generator(struct brw_context *brw, struct gl_shader_program *prog, struct gl_fragment_program *fp, bool dual_source_output, + bool runtime_check_aads_emit, bool debug_flag) : brw(brw), key(key), prog_data(prog_data), prog(prog), fp(fp), - dual_source_output(dual_source_output), debug_flag(debug_flag), + dual_source_output(dual_source_output), + runtime_check_aads_emit(runtime_check_aads_emit), debug_flag(debug_flag), mem_ctx(mem_ctx) { ctx = &brw->ctx; @@ -96,11 +98,47 @@ fs_generator::patch_discard_jumps_to_fb_writes() } void +fs_generator::fire_fb_write(fs_inst *inst, + GLuint base_reg, + struct brw_reg implied_header, + GLuint nr) +{ + uint32_t msg_control; + + if (brw->gen < 6) { + brw_MOV(p, + brw_message_reg(base_reg + 1), + brw_vec8_grf(1, 0)); + } + + if (this->dual_source_output) + msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01; + else if (dispatch_width == 16) + msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE; + else + msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01; + + uint32_t surf_index = + prog_data->binding_table.render_target_start + inst->target; + + brw_fb_WRITE(p, + dispatch_width, + base_reg, + implied_header, + msg_control, + surf_index, + nr, + 0, + inst->eot, + inst->header_present); + + brw_mark_surface_used(&prog_data->base, surf_index); +} + +void fs_generator::generate_fb_write(fs_inst *inst) { - bool eot = inst->eot; struct brw_reg implied_header; - uint32_t msg_control; /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied * move, here's g1. @@ -153,38 +191,40 @@ fs_generator::generate_fb_write(fs_inst *inst) implied_header = brw_null_reg(); } else { implied_header = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW); - - brw_MOV(p, - brw_message_reg(inst->base_mrf + 1), - brw_vec8_grf(1, 0)); } } else { implied_header = brw_null_reg(); } - if (this->dual_source_output) - msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01; - else if (dispatch_width == 16) - msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE; - else - msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01; - + if (!runtime_check_aads_emit) { + fire_fb_write(inst, inst->base_mrf, implied_header, inst->mlen); + } else { + struct brw_reg v1_null_ud = vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD)); + struct brw_reg tmp_reg_ud = brw_vec1_grf(BRW_MAX_GRF-1, 0); + brw_set_compression_control(p, BRW_COMPRESSION_NONE); + brw_AND(p, + tmp_reg_ud, + get_element_ud(brw_vec8_grf(1,0), 6), + brw_imm_ud(1<<26)); + brw_CMP(p, + v1_null_ud, + BRW_CONDITIONAL_Z, + tmp_reg_ud, + brw_imm_ud(0)); + brw_IF(p, BRW_EXECUTE_1); + { + /* Shift message header one register since we are not sending + * AA data stored in inst->base_mrf+2 + */ + fire_fb_write(inst, inst->base_mrf+1, implied_header, inst->mlen-1); + } + brw_ELSE(p); + { + fire_fb_write(inst, inst->base_mrf, implied_header, inst->mlen); + } + brw_ENDIF(p); + } brw_pop_insn_state(p); - - uint32_t surf_index = - prog_data->binding_table.render_target_start + inst->target; - brw_fb_WRITE(p, - dispatch_width, - inst->base_mrf, - implied_header, - msg_control, - surf_index, - inst->mlen, - 0, - eot, - inst->header_present); - - brw_mark_surface_used(&prog_data->base, surf_index); } void