Bug 101664

Summary: [IGT][BDW] kms_universal_plane@universal-plane-pipe-a-functional dmesg-warn due to assert
Product: DRI Reporter: Marta Löfstedt <marta.lofstedt>
Component: DRM/IntelAssignee: Maarten Lankhorst <bugs>
Status: CLOSED FIXED QA Contact: Intel GFX Bugs mailing list <intel-gfx-bugs>
Severity: normal    
Priority: medium CC: bugs, intel-gfx-bugs
Version: DRI git   
Hardware: Other   
OS: All   
Whiteboard: ReadyForDev
i915 platform: BDW i915 features: display/Other
Attachments:
Description Flags
Only enable IPS if primary plane is enabled.
none
Only enable IPS if primary plane is enabled, v2. none

Description Marta Löfstedt 2017-06-30 13:10:46 UTC 
kms_universal_plane --run-subtest universal-plane-pipe-A-functional

BDW NUCi5 

I suspect that thsi issue has been around for a long time, but last seen on drm-tip:
"commit 1da9a6d8d2402de8798b36d75bdd7d8b49728a5e
Author: Rodrigo Vivi <rodrigo.vivi@intel.com>
Date:   Thu Jun 29 13:17:09 2017 -0700

    drm-tip: 2017y-06m-29d-20h-16m-45s UTC integration manifest"

dmesg-warn due to the following assert:

[ 2888.641550] plane A assertion failure (expected on, current off)
[ 2888.641596] ------------[ cut here ]------------
[ 2888.641682] WARNING: CPU: 3 PID: 4356 at drivers/gpu/drm/i915/intel_display.c:1225 assert_plane+0xb5/0xc0 [i915]
[ 2888.641683] Modules linked in: rfcomm bnep arc4 iwlmvm mac80211 binfmt_misc nls_iso8859_1 intel_rapl x86_pkg_temp_thermal intel_powerclamp iwlwifi coretemp crct10dif_pclmul crc32_pclmul ghash_clmulni_intel pcbc aesni_intel aes_x86_64 crypto_simd cryptd glue_helper intel_cstate cfg80211 intel_rapl_perf snd_hda_codec_realtek snd_hda_codec_generic snd_hda_codec_hdmi snd_hda_intel snd_hda_codec snd_soc_ssm4567 btusb snd_soc_rt5640 snd_hwdep btrtl shpchp btbcm snd_soc_rl6231 lpc_ich btintel ir_rc6_decoder input_leds snd_soc_core snd_hda_core bluetooth snd_compress snd_pcm rc_rc6_mce snd_seq ir_lirc_codec mei_me ecdh_generic lirc_dev mei snd_timer nuvoton_cir snd_seq_device rc_core acpi_als snd elan_i2c dw_dmac kfifo_buf snd_soc_sst_acpi dw_dmac_core 8250_dw snd_soc_sst_match soundcore mac_hid industrialio
[ 2888.641755]  spi_pxa2xx_platform acpi_pad parport_pc ppdev lp parport ip_tables x_tables autofs4 i915 hid_generic usbhid i2c_algo_bit drm_kms_helper syscopyarea sysfillrect sysimgblt fb_sys_fops drm e1000e ptp ahci libahci pps_core sdhci_acpi video sdhci i2c_hid hid
[ 2888.641789] CPU: 3 PID: 4356 Comm: kms_universal_p Tainted: G        W       4.12.0-rc7-next-20170630 #2
[ 2888.641791] Hardware name:                  /NUC5i5RYB, BIOS RYBDWi35.86A.0249.2015.0529.1640 05/29/2015
[ 2888.641794] task: ffff90c00a46dc00 task.stack: ffff9f83c1c54000
[ 2888.641868] RIP: 0010:assert_plane+0xb5/0xc0 [i915]
[ 2888.641870] RSP: 0018:ffff9f83c1c57b18 EFLAGS: 00010286
[ 2888.641874] RAX: 0000000000000034 RBX: 0000000000000000 RCX: 0000000000000000
[ 2888.641876] RDX: 0000000000000000 RSI: ffff90c01ed8dc78 RDI: ffff90c01ed8dc78
[ 2888.641878] RBP: ffff9f83c1c57b28 R08: 0000000000000001 R09: 0000000000000aac
[ 2888.641880] R10: ffff90c013f9b600 R11: 0000000000000aac R12: 0000000000000001
[ 2888.641881] R13: 0000000000000000 R14: 0000000000000000 R15: ffff9f83c1c57bb0
[ 2888.641885] FS:  00007f02c23d2a40(0000) GS:ffff90c01ed80000(0000) knlGS:0000000000000000
[ 2888.641887] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[ 2888.641889] CR2: 00007f434db88000 CR3: 000000020b92c000 CR4: 00000000003406e0
[ 2888.641892] Call Trace:
[ 2888.641968]  hsw_disable_ips+0x38/0x100 [i915]
[ 2888.642031]  intel_crtc_set_crc_source+0x197/0x220 [i915]
[ 2888.642060]  crtc_crc_open+0x54/0x1f0 [drm]
[ 2888.642067]  ? _cond_resched+0x1a/0x50
[ 2888.642073]  ? kmem_cache_alloc_trace+0x181/0x190
[ 2888.642080]  full_proxy_open+0xff/0x1c0
[ 2888.642085]  do_dentry_open+0x1fc/0x300
[ 2888.642090]  ? full_proxy_release+0x90/0x90
[ 2888.642095]  vfs_open+0x4e/0x80
[ 2888.642100]  path_openat+0x614/0x14b0
[ 2888.642106]  ? copy_termios+0x71/0x80
[ 2888.642110]  ? _copy_to_user+0x2a/0x40
[ 2888.642116]  ? __check_object_size+0xb3/0x190
[ 2888.642119]  ? _copy_from_user+0x36/0x70
[ 2888.642124]  do_filp_open+0x99/0x110
[ 2888.642129]  ? __check_object_size+0xb3/0x190
[ 2888.642135]  ? __alloc_fd+0x46/0x170
[ 2888.642140]  do_sys_open+0x130/0x220
[ 2888.642145]  ? do_sys_open+0x130/0x220
[ 2888.642151]  SyS_openat+0x14/0x20
[ 2888.642155]  entry_SYSCALL_64_fastpath+0x1e/0xa9
[ 2888.642158] RIP: 0033:0x7f02c08e075a
[ 2888.642160] RSP: 002b:00007ffc253d5060 EFLAGS: 00000246 ORIG_RAX: 0000000000000101
[ 2888.642164] RAX: ffffffffffffffda RBX: 000000094d3612c0 RCX: 00007f02c08e075a
[ 2888.642166] RDX: 0000000000000000 RSI: 00007ffc253d5120 RDI: 0000000000000005
[ 2888.642167] RBP: 00007f02c0ba6400 R08: 0000000000000000 R09: 000000000000000f
[ 2888.642169] R10: 0000000000000000 R11: 0000000000000246 R12: 0000000000000000
[ 2888.642171] R13: 00000000000001e0 R14: 00007ffc253d5b28 R15: 000000094d35d9c0
[ 2888.642174] Code: c6 7b b6 5f c0 85 c0 48 c7 c2 7e b6 5f c0 48 89 f1 48 c7 c7 70 dd 60 c0 48 0f 49 ca 45 84 e4 48 0f 45 d6 8d 73 41 e8 5c 08 5b d0 <0f> ff eb 89 0f 1f 80 00 00 00 00 0f 1f 44 00 00 55 48 89 e5 41 
[ 2888.642247] ---[ end trace c7632b8a39606034 ]---

Above assert in then followed by similar assert, but with hsw_enable_ips instead of hsw_disable_ips.

The issue happens in the "functional_test_pipe" part of the tests. The asserts are fired during: igt_pipe_crc_collect_crc(...)
During the following steps of the test:
"Step 5: Universal API's, disable primary plane (CRC 5)"
"Step 14: Universal API, set primary completely offscreen (CRC 9)"
"Step 15: Explicitly disable primary after it's already been implicitly disabled (CRC 10)."                                                                                          

Note that the identical test for pipe-B and pipe-C that also pass, but with out firing the assert and that it only appears for BDW out of many other tested HW in Intel Espoo lab.
Comment 1 Maarten Lankhorst 2017-08-09 16:36:46 UTC 
Created attachment 133408 [details] [review]
Only enable IPS if primary plane is enabled.

Does this patch fix it?
Comment 2 Marta Löfstedt 2017-08-10 06:14:06 UTC 
(In reply to Maarten Lankhorst from comment #1)
> Created attachment 133408 [details] [review] [review]
> Only enable IPS if primary plane is enabled.
> 
> Does this patch fix it?

Yes, indeed!
Comment 3 Maarten Lankhorst 2017-08-10 09:27:54 UTC 
Created attachment 133422 [details] [review]
Only enable IPS if primary plane is enabled, v2.

v2, more thorough version. Could you test this too and then I'll send it to the list. :)
Comment 4 Marta Löfstedt 2017-08-10 11:49:01 UTC 
(In reply to Maarten Lankhorst from comment #3)
> Created attachment 133422 [details] [review] [review]
> Only enable IPS if primary plane is enabled, v2.
> 
> v2, more thorough version. Could you test this too and then I'll send it to
> the list. :)

Yes, that works good too.
Comment 5 Marta Löfstedt 2017-08-15 07:22:34 UTC 
https://patchwork.freedesktop.org/patch/171211/
Comment 6 Maarten Lankhorst 2017-08-16 09:36:23 UTC 
Seems ville has a version too..

https://patchwork.kernel.org/patch/9482787/

Might be useful to have that with a rename of ips_force_disable to collecting_crc or something..
Comment 7 Marta Löfstedt 2017-08-17 07:38:30 UTC 
Tested OK with Villes patch:
https://patchwork.freedesktop.org/patch/172077/
Comment 8 Marta Löfstedt 2017-08-28 07:10:04 UTC 
Villes patch is merged. However, the issue persist.
Comment 9 Marta Löfstedt 2017-08-28 11:30:19 UTC 
The patch that was merged is not the same as I tested OK with.
I sent up a patch that fix this:

https://patchwork.freedesktop.org/patch/173896/
Comment 10 Marta Löfstedt 2017-08-29 06:14:10 UTC 
Fixed by:
Author: Marta Lofstedt <marta.lofstedt@intel.com>
Date:   Mon Aug 28 15:18:10 2017 +0300

    drm/i915: Beef up of Beef up the IPS vs. CRC workaround
    
    Commit 6e644626945c ("drm/i915: Beef up the IPS vs. CRC
    workaround") was supposed to solve below bug. However, the
    patch I tested is not the same as the one that got merged.
    With this addition the test pass.

Use of freedesktop.org services, including Bugzilla, is subject to our Code of Conduct. How we collect and use information is described in our Privacy Policy.