Bug 18893 - 23.97/24.00hz modeline is actually played at 23.93hz/24.04hz
Summary: 23.97/24.00hz modeline is actually played at 23.93hz/24.04hz
Status: RESOLVED FIXED
Alias: None
Product: xorg
Classification: Unclassified
Component: Driver/intel (show other bugs)
Version: unspecified
Hardware: Other All
: medium enhancement
Assignee: MaLing
QA Contact: Xorg Project Team
URL:
Whiteboard:
Keywords:
Depends on:
Blocks:
 
Reported: 2008-12-04 15:46 UTC by elupus
Modified: 2008-12-17 02:59 UTC (History)
1 user (show)

See Also:
i915 platform:
i915 features:


Attachments
Hi, This patch I have test it will treate 23.97/24 as 24HZ, it will meet your requirment. please try it Thanks Ma Ling (558 bytes, patch)
2008-12-14 18:47 UTC, MaLing
no flags Details | Splinter Review

Description elupus 2008-12-04 15:46:03 UTC
Hi, 

I'm using an Intel GM965 graphic card in a AOpen MP965-DR for video playback on a HDMI display.

I've setup a few specific EIA/CEA-861B modelines to get some good modes on my hdtv.

Two example of these are..
# 1920x1080p @ 23.976Hz (EIA/CEA-861B)
ModeLine "1920x1080" 74.176 1920 2558 2602 2750 1080 1084 1089 1125 +hsync +vsync
# 1920x1080p @ 24.000Hz (EIA/CEA-861B)
ModeLine "1920x1080" 74.250 1920 2558 2602 2750 1080 1084 1089 1125 +hsync +vsync


Which are two 24fps modes, one being exactly 24hz and the other very close to 24*1000/1001 which is a proper mode for alot of video sources.

While using these I've found that the refresh rate isn't actually matching the modelines very accuratly. the 23.976 mode is actually 23.93Hz and the 24.000 mode is more like 24.04Hz. 

This causes quite alot of stutter during playback of sources with that speed. 

After looking through the docs and source, i've concluded that the calculation of the pixelclock is probably not accurate enough.

Ripping the specific calculation out of i830_display.c, the pixelclock for the above two modes seem to both end up on 74.240Mhz which seem abit odd since they play at different rates. 

Looking through the docs i've found that the "DPLL A HDMI Divider: Hi-Res" isn't currently being used. A quick test in my sample program showed that adding the divider and multiplier to the exahaustive pll search, both frequencies are possible to achieve spot on. 

I've not tried to implement this in the driver itself. Partly since i find it horribly hard to debug them and get through the maze of xorg dependencies. Also i'm not sure they are applicable due to only being valid for "HDMI (fixed frequency mode)"

The rate error also seem to be visible for other modes 60 and 59.9.., but since there are generally no movies playing at those rates, it's not as visible. 

I know this is a low prio request, but if the intel gfx are to be usable for mediacenters, this is one feature that is quite nice to have.
Comment 1 elupus 2008-12-05 16:50:51 UTC
I think I've atleast tracked down how it get's those framerates. If there is multiplier of 4 used. (adjusted_mode->Clock is mode->Clock / 4). I get the pixel clocks of 74.056 vs 74.400 which makes the framerate match my spotted 23.93 and 24.04.. So atleast it seem to make sence.

However while looking at this I also spotted something odd. This comment can be found in the file...

/*
 * These values are taken from the broadwater/crestline PLL spreadsheet.
 * All of the defines here are for the programmed register value, not
 * the 'counter' value (e.g. Ncounter = Nregister + 2)
 */

However only the I9XX_N_MIN/MAX values have been corrected. The M1/M2 values (where the value is also 2 larger than the register value), have not. Thus the ranges setup are wrong. Since both m1/m2 and n value are used like this:

  fp = clock.n << 16 | clock.m1 << 8 | clock.m2;

The defines should be this instead.

  #define I9XX_M1_MIN              8
  #define I9XX_M1_MAX             18
  #define I9XX_M2_MIN              3
  #define I9XX_M2_MAX              7

Potentially the 18 should be 20, after the bump made in the same commit as the above comment was added, but that wouldn't match the docs.


Comment 2 Eric Anholt 2008-12-08 20:02:31 UTC
I haven't spent the time to analyze the m/n issue you reported, but by my reading the SDVO/HDMI multiplier/divider is not supposed to be the thing to be using for getting a more accurate clock.  It's about keeping the clock rate over the bus between.  The note about setting the divider to non-1 is for integrated hdmi, not sdvo (which is what you're using on a gm965).
Comment 3 Eric Anholt 2008-12-08 20:03:17 UTC
sorry, "between 1-2 ghz" that was supposed to be.
Comment 4 MaLing 2008-12-14 18:47:02 UTC
Created attachment 21142 [details] [review]
 Hi, This patch I have test it will treate 23.97/24 as 24HZ, it will meet your requirment. please try it Thanks Ma Ling
Comment 5 elupus 2008-12-15 09:47:06 UTC
Well that patch still doesn't match documentation, it only reverts back to how it was before the N values was changed.

Valid change would be like mentioned before:
  #define I9XX_M1_MIN              8
  #define I9XX_M1_MAX             18
  #define I9XX_M2_MIN              3
  #define I9XX_M2_MAX              7
But that does not solve my issue anyway.


As Eric Anholt said that the multipliers/dividers are only for making sure the SDVO busrate is withing specification, I'm not even sure this issue can be solved at all.

It would however be very nice if the driver actually output what pixelrate it has configured to log, so that one can adjust modlines in other ways to achieve the wanted refreshrate. 

I've not read the specifications myself, so i'm not sure if the modelines above are just one way of achieving the specifications, or if it's the only way.

If it's the "only" way, It's abit weird that the intel hardware can't match the EIA/CEA-861B specifications.


Ps.
I've been able to solve my own issue, by mimicing the exhaustive search of freqencies in my own program and then modifying the modelines backporch (and frequency) to achieve the wanted refresh-rate. But I suspect I'm lucky that I have a very forgiving TV. I can post the modelines here if anybody is interested.


Comment 6 MaLing 2008-12-15 18:22:24 UTC
(In reply to comment #5)
> Well that patch still doesn't match documentation, it only reverts back to how
> it was before the N values was changed.
> Valid change would be like mentioned before:
>   #define I9XX_M1_MIN              8
>   #define I9XX_M1_MAX             18
>   #define I9XX_M2_MIN              3
>   #define I9XX_M2_MAX              7
> But that does not solve my issue anyway.
hi,
thanks for your reply !
/*
 * These values are taken from the broadwater/crestline PLL spreadsheet.
 * All of the defines here are for the programmed register value, not
 * the 'counter' value (e.g. Ncounter = Nregister + 2)
 */
and formula is dot clock = reflck *(5 * (m1 + 2) + (m2 + 2))/(n +2)/p1/p2
the I9XX_M1/M2_MIN/MAX store the resgister limit value, based on spec they should be as follow
#define I9XX_M1_MIN		    10
#define I9XX_M1_MAX		    20
#define I9XX_M2_MIN		    5 
#define I9XX_M2_MAX		    9 

yes there is a pity that we can not provide exact vertical frash rate for all modeline, may be it can be improved later.
thanks for your solution, could you post your modeline, it is very helpful for us!

best regards
Ma Ling

Comment 7 elupus 2008-12-16 09:21:33 UTC
The spec says what you mention, but what it fails to mention is that the formula above is based on the register values not the counter values. And that is the same formula the code uses to calculate the rate during the exhaustive search. 

The N value was already corrected for this inconsistency, but the M values should be corrected too i think. 

# 1920x1080p @ 59.94Hz (EIA/CEA-861B)
#	ModeLine "1920x1080" 148.352 1920 2008 2052 2200 1080 1084 1089 1125 +hsync +vsync
	ModeLine "1920x1080" 148.800 1920 2008 2052 2193 1080 1084 1089 1132 +hsync +vsync #INTEL

# 1920x1080p @ 60Hz (EIA/CEA-861B)
#	ModeLine "1920x1080" 148.500 1920 2008 2052 2200 1080 1084 1089 1125 +hsync +vsync
	ModeLine "1920x1080" 148.800 1920 2008 2052 2185 1080 1084 1089 1135 +hsync +vsync #INTEL

# 1920x1080p @ 50Hz (EIA/CEA-861B) 
#	ModeLine "1920x1080" 148.500 1920 2448 2492 2640 1080 1084 1089 1125 +hsync +vsync
	ModeLine "1920x1080" 148.800 1920 2448 2492 2622 1080 1084 1089 1135 +hsync +vsync #INTEL

# 1920x1080p @ 23.976Hz (EIA/CEA-861B)
#	ModeLine "1920x1080" 74.175 1920 2558 2602 2750 1080 1084 1089 1125 +hsync +vsync
	ModeLine "1920x1080" 74.057 1920 2558 2602 2719 1080 1084 1089 1136 +hsync +vsync #INTEL

# 1920x1080p @ 24Hz (EIA/CEA-861B)
#	ModeLine "1920x1080" 74.250 1920 2558 2602 2750 1080 1084 1089 1125 +hsync +vsync
	ModeLine "1920x1080" 74.400 1920 2558 2602 2758 1080 1084 1089 1124 +hsync +vsync #INTEL

# 1920x1080p @ 25Hz (EIA/CEA-861B)
#	ModeLine "1920x1080" 74.250 1920 2448 2492 2640 1080 1084 1089 1125 +hsync +vsync
	ModeLine "1920x1080" 74.400 1920 2448 2492 2622 1080 1084 1089 1135 +hsync +vsync #INTEL

# 1920x1080p @ 29.97Hz (EIA/CEA-861B)
#	ModeLine "1920x1080" 74.175 1920 2008 2052 2200 1080 1084 1089 1125 +hsync +vsync
	ModeLine "1920x1080" 74.400 1920 2008 2052 2193 1080 1084 1089 1132 +hsync +vsync #INTEL

# 1920x1080p @ 30Hz (EIA/CEA-861B)
#	ModeLine "1920x1080" 74.250 1920 2008 2052 2200 1080 1084 1089 1125 +hsync +vsync
	ModeLine "1920x1080" 74.400 1920 2008 2052 2185 1080 1084 1089 1135 +hsync +vsync #INTEL

# 1920x1080i @ 59.94Hz (EIA/CEA-861B)
#	Modeline "1920x1080" 74.175 1920 2008 2052 2200 1080 1085 1095 1125 +hsync +vsync Interlace
#	ModeLine "1920x1080" 74.400 1920 2008 2052 2193 1080 1084 1089 1132 +hsync +vsync Interlace #INTEL

# 1920x1080i @ 60Hz (EIA/CEA-861B)
#	Modeline "1920x1080" 74.250 1920 2008 2052 2200 1080 1085 1095 1125 +hsync +vsync Interlace
#	ModeLine "1920x1080" 74.400 1920 2008 2052 2185 1080 1084 1089 1135 +hsync +vsync Interlace #INTEL

# 1920x1080i @ 50Hz (EIA/CEA-861B)
#	Modeline "1920x1080" 74.250 1920 2448 2492 2640 1080 1085 1095 1125 +hsync +vsync Interlace
#	ModeLine "1920x1080" 74.400 1920 2448 2492 2622 1080 1084 1089 1135 +hsync +vsync Interlace #INTEL

# 1280x720p @ 59.94Hz (EIA/CEA-861B)
#	ModeLine "1280x720" 74.175 1280 1390 1430 1650 720 725 730 750 +hsync +vsync
	ModeLine "1280x720" 74.400 1280 1390 1430 1612 720 725 730 770 +hsync +vsync #INTEL
# 1280x720p @ 60Hz (EIA/CEA-861B)
#	ModeLine "1280x720" 74.250 1280 1390 1430 1650 720 725 730 750 +hsync +vsync
	ModeLine "1280x720" 74.400 1280 1390 1420 1623 720 725 730 764 +hsync +vsync #INTEL

# 1280x720p @ 50Hz (EIA/CEA-861B)
#	ModeLine "1280x720" 74.250 1280 1720 1760 1980 720 725 730 750 +hsync +vsync
	ModeLine "1280x720" 74.400 1280 1720 1760 1984 720 725 730 750 +hsync +vsync #INTEL
Comment 8 MaLing 2008-12-17 02:59:56 UTC
(In reply to comment #7)
Thanks for your modeline,

because our hardware limit , we can not provide 100% exact rate, so I close issue.
thanks
Ma Ling


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