15472 – [945GM] "ESR is 0x00000001, instruction error" after run some GL program using indirect rendering

Bug 15472 - [945GM] "ESR is 0x00000001, instruction error" after run some GL program using indirect rendering

Summary: [945GM] "ESR is 0x00000001, instruction error" after run some GL program usin...

Status:	RESOLVED WONTFIX

Alias:	None

Product:	Mesa
Classification:	Unclassified
Component:	Drivers/DRI/i915 (show other bugs)
Version:	git
Hardware:	x86 (IA32) Linux (All)

Importance:	medium normal
Assignee:	Default DRI bug account
QA Contact:

URL:
Whiteboard:
Keywords:

Depends on:
Blocks:

Reported:	2008-04-12 14:18 UTC by Jie Luo
Modified:	2009-08-24 12:29 UTC (History)
CC List:	0 users

See Also:
i915 platform:
i915 features:

Attachments
Xorg.0.log (20.98 KB, text/plain) 2008-04-12 14:18 UTC, Jie Luo	Details
dmesg (45.03 KB, text/plain) 2008-04-12 14:40 UTC, Jie Luo	Details
View All

Description Jie Luo 2008-04-12 14:18:31 UTC

Created attachment 15852 [details]
Xorg.0.log

Bug description:

After run LIBGL_ALWAYS_INDIRECT=1 glxgears for some times or start compiz, then restart xserver, this warning will show up in my Xorg.log. Currently it didn't cause any visible problem. But this maybe indicate there is a bug in side xf86-intel-driver/mesa/dri/xserver, so I did this report.

System environment:
-- chipset: 

00:02.0 VGA compatible controller: Intel Corporation Mobile 945GM/GMS, 943/940GML Express Integrated Graphics Controller (rev 03)
00:02.1 Display controller: Intel Corporation Mobile 945GM/GMS, 943/940GML Express Integrated Graphics Controller (rev 03)

-- system architecture: 

uname -m 
i686

-- xf86-video-intel: git 55338268bbdbb8c4fbb030adb803e258764e6860
-- xserver: git eabcfce0a68d504d11be9479f09e66f574dd2f21
-- mesa: git 51ad219d6fbcdaa50e2f1b5854dfbbc4b8cab8fc
-- drm: inside kernel 2.6.24
-- kernel: 2.4.24
-- Linux distribution: Gentoo
-- Machine or mobo model: ThinkPad X60

Reproduce steps:

1. startx
2. run LIBGL_ALWAYS_INDIRECT=1 glxgears
3. restartx

This is not 100% hit the bug.

1. startx
2. run LIBGL_ALWAYS_INDIRECT=1 compiz --replace --indirect-rendering --sm-disable ccp
3. restartx

This reproduce every time.

Comment 1 Jie Luo 2008-04-12 14:40:42 UTC

Created attachment 15853 [details]
dmesg

Comment 2 Jie Luo 2008-04-14 01:11:01 UTC

After reading the graphic core document from intel video driver site. I did some debug. Here is the result of dump debug register.

This is the regdump of normal state.
IPEIR: 0 IPEHR: 0
EIR: 0 ESR: 0 EMR: 0xffff
INSTDONE: 0xffc0 INSTPM: 0
MEMMODE: 0x306  INSTPS: 0xf0000 
HWSTAM: 0xfffe IER: 0x2 IMR: 0 IIR: 0x20

This is the regdump of the state ESR being set to 0x00000001.
IPEIR: 0 IPEHR: 0
EIR: 0 ESR: 0x1 EMR: 0xffff
INSTDONE: 0xffc0 INSTPM: 0
MEMMODE: 0x306  INSTPS: 0xf0000 
HWSTAM: 0xfffe IER: 0xa2 IMR: 0 IIR: 0x50

According to the document, ESR being set to 0x1 indicate Instruction Error. The document said that IPEHR register contains the header (DWord 0) of the faulting instruction. So the faulting instruction is a MI instruction. IER being set to be 0xa2 means 'Display Plane C Flip Pending' and 'Display Pipe B VBLANK' is enabled. But because I don't have a PIPE C, this means the Instruction Error is caused by a MI_DISPLAY_BUFFER_INFO instruction with a defeatured opcode (PIPE C). Any comments?

Comment 3 Jie Luo 2008-04-20 22:01:18 UTC

(In reply to comment #2)
> After reading the graphic core document from intel video driver site. I did
> some debug. Here is the result of dump debug register.
> 
> This is the regdump of normal state.
> IPEIR: 0 IPEHR: 0
> EIR: 0 ESR: 0 EMR: 0xffff
> INSTDONE: 0xffc0 INSTPM: 0
> MEMMODE: 0x306  INSTPS: 0xf0000 
> HWSTAM: 0xfffe IER: 0x2 IMR: 0 IIR: 0x20
> 
> This is the regdump of the state ESR being set to 0x00000001.
> IPEIR: 0 IPEHR: 0
> EIR: 0 ESR: 0x1 EMR: 0xffff
> INSTDONE: 0xffc0 INSTPM: 0
> MEMMODE: 0x306  INSTPS: 0xf0000 
> HWSTAM: 0xfffe IER: 0xa2 IMR: 0 IIR: 0x50
> 
> According to the document, ESR being set to 0x1 indicate Instruction Error. The
> document said that IPEHR register contains the header (DWord 0) of the faulting
> instruction. So the faulting instruction is a MI instruction. IER being set to
> be 0xa2 means 'Display Plane C Flip Pending' and 'Display Pipe B VBLANK' is
> enabled. But because I don't have a PIPE C, this means the Instruction Error is
> caused by a MI_DISPLAY_BUFFER_INFO instruction with a defeatured opcode (PIPE
> C). Any comments?
> 

It seams that my thought above is not correct. The only thing I'm sure is that glXSwapBuffers() may cause this instruction error. My test is done with glxdemo program. With LIBGL_ALWAYS_INDIRECT=1, glxdemo doesn't cause instruction error without call glXSwapBuffers(), but will cause this error with glXSwapBuffers() after some resizing and moving. I give up to track down this problem, it too complicated for me to do this.

Comment 4 Michael Fu 2008-09-25 02:10:23 UTC

thanks for reporting this. I'll close this bug since no obvious issue found..

Comment 5 Adam Jackson 2009-08-24 12:29:52 UTC

Mass version move, cvs -> git

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