Attachment 104148 Details for Bug 82247 – When the DP screen doesn't light up

When the DP screen doesn't light up

pdisp_bug_complete (text/plain), 351.45 KB, created by Martin Peres on 2014-08-06 12:10:56 UTC

(hide)

Description:

Filename:

MIME Type:

Creator: Martin Peres

Created: 2014-08-06 12:10:56 UTC

Size: 351.45 KB

patch

obsolete

>[aoÃ»t 6 13:57] Initializing cgroup subsys cpuset
>[  +0,000000] Initializing cgroup subsys cpu
>[  +0,000000] Initializing cgroup subsys cpuacct
>[  +0,000000] Linux version 3.16.0-1-ARCH (nobody@var-lib-archbuild-testing-x86_64-tobias) (gcc version 4.9.1 (GCC) ) #1 SMP PREEMPT Mon Aug 4 08:15:33 CEST 2014
>[  +0,000000] Command line: root=/dev/sda4 ro init=/usr/lib/systemd/systemd nouveau.debug="PDISP=trace,I2C=trace,VBIOS=trace"
>[  +0,000000] e820: BIOS-provided physical RAM map:
>[  +0,000000] BIOS-e820: [mem 0x0000000000000000-0x000000000009f7ff] usable
>[  +0,000000] BIOS-e820: [mem 0x000000000009f800-0x000000000009ffff] reserved
>[  +0,000000] BIOS-e820: [mem 0x00000000000e8000-0x00000000000fffff] reserved
>[  +0,000000] BIOS-e820: [mem 0x0000000000100000-0x00000000dbfac43f] usable
>[  +0,000000] BIOS-e820: [mem 0x00000000dbfae440-0x00000000dbfae49f] ACPI NVS
>[  +0,000000] BIOS-e820: [mem 0x00000000dbfae4a0-0x00000000dc7fffff] reserved
>[  +0,000000] BIOS-e820: [mem 0x00000000f4000000-0x00000000f7ffffff] reserved
>[  +0,000000] BIOS-e820: [mem 0x00000000fe000000-0x00000000fed3ffff] reserved
>[  +0,000000] BIOS-e820: [mem 0x00000000fed45000-0x00000000ffffffff] reserved
>[  +0,000000] BIOS-e820: [mem 0x0000000100000000-0x000000021fffffff] usable
>[  +0,000000] NX (Execute Disable) protection: active
>[  +0,000000] SMBIOS 2.6 present.
>[  +0,000000] DMI: Hewlett-Packard HP Compaq 8100 Elite SFF PC/304Ah, BIOS 786H1 v01.05 06/09/2010
>[  +0,000000] e820: update [mem 0x00000000-0x00000fff] usable ==> reserved
>[  +0,000000] e820: remove [mem 0x000a0000-0x000fffff] usable
>[  +0,000000] AGP: No AGP bridge found
>[  +0,000000] e820: last_pfn = 0x220000 max_arch_pfn = 0x400000000
>[  +0,000000] MTRR default type: uncachable
>[  +0,000000] MTRR fixed ranges enabled:
>[  +0,000000]   00000-9FFFF write-back
>[  +0,000000]   A0000-BFFFF uncachable
>[  +0,000000]   C0000-E3FFF write-protect
>[  +0,000000]   E4000-EFFFF write-back
>[  +0,000000]   F0000-FFFFF write-protect
>[  +0,000000] MTRR variable ranges enabled:
>[  +0,000000]   0 base 000000000 mask C00000000 write-back
>[  +0,000000]   1 base 0DC000000 mask FFC000000 uncachable
>[  +0,000000]   2 base 0E0000000 mask FE0000000 uncachable
>[  +0,000000]   3 disabled
>[  +0,000000]   4 disabled
>[  +0,000000]   5 disabled
>[  +0,000000]   6 disabled
>[  +0,000000]   7 disabled
>[  +0,000000] x86 PAT enabled: cpu 0, old 0x7040600070406, new 0x7010600070106
>[  +0,000000] e820: update [mem 0xdc000000-0xffffffff] usable ==> reserved
>[  +0,000000] e820: last_pfn = 0xdbfac max_arch_pfn = 0x400000000
>[  +0,000000] found SMP MP-table at [mem 0x000f9bf0-0x000f9bff] mapped at [ffff8800000f9bf0]
>[  +0,000000] Scanning 1 areas for low memory corruption
>[  +0,000000] Base memory trampoline at [ffff880000099000] 99000 size 24576
>[  +0,000000] init_memory_mapping: [mem 0x00000000-0x000fffff]
>[  +0,000000]  [mem 0x00000000-0x000fffff] page 4k
>[  +0,000000] BRK [0x01b23000, 0x01b23fff] PGTABLE
>[  +0,000000] BRK [0x01b24000, 0x01b24fff] PGTABLE
>[  +0,000000] BRK [0x01b25000, 0x01b25fff] PGTABLE
>[  +0,000000] init_memory_mapping: [mem 0x21fe00000-0x21fffffff]
>[  +0,000000]  [mem 0x21fe00000-0x21fffffff] page 2M
>[  +0,000000] BRK [0x01b26000, 0x01b26fff] PGTABLE
>[  +0,000000] init_memory_mapping: [mem 0x21c000000-0x21fdfffff]
>[  +0,000000]  [mem 0x21c000000-0x21fdfffff] page 2M
>[  +0,000000] init_memory_mapping: [mem 0x200000000-0x21bffffff]
>[  +0,000000]  [mem 0x200000000-0x21bffffff] page 2M
>[  +0,000000] init_memory_mapping: [mem 0x00100000-0xdbfabfff]
>[  +0,000000]  [mem 0x00100000-0x001fffff] page 4k
>[  +0,000000]  [mem 0x00200000-0xdbdfffff] page 2M
>[  +0,000000]  [mem 0xdbe00000-0xdbfabfff] page 4k
>[  +0,000000] init_memory_mapping: [mem 0x100000000-0x1ffffffff]
>[  +0,000000]  [mem 0x100000000-0x1ffffffff] page 2M
>[  +0,000000] BRK [0x01b27000, 0x01b27fff] PGTABLE
>[  +0,000000] BRK [0x01b28000, 0x01b28fff] PGTABLE
>[  +0,000000] RAMDISK: [mem 0x37cd0000-0x37feffff]
>[  +0,000000] ACPI: Early table checksum verification disabled
>[  +0,000000] ACPI: RSDP 0x00000000000E5210 000014 (v00 COMPAQ)
>[  +0,000000] ACPI: RSDT 0x00000000DBFD0540 000044 (v01 HPQOEM SLIC-BPC 20100609      00000000)
>[  +0,000000] ACPI: FACP 0x00000000DBFD05E8 000074 (v01 COMPAQ IBEXPEAK 00000001      00000000)
>[  +0,000000] ACPI BIOS Warning (bug): Optional FADT field Pm2ControlBlock has zero address or length: 0x0000000000000050/0x0 (20140424/tbfadt-649)
>[  +0,000000] ACPI BIOS Warning (bug): Invalid length for FADT/Pm2ControlBlock: 0, using default 8 (20140424/tbfadt-699)
>[  +0,000000] ACPI: DSDT 0x00000000DBFD0A4F 00A4E4 (v01 COMPAQ DSDT_PRJ 00000001 MSFT 0100000E)
>[  +0,000000] ACPI: FACS 0x00000000DBFD0500 000040
>[  +0,000000] ACPI: APIC 0x00000000DBFD065C 0000BC (v01 COMPAQ IBEXPEAK 00000001      00000000)
>[  +0,000000] ACPI: ASF! 0x00000000DBFD0718 000063 (v32 COMPAQ IBEXPEAK 00000001      00000000)
>[  +0,000000] ACPI: MCFG 0x00000000DBFD077B 00003C (v01 COMPAQ IBEXPEAK 00000001      00000000)
>[  +0,000000] ACPI: TCPA 0x00000000DBFD07B7 000032 (v01 COMPAQ IBEXPEAK 00000001      00000000)
>[  +0,000000] ACPI: SLIC 0x00000000DBFD07E9 000176 (v01 HPQOEM SLIC-BPC 00000001      00000000)
>[  +0,000000] ACPI: HPET 0x00000000DBFD095F 000038 (v01 COMPAQ IBEXPEAK 00000001      00000000)
>[  +0,000000] ACPI: DMAR 0x00000000DBFD0997 000068 (v01 COMPAQ IBEXPEAK 00000001      00000000)
>[  +0,000000] ACPI: Local APIC address 0xfee00000
>[  +0,000000] No NUMA configuration found
>[  +0,000000] Faking a node at [mem 0x0000000000000000-0x000000021fffffff]
>[  +0,000000] Initmem setup node 0 [mem 0x00000000-0x21fffffff]
>[  +0,000000]   NODE_DATA [mem 0x21fff5000-0x21fff9fff]
>[  +0,000000]  [ffffea0000000000-ffffea00087fffff] PMD -> [ffff880217600000-ffff88021f5fffff] on node 0
>[  +0,000000] Zone ranges:
>[  +0,000000]   DMA      [mem 0x00001000-0x00ffffff]
>[  +0,000000]   DMA32    [mem 0x01000000-0xffffffff]
>[  +0,000000]   Normal   [mem 0x100000000-0x21fffffff]
>[  +0,000000] Movable zone start for each node
>[  +0,000000] Early memory node ranges
>[  +0,000000]   node   0: [mem 0x00001000-0x0009efff]
>[  +0,000000]   node   0: [mem 0x00100000-0xdbfabfff]
>[  +0,000000]   node   0: [mem 0x100000000-0x21fffffff]
>[  +0,000000] On node 0 totalpages: 2080586
>[  +0,000000]   DMA zone: 64 pages used for memmap
>[  +0,000000]   DMA zone: 21 pages reserved
>[  +0,000000]   DMA zone: 3998 pages, LIFO batch:0
>[  +0,000000]   DMA32 zone: 14015 pages used for memmap
>[  +0,000000]   DMA32 zone: 896940 pages, LIFO batch:31
>[  +0,000000]   Normal zone: 18432 pages used for memmap
>[  +0,000000]   Normal zone: 1179648 pages, LIFO batch:31
>[  +0,000000] ACPI: PM-Timer IO Port: 0xf808
>[  +0,000000] ACPI: Local APIC address 0xfee00000
>[  +0,000000] ACPI: LAPIC (acpi_id[0x01] lapic_id[0x00] enabled)
>[  +0,000000] ACPI: LAPIC (acpi_id[0x02] lapic_id[0x01] enabled)
>[  +0,000000] ACPI: LAPIC (acpi_id[0x03] lapic_id[0x04] enabled)
>[  +0,000000] ACPI: LAPIC (acpi_id[0x04] lapic_id[0x06] enabled)
>[  +0,000000] ACPI: LAPIC (acpi_id[0x05] lapic_id[0x02] enabled)
>[  +0,000000] ACPI: LAPIC (acpi_id[0x06] lapic_id[0x05] enabled)
>[  +0,000000] ACPI: LAPIC (acpi_id[0x07] lapic_id[0x03] enabled)
>[  +0,000000] ACPI: LAPIC (acpi_id[0x08] lapic_id[0x07] enabled)
>[  +0,000000] ACPI: LAPIC_NMI (acpi_id[0x01] high edge lint[0x1])
>[  +0,000000] ACPI: LAPIC_NMI (acpi_id[0x02] high edge lint[0x1])
>[  +0,000000] ACPI: LAPIC_NMI (acpi_id[0x03] high edge lint[0x1])
>[  +0,000000] ACPI: LAPIC_NMI (acpi_id[0x04] high edge lint[0x1])
>[  +0,000000] ACPI: LAPIC_NMI (acpi_id[0x05] high edge lint[0x1])
>[  +0,000000] ACPI: LAPIC_NMI (acpi_id[0x06] high edge lint[0x1])
>[  +0,000000] ACPI: LAPIC_NMI (acpi_id[0x07] high edge lint[0x1])
>[  +0,000000] ACPI: LAPIC_NMI (acpi_id[0x08] high edge lint[0x1])
>[  +0,000000] ACPI: IOAPIC (id[0x01] address[0xfec00000] gsi_base[0])
>[  +0,000000] IOAPIC[0]: apic_id 1, version 32, address 0xfec00000, GSI 0-23
>[  +0,000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl)
>[  +0,000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 high level)
>[  +0,000000] ACPI: IRQ0 used by override.
>[  +0,000000] ACPI: IRQ2 used by override.
>[  +0,000000] ACPI: IRQ9 used by override.
>[  +0,000000] Using ACPI (MADT) for SMP configuration information
>[  +0,000000] ACPI: HPET id: 0x8086a201 base: 0xfed00000
>[  +0,000000] smpboot: Allowing 8 CPUs, 0 hotplug CPUs
>[  +0,000000] nr_irqs_gsi: 40
>[  +0,000000] PM: Registered nosave memory: [mem 0x0009f000-0x0009ffff]
>[  +0,000000] PM: Registered nosave memory: [mem 0x000a0000-0x000e7fff]
>[  +0,000000] PM: Registered nosave memory: [mem 0x000e8000-0x000fffff]
>[  +0,000000] PM: Registered nosave memory: [mem 0xdbfac000-0xdbfaefff]
>[  +0,000000] PM: Registered nosave memory: [mem 0xdbfae000-0xdbfaefff]
>[  +0,000000] PM: Registered nosave memory: [mem 0xdbfaf000-0xdc7fffff]
>[  +0,000000] PM: Registered nosave memory: [mem 0xdc800000-0xf3ffffff]
>[  +0,000000] PM: Registered nosave memory: [mem 0xf4000000-0xf7ffffff]
>[  +0,000000] PM: Registered nosave memory: [mem 0xf8000000-0xfdffffff]
>[  +0,000000] PM: Registered nosave memory: [mem 0xfe000000-0xfed3ffff]
>[  +0,000000] PM: Registered nosave memory: [mem 0xfed40000-0xfed44fff]
>[  +0,000000] PM: Registered nosave memory: [mem 0xfed45000-0xffffffff]
>[  +0,000000] e820: [mem 0xdc800000-0xf3ffffff] available for PCI devices
>[  +0,000000] Booting paravirtualized kernel on bare hardware
>[  +0,000000] setup_percpu: NR_CPUS:128 nr_cpumask_bits:128 nr_cpu_ids:8 nr_node_ids:1
>[  +0,000000] PERCPU: Embedded 29 pages/cpu @ffff88021fc00000 s86784 r8192 d23808 u262144
>[  +0,000000] pcpu-alloc: s86784 r8192 d23808 u262144 alloc=1*2097152
>[  +0,000000] pcpu-alloc: [0] 0 1 2 3 4 5 6 7 
>[  +0,000000] Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 2048054
>[  +0,000000] Policy zone: Normal
>[  +0,000000] Kernel command line: root=/dev/sda4 ro init=/usr/lib/systemd/systemd nouveau.debug="PDISP=trace,I2C=trace,VBIOS=trace"
>[  +0,000000] PID hash table entries: 4096 (order: 3, 32768 bytes)
>[  +0,000000] AGP: Checking aperture...
>[  +0,000000] AGP: No AGP bridge found
>[  +0,000000] Calgary: detecting Calgary via BIOS EBDA area
>[  +0,000000] Calgary: Unable to locate Rio Grande table in EBDA - bailing!
>[  +0,000000] Memory: 8109288K/8322344K available (5332K kernel code, 887K rwdata, 1684K rodata, 1128K init, 1164K bss, 213056K reserved)
>[  +0,000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
>[  +0,000000] Preemptible hierarchical RCU implementation.
>[  +0,000000] 	RCU dyntick-idle grace-period acceleration is enabled.
>[  +0,000000] 	Dump stacks of tasks blocking RCU-preempt GP.
>[  +0,000000] 	RCU restricting CPUs from NR_CPUS=128 to nr_cpu_ids=8.
>[  +0,000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
>[  +0,000000] NR_IRQS:8448 nr_irqs:744 16
>[  +0,000000] Console: colour VGA+ 80x25
>[  +0,000000] console [tty0] enabled
>[  +0,000000] allocated 33554432 bytes of page_cgroup
>[  +0,000000] please try 'cgroup_disable=memory' option if you don't want memory cgroups
>[  +0,000000] hpet clockevent registered
>[  +0,000000] tsc: Fast TSC calibration using PIT
>[  +0,000000] tsc: Detected 2793.400 MHz processor
>[  +0,000000] Calibrating delay loop (skipped), value calculated using timer frequency.. 5589.58 BogoMIPS (lpj=9311333)
>[  +0,000103] pid_max: default: 32768 minimum: 301
>[  +0,000056] ACPI: Core revision 20140424
>[  +0,003338] ACPI: All ACPI Tables successfully acquired
>[  +0,002566] Security Framework initialized
>[  +0,000054] Yama: becoming mindful.
>[  +0,000516] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes)
>[  +0,001492] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes)
>[  +0,000685] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes)
>[  +0,000062] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes)
>[  +0,000283] Initializing cgroup subsys memory
>[  +0,000066] Initializing cgroup subsys devices
>[  +0,000055] Initializing cgroup subsys freezer
>[  +0,000051] Initializing cgroup subsys net_cls
>[  +0,000052] Initializing cgroup subsys blkio
>[  +0,000068] CPU: Physical Processor ID: 0
>[  +0,000049] CPU: Processor Core ID: 0
>[  +0,000051] mce: CPU supports 9 MCE banks
>[  +0,000056] CPU0: Thermal monitoring enabled (TM1)
>[  +0,000056] Last level iTLB entries: 4KB 512, 2MB 7, 4MB 7
>Last level dTLB entries: 4KB 512, 2MB 32, 4MB 32, 1GB 0
>tlb_flushall_shift: 6
>[  +0,000160] Freeing SMP alternatives memory: 20K (ffffffff819f9000 - ffffffff819fe000)
>[  +0,000798] ftrace: allocating 20429 entries in 80 pages
>[  +0,008754] dmar: Host address width 36
>[  +0,000050] dmar: DRHD base: 0x000000fed90000 flags: 0x1
>[  +0,000057] dmar: IOMMU 0: reg_base_addr fed90000 ver 1:0 cap c90780106f0462 ecap f020e3
>[  +0,000067] dmar: RMRR base: 0x000000dbfde000 end: 0x000000dbfe7fff
>[  +0,000520] ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1
>[  +0,033092] smpboot: CPU0: Intel(R) Core(TM) i7 CPU         860  @ 2.80GHz (fam: 06, model: 1e, stepping: 05)
>[  +0,104127] Performance Events: PEBS fmt1+, 16-deep LBR, Nehalem events, Intel PMU driver.
>[  +0,000200] perf_event_intel: CPU erratum AAJ80 worked around
>[  +0,000051] perf_event_intel: CPUID marked event: 'bus cycles' unavailable
>[  +0,000053] ... version:                3
>[  +0,000049] ... bit width:              48
>[  +0,000048] ... generic registers:      4
>[  +0,000048] ... value mask:             0000ffffffffffff
>[  +0,000050] ... max period:             000000007fffffff
>[  +0,000051] ... fixed-purpose events:   3
>[  +0,000048] ... event mask:             000000070000000f
>[  +0,026124] x86: Booting SMP configuration:
>[  +0,001064] .... node  #0, CPUs:      #1
>[  +0,013475] NMI watchdog: enabled on all CPUs, permanently consumes one hw-PMU counter.
>[  +0,005485]  #2 #3 #4 #5 #6 #7
>[  +0,113393] x86: Booted up 1 node, 8 CPUs
>[  +0,000099] smpboot: Total of 8 processors activated (44712.66 BogoMIPS)
>[  +0,005549] devtmpfs: initialized
>[  +0,002831] PM: Registering ACPI NVS region [mem 0xdbfae440-0xdbfae49f] (96 bytes)
>[  +0,000072] reboot: HP Compaq Laptop series board detected. Selecting BIOS-method for reboots.
>[  +0,000922] pinctrl core: initialized pinctrl subsystem
>[  +0,000086] RTC time: 11:57:18, date: 08/06/14
>[  +0,000091] NET: Registered protocol family 16
>[  +0,000145] cpuidle: using governor ladder
>[  +0,000051] cpuidle: using governor menu
>[  +0,000068] ACPI: bus type PCI registered
>[  +0,000049] acpiphp: ACPI Hot Plug PCI Controller Driver version: 0.5
>[  +0,000116] PCI: MMCONFIG for domain 0000 [bus 00-3f] at [mem 0xf4000000-0xf7ffffff] (base 0xf4000000)
>[  +0,000071] PCI: MMCONFIG at [mem 0xf4000000-0xf7ffffff] reserved in E820
>[  +0,000169] PCI: Using configuration type 1 for base access
>[  +0,013361] ACPI: Added _OSI(Module Device)
>[  +0,000050] ACPI: Added _OSI(Processor Device)
>[  +0,000050] ACPI: Added _OSI(3.0 _SCP Extensions)
>[  +0,000049] ACPI: Added _OSI(Processor Aggregator Device)
>[  +0,036292] ACPI: Dynamic OEM Table Load:
>[  +0,000114] ACPI: SSDT 0xFFFF880213E03800 0003BA (v01 COMPAQ CPU_TM2  00000001 MSFT 0100000E)
>[  +0,026576] ACPI: Dynamic OEM Table Load:
>[  +0,000112] ACPI: SSDT 0xFFFF880213E03C00 0003D8 (v01 COMPAQ CST      00000001 MSFT 0100000E)
>[  +0,040306] ACPI: Interpreter enabled
>[  +0,000053] ACPI Exception: AE_NOT_FOUND, While evaluating Sleep State [\_S1_] (20140424/hwxface-580)
>[  +0,000130] ACPI Exception: AE_NOT_FOUND, While evaluating Sleep State [\_S2_] (20140424/hwxface-580)
>[  +0,000139] ACPI: (supports S0 S3 S4 S5)
>[  +0,000048] ACPI: Using IOAPIC for interrupt routing
>[  +0,000068] PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug
>[  +0,015437] acpi LNXCPU:00: Invalid PBLK length [7]
>[  +0,000057] acpi LNXCPU:01: Invalid PBLK length [7]
>[  +0,000054] acpi LNXCPU:02: Invalid PBLK length [7]
>[  +0,000054] acpi LNXCPU:03: Invalid PBLK length [7]
>[  +0,000054] acpi LNXCPU:04: Invalid PBLK length [7]
>[  +0,000054] acpi LNXCPU:05: Invalid PBLK length [7]
>[  +0,000054] acpi LNXCPU:06: Invalid PBLK length [7]
>[  +0,000054] acpi LNXCPU:07: Invalid PBLK length [7]
>[  +0,010148] ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-ff])
>[  +0,000056] acpi PNP0A08:00: _OSC: OS supports [ExtendedConfig ASPM ClockPM Segments MSI]
>[  +0,000069] ACPI BIOS Error (bug): \_SB_.PCI0._OSC: Excess arguments - ASL declared 5, ACPI requires 4 (20140424/nsarguments-189)
>[  +0,000166] ACPI Error: [CAPD] Namespace lookup failure, AE_ALREADY_EXISTS (20140424/dsfield-211)
>[  +0,000160] ACPI Error: Method parse/execution failed [\_SB_.PCI0._OSC] (Node ffff88021702d668), AE_ALREADY_EXISTS (20140424/psparse-536)
>[  +0,000199] acpi PNP0A08:00: _OSC failed (AE_ALREADY_EXISTS); disabling ASPM
>[  +0,000287] acpi PNP0A08:00: [Firmware Info]: MMCONFIG for domain 0000 [bus 00-3f] only partially covers this bridge
>[  +0,000173] PCI host bridge to bus 0000:00
>[  +0,000051] pci_bus 0000:00: root bus resource [bus 00-ff]
>[  +0,000052] pci_bus 0000:00: root bus resource [mem 0xf8000000-0xfdffffff]
>[  +0,000053] pci_bus 0000:00: root bus resource [io  0x0000-0x0cf7]
>[  +0,000052] pci_bus 0000:00: root bus resource [io  0x1000-0x2fff]
>[  +0,000053] pci_bus 0000:00: root bus resource [io  0x3000-0x6fff]
>[  +0,000052] pci_bus 0000:00: root bus resource [io  0x7000-0xafff]
>[  +0,000052] pci_bus 0000:00: root bus resource [io  0xb000-0xffff]
>[  +0,000052] pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff]
>[  +0,000053] pci_bus 0000:00: root bus resource [mem 0xe0000000-0xf3ffffff]
>[  +0,000054] pci_bus 0000:00: root bus resource [mem 0xfed40000-0xfed44fff]
>[  +0,000059] pci 0000:00:00.0: [8086:d131] type 00 class 0x060000
>[  +0,000088] pci 0000:00:03.0: [8086:d138] type 01 class 0x060400
>[  +0,000049] pci 0000:00:03.0: PME# supported from D0 D3hot D3cold
>[  +0,000028] pci 0000:00:03.0: System wakeup disabled by ACPI
>[  +0,000087] pci 0000:00:08.0: [8086:d155] type 00 class 0x088000
>[  +0,000079] pci 0000:00:08.1: [8086:d156] type 00 class 0x088000
>[  +0,000079] pci 0000:00:08.2: [8086:d157] type 00 class 0x088000
>[  +0,000076] pci 0000:00:08.3: [8086:d158] type 00 class 0x088000
>[  +0,000071] pci 0000:00:10.0: [8086:d150] type 00 class 0x088000
>[  +0,000065] pci 0000:00:10.1: [8086:d151] type 00 class 0x088000
>[  +0,000081] pci 0000:00:16.0: [8086:3b64] type 00 class 0x078000
>[  +0,000027] pci 0000:00:16.0: reg 0x10: [mem 0xf312a000-0xf312a00f 64bit]
>[  +0,000089] pci 0000:00:16.0: PME# supported from D0 D3hot D3cold
>[  +0,000061] pci 0000:00:16.3: [8086:3b67] type 00 class 0x070002
>[  +0,000022] pci 0000:00:16.3: reg 0x10: [io  0x2180-0x2187]
>[  +0,000010] pci 0000:00:16.3: reg 0x14: [mem 0xf3124000-0xf3124fff]
>[  +0,000135] pci 0000:00:19.0: [8086:10ef] type 00 class 0x020000
>[  +0,000016] pci 0000:00:19.0: reg 0x10: [mem 0xf3100000-0xf311ffff]
>[  +0,000008] pci 0000:00:19.0: reg 0x14: [mem 0xf3125000-0xf3125fff]
>[  +0,000007] pci 0000:00:19.0: reg 0x18: [io  0x2100-0x211f]
>[  +0,000057] pci 0000:00:19.0: PME# supported from D0 D3hot D3cold
>[  +0,000028] pci 0000:00:19.0: System wakeup disabled by ACPI
>[  +0,000090] pci 0000:00:1a.0: [8086:3b3c] type 00 class 0x0c0320
>[  +0,000019] pci 0000:00:1a.0: reg 0x10: [mem 0xf3127000-0xf31273ff]
>[  +0,000085] pci 0000:00:1a.0: PME# supported from D0 D3hot D3cold
>[  +0,000029] pci 0000:00:1a.0: System wakeup disabled by ACPI
>[  +0,000089] pci 0000:00:1b.0: [8086:3b56] type 00 class 0x040300
>[  +0,000015] pci 0000:00:1b.0: reg 0x10: [mem 0xf3120000-0xf3123fff 64bit]
>[  +0,000072] pci 0000:00:1b.0: PME# supported from D0 D3hot D3cold
>[  +0,000059] pci 0000:00:1c.0: [8086:3b42] type 01 class 0x060400
>[  +0,000066] pci 0000:00:1c.0: PME# supported from D0 D3hot D3cold
>[  +0,000031] pci 0000:00:1c.0: System wakeup disabled by ACPI
>[  +0,000088] pci 0000:00:1c.4: [8086:3b4a] type 01 class 0x060400
>[  +0,000067] pci 0000:00:1c.4: PME# supported from D0 D3hot D3cold
>[  +0,000029] pci 0000:00:1c.4: System wakeup disabled by ACPI
>[  +0,000085] pci 0000:00:1c.6: [8086:3b4e] type 01 class 0x060400
>[  +0,000066] pci 0000:00:1c.6: PME# supported from D0 D3hot D3cold
>[  +0,000031] pci 0000:00:1c.6: System wakeup disabled by ACPI
>[  +0,000090] pci 0000:00:1d.0: [8086:3b34] type 00 class 0x0c0320
>[  +0,000020] pci 0000:00:1d.0: reg 0x10: [mem 0xf3128000-0xf31283ff]
>[  +0,000082] pci 0000:00:1d.0: PME# supported from D0 D3hot D3cold
>[  +0,000030] pci 0000:00:1d.0: System wakeup disabled by ACPI
>[  +0,000085] pci 0000:00:1e.0: [8086:244e] type 01 class 0x060401
>[  +0,000064] pci 0000:00:1e.0: System wakeup disabled by ACPI
>[  +0,000086] pci 0000:00:1f.0: [8086:3b0a] type 00 class 0x060100
>[  +0,000152] pci 0000:00:1f.2: [8086:3b22] type 00 class 0x010601
>[  +0,000017] pci 0000:00:1f.2: reg 0x10: [io  0x2188-0x218f]
>[  +0,000007] pci 0000:00:1f.2: reg 0x14: [io  0x21a0-0x21a3]
>[  +0,000007] pci 0000:00:1f.2: reg 0x18: [io  0x2190-0x2197]
>[  +0,000007] pci 0000:00:1f.2: reg 0x1c: [io  0x21a4-0x21a7]
>[  +0,000007] pci 0000:00:1f.2: reg 0x20: [io  0x2120-0x213f]
>[  +0,000007] pci 0000:00:1f.2: reg 0x24: [mem 0xf3126000-0xf31267ff]
>[  +0,000041] pci 0000:00:1f.2: PME# supported from D3hot
>[  +0,000119] pci 0000:01:00.0: [10de:0a63] type 00 class 0x030000
>[  +0,000011] pci 0000:01:00.0: reg 0x10: [mem 0xf2000000-0xf2ffffff]
>[  +0,000009] pci 0000:01:00.0: reg 0x14: [mem 0xe0000000-0xefffffff 64bit pref]
>[  +0,000010] pci 0000:01:00.0: reg 0x1c: [mem 0xf0000000-0xf1ffffff 64bit pref]
>[  +0,000006] pci 0000:01:00.0: reg 0x24: [io  0x1100-0x117f]
>[  +0,000007] pci 0000:01:00.0: reg 0x30: [mem 0x00000000-0x0007ffff pref]
>[  +0,000087] pci 0000:01:00.1: [10de:0be3] type 00 class 0x040300
>[  +0,000011] pci 0000:01:00.1: reg 0x10: [mem 0xf3000000-0xf3003fff]
>[  +0,005165] pci 0000:00:03.0: PCI bridge to [bus 01]
>[  +0,000053] pci 0000:00:03.0:   bridge window [io  0x1000-0x1fff]
>[  +0,000003] pci 0000:00:03.0:   bridge window [mem 0xf2000000-0xf30fffff]
>[  +0,000004] pci 0000:00:03.0:   bridge window [mem 0xe0000000-0xf1ffffff 64bit pref]
>[  +0,000068] pci 0000:00:1c.0: PCI bridge to [bus 18]
>[  +0,000144] pci 0000:24:00.0: [1033:0194] type 00 class 0x0c0330
>[  +0,000029] pci 0000:24:00.0: reg 0x10: [mem 0xf3200000-0xf3201fff 64bit]
>[  +0,000143] pci 0000:24:00.0: PME# supported from D0 D3hot
>[  +0,006233] pci 0000:00:1c.4: PCI bridge to [bus 24]
>[  +0,000055] pci 0000:00:1c.4:   bridge window [mem 0xf3200000-0xf32fffff]
>[  +0,000070] pci 0000:00:1c.6: PCI bridge to [bus 30]
>[  +0,000164] pci 0000:00:1e.0: PCI bridge to [bus 0d] (subtractive decode)
>[  +0,000061] pci 0000:00:1e.0:   bridge window [mem 0xf8000000-0xfdffffff] (subtractive decode)
>[  +0,000002] pci 0000:00:1e.0:   bridge window [io  0x0000-0x0cf7] (subtractive decode)
>[  +0,000001] pci 0000:00:1e.0:   bridge window [io  0x1000-0x2fff] (subtractive decode)
>[  +0,000002] pci 0000:00:1e.0:   bridge window [io  0x3000-0x6fff] (subtractive decode)
>[  +0,000001] pci 0000:00:1e.0:   bridge window [io  0x7000-0xafff] (subtractive decode)
>[  +0,000002] pci 0000:00:1e.0:   bridge window [io  0xb000-0xffff] (subtractive decode)
>[  +0,000001] pci 0000:00:1e.0:   bridge window [mem 0x000a0000-0x000bffff] (subtractive decode)
>[  +0,000002] pci 0000:00:1e.0:   bridge window [mem 0xe0000000-0xf3ffffff] (subtractive decode)
>[  +0,000002] pci 0000:00:1e.0:   bridge window [mem 0xfed40000-0xfed44fff] (subtractive decode)
>[  +0,000303] ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 *5 6 7 10 11 14 15)
>[  +0,000425] ACPI: PCI Interrupt Link [LNKB] (IRQs 3 4 5 6 7 *10 11 14 15)
>[  +0,000426] ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 *5 6 7 10 11 14 15)
>[  +0,000424] ACPI: PCI Interrupt Link [LNKD] (IRQs 3 4 5 6 7 *10 11 14 15)
>[  +0,000423] ACPI: PCI Interrupt Link [LNKE] (IRQs 3 4 5 6 7 10 *11 14 15)
>[  +0,000423] ACPI: PCI Interrupt Link [LNKF] (IRQs 3 4 *5 6 7 10 11 14 15)
>[  +0,000423] ACPI: PCI Interrupt Link [LNKG] (IRQs 3 4 5 6 7 *10 11 14 15)
>[  +0,000427] ACPI: PCI Interrupt Link [LNKH] (IRQs 3 4 5 6 7 10 11 14 15) *0, disabled.
>[  +0,000647] vgaarb: device added: PCI:0000:01:00.0,decodes=io+mem,owns=io+mem,locks=none
>[  +0,000068] vgaarb: loaded
>[  +0,000047] vgaarb: bridge control possible 0000:01:00.0
>[  +0,000078] PCI: Using ACPI for IRQ routing
>[  +0,001324] PCI: Discovered peer bus 3f
>[  +0,000049] PCI: root bus 3f: using default resources
>[  +0,000001] PCI: Probing PCI hardware (bus 3f)
>[  +0,000022] PCI host bridge to bus 0000:3f
>[  +0,000050] pci_bus 0000:3f: root bus resource [io  0x0000-0xffff]
>[  +0,000052] pci_bus 0000:3f: root bus resource [mem 0x00000000-0xfffffffff]
>[  +0,000053] pci_bus 0000:3f: No busn resource found for root bus, will use [bus 3f-ff]
>[  +0,000068] pci_bus 0000:3f: busn_res: can not insert [bus 3f-ff] under domain [bus 00-ff] (conflicts with (null) [bus 00-ff])
>[  +0,000005] pci 0000:3f:00.0: [8086:2c51] type 00 class 0x060000
>[  +0,000038] pci 0000:3f:00.1: [8086:2c81] type 00 class 0x060000
>[  +0,000037] pci 0000:3f:02.0: [8086:2c90] type 00 class 0x060000
>[  +0,000035] pci 0000:3f:02.1: [8086:2c91] type 00 class 0x060000
>[  +0,000036] pci 0000:3f:03.0: [8086:2c98] type 00 class 0x060000
>[  +0,000035] pci 0000:3f:03.1: [8086:2c99] type 00 class 0x060000
>[  +0,000037] pci 0000:3f:03.4: [8086:2c9c] type 00 class 0x060000
>[  +0,000035] pci 0000:3f:04.0: [8086:2ca0] type 00 class 0x060000
>[  +0,000035] pci 0000:3f:04.1: [8086:2ca1] type 00 class 0x060000
>[  +0,000035] pci 0000:3f:04.2: [8086:2ca2] type 00 class 0x060000
>[  +0,000034] pci 0000:3f:04.3: [8086:2ca3] type 00 class 0x060000
>[  +0,000036] pci 0000:3f:05.0: [8086:2ca8] type 00 class 0x060000
>[  +0,000035] pci 0000:3f:05.1: [8086:2ca9] type 00 class 0x060000
>[  +0,000034] pci 0000:3f:05.2: [8086:2caa] type 00 class 0x060000
>[  +0,000035] pci 0000:3f:05.3: [8086:2cab] type 00 class 0x060000
>[  +0,000045] pci_bus 0000:3f: busn_res: [bus 3f-ff] end is updated to 3f
>[  +0,000003] pci_bus 0000:3f: busn_res: can not insert [bus 3f] under domain [bus 00-ff] (conflicts with (null) [bus 00-ff])
>[  +0,000003] PCI: pci_cache_line_size set to 64 bytes
>[  +0,000059] e820: reserve RAM buffer [mem 0x0009f800-0x0009ffff]
>[  +0,000001] e820: reserve RAM buffer [mem 0xdbfac440-0xdbffffff]
>[  +0,000090] NetLabel: Initializing
>[  +0,000048] NetLabel:  domain hash size = 128
>[  +0,000049] NetLabel:  protocols = UNLABELED CIPSOv4
>[  +0,000059] NetLabel:  unlabeled traffic allowed by default
>[  +0,000082] HPET: 8 timers in total, 5 timers will be used for per-cpu timer
>[  +0,000059] hpet0: at MMIO 0xfed00000, IRQs 2, 8, 40, 41, 42, 43, 44, 0
>[  +0,000324] hpet0: 8 comparators, 64-bit 14.318180 MHz counter
>[  +0,002086] hpet: hpet2 irq 40 for MSI
>[  +0,000039] hpet: hpet3 irq 41 for MSI
>[  +0,000036] hpet: hpet4 irq 42 for MSI
>[  +0,000045] hpet: hpet5 irq 43 for MSI
>[  +0,000042] hpet: hpet6 irq 44 for MSI
>[  +0,000089] Switched to clocksource hpet
>[  +0,004004] pnp: PnP ACPI init
>[  +0,000062] ACPI: bus type PNP registered
>[  +0,000090] pnp 00:00: Plug and Play ACPI device, IDs PNP0b00 (active)
>[  +0,000026] pnp 00:01: Plug and Play ACPI device, IDs PNP0f13 PNP0f0e (active)
>[  +0,000022] pnp 00:02: Plug and Play ACPI device, IDs PNP0303 (active)
>[  +0,000179] pnp 00:03: Plug and Play ACPI device, IDs PNP0501 PNP0500 (active)
>[  +0,000043] pnp 00:04: Plug and Play ACPI device, IDs IFX0102 PNP0c31 (active)
>[  +0,000166] system 00:05: Plug and Play ACPI device, IDs PNP0c02 (active)
>[  +0,000046] system 00:06: [io  0x04d0-0x04d1] has been reserved
>[  +0,000054] system 00:06: Plug and Play ACPI device, IDs PNP0c02 (active)
>[  +0,000047] system 00:07: [io  0x0400-0x041f] has been reserved
>[  +0,000053] system 00:07: [io  0x0420-0x043f] has been reserved
>[  +0,000052] system 00:07: [io  0x0440-0x045f] has been reserved
>[  +0,000052] system 00:07: [io  0x0460-0x047f] has been reserved
>[  +0,000052] system 00:07: [io  0x0480-0x048f] has been reserved
>[  +0,000052] system 00:07: [io  0xf800-0xf81f] has been reserved
>[  +0,000052] system 00:07: [io  0xf820-0xf83f] has been reserved
>[  +0,000052] system 00:07: [io  0xf840-0xf85f] has been reserved
>[  +0,000052] system 00:07: [io  0xf860-0xf87f] has been reserved
>[  +0,000052] system 00:07: [io  0xfa00-0xfa3f] has been reserved
>[  +0,000052] system 00:07: [io  0xfc00-0xfc7f] has been reserved
>[  +0,000052] system 00:07: [io  0xfc80-0xfcff] has been reserved
>[  +0,000052] system 00:07: [io  0xfe00-0xfe7f] has been reserved
>[  +0,000052] system 00:07: [io  0xfe80-0xfeff] has been reserved
>[  +0,000053] system 00:07: Plug and Play ACPI device, IDs PNP0c02 (active)
>[  +0,011284] system 00:08: [mem 0x00000000-0x0009ffff] could not be reserved
>[  +0,000056] system 00:08: [mem 0x00100000-0xdfffffff] could not be reserved
>[  +0,000054] system 00:08: [mem 0x000e4000-0x000fffff] could not be reserved
>[  +0,000054] system 00:08: [mem 0xfec01000-0xfecfffff] has been reserved
>[  +0,000053] system 00:08: [mem 0xfed00400-0xfed3ffff] has been reserved
>[  +0,000053] system 00:08: [mem 0xfed45000-0xffffffff] could not be reserved
>[  +0,000054] system 00:08: [mem 0xf4000000-0xf7ffffff] has been reserved
>[  +0,000053] system 00:08: [mem 0x000d0600-0x000e3fff] has been reserved
>[  +0,000054] system 00:08: Plug and Play ACPI device, IDs PNP0c01 (active)
>[  +0,000009] pnp: PnP ACPI: found 9 devices
>[  +0,000048] ACPI: bus type PNP unregistered
>[  +0,006330] pci 0000:00:1c.0: bridge window [io  0x1000-0x0fff] to [bus 18] add_size 1000
>[  +0,000004] pci 0000:00:1c.0: bridge window [mem 0x00100000-0x000fffff 64bit pref] to [bus 18] add_size 200000
>[  +0,000002] pci 0000:00:1c.0: bridge window [mem 0x00100000-0x000fffff] to [bus 18] add_size 200000
>[  +0,000007] pci 0000:00:1c.4: bridge window [io  0x1000-0x0fff] to [bus 24] add_size 1000
>[  +0,000002] pci 0000:00:1c.4: bridge window [mem 0x00100000-0x000fffff 64bit pref] to [bus 24] add_size 200000
>[  +0,000007] pci 0000:00:1c.6: bridge window [io  0x1000-0x0fff] to [bus 30] add_size 1000
>[  +0,000002] pci 0000:00:1c.6: bridge window [mem 0x00100000-0x000fffff 64bit pref] to [bus 30] add_size 200000
>[  +0,000002] pci 0000:00:1c.6: bridge window [mem 0x00100000-0x000fffff] to [bus 30] add_size 200000
>[  +0,000009] pci 0000:00:1c.0: res[14]=[mem 0x00100000-0x000fffff] get_res_add_size add_size 200000
>[  +0,000002] pci 0000:00:1c.0: res[15]=[mem 0x00100000-0x000fffff 64bit pref] get_res_add_size add_size 200000
>[  +0,000002] pci 0000:00:1c.4: res[15]=[mem 0x00100000-0x000fffff 64bit pref] get_res_add_size add_size 200000
>[  +0,000002] pci 0000:00:1c.6: res[14]=[mem 0x00100000-0x000fffff] get_res_add_size add_size 200000
>[  +0,000001] pci 0000:00:1c.6: res[15]=[mem 0x00100000-0x000fffff 64bit pref] get_res_add_size add_size 200000
>[  +0,000002] pci 0000:00:1c.0: res[13]=[io  0x1000-0x0fff] get_res_add_size add_size 1000
>[  +0,000002] pci 0000:00:1c.4: res[13]=[io  0x1000-0x0fff] get_res_add_size add_size 1000
>[  +0,000002] pci 0000:00:1c.6: res[13]=[io  0x1000-0x0fff] get_res_add_size add_size 1000
>[  +0,000003] pci 0000:00:1c.0: BAR 14: assigned [mem 0xf8000000-0xf81fffff]
>[  +0,000057] pci 0000:00:1c.0: BAR 15: assigned [mem 0xf8200000-0xf83fffff 64bit pref]
>[  +0,000068] pci 0000:00:1c.4: BAR 15: assigned [mem 0xf8400000-0xf85fffff 64bit pref]
>[  +0,000067] pci 0000:00:1c.6: BAR 14: assigned [mem 0xf8600000-0xf87fffff]
>[  +0,000055] pci 0000:00:1c.6: BAR 15: assigned [mem 0xf8800000-0xf89fffff 64bit pref]
>[  +0,000067] pci 0000:00:1c.0: BAR 13: assigned [io  0x3000-0x3fff]
>[  +0,000053] pci 0000:00:1c.4: BAR 13: assigned [io  0x4000-0x4fff]
>[  +0,000053] pci 0000:00:1c.6: BAR 13: assigned [io  0x5000-0x5fff]
>[  +0,000054] pci 0000:01:00.0: BAR 6: assigned [mem 0xf3080000-0xf30fffff pref]
>[  +0,000066] pci 0000:00:03.0: PCI bridge to [bus 01]
>[  +0,000051] pci 0000:00:03.0:   bridge window [io  0x1000-0x1fff]
>[  +0,000054] pci 0000:00:03.0:   bridge window [mem 0xf2000000-0xf30fffff]
>[  +0,000055] pci 0000:00:03.0:   bridge window [mem 0xe0000000-0xf1ffffff 64bit pref]
>[  +0,000068] pci 0000:00:1c.0: PCI bridge to [bus 18]
>[  +0,000051] pci 0000:00:1c.0:   bridge window [io  0x3000-0x3fff]
>[  +0,000055] pci 0000:00:1c.0:   bridge window [mem 0xf8000000-0xf81fffff]
>[  +0,000054] pci 0000:00:1c.0:   bridge window [mem 0xf8200000-0xf83fffff 64bit pref]
>[  +0,000070] pci 0000:00:1c.4: PCI bridge to [bus 24]
>[  +0,000051] pci 0000:00:1c.4:   bridge window [io  0x4000-0x4fff]
>[  +0,000054] pci 0000:00:1c.4:   bridge window [mem 0xf3200000-0xf32fffff]
>[  +0,000055] pci 0000:00:1c.4:   bridge window [mem 0xf8400000-0xf85fffff 64bit pref]
>[  +0,000069] pci 0000:00:1c.6: PCI bridge to [bus 30]
>[  +0,000051] pci 0000:00:1c.6:   bridge window [io  0x5000-0x5fff]
>[  +0,000055] pci 0000:00:1c.6:   bridge window [mem 0xf8600000-0xf87fffff]
>[  +0,000055] pci 0000:00:1c.6:   bridge window [mem 0xf8800000-0xf89fffff 64bit pref]
>[  +0,000069] pci 0000:00:1e.0: PCI bridge to [bus 0d]
>[  +0,000058] pci_bus 0000:00: resource 4 [mem 0xf8000000-0xfdffffff]
>[  +0,000002] pci_bus 0000:00: resource 5 [io  0x0000-0x0cf7]
>[  +0,000001] pci_bus 0000:00: resource 6 [io  0x1000-0x2fff]
>[  +0,000002] pci_bus 0000:00: resource 7 [io  0x3000-0x6fff]
>[  +0,000001] pci_bus 0000:00: resource 8 [io  0x7000-0xafff]
>[  +0,000001] pci_bus 0000:00: resource 9 [io  0xb000-0xffff]
>[  +0,000002] pci_bus 0000:00: resource 10 [mem 0x000a0000-0x000bffff]
>[  +0,000001] pci_bus 0000:00: resource 11 [mem 0xe0000000-0xf3ffffff]
>[  +0,000002] pci_bus 0000:00: resource 12 [mem 0xfed40000-0xfed44fff]
>[  +0,000002] pci_bus 0000:01: resource 0 [io  0x1000-0x1fff]
>[  +0,000001] pci_bus 0000:01: resource 1 [mem 0xf2000000-0xf30fffff]
>[  +0,000002] pci_bus 0000:01: resource 2 [mem 0xe0000000-0xf1ffffff 64bit pref]
>[  +0,000002] pci_bus 0000:18: resource 0 [io  0x3000-0x3fff]
>[  +0,000001] pci_bus 0000:18: resource 1 [mem 0xf8000000-0xf81fffff]
>[  +0,000002] pci_bus 0000:18: resource 2 [mem 0xf8200000-0xf83fffff 64bit pref]
>[  +0,000001] pci_bus 0000:24: resource 0 [io  0x4000-0x4fff]
>[  +0,000002] pci_bus 0000:24: resource 1 [mem 0xf3200000-0xf32fffff]
>[  +0,000001] pci_bus 0000:24: resource 2 [mem 0xf8400000-0xf85fffff 64bit pref]
>[  +0,000002] pci_bus 0000:30: resource 0 [io  0x5000-0x5fff]
>[  +0,000001] pci_bus 0000:30: resource 1 [mem 0xf8600000-0xf87fffff]
>[  +0,000002] pci_bus 0000:30: resource 2 [mem 0xf8800000-0xf89fffff 64bit pref]
>[  +0,000002] pci_bus 0000:0d: resource 4 [mem 0xf8000000-0xfdffffff]
>[  +0,000001] pci_bus 0000:0d: resource 5 [io  0x0000-0x0cf7]
>[  +0,000002] pci_bus 0000:0d: resource 6 [io  0x1000-0x2fff]
>[  +0,000001] pci_bus 0000:0d: resource 7 [io  0x3000-0x6fff]
>[  +0,000002] pci_bus 0000:0d: resource 8 [io  0x7000-0xafff]
>[  +0,000001] pci_bus 0000:0d: resource 9 [io  0xb000-0xffff]
>[  +0,000002] pci_bus 0000:0d: resource 10 [mem 0x000a0000-0x000bffff]
>[  +0,000001] pci_bus 0000:0d: resource 11 [mem 0xe0000000-0xf3ffffff]
>[  +0,000002] pci_bus 0000:0d: resource 12 [mem 0xfed40000-0xfed44fff]
>[  +0,000002] pci_bus 0000:3f: resource 4 [io  0x0000-0xffff]
>[  +0,000002] pci_bus 0000:3f: resource 5 [mem 0x00000000-0xfffffffff]
>[  +0,000024] NET: Registered protocol family 2
>[  +0,000226] TCP established hash table entries: 65536 (order: 7, 524288 bytes)
>[  +0,000263] TCP bind hash table entries: 65536 (order: 8, 1048576 bytes)
>[  +0,000318] TCP: Hash tables configured (established 65536 bind 65536)
>[  +0,000071] TCP: reno registered
>[  +0,001077] UDP hash table entries: 4096 (order: 5, 131072 bytes)
>[  +0,000107] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes)
>[  +0,000136] NET: Registered protocol family 1
>[  +0,000450] pci 0000:01:00.0: Boot video device
>[  +0,000177] PCI: CLS 64 bytes, default 64
>[  +0,000042] Unpacking initramfs...
>[  +0,051373] Freeing initrd memory: 3200K (ffff880037cd0000 - ffff880037ff0000)
>[  +0,000099] PCI-DMA: Using software bounce buffering for IO (SWIOTLB)
>[  +0,000053] software IO TLB [mem 0xd7fac000-0xdbfac000] (64MB) mapped at [ffff8800d7fac000-ffff8800dbfabfff]
>[  +0,000373] Scanning for low memory corruption every 60 seconds
>[  +0,000342] futex hash table entries: 2048 (order: 5, 131072 bytes)
>[  +0,000352] HugeTLB registered 2 MB page size, pre-allocated 0 pages
>[  +0,001227] zbud: loaded
>[  +0,000184] VFS: Disk quotas dquot_6.5.2
>[  +0,000080] Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
>[  +0,000152] msgmni has been set to 15844
>[  +0,000097] Key type big_key registered
>[  +0,000209] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 252)
>[  +0,000136] io scheduler noop registered
>[  +0,000051] io scheduler deadline registered
>[  +0,000089] io scheduler cfq registered (default)
>[  +0,000526] pci_hotplug: PCI Hot Plug PCI Core version: 0.5
>[  +0,000075] pciehp: PCI Express Hot Plug Controller Driver version: 0.4
>[  +0,000079] intel_idle: MWAIT substates: 0x1120
>[  +0,000008] intel_idle: v0.4 model 0x1E
>[  +0,000002] intel_idle: lapic_timer_reliable_states 0x2
>[  +0,000261] GHES: HEST is not enabled!
>[  +0,000108] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
>[  +0,020646] 00:03: ttyS0 at I/O 0x3f8 (irq = 4, base_baud = 115200) is a 16550A
>[  +0,020909] 0000:00:16.3: ttyS1 at I/O 0x2180 (irq = 17, base_baud = 115200) is a 16550A
>[  +0,000226] Linux agpgart interface v0.103
>[  +0,000102] rtc_cmos 00:00: RTC can wake from S4
>[  +0,000170] rtc_cmos 00:00: rtc core: registered rtc_cmos as rtc0
>[  +0,000077] rtc_cmos 00:00: alarms up to one month, y3k, 114 bytes nvram, hpet irqs
>[  +0,000079] ledtrig-cpu: registered to indicate activity on CPUs
>[  +0,000146] TCP: cubic registered
>[  +0,000131] NET: Registered protocol family 10
>[  +0,000247] NET: Registered protocol family 17
>[  +0,000386] registered taskstats version 1
>[  +0,000436]   Magic number: 10:71:984
>[  +0,000148] rtc_cmos 00:00: setting system clock to 2014-08-06 11:57:18 UTC (1407326238)
>[  +0,000107] PM: Hibernation image not present or could not be loaded.
>[  +0,000777] Freeing unused kernel memory: 1128K (ffffffff818df000 - ffffffff819f9000)
>[  +0,000068] Write protecting the kernel read-only data: 8192k
>[  +0,002192] Freeing unused kernel memory: 800K (ffff880001538000 - ffff880001600000)
>[  +0,001019] Freeing unused kernel memory: 364K (ffff8800017a5000 - ffff880001800000)
>[  +0,006232] random: systemd-tmpfile urandom read with 5 bits of entropy available
>[  +0,001190] systemd-udevd[83]: starting version 215
>[  +0,008651] i8042: PNP: PS/2 Controller [PNP0303:KBD,PNP0f0e:PS2M] at 0x60,0x64 irq 1,12
>[  +0,002858] serio: i8042 KBD port at 0x60,0x64 irq 1
>[  +0,000099] serio: i8042 AUX port at 0x60,0x64 irq 12
>[  +0,001316] ACPI: bus type USB registered
>[  +0,000070] usbcore: registered new interface driver usbfs
>[  +0,000060] usbcore: registered new interface driver hub
>[  +0,000109] usbcore: registered new device driver usb
>[  +0,000401] SCSI subsystem initialized
>[  +0,000224] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
>[  +0,000265] ehci-pci: EHCI PCI platform driver
>[  +0,000030] xhci_hcd 0000:24:00.0: xHCI Host Controller
>[  +0,000008] xhci_hcd 0000:24:00.0: new USB bus registered, assigned bus number 1
>[  +0,000225] xhci_hcd 0000:24:00.0: irq 45 for MSI/MSI-X
>[  +0,000007] xhci_hcd 0000:24:00.0: irq 46 for MSI/MSI-X
>[  +0,000006] xhci_hcd 0000:24:00.0: irq 47 for MSI/MSI-X
>[  +0,000006] xhci_hcd 0000:24:00.0: irq 48 for MSI/MSI-X
>[  +0,000004] xhci_hcd 0000:24:00.0: irq 49 for MSI/MSI-X
>[  +0,000004] xhci_hcd 0000:24:00.0: irq 50 for MSI/MSI-X
>[  +0,000003] xhci_hcd 0000:24:00.0: irq 51 for MSI/MSI-X
>[  +0,000004] xhci_hcd 0000:24:00.0: irq 52 for MSI/MSI-X
>[  +0,000316] hub 1-0:1.0: USB hub found
>[  +0,000062] hub 1-0:1.0: 2 ports detected
>[  +0,000182] xhci_hcd 0000:24:00.0: xHCI Host Controller
>[  +0,000026] ehci-pci 0000:00:1a.0: EHCI Host Controller
>[  +0,000005] ehci-pci 0000:00:1a.0: new USB bus registered, assigned bus number 2
>[  +0,000012] ehci-pci 0000:00:1a.0: debug port 2
>[  +0,003938] ehci-pci 0000:00:1a.0: cache line size of 64 is not supported
>[  +0,000012] ehci-pci 0000:00:1a.0: irq 20, io mem 0xf3127000
>[  +0,000019] libata version 3.00 loaded.
>[  +0,000174] xhci_hcd 0000:24:00.0: new USB bus registered, assigned bus number 3
>[  +0,000253] hub 3-0:1.0: USB hub found
>[  +0,000068] hub 3-0:1.0: 2 ports detected
>[  +0,008258] ehci-pci 0000:00:1a.0: USB 2.0 started, EHCI 1.00
>[  +0,000199] hub 2-0:1.0: USB hub found
>[  +0,000054] hub 2-0:1.0: 3 ports detected
>[  +0,000288] ehci-pci 0000:00:1d.0: EHCI Host Controller
>[  +0,000055] ehci-pci 0000:00:1d.0: new USB bus registered, assigned bus number 4
>[  +0,000075] ehci-pci 0000:00:1d.0: debug port 2
>[  +0,003954] ehci-pci 0000:00:1d.0: cache line size of 64 is not supported
>[  +0,000006] ehci-pci 0000:00:1d.0: irq 20, io mem 0xf3128000
>[  +0,008819] ehci-pci 0000:00:1d.0: USB 2.0 started, EHCI 1.00
>[  +0,000214] hub 4-0:1.0: USB hub found
>[  +0,000058] hub 4-0:1.0: 3 ports detected
>[  +0,000229] ahci 0000:00:1f.2: version 3.0
>[  +0,000145] ahci 0000:00:1f.2: irq 53 for MSI/MSI-X
>[  +0,000050] ahci 0000:00:1f.2: AHCI 0001.0300 32 slots 6 ports 3 Gbps 0x17 impl SATA mode
>[  +0,000069] ahci 0000:00:1f.2: flags: 64bit ncq sntf pm led clo pio slum part sxs apst 
>[  +0,000873] scsi0 : ahci
>[  +0,000330] scsi1 : ahci
>[  +0,000323] scsi2 : ahci
>[  +0,000256] scsi3 : ahci
>[  +0,000221] scsi4 : ahci
>[  +0,000213] scsi5 : ahci
>[  +0,000087] ata1: SATA max UDMA/133 abar m2048@0xf3126000 port 0xf3126100 irq 53
>[  +0,000067] ata2: SATA max UDMA/133 abar m2048@0xf3126000 port 0xf3126180 irq 53
>[  +0,000083] ata3: SATA max UDMA/133 abar m2048@0xf3126000 port 0xf3126200 irq 53
>[  +0,000065] ata4: DUMMY
>[  +0,000047] ata5: SATA max UDMA/133 abar m2048@0xf3126000 port 0xf3126300 irq 53
>[  +0,000065] ata6: DUMMY
>[  +0,290362] usb 2-1: new high-speed USB device number 2 using ehci-pci
>[  +0,030035] ata3: SATA link down (SStatus 0 SControl 300)
>[  +0,000083] ata5: SATA link down (SStatus 0 SControl 300)
>[  +0,000070] ata2: SATA link up 1.5 Gbps (SStatus 113 SControl 300)
>[  +0,000072] ata1: SATA link up 3.0 Gbps (SStatus 123 SControl 300)
>[  +0,001099] ata1.00: ACPI cmd ef/03:0c:00:00:00:a0 (SET FEATURES) filtered out
>[  +0,000072] ata1.00: ACPI cmd ef/03:45:00:00:00:a0 (SET FEATURES) filtered out
>[  +0,000312] ata1.00: ACPI cmd c6/00:10:00:00:00:a0 (SET MULTIPLE MODE) succeeded
>[  +0,000221] ata1.00: ACPI cmd e3/00:00:00:00:00:a0 (IDLE) succeeded
>[  +0,000008] ata1.00: ACPI cmd b1/c1:00:00:00:00:a0 (DEVICE CONFIGURATION OVERLAY) filtered out
>[  +0,000083] ata1.00: ACPI cmd f5/00:00:00:00:00:a0 (SECURITY FREEZE LOCK) filtered out
>[  +0,000071] ata1.00: ACPI cmd ef/10:03:00:00:00:a0 (SET FEATURES) filtered out
>[  +0,001269] ata1.00: ATA-8: Hitachi HDS721025CLA382, JP1OA3GH, max UDMA/133
>[  +0,000067] ata1.00: 488397168 sectors, multi 16: LBA48 NCQ (depth 31/32), AA
>[  +0,001307] ata1.00: ACPI cmd ef/03:0c:00:00:00:a0 (SET FEATURES) filtered out
>[  +0,000074] ata1.00: ACPI cmd ef/03:45:00:00:00:a0 (SET FEATURES) filtered out
>[  +0,000318] ata1.00: ACPI cmd c6/00:10:00:00:00:a0 (SET MULTIPLE MODE) succeeded
>[  +0,000186] ata1.00: ACPI cmd e3/00:00:00:00:00:a0 (IDLE) succeeded
>[  +0,000007] ata1.00: ACPI cmd b1/c1:00:00:00:00:a0 (DEVICE CONFIGURATION OVERLAY) filtered out
>[  +0,000082] ata1.00: ACPI cmd f5/00:00:00:00:00:a0 (SECURITY FREEZE LOCK) filtered out
>[  +0,000073] ata1.00: ACPI cmd ef/10:03:00:00:00:a0 (SET FEATURES) filtered out
>[  +0,000693] ata2.00: ACPI cmd ef/03:0c:00:00:00:a0 (SET FEATURES) filtered out
>[  +0,000075] ata2.00: ACPI cmd ef/03:45:00:00:00:a0 (SET FEATURES) filtered out
>[  +0,000066] ata2.00: ACPI cmd ef/10:03:00:00:00:a0 (SET FEATURES) filtered out
>[  +0,000072] ata2.00: ATAPI: hp      DVD-ROM TS-H353C, H430, max UDMA/100
>[  +0,000280] ata1.00: configured for UDMA/133
>[  +0,000432] scsi 0:0:0:0: Direct-Access     ATA      Hitachi HDS72102 A3GH PQ: 0 ANSI: 5
>[  +0,006827] ata2.00: ACPI cmd ef/03:0c:00:00:00:a0 (SET FEATURES) filtered out
>[  +0,000076] ata2.00: ACPI cmd ef/03:45:00:00:00:a0 (SET FEATURES) filtered out
>[  +0,000066] ata2.00: ACPI cmd ef/10:03:00:00:00:a0 (SET FEATURES) filtered out
>[  +0,000067] ata2.00: configured for UDMA/100
>[  +0,008052] scsi 1:0:0:0: CD-ROM            hp       DVD-ROM TS-H353C H430 PQ: 0 ANSI: 5
>[  +0,016795] sd 0:0:0:0: [sda] 488397168 512-byte logical blocks: (250 GB/232 GiB)
>[  +0,000128] sd 0:0:0:0: [sda] Write Protect is off
>[  +0,000054] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
>[  +0,000015] sd 0:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA
>[  +0,020960]  sda: sda1 sda2 sda3 sda4
>[  +0,001227] sd 0:0:0:0: [sda] Attached SCSI disk
>[  +0,032713] hub 2-1:1.0: USB hub found
>[  +0,000233] hub 2-1:1.0: 6 ports detected
>[  +0,029481] sr0: scsi3-mmc drive: 1x/40x cd/rw xa/form2 cdda tray
>[  +0,000065] cdrom: Uniform CD-ROM driver Revision: 3.20
>[  +0,000370] sr 1:0:0:0: Attached scsi CD-ROM sr0
>[  +0,099382] usb 4-1: new high-speed USB device number 2 using ehci-pci
>[  +0,124354] hub 4-1:1.0: USB hub found
>[  +0,000143] hub 4-1:1.0: 8 ports detected
>[  +0,125779] usb 2-1.3: new low-speed USB device number 3 using ehci-pci
>[  +0,093624] hidraw: raw HID events driver (C) Jiri Kosina
>[  +0,008683] usbcore: registered new interface driver usbhid
>[  +0,000052] usbhid: USB HID core driver
>[  +0,000427] input: Microsoft Wired Keyboard 600 as /devices/pci0000:00/0000:00:1a.0/usb2/2-1/2-1.3/2-1.3:1.0/0003:045E:0750.0001/input/input2
>[  +0,000215] hid-generic 0003:045E:0750.0001: input,hidraw0: USB HID v1.11 Keyboard [Microsoft Wired Keyboard 600] on usb-0000:00:1a.0-1.3/input0
>[  +0,000209] tsc: Refined TSC clocksource calibration: 2793.314 MHz
>[  +0,002432] input: Microsoft Wired Keyboard 600 as /devices/pci0000:00/0000:00:1a.0/usb2/2-1/2-1.3/2-1.3:1.1/0003:045E:0750.0002/input/input3
>[  +0,000268] hid-generic 0003:045E:0750.0002: input,hidraw1: USB HID v1.11 Device [Microsoft Wired Keyboard 600] on usb-0000:00:1a.0-1.3/input1
>[  +0,050875] usb 2-1.4: new low-speed USB device number 4 using ehci-pci
>[  +0,090369] input: Logitech USB Optical Mouse as /devices/pci0000:00/0000:00:1a.0/usb2/2-1/2-1.4/2-1.4:1.0/0003:046D:C06A.0003/input/input4
>[  +0,000198] hid-generic 0003:046D:C06A.0003: input,hidraw2: USB HID v1.11 Mouse [Logitech USB Optical Mouse] on usb-0000:00:1a.0-1.4/input0
>[  +0,478277] EXT4-fs (sda4): mounted filesystem with ordered data mode. Opts: (null)
>[  +0,009298] random: nonblocking pool is initialized
>[  +0,369553] Switched to clocksource tsc
>[  +0,697364] systemd[1]: systemd 215 running in system mode. (+PAM -AUDIT -SELINUX -IMA -SYSVINIT +LIBCRYPTSETUP +GCRYPT +ACL +XZ +SECCOMP -APPARMOR)
>[  +0,000236] systemd[1]: Detected architecture 'x86-64'.
>[  +0,027276] systemd[1]: Set hostname to <umpuf>.
>[  +2,169628] systemd[1]: Starting Forward Password Requests to Wall Directory Watch.
>[  +0,000116] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
>[  +0,000075] systemd[1]: Expecting device sys-subsystem-net-devices-eth0.device...
>[  +0,000252] systemd[1]: Starting Remote File Systems.
>[  +0,000287] systemd[1]: Reached target Remote File Systems.
>[  +0,000062] systemd[1]: Starting Dispatch Password Requests to Console Directory Watch.
>[  +0,000089] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
>[  +0,000073] systemd[1]: Starting Paths.
>[  +0,000283] systemd[1]: Reached target Paths.
>[  +0,000056] systemd[1]: Starting Encrypted Volumes.
>[  +0,000285] systemd[1]: Reached target Encrypted Volumes.
>[  +0,000066] systemd[1]: Starting Arbitrary Executable File Formats File System Automount Point.
>[  +0,000371] systemd[1]: Set up automount Arbitrary Executable File Formats File System Automount Point.
>[  +0,000079] systemd[1]: Starting Swap.
>[  +0,000283] systemd[1]: Reached target Swap.
>[  +0,000056] systemd[1]: Expecting device dev-sda2.device...
>[  +0,000219] systemd[1]: Starting Root Slice.
>[  +0,007346] systemd[1]: Created slice Root Slice.
>[  +0,000059] systemd[1]: Starting User and Session Slice.
>[  +0,000407] systemd[1]: Created slice User and Session Slice.
>[  +0,000060] systemd[1]: Starting /dev/initctl Compatibility Named Pipe.
>[  +0,000311] systemd[1]: Listening on /dev/initctl Compatibility Named Pipe.
>[  +0,000061] systemd[1]: Starting Device-mapper event daemon FIFOs.
>[  +0,000305] systemd[1]: Listening on Device-mapper event daemon FIFOs.
>[  +0,000059] systemd[1]: Starting Delayed Shutdown Socket.
>[  +0,000304] systemd[1]: Listening on Delayed Shutdown Socket.
>[  +0,000059] systemd[1]: Starting Journal Socket (/dev/log).
>[  +0,000314] systemd[1]: Listening on Journal Socket (/dev/log).
>[  +0,000061] systemd[1]: Starting udev Kernel Socket.
>[  +0,000295] systemd[1]: Listening on udev Kernel Socket.
>[  +0,000059] systemd[1]: Starting udev Control Socket.
>[  +0,000302] systemd[1]: Listening on udev Control Socket.
>[  +0,000058] systemd[1]: Starting LVM2 metadata daemon socket.
>[  +0,000302] systemd[1]: Listening on LVM2 metadata daemon socket.
>[  +0,000060] systemd[1]: Starting Journal Socket.
>[  +0,000302] systemd[1]: Listening on Journal Socket.
>[  +0,000063] systemd[1]: Starting System Slice.
>[  +0,000406] systemd[1]: Created slice System Slice.
>[  +0,000064] systemd[1]: Starting File System Check on Root Device...
>[  +0,000501] systemd[1]: Starting system-dhcpcd.slice.
>[  +0,000438] systemd[1]: Created slice system-dhcpcd.slice.
>[  +0,000062] systemd[1]: Starting system-getty.slice.
>[  +0,000468] systemd[1]: Created slice system-getty.slice.
>[  +0,000067] systemd[1]: Starting Setup Virtual Console...
>[  +0,000497] systemd[1]: Starting udev Coldplug all Devices...
>[  +0,058747] systemd[1]: Starting Load Kernel Modules...
>[  +0,061335] systemd[1]: Starting Create list of required static device nodes for the current kernel...
>[  +0,000565] systemd[1]: Mounting Huge Pages File System...
>[  +0,000509] systemd[1]: Mounting POSIX Message Queue File System...
>[  +0,062745] systemd[1]: Started Set Up Additional Binary Formats.
>[  +0,000079] systemd[1]: Starting Journal Service...
>[  +0,000769] systemd[1]: Started Journal Service.
>[  +1,179517] [drm] Initialized drm 1.1.0 20060810
>[  +0,095088] input: Power Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0C:00/input/input5
>[  +0,000071] ACPI: Power Button [PBTN]
>[  +0,000086] input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input6
>[  +0,000067] ACPI: Power Button [PWRF]
>[  +0,034746] wmi: Mapper loaded
>[  +0,146259] nouveau  [  DEVICE][0000:01:00.0] BOOT0  : 0x0a8180b1
>[  +0,000056] nouveau  [  DEVICE][0000:01:00.0] Chipset: GT218 (NVA8)
>[  +0,000053] nouveau  [  DEVICE][0000:01:00.0] Family : NV50
>[  +0,000083] nouveau  [   VBIOS][0000:01:00.0] checking PRAMIN for image...
>[  +0,069592] nouveau  [   VBIOS][0000:01:00.0] ... appears to be valid
>[  +0,000054] nouveau  [   VBIOS][0000:01:00.0] using image from PRAMIN
>[  +0,000142] nouveau  [   VBIOS][0000:01:00.0] BIT signature found
>[  +0,000054] nouveau  [   VBIOS][0000:01:00.0] version 70.18.5b.00.07
>[  +0,000052] nouveau T[   VBIOS][0000:01:00.0] created
>[  +0,000004] nouveau T[     I2C][0000:01:00.0] inc() == 2
>[  +0,000002] nouveau T[     I2C][0000:01:00.0][0x00000000][ffff880212c663c0] created
>[  +0,000002] nouveau T[     I2C][0000:01:00.0][0x00000000][ffff880212c663c0] inc() == 2
>[  +0,000002] nouveau T[     I2C][0000:01:00.0] inc() == 3
>[  +0,000023] nouveau T[     I2C][0000:01:00.0][0x00000005][ffff8800d683f800] created
>[  +0,000002] nouveau T[     I2C][0000:01:00.0][0x00000000][ffff880212c663c0] dec() == 1
>[  +0,000001] nouveau T[     I2C][0000:01:00.0] inc() == 4
>[  +0,000002] nouveau T[     I2C][0000:01:00.0][0x00000000][ffff880212c66380] created
>[  +0,000002] nouveau T[     I2C][0000:01:00.0][0x00000000][ffff880212c66380] inc() == 2
>[  +0,000001] nouveau T[     I2C][0000:01:00.0] inc() == 5
>[  +0,000017] nouveau T[     I2C][0000:01:00.0][0x00000005][ffff8800d6838800] created
>[  +0,000002] nouveau T[     I2C][0000:01:00.0][0x00000000][ffff880212c66380] dec() == 1
>[  +0,000002] nouveau T[     I2C][0000:01:00.0] inc() == 6
>[  +0,000001] nouveau T[     I2C][0000:01:00.0][0x00000000][ffff880212c66280] created
>[  +0,000002] nouveau T[     I2C][0000:01:00.0][0x00000000][ffff880212c66280] inc() == 2
>[  +0,000001] nouveau T[     I2C][0000:01:00.0] inc() == 7
>[  +0,000015] nouveau T[     I2C][0000:01:00.0][0x00000005][ffff880213217800] created
>[  +0,000002] nouveau T[     I2C][0000:01:00.0][0x00000000][ffff880212c66280] dec() == 1
>[  +0,000002] nouveau T[     I2C][0000:01:00.0] inc() == 8
>[  +0,000001] nouveau T[     I2C][0000:01:00.0][0x00000000][ffff880212c66240] created
>[  +0,000002] nouveau T[     I2C][0000:01:00.0][0x00000000][ffff880212c66240] inc() == 2
>[  +0,000001] nouveau T[     I2C][0000:01:00.0] inc() == 9
>[  +0,000016] nouveau T[     I2C][0000:01:00.0][0x00000005][ffff880213210800] created
>[  +0,000002] nouveau T[     I2C][0000:01:00.0][0x00000000][ffff880212c66240] dec() == 1
>[  +0,000002] nouveau T[     I2C][0000:01:00.0] inc() == 10
>[  +0,000001] nouveau T[     I2C][0000:01:00.0][0x00000000][ffff880212c66200] created
>[  +0,000002] nouveau T[     I2C][0000:01:00.0][0x00000000][ffff880212c66200] inc() == 2
>[  +0,000001] nouveau T[     I2C][0000:01:00.0] inc() == 11
>[  +0,000015] nouveau T[     I2C][0000:01:00.0][0x00000005][ffff880213216800] created
>[  +0,000002] nouveau T[     I2C][0000:01:00.0][0x00000000][ffff880212c66200] dec() == 1
>[  +0,000001] nouveau T[     I2C][0000:01:00.0] inc() == 12
>[  +0,000002] nouveau T[     I2C][0000:01:00.0][0x00000000][ffff880212c66100] created
>[  +0,000002] nouveau T[     I2C][0000:01:00.0][0x00000000][ffff880212c66100] inc() == 2
>[  +0,000001] nouveau T[     I2C][0000:01:00.0] inc() == 13
>[  +0,000016] nouveau T[     I2C][0000:01:00.0][0x00000005][ffff880213215000] created
>[  +0,000002] nouveau T[     I2C][0000:01:00.0][0x00000000][ffff880212c66100] dec() == 1
>[  +0,000001] nouveau T[     I2C][0000:01:00.0] inc() == 14
>[  +0,000002] nouveau T[     I2C][0000:01:00.0][0x00000000][ffff880212c660c0] created
>[  +0,000002] nouveau T[     I2C][0000:01:00.0][0x00000000][ffff880212c660c0] inc() == 2
>[  +0,000001] nouveau T[     I2C][0000:01:00.0] inc() == 15
>[  +0,000016] nouveau T[     I2C][0000:01:00.0][0x00000005][ffff880213215800] created
>[  +0,000002] nouveau T[     I2C][0000:01:00.0][0x00000000][ffff880212c660c0] dec() == 1
>[  +0,000001] nouveau T[     I2C][0000:01:00.0] inc() == 16
>[  +0,000002] nouveau T[     I2C][0000:01:00.0][0x00000000][ffff880212c66080] created
>[  +0,000002] nouveau T[     I2C][0000:01:00.0][0x00000000][ffff880212c66080] inc() == 2
>[  +0,000001] nouveau T[     I2C][0000:01:00.0] inc() == 17
>[  +0,000018] nouveau T[     I2C][0000:01:00.0][0x00000005][ffff880213214000] created
>[  +0,000002] nouveau T[     I2C][0000:01:00.0][0x00000000][ffff880212c66080] dec() == 1
>[  +0,000002] nouveau T[     I2C][0000:01:00.0][0x00000000][ffff880212c66200] inc() == 3
>[  +0,000001] nouveau T[     I2C][0000:01:00.0] inc() == 18
>[  +0,000016] nouveau T[     I2C][0000:01:00.0][0x00000006][ffff880213216000] created
>[  +0,000002] nouveau T[     I2C][0000:01:00.0][0x00000000][ffff880212c66200] dec() == 2
>[  +0,000002] nouveau T[     I2C][0000:01:00.0][0x00000000][ffff880212c66100] inc() == 3
>[  +0,000002] nouveau T[     I2C][0000:01:00.0] inc() == 19
>[  +0,000016] nouveau T[     I2C][0000:01:00.0][0x00000006][ffff880213214800] created
>[  +0,000002] nouveau T[     I2C][0000:01:00.0][0x00000000][ffff880212c66100] dec() == 2
>[  +0,000002] nouveau T[     I2C][0000:01:00.0][0x00000000][ffff880212c660c0] inc() == 3
>[  +0,000001] nouveau T[     I2C][0000:01:00.0] inc() == 20
>[  +0,000017] nouveau T[     I2C][0000:01:00.0][0x00000006][ffff880213217000] created
>[  +0,000002] nouveau T[     I2C][0000:01:00.0][0x00000000][ffff880212c660c0] dec() == 2
>[  +0,000002] nouveau T[     I2C][0000:01:00.0][0x00000000][ffff880212c66080] inc() == 3
>[  +0,000001] nouveau T[     I2C][0000:01:00.0] inc() == 21
>[  +0,000015] nouveau T[     I2C][0000:01:00.0][0x00000006][ffff880213212000] created
>[  +0,000002] nouveau T[     I2C][0000:01:00.0][0x00000000][ffff880212c66080] dec() == 2
>[  +0,000002] nouveau T[     I2C][0000:01:00.0] created
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] use(+1) == 1
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] initialising...
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] resetting...
>[  +0,000001] nouveau D[   VBIOS][0000:01:00.0] reset
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] initialised
>[  +0,000005] nouveau T[   VBIOS][0000:01:00.0] 0xd9c1[ ]: RESERVED 0x8c	
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xd9c2[ ]: NV_REG	R[0x022210] &= 0xfffffffe |= 0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xd9cf[ ]: ZM_REG	R[0x000200] = 0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xd9d8[ ]: REPEAT	0x14
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xd9da[ ]: NV_REG	R[0x000000] &= 0xffffffff |= 0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xd9e7[ ]: END_REPEAT
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x13
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xd9da[ ]: NV_REG	R[0x000000] &= 0xffffffff |= 0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xd9e7[ ]: END_REPEAT
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x12
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xd9da[ ]: NV_REG	R[0x000000] &= 0xffffffff |= 0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xd9e7[ ]: END_REPEAT
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x11
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xd9da[ ]: NV_REG	R[0x000000] &= 0xffffffff |= 0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xd9e7[ ]: END_REPEAT
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x10
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xd9da[ ]: NV_REG	R[0x000000] &= 0xffffffff |= 0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xd9e7[ ]: END_REPEAT
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x0f
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xd9da[ ]: NV_REG	R[0x000000] &= 0xffffffff |= 0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xd9e7[ ]: END_REPEAT
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x0e
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xd9da[ ]: NV_REG	R[0x000000] &= 0xffffffff |= 0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xd9e7[ ]: END_REPEAT
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x0d
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xd9da[ ]: NV_REG	R[0x000000] &= 0xffffffff |= 0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xd9e7[ ]: END_REPEAT
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x0c
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xd9da[ ]: NV_REG	R[0x000000] &= 0xffffffff |= 0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xd9e7[ ]: END_REPEAT
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x0b
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xd9da[ ]: NV_REG	R[0x000000] &= 0xffffffff |= 0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xd9e7[ ]: END_REPEAT
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x0a
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xd9da[ ]: NV_REG	R[0x000000] &= 0xffffffff |= 0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xd9e7[ ]: END_REPEAT
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x09
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xd9da[ ]: NV_REG	R[0x000000] &= 0xffffffff |= 0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xd9e7[ ]: END_REPEAT
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x08
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xd9da[ ]: NV_REG	R[0x000000] &= 0xffffffff |= 0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xd9e7[ ]: END_REPEAT
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x07
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xd9da[ ]: NV_REG	R[0x000000] &= 0xffffffff |= 0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xd9e7[ ]: END_REPEAT
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x06
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xd9da[ ]: NV_REG	R[0x000000] &= 0xffffffff |= 0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xd9e7[ ]: END_REPEAT
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x05
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xd9da[ ]: NV_REG	R[0x000000] &= 0xffffffff |= 0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xd9e7[ ]: END_REPEAT
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x04
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xd9da[ ]: NV_REG	R[0x000000] &= 0xffffffff |= 0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xd9e7[ ]: END_REPEAT
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x03
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xd9da[ ]: NV_REG	R[0x000000] &= 0xffffffff |= 0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xd9e7[ ]: END_REPEAT
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x02
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xd9da[ ]: NV_REG	R[0x000000] &= 0xffffffff |= 0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xd9e7[ ]: END_REPEAT
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x01
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xd9da[ ]: NV_REG	R[0x000000] &= 0xffffffff |= 0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xd9e7[ ]: END_REPEAT
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xd9e8[ ]: NV_REG	R[0x001084] &= 0xfffff7ff |= 0x00000800
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xd9f5[ ]: ZM_REG	R[0x001540] = 0xf3010001
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xd9fe[ ]: INIT_XLAT	R[0x001540] &= 0xff00ffff |= (X00((R[0x001540] >> 0x10) & 0x01) << 0x10)
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xda0f[ ]: CONDITION	0x12
>[  +0,000003] nouveau T[   VBIOS][0000:01:00.0] 0xda11[ ]: 	[0x12] (R[0x02128c] & 0x00000007) == 0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xda11[ ]: NV_REG	R[0x001540] &= 0xffffffff |= 0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xda1e[ ]: RESUME
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xda1f[ ]: NV_REG	R[0x001540] &= 0xffffffff |= 0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xda2c[ ]: NV_REG	R[0x00c040] &= 0xcfffefff |= 0x20001000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xda39[ ]: ZM_REG	R[0x000200] = 0xdff3f113
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xda42[ ]: NV_REG	R[0x022210] &= 0xfffffffe |= 0x00000001
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xda4f[ ]: RESERVED 0x8d	
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xda50[ ]: SUB_DIRECT	0xd861
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xda53[ ]: NV_REG	R[0x00e108] &= 0xfffffff7 |= 0x00000008
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xda60[ ]: NV_REG	R[0x00e300] &= 0xffffffff |= 0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xda6d[ ]: ZM_REG_SEQUENCE	0x02
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xda73[ ]: 		R[0x020480] = 0x0000006d
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xda77[ ]: 		R[0x020484] = 0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xda7b[ ]: ZM_REG	R[0x0204c0] = 0x00000068
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xda84[ ]: ZM_REG	R[0x0204d8] = 0x00000069
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xda8d[ ]: ZM_REG	R[0x0204e0] = 0x00000066
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xda96[ ]: ZM_REG	R[0x02041c] = 0x00000055
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xda9f[ ]: ZM_REG_SEQUENCE	0x06
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdaa5[ ]: 		R[0x02010c] = 0x00000049
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdaa9[ ]: 		R[0x020110] = 0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdaad[ ]: 		R[0x020114] = 0x00b46600
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdab1[ ]: 		R[0x020118] = 0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdab5[ ]: 		R[0x02011c] = 0x00765481
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdab9[ ]: 		R[0x020120] = 0x00000241
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdabd[ ]: ZM_REG_SEQUENCE	0x02
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdac3[ ]: 		R[0x020074] = 0x00000014
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdac7[ ]: 		R[0x020078] = 0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdacb[ ]: ZM_REG_SEQUENCE	0x02
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdad1[ ]: 		R[0x020094] = 0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdad5[ ]: 		R[0x020098] = 0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdad9[ ]: NV_REG	R[0x00e1f4] &= 0xffffffff |= 0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdae6[ ]: ZM_REG	R[0x02004c] = 0x4407220b
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdaef[ ]: ZM_REG	R[0x020424] = 0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdaf8[ ]: GPIO
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdaf9[ ]: ZM_REG	R[0x00e11c] = 0x00000001
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdb02[ ]: ZM_REG	R[0x00e120] = 0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdb0b[ ]: NV_REG	R[0x00e100] &= 0xffffffff |= 0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdb18[ ]: ZM_REG	R[0x020004] = 0x00100028
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdb21[ ]: CONDITION	0x10
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdb23[ ]: 	[0x10] (R[0x101000] & 0x001c0000) == 0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdb23[ ]: ZM_REG	R[0x089014] = 0x0000e020
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdb2c[ ]: ZM_REG	R[0x089018] = 0x2140ed20
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdb35[ ]: NOT
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdb36[ ]: ZM_REG	R[0x089014] = 0x0000000c
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdb3f[ ]: ZM_REG	R[0x089018] = 0x20e0e014
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdb48[ ]: RESUME
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdb49[ ]: NV_REG	R[0x08818c] &= 0x0ffffffe |= 0xe0000001
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdb56[ ]: NV_REG	R[0x08907c] &= 0xffff0000 |= 0x00000f0f
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdb63[ ]: ZM_REG	R[0x08848c] = 0x0118008c
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdb6c[ ]: NV_REG	R[0x08845c] &= 0x6fffffff |= 0x90000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdb79[ ]: NV_REG	R[0x088158] &= 0xfffffbff |= 0x00000400
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdb86[ ]: NV_REG	R[0x08813c] &= 0x0fffffff |= 0x60000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdb93[ ]: NV_REG	R[0x088150] &= 0xffffffff |= 0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdba0[ ]: NV_REG	R[0x088088] &= 0xfffffffc |= 0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdbad[ ]: NV_REG	R[0x08a088] &= 0xfffffffc |= 0x00000003
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdbba[ ]: ZM_REG	R[0x089008] = 0x00004810
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdbc3[ ]: NV_REG	R[0x088610] &= 0xfffffffe |= 0x00000001
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdbd0[ ]: NV_REG	R[0x001530] &= 0xffe1f0ff |= 0x00180c00
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdbdd[ ]: ZM_REG	R[0x009220] = 0x00000412
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdbe6[ ]: ZM_REG	R[0x009200] = 0x00000804
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdbef[ ]: ZM_REG	R[0x009210] = 0x00000271
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdbf8[ ]: NV_REG	R[0x101000] &= 0xffffffff |= 0x80000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdc05[ ]: NV_REG	R[0x10100c] &= 0xffffffff |= 0x80000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdc12[ ]: SUB_DIRECT	0xd8f9
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdc15[ ]: ZM_REG	R[0x00e18c] = 0x00010000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdc1e[ ]: NV_REG	R[0x00e820] &= 0xffffffed |= 0x00000010
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdc2b[ ]: NV_REG	R[0x00e8a0] &= 0xffffffed |= 0x00000010
>[  +0,000069] nouveau T[   VBIOS][0000:01:00.0] 0xdc38[ ]: NV_REG	R[0x004220] &= 0xffffffed |= 0x00000010
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdc45[ ]: TIME	0x000a
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdc48[ ]: CONDITION_TIME	0x05 0xff
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdc4b[ ]: RESUME
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdc4c[ ]: CONDITION_TIME	0x07 0xff
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdc4f[ ]: RESUME
>[  +0,000004] nouveau T[   VBIOS][0000:01:00.0] 0xdc50[ ]: NV_REG	R[0x00e820] &= 0xffffffee |= 0x00000001
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdc5d[ ]: NV_REG	R[0x00e8a0] &= 0xffffffee |= 0x00000001
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdc6a[ ]: ZM_REG	R[0x00e830] = 0x80291301
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdc73[ ]: ZM_REG	R[0x00e8b0] = 0x80191f01
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdc7c[ ]: ZM_REG	R[0x004700] = 0x80000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdc85[ ]: ZM_REG	R[0x004018] = 0x1000d000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdc8e[ ]: CONDITION_TIME	0x06 0xff
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdc91[ ]: RESUME
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdc92[ ]: CONDITION_TIME	0x08 0xff
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdc95[ ]: RESUME
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdc96[ ]: NV_REG	R[0x00e820] &= 0xfffffffb |= 0x00000004
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdca3[ ]: NV_REG	R[0x00e8a0] &= 0xfffffffb |= 0x00000004
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdcb0[ ]: NV_REG	R[0x00e820] &= 0xffffffe7 |= 0x00000010
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdcbd[ ]: NV_REG	R[0x00e8a0] &= 0xffffffe7 |= 0x00000010
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdcca[ ]: NV_REG	R[0x00e82c] &= 0xfffffff7 |= 0x00000000
>[  +0,000003] nouveau T[   VBIOS][0000:01:00.0] 0xdcd7[ ]: NV_REG	R[0x00e830] &= 0x7fffffff |= 0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdce4[ ]: NV_REG	R[0x00e82c] &= 0xfffffffb |= 0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdcf1[ ]: NV_REG	R[0x00e8ac] &= 0xfffffff7 |= 0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdcfe[ ]: NV_REG	R[0x00e8b0] &= 0x7fffffff |= 0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdd0b[ ]: NV_REG	R[0x00e8ac] &= 0xfffffffb |= 0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdd18[ ]: ZM_REG	R[0x004198] = 0x001c0131
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdd21[ ]: ZM_REG	R[0x004190] = 0x001c0131
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdd2a[ ]: SUB_DIRECT	0xd943
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdd2d[ ]: ZM_REG	R[0x004164] = 0x00020131
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdd36[ ]: ZM_REG	R[0x004160] = 0x00060131
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdd3f[ ]: ZM_REG	R[0x004168] = 0x00060121
>[  +0,000003] nouveau T[   VBIOS][0000:01:00.0] 0xdd48[ ]: SUB_DIRECT	0xd94d
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdd4b[ ]: ZM_REG	R[0x0041b4] = 0x000e0131
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdd54[ ]: SUB_DIRECT	0xd969
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdd57[ ]: NV_REG	R[0x004198] &= 0xffffcfff |= 0x00003000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdd64[ ]: NV_REG	R[0x004190] &= 0xffffcfff |= 0x00003000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdd71[ ]: SUB_DIRECT	0xd973
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdd74[ ]: NV_REG	R[0x004164] &= 0xffffceff |= 0x00003100
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdd81[ ]: NV_REG	R[0x004160] &= 0xffffceff |= 0x00003100
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdd8e[ ]: NV_REG	R[0x004168] &= 0xffffceff |= 0x00003100
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdd9b[ ]: SUB_DIRECT	0xd981
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdd9e[ ]: NV_REG	R[0x0041b4] &= 0xffffcfff |= 0x00003000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xddab[ ]: SUB_DIRECT	0xd98f
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xddae[ ]: NV_REG	R[0x004200] &= 0xfffffff7 |= 0x00000008
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xddbb[ ]: NV_REG	R[0x004220] &= 0xfffffff7 |= 0x00000008
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xddc8[ ]: NV_REG	R[0x004000] &= 0xfffffff7 |= 0x00000008
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xddd5[ ]: ZM_REG	R[0x004120] = 0x00063031
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xddde[ ]: ZM_REG	R[0x004124] = 0x00063031
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdde7[ ]: ZM_REG	R[0x004128] = 0x00063021
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xddf0[ ]: ZM_REG	R[0x004140] = 0x001c0100
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xddf9[ ]: ZM_REG	R[0x004144] = 0x001c0100
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xde02[ ]: SUB_DIRECT	0xd930
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xde05[ ]: SUB_DIRECT	0xde1b
>[  +0,000003] nouveau T[   VBIOS][0000:01:00.0] 0xde08[ ]: ZM_REG	R[0x00c044] = 0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xde11[ ]: ZM_REG	R[0x001538] = 0x00011111
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xde1a[ ]: DONE
>[  +0,000003] nouveau T[   VBIOS][0000:01:00.0] 0xde6c[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x00100710] 0x04 0x01
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xde73[ ]: 	R[0x100710] = {
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xde73[ ]: 		0x00000080
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xde77[ ]: 		0x00000080 *
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xde7b[ ]: 		0x00000080
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xde7f[ ]: 		0x00000080
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xde83[ ]: 		0x00000080
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xde87[ ]: 		0x00000080
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xde8b[ ]: 		0x00000080
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xde8f[ ]: 		0x00000080
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xde93[ ]: 	}
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xde93[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x00100718] 0x04 0x02
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xde9a[ ]: 	R[0x100718] = {
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xde9a[ ]: 		0x40044e77
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xde9e[ ]: 		0x40055f77 *
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdea2[ ]: 		0x40055f77
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdea6[ ]: 		0x40044f77
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdeaa[ ]: 		0x40044e77
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdeae[ ]: 		0x40044e77
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdeb2[ ]: 		0x40044f77
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdeb6[ ]: 		0x40044e77
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdeba[ ]: 	}
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdeba[ ]: 	R[0x10071c] = {
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdeba[ ]: 		0x40044e77
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdebe[ ]: 		0x40044f77 *
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdec2[ ]: 		0x40044f77
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdec6[ ]: 		0x40044f77
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdeca[ ]: 		0x40044e77
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdece[ ]: 		0x40044e77
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xded2[ ]: 		0x40044f77
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xded6[ ]: 		0x40044e77
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdeda[ ]: 	}
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdeda[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x00111140] 0x04 0x01
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdee1[ ]: 	R[0x111140] = {
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdee1[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdee5[ ]: 		0x00000000 *
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdee9[ ]: 		0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdeed[ ]: 		0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdef1[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdef5[ ]: 		0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdef9[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdefd[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdf01[ ]: 	}
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdf01[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x00100720] 0x04 0x01
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdf08[ ]: 	R[0x100720] = {
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdf08[ ]: 		0xcccccccc
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdf0c[ ]: 		0x8bba5555 *
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdf10[ ]: 		0xaaaa4444
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdf14[ ]: 		0x8bba5555
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdf18[ ]: 		0xcccccccc
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdf1c[ ]: 		0xcccccccc
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdf20[ ]: 		0x8bba5555
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdf24[ ]: 		0xcccccccc
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdf28[ ]: 	}
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdf28[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x00111120] 0x04 0x01
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdf2f[ ]: 	R[0x111120] = {
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdf2f[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdf33[ ]: 		0x00000000 *
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdf37[ ]: 		0x00000000
>[  +0,000003] nouveau T[   VBIOS][0000:01:00.0] 0xdf3b[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdf3f[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdf43[ ]: 		0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdf47[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdf4b[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdf4f[ ]: 	}
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdf4f[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x00111380] 0x04 0x01
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdf56[ ]: 	R[0x111380] = {
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdf56[ ]: 		0x80000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdf5a[ ]: 		0x80000404 *
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdf5e[ ]: 		0x80000a0a
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdf62[ ]: 		0x80000404
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdf66[ ]: 		0x80000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdf6a[ ]: 		0x80000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdf6e[ ]: 		0x80000404
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdf72[ ]: 		0x80000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdf76[ ]: 	}
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdf76[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x001008a0] 0x04 0x01
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdf7d[ ]: 	R[0x1008a0] = {
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdf7d[ ]: 		0x87000cce
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdf81[ ]: 		0x87001c7d *
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdf85[ ]: 		0x87003e9f
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdf89[ ]: 		0x87001c9d
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdf8d[ ]: 		0x87000cce
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdf91[ ]: 		0x87000cce
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdf95[ ]: 		0x87001c9d
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdf99[ ]: 		0x87000cce
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdf9d[ ]: 	}
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdf9d[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x00111180] 0x04 0x01
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdfa4[ ]: 	R[0x111180] = {
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdfa4[ ]: 		0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdfa8[ ]: 		0x77777777 *
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdfac[ ]: 		0x77777777
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdfb0[ ]: 		0x77777777
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdfb4[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdfb8[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdfbc[ ]: 		0x77777777
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdfc0[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdfc4[ ]: 	}
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdfc4[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x00111000] 0x04 0x01
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdfcb[ ]: 	R[0x111000] = {
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdfcb[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdfcf[ ]: 		0x77777777 *
>[  +0,000003] nouveau T[   VBIOS][0000:01:00.0] 0xdfd3[ ]: 		0x77777777
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdfd7[ ]: 		0x77777777
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdfdb[ ]: 		0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdfdf[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdfe3[ ]: 		0x77777777
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdfe7[ ]: 		0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdfeb[ ]: 	}
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdfeb[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x00100d80] 0x04 0x01
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdff2[ ]: 	R[0x100d80] = {
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdff2[ ]: 		0xaaaaaaaa
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdff6[ ]: 		0xaaaaaaaa *
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xdffa[ ]: 		0xaaaaaaaa
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xdffe[ ]: 		0xaaaaaaaa
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe002[ ]: 		0xaaaaaaaa
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe006[ ]: 		0xaaaaaaaa
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe00a[ ]: 		0xaaaaaaaa
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe00e[ ]: 		0xaaaaaaaa
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe012[ ]: 	}
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe012[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x001009dc] 0x04 0x01
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe019[ ]: 	R[0x1009dc] = {
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe019[ ]: 		0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe01d[ ]: 		0x00000000 *
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe021[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe025[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe029[ ]: 		0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe02d[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe031[ ]: 		0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe035[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe039[ ]: 	}
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe039[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x001009e4] 0x04 0x01
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe040[ ]: 	R[0x1009e4] = {
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe040[ ]: 		0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe044[ ]: 		0x00000000 *
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe048[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe04c[ ]: 		0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe050[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe054[ ]: 		0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe058[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe05c[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe060[ ]: 	}
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe060[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x00100900] 0x04 0x01
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe067[ ]: 	R[0x100900] = {
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe067[ ]: 		0x0f0f0f0f
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe06b[ ]: 		0x0f0f0f0f *
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe06f[ ]: 		0x0f0f0f0f
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe073[ ]: 		0x0f0f0f0f
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe077[ ]: 		0x0f0f0f0f
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe07b[ ]: 		0x0f0f0f0f
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe07f[ ]: 		0x0f0f0f0f
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe083[ ]: 		0x0f0f0f0f
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe087[ ]: 	}
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe087[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x00100920] 0x04 0x01
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe08e[ ]: 	R[0x100920] = {
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe08e[ ]: 		0x0f0f0f0f
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe092[ ]: 		0x0f0f0f0f *
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe096[ ]: 		0x0f0f0f0f
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe09a[ ]: 		0x0f0f0f0f
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe09e[ ]: 		0x0f0f0f0f
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe0a2[ ]: 		0x0f0f0f0f
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe0a6[ ]: 		0x0f0f0f0f
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe0aa[ ]: 		0x0f0f0f0f
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe0ae[ ]: 	}
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe0ae[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x00100940] 0x04 0x01
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe0b5[ ]: 	R[0x100940] = {
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe0b5[ ]: 		0x0f0f0000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe0b9[ ]: 		0x0f0f0000 *
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe0bd[ ]: 		0x80800000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe0c1[ ]: 		0x90900000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe0c5[ ]: 		0x0f0f0000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe0c9[ ]: 		0x0f0f0000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe0cd[ ]: 		0x90900000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe0d1[ ]: 		0x0f0f0000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe0d5[ ]: 	}
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe0d5[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x00100a20] 0x04 0x01
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe0dc[ ]: 	R[0x100a20] = {
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe0dc[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe0e0[ ]: 		0x00000000 *
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe0e4[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe0e8[ ]: 		0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe0ec[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe0f0[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe0f4[ ]: 		0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe0f8[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe0fc[ ]: 	}
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe0fc[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x00100a40] 0x04 0x01
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe103[ ]: 	R[0x100a40] = {
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe103[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe107[ ]: 		0x00000000 *
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe10b[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe10f[ ]: 		0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe113[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe117[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe11b[ ]: 		0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe11f[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe123[ ]: 	}
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe123[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x00100a60] 0x04 0x01
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe12a[ ]: 	R[0x100a60] = {
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe12a[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe12e[ ]: 		0x00000000 *
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe132[ ]: 		0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe136[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe13a[ ]: 		0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe13e[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe142[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe146[ ]: 		0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe14a[ ]: 	}
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe14a[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x00100a80] 0x04 0x01
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe151[ ]: 	R[0x100a80] = {
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe151[ ]: 		0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe155[ ]: 		0x00000000 *
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe159[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe15d[ ]: 		0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe161[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe165[ ]: 		0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe169[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe16d[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe171[ ]: 	}
>[  +0,000003] nouveau T[   VBIOS][0000:01:00.0] 0xe171[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x00100aa0] 0x04 0x01
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe178[ ]: 	R[0x100aa0] = {
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe178[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe17c[ ]: 		0x00000000 *
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe180[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe184[ ]: 		0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe188[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe18c[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe190[ ]: 		0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe194[ ]: 		0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe198[ ]: 	}
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe198[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x00100ac0] 0x04 0x01
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe19f[ ]: 	R[0x100ac0] = {
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe19f[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe1a3[ ]: 		0x00000000 *
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe1a7[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe1ab[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe1af[ ]: 		0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe1b3[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe1b7[ ]: 		0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe1bb[ ]: 		0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe1bf[ ]: 	}
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe1bf[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x00111400] 0x20 0x06
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe1c6[ ]: 	R[0x111400] = {
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe1c6[ ]: 		0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe1ca[ ]: 		0x00000000 *
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe1ce[ ]: 		0x000f0f00
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe1d2[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe1d6[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe1da[ ]: 		0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe1de[ ]: 		0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe1e2[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe1e6[ ]: 	}
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe1e6[ ]: 	R[0x111420] = {
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe1e6[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe1ea[ ]: 		0x00000000 *
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe1ee[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe1f2[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe1f6[ ]: 		0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe1fa[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe1fe[ ]: 		0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe202[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe206[ ]: 	}
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe206[ ]: 	R[0x111440] = {
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe206[ ]: 		0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe20a[ ]: 		0x00000000 *
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe20e[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe212[ ]: 		0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe216[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe21a[ ]: 		0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe21e[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe222[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe226[ ]: 	}
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe226[ ]: 	R[0x111460] = {
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe226[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe22a[ ]: 		0x00000000 *
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe22e[ ]: 		0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe232[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe236[ ]: 		0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe23a[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe23e[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe242[ ]: 		0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe246[ ]: 	}
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe246[ ]: 	R[0x111480] = {
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe246[ ]: 		0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe24a[ ]: 		0x00000000 *
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe24e[ ]: 		0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe252[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe256[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe25a[ ]: 		0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe25e[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe262[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe266[ ]: 	}
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe266[ ]: 	R[0x1114a0] = {
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe266[ ]: 		0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe26a[ ]: 		0x00000000 *
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe26e[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe272[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe276[ ]: 		0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe27a[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe27e[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe282[ ]: 		0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe286[ ]: 	}
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe286[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x00100dc0] 0x04 0x01
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe28d[ ]: 	R[0x100dc0] = {
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe28d[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe291[ ]: 		0x00000000 *
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe295[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe299[ ]: 		0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe29d[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe2a1[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe2a5[ ]: 		0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe2a9[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe2ad[ ]: 	}
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe2ad[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x001005a0] 0x04 0x02
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe2b4[ ]: 	R[0x1005a0] = {
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe2b4[ ]: 		0x008f8f8f
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe2b8[ ]: 		0x008c8a8a *
>[  +0,000003] nouveau T[   VBIOS][0000:01:00.0] 0xe2bc[ ]: 		0x00aa3737
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe2c0[ ]: 		0x008c8a8a
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe2c4[ ]: 		0x008f8f8f
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe2c8[ ]: 		0x008f8f8f
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe2cc[ ]: 		0x008c8a8a
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe2d0[ ]: 		0x008f8f8f
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe2d4[ ]: 	}
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe2d4[ ]: 	R[0x1005a4] = {
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe2d4[ ]: 		0x00001010
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe2d8[ ]: 		0x00001111 *
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe2dc[ ]: 		0x00001010
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe2e0[ ]: 		0x00001111
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe2e4[ ]: 		0x00001010
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe2e8[ ]: 		0x00001010
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe2ec[ ]: 		0x00001111
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe2f0[ ]: 		0x00001010
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe2f4[ ]: 	}
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe2f4[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x0010f804] 0x04 0x01
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe2fb[ ]: 	R[0x10f804] = {
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe2fb[ ]: 		0x00020003
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe2ff[ ]: 		0x00000004 *
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe303[ ]: 		0x00f00004
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe307[ ]: 		0x00000004
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe30b[ ]: 		0x00020003
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe30f[ ]: 		0x00020003
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe313[ ]: 		0x00000004
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe317[ ]: 		0x00020003
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe31b[ ]: 	}
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe31b[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x0010053c] 0x04 0x01
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe322[ ]: 	R[0x10053c] = {
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe322[ ]: 		0x00001000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe326[ ]: 		0x00001000 *
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe32a[ ]: 		0x00001000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe32e[ ]: 		0x00001000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe332[ ]: 		0x00001000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe336[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe33a[ ]: 		0x00001000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe33e[ ]: 		0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe342[ ]: 	}
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe342[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x00100760] 0x04 0x01
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe349[ ]: 	R[0x100760] = {
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe349[ ]: 		0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe34d[ ]: 		0x22222222 *
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe351[ ]: 		0x33333333
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe355[ ]: 		0x22222222
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe359[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe35d[ ]: 		0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe361[ ]: 		0x22222222
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe365[ ]: 		0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe369[ ]: 	}
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe369[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x00100780] 0x04 0x01
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe370[ ]: 	R[0x100780] = {
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe370[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe374[ ]: 		0xdddddcde *
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe378[ ]: 		0x33333333
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe37c[ ]: 		0xdddddcde
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe380[ ]: 		0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe384[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe388[ ]: 		0xdddddcde
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe38c[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe390[ ]: 	}
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe390[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x001007a0] 0x04 0x01
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe397[ ]: 	R[0x1007a0] = {
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe397[ ]: 		0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe39b[ ]: 		0x33333333 *
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe39f[ ]: 		0x33333333
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe3a3[ ]: 		0x33333333
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe3a7[ ]: 		0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe3ab[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe3af[ ]: 		0x33333333
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe3b3[ ]: 		0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe3b7[ ]: 	}
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe3b7[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x001007c0] 0x04 0x01
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe3be[ ]: 	R[0x1007c0] = {
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe3be[ ]: 		0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe3c2[ ]: 		0xffffffff *
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe3c6[ ]: 		0x33333333
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe3ca[ ]: 		0xffffffff
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe3ce[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe3d2[ ]: 		0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe3d6[ ]: 		0xffffffff
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe3da[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe3de[ ]: 	}
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe3de[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x001007e0] 0x04 0x01
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe3e5[ ]: 	R[0x1007e0] = {
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe3e5[ ]: 		0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe3e9[ ]: 		0x22222222 *
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe3ed[ ]: 		0x22222222
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe3f1[ ]: 		0x22222222
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe3f5[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe3f9[ ]: 		0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe3fd[ ]: 		0x22222222
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe401[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe405[ ]: 	}
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe405[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x00100800] 0x04 0x01
>[  +0,000003] nouveau T[   VBIOS][0000:01:00.0] 0xe40c[ ]: 	R[0x100800] = {
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe40c[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe410[ ]: 		0xdddddddd *
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe414[ ]: 		0xaaaaaaaa
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe418[ ]: 		0xdddddddd
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe41c[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe420[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe424[ ]: 		0xdddddddd
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe428[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe42c[ ]: 	}
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe42c[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x00100820] 0x04 0x01
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe433[ ]: 	R[0x100820] = {
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe433[ ]: 		0x11111111
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe437[ ]: 		0x00000000 *
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe43b[ ]: 		0x11111111
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe43f[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe443[ ]: 		0x11111111
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe447[ ]: 		0x11111111
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe44b[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe44f[ ]: 		0x11111111
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe453[ ]: 	}
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe453[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x00100840] 0x04 0x01
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe45a[ ]: 	R[0x100840] = {
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe45a[ ]: 		0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe45e[ ]: 		0xbbbbbbbb *
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe462[ ]: 		0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe466[ ]: 		0xbbbbbbbb
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe46a[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe46e[ ]: 		0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe472[ ]: 		0xbbbbbbbb
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe476[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe47a[ ]: 	}
>[  +0,000003] nouveau T[   VBIOS][0000:01:00.0] 0xe47a[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x00100860] 0x04 0x01
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe481[ ]: 	R[0x100860] = {
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe481[ ]: 		0x11111111
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe485[ ]: 		0x11111111 *
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe489[ ]: 		0x11111111
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe48d[ ]: 		0x11111111
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe491[ ]: 		0x11111111
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe495[ ]: 		0x11111111
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe499[ ]: 		0x11111111
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe49d[ ]: 		0x11111111
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe4a1[ ]: 	}
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe4a1[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x00100880] 0x04 0x01
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe4a8[ ]: 	R[0x100880] = {
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe4a8[ ]: 		0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe4ac[ ]: 		0x00000000 *
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe4b0[ ]: 		0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe4b4[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe4b8[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe4bc[ ]: 		0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe4c0[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe4c4[ ]: 		0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe4c8[ ]: 	}
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe4c8[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x00100714] 0x04 0x01
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe4cf[ ]: 	R[0x100714] = {
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe4cf[ ]: 		0x00000011
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe4d3[ ]: 		0xf0000001 *
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe4d7[ ]: 		0xf0000001
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe4db[ ]: 		0xf0000001
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe4df[ ]: 		0x00000011
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe4e3[ ]: 		0x00000011
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe4e7[ ]: 		0xf0000001
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe4eb[ ]: 		0x00000011
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe4ef[ ]: 	}
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe4ef[ ]: ZM_REG	R[0x100700] = 0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe4f8[ ]: ZM_REG	R[0x100740] = 0x06000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe501[ ]: ZM_REG	R[0x100da0] = 0x00000010
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe50a[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x00111104] 0x04 0x01
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe511[ ]: 	R[0x111104] = {
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe511[ ]: 		0x00000e7f
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe515[ ]: 		0x000009ff *
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe519[ ]: 		0x00000e7f
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe51d[ ]: 		0x000009ff
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe521[ ]: 		0x00000e7f
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe525[ ]: 		0x00000e7f
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe529[ ]: 		0x000009ff
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe52d[ ]: 		0x00000e7f
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe531[ ]: 	}
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe531[ ]: ZM_REG	R[0x1110c0] = 0x00001801
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe53a[ ]: ZM_REG	R[0x1110e0] = 0x80099000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe543[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x00111100] 0x04 0x01
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe54a[ ]: 	R[0x111100] = {
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe54a[ ]: 		0x45520000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe54e[ ]: 		0x08000000 *
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe552[ ]: 		0x4c020000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe556[ ]: 		0x08000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe55a[ ]: 		0x45520000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe55e[ ]: 		0x41520000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe562[ ]: 		0x08000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe566[ ]: 		0x41520000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe56a[ ]: 	}
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe56a[ ]: ZM_REG	R[0x10024c] = 0x0f000080
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe573[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x001111e0] 0x04 0x01
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe57a[ ]: 	R[0x1111e0] = {
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe57a[ ]: 		0x02000303
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe57e[ ]: 		0x02000404 *
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe582[ ]: 		0x02000404
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe586[ ]: 		0x02000404
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe58a[ ]: 		0x02000303
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe58e[ ]: 		0x02000303
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe592[ ]: 		0x02000404
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe596[ ]: 		0x02000303
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe59a[ ]: 	}
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe59a[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x00100254] 0x04 0x01
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe5a1[ ]: 	R[0x100254] = {
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe5a1[ ]: 		0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe5a5[ ]: 		0x00000000 *
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe5a9[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe5ad[ ]: 		0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe5b1[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe5b5[ ]: 		0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe5b9[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe5bd[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe5c1[ ]: 	}
>[  +0,000003] nouveau T[   VBIOS][0000:01:00.0] 0xe5c1[ ]: NV_REG	R[0x100500] &= 0xfff0ff01 |= 0x000a00fe
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe5ce[ ]: NV_REG	R[0x100c00] &= 0xfffffffb |= 0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe5db[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x00100220] 0x04 0x0b
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe5e2[ ]: 	R[0x100220] = {
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe5e2[ ]: 		0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe5e6[ ]: 		0x070f2d15 *
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe5ea[ ]: 		0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe5ee[ ]: 		0x070f2d15
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe5f2[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe5f6[ ]: 		0x0a192d23
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe5fa[ ]: 		0x070f2d15
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe5fe[ ]: 		0x0a192d23
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe602[ ]: 	}
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe602[ ]: 	R[0x100224] = {
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe602[ ]: 		0x01000105
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe606[ ]: 		0x0e030b05 *
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe60a[ ]: 		0x01000105
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe60e[ ]: 		0x0e030b05
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe612[ ]: 		0x01000105
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe616[ ]: 		0x12020b08
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe61a[ ]: 		0x0e030b05
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe61e[ ]: 		0x12020b08
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe622[ ]: 	}
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe622[ ]: 	R[0x100228] = {
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe622[ ]: 		0xff000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe626[ ]: 		0x05040707 *
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe62a[ ]: 		0xff000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe62e[ ]: 		0x05040707
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe632[ ]: 		0xff000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe636[ ]: 		0x04090306
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe63a[ ]: 		0x05040707
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe63e[ ]: 		0x04090306
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe642[ ]: 	}
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe642[ ]: 	R[0x10022c] = {
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe642[ ]: 		0xffffffff
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe646[ ]: 		0x362d1105 *
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe64a[ ]: 		0xffffffff
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe64e[ ]: 		0x362d1105
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe652[ ]: 		0xffffffff
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe656[ ]: 		0x392f1206
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe65a[ ]: 		0x362d1105
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe65e[ ]: 		0x392f1206
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe662[ ]: 	}
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe662[ ]: 	R[0x100230] = {
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe662[ ]: 		0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe666[ ]: 		0x12030a0a *
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe66a[ ]: 		0x12030000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe66e[ ]: 		0x12030a0a
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe672[ ]: 		0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe676[ ]: 		0x00000cbf
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe67a[ ]: 		0x12030a0a
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe67e[ ]: 		0x00000cbf
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe682[ ]: 	}
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe682[ ]: 	R[0x100234] = {
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe682[ ]: 		0x00000600
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe686[ ]: 		0x2d070c07 *
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe68a[ ]: 		0x00000600
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe68e[ ]: 		0x2d070c07
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe692[ ]: 		0x00000600
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe696[ ]: 		0x35080c08
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe69a[ ]: 		0x2d070c07
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe69e[ ]: 		0x35080c08
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe6a2[ ]: 	}
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe6a2[ ]: 	R[0x100238] = {
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe6a2[ ]: 		0x005a0650
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe6a6[ ]: 		0x00600650 *
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe6aa[ ]: 		0x005a0650
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe6ae[ ]: 		0x00600650
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe6b2[ ]: 		0x005a0650
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe6b6[ ]: 		0x007f0556
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe6ba[ ]: 		0x00600650
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe6be[ ]: 		0x007f0556
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe6c2[ ]: 	}
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe6c2[ ]: 	R[0x10023c] = {
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe6c2[ ]: 		0x04060202
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe6c6[ ]: 		0x0f130202 *
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe6ca[ ]: 		0x0b120202
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe6ce[ ]: 		0x0f130202
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe6d2[ ]: 		0x04060202
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe6d6[ ]: 		0x04060202
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe6da[ ]: 		0x0f130202
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe6de[ ]: 		0x04060202
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe6e2[ ]: 	}
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe6e2[ ]: 	R[0x100240] = {
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe6e2[ ]: 		0x111d0700
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe6e6[ ]: 		0x111d0700 *
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe6ea[ ]: 		0x111d0700
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe6ee[ ]: 		0x111d0700
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe6f2[ ]: 		0x111d0700
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe6f6[ ]: 		0x111d0700
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe6fa[ ]: 		0x111d0700
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe6fe[ ]: 		0x111d0700
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe702[ ]: 	}
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe702[ ]: 	R[0x100244] = {
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe702[ ]: 		0x00000cbf
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe706[ ]: 		0x0000019f *
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe70a[ ]: 		0x0000019f
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe70e[ ]: 		0x0000019f
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe712[ ]: 		0x00000cbf
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe716[ ]: 		0x00000cbf
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe71a[ ]: 		0x0000019f
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe71e[ ]: 		0x00000cbf
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe722[ ]: 	}
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe722[ ]: 	R[0x100248] = {
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe722[ ]: 		0x00c8600f
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe726[ ]: 		0x0200310a *
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe72a[ ]: 		0x0f00310a
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe72e[ ]: 		0x0200310a
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe732[ ]: 		0x00c8600f
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe736[ ]: 		0x00c8600f
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe73a[ ]: 		0x0200310a
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe73e[ ]: 		0x00c8600f
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe742[ ]: 	}
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe742[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x00100258] 0x08 0x02
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe749[ ]: 	R[0x100258] = {
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe749[ ]: 		0x00400200
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe74d[ ]: 		0x00400200 *
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe751[ ]: 		0x00400200
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe755[ ]: 		0x00400200
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe759[ ]: 		0x00400200
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe75d[ ]: 		0x00400200
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe761[ ]: 		0x00400200
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe765[ ]: 		0x00400200
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe769[ ]: 	}
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe769[ ]: 	R[0x100260] = {
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe769[ ]: 		0x00c35000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe76d[ ]: 		0x00c35000 *
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe771[ ]: 		0x00c35000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe775[ ]: 		0x00c35000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe779[ ]: 		0x00c35000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe77d[ ]: 		0x00c35000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe781[ ]: 		0x00c35000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe785[ ]: 		0x00c35000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe789[ ]: 	}
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe789[ ]: NV_REG	R[0x100268] &= 0xfffcffff |= 0x00030000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe796[ ]: CONDITION	0x0d
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe798[ ]: 	[0x0d] (R[0x101000] & 0x00000020) == 0x00000020
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe798[ ]: NV_REG	R[0x100268] &= 0xffffffff |= 0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe7a5[ ]: RESUME
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe7a6[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x00100200] 0x04 0x01
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe7ad[ ]: 	R[0x100200] = {
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe7ad[ ]: 		0x00223000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe7b1[ ]: 		0x00222800 *
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe7b5[ ]: 		0x00222800
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe7b9[ ]: 		0x00222800
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe7bd[ ]: 		0x00223000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe7c1[ ]: 		0x00223000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe7c5[ ]: 		0x00222800
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe7c9[ ]: 		0x00223000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe7cd[ ]: 	}
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe7cd[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x00100204] 0x04 0x01
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe7d4[ ]: 	R[0x100204] = {
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe7d4[ ]: 		0x0155a020
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe7d8[ ]: 		0x0155a020 *
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe7dc[ ]: 		0x0155a020
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe7e0[ ]: 		0x0155a020
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe7e4[ ]: 		0x0155a020
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe7e8[ ]: 		0x0155a020
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe7ec[ ]: 		0x0155a020
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe7f0[ ]: 		0x0155a020
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe7f4[ ]: 	}
>[  +0,000003] nouveau T[   VBIOS][0000:01:00.0] 0xe7f4[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x00100250] 0x04 0x01
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe7fb[ ]: 	R[0x100250] = {
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe7fb[ ]: 		0x00000001
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe7ff[ ]: 		0x00000001 *
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe803[ ]: 		0x00000001
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe807[ ]: 		0x00000001
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe80b[ ]: 		0x00000001
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe80f[ ]: 		0x00000001
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe813[ ]: 		0x00000001
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe817[ ]: 		0x00000001
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe81b[ ]: 	}
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe81b[ ]: ZM_REG	R[0x00122c] = 0x00000001
>[  +0,000003] nouveau T[   VBIOS][0000:01:00.0] 0xe824[ ]: NV_REG	R[0x1008cc] &= 0xfffffff7 |= 0x00000008
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe831[ ]: NV_REG	R[0x1008e0] &= 0x7fffffff |= 0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe83e[ ]: NV_REG	R[0x1008cc] &= 0xfffffff7 |= 0x00000008
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe84b[ ]: CONDITION_TIME	0x0c 0xff
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe84e[ ]: RESUME
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe84f[ ]: ZM_REG	R[0x100ae0] = 0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe858[ ]: ZM_REG	R[0x100ae8] = 0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe861[ ]: ZM_REG	R[0x100af0] = 0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe86a[ ]: TIME	0x0fa0
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe86d[ ]: MACRO	0x01
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe86d[ ]: 		R[0x1002d0] = 0x00000001
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe86f[ ]: ZM_REG	R[0x100218] = 0x01000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe878[ ]: TIME	0x00c8
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe87b[ ]: ZM_REG	R[0x10021c] = 0x00000001
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe884[ ]: ZM_REG	R[0x100218] = 0x01000100
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe88d[ ]: TIME	0x01f4
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe890[ ]: ZM_REG	R[0x100080] = 0x00000020
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe899[ ]: ZM_REG	R[0x100440] = 0x8050000b
>[  +0,000003] nouveau T[   VBIOS][0000:01:00.0] 0xe8a2[ ]: ZM_REG	R[0x1002d8] = 0x00000001
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe8ab[ ]: ZM_REG	R[0x100218] = 0x01000101
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe8b4[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x001002e0] 0x04 0x01
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe8bb[ ]: 	R[0x1002e0] = {
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe8bb[ ]: 		0x00200018
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe8bf[ ]: 		0x00200088 *
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe8c3[ ]: 		0x00200098
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe8c7[ ]: 		0x00200088
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe8cb[ ]: 		0x00200018
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe8cf[ ]: 		0x00200018
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe8d3[ ]: 		0x00200088
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe8d7[ ]: 		0x00200018
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe8db[ ]: 	}
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe8db[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x001002e4] 0x04 0x01
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe8e2[ ]: 	R[0x1002e4] = {
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe8e2[ ]: 		0x00300000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe8e6[ ]: 		0x00300000 *
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe8ea[ ]: 		0x00300000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe8ee[ ]: 		0x00300000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe8f2[ ]: 		0x00300000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe8f6[ ]: 		0x00300000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe8fa[ ]: 		0x00300000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe8fe[ ]: 		0x00300000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe902[ ]: 	}
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe902[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x001002c4] 0x04 0x01
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe909[ ]: 	R[0x1002c4] = {
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe909[ ]: 		0x00100000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe90d[ ]: 		0x00100000 *
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe911[ ]: 		0x00100002
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe915[ ]: 		0x00100000
>[  +0,000003] nouveau T[   VBIOS][0000:01:00.0] 0xe919[ ]: 		0x00100000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe91d[ ]: 		0x00100004
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe921[ ]: 		0x00100000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe925[ ]: 		0x00100004
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe929[ ]: 	}
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe929[ ]: MACRO	0x00
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe929[ ]: 		R[0x1002d4] = 0x00000001
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe92b[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x001002c0] 0x04 0x01
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe932[ ]: 	R[0x1002c0] = {
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe932[ ]: 		0x00001f40
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe936[ ]: 		0x00001720 *
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe93a[ ]: 		0x00001f40
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe93e[ ]: 		0x00001720
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe942[ ]: 		0x00001f40
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe946[ ]: 		0x00001b60
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe94a[ ]: 		0x00001720
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe94e[ ]: 		0x00001b60
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe952[ ]: 	}
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe952[ ]: CONDITION	0x0e
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe954[ ]: 	[0x0e] (R[0x100200] & 0x00000004) == 0x00000004
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe954[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x001002e8] 0x04 0x01
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe95b[ ]: 	R[0x1002e8] = {
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe95b[ ]: 		0x00200018
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe95f[ ]: 		0x00200088 *
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe963[ ]: 		0x00200098
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe967[ ]: 		0x00200088
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe96b[ ]: 		0x00200018
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe96f[ ]: 		0x00200018
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe973[ ]: 		0x00200088
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe977[ ]: 		0x00200018
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe97b[ ]: 	}
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe97b[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x001002ec] 0x04 0x01
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe982[ ]: 	R[0x1002ec] = {
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe982[ ]: 		0x00300000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe986[ ]: 		0x00300000 *
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe98a[ ]: 		0x00300000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe98e[ ]: 		0x00300000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe992[ ]: 		0x00300000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe996[ ]: 		0x00300000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe99a[ ]: 		0x00300000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe99e[ ]: 		0x00300000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe9a2[ ]: 	}
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe9a2[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x001002cc] 0x04 0x01
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe9a9[ ]: 	R[0x1002cc] = {
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe9a9[ ]: 		0x00100000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe9ad[ ]: 		0x00100000 *
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe9b1[ ]: 		0x00100002
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe9b5[ ]: 		0x00100000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe9b9[ ]: 		0x00100000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe9bd[ ]: 		0x00100004
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe9c1[ ]: 		0x00100000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe9c5[ ]: 		0x00100004
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe9c9[ ]: 	}
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe9c9[ ]: RAM_RESTRICT_ZM_REG_GROUP	R[0x001002c8] 0x04 0x01
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe9d0[ ]: 	R[0x1002c8] = {
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe9d0[ ]: 		0x00001f40
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe9d4[ ]: 		0x00001720 *
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe9d8[ ]: 		0x00001f40
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe9dc[ ]: 		0x00001720
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe9e0[ ]: 		0x00001f40
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe9e4[ ]: 		0x00001b60
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe9e8[ ]: 		0x00001720
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe9ec[ ]: 		0x00001b60
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe9f0[ ]: 	}
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xe9f0[ ]: RESUME
>[  +0,000003] nouveau T[   VBIOS][0000:01:00.0] 0xe9f1[ ]: CONDITION	0x0f
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe9f3[ ]: 	[0x0f] (R[0x100710] & 0x00000080) == 0x00000080
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xe9f3[ ]: NV_REG	R[0x00e108] &= 0xffffffff |= 0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xea00[ ]: RESUME
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xea01[ ]: ZM_REG	R[0x1002d8] = 0x00000001
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xea0a[ ]: ZM_REG	R[0x100264] = 0x00000001
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xea13[ ]: TIME	0x03e8
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xea16[ ]: MACRO	0x01
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xea16[ ]: 		R[0x1002d0] = 0x00000001
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xea18[ ]: TIME	0x03e8
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xea1b[ ]: ZM_REG	R[0x100210] = 0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xea24[ ]: ZM_REG	R[0x10025c] = 0x80000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xea2d[ ]: NV_REG	R[0x004018] &= 0xffff3fff |= 0x0000c000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xea3a[ ]: TIME	0x03e8
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xea3d[ ]: DONE
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xea3f[ ]: ZM_REG	R[0x1008c0] = 0x9d0a0293
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xea48[ ]: SUB_DIRECT	0xd99d
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xea4b[ ]: ZM_REG	R[0x00e200] = 0x0003103c
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xea54[ ]: SUB_DIRECT	0xd9b7
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xea57[ ]: DONE
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xea58[ ]: SUB_DIRECT	0xcb0f
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xea5b[ ]: TIME	0x03e8
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xea5e[ ]: SUB_DIRECT	0xea3e
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xea61[ ]: MACRO	0x00
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xea61[ ]: 		R[0x1002d4] = 0x00000001
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xea63[ ]: REPEAT	0x0a
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xea65[ ]: MACRO	0x01
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xea65[ ]: 		R[0x1002d0] = 0x00000001
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xea67[ ]: END_REPEAT
>[  +0,000003] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x09
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xea65[ ]: MACRO	0x01
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xea65[ ]: 		R[0x1002d0] = 0x00000001
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xea67[ ]: END_REPEAT
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x08
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xea65[ ]: MACRO	0x01
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xea65[ ]: 		R[0x1002d0] = 0x00000001
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xea67[ ]: END_REPEAT
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x07
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xea65[ ]: MACRO	0x01
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xea65[ ]: 		R[0x1002d0] = 0x00000001
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xea67[ ]: END_REPEAT
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x06
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xea65[ ]: MACRO	0x01
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xea65[ ]: 		R[0x1002d0] = 0x00000001
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xea67[ ]: END_REPEAT
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x05
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xea65[ ]: MACRO	0x01
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xea65[ ]: 		R[0x1002d0] = 0x00000001
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xea67[ ]: END_REPEAT
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x04
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xea65[ ]: MACRO	0x01
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xea65[ ]: 		R[0x1002d0] = 0x00000001
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xea67[ ]: END_REPEAT
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x03
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xea65[ ]: MACRO	0x01
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xea65[ ]: 		R[0x1002d0] = 0x00000001
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xea67[ ]: END_REPEAT
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x02
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xea65[ ]: MACRO	0x01
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xea65[ ]: 		R[0x1002d0] = 0x00000001
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xea67[ ]: END_REPEAT
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0x0000[ ]: REPEAT	0x01
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xea65[ ]: MACRO	0x01
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xea65[ ]: 		R[0x1002d0] = 0x00000001
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xea67[ ]: END_REPEAT
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xea68[ ]: MACRO	0x00
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xea68[ ]: 		R[0x1002d4] = 0x00000001
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xea6a[ ]: MACRO	0x01
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xea6a[ ]: 		R[0x1002d0] = 0x00000001
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xea6c[ ]: MACRO	0x01
>[  +0,000003] nouveau T[   VBIOS][0000:01:00.0] 0xea6c[ ]: 		R[0x1002d0] = 0x00000001
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xea6e[ ]: ZM_REG	R[0x100210] = 0x80000001
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xea77[ ]: NV_REG	R[0x100710] &= 0xfffffdff |= 0x00000200
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xea84[ ]: NV_REG	R[0x100e04] &= 0xffe0007f |= 0x00064c80
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xea91[ ]: NV_REG	R[0x100e08] &= 0xf01fffff |= 0x0b000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xea9e[ ]: NV_REG	R[0x100200] &= 0xfffff7ff |= 0x00000800
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xeaab[ ]: NV_REG	R[0x100600] &= 0xffffffff |= 0x00004000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xeab8[ ]: COMPUTE_MEM
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xeab9[ ]: SUB_DIRECT	0xd6fb
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xeabc[ ]: NV_REG	R[0x100674] &= 0xffff0000 |= 0x00000404
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xeac9[ ]: NV_REG	R[0x001558] &= 0xfffffffc |= 0x00000003
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xead6[ ]: ZM_REG	R[0x001588] = 0x00000001
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xeadf[ ]: NV_REG	R[0x020060] &= 0x00c0ffff |= 0x00040000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xeaec[ ]: ZM_REG	R[0x020080] = 0x100c0736
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xeaf5[ ]: NV_REG	R[0x020018] &= 0xffffffff |= 0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xeb02[ ]: NV_REG	R[0x08814c] &= 0xffffffff |= 0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xeb0f[ ]: ZM_REG	R[0x088154] = 0x00007120
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xeb18[ ]: ZM_REG	R[0x082000] = 0x00000002
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xeb21[ ]: SUB_DIRECT	0xd81f
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xeb24[ ]: NV_REG	R[0x00e1e4] &= 0xfffffffc |= 0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xeb31[ ]: NV_REG	R[0x001084] &= 0xfffff7ff |= 0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xeb3e[ ]: DONE
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xeb3f[ ]: DONE
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xeba4[ ]: SUB_DIRECT	0xd835
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xeba7[ ]: DONE
>[  +0,000008] nouveau T[     I2C][0000:01:00.0] use(+1) == 1
>[  +0,000002] nouveau T[     I2C][0000:01:00.0] initialising...
>[  +0,000001] nouveau T[     I2C][0000:01:00.0] resetting...
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] PAD:X:00: -> NULL
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] PAD:X:01: -> NULL
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] PAD:X:03: -> NULL
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] PAD:X:05: -> NULL
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] PAD:S:00: -> NULL
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] PAD:S:01: -> NULL
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] PAD:S:02: -> NULL
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] PAD:S:03: -> NULL
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] PAD:S:00: -> NULL
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] PAD:S:01: -> NULL
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] PAD:S:02: -> NULL
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] PAD:S:03: -> NULL
>[  +0,000004] nouveau D[     I2C][0000:01:00.0] reset
>[  +0,000002] nouveau T[     I2C][0000:01:00.0] initialised
>[  +0,000018] nouveau 0000:01:00.0: irq 54 for MSI/MSI-X
>[  +0,000007] nouveau  [     PMC][0000:01:00.0] MSI interrupts enabled
>[  +0,000076] nouveau  [     PFB][0000:01:00.0] RAM type: DDR3
>[  +0,000053] nouveau  [     PFB][0000:01:00.0] RAM size: 512 MiB
>[  +0,000051] nouveau  [     PFB][0000:01:00.0]    ZCOMP: 960 tags
>[  +0,002732] nouveau  [    VOLT][0000:01:00.0] GPU voltage: 900000uv
>[  +0,000056] nouveau D[     I2C][0000:01:00.0] probing monitoring devices on bus: 2
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] PAD:X:03: -> PORT:02
>[  +0,052156] nouveau D[     I2C][0000:01:00.0] PAD:X:03: -> NULL
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] PAD:X:03: -> PORT:02
>[  +0,053387] nouveau D[     I2C][0000:01:00.0] PAD:X:03: -> NULL
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] using custom udelay 40 instead of 10
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] PAD:X:03: -> PORT:02
>[  +0,053418] nouveau D[     I2C][0000:01:00.0] PAD:X:03: -> NULL
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] using custom udelay 40 instead of 10
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] PAD:X:03: -> PORT:02
>[  +0,053389] nouveau D[     I2C][0000:01:00.0] PAD:X:03: -> NULL
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] using custom udelay 40 instead of 10
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] PAD:X:03: -> PORT:02
>[  +0,033805] EXT4-fs (sda4): re-mounted. Opts: (null)
>[  +0,019631] nouveau D[     I2C][0000:01:00.0] PAD:X:03: -> NULL
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] PAD:X:03: -> PORT:02
>[  +0,053315] nouveau D[     I2C][0000:01:00.0] PAD:X:03: -> NULL
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] PAD:X:03: -> PORT:02
>[  +0,053436] nouveau D[     I2C][0000:01:00.0] PAD:X:03: -> NULL
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] PAD:X:03: -> PORT:02
>[  +0,053394] nouveau D[     I2C][0000:01:00.0] PAD:X:03: -> NULL
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] PAD:X:03: -> PORT:02
>[  +0,053390] nouveau D[     I2C][0000:01:00.0] PAD:X:03: -> NULL
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] PAD:X:03: -> PORT:02
>[  +0,053394] nouveau D[     I2C][0000:01:00.0] PAD:X:03: -> NULL
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] PAD:X:03: -> PORT:02
>[  +0,053395] nouveau D[     I2C][0000:01:00.0] PAD:X:03: -> NULL
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] PAD:X:03: -> PORT:02
>[  +0,053366] nouveau D[     I2C][0000:01:00.0] PAD:X:03: -> NULL
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] PAD:X:03: -> PORT:02
>[  +0,032980] systemd-udevd[200]: starting version 215
>[  +0,020413] nouveau D[     I2C][0000:01:00.0] PAD:X:03: -> NULL
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] PAD:X:03: -> PORT:02
>[  +0,053396] nouveau D[     I2C][0000:01:00.0] PAD:X:03: -> NULL
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] PAD:X:03: -> PORT:02
>[  +0,053405] nouveau D[     I2C][0000:01:00.0] PAD:X:03: -> NULL
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] PAD:X:03: -> PORT:02
>[  +0,053340] nouveau D[     I2C][0000:01:00.0] PAD:X:03: -> NULL
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] PAD:X:03: -> PORT:02
>[  +0,053391] nouveau D[     I2C][0000:01:00.0] PAD:X:03: -> NULL
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] PAD:X:03: -> PORT:02
>[  +0,053393] nouveau D[     I2C][0000:01:00.0] PAD:X:03: -> NULL
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] PAD:X:03: -> PORT:02
>[  +0,053420] nouveau D[     I2C][0000:01:00.0] PAD:X:03: -> NULL
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] PAD:X:03: -> PORT:02
>[  +0,053361] nouveau D[     I2C][0000:01:00.0] PAD:X:03: -> NULL
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] no devices found.
>[  +0,000005] nouveau  [  PTHERM][0000:01:00.0] FAN control: none / external
>[  +0,000060] nouveau  [  PTHERM][0000:01:00.0] fan management: automatic
>[  +0,000053] nouveau  [  PTHERM][0000:01:00.0] internal sensor: yes
>[  +0,000073] nouveau  [     CLK][0000:01:00.0] 03: core 135 MHz shader 270 MHz memory 135 MHz
>[  +0,000069] nouveau  [     CLK][0000:01:00.0] 07: core 405 MHz shader 810 MHz memory 405 MHz
>[  +0,000068] nouveau  [     CLK][0000:01:00.0] 0f: core 589 MHz shader 1402 MHz memory 790 MHz
>[  +0,000084] nouveau  [     CLK][0000:01:00.0] --: core 405 MHz shader 810 MHz memory 405 MHz
>[  +0,000108] nouveau T[   PDISP][0000:01:00.0] inc() == 2
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0] inc() == 3
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 00:ff00:0302: type 00 loc 0 or 2 link 0 con 0 edid 0 bus 0 head 3
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0] inc() == 4
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0] inc() == 5
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 00:0030: type 30 loc 0 hpd 01 dp 0 di 0 sr 0 lcdid 0
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 00:0030: func 07 (HPD)
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0x00000000][ffff880212ff8280] created
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0x00000000][ffff880212ff8100] created
>[  +0,000003] nouveau T[   PDISP][0000:01:00.0] inc() == 6
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0] inc() == 7
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 01:0002:03c1: type 02 loc 0 or 1 link 3 con 0 edid 0 bus 0 head 3
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0x00000000][ffff880213782000] created
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0] inc() == 8
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0] inc() == 9
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: type 06 loc 0 or 4 link 1 con 1 edid b bus 1 head 3
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0] inc() == 10
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0] inc() == 11
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 01:0146: type 46 loc 1 hpd 02 dp 0 di 2 sr 0 lcdid 0
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 01:0146: func 08 (HPD)
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0x00000000][ffff880213782080] created
>[  +0,000004] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: bios dp 21 12 0a 05
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0x00000006][ffff8800d78c0e00] created
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0] inc() == 12
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0] inc() == 13
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 03:0002:0344: type 02 loc 0 or 4 link 1 con 1 edid 7 bus 1 head 3
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0x00000000][ffff880213782100] created
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0] created
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0] resetting...
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] reset
>[  +0,000233] [TTM] Zone  kernel: Available graphics memory: 4057400 kiB
>[  +0,000055] [TTM] Zone   dma32: Available graphics memory: 2097152 kiB
>[  +0,000053] [TTM] Initializing pool allocator
>[  +0,001065] [TTM] Initializing DMA pool allocator
>[  +0,000058] nouveau  [     DRM] VRAM: 512 MiB
>[  +0,000050] nouveau  [     DRM] GART: 1048576 MiB
>[  +0,000051] nouveau  [     DRM] TMDS table version 2.0
>[  +0,000051] nouveau  [     DRM] DCB version 4.0
>[  +0,000050] nouveau  [     DRM] DCB outp 00: 02000300 00000000
>[  +0,000052] nouveau  [     DRM] DCB outp 01: 01000302 00020030
>[  +0,000051] nouveau  [     DRM] DCB outp 02: 048113b6 0f220010
>[  +0,000052] nouveau  [     DRM] DCB outp 03: 04011372 00020010
>[  +0,000051] nouveau  [     DRM] DCB conn 00: 00001030
>[  +0,000081] nouveau  [     DRM] DCB conn 01: 00202146
>[  +0,000096] nouveau T[   PDISP][0000:01:00.0] use(+1) == 1
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0] initialising...
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0] resetting...
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] reset
>[  +0,000009] nouveau D[     I2C][0000:01:00.0] PAD:S:01: -> PORT:0b
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000000 16
>[  +0,000563] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110900f 0x10000010
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: aux power -> always
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000100 2
>[  +0,000144] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109001 0x10000002
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0101840a
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[  +0,000012] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000202 3
>[  +0,000154] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01800000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: no inter-lane alignment
>[  +0,000007] nouveau T[   VBIOS][0000:01:00.0] 0xc535[0]: NV_REG	R[0x004710] &= 0xf8ffffff |= 0x00000000
>[  +0,000003] nouveau T[   VBIOS][0000:01:00.0] 0xc542[0]: DP_CONDITION	0x01 0x10
>[  +0,000004] nouveau T[   VBIOS][0000:01:00.0] 0xc545[ ]: NV_REG	R[0x00e820] &= 0xfffffeff |= 0x00000100
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc552[ ]: IO_OR	0x03d4[0x86] |= (1 << 0x00)
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc554[ ]: RESUME
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc555[0]: DP_CONDITION	0x02 0x10
>[  +0,000003] nouveau T[   VBIOS][0000:01:00.0] 0xc558[0]: NV_REG	R[0x00e8a0] &= 0xfffffeff |= 0x00000100
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc565[0]: IO_OR	0x03d4[0x8e] |= (1 << 0x02)
>[  +0,000003] nouveau T[   VBIOS][0000:01:00.0] 0xc567[0]: RESUME
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc568[0]: NV_REG	R[0x6061c10c] &= 0xffffbffe |= 0x00004001
>[  +0,000004] nouveau T[   VBIOS][0000:01:00.0] 0xc575[0]: NV_REG	R[0x6061c128] &= 0x7fffffff |= 0x80000000
>[  +0,000004] nouveau T[   VBIOS][0000:01:00.0] 0xc582[0]: NV_REG	R[0x40614300] &= 0xfcffffff |= 0x03000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc58f[0]: ZM_REG	R[0x4061c00c] = 0x01000300
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc598[0]: ZM_REG	R[0x4061c010] = 0x0030152f
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc5a1[0]: ZM_REG	R[0x4061c014] = 0x00020000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc5aa[0]: SUB_DIRECT	0x46bb
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0x46bb[1]: NV_REG	R[0x4061c010] &= 0xffffe1ff |= 0x00001000
>[  +0,000004] nouveau T[   VBIOS][0000:01:00.0] 0x46c8[1]: TIME	0x0064
>[  +0,000102] nouveau T[   VBIOS][0000:01:00.0] 0x46cb[1]: CONDITION	0x11
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0x46cd[1]: 	[0x11] (R[0x4061c010] & 0x00008000) == 0x00008000
>[  +0,000004] nouveau T[   VBIOS][0000:01:00.0] 0x46cd[1]: NV_REG	R[0x4061c010] &= 0xffffefff |= 0x00000000
>[  +0,000003] nouveau T[   VBIOS][0000:01:00.0] 0x46da[1]: RESUME
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0x46db[1]: NV_REG	R[0x4061c010] &= 0xfffff7ff |= 0x00000800
>[  +0,000003] nouveau T[   VBIOS][0000:01:00.0] 0x46e8[1]: TIME	0x0064
>[  +0,000102] nouveau T[   VBIOS][0000:01:00.0] 0x46eb[1]: CONDITION	0x11
>[  +0,000003] nouveau T[   VBIOS][0000:01:00.0] 0x46ed[1]: 	[0x11] (R[0x4061c010] & 0x00008000) == 0x00008000
>[  +0,000003] nouveau T[   VBIOS][0000:01:00.0] 0x46ed[1]: NV_REG	R[0x4061c010] &= 0xfffff7ff |= 0x00000000
>[  +0,000003] nouveau T[   VBIOS][0000:01:00.0] 0x46fa[1]: RESUME
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0x46fb[1]: NV_REG	R[0x4061c010] &= 0xfffffbff |= 0x00000400
>[  +0,000003] nouveau T[   VBIOS][0000:01:00.0] 0x4708[1]: TIME	0x0064
>[  +0,000102] nouveau T[   VBIOS][0000:01:00.0] 0x470b[1]: CONDITION	0x11
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0x470d[1]: 	[0x11] (R[0x4061c010] & 0x00008000) == 0x00008000
>[  +0,000003] nouveau T[   VBIOS][0000:01:00.0] 0x470d[ ]: NV_REG	R[0x4061c010] &= 0xfffffbff |= 0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0x471a[ ]: RESUME
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0x471b[1]: NV_REG	R[0x4061c010] &= 0xfffffdff |= 0x00000200
>[  +0,000003] nouveau T[   VBIOS][0000:01:00.0] 0x4728[1]: TIME	0x0064
>[  +0,000102] nouveau T[   VBIOS][0000:01:00.0] 0x472b[1]: CONDITION	0x11
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0x472d[1]: 	[0x11] (R[0x4061c010] & 0x00008000) == 0x00008000
>[  +0,000003] nouveau T[   VBIOS][0000:01:00.0] 0x472d[ ]: NV_REG	R[0x4061c010] &= 0xfffffdff |= 0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0x473a[ ]: RESUME
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0x473b[1]: DONE
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc5ad[0]: NV_REG	R[0x40614300] &= 0xfffcffff |= 0x00010000
>[  +0,000003] nouveau T[   VBIOS][0000:01:00.0] 0xc5ba[0]: NV_REG	R[0x6061c130] &= 0xffbfff00 |= 0x004000ff
>[  +0,000003] nouveau T[   VBIOS][0000:01:00.0] 0xc5c7[0]: TIME	0x000a
>[  +0,000012] nouveau T[   VBIOS][0000:01:00.0] 0xc5ca[0]: NV_REG	R[0x6061c130] &= 0xffffff0f |= 0x00000000
>[  +0,000003] nouveau T[   VBIOS][0000:01:00.0] 0xc5d7[0]: NV_REG	R[0x6061c10c] &= 0xfcffcfff |= 0x00000000
>[  +0,000003] nouveau T[   VBIOS][0000:01:00.0] 0xc5e4[0]: AUXCH	AUX[0x00000600] 0x01
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc5ea[0]: 	AUX[0x00000600] &= 0xfc |= 0x01
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000600 1
>[  +0,000136] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01800001
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000600 1
>[  +0,000007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000001
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000132] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  +0,000003] nouveau T[   VBIOS][0000:01:00.0] 0xc5ec[0]: AUXCH	AUX[0x00000102] 0x01
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc5f2[0]: 	AUX[0x00000102] &= 0xdf |= 0x20
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000102 1
>[  +0,000137] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01800000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000102 1
>[  +0,000007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000020
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000132] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  +0,000003] nouveau T[   VBIOS][0000:01:00.0] 0xc5f4[0]: DP_CONDITION	0x05 0x15
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x0000000d 1
>[  +0,000135] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01800000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc5f7[ ]: NV_REG	R[0x6061c140] &= 0xfffffffd |= 0x00000002
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc604[ ]: AUXCH	AUX[0x0000010a] 0x01
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc60a[ ]: 	AUX[0x0000010a] &= 0xfe |= 0x01
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc60c[ ]: DONE
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: 0 lanes at 0 KB/s
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc62d[0]: ZM_REG	R[0x4061c00c] = 0x01000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc636[0]: DONE
>[  +0,000008] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000100 2
>[  +0,000007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000139] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108001 0x10000000
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: training pattern 1
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000102 1
>[  +0,000137] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01800020
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000102 1
>[  +0,000007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000021
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000132] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000103 4
>[  +0,000007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000156] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108003 0x10000000
>[  +0,004007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000202 6
>[  +0,000178] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00800000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01013333
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: status 00 00 80 00 33 33
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: training pattern 2
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000102 1
>[  +0,000138] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00800021
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01013333
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000102 1
>[  +0,000007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000022
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000132] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  +0,004008] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000202 6
>[  +0,000177] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00800000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0101bbbb
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: status 00 00 80 00 bb bb
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000103 4
>[  +0,000007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000156] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108003 0x10000000
>[  +0,004007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000202 6
>[  +0,000178] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0101bbbb
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: status 00 00 00 00 bb bb
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000103 4
>[  +0,000007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000156] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108003 0x10000000
>[  +0,004007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000202 6
>[  +0,000178] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0101bbbb
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: status 00 00 00 00 bb bb
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000103 4
>[  +0,000007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000156] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108003 0x10000000
>[  +0,004008] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000202 6
>[  +0,000177] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0101bbbb
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: status 00 00 00 00 bb bb
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000103 4
>[  +0,000007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000155] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108003 0x10000000
>[  +0,004008] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000202 6
>[  +0,000178] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0101bbbb
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: status 00 00 00 00 bb bb
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000103 4
>[  +0,000007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000155] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108003 0x10000000
>[  +0,004008] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000202 6
>[  +0,000177] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0101bbbb
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: status 00 00 00 00 bb bb
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: 0 lanes at 0 KB/s
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc62d[0]: ZM_REG	R[0x4061c00c] = 0x01000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc636[0]: DONE
>[  +0,000008] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000100 2
>[  +0,000007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000139] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108001 0x10000000
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: training pattern 1
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000102 1
>[  +0,000137] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000022
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0101bbbb
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000102 1
>[  +0,000007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000021
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000132] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000103 4
>[  +0,000007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000155] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108003 0x10000000
>[  +0,004008] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000202 6
>[  +0,000177] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00800000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01013333
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: status 00 00 80 00 33 33
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: training pattern 2
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000102 1
>[  +0,000137] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00800021
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01013333
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000102 1
>[  +0,000007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000022
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000130] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  +0,004007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000202 6
>[  +0,000178] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00800000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0101bbbb
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: status 00 00 80 00 bb bb
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000103 4
>[  +0,000007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000156] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108003 0x10000000
>[  +0,004007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000202 6
>[  +0,000178] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0101bbbb
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: status 00 00 00 00 bb bb
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000103 4
>[  +0,000007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000155] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108003 0x10000000
>[  +0,004008] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000202 6
>[  +0,000178] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0101bbbb
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: status 00 00 00 00 bb bb
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000103 4
>[  +0,000007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000156] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108003 0x10000000
>[  +0,004007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000202 6
>[  +0,000178] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0101bbbb
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: status 00 00 00 00 bb bb
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000103 4
>[  +0,000006] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000155] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108003 0x10000000
>[  +0,004008] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000202 6
>[  +0,000177] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0101bbbb
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: status 00 00 00 00 bb bb
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000103 4
>[  +0,000007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000156] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108003 0x10000000
>[  +0,004007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000202 6
>[  +0,000178] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0101bbbb
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: status 00 00 00 00 bb bb
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: training pattern 0
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000102 1
>[  +0,000138] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000022
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0101bbbb
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000102 1
>[  +0,000006] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000020
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000132] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  +0,000002] nouveau E[   PDISP][0000:01:00.0] 02:0006:0344: link training failed
>[  +0,000067] nouveau T[   VBIOS][0000:01:00.0] 0xc60d[0]: NV_REG	R[0x6061c10c] &= 0xfcffcfff |= 0x00001000
>[  +0,000003] nouveau T[   VBIOS][0000:01:00.0] 0xc61a[0]: AUXCH	AUX[0x00000102] 0x01
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc620[0]: 	AUX[0x00000102] &= 0xdf |= 0x00
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000102 1
>[  +0,000137] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000020
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0101bbbb
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000102 1
>[  +0,000007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000130] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  +0,000003] nouveau T[   VBIOS][0000:01:00.0] 0xc622[0]: DONE
>[  +0,000001] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: training complete
>[  +0,000086] nouveau T[   PDISP][0000:01:00.0] initialised
>[  +0,000029] nouveau T[   PDISP][0000:01:00.0] inc() == 2
>[  +0,000006] nouveau T[   PDISP][0000:01:00.0][0x03005023][ffff8800d6e49900] created
>[  +0,000005] nouveau T[   PDISP][0000:01:00.0][0x03005023][ffff8800d6e49900] inc() == 2
>[  +0,000003] nouveau T[   PDISP][0000:01:00.0] inc() == 3
>[  +0,000004] nouveau T[   PDISP][0000:01:00.0][0x80008570][ffff880212c08300] inc() == 3
>[  +0,000003] nouveau T[   PDISP][0000:01:00.0] inc() == 4
>[  +0,000004] nouveau T[   PDISP][0000:01:00.0][0x80008570][ffff880212c08300] dec() == 2
>[  +0,000149] nouveau T[   PDISP][0000:01:00.0][0x80008570][ffff880212c08300] created
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0x80008570][ffff880212c08300] use(+1) == 1
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0x80008570][ffff880212c08300] initialising...
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0x03005023][ffff8800d6e49900] use(+1) == 1
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0x03005023][ffff8800d6e49900] initialising...
>[  +0,000003] nouveau T[   PDISP][0000:01:00.0] use(+1) == 2
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0x03005023][ffff8800d6e49900] initialised
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0] use(+1) == 3
>[  +0,000027] nouveau T[   PDISP][0000:01:00.0][0x80008570][ffff880212c08300] initialised
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0x80008570][ffff880212c08300] inc() == 2
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0x80008570][ffff880212c08300] use(+1) == 2
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0x80008570][ffff880212c08300] use(-1) == 1
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0x80008570][ffff880212c08300] dec() == 1
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0x03005023][ffff8800d6e49900] dec() == 1
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0] use(-1) == 2
>[  +0,034369] nouveau T[   PDISP][0000:01:00.0][0x80008570][ffff880212c08300] inc() == 2
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0] use(+1) == 3
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0x80008570][ffff880212c08300] inc() == 4
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0] inc() == 5
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857d][ffff88021327d600] created
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857d][ffff88021327d600] use(+1) == 1
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0xc000857d][ffff88021327d600] initialising...
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0x80008570][ffff880212c08300] use(+1) == 2
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0] use(+1) == 4
>[  +0,000032] nouveau T[   PDISP][0000:01:00.0][0xc000857d][ffff88021327d600] initialised
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857d][ffff88021327d600] inc() == 2
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0xc000857d][ffff88021327d600] use(+1) == 2
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857d][ffff88021327d600] use(-1) == 1
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857d][ffff88021327d600] dec() == 1
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0x80008570][ffff880212c08300] dec() == 3
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0] use(-1) == 3
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0x80008570][ffff880212c08300] dec() == 2
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857d][ffff88021327d600] inc() == 2
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857d][ffff88021327d600] inc() == 3
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0xc000857d][ffff88021327d600] inc() == 4
>[  +0,000006] nouveau T[   PDISP][0000:01:00.0][0xc000857d][ffff88021327d600] use(+1) == 2
>[  +0,000008] nouveau T[   PDISP][0000:01:00.0][0xc000857d][ffff88021327d600] dec() == 3
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0xc000857d][ffff88021327d600] dec() == 2
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857d][ffff88021327d600] inc() == 3
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857d][ffff88021327d600] inc() == 4
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0xc000857d][ffff88021327d600] inc() == 5
>[  +0,000005] nouveau T[   PDISP][0000:01:00.0][0xc000857d][ffff88021327d600] use(+1) == 3
>[  +0,000008] nouveau T[   PDISP][0000:01:00.0][0xc000857d][ffff88021327d600] dec() == 4
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0xc000857d][ffff88021327d600] dec() == 3
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857d][ffff88021327d600] inc() == 4
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857d][ffff88021327d600] inc() == 5
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0xc000857d][ffff88021327d600] inc() == 6
>[  +0,000005] nouveau T[   PDISP][0000:01:00.0][0xc000857d][ffff88021327d600] use(+1) == 4
>[  +0,000008] nouveau T[   PDISP][0000:01:00.0][0xc000857d][ffff88021327d600] dec() == 5
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0xc000857d][ffff88021327d600] dec() == 4
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857d][ffff88021327d600] inc() == 5
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857d][ffff88021327d600] inc() == 6
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0xc000857d][ffff88021327d600] inc() == 7
>[  +0,000005] nouveau T[   PDISP][0000:01:00.0][0xc000857d][ffff88021327d600] use(+1) == 5
>[  +0,000008] nouveau T[   PDISP][0000:01:00.0][0xc000857d][ffff88021327d600] dec() == 6
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0xc000857d][ffff88021327d600] dec() == 5
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857d][ffff88021327d600] inc() == 6
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0xc000857d][ffff88021327d600] inc() == 7
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857d][ffff88021327d600] inc() == 8
>[  +0,000005] nouveau T[   PDISP][0000:01:00.0][0xc000857d][ffff88021327d600] use(+1) == 6
>[  +0,000007] nouveau T[   PDISP][0000:01:00.0][0xc000857d][ffff88021327d600] dec() == 7
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857d][ffff88021327d600] dec() == 6
>[  +0,000021] nouveau T[   PDISP][0000:01:00.0][0x80008570][ffff880212c08300] inc() == 3
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0] use(+1) == 4
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0x80008570][ffff880212c08300] inc() == 5
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0] inc() == 6
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0xc000857a][ffff88021327d280] created
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857a][ffff88021327d280] use(+1) == 1
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857a][ffff88021327d280] initialising...
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0x80008570][ffff880212c08300] use(+1) == 3
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0] use(+1) == 5
>[  +0,000006] nouveau T[   PDISP][0000:01:00.0][0xc000857a][ffff88021327d280] initialised
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857a][ffff88021327d280] inc() == 2
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857a][ffff88021327d280] use(+1) == 2
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857a][ffff88021327d280] use(-1) == 1
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0xc000857a][ffff88021327d280] dec() == 1
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0x80008570][ffff880212c08300] dec() == 4
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0] use(-1) == 4
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0x80008570][ffff880212c08300] dec() == 3
>[  +0,000016] nouveau T[   PDISP][0000:01:00.0][0x80008570][ffff880212c08300] inc() == 4
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0] use(+1) == 5
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0x80008570][ffff880212c08300] inc() == 6
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0] inc() == 7
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327d180] created
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327d180] use(+1) == 1
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327d180] initialising...
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0x80008570][ffff880212c08300] use(+1) == 4
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0] use(+1) == 6
>[  +0,000006] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327d180] initialised
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327d180] inc() == 2
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327d180] use(+1) == 2
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327d180] use(-1) == 1
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327d180] dec() == 1
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0x80008570][ffff880212c08300] dec() == 5
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0] use(-1) == 5
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0x80008570][ffff880212c08300] dec() == 4
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327d180] inc() == 2
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327d180] inc() == 3
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327d180] inc() == 4
>[  +0,000005] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327d180] use(+1) == 2
>[  +0,000008] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327d180] dec() == 3
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327d180] dec() == 2
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327d180] inc() == 3
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327d180] inc() == 4
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327d180] inc() == 5
>[  +0,000005] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327d180] use(+1) == 3
>[  +0,000008] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327d180] dec() == 4
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327d180] dec() == 3
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327d180] inc() == 4
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327d180] inc() == 5
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327d180] inc() == 6
>[  +0,000005] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327d180] use(+1) == 4
>[  +0,000008] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327d180] dec() == 5
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327d180] dec() == 4
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327d180] inc() == 5
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327d180] inc() == 6
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327d180] inc() == 7
>[  +0,000005] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327d180] use(+1) == 5
>[  +0,000007] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327d180] dec() == 6
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327d180] dec() == 5
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327d180] inc() == 6
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327d180] inc() == 7
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327d180] inc() == 8
>[  +0,000005] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327d180] use(+1) == 6
>[  +0,000007] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327d180] dec() == 7
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327d180] dec() == 6
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0x80008570][ffff880212c08300] inc() == 5
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0] use(+1) == 6
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0x80008570][ffff880212c08300] inc() == 7
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0] inc() == 8
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857b][ffff88021327d980] created
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0xc000857b][ffff88021327d980] use(+1) == 1
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857b][ffff88021327d980] initialising...
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0x80008570][ffff880212c08300] use(+1) == 5
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0] use(+1) == 7
>[  +0,000007] nouveau T[   PDISP][0000:01:00.0][0xc000857b][ffff88021327d980] initialised
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857b][ffff88021327d980] inc() == 2
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857b][ffff88021327d980] use(+1) == 2
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0xc000857b][ffff88021327d980] use(-1) == 1
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857b][ffff88021327d980] dec() == 1
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0x80008570][ffff880212c08300] dec() == 6
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0] use(-1) == 6
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0x80008570][ffff880212c08300] dec() == 5
>[  +0,000006] nouveau T[   PDISP][0000:01:00.0][0x80008570][ffff880212c08300] inc() == 6
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0] use(+1) == 7
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0x80008570][ffff880212c08300] inc() == 8
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0] inc() == 9
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff88021327da00] created
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff88021327da00] use(+1) == 1
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff88021327da00] initialising...
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0x80008570][ffff880212c08300] use(+1) == 6
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0] use(+1) == 8
>[  +0,000007] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff88021327da00] initialised
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff88021327da00] inc() == 2
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff88021327da00] use(+1) == 2
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff88021327da00] use(-1) == 1
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff88021327da00] dec() == 1
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0x80008570][ffff880212c08300] dec() == 7
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0] use(-1) == 7
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0x80008570][ffff880212c08300] dec() == 6
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff88021327da00] inc() == 2
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff88021327da00] inc() == 3
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff88021327da00] inc() == 4
>[  +0,000005] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff88021327da00] use(+1) == 2
>[  +0,000007] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff88021327da00] dec() == 3
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff88021327da00] dec() == 2
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff88021327da00] inc() == 3
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff88021327da00] inc() == 4
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff88021327da00] inc() == 5
>[  +0,000005] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff88021327da00] use(+1) == 3
>[  +0,000007] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff88021327da00] dec() == 4
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff88021327da00] dec() == 3
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff88021327da00] inc() == 4
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff88021327da00] inc() == 5
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff88021327da00] inc() == 6
>[  +0,000006] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff88021327da00] use(+1) == 4
>[  +0,000007] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff88021327da00] dec() == 5
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff88021327da00] dec() == 4
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff88021327da00] inc() == 5
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff88021327da00] inc() == 6
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff88021327da00] inc() == 7
>[  +0,000006] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff88021327da00] use(+1) == 5
>[  +0,000007] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff88021327da00] dec() == 6
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff88021327da00] dec() == 5
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff88021327da00] inc() == 6
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff88021327da00] inc() == 7
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff88021327da00] inc() == 8
>[  +0,000006] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff88021327da00] use(+1) == 6
>[  +0,000007] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff88021327da00] dec() == 7
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff88021327da00] dec() == 6
>[  +0,000025] nouveau T[   PDISP][0000:01:00.0][0x80008570][ffff880212c08300] inc() == 7
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0] use(+1) == 8
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0x80008570][ffff880212c08300] inc() == 9
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0] inc() == 10
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857a][ffff88021327dc80] created
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0xc000857a][ffff88021327dc80] use(+1) == 1
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857a][ffff88021327dc80] initialising...
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0x80008570][ffff880212c08300] use(+1) == 7
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0] use(+1) == 9
>[  +0,000007] nouveau T[   PDISP][0000:01:00.0][0xc000857a][ffff88021327dc80] initialised
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0xc000857a][ffff88021327dc80] inc() == 2
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857a][ffff88021327dc80] use(+1) == 2
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857a][ffff88021327dc80] use(-1) == 1
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0xc000857a][ffff88021327dc80] dec() == 1
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0x80008570][ffff880212c08300] dec() == 8
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0] use(-1) == 8
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0x80008570][ffff880212c08300] dec() == 7
>[  +0,000015] nouveau T[   PDISP][0000:01:00.0][0x80008570][ffff880212c08300] inc() == 8
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0] use(+1) == 9
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0x80008570][ffff880212c08300] inc() == 10
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0] inc() == 11
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327dd80] created
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327dd80] use(+1) == 1
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327dd80] initialising...
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0x80008570][ffff880212c08300] use(+1) == 8
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0] use(+1) == 10
>[  +0,000007] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327dd80] initialised
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327dd80] inc() == 2
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327dd80] use(+1) == 2
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327dd80] use(-1) == 1
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327dd80] dec() == 1
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0x80008570][ffff880212c08300] dec() == 9
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0] use(-1) == 9
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0x80008570][ffff880212c08300] dec() == 8
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327dd80] inc() == 2
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327dd80] inc() == 3
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327dd80] inc() == 4
>[  +0,000005] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327dd80] use(+1) == 2
>[  +0,000008] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327dd80] dec() == 3
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327dd80] dec() == 2
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327dd80] inc() == 3
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327dd80] inc() == 4
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327dd80] inc() == 5
>[  +0,000005] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327dd80] use(+1) == 3
>[  +0,000008] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327dd80] dec() == 4
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327dd80] dec() == 3
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327dd80] inc() == 4
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327dd80] inc() == 5
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327dd80] inc() == 6
>[  +0,000005] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327dd80] use(+1) == 4
>[  +0,000008] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327dd80] dec() == 5
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327dd80] dec() == 4
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327dd80] inc() == 5
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327dd80] inc() == 6
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327dd80] inc() == 7
>[  +0,000006] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327dd80] use(+1) == 5
>[  +0,000008] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327dd80] dec() == 6
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327dd80] dec() == 5
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327dd80] inc() == 6
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327dd80] inc() == 7
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327dd80] inc() == 8
>[  +0,000005] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327dd80] use(+1) == 6
>[  +0,000008] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327dd80] dec() == 7
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0xc000857c][ffff88021327dd80] dec() == 6
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0x80008570][ffff880212c08300] inc() == 9
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0] use(+1) == 10
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0x80008570][ffff880212c08300] inc() == 11
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0] inc() == 12
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857b][ffff880213c08100] created
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857b][ffff880213c08100] use(+1) == 1
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0xc000857b][ffff880213c08100] initialising...
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0x80008570][ffff880212c08300] use(+1) == 9
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0] use(+1) == 11
>[  +0,000007] nouveau T[   PDISP][0000:01:00.0][0xc000857b][ffff880213c08100] initialised
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857b][ffff880213c08100] inc() == 2
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857b][ffff880213c08100] use(+1) == 2
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857b][ffff880213c08100] use(-1) == 1
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0xc000857b][ffff880213c08100] dec() == 1
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0x80008570][ffff880212c08300] dec() == 10
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0] use(-1) == 10
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0x80008570][ffff880212c08300] dec() == 9
>[  +0,000006] nouveau T[   PDISP][0000:01:00.0][0x80008570][ffff880212c08300] inc() == 10
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0] use(+1) == 11
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0x80008570][ffff880212c08300] inc() == 12
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0] inc() == 13
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff880213c08180] created
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff880213c08180] use(+1) == 1
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff880213c08180] initialising...
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0x80008570][ffff880212c08300] use(+1) == 10
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0] use(+1) == 12
>[  +0,000007] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff880213c08180] initialised
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff880213c08180] inc() == 2
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff880213c08180] use(+1) == 2
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff880213c08180] use(-1) == 1
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff880213c08180] dec() == 1
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0x80008570][ffff880212c08300] dec() == 11
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0] use(-1) == 11
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0x80008570][ffff880212c08300] dec() == 10
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff880213c08180] inc() == 2
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff880213c08180] inc() == 3
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff880213c08180] inc() == 4
>[  +0,000005] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff880213c08180] use(+1) == 2
>[  +0,000008] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff880213c08180] dec() == 3
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff880213c08180] dec() == 2
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff880213c08180] inc() == 3
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff880213c08180] inc() == 4
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff880213c08180] inc() == 5
>[  +0,000005] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff880213c08180] use(+1) == 3
>[  +0,000008] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff880213c08180] dec() == 4
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff880213c08180] dec() == 3
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff880213c08180] inc() == 4
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff880213c08180] inc() == 5
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff880213c08180] inc() == 6
>[  +0,000005] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff880213c08180] use(+1) == 4
>[  +0,000007] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff880213c08180] dec() == 5
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff880213c08180] dec() == 4
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff880213c08180] inc() == 5
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff880213c08180] inc() == 6
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff880213c08180] inc() == 7
>[  +0,000005] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff880213c08180] use(+1) == 5
>[  +0,000007] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff880213c08180] dec() == 6
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff880213c08180] dec() == 5
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff880213c08180] inc() == 6
>[  +0,000001] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff880213c08180] inc() == 7
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff880213c08180] inc() == 8
>[  +0,000005] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff880213c08180] use(+1) == 6
>[  +0,000007] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff880213c08180] dec() == 7
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0][0xc000857e][ffff880213c08180] dec() == 6
>[  +0,000084] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
>[  +0,000084] [drm] Driver supports precise vblank timestamp query.
>[  +0,038700] nouveau  [     DRM] MM: using COPY for buffer copies
>[  +0,000206] nouveau D[   PDISP][0000:01:00.0] supervisor 0x00000010 0x000002a0
>[  +0,000006] nouveau D[   PDISP][0000:01:00.0] Core:
>[  +0,000006] nouveau D[   PDISP][0000:01:00.0] 	0x0084: 0x019e02e2 -> 0x80000000
>[  +0,000006] nouveau D[   PDISP][0000:01:00.0] 	0x0088: 0x00000000 -> 0xcafe0000
>[  +0,000004] nouveau D[   PDISP][0000:01:00.0] Core - DAC 0:
>[  +0,000006] nouveau D[   PDISP][0000:01:00.0] 	0x0400: 0x00000000              
>[  +0,000005] nouveau D[   PDISP][0000:01:00.0] 	0x0404: 0x00000000              
>[  +0,000005] nouveau D[   PDISP][0000:01:00.0] 	0x0420: 0x00010000              
>[  +0,000004] nouveau D[   PDISP][0000:01:00.0] Core - DAC 1:
>[  +0,000005] nouveau D[   PDISP][0000:01:00.0] 	0x0480: 0x00000000              
>[  +0,000006] nouveau D[   PDISP][0000:01:00.0] 	0x0484: 0x00000000              
>[  +0,000004] nouveau D[   PDISP][0000:01:00.0] 	0x04a0: 0x00010000              
>[  +0,000004] nouveau D[   PDISP][0000:01:00.0] Core - DAC 2:
>[  +0,000005] nouveau D[   PDISP][0000:01:00.0] 	0x0500: 0x00000000              
>[  +0,000005] nouveau D[   PDISP][0000:01:00.0] 	0x0504: 0x00000000              
>[  +0,000005] nouveau D[   PDISP][0000:01:00.0] 	0x0520: 0x00010000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] Core - SOR 0:
>[  +0,000007] nouveau D[   PDISP][0000:01:00.0] 	0x0600: 0x00002101 -> 0x00000000
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] Core - SOR 1:
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0640: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] Core - SOR 2:
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0680: 0x00000000              
>[  +0,000001] nouveau D[   PDISP][0000:01:00.0] Core - SOR 3:
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x06c0: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] Core - PIOR 0:
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0700: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] Core - PIOR 1:
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0740: 0x00000000              
>[  +0,000001] nouveau D[   PDISP][0000:01:00.0] Core - PIOR 2:
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0780: 0x00000000              
>[  +0,000001] nouveau D[   PDISP][0000:01:00.0] Core - HEAD 0:
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0800: 0x00000000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0804: 0x0281d0d8 -> 0x00000000
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0808: 0x00000000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x080c: 0x00000000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0810: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0814: 0x04380730 -> 0x00050008
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0818: 0x0005001f -> 0x00000001
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x081c: 0x001a006f -> 0x00010003
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0820: 0x043406ff -> 0x00030004
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0824: 0x02360650 -> 0x00000001
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0828: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x082c: 0x00000000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0830: 0x00000000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0838: 0x00000000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0840: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0844: 0x00000000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0848: 0x00000000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x084c: 0x00000000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x085c: 0x00000000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0860: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0864: 0x00000000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0868: 0x00000000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x086c: 0x00000000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0870: 0x0000e900              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0874: 0x00000000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0878: 0x00000000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0880: 0x20000000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0884: 0x00000000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x089c: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x08a0: 0x00000000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x08a4: 0x00000000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x08a8: 0x00040000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x08c0: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x08c4: 0x00000000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x08c8: 0x00000000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x08d4: 0x00000000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x08d8: 0x041a0690 -> 0x00000000
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x08dc: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0900: 0x00000300              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0904: 0x00000100              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0910: 0x00000000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0914: 0x00000000              
>[  +0,000001] nouveau D[   PDISP][0000:01:00.0] Core - HEAD 1:
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0c00: 0x00000000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0c04: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0c08: 0x00000000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0c0c: 0x00000000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0c10: 0x00000000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0c14: 0x00050008              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0c18: 0x00000001              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0c1c: 0x00010003              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0c20: 0x00030004              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0c24: 0x00000001              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0c28: 0x00000000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0c2c: 0x00000000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0c30: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0c38: 0x00000000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0c40: 0x00000000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0c44: 0x00000000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0c48: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0c4c: 0x00000000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0c5c: 0x00000000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0c60: 0x00000000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0c64: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0c68: 0x00000000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0c6c: 0x00000000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0c70: 0x0000e900              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0c74: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0c78: 0x00000000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0c80: 0x20000000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0c84: 0x00000000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0c9c: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0ca0: 0x00000000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0ca4: 0x00000000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0ca8: 0x00040000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0cc0: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0cc4: 0x00000000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0cc8: 0x00000000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0cd4: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0cd8: 0x00000000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0cdc: 0x00000000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0d00: 0x00000300              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0d04: 0x00000100              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0d10: 0x00000000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0d14: 0x00000000              
>[  +0,000006] nouveau T[   VBIOS][0000:01:00.0] 0xc4ca[0]: DONE
>[  +0,025132] nouveau D[   PDISP][0000:01:00.0] supervisor 0x00000020 0x000002b0
>[  +0,000008] nouveau T[   VBIOS][0000:01:00.0] 0xc4cb[0]: NV_REG	R[0x4061c00c] &= 0xfffffffe |= 0x00000001
>[  +0,000004] nouveau T[   VBIOS][0000:01:00.0] 0xc4d8[0]: NV_REG	R[0x4061c014] &= 0xff3fffff |= 0x00c00000
>[  +0,000003] nouveau T[   VBIOS][0000:01:00.0] 0xc4e5[0]: DONE
>[  +0,000020] nouveau D[   PDISP][0000:01:00.0] supervisor 0x00000040 0x000002b0
>[  +0,000058] nouveau D[     I2C][0000:01:00.0] PAD:X:00: -> PORT:00
>[  +0,000852] nouveau D[     I2C][0000:01:00.0] PAD:X:00: -> NULL
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] PAD:X:00: -> PORT:00
>[  +0,000851] nouveau D[     I2C][0000:01:00.0] PAD:X:00: -> NULL
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] PAD:X:00: -> PORT:00
>[  +0,026015] nouveau D[     I2C][0000:01:00.0] PAD:X:00: -> NULL
>[  +0,000016] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000000 8
>[  +0,000195] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109007 0x10000008
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01840a11
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00010000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 4: 0x00000050 1
>[  +0,000007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000130] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 1: 0x00000050 1
>[  +0,000136] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01101000 0x10000001
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01840a00
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00010000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 4: 0x00000050 1
>[  +0,000007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000131] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[  +0,000264] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xffffff00
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00ffffff
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x284cf022
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[  +0,000265] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0401150e
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x782034a5
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xa6c59e22
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x259a4b56
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[  +0,000265] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x21545013
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x40810008
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00958081
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00b340a9
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[  +0,000263] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0101c0d1
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x3c280101
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xb070a080
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x20304023
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[  +0,000265] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x44060036
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x1a000021
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xfd000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x183f3200
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[  +0,000265] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0a00114c
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x20202020
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00002020
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x4c00fc00
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[  +0,000265] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x30343241
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x20200a35
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x20202020
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xff000000
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 1: 0x00000050 16
>[  +0,000265] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110100f 0x10000010
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x344e4300
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x30343131
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0a324243
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x88002020
>[  +0,013220] nouveau  [     DRM] allocated 1920x1200 fb: 0x70000, bo ffff880212e46c00
>[  +0,000205] fbcon: nouveaufb (fb0) is primary device
>[  +0,001186] nouveau D[   PDISP][0000:01:00.0] supervisor 0x00000010 0x000002a0
>[  +0,000001] nouveau D[   PDISP][0000:01:00.0] Core:
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0084: 0x019e02e2 -> 0x00000000
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0088: 0xcafe0000              
>[  +0,000001] nouveau D[   PDISP][0000:01:00.0] Core - DAC 0:
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0400: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0404: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0420: 0x00010000              
>[  +0,000001] nouveau D[   PDISP][0000:01:00.0] Core - DAC 1:
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0480: 0x00000000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0484: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x04a0: 0x00010000              
>[  +0,000001] nouveau D[   PDISP][0000:01:00.0] Core - DAC 2:
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0500: 0x00000000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0504: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0520: 0x00010000              
>[  +0,000001] nouveau D[   PDISP][0000:01:00.0] Core - SOR 0:
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0600: 0x00000000 -> 0x00002101
>[  +0,000001] nouveau D[   PDISP][0000:01:00.0] Core - SOR 1:
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0640: 0x00000000              
>[  +0,000001] nouveau D[   PDISP][0000:01:00.0] Core - SOR 2:
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0680: 0x00000000              
>[  +0,000001] nouveau D[   PDISP][0000:01:00.0] Core - SOR 3:
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x06c0: 0x00000000              
>[  +0,000001] nouveau D[   PDISP][0000:01:00.0] Core - PIOR 0:
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0700: 0x00000000              
>[  +0,000001] nouveau D[   PDISP][0000:01:00.0] Core - PIOR 1:
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0740: 0x00000000              
>[  +0,000001] nouveau D[   PDISP][0000:01:00.0] Core - PIOR 2:
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0780: 0x00000000              
>[  +0,000001] nouveau D[   PDISP][0000:01:00.0] Core - HEAD 0:
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0800: 0x00000000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0804: 0x00000000 -> 0x0081d0d8
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0808: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x080c: 0x00000000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0810: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0814: 0x00050008 -> 0x04380730
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0818: 0x00000001 -> 0x0005001f
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x081c: 0x00010003 -> 0x001a006f
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0820: 0x00030004 -> 0x043406ff
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0824: 0x00000001              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0828: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x082c: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0830: 0x00000000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0838: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0840: 0x00000000 -> 0xc0000000
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0844: 0x00000000 -> 0x00000610
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0848: 0x00000000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x084c: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x085c: 0x00000000 -> 0x01000000
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0860: 0x00000000 -> 0x00000700
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0864: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0868: 0x00000000 -> 0x04b00780
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x086c: 0x00000000 -> 0x00101e00
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0870: 0x0000e900 -> 0x0000cf00
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0874: 0x00000000 -> 0x01000003
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0878: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0880: 0x20000000 -> 0x05000000
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0884: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x089c: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x08a0: 0x00000000 -> 0x00000002
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x08a4: 0x00000000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x08a8: 0x00040000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x08c0: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x08c4: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x08c8: 0x00000000 -> 0x041a0690
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x08d4: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x08d8: 0x00000000 -> 0x041a0690
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x08dc: 0x00000000 -> 0x041a0690
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0900: 0x00000300 -> 0x00000311
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0904: 0x00000100              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0910: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0914: 0x00000000              
>[  +0,000001] nouveau D[   PDISP][0000:01:00.0] Core - HEAD 1:
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0c00: 0x00000000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0c04: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0c08: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0c0c: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0c10: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0c14: 0x00050008              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0c18: 0x00000001              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0c1c: 0x00010003              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0c20: 0x00030004              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0c24: 0x00000001              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0c28: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0c2c: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0c30: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0c38: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0c40: 0x00000000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0c44: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0c48: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0c4c: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0c5c: 0x00000000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0c60: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0c64: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0c68: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0c6c: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0c70: 0x0000e900              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0c74: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0c78: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0c80: 0x20000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0c84: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0c9c: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0ca0: 0x00000000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0ca4: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0ca8: 0x00040000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0cc0: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0cc4: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0cc8: 0x00000000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0cd4: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0cd8: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0cdc: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0d00: 0x00000300              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0d04: 0x00000100              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0d10: 0x00000000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0d14: 0x00000000              
>[  +0,000018] nouveau D[   PDISP][0000:01:00.0] supervisor 0x00000020 0x000002b0
>[  +0,000020] nouveau T[   VBIOS][0000:01:00.0] 0xc203[0]: ZM_REG_SEQUENCE	0x04
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc209[0]: 		R[0x61c00c] = 0x01000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc20d[0]: 		R[0x61c010] = 0x00101500
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc211[0]: 		R[0x61c014] = 0x00020000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc215[0]: 		R[0x61c018] = 0x00245af8
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc219[0]: ZM_REG_SEQUENCE	0x02
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc21f[0]: 		R[0x61c118] = 0x2a2a2a2a
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc223[0]: 		R[0x61c11c] = 0x0000002a
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc227[0]: ZM_REG_SEQUENCE	0x02
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc22d[0]: 		R[0x61c198] = 0x2a2a2a2a
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc231[0]: 		R[0x61c19c] = 0x0000002a
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc235[0]: NV_REG	R[0x61c120] &= 0x00000000 |= 0x00000000
>[  +0,000003] nouveau T[   VBIOS][0000:01:00.0] 0xc242[0]: NV_REG	R[0x61c1a0] &= 0x00000000 |= 0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc24f[0]: SUB_DIRECT	0xcb0f
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xcb0f[1]: DONE
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc252[0]: SUB_DIRECT	0xc2a9
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc2a9[1]: SUB_DIRECT	0xbb32
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xbb32[2]: SUB_DIRECT	0xc4e6
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc4e6[3]: ZM_REG_SEQUENCE	0x10
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc4ec[3]: 		R[0x4061c040] = 0x1f0b0000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc4f0[3]: 		R[0x4061c044] = 0x1f0a0000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc4f4[3]: 		R[0x4061c048] = 0x1e080000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc4f8[3]: 		R[0x4061c04c] = 0x1e042000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc4fc[3]: 		R[0x4061c050] = 0x00008000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc500[3]: 		R[0x4061c054] = 0x00008000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc504[3]: 		R[0x4061c058] = 0x00008000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc508[3]: 		R[0x4061c05c] = 0x00008000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc50c[3]: 		R[0x4061c060] = 0x00002000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc510[3]: 		R[0x4061c064] = 0x1f002000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc514[3]: 		R[0x4061c068] = 0x1f0c0000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc518[3]: 		R[0x4061c06c] = 0x1f0a0000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc51c[3]: 		R[0x4061c070] = 0x1f0b8000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc520[3]: 		R[0x4061c074] = 0x1f0b8000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc524[3]: 		R[0x4061c078] = 0x1f0b8000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc528[3]: 		R[0x4061c07c] = 0x1f0b8000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc52c[3]: DONE
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xbb35[2]: NV_REG	R[0x4061c130] &= 0x00000000 |= 0x00400600
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xbb42[2]: NV_REG	R[0x4061c1b0] &= 0x00000000 |= 0x00400600
>[  +0,000003] nouveau T[   VBIOS][0000:01:00.0] 0xbb4f[2]: NV_REG	R[0x40614300] &= 0xfcf3ffff |= 0x00040000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xbb5c[2]: DONE
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc2ac[1]: DONE
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc255[0]: DONE
>[  +0,000312] nouveau D[   PDISP][0000:01:00.0] supervisor 0x00000040 0x000002b0
>[  +0,000007] nouveau T[   VBIOS][0000:01:00.0] 0xbb5d[0]: SUB_DIRECT	0xbb75
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xbb75[1]: CONDITION_TIME	0x0b 0xff
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xbb78[1]: 	[0x0b] (R[0x4061c030] & 0x10000000) == 0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xbb78[1]: RESUME
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xbb79[1]: DONE
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xbb60[0]: SUB_DIRECT	0xbb7a
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xbb7a[1]: NV_REG	R[0x4061c10c] &= 0xfffffffe |= 0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xbb87[1]: DONE
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xbb63[0]: DONE
>[  +0,050034] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000100 2
>[  +0,000145] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109001 0x10000002
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x344e0000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x30343131
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0a324243
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x88002020
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000202 3
>[  +0,000151] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x34000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x30343131
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0a324243
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x88002020
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: no inter-lane alignment
>[  +0,000005] nouveau T[   VBIOS][0000:01:00.0] 0xc535[0]: NV_REG	R[0x004710] &= 0xf8ffffff |= 0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc542[0]: DP_CONDITION	0x01 0x10
>[  +0,000003] nouveau T[   VBIOS][0000:01:00.0] 0xc545[ ]: NV_REG	R[0x00e820] &= 0xfffffeff |= 0x00000100
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc552[ ]: IO_OR	0x03d4[0x86] |= (1 << 0x00)
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc554[ ]: RESUME
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc555[0]: DP_CONDITION	0x02 0x10
>[  +0,000003] nouveau T[   VBIOS][0000:01:00.0] 0xc558[0]: NV_REG	R[0x00e8a0] &= 0xfffffeff |= 0x00000100
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc565[0]: IO_OR	0x03d4[0x8e] |= (1 << 0x02)
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc567[0]: RESUME
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc568[0]: NV_REG	R[0x6061c10c] &= 0xffffbffe |= 0x00004001
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc575[0]: NV_REG	R[0x6061c128] &= 0x7fffffff |= 0x80000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc582[0]: NV_REG	R[0x40614300] &= 0xfcffffff |= 0x03000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc58f[0]: ZM_REG	R[0x4061c00c] = 0x01000300
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc598[0]: ZM_REG	R[0x4061c010] = 0x0030152f
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc5a1[0]: ZM_REG	R[0x4061c014] = 0x00020000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc5aa[0]: SUB_DIRECT	0x46bb
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0x46bb[1]: NV_REG	R[0x4061c010] &= 0xffffe1ff |= 0x00001000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0x46c8[1]: TIME	0x0064
>[  +0,000101] nouveau T[   VBIOS][0000:01:00.0] 0x46cb[1]: CONDITION	0x11
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0x46cd[1]: 	[0x11] (R[0x4061c010] & 0x00008000) == 0x00008000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0x46cd[1]: NV_REG	R[0x4061c010] &= 0xffffefff |= 0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0x46da[1]: RESUME
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0x46db[1]: NV_REG	R[0x4061c010] &= 0xfffff7ff |= 0x00000800
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0x46e8[1]: TIME	0x0064
>[  +0,000101] nouveau T[   VBIOS][0000:01:00.0] 0x46eb[1]: CONDITION	0x11
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0x46ed[1]: 	[0x11] (R[0x4061c010] & 0x00008000) == 0x00008000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0x46ed[1]: NV_REG	R[0x4061c010] &= 0xfffff7ff |= 0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0x46fa[1]: RESUME
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0x46fb[1]: NV_REG	R[0x4061c010] &= 0xfffffbff |= 0x00000400
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0x4708[1]: TIME	0x0064
>[  +0,000101] nouveau T[   VBIOS][0000:01:00.0] 0x470b[1]: CONDITION	0x11
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0x470d[1]: 	[0x11] (R[0x4061c010] & 0x00008000) == 0x00008000
>[  +0,000003] nouveau T[   VBIOS][0000:01:00.0] 0x470d[ ]: NV_REG	R[0x4061c010] &= 0xfffffbff |= 0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0x471a[ ]: RESUME
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0x471b[1]: NV_REG	R[0x4061c010] &= 0xfffffdff |= 0x00000200
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0x4728[1]: TIME	0x0064
>[  +0,000101] nouveau T[   VBIOS][0000:01:00.0] 0x472b[1]: CONDITION	0x11
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0x472d[1]: 	[0x11] (R[0x4061c010] & 0x00008000) == 0x00008000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0x472d[ ]: NV_REG	R[0x4061c010] &= 0xfffffdff |= 0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0x473a[ ]: RESUME
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0x473b[1]: DONE
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc5ad[0]: NV_REG	R[0x40614300] &= 0xfffcffff |= 0x00010000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc5ba[0]: NV_REG	R[0x6061c130] &= 0xffbfff00 |= 0x004000ff
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc5c7[0]: TIME	0x000a
>[  +0,000012] nouveau T[   VBIOS][0000:01:00.0] 0xc5ca[0]: NV_REG	R[0x6061c130] &= 0xffffff0f |= 0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc5d7[0]: NV_REG	R[0x6061c10c] &= 0xfcffcfff |= 0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc5e4[0]: AUXCH	AUX[0x00000600] 0x01
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc5ea[0]: 	AUX[0x00000600] &= 0xfc |= 0x01
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000600 1
>[  +0,000135] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x34000001
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x30343131
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0a324243
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x88002020
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000600 1
>[  +0,000006] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000001
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000131] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc5ec[0]: AUXCH	AUX[0x00000102] 0x01
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc5f2[0]: 	AUX[0x00000102] &= 0xdf |= 0x20
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000102 1
>[  +0,000135] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x34000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x30343131
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0a324243
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x88002020
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000102 1
>[  +0,000006] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000020
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000130] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc5f4[0]: DP_CONDITION	0x05 0x15
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x0000000d 1
>[  +0,000137] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x34000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x30343131
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0a324243
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x88002020
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc5f7[ ]: NV_REG	R[0x6061c140] &= 0xfffffffd |= 0x00000002
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc604[ ]: AUXCH	AUX[0x0000010a] 0x01
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc60a[ ]: 	AUX[0x0000010a] &= 0xfe |= 0x01
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc60c[ ]: DONE
>[  +0,000001] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: 0 lanes at 0 KB/s
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc62d[0]: ZM_REG	R[0x4061c00c] = 0x01000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc636[0]: DONE
>[  +0,000008] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000100 2
>[  +0,000006] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000139] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108001 0x10000000
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: training pattern 1
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000102 1
>[  +0,000135] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x34000020
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x30343131
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0a324243
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x88002020
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000102 1
>[  +0,000007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000021
>[  +0,000000] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000130] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000103 4
>[  +0,000007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000000] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000155] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108003 0x10000000
>[  +0,004008] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000202 6
>[  +0,000177] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00800000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x30343333
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0a324243
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x88002020
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: status 00 00 80 00 33 33
>[  +0,000001] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: training pattern 2
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000102 1
>[  +0,000136] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00800021
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x30343333
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0a324243
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x88002020
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000102 1
>[  +0,000006] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000022
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000132] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  +0,004007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000202 6
>[  +0,000177] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00800000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x3034bbbb
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0a324243
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x88002020
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: status 00 00 80 00 bb bb
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000103 4
>[  +0,000006] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000155] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108003 0x10000000
>[  +0,004007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000202 6
>[  +0,000178] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x3034bbbb
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0a324243
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x88002020
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: status 00 00 00 00 bb bb
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000103 4
>[  +0,000006] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000155] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108003 0x10000000
>[  +0,004007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000202 6
>[  +0,000178] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x3034bbbb
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0a324243
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x88002020
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: status 00 00 00 00 bb bb
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000103 4
>[  +0,000006] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000155] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108003 0x10000000
>[  +0,004007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000202 6
>[  +0,000177] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x3034bbbb
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0a324243
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x88002020
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: status 00 00 00 00 bb bb
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000103 4
>[  +0,000006] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000155] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108003 0x10000000
>[  +0,004007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000202 6
>[  +0,000177] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x3034bbbb
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0a324243
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x88002020
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: status 00 00 00 00 bb bb
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000103 4
>[  +0,000007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000000] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000156] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108003 0x10000000
>[  +0,004007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000202 6
>[  +0,000177] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x3034bbbb
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0a324243
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x88002020
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: status 00 00 00 00 bb bb
>[  +0,000001] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: 0 lanes at 0 KB/s
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc62d[0]: ZM_REG	R[0x4061c00c] = 0x01000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc636[0]: DONE
>[  +0,000007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000100 2
>[  +0,000007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000000] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000139] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108001 0x10000000
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: training pattern 1
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000102 1
>[  +0,000137] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000022
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x3034bbbb
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0a324243
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x88002020
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000102 1
>[  +0,000007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000021
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000000] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000130] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000103 4
>[  +0,000007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000000] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000156] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108003 0x10000000
>[  +0,004006] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000202 6
>[  +0,000178] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00800000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x30343333
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0a324243
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x88002020
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: status 00 00 80 00 33 33
>[  +0,000001] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: training pattern 2
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000102 1
>[  +0,000137] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00800021
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x30343333
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0a324243
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x88002020
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000102 1
>[  +0,000006] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000022
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000132] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  +0,004007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000202 6
>[  +0,000178] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00800000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x3034bbbb
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0a324243
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x88002020
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: status 00 00 80 00 bb bb
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000103 4
>[  +0,000006] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000155] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108003 0x10000000
>[  +0,004007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000202 6
>[  +0,000178] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x3034bbbb
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0a324243
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x88002020
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: status 00 00 00 00 bb bb
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000103 4
>[  +0,000006] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000155] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108003 0x10000000
>[  +0,004008] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000202 6
>[  +0,000177] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x3034bbbb
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0a324243
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x88002020
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: status 00 00 00 00 bb bb
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000103 4
>[  +0,000006] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000000] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000154] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108003 0x10000000
>[  +0,004007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000202 6
>[  +0,000177] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x3034bbbb
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0a324243
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x88002020
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: status 00 00 00 00 bb bb
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000103 4
>[  +0,000006] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000000] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000155] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108003 0x10000000
>[  +0,004007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000202 6
>[  +0,000177] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x3034bbbb
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0a324243
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x88002020
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: status 00 00 00 00 bb bb
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000103 4
>[  +0,000006] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000000] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000156] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108003 0x10000000
>[  +0,004007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000202 6
>[  +0,000177] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x3034bbbb
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0a324243
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x88002020
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: status 00 00 00 00 bb bb
>[  +0,000001] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: training pattern 0
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000102 1
>[  +0,000137] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000022
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x3034bbbb
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0a324243
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x88002020
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000102 1
>[  +0,000006] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000020
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000000] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000132] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  +0,000002] nouveau E[   PDISP][0000:01:00.0] 02:0006:0344: link training failed
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc60d[0]: NV_REG	R[0x6061c10c] &= 0xfcffcfff |= 0x00001000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc61a[0]: AUXCH	AUX[0x00000102] 0x01
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc620[0]: 	AUX[0x00000102] &= 0xdf |= 0x00
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000102 1
>[  +0,000135] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000020
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x3034bbbb
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0a324243
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x88002020
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000102 1
>[  +0,000006] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000130] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc622[0]: DONE
>[  +0,000001] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: training complete
>[  +0,000105] nouveau D[   PDISP][0000:01:00.0] supervisor 0x00000010 0x00000540
>[  +0,000001] nouveau D[   PDISP][0000:01:00.0] Core:
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0084: 0x019e02e2 -> 0x00000000
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0088: 0xcafe0000              
>[  +0,000001] nouveau D[   PDISP][0000:01:00.0] Core - DAC 0:
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0400: 0x00000000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0404: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0420: 0x00010000              
>[  +0,000001] nouveau D[   PDISP][0000:01:00.0] Core - DAC 1:
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0480: 0x00000000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0484: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x04a0: 0x00010000              
>[  +0,000001] nouveau D[   PDISP][0000:01:00.0] Core - DAC 2:
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0500: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0504: 0x00000000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0520: 0x00010000              
>[  +0,000001] nouveau D[   PDISP][0000:01:00.0] Core - SOR 0:
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0600: 0x00002101              
>[  +0,000000] nouveau D[   PDISP][0000:01:00.0] Core - SOR 1:
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0640: 0x00000000              
>[  +0,000001] nouveau D[   PDISP][0000:01:00.0] Core - SOR 2:
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0680: 0x00000000 -> 0x00052802
>[  +0,000001] nouveau D[   PDISP][0000:01:00.0] Core - SOR 3:
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x06c0: 0x00000000              
>[  +0,000001] nouveau D[   PDISP][0000:01:00.0] Core - PIOR 0:
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0700: 0x00000000              
>[  +0,000001] nouveau D[   PDISP][0000:01:00.0] Core - PIOR 1:
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0740: 0x00000000              
>[  +0,000001] nouveau D[   PDISP][0000:01:00.0] Core - PIOR 2:
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0780: 0x00000000              
>[  +0,000001] nouveau D[   PDISP][0000:01:00.0] Core - HEAD 0:
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0800: 0x00000000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0804: 0x0081d0d8              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0808: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x080c: 0x00000000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0810: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0814: 0x04380730              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0818: 0x0005001f              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x081c: 0x001a006f              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0820: 0x043406ff              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0824: 0x00000001              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0828: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x082c: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0830: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0838: 0x00000000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0840: 0xc0000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0844: 0x00000610              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0848: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x084c: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x085c: 0x01000000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0860: 0x00000700              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0864: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0868: 0x04b00780              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x086c: 0x00101e00              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0870: 0x0000cf00              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0874: 0x01000003              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0878: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0880: 0x05000000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0884: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x089c: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x08a0: 0x00000002              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x08a4: 0x00000000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x08a8: 0x00040000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x08c0: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x08c4: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x08c8: 0x041a0690              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x08d4: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x08d8: 0x041a0690              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x08dc: 0x041a0690              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0900: 0x00000311              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0904: 0x00000100              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0910: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0914: 0x00000000              
>[  +0,000001] nouveau D[   PDISP][0000:01:00.0] Core - HEAD 1:
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0c00: 0x00000000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0c04: 0x00000000 -> 0x00825990
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0c08: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0c0c: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0c10: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0c14: 0x00050008 -> 0x04d30820
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0c18: 0x00000001 -> 0x0005001f
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0c1c: 0x00010003 -> 0x001f006f
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0c20: 0x00030004 -> 0x04cf07ef
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0c24: 0x00000001              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0c28: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0c2c: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0c30: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0c38: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0c40: 0x00000000 -> 0xc0000000
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0c44: 0x00000000 -> 0x00000670
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0c48: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0c4c: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0c5c: 0x00000000 -> 0x01000000
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0c60: 0x00000000 -> 0x00000700
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0c64: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0c68: 0x00000000 -> 0x04b00780
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0c6c: 0x00000000 -> 0x00101e00
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0c70: 0x0000e900 -> 0x0000cf00
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0c74: 0x00000000 -> 0x01000003
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0c78: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0c80: 0x20000000 -> 0x05000000
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0c84: 0x00000000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0c9c: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0ca0: 0x00000000 -> 0x00000002
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0ca4: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0ca8: 0x00040000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0cc0: 0x00000000              
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0cc4: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0cc8: 0x00000000 -> 0x04b00780
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0cd4: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0cd8: 0x00000000 -> 0x04b00780
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 	0x0cdc: 0x00000000 -> 0x04b00780
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0d00: 0x00000300 -> 0x00000311
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0d04: 0x00000100              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0d10: 0x00000000              
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 	0x0d14: 0x00000000              
>[  +0,000019] nouveau D[   PDISP][0000:01:00.0] supervisor 0x00000020 0x00000550
>[  +0,000018] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000100 2
>[  +0,000145] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109001 0x10000002
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x3034bbbb
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0a324243
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x88002020
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: link not trained at sufficient rate
>[  +0,000005] nouveau T[   VBIOS][0000:01:00.0] 0xc535[0]: NV_REG	R[0x004710] &= 0xf8ffffff |= 0x00000000
>[  +0,000003] nouveau T[   VBIOS][0000:01:00.0] 0xc542[0]: DP_CONDITION	0x01 0x10
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc545[ ]: NV_REG	R[0x00e820] &= 0xfffffeff |= 0x00000100
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc552[ ]: IO_OR	0x03d4[0x86] |= (1 << 0x00)
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc554[ ]: RESUME
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc555[0]: DP_CONDITION	0x02 0x10
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc558[0]: NV_REG	R[0x00e8a0] &= 0xfffffeff |= 0x00000100
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc565[0]: IO_OR	0x03d4[0x8e] |= (1 << 0x02)
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc567[0]: RESUME
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc568[0]: NV_REG	R[0x6061c10c] &= 0xffffbffe |= 0x00004001
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc575[0]: NV_REG	R[0x6061c128] &= 0x7fffffff |= 0x80000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc582[0]: NV_REG	R[0x40614300] &= 0xfcffffff |= 0x03000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc58f[0]: ZM_REG	R[0x4061c00c] = 0x01000300
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc598[0]: ZM_REG	R[0x4061c010] = 0x0030152f
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc5a1[0]: ZM_REG	R[0x4061c014] = 0x00020000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc5aa[0]: SUB_DIRECT	0x46bb
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0x46bb[1]: NV_REG	R[0x4061c010] &= 0xffffe1ff |= 0x00001000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0x46c8[1]: TIME	0x0064
>[  +0,000101] nouveau T[   VBIOS][0000:01:00.0] 0x46cb[1]: CONDITION	0x11
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0x46cd[1]: 	[0x11] (R[0x4061c010] & 0x00008000) == 0x00008000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0x46cd[1]: NV_REG	R[0x4061c010] &= 0xffffefff |= 0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0x46da[1]: RESUME
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0x46db[1]: NV_REG	R[0x4061c010] &= 0xfffff7ff |= 0x00000800
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0x46e8[1]: TIME	0x0064
>[  +0,000102] nouveau T[   VBIOS][0000:01:00.0] 0x46eb[1]: CONDITION	0x11
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0x46ed[1]: 	[0x11] (R[0x4061c010] & 0x00008000) == 0x00008000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0x46ed[1]: NV_REG	R[0x4061c010] &= 0xfffff7ff |= 0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0x46fa[1]: RESUME
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0x46fb[1]: NV_REG	R[0x4061c010] &= 0xfffffbff |= 0x00000400
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0x4708[1]: TIME	0x0064
>[  +0,000101] nouveau T[   VBIOS][0000:01:00.0] 0x470b[1]: CONDITION	0x11
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0x470d[1]: 	[0x11] (R[0x4061c010] & 0x00008000) == 0x00008000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0x470d[ ]: NV_REG	R[0x4061c010] &= 0xfffffbff |= 0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0x471a[ ]: RESUME
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0x471b[1]: NV_REG	R[0x4061c010] &= 0xfffffdff |= 0x00000200
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0x4728[1]: TIME	0x0064
>[  +0,000101] nouveau T[   VBIOS][0000:01:00.0] 0x472b[1]: CONDITION	0x11
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0x472d[1]: 	[0x11] (R[0x4061c010] & 0x00008000) == 0x00008000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0x472d[ ]: NV_REG	R[0x4061c010] &= 0xfffffdff |= 0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0x473a[ ]: RESUME
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0x473b[1]: DONE
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc5ad[0]: NV_REG	R[0x40614300] &= 0xfffcffff |= 0x00010000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc5ba[0]: NV_REG	R[0x6061c130] &= 0xffbfff00 |= 0x004000ff
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc5c7[0]: TIME	0x000a
>[  +0,000011] nouveau T[   VBIOS][0000:01:00.0] 0xc5ca[0]: NV_REG	R[0x6061c130] &= 0xffffff0f |= 0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc5d7[0]: NV_REG	R[0x6061c10c] &= 0xfcffcfff |= 0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc5e4[0]: AUXCH	AUX[0x00000600] 0x01
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc5ea[0]: 	AUX[0x00000600] &= 0xfc |= 0x01
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000600 1
>[  +0,000136] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000001
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x3034bbbb
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0a324243
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x88002020
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000600 1
>[  +0,000006] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000001
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000131] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc5ec[0]: AUXCH	AUX[0x00000102] 0x01
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc5f2[0]: 	AUX[0x00000102] &= 0xdf |= 0x20
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000102 1
>[  +0,000135] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x3034bbbb
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0a324243
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x88002020
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000102 1
>[  +0,000006] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000020
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000130] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc5f4[0]: DP_CONDITION	0x05 0x15
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x0000000d 1
>[  +0,000136] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x3034bbbb
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0a324243
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x88002020
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc5f7[ ]: NV_REG	R[0x6061c140] &= 0xfffffffd |= 0x00000002
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc604[ ]: AUXCH	AUX[0x0000010a] 0x01
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc60a[ ]: 	AUX[0x0000010a] &= 0xfe |= 0x01
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc60c[ ]: DONE
>[  +0,000001] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: 0 lanes at 0 KB/s
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc62d[0]: ZM_REG	R[0x4061c00c] = 0x01000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc636[0]: DONE
>[  +0,000008] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000100 2
>[  +0,000007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000000] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000140] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108001 0x10000000
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: training pattern 1
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000102 1
>[  +0,000136] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000020
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x3034bbbb
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0a324243
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x88002020
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000102 1
>[  +0,000007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000021
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000000] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000132] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000103 4
>[  +0,000006] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000155] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108003 0x10000000
>[  +0,004007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000202 6
>[  +0,000176] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00800000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x30343333
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0a324243
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x88002020
>[  +0,000003] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: status 00 00 80 00 33 33
>[  +0,000001] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: training pattern 2
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000102 1
>[  +0,000135] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00800021
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x30343333
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0a324243
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x88002020
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000102 1
>[  +0,000006] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000022
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000130] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  +0,004007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000202 6
>[  +0,000177] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00800000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x3034bbbb
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0a324243
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x88002020
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: status 00 00 80 00 bb bb
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000103 4
>[  +0,000007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000000] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000154] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108003 0x10000000
>[  +0,004007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000202 6
>[  +0,000176] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x3034bbbb
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0a324243
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x88002020
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: status 00 00 00 00 bb bb
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000103 4
>[  +0,000006] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000155] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108003 0x10000000
>[  +0,004007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000202 6
>[  +0,000177] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x3034bbbb
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0a324243
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x88002020
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: status 00 00 00 00 bb bb
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000103 4
>[  +0,000006] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000154] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108003 0x10000000
>[  +0,004007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000202 6
>[  +0,000176] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x3034bbbb
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0a324243
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x88002020
>[  +0,000001] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: status 00 00 00 00 bb bb
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000103 4
>[  +0,000006] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000000] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000155] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108003 0x10000000
>[  +0,004007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000202 6
>[  +0,000176] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x3034bbbb
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0a324243
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x88002020
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: status 00 00 00 00 bb bb
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000103 4
>[  +0,000007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000000] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000155] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108003 0x10000000
>[  +0,004007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000202 6
>[  +0,000176] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x3034bbbb
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0a324243
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x88002020
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: status 00 00 00 00 bb bb
>[  +0,000001] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: 0 lanes at 0 KB/s
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc62d[0]: ZM_REG	R[0x4061c00c] = 0x01000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc636[0]: DONE
>[  +0,000009] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000100 2
>[  +0,000007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000000] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000140] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108001 0x10000000
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: training pattern 1
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000102 1
>[  +0,000135] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000022
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x3034bbbb
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0a324243
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x88002020
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000102 1
>[  +0,000007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000021
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000000] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000132] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000103 4
>[  +0,000006] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000154] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108003 0x10000000
>[  +0,004007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000202 6
>[  +0,000177] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00800000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x30343333
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0a324243
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x88002020
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: status 00 00 80 00 33 33
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: training pattern 2
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000102 1
>[  +0,000136] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00800021
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x30343333
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0a324243
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x88002020
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000102 1
>[  +0,000006] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000022
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000130] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  +0,004007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000202 6
>[  +0,000176] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00800000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x3034bbbb
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0a324243
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x88002020
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: status 00 00 80 00 bb bb
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000103 4
>[  +0,000006] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000154] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108003 0x10000000
>[  +0,004007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000202 6
>[  +0,000178] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x3034bbbb
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0a324243
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x88002020
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: status 00 00 00 00 bb bb
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000103 4
>[  +0,000007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000000] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000155] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108003 0x10000000
>[  +0,004007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000202 6
>[  +0,000176] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x3034bbbb
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0a324243
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x88002020
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: status 00 00 00 00 bb bb
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000103 4
>[  +0,000006] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000154] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108003 0x10000000
>[  +0,004007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000202 6
>[  +0,000178] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x3034bbbb
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0a324243
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x88002020
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: status 00 00 00 00 bb bb
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000103 4
>[  +0,000006] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000155] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108003 0x10000000
>[  +0,004007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000202 6
>[  +0,000177] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x3034bbbb
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0a324243
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x88002020
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: status 00 00 00 00 bb bb
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000103 4
>[  +0,000006] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000155] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108003 0x10000000
>[  +0,004007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000202 6
>[  +0,000176] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x3034bbbb
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0a324243
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x88002020
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: status 00 00 00 00 bb bb
>[  +0,000001] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: training pattern 0
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000102 1
>[  +0,000137] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000022
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x3034bbbb
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0a324243
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x88002020
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000102 1
>[  +0,000007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000020
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000000] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000131] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  +0,000002] nouveau E[   PDISP][0000:01:00.0] 02:0006:0344: link training failed
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc60d[0]: NV_REG	R[0x6061c10c] &= 0xfcffcfff |= 0x00001000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc61a[0]: AUXCH	AUX[0x00000102] 0x01
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc620[0]: 	AUX[0x00000102] &= 0xdf |= 0x00
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000102 1
>[  +0,000135] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000020
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x3034bbbb
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0a324243
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x88002020
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000102 1
>[  +0,000006] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000130] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc622[0]: DONE
>[  +0,000001] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: training complete
>[  +0,000010] nouveau T[   VBIOS][0000:01:00.0] 0xc840[0]: SUB_DIRECT	0xc637
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc637[1]: SUB_DIRECT	0xc9fe
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc9fe[2]: ZM_REG_SEQUENCE	0x10
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xca04[2]: 		R[0x4061c040] = 0x00001032
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xca08[2]: 		R[0x4061c044] = 0x0040a000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xca0c[2]: 		R[0x4061c048] = 0x00408000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xca10[2]: 		R[0x4061c04c] = 0x00408000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xca14[2]: 		R[0x4061c050] = 0x00408000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xca18[2]: 		R[0x4061c054] = 0x00408000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xca1c[2]: 		R[0x4061c058] = 0x00408000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xca20[2]: 		R[0x4061c05c] = 0x00408000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xca24[2]: 		R[0x4061c060] = 0x00002000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xca28[2]: 		R[0x4061c064] = 0x000090c8
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xca2c[2]: 		R[0x4061c068] = 0x00008000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xca30[2]: 		R[0x4061c06c] = 0x00008000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xca34[2]: 		R[0x4061c070] = 0x00008000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xca38[2]: 		R[0x4061c074] = 0x00008000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xca3c[2]: 		R[0x4061c078] = 0x00008000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xca40[2]: 		R[0x4061c07c] = 0x00008000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xca44[2]: DONE
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc63a[1]: NV_REG	R[0x6061c128] &= 0xfbffffff |= 0x04000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc647[1]: DONE
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc843[0]: DP_CONDITION	0x00 0x0d
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc846[ ]: NV_REG	R[0x00e1e4] &= 0xfffffffc |= 0x00000002
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc853[ ]: DONE
>[  +0,450431] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: HPD: 2
>[  +0,000014] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000000 16
>[  +0,000007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): sink not detected
>[  +0,000004] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: aux power -> demand
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] PAD:S:01: -> NULL
>[  +0,001218] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: HPD: 1
>[  +0,000013] nouveau D[     I2C][0000:01:00.0] PAD:S:01: -> PORT:0b
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000000 16
>[  +0,000258] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110900f 0x10000010
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01840a11
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00010000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00060202
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: aux power -> always
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000100 2
>[  +0,000146] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109001 0x10000002
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01840000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00010000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00060202
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000202 3
>[  +0,000154] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00010000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00060202
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: no inter-lane alignment
>[  +0,000049] nouveau T[   VBIOS][0000:01:00.0] 0xc535[0]: NV_REG	R[0x004710] &= 0xf8ffffff |= 0x00000000
>[  +0,000003] nouveau T[   VBIOS][0000:01:00.0] 0xc542[0]: DP_CONDITION	0x01 0x10
>[  +0,000003] nouveau T[   VBIOS][0000:01:00.0] 0xc545[ ]: NV_REG	R[0x00e820] &= 0xfffffeff |= 0x00000100
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc552[ ]: IO_OR	0x03d4[0x86] |= (1 << 0x00)
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc554[ ]: RESUME
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc555[0]: DP_CONDITION	0x02 0x10
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc558[0]: NV_REG	R[0x00e8a0] &= 0xfffffeff |= 0x00000100
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc565[0]: IO_OR	0x03d4[0x8e] |= (1 << 0x02)
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc567[0]: RESUME
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc568[0]: NV_REG	R[0x6061c10c] &= 0xffffbffe |= 0x00004001
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc575[0]: NV_REG	R[0x6061c128] &= 0x7fffffff |= 0x80000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc582[0]: NV_REG	R[0x40614300] &= 0xfcffffff |= 0x03000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc58f[0]: ZM_REG	R[0x4061c00c] = 0x01000300
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc598[0]: ZM_REG	R[0x4061c010] = 0x0030152f
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc5a1[0]: ZM_REG	R[0x4061c014] = 0x00020000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc5aa[0]: SUB_DIRECT	0x46bb
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0x46bb[1]: NV_REG	R[0x4061c010] &= 0xffffe1ff |= 0x00001000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0x46c8[1]: TIME	0x0064
>[  +0,000102] nouveau T[   VBIOS][0000:01:00.0] 0x46cb[1]: CONDITION	0x11
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0x46cd[1]: 	[0x11] (R[0x4061c010] & 0x00008000) == 0x00008000
>[  +0,000003] nouveau T[   VBIOS][0000:01:00.0] 0x46cd[1]: NV_REG	R[0x4061c010] &= 0xffffefff |= 0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0x46da[1]: RESUME
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0x46db[1]: NV_REG	R[0x4061c010] &= 0xfffff7ff |= 0x00000800
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0x46e8[1]: TIME	0x0064
>[  +0,000101] nouveau T[   VBIOS][0000:01:00.0] 0x46eb[1]: CONDITION	0x11
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0x46ed[1]: 	[0x11] (R[0x4061c010] & 0x00008000) == 0x00008000
>[  +0,000003] nouveau T[   VBIOS][0000:01:00.0] 0x46ed[1]: NV_REG	R[0x4061c010] &= 0xfffff7ff |= 0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0x46fa[1]: RESUME
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0x46fb[1]: NV_REG	R[0x4061c010] &= 0xfffffbff |= 0x00000400
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0x4708[1]: TIME	0x0064
>[  +0,000101] nouveau T[   VBIOS][0000:01:00.0] 0x470b[1]: CONDITION	0x11
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0x470d[1]: 	[0x11] (R[0x4061c010] & 0x00008000) == 0x00008000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0x470d[ ]: NV_REG	R[0x4061c010] &= 0xfffffbff |= 0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0x471a[ ]: RESUME
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0x471b[1]: NV_REG	R[0x4061c010] &= 0xfffffdff |= 0x00000200
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0x4728[1]: TIME	0x0064
>[  +0,000101] nouveau T[   VBIOS][0000:01:00.0] 0x472b[1]: CONDITION	0x11
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0x472d[1]: 	[0x11] (R[0x4061c010] & 0x00008000) == 0x00008000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0x472d[ ]: NV_REG	R[0x4061c010] &= 0xfffffdff |= 0x00000000
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0x473a[ ]: RESUME
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0x473b[1]: DONE
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc5ad[0]: NV_REG	R[0x40614300] &= 0xfffcffff |= 0x00010000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc5ba[0]: NV_REG	R[0x6061c130] &= 0xffbfff00 |= 0x004000ff
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc5c7[0]: TIME	0x000a
>[  +0,000011] nouveau T[   VBIOS][0000:01:00.0] 0xc5ca[0]: NV_REG	R[0x6061c130] &= 0xffffff0f |= 0x00000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc5d7[0]: NV_REG	R[0x6061c10c] &= 0xfcffcfff |= 0x00000000
>[  +0,000003] nouveau T[   VBIOS][0000:01:00.0] 0xc5e4[0]: AUXCH	AUX[0x00000600] 0x01
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc5ea[0]: 	AUX[0x00000600] &= 0xfc |= 0x01
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000600 1
>[  +0,000137] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01000001
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00010000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00060202
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000600 1
>[  +0,000006] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000001
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000131] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc5ec[0]: AUXCH	AUX[0x00000102] 0x01
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc5f2[0]: 	AUX[0x00000102] &= 0xdf |= 0x20
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000102 1
>[  +0,000137] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00010000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00060202
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000102 1
>[  +0,000006] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000020
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000000] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000132] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc5f4[0]: DP_CONDITION	0x05 0x15
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x0000000d 1
>[  +0,000137] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00010000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00060202
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[  +0,000003] nouveau T[   VBIOS][0000:01:00.0] 0xc5f7[ ]: NV_REG	R[0x6061c140] &= 0xfffffffd |= 0x00000002
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc604[ ]: AUXCH	AUX[0x0000010a] 0x01
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc60a[ ]: 	AUX[0x0000010a] &= 0xfe |= 0x01
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc60c[ ]: DONE
>[  +0,000001] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: 4 lanes at 270000 KB/s
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc623[0]: ZM_REG	R[0x4061c00c] = 0x01000300
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc62c[0]: DONE
>[  +0,000008] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000100 2
>[  +0,000006] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x0000840a
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000139] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108001 0x10000000
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: training pattern 1
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000102 1
>[  +0,000135] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01000020
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00010000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00060202
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000102 1
>[  +0,000007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000021
>[  +0,000000] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000130] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: config lane 0 00 00
>[  +0,000005] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: config lane 1 00 00
>[  +0,000004] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: config lane 2 00 00
>[  +0,000005] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: config lane 3 00 00
>[  +0,000005] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000103 4
>[  +0,000006] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000154] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108003 0x10000000
>[  +0,000102] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000202 6
>[  +0,000177] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00801111
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00011111
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00060202
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: status 11 11 80 00 11 11
>[  +0,000001] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: training pattern 2
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000102 1
>[  +0,000137] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00801121
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00011111
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00060202
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000102 1
>[  +0,000006] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000022
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000000] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000132] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  +0,000402] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000202 6
>[  +0,000177] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109005 0x10000006
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01817777
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00011111
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00060202
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[  +0,000002] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: status 77 77 81 01 11 11
>[  +0,000001] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: training pattern 0
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000102 1
>[  +0,000137] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01817722
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00011111
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00060202
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000102 1
>[  +0,000006] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000020
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000000] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000131] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  +0,000003] nouveau T[   VBIOS][0000:01:00.0] 0xc60d[0]: NV_REG	R[0x6061c10c] &= 0xfcffcfff |= 0x00001000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc61a[0]: AUXCH	AUX[0x00000102] 0x01
>[  +0,000001] nouveau T[   VBIOS][0000:01:00.0] 0xc620[0]: 	AUX[0x00000102] &= 0xdf |= 0x00
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000102 1
>[  +0,000136] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109000 0x10000001
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01817720
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00011111
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00060202
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000102 1
>[  +0,000007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000000] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000130] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  +0,000002] nouveau T[   VBIOS][0000:01:00.0] 0xc622[0]: DONE
>[  +0,000001] nouveau D[   PDISP][0000:01:00.0] 02:0006:0344: training complete
>[  +0,082388] pps_core: LinuxPPS API ver. 1 registered
>[  +0,000000] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
>[  +0,113680] microcode: CPU0 sig=0x106e5, pf=0x2, revision=0x4
>[  +0,010066] EDAC MC: Ver: 3.0.0
>[  +0,015322] PTP clock support registered
>[  +0,139439] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
>[  +0,000000] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
>[  +0,035029] microcode: CPU1 sig=0x106e5, pf=0x2, revision=0x4
>[  +0,000011] microcode: CPU2 sig=0x106e5, pf=0x2, revision=0x4
>[  +0,000010] microcode: CPU3 sig=0x106e5, pf=0x2, revision=0x4
>[  +0,000011] microcode: CPU4 sig=0x106e5, pf=0x2, revision=0x4
>[  +0,000011] microcode: CPU5 sig=0x106e5, pf=0x2, revision=0x4
>[  +0,000013] microcode: CPU6 sig=0x106e5, pf=0x2, revision=0x4
>[  +0,000009] microcode: CPU7 sig=0x106e5, pf=0x2, revision=0x4
>[  +0,000042] microcode: Microcode Update Driver: v2.00 <tigran@aivazian.fsnet.co.uk>, Peter Oruba
>[  +0,005695] tpm_tis 00:04: 1.2 TPM (device-id 0xB, rev-id 16)
>[  +0,044798] EDAC MC0: Giving out device to module i7core_edac.c controller i7 core #0: DEV 0000:3f:03.0 (POLLED)
>[  +0,000035] EDAC PCI0: Giving out device to module i7core_edac controller EDAC PCI controller: DEV 0000:3f:03.0 (POLLED)
>[  +0,000004] EDAC i7core: Driver loaded, 1 memory controller(s) found.
>[  +0,130285] ppdev: user-space parallel port driver
>[  +0,033007] tpm_tis 00:04: TPM is disabled/deactivated (0x7)
>[  +0,034753] kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL does not work properly. Using workaround
>[  +0,635900] input: HP WMI hotkeys as /devices/virtual/input/input8
>[  +0,201371] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000600 1
>[  +0,000007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000001
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000132] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  +0,002042] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000100 2
>[  +0,000144] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109001 0x10000002
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0181840a
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00011111
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00060202
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000202 3
>[  +0,000153] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01017777
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00011111
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00060202
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[  +0,000076] nouveau D[     I2C][0000:01:00.0] PAD:X:00: -> PORT:00
>[  +0,000853] nouveau D[     I2C][0000:01:00.0] PAD:X:00: -> NULL
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] PAD:X:00: -> PORT:00
>[  +0,000851] nouveau D[     I2C][0000:01:00.0] PAD:X:00: -> NULL
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] PAD:X:00: -> PORT:00
>[  +0,000054] Console: switching to colour frame buffer device 210x65
>[  +0,026095] nouveau D[     I2C][0000:01:00.0] PAD:X:00: -> NULL
>[  +0,000005] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000000 8
>[  +0,000192] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109007 0x10000008
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01840a11
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00010000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00060202
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 4: 0x00000050 1
>[  +0,000006] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000129] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 1: 0x00000050 1
>[  +0,000134] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01101000 0x10000001
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01840a00
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00010000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00060202
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 4: 0x00000050 1
>[  +0,000006] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000000] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000130] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[  +0,000264] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xffffff00
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00ffffff
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x284cf022
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[  +0,000265] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0401150e
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x782034a5
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xa6c59e22
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x259a4b56
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[  +0,000264] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x21545013
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x40810008
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00958081
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00b340a9
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[  +0,000264] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0101c0d1
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x3c280101
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xb070a080
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x20304023
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[  +0,000264] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x44060036
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x1a000021
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xfd000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x183f3200
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[  +0,000263] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0a00114c
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x20202020
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00002020
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x4c00fc00
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[  +0,000262] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x30343241
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x20200a35
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x20202020
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xff000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 1: 0x00000050 16
>[  +0,000262] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110100f 0x10000010
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x344e4300
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x30343131
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0a324243
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x88002020
>[  +0,002663] nouveau 0000:01:00.0: fb0: nouveaufb frame buffer device
>[  +0,000002] nouveau 0000:01:00.0: registered panic notifier
>[  +0,046660] [drm] Initialized nouveau 1.1.1 20120801 for 0000:01:00.0 on minor 0
>[  +0,000142] shpchp: Standard Hot Plug PCI Controller Driver version: 0.4
>[  +0,000409] mei_me 0000:00:16.0: irq 55 for MSI/MSI-X
>[  +0,005152] e1000e 0000:00:19.0: Interrupt Throttling Rate (ints/sec) set to dynamic conservative mode
>[  +0,000024] e1000e 0000:00:19.0: irq 56 for MSI/MSI-X
>[  +0,055202] gpio_ich: GPIO from 180 to 255 on gpio_ich
>[  +0,011411] iTCO_vendor_support: vendor-support=0
>[  +0,132784] e1000e 0000:00:19.0 eth0: (PCI Express:2.5GT/s:Width x1) 78:e3:b5:9a:27:e0
>[  +0,000225] e1000e 0000:00:19.0 eth0: Intel(R) PRO/1000 Network Connection
>[  +0,000438] e1000e 0000:00:19.0 eth0: MAC: 9, PHY: 9, PBA No: A002FF-0FF
>[  +0,000870] snd_hda_intel 0000:01:00.1: Disabling MSI
>[  +0,000414] snd_hda_intel 0000:01:00.1: Handle VGA-switcheroo audio client
>[  +0,001037] snd_hda_intel 0000:00:1b.0: irq 57 for MSI/MSI-X
>[  +0,239287] iTCO_wdt: Intel TCO WatchDog Timer Driver v1.11
>[  +0,000264] iTCO_wdt: Found a Q57 TCO device (Version=2, TCOBASE=0xf860)
>[  +0,000562] iTCO_wdt: initialized. heartbeat=30 sec (nowayout=0)
>[  +0,078959] fuse init (API version 7.23)
>[  +0,049040] sound hdaudioC0D0: autoconfig: line_outs=1 (0x14/0x0/0x0/0x0/0x0) type:line
>[  +0,000538] sound hdaudioC0D0:    speaker_outs=1 (0x15/0x0/0x0/0x0/0x0)
>[  +0,000537] sound hdaudioC0D0:    hp_outs=1 (0x1b/0x0/0x0/0x0/0x0)
>[  +0,000461] sound hdaudioC0D0:    mono: mono_out=0x0
>[  +0,000628] sound hdaudioC0D0:    inputs:
>[  +0,000709] sound hdaudioC0D0:      Mic=0x19
>[  +0,000713] sound hdaudioC0D0:      Line=0x18
>[  +0,010364] input: HDA Intel MID Mic as /devices/pci0000:00/0000:00:1b.0/sound/card0/input9
>[  +0,000346] input: HDA Intel MID Line as /devices/pci0000:00/0000:00:1b.0/sound/card0/input10
>[  +0,000783] input: HDA Intel MID Line Out as /devices/pci0000:00/0000:00:1b.0/sound/card0/input11
>[  +0,000391] input: HDA Intel MID Front Headphone as /devices/pci0000:00/0000:00:1b.0/sound/card0/input12
>[  +0,122018] mousedev: PS/2 mouse device common for all mice
>[  +0,759415] systemd-journald[171]: Received request to flush runtime journal from PID 1
>[  +0,049396] input: HDA NVidia HDMI/DP,pcm=3 as /devices/pci0000:00/0000:00:03.0/0000:01:00.1/sound/card1/input13
>[  +0,000353] input: HDA NVidia HDMI/DP,pcm=7 as /devices/pci0000:00/0000:00:03.0/0000:01:00.1/sound/card1/input14
>[  +0,000630] input: HDA NVidia HDMI/DP,pcm=8 as /devices/pci0000:00/0000:00:03.0/0000:01:00.1/sound/card1/input15
>[  +0,000059] input: HDA NVidia HDMI/DP,pcm=9 as /devices/pci0000:00/0000:00:03.0/0000:01:00.1/sound/card1/input16
>[  +3,496538] e1000e 0000:00:19.0: irq 56 for MSI/MSI-X
>[  +0,102137] e1000e 0000:00:19.0: irq 56 for MSI/MSI-X
>[  +0,000162] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
>[  +3,368114] e1000e: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: Rx
>[  +0,000639] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
>[  +0,388520] nouveau D[     I2C][0000:01:00.0] PAD:X:00: -> PORT:00
>[  +0,000852] nouveau D[     I2C][0000:01:00.0] PAD:X:00: -> NULL
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] PAD:X:00: -> PORT:00
>[  +0,000850] nouveau D[     I2C][0000:01:00.0] PAD:X:00: -> NULL
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] PAD:X:00: -> PORT:00
>[  +0,025971] nouveau D[     I2C][0000:01:00.0] PAD:X:00: -> NULL
>[  +0,000042] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000000 8
>[  +0,000194] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109007 0x10000008
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01840a11
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00010000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0a324243
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x88002020
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 4: 0x00000050 1
>[  +0,000007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000130] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 1: 0x00000050 1
>[  +0,000135] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01101000 0x10000001
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01840a00
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00010000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0a324243
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x88002020
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 4: 0x00000050 1
>[  +0,000007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000130] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[  +0,000264] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xffffff00
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00ffffff
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x284cf022
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[  +0,000263] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0401150e
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x782034a5
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xa6c59e22
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x259a4b56
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[  +0,000264] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x21545013
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x40810008
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00958081
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00b340a9
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[  +0,000264] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0101c0d1
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x3c280101
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xb070a080
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x20304023
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[  +0,000264] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x44060036
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x1a000021
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xfd000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x183f3200
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[  +0,000265] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0a00114c
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x20202020
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00002020
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x4c00fc00
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[  +0,000264] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x30343241
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x20200a35
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x20202020
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xff000000
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 1: 0x00000050 16
>[  +0,000263] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110100f 0x10000010
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x344e4300
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x30343131
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0a324243
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x88002020
>[  +0,000031] nouveau D[     I2C][0000:01:00.0] PAD:X:00: -> PORT:00
>[  +0,000851] nouveau D[     I2C][0000:01:00.0] PAD:X:00: -> NULL
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] PAD:X:00: -> PORT:00
>[  +0,000849] nouveau D[     I2C][0000:01:00.0] PAD:X:00: -> NULL
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] PAD:X:00: -> PORT:00
>[  +0,025957] nouveau D[     I2C][0000:01:00.0] PAD:X:00: -> NULL
>[  +0,000322] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000000 8
>[  +0,000194] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109007 0x10000008
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01840a11
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00010000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0a324243
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x88002020
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 4: 0x00000050 1
>[  +0,000007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000130] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 1: 0x00000050 1
>[  +0,000135] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01101000 0x10000001
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01840a00
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00010000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0a324243
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x88002020
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 4: 0x00000050 1
>[  +0,000007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000130] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[  +0,000264] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xffffff00
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00ffffff
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x284cf022
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[  +0,000264] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0401150e
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x782034a5
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xa6c59e22
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x259a4b56
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[  +0,000264] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x21545013
>[  +0,000008] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x40810008
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00958081
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00b340a9
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[  +0,000263] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0101c0d1
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x3c280101
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xb070a080
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x20304023
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[  +0,000264] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x44060036
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x1a000021
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xfd000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x183f3200
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[  +0,000264] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0a00114c
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x20202020
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00002020
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x4c00fc00
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[  +0,000264] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x30343241
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x20200a35
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x20202020
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xff000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 1: 0x00000050 16
>[  +0,000264] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110100f 0x10000010
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x344e4300
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x30343131
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0a324243
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x88002020
>[  +0,162050] nouveau T[   VBIOS][0000:01:00.0] inc() == 2
>[  +0,000003] nouveau T[     I2C][0000:01:00.0] inc() == 2
>[  +0,000002] nouveau T[   PDISP][0000:01:00.0] inc() == 14
>[aoÃ»t 6 13:58] nouveau E[   PDISP][0000:01:00.0] INVALID_STATE [UNK0B] chid 1 mthd 0x0080 data 0x00000000
>[  +0,000009] nouveau E[   PDISP][0000:01:00.0] Base 0:
>[  +0,000006] nouveau E[   PDISP][0000:01:00.0] 	0x0084: 0x00000000              
>[  +0,000005] nouveau E[   PDISP][0000:01:00.0] 	0x0088: 0x00000000              
>[  +0,000006] nouveau E[   PDISP][0000:01:00.0] 	0x008c: 0x00000000              
>[  +0,000005] nouveau E[   PDISP][0000:01:00.0] 	0x0090: 0x00000000              
>[  +0,000005] nouveau E[   PDISP][0000:01:00.0] 	0x0094: 0x00000000 -> 0xcafe0000
>[  +0,000005] nouveau E[   PDISP][0000:01:00.0] 	0x00a0: 0x00000000              
>[  +0,000005] nouveau E[   PDISP][0000:01:00.0] 	0x00a4: 0x00000000              
>[  +0,000005] nouveau E[   PDISP][0000:01:00.0] 	0x00c0: 0x00000000 -> 0x01000002
>[  +0,000005] nouveau E[   PDISP][0000:01:00.0] 	0x00c4: 0x00000000              
>[  +0,000006] nouveau E[   PDISP][0000:01:00.0] 	0x00c8: 0x00000000              
>[  +0,000004] nouveau E[   PDISP][0000:01:00.0] 	0x00cc: 0x00000000              
>[  +0,000006] nouveau E[   PDISP][0000:01:00.0] 	0x00e0: 0x40000000              
>[  +0,000005] nouveau E[   PDISP][0000:01:00.0] 	0x00e4: 0x00000000              
>[  +0,000005] nouveau E[   PDISP][0000:01:00.0] 	0x00e8: 0x00000000              
>[  +0,000005] nouveau E[   PDISP][0000:01:00.0] 	0x00ec: 0x00000000              
>[  +0,000005] nouveau E[   PDISP][0000:01:00.0] 	0x00fc: 0x00000000              
>[  +0,000006] nouveau E[   PDISP][0000:01:00.0] 	0x0100: 0xfffe0000              
>[  +0,000005] nouveau E[   PDISP][0000:01:00.0] 	0x0104: 0x00000000              
>[  +0,000005] nouveau E[   PDISP][0000:01:00.0] 	0x0110: 0x00000000              
>[  +0,000005] nouveau E[   PDISP][0000:01:00.0] 	0x0114: 0x00000000              
>[  +0,000004] nouveau E[   PDISP][0000:01:00.0] Base 0 - Image 0:
>[  +0,000006] nouveau E[   PDISP][0000:01:00.0] 	0x0800: 0x00000700 -> 0x00009600
>[  +0,000005] nouveau E[   PDISP][0000:01:00.0] 	0x0804: 0x00000000              
>[  +0,000005] nouveau E[   PDISP][0000:01:00.0] 	0x0808: 0x04b00780 -> 0x041a0690
>[  +0,000005] nouveau E[   PDISP][0000:01:00.0] 	0x080c: 0x00101e00 -> 0x00006904
>[  +0,000005] nouveau E[   PDISP][0000:01:00.0] 	0x0810: 0x0000cf00              
>[  +0,000004] nouveau E[   PDISP][0000:01:00.0] Base 0 - Image 1:
>[  +0,000005] nouveau E[   PDISP][0000:01:00.0] 	0x0c00: 0x00000700 -> 0x00009600
>[  +0,000005] nouveau E[   PDISP][0000:01:00.0] 	0x0c04: 0x00000000              
>[  +0,000006] nouveau E[   PDISP][0000:01:00.0] 	0x0c08: 0x04b00780 -> 0x041a0690
>[  +0,000005] nouveau E[   PDISP][0000:01:00.0] 	0x0c0c: 0x00101e00 -> 0x00006904
>[  +0,000005] nouveau E[   PDISP][0000:01:00.0] 	0x0c10: 0x0000cf00              
>[  +4,003858] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000100 2
>[  +0,000149] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109001 0x10000002
>[  +0,000004] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x344e840a
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x30343131
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0a324243
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x88002020
>[  +0,000004] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000202 3
>[  +0,000153] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x34017777
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x30343131
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0a324243
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x88002020
>[  +2,002314] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000600 1
>[  +0,000013] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000001
>[  +0,000004] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000004] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000133] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  +0,001780] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000600 1
>[  +0,000012] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000001
>[  +0,000004] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000004] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000133] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  +4,501450] nouveau D[     I2C][0000:01:00.0] PAD:X:00: -> PORT:00
>[  +0,000870] nouveau D[     I2C][0000:01:00.0] PAD:X:00: -> NULL
>[  +0,000005] nouveau D[     I2C][0000:01:00.0] PAD:X:00: -> PORT:00
>[  +0,000863] nouveau D[     I2C][0000:01:00.0] PAD:X:00: -> NULL
>[  +0,000004] nouveau D[     I2C][0000:01:00.0] PAD:X:00: -> PORT:00
>[  +0,026598] nouveau D[     I2C][0000:01:00.0] PAD:X:00: -> NULL
>[  +0,000168] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000000 8
>[  +0,000194] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109007 0x10000008
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01840a11
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00010000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0a324243
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x88002020
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 4: 0x00000050 1
>[  +0,000006] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000132] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 1: 0x00000050 1
>[  +0,000135] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01101000 0x10000001
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01840a00
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00010000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0a324243
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x88002020
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 4: 0x00000050 1
>[  +0,000007] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000130] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01104000 0x10000001
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[  +0,000264] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xffffff00
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00ffffff
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x284cf022
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x01010101
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[  +0,000264] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0401150e
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x782034a5
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xa6c59e22
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x259a4b56
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[  +0,000264] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x21545013
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x40810008
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00958081
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00b340a9
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[  +0,000263] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0101c0d1
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x3c280101
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xb070a080
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x20304023
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[  +0,000265] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x44060036
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x1a000021
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xfd000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x183f3200
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[  +0,000264] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0a00114c
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x20202020
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x00002020
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x4c00fc00
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 5: 0x00000050 16
>[  +0,000263] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110500f 0x10000010
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x30343241
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x20200a35
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x20202020
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0xff000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 1: 0x00000050 16
>[  +0,000265] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x0110100f 0x10000010
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x344e4300
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x30343131
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0a324243
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x88002020
>[  +4,009648] nouveau E[   PDISP][0000:01:00.0] INVALID_STATE [UNK0B] chid 1 mthd 0x0080 data 0x00000000
>[  +0,000006] nouveau E[   PDISP][0000:01:00.0] Base 0:
>[  +0,000005] nouveau E[   PDISP][0000:01:00.0] 	0x0084: 0x00000000              
>[  +0,000004] nouveau E[   PDISP][0000:01:00.0] 	0x0088: 0x00000000              
>[  +0,000004] nouveau E[   PDISP][0000:01:00.0] 	0x008c: 0x00000000              
>[  +0,000004] nouveau E[   PDISP][0000:01:00.0] 	0x0090: 0x00000000              
>[  +0,000004] nouveau E[   PDISP][0000:01:00.0] 	0x0094: 0x00000000 -> 0xcafe0000
>[  +0,000004] nouveau E[   PDISP][0000:01:00.0] 	0x00a0: 0x00000000              
>[  +0,000004] nouveau E[   PDISP][0000:01:00.0] 	0x00a4: 0x00000000              
>[  +0,000004] nouveau E[   PDISP][0000:01:00.0] 	0x00c0: 0x00000000 -> 0x01000002
>[  +0,000004] nouveau E[   PDISP][0000:01:00.0] 	0x00c4: 0x00000000              
>[  +0,000004] nouveau E[   PDISP][0000:01:00.0] 	0x00c8: 0x00000000              
>[  +0,000004] nouveau E[   PDISP][0000:01:00.0] 	0x00cc: 0x00000000              
>[  +0,000004] nouveau E[   PDISP][0000:01:00.0] 	0x00e0: 0x40000000              
>[  +0,000003] nouveau E[   PDISP][0000:01:00.0] 	0x00e4: 0x00000000              
>[  +0,000004] nouveau E[   PDISP][0000:01:00.0] 	0x00e8: 0x00000000              
>[  +0,000004] nouveau E[   PDISP][0000:01:00.0] 	0x00ec: 0x00000000              
>[  +0,000004] nouveau E[   PDISP][0000:01:00.0] 	0x00fc: 0x00000000              
>[  +0,000004] nouveau E[   PDISP][0000:01:00.0] 	0x0100: 0xfffe0000              
>[  +0,000004] nouveau E[   PDISP][0000:01:00.0] 	0x0104: 0x00000000              
>[  +0,000004] nouveau E[   PDISP][0000:01:00.0] 	0x0110: 0x00000000              
>[  +0,000003] nouveau E[   PDISP][0000:01:00.0] 	0x0114: 0x00000000              
>[  +0,000003] nouveau E[   PDISP][0000:01:00.0] Base 0 - Image 0:
>[  +0,000005] nouveau E[   PDISP][0000:01:00.0] 	0x0800: 0x00009600 -> 0x00012c00
>[  +0,000004] nouveau E[   PDISP][0000:01:00.0] 	0x0804: 0x00000000              
>[  +0,000004] nouveau E[   PDISP][0000:01:00.0] 	0x0808: 0x041a0690 -> 0x051e0e10
>[  +0,000004] nouveau E[   PDISP][0000:01:00.0] 	0x080c: 0x00006904 -> 0x0000e104
>[  +0,000003] nouveau E[   PDISP][0000:01:00.0] 	0x0810: 0x0000cf00              
>[  +0,000003] nouveau E[   PDISP][0000:01:00.0] Base 0 - Image 1:
>[  +0,000004] nouveau E[   PDISP][0000:01:00.0] 	0x0c00: 0x00009600 -> 0x00012c00
>[  +0,000004] nouveau E[   PDISP][0000:01:00.0] 	0x0c04: 0x00000000              
>[  +0,000004] nouveau E[   PDISP][0000:01:00.0] 	0x0c08: 0x041a0690 -> 0x051e0e10
>[  +0,000004] nouveau E[   PDISP][0000:01:00.0] 	0x0c0c: 0x00006904 -> 0x0000e104
>[  +0,000004] nouveau E[   PDISP][0000:01:00.0] 	0x0c10: 0x0000cf00              
>[  +4,003931] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000600 1
>[  +0,000011] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000001
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000132] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108000 0x10000000
>[  +8,318226] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000100 2
>[  +0,000147] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109001 0x10000002
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x344e840a
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x30343131
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0a324243
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x88002020
>[  +0,000004] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 9: 0x00000202 3
>[  +0,000154] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01109002 0x10000003
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x34017777
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x30343131
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x0a324243
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): rd 0x88002020
>[  +2,002293] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 8: 0x00000600 1
>[  +0,000008] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000001
>[  +0,000003] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000002] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000001] nouveau D[     I2C][0000:01:00.0] AUXCH(1): wr 0x00000000
>[  +0,000132] nouveau D[     I2C][0000:01:00.0] AUXCH(1): 00 0x01108000 0x10000000

Actions: View

Attachments on bug 82247: 104148 | 104149

Use of freedesktop.org services, including Bugzilla, is subject to our Code of Conduct. How we collect and use information is described in our Privacy Policy.