Attachment 104475 Details for Bug 82050 – Flush HDP cache via the ring on SI

[patch] Flush HDP cache via the ring on SI

radeon-si-hdp-flush-ring.diff (text/plain), 3.17 KB, created by Michel Dänzer on 2014-08-12 09:03:39 UTC

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Creator: Michel Dänzer

Created: 2014-08-12 09:03:39 UTC

Size: 3.17 KB

patch

obsolete

>commit 339cfd109a873e92e54961664ad170cd05da2988
>Author: Michel DÃ¤nzer <michel.daenzer@amd.com>
>Date:   Tue Aug 12 10:35:35 2014 +0900
>
>    drm/radeon: Flush HDP cache via the ring on SI
>
>diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c
>index eeeeabe..e83c9bd 100644
>--- a/drivers/gpu/drm/radeon/radeon_asic.c
>+++ b/drivers/gpu/drm/radeon/radeon_asic.c
>@@ -1813,6 +1813,7 @@ static struct radeon_asic_ring si_gfx_ring = {
> 	.get_rptr = &cayman_gfx_get_rptr,
> 	.get_wptr = &cayman_gfx_get_wptr,
> 	.set_wptr = &cayman_gfx_set_wptr,
>+	.hdp_flush = si_cp_hdp_flush,
> };
> 
> static struct radeon_asic_ring si_dma_ring = {
>diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
>index 275a5dc..2f28597 100644
>--- a/drivers/gpu/drm/radeon/radeon_asic.h
>+++ b/drivers/gpu/drm/radeon/radeon_asic.h
>@@ -684,6 +684,7 @@ void dce6_audio_fini(struct radeon_device *rdev);
> /*
>  * si
>  */
>+void si_cp_hdp_flush(struct radeon_device *rdev, struct radeon_ring *ring);
> void si_fence_ring_emit(struct radeon_device *rdev,
> 			struct radeon_fence *fence);
> void si_pcie_gart_tlb_flush(struct radeon_device *rdev);
>diff --git a/drivers/gpu/drm/radeon/radeon_ring.c b/drivers/gpu/drm/radeon/radeon_ring.c
>index 6dff529..a3bcc48 100644
>--- a/drivers/gpu/drm/radeon/radeon_ring.c
>+++ b/drivers/gpu/drm/radeon/radeon_ring.c
>@@ -200,7 +200,8 @@ void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *ring)
> 	/* If we are emitting the HDP flush via MMIO, we need to do it after
> 	 * all CPU writes to VRAM finished.
> 	 */
>-	if (rdev->asic->mmio_hdp_flush)
>+	if (!rdev->asic->ring[ring->idx]->hdp_flush &&
>+	    rdev->asic->mmio_hdp_flush)
> 		rdev->asic->mmio_hdp_flush(rdev);
> 	radeon_ring_set_wptr(rdev, ring);
> }
>diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
>index 011779b..997d4b7 100644
>--- a/drivers/gpu/drm/radeon/si.c
>+++ b/drivers/gpu/drm/radeon/si.c
>@@ -3330,6 +3330,21 @@ static void si_scratch_init(struct radeon_device *rdev)
> 	}
> }
> 
>+/**
>+ * si_cp_hdp_flush - flush Host Data Path via a CP ring buffer
>+ * rdev: radeon device structure
>+ * ring: ring buffer struct for emitting packets
>+ */
>+void si_cp_hdp_flush(struct radeon_device *rdev, struct radeon_ring *ring)
>+{
>+	radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
>+	radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
>+				 WRITE_DATA_DST_SEL(0)));
>+	radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2);
>+	radeon_ring_write(ring, 0);
>+	radeon_ring_write(ring, 0x1);
>+}
>+
> void si_fence_ring_emit(struct radeon_device *rdev,
> 			struct radeon_fence *fence)
> {
>@@ -5026,13 +5041,7 @@ void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
> 	radeon_ring_write(ring, 0);
> 	radeon_ring_write(ring, vm->pd_gpu_addr >> 12);
> 
>-	/* flush hdp cache */
>-	radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
>-	radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
>-				 WRITE_DATA_DST_SEL(0)));
>-	radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2);
>-	radeon_ring_write(ring, 0);
>-	radeon_ring_write(ring, 0x1);
>+	si_cp_hdp_flush(rdev, ring);
> 
> 	/* bits 0-15 are the VM contexts0-15 */
> 	radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));

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Attachments on bug 82050: 104082 | 104083 | 104475 | 104549 | 105316 | 105317 | 105318 | 105543 | 105544 | 105563 | 105564 | 107183

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