Attachment 105024 Details for Bug 82455 – Use CPU page size instead of hardcoding 4096

[patch] Use CPU page size instead of hardcoding 4096

winsys-radeon-cpu-page-size.diff (text/plain), 3.01 KB, created by Michel Dänzer on 2014-08-21 09:35:27 UTC

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Creator: Michel Dänzer

Created: 2014-08-21 09:35:27 UTC

Size: 3.01 KB

patch

obsolete

>commit 617b518f35f66257d81627ea0d001f4c523df2f5
>Author: Michel DÃ¤nzer <michel.daenzer@amd.com>
>Date:   Thu Aug 21 18:30:44 2014 +0900
>
>    winsys/radeon: Use CPU page size instead of hardcoding 4096
>
>diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
>index 73f8d38..7a5ae18 100644
>--- a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
>+++ b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
>@@ -77,6 +77,9 @@ struct radeon_bomgr {
>     bool va;
>     uint64_t va_offset;
>     struct list_head va_holes;
>+
>+    /* CPU page size, used for aligning BO sizes */
>+    long cpu_page_size;
> };
> 
> static INLINE struct radeon_bomgr *radeon_bomgr(struct pb_manager *mgr)
>@@ -169,7 +172,7 @@ static uint64_t radeon_bomgr_find_va(struct radeon_bomgr *mgr, uint64_t size, ui
>     uint64_t offset = 0, waste = 0;
> 
>     alignment = MAX2(alignment, 4096);
>-    size = align(size, 4096);
>+    size = align(size, mgr->cpu_page_size);
> 
>     pipe_mutex_lock(mgr->bo_va_mutex);
>     /* first look for a hole */
>@@ -226,7 +229,7 @@ static void radeon_bomgr_free_va(struct radeon_bomgr *mgr, uint64_t va, uint64_t
> {
>     struct radeon_bo_va_hole *hole;
> 
>-    size = align(size, 4096);
>+    size = align(size, mgr->cpu_page_size);
> 
>     pipe_mutex_lock(mgr->bo_va_mutex);
>     if ((va + size) == mgr->va_offset) {
>@@ -317,9 +320,9 @@ static void radeon_bo_destroy(struct pb_buffer *_buf)
>     pipe_mutex_destroy(bo->map_mutex);
> 
>     if (bo->initial_domain & RADEON_DOMAIN_VRAM)
>-        bo->rws->allocated_vram -= align(bo->base.size, 4096);
>+        bo->rws->allocated_vram -= align(bo->base.size, mgr->cpu_page_size);
>     else if (bo->initial_domain & RADEON_DOMAIN_GTT)
>-        bo->rws->allocated_gtt -= align(bo->base.size, 4096);
>+        bo->rws->allocated_gtt -= align(bo->base.size, mgr->cpu_page_size);
>     FREE(bo);
> }
> 
>@@ -570,9 +573,9 @@ static struct pb_buffer *radeon_bomgr_create_bo(struct pb_manager *_mgr,
>     }
> 
>     if (rdesc->initial_domains & RADEON_DOMAIN_VRAM)
>-        rws->allocated_vram += align(size, 4096);
>+        rws->allocated_vram += align(size, mgr->cpu_page_size);
>     else if (rdesc->initial_domains & RADEON_DOMAIN_GTT)
>-        rws->allocated_gtt += align(size, 4096);
>+        rws->allocated_gtt += align(size, mgr->cpu_page_size);
> 
>     return &bo->base;
> }
>@@ -646,6 +649,8 @@ struct pb_manager *radeon_bomgr_create(struct radeon_drm_winsys *rws)
>     mgr->va_offset = rws->va_start;
>     list_inithead(&mgr->va_holes);
> 
>+    mgr->cpu_page_size = sysconf(_SC_PAGESIZE);
>+
>     return &mgr->base;
> }
> 
>@@ -969,9 +974,9 @@ done:
>     bo->initial_domain = radeon_bo_get_initial_domain((void*)bo);
> 
>     if (bo->initial_domain & RADEON_DOMAIN_VRAM)
>-        ws->allocated_vram += align(bo->base.size, 4096);
>+        ws->allocated_vram += align(bo->base.size, mgr->cpu_page_size);
>     else if (bo->initial_domain & RADEON_DOMAIN_GTT)
>-        ws->allocated_gtt += align(bo->base.size, 4096);
>+        ws->allocated_gtt += align(bo->base.size, mgr->cpu_page_size);
> 
>     return (struct pb_buffer*)bo;
>

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