Attachment 105318 Details for Bug 82050 – r600g,radeonsi: Inform the kernel if a BO will likely be accessed by the CPU

[patch] r600g,radeonsi: Inform the kernel if a BO will likely be accessed by the CPU

RADEON_FLAG_CPU_ACCESS.diff (text/plain), 3.50 KB, created by Michel Dänzer on 2014-08-27 07:18:32 UTC

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Creator: Michel Dänzer

Created: 2014-08-27 07:18:32 UTC

Size: 3.50 KB

patch

obsolete

>commit 3f32ca857b577e2b185e644f500a6f5767643dfd
>Author: Michel DÃ¤nzer <michel.daenzer@amd.com>
>Date:   Tue Aug 26 18:06:49 2014 +0900
>
>    r600g,radeonsi: Inform the kernel if a BO will likely be accessed by the CPU
>
>diff --git a/src/gallium/drivers/radeon/r600_buffer_common.c b/src/gallium/drivers/radeon/r600_buffer_common.c
>index ee05776..c4e87a0 100644
>--- a/src/gallium/drivers/radeon/r600_buffer_common.c
>+++ b/src/gallium/drivers/radeon/r600_buffer_common.c
>@@ -124,6 +124,7 @@ bool r600_init_resource(struct r600_common_screen *rscreen,
> 			flags = RADEON_FLAG_GTT_WC;
> 			break;
> 		}
>+		flags = RADEON_FLAG_CPU_ACCESS;
> 		/* fall through */
> 	case PIPE_USAGE_DEFAULT:
> 	case PIPE_USAGE_IMMUTABLE:
>@@ -134,23 +135,27 @@ bool r600_init_resource(struct r600_common_screen *rscreen,
> 		break;
> 	}
> 
>-	/* Use GTT for all persistent mappings with older kernels, because they
>-	 * didn't always flush the HDP cache before CS execution.
>-	 *
>-	 * Write-combined CPU mappings are fine, the kernel ensures all CPU
>-	 * writes finish before the GPU executes a command stream.
>-	 */
>-	if (rscreen->info.drm_minor < 40 &&
>-	    res->b.b.target == PIPE_BUFFER &&
>+	if (res->b.b.target == PIPE_BUFFER &&
> 	    res->b.b.flags & (PIPE_RESOURCE_FLAG_MAP_PERSISTENT |
> 			      PIPE_RESOURCE_FLAG_MAP_COHERENT)) {
>-		res->domains = RADEON_DOMAIN_GTT;
>+		/* Use GTT for all persistent mappings with older kernels,
>+		 * because they didn't always flush the HDP cache before CS
>+		 * execution.
>+		 *
>+		 * Write-combined CPU mappings are fine, the kernel ensures all CPU
>+		 * writes finish before the GPU executes a command stream.
>+		 */
>+		if (rscreen->info.drm_minor < 40)
>+			res->domains = RADEON_DOMAIN_GTT;
>+		else if (res->domains & RADEON_DOMAIN_VRAM)
>+			flags |= RADEON_FLAG_CPU_ACCESS;
> 	}
> 
> 	/* Tiled textures are unmappable. Always put them in VRAM. */
> 	if (res->b.b.target != PIPE_BUFFER &&
> 	    rtex->surface.level[0].mode >= RADEON_SURF_MODE_1D) {
> 		res->domains = RADEON_DOMAIN_VRAM;
>+		flags &= ~RADEON_FLAG_CPU_ACCESS;
> 	}
> 
> 	/* Allocate a new resource. */
>diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
>index 73f8d38..03b9b1d 100644
>--- a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
>+++ b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
>@@ -478,7 +478,11 @@ const struct pb_vtbl radeon_bo_vtbl = {
> };
> 
> #ifndef RADEON_GEM_GTT_WC
>-#define RADEON_GEM_GTT_WC (1 << 2)
>+#define RADEON_GEM_GTT_WC	(1 << 2)
>+#endif
>+#ifndef RADEON_GTM_CPU_ACCESS
>+/* BO is expected to be accessed by the CPU */
>+#define RADEON_GEM_CPU_ACCESS	(1 << 3)
> #endif
> 
> static struct pb_buffer *radeon_bomgr_create_bo(struct pb_manager *_mgr,
>@@ -505,6 +509,8 @@ static struct pb_buffer *radeon_bomgr_create_bo(struct pb_manager *_mgr,
> 
>     if (rdesc->flags & RADEON_FLAG_GTT_WC)
>         args.flags |= RADEON_GEM_GTT_WC;
>+    if (rdesc->flags & RADEON_FLAG_CPU_ACCESS)
>+        args.flags |= RADEON_GEM_CPU_ACCESS;
> 
>     if (drmCommandWriteRead(rws->fd, DRM_RADEON_GEM_CREATE,
>                             &args, sizeof(args))) {
>diff --git a/src/gallium/winsys/radeon/drm/radeon_winsys.h b/src/gallium/winsys/radeon/drm/radeon_winsys.h
>index dbd58f1..69bf6ed 100644
>--- a/src/gallium/winsys/radeon/drm/radeon_winsys.h
>+++ b/src/gallium/winsys/radeon/drm/radeon_winsys.h
>@@ -66,7 +66,8 @@ enum radeon_bo_domain { /* bitfield */
> };
> 
> enum radeon_bo_flag { /* bitfield */
>-   RADEON_FLAG_GTT_WC = (1 << 0)
>+    RADEON_FLAG_GTT_WC =     (1 << 0),
>+    RADEON_FLAG_CPU_ACCESS = (1 << 1),
> };
> 
> enum radeon_bo_usage { /* bitfield */

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Attachments on bug 82050: 104082 | 104083 | 104475 | 104549 | 105316 | 105317 | 105318 | 105543 | 105544 | 105563 | 105564 | 107183

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