Attachment 106370 Details for Bug 83482 – v2: DEBUG: drm/i915: add i915.wa module parameter to control bdw workarounds

v2: DEBUG: drm/i915: add i915.wa module parameter to control bdw workarounds

0001-DEBUG-drm-i915-add-i915.wa-module-parameter-to-contr.patch (text/plain), 4.56 KB, created by Jani Nikula on 2014-09-16 12:45:14 UTC

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Creator: Jani Nikula

Created: 2014-09-16 12:45:14 UTC

Size: 4.56 KB

patch

obsolete

>From d8cb907f07138716d5d5f315013493ee0358391a Mon Sep 17 00:00:00 2001
>From: Jani Nikula <jani.nikula@intel.com>
>Date: Tue, 16 Sep 2014 15:30:22 +0300
>Subject: [PATCH] DEBUG: drm/i915: add i915.wa module parameter to control bdw
> workarounds
>Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo
>Cc: Jani Nikula <jani.nikula@intel.com>
>
>Add i915.wa module parameter, which is a bitmask to control which bdw
>workarounds to apply. There are currently 8 workarounds resulting in
>0..0xff being the valid values for the parameter. Set a bit to enable a
>workaround; 0xff is the default. This can be used to try different sets
>of workarounds.
>
>It's possible to change the wa parameter runtime, and it should be
>enough to e.g. suspend/resume to reset the workarounds applied.
>
>Look dmesg for "Number of Workarounds applied" debug message, which
>should reflect the change.
>
>v2: it's 3 dwords per w/a so 3*hweight8 is needed
>
>Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83482
>---
> drivers/gpu/drm/i915/i915_drv.h         |  1 +
> drivers/gpu/drm/i915/i915_params.c      |  3 +++
> drivers/gpu/drm/i915/intel_ringbuffer.c | 11 ++++++++++-
> 3 files changed, 14 insertions(+), 1 deletion(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>index 17dfce0f4e68..5c6a765358ff 100644
>--- a/drivers/gpu/drm/i915/i915_drv.h
>+++ b/drivers/gpu/drm/i915/i915_drv.h
>@@ -2242,6 +2242,7 @@ struct i915_params {
> 	bool disable_vtd_wa;
> 	int use_mmio_flip;
> 	bool mmio_debug;
>+	int wa;
> };
> extern struct i915_params i915 __read_mostly;
> 
>diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
>index 139f490d464d..152f8a336361 100644
>--- a/drivers/gpu/drm/i915/i915_params.c
>+++ b/drivers/gpu/drm/i915/i915_params.c
>@@ -51,8 +51,11 @@ struct i915_params i915 __read_mostly = {
> 	.disable_vtd_wa = 0,
> 	.use_mmio_flip = 0,
> 	.mmio_debug = 0,
>+	.wa = 0xff,
> };
> 
>+module_param_named(wa, i915.wa, int, 0600);
>+
> module_param_named(modeset, i915.modeset, int, 0400);
> MODULE_PARM_DESC(modeset,
> 	"Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
>diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
>index 681ea86258e2..efd317f56b32 100644
>--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
>+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
>@@ -707,18 +707,21 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring)
> 	 * update the number of dwords required based on the
> 	 * actual number of workarounds applied
> 	 */
>-	ret = intel_ring_begin(ring, 24);
>+	ret = intel_ring_begin(ring, hweight8(i915.wa) * 3);
> 	if (ret)
> 		return ret;
> 
>+
> 	/* WaDisablePartialInstShootdown:bdw */
> 	/* WaDisableThreadStallDopClockGating:bdw */
> 	/* FIXME: Unclear whether we really need this on production bdw. */
>+	if (i915.wa & (1 << 0))
> 	intel_ring_emit_wa(ring, GEN8_ROW_CHICKEN,
> 			   _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE
> 					     | STALL_DOP_GATING_DISABLE));
> 
> 	/* WaDisableDopClockGating:bdw May not be needed for production */
>+	if (i915.wa & (1 << 1))
> 	intel_ring_emit_wa(ring, GEN7_ROW_CHICKEN2,
> 			   _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
> 
>@@ -726,13 +729,16 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring)
> 	 * This GEN8_CENTROID_PIXEL_OPT_DIS W/A is only needed for
> 	 * pre-production hardware
> 	 */
>+	if (i915.wa & (1 << 2))
> 	intel_ring_emit_wa(ring, HALF_SLICE_CHICKEN3,
> 			   _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS
> 					      | GEN8_SAMPLER_POWER_BYPASS_DIS));
> 
>+	if (i915.wa & (1 << 3))
> 	intel_ring_emit_wa(ring, GEN7_HALF_SLICE_CHICKEN1,
> 			   _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE));
> 
>+	if (i915.wa & (1 << 4))
> 	intel_ring_emit_wa(ring, COMMON_SLICE_CHICKEN2,
> 			   _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE));
> 
>@@ -740,9 +746,11 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring)
> 	 * workaround for for a possible hang in the unlikely event a TLB
> 	 * invalidation occurs during a PSD flush.
> 	 */
>+	if (i915.wa & (1 << 5))
> 	intel_ring_emit_wa(ring, HDC_CHICKEN0,
> 			   _MASKED_BIT_ENABLE(HDC_FORCE_NON_COHERENT));
> 
>+	if (i915.wa & (1 << 6))
> 	/* Wa4x4STCOptimizationDisable:bdw */
> 	intel_ring_emit_wa(ring, CACHE_MODE_1,
> 			   _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE));
>@@ -755,6 +763,7 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring)
> 	 * disable bit, which we don't touch here, but it's good
> 	 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
> 	 */
>+	if (i915.wa & (1 << 7))
> 	intel_ring_emit_wa(ring, GEN7_GT_MODE,
> 			   GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
> 
>-- 
>1.9.1
>

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Attachments on bug 83482: 106369 | 106370 | 106436

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