Attachment 106436 Details for Bug 83482 – drm/i915/bdw: Cleanup pre prod workarounds

[patch] drm/i915/bdw: Cleanup pre prod workarounds

0001-drm-i915-bdw-Cleanup-pre-prod-workarounds.patch (text/plain), 1.53 KB, created by Mika Kuoppala on 2014-09-17 15:11:22 UTC

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Creator: Mika Kuoppala

Created: 2014-09-17 15:11:22 UTC

Size: 1.53 KB

patch

obsolete

>From 88b4fa2a89dd6cab9f6ccb5c45bc984326da39e8 Mon Sep 17 00:00:00 2001
>From: Mika Kuoppala <mika.kuoppala@intel.com>
>Date: Wed, 17 Sep 2014 17:46:28 +0300
>Subject: [PATCH] drm/i915/bdw: Cleanup pre prod workarounds
>
>as these have been fixed in production hw and hurt performance
>if applied.
>
>Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
>---
> drivers/gpu/drm/i915/intel_ringbuffer.c | 13 +------------
> 1 file changed, 1 insertion(+), 12 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
>index 681ea86..dfb3bc6 100644
>--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
>+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
>@@ -722,19 +722,8 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring)
> 	intel_ring_emit_wa(ring, GEN7_ROW_CHICKEN2,
> 			   _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
> 
>-	/*
>-	 * This GEN8_CENTROID_PIXEL_OPT_DIS W/A is only needed for
>-	 * pre-production hardware
>-	 */
> 	intel_ring_emit_wa(ring, HALF_SLICE_CHICKEN3,
>-			   _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS
>-					      | GEN8_SAMPLER_POWER_BYPASS_DIS));
>-
>-	intel_ring_emit_wa(ring, GEN7_HALF_SLICE_CHICKEN1,
>-			   _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE));
>-
>-	intel_ring_emit_wa(ring, COMMON_SLICE_CHICKEN2,
>-			   _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE));
>+			   _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
> 
> 	/* Use Force Non-Coherent whenever executing a 3D context. This is a
> 	 * workaround for for a possible hang in the unlikely event a TLB
>-- 
>1.9.1
>

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Attachments on bug 83482: 106369 | 106370 | 106436

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