Attachment 112377 Details for Bug 88521 – Use PTE cache settings for winsys buffers.

[patch] Use PTE cache settings for winsys buffers.

0001-i965-Don-t-override-PTE-cache-settings-on-potential-.patch (text/plain), 3.44 KB, created by Chris Wilson on 2015-01-17 09:31:24 UTC

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Creator: Chris Wilson

Created: 2015-01-17 09:31:24 UTC

Size: 3.44 KB

patch

obsolete

>From 22610c74626a365ecd1d2735146e3fb9fa23897c Mon Sep 17 00:00:00 2001
>From: Chris Wilson <chris@chris-wilson.co.uk>
>Date: Fri, 16 Jan 2015 21:52:26 +0000
>Subject: [PATCH] i965: Don't override PTE cache settings on potential winsys
> render targets
>
>A winsys buffer may be uncached or using write-through caching in order
>for it to be coherent with the display (i.e. so that it can be used to
>immediately the scanout without display corruption). Without knowing
>which render targets are actually exported and uncached render buffers,
>it is safer to not override the MOCS for any render target.
>
>Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
>---
> src/mesa/drivers/dri/i965/gen7_blorp.cpp          | 5 +++--
> src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 3 ++-
> src/mesa/drivers/dri/i965/gen8_surface_state.c    | 7 +++++--
> 3 files changed, 10 insertions(+), 5 deletions(-)
>
>diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
>index 206a6ff..f29a483 100644
>--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
>+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
>@@ -184,8 +184,9 @@ gen7_blorp_emit_surface_state(struct brw_context *brw,
>    assert(tile_x % 4 == 0);
>    assert(tile_y % 2 == 0);
>    surf[5] = SET_FIELD(tile_x / 4, BRW_SURFACE_X_OFFSET) |
>-             SET_FIELD(tile_y / 2, BRW_SURFACE_Y_OFFSET) |
>-             SET_FIELD(mocs, GEN7_SURFACE_MOCS);
>+             SET_FIELD(tile_y / 2, BRW_SURFACE_Y_OFFSET);
>+   if (!is_render_target)
>+	   surf[5] |= SET_FIELD(mocs, GEN7_SURFACE_MOCS);
> 
>    surf[2] = SET_FIELD(width - 1, GEN7_SURFACE_WIDTH) |
>              SET_FIELD(height - 1, GEN7_SURFACE_HEIGHT);
>diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
>index e2c347a..de1482d 100644
>--- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
>+++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
>@@ -241,7 +241,8 @@ gen7_emit_buffer_surface_state(struct brw_context *brw,
>    surf[3] = SET_FIELD(((buffer_size - 1) >> 21) & 0x3f, BRW_SURFACE_DEPTH) |
>              (pitch - 1);
> 
>-   surf[5] = SET_FIELD(mocs, GEN7_SURFACE_MOCS);
>+   if (!rw)
>+      surf[5] = SET_FIELD(mocs, GEN7_SURFACE_MOCS);
> 
>    if (brw->is_haswell) {
>       surf[7] |= (SET_FIELD(HSW_SCS_RED,   GEN7_SURFACE_SCS_R) |
>diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c b/src/mesa/drivers/dri/i965/gen8_surface_state.c
>index d1b095c..eeb615b 100644
>--- a/src/mesa/drivers/dri/i965/gen8_surface_state.c
>+++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c
>@@ -124,7 +124,8 @@ gen8_emit_buffer_surface_state(struct brw_context *brw,
>    surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
>              surface_format << BRW_SURFACE_FORMAT_SHIFT |
>              BRW_SURFACE_RC_READ_WRITE;
>-   surf[1] = SET_FIELD(mocs, GEN8_SURFACE_MOCS);
>+   if (!rw)
>+      surf[1] = SET_FIELD(mocs, GEN8_SURFACE_MOCS);
> 
>    surf[2] = SET_FIELD((buffer_size - 1) & 0x7f, GEN7_SURFACE_WIDTH) |
>              SET_FIELD(((buffer_size - 1) >> 7) & 0x3fff, GEN7_SURFACE_HEIGHT);
>@@ -402,7 +403,9 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
>              horizontal_alignment(mt) |
>              surface_tiling_mode(tiling);
> 
>-   surf[1] = SET_FIELD(mocs, GEN8_SURFACE_MOCS) | mt->qpitch >> 2;
>+   surf[1] = mt->qpitch >> 2;
>+   if (0)
>+      surf[1] = SET_FIELD(mocs, GEN8_SURFACE_MOCS);
> 
>    surf[2] = SET_FIELD(width - 1, GEN7_SURFACE_WIDTH) |
>              SET_FIELD(height - 1, GEN7_SURFACE_HEIGHT);
>-- 
>2.1.4
>

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