Attachment 113659 Details for Bug 88561 – possible fix

[patch] possible fix

0001-radeonsi-don-t-use-SQC_CACHES-to-flush-ICACHE-and-KC.patch (text/plain), 3.03 KB, created by Marek Olšák on 2015-02-19 12:12:06 UTC

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Creator: Marek Olšák

Created: 2015-02-19 12:12:06 UTC

Size: 3.03 KB

patch

obsolete

>From 8aace585f63358f52caebcfcef64a15f5fd3c0bb Mon Sep 17 00:00:00 2001
>From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= <marek.olsak@amd.com>
>Date: Thu, 19 Feb 2015 13:03:54 +0100
>Subject: [PATCH] radeonsi: don't use SQC_CACHES to flush ICACHE and KCACHE on
> SI
>
>This reverts 73c2b0d18c51459697d8ec194ecfc4438c98c139.
>
>It doesn't seem to be reliable. It's probably missing a wait packet or
>something, because it's just a register write and doesn't wait for anything.
>SURFACE_SYNC at least seems to wait until the flush is done. Just guessing.
>
>Let's not complicate things and revert this.
>
>Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88561
>
>Cc: 10.5 <mesa-stable@lists.freedesktop.org>
>---
> src/gallium/drivers/radeonsi/si_state_draw.c | 29 +++++++++++-----------------
> 1 file changed, 11 insertions(+), 18 deletions(-)
>
>diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
>index 128ea04..511bea2 100644
>--- a/src/gallium/drivers/radeonsi/si_state_draw.c
>+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
>@@ -367,24 +367,21 @@ void si_emit_cache_flush(struct r600_common_context *sctx, struct r600_atom *ato
> {
> 	struct radeon_winsys_cs *cs = sctx->rings.gfx.cs;
> 	uint32_t cp_coher_cntl = 0;
>-	uint32_t sqc_caches = 0;
> 	uint32_t compute =
> 		PKT3_SHADER_TYPE_S(!!(sctx->flags & SI_CONTEXT_FLAG_COMPUTE));
> 
> 	/* SI has a bug that it always flushes ICACHE and KCACHE if either
>-	 * bit is set. An alternative way is to write SQC_CACHES. */
>-	if (sctx->chip_class == SI &&
>-	    sctx->flags & BOTH_ICACHE_KCACHE &&
>-	    (sctx->flags & BOTH_ICACHE_KCACHE) != BOTH_ICACHE_KCACHE) {
>-		sqc_caches =
>-			S_008C08_INST_INVALIDATE(!!(sctx->flags & SI_CONTEXT_INV_ICACHE)) |
>-			S_008C08_DATA_INVALIDATE(!!(sctx->flags & SI_CONTEXT_INV_KCACHE));
>-	} else {
>-		if (sctx->flags & SI_CONTEXT_INV_ICACHE)
>-			cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
>-		if (sctx->flags & SI_CONTEXT_INV_KCACHE)
>-			cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
>-	}
>+	 * bit is set. An alternative way is to write SQC_CACHES, but that
>+	 * doesn't seem to work reliably. Since the bug doesn't affect
>+	 * correctness (it only does more work than necessary) and
>+	 * the performance impact is likely negligible, there is no plan
>+	 * to fix it.
>+	 */
>+
>+	if (sctx->flags & SI_CONTEXT_INV_ICACHE)
>+		cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
>+	if (sctx->flags & SI_CONTEXT_INV_KCACHE)
>+		cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
> 
> 	if (sctx->flags & SI_CONTEXT_INV_TC_L1)
> 		cp_coher_cntl |= S_0085F0_TCL1_ACTION_ENA(1);
>@@ -451,10 +448,6 @@ void si_emit_cache_flush(struct r600_common_context *sctx, struct r600_atom *ato
> 	 * It looks like SURFACE_SYNC flushes caches immediately and doesn't
> 	 * wait for any engines. This should be last.
> 	 */
>-	if (sqc_caches) {
>-		r600_write_config_reg(cs, R_008C08_SQC_CACHES, sqc_caches);
>-		cs->buf[cs->cdw-3] |= compute; /* set the compute bit in the header */
>-	}
> 	if (cp_coher_cntl) {
> 		if (sctx->chip_class >= CIK) {
> 			radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, 0) | compute);
>-- 
>2.1.0
>

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Attachments on bug 88561: 112428 | 112429 | 113176 | 113659 | 115651

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