Attachment 113681 Details for Bug 88999 – Fix uniform pull constant payload size

[patch] Fix uniform pull constant payload size

0001-i965-skl-Use-1-register-for-uniform-pull-constant-pa.patch (text/plain), 1.46 KB, created by Ben Widawsky on 2015-02-20 01:50:06 UTC

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Creator: Ben Widawsky

Created: 2015-02-20 01:50:06 UTC

Size: 1.46 KB

patch

obsolete

>From 5255e1a9e6599942b10724fe5e573979f123b7e0 Mon Sep 17 00:00:00 2001
>From: Ben Widawsky <benjamin.widawsky@intel.com>
>Date: Thu, 19 Feb 2015 15:49:34 -0800
>Subject: [PATCH] i965/skl: Use 1 register for uniform pull constant payload
>
>When under dispatch_width=16 the previous code would allocate 2 registers for
>the payload when only one is needed. This manifested itself through bugs on SKL
>which needs to mess with this instruction.
>
>Ken says this might have some positive impact on shader-db.
>
>Cc: Kenneth Graunke <kenneth@whitecape.org>
>Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89118
>Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88999
>Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
>---
> src/mesa/drivers/dri/i965/brw_fs.cpp | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
>diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
>index a562b8a..bb647bd 100644
>--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
>+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
>@@ -3062,7 +3062,7 @@ fs_visitor::lower_uniform_pull_constant_loads()
>          assert(const_offset_reg.file == IMM &&
>                 const_offset_reg.type == BRW_REGISTER_TYPE_UD);
>          const_offset_reg.fixed_hw_reg.dw1.ud /= 4;
>-         fs_reg payload = vgrf(glsl_type::uint_type);
>+         fs_reg payload = fs_reg(GRF, alloc.allocate(1));
> 
>          /* We have to use a message header on Skylake to get SIMD4x2 mode.
>           * Reserve space for the register.
>-- 
>2.3.0
>

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