Attachment 113879 Details for Bug 80948 – Don't override PTE cache settings on scanout buffers

[patch] Don't override PTE cache settings on scanout buffers

0001-i965-Don-t-override-PTE-cache-settings-on-potential-.patch (text/plain), 3.89 KB, created by Chris Wilson on 2015-02-27 21:16:27 UTC

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Creator: Chris Wilson

Created: 2015-02-27 21:16:27 UTC

Size: 3.89 KB

patch

obsolete

>From 7d0e91bc5764a044373dec42120ae93dbd0a10c2 Mon Sep 17 00:00:00 2001
>From: Chris Wilson <chris@chris-wilson.co.uk>
>Date: Fri, 16 Jan 2015 21:52:26 +0000
>Subject: [PATCH] i965: Don't override PTE cache settings on potential winsys
> render targets
>
>A winsys buffer may be uncached or using write-through caching in order
>for it to be coherent with the display (i.e. so that it can be used to
>immediately the scanout without display corruption). Without knowing
>which render targets are actually exported and uncached render buffers,
>it is safer to not override the MOCS for any render target.
>
>Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
>---
> src/mesa/drivers/dri/i965/gen7_blorp.cpp          | 5 +++--
> src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 6 +++---
> src/mesa/drivers/dri/i965/gen8_surface_state.c    | 7 +++++--
> 3 files changed, 11 insertions(+), 7 deletions(-)
>
>diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
>index 206a6ff..f29a483 100644
>--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
>+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
>@@ -184,8 +184,9 @@ gen7_blorp_emit_surface_state(struct brw_context *brw,
>    assert(tile_x % 4 == 0);
>    assert(tile_y % 2 == 0);
>    surf[5] = SET_FIELD(tile_x / 4, BRW_SURFACE_X_OFFSET) |
>-             SET_FIELD(tile_y / 2, BRW_SURFACE_Y_OFFSET) |
>-             SET_FIELD(mocs, GEN7_SURFACE_MOCS);
>+             SET_FIELD(tile_y / 2, BRW_SURFACE_Y_OFFSET);
>+   if (!is_render_target)
>+	   surf[5] |= SET_FIELD(mocs, GEN7_SURFACE_MOCS);
> 
>    surf[2] = SET_FIELD(width - 1, GEN7_SURFACE_WIDTH) |
>              SET_FIELD(height - 1, GEN7_SURFACE_HEIGHT);
>diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
>index 12b588f..7d066da 100644
>--- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
>+++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
>@@ -240,7 +240,8 @@ gen7_emit_buffer_surface_state(struct brw_context *brw,
>    surf[3] = SET_FIELD(((buffer_size - 1) >> 21) & 0x3f, BRW_SURFACE_DEPTH) |
>              (pitch - 1);
> 
>-   surf[5] = SET_FIELD(GEN7_MOCS_L3, GEN7_SURFACE_MOCS);
>+   if (!rw)
>+      surf[5] = SET_FIELD(GEN7_MOCS_L3, GEN7_SURFACE_MOCS);
> 
>    if (brw->is_haswell) {
>       surf[7] |= (SET_FIELD(HSW_SCS_RED,   GEN7_SURFACE_SCS_R) |
>@@ -520,8 +521,7 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
> 
>    assert(brw->has_surface_tile_offset);
> 
>-   surf[5] = SET_FIELD(mocs, GEN7_SURFACE_MOCS) |
>-             (irb->mt_level - irb->mt->first_level);
>+   surf[5] = (irb->mt_level - irb->mt->first_level);
> 
>    surf[2] = SET_FIELD(irb->mt->logical_width0 - 1, GEN7_SURFACE_WIDTH) |
>              SET_FIELD(irb->mt->logical_height0 - 1, GEN7_SURFACE_HEIGHT);
>diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c b/src/mesa/drivers/dri/i965/gen8_surface_state.c
>index d6b870e..2afa626 100644
>--- a/src/mesa/drivers/dri/i965/gen8_surface_state.c
>+++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c
>@@ -124,7 +124,8 @@ gen8_emit_buffer_surface_state(struct brw_context *brw,
>    surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
>              surface_format << BRW_SURFACE_FORMAT_SHIFT |
>              BRW_SURFACE_RC_READ_WRITE;
>-   surf[1] = SET_FIELD(mocs, GEN8_SURFACE_MOCS);
>+   if (!rw)
>+      surf[1] = SET_FIELD(mocs, GEN8_SURFACE_MOCS);
> 
>    surf[2] = SET_FIELD((buffer_size - 1) & 0x7f, GEN7_SURFACE_WIDTH) |
>              SET_FIELD(((buffer_size - 1) >> 7) & 0x3fff, GEN7_SURFACE_HEIGHT);
>@@ -397,7 +398,9 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
>              horizontal_alignment(mt) |
>              surface_tiling_mode(tiling);
> 
>-   surf[1] = SET_FIELD(mocs, GEN8_SURFACE_MOCS) | mt->qpitch >> 2;
>+   surf[1] = mt->qpitch >> 2;
>+   if (0)
>+      surf[1] = SET_FIELD(mocs, GEN8_SURFACE_MOCS);
> 
>    surf[2] = SET_FIELD(width - 1, GEN7_SURFACE_WIDTH) |
>              SET_FIELD(height - 1, GEN7_SURFACE_HEIGHT);
>-- 
>2.1.4
>

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Attachments on bug 80948: 102302 | 102472 | 112435 | 113879 | 113937 | 114162

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