Attachment 114377 Details for Bug 89605 – dmesg with "testdisplay -d 16"

dmesg with "testdisplay -d 16"

dmesg_d16.txt (text/plain), 651.70 KB, created by Jeff Zheng on 2015-03-17 07:54:08 UTC

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Creator: Jeff Zheng

Created: 2015-03-17 07:54:08 UTC

Size: 651.70 KB

patch

obsolete

>[    0.000000] Initializing cgroup subsys cpuset
>[    0.000000] Initializing cgroup subsys cpu
>[    0.000000] Initializing cgroup subsys cpuacct
>[    0.000000] Linux version 4.0.0-rc3_drm-intel-testing-2015-03-13+ (root@x-kcloud1) (gcc version 4.8.2 20131212 (Red Hat 4.8.2-7) (GCC) ) #132 SMP Mon Mar 16 00:11:53 EDT 2015
>[    0.000000] Command line: BOOT_IMAGE=kernels//drm-intel-testing/drm-intel-testing-2015-03-13/bzImage_x86_64 root=/dev/sda3 drm.debug=0xe log_buf_len=4M hostname=x-bsw14 modules_path=kernels//drm-intel-testing/drm-intel-testing-2015-03-13/modules_x86_64/lib/modules/4.0.0-rc3_drm-intel-testing-2015-03-13+ acpi_rsdp=0x7b776014 kexec_jump_back_entry=0x71ace358
>[    0.000000] e820: BIOS-provided physical RAM map:
>[    0.000000] BIOS-e820: [mem 0x0000000000000100-0x000000000008efff] usable
>[    0.000000] BIOS-e820: [mem 0x000000000008f000-0x000000000008ffff] ACPI NVS
>[    0.000000] BIOS-e820: [mem 0x0000000000090000-0x000000000009dfff] usable
>[    0.000000] BIOS-e820: [mem 0x000000000009e000-0x000000000009ffff] reserved
>[    0.000000] BIOS-e820: [mem 0x0000000000100000-0x000000001fffffff] usable
>[    0.000000] BIOS-e820: [mem 0x0000000020000000-0x00000000201fffff] reserved
>[    0.000000] BIOS-e820: [mem 0x0000000020200000-0x000000007ac36fff] usable
>[    0.000000] BIOS-e820: [mem 0x000000007ac37000-0x000000007b636fff] reserved
>[    0.000000] BIOS-e820: [mem 0x000000007b637000-0x000000007b736fff] ACPI NVS
>[    0.000000] BIOS-e820: [mem 0x000000007b737000-0x000000007b776fff] ACPI data
>[    0.000000] BIOS-e820: [mem 0x000000007b777000-0x000000007b777fff] usable
>[    0.000000] BIOS-e820: [mem 0x000000007b778000-0x000000007b778fff] reserved
>[    0.000000] BIOS-e820: [mem 0x000000007b779000-0x000000007b77bfff] usable
>[    0.000000] BIOS-e820: [mem 0x000000007b77c000-0x000000007b77cfff] reserved
>[    0.000000] BIOS-e820: [mem 0x000000007b77d000-0x000000007bffffff] usable
>[    0.000000] BIOS-e820: [mem 0x00000000e0000000-0x00000000e3ffffff] reserved
>[    0.000000] BIOS-e820: [mem 0x00000000fea00000-0x00000000feafffff] reserved
>[    0.000000] BIOS-e820: [mem 0x00000000fec00000-0x00000000fec00fff] reserved
>[    0.000000] BIOS-e820: [mem 0x00000000fed01000-0x00000000fed01fff] reserved
>[    0.000000] BIOS-e820: [mem 0x00000000fed03000-0x00000000fed03fff] reserved
>[    0.000000] BIOS-e820: [mem 0x00000000fed06000-0x00000000fed06fff] reserved
>[    0.000000] BIOS-e820: [mem 0x00000000fed08000-0x00000000fed09fff] reserved
>[    0.000000] BIOS-e820: [mem 0x00000000fed1c000-0x00000000fed1cfff] reserved
>[    0.000000] BIOS-e820: [mem 0x00000000fed80000-0x00000000fedbffff] reserved
>[    0.000000] BIOS-e820: [mem 0x00000000fee00000-0x00000000fee00fff] reserved
>[    0.000000] BIOS-e820: [mem 0x0000000100000000-0x000000017fffffff] usable
>[    0.000000] NX (Execute Disable) protection: active
>[    0.000000] DMI not present or invalid.
>[    0.000000] e820: update [mem 0x00000000-0x00000fff] usable ==> reserved
>[    0.000000] e820: remove [mem 0x000a0000-0x000fffff] usable
>[    0.000000] AGP: No AGP bridge found
>[    0.000000] e820: last_pfn = 0x180000 max_arch_pfn = 0x400000000
>[    0.000000] MTRR default type: uncachable
>[    0.000000] MTRR fixed ranges enabled:
>[    0.000000]   00000-9FFFF write-back
>[    0.000000]   A0000-FFFFF write-protect
>[    0.000000] MTRR variable ranges enabled:
>[    0.000000]   0 base 0FF800000 mask FFF800000 write-protect
>[    0.000000]   1 base 000000000 mask F80000000 write-back
>[    0.000000]   2 base 07E000000 mask FFE000000 uncachable
>[    0.000000]   3 base 07D000000 mask FFF000000 uncachable
>[    0.000000]   4 base 07CC00000 mask FFFC00000 uncachable
>[    0.000000]   5 base 07CA00000 mask FFFE00000 uncachable
>[    0.000000]   6 base 100000000 mask F80000000 write-back
>[    0.000000]   7 disabled
>[    0.000000] PAT configuration [0-7]: WB  WC  UC- UC  WB  WC  UC- UC  
>[    0.000000] e820: last_pfn = 0x7c000 max_arch_pfn = 0x400000000
>[    0.000000] Base memory trampoline at [ffff880000098000] 98000 size 24576
>[    0.000000] init_memory_mapping: [mem 0x00000000-0x000fffff]
>[    0.000000]  [mem 0x00000000-0x000fffff] page 4k
>[    0.000000] BRK [0x033ce000, 0x033cefff] PGTABLE
>[    0.000000] BRK [0x033cf000, 0x033cffff] PGTABLE
>[    0.000000] BRK [0x033d0000, 0x033d0fff] PGTABLE
>[    0.000000] init_memory_mapping: [mem 0x17fe00000-0x17fffffff]
>[    0.000000]  [mem 0x17fe00000-0x17fffffff] page 2M
>[    0.000000] BRK [0x033d1000, 0x033d1fff] PGTABLE
>[    0.000000] init_memory_mapping: [mem 0x160000000-0x17fdfffff]
>[    0.000000]  [mem 0x160000000-0x17fdfffff] page 2M
>[    0.000000] init_memory_mapping: [mem 0x00100000-0x1fffffff]
>[    0.000000]  [mem 0x00100000-0x001fffff] page 4k
>[    0.000000]  [mem 0x00200000-0x1fffffff] page 2M
>[    0.000000] init_memory_mapping: [mem 0x20200000-0x7ac36fff]
>[    0.000000]  [mem 0x20200000-0x7abfffff] page 2M
>[    0.000000]  [mem 0x7ac00000-0x7ac36fff] page 4k
>[    0.000000] BRK [0x033d2000, 0x033d2fff] PGTABLE
>[    0.000000] BRK [0x033d3000, 0x033d3fff] PGTABLE
>[    0.000000] init_memory_mapping: [mem 0x7b777000-0x7b777fff]
>[    0.000000]  [mem 0x7b777000-0x7b777fff] page 4k
>[    0.000000] init_memory_mapping: [mem 0x7b779000-0x7b77bfff]
>[    0.000000]  [mem 0x7b779000-0x7b77bfff] page 4k
>[    0.000000] init_memory_mapping: [mem 0x7b77d000-0x7bffffff]
>[    0.000000]  [mem 0x7b77d000-0x7b7fffff] page 4k
>[    0.000000]  [mem 0x7b800000-0x7bffffff] page 2M
>[    0.000000] init_memory_mapping: [mem 0x100000000-0x15fffffff]
>[    0.000000]  [mem 0x100000000-0x15fffffff] page 2M
>[    0.000000] log_buf_len: 4194304 bytes
>[    0.000000] early log buf free: 125456(95%)
>[    0.000000] ACPI: Early table checksum verification disabled
>[    0.000000] ACPI: RSDP 0x000000007B776014 000024 (v02 INTEL )
>[    0.000000] ACPI: XSDT 0x000000007B7750E8 000094 (v01 INTEL  EDK2     00000003      01000013)
>[    0.000000] ACPI: FACP 0x000000007B771000 00010C (v05 INTEL  EDK2     00000003 CHV  0100000D)
>[    0.000000] ACPI: DSDT 0x000000007B75D000 00CAA4 (v02 INTEL  EDK2     00000003 CHV  0100000D)
>[    0.000000] ACPI: FACS 0x000000007B722000 000040
>[    0.000000] ACPI: TCPA 0x000000007B774000 000032 (v02 INTEL  EDK2     00000002      01000013)
>[    0.000000] ACPI: SSDT 0x000000007B773000 0000B1 (v01 Intel_ ADebTabl 00001000 INTL 20141107)
>[    0.000000] ACPI: UEFI 0x000000007B725000 000042 (v01 INTEL  EDK2     00000002      01000013)
>[    0.000000] ACPI: HPET 0x000000007B770000 000038 (v01 INTEL  EDK2     00000003 CHV  0100000D)
>[    0.000000] ACPI: APIC 0x000000007B76F000 000084 (v03 INTEL  EDK2     00000003 CHV  0100000D)
>[    0.000000] ACPI: MCFG 0x000000007B76E000 00003C (v01 INTEL  EDK2     00000003 CHV  0100000D)
>[    0.000000] ACPI: SSDT 0x000000007B75C000 000451 (v01 Intel_ Tpm2Tabl 00001000 INTL 20141107)
>[    0.000000] ACPI: TPM2 0x000000007B75B000 000034 (v03                 00000000      00000000)
>[    0.000000] ACPI: SSDT 0x000000007B75A000 000763 (v01 PmRef  CpuPm    00003000 INTL 20141107)
>[    0.000000] ACPI: SSDT 0x000000007B759000 000290 (v01 PmRef  Cpu0Tst  00003000 INTL 20141107)
>[    0.000000] ACPI: SSDT 0x000000007B758000 00017A (v01 PmRef  ApTst    00003000 INTL 20141107)
>[    0.000000] ACPI: CSRT 0x000000007B772000 00014C (v00 INTEL  EDK2     00000003 CHV  0100000D)
>[    0.000000] ACPI: FPDT 0x000000007B757000 000044 (v01 INTEL  EDK2     00000002      01000013)
>[    0.000000] ACPI: Local APIC address 0xfee00000
>[    0.000000] No NUMA configuration found
>[    0.000000] Faking a node at [mem 0x0000000000000000-0x000000017fffffff]
>[    0.000000] NODE_DATA(0) allocated [mem 0x17fbfa000-0x17fbfdfff]
>[    0.000000]  [ffffea0000000000-ffffea0005ffffff] PMD -> [ffff88017b200000-ffff88017f1fffff] on node 0
>[    0.000000] Zone ranges:
>[    0.000000]   DMA      [mem 0x0000000000001000-0x0000000000ffffff]
>[    0.000000]   DMA32    [mem 0x0000000001000000-0x00000000ffffffff]
>[    0.000000]   Normal   [mem 0x0000000100000000-0x000000017fffffff]
>[    0.000000] Movable zone start for each node
>[    0.000000] Early memory node ranges
>[    0.000000]   node   0: [mem 0x0000000000001000-0x000000000008efff]
>[    0.000000]   node   0: [mem 0x0000000000090000-0x000000000009dfff]
>[    0.000000]   node   0: [mem 0x0000000000100000-0x000000001fffffff]
>[    0.000000]   node   0: [mem 0x0000000020200000-0x000000007ac36fff]
>[    0.000000]   node   0: [mem 0x000000007b777000-0x000000007b777fff]
>[    0.000000]   node   0: [mem 0x000000007b779000-0x000000007b77bfff]
>[    0.000000]   node   0: [mem 0x000000007b77d000-0x000000007bffffff]
>[    0.000000]   node   0: [mem 0x0000000100000000-0x000000017fffffff]
>[    0.000000] Initmem setup node 0 [mem 0x0000000000001000-0x000000017fffffff]
>[    0.000000] On node 0 totalpages: 1028698
>[    0.000000]   DMA zone: 64 pages used for memmap
>[    0.000000]   DMA zone: 21 pages reserved
>[    0.000000]   DMA zone: 3996 pages, LIFO batch:0
>[    0.000000]   DMA32 zone: 7819 pages used for memmap
>[    0.000000]   DMA32 zone: 500414 pages, LIFO batch:31
>[    0.000000]   Normal zone: 8192 pages used for memmap
>[    0.000000]   Normal zone: 524288 pages, LIFO batch:31
>[    0.000000] Reserving Intel graphics stolen memory at 0x7ce00000-0x7edfffff
>[    0.000000] ACPI: PM-Timer IO Port: 0x408
>[    0.000000] ACPI: Local APIC address 0xfee00000
>[    0.000000] ACPI: LAPIC (acpi_id[0x01] lapic_id[0x00] enabled)
>[    0.000000] ACPI: LAPIC (acpi_id[0x02] lapic_id[0x02] enabled)
>[    0.000000] ACPI: LAPIC (acpi_id[0x03] lapic_id[0x04] enabled)
>[    0.000000] ACPI: LAPIC (acpi_id[0x04] lapic_id[0x06] enabled)
>[    0.000000] ACPI: LAPIC_NMI (acpi_id[0x01] high level lint[0x1])
>[    0.000000] ACPI: LAPIC_NMI (acpi_id[0x02] high level lint[0x1])
>[    0.000000] ACPI: LAPIC_NMI (acpi_id[0x03] high level lint[0x1])
>[    0.000000] ACPI: LAPIC_NMI (acpi_id[0x04] high level lint[0x1])
>[    0.000000] ACPI: IOAPIC (id[0x01] address[0xfec00000] gsi_base[0])
>[    0.000000] IOAPIC[0]: apic_id 1, version 32, address 0xfec00000, GSI 0-114
>[    0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl)
>[    0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 high level)
>[    0.000000] ACPI: IRQ0 used by override.
>[    0.000000] ACPI: IRQ9 used by override.
>[    0.000000] Using ACPI (MADT) for SMP configuration information
>[    0.000000] ACPI: HPET id: 0x8086a201 base: 0xfed00000
>[    0.000000] smpboot: Allowing 4 CPUs, 0 hotplug CPUs
>[    0.000000] PM: Registered nosave memory: [mem 0x00000000-0x00000fff]
>[    0.000000] PM: Registered nosave memory: [mem 0x0008f000-0x0008ffff]
>[    0.000000] PM: Registered nosave memory: [mem 0x0009e000-0x0009ffff]
>[    0.000000] PM: Registered nosave memory: [mem 0x000a0000-0x000fffff]
>[    0.000000] PM: Registered nosave memory: [mem 0x20000000-0x201fffff]
>[    0.000000] PM: Registered nosave memory: [mem 0x7ac37000-0x7b636fff]
>[    0.000000] PM: Registered nosave memory: [mem 0x7b637000-0x7b736fff]
>[    0.000000] PM: Registered nosave memory: [mem 0x7b737000-0x7b776fff]
>[    0.000000] PM: Registered nosave memory: [mem 0x7b778000-0x7b778fff]
>[    0.000000] PM: Registered nosave memory: [mem 0x7b77c000-0x7b77cfff]
>[    0.000000] PM: Registered nosave memory: [mem 0x7c000000-0x7cdfffff]
>[    0.000000] PM: Registered nosave memory: [mem 0x7ce00000-0x7edfffff]
>[    0.000000] PM: Registered nosave memory: [mem 0x7ee00000-0xdfffffff]
>[    0.000000] PM: Registered nosave memory: [mem 0xe0000000-0xe3ffffff]
>[    0.000000] PM: Registered nosave memory: [mem 0xe4000000-0xfe9fffff]
>[    0.000000] PM: Registered nosave memory: [mem 0xfea00000-0xfeafffff]
>[    0.000000] PM: Registered nosave memory: [mem 0xfeb00000-0xfebfffff]
>[    0.000000] PM: Registered nosave memory: [mem 0xfec00000-0xfec00fff]
>[    0.000000] PM: Registered nosave memory: [mem 0xfec01000-0xfed00fff]
>[    0.000000] PM: Registered nosave memory: [mem 0xfed01000-0xfed01fff]
>[    0.000000] PM: Registered nosave memory: [mem 0xfed02000-0xfed02fff]
>[    0.000000] PM: Registered nosave memory: [mem 0xfed03000-0xfed03fff]
>[    0.000000] PM: Registered nosave memory: [mem 0xfed04000-0xfed05fff]
>[    0.000000] PM: Registered nosave memory: [mem 0xfed06000-0xfed06fff]
>[    0.000000] PM: Registered nosave memory: [mem 0xfed07000-0xfed07fff]
>[    0.000000] PM: Registered nosave memory: [mem 0xfed08000-0xfed09fff]
>[    0.000000] PM: Registered nosave memory: [mem 0xfed0a000-0xfed1bfff]
>[    0.000000] PM: Registered nosave memory: [mem 0xfed1c000-0xfed1cfff]
>[    0.000000] PM: Registered nosave memory: [mem 0xfed1d000-0xfed7ffff]
>[    0.000000] PM: Registered nosave memory: [mem 0xfed80000-0xfedbffff]
>[    0.000000] PM: Registered nosave memory: [mem 0xfedc0000-0xfedfffff]
>[    0.000000] PM: Registered nosave memory: [mem 0xfee00000-0xfee00fff]
>[    0.000000] PM: Registered nosave memory: [mem 0xfee01000-0xffffffff]
>[    0.000000] e820: [mem 0x7ee00000-0xdfffffff] available for PCI devices
>[    0.000000] setup_percpu: NR_CPUS:64 nr_cpumask_bits:64 nr_cpu_ids:4 nr_node_ids:1
>[    0.000000] PERCPU: Embedded 30 pages/cpu @ffff88017f800000 s82904 r8192 d31784 u524288
>[    0.000000] pcpu-alloc: s82904 r8192 d31784 u524288 alloc=1*2097152
>[    0.000000] pcpu-alloc: [0] 0 1 2 3 
>[    0.000000] Built 1 zonelists in Node order, mobility grouping on.  Total pages: 1012602
>[    0.000000] Policy zone: Normal
>[    0.000000] Kernel command line: BOOT_IMAGE=kernels//drm-intel-testing/drm-intel-testing-2015-03-13/bzImage_x86_64 root=/dev/sda3 drm.debug=0xe log_buf_len=4M hostname=x-bsw14 modules_path=kernels//drm-intel-testing/drm-intel-testing-2015-03-13/modules_x86_64/lib/modules/4.0.0-rc3_drm-intel-testing-2015-03-13+ acpi_rsdp=0x7b776014 kexec_jump_back_entry=0x71ace358
>[    0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes)
>[    0.000000] AGP: Checking aperture...
>[    0.000000] AGP: No AGP bridge found
>[    0.000000] Calgary: detecting Calgary via BIOS EBDA area
>[    0.000000] Calgary: Unable to locate Rio Grande table in EBDA - bailing!
>[    0.000000] Memory: 3941724K/4114792K available (7800K kernel code, 891K rwdata, 4016K rodata, 23280K init, 624K bss, 173068K reserved, 0K cma-reserved)
>[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
>[    0.000000] Hierarchical RCU implementation.
>[    0.000000] 	RCU restricting CPUs from NR_CPUS=64 to nr_cpu_ids=4.
>[    0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
>[    0.000000] NR_IRQS:4352 nr_irqs:1024 16
>[    0.000000] Console: colour dummy device 80x25
>[    0.000000] console [tty0] enabled
>[    0.000000] hpet clockevent registered
>[    0.000000] tsc: Fast TSC calibration failed
>[    0.000000] tsc: PIT calibration matches HPET. 1 loops
>[    0.000000] tsc: Detected 1519.927 MHz processor
>[    0.000004] Calibrating delay loop (skipped), value calculated using timer frequency.. 3039.85 BogoMIPS (lpj=1519927)
>[    0.000025] pid_max: default: 32768 minimum: 301
>[    0.000049] ACPI: Core revision 20150204
>[    0.022595] ACPI: All ACPI Tables successfully acquired
>[    0.022674] Security Framework initialized
>[    0.023266] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes)
>[    0.025677] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes)
>[    0.026774] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes)
>[    0.026799] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes)
>[    0.027287] CPU: Physical Processor ID: 0
>[    0.027302] CPU: Processor Core ID: 0
>[    0.032752] mce: CPU supports 6 MCE banks
>[    0.032773] CPU0: Thermal LVT vector (0xfa) already installed
>[    0.032786] Last level iTLB entries: 4KB 48, 2MB 0, 4MB 0
>[    0.032798] Last level dTLB entries: 4KB 256, 2MB 16, 4MB 16, 1GB 0
>[    0.032988] Freeing SMP alternatives memory: 32K (ffffffff83329000 - ffffffff83331000)
>[    0.035403] ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1
>[    0.045437] TSC deadline timer enabled
>[    0.045444] smpboot: CPU0: Genuine Intel(R) CPU         @ 1.52GHz (fam: 06, model: 4c, stepping: 03)
>[    0.045508] Performance Events: PEBS fmt2+, 8-deep LBR, Silvermont events, full-width counters, Intel PMU driver.
>[    0.045549] ... version:                3
>[    0.045559] ... bit width:              40
>[    0.045569] ... generic registers:      2
>[    0.045579] ... value mask:             000000ffffffffff
>[    0.045589] ... max period:             000000ffffffffff
>[    0.045599] ... fixed-purpose events:   3
>[    0.045609] ... event mask:             0000000700000003
>[    0.046316] x86: Booting SMP configuration:
>[    0.046335] .... node  #0, CPUs:      #1
>[    0.062912] CPU1: Thermal LVT vector (0xfa) already installed
>[    0.065242]  #2<7>[    0.081832] CPU2: Thermal LVT vector (0xfa) already installed
>[    0.100684]  #3
>[    0.100685] CPU3: Thermal LVT vector (0xfa) already installed
>[    0.102791] x86: Booted up 1 node, 4 CPUs
>[    0.102815] smpboot: Total of 4 processors activated (12159.41 BogoMIPS)
>[    0.103853] devtmpfs: initialized
>[    0.104699] PM: Registering ACPI NVS region [mem 0x0008f000-0x0008ffff] (4096 bytes)
>[    0.104719] PM: Registering ACPI NVS region [mem 0x7b637000-0x7b736fff] (1048576 bytes)
>[    0.105119] xor: measuring software checksum speed
>[    0.114827]    prefetch64-sse:  5300.000 MB/sec
>[    0.124872]    generic_sse:  4720.000 MB/sec
>[    0.124883] xor: using function: prefetch64-sse (5300.000 MB/sec)
>[    0.124962] RTC time: 12:04:33, date: 01/20/15
>[    0.125298] NET: Registered protocol family 16
>[    0.131917] cpuidle: using governor ladder
>[    0.137939] cpuidle: using governor menu
>[    0.138254] ACPI: bus type PCI registered
>[    0.138359] PCI: MMCONFIG for domain 0000 [bus 00-3f] at [mem 0xe0000000-0xe3ffffff] (base 0xe0000000)
>[    0.138384] PCI: MMCONFIG at [mem 0xe0000000-0xe3ffffff] reserved in E820
>[    0.138583] PCI: Using configuration type 1 for base access
>[    0.165116] raid6: sse2x1     542 MB/s
>[    0.182203] raid6: sse2x2     679 MB/s
>[    0.199208] raid6: sse2x4    1191 MB/s
>[    0.199220] raid6: using algorithm sse2x4 (1191 MB/s)
>[    0.199233] raid6: using ssse3x2 recovery algorithm
>[    0.199353] ACPI: Added _OSI(Module Device)
>[    0.199366] ACPI: Added _OSI(Processor Device)
>[    0.199377] ACPI: Added _OSI(3.0 _SCP Extensions)
>[    0.199388] ACPI: Added _OSI(Processor Aggregator Device)
>[    0.215052] ACPI: Dynamic OEM Table Load:
>[    0.215085] ACPI: SSDT 0xFFFF880179CC9800 000676 (v01 PmRef  Cpu0Ist  00003000 INTL 20141107)
>[    0.216400] ACPI: Dynamic OEM Table Load:
>[    0.216422] ACPI: SSDT 0xFFFF88017A2BB800 0003A5 (v01 PmRef  Cpu0Cst  00003001 INTL 20141107)
>[    0.218128] ACPI: Dynamic OEM Table Load:
>[    0.218150] ACPI: SSDT 0xFFFF880179E45C00 00015F (v01 PmRef  ApIst    00003000 INTL 20141107)
>[    0.219412] ACPI: Dynamic OEM Table Load:
>[    0.219434] ACPI: SSDT 0xFFFF88017A313540 00008D (v01 PmRef  ApCst    00003000 INTL 20141107)
>[    0.428713] ACPI: Interpreter enabled
>[    0.428744] ACPI Exception: AE_NOT_FOUND, While evaluating Sleep State [\_S1_] (20150204/hwxface-580)
>[    0.428777] ACPI Exception: AE_NOT_FOUND, While evaluating Sleep State [\_S2_] (20150204/hwxface-580)
>[    0.428837] ACPI: (supports S0 S3 S4 S5)
>[    0.428851] ACPI: Using IOAPIC for interrupt routing
>[    0.428962] PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug
>[    0.432825] ACPI: Power Resource [USBC] (on)
>[    0.440733] ACPI: Power Resource [CLK0] (off)
>[    0.441319] ACPI: Power Resource [CLK0] (off)
>[    0.441428] ACPI: Power Resource [CLK1] (off)
>[    0.447401] ACPI: Power Resource [ID3C] (on)
>[    0.453393] ACPI: Power Resource [FN00] (off)
>[    0.454581] ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-ff])
>[    0.454609] acpi PNP0A08:00: _OSC: OS supports [ExtendedConfig ASPM ClockPM Segments MSI]
>[    0.455120] acpi PNP0A08:00: _OSC: OS now controls [PCIeHotplug PME AER PCIeCapability]
>[    0.455395] acpi PNP0A08:00: [Firmware Info]: MMCONFIG for domain 0000 [bus 00-3f] only partially covers this bridge
>[    0.455500] PCI host bridge to bus 0000:00
>[    0.455516] pci_bus 0000:00: root bus resource [bus 00-ff]
>[    0.455530] pci_bus 0000:00: root bus resource [io  0x0000-0x006f window]
>[    0.455544] pci_bus 0000:00: root bus resource [io  0x0078-0x0cf7 window]
>[    0.455557] pci_bus 0000:00: root bus resource [io  0x0d00-0xffff window]
>[    0.455571] pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff window]
>[    0.455590] pci_bus 0000:00: root bus resource [mem 0x000c0000-0x000dffff window]
>[    0.455609] pci_bus 0000:00: root bus resource [mem 0x000e0000-0x000fffff window]
>[    0.455628] pci_bus 0000:00: root bus resource [mem 0x80000000-0xdfffffff window]
>[    0.455661] pci 0000:00:00.0: [8086:2280] type 00 class 0x060000
>[    0.455983] pci 0000:00:02.0: [8086:22b1] type 00 class 0x030000
>[    0.456020] pci 0000:00:02.0: reg 0x10: [mem 0x90000000-0x90ffffff 64bit]
>[    0.456037] pci 0000:00:02.0: reg 0x18: [mem 0x80000000-0x8fffffff 64bit pref]
>[    0.456050] pci 0000:00:02.0: reg 0x20: [io  0x1000-0x103f]
>[    0.456304] pci 0000:00:03.0: [8086:22b8] type 00 class 0x048000
>[    0.456329] pci 0000:00:03.0: reg 0x10: [mem 0x91000000-0x913fffff]
>[    0.456623] pci 0000:00:0b.0: [8086:22dc] type 00 class 0x118000
>[    0.456653] pci 0000:00:0b.0: reg 0x10: [mem 0x9171c000-0x9171cfff 64bit]
>[    0.456911] pci 0000:00:13.0: [8086:22a3] type 00 class 0x010601
>[    0.456981] pci 0000:00:13.0: reg 0x20: [io  0x1060-0x107f]
>[    0.456996] pci 0000:00:13.0: reg 0x24: [mem 0x91730000-0x917307ff]
>[    0.457076] pci 0000:00:13.0: PME# supported from D3hot
>[    0.457279] pci 0000:00:14.0: [8086:22b5] type 00 class 0x0c0330
>[    0.457316] pci 0000:00:14.0: reg 0x10: [mem 0x91700000-0x9170ffff 64bit]
>[    0.457425] pci 0000:00:14.0: PME# supported from D3hot D3cold
>[    0.457540] pci 0000:00:14.0: System wakeup disabled by ACPI
>[    0.457669] pci 0000:00:1a.0: [8086:2298] type 00 class 0x108000
>[    0.457700] pci 0000:00:1a.0: reg 0x10: [mem 0x91600000-0x916fffff]
>[    0.457715] pci 0000:00:1a.0: reg 0x14: [mem 0x91500000-0x915fffff]
>[    0.457821] pci 0000:00:1a.0: PME# supported from D0 D3hot
>[    0.458036] pci 0000:00:1b.0: [8086:2284] type 00 class 0x040300
>[    0.458070] pci 0000:00:1b.0: reg 0x10: [mem 0x91710000-0x91713fff 64bit]
>[    0.458216] pci 0000:00:1b.0: PME# supported from D0 D3hot D3cold
>[    0.458344] pci 0000:00:1b.0: System wakeup disabled by ACPI
>[    0.458619] pci 0000:00:1c.0: [8086:22c8] type 01 class 0x060400
>[    0.460281] pci 0000:00:1c.0: PME# supported from D0 D3hot D3cold
>[    0.460636] pci 0000:00:1c.0: System wakeup disabled by ACPI
>[    0.460907] pci 0000:00:1c.1: [8086:22ca] type 01 class 0x060400
>[    0.462645] pci 0000:00:1c.1: PME# supported from D0 D3hot D3cold
>[    0.462992] pci 0000:00:1c.1: System wakeup disabled by ACPI
>[    0.463120] pci 0000:00:1f.0: [8086:229c] type 00 class 0x060100
>[    0.463453] pci 0000:00:1f.3: [8086:2292] type 00 class 0x0c0500
>[    0.463514] pci 0000:00:1f.3: reg 0x10: [mem 0x9171d000-0x9171d01f]
>[    0.463642] pci 0000:00:1f.3: reg 0x20: [io  0x1040-0x105f]
>[    0.464821] pci 0000:00:1c.0: PCI bridge to [bus 01]
>[    0.464878] pci 0000:00:1c.0:   bridge window [io  0x2000-0x2fff]
>[    0.464925] pci 0000:00:1c.0:   bridge window [mem 0x91800000-0x919fffff]
>[    0.465014] pci 0000:00:1c.0:   bridge window [mem 0x91a00000-0x91bfffff 64bit pref]
>[    0.466563] pci 0000:02:00.0: [8086:095a] type 00 class 0x028000
>[    0.467553] pci 0000:02:00.0: reg 0x10: [mem 0x91400000-0x91401fff 64bit]
>[    0.471653] pci 0000:02:00.0: PME# supported from D0 D3hot D3cold
>[    0.472409] pci 0000:02:00.0: System wakeup disabled by ACPI
>[    0.475421] pci 0000:00:1c.1: PCI bridge to [bus 02]
>[    0.475521] pci 0000:00:1c.1:   bridge window [mem 0x91400000-0x914fffff]
>[    0.480544] ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 5 6 10 11 12 14 15) *0, disabled.
>[    0.480709] ACPI: PCI Interrupt Link [LNKB] (IRQs 3 4 5 6 10 11 12 14 15) *0, disabled.
>[    0.480868] ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 5 6 10 11 12 14 15) *0, disabled.
>[    0.481030] ACPI: PCI Interrupt Link [LNKD] (IRQs 3 4 5 6 10 11 12 14 15) *0, disabled.
>[    0.481205] ACPI: PCI Interrupt Link [LNKE] (IRQs 3 4 5 6 10 11 12 14 15) *0, disabled.
>[    0.481360] ACPI: PCI Interrupt Link [LNKF] (IRQs 3 4 5 6 10 11 12 14 15) *0, disabled.
>[    0.481519] ACPI: PCI Interrupt Link [LNKG] (IRQs 3 4 5 6 10 11 12 14 15) *0, disabled.
>[    0.481678] ACPI: PCI Interrupt Link [LNKH] (IRQs 3 4 5 6 10 11 12 14 15) *0, disabled.
>[    0.483535] ACPI: Enabled 5 GPEs in block 00 to 3F
>[    0.483658] ACPI : EC: GPE = 0x16, I/O: command/status = 0x66, data = 0x62
>[    0.483980] vgaarb: setting as boot device: PCI:0000:00:02.0
>[    0.483998] vgaarb: device added: PCI:0000:00:02.0,decodes=io+mem,owns=io+mem,locks=none
>[    0.484021] vgaarb: loaded
>[    0.484031] vgaarb: bridge control possible 0000:00:02.0
>[    0.484302] SCSI subsystem initialized
>[    0.484456] libata version 3.00 loaded.
>[    0.484555] ACPI: bus type USB registered
>[    0.484636] usbcore: registered new interface driver usbfs
>[    0.484682] usbcore: registered new interface driver hub
>[    0.484746] usbcore: registered new device driver usb
>[    0.484840] pps_core: LinuxPPS API ver. 1 registered
>[    0.484852] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
>[    0.484885] PTP clock support registered
>[    0.485098] PCI: Using ACPI for IRQ routing
>[    0.487880] PCI: pci_cache_line_size set to 64 bytes
>[    0.488366] e820: reserve RAM buffer [mem 0x0008f000-0x0008ffff]
>[    0.488373] e820: reserve RAM buffer [mem 0x0009e000-0x0009ffff]
>[    0.488376] e820: reserve RAM buffer [mem 0x7ac37000-0x7bffffff]
>[    0.488380] e820: reserve RAM buffer [mem 0x7b778000-0x7bffffff]
>[    0.488384] e820: reserve RAM buffer [mem 0x7b77c000-0x7bffffff]
>[    0.488698] NetLabel: Initializing
>[    0.488713] NetLabel:  domain hash size = 128
>[    0.488723] NetLabel:  protocols = UNLABELED CIPSOv4
>[    0.488767] NetLabel:  unlabeled traffic allowed by default
>[    0.489073] hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0
>[    0.489091] hpet0: 3 comparators, 64-bit 14.318180 MHz counter
>[    0.491173] Switched to clocksource hpet
>[    0.499215] pnp: PnP ACPI init
>[    0.499865] system 00:00: [io  0x0680-0x069f] has been reserved
>[    0.499881] system 00:00: [io  0x0400-0x047f] has been reserved
>[    0.499895] system 00:00: [io  0x0500-0x05fe] has been reserved
>[    0.499913] system 00:00: Plug and Play ACPI device, IDs PNP0c02 (active)
>[    0.500094] pnp 00:01: Plug and Play ACPI device, IDs PNP0501 (active)
>[    0.500270] pnp 00:02: Plug and Play ACPI device, IDs PNP0303 (active)
>[    0.500406] pnp 00:03: Plug and Play ACPI device, IDs PNP0f13 (active)
>[    0.502350] pnp 00:04: unknown resource type 19 in _CRS
>[    0.502364] pnp 00:04: can't evaluate _CRS: 1
>[    0.502441] system 00:04: Plug and Play ACPI device, IDs PNP0c02 (active)
>[    0.504043] system 00:05: [mem 0x91733000-0x91733fff] has been reserved
>[    0.504060] system 00:05: [mem 0x91731000-0x91731fff] has been reserved
>[    0.504074] system 00:05: [mem 0x91722000-0x91722fff] has been reserved
>[    0.504088] system 00:05: [mem 0x91720000-0x91720fff] has been reserved
>[    0.504102] system 00:05: [mem 0x9171e000-0x9171efff] has been reserved
>[    0.504115] system 00:05: [mem 0x9172f000-0x9172ffff] has been reserved
>[    0.504129] system 00:05: [mem 0x9172d000-0x9172dfff] has been reserved
>[    0.504145] system 00:05: [mem 0x9172b000-0x9172bfff] has been reserved
>[    0.504168] system 00:05: [mem 0x91729000-0x91729fff] has been reserved
>[    0.504214] system 00:05: [mem 0x91727000-0x91727fff] has been reserved
>[    0.504230] system 00:05: [mem 0x91725000-0x91725fff] has been reserved
>[    0.504244] system 00:05: [mem 0x91723000-0x91723fff] has been reserved
>[    0.504259] system 00:05: Plug and Play ACPI device, IDs PNP0c02 (active)
>[    0.504466] system 00:06: [mem 0xe0000000-0xefffffff] could not be reserved
>[    0.504482] system 00:06: [mem 0xfea00000-0xfeafffff] has been reserved
>[    0.504496] system 00:06: [mem 0xfed01000-0xfed01fff] has been reserved
>[    0.504509] system 00:06: [mem 0xfed03000-0xfed03fff] has been reserved
>[    0.504523] system 00:06: [mem 0xfed06000-0xfed06fff] has been reserved
>[    0.504537] system 00:06: [mem 0xfed08000-0xfed09fff] has been reserved
>[    0.504552] system 00:06: [mem 0xfed80000-0xfedbffff] could not be reserved
>[    0.504566] system 00:06: [mem 0xfed1c000-0xfed1cfff] has been reserved
>[    0.504580] system 00:06: [mem 0xfee00000-0xfeefffff] could not be reserved
>[    0.504595] system 00:06: Plug and Play ACPI device, IDs PNP0c02 (active)
>[    0.504953] pnp 00:07: Plug and Play ACPI device, IDs PNP0b00 (active)
>[    0.505305] pnp: PnP ACPI: found 8 devices
>[    0.515940] pci 0000:00:1c.0: PCI bridge to [bus 01]
>[    0.515982] pci 0000:00:1c.0:   bridge window [io  0x2000-0x2fff]
>[    0.516062] pci 0000:00:1c.0:   bridge window [mem 0x91800000-0x919fffff]
>[    0.516119] pci 0000:00:1c.0:   bridge window [mem 0x91a00000-0x91bfffff 64bit pref]
>[    0.516255] pci 0000:00:1c.1: PCI bridge to [bus 02]
>[    0.516331] pci 0000:00:1c.1:   bridge window [mem 0x91400000-0x914fffff]
>[    0.516475] pci_bus 0000:00: resource 4 [io  0x0000-0x006f window]
>[    0.516480] pci_bus 0000:00: resource 5 [io  0x0078-0x0cf7 window]
>[    0.516485] pci_bus 0000:00: resource 6 [io  0x0d00-0xffff window]
>[    0.516491] pci_bus 0000:00: resource 7 [mem 0x000a0000-0x000bffff window]
>[    0.516496] pci_bus 0000:00: resource 8 [mem 0x000c0000-0x000dffff window]
>[    0.516501] pci_bus 0000:00: resource 9 [mem 0x000e0000-0x000fffff window]
>[    0.516506] pci_bus 0000:00: resource 10 [mem 0x80000000-0xdfffffff window]
>[    0.516511] pci_bus 0000:01: resource 0 [io  0x2000-0x2fff]
>[    0.516516] pci_bus 0000:01: resource 1 [mem 0x91800000-0x919fffff]
>[    0.516522] pci_bus 0000:01: resource 2 [mem 0x91a00000-0x91bfffff 64bit pref]
>[    0.516527] pci_bus 0000:02: resource 1 [mem 0x91400000-0x914fffff]
>[    0.516604] NET: Registered protocol family 2
>[    0.517092] TCP established hash table entries: 32768 (order: 6, 262144 bytes)
>[    0.517358] TCP bind hash table entries: 32768 (order: 7, 524288 bytes)
>[    0.517573] TCP: Hash tables configured (established 32768 bind 32768)
>[    0.517651] TCP: reno registered
>[    0.517681] UDP hash table entries: 2048 (order: 4, 65536 bytes)
>[    0.517746] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes)
>[    0.517919] NET: Registered protocol family 1
>[    0.518131] RPC: Registered named UNIX socket transport module.
>[    0.518146] RPC: Registered udp transport module.
>[    0.518156] RPC: Registered tcp transport module.
>[    0.518166] RPC: Registered tcp NFSv4.1 backchannel transport module.
>[    0.518278] pci 0000:00:02.0: Video device with shadowed ROM
>[    0.518792] PCI: CLS 0 bytes, default 64
>[    1.423548] PCI-DMA: Using software bounce buffering for IO (SWIOTLB)
>[    1.423572] software IO TLB [mem 0x76c37000-0x7ac37000] (64MB) mapped at [ffff880076c37000-ffff88007ac36fff]
>[    1.425695] futex hash table entries: 1024 (order: 4, 65536 bytes)
>[    1.425776] audit: initializing netlink subsys (disabled)
>[    1.425811] audit: type=2000 audit(1421755473.381:1): initialized
>[    1.426318] HugeTLB registered 2 MB page size, pre-allocated 0 pages
>[    1.431005] VFS: Disk quotas dquot_6.5.2
>[    1.431116] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
>[    1.432887] NFS: Registering the id_resolver key type
>[    1.432932] Key type id_resolver registered
>[    1.432945] Key type id_legacy registered
>[    1.432964] Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
>[    1.433374] fuse init (API version 7.23)
>[    1.434335] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 250)
>[    1.434363] io scheduler noop registered
>[    1.434379] io scheduler deadline registered
>[    1.434479] io scheduler cfq registered (default)
>[    1.438015] pcieport 0000:00:1c.0: Signaling PME through PCIe PME interrupt
>[    1.438078] pcie_pme 0000:00:1c.0:pcie01: service driver pcie_pme loaded
>[    1.438271] pcieport 0000:00:1c.1: Signaling PME through PCIe PME interrupt
>[    1.438287] pci 0000:02:00.0: Signaling PME through PCIe PME interrupt
>[    1.438343] pcie_pme 0000:00:1c.1:pcie01: service driver pcie_pme loaded
>[    1.438373] pci_hotplug: PCI Hot Plug PCI Core version: 0.5
>[    1.438466] efifb: probing for efifb
>[    1.438526] efifb: framebuffer at 0x80000000, mapped to 0xffffc90004800000, using 8100k, total 8100k
>[    1.438548] efifb: mode is 1920x1080x32, linelength=7680, pages=2032
>[    1.438558] efifb: scrolling: redraw
>[    1.438571] efifb: Truecolor: size=8:8:8:8, shift=24:16:8:0
>[    1.459838] Console: switching to colour frame buffer device 240x67
>[    1.479565] fb0: EFI VGA frame buffer device
>[    1.483942] Monitor-Mwait will be used to enter C-1 state
>[    1.483974] Monitor-Mwait will be used to enter C-2 state
>[    1.484000] Monitor-Mwait will be used to enter C-3 state
>[    1.484046] ACPI: acpi_idle registered with cpuidle
>[    1.491490] thermal LNXTHERM:00: registered as thermal_zone0
>[    1.491592] ACPI: Thermal Zone [TZ01] (45 C)
>[    1.491824] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
>[    1.512452] 00:01: ttyS0 at I/O 0x3f8 (irq = 4, base_baud = 115200) is a 16550A
>[    1.513836] Non-volatile memory driver v1.3
>[    1.514007] Linux agpgart interface v0.103
>[    1.519018] brd: module loaded
>[    1.519208] Loading iSCSI transport class v2.0-870.
>[    1.519688] iscsi: registered transport (tcp)
>[    1.520021] Adaptec aacraid driver 1.2-0[30300]-ms
>[    1.520149] aic94xx: Adaptec aic94xx SAS/SATA driver version 1.0.3 loaded
>[    1.520428] qla2xxx [0000:00:00.0]-0005: : QLogic Fibre Channel HBA Driver: 8.07.00.16-k.
>[    1.520686] iscsi: registered transport (qla4xxx)
>[    1.520803] QLogic iSCSI HBA Driver
>[    1.520981] GDT-HA: Storage RAID Controller Driver. Version: 3.05
>[    1.521172] RocketRAID 3xxx/4xxx Controller driver v1.8
>[    1.521296] stex: Promise SuperTrak EX Driver version: 4.6.0000.4
>[    1.521473] st: Version 20101219, fixed bufsize 32768, s/g segs 256
>[    1.521657] osst :I: Tape driver with OnStream support version 0.99.4
>[    1.521657] osst :I: $Id: osst.c,v 1.73 2005/01/01 21:13:34 wriede Exp $
>[    1.522096] SCSI Media Changer driver v0.25 
>[    1.522239] ahci 0000:00:13.0: version 3.0
>[    1.522591] ahci 0000:00:13.0: AHCI 0001.0301 32 slots 2 ports 6 Gbps 0x3 impl SATA mode
>[    1.522761] ahci 0000:00:13.0: flags: 64bit ncq ilck pm led clo only pio slum part deso sadm sds apst 
>[    1.523684] scsi host0: ahci
>[    1.524058] scsi host1: ahci
>[    1.524249] ata1: SATA max UDMA/133 abar m2048@0x91730000 port 0x91730100 irq 117
>[    1.524371] ata2: SATA max UDMA/133 abar m2048@0x91730000 port 0x91730180 irq 117
>[    1.526814] bnx2x: Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver bnx2x 1.710.51-0 (2014/02/10)
>[    1.527234] e100: Intel(R) PRO/100 Network Driver, 3.5.24-k2-NAPI
>[    1.527333] e100: Copyright(c) 1999-2006 Intel Corporation
>[    1.527466] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
>[    1.527580] e1000: Copyright (c) 1999-2006 Intel Corporation.
>[    1.527751] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
>[    1.527845] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
>[    1.527983] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.2.15-k
>[    1.528095] igb: Copyright (c) 2007-2014 Intel Corporation.
>[    1.532750] usbcore: registered new interface driver catc
>[    1.537291] usbcore: registered new interface driver kaweth
>[    1.541755] pegasus: v0.9.3 (2013/04/25), Pegasus/Pegasus II USB Ethernet driver
>[    1.546281] usbcore: registered new interface driver pegasus
>[    1.550819] usbcore: registered new interface driver rtl8150
>[    1.555311] usbcore: registered new interface driver asix
>[    1.559795] usbcore: registered new interface driver ax88179_178a
>[    1.564211] usbcore: registered new interface driver cdc_ether
>[    1.568575] usbcore: registered new interface driver dm9601
>[    1.572877] usbcore: registered new interface driver gl620a
>[    1.577095] usbcore: registered new interface driver net1080
>[    1.581280] usbcore: registered new interface driver plusb
>[    1.585451] usbcore: registered new interface driver rndis_host
>[    1.589610] usbcore: registered new interface driver cdc_subset
>[    1.593728] usbcore: registered new interface driver zaurus
>[    1.597852] usbcore: registered new interface driver MOSCHIP usb-ethernet driver
>[    1.601986] usbcore: registered new interface driver cdc_ncm
>[    1.606328] xhci_hcd 0000:00:14.0: xHCI Host Controller
>[    1.610466] xhci_hcd 0000:00:14.0: new USB bus registered, assigned bus number 1
>[    1.614755] xhci_hcd 0000:00:14.0: hcc params 0x200077c1 hci version 0x100 quirks 0x00101810
>[    1.618811] xhci_hcd 0000:00:14.0: cache line size of 64 is not supported
>[    1.619006] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002
>[    1.623050] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
>[    1.627062] usb usb1: Product: xHCI Host Controller
>[    1.631076] usb usb1: Manufacturer: Linux 4.0.0-rc3_drm-intel-testing-2015-03-13+ xhci-hcd
>[    1.635157] usb usb1: SerialNumber: 0000:00:14.0
>[    1.639539] hub 1-0:1.0: USB hub found
>[    1.643545] hub 1-0:1.0: 7 ports detected
>[    1.648731] xhci_hcd 0000:00:14.0: xHCI Host Controller
>[    1.652808] xhci_hcd 0000:00:14.0: new USB bus registered, assigned bus number 2
>[    1.656834] usb usb2: New USB device found, idVendor=1d6b, idProduct=0003
>[    1.660754] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1
>[    1.664699] usb usb2: Product: xHCI Host Controller
>[    1.668631] usb usb2: Manufacturer: Linux 4.0.0-rc3_drm-intel-testing-2015-03-13+ xhci-hcd
>[    1.672646] usb usb2: SerialNumber: 0000:00:14.0
>[    1.676988] hub 2-0:1.0: USB hub found
>[    1.681017] hub 2-0:1.0: 6 ports detected
>[    1.686131] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
>[    1.690118] ehci-pci: EHCI PCI platform driver
>[    1.694099] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
>[    1.698048] ohci-pci: OHCI PCI platform driver
>[    1.701999] uhci_hcd: USB Universal Host Controller Interface driver
>[    1.706073] usbcore: registered new interface driver usb-storage
>[    1.710133] i8042: PNP: PS/2 Controller [PNP0303:PS2K,PNP0f13:PS2M] at 0x60,0x64 irq 1,12
>[    1.714570] i8042: Warning: Keylock active
>[    1.719961] serio: i8042 KBD port at 0x60,0x64 irq 1
>[    1.724035] serio: i8042 AUX port at 0x60,0x64 irq 12
>[    1.728282] mousedev: PS/2 mouse device common for all mice
>[    1.732636] rtc_cmos 00:07: RTC can wake from S4
>[    1.736905] rtc_cmos 00:07: rtc core: registered rtc_cmos as rtc0
>[    1.740855] rtc_cmos 00:07: alarms up to one month, y3k, 242 bytes nvram, hpet irqs
>[    1.744853] i2c /dev entries driver
>[    1.748981] hidraw: raw HID events driver (C) Jiri Kosina
>[    1.753598] usbcore: registered new interface driver usbhid
>[    1.757543] usbhid: USB HID core driver
>[    1.761520] TCP: cubic registered
>[    1.765316] Initializing XFRM netlink socket
>[    1.769092] NET: Registered protocol family 17
>[    1.772895] Key type dns_resolver registered
>[    1.777794] registered taskstats version 1
>[    1.782908] Btrfs loaded
>[    1.788199]   Magic number: 15:256:77
>[    1.792153] PM: Hibernation image not present or could not be loaded.
>[    1.792209] Warning: unable to open an initial console.
>[    1.830800] ata1: SATA link down (SStatus 4 SControl 300)
>[    1.834521] ata2: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
>[    1.872584] ata2.00: ATA-9: INTEL SSDSC2BW080A4, DC32, max UDMA/133
>[    1.876194] ata2.00: 156301488 sectors, multi 16: LBA48 NCQ (depth 31/32), AA
>[    1.909613] ata2.00: configured for UDMA/133
>[    1.913768] scsi 1:0:0:0: Direct-Access     ATA      INTEL SSDSC2BW08 DC32 PQ: 0 ANSI: 5
>[    1.918141] sd 1:0:0:0: [sda] 156301488 512-byte logical blocks: (80.0 GB/74.5 GiB)
>[    1.918144] sd 1:0:0:0: Attached scsi generic sg0 type 0
>[    1.926271] sd 1:0:0:0: [sda] Write Protect is off
>[    1.930262] sd 1:0:0:0: [sda] Mode Sense: 00 3a 00 00
>[    1.930315] sd 1:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA
>[    1.935566]  sda: sda1 sda2 sda3
>[    1.940485] sd 1:0:0:0: [sda] Attached SCSI disk
>[    1.955918] Freeing unused kernel memory: 23280K (ffffffff81c6d000 - ffffffff83329000)
>[    1.960871] atkbd serio0: Failed to deactivate keyboard on isa0060/serio0
>[    2.001908] usb 1-5: new full-speed USB device number 2 using xhci_hcd
>[    2.071198] dracut: dracut-018-35.git20120510.fc17
>[    2.170454] usb 1-5: No LPM exit latency info found, disabling LPM.
>[    2.175804] usb 1-5: New USB device found, idVendor=8087, idProduct=0a2a
>[    2.180246] usb 1-5: New USB device strings: Mfr=0, Product=0, SerialNumber=0
>[    2.185377] udevd[1255]: starting version 182
>[    2.226983] atkbd serio0: Failed to enable keyboard on isa0060/serio0
>[    2.231614] input: AT Translated Set 2 keyboard as /devices/platform/i8042/serio0/input/input0
>[    2.235773] [drm] Initialized drm 1.1.0 20060810
>[    2.238167] input: Lid Switch as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0D:00/input/input1
>[    2.240633] ACPI: Lid Switch [LID0]
>[    2.240808] input: Power Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0C:00/input/input2
>[    2.240912] ACPI: Power Button [PWRB]
>[    2.241074] input: Sleep Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0E:00/input/input3
>[    2.241167] ACPI: Sleep Button [SLPB]
>[    2.241313] input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input4
>[    2.244754] ACPI: Power Button [PWRF]
>[    2.260306] [drm:i915_dump_device_info] i915 device info: gen=8, pciid=0x22b1 rev=0x21 flags=need_gfx_hws,is_valleyview,has_hotplug,
>[    2.260307] [drm:intel_detect_pch] No PCH found.
>[    2.273045] [drm] Memory usable by graphics device = 2048M
>[    2.273048] [drm:i915_gem_gtt_init] GMADR size = 256M
>[    2.273050] [drm:i915_gem_gtt_init] GTT stolen size = 32M
>[    2.273052] [drm:i915_gem_gtt_init] ppgtt mode: 2
>[    2.273057] checking generic (80000000 7e9000) vs hw (80000000 10000000)
>[    2.273058] fb: switching to inteldrmfb from EFI VGA
>[    2.287309] Console: switching to colour dummy device 80x25
>[    2.287552] [drm] Replacing VGA console driver
>[    2.290187] [drm:intel_opregion_setup] graphic opregion physical addr: 0x7b6c3000
>[    2.290212] [drm:intel_opregion_setup] Public ACPI methods supported
>[    2.290217] [drm:intel_opregion_setup] ASLE supported
>[    2.290419] [drm:intel_device_info_runtime_init] slice total: 1
>[    2.290424] [drm:intel_device_info_runtime_init] subslice total: 2
>[    2.290427] [drm:intel_device_info_runtime_init] subslice per slice: 2
>[    2.290430] [drm:intel_device_info_runtime_init] EU total: 12
>[    2.290434] [drm:intel_device_info_runtime_init] EU per subslice: 6
>[    2.290437] [drm:intel_device_info_runtime_init] has slice power gating: n
>[    2.290440] [drm:intel_device_info_runtime_init] has subslice power gating: y
>[    2.290443] [drm:intel_device_info_runtime_init] has EU power gating: y
>[    2.290447] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
>[    2.290462] [drm] Driver supports precise vblank timestamp query.
>[    2.290475] [drm:init_vbt_defaults] Set default to SSC at 100000 kHz
>[    2.290480] [drm:validate_vbt] Using VBT from OpRegion: $VBT CHERRYVIEW     d
>[    2.290485] [drm:parse_general_features] BDB_GENERAL_FEATURES int_tv_support 0 int_crt_support 1 lvds_use_ssc 0 lvds_ssc_freq 120000 display_clock_mode 0 fdi_rx_polarity_inverted 0
>[    2.290489] [drm:parse_general_definitions] crt_ddc_bus_pin: 2
>[    2.290493] [drm:parse_lfp_panel_data] DRRS supported mode is seamless
>[    2.290498] [drm:parse_lfp_panel_data] Found panel mode in BIOS VBT tables:
>[    2.290505] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 0 65000 1024 1048 1184 1344 768 771 777 806 0x8 0xa
>[    2.290510] [drm:parse_lfp_panel_data] VBT initial LVDS value 0
>[    2.290514] [drm:parse_lfp_backlight] VBT backlight PWM modulation frequency 200 Hz, active high, min brightness 0, level 255
>[    2.290519] [drm:parse_sdvo_device_mapping] No SDVO device info is found in VBT
>[    2.290524] [drm:parse_driver_features] DRRS State Enabled:1
>[    2.290542] [drm:intel_dsm_pci_probe] no _DSM method for intel device
>[    2.290557] [drm:i915_gem_init_stolen] found 33554432 bytes of stolen memory at 7ce00000
>[    2.290566] [drm:intel_display_power_get] enabling always-on
>[    2.290569] [drm:intel_display_power_get] enabling pipe-a
>[    2.291989] [drm:intel_display_power_get] enabling dpio-common-bc
>[    2.294002] [drm:intel_display_power_get] enabling dpio-common-d
>[    2.320092] [drm:intel_modeset_init] 3 display pipes available.
>[    2.320137] vgaarb: device changed decodes: PCI:0000:00:02.0,olddecodes=io+mem,decodes=io+mem:owns=io+mem
>[    2.320622] [drm:intel_dp_init_connector] Adding DP connector on port B
>[    2.320722] [drm:intel_dp_aux_init] registering DPDDC-B bus for card0-DP-1
>[    2.321072] [drm:intel_dp_init_connector] Adding eDP connector on port C
>[    2.321182] [drm:vlv_initial_power_sequencer_setup] initial power sequencer for port C: pipe B
>[    2.321198] [drm:intel_dp_init_panel_power_sequencer] cur t1_t3 0 t8 0 t9 0 t10 0 t11_t12 4000
>[    2.321203] [drm:intel_dp_init_panel_power_sequencer] vbt t1_t3 2000 t8 10 t9 2000 t10 500 t11_t12 5000
>[    2.321208] [drm:intel_dp_init_panel_power_sequencer] panel power up delay 200, power down delay 50, power cycle delay 500
>[    2.321212] [drm:intel_dp_init_panel_power_sequencer] backlight on delay 1, off delay 200
>[    2.321220] [drm:intel_dp_init_panel_power_sequencer_registers] panel power sequencer register settings: PP_ON 0x87d00001, PP_OFF 0x1f40001, PP_DIV 0x270f05
>[    2.321225] [drm:intel_dp_aux_init] registering DPDDC-C bus for card0-eDP-1
>[    2.321471] [drm:intel_edp_panel_vdd_sanitize] VDD left on by BIOS, adjusting state tracking
>[    2.322033] [drm:intel_dp_get_dpcd] DPCD: 12 0a 82 41 00 00 01 80 02 00 00 00 0f 0b 00
>[    2.322441] [drm:intel_dp_get_dpcd] Detected EDP PSR Panel.
>[    2.322845] [drm:intel_dp_init_panel_power_sequencer_registers] panel power sequencer register settings: PP_ON 0x87d00001, PP_OFF 0x1f40001, PP_DIV 0x270f05
>[    2.326918] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[    2.326926] [drm:intel_dp_drrs_init] Downclock mode is not found. DRRS not supported
>[    2.326934] [drm:intel_edp_init_connector] using pipe B for initial backlight setup
>[    2.326947] [drm:intel_panel_setup_backlight] Connector eDP-1 backlight initialized, disabled, brightness 0/7812
>[    2.327138] [drm:intel_dp_init_connector] Adding DP connector on port D
>[    2.327232] [drm:intel_dp_aux_init] registering DPDDC-D bus for card0-DP-2
>[    2.327540] [drm:intel_dsi_init] 
>[    2.335039] [drm:intel_modeset_readout_hw_state] [CRTC:20] hw state readout: enabled
>[    2.335047] [drm:intel_modeset_readout_hw_state] [CRTC:25] hw state readout: disabled
>[    2.335057] [drm:intel_modeset_readout_hw_state] [CRTC:30] hw state readout: disabled
>[    2.335068] [drm:intel_modeset_readout_hw_state] [ENCODER:33:TMDS-33] hw state readout: disabled, pipe A
>[    2.335083] [drm:intel_modeset_readout_hw_state] [ENCODER:38:TMDS-38] hw state readout: enabled, pipe A
>[    2.335089] [drm:intel_modeset_readout_hw_state] [ENCODER:40:TMDS-40] hw state readout: disabled, pipe A
>[    2.335095] [drm:intel_modeset_readout_hw_state] [ENCODER:46:TMDS-46] hw state readout: disabled, pipe A
>[    2.335101] [drm:intel_modeset_readout_hw_state] [ENCODER:48:TMDS-48] hw state readout: disabled, pipe A
>[    2.335109] [drm:intel_modeset_readout_hw_state] [CONNECTOR:41:eDP-1] hw state readout: disabled
>[    2.335117] [drm:intel_modeset_readout_hw_state] [CONNECTOR:34:HDMI-A-1] hw state readout: disabled
>[    2.335124] [drm:intel_modeset_readout_hw_state] [CONNECTOR:39:DP-1] hw state readout: enabled
>[    2.335130] [drm:intel_modeset_readout_hw_state] [CONNECTOR:47:HDMI-A-2] hw state readout: disabled
>[    2.335135] [drm:intel_modeset_readout_hw_state] [CONNECTOR:49:DP-2] hw state readout: disabled
>[    2.335146] [drm:intel_dump_pipe_config] [CRTC:20][setup_hw_state] config for pipe A
>[    2.335149] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[    2.335153] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[    2.335158] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[    2.335163] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 3460300, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[    2.335167] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[    2.335171] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[    2.335174] [drm:intel_dump_pipe_config] requested mode:
>[    2.335181] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 1920 0 0 0 1080 0 0 0 0x0 0x0
>[    2.335184] [drm:intel_dump_pipe_config] adjusted mode:
>[    2.335190] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x5
>[    2.335197] [drm:intel_dump_crtc_timings] crtc timings: 148499 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x0 flags: 0x5
>[    2.335200] [drm:intel_dump_pipe_config] port clock: 270000
>[    2.335204] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[    2.335208] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[    2.335212] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[    2.335215] [drm:intel_dump_pipe_config] ips: 0
>[    2.335219] [drm:intel_dump_pipe_config] double wide: 0
>[    2.335226] [drm:intel_dump_pipe_config] [CRTC:25][setup_hw_state] config for pipe B
>[    2.335229] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[    2.335233] [drm:intel_dump_pipe_config] pipe bpp: 0, dithering: 0
>[    2.335237] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[    2.335242] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[    2.335246] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[    2.335250] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[    2.335253] [drm:intel_dump_pipe_config] requested mode:
>[    2.335258] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[    2.335261] [drm:intel_dump_pipe_config] adjusted mode:
>[    2.335267] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[    2.335272] [drm:intel_dump_crtc_timings] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[    2.335276] [drm:intel_dump_pipe_config] port clock: 0
>[    2.335279] [drm:intel_dump_pipe_config] pipe src size: 0x0
>[    2.335283] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[    2.335287] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[    2.335290] [drm:intel_dump_pipe_config] ips: 0
>[    2.335293] [drm:intel_dump_pipe_config] double wide: 0
>[    2.335300] [drm:intel_dump_pipe_config] [CRTC:30][setup_hw_state] config for pipe C
>[    2.335304] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[    2.335307] [drm:intel_dump_pipe_config] pipe bpp: 0, dithering: 0
>[    2.335312] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[    2.335316] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[    2.335321] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[    2.335324] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[    2.335327] [drm:intel_dump_pipe_config] requested mode:
>[    2.335333] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[    2.335336] [drm:intel_dump_pipe_config] adjusted mode:
>[    2.335342] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[    2.335347] [drm:intel_dump_crtc_timings] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[    2.335350] [drm:intel_dump_pipe_config] port clock: 0
>[    2.335354] [drm:intel_dump_pipe_config] pipe src size: 0x0
>[    2.335358] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[    2.335362] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[    2.335365] [drm:intel_dump_pipe_config] ips: 0
>[    2.335368] [drm:intel_dump_pipe_config] double wide: 0
>[    2.335377] [drm:intel_connector_check_state] [CONNECTOR:39:DP-1]
>[    2.335385] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[    2.335391] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[    2.335396] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[    2.335401] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[    2.335406] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[    2.335412] [drm:check_crtc_state] [CRTC:20]
>[    2.338061] usb 1-6: new high-speed USB device number 3 using xhci_hcd
>[    2.343012] [drm:check_crtc_state] [CRTC:25]
>[    2.343019] [drm:check_crtc_state] [CRTC:30]
>[    2.343037] [drm:i9xx_get_initial_plane_config] pipe/plane A/0 with fb: size=1920x1080@32, offset=0, pitch 7680, size 0x7e9000
>[    2.343043] [drm:i915_gem_object_create_stolen_for_preallocated] creating preallocated stolen object: stolen_offset=0, gtt_offset=0, size=7e9000
>[    2.343055] [drm:i915_pages_create_for_stolen] offset=0x0, size=8294400
>[    2.343065] [drm:intel_alloc_plane_obj] plane fb obj ffff880175556000
>[    2.343077] [drm:i915_gem_setup_global_gtt] reserving preallocated space: 0 + 7e9000
>[    2.343081] [drm:i915_gem_setup_global_gtt] clearing unused GTT space: [7e9000, 7ffff000]
>[    2.348799] [drm:gen8_ppgtt_init] Allocated 4 pages for page directories (2 wasted)
>[    2.348807] [drm:gen8_ppgtt_init] Allocated 2048 pages for page tables (1024 wasted)
>[    2.348812] [drm:i915_gem_context_init] LR context support initialized
>[    2.348916] [drm:i915_gem_object_create_stolen] creating stolen object: size=20000
>[    2.348923] [drm:i915_pages_create_for_stolen] offset=0x7e9000, size=131072
>[    2.349018] [drm:intel_init_pipe_control] render ring pipe control offset: 0x0081e000
>[    2.349043] [drm:i915_gem_object_create_stolen] creating stolen object: size=20000
>[    2.349050] [drm:i915_pages_create_for_stolen] offset=0x809000, size=131072
>[    2.349093] [drm:i915_gem_object_create_stolen] creating stolen object: size=20000
>[    2.349100] [drm:i915_pages_create_for_stolen] offset=0x829000, size=131072
>[    2.349142] [drm:i915_gem_object_create_stolen] creating stolen object: size=20000
>[    2.349148] [drm:i915_pages_create_for_stolen] offset=0x849000, size=131072
>[    2.349184] [drm:gen8_init_common_ring] Execlists enabled for render ring
>[    2.349191] [drm:gen8_init_common_ring] Execlists enabled for bsd ring
>[    2.349196] [drm:gen8_init_common_ring] Execlists enabled for blitter ring
>[    2.349201] [drm:gen8_init_common_ring] Execlists enabled for video enhancement ring
>[    2.349259] [drm:cherryview_setup_pctx] PCBR: 0x7edf8001
>[    2.351003] [drm:cherryview_init_gt_powersave] DDR speed: 1600 MHz
>[    2.353008] [drm:cherryview_init_gt_powersave] max GPU freq: 640 MHz (64)
>[    2.355008] [drm:cherryview_init_gt_powersave] RPe GPU freq: 400 MHz (40)
>[    2.357004] [drm:cherryview_init_gt_powersave] RP1(Guar) GPU freq: 400 MHz (40)
>[    2.359009] [drm:cherryview_init_gt_powersave] min GPU freq: 200 MHz (20)
>[    2.363010] [drm:vlv_update_cdclk] Current CD clock rate: 266667 kHz
>[    2.363164] [drm:intel_backlight_device_register] Connector eDP-1 backlight sysfs interface registered
>[    2.363301] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:41:eDP-1]
>[    2.363308] [drm:intel_dp_detect] [CONNECTOR:41:eDP-1]
>[    2.363683] [drm:intel_dp_probe_oui] Sink OUI: 001cf8
>[    2.364042] [drm:intel_dp_probe_oui] Branch OUI: 000000
>[    2.364050] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:41:eDP-1] status updated from 3 to 1
>[    2.364074] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[    2.364082] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:41:eDP-1] probed modes :
>[    2.364089] [drm:drm_mode_debug_printmodeline] Modeline 42:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[    2.364095] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:34:HDMI-A-1]
>[    2.364100] [drm:intel_hdmi_detect] [CONNECTOR:34:HDMI-A-1]
>[    2.364278] [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 r(1)
>[    2.364285] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[    2.364291] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:34:HDMI-A-1] status updated from 3 to 2
>[    2.364300] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:34:HDMI-A-1] disconnected
>[    2.364306] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:39:DP-1]
>[    2.364309] [drm:intel_dp_detect] [CONNECTOR:39:DP-1]
>[    2.364785] [drm:intel_dp_get_dpcd] DPCD: 11 0a 84 00 01 00 00 00 00 00 00 00 00 00 00
>[    2.364930] ACPI: Video Device [GFX0] (multi-head: yes  rom: no  post: no)
>[    2.366495] input: Video Bus as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/LNXVIDEO:00/input/input6
>[    2.366701] [drm] Initialized i915 1.6.0 20150227 for 0000:00:02.0 on minor 0
>[    2.372590] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[    2.372598] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:39:DP-1] status updated from 3 to 1
>[    2.372799] [drm:drm_edid_to_eld] ELD monitor ASUS PA238
>[    2.372805] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[    2.372875] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:39:DP-1] probed modes :
>[    2.372883] [drm:drm_mode_debug_printmodeline] Modeline 52:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[    2.372889] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[    2.372896] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[    2.372902] [drm:drm_mode_debug_printmodeline] Modeline 100:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[    2.372909] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[    2.372915] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[    2.372922] [drm:drm_mode_debug_printmodeline] Modeline 61:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[    2.372928] [drm:drm_mode_debug_printmodeline] Modeline 70:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[    2.372935] [drm:drm_mode_debug_printmodeline] Modeline 59:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[    2.372941] [drm:drm_mode_debug_printmodeline] Modeline 60:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6
>[    2.372948] [drm:drm_mode_debug_printmodeline] Modeline 57:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[    2.372954] [drm:drm_mode_debug_printmodeline] Modeline 58:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[    2.372961] [drm:drm_mode_debug_printmodeline] Modeline 62:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[    2.372967] [drm:drm_mode_debug_printmodeline] Modeline 54:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[    2.372974] [drm:drm_mode_debug_printmodeline] Modeline 94:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[    2.372980] [drm:drm_mode_debug_printmodeline] Modeline 55:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[    2.372987] [drm:drm_mode_debug_printmodeline] Modeline 90:"1440x576" 50 54000 1440 1464 1592 1728 576 581 586 625 0x40 0xa
>[    2.373041] [drm:drm_mode_debug_printmodeline] Modeline 71:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[    2.373048] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[    2.373054] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[    2.373061] [drm:drm_mode_debug_printmodeline] Modeline 102:"1440x480" 60 54054 1440 1472 1596 1716 480 489 495 525 0x40 0xa
>[    2.373067] [drm:drm_mode_debug_printmodeline] Modeline 88:"1440x480" 60 54000 1440 1472 1596 1716 480 489 495 525 0x40 0xa
>[    2.373074] [drm:drm_mode_debug_printmodeline] Modeline 74:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[    2.373080] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[    2.373087] [drm:drm_mode_debug_printmodeline] Modeline 76:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[    2.373093] [drm:drm_mode_debug_printmodeline] Modeline 63:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[    2.373099] [drm:drm_mode_debug_printmodeline] Modeline 64:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[    2.373106] [drm:drm_mode_debug_printmodeline] Modeline 56:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[    2.373112] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[    2.373119] [drm:drm_mode_debug_printmodeline] Modeline 53:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[    2.373125] [drm:drm_mode_debug_printmodeline] Modeline 65:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[    2.373131] [drm:drm_mode_debug_printmodeline] Modeline 66:"640x480" 73 31500 640 664 704 832 480 489 491 520 0x40 0xa
>[    2.373138] [drm:drm_mode_debug_printmodeline] Modeline 67:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[    2.373144] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[    2.373151] [drm:drm_mode_debug_printmodeline] Modeline 77:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[    2.373157] [drm:drm_mode_debug_printmodeline] Modeline 69:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[    2.373162] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:47:HDMI-A-2]
>[    2.373166] [drm:intel_hdmi_detect] [CONNECTOR:47:HDMI-A-2]
>[    2.397710] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[    2.397717] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:47:HDMI-A-2] status updated from 3 to 1
>[    2.397899] [drm:drm_edid_to_eld] ELD monitor ASUS VS239
>[    2.397905] [drm:parse_hdmi_vsdb] HDMI: DVI dual 0, max TMDS clock 0, latency present 0 0, video latency 0 0, audio latency 0 0
>[    2.397909] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[    2.397972] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:47:HDMI-A-2] probed modes :
>[    2.397979] [drm:drm_mode_debug_printmodeline] Modeline 79:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[    2.397985] [drm:drm_mode_debug_printmodeline] Modeline 128:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[    2.397992] [drm:drm_mode_debug_printmodeline] Modeline 121:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[    2.397998] [drm:drm_mode_debug_printmodeline] Modeline 136:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[    2.398024] [drm:drm_mode_debug_printmodeline] Modeline 126:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[    2.398031] [drm:drm_mode_debug_printmodeline] Modeline 120:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[    2.398037] [drm:drm_mode_debug_printmodeline] Modeline 95:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[    2.398044] [drm:drm_mode_debug_printmodeline] Modeline 106:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[    2.398050] [drm:drm_mode_debug_printmodeline] Modeline 89:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[    2.398057] [drm:drm_mode_debug_printmodeline] Modeline 91:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[    2.398063] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[    2.398070] [drm:drm_mode_debug_printmodeline] Modeline 97:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[    2.398076] [drm:drm_mode_debug_printmodeline] Modeline 96:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[    2.398083] [drm:drm_mode_debug_printmodeline] Modeline 81:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[    2.398089] [drm:drm_mode_debug_printmodeline] Modeline 130:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[    2.398096] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[    2.398102] [drm:drm_mode_debug_printmodeline] Modeline 124:"1440x576" 50 54000 1440 1464 1592 1728 576 581 586 625 0x40 0xa
>[    2.398109] [drm:drm_mode_debug_printmodeline] Modeline 107:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[    2.398115] [drm:drm_mode_debug_printmodeline] Modeline 108:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[    2.398122] [drm:drm_mode_debug_printmodeline] Modeline 109:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[    2.398128] [drm:drm_mode_debug_printmodeline] Modeline 137:"1440x480" 60 54054 1440 1472 1596 1716 480 489 495 525 0x40 0xa
>[    2.398135] [drm:drm_mode_debug_printmodeline] Modeline 122:"1440x480" 60 54000 1440 1472 1596 1716 480 489 495 525 0x40 0xa
>[    2.398141] [drm:drm_mode_debug_printmodeline] Modeline 110:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[    2.398148] [drm:drm_mode_debug_printmodeline] Modeline 111:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[    2.398154] [drm:drm_mode_debug_printmodeline] Modeline 112:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[    2.398161] [drm:drm_mode_debug_printmodeline] Modeline 98:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[    2.398167] [drm:drm_mode_debug_printmodeline] Modeline 99:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[    2.398173] [drm:drm_mode_debug_printmodeline] Modeline 83:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[    2.398180] [drm:drm_mode_debug_printmodeline] Modeline 129:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[    2.398186] [drm:drm_mode_debug_printmodeline] Modeline 80:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[    2.398193] [drm:drm_mode_debug_printmodeline] Modeline 101:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[    2.398199] [drm:drm_mode_debug_printmodeline] Modeline 103:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[    2.398205] [drm:drm_mode_debug_printmodeline] Modeline 104:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[    2.398212] [drm:drm_mode_debug_printmodeline] Modeline 113:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[    2.398218] [drm:drm_mode_debug_printmodeline] Modeline 105:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[    2.398223] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:49:DP-2]
>[    2.398227] [drm:intel_dp_detect] [CONNECTOR:49:DP-2]
>[    2.398737] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    2.398744] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 2 - cnt: 0
>[    2.399264] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    2.399272] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 2 - cnt: 1
>[    2.399787] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    2.399794] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 2 - cnt: 2
>[    2.400308] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    2.400314] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 2 - cnt: 3
>[    2.400822] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    2.400830] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 2 - cnt: 4
>[    2.400854] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[    2.401364] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    2.401371] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 2 - cnt: 5
>[    2.401890] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    2.401898] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 2 - cnt: 6
>[    2.402414] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    2.402419] [drm:intel_hpd_irq_handler] HPD interrupt storm detected on PIN 2
>[    2.402930] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    2.403442] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    2.403468] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[    2.405526] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    2.406039] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    2.406549] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    2.407064] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    2.407575] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    2.407599] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[    2.409529] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    2.410041] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    2.410549] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    2.411065] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    2.411573] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    2.411596] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[    2.413035] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:49:DP-2] status updated from 3 to 2
>[    2.413041] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:49:DP-2] disconnected
>[    2.413048] [drm:drm_setup_crtcs] 
>[    2.413054] [drm:drm_enable_connectors] connector 41 enabled? yes
>[    2.413058] [drm:drm_enable_connectors] connector 34 enabled? no
>[    2.413061] [drm:drm_enable_connectors] connector 39 enabled? yes
>[    2.413065] [drm:drm_enable_connectors] connector 47 enabled? yes
>[    2.413068] [drm:drm_enable_connectors] connector 49 enabled? no
>[    2.413073] [drm:intel_fb_initial_config] connector eDP-1 has no encoder or crtc, skipping
>[    2.413078] [drm:i915_hotplug_work_func] running encoder hotplug functions
>[    2.413082] [drm:intel_fb_initial_config] connector HDMI-A-1 not enabled, skipping
>[    2.413084] [drm:i915_hotplug_work_func] running encoder hotplug functions
>[    2.413090] [drm:intel_fb_initial_config] looking for cmdline mode on connector DP-1
>[    2.413094] [drm:intel_fb_initial_config] looking for preferred mode on connector DP-1 0
>[    2.413099] [drm:intel_fb_initial_config] connector DP-1 on pipe A [CRTC:20]: 1920x1080
>[    2.413102] [drm:intel_fb_initial_config] connector HDMI-A-2 has no encoder or crtc, skipping
>[    2.413106] [drm:intel_fb_initial_config] connector DP-2 not enabled, skipping
>[    2.413109] [drm:intel_fb_initial_config] fallback: Not all outputs enabled
>[    2.413113] [drm:intel_fb_initial_config] Enabled: 1, detected: 3
>[    2.413116] [drm:intel_fb_initial_config] Not using firmware configuration
>[    2.413121] [drm:drm_target_preferred] looking for cmdline mode on connector 41
>[    2.413125] [drm:drm_target_preferred] looking for preferred mode on connector 41 0
>[    2.413128] [drm:drm_target_preferred] found mode 1920x1080
>[    2.413131] [drm:drm_target_preferred] looking for cmdline mode on connector 39
>[    2.413135] [drm:drm_target_preferred] looking for preferred mode on connector 39 0
>[    2.413138] [drm:drm_target_preferred] found mode 1920x1080
>[    2.413142] [drm:drm_target_preferred] looking for cmdline mode on connector 47
>[    2.413145] [drm:drm_target_preferred] looking for preferred mode on connector 47 0
>[    2.413149] [drm:drm_target_preferred] found mode 1920x1080
>[    2.413152] [drm:drm_setup_crtcs] picking CRTCs for 8192x8192 config
>[    2.413163] [drm:drm_setup_crtcs] desired mode 1920x1080 set on crtc 20 (0,0)
>[    2.413169] [drm:drm_setup_crtcs] desired mode 1920x1080 set on crtc 25 (0,0)
>[    2.413174] [drm:drm_setup_crtcs] desired mode 1920x1080 set on crtc 30 (0,0)
>[    2.413179] [drm:intelfb_create] no BIOS fb, allocating a new one
>[    2.413183] [drm:i915_gem_object_create_stolen] creating stolen object: size=7e9000
>[    2.413197] [drm:i915_pages_create_for_stolen] offset=0x869000, size=8294400
>[    2.415573] [drm:intelfb_create] allocated 1920x1080 fb: 0x00887000, bo ffff880174c82000
>[    2.415731] fbcon: inteldrmfb (fb0) is primary device
>[    2.415943] [drm:intel_crtc_set_config] [CRTC:20] [FB:117] #connectors=1 (x y) (0 0)
>[    2.415947] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[    2.415952] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[    2.415956] [drm:drm_mode_debug_printmodeline] Modeline 114:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[    2.415958] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=1, fb_changed=1
>[    2.415961] [drm:intel_modeset_stage_output_state] [CONNECTOR:41:eDP-1] encoder changed, full mode switch
>[    2.415963] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [NOCRTC]
>[    2.415965] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] encoder changed, full mode switch
>[    2.415967] [drm:intel_modeset_stage_output_state] [CONNECTOR:41:eDP-1] to [CRTC:20]
>[    2.415969] [drm:intel_modeset_stage_output_state] [ENCODER:38:TMDS-38] crtc changed, full mode switch
>[    2.415971] [drm:intel_modeset_stage_output_state] [ENCODER:40:TMDS-40] crtc changed, full mode switch
>[    2.415976] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[    2.415980] [drm:connected_sink_compute_bpp] [CONNECTOR:41:eDP-1] checking for sink bpp constrains
>[    2.415985] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[    2.415987] [drm:intel_dp_compute_config] clamping bpp for eDP panel to BIOS-provided 18
>[    2.415990] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 18
>[    2.415992] [drm:intel_dp_compute_config] DP link bw required 249804 available 432000
>[    2.415995] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 18, dithering: 1
>[    2.415998] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[    2.415999] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[    2.416001] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
>[    2.416004] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[    2.416038] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 4850712, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[    2.416041] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[    2.416042] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[    2.416044] [drm:intel_dump_pipe_config] requested mode:
>[    2.416048] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[    2.416049] [drm:intel_dump_pipe_config] adjusted mode:
>[    2.416054] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[    2.416058] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[    2.416060] [drm:intel_dump_pipe_config] port clock: 270000
>[    2.416062] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[    2.416064] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[    2.416066] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[    2.416068] [drm:intel_dump_pipe_config] ips: 0
>[    2.416069] [drm:intel_dump_pipe_config] double wide: 0
>[    2.420077] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[    2.426081] tsc: Refined TSC clocksource calibration: 1519.950 MHz
>[    2.453053] [drm:intel_dp_link_down] 
>[    2.478072] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[    2.478087] [drm:intel_display_power_put] disabling always-on
>[    2.502509] usb 1-6: New USB device found, idVendor=0424, idProduct=4604
>[    2.502514] usb 1-6: New USB device strings: Mfr=0, Product=0, SerialNumber=0
>[    2.503678] hub 1-6:1.0: USB hub found
>[    2.503725] hub 1-6:1.0: 5 ports detected
>[    2.564156] [drm:edp_panel_vdd_off_sync] Turning eDP port C VDD off
>[    2.564162] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0000
>[    2.564165] [drm:vlv_detach_power_sequencer] detaching pipe B power sequencer from port C
>[    2.564168] [drm:vlv_init_panel_power_sequencer] initializing pipe A power sequencer for port C
>[    2.564178] [drm:intel_dp_init_panel_power_sequencer_registers] panel power sequencer register settings: PP_ON 0x87d00001, PP_OFF 0x1f40001, PP_DIV 0x270f05
>[    2.564188] [drm:edp_panel_vdd_on] Turning eDP port C VDD on
>[    2.564192] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[    2.566661] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00100000, dig 0x00000000
>[    2.566666] [drm:intel_hpd_irq_handler] digital hpd port C - long
>[    2.566671] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 5 - cnt: 0
>[    2.566701] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port C
>[    2.612697] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00100000, dig 0x00000000
>[    2.612700] [drm:intel_hpd_irq_handler] digital hpd port C - long
>[    2.612702] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 5 - cnt: 1
>[    2.612725] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port C
>[    2.614638] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00100000, dig 0x00000000
>[    2.614640] [drm:intel_hpd_irq_handler] digital hpd port C - long
>[    2.614643] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 5 - cnt: 2
>[    2.614668] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port C
>[    2.625046] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00100000, dig 0x00000000
>[    2.625049] [drm:intel_hpd_irq_handler] digital hpd port C - long
>[    2.625052] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 5 - cnt: 3
>[    2.625125] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port C
>[    2.627059] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00100000, dig 0x00000000
>[    2.627062] [drm:intel_hpd_irq_handler] digital hpd port C - long
>[    2.627065] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 5 - cnt: 4
>[    2.627133] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port C
>[    2.647397] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00100000, dig 0x00000000
>[    2.647401] [drm:intel_hpd_irq_handler] digital hpd port C - long
>[    2.647404] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 5 - cnt: 5
>[    2.647432] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port C
>[    2.647928] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00080000, dig 0x00000000
>[    2.647936] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[    2.648016] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[    2.648601] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00080000, dig 0x00000000
>[    2.648610] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[    2.649082] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00080000, dig 0x00000000
>[    2.649091] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[    2.649784] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00080000, dig 0x00000000
>[    2.649794] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[    2.649991] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00080000, dig 0x00000000
>[    2.649994] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[    2.650369] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00080000, dig 0x00000000
>[    2.650379] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[    2.650935] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00080000, dig 0x00000000
>[    2.650944] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[    2.651552] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00080000, dig 0x00000000
>[    2.651562] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[    2.651985] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00080000, dig 0x00000000
>[    2.651993] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[    2.652684] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00080000, dig 0x00000000
>[    2.652692] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[    2.653086] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00080000, dig 0x00000000
>[    2.653094] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[    2.653367] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00080000, dig 0x00000000
>[    2.653376] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[    2.653862] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00080000, dig 0x00000000
>[    2.653870] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[    2.654560] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00080000, dig 0x00000000
>[    2.654569] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[    2.654999] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00080000, dig 0x00000000
>[    2.655009] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[    2.655645] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00080000, dig 0x00000000
>[    2.655655] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[    2.656115] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00080000, dig 0x00000000
>[    2.656123] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[    2.656632] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00080000, dig 0x00000000
>[    2.656642] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[    2.657343] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00080000, dig 0x00000000
>[    2.657351] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[    2.657737] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00080000, dig 0x00000000
>[    2.657746] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[    2.658304] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00080000, dig 0x00000000
>[    2.658313] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[    2.658928] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00080000, dig 0x00000000
>[    2.658938] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[    2.659371] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00080000, dig 0x00000000
>[    2.659380] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[    2.660007] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00080000, dig 0x00000000
>[    2.660015] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[    2.660500] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00080000, dig 0x00000000
>[    2.660510] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[    2.662687] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00100000, dig 0x00000000
>[    2.662690] [drm:intel_hpd_irq_handler] digital hpd port C - long
>[    2.662694] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 5 - cnt: 6
>[    2.705159] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00100000, dig 0x00000000
>[    2.705167] [drm:intel_hpd_irq_handler] digital hpd port C - long
>[    2.705176] [drm:intel_hpd_irq_handler] HPD interrupt storm detected on PIN 5
>[    2.777548] usb 1-6.1: new high-speed USB device number 4 using xhci_hcd
>[    2.863772] usb 1-6.1: New USB device found, idVendor=1a40, idProduct=0101
>[    2.863778] usb 1-6.1: New USB device strings: Mfr=0, Product=1, SerialNumber=0
>[    2.863781] usb 1-6.1: Product: USB 2.0 Hub
>[    2.865928] hub 1-6.1:1.0: USB hub found
>[    2.865979] hub 1-6.1:1.0: 4 ports detected
>[    2.939360] usb 1-6.5: new high-speed USB device number 5 using xhci_hcd
>[    3.027135] usb 1-6.5: New USB device found, idVendor=0424, idProduct=2530
>[    3.027141] usb 1-6.5: New USB device strings: Mfr=0, Product=2, SerialNumber=0
>[    3.027144] usb 1-6.5: Product: Bridge device
>[    3.065561] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0000
>[    3.065566] [drm:wait_panel_status] Wait complete
>[    3.065575] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008
>[    3.065579] [drm:edp_panel_vdd_on] eDP port C panel power wasn't enabled
>[    3.141650] usb 1-6.1.1: new low-speed USB device number 6 using xhci_hcd
>[    3.236117] usb 1-6.1.1: New USB device found, idVendor=046d, idProduct=c31c
>[    3.236122] usb 1-6.1.1: New USB device strings: Mfr=1, Product=2, SerialNumber=0
>[    3.236126] usb 1-6.1.1: Product: USB Keyboard
>[    3.236129] usb 1-6.1.1: Manufacturer: Logitech
>[    3.236698] usb 1-6.1.1: ep 0x81 - rounding interval to 64 microframes, ep desc says 80 microframes
>[    3.236711] usb 1-6.1.1: ep 0x82 - rounding interval to 1024 microframes, ep desc says 2040 microframes
>[    3.243560] input: Logitech USB Keyboard as /devices/pci0000:00/0000:00:14.0/usb1/1-6/1-6.1/1-6.1.1/1-6.1.1:1.0/0003:046D:C31C.0001/input/input8
>[    3.266603] [drm:edp_panel_on] Turn eDP port C panel power on
>[    3.266609] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[    3.266616] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0008
>[    3.266618] [drm:wait_panel_status] Wait complete
>[    3.266625] [drm:wait_panel_on] Wait for panel power on
>[    3.266629] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd000b
>[    3.294732] hid-generic 0003:046D:C31C.0001: input,hidraw0: USB HID v1.10 Keyboard [Logitech USB Keyboard] on usb-0000:00:14.0-6.1.1/input0
>[    3.302817] input: Logitech USB Keyboard as /devices/pci0000:00/0000:00:14.0/usb1/1-6/1-6.1/1-6.1.1/1-6.1.1:1.1/0003:046D:C31C.0002/input/input9
>[    3.353841] hid-generic 0003:046D:C31C.0002: input,hidraw1: USB HID v1.10 Device [Logitech USB Keyboard] on usb-0000:00:14.0-6.1.1/input1
>[    3.420700] [drm:wait_panel_status] Wait complete
>[    3.420707] [drm:edp_panel_vdd_off_sync] Turning eDP port C VDD off
>[    3.420717] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003
>[    3.420730] [drm:edp_panel_vdd_on] Turning eDP port C VDD on
>[    3.420736] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
>[    3.426979] usb 1-6.1.4: new high-speed USB device number 7 using xhci_hcd
>[    3.427107] Switched to clocksource tsc
>[    3.496570] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[    3.497395] [drm:intel_dp_start_link_train] clock recovery OK
>[    3.498374] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[    3.498627] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[    3.498634] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=8, cursor=0, SR: plane=8, cursor=0
>[    3.508650] [drm:intel_set_memory_cxsr] memory self-refresh is enabled
>[    3.508665] [drm:intel_edp_backlight_on] 
>[    3.508667] [drm:intel_panel_enable_backlight] pipe A
>[    3.508672] [drm:intel_panel_actually_set_backlight] set backlight PWM = 7812
>[    3.508684] [drm:intel_psr_match_conditions] PSR disable by flag
>[    3.508711] [drm:intel_connector_check_state] [CONNECTOR:41:eDP-1]
>[    3.508728] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[    3.508732] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[    3.508735] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[    3.508739] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[    3.508742] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[    3.508746] [drm:check_crtc_state] [CRTC:20]
>[    3.516576] [drm:check_crtc_state] [CRTC:25]
>[    3.516580] [drm:check_crtc_state] [CRTC:30]
>[    3.516613] [drm:intel_crtc_set_config] [CRTC:25] [FB:117] #connectors=1 (x y) (0 0)
>[    3.516617] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
>[    3.516620] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[    3.516625] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[    3.516632] [drm:drm_mode_debug_printmodeline] Modeline 115:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[    3.516634] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:25], mode_changed=1, fb_changed=0
>[    3.516636] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] encoder changed, full mode switch
>[    3.516639] [drm:intel_modeset_stage_output_state] [CONNECTOR:41:eDP-1] to [CRTC:20]
>[    3.516641] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:25]
>[    3.516643] [drm:intel_modeset_stage_output_state] [ENCODER:38:TMDS-38] crtc changed, full mode switch
>[    3.516646] [drm:intel_modeset_stage_output_state] [CRTC:25] enabled, full mode switch
>[    3.516650] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[    3.516654] [drm:connected_sink_compute_bpp] [CONNECTOR:39:DP-1] checking for sink bpp constrains
>[    3.516659] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[    3.516666] [drm:intel_dp_compute_config] DP link bw 06 lane count 4 clock 162000 bpp 24
>[    3.516668] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400
>[    3.516671] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[    3.516675] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config for pipe B
>[    3.516676] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[    3.516678] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[    3.516682] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[    3.516685] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[    3.516688] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[    3.516690] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[    3.516691] [drm:intel_dump_pipe_config] requested mode:
>[    3.516695] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[    3.516696] [drm:intel_dump_pipe_config] adjusted mode:
>[    3.516701] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[    3.516704] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[    3.516706] [drm:intel_dump_pipe_config] port clock: 162000
>[    3.516708] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[    3.516710] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[    3.516712] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[    3.516713] [drm:intel_dump_pipe_config] ips: 0
>[    3.516715] [drm:intel_dump_pipe_config] double wide: 0
>[    3.527745] usb 1-6.1.4: New USB device found, idVendor=0b95, idProduct=772a
>[    3.527751] usb 1-6.1.4: New USB device strings: Mfr=1, Product=2, SerialNumber=3
>[    3.527754] usb 1-6.1.4: Product: AX88x72A
>[    3.527758] usb 1-6.1.4: Manufacturer: ASIX Elec. Corp.
>[    3.527761] usb 1-6.1.4: SerialNumber: 0001F3
>[    3.680697] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[    3.740795] [drm:cherryview_enable_rps] GT fifo had a previous error 1080000
>[    3.757663] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[    3.758551] [drm:intel_dp_start_link_train] clock recovery OK
>[    3.759620] [drm:cherryview_enable_rps] GPLL enabled? yes
>[    3.759623] [drm:cherryview_enable_rps] GPU status: 0x00002810
>[    3.759627] [drm:cherryview_enable_rps] current GPU freq: 400 MHz (40)
>[    3.759629] [drm:cherryview_enable_rps] setting GPU freq to 400 MHz (40)
>[    3.835690] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[    3.912823] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[    3.990759] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[    4.067791] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[    4.069071] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[    4.069249] [drm:intel_enable_dp] Enabling DP audio on pipe B
>[    4.069255] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:39:DP-1], [ENCODER:38:TMDS-38]
>[    4.069258] [drm:ilk_audio_codec_enable] Enable audio codec on port B, pipe B, 36 bytes ELD
>[    4.069333] [drm:vlv_get_fifo_size] Pipe B primary B FIFO size: 256
>[    4.069340] [drm:valleyview_update_wm] Setting FIFO watermarks - B: plane=8, cursor=0, SR: plane=0, cursor=0
>[    4.078822] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[    4.078842] [drm:intel_psr_enable] PSR not supported by this panel
>[    4.078870] [drm:intel_connector_check_state] [CONNECTOR:41:eDP-1]
>[    4.078876] [drm:intel_connector_check_state] [CONNECTOR:39:DP-1]
>[    4.078886] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[    4.078889] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[    4.078892] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[    4.078895] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[    4.078898] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[    4.078902] [drm:check_crtc_state] [CRTC:20]
>[    4.086816] [drm:check_crtc_state] [CRTC:25]
>[    4.094844] [drm:check_crtc_state] [CRTC:30]
>[    4.094856] [drm:intel_crtc_set_config] [CRTC:30] [FB:117] #connectors=1 (x y) (0 0)
>[    4.094861] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
>[    4.094862] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[    4.094867] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[    4.094873] [drm:drm_mode_debug_printmodeline] Modeline 116:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[    4.094875] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:30], mode_changed=1, fb_changed=0
>[    4.094879] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] encoder changed, full mode switch
>[    4.094882] [drm:intel_modeset_stage_output_state] [CONNECTOR:41:eDP-1] to [CRTC:20]
>[    4.094884] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:25]
>[    4.094886] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[    4.094888] [drm:intel_modeset_stage_output_state] [ENCODER:46:TMDS-46] crtc changed, full mode switch
>[    4.094892] [drm:intel_modeset_stage_output_state] [CRTC:30] enabled, full mode switch
>[    4.094897] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 4, prepare: 4, disable: 0
>[    4.094901] [drm:connected_sink_compute_bpp] [CONNECTOR:47:HDMI-A-2] checking for sink bpp constrains
>[    4.094909] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[    4.094911] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[    4.094915] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[    4.094920] [drm:intel_dump_pipe_config] [CRTC:30][modeset] config for pipe C
>[    4.094921] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[    4.094923] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[    4.094927] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[    4.094930] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[    4.094932] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[    4.094934] [drm:intel_dump_pipe_config] audio: 1, infoframes: 1
>[    4.094935] [drm:intel_dump_pipe_config] requested mode:
>[    4.094939] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[    4.094940] [drm:intel_dump_pipe_config] adjusted mode:
>[    4.094945] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[    4.094948] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[    4.094950] [drm:intel_dump_pipe_config] port clock: 148500
>[    4.094952] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[    4.094954] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[    4.094956] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[    4.094958] [drm:intel_dump_pipe_config] ips: 0
>[    4.094959] [drm:intel_dump_pipe_config] double wide: 0
>[    4.258899] [drm:intel_enable_hdmi] Enabling HDMI audio on pipe C
>[    4.258906] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:HDMI-A-2], [ENCODER:46:TMDS-46]
>[    4.258909] [drm:ilk_audio_codec_enable] Enable audio codec on port D, pipe C, 36 bytes ELD
>[    4.258919] [drm:audio_config_hdmi_pixel_clock] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[    4.258982] [drm:vlv_get_fifo_size] Pipe C primary C FIFO size: 256
>[    4.258986] [drm:valleyview_update_wm] Setting FIFO watermarks - C: plane=8, cursor=0, SR: plane=0, cursor=0
>[    4.269008] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[    4.269038] [drm:intel_connector_check_state] [CONNECTOR:41:eDP-1]
>[    4.269044] [drm:intel_connector_check_state] [CONNECTOR:39:DP-1]
>[    4.269048] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[    4.269052] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[    4.269055] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[    4.269059] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[    4.269063] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[    4.269067] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[    4.269071] [drm:check_crtc_state] [CRTC:20]
>[    4.276888] [drm:check_crtc_state] [CRTC:25]
>[    4.285011] [drm:check_crtc_state] [CRTC:30]
>[    4.292903] [drm:drm_fb_helper_hotplug_event] 
>[    4.292908] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:41:eDP-1]
>[    4.292912] [drm:intel_dp_detect] [CONNECTOR:41:eDP-1]
>[    4.293370] [drm:intel_dp_probe_oui] Sink OUI: 001cf8
>[    4.294193] [drm:intel_dp_get_dpcd] DPCD: 12 0a 82 41 00 00 01 80 02 00 00 00 0f 0b 00
>[    4.294550] [drm:intel_dp_probe_oui] Branch OUI: 000000
>[    4.294574] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[    4.294581] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:41:eDP-1] probed modes :
>[    4.294586] [drm:drm_mode_debug_printmodeline] Modeline 42:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[    4.294593] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:34:HDMI-A-1]
>[    4.294596] [drm:intel_hdmi_detect] [CONNECTOR:34:HDMI-A-1]
>[    4.294780] [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 r(1)
>[    4.294783] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[    4.294787] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:34:HDMI-A-1] disconnected
>[    4.294793] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:39:DP-1]
>[    4.294800] [drm:intel_dp_detect] [CONNECTOR:39:DP-1]
>[    4.294896] [drm:intel_dp_get_dpcd] Detected EDP PSR Panel.
>[    4.295360] [drm:intel_dp_get_dpcd] DPCD: 11 0a 84 00 01 00 00 00 00 00 00 00 00 00 00
>[    4.296180] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port C
>[    4.297478] asix 1-6.1.4:1.0 eth0: register 'asix' at usb-0000:00:14.0-6.1.4, ASIX AX88772 USB 2.0 Ethernet, 8c:ae:4c:fd:a6:77
>[    4.304630] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[    4.304855] [drm:drm_edid_to_eld] ELD monitor ASUS PA238
>[    4.304858] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[    4.304946] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:39:DP-1] probed modes :
>[    4.304953] [drm:drm_mode_debug_printmodeline] Modeline 52:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[    4.304957] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[    4.304963] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[    4.304969] [drm:drm_mode_debug_printmodeline] Modeline 100:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[    4.304973] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[    4.304978] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[    4.304982] [drm:drm_mode_debug_printmodeline] Modeline 61:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[    4.304986] [drm:drm_mode_debug_printmodeline] Modeline 70:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[    4.304991] [drm:drm_mode_debug_printmodeline] Modeline 59:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[    4.304995] [drm:drm_mode_debug_printmodeline] Modeline 60:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6
>[    4.304999] [drm:drm_mode_debug_printmodeline] Modeline 57:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[    4.305004] [drm:drm_mode_debug_printmodeline] Modeline 58:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[    4.305008] [drm:drm_mode_debug_printmodeline] Modeline 62:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[    4.305012] [drm:drm_mode_debug_printmodeline] Modeline 54:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[    4.305017] [drm:drm_mode_debug_printmodeline] Modeline 94:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[    4.305021] [drm:drm_mode_debug_printmodeline] Modeline 55:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[    4.305026] [drm:drm_mode_debug_printmodeline] Modeline 90:"1440x576" 50 54000 1440 1464 1592 1728 576 581 586 625 0x40 0xa
>[    4.305030] [drm:drm_mode_debug_printmodeline] Modeline 71:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[    4.305034] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[    4.305039] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[    4.305043] [drm:drm_mode_debug_printmodeline] Modeline 102:"1440x480" 60 54054 1440 1472 1596 1716 480 489 495 525 0x40 0xa
>[    4.305048] [drm:drm_mode_debug_printmodeline] Modeline 88:"1440x480" 60 54000 1440 1472 1596 1716 480 489 495 525 0x40 0xa
>[    4.305052] [drm:drm_mode_debug_printmodeline] Modeline 74:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[    4.305056] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[    4.305061] [drm:drm_mode_debug_printmodeline] Modeline 76:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[    4.305065] [drm:drm_mode_debug_printmodeline] Modeline 63:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[    4.305069] [drm:drm_mode_debug_printmodeline] Modeline 64:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[    4.305074] [drm:drm_mode_debug_printmodeline] Modeline 56:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[    4.305078] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[    4.305082] [drm:drm_mode_debug_printmodeline] Modeline 53:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[    4.305087] [drm:drm_mode_debug_printmodeline] Modeline 65:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[    4.305091] [drm:drm_mode_debug_printmodeline] Modeline 66:"640x480" 73 31500 640 664 704 832 480 489 491 520 0x40 0xa
>[    4.305095] [drm:drm_mode_debug_printmodeline] Modeline 67:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[    4.305100] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[    4.305104] [drm:drm_mode_debug_printmodeline] Modeline 77:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[    4.305108] [drm:drm_mode_debug_printmodeline] Modeline 69:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[    4.305115] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:47:HDMI-A-2]
>[    4.305119] [drm:intel_hdmi_detect] [CONNECTOR:47:HDMI-A-2]
>[    4.329974] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[    4.330174] [drm:drm_edid_to_eld] ELD monitor ASUS VS239
>[    4.330180] [drm:parse_hdmi_vsdb] HDMI: DVI dual 0, max TMDS clock 0, latency present 0 0, video latency 0 0, audio latency 0 0
>[    4.330181] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[    4.330262] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:47:HDMI-A-2] probed modes :
>[    4.330268] [drm:drm_mode_debug_printmodeline] Modeline 79:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[    4.330272] [drm:drm_mode_debug_printmodeline] Modeline 128:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[    4.330277] [drm:drm_mode_debug_printmodeline] Modeline 121:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[    4.330282] [drm:drm_mode_debug_printmodeline] Modeline 136:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[    4.330287] [drm:drm_mode_debug_printmodeline] Modeline 126:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[    4.330291] [drm:drm_mode_debug_printmodeline] Modeline 120:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[    4.330295] [drm:drm_mode_debug_printmodeline] Modeline 95:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[    4.330300] [drm:drm_mode_debug_printmodeline] Modeline 106:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[    4.330304] [drm:drm_mode_debug_printmodeline] Modeline 89:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[    4.330308] [drm:drm_mode_debug_printmodeline] Modeline 91:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[    4.330313] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[    4.330317] [drm:drm_mode_debug_printmodeline] Modeline 97:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[    4.330321] [drm:drm_mode_debug_printmodeline] Modeline 96:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[    4.330326] [drm:drm_mode_debug_printmodeline] Modeline 81:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[    4.330330] [drm:drm_mode_debug_printmodeline] Modeline 130:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[    4.330335] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[    4.330339] [drm:drm_mode_debug_printmodeline] Modeline 124:"1440x576" 50 54000 1440 1464 1592 1728 576 581 586 625 0x40 0xa
>[    4.330343] [drm:drm_mode_debug_printmodeline] Modeline 107:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[    4.330348] [drm:drm_mode_debug_printmodeline] Modeline 108:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[    4.330352] [drm:drm_mode_debug_printmodeline] Modeline 109:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[    4.330357] [drm:drm_mode_debug_printmodeline] Modeline 137:"1440x480" 60 54054 1440 1472 1596 1716 480 489 495 525 0x40 0xa
>[    4.330361] [drm:drm_mode_debug_printmodeline] Modeline 122:"1440x480" 60 54000 1440 1472 1596 1716 480 489 495 525 0x40 0xa
>[    4.330365] [drm:drm_mode_debug_printmodeline] Modeline 110:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[    4.330369] [drm:drm_mode_debug_printmodeline] Modeline 111:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[    4.330374] [drm:drm_mode_debug_printmodeline] Modeline 112:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[    4.330378] [drm:drm_mode_debug_printmodeline] Modeline 98:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[    4.330383] [drm:drm_mode_debug_printmodeline] Modeline 99:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[    4.330387] [drm:drm_mode_debug_printmodeline] Modeline 83:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[    4.330391] [drm:drm_mode_debug_printmodeline] Modeline 129:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[    4.330395] [drm:drm_mode_debug_printmodeline] Modeline 80:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[    4.330400] [drm:drm_mode_debug_printmodeline] Modeline 101:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[    4.330404] [drm:drm_mode_debug_printmodeline] Modeline 103:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[    4.330408] [drm:drm_mode_debug_printmodeline] Modeline 104:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[    4.330412] [drm:drm_mode_debug_printmodeline] Modeline 113:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[    4.330417] [drm:drm_mode_debug_printmodeline] Modeline 105:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[    4.330422] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:49:DP-2]
>[    4.330426] [drm:intel_dp_detect] [CONNECTOR:49:DP-2]
>[    4.330936] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    4.331438] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    4.331935] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    4.332439] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    4.332942] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    4.332959] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[    4.333462] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    4.333960] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    4.334466] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    4.334970] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    4.335468] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    4.335484] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[    4.337350] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    4.337854] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    4.338357] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    4.338858] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    4.339357] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    4.339375] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[    4.341358] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    4.341860] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    4.342362] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    4.342867] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    4.343368] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    4.343383] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[    4.344870] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:49:DP-2] disconnected
>[    4.344880] [drm:drm_setup_crtcs] 
>[    4.344885] [drm:drm_enable_connectors] connector 41 enabled? yes
>[    4.344888] [drm:drm_enable_connectors] connector 34 enabled? no
>[    4.344890] [drm:drm_enable_connectors] connector 39 enabled? yes
>[    4.344892] [drm:drm_enable_connectors] connector 47 enabled? yes
>[    4.344893] [drm:drm_enable_connectors] connector 49 enabled? no
>[    4.344899] [drm:intel_fb_initial_config] looking for cmdline mode on connector eDP-1
>[    4.344901] [drm:intel_fb_initial_config] looking for preferred mode on connector eDP-1 0
>[    4.344906] [drm:intel_fb_initial_config] connector eDP-1 on pipe A [CRTC:20]: 1920x1080
>[    4.344907] [drm:intel_fb_initial_config] connector HDMI-A-1 not enabled, skipping
>[    4.344909] [drm:intel_fb_initial_config] looking for cmdline mode on connector DP-1
>[    4.344911] [drm:intel_fb_initial_config] looking for preferred mode on connector DP-1 0
>[    4.344915] [drm:intel_fb_initial_config] connector DP-1 on pipe B [CRTC:25]: 1920x1080
>[    4.344918] [drm:intel_fb_initial_config] looking for cmdline mode on connector HDMI-A-2
>[    4.344920] [drm:intel_fb_initial_config] looking for preferred mode on connector HDMI-A-2 0
>[    4.344923] [drm:intel_fb_initial_config] connector HDMI-A-2 on pipe C [CRTC:30]: 1920x1080
>[    4.344925] [drm:intel_fb_initial_config] connector DP-2 not enabled, skipping
>[    4.344929] [drm:drm_setup_crtcs] desired mode 1920x1080 set on crtc 20 (0,0)
>[    4.344934] [drm:drm_setup_crtcs] desired mode 1920x1080 set on crtc 25 (0,0)
>[    4.344937] [drm:drm_setup_crtcs] desired mode 1920x1080 set on crtc 30 (0,0)
>[    4.345111] [drm:intel_crtc_set_config] [CRTC:20] [FB:117] #connectors=1 (x y) (0 0)
>[    4.345116] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=0, fb_changed=0
>[    4.345121] [drm:intel_modeset_stage_output_state] [CONNECTOR:41:eDP-1] to [CRTC:20]
>[    4.345123] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:25]
>[    4.345125] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[    4.345130] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[    4.345135] [drm:connected_sink_compute_bpp] [CONNECTOR:41:eDP-1] checking for sink bpp constrains
>[    4.345140] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[    4.345142] [drm:intel_dp_compute_config] clamping bpp for eDP panel to BIOS-provided 18
>[    4.345145] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 18
>[    4.345147] [drm:intel_dp_compute_config] DP link bw required 249804 available 432000
>[    4.345153] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 18, dithering: 1
>[    4.345156] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[    4.345158] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[    4.345160] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
>[    4.345162] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[    4.345166] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 4850712, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[    4.345168] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[    4.345170] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[    4.345171] [drm:intel_dump_pipe_config] requested mode:
>[    4.345175] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[    4.345177] [drm:intel_dump_pipe_config] adjusted mode:
>[    4.345181] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[    4.345185] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[    4.345186] [drm:intel_dump_pipe_config] port clock: 270000
>[    4.345188] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[    4.345190] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[    4.345192] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[    4.345194] [drm:intel_dump_pipe_config] ips: 0
>[    4.345195] [drm:intel_dump_pipe_config] double wide: 0
>[    4.345200] [drm:intel_crtc_set_config] [CRTC:25] [FB:117] #connectors=1 (x y) (0 0)
>[    4.345203] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:25], mode_changed=0, fb_changed=0
>[    4.345206] [drm:intel_modeset_stage_output_state] [CONNECTOR:41:eDP-1] to [CRTC:20]
>[    4.345208] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:25]
>[    4.345210] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[    4.345213] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[    4.345216] [drm:connected_sink_compute_bpp] [CONNECTOR:39:DP-1] checking for sink bpp constrains
>[    4.345219] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[    4.345225] [drm:intel_dp_compute_config] DP link bw 06 lane count 4 clock 162000 bpp 24
>[    4.345227] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400
>[    4.345230] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[    4.345232] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config for pipe B
>[    4.345233] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[    4.345235] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[    4.345238] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[    4.345241] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[    4.345243] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[    4.345245] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[    4.345246] [drm:intel_dump_pipe_config] requested mode:
>[    4.345250] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[    4.345252] [drm:intel_dump_pipe_config] adjusted mode:
>[    4.345256] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[    4.345260] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[    4.345261] [drm:intel_dump_pipe_config] port clock: 162000
>[    4.345263] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[    4.345265] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[    4.345267] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[    4.345268] [drm:intel_dump_pipe_config] ips: 0
>[    4.345270] [drm:intel_dump_pipe_config] double wide: 0
>[    4.345273] [drm:intel_crtc_set_config] [CRTC:30] [FB:117] #connectors=1 (x y) (0 0)
>[    4.345277] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:30], mode_changed=0, fb_changed=0
>[    4.345279] [drm:intel_modeset_stage_output_state] [CONNECTOR:41:eDP-1] to [CRTC:20]
>[    4.345282] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:25]
>[    4.345284] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[    4.345286] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 4, prepare: 4, disable: 0
>[    4.345289] [drm:connected_sink_compute_bpp] [CONNECTOR:47:HDMI-A-2] checking for sink bpp constrains
>[    4.345294] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[    4.345296] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[    4.345298] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[    4.345300] [drm:intel_dump_pipe_config] [CRTC:30][modeset] config for pipe C
>[    4.345302] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[    4.345303] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[    4.345306] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[    4.345309] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[    4.345311] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[    4.345313] [drm:intel_dump_pipe_config] audio: 1, infoframes: 1
>[    4.345314] [drm:intel_dump_pipe_config] requested mode:
>[    4.345319] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[    4.345320] [drm:intel_dump_pipe_config] adjusted mode:
>[    4.345324] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[    4.345328] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[    4.345329] [drm:intel_dump_pipe_config] port clock: 148500
>[    4.345331] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[    4.345333] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[    4.345335] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[    4.345337] [drm:intel_dump_pipe_config] ips: 0
>[    4.345338] [drm:intel_dump_pipe_config] double wide: 0
>[    4.345352] Console: switching to colour frame buffer device 240x67
>[    4.345370] [drm:intel_crtc_set_config] [CRTC:20] [FB:117] #connectors=1 (x y) (0 0)
>[    4.345374] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=0, fb_changed=0
>[    4.345376] [drm:intel_modeset_stage_output_state] [CONNECTOR:41:eDP-1] to [CRTC:20]
>[    4.345379] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:25]
>[    4.345381] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[    4.345384] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[    4.345387] [drm:connected_sink_compute_bpp] [CONNECTOR:41:eDP-1] checking for sink bpp constrains
>[    4.345390] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[    4.345392] [drm:intel_dp_compute_config] clamping bpp for eDP panel to BIOS-provided 18
>[    4.345394] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 18
>[    4.345396] [drm:intel_dp_compute_config] DP link bw required 249804 available 432000
>[    4.345399] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 18, dithering: 1
>[    4.345401] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[    4.345402] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[    4.345404] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
>[    4.345407] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[    4.345410] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 4850712, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[    4.345413] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[    4.345414] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[    4.345415] [drm:intel_dump_pipe_config] requested mode:
>[    4.345420] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[    4.345421] [drm:intel_dump_pipe_config] adjusted mode:
>[    4.345425] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[    4.345429] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[    4.345430] [drm:intel_dump_pipe_config] port clock: 270000
>[    4.345432] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[    4.345434] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[    4.345436] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[    4.345438] [drm:intel_dump_pipe_config] ips: 0
>[    4.345439] [drm:intel_dump_pipe_config] double wide: 0
>[    4.345443] [drm:intel_crtc_set_config] [CRTC:25] [FB:117] #connectors=1 (x y) (0 0)
>[    4.345446] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:25], mode_changed=0, fb_changed=0
>[    4.345448] [drm:intel_modeset_stage_output_state] [CONNECTOR:41:eDP-1] to [CRTC:20]
>[    4.345451] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:25]
>[    4.345453] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[    4.345456] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[    4.345458] [drm:connected_sink_compute_bpp] [CONNECTOR:39:DP-1] checking for sink bpp constrains
>[    4.345461] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[    4.345466] [drm:intel_dp_compute_config] DP link bw 06 lane count 4 clock 162000 bpp 24
>[    4.345467] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400
>[    4.345470] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[    4.345472] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config for pipe B
>[    4.345473] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[    4.345475] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[    4.345478] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[    4.345481] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[    4.345483] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[    4.345485] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[    4.345486] [drm:intel_dump_pipe_config] requested mode:
>[    4.345490] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[    4.345492] [drm:intel_dump_pipe_config] adjusted mode:
>[    4.345496] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[    4.345500] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[    4.345501] [drm:intel_dump_pipe_config] port clock: 162000
>[    4.345503] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[    4.345505] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[    4.345507] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[    4.345508] [drm:intel_dump_pipe_config] ips: 0
>[    4.345510] [drm:intel_dump_pipe_config] double wide: 0
>[    4.345513] [drm:intel_crtc_set_config] [CRTC:30] [FB:117] #connectors=1 (x y) (0 0)
>[    4.345516] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:30], mode_changed=0, fb_changed=0
>[    4.345519] [drm:intel_modeset_stage_output_state] [CONNECTOR:41:eDP-1] to [CRTC:20]
>[    4.345521] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:25]
>[    4.345523] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[    4.345526] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 4, prepare: 4, disable: 0
>[    4.345529] [drm:connected_sink_compute_bpp] [CONNECTOR:47:HDMI-A-2] checking for sink bpp constrains
>[    4.345532] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[    4.345534] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[    4.345536] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[    4.345538] [drm:intel_dump_pipe_config] [CRTC:30][modeset] config for pipe C
>[    4.345539] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[    4.345541] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[    4.345544] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[    4.345546] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[    4.345549] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[    4.345551] [drm:intel_dump_pipe_config] audio: 1, infoframes: 1
>[    4.345552] [drm:intel_dump_pipe_config] requested mode:
>[    4.345556] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[    4.345557] [drm:intel_dump_pipe_config] adjusted mode:
>[    4.345561] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[    4.345565] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[    4.345567] [drm:intel_dump_pipe_config] port clock: 148500
>[    4.345568] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[    4.345570] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[    4.345572] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[    4.345574] [drm:intel_dump_pipe_config] ips: 0
>[    4.345575] [drm:intel_dump_pipe_config] double wide: 0
>[    4.370817] i915 0000:00:02.0: fb0: inteldrmfb frame buffer device
>[    4.370921] i915 0000:00:02.0: registered panic notifier
>[    4.382520] dracut: Starting plymouth daemon
>[    4.403683] [drm:intel_crtc_set_config] [CRTC:20] [FB:117] #connectors=1 (x y) (0 0)
>[    4.403692] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=0, fb_changed=0
>[    4.403697] [drm:intel_modeset_stage_output_state] [CONNECTOR:41:eDP-1] to [CRTC:20]
>[    4.403699] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:25]
>[    4.403702] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[    4.403706] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[    4.403711] [drm:connected_sink_compute_bpp] [CONNECTOR:41:eDP-1] checking for sink bpp constrains
>[    4.403718] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[    4.403721] [drm:intel_dp_compute_config] clamping bpp for eDP panel to BIOS-provided 18
>[    4.403725] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 18
>[    4.403727] [drm:intel_dp_compute_config] DP link bw required 249804 available 432000
>[    4.403731] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 18, dithering: 1
>[    4.403735] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[    4.403736] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[    4.403738] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
>[    4.403741] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[    4.403744] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 4850712, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[    4.403747] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[    4.403748] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[    4.403750] [drm:intel_dump_pipe_config] requested mode:
>[    4.403755] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[    4.403756] [drm:intel_dump_pipe_config] adjusted mode:
>[    4.403760] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[    4.403764] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[    4.403766] [drm:intel_dump_pipe_config] port clock: 270000
>[    4.403767] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[    4.403770] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[    4.403772] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[    4.403773] [drm:intel_dump_pipe_config] ips: 0
>[    4.403775] [drm:intel_dump_pipe_config] double wide: 0
>[    4.403781] [drm:intel_crtc_set_config] [CRTC:25] [FB:117] #connectors=1 (x y) (0 0)
>[    4.403785] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:25], mode_changed=0, fb_changed=0
>[    4.403789] [drm:intel_modeset_stage_output_state] [CONNECTOR:41:eDP-1] to [CRTC:20]
>[    4.403791] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:25]
>[    4.403793] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[    4.403796] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[    4.403800] [drm:connected_sink_compute_bpp] [CONNECTOR:39:DP-1] checking for sink bpp constrains
>[    4.403804] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[    4.403812] [drm:intel_dp_compute_config] DP link bw 06 lane count 4 clock 162000 bpp 24
>[    4.403813] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400
>[    4.403817] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[    4.403819] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config for pipe B
>[    4.403820] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[    4.403822] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[    4.403825] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[    4.403828] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[    4.403830] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[    4.403832] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[    4.403833] [drm:intel_dump_pipe_config] requested mode:
>[    4.403838] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[    4.403839] [drm:intel_dump_pipe_config] adjusted mode:
>[    4.403843] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[    4.403847] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[    4.403848] [drm:intel_dump_pipe_config] port clock: 162000
>[    4.403850] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[    4.403852] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[    4.403854] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[    4.403855] [drm:intel_dump_pipe_config] ips: 0
>[    4.403857] [drm:intel_dump_pipe_config] double wide: 0
>[    4.403861] [drm:intel_crtc_set_config] [CRTC:30] [FB:117] #connectors=1 (x y) (0 0)
>[    4.403866] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:30], mode_changed=0, fb_changed=0
>[    4.403868] [drm:intel_modeset_stage_output_state] [CONNECTOR:41:eDP-1] to [CRTC:20]
>[    4.403870] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:25]
>[    4.403884] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[    4.403887] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 4, prepare: 4, disable: 0
>[    4.403891] [drm:connected_sink_compute_bpp] [CONNECTOR:47:HDMI-A-2] checking for sink bpp constrains
>[    4.403898] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[    4.403899] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[    4.403902] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[    4.403904] [drm:intel_dump_pipe_config] [CRTC:30][modeset] config for pipe C
>[    4.403905] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[    4.403907] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[    4.403910] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[    4.403912] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[    4.403915] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[    4.403916] [drm:intel_dump_pipe_config] audio: 1, infoframes: 1
>[    4.403917] [drm:intel_dump_pipe_config] requested mode:
>[    4.403922] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[    4.403923] [drm:intel_dump_pipe_config] adjusted mode:
>[    4.403927] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[    4.403931] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[    4.403932] [drm:intel_dump_pipe_config] port clock: 148500
>[    4.403934] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[    4.403936] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[    4.403938] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[    4.403940] [drm:intel_dump_pipe_config] ips: 0
>[    4.403941] [drm:intel_dump_pipe_config] double wide: 0
>[    4.443535] [drm:intel_crtc_set_config] [CRTC:20] [FB:117] #connectors=1 (x y) (0 0)
>[    4.443543] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=0, fb_changed=0
>[    4.443549] [drm:intel_modeset_stage_output_state] [CONNECTOR:41:eDP-1] to [CRTC:20]
>[    4.443551] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:25]
>[    4.443553] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[    4.443558] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[    4.443563] [drm:connected_sink_compute_bpp] [CONNECTOR:41:eDP-1] checking for sink bpp constrains
>[    4.443569] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[    4.443571] [drm:intel_dp_compute_config] clamping bpp for eDP panel to BIOS-provided 18
>[    4.443574] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 18
>[    4.443576] [drm:intel_dp_compute_config] DP link bw required 249804 available 432000
>[    4.443580] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 18, dithering: 1
>[    4.443584] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[    4.443585] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[    4.443587] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
>[    4.443591] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[    4.443594] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 4850712, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[    4.443597] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[    4.443598] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[    4.443600] [drm:intel_dump_pipe_config] requested mode:
>[    4.443606] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[    4.443607] [drm:intel_dump_pipe_config] adjusted mode:
>[    4.443611] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[    4.443616] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[    4.443618] [drm:intel_dump_pipe_config] port clock: 270000
>[    4.443620] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[    4.443622] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[    4.443624] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[    4.443625] [drm:intel_dump_pipe_config] ips: 0
>[    4.443627] [drm:intel_dump_pipe_config] double wide: 0
>[    4.443633] [drm:intel_crtc_set_config] [CRTC:25] [FB:117] #connectors=1 (x y) (0 0)
>[    4.443638] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:25], mode_changed=0, fb_changed=0
>[    4.443640] [drm:intel_modeset_stage_output_state] [CONNECTOR:41:eDP-1] to [CRTC:20]
>[    4.443644] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:25]
>[    4.443646] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[    4.443649] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[    4.443653] [drm:connected_sink_compute_bpp] [CONNECTOR:39:DP-1] checking for sink bpp constrains
>[    4.443656] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[    4.443663] [drm:intel_dp_compute_config] DP link bw 06 lane count 4 clock 162000 bpp 24
>[    4.443665] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400
>[    4.443668] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[    4.443670] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config for pipe B
>[    4.443671] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[    4.443673] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[    4.443676] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[    4.443679] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[    4.443682] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[    4.443683] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[    4.443684] [drm:intel_dump_pipe_config] requested mode:
>[    4.443689] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[    4.443690] [drm:intel_dump_pipe_config] adjusted mode:
>[    4.443694] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[    4.443698] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[    4.443699] [drm:intel_dump_pipe_config] port clock: 162000
>[    4.443701] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[    4.443703] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[    4.443705] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[    4.443707] [drm:intel_dump_pipe_config] ips: 0
>[    4.443708] [drm:intel_dump_pipe_config] double wide: 0
>[    4.443712] [drm:intel_crtc_set_config] [CRTC:30] [FB:117] #connectors=1 (x y) (0 0)
>[    4.443716] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:30], mode_changed=0, fb_changed=0
>[    4.443718] [drm:intel_modeset_stage_output_state] [CONNECTOR:41:eDP-1] to [CRTC:20]
>[    4.443720] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:25]
>[    4.443722] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[    4.443725] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 4, prepare: 4, disable: 0
>[    4.443728] [drm:connected_sink_compute_bpp] [CONNECTOR:47:HDMI-A-2] checking for sink bpp constrains
>[    4.443732] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[    4.443734] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[    4.443736] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[    4.443738] [drm:intel_dump_pipe_config] [CRTC:30][modeset] config for pipe C
>[    4.443740] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[    4.443741] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[    4.443744] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[    4.443747] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[    4.443749] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[    4.443751] [drm:intel_dump_pipe_config] audio: 1, infoframes: 1
>[    4.443752] [drm:intel_dump_pipe_config] requested mode:
>[    4.443756] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[    4.443758] [drm:intel_dump_pipe_config] adjusted mode:
>[    4.443762] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[    4.443766] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[    4.443767] [drm:intel_dump_pipe_config] port clock: 148500
>[    4.443769] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[    4.443771] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[    4.443773] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[    4.443774] [drm:intel_dump_pipe_config] ips: 0
>[    4.443776] [drm:intel_dump_pipe_config] double wide: 0
>[    4.617269] ACPI: Deprecated procfs I/F for AC is loaded, please retry with CONFIG_ACPI_PROCFS_POWER cleared
>[    4.617576] ACPI: AC Adapter [ADP1] (on-line)
>[    4.642496] ACPI: Deprecated procfs I/F for battery is loaded, please retry with CONFIG_ACPI_PROCFS_POWER cleared
>[    4.642674] ACPI: Battery Slot [BAT0] (battery present)
>[    4.648956] ACPI: Deprecated procfs I/F for battery is loaded, please retry with CONFIG_ACPI_PROCFS_POWER cleared
>[    4.655291] ACPI: Battery Slot [BAT1] (battery absent)
>[    4.674343] ACPI Warning: SystemIO range 0x0000000000001040-0x000000000000105f conflicts with OpRegion 0x0000000000001040-0x000000000000104f (\_SB_.PCI0.SBUS.SMBI) (20150204/utaddress-258)
>[    4.680622] ACPI: If an ACPI driver is available for this device, you should use it instead of the native driver
>[    4.692288] input: PC Speaker as /devices/platform/pcspkr/input/input10
>[    4.703503] sound hdaudioC0D0: autoconfig for ALC282: line_outs=1 (0x1b/0x0/0x0/0x0/0x0) type:line
>[    4.709731] sound hdaudioC0D0:    speaker_outs=1 (0x14/0x0/0x0/0x0/0x0)
>[    4.715929] sound hdaudioC0D0:    hp_outs=1 (0x21/0x0/0x0/0x0/0x0)
>[    4.722079] sound hdaudioC0D0:    mono: mono_out=0x0
>[    4.726815] iTCO_vendor_support: vendor-support=0
>[    4.727594] iTCO_wdt: Intel TCO WatchDog Timer Driver v1.11
>[    4.727675] iTCO_wdt: Found a Braswell SoC TCO device (Version=3, TCOBASE=0x0460)
>[    4.728178] iTCO_wdt: initialized. heartbeat=30 sec (nowayout=0)
>[    4.752397] sound hdaudioC0D0:    dig-out=0x1e/0x0
>[    4.752400] sound hdaudioC0D0:    inputs:
>[    4.752404] sound hdaudioC0D0:      Internal Mic=0x12
>[    4.752408] sound hdaudioC0D0:      Rear Mic=0x19
>[    4.752417] sound hdaudioC0D0:      Front Mic=0x18
>[    4.752420] sound hdaudioC0D0:      Line=0x1a
>[    4.796790] [drm:intel_crtc_set_config] [CRTC:20] [FB:117] #connectors=1 (x y) (0 0)
>[    4.796797] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=0, fb_changed=0
>[    4.796802] [drm:intel_modeset_stage_output_state] [CONNECTOR:41:eDP-1] to [CRTC:20]
>[    4.796804] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:25]
>[    4.796807] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[    4.796811] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[    4.796816] [drm:connected_sink_compute_bpp] [CONNECTOR:41:eDP-1] checking for sink bpp constrains
>[    4.796822] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[    4.796826] [drm:intel_dp_compute_config] clamping bpp for eDP panel to BIOS-provided 18
>[    4.796830] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 18
>[    4.796832] [drm:intel_dp_compute_config] DP link bw required 249804 available 432000
>[    4.796836] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 18, dithering: 1
>[    4.796839] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[    4.796840] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[    4.796842] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
>[    4.796845] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[    4.796848] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 4850712, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[    4.796851] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[    4.796852] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[    4.796854] [drm:intel_dump_pipe_config] requested mode:
>[    4.796860] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[    4.796861] [drm:intel_dump_pipe_config] adjusted mode:
>[    4.796865] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[    4.796877] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[    4.796878] [drm:intel_dump_pipe_config] port clock: 270000
>[    4.796880] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[    4.796882] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[    4.796886] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[    4.796887] [drm:intel_dump_pipe_config] ips: 0
>[    4.796889] [drm:intel_dump_pipe_config] double wide: 0
>[    4.796894] [drm:intel_crtc_set_config] [CRTC:25] [FB:117] #connectors=1 (x y) (0 0)
>[    4.796898] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:25], mode_changed=0, fb_changed=0
>[    4.796901] [drm:intel_modeset_stage_output_state] [CONNECTOR:41:eDP-1] to [CRTC:20]
>[    4.796903] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:25]
>[    4.796906] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[    4.796909] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[    4.796913] [drm:connected_sink_compute_bpp] [CONNECTOR:39:DP-1] checking for sink bpp constrains
>[    4.796917] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[    4.796924] [drm:intel_dp_compute_config] DP link bw 06 lane count 4 clock 162000 bpp 24
>[    4.796926] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400
>[    4.796929] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[    4.796931] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config for pipe B
>[    4.796932] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[    4.796934] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[    4.796937] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[    4.796940] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[    4.796942] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[    4.796944] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[    4.796945] [drm:intel_dump_pipe_config] requested mode:
>[    4.796950] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[    4.796951] [drm:intel_dump_pipe_config] adjusted mode:
>[    4.796955] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[    4.796959] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[    4.796960] [drm:intel_dump_pipe_config] port clock: 162000
>[    4.796962] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[    4.796964] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[    4.796966] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[    4.796968] [drm:intel_dump_pipe_config] ips: 0
>[    4.796969] [drm:intel_dump_pipe_config] double wide: 0
>[    4.796973] [drm:intel_crtc_set_config] [CRTC:30] [FB:117] #connectors=1 (x y) (0 0)
>[    4.796977] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:30], mode_changed=0, fb_changed=0
>[    4.796981] [drm:intel_modeset_stage_output_state] [CONNECTOR:41:eDP-1] to [CRTC:20]
>[    4.796983] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:25]
>[    4.796985] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[    4.796988] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 4, prepare: 4, disable: 0
>[    4.796999] [drm:connected_sink_compute_bpp] [CONNECTOR:47:HDMI-A-2] checking for sink bpp constrains
>[    4.797005] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[    4.797007] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[    4.797009] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[    4.797011] [drm:intel_dump_pipe_config] [CRTC:30][modeset] config for pipe C
>[    4.797012] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[    4.797014] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[    4.797017] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[    4.797020] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[    4.797022] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[    4.797024] [drm:intel_dump_pipe_config] audio: 1, infoframes: 1
>[    4.797025] [drm:intel_dump_pipe_config] requested mode:
>[    4.797029] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[    4.797030] [drm:intel_dump_pipe_config] adjusted mode:
>[    4.797035] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[    4.797038] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[    4.797040] [drm:intel_dump_pipe_config] port clock: 148500
>[    4.797061] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[    4.797063] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[    4.797065] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[    4.797067] [drm:intel_dump_pipe_config] ips: 0
>[    4.797068] [drm:intel_dump_pipe_config] double wide: 0
>[    4.865017] EXT4-fs (sda3): mounted filesystem with ordered data mode. Opts: (null)
>[    4.932203] dracut: Checking ext4: /dev/sda3
>[    4.938526] dracut: issuing e2fsck -a  /dev/sda3
>[    4.974778] dracut: /dev/sda3: clean, 627605/4751360 files, 8394281/19000576 blocks
>[    4.982046] dracut: Remounting /dev/sda3 with -o errors=remount-ro,ro
>[    4.999045] EXT4-fs (sda3): mounted filesystem with ordered data mode. Opts: errors=remount-ro
>[    5.013567] dracut: Mounted root filesystem /dev/sda3
>[    5.051515] device-mapper: uevent: version 1.0.3
>[    5.057558] device-mapper: ioctl: 4.30.0-ioctl (2014-12-22) initialised: dm-devel@redhat.com
>[    5.123146] dracut: Switching root
>[    5.193939] random: init urandom read with 50 bits of entropy available
>[    5.243568] init: plymouth-upstart-bridge main process (2438) terminated with status 1
>[    5.249649] init: plymouth-upstart-bridge main process ended, respawning
>[    5.268003] init: plymouth-upstart-bridge main process (2448) terminated with status 1
>[    5.274021] init: plymouth-upstart-bridge main process ended, respawning
>[    5.280457] init: ureadahead main process (2441) terminated with status 5
>[    5.614217] systemd-udevd[2564]: starting version 204
>[    5.772735] [drm:intel_crtc_set_config] [CRTC:20] [FB:117] #connectors=1 (x y) (0 0)
>[    5.772743] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=0, fb_changed=0
>[    5.772747] [drm:intel_modeset_stage_output_state] [CONNECTOR:41:eDP-1] to [CRTC:20]
>[    5.772750] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:25]
>[    5.772752] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[    5.772757] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[    5.772761] [drm:connected_sink_compute_bpp] [CONNECTOR:41:eDP-1] checking for sink bpp constrains
>[    5.772768] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[    5.772770] [drm:intel_dp_compute_config] clamping bpp for eDP panel to BIOS-provided 18
>[    5.772773] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 18
>[    5.772775] [drm:intel_dp_compute_config] DP link bw required 249804 available 432000
>[    5.772780] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 18, dithering: 1
>[    5.772782] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[    5.772784] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[    5.772785] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
>[    5.772789] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[    5.772792] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 4850712, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[    5.772794] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[    5.772796] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[    5.772797] [drm:intel_dump_pipe_config] requested mode:
>[    5.772802] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[    5.772803] [drm:intel_dump_pipe_config] adjusted mode:
>[    5.772808] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[    5.772812] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[    5.772813] [drm:intel_dump_pipe_config] port clock: 270000
>[    5.772815] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[    5.772817] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[    5.772819] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[    5.772821] [drm:intel_dump_pipe_config] ips: 0
>[    5.772822] [drm:intel_dump_pipe_config] double wide: 0
>[    5.772828] [drm:intel_crtc_set_config] [CRTC:25] [FB:117] #connectors=1 (x y) (0 0)
>[    5.772832] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:25], mode_changed=0, fb_changed=0
>[    5.772834] [drm:intel_modeset_stage_output_state] [CONNECTOR:41:eDP-1] to [CRTC:20]
>[    5.772837] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:25]
>[    5.772839] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[    5.772842] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[    5.772845] [drm:connected_sink_compute_bpp] [CONNECTOR:39:DP-1] checking for sink bpp constrains
>[    5.772848] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[    5.772854] [drm:intel_dp_compute_config] DP link bw 06 lane count 4 clock 162000 bpp 24
>[    5.772856] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400
>[    5.772859] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[    5.772861] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config for pipe B
>[    5.772862] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[    5.772864] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[    5.772867] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[    5.772870] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[    5.772872] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[    5.772874] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[    5.772875] [drm:intel_dump_pipe_config] requested mode:
>[    5.772880] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[    5.772881] [drm:intel_dump_pipe_config] adjusted mode:
>[    5.772885] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[    5.772889] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[    5.772890] [drm:intel_dump_pipe_config] port clock: 162000
>[    5.772892] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[    5.772894] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[    5.772896] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[    5.772898] [drm:intel_dump_pipe_config] ips: 0
>[    5.772899] [drm:intel_dump_pipe_config] double wide: 0
>[    5.772903] [drm:intel_crtc_set_config] [CRTC:30] [FB:117] #connectors=1 (x y) (0 0)
>[    5.772907] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:30], mode_changed=0, fb_changed=0
>[    5.772909] [drm:intel_modeset_stage_output_state] [CONNECTOR:41:eDP-1] to [CRTC:20]
>[    5.772911] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:25]
>[    5.772913] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[    5.772916] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 4, prepare: 4, disable: 0
>[    5.772919] [drm:connected_sink_compute_bpp] [CONNECTOR:47:HDMI-A-2] checking for sink bpp constrains
>[    5.772924] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[    5.772925] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[    5.772927] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[    5.772929] [drm:intel_dump_pipe_config] [CRTC:30][modeset] config for pipe C
>[    5.772931] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[    5.772932] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[    5.772935] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[    5.772938] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[    5.772940] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[    5.772942] [drm:intel_dump_pipe_config] audio: 1, infoframes: 1
>[    5.772943] [drm:intel_dump_pipe_config] requested mode:
>[    5.772948] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[    5.772949] [drm:intel_dump_pipe_config] adjusted mode:
>[    5.772953] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[    5.772957] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[    5.772958] [drm:intel_dump_pipe_config] port clock: 148500
>[    5.772960] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[    5.772962] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[    5.772964] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[    5.772966] [drm:intel_dump_pipe_config] ips: 0
>[    5.772967] [drm:intel_dump_pipe_config] double wide: 0
>[    5.863431] [drm:i915_gem_open] 
>[    5.867643] [drm:gen8_ppgtt_init] Allocated 4 pages for page directories (2 wasted)
>[    5.867651] [drm:gen8_ppgtt_init] Allocated 2048 pages for page tables (1024 wasted)
>[    5.868634] [drm:intel_crtc_set_config] [CRTC:20] [FB:117] #connectors=1 (x y) (0 0)
>[    5.868645] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=0, fb_changed=0
>[    5.868651] [drm:intel_modeset_stage_output_state] [CONNECTOR:41:eDP-1] to [CRTC:20]
>[    5.868655] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:25]
>[    5.868660] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[    5.868666] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[    5.868672] [drm:connected_sink_compute_bpp] [CONNECTOR:41:eDP-1] checking for sink bpp constrains
>[    5.868680] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[    5.868684] [drm:intel_dp_compute_config] clamping bpp for eDP panel to BIOS-provided 18
>[    5.868689] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 18
>[    5.868693] [drm:intel_dp_compute_config] DP link bw required 249804 available 432000
>[    5.868699] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 18, dithering: 1
>[    5.868703] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[    5.868707] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[    5.868710] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
>[    5.868715] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[    5.868720] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 4850712, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[    5.868725] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[    5.868729] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[    5.868732] [drm:intel_dump_pipe_config] requested mode:
>[    5.868738] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[    5.868742] [drm:intel_dump_pipe_config] adjusted mode:
>[    5.868748] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[    5.868754] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[    5.868757] [drm:intel_dump_pipe_config] port clock: 270000
>[    5.868761] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[    5.868765] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[    5.868769] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[    5.868773] [drm:intel_dump_pipe_config] ips: 0
>[    5.868776] [drm:intel_dump_pipe_config] double wide: 0
>[    5.868782] [drm:intel_crtc_set_config] [CRTC:25] [FB:117] #connectors=1 (x y) (0 0)
>[    5.868788] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:25], mode_changed=0, fb_changed=0
>[    5.868792] [drm:intel_modeset_stage_output_state] [CONNECTOR:41:eDP-1] to [CRTC:20]
>[    5.868796] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:25]
>[    5.868800] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[    5.868806] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[    5.868811] [drm:connected_sink_compute_bpp] [CONNECTOR:39:DP-1] checking for sink bpp constrains
>[    5.868816] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[    5.868824] [drm:intel_dp_compute_config] DP link bw 06 lane count 4 clock 162000 bpp 24
>[    5.868828] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400
>[    5.868833] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[    5.868837] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config for pipe B
>[    5.868840] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[    5.868844] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[    5.868848] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[    5.868853] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[    5.868858] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[    5.868862] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[    5.868865] [drm:intel_dump_pipe_config] requested mode:
>[    5.868871] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[    5.868874] [drm:intel_dump_pipe_config] adjusted mode:
>[    5.868880] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[    5.868886] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[    5.868889] [drm:intel_dump_pipe_config] port clock: 162000
>[    5.868893] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[    5.868897] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[    5.868901] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[    5.868904] [drm:intel_dump_pipe_config] ips: 0
>[    5.868908] [drm:intel_dump_pipe_config] double wide: 0
>[    5.868913] [drm:intel_crtc_set_config] [CRTC:30] [FB:117] #connectors=1 (x y) (0 0)
>[    5.868919] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:30], mode_changed=0, fb_changed=0
>[    5.868923] [drm:intel_modeset_stage_output_state] [CONNECTOR:41:eDP-1] to [CRTC:20]
>[    5.868927] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:25]
>[    5.868931] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[    5.868936] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 4, prepare: 4, disable: 0
>[    5.868941] [drm:connected_sink_compute_bpp] [CONNECTOR:47:HDMI-A-2] checking for sink bpp constrains
>[    5.868948] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[    5.868951] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[    5.868955] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[    5.868959] [drm:intel_dump_pipe_config] [CRTC:30][modeset] config for pipe C
>[    5.868962] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[    5.868966] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[    5.868971] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[    5.868975] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[    5.868980] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[    5.868983] [drm:intel_dump_pipe_config] audio: 1, infoframes: 1
>[    5.868986] [drm:intel_dump_pipe_config] requested mode:
>[    5.868992] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[    5.868996] [drm:intel_dump_pipe_config] adjusted mode:
>[    5.869002] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[    5.869007] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[    5.869011] [drm:intel_dump_pipe_config] port clock: 148500
>[    5.869014] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[    5.869019] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[    5.869023] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[    5.869026] [drm:intel_dump_pipe_config] ips: 0
>[    5.869029] [drm:intel_dump_pipe_config] double wide: 0
>[    5.869064] [drm:i915_gem_open] 
>[    5.879235] [drm:gen8_ppgtt_init] Allocated 4 pages for page directories (2 wasted)
>[    5.879246] [drm:gen8_ppgtt_init] Allocated 2048 pages for page tables (1024 wasted)
>[    5.883859] [drm:intel_crtc_set_config] [CRTC:20] [FB:117] #connectors=1 (x y) (0 0)
>[    5.883870] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=0, fb_changed=0
>[    5.883876] [drm:intel_modeset_stage_output_state] [CONNECTOR:41:eDP-1] to [CRTC:20]
>[    5.883881] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:25]
>[    5.883885] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[    5.883892] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[    5.883897] [drm:connected_sink_compute_bpp] [CONNECTOR:41:eDP-1] checking for sink bpp constrains
>[    5.883906] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[    5.883910] [drm:intel_dp_compute_config] clamping bpp for eDP panel to BIOS-provided 18
>[    5.883915] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 18
>[    5.883919] [drm:intel_dp_compute_config] DP link bw required 249804 available 432000
>[    5.883925] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 18, dithering: 1
>[    5.883929] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[    5.883933] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[    5.883936] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
>[    5.883941] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[    5.883946] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 4850712, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[    5.883951] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[    5.883954] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[    5.883957] [drm:intel_dump_pipe_config] requested mode:
>[    5.883964] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[    5.883967] [drm:intel_dump_pipe_config] adjusted mode:
>[    5.883974] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[    5.883980] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[    5.883983] [drm:intel_dump_pipe_config] port clock: 270000
>[    5.883987] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[    5.883991] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[    5.883995] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[    5.883998] [drm:intel_dump_pipe_config] ips: 0
>[    5.884002] [drm:intel_dump_pipe_config] double wide: 0
>[    5.884010] [drm:intel_crtc_set_config] [CRTC:25] [FB:117] #connectors=1 (x y) (0 0)
>[    5.886607] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:25], mode_changed=0, fb_changed=0
>[    5.886643] [drm:intel_modeset_stage_output_state] [CONNECTOR:41:eDP-1] to [CRTC:20]
>[    5.886648] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:25]
>[    5.886652] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[    5.886659] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[    5.887370] [drm:connected_sink_compute_bpp] [CONNECTOR:39:DP-1] checking for sink bpp constrains
>[    5.887380] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[    5.887388] [drm:intel_dp_compute_config] DP link bw 06 lane count 4 clock 162000 bpp 24
>[    5.887392] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400
>[    5.887398] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[    5.887403] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config for pipe B
>[    5.887406] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[    5.887410] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[    5.887415] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[    5.887420] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[    5.887425] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[    5.887428] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[    5.887431] [drm:intel_dump_pipe_config] requested mode:
>[    5.887438] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[    5.887442] [drm:intel_dump_pipe_config] adjusted mode:
>[    5.887448] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[    5.887454] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[    5.887457] [drm:intel_dump_pipe_config] port clock: 162000
>[    5.887461] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[    5.887465] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[    5.887469] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[    5.887473] [drm:intel_dump_pipe_config] ips: 0
>[    5.887476] [drm:intel_dump_pipe_config] double wide: 0
>[    5.887486] [drm:intel_crtc_set_config] [CRTC:30] [FB:117] #connectors=1 (x y) (0 0)
>[    5.887493] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:30], mode_changed=0, fb_changed=0
>[    5.887498] [drm:intel_modeset_stage_output_state] [CONNECTOR:41:eDP-1] to [CRTC:20]
>[    5.887502] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:25]
>[    5.887507] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[    5.887513] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 4, prepare: 4, disable: 0
>[    5.887550] [drm:connected_sink_compute_bpp] [CONNECTOR:47:HDMI-A-2] checking for sink bpp constrains
>[    5.887557] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[    5.887561] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[    5.887565] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[    5.887569] [drm:intel_dump_pipe_config] [CRTC:30][modeset] config for pipe C
>[    5.887572] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[    5.887576] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[    5.887581] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[    5.887585] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[    5.887590] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[    5.887593] [drm:intel_dump_pipe_config] audio: 1, infoframes: 1
>[    5.887596] [drm:intel_dump_pipe_config] requested mode:
>[    5.887603] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[    5.887606] [drm:intel_dump_pipe_config] adjusted mode:
>[    5.887612] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[    5.887618] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[    5.887621] [drm:intel_dump_pipe_config] port clock: 148500
>[    5.887625] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[    5.887629] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[    5.887633] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[    5.887637] [drm:intel_dump_pipe_config] ips: 0
>[    5.887640] [drm:intel_dump_pipe_config] double wide: 0
>[    5.887688] [drm:i915_gem_open] 
>[    5.893290] [drm:gen8_ppgtt_init] Allocated 4 pages for page directories (2 wasted)
>[    5.893298] [drm:gen8_ppgtt_init] Allocated 2048 pages for page tables (1024 wasted)
>[    5.893470] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[5] ENCODERS[5]
>[    5.893480] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[5] ENCODERS[5]
>[    5.893501] [drm:drm_mode_getconnector] [CONNECTOR:41:?]
>[    5.893508] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:41:eDP-1]
>[    5.893513] [drm:intel_dp_detect] [CONNECTOR:41:eDP-1]
>[    5.896062] [drm:intel_dp_probe_oui] Sink OUI: 001cf8
>[    5.902313] [drm:intel_dp_probe_oui] Branch OUI: 000000
>[    5.902340] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[    5.902348] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:41:eDP-1] probed modes :
>[    5.902355] [drm:drm_mode_debug_printmodeline] Modeline 42:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[    5.902372] [drm:drm_mode_getconnector] [CONNECTOR:41:?]
>[    5.935896] [drm:drm_mode_getconnector] [CONNECTOR:34:?]
>[    5.935907] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:34:HDMI-A-1]
>[    5.935912] [drm:intel_hdmi_detect] [CONNECTOR:34:HDMI-A-1]
>[    5.937270] [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 r(1)
>[    5.937279] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[    5.937287] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:34:HDMI-A-1] disconnected
>[    5.937304] [drm:drm_mode_getconnector] [CONNECTOR:34:?]
>[    5.937309] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:34:HDMI-A-1]
>[    5.937312] [drm:intel_hdmi_detect] [CONNECTOR:34:HDMI-A-1]
>[    5.937622] [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 r(1)
>[    5.937628] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[    5.937633] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:34:HDMI-A-1] disconnected
>[    5.937648] [drm:drm_mode_getconnector] [CONNECTOR:39:?]
>[    5.937653] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:39:DP-1]
>[    5.937663] [drm:intel_dp_detect] [CONNECTOR:39:DP-1]
>[    5.938235] [drm:intel_dp_get_dpcd] DPCD: 11 0a 84 00 01 00 00 00 00 00 00 00 00 00 00
>[    5.949674] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[    5.949927] [drm:drm_edid_to_eld] ELD monitor ASUS PA238
>[    5.949933] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[    5.950035] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:39:DP-1] probed modes :
>[    5.950043] [drm:drm_mode_debug_printmodeline] Modeline 52:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[    5.950050] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[    5.950064] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[    5.950071] [drm:drm_mode_debug_printmodeline] Modeline 100:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[    5.950078] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[    5.950084] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[    5.950091] [drm:drm_mode_debug_printmodeline] Modeline 61:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[    5.950097] [drm:drm_mode_debug_printmodeline] Modeline 70:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[    5.950104] [drm:drm_mode_debug_printmodeline] Modeline 59:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[    5.950110] [drm:drm_mode_debug_printmodeline] Modeline 60:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6
>[    5.950117] [drm:drm_mode_debug_printmodeline] Modeline 57:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[    5.950123] [drm:drm_mode_debug_printmodeline] Modeline 58:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[    5.950130] [drm:drm_mode_debug_printmodeline] Modeline 62:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[    5.950136] [drm:drm_mode_debug_printmodeline] Modeline 54:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[    5.950143] [drm:drm_mode_debug_printmodeline] Modeline 94:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[    5.950158] [drm:drm_mode_debug_printmodeline] Modeline 55:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[    5.950164] [drm:drm_mode_debug_printmodeline] Modeline 90:"1440x576" 50 54000 1440 1464 1592 1728 576 581 586 625 0x40 0xa
>[    5.950171] [drm:drm_mode_debug_printmodeline] Modeline 71:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[    5.950177] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[    5.950184] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[    5.950191] [drm:drm_mode_debug_printmodeline] Modeline 102:"1440x480" 60 54054 1440 1472 1596 1716 480 489 495 525 0x40 0xa
>[    5.950197] [drm:drm_mode_debug_printmodeline] Modeline 88:"1440x480" 60 54000 1440 1472 1596 1716 480 489 495 525 0x40 0xa
>[    5.950204] [drm:drm_mode_debug_printmodeline] Modeline 74:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[    5.950210] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[    5.950216] [drm:drm_mode_debug_printmodeline] Modeline 76:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[    5.950223] [drm:drm_mode_debug_printmodeline] Modeline 63:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[    5.950229] [drm:drm_mode_debug_printmodeline] Modeline 64:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[    5.950244] [drm:drm_mode_debug_printmodeline] Modeline 56:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[    5.950250] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[    5.950257] [drm:drm_mode_debug_printmodeline] Modeline 53:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[    5.950263] [drm:drm_mode_debug_printmodeline] Modeline 65:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[    5.950269] [drm:drm_mode_debug_printmodeline] Modeline 66:"640x480" 73 31500 640 664 704 832 480 489 491 520 0x40 0xa
>[    5.950276] [drm:drm_mode_debug_printmodeline] Modeline 67:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[    5.950282] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[    5.950289] [drm:drm_mode_debug_printmodeline] Modeline 77:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[    5.950295] [drm:drm_mode_debug_printmodeline] Modeline 69:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[    5.950315] [drm:drm_mode_getconnector] [CONNECTOR:39:?]
>[    5.962467] asix 1-6.1.4:1.0 eth1: renamed from eth0
>[    5.967691] systemd-udevd[2720]: renamed network interface eth0 to eth1
>[    5.987358] [drm:drm_mode_getconnector] [CONNECTOR:47:?]
>[    5.987370] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:47:HDMI-A-2]
>[    5.987380] [drm:intel_hdmi_detect] [CONNECTOR:47:HDMI-A-2]
>[    6.017392] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[    6.017613] [drm:drm_edid_to_eld] ELD monitor ASUS VS239
>[    6.017620] [drm:parse_hdmi_vsdb] HDMI: DVI dual 0, max TMDS clock 0, latency present 0 0, video latency 0 0, audio latency 0 0
>[    6.017624] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[    6.017705] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:47:HDMI-A-2] probed modes :
>[    6.017714] [drm:drm_mode_debug_printmodeline] Modeline 79:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[    6.017721] [drm:drm_mode_debug_printmodeline] Modeline 128:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[    6.017728] [drm:drm_mode_debug_printmodeline] Modeline 121:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[    6.017734] [drm:drm_mode_debug_printmodeline] Modeline 136:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[    6.017741] [drm:drm_mode_debug_printmodeline] Modeline 126:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[    6.017747] [drm:drm_mode_debug_printmodeline] Modeline 120:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[    6.017754] [drm:drm_mode_debug_printmodeline] Modeline 95:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[    6.017760] [drm:drm_mode_debug_printmodeline] Modeline 106:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[    6.017766] [drm:drm_mode_debug_printmodeline] Modeline 89:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[    6.017773] [drm:drm_mode_debug_printmodeline] Modeline 91:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[    6.017779] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[    6.017786] [drm:drm_mode_debug_printmodeline] Modeline 97:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[    6.017792] [drm:drm_mode_debug_printmodeline] Modeline 96:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[    6.017799] [drm:drm_mode_debug_printmodeline] Modeline 81:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[    6.017805] [drm:drm_mode_debug_printmodeline] Modeline 130:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[    6.017812] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[    6.017818] [drm:drm_mode_debug_printmodeline] Modeline 124:"1440x576" 50 54000 1440 1464 1592 1728 576 581 586 625 0x40 0xa
>[    6.017825] [drm:drm_mode_debug_printmodeline] Modeline 107:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[    6.017831] [drm:drm_mode_debug_printmodeline] Modeline 108:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[    6.017838] [drm:drm_mode_debug_printmodeline] Modeline 109:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[    6.017844] [drm:drm_mode_debug_printmodeline] Modeline 137:"1440x480" 60 54054 1440 1472 1596 1716 480 489 495 525 0x40 0xa
>[    6.017851] [drm:drm_mode_debug_printmodeline] Modeline 122:"1440x480" 60 54000 1440 1472 1596 1716 480 489 495 525 0x40 0xa
>[    6.017857] [drm:drm_mode_debug_printmodeline] Modeline 110:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[    6.017864] [drm:drm_mode_debug_printmodeline] Modeline 111:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[    6.017870] [drm:drm_mode_debug_printmodeline] Modeline 112:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[    6.017877] [drm:drm_mode_debug_printmodeline] Modeline 98:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[    6.017883] [drm:drm_mode_debug_printmodeline] Modeline 99:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[    6.017889] [drm:drm_mode_debug_printmodeline] Modeline 83:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[    6.017896] [drm:drm_mode_debug_printmodeline] Modeline 129:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[    6.017902] [drm:drm_mode_debug_printmodeline] Modeline 80:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[    6.017909] [drm:drm_mode_debug_printmodeline] Modeline 101:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[    6.017915] [drm:drm_mode_debug_printmodeline] Modeline 103:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[    6.017921] [drm:drm_mode_debug_printmodeline] Modeline 104:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[    6.017928] [drm:drm_mode_debug_printmodeline] Modeline 113:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[    6.017934] [drm:drm_mode_debug_printmodeline] Modeline 105:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[    6.017963] [drm:drm_mode_getconnector] [CONNECTOR:47:?]
>[    6.047542] [drm:drm_mode_getconnector] [CONNECTOR:49:?]
>[    6.047554] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:49:DP-2]
>[    6.047559] [drm:intel_dp_detect] [CONNECTOR:49:DP-2]
>[    6.048078] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    6.051838] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    6.052537] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    6.053051] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    6.054224] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    6.054425] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[    6.054933] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    6.055447] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    6.055954] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    6.056452] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    6.056958] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    6.059867] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[    6.062801] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    6.063308] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    6.063819] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    6.064328] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    6.064845] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    6.064868] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[    6.067210] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    6.067720] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    6.068391] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    6.068988] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    6.069499] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    6.070067] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[    6.071696] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:49:DP-2] disconnected
>[    6.071716] [drm:drm_mode_getconnector] [CONNECTOR:49:?]
>[    6.071719] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:49:DP-2]
>[    6.071721] [drm:intel_dp_detect] [CONNECTOR:49:DP-2]
>[    6.072236] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    6.072751] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    6.073260] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    6.073827] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    6.074339] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    6.074373] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[    6.074881] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    6.075389] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    6.075896] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    6.076421] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    6.076931] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    6.076955] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[    6.079147] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    6.079656] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    6.080174] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    6.080682] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    6.081185] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    6.081201] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[    6.083128] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    6.083630] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    6.084129] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    6.084635] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    6.085151] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[    6.085195] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[    6.086628] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:49:DP-2] disconnected
>[    6.086686] [drm:drm_mode_addfb2] [FB:116]
>[    6.146945] Adding 1952764k swap on /dev/sda2.  Priority:-1 extents:1 across:1952764k SS
>[    6.156535] EXT4-fs (sda3): re-mounted. Opts: errors=remount-ro
>[    6.741773] init: bluetooth main process (3337) terminated with status 1
>[    6.741808] init: bluetooth main process ended, respawning
>[    6.942196] init: bluetooth main process (3386) terminated with status 1
>[    6.942235] init: bluetooth main process ended, respawning
>[    7.275737] asix 1-6.1.4:1.0 eth1: link up, 100Mbps, full-duplex, lpa 0xC5E1
>[    7.484085] asix 1-6.1.4:1.0 eth1: link up, 100Mbps, full-duplex, lpa 0xC5E1
>[    7.670749] init: bluetooth main process (3614) terminated with status 1
>[    7.670786] init: bluetooth main process ended, respawning
>[    7.955061] [drm:intel_crtc_set_config] [CRTC:20] [FB:117] #connectors=1 (x y) (0 0)
>[    7.955074] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=0, fb_changed=0
>[    7.955081] [drm:intel_modeset_stage_output_state] [CONNECTOR:41:eDP-1] to [CRTC:20]
>[    7.955085] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:25]
>[    7.955090] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[    7.955096] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[    7.955101] [drm:connected_sink_compute_bpp] [CONNECTOR:41:eDP-1] checking for sink bpp constrains
>[    7.955110] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[    7.955114] [drm:intel_dp_compute_config] clamping bpp for eDP panel to BIOS-provided 18
>[    7.955119] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 18
>[    7.955123] [drm:intel_dp_compute_config] DP link bw required 249804 available 432000
>[    7.955128] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 18, dithering: 1
>[    7.955133] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[    7.955136] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[    7.955140] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
>[    7.955145] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[    7.955150] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 4850712, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[    7.955155] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[    7.955158] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[    7.955161] [drm:intel_dump_pipe_config] requested mode:
>[    7.955168] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[    7.955171] [drm:intel_dump_pipe_config] adjusted mode:
>[    7.955177] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[    7.955183] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[    7.955187] [drm:intel_dump_pipe_config] port clock: 270000
>[    7.955191] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[    7.955195] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[    7.955199] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[    7.955202] [drm:intel_dump_pipe_config] ips: 0
>[    7.955206] [drm:intel_dump_pipe_config] double wide: 0
>[    7.955212] [drm:intel_crtc_set_config] [CRTC:25] [FB:117] #connectors=1 (x y) (0 0)
>[    7.955217] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:25], mode_changed=0, fb_changed=0
>[    7.955222] [drm:intel_modeset_stage_output_state] [CONNECTOR:41:eDP-1] to [CRTC:20]
>[    7.955226] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:25]
>[    7.955230] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[    7.955236] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[    7.955241] [drm:connected_sink_compute_bpp] [CONNECTOR:39:DP-1] checking for sink bpp constrains
>[    7.955246] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[    7.955254] [drm:intel_dp_compute_config] DP link bw 06 lane count 4 clock 162000 bpp 24
>[    7.955258] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400
>[    7.955263] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[    7.955267] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config for pipe B
>[    7.955270] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[    7.955274] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[    7.955279] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[    7.955283] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[    7.955288] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[    7.955292] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[    7.955295] [drm:intel_dump_pipe_config] requested mode:
>[    7.955301] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[    7.955304] [drm:intel_dump_pipe_config] adjusted mode:
>[    7.955310] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[    7.955316] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[    7.955320] [drm:intel_dump_pipe_config] port clock: 162000
>[    7.955323] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[    7.955327] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[    7.955331] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[    7.955335] [drm:intel_dump_pipe_config] ips: 0
>[    7.955338] [drm:intel_dump_pipe_config] double wide: 0
>[    7.955343] [drm:intel_crtc_set_config] [CRTC:30] [FB:117] #connectors=1 (x y) (0 0)
>[    7.955349] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:30], mode_changed=0, fb_changed=0
>[    7.955353] [drm:intel_modeset_stage_output_state] [CONNECTOR:41:eDP-1] to [CRTC:20]
>[    7.955358] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:25]
>[    7.955362] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[    7.955366] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 4, prepare: 4, disable: 0
>[    7.955371] [drm:connected_sink_compute_bpp] [CONNECTOR:47:HDMI-A-2] checking for sink bpp constrains
>[    7.955378] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[    7.955381] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[    7.955386] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[    7.955390] [drm:intel_dump_pipe_config] [CRTC:30][modeset] config for pipe C
>[    7.955393] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[    7.955396] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[    7.955401] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[    7.955406] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[    7.955410] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[    7.955414] [drm:intel_dump_pipe_config] audio: 1, infoframes: 1
>[    7.955417] [drm:intel_dump_pipe_config] requested mode:
>[    7.955450] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[    7.955466] [drm:intel_dump_pipe_config] adjusted mode:
>[    7.955482] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[    7.955506] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[    7.955520] [drm:intel_dump_pipe_config] port clock: 148500
>[    7.955535] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[    7.955550] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[    7.955565] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[    7.955580] [drm:intel_dump_pipe_config] ips: 0
>[    7.955594] [drm:intel_dump_pipe_config] double wide: 0
>[    7.955701] [drm:intel_crtc_set_config] [CRTC:20] [FB:117] #connectors=1 (x y) (0 0)
>[    7.955705] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=0, fb_changed=0
>[    7.955708] [drm:intel_modeset_stage_output_state] [CONNECTOR:41:eDP-1] to [CRTC:20]
>[    7.955710] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:25]
>[    7.955713] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[    7.955716] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[    7.955719] [drm:connected_sink_compute_bpp] [CONNECTOR:41:eDP-1] checking for sink bpp constrains
>[    7.955723] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[    7.955725] [drm:intel_dp_compute_config] clamping bpp for eDP panel to BIOS-provided 18
>[    7.955728] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 18
>[    7.955730] [drm:intel_dp_compute_config] DP link bw required 249804 available 432000
>[    7.955733] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 18, dithering: 1
>[    7.955735] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[    7.955737] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[    7.955738] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
>[    7.955741] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[    7.955744] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 4850712, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[    7.955747] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[    7.955748] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[    7.955750] [drm:intel_dump_pipe_config] requested mode:
>[    7.955754] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[    7.955755] [drm:intel_dump_pipe_config] adjusted mode:
>[    7.955760] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[    7.955763] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[    7.955765] [drm:intel_dump_pipe_config] port clock: 270000
>[    7.955767] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[    7.955769] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[    7.955771] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[    7.955772] [drm:intel_dump_pipe_config] ips: 0
>[    7.955774] [drm:intel_dump_pipe_config] double wide: 0
>[    7.955778] [drm:intel_crtc_set_config] [CRTC:25] [FB:117] #connectors=1 (x y) (0 0)
>[    7.955782] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:25], mode_changed=0, fb_changed=0
>[    7.955784] [drm:intel_modeset_stage_output_state] [CONNECTOR:41:eDP-1] to [CRTC:20]
>[    7.955786] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:25]
>[    7.955788] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[    7.955791] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[    7.955794] [drm:connected_sink_compute_bpp] [CONNECTOR:39:DP-1] checking for sink bpp constrains
>[    7.955797] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[    7.955802] [drm:intel_dp_compute_config] DP link bw 06 lane count 4 clock 162000 bpp 24
>[    7.955804] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400
>[    7.955806] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[    7.955808] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config for pipe B
>[    7.955810] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[    7.955811] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[    7.955814] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[    7.955817] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[    7.955820] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[    7.955822] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[    7.955823] [drm:intel_dump_pipe_config] requested mode:
>[    7.955827] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[    7.955828] [drm:intel_dump_pipe_config] adjusted mode:
>[    7.955833] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[    7.955836] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[    7.955838] [drm:intel_dump_pipe_config] port clock: 162000
>[    7.955839] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[    7.955842] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[    7.955844] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[    7.955845] [drm:intel_dump_pipe_config] ips: 0
>[    7.955846] [drm:intel_dump_pipe_config] double wide: 0
>[    7.955850] [drm:intel_crtc_set_config] [CRTC:30] [FB:117] #connectors=1 (x y) (0 0)
>[    7.955854] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:30], mode_changed=0, fb_changed=0
>[    7.955856] [drm:intel_modeset_stage_output_state] [CONNECTOR:41:eDP-1] to [CRTC:20]
>[    7.955858] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:25]
>[    7.955860] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[    7.955863] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 4, prepare: 4, disable: 0
>[    7.955866] [drm:connected_sink_compute_bpp] [CONNECTOR:47:HDMI-A-2] checking for sink bpp constrains
>[    7.955870] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[    7.955871] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[    7.955873] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[    7.955875] [drm:intel_dump_pipe_config] [CRTC:30][modeset] config for pipe C
>[    7.955877] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[    7.955878] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[    7.955881] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[    7.955884] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[    7.955886] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[    7.955888] [drm:intel_dump_pipe_config] audio: 1, infoframes: 1
>[    7.955889] [drm:intel_dump_pipe_config] requested mode:
>[    7.955894] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[    7.955895] [drm:intel_dump_pipe_config] adjusted mode:
>[    7.955899] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[    7.955903] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[    7.955904] [drm:intel_dump_pipe_config] port clock: 148500
>[    7.955906] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[    7.955908] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[    7.955910] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[    7.955912] [drm:intel_dump_pipe_config] ips: 0
>[    7.955913] [drm:intel_dump_pipe_config] double wide: 0
>[    7.981100] init: plymouth-upstart-bridge main process ended, respawning
>[    8.047558] init: bluetooth main process (3776) terminated with status 1
>[    8.047593] init: bluetooth main process ended, respawning
>[    8.052170] init: Failed to obtain startpar-bridge instance: Unknown parameter: INSTANCE
>[    8.155581] init: bluetooth main process (3817) terminated with status 1
>[    8.155616] init: bluetooth main process ended, respawning
>[    8.206660] init: bluetooth main process (3845) terminated with status 1
>[    8.206695] init: bluetooth main process ended, respawning
>[    8.252054] init: bluetooth main process (3869) terminated with status 1
>[    8.252088] init: bluetooth main process ended, respawning
>[    8.306323] init: bluetooth main process (3893) terminated with status 1
>[    8.306359] init: bluetooth main process ended, respawning
>[    8.372751] init: bluetooth main process (3920) terminated with status 1
>[    8.372784] init: bluetooth main process ended, respawning
>[    8.406654] [drm:edp_panel_vdd_off_sync] Turning eDP port C VDD off
>[    8.406669] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0007
>[    8.419355] init: bluetooth main process (3954) terminated with status 1
>[    8.419391] init: bluetooth main process ended, respawning
>[    8.467065] init: bluetooth main process (3994) terminated with status 1
>[    8.467098] init: bluetooth respawning too fast, stopped
>[    9.660428] random: nonblocking pool is initialized
>[   41.737041] [drm:i915_gem_open] 
>[   41.741211] [drm:gen8_ppgtt_init] Allocated 4 pages for page directories (2 wasted)
>[   41.741220] [drm:gen8_ppgtt_init] Allocated 2048 pages for page tables (1024 wasted)
>[   41.741461] [drm:i915_gem_object_create_stolen] creating stolen object: size=20000
>[   41.741469] [drm:i915_pages_create_for_stolen] offset=0x0, size=131072
>[   41.741863] [drm:i915_gem_object_create_stolen] creating stolen object: size=20000
>[   41.741870] [drm:i915_pages_create_for_stolen] offset=0x20000, size=131072
>[   41.743228] [drm:i915_gem_object_create_stolen] creating stolen object: size=20000
>[   41.743236] [drm:i915_pages_create_for_stolen] offset=0x40000, size=131072
>[   41.743316] [drm:i915_gem_object_create_stolen] creating stolen object: size=20000
>[   41.743325] [drm:i915_pages_create_for_stolen] offset=0x60000, size=131072
>[   41.743492] [drm:i915_gem_open] 
>[   41.747445] [drm:gen8_ppgtt_init] Allocated 4 pages for page directories (2 wasted)
>[   41.747454] [drm:gen8_ppgtt_init] Allocated 2048 pages for page tables (1024 wasted)
>[   41.748082] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[5] ENCODERS[5]
>[   41.748099] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[5] ENCODERS[5]
>[   41.748116] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[5] ENCODERS[5]
>[   41.748123] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[5] ENCODERS[5]
>[   41.748140] [drm:drm_mode_getconnector] [CONNECTOR:41:?]
>[   41.748182] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:41:eDP-1]
>[   41.748189] [drm:intel_dp_detect] [CONNECTOR:41:eDP-1]
>[   41.748205] [drm:edp_panel_vdd_on] Turning eDP port C VDD on
>[   41.748216] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f
>[   41.748575] [drm:intel_dp_probe_oui] Sink OUI: 001cf8
>[   41.748964] [drm:intel_dp_probe_oui] Branch OUI: 000000
>[   41.748994] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[   41.749004] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:41:eDP-1] probed modes :
>[   41.749013] [drm:drm_mode_debug_printmodeline] Modeline 42:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[   41.749036] [drm:drm_mode_getconnector] [CONNECTOR:41:?]
>[   41.749138] [drm:drm_mode_addfb2] [FB:116]
>[   42.008210] [drm:drm_mode_setcrtc] [CRTC:20]
>[   42.008227] [drm:drm_mode_setcrtc] [CONNECTOR:41:eDP-1]
>[   42.008236] [drm:intel_crtc_set_config] [CRTC:20] [FB:116] #connectors=1 (x y) (0 0)
>[   42.008246] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=1, fb_changed=0
>[   42.008253] [drm:intel_modeset_stage_output_state] [CONNECTOR:41:eDP-1] to [CRTC:20]
>[   42.008277] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:25]
>[   42.008283] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[   42.008290] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[   42.008297] [drm:connected_sink_compute_bpp] [CONNECTOR:41:eDP-1] checking for sink bpp constrains
>[   42.008307] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[   42.008312] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 18
>[   42.008316] [drm:intel_dp_compute_config] DP link bw required 249804 available 432000
>[   42.008322] [drm:intel_modeset_pipe_config] plane bpp: 18, pipe bpp: 18, dithering: 0
>[   42.008327] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[   42.008330] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[   42.008334] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 0
>[   42.008339] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   42.008344] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 4850712, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[   42.008349] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   42.008352] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[   42.008355] [drm:intel_dump_pipe_config] requested mode:
>[   42.008362] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[   42.008365] [drm:intel_dump_pipe_config] adjusted mode:
>[   42.008371] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[   42.008377] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[   42.008381] [drm:intel_dump_pipe_config] port clock: 270000
>[   42.008384] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   42.008388] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   42.008393] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   42.008396] [drm:intel_dump_pipe_config] ips: 0
>[   42.008399] [drm:intel_dump_pipe_config] double wide: 0
>[   42.012273] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[   42.026295] [drm:intel_edp_backlight_off] 
>[   42.227378] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[   42.227610] [drm:edp_panel_off] Turn eDP port C panel power off
>[   42.227618] [drm:wait_panel_off] Wait for panel power off time
>[   42.227625] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000
>[   42.271811] [drm:wait_panel_status] Wait complete
>[   42.277518] [drm:intel_dp_link_down] 
>[   42.352485] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[   42.352496] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=0, cursor=0, SR: plane=0, cursor=0
>[   42.362474] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[   42.448525] [drm:edp_panel_vdd_on] Turning eDP port C VDD on
>[   42.448534] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   42.728643] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0000
>[   42.728650] [drm:wait_panel_status] Wait complete
>[   42.728660] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008
>[   42.728666] [drm:edp_panel_vdd_on] eDP port C panel power wasn't enabled
>[   42.930096] [drm:edp_panel_on] Turn eDP port C panel power on
>[   42.930110] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[   42.930122] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0008
>[   42.930127] [drm:wait_panel_status] Wait complete
>[   42.930137] [drm:wait_panel_on] Wait for panel power on
>[   42.930144] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd000b
>[   43.084098] [drm:wait_panel_status] Wait complete
>[   43.084126] [drm:edp_panel_vdd_off_sync] Turning eDP port C VDD off
>[   43.084138] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003
>[   43.084157] [drm:edp_panel_vdd_on] Turning eDP port C VDD on
>[   43.084166] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
>[   43.160830] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   43.161533] [drm:intel_dp_start_link_train] clock recovery OK
>[   43.162484] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[   43.162719] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[   43.162728] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=8, cursor=0, SR: plane=0, cursor=0
>[   43.171905] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[   43.171928] [drm:intel_edp_backlight_on] 
>[   43.171936] [drm:intel_panel_enable_backlight] pipe A
>[   43.171945] [drm:intel_panel_actually_set_backlight] set backlight PWM = 7812
>[   43.171959] [drm:intel_psr_match_conditions] PSR disable by flag
>[   43.171987] [drm:intel_connector_check_state] [CONNECTOR:41:eDP-1]
>[   43.172000] [drm:intel_connector_check_state] [CONNECTOR:39:DP-1]
>[   43.172015] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[   43.172026] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[   43.172034] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[   43.172039] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[   43.172047] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[   43.172052] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[   43.172058] [drm:check_crtc_state] [CRTC:20]
>[   43.179846] [drm:check_crtc_state] [CRTC:25]
>[   43.187916] [drm:check_crtc_state] [CRTC:30]
>[   45.671153] [drm:edp_panel_vdd_off_sync] Turning eDP port C VDD off
>[   45.671170] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0007
>[   48.198541] [drm:intel_crtc_set_config] [CRTC:20] [NOFB]
>[   48.198572] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=1, fb_changed=0
>[   48.198578] [drm:intel_modeset_stage_output_state] [CONNECTOR:41:eDP-1] to [NOCRTC]
>[   48.198584] [drm:intel_modeset_stage_output_state] [CONNECTOR:41:eDP-1] encoder changed, full mode switch
>[   48.198592] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:25]
>[   48.198596] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[   48.198601] [drm:intel_modeset_stage_output_state] [ENCODER:40:TMDS-40] crtc changed, full mode switch
>[   48.198608] [drm:intel_modeset_stage_output_state] [CRTC:20] disabled, full mode switch
>[   48.198614] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[   48.202022] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[   48.208024] [drm:edp_panel_vdd_on] Turning eDP port C VDD on
>[   48.208041] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f
>[   48.208048] [drm:intel_edp_backlight_off] 
>[   48.409328] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[   48.409580] [drm:edp_panel_off] Turn eDP port C panel power off
>[   48.409589] [drm:wait_panel_off] Wait for panel power off time
>[   48.409598] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000
>[   48.453347] [drm:wait_panel_status] Wait complete
>[   48.459134] [drm:intel_dp_link_down] 
>[   48.534229] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[   48.534241] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=0, cursor=0, SR: plane=0, cursor=0
>[   48.544272] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[   48.544320] [drm:intel_connector_check_state] [CONNECTOR:39:DP-1]
>[   48.544332] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[   48.544338] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[   48.544344] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[   48.544352] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[   48.544357] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[   48.544362] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[   48.544369] [drm:check_crtc_state] [CRTC:20]
>[   48.544376] [drm:check_crtc_state] [CRTC:25]
>[   48.552185] [drm:check_crtc_state] [CRTC:30]
>[   48.561140] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[5] ENCODERS[5]
>[   48.561153] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[5] ENCODERS[5]
>[   48.561163] [drm:drm_mode_getconnector] [CONNECTOR:34:?]
>[   48.561170] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:34:HDMI-A-1]
>[   48.561174] [drm:intel_hdmi_detect] [CONNECTOR:34:HDMI-A-1]
>[   48.561572] [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 r(1)
>[   48.561578] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[   48.561583] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:34:HDMI-A-1] disconnected
>[   48.561592] [drm:drm_mode_getconnector] [CONNECTOR:34:?]
>[   48.561597] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:34:HDMI-A-1]
>[   48.561600] [drm:intel_hdmi_detect] [CONNECTOR:34:HDMI-A-1]
>[   48.561773] [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 r(1)
>[   48.561778] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[   48.561783] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:34:HDMI-A-1] disconnected
>[   48.561798] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[5] ENCODERS[5]
>[   48.561804] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[5] ENCODERS[5]
>[   48.561809] [drm:drm_mode_getconnector] [CONNECTOR:39:?]
>[   48.561815] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:39:DP-1]
>[   48.561825] [drm:intel_dp_detect] [CONNECTOR:39:DP-1]
>[   48.562460] [drm:intel_dp_get_dpcd] DPCD: 11 0a 84 00 01 00 00 00 00 00 00 00 00 00 00
>[   48.570138] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[   48.570362] [drm:drm_edid_to_eld] ELD monitor ASUS PA238
>[   48.570368] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[   48.570453] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:39:DP-1] probed modes :
>[   48.570462] [drm:drm_mode_debug_printmodeline] Modeline 52:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   48.570469] [drm:drm_mode_debug_printmodeline] Modeline 92:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[   48.570475] [drm:drm_mode_debug_printmodeline] Modeline 85:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[   48.570482] [drm:drm_mode_debug_printmodeline] Modeline 100:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[   48.570489] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[   48.570495] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[   48.570502] [drm:drm_mode_debug_printmodeline] Modeline 61:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[   48.570508] [drm:drm_mode_debug_printmodeline] Modeline 70:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[   48.570515] [drm:drm_mode_debug_printmodeline] Modeline 59:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[   48.570521] [drm:drm_mode_debug_printmodeline] Modeline 60:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6
>[   48.570528] [drm:drm_mode_debug_printmodeline] Modeline 57:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[   48.570534] [drm:drm_mode_debug_printmodeline] Modeline 58:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[   48.570541] [drm:drm_mode_debug_printmodeline] Modeline 62:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[   48.570547] [drm:drm_mode_debug_printmodeline] Modeline 54:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[   48.570554] [drm:drm_mode_debug_printmodeline] Modeline 94:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[   48.570560] [drm:drm_mode_debug_printmodeline] Modeline 55:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[   48.570567] [drm:drm_mode_debug_printmodeline] Modeline 90:"1440x576" 50 54000 1440 1464 1592 1728 576 581 586 625 0x40 0xa
>[   48.570573] [drm:drm_mode_debug_printmodeline] Modeline 71:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[   48.570580] [drm:drm_mode_debug_printmodeline] Modeline 72:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[   48.570586] [drm:drm_mode_debug_printmodeline] Modeline 73:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[   48.570593] [drm:drm_mode_debug_printmodeline] Modeline 102:"1440x480" 60 54054 1440 1472 1596 1716 480 489 495 525 0x40 0xa
>[   48.570599] [drm:drm_mode_debug_printmodeline] Modeline 88:"1440x480" 60 54000 1440 1472 1596 1716 480 489 495 525 0x40 0xa
>[   48.570606] [drm:drm_mode_debug_printmodeline] Modeline 74:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[   48.570612] [drm:drm_mode_debug_printmodeline] Modeline 75:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[   48.570619] [drm:drm_mode_debug_printmodeline] Modeline 76:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[   48.570625] [drm:drm_mode_debug_printmodeline] Modeline 63:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[   48.570632] [drm:drm_mode_debug_printmodeline] Modeline 64:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[   48.570638] [drm:drm_mode_debug_printmodeline] Modeline 56:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[   48.570645] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[   48.570651] [drm:drm_mode_debug_printmodeline] Modeline 53:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[   48.570658] [drm:drm_mode_debug_printmodeline] Modeline 65:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[   48.570664] [drm:drm_mode_debug_printmodeline] Modeline 66:"640x480" 73 31500 640 664 704 832 480 489 491 520 0x40 0xa
>[   48.570671] [drm:drm_mode_debug_printmodeline] Modeline 67:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[   48.570677] [drm:drm_mode_debug_printmodeline] Modeline 68:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[   48.570684] [drm:drm_mode_debug_printmodeline] Modeline 77:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[   48.570690] [drm:drm_mode_debug_printmodeline] Modeline 69:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[   48.570705] [drm:drm_mode_getconnector] [CONNECTOR:39:?]
>[   48.570782] [drm:drm_mode_addfb2] [FB:116]
>[   48.878867] [drm:drm_mode_setcrtc] [CRTC:20]
>[   48.878886] [drm:drm_mode_setcrtc] [CONNECTOR:39:DP-1]
>[   48.878894] [drm:intel_crtc_set_config] [CRTC:20] [FB:116] #connectors=1 (x y) (0 0)
>[   48.878902] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
>[   48.878905] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[   48.878912] [drm:drm_mode_debug_printmodeline] Modeline 118:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[   48.878919] [drm:drm_mode_debug_printmodeline] Modeline 118:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   48.878924] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=1, fb_changed=0
>[   48.878930] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:20]
>[   48.878936] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[   48.878940] [drm:intel_modeset_stage_output_state] [ENCODER:38:TMDS-38] crtc changed, full mode switch
>[   48.878947] [drm:intel_modeset_stage_output_state] [CRTC:20] enabled, full mode switch
>[   48.878951] [drm:intel_modeset_stage_output_state] [CRTC:25] disabled, full mode switch
>[   48.878958] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 2
>[   48.878965] [drm:connected_sink_compute_bpp] [CONNECTOR:39:DP-1] checking for sink bpp constrains
>[   48.878972] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[   48.878979] [drm:intel_dp_compute_config] DP link bw 06 lane count 4 clock 162000 bpp 18
>[   48.878983] [drm:intel_dp_compute_config] DP link bw required 267300 available 518400
>[   48.878989] [drm:intel_modeset_pipe_config] plane bpp: 18, pipe bpp: 18, dithering: 0
>[   48.878994] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[   48.878997] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[   48.879000] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 0
>[   48.879005] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   48.879010] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 4325376, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[   48.879015] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   48.879019] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[   48.879022] [drm:intel_dump_pipe_config] requested mode:
>[   48.879028] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   48.879031] [drm:intel_dump_pipe_config] adjusted mode:
>[   48.879037] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   48.879043] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[   48.879047] [drm:intel_dump_pipe_config] port clock: 162000
>[   48.879050] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   48.879055] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   48.879059] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   48.879062] [drm:intel_dump_pipe_config] ips: 0
>[   48.879065] [drm:intel_dump_pipe_config] double wide: 0
>[   48.882314] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[   48.883712] [drm:ilk_audio_codec_disable] Disable audio codec on port B, pipe B
>[   48.901352] [drm:intel_dp_link_down] 
>[   48.926411] [drm:vlv_get_fifo_size] Pipe B primary B FIFO size: 256
>[   48.926421] [drm:valleyview_update_wm] Setting FIFO watermarks - B: plane=0, cursor=0, SR: plane=0, cursor=0
>[   48.936364] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[   49.100415] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   49.176443] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   49.177302] [drm:intel_dp_start_link_train] clock recovery OK
>[   49.254497] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   49.331516] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   49.408548] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   49.485578] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   49.562717] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   49.639676] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   49.716684] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   49.792716] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   49.793584] [drm:intel_dp_start_link_train] clock recovery OK
>[   49.870747] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   49.947728] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   50.024835] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   50.101845] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   50.178879] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   50.255867] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   50.333015] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   50.409985] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   50.410841] [drm:intel_dp_start_link_train] clock recovery OK
>[   50.488014] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   50.565192] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   50.642103] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   50.719113] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   50.796147] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   50.873181] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   50.950293] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   51.027271] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   51.028166] [drm:intel_dp_start_link_train] clock recovery OK
>[   51.105283] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   51.182425] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   51.259423] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   51.336384] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   51.413417] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   51.490451] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   51.567621] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   51.644572] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   51.645427] [drm:intel_dp_start_link_train] clock recovery OK
>[   51.722552] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   51.799609] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   51.876709] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   51.953659] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   52.030689] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   52.107723] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   52.184809] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   52.261883] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   52.262853] [drm:intel_dp_start_link_train] clock recovery OK
>[   52.339826] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   52.416856] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   52.493982] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   52.570943] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   52.647957] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   52.724993] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   52.802028] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   52.879166] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   52.880158] [drm:intel_dp_start_link_train] clock recovery OK
>[   52.880546] [drm:intel_dp_complete_link_train [i915]] *ERROR* failed to train DP, aborting
>[   52.880747] [drm:intel_enable_dp] Enabling DP audio on pipe A
>[   52.880761] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:39:DP-1], [ENCODER:38:TMDS-38]
>[   52.880768] [drm:ilk_audio_codec_enable] Enable audio codec on port B, pipe A, 36 bytes ELD
>[   52.880843] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[   52.880854] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=8, cursor=0, SR: plane=0, cursor=0
>[   52.890016] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[   52.890039] [drm:intel_psr_enable] PSR not supported by this panel
>[   52.890075] [drm:intel_connector_check_state] [CONNECTOR:39:DP-1]
>[   52.890086] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[   52.890096] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[   52.890102] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[   52.890108] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[   52.890113] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[   52.890118] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[   52.890125] [drm:check_crtc_state] [CRTC:20]
>[   52.898030] [drm:check_crtc_state] [CRTC:25]
>[   52.898038] [drm:check_crtc_state] [CRTC:30]
>[   53.283633] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00020000, dig 0x00000000
>[   53.283644] [drm:intel_hpd_irq_handler] digital hpd port B - short
>[   53.283705] [drm:intel_dp_hpd_pulse] got hpd irq on port B - short
>[   53.284564] [drm:intel_dp_get_dpcd] DPCD: 11 0a 84 00 01 00 00 00 00 00 00 00 00 00 00
>[   53.285077] [drm:intel_dp_check_link_status] TMDS-38: channel EQ not ok, retraining
>[   53.361214] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   53.437246] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   53.438089] [drm:intel_dp_start_link_train] clock recovery OK
>[   53.515282] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   53.592316] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   53.669349] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   53.746382] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   53.823416] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   53.900450] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   53.977482] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   54.053516] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   54.054481] [drm:intel_dp_start_link_train] clock recovery OK
>[   54.131550] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   54.208583] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   54.285616] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   54.362651] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   54.439685] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   54.516717] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   54.593752] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   54.669785] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   54.670642] [drm:intel_dp_start_link_train] clock recovery OK
>[   54.747819] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   54.824853] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   54.901886] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   54.978921] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   55.056114] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   55.133068] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   55.210071] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   55.286105] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   55.287030] [drm:intel_dp_start_link_train] clock recovery OK
>[   55.364143] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   55.441252] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   55.518229] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   55.595240] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   55.672274] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   55.749329] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   55.826410] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   55.903375] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   55.904287] [drm:intel_dp_start_link_train] clock recovery OK
>[   55.981413] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   56.058594] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   56.135499] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   56.212513] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   56.213418] [drm:intel_dp_start_link_train] clock recovery OK
>[   56.290630] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   56.367654] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   56.444615] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   56.521643] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   56.598683] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   56.675819] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   56.676714] [drm:intel_dp_start_link_train] clock recovery OK
>[   56.677095] [drm:intel_dp_complete_link_train [i915]] *ERROR* failed to train DP, aborting
>[   57.080463] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00020000, dig 0x00000000
>[   57.080494] [drm:intel_hpd_irq_handler] digital hpd port B - short
>[   57.080547] [drm:intel_dp_hpd_pulse] got hpd irq on port B - short
>[   57.081484] [drm:intel_dp_get_dpcd] DPCD: 11 0a 84 00 01 00 00 00 00 00 00 00 00 00 00
>[   57.082027] [drm:intel_dp_check_link_status] TMDS-38: channel EQ not ok, retraining
>[   57.157923] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   57.234955] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   57.235869] [drm:intel_dp_start_link_train] clock recovery OK
>[   57.313064] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   57.390022] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   57.467056] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   57.544090] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   57.621258] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   57.698207] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   57.775195] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   57.852226] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   57.853132] [drm:intel_dp_start_link_train] clock recovery OK
>[   57.908693] [drm:drm_mode_addfb2] [FB:118]
>[   57.930334] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   58.007293] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   58.084323] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   58.161357] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   58.238491] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   58.315510] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   58.392412] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   58.468441] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   58.469308] [drm:intel_dp_start_link_train] clock recovery OK
>[   58.546529] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   58.623682] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   58.700635] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   58.777632] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   58.854660] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   58.931693] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   59.008850] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   59.085823] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   59.086733] [drm:intel_dp_start_link_train] clock recovery OK
>[   59.163797] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   59.240863] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   59.317938] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   59.394900] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   59.471928] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   59.548963] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   59.626061] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   59.703123] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   59.703993] [drm:intel_dp_start_link_train] clock recovery OK
>[   59.781070] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   59.858096] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   59.935238] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   60.012196] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   60.089198] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   60.166231] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   60.243268] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   60.320372] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   60.321289] [drm:intel_dp_start_link_train] clock recovery OK
>[   60.398338] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   60.475366] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   60.552528] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   60.629483] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   60.706466] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   60.783499] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   60.860537] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   60.937736] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   60.938676] [drm:intel_dp_start_link_train] clock recovery OK
>[   60.939068] [drm:intel_dp_complete_link_train [i915]] *ERROR* failed to train DP, aborting
>[   60.939292] [drm:drm_mode_setcrtc] [CRTC:20]
>[   60.939306] [drm:drm_mode_setcrtc] [CONNECTOR:39:DP-1]
>[   60.939313] [drm:intel_crtc_set_config] [CRTC:20] [FB:118] #connectors=1 (x y) (0 0)
>[   60.939324] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[   60.939332] [drm:drm_mode_debug_printmodeline] Modeline 118:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[   60.939340] [drm:drm_mode_debug_printmodeline] Modeline 119:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[   60.939344] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=1, fb_changed=1
>[   60.939351] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:20]
>[   60.939355] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[   60.939363] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[   60.939370] [drm:connected_sink_compute_bpp] [CONNECTOR:39:DP-1] checking for sink bpp constrains
>[   60.939377] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148352KHz
>[   60.939382] [drm:intel_dp_compute_config] DP link bw 06 lane count 4 clock 162000 bpp 18
>[   60.939386] [drm:intel_dp_compute_config] DP link bw required 267034 available 518400
>[   60.939393] [drm:intel_modeset_pipe_config] plane bpp: 18, pipe bpp: 18, dithering: 0
>[   60.939400] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[   60.939403] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[   60.939407] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 0
>[   60.939413] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   60.939418] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 4321065, gmch_n: 8388608, link_m: 240059, link_n: 262144, tu: 64
>[   60.939423] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   60.939426] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[   60.939429] [drm:intel_dump_pipe_config] requested mode:
>[   60.939436] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[   60.939439] [drm:intel_dump_pipe_config] adjusted mode:
>[   60.939445] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[   60.939451] [drm:intel_dump_crtc_timings] crtc timings: 148352 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x40 flags: 0x5
>[   60.939454] [drm:intel_dump_pipe_config] port clock: 162000
>[   60.939458] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   60.939462] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   60.939468] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   60.939471] [drm:intel_dump_pipe_config] ips: 0
>[   60.939474] [drm:intel_dump_pipe_config] double wide: 0
>[   60.942571] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[   60.956350] [drm:ilk_audio_codec_disable] Disable audio codec on port B, pipe A
>[   60.972734] [drm:intel_dp_link_down] 
>[   60.997617] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[   60.997627] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=0, cursor=0, SR: plane=0, cursor=0
>[   61.007763] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[   61.171674] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   61.247707] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   61.248557] [drm:intel_dp_start_link_train] clock recovery OK
>[   61.325873] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   61.402830] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   61.479804] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   61.481174] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[   61.481358] [drm:intel_enable_dp] Enabling DP audio on pipe A
>[   61.481366] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:39:DP-1], [ENCODER:38:TMDS-38]
>[   61.481371] [drm:ilk_audio_codec_enable] Enable audio codec on port B, pipe A, 36 bytes ELD
>[   61.481454] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[   61.481462] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=8, cursor=0, SR: plane=0, cursor=0
>[   61.490762] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[   61.490783] [drm:intel_psr_enable] PSR not supported by this panel
>[   61.490810] [drm:intel_connector_check_state] [CONNECTOR:39:DP-1]
>[   61.490820] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[   61.490827] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[   61.490832] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[   61.490839] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[   61.490845] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[   61.490850] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[   61.490856] [drm:check_crtc_state] [CRTC:20]
>[   61.498778] [drm:check_crtc_state] [CRTC:25]
>[   61.498786] [drm:check_crtc_state] [CRTC:30]
>[   66.510300] [drm:drm_mode_addfb2] [FB:116]
>[   66.817673] [drm:drm_mode_setcrtc] [CRTC:20]
>[   66.817690] [drm:drm_mode_setcrtc] [CONNECTOR:39:DP-1]
>[   66.817698] [drm:intel_crtc_set_config] [CRTC:20] [FB:116] #connectors=1 (x y) (0 0)
>[   66.817707] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[   66.817715] [drm:drm_mode_debug_printmodeline] Modeline 119:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[   66.817722] [drm:drm_mode_debug_printmodeline] Modeline 119:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[   66.817726] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=1, fb_changed=1
>[   66.817733] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:20]
>[   66.817737] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[   66.817744] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[   66.817751] [drm:connected_sink_compute_bpp] [CONNECTOR:39:DP-1] checking for sink bpp constrains
>[   66.817758] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 74250KHz
>[   66.817764] [drm:intel_dp_compute_config] DP link bw 06 lane count 2 clock 162000 bpp 18
>[   66.817768] [drm:intel_dp_compute_config] DP link bw required 133650 available 259200
>[   66.817777] [drm:intel_modeset_pipe_config] plane bpp: 18, pipe bpp: 18, dithering: 0
>[   66.817781] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[   66.817784] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[   66.817788] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 0
>[   66.817793] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   66.817798] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 2162688, gmch_n: 4194304, link_m: 120149, link_n: 262144, tu: 64
>[   66.817803] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   66.817807] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[   66.817810] [drm:intel_dump_pipe_config] requested mode:
>[   66.817816] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[   66.817819] [drm:intel_dump_pipe_config] adjusted mode:
>[   66.817825] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[   66.817832] [drm:intel_dump_crtc_timings] crtc timings: 74250 1920 2008 2052 2200 1080 1084 1094 1125, type: 0x40 flags: 0x15
>[   66.817835] [drm:intel_dump_pipe_config] port clock: 162000
>[   66.817839] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   66.817843] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   66.817847] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   66.817851] [drm:intel_dump_pipe_config] ips: 0
>[   66.817854] [drm:intel_dump_pipe_config] double wide: 0
>[   66.821132] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[   66.832455] [drm:ilk_audio_codec_disable] Disable audio codec on port B, pipe A
>[   66.850151] [drm:intel_dp_link_down] 
>[   66.875161] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[   66.875171] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=0, cursor=0, SR: plane=0, cursor=0
>[   66.885162] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[   67.049259] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   67.125347] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   67.126232] [drm:intel_dp_start_link_train] clock recovery OK
>[   67.203303] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   67.280351] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   67.357433] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   67.434396] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   67.435859] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[   67.436047] [drm:intel_enable_dp] Enabling DP audio on pipe A
>[   67.436055] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:39:DP-1], [ENCODER:38:TMDS-38]
>[   67.436062] [drm:ilk_audio_codec_enable] Enable audio codec on port B, pipe A, 36 bytes ELD
>[   67.436138] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[   67.436145] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=8, cursor=0, SR: plane=0, cursor=0
>[   67.445357] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[   67.445385] [drm:intel_psr_enable] PSR not supported by this panel
>[   67.445416] [drm:intel_connector_check_state] [CONNECTOR:39:DP-1]
>[   67.445426] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[   67.445438] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[   67.445443] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[   67.445450] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[   67.445456] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[   67.445461] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[   67.445466] [drm:check_crtc_state] [CRTC:20]
>[   67.453374] [drm:check_crtc_state] [CRTC:25]
>[   67.453382] [drm:check_crtc_state] [CRTC:30]
>[   72.464831] [drm:drm_mode_addfb2] [FB:118]
>[   72.775160] [drm:drm_mode_setcrtc] [CRTC:20]
>[   72.775177] [drm:drm_mode_setcrtc] [CONNECTOR:39:DP-1]
>[   72.775184] [drm:intel_crtc_set_config] [CRTC:20] [FB:118] #connectors=1 (x y) (0 0)
>[   72.775192] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[   72.775199] [drm:drm_mode_debug_printmodeline] Modeline 119:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[   72.775205] [drm:drm_mode_debug_printmodeline] Modeline 119:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[   72.775210] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=1, fb_changed=1
>[   72.775216] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:20]
>[   72.775220] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[   72.775226] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[   72.775233] [drm:connected_sink_compute_bpp] [CONNECTOR:39:DP-1] checking for sink bpp constrains
>[   72.775239] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 74176KHz
>[   72.775245] [drm:intel_dp_compute_config] DP link bw 06 lane count 2 clock 162000 bpp 18
>[   72.775249] [drm:intel_dp_compute_config] DP link bw required 133517 available 259200
>[   72.775256] [drm:intel_modeset_pipe_config] plane bpp: 18, pipe bpp: 18, dithering: 0
>[   72.775261] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[   72.775264] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[   72.775268] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 0
>[   72.775273] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   72.775278] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 2160532, gmch_n: 4194304, link_m: 120029, link_n: 262144, tu: 64
>[   72.775283] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   72.775286] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[   72.775289] [drm:intel_dump_pipe_config] requested mode:
>[   72.775296] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[   72.775299] [drm:intel_dump_pipe_config] adjusted mode:
>[   72.775305] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[   72.775311] [drm:intel_dump_crtc_timings] crtc timings: 74176 1920 2008 2052 2200 1080 1084 1094 1125, type: 0x40 flags: 0x15
>[   72.775315] [drm:intel_dump_pipe_config] port clock: 162000
>[   72.775318] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   72.775323] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   72.775328] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   72.775332] [drm:intel_dump_pipe_config] ips: 0
>[   72.775335] [drm:intel_dump_pipe_config] double wide: 0
>[   72.778729] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[   72.781551] [drm:intel_set_cpu_fifo_underrun_reporting [i915]] *ERROR* pipe C underrun
>[   72.781591] [drm:valleyview_pipestat_irq_handler [i915]] *ERROR* CPU pipe C FIFO underrun
>[   72.781650] [drm:ilk_audio_codec_disable] Disable audio codec on port B, pipe A
>[   72.815811] [drm:intel_dp_link_down] 
>[   72.840854] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[   72.840865] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=0, cursor=0, SR: plane=0, cursor=0
>[   72.850832] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[   73.014832] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   73.090860] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   73.091736] [drm:intel_dp_start_link_train] clock recovery OK
>[   73.168991] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   73.245949] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   73.322961] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   73.399995] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   73.401325] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[   73.401509] [drm:intel_enable_dp] Enabling DP audio on pipe A
>[   73.401518] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:39:DP-1], [ENCODER:38:TMDS-38]
>[   73.401525] [drm:ilk_audio_codec_enable] Enable audio codec on port B, pipe A, 36 bytes ELD
>[   73.401600] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[   73.401608] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=8, cursor=0, SR: plane=0, cursor=0
>[   73.410953] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[   73.410979] [drm:intel_psr_enable] PSR not supported by this panel
>[   73.411011] [drm:intel_connector_check_state] [CONNECTOR:39:DP-1]
>[   73.411021] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[   73.411032] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[   73.411038] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[   73.411044] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[   73.411050] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[   73.411056] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[   73.411061] [drm:check_crtc_state] [CRTC:20]
>[   73.418968] [drm:check_crtc_state] [CRTC:25]
>[   73.418976] [drm:check_crtc_state] [CRTC:30]
>[   78.430635] [drm:drm_mode_addfb2] [FB:116]
>[   78.740886] [drm:drm_mode_setcrtc] [CRTC:20]
>[   78.740902] [drm:drm_mode_setcrtc] [CONNECTOR:39:DP-1]
>[   78.740910] [drm:intel_crtc_set_config] [CRTC:20] [FB:116] #connectors=1 (x y) (0 0)
>[   78.740920] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[   78.740928] [drm:drm_mode_debug_printmodeline] Modeline 119:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[   78.740936] [drm:drm_mode_debug_printmodeline] Modeline 119:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[   78.740941] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=1, fb_changed=1
>[   78.740947] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:20]
>[   78.740951] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[   78.740958] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[   78.740965] [drm:connected_sink_compute_bpp] [CONNECTOR:39:DP-1] checking for sink bpp constrains
>[   78.740972] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[   78.740980] [drm:intel_dp_compute_config] DP link bw 06 lane count 4 clock 162000 bpp 18
>[   78.740984] [drm:intel_dp_compute_config] DP link bw required 267300 available 518400
>[   78.740994] [drm:intel_modeset_pipe_config] plane bpp: 18, pipe bpp: 18, dithering: 0
>[   78.741001] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[   78.741004] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[   78.741008] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 0
>[   78.741014] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   78.741019] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 4325376, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[   78.741024] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   78.741028] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[   78.741031] [drm:intel_dump_pipe_config] requested mode:
>[   78.741037] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[   78.741040] [drm:intel_dump_pipe_config] adjusted mode:
>[   78.741046] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[   78.741052] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2448 2492 2640 1080 1084 1089 1125, type: 0x40 flags: 0x5
>[   78.741056] [drm:intel_dump_pipe_config] port clock: 162000
>[   78.741059] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   78.741064] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   78.741069] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   78.741072] [drm:intel_dump_pipe_config] ips: 0
>[   78.741076] [drm:intel_dump_pipe_config] double wide: 0
>[   78.744328] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[   78.752511] [drm:ilk_audio_codec_disable] Disable audio codec on port B, pipe A
>[   78.786420] [drm:intel_dp_link_down] 
>[   78.811382] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[   78.811393] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=0, cursor=0, SR: plane=0, cursor=0
>[   78.821437] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[   78.985434] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   79.061464] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   79.062379] [drm:intel_dp_start_link_train] clock recovery OK
>[   79.139630] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   79.216606] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   79.293567] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   79.370600] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   79.372017] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[   79.372207] [drm:intel_enable_dp] Enabling DP audio on pipe A
>[   79.372214] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:39:DP-1], [ENCODER:38:TMDS-38]
>[   79.372220] [drm:ilk_audio_codec_enable] Enable audio codec on port B, pipe A, 36 bytes ELD
>[   79.372299] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[   79.372308] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=8, cursor=0, SR: plane=0, cursor=0
>[   79.381553] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[   79.381580] [drm:intel_psr_enable] PSR not supported by this panel
>[   79.381612] [drm:intel_connector_check_state] [CONNECTOR:39:DP-1]
>[   79.381622] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[   79.381633] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[   79.381639] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[   79.381646] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[   79.381653] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[   79.381658] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[   79.381664] [drm:check_crtc_state] [CRTC:20]
>[   79.389619] [drm:check_crtc_state] [CRTC:25]
>[   79.389628] [drm:check_crtc_state] [CRTC:30]
>[   84.401273] [drm:drm_mode_addfb2] [FB:118]
>[   84.707262] [drm:drm_mode_setcrtc] [CRTC:20]
>[   84.707279] [drm:drm_mode_setcrtc] [CONNECTOR:39:DP-1]
>[   84.707288] [drm:intel_crtc_set_config] [CRTC:20] [FB:118] #connectors=1 (x y) (0 0)
>[   84.707296] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[   84.707303] [drm:drm_mode_debug_printmodeline] Modeline 119:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[   84.707310] [drm:drm_mode_debug_printmodeline] Modeline 119:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[   84.707314] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=1, fb_changed=1
>[   84.707320] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:20]
>[   84.707324] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[   84.707331] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[   84.707337] [drm:connected_sink_compute_bpp] [CONNECTOR:39:DP-1] checking for sink bpp constrains
>[   84.707344] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 74250KHz
>[   84.707349] [drm:intel_dp_compute_config] DP link bw 06 lane count 2 clock 162000 bpp 18
>[   84.707353] [drm:intel_dp_compute_config] DP link bw required 133650 available 259200
>[   84.707360] [drm:intel_modeset_pipe_config] plane bpp: 18, pipe bpp: 18, dithering: 0
>[   84.707365] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[   84.707368] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[   84.707372] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 0
>[   84.707377] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   84.707382] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 2162688, gmch_n: 4194304, link_m: 120149, link_n: 262144, tu: 64
>[   84.707387] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   84.707391] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[   84.707394] [drm:intel_dump_pipe_config] requested mode:
>[   84.707400] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[   84.707403] [drm:intel_dump_pipe_config] adjusted mode:
>[   84.707409] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[   84.707416] [drm:intel_dump_crtc_timings] crtc timings: 74250 1920 2448 2492 2640 1080 1084 1094 1125, type: 0x40 flags: 0x15
>[   84.707419] [drm:intel_dump_pipe_config] port clock: 162000
>[   84.707423] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[   84.707427] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   84.707431] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   84.707435] [drm:intel_dump_pipe_config] ips: 0
>[   84.707438] [drm:intel_dump_pipe_config] double wide: 0
>[   84.710931] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[   84.724443] [drm:ilk_audio_codec_disable] Disable audio codec on port B, pipe A
>[   84.745018] [drm:intel_dp_link_down] 
>[   84.770068] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[   84.770078] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=0, cursor=0, SR: plane=0, cursor=0
>[   84.780091] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[   84.944031] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   85.021155] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   85.022057] [drm:intel_dp_start_link_train] clock recovery OK
>[   85.099099] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   85.176129] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   85.253166] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   85.330274] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   85.331614] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[   85.331803] [drm:intel_enable_dp] Enabling DP audio on pipe A
>[   85.331811] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:39:DP-1], [ENCODER:38:TMDS-38]
>[   85.331818] [drm:ilk_audio_codec_enable] Enable audio codec on port B, pipe A, 36 bytes ELD
>[   85.331894] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[   85.331902] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=8, cursor=0, SR: plane=0, cursor=0
>[   85.341155] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[   85.341183] [drm:intel_psr_enable] PSR not supported by this panel
>[   85.341217] [drm:intel_connector_check_state] [CONNECTOR:39:DP-1]
>[   85.341228] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[   85.341237] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[   85.341242] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[   85.341249] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[   85.341255] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[   85.341260] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[   85.341267] [drm:check_crtc_state] [CRTC:20]
>[   85.349170] [drm:check_crtc_state] [CRTC:25]
>[   85.349178] [drm:check_crtc_state] [CRTC:30]
>[   90.360624] [drm:drm_mode_addfb2] [FB:116]
>[   90.648218] [drm:drm_mode_setcrtc] [CRTC:20]
>[   90.648235] [drm:drm_mode_setcrtc] [CONNECTOR:39:DP-1]
>[   90.648242] [drm:intel_crtc_set_config] [CRTC:20] [FB:116] #connectors=1 (x y) (0 0)
>[   90.648250] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[   90.648257] [drm:drm_mode_debug_printmodeline] Modeline 119:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[   90.648264] [drm:drm_mode_debug_printmodeline] Modeline 119:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[   90.648268] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=1, fb_changed=1
>[   90.648274] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:20]
>[   90.648278] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[   90.648284] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[   90.648290] [drm:connected_sink_compute_bpp] [CONNECTOR:39:DP-1] checking for sink bpp constrains
>[   90.648297] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 119000KHz
>[   90.648303] [drm:intel_dp_compute_config] DP link bw 06 lane count 2 clock 162000 bpp 18
>[   90.648306] [drm:intel_dp_compute_config] DP link bw required 214200 available 259200
>[   90.648313] [drm:intel_modeset_pipe_config] plane bpp: 18, pipe bpp: 18, dithering: 0
>[   90.648318] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[   90.648321] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[   90.648325] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 0
>[   90.648330] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   90.648335] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 3466126, gmch_n: 4194304, link_m: 192562, link_n: 262144, tu: 64
>[   90.648340] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   90.648344] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[   90.648347] [drm:intel_dump_pipe_config] requested mode:
>[   90.648353] [drm:drm_mode_debug_printmodeline] Modeline 0:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[   90.648356] [drm:intel_dump_pipe_config] adjusted mode:
>[   90.648362] [drm:drm_mode_debug_printmodeline] Modeline 0:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[   90.648391] [drm:intel_dump_crtc_timings] crtc timings: 119000 1680 1728 1760 1840 1050 1053 1059 1080, type: 0x40 flags: 0x9
>[   90.648394] [drm:intel_dump_pipe_config] port clock: 162000
>[   90.648398] [drm:intel_dump_pipe_config] pipe src size: 1680x1050
>[   90.648402] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   90.648407] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   90.648410] [drm:intel_dump_pipe_config] ips: 0
>[   90.648413] [drm:intel_dump_pipe_config] double wide: 0
>[   90.651659] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[   90.664055] [drm:ilk_audio_codec_disable] Disable audio codec on port B, pipe A
>[   90.704545] [drm:intel_dp_link_down] 
>[   90.729555] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[   90.729565] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=0, cursor=0, SR: plane=0, cursor=0
>[   90.739552] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[   90.903640] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   90.979735] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   90.980724] [drm:intel_dp_start_link_train] clock recovery OK
>[   91.057694] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   91.134724] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   91.211849] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   91.288812] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   91.289702] [drm:intel_dp_start_link_train] clock recovery OK
>[   91.366825] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   91.368228] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[   91.368406] [drm:intel_enable_dp] Enabling DP audio on pipe A
>[   91.368415] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:39:DP-1], [ENCODER:38:TMDS-38]
>[   91.368422] [drm:ilk_audio_codec_enable] Enable audio codec on port B, pipe A, 36 bytes ELD
>[   91.368499] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[   91.368507] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=8, cursor=0, SR: plane=0, cursor=0
>[   91.377783] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[   91.377811] [drm:intel_psr_enable] PSR not supported by this panel
>[   91.377843] [drm:intel_connector_check_state] [CONNECTOR:39:DP-1]
>[   91.377853] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[   91.377864] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[   91.377869] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[   91.377876] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[   91.377882] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[   91.377887] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[   91.377895] [drm:check_crtc_state] [CRTC:20]
>[   91.385848] [drm:check_crtc_state] [CRTC:25]
>[   91.385857] [drm:check_crtc_state] [CRTC:30]
>[   96.397484] [drm:drm_mode_addfb2] [FB:118]
>[   96.643445] [drm:drm_mode_setcrtc] [CRTC:20]
>[   96.643463] [drm:drm_mode_setcrtc] [CONNECTOR:39:DP-1]
>[   96.643470] [drm:intel_crtc_set_config] [CRTC:20] [FB:118] #connectors=1 (x y) (0 0)
>[   96.643478] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[   96.643485] [drm:drm_mode_debug_printmodeline] Modeline 119:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[   96.643491] [drm:drm_mode_debug_printmodeline] Modeline 119:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[   96.643496] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=1, fb_changed=1
>[   96.643502] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:20]
>[   96.643506] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[   96.643513] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[   96.643519] [drm:connected_sink_compute_bpp] [CONNECTOR:39:DP-1] checking for sink bpp constrains
>[   96.643526] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 135000KHz
>[   96.643532] [drm:intel_dp_compute_config] DP link bw 06 lane count 2 clock 162000 bpp 18
>[   96.643536] [drm:intel_dp_compute_config] DP link bw required 243000 available 259200
>[   96.643542] [drm:intel_modeset_pipe_config] plane bpp: 18, pipe bpp: 18, dithering: 0
>[   96.643547] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[   96.643550] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[   96.643554] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 0
>[   96.643559] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[   96.643564] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 3932160, gmch_n: 4194304, link_m: 218453, link_n: 262144, tu: 64
>[   96.643569] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[   96.643572] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[   96.643575] [drm:intel_dump_pipe_config] requested mode:
>[   96.643602] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[   96.643605] [drm:intel_dump_pipe_config] adjusted mode:
>[   96.643611] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[   96.643620] [drm:intel_dump_crtc_timings] crtc timings: 135000 1280 1296 1440 1688 1024 1025 1028 1066, type: 0x40 flags: 0x5
>[   96.643623] [drm:intel_dump_pipe_config] port clock: 162000
>[   96.643627] [drm:intel_dump_pipe_config] pipe src size: 1280x1024
>[   96.643631] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[   96.643635] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[   96.643639] [drm:intel_dump_pipe_config] ips: 0
>[   96.643642] [drm:intel_dump_pipe_config] double wide: 0
>[   96.647128] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[   96.657722] [drm:ilk_audio_codec_disable] Disable audio codec on port B, pipe A
>[   96.675142] [drm:intel_dp_link_down] 
>[   96.700157] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[   96.700168] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=0, cursor=0, SR: plane=0, cursor=0
>[   96.710156] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[   96.874300] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   96.951261] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   96.952111] [drm:intel_dp_start_link_train] clock recovery OK
>[   97.029315] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   97.106413] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   97.183357] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   97.260390] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[   97.261814] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[   97.261995] [drm:intel_enable_dp] Enabling DP audio on pipe A
>[   97.262004] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:39:DP-1], [ENCODER:38:TMDS-38]
>[   97.262011] [drm:ilk_audio_codec_enable] Enable audio codec on port B, pipe A, 36 bytes ELD
>[   97.262088] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[   97.262096] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=8, cursor=0, SR: plane=0, cursor=0
>[   97.271350] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[   97.271372] [drm:intel_psr_enable] PSR not supported by this panel
>[   97.271404] [drm:intel_connector_check_state] [CONNECTOR:39:DP-1]
>[   97.271413] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[   97.271424] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[   97.271429] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[   97.271435] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[   97.271442] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[   97.271447] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[   97.271452] [drm:check_crtc_state] [CRTC:20]
>[   97.279417] [drm:check_crtc_state] [CRTC:25]
>[   97.279426] [drm:check_crtc_state] [CRTC:30]
>[  102.290961] [drm:drm_mode_addfb2] [FB:116]
>[  102.538564] [drm:drm_mode_setcrtc] [CRTC:20]
>[  102.538579] [drm:drm_mode_setcrtc] [CONNECTOR:39:DP-1]
>[  102.538587] [drm:intel_crtc_set_config] [CRTC:20] [FB:116] #connectors=1 (x y) (0 0)
>[  102.538596] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[  102.538604] [drm:drm_mode_debug_printmodeline] Modeline 119:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  102.538611] [drm:drm_mode_debug_printmodeline] Modeline 119:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  102.538615] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=1, fb_changed=1
>[  102.538622] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:20]
>[  102.538641] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[  102.538649] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  102.538656] [drm:connected_sink_compute_bpp] [CONNECTOR:39:DP-1] checking for sink bpp constrains
>[  102.538665] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 108000KHz
>[  102.538672] [drm:intel_dp_compute_config] DP link bw 06 lane count 2 clock 162000 bpp 18
>[  102.538676] [drm:intel_dp_compute_config] DP link bw required 194400 available 259200
>[  102.538682] [drm:intel_modeset_pipe_config] plane bpp: 18, pipe bpp: 18, dithering: 0
>[  102.538687] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[  102.538690] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[  102.538693] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 0
>[  102.538699] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  102.538704] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 3145728, gmch_n: 4194304, link_m: 174762, link_n: 262144, tu: 64
>[  102.538709] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  102.538712] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[  102.538715] [drm:intel_dump_pipe_config] requested mode:
>[  102.538722] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  102.538725] [drm:intel_dump_pipe_config] adjusted mode:
>[  102.538731] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  102.538737] [drm:intel_dump_crtc_timings] crtc timings: 108000 1280 1328 1440 1688 1024 1025 1028 1066, type: 0x40 flags: 0x5
>[  102.538741] [drm:intel_dump_pipe_config] port clock: 162000
>[  102.538744] [drm:intel_dump_pipe_config] pipe src size: 1280x1024
>[  102.538749] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  102.538753] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  102.538756] [drm:intel_dump_pipe_config] ips: 0
>[  102.538759] [drm:intel_dump_pipe_config] double wide: 0
>[  102.542744] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  102.552457] [drm:ilk_audio_codec_disable] Disable audio codec on port B, pipe A
>[  102.566714] [drm:intel_dp_link_down] 
>[  102.591724] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[  102.591734] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=0, cursor=0, SR: plane=0, cursor=0
>[  102.601720] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  102.691140] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00020000, dig 0x00000000
>[  102.691151] [drm:intel_hpd_irq_handler] digital hpd port B - short
>[  102.691180] [drm:intel_dp_hpd_pulse] got hpd irq on port B - short
>[  102.765816] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  102.842824] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  102.843748] [drm:intel_dp_start_link_train] clock recovery OK
>[  102.920991] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  102.997969] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  103.074925] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  103.151957] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  103.153392] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[  103.153590] [drm:intel_enable_dp] Enabling DP audio on pipe A
>[  103.153600] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:39:DP-1], [ENCODER:38:TMDS-38]
>[  103.153607] [drm:ilk_audio_codec_enable] Enable audio codec on port B, pipe A, 36 bytes ELD
>[  103.153683] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[  103.153693] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=8, cursor=0, SR: plane=0, cursor=0
>[  103.162918] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  103.162942] [drm:intel_psr_enable] PSR not supported by this panel
>[  103.162975] [drm:intel_connector_check_state] [CONNECTOR:39:DP-1]
>[  103.162986] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[  103.162996] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  103.163001] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  103.163008] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[  103.163014] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[  103.163020] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[  103.163028] [drm:check_crtc_state] [CRTC:20]
>[  103.170935] [drm:check_crtc_state] [CRTC:25]
>[  103.170944] [drm:check_crtc_state] [CRTC:30]
>[  103.179836] [drm:intel_dp_get_dpcd] DPCD: 11 0a 84 00 01 00 00 00 00 00 00 00 00 00 00
>[  108.182236] [drm:drm_mode_addfb2] [FB:118]
>[  108.427289] [drm:drm_mode_setcrtc] [CRTC:20]
>[  108.427305] [drm:drm_mode_setcrtc] [CONNECTOR:39:DP-1]
>[  108.427313] [drm:intel_crtc_set_config] [CRTC:20] [FB:118] #connectors=1 (x y) (0 0)
>[  108.427323] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[  108.427331] [drm:drm_mode_debug_printmodeline] Modeline 119:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  108.427340] [drm:drm_mode_debug_printmodeline] Modeline 119:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6
>[  108.427344] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=1, fb_changed=1
>[  108.427351] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:20]
>[  108.427355] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[  108.427361] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  108.427367] [drm:connected_sink_compute_bpp] [CONNECTOR:39:DP-1] checking for sink bpp constrains
>[  108.427374] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 136750KHz
>[  108.427380] [drm:intel_dp_compute_config] DP link bw 06 lane count 2 clock 162000 bpp 18
>[  108.427384] [drm:intel_dp_compute_config] DP link bw required 246150 available 259200
>[  108.427390] [drm:intel_modeset_pipe_config] plane bpp: 18, pipe bpp: 18, dithering: 0
>[  108.427395] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[  108.427398] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[  108.427402] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 0
>[  108.427407] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  108.427412] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 3983132, gmch_n: 4194304, link_m: 221285, link_n: 262144, tu: 64
>[  108.427417] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  108.427421] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[  108.427424] [drm:intel_dump_pipe_config] requested mode:
>[  108.427430] [drm:drm_mode_debug_printmodeline] Modeline 0:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6
>[  108.427433] [drm:intel_dump_pipe_config] adjusted mode:
>[  108.427439] [drm:drm_mode_debug_printmodeline] Modeline 0:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6
>[  108.427446] [drm:intel_dump_crtc_timings] crtc timings: 136750 1440 1536 1688 1936 900 903 909 942, type: 0x40 flags: 0x6
>[  108.427449] [drm:intel_dump_pipe_config] port clock: 162000
>[  108.427453] [drm:intel_dump_pipe_config] pipe src size: 1440x900
>[  108.427457] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  108.427461] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  108.427465] [drm:intel_dump_pipe_config] ips: 0
>[  108.427468] [drm:intel_dump_pipe_config] double wide: 0
>[  108.431263] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  108.447528] [drm:ilk_audio_codec_disable] Disable audio codec on port B, pipe A
>[  108.465434] [drm:intel_dp_link_down] 
>[  108.490316] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[  108.490326] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=0, cursor=0, SR: plane=0, cursor=0
>[  108.500451] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  108.664361] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  108.740393] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  108.741301] [drm:intel_dp_start_link_train] clock recovery OK
>[  108.818560] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  108.895526] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  108.972499] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  109.049526] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  109.050716] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[  109.050901] [drm:intel_enable_dp] Enabling DP audio on pipe A
>[  109.050912] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:39:DP-1], [ENCODER:38:TMDS-38]
>[  109.050918] [drm:ilk_audio_codec_enable] Enable audio codec on port B, pipe A, 36 bytes ELD
>[  109.051010] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[  109.051019] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=8, cursor=0, SR: plane=0, cursor=0
>[  109.060486] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  109.060511] [drm:intel_psr_enable] PSR not supported by this panel
>[  109.060545] [drm:intel_connector_check_state] [CONNECTOR:39:DP-1]
>[  109.060553] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[  109.060562] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  109.060568] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  109.060574] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[  109.060581] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[  109.060586] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[  109.060591] [drm:check_crtc_state] [CRTC:20]
>[  109.068553] [drm:check_crtc_state] [CRTC:25]
>[  109.068562] [drm:check_crtc_state] [CRTC:30]
>[  114.080071] [drm:drm_mode_addfb2] [FB:116]
>[  114.325642] [drm:drm_mode_setcrtc] [CRTC:20]
>[  114.325659] [drm:drm_mode_setcrtc] [CONNECTOR:39:DP-1]
>[  114.325666] [drm:intel_crtc_set_config] [CRTC:20] [FB:116] #connectors=1 (x y) (0 0)
>[  114.325673] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[  114.325681] [drm:drm_mode_debug_printmodeline] Modeline 119:"1440x900" 75 136750 1440 1536 1688 1936 900 903 909 942 0x40 0x6
>[  114.325687] [drm:drm_mode_debug_printmodeline] Modeline 119:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  114.325692] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=1, fb_changed=1
>[  114.325698] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:20]
>[  114.325702] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[  114.325708] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  114.325714] [drm:connected_sink_compute_bpp] [CONNECTOR:39:DP-1] checking for sink bpp constrains
>[  114.325721] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 88750KHz
>[  114.325727] [drm:intel_dp_compute_config] DP link bw 06 lane count 2 clock 162000 bpp 18
>[  114.325731] [drm:intel_dp_compute_config] DP link bw required 159750 available 259200
>[  114.325737] [drm:intel_modeset_pipe_config] plane bpp: 18, pipe bpp: 18, dithering: 0
>[  114.325741] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[  114.325745] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[  114.325748] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 0
>[  114.325753] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  114.325759] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 2585031, gmch_n: 4194304, link_m: 143612, link_n: 262144, tu: 64
>[  114.325781] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  114.325784] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[  114.325787] [drm:intel_dump_pipe_config] requested mode:
>[  114.325794] [drm:drm_mode_debug_printmodeline] Modeline 0:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  114.325797] [drm:intel_dump_pipe_config] adjusted mode:
>[  114.325803] [drm:drm_mode_debug_printmodeline] Modeline 0:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  114.325810] [drm:intel_dump_crtc_timings] crtc timings: 88750 1440 1488 1520 1600 900 903 909 926, type: 0x40 flags: 0x9
>[  114.325828] [drm:intel_dump_pipe_config] port clock: 162000
>[  114.325846] [drm:intel_dump_pipe_config] pipe src size: 1440x900
>[  114.325863] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  114.325885] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  114.325904] [drm:intel_dump_pipe_config] ips: 0
>[  114.325914] [drm:intel_dump_pipe_config] double wide: 0
>[  114.329835] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  114.331211] [drm:ilk_audio_codec_disable] Disable audio codec on port B, pipe A
>[  114.344841] [drm:intel_dp_link_down] 
>[  114.369882] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[  114.369891] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=0, cursor=0, SR: plane=0, cursor=0
>[  114.379852] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  114.543958] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  114.621032] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  114.621975] [drm:intel_dp_start_link_train] clock recovery OK
>[  114.698987] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  114.776021] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  114.853138] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  114.930109] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  114.931353] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[  114.931557] [drm:intel_enable_dp] Enabling DP audio on pipe A
>[  114.931567] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:39:DP-1], [ENCODER:38:TMDS-38]
>[  114.931573] [drm:ilk_audio_codec_enable] Enable audio codec on port B, pipe A, 36 bytes ELD
>[  114.931649] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[  114.931659] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=8, cursor=0, SR: plane=0, cursor=0
>[  114.941047] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  114.941076] [drm:intel_psr_enable] PSR not supported by this panel
>[  114.941108] [drm:intel_connector_check_state] [CONNECTOR:39:DP-1]
>[  114.941118] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[  114.941130] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  114.941136] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  114.941142] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[  114.941149] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[  114.941154] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[  114.941160] [drm:check_crtc_state] [CRTC:20]
>[  114.949142] [drm:check_crtc_state] [CRTC:25]
>[  114.949151] [drm:check_crtc_state] [CRTC:30]
>[  119.960372] [drm:drm_mode_addfb2] [FB:118]
>[  120.200755] [drm:drm_mode_setcrtc] [CRTC:20]
>[  120.200772] [drm:drm_mode_setcrtc] [CONNECTOR:39:DP-1]
>[  120.200780] [drm:intel_crtc_set_config] [CRTC:20] [FB:118] #connectors=1 (x y) (0 0)
>[  120.200788] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[  120.200796] [drm:drm_mode_debug_printmodeline] Modeline 119:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  120.200804] [drm:drm_mode_debug_printmodeline] Modeline 119:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  120.200809] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=1, fb_changed=1
>[  120.200815] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:20]
>[  120.200821] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[  120.200827] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  120.200834] [drm:connected_sink_compute_bpp] [CONNECTOR:39:DP-1] checking for sink bpp constrains
>[  120.200842] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 108000KHz
>[  120.200849] [drm:intel_dp_compute_config] DP link bw 06 lane count 2 clock 162000 bpp 18
>[  120.200853] [drm:intel_dp_compute_config] DP link bw required 194400 available 259200
>[  120.200863] [drm:intel_modeset_pipe_config] plane bpp: 18, pipe bpp: 18, dithering: 0
>[  120.200869] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[  120.200872] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[  120.200876] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 0
>[  120.200881] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  120.200886] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 3145728, gmch_n: 4194304, link_m: 174762, link_n: 262144, tu: 64
>[  120.200891] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  120.200894] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[  120.200898] [drm:intel_dump_pipe_config] requested mode:
>[  120.200904] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  120.200907] [drm:intel_dump_pipe_config] adjusted mode:
>[  120.200913] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  120.200919] [drm:intel_dump_crtc_timings] crtc timings: 108000 1280 1376 1488 1800 960 961 964 1000, type: 0x40 flags: 0x5
>[  120.200923] [drm:intel_dump_pipe_config] port clock: 162000
>[  120.200927] [drm:intel_dump_pipe_config] pipe src size: 1280x960
>[  120.200931] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  120.200935] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  120.200938] [drm:intel_dump_pipe_config] ips: 0
>[  120.200942] [drm:intel_dump_pipe_config] double wide: 0
>[  120.204387] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  120.219400] [drm:ilk_audio_codec_disable] Disable audio codec on port B, pipe A
>[  120.237406] [drm:intel_dp_link_down] 
>[  120.262425] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[  120.262435] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=0, cursor=0, SR: plane=0, cursor=0
>[  120.272423] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  120.436492] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  120.512540] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  120.513411] [drm:intel_dp_start_link_train] clock recovery OK
>[  120.590555] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  120.667666] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  120.744689] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  120.821654] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  120.822863] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[  120.823052] [drm:intel_enable_dp] Enabling DP audio on pipe A
>[  120.823059] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:39:DP-1], [ENCODER:38:TMDS-38]
>[  120.823066] [drm:ilk_audio_codec_enable] Enable audio codec on port B, pipe A, 36 bytes ELD
>[  120.823162] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[  120.823170] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=8, cursor=0, SR: plane=0, cursor=0
>[  120.832615] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  120.832646] [drm:intel_psr_enable] PSR not supported by this panel
>[  120.832680] [drm:intel_connector_check_state] [CONNECTOR:39:DP-1]
>[  120.832691] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[  120.832702] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  120.832708] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  120.832715] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[  120.832722] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[  120.832727] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[  120.832735] [drm:check_crtc_state] [CRTC:20]
>[  120.840682] [drm:check_crtc_state] [CRTC:25]
>[  120.840692] [drm:check_crtc_state] [CRTC:30]
>[  125.851967] [drm:drm_mode_addfb2] [FB:116]
>[  126.076034] [drm:drm_mode_setcrtc] [CRTC:20]
>[  126.076050] [drm:drm_mode_setcrtc] [CONNECTOR:39:DP-1]
>[  126.076058] [drm:intel_crtc_set_config] [CRTC:20] [FB:116] #connectors=1 (x y) (0 0)
>[  126.076065] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[  126.076074] [drm:drm_mode_debug_printmodeline] Modeline 119:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  126.076081] [drm:drm_mode_debug_printmodeline] Modeline 119:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  126.076086] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=1, fb_changed=1
>[  126.076092] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:20]
>[  126.076096] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[  126.076103] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  126.076109] [drm:connected_sink_compute_bpp] [CONNECTOR:39:DP-1] checking for sink bpp constrains
>[  126.076116] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 108000KHz
>[  126.076121] [drm:intel_dp_compute_config] DP link bw 06 lane count 2 clock 162000 bpp 18
>[  126.076125] [drm:intel_dp_compute_config] DP link bw required 194400 available 259200
>[  126.076131] [drm:intel_modeset_pipe_config] plane bpp: 18, pipe bpp: 18, dithering: 0
>[  126.076136] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[  126.076139] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[  126.076143] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 0
>[  126.076148] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  126.076153] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 3145728, gmch_n: 4194304, link_m: 174762, link_n: 262144, tu: 64
>[  126.076158] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  126.076161] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[  126.076164] [drm:intel_dump_pipe_config] requested mode:
>[  126.076171] [drm:drm_mode_debug_printmodeline] Modeline 0:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  126.076174] [drm:intel_dump_pipe_config] adjusted mode:
>[  126.076180] [drm:drm_mode_debug_printmodeline] Modeline 0:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  126.076186] [drm:intel_dump_crtc_timings] crtc timings: 108000 1152 1216 1344 1600 864 865 868 900, type: 0x40 flags: 0x5
>[  126.076190] [drm:intel_dump_pipe_config] port clock: 162000
>[  126.076193] [drm:intel_dump_pipe_config] pipe src size: 1152x864
>[  126.076198] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  126.076202] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  126.076205] [drm:intel_dump_pipe_config] ips: 0
>[  126.076208] [drm:intel_dump_pipe_config] double wide: 0
>[  126.079949] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  126.085448] [drm:ilk_audio_codec_disable] Disable audio codec on port B, pipe A
>[  126.102966] [drm:intel_dp_link_down] 
>[  126.127979] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[  126.127989] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=0, cursor=0, SR: plane=0, cursor=0
>[  126.137975] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  126.302086] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  126.379082] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  126.380001] [drm:intel_dp_start_link_train] clock recovery OK
>[  126.457232] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  126.534216] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  126.611180] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  126.688212] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  126.689695] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[  126.689895] [drm:intel_enable_dp] Enabling DP audio on pipe A
>[  126.689904] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:39:DP-1], [ENCODER:38:TMDS-38]
>[  126.689911] [drm:ilk_audio_codec_enable] Enable audio codec on port B, pipe A, 36 bytes ELD
>[  126.689987] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[  126.689994] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=8, cursor=0, SR: plane=0, cursor=0
>[  126.699173] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  126.699196] [drm:intel_psr_enable] PSR not supported by this panel
>[  126.699233] [drm:intel_connector_check_state] [CONNECTOR:39:DP-1]
>[  126.699244] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[  126.699254] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  126.699260] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  126.699267] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[  126.699273] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[  126.699278] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[  126.699284] [drm:check_crtc_state] [CRTC:20]
>[  126.707187] [drm:check_crtc_state] [CRTC:25]
>[  126.707195] [drm:check_crtc_state] [CRTC:30]
>[  127.552884] init: plymouth-stop pre-start process (4367) terminated with status 1
>[  131.718506] [drm:drm_mode_addfb2] [FB:118]
>[  131.935816] [drm:drm_mode_setcrtc] [CRTC:20]
>[  131.935833] [drm:drm_mode_setcrtc] [CONNECTOR:39:DP-1]
>[  131.935841] [drm:intel_crtc_set_config] [CRTC:20] [FB:118] #connectors=1 (x y) (0 0)
>[  131.935850] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[  131.935858] [drm:drm_mode_debug_printmodeline] Modeline 119:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  131.935866] [drm:drm_mode_debug_printmodeline] Modeline 119:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  131.935871] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=1, fb_changed=1
>[  131.935877] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:20]
>[  131.935882] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[  131.935888] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  131.935894] [drm:connected_sink_compute_bpp] [CONNECTOR:39:DP-1] checking for sink bpp constrains
>[  131.935901] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 74250KHz
>[  131.935907] [drm:intel_dp_compute_config] DP link bw 06 lane count 2 clock 162000 bpp 18
>[  131.935911] [drm:intel_dp_compute_config] DP link bw required 133650 available 259200
>[  131.935917] [drm:intel_modeset_pipe_config] plane bpp: 18, pipe bpp: 18, dithering: 0
>[  131.935922] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[  131.935925] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[  131.935929] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 0
>[  131.935934] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  131.935939] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 2162688, gmch_n: 4194304, link_m: 120149, link_n: 262144, tu: 64
>[  131.935944] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  131.935947] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[  131.935950] [drm:intel_dump_pipe_config] requested mode:
>[  131.935957] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  131.935960] [drm:intel_dump_pipe_config] adjusted mode:
>[  131.935966] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  131.935973] [drm:intel_dump_crtc_timings] crtc timings: 74250 1280 1390 1430 1650 720 725 730 750, type: 0x40 flags: 0x5
>[  131.935976] [drm:intel_dump_pipe_config] port clock: 162000
>[  131.935980] [drm:intel_dump_pipe_config] pipe src size: 1280x720
>[  131.935984] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  131.935988] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  131.935992] [drm:intel_dump_pipe_config] ips: 0
>[  131.935995] [drm:intel_dump_pipe_config] double wide: 0
>[  131.939501] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  131.942223] [drm:ilk_audio_codec_disable] Disable audio codec on port B, pipe A
>[  131.956508] [drm:intel_dp_link_down] 
>[  131.981528] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[  131.981538] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=0, cursor=0, SR: plane=0, cursor=0
>[  131.991526] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  132.085787] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00020000, dig 0x00000000
>[  132.085817] [drm:intel_hpd_irq_handler] digital hpd port B - short
>[  132.085889] [drm:intel_dp_hpd_pulse] got hpd irq on port B - short
>[  132.155598] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  132.232627] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  132.233517] [drm:intel_dp_start_link_train] clock recovery OK
>[  132.310749] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  132.387699] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  132.464727] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  132.541761] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  132.543184] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[  132.543388] [drm:intel_enable_dp] Enabling DP audio on pipe A
>[  132.543398] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:39:DP-1], [ENCODER:38:TMDS-38]
>[  132.543404] [drm:ilk_audio_codec_enable] Enable audio codec on port B, pipe A, 36 bytes ELD
>[  132.543482] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[  132.543491] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=8, cursor=0, SR: plane=0, cursor=0
>[  132.552720] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  132.552747] [drm:intel_psr_enable] PSR not supported by this panel
>[  132.552782] [drm:intel_connector_check_state] [CONNECTOR:39:DP-1]
>[  132.552792] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[  132.552802] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  132.552807] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  132.552814] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[  132.552821] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[  132.552826] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[  132.552833] [drm:check_crtc_state] [CRTC:20]
>[  132.560737] [drm:check_crtc_state] [CRTC:25]
>[  132.560745] [drm:check_crtc_state] [CRTC:30]
>[  132.569654] [drm:intel_dp_get_dpcd] DPCD: 11 0a 84 00 01 00 00 00 00 00 00 00 00 00 00
>[  137.571869] [drm:drm_mode_addfb2] [FB:116]
>[  137.789973] [drm:drm_mode_setcrtc] [CRTC:20]
>[  137.790003] [drm:drm_mode_setcrtc] [CONNECTOR:39:DP-1]
>[  137.790011] [drm:intel_crtc_set_config] [CRTC:20] [FB:116] #connectors=1 (x y) (0 0)
>[  137.790018] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[  137.790026] [drm:drm_mode_debug_printmodeline] Modeline 119:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  137.790032] [drm:drm_mode_debug_printmodeline] Modeline 119:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  137.790037] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=1, fb_changed=1
>[  137.790042] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:20]
>[  137.790047] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[  137.790066] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  137.790082] [drm:connected_sink_compute_bpp] [CONNECTOR:39:DP-1] checking for sink bpp constrains
>[  137.790089] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 74176KHz
>[  137.790094] [drm:intel_dp_compute_config] DP link bw 06 lane count 2 clock 162000 bpp 18
>[  137.790098] [drm:intel_dp_compute_config] DP link bw required 133517 available 259200
>[  137.790105] [drm:intel_modeset_pipe_config] plane bpp: 18, pipe bpp: 18, dithering: 0
>[  137.790109] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[  137.790113] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[  137.790116] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 0
>[  137.790121] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  137.790127] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 2160532, gmch_n: 4194304, link_m: 120029, link_n: 262144, tu: 64
>[  137.790131] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  137.790135] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[  137.790138] [drm:intel_dump_pipe_config] requested mode:
>[  137.790144] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  137.790148] [drm:intel_dump_pipe_config] adjusted mode:
>[  137.790154] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  137.790161] [drm:intel_dump_crtc_timings] crtc timings: 74176 1280 1390 1430 1650 720 725 730 750, type: 0x40 flags: 0x5
>[  137.790164] [drm:intel_dump_pipe_config] port clock: 162000
>[  137.790168] [drm:intel_dump_pipe_config] pipe src size: 1280x720
>[  137.790172] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  137.790178] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  137.790181] [drm:intel_dump_pipe_config] ips: 0
>[  137.790185] [drm:intel_dump_pipe_config] double wide: 0
>[  137.794195] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  137.805572] [drm:ilk_audio_codec_disable] Disable audio codec on port B, pipe A
>[  137.822069] [drm:intel_dp_link_down] 
>[  137.847084] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[  137.847094] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=0, cursor=0, SR: plane=0, cursor=0
>[  137.857081] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  138.021153] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  138.097203] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  138.098094] [drm:intel_dp_start_link_train] clock recovery OK
>[  138.175221] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  138.252374] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  138.329325] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  138.406321] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  138.407543] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[  138.407743] [drm:intel_enable_dp] Enabling DP audio on pipe A
>[  138.407755] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:39:DP-1], [ENCODER:38:TMDS-38]
>[  138.407762] [drm:ilk_audio_codec_enable] Enable audio codec on port B, pipe A, 36 bytes ELD
>[  138.407838] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[  138.407845] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=8, cursor=0, SR: plane=0, cursor=0
>[  138.417277] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  138.417302] [drm:intel_psr_enable] PSR not supported by this panel
>[  138.417334] [drm:intel_connector_check_state] [CONNECTOR:39:DP-1]
>[  138.417343] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[  138.417351] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  138.417356] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  138.417364] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[  138.417370] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[  138.417376] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[  138.417382] [drm:check_crtc_state] [CRTC:20]
>[  138.425294] [drm:check_crtc_state] [CRTC:25]
>[  138.425303] [drm:check_crtc_state] [CRTC:30]
>[  143.436599] [drm:drm_mode_addfb2] [FB:118]
>[  143.653959] [drm:drm_mode_setcrtc] [CRTC:20]
>[  143.653975] [drm:drm_mode_setcrtc] [CONNECTOR:39:DP-1]
>[  143.653982] [drm:intel_crtc_set_config] [CRTC:20] [FB:118] #connectors=1 (x y) (0 0)
>[  143.653990] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[  143.653998] [drm:drm_mode_debug_printmodeline] Modeline 119:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  143.654004] [drm:drm_mode_debug_printmodeline] Modeline 119:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  143.654009] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=1, fb_changed=1
>[  143.654014] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:20]
>[  143.654019] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[  143.654026] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  143.654032] [drm:connected_sink_compute_bpp] [CONNECTOR:39:DP-1] checking for sink bpp constrains
>[  143.654039] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 74250KHz
>[  143.654044] [drm:intel_dp_compute_config] DP link bw 06 lane count 2 clock 162000 bpp 18
>[  143.654048] [drm:intel_dp_compute_config] DP link bw required 133650 available 259200
>[  143.654054] [drm:intel_modeset_pipe_config] plane bpp: 18, pipe bpp: 18, dithering: 0
>[  143.654059] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[  143.654063] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[  143.654066] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 0
>[  143.654071] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  143.654076] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 2162688, gmch_n: 4194304, link_m: 120149, link_n: 262144, tu: 64
>[  143.654081] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  143.654085] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[  143.654088] [drm:intel_dump_pipe_config] requested mode:
>[  143.654094] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  143.654118] [drm:intel_dump_pipe_config] adjusted mode:
>[  143.654125] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  143.654132] [drm:intel_dump_crtc_timings] crtc timings: 74250 1280 1720 1760 1980 720 725 730 750, type: 0x40 flags: 0x5
>[  143.654136] [drm:intel_dump_pipe_config] port clock: 162000
>[  143.654139] [drm:intel_dump_pipe_config] pipe src size: 1280x720
>[  143.654144] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  143.654148] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  143.654151] [drm:intel_dump_pipe_config] ips: 0
>[  143.654155] [drm:intel_dump_pipe_config] double wide: 0
>[  143.657609] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  143.658611] [drm:ilk_audio_codec_disable] Disable audio codec on port B, pipe A
>[  143.676641] [drm:intel_dp_link_down] 
>[  143.701725] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[  143.701735] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=0, cursor=0, SR: plane=0, cursor=0
>[  143.711653] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  143.875707] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  143.952812] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  143.953708] [drm:intel_dp_start_link_train] clock recovery OK
>[  144.030771] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  144.107807] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  144.184948] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  144.261942] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  144.263173] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[  144.263349] [drm:intel_enable_dp] Enabling DP audio on pipe A
>[  144.263356] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:39:DP-1], [ENCODER:38:TMDS-38]
>[  144.263363] [drm:ilk_audio_codec_enable] Enable audio codec on port B, pipe A, 36 bytes ELD
>[  144.263459] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[  144.263468] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=8, cursor=0, SR: plane=0, cursor=0
>[  144.272828] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  144.272853] [drm:intel_psr_enable] PSR not supported by this panel
>[  144.272888] [drm:intel_connector_check_state] [CONNECTOR:39:DP-1]
>[  144.272898] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[  144.272906] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  144.272912] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  144.272918] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[  144.272923] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[  144.272929] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[  144.272937] [drm:check_crtc_state] [CRTC:20]
>[  144.280844] [drm:check_crtc_state] [CRTC:25]
>[  144.280852] [drm:check_crtc_state] [CRTC:30]
>[  149.291944] [drm:drm_mode_addfb2] [FB:116]
>[  149.503564] [drm:drm_mode_setcrtc] [CRTC:20]
>[  149.503581] [drm:drm_mode_setcrtc] [CONNECTOR:39:DP-1]
>[  149.503589] [drm:intel_crtc_set_config] [CRTC:20] [FB:116] #connectors=1 (x y) (0 0)
>[  149.503599] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[  149.503607] [drm:drm_mode_debug_printmodeline] Modeline 119:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  149.503615] [drm:drm_mode_debug_printmodeline] Modeline 119:"1440x576" 50 54000 1440 1464 1592 1728 576 581 586 625 0x40 0xa
>[  149.503621] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=1, fb_changed=1
>[  149.503627] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:20]
>[  149.503633] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[  149.503639] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  149.503645] [drm:connected_sink_compute_bpp] [CONNECTOR:39:DP-1] checking for sink bpp constrains
>[  149.503654] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 54000KHz
>[  149.503662] [drm:intel_dp_compute_config] DP link bw 06 lane count 1 clock 162000 bpp 18
>[  149.503666] [drm:intel_dp_compute_config] DP link bw required 97200 available 129600
>[  149.503674] [drm:intel_modeset_pipe_config] plane bpp: 18, pipe bpp: 18, dithering: 0
>[  149.503678] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[  149.503682] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[  149.503685] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 0
>[  149.503690] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  149.503696] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 1572864, gmch_n: 2097152, link_m: 87381, link_n: 262144, tu: 64
>[  149.503700] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  149.503704] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[  149.503707] [drm:intel_dump_pipe_config] requested mode:
>[  149.503713] [drm:drm_mode_debug_printmodeline] Modeline 0:"1440x576" 50 54000 1440 1464 1592 1728 576 581 586 625 0x40 0xa
>[  149.503717] [drm:intel_dump_pipe_config] adjusted mode:
>[  149.503723] [drm:drm_mode_debug_printmodeline] Modeline 0:"1440x576" 50 54000 1440 1464 1592 1728 576 581 586 625 0x40 0xa
>[  149.503729] [drm:intel_dump_crtc_timings] crtc timings: 54000 1440 1464 1592 1728 576 581 586 625, type: 0x40 flags: 0xa
>[  149.503733] [drm:intel_dump_pipe_config] port clock: 162000
>[  149.503736] [drm:intel_dump_pipe_config] pipe src size: 1440x576
>[  149.503740] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  149.503745] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  149.503748] [drm:intel_dump_pipe_config] ips: 0
>[  149.503751] [drm:intel_dump_pipe_config] double wide: 0
>[  149.507210] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  149.515643] [drm:ilk_audio_codec_disable] Disable audio codec on port B, pipe A
>[  149.537177] [drm:intel_dp_link_down] 
>[  149.562187] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[  149.562198] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=0, cursor=0, SR: plane=0, cursor=0
>[  149.572186] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  149.736330] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  149.813291] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  149.814202] [drm:intel_dp_start_link_train] clock recovery OK
>[  149.891366] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  149.968436] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  150.045389] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  150.122424] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  150.123888] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[  150.124077] [drm:intel_enable_dp] Enabling DP audio on pipe A
>[  150.124084] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:39:DP-1], [ENCODER:38:TMDS-38]
>[  150.124091] [drm:ilk_audio_codec_enable] Enable audio codec on port B, pipe A, 36 bytes ELD
>[  150.124169] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[  150.124177] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=8, cursor=0, SR: plane=0, cursor=0
>[  150.133381] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  150.133403] [drm:intel_psr_enable] PSR not supported by this panel
>[  150.133439] [drm:intel_connector_check_state] [CONNECTOR:39:DP-1]
>[  150.133448] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[  150.133458] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  150.133464] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  150.133470] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[  150.133477] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[  150.133482] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[  150.133487] [drm:check_crtc_state] [CRTC:20]
>[  150.141395] [drm:check_crtc_state] [CRTC:25]
>[  150.141404] [drm:check_crtc_state] [CRTC:30]
>[  155.152583] [drm:drm_mode_addfb2] [FB:118]
>[  155.360908] [drm:drm_mode_setcrtc] [CRTC:20]
>[  155.360923] [drm:drm_mode_setcrtc] [CONNECTOR:39:DP-1]
>[  155.360930] [drm:intel_crtc_set_config] [CRTC:20] [FB:118] #connectors=1 (x y) (0 0)
>[  155.360937] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[  155.360945] [drm:drm_mode_debug_printmodeline] Modeline 119:"1440x576" 50 54000 1440 1464 1592 1728 576 581 586 625 0x40 0xa
>[  155.360951] [drm:drm_mode_debug_printmodeline] Modeline 119:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  155.360956] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=1, fb_changed=1
>[  155.360962] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:20]
>[  155.360966] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[  155.360973] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  155.360979] [drm:connected_sink_compute_bpp] [CONNECTOR:39:DP-1] checking for sink bpp constrains
>[  155.360986] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 78800KHz
>[  155.360991] [drm:intel_dp_compute_config] DP link bw 06 lane count 2 clock 162000 bpp 18
>[  155.360995] [drm:intel_dp_compute_config] DP link bw required 141840 available 259200
>[  155.361001] [drm:intel_modeset_pipe_config] plane bpp: 18, pipe bpp: 18, dithering: 0
>[  155.361006] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[  155.361010] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[  155.361013] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 0
>[  155.361018] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  155.361023] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 2295216, gmch_n: 4194304, link_m: 127512, link_n: 262144, tu: 64
>[  155.361028] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  155.361032] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[  155.361035] [drm:intel_dump_pipe_config] requested mode:
>[  155.361041] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  155.361044] [drm:intel_dump_pipe_config] adjusted mode:
>[  155.361051] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  155.361058] [drm:intel_dump_crtc_timings] crtc timings: 78800 1024 1040 1136 1312 768 769 772 800, type: 0x40 flags: 0x5
>[  155.361062] [drm:intel_dump_pipe_config] port clock: 162000
>[  155.361065] [drm:intel_dump_pipe_config] pipe src size: 1024x768
>[  155.361071] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  155.361075] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  155.361078] [drm:intel_dump_pipe_config] ips: 0
>[  155.361082] [drm:intel_dump_pipe_config] double wide: 0
>[  155.364708] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  155.376336] [drm:ilk_audio_codec_disable] Disable audio codec on port B, pipe A
>[  155.397853] [drm:intel_dp_link_down] 
>[  155.422741] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[  155.422751] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=0, cursor=0, SR: plane=0, cursor=0
>[  155.432873] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  155.596812] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  155.672840] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  155.673689] [drm:intel_dp_start_link_train] clock recovery OK
>[  155.750984] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  155.827989] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  155.904940] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  155.981975] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  155.983438] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[  155.983624] [drm:intel_enable_dp] Enabling DP audio on pipe A
>[  155.983633] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:39:DP-1], [ENCODER:38:TMDS-38]
>[  155.983639] [drm:ilk_audio_codec_enable] Enable audio codec on port B, pipe A, 36 bytes ELD
>[  155.983714] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[  155.983722] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=8, cursor=0, SR: plane=0, cursor=0
>[  155.992942] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  155.992975] [drm:intel_psr_enable] PSR not supported by this panel
>[  155.993009] [drm:intel_connector_check_state] [CONNECTOR:39:DP-1]
>[  155.993019] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[  155.993030] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  155.993036] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  155.993043] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[  155.993049] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[  155.993054] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[  155.993060] [drm:check_crtc_state] [CRTC:20]
>[  156.000953] [drm:check_crtc_state] [CRTC:25]
>[  156.000962] [drm:check_crtc_state] [CRTC:30]
>[  161.012001] [drm:drm_mode_addfb2] [FB:116]
>[  161.219655] [drm:drm_mode_setcrtc] [CRTC:20]
>[  161.219671] [drm:drm_mode_setcrtc] [CONNECTOR:39:DP-1]
>[  161.219678] [drm:intel_crtc_set_config] [CRTC:20] [FB:116] #connectors=1 (x y) (0 0)
>[  161.219686] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[  161.219693] [drm:drm_mode_debug_printmodeline] Modeline 119:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  161.219700] [drm:drm_mode_debug_printmodeline] Modeline 119:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  161.219704] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=1, fb_changed=1
>[  161.219710] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:20]
>[  161.219714] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[  161.219721] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  161.219727] [drm:connected_sink_compute_bpp] [CONNECTOR:39:DP-1] checking for sink bpp constrains
>[  161.219734] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 75000KHz
>[  161.219741] [drm:intel_dp_compute_config] DP link bw 06 lane count 2 clock 162000 bpp 18
>[  161.219745] [drm:intel_dp_compute_config] DP link bw required 135000 available 259200
>[  161.219751] [drm:intel_modeset_pipe_config] plane bpp: 18, pipe bpp: 18, dithering: 0
>[  161.219756] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[  161.219760] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[  161.219763] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 0
>[  161.219768] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  161.219774] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 2184533, gmch_n: 4194304, link_m: 121362, link_n: 262144, tu: 64
>[  161.219778] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  161.219782] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[  161.219785] [drm:intel_dump_pipe_config] requested mode:
>[  161.219791] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  161.219813] [drm:intel_dump_pipe_config] adjusted mode:
>[  161.219820] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  161.219829] [drm:intel_dump_crtc_timings] crtc timings: 75000 1024 1048 1184 1328 768 771 777 806, type: 0x40 flags: 0xa
>[  161.219832] [drm:intel_dump_pipe_config] port clock: 162000
>[  161.219836] [drm:intel_dump_pipe_config] pipe src size: 1024x768
>[  161.219840] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  161.219844] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  161.219848] [drm:intel_dump_pipe_config] ips: 0
>[  161.219851] [drm:intel_dump_pipe_config] double wide: 0
>[  161.223263] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  161.230473] [drm:ilk_audio_codec_disable] Disable audio codec on port B, pipe A
>[  161.244390] [drm:intel_dp_link_down] 
>[  161.269288] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[  161.269298] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=0, cursor=0, SR: plane=0, cursor=0
>[  161.279400] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  161.443359] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  161.519385] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  161.520239] [drm:intel_dp_start_link_train] clock recovery OK
>[  161.597473] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  161.674545] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  161.751486] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  161.828520] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  161.829714] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[  161.829892] [drm:intel_enable_dp] Enabling DP audio on pipe A
>[  161.829903] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:39:DP-1], [ENCODER:38:TMDS-38]
>[  161.829910] [drm:ilk_audio_codec_enable] Enable audio codec on port B, pipe A, 36 bytes ELD
>[  161.830005] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[  161.830014] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=8, cursor=0, SR: plane=0, cursor=0
>[  161.839480] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  161.839507] [drm:intel_psr_enable] PSR not supported by this panel
>[  161.839541] [drm:intel_connector_check_state] [CONNECTOR:39:DP-1]
>[  161.839552] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[  161.839563] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  161.839569] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  161.839575] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[  161.839582] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[  161.839587] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[  161.839593] [drm:check_crtc_state] [CRTC:20]
>[  161.847549] [drm:check_crtc_state] [CRTC:25]
>[  161.847558] [drm:check_crtc_state] [CRTC:30]
>[  166.858548] [drm:drm_mode_addfb2] [FB:118]
>[  167.067326] [drm:drm_mode_setcrtc] [CRTC:20]
>[  167.067344] [drm:drm_mode_setcrtc] [CONNECTOR:39:DP-1]
>[  167.067352] [drm:intel_crtc_set_config] [CRTC:20] [FB:118] #connectors=1 (x y) (0 0)
>[  167.067360] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[  167.067368] [drm:drm_mode_debug_printmodeline] Modeline 119:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  167.067374] [drm:drm_mode_debug_printmodeline] Modeline 119:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  167.067379] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=1, fb_changed=1
>[  167.067384] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:20]
>[  167.067389] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[  167.067395] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  167.067401] [drm:connected_sink_compute_bpp] [CONNECTOR:39:DP-1] checking for sink bpp constrains
>[  167.067408] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 65000KHz
>[  167.067414] [drm:intel_dp_compute_config] DP link bw 06 lane count 1 clock 162000 bpp 18
>[  167.067417] [drm:intel_dp_compute_config] DP link bw required 117000 available 129600
>[  167.067424] [drm:intel_modeset_pipe_config] plane bpp: 18, pipe bpp: 18, dithering: 0
>[  167.067430] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[  167.067433] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[  167.067436] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 0
>[  167.067441] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  167.067446] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 1893262, gmch_n: 2097152, link_m: 105181, link_n: 262144, tu: 64
>[  167.067451] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  167.067455] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[  167.067458] [drm:intel_dump_pipe_config] requested mode:
>[  167.067464] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  167.067467] [drm:intel_dump_pipe_config] adjusted mode:
>[  167.067474] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  167.067481] [drm:intel_dump_crtc_timings] crtc timings: 65000 1024 1048 1184 1344 768 771 777 806, type: 0x40 flags: 0xa
>[  167.067485] [drm:intel_dump_pipe_config] port clock: 162000
>[  167.067488] [drm:intel_dump_pipe_config] pipe src size: 1024x768
>[  167.067493] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  167.067498] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  167.067501] [drm:intel_dump_pipe_config] ips: 0
>[  167.067505] [drm:intel_dump_pipe_config] double wide: 0
>[  167.070810] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  167.080157] [drm:ilk_audio_codec_disable] Disable audio codec on port B, pipe A
>[  167.095820] [drm:intel_dp_link_down] 
>[  167.120883] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[  167.120894] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=0, cursor=0, SR: plane=0, cursor=0
>[  167.130834] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  167.294995] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  167.371952] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  167.372827] [drm:intel_dp_start_link_train] clock recovery OK
>[  167.449970] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  167.527129] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  167.604083] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  167.681070] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  167.682484] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[  167.682686] [drm:intel_enable_dp] Enabling DP audio on pipe A
>[  167.682694] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:39:DP-1], [ENCODER:38:TMDS-38]
>[  167.682700] [drm:ilk_audio_codec_enable] Enable audio codec on port B, pipe A, 36 bytes ELD
>[  167.682773] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[  167.682783] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=8, cursor=0, SR: plane=0, cursor=0
>[  167.692031] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  167.692058] [drm:intel_psr_enable] PSR not supported by this panel
>[  167.692091] [drm:intel_connector_check_state] [CONNECTOR:39:DP-1]
>[  167.692102] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[  167.692113] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  167.692118] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  167.692123] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[  167.692130] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[  167.692135] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[  167.692140] [drm:check_crtc_state] [CRTC:20]
>[  167.700046] [drm:check_crtc_state] [CRTC:25]
>[  167.700055] [drm:check_crtc_state] [CRTC:30]
>[  172.711201] [drm:drm_mode_addfb2] [FB:116]
>[  172.903705] [drm:drm_mode_setcrtc] [CRTC:20]
>[  172.903723] [drm:drm_mode_setcrtc] [CONNECTOR:39:DP-1]
>[  172.903731] [drm:intel_crtc_set_config] [CRTC:20] [FB:116] #connectors=1 (x y) (0 0)
>[  172.903738] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[  172.903746] [drm:drm_mode_debug_printmodeline] Modeline 119:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  172.903753] [drm:drm_mode_debug_printmodeline] Modeline 119:"1440x480" 60 54054 1440 1472 1596 1716 480 489 495 525 0x40 0xa
>[  172.903758] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=1, fb_changed=1
>[  172.903764] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:20]
>[  172.903768] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[  172.903776] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  172.903783] [drm:connected_sink_compute_bpp] [CONNECTOR:39:DP-1] checking for sink bpp constrains
>[  172.903791] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 54054KHz
>[  172.903798] [drm:intel_dp_compute_config] DP link bw 06 lane count 1 clock 162000 bpp 18
>[  172.903802] [drm:intel_dp_compute_config] DP link bw required 97298 available 129600
>[  172.903810] [drm:intel_modeset_pipe_config] plane bpp: 18, pipe bpp: 18, dithering: 0
>[  172.903817] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[  172.903820] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[  172.903824] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 0
>[  172.903830] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  172.903835] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 1574436, gmch_n: 2097152, link_m: 87468, link_n: 262144, tu: 64
>[  172.903840] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  172.903844] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[  172.903847] [drm:intel_dump_pipe_config] requested mode:
>[  172.903853] [drm:drm_mode_debug_printmodeline] Modeline 0:"1440x480" 60 54054 1440 1472 1596 1716 480 489 495 525 0x40 0xa
>[  172.903856] [drm:intel_dump_pipe_config] adjusted mode:
>[  172.903862] [drm:drm_mode_debug_printmodeline] Modeline 0:"1440x480" 60 54054 1440 1472 1596 1716 480 489 495 525 0x40 0xa
>[  172.903870] [drm:intel_dump_crtc_timings] crtc timings: 54054 1440 1472 1596 1716 480 489 495 525, type: 0x40 flags: 0xa
>[  172.903873] [drm:intel_dump_pipe_config] port clock: 162000
>[  172.903877] [drm:intel_dump_pipe_config] pipe src size: 1440x480
>[  172.903881] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  172.903885] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  172.903889] [drm:intel_dump_pipe_config] ips: 0
>[  172.903892] [drm:intel_dump_pipe_config] double wide: 0
>[  172.907355] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  172.911420] [drm:ilk_audio_codec_disable] Disable audio codec on port B, pipe A
>[  172.929363] [drm:intel_dp_link_down] 
>[  172.954393] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[  172.954403] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=0, cursor=0, SR: plane=0, cursor=0
>[  172.964378] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  173.129468] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  173.206483] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  173.207354] [drm:intel_dp_start_link_train] clock recovery OK
>[  173.284622] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  173.361621] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  173.438583] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  173.515613] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  173.516893] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[  173.517090] [drm:intel_enable_dp] Enabling DP audio on pipe A
>[  173.517098] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:39:DP-1], [ENCODER:38:TMDS-38]
>[  173.517104] [drm:ilk_audio_codec_enable] Enable audio codec on port B, pipe A, 36 bytes ELD
>[  173.517179] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[  173.517186] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=8, cursor=0, SR: plane=0, cursor=0
>[  173.526570] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  173.526594] [drm:intel_psr_enable] PSR not supported by this panel
>[  173.526629] [drm:intel_connector_check_state] [CONNECTOR:39:DP-1]
>[  173.526638] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[  173.526649] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  173.526654] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  173.526660] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[  173.526667] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[  173.526672] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[  173.526681] [drm:check_crtc_state] [CRTC:20]
>[  173.534640] [drm:check_crtc_state] [CRTC:25]
>[  173.534649] [drm:check_crtc_state] [CRTC:30]
>[  178.545736] [drm:drm_mode_addfb2] [FB:118]
>[  178.738214] [drm:drm_mode_setcrtc] [CRTC:20]
>[  178.738230] [drm:drm_mode_setcrtc] [CONNECTOR:39:DP-1]
>[  178.738238] [drm:intel_crtc_set_config] [CRTC:20] [FB:118] #connectors=1 (x y) (0 0)
>[  178.738246] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[  178.738255] [drm:drm_mode_debug_printmodeline] Modeline 119:"1440x480" 60 54054 1440 1472 1596 1716 480 489 495 525 0x40 0xa
>[  178.738263] [drm:drm_mode_debug_printmodeline] Modeline 119:"1440x480" 60 54000 1440 1472 1596 1716 480 489 495 525 0x40 0xa
>[  178.738269] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=1, fb_changed=1
>[  178.738275] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:20]
>[  178.738281] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[  178.738288] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  178.738295] [drm:connected_sink_compute_bpp] [CONNECTOR:39:DP-1] checking for sink bpp constrains
>[  178.738302] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 54000KHz
>[  178.738309] [drm:intel_dp_compute_config] DP link bw 06 lane count 1 clock 162000 bpp 18
>[  178.738312] [drm:intel_dp_compute_config] DP link bw required 97200 available 129600
>[  178.738322] [drm:intel_modeset_pipe_config] plane bpp: 18, pipe bpp: 18, dithering: 0
>[  178.738330] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[  178.738333] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[  178.738336] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 0
>[  178.738341] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  178.738347] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 1572864, gmch_n: 2097152, link_m: 87381, link_n: 262144, tu: 64
>[  178.738351] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  178.738355] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[  178.738358] [drm:intel_dump_pipe_config] requested mode:
>[  178.738364] [drm:drm_mode_debug_printmodeline] Modeline 0:"1440x480" 60 54000 1440 1472 1596 1716 480 489 495 525 0x40 0xa
>[  178.738368] [drm:intel_dump_pipe_config] adjusted mode:
>[  178.738374] [drm:drm_mode_debug_printmodeline] Modeline 0:"1440x480" 60 54000 1440 1472 1596 1716 480 489 495 525 0x40 0xa
>[  178.738381] [drm:intel_dump_crtc_timings] crtc timings: 54000 1440 1472 1596 1716 480 489 495 525, type: 0x40 flags: 0xa
>[  178.738384] [drm:intel_dump_pipe_config] port clock: 162000
>[  178.738388] [drm:intel_dump_pipe_config] pipe src size: 1440x480
>[  178.738392] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  178.738396] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  178.738400] [drm:intel_dump_pipe_config] ips: 0
>[  178.738403] [drm:intel_dump_pipe_config] double wide: 0
>[  178.741897] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  178.746121] [drm:ilk_audio_codec_disable] Disable audio codec on port B, pipe A
>[  178.763910] [drm:intel_dp_link_down] 
>[  178.788921] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[  178.788931] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=0, cursor=0, SR: plane=0, cursor=0
>[  178.798920] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  178.963063] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  179.040024] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  179.040878] [drm:intel_dp_start_link_train] clock recovery OK
>[  179.118056] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  179.195164] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  179.272143] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  179.349153] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  179.350468] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[  179.350648] [drm:intel_enable_dp] Enabling DP audio on pipe A
>[  179.350655] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:39:DP-1], [ENCODER:38:TMDS-38]
>[  179.350662] [drm:ilk_audio_codec_enable] Enable audio codec on port B, pipe A, 36 bytes ELD
>[  179.350757] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[  179.350765] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=8, cursor=0, SR: plane=0, cursor=0
>[  179.360115] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  179.360144] [drm:intel_psr_enable] PSR not supported by this panel
>[  179.360176] [drm:intel_connector_check_state] [CONNECTOR:39:DP-1]
>[  179.360186] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[  179.360196] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  179.360202] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  179.360209] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[  179.360215] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[  179.360220] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[  179.360225] [drm:check_crtc_state] [CRTC:20]
>[  179.368130] [drm:check_crtc_state] [CRTC:25]
>[  179.368138] [drm:check_crtc_state] [CRTC:30]
>[  184.379329] [drm:drm_mode_addfb2] [FB:116]
>[  184.563032] [drm:drm_mode_setcrtc] [CRTC:20]
>[  184.563050] [drm:drm_mode_setcrtc] [CONNECTOR:39:DP-1]
>[  184.563058] [drm:intel_crtc_set_config] [CRTC:20] [FB:116] #connectors=1 (x y) (0 0)
>[  184.563067] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[  184.563075] [drm:drm_mode_debug_printmodeline] Modeline 119:"1440x480" 60 54000 1440 1472 1596 1716 480 489 495 525 0x40 0xa
>[  184.563081] [drm:drm_mode_debug_printmodeline] Modeline 119:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[  184.563087] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=1, fb_changed=1
>[  184.563093] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:20]
>[  184.563099] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[  184.563106] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  184.563113] [drm:connected_sink_compute_bpp] [CONNECTOR:39:DP-1] checking for sink bpp constrains
>[  184.563120] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 57284KHz
>[  184.563126] [drm:intel_dp_compute_config] DP link bw 06 lane count 1 clock 162000 bpp 18
>[  184.563130] [drm:intel_dp_compute_config] DP link bw required 103112 available 129600
>[  184.563140] [drm:intel_modeset_pipe_config] plane bpp: 18, pipe bpp: 18, dithering: 0
>[  184.563146] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[  184.563149] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[  184.563153] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 0
>[  184.563159] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  184.563164] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 1668517, gmch_n: 2097152, link_m: 92695, link_n: 262144, tu: 64
>[  184.563169] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  184.563172] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[  184.563175] [drm:intel_dump_pipe_config] requested mode:
>[  184.563182] [drm:drm_mode_debug_printmodeline] Modeline 0:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[  184.563185] [drm:intel_dump_pipe_config] adjusted mode:
>[  184.563191] [drm:drm_mode_debug_printmodeline] Modeline 0:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[  184.563198] [drm:intel_dump_crtc_timings] crtc timings: 57284 832 864 928 1152 624 625 628 667, type: 0x40 flags: 0xa
>[  184.563201] [drm:intel_dump_pipe_config] port clock: 162000
>[  184.563205] [drm:intel_dump_pipe_config] pipe src size: 832x624
>[  184.563209] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  184.563215] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  184.563218] [drm:intel_dump_pipe_config] ips: 0
>[  184.563221] [drm:intel_dump_pipe_config] double wide: 0
>[  184.566432] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  184.567928] [drm:ilk_audio_codec_disable] Disable audio codec on port B, pipe A
>[  184.585442] [drm:intel_dp_link_down] 
>[  184.610457] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[  184.610469] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=0, cursor=0, SR: plane=0, cursor=0
>[  184.620456] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  184.784582] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  184.861560] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  184.862431] [drm:intel_dp_start_link_train] clock recovery OK
>[  184.939660] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  185.016710] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  185.093659] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  185.170694] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  185.171904] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[  185.172093] [drm:intel_enable_dp] Enabling DP audio on pipe A
>[  185.172100] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:39:DP-1], [ENCODER:38:TMDS-38]
>[  185.172107] [drm:ilk_audio_codec_enable] Enable audio codec on port B, pipe A, 36 bytes ELD
>[  185.172180] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[  185.172187] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=8, cursor=0, SR: plane=0, cursor=0
>[  185.181647] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  185.181678] [drm:intel_psr_enable] PSR not supported by this panel
>[  185.181710] [drm:intel_connector_check_state] [CONNECTOR:39:DP-1]
>[  185.181720] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[  185.181728] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  185.181734] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  185.181740] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[  185.181746] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[  185.181751] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[  185.181757] [drm:check_crtc_state] [CRTC:20]
>[  185.189661] [drm:check_crtc_state] [CRTC:25]
>[  185.189669] [drm:check_crtc_state] [CRTC:30]
>[  190.200696] [drm:drm_mode_addfb2] [FB:118]
>[  190.373148] [drm:drm_mode_setcrtc] [CRTC:20]
>[  190.373166] [drm:drm_mode_setcrtc] [CONNECTOR:39:DP-1]
>[  190.373174] [drm:intel_crtc_set_config] [CRTC:20] [FB:118] #connectors=1 (x y) (0 0)
>[  190.373181] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[  190.373190] [drm:drm_mode_debug_printmodeline] Modeline 119:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[  190.373198] [drm:drm_mode_debug_printmodeline] Modeline 119:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  190.373202] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=1, fb_changed=1
>[  190.373209] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:20]
>[  190.373213] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[  190.373220] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  190.373227] [drm:connected_sink_compute_bpp] [CONNECTOR:39:DP-1] checking for sink bpp constrains
>[  190.373234] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 49500KHz
>[  190.373242] [drm:intel_dp_compute_config] DP link bw 06 lane count 1 clock 162000 bpp 18
>[  190.373246] [drm:intel_dp_compute_config] DP link bw required 89100 available 129600
>[  190.373253] [drm:intel_modeset_pipe_config] plane bpp: 18, pipe bpp: 18, dithering: 0
>[  190.373261] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[  190.373264] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[  190.373267] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 0
>[  190.373272] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  190.373278] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 1441792, gmch_n: 2097152, link_m: 80099, link_n: 262144, tu: 64
>[  190.373282] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  190.373286] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[  190.373289] [drm:intel_dump_pipe_config] requested mode:
>[  190.373295] [drm:drm_mode_debug_printmodeline] Modeline 0:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  190.373299] [drm:intel_dump_pipe_config] adjusted mode:
>[  190.373305] [drm:drm_mode_debug_printmodeline] Modeline 0:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  190.373311] [drm:intel_dump_crtc_timings] crtc timings: 49500 800 816 896 1056 600 601 604 625, type: 0x40 flags: 0x5
>[  190.373315] [drm:intel_dump_pipe_config] port clock: 162000
>[  190.373318] [drm:intel_dump_pipe_config] pipe src size: 800x600
>[  190.373323] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  190.373327] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  190.373330] [drm:intel_dump_pipe_config] ips: 0
>[  190.373334] [drm:intel_dump_pipe_config] double wide: 0
>[  190.376964] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  190.388952] [drm:ilk_audio_codec_disable] Disable audio codec on port B, pipe A
>[  190.402979] [drm:intel_dp_link_down] 
>[  190.427991] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[  190.428001] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=0, cursor=0, SR: plane=0, cursor=0
>[  190.437989] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  190.602165] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  190.679122] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  190.679985] [drm:intel_dp_start_link_train] clock recovery OK
>[  190.757125] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  190.834289] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  190.911255] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  190.988225] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  190.989753] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[  190.989937] [drm:intel_enable_dp] Enabling DP audio on pipe A
>[  190.989945] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:39:DP-1], [ENCODER:38:TMDS-38]
>[  190.989952] [drm:ilk_audio_codec_enable] Enable audio codec on port B, pipe A, 36 bytes ELD
>[  190.990030] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[  190.990038] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=8, cursor=0, SR: plane=0, cursor=0
>[  190.999183] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  190.999213] [drm:intel_psr_enable] PSR not supported by this panel
>[  190.999246] [drm:intel_connector_check_state] [CONNECTOR:39:DP-1]
>[  190.999256] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[  190.999268] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  190.999273] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  190.999280] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[  190.999286] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[  190.999291] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[  190.999297] [drm:check_crtc_state] [CRTC:20]
>[  191.007254] [drm:check_crtc_state] [CRTC:25]
>[  191.007263] [drm:check_crtc_state] [CRTC:30]
>[  196.018383] [drm:drm_mode_addfb2] [FB:116]
>[  196.190537] [drm:drm_mode_setcrtc] [CRTC:20]
>[  196.190553] [drm:drm_mode_setcrtc] [CONNECTOR:39:DP-1]
>[  196.190560] [drm:intel_crtc_set_config] [CRTC:20] [FB:116] #connectors=1 (x y) (0 0)
>[  196.190568] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[  196.190575] [drm:drm_mode_debug_printmodeline] Modeline 119:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  196.190582] [drm:drm_mode_debug_printmodeline] Modeline 119:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[  196.190586] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=1, fb_changed=1
>[  196.190592] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:20]
>[  196.190596] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[  196.190603] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  196.190610] [drm:connected_sink_compute_bpp] [CONNECTOR:39:DP-1] checking for sink bpp constrains
>[  196.190616] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 50000KHz
>[  196.190622] [drm:intel_dp_compute_config] DP link bw 06 lane count 1 clock 162000 bpp 18
>[  196.190626] [drm:intel_dp_compute_config] DP link bw required 90000 available 129600
>[  196.190632] [drm:intel_modeset_pipe_config] plane bpp: 18, pipe bpp: 18, dithering: 0
>[  196.190637] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[  196.190640] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[  196.190644] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 0
>[  196.190649] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  196.190654] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 1456355, gmch_n: 2097152, link_m: 80908, link_n: 262144, tu: 64
>[  196.190659] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  196.190663] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[  196.190666] [drm:intel_dump_pipe_config] requested mode:
>[  196.190672] [drm:drm_mode_debug_printmodeline] Modeline 0:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[  196.190696] [drm:intel_dump_pipe_config] adjusted mode:
>[  196.190703] [drm:drm_mode_debug_printmodeline] Modeline 0:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[  196.190711] [drm:intel_dump_crtc_timings] crtc timings: 50000 800 856 976 1040 600 637 643 666, type: 0x40 flags: 0x5
>[  196.190714] [drm:intel_dump_pipe_config] port clock: 162000
>[  196.190718] [drm:intel_dump_pipe_config] pipe src size: 800x600
>[  196.190722] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  196.190726] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  196.190730] [drm:intel_dump_pipe_config] ips: 0
>[  196.190733] [drm:intel_dump_pipe_config] double wide: 0
>[  196.194548] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  196.202187] [drm:ilk_audio_codec_disable] Disable audio codec on port B, pipe A
>[  196.216582] [drm:intel_dp_link_down] 
>[  196.241643] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[  196.241655] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=0, cursor=0, SR: plane=0, cursor=0
>[  196.251594] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  196.415594] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  196.492626] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  196.493516] [drm:intel_dp_start_link_train] clock recovery OK
>[  196.570659] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  196.647690] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  196.724723] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  196.801870] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  196.803119] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[  196.803301] [drm:intel_enable_dp] Enabling DP audio on pipe A
>[  196.803309] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:39:DP-1], [ENCODER:38:TMDS-38]
>[  196.803316] [drm:ilk_audio_codec_enable] Enable audio codec on port B, pipe A, 36 bytes ELD
>[  196.803394] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[  196.803403] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=8, cursor=0, SR: plane=0, cursor=0
>[  196.812719] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  196.812748] [drm:intel_psr_enable] PSR not supported by this panel
>[  196.812783] [drm:intel_connector_check_state] [CONNECTOR:39:DP-1]
>[  196.812794] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[  196.812802] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  196.812808] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  196.812815] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[  196.812822] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[  196.812827] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[  196.812832] [drm:check_crtc_state] [CRTC:20]
>[  196.820733] [drm:check_crtc_state] [CRTC:25]
>[  196.820742] [drm:check_crtc_state] [CRTC:30]
>[  201.831578] [drm:drm_mode_addfb2] [FB:118]
>[  202.004449] [drm:drm_mode_setcrtc] [CRTC:20]
>[  202.004467] [drm:drm_mode_setcrtc] [CONNECTOR:39:DP-1]
>[  202.004475] [drm:intel_crtc_set_config] [CRTC:20] [FB:118] #connectors=1 (x y) (0 0)
>[  202.004484] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[  202.004492] [drm:drm_mode_debug_printmodeline] Modeline 119:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[  202.004500] [drm:drm_mode_debug_printmodeline] Modeline 119:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  202.004504] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=1, fb_changed=1
>[  202.004511] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:20]
>[  202.004516] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[  202.004523] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  202.004530] [drm:connected_sink_compute_bpp] [CONNECTOR:39:DP-1] checking for sink bpp constrains
>[  202.004539] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 40000KHz
>[  202.004546] [drm:intel_dp_compute_config] DP link bw 06 lane count 1 clock 162000 bpp 18
>[  202.004550] [drm:intel_dp_compute_config] DP link bw required 72000 available 129600
>[  202.004560] [drm:intel_modeset_pipe_config] plane bpp: 18, pipe bpp: 18, dithering: 0
>[  202.004567] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[  202.004570] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[  202.004574] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 0
>[  202.004580] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  202.004585] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 1165084, gmch_n: 2097152, link_m: 64726, link_n: 262144, tu: 64
>[  202.004590] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  202.004593] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[  202.004596] [drm:intel_dump_pipe_config] requested mode:
>[  202.004603] [drm:drm_mode_debug_printmodeline] Modeline 0:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  202.004606] [drm:intel_dump_pipe_config] adjusted mode:
>[  202.004612] [drm:drm_mode_debug_printmodeline] Modeline 0:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  202.004619] [drm:intel_dump_crtc_timings] crtc timings: 40000 800 840 968 1056 600 601 605 628, type: 0x40 flags: 0x5
>[  202.004622] [drm:intel_dump_pipe_config] port clock: 162000
>[  202.004626] [drm:intel_dump_pipe_config] pipe src size: 800x600
>[  202.004630] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  202.004634] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  202.004638] [drm:intel_dump_pipe_config] ips: 0
>[  202.004641] [drm:intel_dump_pipe_config] double wide: 0
>[  202.008032] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  202.010329] [drm:ilk_audio_codec_disable] Disable audio codec on port B, pipe A
>[  202.024043] [drm:intel_dp_link_down] 
>[  202.049054] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[  202.049066] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=0, cursor=0, SR: plane=0, cursor=0
>[  202.059054] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  202.223125] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  202.299175] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  202.300119] [drm:intel_dp_start_link_train] clock recovery OK
>[  202.377193] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  202.454328] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  202.531328] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  202.608287] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  202.609488] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[  202.609682] [drm:intel_enable_dp] Enabling DP audio on pipe A
>[  202.609690] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:39:DP-1], [ENCODER:38:TMDS-38]
>[  202.609697] [drm:ilk_audio_codec_enable] Enable audio codec on port B, pipe A, 36 bytes ELD
>[  202.609772] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[  202.609781] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=8, cursor=0, SR: plane=0, cursor=0
>[  202.619249] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  202.619278] [drm:intel_psr_enable] PSR not supported by this panel
>[  202.619310] [drm:intel_connector_check_state] [CONNECTOR:39:DP-1]
>[  202.619321] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[  202.619329] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  202.619335] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  202.619341] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[  202.619348] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[  202.619353] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[  202.619360] [drm:check_crtc_state] [CRTC:20]
>[  202.627315] [drm:check_crtc_state] [CRTC:25]
>[  202.627324] [drm:check_crtc_state] [CRTC:30]
>[  207.638369] [drm:drm_mode_addfb2] [FB:116]
>[  207.811283] [drm:drm_mode_setcrtc] [CRTC:20]
>[  207.811299] [drm:drm_mode_setcrtc] [CONNECTOR:39:DP-1]
>[  207.811306] [drm:intel_crtc_set_config] [CRTC:20] [FB:116] #connectors=1 (x y) (0 0)
>[  207.811314] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[  207.811321] [drm:drm_mode_debug_printmodeline] Modeline 119:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  207.811327] [drm:drm_mode_debug_printmodeline] Modeline 119:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  207.811332] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=1, fb_changed=1
>[  207.811338] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:20]
>[  207.811342] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[  207.811349] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  207.811355] [drm:connected_sink_compute_bpp] [CONNECTOR:39:DP-1] checking for sink bpp constrains
>[  207.811362] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 36000KHz
>[  207.811367] [drm:intel_dp_compute_config] DP link bw 06 lane count 1 clock 162000 bpp 18
>[  207.811371] [drm:intel_dp_compute_config] DP link bw required 64800 available 129600
>[  207.811377] [drm:intel_modeset_pipe_config] plane bpp: 18, pipe bpp: 18, dithering: 0
>[  207.811382] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[  207.811385] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[  207.811389] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 0
>[  207.811394] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  207.811399] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 1048576, gmch_n: 2097152, link_m: 58254, link_n: 262144, tu: 64
>[  207.811404] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  207.811408] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[  207.811411] [drm:intel_dump_pipe_config] requested mode:
>[  207.811436] [drm:drm_mode_debug_printmodeline] Modeline 0:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  207.811439] [drm:intel_dump_pipe_config] adjusted mode:
>[  207.811446] [drm:drm_mode_debug_printmodeline] Modeline 0:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  207.811453] [drm:intel_dump_crtc_timings] crtc timings: 36000 800 824 896 1024 600 601 603 625, type: 0x40 flags: 0x5
>[  207.811457] [drm:intel_dump_pipe_config] port clock: 162000
>[  207.811460] [drm:intel_dump_pipe_config] pipe src size: 800x600
>[  207.811465] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  207.811469] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  207.811472] [drm:intel_dump_pipe_config] ips: 0
>[  207.811475] [drm:intel_dump_pipe_config] double wide: 0
>[  207.815560] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  207.828239] [drm:ilk_audio_codec_disable] Disable audio codec on port B, pipe A
>[  207.844575] [drm:intel_dp_link_down] 
>[  207.869590] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[  207.869601] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=0, cursor=0, SR: plane=0, cursor=0
>[  207.879589] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  208.043740] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  208.120688] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  208.121645] [drm:intel_dp_start_link_train] clock recovery OK
>[  208.198730] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  208.275865] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  208.352820] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  208.429825] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  208.431043] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[  208.431224] [drm:intel_enable_dp] Enabling DP audio on pipe A
>[  208.431233] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:39:DP-1], [ENCODER:38:TMDS-38]
>[  208.431240] [drm:ilk_audio_codec_enable] Enable audio codec on port B, pipe A, 36 bytes ELD
>[  208.431316] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[  208.431324] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=8, cursor=0, SR: plane=0, cursor=0
>[  208.440784] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  208.440813] [drm:intel_psr_enable] PSR not supported by this panel
>[  208.440845] [drm:intel_connector_check_state] [CONNECTOR:39:DP-1]
>[  208.440856] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[  208.440864] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  208.440870] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  208.440876] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[  208.440883] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[  208.440888] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[  208.440896] [drm:check_crtc_state] [CRTC:20]
>[  208.448801] [drm:check_crtc_state] [CRTC:25]
>[  208.448809] [drm:check_crtc_state] [CRTC:30]
>[  213.459721] [drm:drm_mode_addfb2] [FB:118]
>[  213.617155] [drm:drm_mode_setcrtc] [CRTC:20]
>[  213.617172] [drm:drm_mode_setcrtc] [CONNECTOR:39:DP-1]
>[  213.617179] [drm:intel_crtc_set_config] [CRTC:20] [FB:118] #connectors=1 (x y) (0 0)
>[  213.617186] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[  213.617193] [drm:drm_mode_debug_printmodeline] Modeline 119:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  213.617200] [drm:drm_mode_debug_printmodeline] Modeline 119:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  213.617204] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=1, fb_changed=1
>[  213.617210] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:20]
>[  213.617215] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[  213.617221] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  213.617227] [drm:connected_sink_compute_bpp] [CONNECTOR:39:DP-1] checking for sink bpp constrains
>[  213.617234] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 27000KHz
>[  213.617239] [drm:intel_dp_compute_config] DP link bw 06 lane count 1 clock 162000 bpp 18
>[  213.617243] [drm:intel_dp_compute_config] DP link bw required 48600 available 129600
>[  213.617250] [drm:intel_modeset_pipe_config] plane bpp: 18, pipe bpp: 18, dithering: 0
>[  213.617255] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[  213.617258] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[  213.617262] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 0
>[  213.617267] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  213.617272] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 786432, gmch_n: 2097152, link_m: 43690, link_n: 262144, tu: 64
>[  213.617277] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  213.617280] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[  213.617283] [drm:intel_dump_pipe_config] requested mode:
>[  213.617290] [drm:drm_mode_debug_printmodeline] Modeline 0:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  213.617293] [drm:intel_dump_pipe_config] adjusted mode:
>[  213.617299] [drm:drm_mode_debug_printmodeline] Modeline 0:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  213.617305] [drm:intel_dump_crtc_timings] crtc timings: 27000 720 732 796 864 576 581 586 625, type: 0x40 flags: 0xa
>[  213.617309] [drm:intel_dump_pipe_config] port clock: 162000
>[  213.617312] [drm:intel_dump_pipe_config] pipe src size: 720x576
>[  213.617317] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  213.617321] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  213.617324] [drm:intel_dump_pipe_config] ips: 0
>[  213.617328] [drm:intel_dump_pipe_config] double wide: 0
>[  213.621092] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  213.634711] [drm:ilk_audio_codec_disable] Disable audio codec on port B, pipe A
>[  213.653109] [drm:intel_dp_link_down] 
>[  213.678121] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[  213.678132] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=0, cursor=0, SR: plane=0, cursor=0
>[  213.688118] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  213.852268] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  213.929219] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  213.930086] [drm:intel_dp_start_link_train] clock recovery OK
>[  214.007252] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  214.084409] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  214.161348] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  214.238354] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  214.239715] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[  214.239907] [drm:intel_enable_dp] Enabling DP audio on pipe A
>[  214.239915] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:39:DP-1], [ENCODER:38:TMDS-38]
>[  214.239922] [drm:ilk_audio_codec_enable] Enable audio codec on port B, pipe A, 36 bytes ELD
>[  214.239999] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[  214.240007] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=40, cursor=0, SR: plane=0, cursor=0
>[  214.249314] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  214.249344] [drm:intel_psr_enable] PSR not supported by this panel
>[  214.249376] [drm:intel_connector_check_state] [CONNECTOR:39:DP-1]
>[  214.249386] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[  214.249398] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  214.249403] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  214.249410] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[  214.249416] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[  214.249422] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[  214.249430] [drm:check_crtc_state] [CRTC:20]
>[  214.257328] [drm:check_crtc_state] [CRTC:25]
>[  214.257337] [drm:check_crtc_state] [CRTC:30]
>[  219.268194] [drm:drm_mode_addfb2] [FB:116]
>[  219.395822] [drm:drm_mode_setcrtc] [CRTC:20]
>[  219.395838] [drm:drm_mode_setcrtc] [CONNECTOR:39:DP-1]
>[  219.395845] [drm:intel_crtc_set_config] [CRTC:20] [FB:116] #connectors=1 (x y) (0 0)
>[  219.395853] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[  219.395860] [drm:drm_mode_debug_printmodeline] Modeline 119:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  219.395867] [drm:drm_mode_debug_printmodeline] Modeline 119:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  219.395871] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=1, fb_changed=1
>[  219.395877] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:20]
>[  219.395881] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[  219.395887] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  219.395894] [drm:connected_sink_compute_bpp] [CONNECTOR:39:DP-1] checking for sink bpp constrains
>[  219.395901] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 27027KHz
>[  219.395907] [drm:intel_dp_compute_config] DP link bw 06 lane count 1 clock 162000 bpp 18
>[  219.395910] [drm:intel_dp_compute_config] DP link bw required 48649 available 129600
>[  219.395917] [drm:intel_modeset_pipe_config] plane bpp: 18, pipe bpp: 18, dithering: 0
>[  219.395921] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[  219.395925] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[  219.395928] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 0
>[  219.395933] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  219.395938] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 787218, gmch_n: 2097152, link_m: 43734, link_n: 262144, tu: 64
>[  219.395943] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  219.395947] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[  219.395950] [drm:intel_dump_pipe_config] requested mode:
>[  219.395956] [drm:drm_mode_debug_printmodeline] Modeline 0:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  219.395959] [drm:intel_dump_pipe_config] adjusted mode:
>[  219.395966] [drm:drm_mode_debug_printmodeline] Modeline 0:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  219.395972] [drm:intel_dump_crtc_timings] crtc timings: 27027 720 736 798 858 480 489 495 525, type: 0x40 flags: 0xa
>[  219.395975] [drm:intel_dump_pipe_config] port clock: 162000
>[  219.395979] [drm:intel_dump_pipe_config] pipe src size: 720x480
>[  219.395983] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  219.395987] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  219.395991] [drm:intel_dump_pipe_config] ips: 0
>[  219.395994] [drm:intel_dump_pipe_config] double wide: 0
>[  219.399699] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  219.412331] [drm:ilk_audio_codec_disable] Disable audio codec on port B, pipe A
>[  219.432623] [drm:intel_dp_link_down] 
>[  219.457640] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[  219.457650] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=0, cursor=0, SR: plane=0, cursor=0
>[  219.467638] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  219.631811] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  219.708763] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  219.709699] [drm:intel_dp_start_link_train] clock recovery OK
>[  219.786779] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  219.863938] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  219.940893] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  220.017873] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  220.019373] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[  220.019556] [drm:intel_enable_dp] Enabling DP audio on pipe A
>[  220.019565] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:39:DP-1], [ENCODER:38:TMDS-38]
>[  220.019571] [drm:ilk_audio_codec_enable] Enable audio codec on port B, pipe A, 36 bytes ELD
>[  220.019650] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[  220.019658] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=32, cursor=0, SR: plane=0, cursor=0
>[  220.030829] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  220.030855] [drm:intel_psr_enable] PSR not supported by this panel
>[  220.030888] [drm:intel_connector_check_state] [CONNECTOR:39:DP-1]
>[  220.030898] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[  220.030911] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  220.030917] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  220.030923] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[  220.030929] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[  220.030935] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[  220.030940] [drm:check_crtc_state] [CRTC:20]
>[  220.039026] [drm:check_crtc_state] [CRTC:25]
>[  220.039035] [drm:check_crtc_state] [CRTC:30]
>[  225.049742] [drm:drm_mode_addfb2] [FB:118]
>[  225.177338] [drm:drm_mode_setcrtc] [CRTC:20]
>[  225.177356] [drm:drm_mode_setcrtc] [CONNECTOR:39:DP-1]
>[  225.177363] [drm:intel_crtc_set_config] [CRTC:20] [FB:118] #connectors=1 (x y) (0 0)
>[  225.177371] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[  225.177378] [drm:drm_mode_debug_printmodeline] Modeline 119:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  225.177384] [drm:drm_mode_debug_printmodeline] Modeline 119:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  225.177389] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=1, fb_changed=1
>[  225.177394] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:20]
>[  225.177399] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[  225.177405] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  225.177412] [drm:connected_sink_compute_bpp] [CONNECTOR:39:DP-1] checking for sink bpp constrains
>[  225.177418] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 27000KHz
>[  225.177423] [drm:intel_dp_compute_config] DP link bw 06 lane count 1 clock 162000 bpp 18
>[  225.177427] [drm:intel_dp_compute_config] DP link bw required 48600 available 129600
>[  225.177434] [drm:intel_modeset_pipe_config] plane bpp: 18, pipe bpp: 18, dithering: 0
>[  225.177439] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[  225.177442] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[  225.177446] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 0
>[  225.177451] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  225.177456] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 786432, gmch_n: 2097152, link_m: 43690, link_n: 262144, tu: 64
>[  225.177461] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  225.177465] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[  225.177468] [drm:intel_dump_pipe_config] requested mode:
>[  225.177474] [drm:drm_mode_debug_printmodeline] Modeline 0:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  225.177477] [drm:intel_dump_pipe_config] adjusted mode:
>[  225.177483] [drm:drm_mode_debug_printmodeline] Modeline 0:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  225.177490] [drm:intel_dump_crtc_timings] crtc timings: 27000 720 736 798 858 480 489 495 525, type: 0x40 flags: 0xa
>[  225.177493] [drm:intel_dump_pipe_config] port clock: 162000
>[  225.177497] [drm:intel_dump_pipe_config] pipe src size: 720x480
>[  225.177501] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  225.177506] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  225.177509] [drm:intel_dump_pipe_config] ips: 0
>[  225.177512] [drm:intel_dump_pipe_config] double wide: 0
>[  225.181125] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  225.183994] [drm:ilk_audio_codec_disable] Disable audio codec on port B, pipe A
>[  225.200133] [drm:intel_dp_link_down] 
>[  225.225151] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[  225.225161] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=0, cursor=0, SR: plane=0, cursor=0
>[  225.235149] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  225.399271] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  225.476253] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  225.477101] [drm:intel_dp_start_link_train] clock recovery OK
>[  225.554304] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  225.631411] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  225.708351] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  225.785384] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  225.786823] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[  225.787006] [drm:intel_enable_dp] Enabling DP audio on pipe A
>[  225.787013] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:39:DP-1], [ENCODER:38:TMDS-38]
>[  225.787020] [drm:ilk_audio_codec_enable] Enable audio codec on port B, pipe A, 36 bytes ELD
>[  225.787098] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[  225.787106] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=40, cursor=0, SR: plane=0, cursor=0
>[  225.796344] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  225.796368] [drm:intel_psr_enable] PSR not supported by this panel
>[  225.796403] [drm:intel_connector_check_state] [CONNECTOR:39:DP-1]
>[  225.796413] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[  225.796421] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  225.796426] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  225.796433] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[  225.796439] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[  225.796444] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[  225.796450] [drm:check_crtc_state] [CRTC:20]
>[  225.804408] [drm:check_crtc_state] [CRTC:25]
>[  225.804418] [drm:check_crtc_state] [CRTC:30]
>[  230.815370] [drm:drm_mode_addfb2] [FB:116]
>[  230.936626] [drm:drm_mode_setcrtc] [CRTC:20]
>[  230.936643] [drm:drm_mode_setcrtc] [CONNECTOR:39:DP-1]
>[  230.936651] [drm:intel_crtc_set_config] [CRTC:20] [FB:116] #connectors=1 (x y) (0 0)
>[  230.936661] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[  230.936669] [drm:drm_mode_debug_printmodeline] Modeline 119:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  230.936675] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  230.936681] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=1, fb_changed=1
>[  230.936688] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:20]
>[  230.936693] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[  230.936700] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  230.936707] [drm:connected_sink_compute_bpp] [CONNECTOR:39:DP-1] checking for sink bpp constrains
>[  230.936716] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 31500KHz
>[  230.936724] [drm:intel_dp_compute_config] DP link bw 06 lane count 1 clock 162000 bpp 18
>[  230.936727] [drm:intel_dp_compute_config] DP link bw required 56700 available 129600
>[  230.936735] [drm:intel_modeset_pipe_config] plane bpp: 18, pipe bpp: 18, dithering: 0
>[  230.936741] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[  230.936744] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[  230.936748] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 0
>[  230.936754] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  230.936759] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 917504, gmch_n: 2097152, link_m: 50972, link_n: 262144, tu: 64
>[  230.936764] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  230.936768] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[  230.936771] [drm:intel_dump_pipe_config] requested mode:
>[  230.936777] [drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  230.936780] [drm:intel_dump_pipe_config] adjusted mode:
>[  230.936786] [drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  230.936793] [drm:intel_dump_crtc_timings] crtc timings: 31500 640 656 720 840 480 481 484 500, type: 0x40 flags: 0xa
>[  230.936796] [drm:intel_dump_pipe_config] port clock: 162000
>[  230.936800] [drm:intel_dump_pipe_config] pipe src size: 640x480
>[  230.936804] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  230.936810] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  230.936813] [drm:intel_dump_pipe_config] ips: 0
>[  230.936816] [drm:intel_dump_pipe_config] double wide: 0
>[  230.940659] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  230.954537] [drm:ilk_audio_codec_disable] Disable audio codec on port B, pipe A
>[  230.972652] [drm:intel_dp_link_down] 
>[  230.997616] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[  230.997626] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=0, cursor=0, SR: plane=0, cursor=0
>[  231.007613] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  231.171741] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  231.247764] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  231.248608] [drm:intel_dp_start_link_train] clock recovery OK
>[  231.325823] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  231.402832] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  231.479865] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  231.556914] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  231.558220] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[  231.558399] [drm:intel_enable_dp] Enabling DP audio on pipe A
>[  231.558408] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:39:DP-1], [ENCODER:38:TMDS-38]
>[  231.558414] [drm:ilk_audio_codec_enable] Enable audio codec on port B, pipe A, 36 bytes ELD
>[  231.558493] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[  231.558501] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=8, cursor=0, SR: plane=0, cursor=0
>[  231.567858] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  231.567882] [drm:intel_psr_enable] PSR not supported by this panel
>[  231.567913] [drm:intel_connector_check_state] [CONNECTOR:39:DP-1]
>[  231.567923] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[  231.567936] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  231.567942] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  231.567947] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[  231.567953] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[  231.567959] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[  231.567965] [drm:check_crtc_state] [CRTC:20]
>[  231.575938] [drm:check_crtc_state] [CRTC:25]
>[  231.575947] [drm:check_crtc_state] [CRTC:30]
>[  236.586759] [drm:drm_mode_addfb2] [FB:118]
>[  236.707030] [drm:drm_mode_setcrtc] [CRTC:20]
>[  236.707046] [drm:drm_mode_setcrtc] [CONNECTOR:39:DP-1]
>[  236.707054] [drm:intel_crtc_set_config] [CRTC:20] [FB:118] #connectors=1 (x y) (0 0)
>[  236.707064] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[  236.707073] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  236.707079] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 73 31500 640 664 704 832 480 489 491 520 0x40 0xa
>[  236.707105] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=1, fb_changed=1
>[  236.707110] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:20]
>[  236.707115] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[  236.707121] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  236.707128] [drm:connected_sink_compute_bpp] [CONNECTOR:39:DP-1] checking for sink bpp constrains
>[  236.707135] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 31500KHz
>[  236.707141] [drm:intel_dp_compute_config] DP link bw 06 lane count 1 clock 162000 bpp 18
>[  236.707145] [drm:intel_dp_compute_config] DP link bw required 56700 available 129600
>[  236.707152] [drm:intel_modeset_pipe_config] plane bpp: 18, pipe bpp: 18, dithering: 0
>[  236.707156] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[  236.707159] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[  236.707163] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 0
>[  236.707168] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  236.707173] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 917504, gmch_n: 2097152, link_m: 50972, link_n: 262144, tu: 64
>[  236.707178] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  236.707182] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[  236.707185] [drm:intel_dump_pipe_config] requested mode:
>[  236.707191] [drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 73 31500 640 664 704 832 480 489 491 520 0x40 0xa
>[  236.707194] [drm:intel_dump_pipe_config] adjusted mode:
>[  236.707200] [drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 73 31500 640 664 704 832 480 489 491 520 0x40 0xa
>[  236.707206] [drm:intel_dump_crtc_timings] crtc timings: 31500 640 664 704 832 480 489 491 520, type: 0x40 flags: 0xa
>[  236.707210] [drm:intel_dump_pipe_config] port clock: 162000
>[  236.707214] [drm:intel_dump_pipe_config] pipe src size: 640x480
>[  236.707218] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  236.707222] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  236.707226] [drm:intel_dump_pipe_config] ips: 0
>[  236.707265] [drm:intel_dump_pipe_config] double wide: 0
>[  236.711150] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  236.717410] [drm:ilk_audio_codec_disable] Disable audio codec on port B, pipe A
>[  236.731163] [drm:intel_dp_link_down] 
>[  236.756175] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[  236.756184] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=0, cursor=0, SR: plane=0, cursor=0
>[  236.766173] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  236.930295] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  237.007274] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  237.008185] [drm:intel_dp_start_link_train] clock recovery OK
>[  237.085334] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  237.162427] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  237.239376] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  237.316409] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  237.317944] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[  237.318129] [drm:intel_enable_dp] Enabling DP audio on pipe A
>[  237.318137] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:39:DP-1], [ENCODER:38:TMDS-38]
>[  237.318144] [drm:ilk_audio_codec_enable] Enable audio codec on port B, pipe A, 36 bytes ELD
>[  237.318216] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[  237.318223] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=8, cursor=0, SR: plane=0, cursor=0
>[  237.327372] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  237.327401] [drm:intel_psr_enable] PSR not supported by this panel
>[  237.327436] [drm:intel_connector_check_state] [CONNECTOR:39:DP-1]
>[  237.327446] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[  237.327457] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  237.327463] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  237.327469] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[  237.327476] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[  237.327482] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[  237.327491] [drm:check_crtc_state] [CRTC:20]
>[  237.335381] [drm:check_crtc_state] [CRTC:25]
>[  237.335391] [drm:check_crtc_state] [CRTC:30]
>[  242.346155] [drm:drm_mode_addfb2] [FB:116]
>[  242.466724] [drm:drm_mode_setcrtc] [CRTC:20]
>[  242.466741] [drm:drm_mode_setcrtc] [CONNECTOR:39:DP-1]
>[  242.466749] [drm:intel_crtc_set_config] [CRTC:20] [FB:116] #connectors=1 (x y) (0 0)
>[  242.466758] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[  242.466767] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 73 31500 640 664 704 832 480 489 491 520 0x40 0xa
>[  242.466773] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  242.466779] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=1, fb_changed=1
>[  242.466786] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:20]
>[  242.466791] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[  242.466798] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  242.466805] [drm:connected_sink_compute_bpp] [CONNECTOR:39:DP-1] checking for sink bpp constrains
>[  242.466812] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 30240KHz
>[  242.466818] [drm:intel_dp_compute_config] DP link bw 06 lane count 1 clock 162000 bpp 18
>[  242.466822] [drm:intel_dp_compute_config] DP link bw required 54432 available 129600
>[  242.466829] [drm:intel_modeset_pipe_config] plane bpp: 18, pipe bpp: 18, dithering: 0
>[  242.466837] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[  242.466840] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[  242.466843] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 0
>[  242.466848] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  242.466854] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 880803, gmch_n: 2097152, link_m: 48933, link_n: 262144, tu: 64
>[  242.466858] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  242.466862] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[  242.466865] [drm:intel_dump_pipe_config] requested mode:
>[  242.466871] [drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  242.466874] [drm:intel_dump_pipe_config] adjusted mode:
>[  242.466880] [drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  242.466886] [drm:intel_dump_crtc_timings] crtc timings: 30240 640 704 768 864 480 483 486 525, type: 0x40 flags: 0xa
>[  242.466890] [drm:intel_dump_pipe_config] port clock: 162000
>[  242.466893] [drm:intel_dump_pipe_config] pipe src size: 640x480
>[  242.466898] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  242.466903] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  242.466906] [drm:intel_dump_pipe_config] ips: 0
>[  242.466909] [drm:intel_dump_pipe_config] double wide: 0
>[  242.470754] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  242.481081] [drm:ilk_audio_codec_disable] Disable audio codec on port B, pipe A
>[  242.494671] [drm:intel_dp_link_down] 
>[  242.519686] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[  242.519697] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=0, cursor=0, SR: plane=0, cursor=0
>[  242.529684] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  242.693849] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  242.770804] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  242.771652] [drm:intel_dp_start_link_train] clock recovery OK
>[  242.848821] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  242.925983] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  243.002937] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  243.079921] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  243.081419] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[  243.081599] [drm:intel_enable_dp] Enabling DP audio on pipe A
>[  243.081608] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:39:DP-1], [ENCODER:38:TMDS-38]
>[  243.081615] [drm:ilk_audio_codec_enable] Enable audio codec on port B, pipe A, 36 bytes ELD
>[  243.081691] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[  243.081699] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=8, cursor=0, SR: plane=0, cursor=0
>[  243.090878] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  243.090906] [drm:intel_psr_enable] PSR not supported by this panel
>[  243.090943] [drm:intel_connector_check_state] [CONNECTOR:39:DP-1]
>[  243.090954] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[  243.090964] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  243.090970] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  243.090977] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[  243.090983] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[  243.090988] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[  243.090997] [drm:check_crtc_state] [CRTC:20]
>[  243.098944] [drm:check_crtc_state] [CRTC:25]
>[  243.098953] [drm:check_crtc_state] [CRTC:30]
>[  248.109450] [drm:drm_mode_addfb2] [FB:118]
>[  248.229978] [drm:drm_mode_setcrtc] [CRTC:20]
>[  248.229994] [drm:drm_mode_setcrtc] [CONNECTOR:39:DP-1]
>[  248.230001] [drm:intel_crtc_set_config] [CRTC:20] [FB:118] #connectors=1 (x y) (0 0)
>[  248.230009] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[  248.230016] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  248.230022] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  248.230027] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=1, fb_changed=1
>[  248.230033] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:20]
>[  248.230037] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[  248.230043] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  248.230050] [drm:connected_sink_compute_bpp] [CONNECTOR:39:DP-1] checking for sink bpp constrains
>[  248.230057] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 25200KHz
>[  248.230062] [drm:intel_dp_compute_config] DP link bw 06 lane count 1 clock 162000 bpp 18
>[  248.230066] [drm:intel_dp_compute_config] DP link bw required 45360 available 129600
>[  248.230073] [drm:intel_modeset_pipe_config] plane bpp: 18, pipe bpp: 18, dithering: 0
>[  248.230078] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[  248.230081] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[  248.230085] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 0
>[  248.230089] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  248.230095] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 734003, gmch_n: 2097152, link_m: 40777, link_n: 262144, tu: 64
>[  248.230117] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  248.230121] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[  248.230125] [drm:intel_dump_pipe_config] requested mode:
>[  248.230131] [drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  248.230134] [drm:intel_dump_pipe_config] adjusted mode:
>[  248.230140] [drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  248.230149] [drm:intel_dump_crtc_timings] crtc timings: 25200 640 656 752 800 480 490 492 525, type: 0x40 flags: 0xa
>[  248.230152] [drm:intel_dump_pipe_config] port clock: 162000
>[  248.230156] [drm:intel_dump_pipe_config] pipe src size: 640x480
>[  248.230162] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  248.230166] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  248.230169] [drm:intel_dump_pipe_config] ips: 0
>[  248.230172] [drm:intel_dump_pipe_config] double wide: 0
>[  248.234176] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  248.238849] [drm:ilk_audio_codec_disable] Disable audio codec on port B, pipe A
>[  248.254249] [drm:intel_dp_link_down] 
>[  248.279320] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[  248.279330] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=0, cursor=0, SR: plane=0, cursor=0
>[  248.289269] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  248.453268] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  248.530294] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  248.531196] [drm:intel_dp_start_link_train] clock recovery OK
>[  248.608333] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  248.685362] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  248.762394] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  248.839542] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  248.840715] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[  248.840897] [drm:intel_enable_dp] Enabling DP audio on pipe A
>[  248.840904] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:39:DP-1], [ENCODER:38:TMDS-38]
>[  248.840911] [drm:ilk_audio_codec_enable] Enable audio codec on port B, pipe A, 36 bytes ELD
>[  248.840988] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[  248.840996] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=48, cursor=0, SR: plane=0, cursor=0
>[  248.850390] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  248.850418] [drm:intel_psr_enable] PSR not supported by this panel
>[  248.850454] [drm:intel_connector_check_state] [CONNECTOR:39:DP-1]
>[  248.850464] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[  248.850474] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  248.850480] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  248.850487] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[  248.850493] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[  248.850499] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[  248.850507] [drm:check_crtc_state] [CRTC:20]
>[  248.858592] [drm:check_crtc_state] [CRTC:25]
>[  248.858600] [drm:check_crtc_state] [CRTC:30]
>[  253.869084] [drm:drm_mode_addfb2] [FB:116]
>[  253.990920] [drm:drm_mode_setcrtc] [CRTC:20]
>[  253.990937] [drm:drm_mode_setcrtc] [CONNECTOR:39:DP-1]
>[  253.990945] [drm:intel_crtc_set_config] [CRTC:20] [FB:116] #connectors=1 (x y) (0 0)
>[  253.990954] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[  253.990963] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  253.990971] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  253.990975] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=1, fb_changed=1
>[  253.990981] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:20]
>[  253.990987] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[  253.990994] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  253.991000] [drm:connected_sink_compute_bpp] [CONNECTOR:39:DP-1] checking for sink bpp constrains
>[  253.991008] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 25175KHz
>[  253.991015] [drm:intel_dp_compute_config] DP link bw 06 lane count 1 clock 162000 bpp 18
>[  253.991018] [drm:intel_dp_compute_config] DP link bw required 45315 available 129600
>[  253.991028] [drm:intel_modeset_pipe_config] plane bpp: 18, pipe bpp: 18, dithering: 0
>[  253.991034] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[  253.991038] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[  253.991041] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 0
>[  253.991046] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  253.991051] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 733275, gmch_n: 2097152, link_m: 40737, link_n: 262144, tu: 64
>[  253.991056] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  253.991060] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[  253.991063] [drm:intel_dump_pipe_config] requested mode:
>[  253.991069] [drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  253.991072] [drm:intel_dump_pipe_config] adjusted mode:
>[  253.991078] [drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  253.991084] [drm:intel_dump_crtc_timings] crtc timings: 25175 640 656 752 800 480 490 492 525, type: 0x40 flags: 0xa
>[  253.991088] [drm:intel_dump_pipe_config] port clock: 162000
>[  253.991091] [drm:intel_dump_pipe_config] pipe src size: 640x480
>[  253.991096] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  253.991100] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  253.991103] [drm:intel_dump_pipe_config] ips: 0
>[  253.991107] [drm:intel_dump_pipe_config] double wide: 0
>[  253.994680] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  254.003562] [drm:ilk_audio_codec_disable] Disable audio codec on port B, pipe A
>[  254.021637] [drm:intel_dp_link_down] 
>[  254.046786] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[  254.046796] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=0, cursor=0, SR: plane=0, cursor=0
>[  254.056726] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  254.220780] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  254.296810] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  254.297653] [drm:intel_dp_start_link_train] clock recovery OK
>[  254.374896] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  254.451874] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  254.528907] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  254.605946] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  254.607162] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[  254.607345] [drm:intel_enable_dp] Enabling DP audio on pipe A
>[  254.607354] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:39:DP-1], [ENCODER:38:TMDS-38]
>[  254.607361] [drm:ilk_audio_codec_enable] Enable audio codec on port B, pipe A, 36 bytes ELD
>[  254.607450] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[  254.607458] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=48, cursor=0, SR: plane=0, cursor=0
>[  254.616899] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  254.616928] [drm:intel_psr_enable] PSR not supported by this panel
>[  254.616961] [drm:intel_connector_check_state] [CONNECTOR:39:DP-1]
>[  254.616971] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[  254.616984] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  254.616989] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  254.616996] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[  254.617002] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[  254.617007] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[  254.617014] [drm:check_crtc_state] [CRTC:20]
>[  254.624964] [drm:check_crtc_state] [CRTC:25]
>[  254.624973] [drm:check_crtc_state] [CRTC:30]
>[  259.635577] [drm:drm_mode_addfb2] [FB:118]
>[  259.743964] [drm:drm_mode_setcrtc] [CRTC:20]
>[  259.743981] [drm:drm_mode_setcrtc] [CONNECTOR:39:DP-1]
>[  259.743988] [drm:intel_crtc_set_config] [CRTC:20] [FB:118] #connectors=1 (x y) (0 0)
>[  259.743995] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[  259.744002] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  259.744009] [drm:drm_mode_debug_printmodeline] Modeline 119:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  259.744013] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=1, fb_changed=1
>[  259.744019] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:20]
>[  259.744023] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[  259.744030] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  259.744036] [drm:connected_sink_compute_bpp] [CONNECTOR:39:DP-1] checking for sink bpp constrains
>[  259.744043] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 28320KHz
>[  259.744049] [drm:intel_dp_compute_config] DP link bw 06 lane count 1 clock 162000 bpp 18
>[  259.744052] [drm:intel_dp_compute_config] DP link bw required 50976 available 129600
>[  259.744059] [drm:intel_modeset_pipe_config] plane bpp: 18, pipe bpp: 18, dithering: 0
>[  259.744063] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[  259.744067] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[  259.744070] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 0
>[  259.744075] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  259.744081] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 824879, gmch_n: 2097152, link_m: 45826, link_n: 262144, tu: 64
>[  259.744085] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  259.744089] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[  259.744092] [drm:intel_dump_pipe_config] requested mode:
>[  259.744098] [drm:drm_mode_debug_printmodeline] Modeline 0:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  259.744102] [drm:intel_dump_pipe_config] adjusted mode:
>[  259.744108] [drm:drm_mode_debug_printmodeline] Modeline 0:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  259.744114] [drm:intel_dump_crtc_timings] crtc timings: 28320 720 738 846 900 400 412 414 449, type: 0x40 flags: 0x6
>[  259.744135] [drm:intel_dump_pipe_config] port clock: 162000
>[  259.744139] [drm:intel_dump_pipe_config] pipe src size: 720x400
>[  259.744143] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  259.744147] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  259.744151] [drm:intel_dump_pipe_config] ips: 0
>[  259.744155] [drm:intel_dump_pipe_config] double wide: 0
>[  259.748192] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  259.758169] [drm:ilk_audio_codec_disable] Disable audio codec on port B, pipe A
>[  259.776226] [drm:intel_dp_link_down] 
>[  259.801302] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[  259.801312] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=0, cursor=0, SR: plane=0, cursor=0
>[  259.811237] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  259.975286] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  260.052403] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  260.053299] [drm:intel_dp_start_link_train] clock recovery OK
>[  260.130353] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  260.207388] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  260.284523] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  260.361529] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  260.362818] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[  260.363007] [drm:intel_enable_dp] Enabling DP audio on pipe A
>[  260.363016] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:39:DP-1], [ENCODER:38:TMDS-38]
>[  260.363022] [drm:ilk_audio_codec_enable] Enable audio codec on port B, pipe A, 36 bytes ELD
>[  260.363100] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[  260.363108] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=24, cursor=0, SR: plane=0, cursor=0
>[  260.372410] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  260.372431] [drm:intel_psr_enable] PSR not supported by this panel
>[  260.372463] [drm:intel_connector_check_state] [CONNECTOR:39:DP-1]
>[  260.372474] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[  260.372482] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  260.372488] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  260.372496] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[  260.372502] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[  260.372508] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[  260.372513] [drm:check_crtc_state] [CRTC:20]
>[  260.380556] [drm:check_crtc_state] [CRTC:25]
>[  260.380565] [drm:check_crtc_state] [CRTC:30]
>[  265.391416] [drm:intel_crtc_set_config] [CRTC:20] [NOFB]
>[  265.391432] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=1, fb_changed=0
>[  265.391439] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [NOCRTC]
>[  265.391445] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] encoder changed, full mode switch
>[  265.391452] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[  265.391456] [drm:intel_modeset_stage_output_state] [ENCODER:38:TMDS-38] crtc changed, full mode switch
>[  265.391463] [drm:intel_modeset_stage_output_state] [CRTC:20] disabled, full mode switch
>[  265.391470] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 1
>[  265.394646] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  265.397906] [drm:ilk_audio_codec_disable] Disable audio codec on port B, pipe A
>[  265.413656] [drm:intel_dp_link_down] 
>[  265.438671] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[  265.438681] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=0, cursor=0, SR: plane=0, cursor=0
>[  265.448669] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  265.448716] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[  265.448724] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  265.448730] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  265.448736] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[  265.448743] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[  265.448748] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[  265.448753] [drm:check_crtc_state] [CRTC:20]
>[  265.448760] [drm:check_crtc_state] [CRTC:25]
>[  265.448765] [drm:check_crtc_state] [CRTC:30]
>[  265.457033] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[5] ENCODERS[5]
>[  265.457046] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[5] ENCODERS[5]
>[  265.457056] [drm:drm_mode_getconnector] [CONNECTOR:47:?]
>[  265.457064] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:47:HDMI-A-2]
>[  265.457074] [drm:intel_hdmi_detect] [CONNECTOR:47:HDMI-A-2]
>[  265.481931] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  265.482151] [drm:drm_edid_to_eld] ELD monitor ASUS VS239
>[  265.482160] [drm:parse_hdmi_vsdb] HDMI: DVI dual 0, max TMDS clock 0, latency present 0 0, video latency 0 0, audio latency 0 0
>[  265.482165] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  265.482270] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:47:HDMI-A-2] probed modes :
>[  265.482280] [drm:drm_mode_debug_printmodeline] Modeline 79:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  265.482289] [drm:drm_mode_debug_printmodeline] Modeline 128:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  265.482296] [drm:drm_mode_debug_printmodeline] Modeline 121:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  265.482304] [drm:drm_mode_debug_printmodeline] Modeline 136:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  265.482311] [drm:drm_mode_debug_printmodeline] Modeline 126:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  265.482318] [drm:drm_mode_debug_printmodeline] Modeline 120:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  265.482326] [drm:drm_mode_debug_printmodeline] Modeline 95:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  265.482332] [drm:drm_mode_debug_printmodeline] Modeline 106:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  265.482339] [drm:drm_mode_debug_printmodeline] Modeline 89:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  265.482345] [drm:drm_mode_debug_printmodeline] Modeline 91:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  265.482353] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  265.482360] [drm:drm_mode_debug_printmodeline] Modeline 97:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  265.482366] [drm:drm_mode_debug_printmodeline] Modeline 96:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  265.482374] [drm:drm_mode_debug_printmodeline] Modeline 81:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  265.482380] [drm:drm_mode_debug_printmodeline] Modeline 130:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  265.482387] [drm:drm_mode_debug_printmodeline] Modeline 82:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  265.482393] [drm:drm_mode_debug_printmodeline] Modeline 124:"1440x576" 50 54000 1440 1464 1592 1728 576 581 586 625 0x40 0xa
>[  265.482400] [drm:drm_mode_debug_printmodeline] Modeline 107:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  265.482408] [drm:drm_mode_debug_printmodeline] Modeline 108:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  265.482416] [drm:drm_mode_debug_printmodeline] Modeline 109:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  265.482422] [drm:drm_mode_debug_printmodeline] Modeline 137:"1440x480" 60 54054 1440 1472 1596 1716 480 489 495 525 0x40 0xa
>[  265.482429] [drm:drm_mode_debug_printmodeline] Modeline 122:"1440x480" 60 54000 1440 1472 1596 1716 480 489 495 525 0x40 0xa
>[  265.482435] [drm:drm_mode_debug_printmodeline] Modeline 110:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[  265.482443] [drm:drm_mode_debug_printmodeline] Modeline 111:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  265.482451] [drm:drm_mode_debug_printmodeline] Modeline 112:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[  265.482457] [drm:drm_mode_debug_printmodeline] Modeline 98:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  265.482464] [drm:drm_mode_debug_printmodeline] Modeline 99:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  265.482470] [drm:drm_mode_debug_printmodeline] Modeline 83:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  265.482476] [drm:drm_mode_debug_printmodeline] Modeline 129:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  265.482483] [drm:drm_mode_debug_printmodeline] Modeline 80:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  265.482489] [drm:drm_mode_debug_printmodeline] Modeline 101:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  265.482496] [drm:drm_mode_debug_printmodeline] Modeline 103:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  265.482502] [drm:drm_mode_debug_printmodeline] Modeline 104:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  265.482509] [drm:drm_mode_debug_printmodeline] Modeline 113:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  265.482515] [drm:drm_mode_debug_printmodeline] Modeline 105:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  265.482543] [drm:drm_mode_getconnector] [CONNECTOR:47:?]
>[  265.482652] [drm:drm_mode_addfb2] [FB:116]
>[  265.795234] [drm:drm_mode_setcrtc] [CRTC:30]
>[  265.795251] [drm:drm_mode_setcrtc] [CONNECTOR:47:HDMI-A-2]
>[  265.795259] [drm:intel_crtc_set_config] [CRTC:30] [FB:116] #connectors=1 (x y) (0 0)
>[  265.795268] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:30], mode_changed=1, fb_changed=0
>[  265.795275] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[  265.795282] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 4, prepare: 4, disable: 0
>[  265.795288] [drm:connected_sink_compute_bpp] [CONNECTOR:47:HDMI-A-2] checking for sink bpp constrains
>[  265.795296] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[  265.795300] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[  265.795305] [drm:intel_modeset_pipe_config] plane bpp: 18, pipe bpp: 24, dithering: 1
>[  265.795309] [drm:intel_dump_pipe_config] [CRTC:30][modeset] config for pipe C
>[  265.795313] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[  265.795316] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 1
>[  265.795321] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  265.795326] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  265.795331] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  265.795334] [drm:intel_dump_pipe_config] audio: 1, infoframes: 1
>[  265.795337] [drm:intel_dump_pipe_config] requested mode:
>[  265.795344] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  265.795348] [drm:intel_dump_pipe_config] adjusted mode:
>[  265.795354] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  265.795360] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  265.795364] [drm:intel_dump_pipe_config] port clock: 148500
>[  265.795367] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  265.795371] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  265.795376] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  265.795379] [drm:intel_dump_pipe_config] ips: 0
>[  265.795382] [drm:intel_dump_pipe_config] double wide: 0
>[  265.798769] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  265.808268] [drm:ilk_audio_codec_disable] Disable audio codec on port D, pipe C
>[  265.849799] [drm:vlv_get_fifo_size] Pipe C primary C FIFO size: 256
>[  265.849809] [drm:valleyview_update_wm] Setting FIFO watermarks - C: plane=0, cursor=0, SR: plane=0, cursor=0
>[  265.859792] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  266.023888] [drm:intel_enable_hdmi] Enabling HDMI audio on pipe C
>[  266.023897] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:HDMI-A-2], [ENCODER:46:TMDS-46]
>[  266.023903] [drm:ilk_audio_codec_enable] Enable audio codec on port D, pipe C, 36 bytes ELD
>[  266.023916] [drm:audio_config_hdmi_pixel_clock] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  266.024148] [drm:vlv_get_fifo_size] Pipe C primary C FIFO size: 256
>[  266.024154] [drm:valleyview_update_wm] Setting FIFO watermarks - C: plane=8, cursor=0, SR: plane=0, cursor=0
>[  266.033878] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  266.033921] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[  266.033933] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  266.033939] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  266.033945] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[  266.033950] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[  266.033955] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[  266.033960] [drm:check_crtc_state] [CRTC:20]
>[  266.033967] [drm:check_crtc_state] [CRTC:25]
>[  266.033972] [drm:check_crtc_state] [CRTC:30]
>[  271.044229] [drm:drm_mode_addfb2] [FB:118]
>[  271.357215] [drm:drm_mode_setcrtc] [CRTC:30]
>[  271.357232] [drm:drm_mode_setcrtc] [CONNECTOR:47:HDMI-A-2]
>[  271.357240] [drm:intel_crtc_set_config] [CRTC:30] [FB:118] #connectors=1 (x y) (0 0)
>[  271.357248] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[  271.357257] [drm:drm_mode_debug_printmodeline] Modeline 118:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  271.357263] [drm:drm_mode_debug_printmodeline] Modeline 119:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  271.357268] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:30], mode_changed=1, fb_changed=1
>[  271.357274] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[  271.357281] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 4, prepare: 4, disable: 0
>[  271.357286] [drm:connected_sink_compute_bpp] [CONNECTOR:47:HDMI-A-2] checking for sink bpp constrains
>[  271.357295] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[  271.357298] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[  271.357305] [drm:intel_modeset_pipe_config] plane bpp: 18, pipe bpp: 24, dithering: 1
>[  271.357311] [drm:intel_dump_pipe_config] [CRTC:30][modeset] config for pipe C
>[  271.357314] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[  271.357317] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 1
>[  271.357324] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  271.357328] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  271.357333] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  271.357337] [drm:intel_dump_pipe_config] audio: 1, infoframes: 1
>[  271.357340] [drm:intel_dump_pipe_config] requested mode:
>[  271.357346] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  271.357350] [drm:intel_dump_pipe_config] adjusted mode:
>[  271.357357] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  271.357363] [drm:intel_dump_crtc_timings] crtc timings: 148352 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x40 flags: 0x5
>[  271.357367] [drm:intel_dump_pipe_config] port clock: 148352
>[  271.357371] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  271.357375] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  271.357381] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  271.357385] [drm:intel_dump_pipe_config] ips: 0
>[  271.357388] [drm:intel_dump_pipe_config] double wide: 0
>[  271.361193] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  271.370204] [drm:valleyview_pipestat_irq_handler [i915]] *ERROR* CPU pipe C FIFO underrun
>[  271.370275] [drm:ilk_audio_codec_disable] Disable audio codec on port D, pipe C
>[  271.412302] [drm:vlv_get_fifo_size] Pipe C primary C FIFO size: 256
>[  271.412311] [drm:valleyview_update_wm] Setting FIFO watermarks - C: plane=0, cursor=0, SR: plane=0, cursor=0
>[  271.422268] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  271.586506] [drm:intel_enable_hdmi] Enabling HDMI audio on pipe C
>[  271.586516] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:HDMI-A-2], [ENCODER:46:TMDS-46]
>[  271.586522] [drm:ilk_audio_codec_enable] Enable audio codec on port D, pipe C, 36 bytes ELD
>[  271.586536] [drm:audio_config_hdmi_pixel_clock] Configuring HDMI audio for pixel clock 148352 (0x00080000)
>[  271.586602] [drm:vlv_get_fifo_size] Pipe C primary C FIFO size: 256
>[  271.586609] [drm:valleyview_update_wm] Setting FIFO watermarks - C: plane=8, cursor=0, SR: plane=0, cursor=0
>[  271.596300] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  271.596342] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[  271.596351] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  271.596356] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  271.596363] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[  271.596368] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[  271.596373] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[  271.596379] [drm:check_crtc_state] [CRTC:20]
>[  271.596388] [drm:check_crtc_state] [CRTC:25]
>[  271.596393] [drm:check_crtc_state] [CRTC:30]
>[  276.607878] [drm:drm_mode_addfb2] [FB:116]
>[  276.920474] [drm:drm_mode_setcrtc] [CRTC:30]
>[  276.920492] [drm:drm_mode_setcrtc] [CONNECTOR:47:HDMI-A-2]
>[  276.920500] [drm:intel_crtc_set_config] [CRTC:30] [FB:116] #connectors=1 (x y) (0 0)
>[  276.920509] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[  276.920518] [drm:drm_mode_debug_printmodeline] Modeline 119:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  276.920525] [drm:drm_mode_debug_printmodeline] Modeline 119:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  276.920529] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:30], mode_changed=1, fb_changed=1
>[  276.920536] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[  276.920542] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 4, prepare: 4, disable: 0
>[  276.920548] [drm:connected_sink_compute_bpp] [CONNECTOR:47:HDMI-A-2] checking for sink bpp constrains
>[  276.920554] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[  276.920558] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[  276.920563] [drm:intel_modeset_pipe_config] plane bpp: 18, pipe bpp: 24, dithering: 1
>[  276.920568] [drm:intel_dump_pipe_config] [CRTC:30][modeset] config for pipe C
>[  276.920571] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[  276.920575] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 1
>[  276.920580] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  276.920584] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  276.920589] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  276.920593] [drm:intel_dump_pipe_config] audio: 1, infoframes: 1
>[  276.920596] [drm:intel_dump_pipe_config] requested mode:
>[  276.920618] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  276.920622] [drm:intel_dump_pipe_config] adjusted mode:
>[  276.920628] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  276.920634] [drm:intel_dump_crtc_timings] crtc timings: 74250 1920 2008 2052 2200 1080 1084 1094 1125, type: 0x40 flags: 0x15
>[  276.920638] [drm:intel_dump_pipe_config] port clock: 74250
>[  276.920641] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  276.920646] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  276.920650] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  276.920654] [drm:intel_dump_pipe_config] ips: 0
>[  276.920657] [drm:intel_dump_pipe_config] double wide: 0
>[  276.924619] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  276.937836] [drm:valleyview_pipestat_irq_handler [i915]] *ERROR* CPU pipe C FIFO underrun
>[  276.937900] [drm:ilk_audio_codec_disable] Disable audio codec on port D, pipe C
>[  276.979704] [drm:vlv_get_fifo_size] Pipe C primary C FIFO size: 256
>[  276.979714] [drm:valleyview_update_wm] Setting FIFO watermarks - C: plane=0, cursor=0, SR: plane=0, cursor=0
>[  276.989694] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  277.153806] [drm:intel_enable_hdmi] Enabling HDMI audio on pipe C
>[  277.153816] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:HDMI-A-2], [ENCODER:46:TMDS-46]
>[  277.153823] [drm:ilk_audio_codec_enable] Enable audio codec on port D, pipe C, 36 bytes ELD
>[  277.153838] [drm:audio_config_hdmi_pixel_clock] Configuring HDMI audio for pixel clock 74250 (0x00070000)
>[  277.154114] [drm:vlv_get_fifo_size] Pipe C primary C FIFO size: 256
>[  277.154120] [drm:valleyview_update_wm] Setting FIFO watermarks - C: plane=8, cursor=0, SR: plane=0, cursor=0
>[  277.163722] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  277.163773] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[  277.163780] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  277.163786] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  277.163791] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[  277.163796] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[  277.163801] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[  277.163806] [drm:check_crtc_state] [CRTC:20]
>[  277.163812] [drm:check_crtc_state] [CRTC:25]
>[  277.163817] [drm:check_crtc_state] [CRTC:30]
>[  282.175165] [drm:drm_mode_addfb2] [FB:118]
>[  282.487695] [drm:drm_mode_setcrtc] [CRTC:30]
>[  282.487713] [drm:drm_mode_setcrtc] [CONNECTOR:47:HDMI-A-2]
>[  282.487721] [drm:intel_crtc_set_config] [CRTC:30] [FB:118] #connectors=1 (x y) (0 0)
>[  282.487729] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[  282.487737] [drm:drm_mode_debug_printmodeline] Modeline 119:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  282.487744] [drm:drm_mode_debug_printmodeline] Modeline 119:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  282.487750] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:30], mode_changed=1, fb_changed=1
>[  282.487756] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[  282.487763] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 4, prepare: 4, disable: 0
>[  282.487769] [drm:connected_sink_compute_bpp] [CONNECTOR:47:HDMI-A-2] checking for sink bpp constrains
>[  282.487779] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[  282.487782] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[  282.487789] [drm:intel_modeset_pipe_config] plane bpp: 18, pipe bpp: 24, dithering: 1
>[  282.487794] [drm:intel_dump_pipe_config] [CRTC:30][modeset] config for pipe C
>[  282.487798] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[  282.487801] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 1
>[  282.487808] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  282.487812] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  282.487817] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  282.487820] [drm:intel_dump_pipe_config] audio: 1, infoframes: 1
>[  282.487823] [drm:intel_dump_pipe_config] requested mode:
>[  282.487830] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  282.487833] [drm:intel_dump_pipe_config] adjusted mode:
>[  282.487839] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  282.487845] [drm:intel_dump_crtc_timings] crtc timings: 74176 1920 2008 2052 2200 1080 1084 1094 1125, type: 0x40 flags: 0x15
>[  282.487849] [drm:intel_dump_pipe_config] port clock: 74176
>[  282.487852] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  282.487857] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  282.487861] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  282.487864] [drm:intel_dump_pipe_config] ips: 0
>[  282.487868] [drm:intel_dump_pipe_config] double wide: 0
>[  282.491047] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  282.499903] [drm:valleyview_pipestat_irq_handler [i915]] *ERROR* CPU pipe C FIFO underrun
>[  282.499972] [drm:ilk_audio_codec_disable] Disable audio codec on port D, pipe C
>[  282.541183] [drm:vlv_get_fifo_size] Pipe C primary C FIFO size: 256
>[  282.541193] [drm:valleyview_update_wm] Setting FIFO watermarks - C: plane=0, cursor=0, SR: plane=0, cursor=0
>[  282.551223] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  282.715212] [drm:intel_enable_hdmi] Enabling HDMI audio on pipe C
>[  282.715221] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:HDMI-A-2], [ENCODER:46:TMDS-46]
>[  282.715228] [drm:ilk_audio_codec_enable] Enable audio codec on port D, pipe C, 36 bytes ELD
>[  282.715242] [drm:audio_config_hdmi_pixel_clock] Configuring HDMI audio for pixel clock 74176 (0x00060000)
>[  282.715440] [drm:vlv_get_fifo_size] Pipe C primary C FIFO size: 256
>[  282.715446] [drm:valleyview_update_wm] Setting FIFO watermarks - C: plane=8, cursor=0, SR: plane=0, cursor=0
>[  282.725152] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  282.725196] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[  282.725204] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  282.725211] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  282.725217] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[  282.725222] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[  282.725227] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[  282.725234] [drm:check_crtc_state] [CRTC:20]
>[  282.725242] [drm:check_crtc_state] [CRTC:25]
>[  282.725247] [drm:check_crtc_state] [CRTC:30]
>[  287.736728] [drm:drm_mode_addfb2] [FB:116]
>[  288.049138] [drm:drm_mode_setcrtc] [CRTC:30]
>[  288.049156] [drm:drm_mode_setcrtc] [CONNECTOR:47:HDMI-A-2]
>[  288.049164] [drm:intel_crtc_set_config] [CRTC:30] [FB:116] #connectors=1 (x y) (0 0)
>[  288.049172] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[  288.049180] [drm:drm_mode_debug_printmodeline] Modeline 119:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  288.049188] [drm:drm_mode_debug_printmodeline] Modeline 119:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  288.049194] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:30], mode_changed=1, fb_changed=1
>[  288.049200] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[  288.049207] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 4, prepare: 4, disable: 0
>[  288.049214] [drm:connected_sink_compute_bpp] [CONNECTOR:47:HDMI-A-2] checking for sink bpp constrains
>[  288.049224] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[  288.049228] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[  288.049234] [drm:intel_modeset_pipe_config] plane bpp: 18, pipe bpp: 24, dithering: 1
>[  288.049238] [drm:intel_dump_pipe_config] [CRTC:30][modeset] config for pipe C
>[  288.049242] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[  288.049245] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 1
>[  288.049250] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  288.049255] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  288.049259] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  288.049263] [drm:intel_dump_pipe_config] audio: 1, infoframes: 1
>[  288.049266] [drm:intel_dump_pipe_config] requested mode:
>[  288.049272] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  288.049276] [drm:intel_dump_pipe_config] adjusted mode:
>[  288.049282] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  288.049288] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2448 2492 2640 1080 1084 1089 1125, type: 0x40 flags: 0x5
>[  288.049291] [drm:intel_dump_pipe_config] port clock: 148500
>[  288.049295] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  288.049299] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  288.049303] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  288.049307] [drm:intel_dump_pipe_config] ips: 0
>[  288.049310] [drm:intel_dump_pipe_config] double wide: 0
>[  288.052472] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  288.066494] [drm:valleyview_pipestat_irq_handler [i915]] *ERROR* CPU pipe C FIFO underrun
>[  288.066550] [drm:ilk_audio_codec_disable] Disable audio codec on port D, pipe C
>[  288.108611] [drm:vlv_get_fifo_size] Pipe C primary C FIFO size: 256
>[  288.108621] [drm:valleyview_update_wm] Setting FIFO watermarks - C: plane=0, cursor=0, SR: plane=0, cursor=0
>[  288.118543] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  288.282648] [drm:intel_enable_hdmi] Enabling HDMI audio on pipe C
>[  288.282657] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:HDMI-A-2], [ENCODER:46:TMDS-46]
>[  288.282664] [drm:ilk_audio_codec_enable] Enable audio codec on port D, pipe C, 36 bytes ELD
>[  288.282678] [drm:audio_config_hdmi_pixel_clock] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  288.282882] [drm:vlv_get_fifo_size] Pipe C primary C FIFO size: 256
>[  288.282887] [drm:valleyview_update_wm] Setting FIFO watermarks - C: plane=8, cursor=0, SR: plane=0, cursor=0
>[  288.292570] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  288.292627] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[  288.292636] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  288.292641] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  288.292646] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[  288.292652] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[  288.292657] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[  288.292664] [drm:check_crtc_state] [CRTC:20]
>[  288.292672] [drm:check_crtc_state] [CRTC:25]
>[  288.292677] [drm:check_crtc_state] [CRTC:30]
>[  293.304032] [drm:drm_mode_addfb2] [FB:118]
>[  293.616263] [drm:drm_mode_setcrtc] [CRTC:30]
>[  293.616281] [drm:drm_mode_setcrtc] [CONNECTOR:47:HDMI-A-2]
>[  293.616288] [drm:intel_crtc_set_config] [CRTC:30] [FB:118] #connectors=1 (x y) (0 0)
>[  293.616296] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[  293.616303] [drm:drm_mode_debug_printmodeline] Modeline 119:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  293.616309] [drm:drm_mode_debug_printmodeline] Modeline 119:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  293.616314] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:30], mode_changed=1, fb_changed=1
>[  293.616320] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[  293.616326] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 4, prepare: 4, disable: 0
>[  293.616332] [drm:connected_sink_compute_bpp] [CONNECTOR:47:HDMI-A-2] checking for sink bpp constrains
>[  293.616341] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[  293.616344] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[  293.616349] [drm:intel_modeset_pipe_config] plane bpp: 18, pipe bpp: 24, dithering: 1
>[  293.616354] [drm:intel_dump_pipe_config] [CRTC:30][modeset] config for pipe C
>[  293.616358] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[  293.616361] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 1
>[  293.616366] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  293.616371] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  293.616376] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  293.616379] [drm:intel_dump_pipe_config] audio: 1, infoframes: 1
>[  293.616382] [drm:intel_dump_pipe_config] requested mode:
>[  293.616389] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  293.616392] [drm:intel_dump_pipe_config] adjusted mode:
>[  293.616398] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  293.616406] [drm:intel_dump_crtc_timings] crtc timings: 74250 1920 2448 2492 2640 1080 1084 1094 1125, type: 0x40 flags: 0x15
>[  293.616409] [drm:intel_dump_pipe_config] port clock: 74250
>[  293.616413] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  293.616417] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  293.616423] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  293.616426] [drm:intel_dump_pipe_config] ips: 0
>[  293.616429] [drm:intel_dump_pipe_config] double wide: 0
>[  293.619889] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  293.635423] [drm:valleyview_pipestat_irq_handler [i915]] *ERROR* CPU pipe C FIFO underrun
>[  293.635486] [drm:ilk_audio_codec_disable] Disable audio codec on port D, pipe C
>[  293.681133] [drm:vlv_get_fifo_size] Pipe C primary C FIFO size: 256
>[  293.681143] [drm:valleyview_update_wm] Setting FIFO watermarks - C: plane=0, cursor=0, SR: plane=0, cursor=0
>[  293.691040] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  293.855070] [drm:intel_enable_hdmi] Enabling HDMI audio on pipe C
>[  293.855082] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:HDMI-A-2], [ENCODER:46:TMDS-46]
>[  293.855088] [drm:ilk_audio_codec_enable] Enable audio codec on port D, pipe C, 36 bytes ELD
>[  293.855103] [drm:audio_config_hdmi_pixel_clock] Configuring HDMI audio for pixel clock 74250 (0x00070000)
>[  293.855306] [drm:vlv_get_fifo_size] Pipe C primary C FIFO size: 256
>[  293.855312] [drm:valleyview_update_wm] Setting FIFO watermarks - C: plane=8, cursor=0, SR: plane=0, cursor=0
>[  293.864998] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  293.865042] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[  293.865050] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  293.865056] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  293.865062] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[  293.865067] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[  293.865072] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[  293.865079] [drm:check_crtc_state] [CRTC:20]
>[  293.865088] [drm:check_crtc_state] [CRTC:25]
>[  293.865092] [drm:check_crtc_state] [CRTC:30]
>[  298.876535] [drm:drm_mode_addfb2] [FB:116]
>[  299.165796] [drm:drm_mode_setcrtc] [CRTC:30]
>[  299.165812] [drm:drm_mode_setcrtc] [CONNECTOR:47:HDMI-A-2]
>[  299.165821] [drm:intel_crtc_set_config] [CRTC:30] [FB:116] #connectors=1 (x y) (0 0)
>[  299.165830] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[  299.165838] [drm:drm_mode_debug_printmodeline] Modeline 119:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  299.165845] [drm:drm_mode_debug_printmodeline] Modeline 119:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  299.165849] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:30], mode_changed=1, fb_changed=1
>[  299.165856] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[  299.165862] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 4, prepare: 4, disable: 0
>[  299.165869] [drm:connected_sink_compute_bpp] [CONNECTOR:47:HDMI-A-2] checking for sink bpp constrains
>[  299.165886] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[  299.165890] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[  299.165896] [drm:intel_modeset_pipe_config] plane bpp: 18, pipe bpp: 24, dithering: 1
>[  299.165902] [drm:intel_dump_pipe_config] [CRTC:30][modeset] config for pipe C
>[  299.165905] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[  299.165909] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 1
>[  299.165913] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  299.165918] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  299.165923] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  299.165926] [drm:intel_dump_pipe_config] audio: 1, infoframes: 1
>[  299.165929] [drm:intel_dump_pipe_config] requested mode:
>[  299.165936] [drm:drm_mode_debug_printmodeline] Modeline 0:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  299.165939] [drm:intel_dump_pipe_config] adjusted mode:
>[  299.165945] [drm:drm_mode_debug_printmodeline] Modeline 0:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  299.165951] [drm:intel_dump_crtc_timings] crtc timings: 119000 1680 1728 1760 1840 1050 1053 1059 1080, type: 0x40 flags: 0x9
>[  299.165955] [drm:intel_dump_pipe_config] port clock: 119000
>[  299.165958] [drm:intel_dump_pipe_config] pipe src size: 1680x1050
>[  299.165963] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  299.165967] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  299.165970] [drm:intel_dump_pipe_config] ips: 0
>[  299.165974] [drm:intel_dump_pipe_config] double wide: 0
>[  299.169312] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  299.187994] [drm:valleyview_pipestat_irq_handler [i915]] *ERROR* CPU pipe C FIFO underrun
>[  299.188067] [drm:ilk_audio_codec_disable] Disable audio codec on port D, pipe C
>[  299.233396] [drm:vlv_get_fifo_size] Pipe C primary C FIFO size: 256
>[  299.233405] [drm:valleyview_update_wm] Setting FIFO watermarks - C: plane=0, cursor=0, SR: plane=0, cursor=0
>[  299.243390] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  299.407520] [drm:intel_enable_hdmi] Enabling HDMI audio on pipe C
>[  299.407530] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:HDMI-A-2], [ENCODER:46:TMDS-46]
>[  299.407537] [drm:ilk_audio_codec_enable] Enable audio codec on port D, pipe C, 36 bytes ELD
>[  299.407550] [drm:audio_config_hdmi_pixel_clock] HDMI audio pixel clock setting for 119000 not found, falling back to defaults
>[  299.407554] [drm:audio_config_hdmi_pixel_clock] Configuring HDMI audio for pixel clock 25200 (0x00010000)
>[  299.407624] [drm:vlv_get_fifo_size] Pipe C primary C FIFO size: 256
>[  299.407631] [drm:valleyview_update_wm] Setting FIFO watermarks - C: plane=8, cursor=0, SR: plane=0, cursor=0
>[  299.417420] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  299.417463] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[  299.417485] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  299.417491] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  299.417496] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[  299.417501] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[  299.417506] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[  299.417512] [drm:check_crtc_state] [CRTC:20]
>[  299.417519] [drm:check_crtc_state] [CRTC:25]
>[  299.417524] [drm:check_crtc_state] [CRTC:30]
>[  304.428913] [drm:drm_mode_addfb2] [FB:118]
>[  304.680098] [drm:drm_mode_setcrtc] [CRTC:30]
>[  304.680115] [drm:drm_mode_setcrtc] [CONNECTOR:47:HDMI-A-2]
>[  304.680122] [drm:intel_crtc_set_config] [CRTC:30] [FB:118] #connectors=1 (x y) (0 0)
>[  304.680129] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[  304.680137] [drm:drm_mode_debug_printmodeline] Modeline 119:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  304.680143] [drm:drm_mode_debug_printmodeline] Modeline 119:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  304.680148] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:30], mode_changed=1, fb_changed=1
>[  304.680153] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[  304.680160] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 4, prepare: 4, disable: 0
>[  304.680166] [drm:connected_sink_compute_bpp] [CONNECTOR:47:HDMI-A-2] checking for sink bpp constrains
>[  304.680180] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[  304.680183] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[  304.680188] [drm:intel_modeset_pipe_config] plane bpp: 18, pipe bpp: 24, dithering: 1
>[  304.680193] [drm:intel_dump_pipe_config] [CRTC:30][modeset] config for pipe C
>[  304.680196] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[  304.680200] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 1
>[  304.680206] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  304.680210] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  304.680215] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  304.680219] [drm:intel_dump_pipe_config] audio: 1, infoframes: 1
>[  304.680222] [drm:intel_dump_pipe_config] requested mode:
>[  304.680228] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  304.680232] [drm:intel_dump_pipe_config] adjusted mode:
>[  304.680239] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  304.680245] [drm:intel_dump_crtc_timings] crtc timings: 135000 1280 1296 1440 1688 1024 1025 1028 1066, type: 0x40 flags: 0x5
>[  304.680248] [drm:intel_dump_pipe_config] port clock: 135000
>[  304.680252] [drm:intel_dump_pipe_config] pipe src size: 1280x1024
>[  304.680256] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  304.680260] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  304.680264] [drm:intel_dump_pipe_config] ips: 0
>[  304.680267] [drm:intel_dump_pipe_config] double wide: 0
>[  304.683865] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  304.697303] [drm:valleyview_pipestat_irq_handler [i915]] *ERROR* CPU pipe C FIFO underrun
>[  304.697371] [drm:ilk_audio_codec_disable] Disable audio codec on port D, pipe C
>[  304.738795] [drm:vlv_get_fifo_size] Pipe C primary C FIFO size: 256
>[  304.738806] [drm:valleyview_update_wm] Setting FIFO watermarks - C: plane=0, cursor=0, SR: plane=0, cursor=0
>[  304.748787] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  304.912966] [drm:intel_enable_hdmi] Enabling HDMI audio on pipe C
>[  304.912977] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:HDMI-A-2], [ENCODER:46:TMDS-46]
>[  304.912983] [drm:ilk_audio_codec_enable] Enable audio codec on port D, pipe C, 36 bytes ELD
>[  304.912997] [drm:audio_config_hdmi_pixel_clock] HDMI audio pixel clock setting for 135000 not found, falling back to defaults
>[  304.913017] [drm:audio_config_hdmi_pixel_clock] Configuring HDMI audio for pixel clock 25200 (0x00010000)
>[  304.913279] [drm:vlv_get_fifo_size] Pipe C primary C FIFO size: 256
>[  304.913285] [drm:valleyview_update_wm] Setting FIFO watermarks - C: plane=8, cursor=0, SR: plane=0, cursor=0
>[  304.922815] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  304.922855] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[  304.922864] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  304.922869] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  304.922875] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[  304.922880] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[  304.922884] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[  304.922889] [drm:check_crtc_state] [CRTC:20]
>[  304.922899] [drm:check_crtc_state] [CRTC:25]
>[  304.922904] [drm:check_crtc_state] [CRTC:30]
>[  309.934247] [drm:drm_mode_addfb2] [FB:116]
>[  310.185960] [drm:drm_mode_setcrtc] [CRTC:30]
>[  310.185977] [drm:drm_mode_setcrtc] [CONNECTOR:47:HDMI-A-2]
>[  310.185985] [drm:intel_crtc_set_config] [CRTC:30] [FB:116] #connectors=1 (x y) (0 0)
>[  310.185993] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[  310.186002] [drm:drm_mode_debug_printmodeline] Modeline 119:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  310.186010] [drm:drm_mode_debug_printmodeline] Modeline 119:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  310.186016] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:30], mode_changed=1, fb_changed=1
>[  310.186022] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[  310.186028] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 4, prepare: 4, disable: 0
>[  310.186034] [drm:connected_sink_compute_bpp] [CONNECTOR:47:HDMI-A-2] checking for sink bpp constrains
>[  310.186049] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[  310.186052] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[  310.186060] [drm:intel_modeset_pipe_config] plane bpp: 18, pipe bpp: 24, dithering: 1
>[  310.186067] [drm:intel_dump_pipe_config] [CRTC:30][modeset] config for pipe C
>[  310.186070] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[  310.186074] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 1
>[  310.186079] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  310.186084] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  310.186088] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  310.186110] [drm:intel_dump_pipe_config] audio: 1, infoframes: 1
>[  310.186114] [drm:intel_dump_pipe_config] requested mode:
>[  310.186120] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  310.186125] [drm:intel_dump_pipe_config] adjusted mode:
>[  310.186131] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  310.186137] [drm:intel_dump_crtc_timings] crtc timings: 108000 1280 1328 1440 1688 1024 1025 1028 1066, type: 0x40 flags: 0x5
>[  310.186141] [drm:intel_dump_pipe_config] port clock: 108000
>[  310.186145] [drm:intel_dump_pipe_config] pipe src size: 1280x1024
>[  310.186149] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  310.186154] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  310.186158] [drm:intel_dump_pipe_config] ips: 0
>[  310.186161] [drm:intel_dump_pipe_config] double wide: 0
>[  310.190111] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  310.190698] [drm:valleyview_pipestat_irq_handler [i915]] *ERROR* CPU pipe C FIFO underrun
>[  310.190765] [drm:ilk_audio_codec_disable] Disable audio codec on port D, pipe C
>[  310.228264] [drm:vlv_get_fifo_size] Pipe C primary C FIFO size: 256
>[  310.228274] [drm:valleyview_update_wm] Setting FIFO watermarks - C: plane=0, cursor=0, SR: plane=0, cursor=0
>[  310.238201] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  310.402284] [drm:intel_enable_hdmi] Enabling HDMI audio on pipe C
>[  310.402294] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:HDMI-A-2], [ENCODER:46:TMDS-46]
>[  310.402300] [drm:ilk_audio_codec_enable] Enable audio codec on port D, pipe C, 36 bytes ELD
>[  310.402315] [drm:audio_config_hdmi_pixel_clock] HDMI audio pixel clock setting for 108000 not found, falling back to defaults
>[  310.402339] [drm:audio_config_hdmi_pixel_clock] Configuring HDMI audio for pixel clock 25200 (0x00010000)
>[  310.402572] [drm:vlv_get_fifo_size] Pipe C primary C FIFO size: 256
>[  310.402578] [drm:valleyview_update_wm] Setting FIFO watermarks - C: plane=8, cursor=0, SR: plane=0, cursor=0
>[  310.412210] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  310.412256] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[  310.412265] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  310.412271] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  310.412275] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[  310.412280] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[  310.412298] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[  310.412303] [drm:check_crtc_state] [CRTC:20]
>[  310.412311] [drm:check_crtc_state] [CRTC:25]
>[  310.412316] [drm:check_crtc_state] [CRTC:30]
>[  315.423482] [drm:drm_mode_addfb2] [FB:118]
>[  315.674736] [drm:drm_mode_setcrtc] [CRTC:30]
>[  315.674753] [drm:drm_mode_setcrtc] [CONNECTOR:47:HDMI-A-2]
>[  315.674761] [drm:intel_crtc_set_config] [CRTC:30] [FB:118] #connectors=1 (x y) (0 0)
>[  315.674769] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[  315.674778] [drm:drm_mode_debug_printmodeline] Modeline 119:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  315.674784] [drm:drm_mode_debug_printmodeline] Modeline 119:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  315.674789] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:30], mode_changed=1, fb_changed=1
>[  315.674795] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[  315.674802] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 4, prepare: 4, disable: 0
>[  315.674808] [drm:connected_sink_compute_bpp] [CONNECTOR:47:HDMI-A-2] checking for sink bpp constrains
>[  315.674822] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[  315.674825] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[  315.674831] [drm:intel_modeset_pipe_config] plane bpp: 18, pipe bpp: 24, dithering: 1
>[  315.674835] [drm:intel_dump_pipe_config] [CRTC:30][modeset] config for pipe C
>[  315.674839] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[  315.674842] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 1
>[  315.674847] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  315.674852] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  315.674857] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  315.674860] [drm:intel_dump_pipe_config] audio: 1, infoframes: 1
>[  315.674863] [drm:intel_dump_pipe_config] requested mode:
>[  315.674870] [drm:drm_mode_debug_printmodeline] Modeline 0:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  315.674873] [drm:intel_dump_pipe_config] adjusted mode:
>[  315.674879] [drm:drm_mode_debug_printmodeline] Modeline 0:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  315.674885] [drm:intel_dump_crtc_timings] crtc timings: 88750 1440 1488 1520 1600 900 903 909 926, type: 0x40 flags: 0x9
>[  315.674889] [drm:intel_dump_pipe_config] port clock: 88750
>[  315.674892] [drm:intel_dump_pipe_config] pipe src size: 1440x900
>[  315.674897] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  315.674901] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  315.674905] [drm:intel_dump_pipe_config] ips: 0
>[  315.674908] [drm:intel_dump_pipe_config] double wide: 0
>[  315.678502] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  315.679876] [drm:valleyview_pipestat_irq_handler [i915]] *ERROR* CPU pipe C FIFO underrun
>[  315.679925] [drm:ilk_audio_codec_disable] Disable audio codec on port D, pipe C
>[  315.721656] [drm:vlv_get_fifo_size] Pipe C primary C FIFO size: 256
>[  315.721665] [drm:valleyview_update_wm] Setting FIFO watermarks - C: plane=0, cursor=0, SR: plane=0, cursor=0
>[  315.731593] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  315.895677] [drm:intel_enable_hdmi] Enabling HDMI audio on pipe C
>[  315.895688] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:HDMI-A-2], [ENCODER:46:TMDS-46]
>[  315.895694] [drm:ilk_audio_codec_enable] Enable audio codec on port D, pipe C, 36 bytes ELD
>[  315.895707] [drm:audio_config_hdmi_pixel_clock] HDMI audio pixel clock setting for 88750 not found, falling back to defaults
>[  315.895712] [drm:audio_config_hdmi_pixel_clock] Configuring HDMI audio for pixel clock 25200 (0x00010000)
>[  315.895778] [drm:vlv_get_fifo_size] Pipe C primary C FIFO size: 256
>[  315.895785] [drm:valleyview_update_wm] Setting FIFO watermarks - C: plane=8, cursor=0, SR: plane=0, cursor=0
>[  315.905606] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  315.905652] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[  315.905659] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  315.905665] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  315.905670] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[  315.905675] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[  315.905679] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[  315.905685] [drm:check_crtc_state] [CRTC:20]
>[  315.905692] [drm:check_crtc_state] [CRTC:25]
>[  315.905697] [drm:check_crtc_state] [CRTC:30]
>[  320.916893] [drm:drm_mode_addfb2] [FB:116]
>[  321.162294] [drm:drm_mode_setcrtc] [CRTC:30]
>[  321.162311] [drm:drm_mode_setcrtc] [CONNECTOR:47:HDMI-A-2]
>[  321.162319] [drm:intel_crtc_set_config] [CRTC:30] [FB:116] #connectors=1 (x y) (0 0)
>[  321.162327] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[  321.162335] [drm:drm_mode_debug_printmodeline] Modeline 119:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  321.162342] [drm:drm_mode_debug_printmodeline] Modeline 119:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  321.162346] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:30], mode_changed=1, fb_changed=1
>[  321.162353] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[  321.162360] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 4, prepare: 4, disable: 0
>[  321.162365] [drm:connected_sink_compute_bpp] [CONNECTOR:47:HDMI-A-2] checking for sink bpp constrains
>[  321.162379] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[  321.162382] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[  321.162387] [drm:intel_modeset_pipe_config] plane bpp: 18, pipe bpp: 24, dithering: 1
>[  321.162392] [drm:intel_dump_pipe_config] [CRTC:30][modeset] config for pipe C
>[  321.162395] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[  321.162399] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 1
>[  321.162404] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  321.162409] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  321.162413] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  321.162417] [drm:intel_dump_pipe_config] audio: 1, infoframes: 1
>[  321.162420] [drm:intel_dump_pipe_config] requested mode:
>[  321.162427] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  321.162430] [drm:intel_dump_pipe_config] adjusted mode:
>[  321.162436] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  321.162442] [drm:intel_dump_crtc_timings] crtc timings: 108000 1280 1376 1488 1800 960 961 964 1000, type: 0x40 flags: 0x5
>[  321.162446] [drm:intel_dump_pipe_config] port clock: 108000
>[  321.162450] [drm:intel_dump_pipe_config] pipe src size: 1280x960
>[  321.162454] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  321.162458] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  321.162462] [drm:intel_dump_pipe_config] ips: 0
>[  321.162465] [drm:intel_dump_pipe_config] double wide: 0
>[  321.165944] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  321.167171] [drm:valleyview_pipestat_irq_handler [i915]] *ERROR* CPU pipe C FIFO underrun
>[  321.167240] [drm:ilk_audio_codec_disable] Disable audio codec on port D, pipe C
>[  321.209049] [drm:vlv_get_fifo_size] Pipe C primary C FIFO size: 256
>[  321.209058] [drm:valleyview_update_wm] Setting FIFO watermarks - C: plane=0, cursor=0, SR: plane=0, cursor=0
>[  321.218963] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  321.383086] [drm:intel_enable_hdmi] Enabling HDMI audio on pipe C
>[  321.383096] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:HDMI-A-2], [ENCODER:46:TMDS-46]
>[  321.383102] [drm:ilk_audio_codec_enable] Enable audio codec on port D, pipe C, 36 bytes ELD
>[  321.383131] [drm:audio_config_hdmi_pixel_clock] HDMI audio pixel clock setting for 108000 not found, falling back to defaults
>[  321.383135] [drm:audio_config_hdmi_pixel_clock] Configuring HDMI audio for pixel clock 25200 (0x00010000)
>[  321.383262] [drm:vlv_get_fifo_size] Pipe C primary C FIFO size: 256
>[  321.383269] [drm:valleyview_update_wm] Setting FIFO watermarks - C: plane=8, cursor=0, SR: plane=0, cursor=0
>[  321.392997] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  321.393039] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[  321.393046] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  321.393053] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  321.393058] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[  321.393063] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[  321.393068] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[  321.393073] [drm:check_crtc_state] [CRTC:20]
>[  321.393079] [drm:check_crtc_state] [CRTC:25]
>[  321.393084] [drm:check_crtc_state] [CRTC:30]
>[  326.404267] [drm:drm_mode_addfb2] [FB:118]
>[  326.634777] [drm:drm_mode_setcrtc] [CRTC:30]
>[  326.634794] [drm:drm_mode_setcrtc] [CONNECTOR:47:HDMI-A-2]
>[  326.634803] [drm:intel_crtc_set_config] [CRTC:30] [FB:118] #connectors=1 (x y) (0 0)
>[  326.634812] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[  326.634821] [drm:drm_mode_debug_printmodeline] Modeline 119:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  326.634827] [drm:drm_mode_debug_printmodeline] Modeline 119:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  326.634832] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:30], mode_changed=1, fb_changed=1
>[  326.634838] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[  326.634844] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 4, prepare: 4, disable: 0
>[  326.634851] [drm:connected_sink_compute_bpp] [CONNECTOR:47:HDMI-A-2] checking for sink bpp constrains
>[  326.634868] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[  326.634871] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[  326.634877] [drm:intel_modeset_pipe_config] plane bpp: 18, pipe bpp: 24, dithering: 1
>[  326.634883] [drm:intel_dump_pipe_config] [CRTC:30][modeset] config for pipe C
>[  326.634887] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[  326.634890] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 1
>[  326.634895] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  326.634900] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  326.634904] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  326.634908] [drm:intel_dump_pipe_config] audio: 1, infoframes: 1
>[  326.634911] [drm:intel_dump_pipe_config] requested mode:
>[  326.634917] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  326.634921] [drm:intel_dump_pipe_config] adjusted mode:
>[  326.634927] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  326.634933] [drm:intel_dump_crtc_timings] crtc timings: 71000 1280 1328 1360 1440 800 803 809 823, type: 0x40 flags: 0x9
>[  326.634936] [drm:intel_dump_pipe_config] port clock: 71000
>[  326.634940] [drm:intel_dump_pipe_config] pipe src size: 1280x800
>[  326.634944] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  326.634954] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  326.634958] [drm:intel_dump_pipe_config] ips: 0
>[  326.634961] [drm:intel_dump_pipe_config] double wide: 0
>[  326.638402] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  326.646176] [drm:valleyview_pipestat_irq_handler [i915]] *ERROR* CPU pipe C FIFO underrun
>[  326.646257] [drm:ilk_audio_codec_disable] Disable audio codec on port D, pipe C
>[  326.686401] [drm:vlv_get_fifo_size] Pipe C primary C FIFO size: 256
>[  326.686410] [drm:valleyview_update_wm] Setting FIFO watermarks - C: plane=0, cursor=0, SR: plane=0, cursor=0
>[  326.696354] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  326.860460] [drm:intel_enable_hdmi] Enabling HDMI audio on pipe C
>[  326.860470] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:HDMI-A-2], [ENCODER:46:TMDS-46]
>[  326.860476] [drm:ilk_audio_codec_enable] Enable audio codec on port D, pipe C, 36 bytes ELD
>[  326.860630] [drm:audio_config_hdmi_pixel_clock] HDMI audio pixel clock setting for 71000 not found, falling back to defaults
>[  326.860635] [drm:audio_config_hdmi_pixel_clock] Configuring HDMI audio for pixel clock 25200 (0x00010000)
>[  326.860703] [drm:vlv_get_fifo_size] Pipe C primary C FIFO size: 256
>[  326.860709] [drm:valleyview_update_wm] Setting FIFO watermarks - C: plane=8, cursor=0, SR: plane=0, cursor=0
>[  326.870375] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  326.870427] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[  326.870436] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  326.870442] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  326.870447] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[  326.870451] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[  326.870456] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[  326.870461] [drm:check_crtc_state] [CRTC:20]
>[  326.870466] [drm:check_crtc_state] [CRTC:25]
>[  326.870471] [drm:check_crtc_state] [CRTC:30]
>[  331.881623] [drm:drm_mode_addfb2] [FB:116]
>[  332.109025] [drm:drm_mode_setcrtc] [CRTC:30]
>[  332.109040] [drm:drm_mode_setcrtc] [CONNECTOR:47:HDMI-A-2]
>[  332.109047] [drm:intel_crtc_set_config] [CRTC:30] [FB:116] #connectors=1 (x y) (0 0)
>[  332.109055] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[  332.109062] [drm:drm_mode_debug_printmodeline] Modeline 119:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  332.109068] [drm:drm_mode_debug_printmodeline] Modeline 119:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  332.109073] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:30], mode_changed=1, fb_changed=1
>[  332.109079] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[  332.109085] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 4, prepare: 4, disable: 0
>[  332.109092] [drm:connected_sink_compute_bpp] [CONNECTOR:47:HDMI-A-2] checking for sink bpp constrains
>[  332.109106] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[  332.109109] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[  332.109115] [drm:intel_modeset_pipe_config] plane bpp: 18, pipe bpp: 24, dithering: 1
>[  332.109120] [drm:intel_dump_pipe_config] [CRTC:30][modeset] config for pipe C
>[  332.109123] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[  332.109127] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 1
>[  332.109132] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  332.109136] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  332.109141] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  332.109145] [drm:intel_dump_pipe_config] audio: 1, infoframes: 1
>[  332.109148] [drm:intel_dump_pipe_config] requested mode:
>[  332.109154] [drm:drm_mode_debug_printmodeline] Modeline 0:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  332.109157] [drm:intel_dump_pipe_config] adjusted mode:
>[  332.109164] [drm:drm_mode_debug_printmodeline] Modeline 0:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  332.109171] [drm:intel_dump_crtc_timings] crtc timings: 108000 1152 1216 1344 1600 864 865 868 900, type: 0x40 flags: 0x5
>[  332.109174] [drm:intel_dump_pipe_config] port clock: 108000
>[  332.109178] [drm:intel_dump_pipe_config] pipe src size: 1152x864
>[  332.109182] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  332.109186] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  332.109190] [drm:intel_dump_pipe_config] ips: 0
>[  332.109193] [drm:intel_dump_pipe_config] double wide: 0
>[  332.112659] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  332.114464] [drm:valleyview_pipestat_irq_handler [i915]] *ERROR* CPU pipe C FIFO underrun
>[  332.114528] [drm:ilk_audio_codec_disable] Disable audio codec on port D, pipe C
>[  332.155741] [drm:vlv_get_fifo_size] Pipe C primary C FIFO size: 256
>[  332.155750] [drm:valleyview_update_wm] Setting FIFO watermarks - C: plane=0, cursor=0, SR: plane=0, cursor=0
>[  332.165732] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  332.329837] [drm:intel_enable_hdmi] Enabling HDMI audio on pipe C
>[  332.329847] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:HDMI-A-2], [ENCODER:46:TMDS-46]
>[  332.329853] [drm:ilk_audio_codec_enable] Enable audio codec on port D, pipe C, 36 bytes ELD
>[  332.330025] [drm:audio_config_hdmi_pixel_clock] HDMI audio pixel clock setting for 108000 not found, falling back to defaults
>[  332.330030] [drm:audio_config_hdmi_pixel_clock] Configuring HDMI audio for pixel clock 25200 (0x00010000)
>[  332.330093] [drm:vlv_get_fifo_size] Pipe C primary C FIFO size: 256
>[  332.330101] [drm:valleyview_update_wm] Setting FIFO watermarks - C: plane=8, cursor=0, SR: plane=0, cursor=0
>[  332.339763] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  332.339804] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[  332.339813] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  332.339818] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  332.339824] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[  332.339841] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[  332.339846] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[  332.339854] [drm:check_crtc_state] [CRTC:20]
>[  332.339862] [drm:check_crtc_state] [CRTC:25]
>[  332.339868] [drm:check_crtc_state] [CRTC:30]
>[  337.350998] [drm:drm_mode_addfb2] [FB:118]
>[  337.571577] [drm:drm_mode_setcrtc] [CRTC:30]
>[  337.571593] [drm:drm_mode_setcrtc] [CONNECTOR:47:HDMI-A-2]
>[  337.571600] [drm:intel_crtc_set_config] [CRTC:30] [FB:118] #connectors=1 (x y) (0 0)
>[  337.571607] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[  337.571614] [drm:drm_mode_debug_printmodeline] Modeline 119:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  337.571621] [drm:drm_mode_debug_printmodeline] Modeline 119:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  337.571625] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:30], mode_changed=1, fb_changed=1
>[  337.571631] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[  337.571637] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 4, prepare: 4, disable: 0
>[  337.571644] [drm:connected_sink_compute_bpp] [CONNECTOR:47:HDMI-A-2] checking for sink bpp constrains
>[  337.571650] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[  337.571653] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[  337.571658] [drm:intel_modeset_pipe_config] plane bpp: 18, pipe bpp: 24, dithering: 1
>[  337.571663] [drm:intel_dump_pipe_config] [CRTC:30][modeset] config for pipe C
>[  337.571666] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[  337.571670] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 1
>[  337.571675] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  337.571679] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  337.571684] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  337.571688] [drm:intel_dump_pipe_config] audio: 1, infoframes: 1
>[  337.571691] [drm:intel_dump_pipe_config] requested mode:
>[  337.571697] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  337.571700] [drm:intel_dump_pipe_config] adjusted mode:
>[  337.571707] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  337.571713] [drm:intel_dump_crtc_timings] crtc timings: 74250 1280 1390 1430 1650 720 725 730 750, type: 0x40 flags: 0x5
>[  337.571738] [drm:intel_dump_pipe_config] port clock: 74250
>[  337.571743] [drm:intel_dump_pipe_config] pipe src size: 1280x720
>[  337.571747] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  337.571752] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  337.571756] [drm:intel_dump_pipe_config] ips: 0
>[  337.571759] [drm:intel_dump_pipe_config] double wide: 0
>[  337.575088] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  337.582529] [drm:valleyview_pipestat_irq_handler [i915]] *ERROR* CPU pipe C FIFO underrun
>[  337.582594] [drm:ilk_audio_codec_disable] Disable audio codec on port D, pipe C
>[  337.620118] [drm:vlv_get_fifo_size] Pipe C primary C FIFO size: 256
>[  337.620128] [drm:valleyview_update_wm] Setting FIFO watermarks - C: plane=0, cursor=0, SR: plane=0, cursor=0
>[  337.630114] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  337.794236] [drm:intel_enable_hdmi] Enabling HDMI audio on pipe C
>[  337.794247] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:HDMI-A-2], [ENCODER:46:TMDS-46]
>[  337.794254] [drm:ilk_audio_codec_enable] Enable audio codec on port D, pipe C, 36 bytes ELD
>[  337.794288] [drm:audio_config_hdmi_pixel_clock] Configuring HDMI audio for pixel clock 74250 (0x00070000)
>[  337.794361] [drm:vlv_get_fifo_size] Pipe C primary C FIFO size: 256
>[  337.794368] [drm:valleyview_update_wm] Setting FIFO watermarks - C: plane=8, cursor=0, SR: plane=0, cursor=0
>[  337.802138] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  337.802185] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[  337.802194] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  337.802199] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  337.802205] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[  337.802210] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[  337.802215] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[  337.802220] [drm:check_crtc_state] [CRTC:20]
>[  337.802225] [drm:check_crtc_state] [CRTC:25]
>[  337.802231] [drm:check_crtc_state] [CRTC:30]
>[  342.813254] [drm:drm_mode_addfb2] [FB:116]
>[  343.034222] [drm:drm_mode_setcrtc] [CRTC:30]
>[  343.034240] [drm:drm_mode_setcrtc] [CONNECTOR:47:HDMI-A-2]
>[  343.034247] [drm:intel_crtc_set_config] [CRTC:30] [FB:116] #connectors=1 (x y) (0 0)
>[  343.034255] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[  343.034263] [drm:drm_mode_debug_printmodeline] Modeline 119:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  343.034270] [drm:drm_mode_debug_printmodeline] Modeline 119:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  343.034274] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:30], mode_changed=1, fb_changed=1
>[  343.034281] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[  343.034287] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 4, prepare: 4, disable: 0
>[  343.034294] [drm:connected_sink_compute_bpp] [CONNECTOR:47:HDMI-A-2] checking for sink bpp constrains
>[  343.034301] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[  343.034305] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[  343.034311] [drm:intel_modeset_pipe_config] plane bpp: 18, pipe bpp: 24, dithering: 1
>[  343.034317] [drm:intel_dump_pipe_config] [CRTC:30][modeset] config for pipe C
>[  343.034320] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[  343.034324] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 1
>[  343.034330] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  343.034334] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  343.034339] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  343.034342] [drm:intel_dump_pipe_config] audio: 1, infoframes: 1
>[  343.034345] [drm:intel_dump_pipe_config] requested mode:
>[  343.034352] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  343.034355] [drm:intel_dump_pipe_config] adjusted mode:
>[  343.034361] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  343.034367] [drm:intel_dump_crtc_timings] crtc timings: 74176 1280 1390 1430 1650 720 725 730 750, type: 0x40 flags: 0x5
>[  343.034370] [drm:intel_dump_pipe_config] port clock: 74176
>[  343.034374] [drm:intel_dump_pipe_config] pipe src size: 1280x720
>[  343.034378] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  343.034383] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  343.034386] [drm:intel_dump_pipe_config] ips: 0
>[  343.034389] [drm:intel_dump_pipe_config] double wide: 0
>[  343.038423] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  343.054934] [drm:valleyview_pipestat_irq_handler [i915]] *ERROR* CPU pipe C FIFO underrun
>[  343.055002] [drm:ilk_audio_codec_disable] Disable audio codec on port D, pipe C
>[  343.096564] [drm:vlv_get_fifo_size] Pipe C primary C FIFO size: 256
>[  343.096574] [drm:valleyview_update_wm] Setting FIFO watermarks - C: plane=0, cursor=0, SR: plane=0, cursor=0
>[  343.106500] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  343.270597] [drm:intel_enable_hdmi] Enabling HDMI audio on pipe C
>[  343.270609] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:HDMI-A-2], [ENCODER:46:TMDS-46]
>[  343.270615] [drm:ilk_audio_codec_enable] Enable audio codec on port D, pipe C, 36 bytes ELD
>[  343.270629] [drm:audio_config_hdmi_pixel_clock] Configuring HDMI audio for pixel clock 74176 (0x00060000)
>[  343.270829] [drm:vlv_get_fifo_size] Pipe C primary C FIFO size: 256
>[  343.270835] [drm:valleyview_update_wm] Setting FIFO watermarks - C: plane=8, cursor=0, SR: plane=0, cursor=0
>[  343.280527] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  343.280575] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[  343.280583] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  343.280587] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  343.280594] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[  343.280598] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[  343.280604] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[  343.280609] [drm:check_crtc_state] [CRTC:20]
>[  343.280619] [drm:check_crtc_state] [CRTC:25]
>[  343.280624] [drm:check_crtc_state] [CRTC:30]
>[  348.291621] [drm:drm_mode_addfb2] [FB:118]
>[  348.512064] [drm:drm_mode_setcrtc] [CRTC:30]
>[  348.512081] [drm:drm_mode_setcrtc] [CONNECTOR:47:HDMI-A-2]
>[  348.512090] [drm:intel_crtc_set_config] [CRTC:30] [FB:118] #connectors=1 (x y) (0 0)
>[  348.512098] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[  348.512106] [drm:drm_mode_debug_printmodeline] Modeline 119:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  348.512112] [drm:drm_mode_debug_printmodeline] Modeline 119:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  348.512117] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:30], mode_changed=1, fb_changed=1
>[  348.512123] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[  348.512130] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 4, prepare: 4, disable: 0
>[  348.512137] [drm:connected_sink_compute_bpp] [CONNECTOR:47:HDMI-A-2] checking for sink bpp constrains
>[  348.512146] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[  348.512150] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[  348.512156] [drm:intel_modeset_pipe_config] plane bpp: 18, pipe bpp: 24, dithering: 1
>[  348.512162] [drm:intel_dump_pipe_config] [CRTC:30][modeset] config for pipe C
>[  348.512165] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[  348.512169] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 1
>[  348.512175] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  348.512180] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  348.512184] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  348.512188] [drm:intel_dump_pipe_config] audio: 1, infoframes: 1
>[  348.512191] [drm:intel_dump_pipe_config] requested mode:
>[  348.512197] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  348.512200] [drm:intel_dump_pipe_config] adjusted mode:
>[  348.512207] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  348.512213] [drm:intel_dump_crtc_timings] crtc timings: 74250 1280 1720 1760 1980 720 725 730 750, type: 0x40 flags: 0x5
>[  348.512216] [drm:intel_dump_pipe_config] port clock: 74250
>[  348.512220] [drm:intel_dump_pipe_config] pipe src size: 1280x720
>[  348.512224] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  348.512228] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  348.512232] [drm:intel_dump_pipe_config] ips: 0
>[  348.512235] [drm:intel_dump_pipe_config] double wide: 0
>[  348.515807] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  348.522036] [drm:valleyview_pipestat_irq_handler [i915]] *ERROR* CPU pipe C FIFO underrun
>[  348.522113] [drm:ilk_audio_codec_disable] Disable audio codec on port D, pipe C
>[  348.564004] [drm:vlv_get_fifo_size] Pipe C primary C FIFO size: 256
>[  348.564013] [drm:valleyview_update_wm] Setting FIFO watermarks - C: plane=0, cursor=0, SR: plane=0, cursor=0
>[  348.573971] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  348.737976] [drm:intel_enable_hdmi] Enabling HDMI audio on pipe C
>[  348.737987] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:HDMI-A-2], [ENCODER:46:TMDS-46]
>[  348.737993] [drm:ilk_audio_codec_enable] Enable audio codec on port D, pipe C, 36 bytes ELD
>[  348.738007] [drm:audio_config_hdmi_pixel_clock] Configuring HDMI audio for pixel clock 74250 (0x00070000)
>[  348.738208] [drm:vlv_get_fifo_size] Pipe C primary C FIFO size: 256
>[  348.738213] [drm:valleyview_update_wm] Setting FIFO watermarks - C: plane=8, cursor=0, SR: plane=0, cursor=0
>[  348.747914] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  348.747960] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[  348.747969] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  348.747974] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  348.747980] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[  348.747985] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[  348.747990] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[  348.747997] [drm:check_crtc_state] [CRTC:20]
>[  348.748007] [drm:check_crtc_state] [CRTC:25]
>[  348.748012] [drm:check_crtc_state] [CRTC:30]
>[  353.759008] [drm:drm_mode_addfb2] [FB:116]
>[  353.972714] [drm:drm_mode_setcrtc] [CRTC:30]
>[  353.972731] [drm:drm_mode_setcrtc] [CONNECTOR:47:HDMI-A-2]
>[  353.972739] [drm:intel_crtc_set_config] [CRTC:30] [FB:116] #connectors=1 (x y) (0 0)
>[  353.972749] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[  353.972757] [drm:drm_mode_debug_printmodeline] Modeline 119:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  353.972763] [drm:drm_mode_debug_printmodeline] Modeline 119:"1440x576" 50 54000 1440 1464 1592 1728 576 581 586 625 0x40 0xa
>[  353.972768] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:30], mode_changed=1, fb_changed=1
>[  353.972774] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[  353.972781] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 4, prepare: 4, disable: 0
>[  353.972787] [drm:connected_sink_compute_bpp] [CONNECTOR:47:HDMI-A-2] checking for sink bpp constrains
>[  353.972797] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[  353.972801] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[  353.972807] [drm:intel_modeset_pipe_config] plane bpp: 18, pipe bpp: 24, dithering: 1
>[  353.972813] [drm:intel_dump_pipe_config] [CRTC:30][modeset] config for pipe C
>[  353.972816] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[  353.972820] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 1
>[  353.972826] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  353.972831] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  353.972835] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  353.972839] [drm:intel_dump_pipe_config] audio: 1, infoframes: 1
>[  353.972842] [drm:intel_dump_pipe_config] requested mode:
>[  353.972848] [drm:drm_mode_debug_printmodeline] Modeline 0:"1440x576" 50 54000 1440 1464 1592 1728 576 581 586 625 0x40 0xa
>[  353.972853] [drm:intel_dump_pipe_config] adjusted mode:
>[  353.972859] [drm:drm_mode_debug_printmodeline] Modeline 0:"1440x576" 50 54000 1440 1464 1592 1728 576 581 586 625 0x40 0xa
>[  353.972865] [drm:intel_dump_crtc_timings] crtc timings: 54000 1440 1464 1592 1728 576 581 586 625, type: 0x40 flags: 0xa
>[  353.972869] [drm:intel_dump_pipe_config] port clock: 54000
>[  353.972872] [drm:intel_dump_pipe_config] pipe src size: 1440x576
>[  353.972877] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  353.972882] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  353.972886] [drm:intel_dump_pipe_config] ips: 0
>[  353.972889] [drm:intel_dump_pipe_config] double wide: 0
>[  353.976189] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  353.990818] [drm:valleyview_pipestat_irq_handler [i915]] *ERROR* CPU pipe C FIFO underrun
>[  353.990898] [drm:ilk_audio_codec_disable] Disable audio codec on port D, pipe C
>[  354.036273] [drm:vlv_get_fifo_size] Pipe C primary C FIFO size: 256
>[  354.036282] [drm:valleyview_update_wm] Setting FIFO watermarks - C: plane=0, cursor=0, SR: plane=0, cursor=0
>[  354.046265] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  354.210433] [drm:intel_enable_hdmi] Enabling HDMI audio on pipe C
>[  354.210443] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:HDMI-A-2], [ENCODER:46:TMDS-46]
>[  354.210449] [drm:ilk_audio_codec_enable] Enable audio codec on port D, pipe C, 36 bytes ELD
>[  354.210464] [drm:audio_config_hdmi_pixel_clock] Configuring HDMI audio for pixel clock 54000 (0x00040000)
>[  354.210803] [drm:vlv_get_fifo_size] Pipe C primary C FIFO size: 256
>[  354.210810] [drm:valleyview_update_wm] Setting FIFO watermarks - C: plane=8, cursor=0, SR: plane=0, cursor=0
>[  354.220360] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  354.220402] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[  354.220411] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  354.220417] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  354.220422] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[  354.220427] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[  354.220432] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[  354.220440] [drm:check_crtc_state] [CRTC:20]
>[  354.220449] [drm:check_crtc_state] [CRTC:25]
>[  354.220454] [drm:check_crtc_state] [CRTC:30]
>[  359.231551] [drm:drm_mode_addfb2] [FB:118]
>[  359.441648] [drm:drm_mode_setcrtc] [CRTC:30]
>[  359.441664] [drm:drm_mode_setcrtc] [CONNECTOR:47:HDMI-A-2]
>[  359.441671] [drm:intel_crtc_set_config] [CRTC:30] [FB:118] #connectors=1 (x y) (0 0)
>[  359.441678] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[  359.441685] [drm:drm_mode_debug_printmodeline] Modeline 119:"1440x576" 50 54000 1440 1464 1592 1728 576 581 586 625 0x40 0xa
>[  359.441692] [drm:drm_mode_debug_printmodeline] Modeline 119:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  359.441697] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:30], mode_changed=1, fb_changed=1
>[  359.441702] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[  359.441709] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 4, prepare: 4, disable: 0
>[  359.441715] [drm:connected_sink_compute_bpp] [CONNECTOR:47:HDMI-A-2] checking for sink bpp constrains
>[  359.441729] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[  359.441732] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[  359.441737] [drm:intel_modeset_pipe_config] plane bpp: 18, pipe bpp: 24, dithering: 1
>[  359.441742] [drm:intel_dump_pipe_config] [CRTC:30][modeset] config for pipe C
>[  359.441745] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[  359.441749] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 1
>[  359.441754] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  359.441759] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  359.441763] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  359.441767] [drm:intel_dump_pipe_config] audio: 1, infoframes: 1
>[  359.441770] [drm:intel_dump_pipe_config] requested mode:
>[  359.441776] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  359.441780] [drm:intel_dump_pipe_config] adjusted mode:
>[  359.441786] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  359.441792] [drm:intel_dump_crtc_timings] crtc timings: 78800 1024 1040 1136 1312 768 769 772 800, type: 0x40 flags: 0x5
>[  359.441796] [drm:intel_dump_pipe_config] port clock: 78800
>[  359.441799] [drm:intel_dump_pipe_config] pipe src size: 1024x768
>[  359.441804] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  359.441808] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  359.441811] [drm:intel_dump_pipe_config] ips: 0
>[  359.441814] [drm:intel_dump_pipe_config] double wide: 0
>[  359.445730] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  359.463573] [drm:valleyview_pipestat_irq_handler [i915]] *ERROR* CPU pipe C FIFO underrun
>[  359.463643] [drm:ilk_audio_codec_disable] Disable audio codec on port D, pipe C
>[  359.507654] [drm:vlv_get_fifo_size] Pipe C primary C FIFO size: 256
>[  359.507664] [drm:valleyview_update_wm] Setting FIFO watermarks - C: plane=0, cursor=0, SR: plane=0, cursor=0
>[  359.517651] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  359.681806] [drm:intel_enable_hdmi] Enabling HDMI audio on pipe C
>[  359.681816] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:HDMI-A-2], [ENCODER:46:TMDS-46]
>[  359.681823] [drm:ilk_audio_codec_enable] Enable audio codec on port D, pipe C, 36 bytes ELD
>[  359.681838] [drm:audio_config_hdmi_pixel_clock] HDMI audio pixel clock setting for 78800 not found, falling back to defaults
>[  359.681842] [drm:audio_config_hdmi_pixel_clock] Configuring HDMI audio for pixel clock 25200 (0x00010000)
>[  359.681913] [drm:vlv_get_fifo_size] Pipe C primary C FIFO size: 256
>[  359.681919] [drm:valleyview_update_wm] Setting FIFO watermarks - C: plane=8, cursor=0, SR: plane=0, cursor=0
>[  359.691677] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  359.691723] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[  359.691732] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  359.691737] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  359.691742] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[  359.691746] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[  359.691751] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[  359.691758] [drm:check_crtc_state] [CRTC:20]
>[  359.691764] [drm:check_crtc_state] [CRTC:25]
>[  359.691769] [drm:check_crtc_state] [CRTC:30]
>[  364.702939] [drm:drm_mode_addfb2] [FB:116]
>[  364.912993] [drm:drm_mode_setcrtc] [CRTC:30]
>[  364.913009] [drm:drm_mode_setcrtc] [CONNECTOR:47:HDMI-A-2]
>[  364.913017] [drm:intel_crtc_set_config] [CRTC:30] [FB:116] #connectors=1 (x y) (0 0)
>[  364.913027] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[  364.913036] [drm:drm_mode_debug_printmodeline] Modeline 119:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  364.913042] [drm:drm_mode_debug_printmodeline] Modeline 119:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  364.913047] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:30], mode_changed=1, fb_changed=1
>[  364.913054] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[  364.913061] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 4, prepare: 4, disable: 0
>[  364.913068] [drm:connected_sink_compute_bpp] [CONNECTOR:47:HDMI-A-2] checking for sink bpp constrains
>[  364.913084] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[  364.913088] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[  364.913094] [drm:intel_modeset_pipe_config] plane bpp: 18, pipe bpp: 24, dithering: 1
>[  364.913103] [drm:intel_dump_pipe_config] [CRTC:30][modeset] config for pipe C
>[  364.913107] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[  364.913110] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 1
>[  364.913115] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  364.913120] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  364.913124] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  364.913128] [drm:intel_dump_pipe_config] audio: 1, infoframes: 1
>[  364.913131] [drm:intel_dump_pipe_config] requested mode:
>[  364.913137] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  364.913141] [drm:intel_dump_pipe_config] adjusted mode:
>[  364.913147] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  364.913153] [drm:intel_dump_crtc_timings] crtc timings: 75000 1024 1048 1184 1328 768 771 777 806, type: 0x40 flags: 0xa
>[  364.913156] [drm:intel_dump_pipe_config] port clock: 75000
>[  364.913160] [drm:intel_dump_pipe_config] pipe src size: 1024x768
>[  364.913164] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  364.913172] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  364.913176] [drm:intel_dump_pipe_config] ips: 0
>[  364.913179] [drm:intel_dump_pipe_config] double wide: 0
>[  364.916951] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  364.929275] [drm:valleyview_pipestat_irq_handler [i915]] *ERROR* CPU pipe C FIFO underrun
>[  364.929354] [drm:ilk_audio_codec_disable] Disable audio codec on port D, pipe C
>[  364.967035] [drm:vlv_get_fifo_size] Pipe C primary C FIFO size: 256
>[  364.967045] [drm:valleyview_update_wm] Setting FIFO watermarks - C: plane=0, cursor=0, SR: plane=0, cursor=0
>[  364.977106] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  365.139136] [drm:intel_enable_hdmi] Enabling HDMI audio on pipe C
>[  365.139145] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:HDMI-A-2], [ENCODER:46:TMDS-46]
>[  365.139152] [drm:ilk_audio_codec_enable] Enable audio codec on port D, pipe C, 36 bytes ELD
>[  365.139166] [drm:audio_config_hdmi_pixel_clock] HDMI audio pixel clock setting for 75000 not found, falling back to defaults
>[  365.139170] [drm:audio_config_hdmi_pixel_clock] Configuring HDMI audio for pixel clock 25200 (0x00010000)
>[  365.139371] [drm:vlv_get_fifo_size] Pipe C primary C FIFO size: 256
>[  365.139377] [drm:valleyview_update_wm] Setting FIFO watermarks - C: plane=8, cursor=0, SR: plane=0, cursor=0
>[  365.149054] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  365.149101] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[  365.149110] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  365.149115] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  365.149120] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[  365.149125] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[  365.149130] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[  365.149138] [drm:check_crtc_state] [CRTC:20]
>[  365.149146] [drm:check_crtc_state] [CRTC:25]
>[  365.149151] [drm:check_crtc_state] [CRTC:30]
>[  370.160094] [drm:drm_mode_addfb2] [FB:118]
>[  370.370445] [drm:drm_mode_setcrtc] [CRTC:30]
>[  370.370460] [drm:drm_mode_setcrtc] [CONNECTOR:47:HDMI-A-2]
>[  370.370468] [drm:intel_crtc_set_config] [CRTC:30] [FB:118] #connectors=1 (x y) (0 0)
>[  370.370475] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[  370.370482] [drm:drm_mode_debug_printmodeline] Modeline 119:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  370.370489] [drm:drm_mode_debug_printmodeline] Modeline 119:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  370.370493] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:30], mode_changed=1, fb_changed=1
>[  370.370499] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[  370.370505] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 4, prepare: 4, disable: 0
>[  370.370512] [drm:connected_sink_compute_bpp] [CONNECTOR:47:HDMI-A-2] checking for sink bpp constrains
>[  370.370525] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[  370.370529] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[  370.370534] [drm:intel_modeset_pipe_config] plane bpp: 18, pipe bpp: 24, dithering: 1
>[  370.370539] [drm:intel_dump_pipe_config] [CRTC:30][modeset] config for pipe C
>[  370.370542] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[  370.370546] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 1
>[  370.370551] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  370.370556] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  370.370560] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  370.370564] [drm:intel_dump_pipe_config] audio: 1, infoframes: 1
>[  370.370567] [drm:intel_dump_pipe_config] requested mode:
>[  370.370573] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  370.370577] [drm:intel_dump_pipe_config] adjusted mode:
>[  370.370583] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  370.370589] [drm:intel_dump_crtc_timings] crtc timings: 65000 1024 1048 1184 1344 768 771 777 806, type: 0x40 flags: 0xa
>[  370.370593] [drm:intel_dump_pipe_config] port clock: 65000
>[  370.370597] [drm:intel_dump_pipe_config] pipe src size: 1024x768
>[  370.370601] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  370.370607] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  370.370610] [drm:intel_dump_pipe_config] ips: 0
>[  370.370613] [drm:intel_dump_pipe_config] double wide: 0
>[  370.374328] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  370.375016] [drm:valleyview_pipestat_irq_handler [i915]] *ERROR* CPU pipe C FIFO underrun
>[  370.375067] [drm:ilk_audio_codec_disable] Disable audio codec on port D, pipe C
>[  370.414403] [drm:vlv_get_fifo_size] Pipe C primary C FIFO size: 256
>[  370.414414] [drm:valleyview_update_wm] Setting FIFO watermarks - C: plane=0, cursor=0, SR: plane=0, cursor=0
>[  370.424402] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  370.588587] [drm:intel_enable_hdmi] Enabling HDMI audio on pipe C
>[  370.588598] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:HDMI-A-2], [ENCODER:46:TMDS-46]
>[  370.588605] [drm:ilk_audio_codec_enable] Enable audio codec on port D, pipe C, 36 bytes ELD
>[  370.588619] [drm:audio_config_hdmi_pixel_clock] HDMI audio pixel clock setting for 65000 not found, falling back to defaults
>[  370.588639] [drm:audio_config_hdmi_pixel_clock] Configuring HDMI audio for pixel clock 25200 (0x00010000)
>[  370.588889] [drm:vlv_get_fifo_size] Pipe C primary C FIFO size: 256
>[  370.588895] [drm:valleyview_update_wm] Setting FIFO watermarks - C: plane=8, cursor=0, SR: plane=0, cursor=0
>[  370.598538] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  370.598583] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[  370.598591] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  370.598597] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  370.598603] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[  370.598608] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[  370.598613] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[  370.598619] [drm:check_crtc_state] [CRTC:20]
>[  370.598626] [drm:check_crtc_state] [CRTC:25]
>[  370.598631] [drm:check_crtc_state] [CRTC:30]
>[  375.609566] [drm:drm_mode_addfb2] [FB:116]
>[  375.806901] [drm:drm_mode_setcrtc] [CRTC:30]
>[  375.806917] [drm:drm_mode_setcrtc] [CONNECTOR:47:HDMI-A-2]
>[  375.806924] [drm:intel_crtc_set_config] [CRTC:30] [FB:116] #connectors=1 (x y) (0 0)
>[  375.806931] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[  375.806938] [drm:drm_mode_debug_printmodeline] Modeline 119:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  375.806945] [drm:drm_mode_debug_printmodeline] Modeline 119:"1440x480" 60 54054 1440 1472 1596 1716 480 489 495 525 0x40 0xa
>[  375.806949] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:30], mode_changed=1, fb_changed=1
>[  375.806955] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[  375.806961] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 4, prepare: 4, disable: 0
>[  375.806968] [drm:connected_sink_compute_bpp] [CONNECTOR:47:HDMI-A-2] checking for sink bpp constrains
>[  375.806976] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[  375.806979] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[  375.806985] [drm:intel_modeset_pipe_config] plane bpp: 18, pipe bpp: 24, dithering: 1
>[  375.806989] [drm:intel_dump_pipe_config] [CRTC:30][modeset] config for pipe C
>[  375.806993] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[  375.806996] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 1
>[  375.807001] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  375.807006] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  375.807011] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  375.807014] [drm:intel_dump_pipe_config] audio: 1, infoframes: 1
>[  375.807017] [drm:intel_dump_pipe_config] requested mode:
>[  375.807024] [drm:drm_mode_debug_printmodeline] Modeline 0:"1440x480" 60 54054 1440 1472 1596 1716 480 489 495 525 0x40 0xa
>[  375.807027] [drm:intel_dump_pipe_config] adjusted mode:
>[  375.807033] [drm:drm_mode_debug_printmodeline] Modeline 0:"1440x480" 60 54054 1440 1472 1596 1716 480 489 495 525 0x40 0xa
>[  375.807040] [drm:intel_dump_crtc_timings] crtc timings: 54054 1440 1472 1596 1716 480 489 495 525, type: 0x40 flags: 0xa
>[  375.807044] [drm:intel_dump_pipe_config] port clock: 54054
>[  375.807047] [drm:intel_dump_pipe_config] pipe src size: 1440x480
>[  375.807051] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  375.807056] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  375.807059] [drm:intel_dump_pipe_config] ips: 0
>[  375.807062] [drm:intel_dump_pipe_config] double wide: 0
>[  375.810750] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  375.817665] [drm:valleyview_pipestat_irq_handler [i915]] *ERROR* CPU pipe C FIFO underrun
>[  375.817728] [drm:ilk_audio_codec_disable] Disable audio codec on port D, pipe C
>[  375.859803] [drm:vlv_get_fifo_size] Pipe C primary C FIFO size: 256
>[  375.859812] [drm:valleyview_update_wm] Setting FIFO watermarks - C: plane=0, cursor=0, SR: plane=0, cursor=0
>[  375.869772] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  376.033964] [drm:intel_enable_hdmi] Enabling HDMI audio on pipe C
>[  376.033976] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:HDMI-A-2], [ENCODER:46:TMDS-46]
>[  376.033982] [drm:ilk_audio_codec_enable] Enable audio codec on port D, pipe C, 36 bytes ELD
>[  376.034131] [drm:audio_config_hdmi_pixel_clock] Configuring HDMI audio for pixel clock 54054 (0x00050000)
>[  376.034201] [drm:vlv_get_fifo_size] Pipe C primary C FIFO size: 256
>[  376.034207] [drm:valleyview_update_wm] Setting FIFO watermarks - C: plane=8, cursor=0, SR: plane=0, cursor=0
>[  376.043802] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  376.043848] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[  376.043857] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  376.043862] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  376.043869] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[  376.043874] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[  376.043879] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[  376.043884] [drm:check_crtc_state] [CRTC:20]
>[  376.043891] [drm:check_crtc_state] [CRTC:25]
>[  376.043896] [drm:check_crtc_state] [CRTC:30]
>[  381.054852] [drm:drm_mode_addfb2] [FB:118]
>[  381.250952] [drm:drm_mode_setcrtc] [CRTC:30]
>[  381.250969] [drm:drm_mode_setcrtc] [CONNECTOR:47:HDMI-A-2]
>[  381.250978] [drm:intel_crtc_set_config] [CRTC:30] [FB:118] #connectors=1 (x y) (0 0)
>[  381.250987] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[  381.250995] [drm:drm_mode_debug_printmodeline] Modeline 119:"1440x480" 60 54054 1440 1472 1596 1716 480 489 495 525 0x40 0xa
>[  381.251003] [drm:drm_mode_debug_printmodeline] Modeline 119:"1440x480" 60 54000 1440 1472 1596 1716 480 489 495 525 0x40 0xa
>[  381.251009] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:30], mode_changed=1, fb_changed=1
>[  381.251016] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[  381.251022] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 4, prepare: 4, disable: 0
>[  381.251029] [drm:connected_sink_compute_bpp] [CONNECTOR:47:HDMI-A-2] checking for sink bpp constrains
>[  381.251038] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[  381.251041] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[  381.251047] [drm:intel_modeset_pipe_config] plane bpp: 18, pipe bpp: 24, dithering: 1
>[  381.251070] [drm:intel_dump_pipe_config] [CRTC:30][modeset] config for pipe C
>[  381.251074] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[  381.251078] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 1
>[  381.251083] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  381.251087] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  381.251092] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  381.251096] [drm:intel_dump_pipe_config] audio: 1, infoframes: 1
>[  381.251099] [drm:intel_dump_pipe_config] requested mode:
>[  381.251105] [drm:drm_mode_debug_printmodeline] Modeline 0:"1440x480" 60 54000 1440 1472 1596 1716 480 489 495 525 0x40 0xa
>[  381.251108] [drm:intel_dump_pipe_config] adjusted mode:
>[  381.251114] [drm:drm_mode_debug_printmodeline] Modeline 0:"1440x480" 60 54000 1440 1472 1596 1716 480 489 495 525 0x40 0xa
>[  381.251121] [drm:intel_dump_crtc_timings] crtc timings: 54000 1440 1472 1596 1716 480 489 495 525, type: 0x40 flags: 0xa
>[  381.251124] [drm:intel_dump_pipe_config] port clock: 54000
>[  381.251128] [drm:intel_dump_pipe_config] pipe src size: 1440x480
>[  381.251132] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  381.251136] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  381.251140] [drm:intel_dump_pipe_config] ips: 0
>[  381.251143] [drm:intel_dump_pipe_config] double wide: 0
>[  381.255071] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  381.263417] [drm:valleyview_pipestat_irq_handler [i915]] *ERROR* CPU pipe C FIFO underrun
>[  381.263485] [drm:ilk_audio_codec_disable] Disable audio codec on port D, pipe C
>[  381.305228] [drm:vlv_get_fifo_size] Pipe C primary C FIFO size: 256
>[  381.305237] [drm:valleyview_update_wm] Setting FIFO watermarks - C: plane=0, cursor=0, SR: plane=0, cursor=0
>[  381.315145] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  381.479243] [drm:intel_enable_hdmi] Enabling HDMI audio on pipe C
>[  381.479254] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:HDMI-A-2], [ENCODER:46:TMDS-46]
>[  381.479261] [drm:ilk_audio_codec_enable] Enable audio codec on port D, pipe C, 36 bytes ELD
>[  381.479290] [drm:audio_config_hdmi_pixel_clock] Configuring HDMI audio for pixel clock 54000 (0x00040000)
>[  381.479421] [drm:vlv_get_fifo_size] Pipe C primary C FIFO size: 256
>[  381.479428] [drm:valleyview_update_wm] Setting FIFO watermarks - C: plane=8, cursor=0, SR: plane=0, cursor=0
>[  381.489363] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  381.489408] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[  381.489420] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  381.489425] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  381.489430] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[  381.489435] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[  381.489440] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[  381.489445] [drm:check_crtc_state] [CRTC:20]
>[  381.489451] [drm:check_crtc_state] [CRTC:25]
>[  381.489456] [drm:check_crtc_state] [CRTC:30]
>[  386.500196] [drm:drm_mode_addfb2] [FB:116]
>[  386.686837] [drm:drm_mode_setcrtc] [CRTC:30]
>[  386.686853] [drm:drm_mode_setcrtc] [CONNECTOR:47:HDMI-A-2]
>[  386.686861] [drm:intel_crtc_set_config] [CRTC:30] [FB:116] #connectors=1 (x y) (0 0)
>[  386.686870] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[  386.686878] [drm:drm_mode_debug_printmodeline] Modeline 119:"1440x480" 60 54000 1440 1472 1596 1716 480 489 495 525 0x40 0xa
>[  386.686885] [drm:drm_mode_debug_printmodeline] Modeline 119:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[  386.686889] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:30], mode_changed=1, fb_changed=1
>[  386.686896] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[  386.686902] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 4, prepare: 4, disable: 0
>[  386.686909] [drm:connected_sink_compute_bpp] [CONNECTOR:47:HDMI-A-2] checking for sink bpp constrains
>[  386.686923] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[  386.686927] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[  386.686933] [drm:intel_modeset_pipe_config] plane bpp: 18, pipe bpp: 24, dithering: 1
>[  386.686939] [drm:intel_dump_pipe_config] [CRTC:30][modeset] config for pipe C
>[  386.686942] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[  386.686946] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 1
>[  386.686951] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  386.686955] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  386.686960] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  386.686964] [drm:intel_dump_pipe_config] audio: 1, infoframes: 1
>[  386.686967] [drm:intel_dump_pipe_config] requested mode:
>[  386.686973] [drm:drm_mode_debug_printmodeline] Modeline 0:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[  386.686976] [drm:intel_dump_pipe_config] adjusted mode:
>[  386.686982] [drm:drm_mode_debug_printmodeline] Modeline 0:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[  386.686988] [drm:intel_dump_crtc_timings] crtc timings: 57284 832 864 928 1152 624 625 628 667, type: 0x40 flags: 0xa
>[  386.686992] [drm:intel_dump_pipe_config] port clock: 57284
>[  386.686995] [drm:intel_dump_pipe_config] pipe src size: 832x624
>[  386.687000] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  386.687004] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  386.687007] [drm:intel_dump_pipe_config] ips: 0
>[  386.687010] [drm:intel_dump_pipe_config] double wide: 0
>[  386.690505] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  386.697335] [drm:valleyview_pipestat_irq_handler [i915]] *ERROR* CPU pipe C FIFO underrun
>[  386.697400] [drm:ilk_audio_codec_disable] Disable audio codec on port D, pipe C
>[  386.739519] [drm:vlv_get_fifo_size] Pipe C primary C FIFO size: 256
>[  386.739529] [drm:valleyview_update_wm] Setting FIFO watermarks - C: plane=0, cursor=0, SR: plane=0, cursor=0
>[  386.749513] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  386.913616] [drm:intel_enable_hdmi] Enabling HDMI audio on pipe C
>[  386.913627] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:HDMI-A-2], [ENCODER:46:TMDS-46]
>[  386.913633] [drm:ilk_audio_codec_enable] Enable audio codec on port D, pipe C, 36 bytes ELD
>[  386.913646] [drm:audio_config_hdmi_pixel_clock] HDMI audio pixel clock setting for 57284 not found, falling back to defaults
>[  386.913651] [drm:audio_config_hdmi_pixel_clock] Configuring HDMI audio for pixel clock 25200 (0x00010000)
>[  386.913871] [drm:vlv_get_fifo_size] Pipe C primary C FIFO size: 256
>[  386.913876] [drm:valleyview_update_wm] Setting FIFO watermarks - C: plane=8, cursor=0, SR: plane=0, cursor=0
>[  386.923542] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  386.923581] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[  386.923590] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  386.923595] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  386.923600] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[  386.923606] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[  386.923611] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[  386.923616] [drm:check_crtc_state] [CRTC:20]
>[  386.923626] [drm:check_crtc_state] [CRTC:25]
>[  386.923631] [drm:check_crtc_state] [CRTC:30]
>[  391.934649] [drm:drm_mode_addfb2] [FB:118]
>[  392.111149] [drm:drm_mode_setcrtc] [CRTC:30]
>[  392.111167] [drm:drm_mode_setcrtc] [CONNECTOR:47:HDMI-A-2]
>[  392.111175] [drm:intel_crtc_set_config] [CRTC:30] [FB:118] #connectors=1 (x y) (0 0)
>[  392.111184] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[  392.111192] [drm:drm_mode_debug_printmodeline] Modeline 119:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[  392.111199] [drm:drm_mode_debug_printmodeline] Modeline 119:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  392.111203] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:30], mode_changed=1, fb_changed=1
>[  392.111210] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[  392.111216] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 4, prepare: 4, disable: 0
>[  392.111222] [drm:connected_sink_compute_bpp] [CONNECTOR:47:HDMI-A-2] checking for sink bpp constrains
>[  392.111237] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[  392.111240] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[  392.111246] [drm:intel_modeset_pipe_config] plane bpp: 18, pipe bpp: 24, dithering: 1
>[  392.111254] [drm:intel_dump_pipe_config] [CRTC:30][modeset] config for pipe C
>[  392.111257] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[  392.111261] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 1
>[  392.111267] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  392.111271] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  392.111276] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  392.111279] [drm:intel_dump_pipe_config] audio: 1, infoframes: 1
>[  392.111283] [drm:intel_dump_pipe_config] requested mode:
>[  392.111289] [drm:drm_mode_debug_printmodeline] Modeline 0:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  392.111292] [drm:intel_dump_pipe_config] adjusted mode:
>[  392.111298] [drm:drm_mode_debug_printmodeline] Modeline 0:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  392.111305] [drm:intel_dump_crtc_timings] crtc timings: 49500 800 816 896 1056 600 601 604 625, type: 0x40 flags: 0x5
>[  392.111309] [drm:intel_dump_pipe_config] port clock: 49500
>[  392.111312] [drm:intel_dump_pipe_config] pipe src size: 800x600
>[  392.111317] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  392.111322] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  392.111326] [drm:intel_dump_pipe_config] ips: 0
>[  392.111329] [drm:intel_dump_pipe_config] double wide: 0
>[  392.114801] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  392.117564] [drm:valleyview_pipestat_irq_handler [i915]] *ERROR* CPU pipe C FIFO underrun
>[  392.117636] [drm:ilk_audio_codec_disable] Disable audio codec on port D, pipe C
>[  392.154967] [drm:vlv_get_fifo_size] Pipe C primary C FIFO size: 256
>[  392.154977] [drm:valleyview_update_wm] Setting FIFO watermarks - C: plane=0, cursor=0, SR: plane=0, cursor=0
>[  392.164883] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  392.328978] [drm:intel_enable_hdmi] Enabling HDMI audio on pipe C
>[  392.328987] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:HDMI-A-2], [ENCODER:46:TMDS-46]
>[  392.328994] [drm:ilk_audio_codec_enable] Enable audio codec on port D, pipe C, 36 bytes ELD
>[  392.329008] [drm:audio_config_hdmi_pixel_clock] HDMI audio pixel clock setting for 49500 not found, falling back to defaults
>[  392.329013] [drm:audio_config_hdmi_pixel_clock] Configuring HDMI audio for pixel clock 25200 (0x00010000)
>[  392.329213] [drm:vlv_get_fifo_size] Pipe C primary C FIFO size: 256
>[  392.329221] [drm:valleyview_update_wm] Setting FIFO watermarks - C: plane=8, cursor=0, SR: plane=0, cursor=0
>[  392.338901] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  392.338954] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[  392.338963] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  392.338970] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  392.338975] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[  392.338979] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[  392.338984] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[  392.338989] [drm:check_crtc_state] [CRTC:20]
>[  392.338996] [drm:check_crtc_state] [CRTC:25]
>[  392.339001] [drm:check_crtc_state] [CRTC:30]
>[  397.349787] [drm:drm_mode_addfb2] [FB:116]
>[  397.526388] [drm:drm_mode_setcrtc] [CRTC:30]
>[  397.526403] [drm:drm_mode_setcrtc] [CONNECTOR:47:HDMI-A-2]
>[  397.526410] [drm:intel_crtc_set_config] [CRTC:30] [FB:116] #connectors=1 (x y) (0 0)
>[  397.526418] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[  397.526425] [drm:drm_mode_debug_printmodeline] Modeline 119:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  397.526432] [drm:drm_mode_debug_printmodeline] Modeline 119:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[  397.526436] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:30], mode_changed=1, fb_changed=1
>[  397.526442] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[  397.526448] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 4, prepare: 4, disable: 0
>[  397.526455] [drm:connected_sink_compute_bpp] [CONNECTOR:47:HDMI-A-2] checking for sink bpp constrains
>[  397.526469] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[  397.526473] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[  397.526478] [drm:intel_modeset_pipe_config] plane bpp: 18, pipe bpp: 24, dithering: 1
>[  397.526482] [drm:intel_dump_pipe_config] [CRTC:30][modeset] config for pipe C
>[  397.526486] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[  397.526489] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 1
>[  397.526494] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  397.526499] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  397.526504] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  397.526507] [drm:intel_dump_pipe_config] audio: 1, infoframes: 1
>[  397.526510] [drm:intel_dump_pipe_config] requested mode:
>[  397.526516] [drm:drm_mode_debug_printmodeline] Modeline 0:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[  397.526520] [drm:intel_dump_pipe_config] adjusted mode:
>[  397.526526] [drm:drm_mode_debug_printmodeline] Modeline 0:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[  397.526533] [drm:intel_dump_crtc_timings] crtc timings: 50000 800 856 976 1040 600 637 643 666, type: 0x40 flags: 0x5
>[  397.526536] [drm:intel_dump_pipe_config] port clock: 50000
>[  397.526540] [drm:intel_dump_pipe_config] pipe src size: 800x600
>[  397.526544] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  397.526549] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  397.526552] [drm:intel_dump_pipe_config] ips: 0
>[  397.526555] [drm:intel_dump_pipe_config] double wide: 0
>[  397.530159] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  397.541811] [drm:valleyview_pipestat_irq_handler [i915]] *ERROR* CPU pipe C FIFO underrun
>[  397.541891] [drm:ilk_audio_codec_disable] Disable audio codec on port D, pipe C
>[  397.579242] [drm:vlv_get_fifo_size] Pipe C primary C FIFO size: 256
>[  397.579253] [drm:valleyview_update_wm] Setting FIFO watermarks - C: plane=0, cursor=0, SR: plane=0, cursor=0
>[  397.589237] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  397.751343] [drm:intel_enable_hdmi] Enabling HDMI audio on pipe C
>[  397.751353] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:HDMI-A-2], [ENCODER:46:TMDS-46]
>[  397.751360] [drm:ilk_audio_codec_enable] Enable audio codec on port D, pipe C, 36 bytes ELD
>[  397.751389] [drm:audio_config_hdmi_pixel_clock] HDMI audio pixel clock setting for 50000 not found, falling back to defaults
>[  397.751394] [drm:audio_config_hdmi_pixel_clock] Configuring HDMI audio for pixel clock 25200 (0x00010000)
>[  397.751521] [drm:vlv_get_fifo_size] Pipe C primary C FIFO size: 256
>[  397.751528] [drm:valleyview_update_wm] Setting FIFO watermarks - C: plane=8, cursor=0, SR: plane=0, cursor=0
>[  397.761264] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  397.761311] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[  397.761320] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  397.761325] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  397.761332] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[  397.761337] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[  397.761342] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[  397.761347] [drm:check_crtc_state] [CRTC:20]
>[  397.761354] [drm:check_crtc_state] [CRTC:25]
>[  397.761359] [drm:check_crtc_state] [CRTC:30]
>[  402.772163] [drm:drm_mode_addfb2] [FB:118]
>[  402.949130] [drm:drm_mode_setcrtc] [CRTC:30]
>[  402.949147] [drm:drm_mode_setcrtc] [CONNECTOR:47:HDMI-A-2]
>[  402.949155] [drm:intel_crtc_set_config] [CRTC:30] [FB:118] #connectors=1 (x y) (0 0)
>[  402.949165] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[  402.949173] [drm:drm_mode_debug_printmodeline] Modeline 119:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[  402.949181] [drm:drm_mode_debug_printmodeline] Modeline 119:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  402.949187] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:30], mode_changed=1, fb_changed=1
>[  402.949193] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[  402.949200] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 4, prepare: 4, disable: 0
>[  402.949206] [drm:connected_sink_compute_bpp] [CONNECTOR:47:HDMI-A-2] checking for sink bpp constrains
>[  402.949219] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[  402.949223] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[  402.949228] [drm:intel_modeset_pipe_config] plane bpp: 18, pipe bpp: 24, dithering: 1
>[  402.949233] [drm:intel_dump_pipe_config] [CRTC:30][modeset] config for pipe C
>[  402.949236] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[  402.949240] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 1
>[  402.949245] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  402.949250] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  402.949254] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  402.949258] [drm:intel_dump_pipe_config] audio: 1, infoframes: 1
>[  402.949261] [drm:intel_dump_pipe_config] requested mode:
>[  402.949267] [drm:drm_mode_debug_printmodeline] Modeline 0:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  402.949271] [drm:intel_dump_pipe_config] adjusted mode:
>[  402.949277] [drm:drm_mode_debug_printmodeline] Modeline 0:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  402.949283] [drm:intel_dump_crtc_timings] crtc timings: 40000 800 840 968 1056 600 601 605 628, type: 0x40 flags: 0x5
>[  402.949286] [drm:intel_dump_pipe_config] port clock: 40000
>[  402.949290] [drm:intel_dump_pipe_config] pipe src size: 800x600
>[  402.949294] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  402.949299] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  402.949302] [drm:intel_dump_pipe_config] ips: 0
>[  402.949305] [drm:intel_dump_pipe_config] double wide: 0
>[  402.953711] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  402.958836] [drm:valleyview_pipestat_irq_handler [i915]] *ERROR* CPU pipe C FIFO underrun
>[  402.958900] [drm:ilk_audio_codec_disable] Disable audio codec on port D, pipe C
>[  402.996601] [drm:vlv_get_fifo_size] Pipe C primary C FIFO size: 256
>[  402.996611] [drm:valleyview_update_wm] Setting FIFO watermarks - C: plane=0, cursor=0, SR: plane=0, cursor=0
>[  403.006595] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  403.168704] [drm:intel_enable_hdmi] Enabling HDMI audio on pipe C
>[  403.168714] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:HDMI-A-2], [ENCODER:46:TMDS-46]
>[  403.168721] [drm:ilk_audio_codec_enable] Enable audio codec on port D, pipe C, 36 bytes ELD
>[  403.168735] [drm:audio_config_hdmi_pixel_clock] HDMI audio pixel clock setting for 40000 not found, falling back to defaults
>[  403.168739] [drm:audio_config_hdmi_pixel_clock] Configuring HDMI audio for pixel clock 25200 (0x00010000)
>[  403.168937] [drm:vlv_get_fifo_size] Pipe C primary C FIFO size: 256
>[  403.168943] [drm:valleyview_update_wm] Setting FIFO watermarks - C: plane=8, cursor=0, SR: plane=0, cursor=0
>[  403.178619] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  403.178665] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[  403.178672] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  403.178679] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  403.178685] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[  403.178690] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[  403.178695] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[  403.178701] [drm:check_crtc_state] [CRTC:20]
>[  403.178722] [drm:check_crtc_state] [CRTC:25]
>[  403.178728] [drm:check_crtc_state] [CRTC:30]
>[  408.189517] [drm:drm_mode_addfb2] [FB:116]
>[  408.366242] [drm:drm_mode_setcrtc] [CRTC:30]
>[  408.366258] [drm:drm_mode_setcrtc] [CONNECTOR:47:HDMI-A-2]
>[  408.366265] [drm:intel_crtc_set_config] [CRTC:30] [FB:116] #connectors=1 (x y) (0 0)
>[  408.366272] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[  408.366280] [drm:drm_mode_debug_printmodeline] Modeline 119:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  408.366286] [drm:drm_mode_debug_printmodeline] Modeline 119:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  408.366291] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:30], mode_changed=1, fb_changed=1
>[  408.366296] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[  408.366303] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 4, prepare: 4, disable: 0
>[  408.366309] [drm:connected_sink_compute_bpp] [CONNECTOR:47:HDMI-A-2] checking for sink bpp constrains
>[  408.366323] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[  408.366326] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[  408.366332] [drm:intel_modeset_pipe_config] plane bpp: 18, pipe bpp: 24, dithering: 1
>[  408.366336] [drm:intel_dump_pipe_config] [CRTC:30][modeset] config for pipe C
>[  408.366340] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[  408.366343] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 1
>[  408.366348] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  408.366353] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  408.366358] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  408.366361] [drm:intel_dump_pipe_config] audio: 1, infoframes: 1
>[  408.366364] [drm:intel_dump_pipe_config] requested mode:
>[  408.366370] [drm:drm_mode_debug_printmodeline] Modeline 0:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  408.366374] [drm:intel_dump_pipe_config] adjusted mode:
>[  408.366380] [drm:drm_mode_debug_printmodeline] Modeline 0:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  408.366387] [drm:intel_dump_crtc_timings] crtc timings: 36000 800 824 896 1024 600 601 603 625, type: 0x40 flags: 0x5
>[  408.366390] [drm:intel_dump_pipe_config] port clock: 36000
>[  408.366394] [drm:intel_dump_pipe_config] pipe src size: 800x600
>[  408.366398] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  408.366403] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  408.366406] [drm:intel_dump_pipe_config] ips: 0
>[  408.366409] [drm:intel_dump_pipe_config] double wide: 0
>[  408.369931] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  408.370418] [drm:valleyview_pipestat_irq_handler [i915]] *ERROR* CPU pipe C FIFO underrun
>[  408.370459] [drm:ilk_audio_codec_disable] Disable audio codec on port D, pipe C
>[  408.412106] [drm:vlv_get_fifo_size] Pipe C primary C FIFO size: 256
>[  408.412115] [drm:valleyview_update_wm] Setting FIFO watermarks - C: plane=0, cursor=0, SR: plane=0, cursor=0
>[  408.422040] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  408.586058] [drm:intel_enable_hdmi] Enabling HDMI audio on pipe C
>[  408.586069] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:HDMI-A-2], [ENCODER:46:TMDS-46]
>[  408.586076] [drm:ilk_audio_codec_enable] Enable audio codec on port D, pipe C, 36 bytes ELD
>[  408.586088] [drm:audio_config_hdmi_pixel_clock] HDMI audio pixel clock setting for 36000 not found, falling back to defaults
>[  408.586093] [drm:audio_config_hdmi_pixel_clock] Configuring HDMI audio for pixel clock 25200 (0x00010000)
>[  408.586290] [drm:vlv_get_fifo_size] Pipe C primary C FIFO size: 256
>[  408.586297] [drm:valleyview_update_wm] Setting FIFO watermarks - C: plane=8, cursor=0, SR: plane=0, cursor=0
>[  408.595990] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  408.596038] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[  408.596045] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  408.596051] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  408.596056] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[  408.596061] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[  408.596066] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[  408.596071] [drm:check_crtc_state] [CRTC:20]
>[  408.596078] [drm:check_crtc_state] [CRTC:25]
>[  408.596083] [drm:check_crtc_state] [CRTC:30]
>[  413.606625] [drm:drm_mode_addfb2] [FB:118]
>[  413.768979] [drm:drm_mode_setcrtc] [CRTC:30]
>[  413.768995] [drm:drm_mode_setcrtc] [CONNECTOR:47:HDMI-A-2]
>[  413.769002] [drm:intel_crtc_set_config] [CRTC:30] [FB:118] #connectors=1 (x y) (0 0)
>[  413.769009] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[  413.769016] [drm:drm_mode_debug_printmodeline] Modeline 119:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  413.769022] [drm:drm_mode_debug_printmodeline] Modeline 119:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  413.769027] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:30], mode_changed=1, fb_changed=1
>[  413.769033] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[  413.769039] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 4, prepare: 4, disable: 0
>[  413.769046] [drm:connected_sink_compute_bpp] [CONNECTOR:47:HDMI-A-2] checking for sink bpp constrains
>[  413.769054] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[  413.769057] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[  413.769063] [drm:intel_modeset_pipe_config] plane bpp: 18, pipe bpp: 24, dithering: 1
>[  413.769067] [drm:intel_dump_pipe_config] [CRTC:30][modeset] config for pipe C
>[  413.769071] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[  413.769074] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 1
>[  413.769079] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  413.769084] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  413.769089] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  413.769092] [drm:intel_dump_pipe_config] audio: 1, infoframes: 1
>[  413.769095] [drm:intel_dump_pipe_config] requested mode:
>[  413.769102] [drm:drm_mode_debug_printmodeline] Modeline 0:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  413.769105] [drm:intel_dump_pipe_config] adjusted mode:
>[  413.769111] [drm:drm_mode_debug_printmodeline] Modeline 0:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  413.769117] [drm:intel_dump_crtc_timings] crtc timings: 27000 720 732 796 864 576 581 586 625, type: 0x40 flags: 0xa
>[  413.769121] [drm:intel_dump_pipe_config] port clock: 27000
>[  413.769124] [drm:intel_dump_pipe_config] pipe src size: 720x576
>[  413.769129] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  413.769133] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  413.769137] [drm:intel_dump_pipe_config] ips: 0
>[  413.769140] [drm:intel_dump_pipe_config] double wide: 0
>[  413.773286] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  413.789880] [drm:valleyview_pipestat_irq_handler [i915]] *ERROR* CPU pipe C FIFO underrun
>[  413.789948] [drm:ilk_audio_codec_disable] Disable audio codec on port D, pipe C
>[  413.831322] [drm:vlv_get_fifo_size] Pipe C primary C FIFO size: 256
>[  413.831332] [drm:valleyview_update_wm] Setting FIFO watermarks - C: plane=0, cursor=0, SR: plane=0, cursor=0
>[  413.841329] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  414.005416] [drm:intel_enable_hdmi] Enabling HDMI audio on pipe C
>[  414.005426] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:HDMI-A-2], [ENCODER:46:TMDS-46]
>[  414.005432] [drm:ilk_audio_codec_enable] Enable audio codec on port D, pipe C, 36 bytes ELD
>[  414.005586] [drm:audio_config_hdmi_pixel_clock] Configuring HDMI audio for pixel clock 27000 (0x00020000)
>[  414.005650] [drm:vlv_get_fifo_size] Pipe C primary C FIFO size: 256
>[  414.005655] [drm:valleyview_update_wm] Setting FIFO watermarks - C: plane=40, cursor=0, SR: plane=0, cursor=0
>[  414.015344] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  414.015393] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[  414.015404] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  414.015413] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  414.015418] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[  414.015423] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[  414.015427] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[  414.015433] [drm:check_crtc_state] [CRTC:20]
>[  414.015440] [drm:check_crtc_state] [CRTC:25]
>[  414.015445] [drm:check_crtc_state] [CRTC:30]
>[  419.026243] [drm:drm_mode_addfb2] [FB:116]
>[  419.157095] [drm:drm_mode_setcrtc] [CRTC:30]
>[  419.157110] [drm:drm_mode_setcrtc] [CONNECTOR:47:HDMI-A-2]
>[  419.157117] [drm:intel_crtc_set_config] [CRTC:30] [FB:116] #connectors=1 (x y) (0 0)
>[  419.157124] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[  419.157131] [drm:drm_mode_debug_printmodeline] Modeline 119:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  419.157138] [drm:drm_mode_debug_printmodeline] Modeline 119:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  419.157143] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:30], mode_changed=1, fb_changed=1
>[  419.157148] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[  419.157155] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 4, prepare: 4, disable: 0
>[  419.157161] [drm:connected_sink_compute_bpp] [CONNECTOR:47:HDMI-A-2] checking for sink bpp constrains
>[  419.157167] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[  419.157170] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[  419.157175] [drm:intel_modeset_pipe_config] plane bpp: 18, pipe bpp: 24, dithering: 1
>[  419.157180] [drm:intel_dump_pipe_config] [CRTC:30][modeset] config for pipe C
>[  419.157183] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[  419.157187] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 1
>[  419.157192] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  419.157197] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  419.157201] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  419.157205] [drm:intel_dump_pipe_config] audio: 1, infoframes: 1
>[  419.157208] [drm:intel_dump_pipe_config] requested mode:
>[  419.157214] [drm:drm_mode_debug_printmodeline] Modeline 0:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  419.157218] [drm:intel_dump_pipe_config] adjusted mode:
>[  419.157224] [drm:drm_mode_debug_printmodeline] Modeline 0:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  419.157230] [drm:intel_dump_crtc_timings] crtc timings: 27027 720 736 798 858 480 489 495 525, type: 0x40 flags: 0xa
>[  419.157233] [drm:intel_dump_pipe_config] port clock: 27027
>[  419.157237] [drm:intel_dump_pipe_config] pipe src size: 720x480
>[  419.157241] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  419.157246] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  419.157249] [drm:intel_dump_pipe_config] ips: 0
>[  419.157252] [drm:intel_dump_pipe_config] double wide: 0
>[  419.160696] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  419.178255] [drm:valleyview_pipestat_irq_handler [i915]] *ERROR* CPU pipe C FIFO underrun
>[  419.178332] [drm:ilk_audio_codec_disable] Disable audio codec on port D, pipe C
>[  419.223802] [drm:vlv_get_fifo_size] Pipe C primary C FIFO size: 256
>[  419.223813] [drm:valleyview_update_wm] Setting FIFO watermarks - C: plane=0, cursor=0, SR: plane=0, cursor=0
>[  419.233745] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  419.397766] [drm:intel_enable_hdmi] Enabling HDMI audio on pipe C
>[  419.397776] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:HDMI-A-2], [ENCODER:46:TMDS-46]
>[  419.397782] [drm:ilk_audio_codec_enable] Enable audio codec on port D, pipe C, 36 bytes ELD
>[  419.397795] [drm:audio_config_hdmi_pixel_clock] Configuring HDMI audio for pixel clock 27027 (0x00030000)
>[  419.397863] [drm:vlv_get_fifo_size] Pipe C primary C FIFO size: 256
>[  419.397869] [drm:valleyview_update_wm] Setting FIFO watermarks - C: plane=32, cursor=0, SR: plane=0, cursor=0
>[  419.407694] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  419.407738] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[  419.407746] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  419.407752] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  419.407757] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[  419.407762] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[  419.407766] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[  419.407772] [drm:check_crtc_state] [CRTC:20]
>[  419.407777] [drm:check_crtc_state] [CRTC:25]
>[  419.407782] [drm:check_crtc_state] [CRTC:30]
>[  424.418576] [drm:drm_mode_addfb2] [FB:118]
>[  424.549449] [drm:drm_mode_setcrtc] [CRTC:30]
>[  424.549465] [drm:drm_mode_setcrtc] [CONNECTOR:47:HDMI-A-2]
>[  424.549472] [drm:intel_crtc_set_config] [CRTC:30] [FB:118] #connectors=1 (x y) (0 0)
>[  424.549479] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[  424.549487] [drm:drm_mode_debug_printmodeline] Modeline 119:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  424.549493] [drm:drm_mode_debug_printmodeline] Modeline 119:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  424.549498] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:30], mode_changed=1, fb_changed=1
>[  424.549503] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[  424.549510] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 4, prepare: 4, disable: 0
>[  424.549516] [drm:connected_sink_compute_bpp] [CONNECTOR:47:HDMI-A-2] checking for sink bpp constrains
>[  424.549522] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[  424.549526] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[  424.549532] [drm:intel_modeset_pipe_config] plane bpp: 18, pipe bpp: 24, dithering: 1
>[  424.549537] [drm:intel_dump_pipe_config] [CRTC:30][modeset] config for pipe C
>[  424.549540] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[  424.549544] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 1
>[  424.549549] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  424.549553] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  424.549558] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  424.549562] [drm:intel_dump_pipe_config] audio: 1, infoframes: 1
>[  424.549565] [drm:intel_dump_pipe_config] requested mode:
>[  424.549571] [drm:drm_mode_debug_printmodeline] Modeline 0:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  424.549574] [drm:intel_dump_pipe_config] adjusted mode:
>[  424.549580] [drm:drm_mode_debug_printmodeline] Modeline 0:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  424.549586] [drm:intel_dump_crtc_timings] crtc timings: 27000 720 736 798 858 480 489 495 525, type: 0x40 flags: 0xa
>[  424.549590] [drm:intel_dump_pipe_config] port clock: 27000
>[  424.549593] [drm:intel_dump_pipe_config] pipe src size: 720x480
>[  424.549598] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  424.549602] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  424.549605] [drm:intel_dump_pipe_config] ips: 0
>[  424.549609] [drm:intel_dump_pipe_config] double wide: 0
>[  424.552937] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  424.560444] [drm:valleyview_pipestat_irq_handler [i915]] *ERROR* CPU pipe C FIFO underrun
>[  424.560510] [drm:ilk_audio_codec_disable] Disable audio codec on port D, pipe C
>[  424.602015] [drm:vlv_get_fifo_size] Pipe C primary C FIFO size: 256
>[  424.602024] [drm:valleyview_update_wm] Setting FIFO watermarks - C: plane=0, cursor=0, SR: plane=0, cursor=0
>[  424.612133] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  424.776107] [drm:intel_enable_hdmi] Enabling HDMI audio on pipe C
>[  424.776117] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:HDMI-A-2], [ENCODER:46:TMDS-46]
>[  424.776124] [drm:ilk_audio_codec_enable] Enable audio codec on port D, pipe C, 36 bytes ELD
>[  424.776276] [drm:audio_config_hdmi_pixel_clock] Configuring HDMI audio for pixel clock 27000 (0x00020000)
>[  424.776340] [drm:vlv_get_fifo_size] Pipe C primary C FIFO size: 256
>[  424.776347] [drm:valleyview_update_wm] Setting FIFO watermarks - C: plane=40, cursor=0, SR: plane=0, cursor=0
>[  424.786044] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  424.786096] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[  424.786104] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  424.786110] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  424.786116] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[  424.786121] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[  424.786126] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[  424.786133] [drm:check_crtc_state] [CRTC:20]
>[  424.786141] [drm:check_crtc_state] [CRTC:25]
>[  424.786146] [drm:check_crtc_state] [CRTC:30]
>[  429.796877] [drm:drm_mode_addfb2] [FB:116]
>[  429.920971] [drm:drm_mode_setcrtc] [CRTC:30]
>[  429.920987] [drm:drm_mode_setcrtc] [CONNECTOR:47:HDMI-A-2]
>[  429.920994] [drm:intel_crtc_set_config] [CRTC:30] [FB:116] #connectors=1 (x y) (0 0)
>[  429.921001] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[  429.921008] [drm:drm_mode_debug_printmodeline] Modeline 119:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  429.921015] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  429.921020] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:30], mode_changed=1, fb_changed=1
>[  429.921025] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[  429.921032] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 4, prepare: 4, disable: 0
>[  429.921038] [drm:connected_sink_compute_bpp] [CONNECTOR:47:HDMI-A-2] checking for sink bpp constrains
>[  429.921052] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[  429.921056] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[  429.921061] [drm:intel_modeset_pipe_config] plane bpp: 18, pipe bpp: 24, dithering: 1
>[  429.921066] [drm:intel_dump_pipe_config] [CRTC:30][modeset] config for pipe C
>[  429.921069] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[  429.921073] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 1
>[  429.921078] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  429.921082] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  429.921087] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  429.921091] [drm:intel_dump_pipe_config] audio: 1, infoframes: 1
>[  429.921094] [drm:intel_dump_pipe_config] requested mode:
>[  429.921100] [drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  429.921104] [drm:intel_dump_pipe_config] adjusted mode:
>[  429.921110] [drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  429.921116] [drm:intel_dump_crtc_timings] crtc timings: 31500 640 656 720 840 480 481 484 500, type: 0x40 flags: 0xa
>[  429.921120] [drm:intel_dump_pipe_config] port clock: 31500
>[  429.921124] [drm:intel_dump_pipe_config] pipe src size: 640x480
>[  429.921129] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  429.921133] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  429.921136] [drm:intel_dump_pipe_config] ips: 0
>[  429.921140] [drm:intel_dump_pipe_config] double wide: 0
>[  429.925323] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  429.927607] [drm:valleyview_pipestat_irq_handler [i915]] *ERROR* CPU pipe C FIFO underrun
>[  429.927679] [drm:ilk_audio_codec_disable] Disable audio codec on port D, pipe C
>[  429.969367] [drm:vlv_get_fifo_size] Pipe C primary C FIFO size: 256
>[  429.969377] [drm:valleyview_update_wm] Setting FIFO watermarks - C: plane=0, cursor=0, SR: plane=0, cursor=0
>[  429.979353] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  430.143545] [drm:intel_enable_hdmi] Enabling HDMI audio on pipe C
>[  430.143554] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:HDMI-A-2], [ENCODER:46:TMDS-46]
>[  430.143561] [drm:ilk_audio_codec_enable] Enable audio codec on port D, pipe C, 36 bytes ELD
>[  430.143573] [drm:audio_config_hdmi_pixel_clock] HDMI audio pixel clock setting for 31500 not found, falling back to defaults
>[  430.143577] [drm:audio_config_hdmi_pixel_clock] Configuring HDMI audio for pixel clock 25200 (0x00010000)
>[  430.143644] [drm:vlv_get_fifo_size] Pipe C primary C FIFO size: 256
>[  430.143651] [drm:valleyview_update_wm] Setting FIFO watermarks - C: plane=8, cursor=0, SR: plane=0, cursor=0
>[  430.153377] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  430.153424] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[  430.153433] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  430.153438] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  430.153445] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[  430.153450] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[  430.153455] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[  430.153462] [drm:check_crtc_state] [CRTC:20]
>[  430.153476] [drm:check_crtc_state] [CRTC:25]
>[  430.153481] [drm:check_crtc_state] [CRTC:30]
>[  435.164371] [drm:drm_mode_addfb2] [FB:118]
>[  435.288704] [drm:drm_mode_setcrtc] [CRTC:30]
>[  435.288720] [drm:drm_mode_setcrtc] [CONNECTOR:47:HDMI-A-2]
>[  435.288727] [drm:intel_crtc_set_config] [CRTC:30] [FB:118] #connectors=1 (x y) (0 0)
>[  435.288734] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[  435.288741] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  435.288748] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  435.288752] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:30], mode_changed=1, fb_changed=1
>[  435.288758] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[  435.288765] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 4, prepare: 4, disable: 0
>[  435.288771] [drm:connected_sink_compute_bpp] [CONNECTOR:47:HDMI-A-2] checking for sink bpp constrains
>[  435.288785] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[  435.288788] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[  435.288794] [drm:intel_modeset_pipe_config] plane bpp: 18, pipe bpp: 24, dithering: 1
>[  435.288798] [drm:intel_dump_pipe_config] [CRTC:30][modeset] config for pipe C
>[  435.288801] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[  435.288805] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 1
>[  435.288810] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  435.288815] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  435.288820] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  435.288823] [drm:intel_dump_pipe_config] audio: 1, infoframes: 1
>[  435.288826] [drm:intel_dump_pipe_config] requested mode:
>[  435.288832] [drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  435.288836] [drm:intel_dump_pipe_config] adjusted mode:
>[  435.288842] [drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  435.288848] [drm:intel_dump_crtc_timings] crtc timings: 30240 640 704 768 864 480 483 486 525, type: 0x40 flags: 0xa
>[  435.288851] [drm:intel_dump_pipe_config] port clock: 30240
>[  435.288855] [drm:intel_dump_pipe_config] pipe src size: 640x480
>[  435.288860] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  435.288864] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  435.288867] [drm:intel_dump_pipe_config] ips: 0
>[  435.288870] [drm:intel_dump_pipe_config] double wide: 0
>[  435.292613] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  435.303071] [drm:valleyview_pipestat_irq_handler [i915]] *ERROR* CPU pipe C FIFO underrun
>[  435.303143] [drm:ilk_audio_codec_disable] Disable audio codec on port D, pipe C
>[  435.340727] [drm:vlv_get_fifo_size] Pipe C primary C FIFO size: 256
>[  435.340737] [drm:valleyview_update_wm] Setting FIFO watermarks - C: plane=0, cursor=0, SR: plane=0, cursor=0
>[  435.350780] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  435.514788] [drm:intel_enable_hdmi] Enabling HDMI audio on pipe C
>[  435.514800] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:HDMI-A-2], [ENCODER:46:TMDS-46]
>[  435.514806] [drm:ilk_audio_codec_enable] Enable audio codec on port D, pipe C, 36 bytes ELD
>[  435.514819] [drm:audio_config_hdmi_pixel_clock] HDMI audio pixel clock setting for 30240 not found, falling back to defaults
>[  435.514825] [drm:audio_config_hdmi_pixel_clock] Configuring HDMI audio for pixel clock 25200 (0x00010000)
>[  435.514893] [drm:vlv_get_fifo_size] Pipe C primary C FIFO size: 256
>[  435.514900] [drm:valleyview_update_wm] Setting FIFO watermarks - C: plane=8, cursor=0, SR: plane=0, cursor=0
>[  435.524718] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  435.524762] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[  435.524771] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  435.524787] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  435.524794] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[  435.524799] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[  435.524804] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[  435.524810] [drm:check_crtc_state] [CRTC:20]
>[  435.524816] [drm:check_crtc_state] [CRTC:25]
>[  435.524822] [drm:check_crtc_state] [CRTC:30]
>[  440.535505] [drm:drm_mode_addfb2] [FB:116]
>[  440.659981] [drm:drm_mode_setcrtc] [CRTC:30]
>[  440.659997] [drm:drm_mode_setcrtc] [CONNECTOR:47:HDMI-A-2]
>[  440.660005] [drm:intel_crtc_set_config] [CRTC:30] [FB:116] #connectors=1 (x y) (0 0)
>[  440.660012] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[  440.660021] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  440.660029] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  440.660033] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:30], mode_changed=1, fb_changed=1
>[  440.660040] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[  440.660046] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 4, prepare: 4, disable: 0
>[  440.660053] [drm:connected_sink_compute_bpp] [CONNECTOR:47:HDMI-A-2] checking for sink bpp constrains
>[  440.660059] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[  440.660063] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[  440.660069] [drm:intel_modeset_pipe_config] plane bpp: 18, pipe bpp: 24, dithering: 1
>[  440.660075] [drm:intel_dump_pipe_config] [CRTC:30][modeset] config for pipe C
>[  440.660078] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[  440.660082] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 1
>[  440.660088] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  440.660092] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  440.660097] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  440.660101] [drm:intel_dump_pipe_config] audio: 1, infoframes: 1
>[  440.660104] [drm:intel_dump_pipe_config] requested mode:
>[  440.660110] [drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  440.660113] [drm:intel_dump_pipe_config] adjusted mode:
>[  440.660119] [drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  440.660126] [drm:intel_dump_crtc_timings] crtc timings: 25200 640 656 752 800 480 490 492 525, type: 0x40 flags: 0xa
>[  440.660130] [drm:intel_dump_pipe_config] port clock: 25200
>[  440.660133] [drm:intel_dump_pipe_config] pipe src size: 640x480
>[  440.660137] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  440.660142] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  440.660145] [drm:intel_dump_pipe_config] ips: 0
>[  440.660148] [drm:intel_dump_pipe_config] double wide: 0
>[  440.664001] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  440.672483] [drm:valleyview_pipestat_irq_handler [i915]] *ERROR* CPU pipe C FIFO underrun
>[  440.672548] [drm:ilk_audio_codec_disable] Disable audio codec on port D, pipe C
>[  440.712031] [drm:vlv_get_fifo_size] Pipe C primary C FIFO size: 256
>[  440.712041] [drm:valleyview_update_wm] Setting FIFO watermarks - C: plane=0, cursor=0, SR: plane=0, cursor=0
>[  440.722031] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  440.886144] [drm:intel_enable_hdmi] Enabling HDMI audio on pipe C
>[  440.886154] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:HDMI-A-2], [ENCODER:46:TMDS-46]
>[  440.886161] [drm:ilk_audio_codec_enable] Enable audio codec on port D, pipe C, 36 bytes ELD
>[  440.886366] [drm:audio_config_hdmi_pixel_clock] Configuring HDMI audio for pixel clock 25200 (0x00010000)
>[  440.886430] [drm:vlv_get_fifo_size] Pipe C primary C FIFO size: 256
>[  440.886435] [drm:valleyview_update_wm] Setting FIFO watermarks - C: plane=48, cursor=0, SR: plane=0, cursor=0
>[  440.896054] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  440.896095] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[  440.896104] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  440.896109] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  440.896116] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[  440.896120] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[  440.896125] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[  440.896131] [drm:check_crtc_state] [CRTC:20]
>[  440.896141] [drm:check_crtc_state] [CRTC:25]
>[  440.896146] [drm:check_crtc_state] [CRTC:30]
>[  445.906838] [drm:drm_mode_addfb2] [FB:118]
>[  446.031494] [drm:drm_mode_setcrtc] [CRTC:30]
>[  446.031510] [drm:drm_mode_setcrtc] [CONNECTOR:47:HDMI-A-2]
>[  446.031518] [drm:intel_crtc_set_config] [CRTC:30] [FB:118] #connectors=1 (x y) (0 0)
>[  446.031526] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[  446.031534] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  446.031540] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  446.031546] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:30], mode_changed=1, fb_changed=1
>[  446.031553] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[  446.031560] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 4, prepare: 4, disable: 0
>[  446.031567] [drm:connected_sink_compute_bpp] [CONNECTOR:47:HDMI-A-2] checking for sink bpp constrains
>[  446.031574] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[  446.031577] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[  446.031583] [drm:intel_modeset_pipe_config] plane bpp: 18, pipe bpp: 24, dithering: 1
>[  446.031591] [drm:intel_dump_pipe_config] [CRTC:30][modeset] config for pipe C
>[  446.031594] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[  446.031598] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 1
>[  446.031604] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  446.031608] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  446.031613] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  446.031617] [drm:intel_dump_pipe_config] audio: 1, infoframes: 1
>[  446.031620] [drm:intel_dump_pipe_config] requested mode:
>[  446.031626] [drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  446.031629] [drm:intel_dump_pipe_config] adjusted mode:
>[  446.031635] [drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  446.031641] [drm:intel_dump_crtc_timings] crtc timings: 25175 640 656 752 800 480 490 492 525, type: 0x40 flags: 0xa
>[  446.031645] [drm:intel_dump_pipe_config] port clock: 25175
>[  446.031648] [drm:intel_dump_pipe_config] pipe src size: 640x480
>[  446.031652] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  446.031657] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  446.031660] [drm:intel_dump_pipe_config] ips: 0
>[  446.031663] [drm:intel_dump_pipe_config] double wide: 0
>[  446.035294] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  446.049001] [drm:valleyview_pipestat_irq_handler [i915]] *ERROR* CPU pipe C FIFO underrun
>[  446.049067] [drm:ilk_audio_codec_disable] Disable audio codec on port D, pipe C
>[  446.090379] [drm:vlv_get_fifo_size] Pipe C primary C FIFO size: 256
>[  446.090389] [drm:valleyview_update_wm] Setting FIFO watermarks - C: plane=0, cursor=0, SR: plane=0, cursor=0
>[  446.100370] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  446.264555] [drm:intel_enable_hdmi] Enabling HDMI audio on pipe C
>[  446.264565] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:HDMI-A-2], [ENCODER:46:TMDS-46]
>[  446.264571] [drm:ilk_audio_codec_enable] Enable audio codec on port D, pipe C, 36 bytes ELD
>[  446.264867] [drm:audio_config_hdmi_pixel_clock] Configuring HDMI audio for pixel clock 25175 (0x00000000)
>[  446.264930] [drm:vlv_get_fifo_size] Pipe C primary C FIFO size: 256
>[  446.264936] [drm:valleyview_update_wm] Setting FIFO watermarks - C: plane=48, cursor=0, SR: plane=0, cursor=0
>[  446.274400] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  446.274444] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[  446.274453] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  446.274458] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  446.274463] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[  446.274468] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[  446.274473] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[  446.274487] [drm:check_crtc_state] [CRTC:20]
>[  446.274497] [drm:check_crtc_state] [CRTC:25]
>[  446.274501] [drm:check_crtc_state] [CRTC:30]
>[  451.285332] [drm:drm_mode_addfb2] [FB:116]
>[  451.396952] [drm:drm_mode_setcrtc] [CRTC:30]
>[  451.396967] [drm:drm_mode_setcrtc] [CONNECTOR:47:HDMI-A-2]
>[  451.396974] [drm:intel_crtc_set_config] [CRTC:30] [FB:116] #connectors=1 (x y) (0 0)
>[  451.396983] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[  451.396990] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  451.396997] [drm:drm_mode_debug_printmodeline] Modeline 119:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  451.397001] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:30], mode_changed=1, fb_changed=1
>[  451.397007] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[  451.397014] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 4, prepare: 4, disable: 0
>[  451.397020] [drm:connected_sink_compute_bpp] [CONNECTOR:47:HDMI-A-2] checking for sink bpp constrains
>[  451.397033] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[  451.397036] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[  451.397041] [drm:intel_modeset_pipe_config] plane bpp: 18, pipe bpp: 24, dithering: 1
>[  451.397046] [drm:intel_dump_pipe_config] [CRTC:30][modeset] config for pipe C
>[  451.397049] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[  451.397053] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 1
>[  451.397058] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  451.397063] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  451.397067] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  451.397071] [drm:intel_dump_pipe_config] audio: 1, infoframes: 1
>[  451.397074] [drm:intel_dump_pipe_config] requested mode:
>[  451.397080] [drm:drm_mode_debug_printmodeline] Modeline 0:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  451.397083] [drm:intel_dump_pipe_config] adjusted mode:
>[  451.397090] [drm:drm_mode_debug_printmodeline] Modeline 0:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  451.397096] [drm:intel_dump_crtc_timings] crtc timings: 28320 720 738 846 900 400 412 414 449, type: 0x40 flags: 0x6
>[  451.397100] [drm:intel_dump_pipe_config] port clock: 28320
>[  451.397103] [drm:intel_dump_pipe_config] pipe src size: 720x400
>[  451.397109] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  451.397115] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  451.397118] [drm:intel_dump_pipe_config] ips: 0
>[  451.397122] [drm:intel_dump_pipe_config] double wide: 0
>[  451.400702] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  451.415571] [drm:valleyview_pipestat_irq_handler [i915]] *ERROR* CPU pipe C FIFO underrun
>[  451.415657] [drm:ilk_audio_codec_disable] Disable audio codec on port D, pipe C
>[  451.457715] [drm:vlv_get_fifo_size] Pipe C primary C FIFO size: 256
>[  451.457724] [drm:valleyview_update_wm] Setting FIFO watermarks - C: plane=0, cursor=0, SR: plane=0, cursor=0
>[  451.467809] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  451.631811] [drm:intel_enable_hdmi] Enabling HDMI audio on pipe C
>[  451.631821] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:HDMI-A-2], [ENCODER:46:TMDS-46]
>[  451.631828] [drm:ilk_audio_codec_enable] Enable audio codec on port D, pipe C, 36 bytes ELD
>[  451.631843] [drm:audio_config_hdmi_pixel_clock] HDMI audio pixel clock setting for 28320 not found, falling back to defaults
>[  451.631848] [drm:audio_config_hdmi_pixel_clock] Configuring HDMI audio for pixel clock 25200 (0x00010000)
>[  451.632042] [drm:vlv_get_fifo_size] Pipe C primary C FIFO size: 256
>[  451.632048] [drm:valleyview_update_wm] Setting FIFO watermarks - C: plane=24, cursor=0, SR: plane=0, cursor=0
>[  451.641736] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  451.641782] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[  451.641792] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  451.641797] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  451.641802] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[  451.641807] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[  451.641812] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[  451.641817] [drm:check_crtc_state] [CRTC:20]
>[  451.641826] [drm:check_crtc_state] [CRTC:25]
>[  451.641843] [drm:check_crtc_state] [CRTC:30]
>[  456.652473] [drm:intel_crtc_set_config] [CRTC:30] [NOFB]
>[  456.652489] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:30], mode_changed=1, fb_changed=0
>[  456.652497] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [NOCRTC]
>[  456.652502] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] encoder changed, full mode switch
>[  456.652508] [drm:intel_modeset_stage_output_state] [ENCODER:46:TMDS-46] crtc changed, full mode switch
>[  456.652516] [drm:intel_modeset_stage_output_state] [CRTC:30] disabled, full mode switch
>[  456.652522] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 0, prepare: 0, disable: 4
>[  456.655921] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  456.667141] [drm:valleyview_pipestat_irq_handler [i915]] *ERROR* CPU pipe C FIFO underrun
>[  456.667201] [drm:ilk_audio_codec_disable] Disable audio codec on port D, pipe C
>[  456.707096] [drm:vlv_get_fifo_size] Pipe C primary C FIFO size: 256
>[  456.707105] [drm:valleyview_update_wm] Setting FIFO watermarks - C: plane=0, cursor=0, SR: plane=0, cursor=0
>[  456.717018] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  456.727000] [drm:vlv_update_cdclk] Current CD clock rate: 200000 kHz
>[  456.727012] [drm:intel_display_power_put] disabling dpio-common-d
>[  456.735039] [drm:intel_display_power_put] disabling dpio-common-bc
>[  456.743005] [drm:intel_display_power_put] disabling pipe-a
>[  456.751095] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  456.751103] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  456.751108] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[  456.751112] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[  456.751116] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[  456.751121] [drm:check_crtc_state] [CRTC:20]
>[  456.751128] [drm:check_crtc_state] [CRTC:25]
>[  456.751132] [drm:check_crtc_state] [CRTC:30]
>[  456.751397] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[5] ENCODERS[5]
>[  456.751409] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[5] ENCODERS[5]
>[  456.751418] [drm:drm_mode_getconnector] [CONNECTOR:49:?]
>[  456.751426] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:49:DP-2]
>[  456.751432] [drm:intel_dp_detect] [CONNECTOR:49:DP-2]
>[  456.751439] [drm:intel_display_power_get] enabling pipe-a
>[  456.759040] [drm:i915_redisable_vga_power_on] Something enabled VGA plane, disabling it
>[  456.759360] [drm:intel_display_power_get] enabling dpio-common-bc
>[  456.767141] [drm:intel_display_power_get] enabling dpio-common-d
>[  456.775407] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00100000, dig 0x00000000
>[  456.775414] [drm:intel_hpd_irq_handler] digital hpd port C - long
>[  456.775420] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 5 - cnt: 0
>[  456.775459] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port C
>[  456.775522] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[  456.775529] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 2 - cnt: 0
>[  456.776057] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[  456.776069] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 2 - cnt: 1
>[  456.776581] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[  456.776590] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 2 - cnt: 2
>[  456.777121] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[  456.777129] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 2 - cnt: 3
>[  456.777642] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[  456.777650] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 2 - cnt: 4
>[  456.777686] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[  456.778199] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[  456.778208] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 2 - cnt: 5
>[  456.778715] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[  456.778723] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 2 - cnt: 6
>[  456.779247] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[  456.779255] [drm:intel_hpd_irq_handler] HPD interrupt storm detected on PIN 2
>[  456.779773] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[  456.780297] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[  456.780316] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[  456.780464] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00080000, dig 0x00000000
>[  456.780473] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  456.780535] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  456.782501] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[  456.782873] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00080000, dig 0x00000000
>[  456.782881] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  456.782908] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  456.783012] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[  456.783521] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[  456.784050] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[  456.784561] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[  456.784599] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[  456.786494] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[  456.787009] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[  456.787481] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00080000, dig 0x00000000
>[  456.787488] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  456.787523] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  456.787535] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[  456.788049] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[  456.788554] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[  456.788595] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[  456.789995] [drm:intel_display_power_put] disabling dpio-common-d
>[  456.798033] [drm:intel_display_power_put] disabling dpio-common-bc
>[  456.805824] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00080000, dig 0x00000000
>[  456.805836] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  456.805887] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  456.806066] [drm:intel_display_power_put] disabling pipe-a
>[  456.814047] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:49:DP-2] disconnected
>[  456.814074] [drm:drm_mode_getconnector] [CONNECTOR:49:?]
>[  456.814082] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:49:DP-2]
>[  456.814086] [drm:intel_dp_detect] [CONNECTOR:49:DP-2]
>[  456.814091] [drm:intel_display_power_get] enabling pipe-a
>[  456.822094] [drm:i915_redisable_vga_power_on] Something enabled VGA plane, disabling it
>[  456.822414] [drm:intel_display_power_get] enabling dpio-common-bc
>[  456.830049] [drm:intel_display_power_get] enabling dpio-common-d
>[  456.838595] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[  456.838607] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 2 - cnt: 1
>[  456.839137] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[  456.839146] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 2 - cnt: 2
>[  456.839653] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[  456.839662] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 2 - cnt: 3
>[  456.840175] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[  456.840184] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 2 - cnt: 4
>[  456.840577] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00100000, dig 0x00000000
>[  456.840587] [drm:intel_hpd_irq_handler] digital hpd port C - long
>[  456.840593] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 5 - cnt: 1
>[  456.840626] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port C
>[  456.840690] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[  456.840696] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 2 - cnt: 5
>[  456.840716] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[  456.841240] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[  456.841247] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 2 - cnt: 6
>[  456.841756] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[  456.841762] [drm:intel_hpd_irq_handler] HPD interrupt storm detected on PIN 2
>[  456.842274] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[  456.842793] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[  456.843301] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[  456.843321] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[  456.845514] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[  456.846026] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[  456.846534] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[  456.847046] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[  456.847553] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[  456.847580] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[  456.849509] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[  456.850017] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[  456.850528] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[  456.851039] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[  456.851559] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00000040, dig 0x00000000
>[  456.851583] [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064
>[  456.853016] [drm:intel_display_power_put] disabling dpio-common-d
>[  456.861061] [drm:intel_display_power_put] disabling dpio-common-bc
>[  456.869141] [drm:intel_display_power_put] disabling pipe-a
>[  456.877070] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:49:DP-2] disconnected
>[  456.877092] [drm:i915_hotplug_work_func] running encoder hotplug functions
>[  456.877099] [drm:i915_hotplug_work_func] running encoder hotplug functions
>[  456.878478] (null): exiting, ret=0
>[  456.878713] [drm:intel_crtc_set_config] [CRTC:20] [FB:117] #connectors=1 (x y) (0 0)
>[  456.878718] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
>[  456.878720] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[  456.878725] [drm:drm_mode_debug_printmodeline] Modeline 119:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  456.878730] [drm:drm_mode_debug_printmodeline] Modeline 78:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  456.878732] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=1, fb_changed=0
>[  456.878735] [drm:intel_modeset_stage_output_state] [CONNECTOR:41:eDP-1] encoder changed, full mode switch
>[  456.878738] [drm:intel_modeset_stage_output_state] [CONNECTOR:41:eDP-1] to [CRTC:20]
>[  456.878740] [drm:intel_modeset_stage_output_state] [ENCODER:40:TMDS-40] crtc changed, full mode switch
>[  456.878744] [drm:intel_modeset_stage_output_state] [CRTC:20] enabled, full mode switch
>[  456.878748] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  456.878753] [drm:connected_sink_compute_bpp] [CONNECTOR:41:eDP-1] checking for sink bpp constrains
>[  456.878759] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[  456.878761] [drm:intel_dp_compute_config] clamping bpp for eDP panel to BIOS-provided 18
>[  456.878764] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 18
>[  456.878766] [drm:intel_dp_compute_config] DP link bw required 249804 available 432000
>[  456.878770] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 18, dithering: 1
>[  456.878773] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[  456.878774] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[  456.878776] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
>[  456.878779] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  456.878782] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 4850712, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[  456.878785] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  456.878786] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  456.878787] [drm:intel_dump_pipe_config] requested mode:
>[  456.878792] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  456.878793] [drm:intel_dump_pipe_config] adjusted mode:
>[  456.878797] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  456.878802] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  456.878803] [drm:intel_dump_pipe_config] port clock: 270000
>[  456.878805] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  456.878807] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  456.878811] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  456.878812] [drm:intel_dump_pipe_config] ips: 0
>[  456.878814] [drm:intel_dump_pipe_config] double wide: 0
>[  456.878826] [drm:intel_display_power_get] enabling pipe-a
>[  456.886043] [drm:i915_redisable_vga_power_on] Something enabled VGA plane, disabling it
>[  456.886358] [drm:intel_display_power_get] enabling dpio-common-bc
>[  456.894028] [drm:intel_display_power_get] enabling dpio-common-d
>[  456.912080] [drm:vlv_update_cdclk] Current CD clock rate: 266667 kHz
>[  456.936691] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00100000, dig 0x00000000
>[  456.936695] [drm:intel_hpd_irq_handler] digital hpd port C - long
>[  456.936700] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 5 - cnt: 1
>[  456.936725] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port C
>[  456.998124] [drm:vlv_init_panel_power_sequencer] initializing pipe A power sequencer for port C
>[  456.998136] [drm:intel_dp_init_panel_power_sequencer_registers] panel power sequencer register settings: PP_ON 0x87d00001, PP_OFF 0x1f40001, PP_DIV 0x270f05
>[  456.998143] [drm:edp_panel_vdd_on] Turning eDP port C VDD on
>[  456.998147] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  456.998153] [drm:wait_panel_status] mask b800000f value 00000000 status 08000001 control 00000000
>[  457.036923] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00100000, dig 0x00000000
>[  457.036926] [drm:intel_hpd_irq_handler] digital hpd port C - long
>[  457.036930] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 5 - cnt: 2
>[  457.036955] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port C
>[  457.037374] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00100000, dig 0x00000000
>[  457.037382] [drm:intel_hpd_irq_handler] digital hpd port C - long
>[  457.037393] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 5 - cnt: 3
>[  457.037447] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port C
>[  457.037800] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00080000, dig 0x00000000
>[  457.037808] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  457.037870] [drm:intel_dp_hpd_pulse] got hpd irq on port C - short
>[  457.038279] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00080000, dig 0x00000000
>[  457.038287] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  457.038990] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00080000, dig 0x00000000
>[  457.038999] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  457.039379] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00080000, dig 0x00000000
>[  457.039389] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  457.039851] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00080000, dig 0x00000000
>[  457.039860] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  457.041843] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00100000, dig 0x00000000
>[  457.041846] [drm:intel_hpd_irq_handler] digital hpd port C - long
>[  457.041849] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 5 - cnt: 4
>[  457.042556] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00100000, dig 0x00000000
>[  457.042565] [drm:intel_hpd_irq_handler] digital hpd port C - long
>[  457.042574] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 5 - cnt: 5
>[  457.043239] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00080000, dig 0x00000000
>[  457.043249] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  457.043622] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00080000, dig 0x00000000
>[  457.043631] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  457.044071] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00080000, dig 0x00000000
>[  457.044079] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  457.044777] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00080000, dig 0x00000000
>[  457.044786] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  457.045157] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00080000, dig 0x00000000
>[  457.045165] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  457.045585] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00080000, dig 0x00000000
>[  457.045594] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  457.046208] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00080000, dig 0x00000000
>[  457.046218] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  457.046660] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00080000, dig 0x00000000
>[  457.046670] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  457.047118] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00080000, dig 0x00000000
>[  457.047126] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  457.047802] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00080000, dig 0x00000000
>[  457.047812] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  457.048186] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00080000, dig 0x00000000
>[  457.048196] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  457.048672] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00080000, dig 0x00000000
>[  457.048681] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  457.049353] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00080000, dig 0x00000000
>[  457.049363] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  457.049738] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00080000, dig 0x00000000
>[  457.049746] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  457.051322] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00080000, dig 0x00000000
>[  457.051325] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  457.052102] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00080000, dig 0x00000000
>[  457.052105] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  457.053517] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00080000, dig 0x00000000
>[  457.053527] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  457.053904] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00080000, dig 0x00000000
>[  457.053912] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  457.054335] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00080000, dig 0x00000000
>[  457.054344] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  457.054955] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00080000, dig 0x00000000
>[  457.054963] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  457.055429] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00080000, dig 0x00000000
>[  457.055437] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  457.055876] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00080000, dig 0x00000000
>[  457.055884] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  457.056558] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00080000, dig 0x00000000
>[  457.056566] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  457.056945] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00080000, dig 0x00000000
>[  457.056955] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  457.057440] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00080000, dig 0x00000000
>[  457.057450] [drm:intel_hpd_irq_handler] digital hpd port C - short
>[  457.059246] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00100000, dig 0x00000000
>[  457.059250] [drm:intel_hpd_irq_handler] digital hpd port C - long
>[  457.059254] [drm:intel_hpd_irq_handler] Received HPD interrupt on PIN 5 - cnt: 6
>[  457.102042] [drm:intel_hpd_irq_handler] hotplug event received, stat 0x00100000, dig 0x00000000
>[  457.102051] [drm:intel_hpd_irq_handler] digital hpd port C - long
>[  457.102059] [drm:intel_hpd_irq_handler] HPD interrupt storm detected on PIN 5
>[  457.306484] [drm:wait_panel_status] Wait complete
>[  457.306494] [drm:edp_panel_vdd_on] PP_STATUS: 0x00000000 PP_CONTROL: 0xabcd0008
>[  457.306498] [drm:edp_panel_vdd_on] eDP port C panel power wasn't enabled
>[  457.507560] [drm:edp_panel_on] Turn eDP port C panel power on
>[  457.507565] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  457.507575] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0008
>[  457.507578] [drm:wait_panel_status] Wait complete
>[  457.507584] [drm:wait_panel_on] Wait for panel power on
>[  457.507588] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd000b
>[  457.661717] [drm:wait_panel_status] Wait complete
>[  457.661724] [drm:edp_panel_vdd_off_sync] Turning eDP port C VDD off
>[  457.661735] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0003
>[  457.661751] [drm:edp_panel_vdd_on] Turning eDP port C VDD on
>[  457.661757] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
>[  457.737447] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  457.738352] [drm:intel_dp_start_link_train] clock recovery OK
>[  457.739689] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[  457.739938] [drm:vlv_get_fifo_size] Pipe A primary A FIFO size: 256
>[  457.739944] [drm:valleyview_update_wm] Setting FIFO watermarks - A: plane=8, cursor=0, SR: plane=8, cursor=0
>[  457.749449] [drm:intel_set_memory_cxsr] memory self-refresh is enabled
>[  457.749469] [drm:intel_edp_backlight_on] 
>[  457.749471] [drm:intel_panel_enable_backlight] pipe A
>[  457.749476] [drm:intel_panel_actually_set_backlight] set backlight PWM = 7812
>[  457.749488] [drm:intel_psr_match_conditions] PSR disable by flag
>[  457.749513] [drm:intel_connector_check_state] [CONNECTOR:41:eDP-1]
>[  457.749530] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  457.749533] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  457.749536] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[  457.749541] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[  457.749544] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[  457.749547] [drm:check_crtc_state] [CRTC:20]
>[  457.757533] [drm:check_crtc_state] [CRTC:25]
>[  457.757538] [drm:check_crtc_state] [CRTC:30]
>[  457.757551] [drm:intel_crtc_set_config] [CRTC:25] [FB:117] #connectors=1 (x y) (0 0)
>[  457.757556] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
>[  457.757559] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:25], mode_changed=1, fb_changed=0
>[  457.757561] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] encoder changed, full mode switch
>[  457.757563] [drm:intel_modeset_stage_output_state] [CONNECTOR:41:eDP-1] to [CRTC:20]
>[  457.757565] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:25]
>[  457.757568] [drm:intel_modeset_stage_output_state] [ENCODER:38:TMDS-38] crtc changed, full mode switch
>[  457.757572] [drm:intel_modeset_stage_output_state] [CRTC:25] enabled, full mode switch
>[  457.757576] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[  457.757580] [drm:connected_sink_compute_bpp] [CONNECTOR:39:DP-1] checking for sink bpp constrains
>[  457.757585] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[  457.757593] [drm:intel_dp_compute_config] DP link bw 06 lane count 4 clock 162000 bpp 24
>[  457.757595] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400
>[  457.757599] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[  457.757602] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config for pipe B
>[  457.757604] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  457.757606] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  457.757610] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  457.757613] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[  457.757616] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  457.757617] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[  457.757619] [drm:intel_dump_pipe_config] requested mode:
>[  457.757624] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  457.757625] [drm:intel_dump_pipe_config] adjusted mode:
>[  457.757629] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  457.757633] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  457.757634] [drm:intel_dump_pipe_config] port clock: 162000
>[  457.757636] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  457.757638] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  457.757642] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  457.757643] [drm:intel_dump_pipe_config] ips: 0
>[  457.757645] [drm:intel_dump_pipe_config] double wide: 0
>[  457.921524] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  458.001560] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  458.005404] [drm:intel_dp_start_link_train] clock recovery OK
>[  458.084684] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  458.163632] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  458.242659] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  458.322705] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  458.327054] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[  458.327258] [drm:intel_enable_dp] Enabling DP audio on pipe B
>[  458.327264] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:39:DP-1], [ENCODER:38:TMDS-38]
>[  458.327267] [drm:ilk_audio_codec_enable] Enable audio codec on port B, pipe B, 36 bytes ELD
>[  458.327343] [drm:vlv_get_fifo_size] Pipe B primary B FIFO size: 256
>[  458.327349] [drm:valleyview_update_wm] Setting FIFO watermarks - B: plane=8, cursor=0, SR: plane=0, cursor=0
>[  458.336658] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  458.336677] [drm:intel_psr_enable] PSR not supported by this panel
>[  458.336704] [drm:intel_connector_check_state] [CONNECTOR:41:eDP-1]
>[  458.336712] [drm:intel_connector_check_state] [CONNECTOR:39:DP-1]
>[  458.336723] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  458.336726] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  458.336729] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[  458.336734] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[  458.336737] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[  458.336740] [drm:check_crtc_state] [CRTC:20]
>[  458.344672] [drm:check_crtc_state] [CRTC:25]
>[  458.352667] [drm:check_crtc_state] [CRTC:30]
>[  458.352680] [drm:intel_crtc_set_config] [CRTC:30] [FB:117] #connectors=1 (x y) (0 0)
>[  458.352686] [drm:intel_set_config_compute_mode_changes] inactive crtc, full mode set
>[  458.352688] [drm:intel_set_config_compute_mode_changes] modes are different, full mode set
>[  458.352694] [drm:drm_mode_debug_printmodeline] Modeline 119:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  458.352700] [drm:drm_mode_debug_printmodeline] Modeline 115:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  458.352702] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:30], mode_changed=1, fb_changed=0
>[  458.352706] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] encoder changed, full mode switch
>[  458.352708] [drm:intel_modeset_stage_output_state] [CONNECTOR:41:eDP-1] to [CRTC:20]
>[  458.352710] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:25]
>[  458.352712] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[  458.352715] [drm:intel_modeset_stage_output_state] [ENCODER:46:TMDS-46] crtc changed, full mode switch
>[  458.352719] [drm:intel_modeset_stage_output_state] [CRTC:30] enabled, full mode switch
>[  458.352723] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 4, prepare: 4, disable: 0
>[  458.352728] [drm:connected_sink_compute_bpp] [CONNECTOR:47:HDMI-A-2] checking for sink bpp constrains
>[  458.352735] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[  458.352736] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[  458.352739] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[  458.352743] [drm:intel_dump_pipe_config] [CRTC:30][modeset] config for pipe C
>[  458.352744] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[  458.352746] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  458.352749] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  458.352751] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  458.352754] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  458.352756] [drm:intel_dump_pipe_config] audio: 1, infoframes: 1
>[  458.352757] [drm:intel_dump_pipe_config] requested mode:
>[  458.352761] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  458.352762] [drm:intel_dump_pipe_config] adjusted mode:
>[  458.352767] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  458.352770] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  458.352772] [drm:intel_dump_pipe_config] port clock: 148500
>[  458.352773] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  458.352776] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  458.352778] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  458.352779] [drm:intel_dump_pipe_config] ips: 0
>[  458.352781] [drm:intel_dump_pipe_config] double wide: 0
>[  458.516758] [drm:intel_enable_hdmi] Enabling HDMI audio on pipe C
>[  458.516762] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:47:HDMI-A-2], [ENCODER:46:TMDS-46]
>[  458.516764] [drm:ilk_audio_codec_enable] Enable audio codec on port D, pipe C, 36 bytes ELD
>[  458.516776] [drm:audio_config_hdmi_pixel_clock] Configuring HDMI audio for pixel clock 148500 (0x00090000)
>[  458.516856] [drm:vlv_get_fifo_size] Pipe C primary C FIFO size: 256
>[  458.516859] [drm:valleyview_update_wm] Setting FIFO watermarks - C: plane=8, cursor=0, SR: plane=0, cursor=0
>[  458.526738] [drm:intel_set_memory_cxsr] memory self-refresh is disabled
>[  458.526762] [drm:intel_connector_check_state] [CONNECTOR:41:eDP-1]
>[  458.526768] [drm:intel_connector_check_state] [CONNECTOR:39:DP-1]
>[  458.526772] [drm:intel_connector_check_state] [CONNECTOR:47:HDMI-A-2]
>[  458.526777] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  458.526780] [drm:check_encoder_state] [ENCODER:38:TMDS-38]
>[  458.526783] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[  458.526786] [drm:check_encoder_state] [ENCODER:46:TMDS-46]
>[  458.526790] [drm:check_encoder_state] [ENCODER:48:TMDS-48]
>[  458.526793] [drm:check_crtc_state] [CRTC:20]
>[  458.534743] [drm:check_crtc_state] [CRTC:25]
>[  458.542747] [drm:check_crtc_state] [CRTC:30]
>[  458.550764] [drm:intel_crtc_set_config] [CRTC:20] [FB:117] #connectors=1 (x y) (0 0)
>[  458.550768] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=0, fb_changed=0
>[  458.550771] [drm:intel_modeset_stage_output_state] [CONNECTOR:41:eDP-1] to [CRTC:20]
>[  458.550773] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:25]
>[  458.550775] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[  458.550779] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  458.550784] [drm:connected_sink_compute_bpp] [CONNECTOR:41:eDP-1] checking for sink bpp constrains
>[  458.550789] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[  458.550791] [drm:intel_dp_compute_config] clamping bpp for eDP panel to BIOS-provided 18
>[  458.550794] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 18
>[  458.550796] [drm:intel_dp_compute_config] DP link bw required 249804 available 432000
>[  458.550799] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 18, dithering: 1
>[  458.550801] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[  458.550803] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[  458.550804] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
>[  458.550807] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  458.550810] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 4850712, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[  458.550813] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  458.550815] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  458.550816] [drm:intel_dump_pipe_config] requested mode:
>[  458.550820] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  458.550821] [drm:intel_dump_pipe_config] adjusted mode:
>[  458.550826] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  458.550829] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  458.550831] [drm:intel_dump_pipe_config] port clock: 270000
>[  458.550833] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  458.550835] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  458.550837] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  458.550838] [drm:intel_dump_pipe_config] ips: 0
>[  458.550840] [drm:intel_dump_pipe_config] double wide: 0
>[  458.550845] [drm:intel_crtc_set_config] [CRTC:25] [FB:117] #connectors=1 (x y) (0 0)
>[  458.550850] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:25], mode_changed=0, fb_changed=0
>[  458.550852] [drm:intel_modeset_stage_output_state] [CONNECTOR:41:eDP-1] to [CRTC:20]
>[  458.550855] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:25]
>[  458.550857] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[  458.550860] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[  458.550863] [drm:connected_sink_compute_bpp] [CONNECTOR:39:DP-1] checking for sink bpp constrains
>[  458.550868] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[  458.550872] [drm:intel_dp_compute_config] DP link bw 06 lane count 4 clock 162000 bpp 24
>[  458.550874] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400
>[  458.550877] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[  458.550879] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config for pipe B
>[  458.550880] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  458.550882] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  458.550885] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  458.550888] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[  458.550890] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  458.550892] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[  458.550893] [drm:intel_dump_pipe_config] requested mode:
>[  458.550898] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  458.550899] [drm:intel_dump_pipe_config] adjusted mode:
>[  458.550903] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  458.550907] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  458.550908] [drm:intel_dump_pipe_config] port clock: 162000
>[  458.550910] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  458.550912] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  458.550914] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  458.550915] [drm:intel_dump_pipe_config] ips: 0
>[  458.550917] [drm:intel_dump_pipe_config] double wide: 0
>[  458.550921] [drm:intel_crtc_set_config] [CRTC:30] [FB:117] #connectors=1 (x y) (0 0)
>[  458.550924] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:30], mode_changed=0, fb_changed=0
>[  458.550926] [drm:intel_modeset_stage_output_state] [CONNECTOR:41:eDP-1] to [CRTC:20]
>[  458.550928] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:25]
>[  458.550931] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[  458.550933] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 4, prepare: 4, disable: 0
>[  458.550936] [drm:connected_sink_compute_bpp] [CONNECTOR:47:HDMI-A-2] checking for sink bpp constrains
>[  458.550940] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[  458.550941] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[  458.550943] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[  458.550945] [drm:intel_dump_pipe_config] [CRTC:30][modeset] config for pipe C
>[  458.550947] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[  458.550948] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  458.550951] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  458.550954] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  458.550956] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  458.550958] [drm:intel_dump_pipe_config] audio: 1, infoframes: 1
>[  458.550959] [drm:intel_dump_pipe_config] requested mode:
>[  458.550964] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  458.550966] [drm:intel_dump_pipe_config] adjusted mode:
>[  458.550970] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  458.550974] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  458.550976] [drm:intel_dump_pipe_config] port clock: 148500
>[  458.550977] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  458.550980] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  458.550982] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  458.550983] [drm:intel_dump_pipe_config] ips: 0
>[  458.550984] [drm:intel_dump_pipe_config] double wide: 0
>[  458.551849] [drm:intel_dp_get_dpcd] DPCD: 12 0a 82 41 00 00 01 80 02 00 00 00 0f 0b 00
>[  458.552202] [drm:intel_dp_get_dpcd] Detected EDP PSR Panel.
>[  458.553065] [drm:intel_dp_hpd_pulse] ignoring long hpd on eDP port C
>[  458.553088] [drm:intel_crtc_set_config] [CRTC:20] [FB:117] #connectors=1 (x y) (0 0)
>[  458.553098] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=0, fb_changed=0
>[  458.553103] [drm:intel_modeset_stage_output_state] [CONNECTOR:41:eDP-1] to [CRTC:20]
>[  458.553105] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:25]
>[  458.553108] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[  458.553113] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  458.553118] [drm:connected_sink_compute_bpp] [CONNECTOR:41:eDP-1] checking for sink bpp constrains
>[  458.553124] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[  458.553126] [drm:intel_dp_compute_config] clamping bpp for eDP panel to BIOS-provided 18
>[  458.553129] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 18
>[  458.553131] [drm:intel_dp_compute_config] DP link bw required 249804 available 432000
>[  458.553135] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 18, dithering: 1
>[  458.553138] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[  458.553140] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[  458.553141] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
>[  458.553146] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  458.553149] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 4850712, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[  458.553151] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  458.553153] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  458.553154] [drm:intel_dump_pipe_config] requested mode:
>[  458.553160] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  458.553162] [drm:intel_dump_pipe_config] adjusted mode:
>[  458.553166] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  458.553171] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  458.553172] [drm:intel_dump_pipe_config] port clock: 270000
>[  458.553174] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  458.553176] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  458.553179] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  458.553180] [drm:intel_dump_pipe_config] ips: 0
>[  458.553181] [drm:intel_dump_pipe_config] double wide: 0
>[  458.553188] [drm:intel_crtc_set_config] [CRTC:25] [FB:117] #connectors=1 (x y) (0 0)
>[  458.553193] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:25], mode_changed=0, fb_changed=0
>[  458.553197] [drm:intel_modeset_stage_output_state] [CONNECTOR:41:eDP-1] to [CRTC:20]
>[  458.553199] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:25]
>[  458.553201] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[  458.553204] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[  458.553208] [drm:connected_sink_compute_bpp] [CONNECTOR:39:DP-1] checking for sink bpp constrains
>[  458.553211] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[  458.553219] [drm:intel_dp_compute_config] DP link bw 06 lane count 4 clock 162000 bpp 24
>[  458.553220] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400
>[  458.553223] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[  458.553225] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config for pipe B
>[  458.553227] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  458.553228] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  458.553231] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  458.553234] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[  458.553237] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  458.553238] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[  458.553240] [drm:intel_dump_pipe_config] requested mode:
>[  458.553244] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  458.553245] [drm:intel_dump_pipe_config] adjusted mode:
>[  458.553249] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  458.553253] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  458.553255] [drm:intel_dump_pipe_config] port clock: 162000
>[  458.553256] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  458.553258] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  458.553261] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  458.553262] [drm:intel_dump_pipe_config] ips: 0
>[  458.553263] [drm:intel_dump_pipe_config] double wide: 0
>[  458.553267] [drm:intel_crtc_set_config] [CRTC:30] [FB:117] #connectors=1 (x y) (0 0)
>[  458.553272] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:30], mode_changed=0, fb_changed=0
>[  458.553275] [drm:intel_modeset_stage_output_state] [CONNECTOR:41:eDP-1] to [CRTC:20]
>[  458.553278] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:25]
>[  458.553280] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[  458.553282] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 4, prepare: 4, disable: 0
>[  458.553285] [drm:connected_sink_compute_bpp] [CONNECTOR:47:HDMI-A-2] checking for sink bpp constrains
>[  458.553291] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[  458.553293] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[  458.553295] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[  458.553297] [drm:intel_dump_pipe_config] [CRTC:30][modeset] config for pipe C
>[  458.553298] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[  458.553300] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  458.553303] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  458.553306] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  458.553308] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  458.553310] [drm:intel_dump_pipe_config] audio: 1, infoframes: 1
>[  458.553311] [drm:intel_dump_pipe_config] requested mode:
>[  458.553315] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  458.553316] [drm:intel_dump_pipe_config] adjusted mode:
>[  458.553321] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  458.553324] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  458.553326] [drm:intel_dump_pipe_config] port clock: 148500
>[  458.553327] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  458.553330] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  458.553332] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  458.553333] [drm:intel_dump_pipe_config] ips: 0
>[  458.553334] [drm:intel_dump_pipe_config] double wide: 0
>[  458.574879] [drm:i915_gem_object_create_stolen] creating stolen object: size=20000
>[  458.574904] [drm:i915_pages_create_for_stolen] offset=0x0, size=131072
>[  458.575223] [drm:i915_gem_object_create_stolen] creating stolen object: size=20000
>[  458.575230] [drm:i915_pages_create_for_stolen] offset=0x20000, size=131072
>[  458.576813] [drm:i915_gem_object_create_stolen] creating stolen object: size=20000
>[  458.576821] [drm:i915_pages_create_for_stolen] offset=0x40000, size=131072
>[  458.576902] [drm:i915_gem_object_create_stolen] creating stolen object: size=20000
>[  458.576908] [drm:i915_pages_create_for_stolen] offset=0x60000, size=131072
>[  458.578124] [drm:intel_crtc_set_config] [CRTC:20] [FB:117] #connectors=1 (x y) (0 0)
>[  458.578133] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:20], mode_changed=0, fb_changed=0
>[  458.578138] [drm:intel_modeset_stage_output_state] [CONNECTOR:41:eDP-1] to [CRTC:20]
>[  458.578144] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:25]
>[  458.578148] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[  458.578155] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
>[  458.578161] [drm:connected_sink_compute_bpp] [CONNECTOR:41:eDP-1] checking for sink bpp constrains
>[  458.578170] [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[  458.578175] [drm:intel_dp_compute_config] clamping bpp for eDP panel to BIOS-provided 18
>[  458.578180] [drm:intel_dp_compute_config] DP link bw 0a lane count 2 clock 270000 bpp 18
>[  458.578185] [drm:intel_dp_compute_config] DP link bw required 249804 available 432000
>[  458.578193] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 18, dithering: 1
>[  458.578197] [drm:intel_dump_pipe_config] [CRTC:20][modeset] config for pipe A
>[  458.578200] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[  458.578204] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
>[  458.578209] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  458.578214] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 4850712, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[  458.578219] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  458.578222] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  458.578225] [drm:intel_dump_pipe_config] requested mode:
>[  458.578232] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  458.578235] [drm:intel_dump_pipe_config] adjusted mode:
>[  458.578242] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  458.578248] [drm:intel_dump_crtc_timings] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  458.578261] [drm:intel_dump_pipe_config] port clock: 270000
>[  458.578283] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  458.578308] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  458.578327] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  458.578346] [drm:intel_dump_pipe_config] ips: 0
>[  458.578364] [drm:intel_dump_pipe_config] double wide: 0
>[  458.578379] [drm:intel_crtc_set_config] [CRTC:25] [FB:117] #connectors=1 (x y) (0 0)
>[  458.578385] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:25], mode_changed=0, fb_changed=0
>[  458.578392] [drm:intel_modeset_stage_output_state] [CONNECTOR:41:eDP-1] to [CRTC:20]
>[  458.578397] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:25]
>[  458.578403] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[  458.578408] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 2, prepare: 2, disable: 0
>[  458.578415] [drm:connected_sink_compute_bpp] [CONNECTOR:39:DP-1] checking for sink bpp constrains
>[  458.578420] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[  458.578429] [drm:intel_dp_compute_config] DP link bw 06 lane count 4 clock 162000 bpp 24
>[  458.578433] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400
>[  458.578438] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[  458.578442] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config for pipe B
>[  458.578445] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  458.578450] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  458.578454] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  458.578459] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[  458.578464] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  458.578468] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[  458.578471] [drm:intel_dump_pipe_config] requested mode:
>[  458.578477] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  458.578480] [drm:intel_dump_pipe_config] adjusted mode:
>[  458.578486] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  458.578492] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  458.578496] [drm:intel_dump_pipe_config] port clock: 162000
>[  458.578499] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  458.578504] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  458.578508] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  458.578511] [drm:intel_dump_pipe_config] ips: 0
>[  458.578514] [drm:intel_dump_pipe_config] double wide: 0
>[  458.578520] [drm:intel_crtc_set_config] [CRTC:30] [FB:117] #connectors=1 (x y) (0 0)
>[  458.578525] [drm:intel_set_config_compute_mode_changes] computed changes for [CRTC:30], mode_changed=0, fb_changed=0
>[  458.578529] [drm:intel_modeset_stage_output_state] [CONNECTOR:41:eDP-1] to [CRTC:20]
>[  458.578534] [drm:intel_modeset_stage_output_state] [CONNECTOR:39:DP-1] to [CRTC:25]
>[  458.578538] [drm:intel_modeset_stage_output_state] [CONNECTOR:47:HDMI-A-2] to [CRTC:30]
>[  458.578543] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 4, prepare: 4, disable: 0
>[  458.578565] [drm:connected_sink_compute_bpp] [CONNECTOR:47:HDMI-A-2] checking for sink bpp constrains
>[  458.578588] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
>[  458.578607] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
>[  458.578628] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0
>[  458.578648] [drm:intel_dump_pipe_config] [CRTC:30][modeset] config for pipe C
>[  458.578665] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[  458.578687] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  458.578708] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  458.578719] [drm:intel_dump_pipe_config] dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  458.578724] [drm:intel_dump_pipe_config] dp: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  458.578729] [drm:intel_dump_pipe_config] audio: 1, infoframes: 1
>[  458.578733] [drm:intel_dump_pipe_config] requested mode:
>[  458.578739] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  458.578757] [drm:intel_dump_pipe_config] adjusted mode:
>[  458.578763] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  458.578770] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  458.578775] [drm:intel_dump_pipe_config] port clock: 148500
>[  458.578778] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  458.578783] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  458.578787] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  458.578791] [drm:intel_dump_pipe_config] ips: 0
>[  458.578795] [drm:intel_dump_pipe_config] double wide: 0
>[  461.060106] [drm:edp_panel_vdd_off_sync] Turning eDP port C VDD off
>[  461.060124] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0007

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