Attachment 115421 Details for Bug 89685 – Possible fix

[patch] Possible fix

0001-R600-SI-Add-VCC-as-an-implict-def-of-SI_KILL.patch (text/plain), 2.85 KB, created by Tom Stellard on 2015-04-29 01:53:06 UTC

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Creator: Tom Stellard

Created: 2015-04-29 01:53:06 UTC

Size: 2.85 KB

patch

obsolete

>From 36d89bfaa834151adbc56315c771e1ba7fa12c7f Mon Sep 17 00:00:00 2001
>From: Tom Stellard <thomas.stellard@amd.com>
>Date: Tue, 31 Mar 2015 17:52:24 +0000
>Subject: [PATCH] R600/SI: Add VCC as an implict def of SI_KILL
>
>When SI_KILL has a register operand, its lowered form writes to vcc.
>---
> lib/Target/R600/SIInstructions.td     |  9 ++++++---
> test/CodeGen/R600/llvm.AMDGPU.kill.ll | 16 ++++++++++++++++
> 2 files changed, 22 insertions(+), 3 deletions(-)
>
>diff --git a/lib/Target/R600/SIInstructions.td b/lib/Target/R600/SIInstructions.td
>index 95b2470..d1db4ab 100644
>--- a/lib/Target/R600/SIInstructions.td
>+++ b/lib/Target/R600/SIInstructions.td
>@@ -1895,8 +1895,8 @@ def SGPR_USE : InstSI <(outs),(ins), "", []>;
> // SI pseudo instructions. These are used by the CFG structurizer pass
> // and should be lowered to ISA instructions prior to codegen.
> 
>-let mayLoad = 1, mayStore = 1, hasSideEffects = 1,
>-    Uses = [EXEC], Defs = [EXEC] in {
>+let mayLoad = 1, mayStore = 1, hasSideEffects = 1 in {
>+let Uses = [EXEC], Defs = [EXEC] in {
> 
> let isBranch = 1, isTerminator = 1 in {
> 
>@@ -1953,15 +1953,18 @@ def SI_END_CF : InstSI <
>   [(int_SI_end_cf i64:$saved)]
> >;
> 
>+} // End Uses = [EXEC], Defs = [EXEC]
>+
>+let Uses = [EXEC], Defs = [EXEC,VCC] in {
> def SI_KILL : InstSI <
>   (outs),
>   (ins VSrc_32:$src),
>   "si_kill $src",
>   [(int_AMDGPU_kill f32:$src)]
> >;
>+} // End Uses = [EXEC], Defs = [EXEC,VCC]
> 
> } // end mayLoad = 1, mayStore = 1, hasSideEffects = 1
>-  // Uses = [EXEC], Defs = [EXEC]
> 
> let Uses = [EXEC], Defs = [EXEC,VCC,M0] in {
> 
>diff --git a/test/CodeGen/R600/llvm.AMDGPU.kill.ll b/test/CodeGen/R600/llvm.AMDGPU.kill.ll
>index d1ff3b1..057708e 100644
>--- a/test/CodeGen/R600/llvm.AMDGPU.kill.ll
>+++ b/test/CodeGen/R600/llvm.AMDGPU.kill.ll
>@@ -16,8 +16,24 @@ main_body:
>   ret void
> }
> 
>+; SI-LABEL: {{^}}kill_vcc_implicit_def:
>+; SI-NOT: v_cmp_gt_f32_e32 vcc,
>+; SI: v_cmp_gt_f32_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], 0, v{{[0-9]+}}
>+; SI: v_cmpx_le_f32_e32 vcc, 0, v{{[0-9]+}}
>+; SI: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1.0, [[CMP]]
>+define void @kill_vcc_implicit_def([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #1 {
>+entry:
>+  %tmp0 = fcmp olt float %13, 0.0
>+  call void @llvm.AMDGPU.kill(float %14)
>+  %tmp1 = select i1 %tmp0, float 1.0, float 0.0
>+  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 1, i32 1, float %tmp1, float %tmp1, float %tmp1, float %tmp1)
>+  ret void
>+}
>+
> declare void @llvm.AMDGPU.kill(float)
>+declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
> 
> attributes #0 = { "ShaderType"="2" }
>+attributes #1 = { "ShaderType"="0" }
> 
> !0 = !{!"const", null, i32 1}
>-- 
>2.0.4
>

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Attachments on bug 89685: 114624 | 114625 | 114857 | 114858 | 114859 | 114868 | 114869 | 115420 | 115421

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