Attachment 116308 Details for Bug 90863 – dmesg

dmesg

dmesg_pm_rpm_skly05_0605.txt (text/plain), 32.93 KB, created by lu hua on 2015-06-05 07:33:53 UTC

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Creator: lu hua

Created: 2015-06-05 07:33:53 UTC

Size: 32.93 KB

patch

obsolete

>[  145.337857] pm_rpm: executing
>[  145.338056] [drm:i915_gem_open] 
>[  145.339134] [drm:i915_gem_open] 
>[  145.339172] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[5] ENCODERS[9]
>[  145.339187] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[5] ENCODERS[9]
>[  145.339205] [drm:drm_mode_getconnector] [CONNECTOR:35:?]
>[  145.339211] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:eDP-1]
>[  145.339215] [drm:intel_dp_detect] [CONNECTOR:35:eDP-1]
>[  145.339240] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[  145.339311] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000f
>[  145.339737] [drm:intel_dp_probe_oui] Sink OUI: 0022b9
>[  145.340111] [drm:intel_dp_probe_oui] Branch OUI: 000000
>[  145.340658] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  145.340668] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:35:eDP-1] probed modes :
>[  145.340676] [drm:drm_mode_debug_printmodeline] Modeline 36:"3200x1800" 60 361310 3200 3248 3280 3316 1800 1802 1807 1816 0x48 0xa
>[  145.340682] [drm:drm_mode_debug_printmodeline] Modeline 37:"3200x1800" 48 361310 3200 3248 3280 3680 1800 1802 1807 2045 0x40 0xa
>[  145.340694] [drm:drm_mode_getconnector] [CONNECTOR:35:?]
>[  145.340761] [drm:drm_mode_getconnector] [CONNECTOR:44:?]
>[  145.340768] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:44:DP-1]
>[  145.340772] [drm:intel_dp_detect] [CONNECTOR:44:DP-1]
>[  145.340776] [drm:intel_display_power_get] enabling DDI B power well
>[  145.340782] [drm:skl_set_power_well] Enabling DDI B power well
>[  145.340802] [drm:intel_display_power_put] disabling DDI B power well
>[  145.340807] [drm:skl_set_power_well] Disabling DDI B power well
>[  145.340811] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:44:DP-1] disconnected
>[  145.340816] [drm:drm_mode_getconnector] [CONNECTOR:44:?]
>[  145.340847] [drm:drm_mode_getconnector] [CONNECTOR:48:?]
>[  145.340851] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:48:HDMI-A-1]
>[  145.340855] [drm:intel_hdmi_detect] [CONNECTOR:48:HDMI-A-1]
>[  145.340858] [drm:intel_display_power_get] enabling DDI B power well
>[  145.340862] [drm:skl_set_power_well] Enabling DDI B power well
>[  145.341172] [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 r(1)
>[  145.341177] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[  145.341181] [drm:intel_display_power_put] disabling DDI B power well
>[  145.341186] [drm:skl_set_power_well] Disabling DDI B power well
>[  145.341190] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:48:HDMI-A-1] disconnected
>[  145.341197] [drm:drm_mode_getconnector] [CONNECTOR:48:?]
>[  145.341229] [drm:drm_mode_getconnector] [CONNECTOR:51:?]
>[  145.341233] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:51:DP-2]
>[  145.341236] [drm:intel_dp_detect] [CONNECTOR:51:DP-2]
>[  145.341240] [drm:intel_display_power_get] enabling DDI C power well
>[  145.341244] [drm:skl_set_power_well] Enabling DDI C power well
>[  145.341264] [drm:intel_display_power_put] disabling DDI C power well
>[  145.341268] [drm:skl_set_power_well] Disabling DDI C power well
>[  145.341272] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:51:DP-2] disconnected
>[  145.341276] [drm:drm_mode_getconnector] [CONNECTOR:51:?]
>[  145.341302] [drm:drm_mode_getconnector] [CONNECTOR:55:?]
>[  145.341305] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:55:HDMI-A-2]
>[  145.341308] [drm:intel_hdmi_detect] [CONNECTOR:55:HDMI-A-2]
>[  145.341312] [drm:intel_display_power_get] enabling DDI C power well
>[  145.341316] [drm:skl_set_power_well] Enabling DDI C power well
>[  145.341641] [drm:gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0050 r(1)
>[  145.341647] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  145.341651] [drm:intel_display_power_put] disabling DDI C power well
>[  145.341658] [drm:skl_set_power_well] Disabling DDI C power well
>[  145.341664] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:55:HDMI-A-2] disconnected
>[  145.341671] [drm:drm_mode_getconnector] [CONNECTOR:55:?]
>[  145.341835] [drm:drm_mode_addfb2] [FB:56]
>[  145.779230] [drm:intel_display_power_put] disabling power well 2
>[  145.779241] [drm:skl_set_power_well] Disabling power well 2
>[  145.779275] [drm:skl_set_power_well [i915]] *ERROR* CSR firmware not ready (2)
>[  145.779443] pm_rpm: starting subtest dpms-lpsp
>[  145.779513] [drm:intel_edp_backlight_off] 
>[  145.980658] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[  145.982856] [drm:skylake_pfit_update] for crtc_state = ffff88008bfc1400
>[  145.982868] [drm:intel_atomic_setup_scalers] crtc_state = ffff88008bfc1400 need = 0 avail = 2 scaler_users = 0x0
>[  145.982875] [drm:skl_detach_scalers] CRTC:21 Disabled scaler id 0.0
>[  145.982880] [drm:skl_detach_scalers] CRTC:21 Disabled scaler id 0.1
>[  145.983124] [drm:edp_panel_off] Turn eDP port A panel power off
>[  145.983167] [drm:wait_panel_off] Wait for panel power off time
>[  145.983198] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000
>[  146.043833] [drm:wait_panel_status] Wait complete
>[  146.043877] [drm:intel_display_power_put] disabling DDI A/E power well
>[  146.043883] [drm:skl_set_power_well] Disabling DDI A/E power well
>[  146.043899] [drm:check_encoder_state] [ENCODER:34:TMDS-34]
>[  146.043903] [drm:check_encoder_state] [ENCODER:43:TMDS-43]
>[  146.043907] [drm:check_encoder_state] [ENCODER:45:DP MST-45]
>[  146.043910] [drm:check_encoder_state] [ENCODER:46:DP MST-46]
>[  146.043913] [drm:check_encoder_state] [ENCODER:47:DP MST-47]
>[  146.043917] [drm:check_encoder_state] [ENCODER:50:TMDS-50]
>[  146.043920] [drm:check_encoder_state] [ENCODER:52:DP MST-52]
>[  146.043923] [drm:check_encoder_state] [ENCODER:53:DP MST-53]
>[  146.043926] [drm:check_encoder_state] [ENCODER:54:DP MST-54]
>[  146.043930] [drm:check_crtc_state] [CRTC:21]
>[  146.043935] [drm:check_crtc_state] [CRTC:26]
>[  146.043939] [drm:check_crtc_state] [CRTC:31]
>[  146.043943] [drm:check_shared_dpll_state] DPLL 1
>[  146.043947] [drm:check_shared_dpll_state] DPLL 2
>[  146.043951] [drm:check_shared_dpll_state] DPLL 3
>[  156.096194] pm_rpm: exiting, ret=99
>[  156.096290] [drm:intel_atomic_setup_scalers] crtc_state = ffff880163054800 need = 0 avail = 2 scaler_users = 0x0
>[  156.096300] [drm:skl_detach_scalers] CRTC:21 Disabled scaler id 0.0
>[  156.096303] [drm:skl_detach_scalers] CRTC:21 Disabled scaler id 0.1
>[  156.096333] [drm:skl_detach_scalers] CRTC:26 Disabled scaler id 1.0
>[  156.096336] [drm:skl_detach_scalers] CRTC:26 Disabled scaler id 1.1
>[  156.096357] [drm:skl_detach_scalers] CRTC:31 Disabled scaler id 2.0
>[  156.096374] [drm:intel_crtc_set_config] [CRTC:21] [FB:58] #connectors=1 (x y) (0 0)
>[  156.096380] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:eDP-1] to [CRTC:21]
>[  156.096391] [drm:connected_sink_compute_bpp] [CONNECTOR:35:eDP-1] checking for sink bpp constrains
>[  156.096392] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  156.096398] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 361310KHz
>[  156.096400] [drm:intel_dp_compute_config] clamping bpp for eDP panel to BIOS-provided 18
>[  156.096403] [drm:intel_dp_compute_config] DP link bw 14 lane count 4 clock 540000 bpp 18
>[  156.096405] [drm:intel_dp_compute_config] DP link bw required 650358 available 1728000
>[  156.096408] [drm:intel_crtc_compute_config] intel_crtc = ffff880168597000 drm_state (pipe_config->base.state) = ffff880163d3f120
>[  156.096411] [drm:intel_atomic_setup_scalers] crtc_state = ffff880163054800 need = 0 avail = 2 scaler_users = 0x0
>[  156.096413] [drm:intel_modeset_pipe_config] plane bpp: 36, pipe bpp: 18, dithering: 1
>[  156.096416] [drm:intel_dump_pipe_config] [CRTC:21][modeset] config ffff880163054800 for pipe A
>[  156.096417] [drm:intel_dump_pipe_config] cpu_transcoder: D
>[  156.096419] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
>[  156.096422] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  156.096425] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 3157174, gmch_n: 8388608, link_m: 701594, link_n: 1048576, tu: 64
>[  156.096428] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  156.096430] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  156.096431] [drm:intel_dump_pipe_config] requested mode:
>[  156.096436] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 361310 3200 3248 3280 3316 1800 1802 1807 1816 0x48 0xa
>[  156.096437] [drm:intel_dump_pipe_config] adjusted mode:
>[  156.096441] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 361310 3200 3248 3280 3316 1800 1802 1807 1816 0x48 0xa
>[  156.096445] [drm:intel_dump_crtc_timings] crtc timings: 361310 3200 3248 3280 3316 1800 1802 1807 1816, type: 0x48 flags: 0xa
>[  156.096446] [drm:intel_dump_pipe_config] port clock: 540000
>[  156.096448] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
>[  156.096450] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  156.096452] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  156.096455] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  156.096456] [drm:intel_dump_pipe_config] ips: 0
>[  156.096457] [drm:intel_dump_pipe_config] double wide: 0
>[  156.096460] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  156.096461] [drm:intel_dump_pipe_config] planes on this crtc
>[  156.096467] [drm:intel_dump_pipe_config] STANDARD PLANE:18 plane: 0.0 idx: 0 enabled
>[  156.096470] [drm:intel_dump_pipe_config] 	FB:58, fb = 3200x1800 format = 0x34325258
>[  156.096471] [drm:intel_dump_pipe_config] 	scaler:-1 src (0, 0) 0x0 dst (0, 0) 0x0
>[  156.096474] [drm:intel_dump_pipe_config] CURSOR PLANE:20 plane: 0.1 idx: 1 disabled, scaler_id = -1
>[  156.096476] [drm:intel_dump_pipe_config] STANDARD PLANE:22 plane: 0.1 idx: 2 disabled, scaler_id = -1
>[  156.096478] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 0.2 idx: 3 disabled, scaler_id = -1
>[  156.096508] [drm:intel_display_power_get] enabling DDI A/E power well
>[  156.096512] [drm:skl_set_power_well] Enabling DDI A/E power well
>[  156.096533] [drm:edp_panel_on] Turn eDP port A panel power on
>[  156.096550] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  156.096574] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0000
>[  156.096586] [drm:wait_panel_status] Wait complete
>[  156.096619] [drm:wait_panel_on] Wait for panel power on
>[  156.096642] [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control abcd0003
>[  156.298671] [drm:wait_panel_status] Wait complete
>[  156.298701] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[  156.298767] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
>[  156.299936] [drm:intel_dp_set_signal_levels] Using signal levels 05000000
>[  156.299939] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[  156.299941] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[  156.300635] [drm:intel_dp_start_link_train] clock recovery OK
>[  156.301631] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[  156.301811] [drm:skylake_pfit_update] for crtc_state = ffff880163054800
>[  156.301816] [drm:intel_atomic_setup_scalers] crtc_state = ffff880163054800 need = 0 avail = 2 scaler_users = 0x0
>[  156.301820] [drm:skl_detach_scalers] CRTC:21 Disabled scaler id 0.0
>[  156.301823] [drm:skl_detach_scalers] CRTC:21 Disabled scaler id 0.1
>[  156.301946] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[  156.301959] [drm:intel_edp_backlight_on] 
>[  156.301962] [drm:intel_panel_enable_backlight] pipe A
>[  156.302022] [drm:intel_panel_actually_set_backlight] set backlight PWM = 937
>[  156.302077] [drm:intel_psr_match_conditions] PSR disable by flag
>[  156.302079] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[  156.302112] [drm:intel_connector_check_state] [CONNECTOR:35:eDP-1]
>[  156.302116] [drm:check_encoder_state] [ENCODER:34:TMDS-34]
>[  156.302120] [drm:check_encoder_state] [ENCODER:43:TMDS-43]
>[  156.302122] [drm:check_encoder_state] [ENCODER:45:DP MST-45]
>[  156.302123] [drm:check_encoder_state] [ENCODER:46:DP MST-46]
>[  156.302125] [drm:check_encoder_state] [ENCODER:47:DP MST-47]
>[  156.302126] [drm:check_encoder_state] [ENCODER:50:TMDS-50]
>[  156.302128] [drm:check_encoder_state] [ENCODER:52:DP MST-52]
>[  156.302129] [drm:check_encoder_state] [ENCODER:53:DP MST-53]
>[  156.302130] [drm:check_encoder_state] [ENCODER:54:DP MST-54]
>[  156.302132] [drm:check_crtc_state] [CRTC:21]
>[  156.302150] [drm:check_crtc_state] [CRTC:26]
>[  156.302151] [drm:check_crtc_state] [CRTC:31]
>[  156.302154] [drm:check_shared_dpll_state] DPLL 1
>[  156.302156] [drm:check_shared_dpll_state] DPLL 2
>[  156.302158] [drm:check_shared_dpll_state] DPLL 3
>[  156.302162] [drm:intel_crtc_set_config] [CRTC:26] [NOFB]
>[  156.302201] [drm:intel_connector_check_state] [CONNECTOR:35:eDP-1]
>[  156.302204] [drm:check_encoder_state] [ENCODER:34:TMDS-34]
>[  156.302207] [drm:check_encoder_state] [ENCODER:43:TMDS-43]
>[  156.302208] [drm:check_encoder_state] [ENCODER:45:DP MST-45]
>[  156.302210] [drm:check_encoder_state] [ENCODER:46:DP MST-46]
>[  156.302211] [drm:check_encoder_state] [ENCODER:47:DP MST-47]
>[  156.302213] [drm:check_encoder_state] [ENCODER:50:TMDS-50]
>[  156.302214] [drm:check_encoder_state] [ENCODER:52:DP MST-52]
>[  156.302216] [drm:check_encoder_state] [ENCODER:53:DP MST-53]
>[  156.302217] [drm:check_encoder_state] [ENCODER:54:DP MST-54]
>[  156.302218] [drm:check_crtc_state] [CRTC:21]
>[  156.302231] [drm:check_crtc_state] [CRTC:26]
>[  156.302233] [drm:check_crtc_state] [CRTC:31]
>[  156.302234] [drm:check_shared_dpll_state] DPLL 1
>[  156.302236] [drm:check_shared_dpll_state] DPLL 2
>[  156.302238] [drm:check_shared_dpll_state] DPLL 3
>[  156.302240] [drm:intel_crtc_set_config] [CRTC:31] [NOFB]
>[  156.302262] [drm:intel_connector_check_state] [CONNECTOR:35:eDP-1]
>[  156.302265] [drm:check_encoder_state] [ENCODER:34:TMDS-34]
>[  156.302268] [drm:check_encoder_state] [ENCODER:43:TMDS-43]
>[  156.302269] [drm:check_encoder_state] [ENCODER:45:DP MST-45]
>[  156.302271] [drm:check_encoder_state] [ENCODER:46:DP MST-46]
>[  156.302272] [drm:check_encoder_state] [ENCODER:47:DP MST-47]
>[  156.302274] [drm:check_encoder_state] [ENCODER:50:TMDS-50]
>[  156.302275] [drm:check_encoder_state] [ENCODER:52:DP MST-52]
>[  156.302276] [drm:check_encoder_state] [ENCODER:53:DP MST-53]
>[  156.302278] [drm:check_encoder_state] [ENCODER:54:DP MST-54]
>[  156.302279] [drm:check_crtc_state] [CRTC:21]
>[  156.302291] [drm:check_crtc_state] [CRTC:26]
>[  156.302293] [drm:check_crtc_state] [CRTC:31]
>[  156.302294] [drm:check_shared_dpll_state] DPLL 1
>[  156.302296] [drm:check_shared_dpll_state] DPLL 2
>[  156.302298] [drm:check_shared_dpll_state] DPLL 3
>[  156.302310] [drm:intel_crtc_set_config] [CRTC:21] [FB:58] #connectors=1 (x y) (0 0)
>[  156.302314] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:eDP-1] to [CRTC:21]
>[  156.302322] [drm:connected_sink_compute_bpp] [CONNECTOR:35:eDP-1] checking for sink bpp constrains
>[  156.302324] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  156.302329] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 361310KHz
>[  156.302330] [drm:intel_dp_compute_config] clamping bpp for eDP panel to BIOS-provided 18
>[  156.302333] [drm:intel_dp_compute_config] DP link bw 14 lane count 4 clock 540000 bpp 18
>[  156.302335] [drm:intel_dp_compute_config] DP link bw required 650358 available 1728000
>[  156.302339] [drm:intel_crtc_compute_config] intel_crtc = ffff880168597000 drm_state (pipe_config->base.state) = ffff8801677e1de0
>[  156.302341] [drm:intel_atomic_setup_scalers] crtc_state = ffff88016320cc00 need = 0 avail = 2 scaler_users = 0x0
>[  156.302344] [drm:intel_modeset_pipe_config] plane bpp: 36, pipe bpp: 18, dithering: 1
>[  156.302346] [drm:intel_dump_pipe_config] [CRTC:21][modeset] config ffff88016320cc00 for pipe A
>[  156.302348] [drm:intel_dump_pipe_config] cpu_transcoder: D
>[  156.302349] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
>[  156.302352] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  156.302355] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 3157174, gmch_n: 8388608, link_m: 701594, link_n: 1048576, tu: 64
>[  156.302358] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  156.302360] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  156.302361] [drm:intel_dump_pipe_config] requested mode:
>[  156.302366] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 361310 3200 3248 3280 3316 1800 1802 1807 1816 0x48 0xa
>[  156.302367] [drm:intel_dump_pipe_config] adjusted mode:
>[  156.302371] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 361310 3200 3248 3280 3316 1800 1802 1807 1816 0x48 0xa
>[  156.302374] [drm:intel_dump_crtc_timings] crtc timings: 361310 3200 3248 3280 3316 1800 1802 1807 1816, type: 0x48 flags: 0xa
>[  156.302376] [drm:intel_dump_pipe_config] port clock: 540000
>[  156.302377] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
>[  156.302380] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  156.302382] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  156.302384] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  156.302386] [drm:intel_dump_pipe_config] ips: 0
>[  156.302387] [drm:intel_dump_pipe_config] double wide: 0
>[  156.302390] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  156.302391] [drm:intel_dump_pipe_config] planes on this crtc
>[  156.302396] [drm:intel_dump_pipe_config] STANDARD PLANE:18 plane: 0.0 idx: 0 enabled
>[  156.302400] [drm:intel_dump_pipe_config] 	FB:58, fb = 3200x1800 format = 0x34325258
>[  156.302400] [drm:intel_dump_pipe_config] 	scaler:-1 src (0, 0) 3200x1800 dst (0, 0) 3200x1800
>[  156.302403] [drm:intel_dump_pipe_config] CURSOR PLANE:20 plane: 0.1 idx: 1 disabled, scaler_id = -1
>[  156.302406] [drm:intel_dump_pipe_config] STANDARD PLANE:22 plane: 0.1 idx: 2 disabled, scaler_id = -1
>[  156.302408] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 0.2 idx: 3 disabled, scaler_id = -1
>[  156.302453] [drm:intel_connector_check_state] [CONNECTOR:35:eDP-1]
>[  156.302456] [drm:check_encoder_state] [ENCODER:34:TMDS-34]
>[  156.302459] [drm:check_encoder_state] [ENCODER:43:TMDS-43]
>[  156.302460] [drm:check_encoder_state] [ENCODER:45:DP MST-45]
>[  156.302462] [drm:check_encoder_state] [ENCODER:46:DP MST-46]
>[  156.302463] [drm:check_encoder_state] [ENCODER:47:DP MST-47]
>[  156.302465] [drm:check_encoder_state] [ENCODER:50:TMDS-50]
>[  156.302466] [drm:check_encoder_state] [ENCODER:52:DP MST-52]
>[  156.302468] [drm:check_encoder_state] [ENCODER:53:DP MST-53]
>[  156.302469] [drm:check_encoder_state] [ENCODER:54:DP MST-54]
>[  156.302470] [drm:check_crtc_state] [CRTC:21]
>[  156.302483] [drm:check_crtc_state] [CRTC:26]
>[  156.302484] [drm:check_crtc_state] [CRTC:31]
>[  156.302485] [drm:check_shared_dpll_state] DPLL 1
>[  156.302487] [drm:check_shared_dpll_state] DPLL 2
>[  156.302489] [drm:check_shared_dpll_state] DPLL 3
>[  156.302510] [drm:intel_crtc_set_config] [CRTC:21] [FB:58] #connectors=1 (x y) (0 0)
>[  156.302514] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:eDP-1] to [CRTC:21]
>[  156.302520] [drm:connected_sink_compute_bpp] [CONNECTOR:35:eDP-1] checking for sink bpp constrains
>[  156.302521] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  156.302525] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 361310KHz
>[  156.302526] [drm:intel_dp_compute_config] clamping bpp for eDP panel to BIOS-provided 18
>[  156.302529] [drm:intel_dp_compute_config] DP link bw 14 lane count 4 clock 540000 bpp 18
>[  156.302531] [drm:intel_dp_compute_config] DP link bw required 650358 available 1728000
>[  156.302533] [drm:intel_crtc_compute_config] intel_crtc = ffff880168597000 drm_state (pipe_config->base.state) = ffff8801677e1de0
>[  156.302536] [drm:intel_atomic_setup_scalers] crtc_state = ffff88016320ec00 need = 0 avail = 2 scaler_users = 0x0
>[  156.302538] [drm:intel_modeset_pipe_config] plane bpp: 36, pipe bpp: 18, dithering: 1
>[  156.302540] [drm:intel_dump_pipe_config] [CRTC:21][modeset] config ffff88016320ec00 for pipe A
>[  156.302541] [drm:intel_dump_pipe_config] cpu_transcoder: D
>[  156.302543] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
>[  156.302546] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  156.302549] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 3157174, gmch_n: 8388608, link_m: 701594, link_n: 1048576, tu: 64
>[  156.302551] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  156.302553] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  156.302554] [drm:intel_dump_pipe_config] requested mode:
>[  156.302558] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 361310 3200 3248 3280 3316 1800 1802 1807 1816 0x48 0xa
>[  156.302560] [drm:intel_dump_pipe_config] adjusted mode:
>[  156.302563] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 361310 3200 3248 3280 3316 1800 1802 1807 1816 0x48 0xa
>[  156.302567] [drm:intel_dump_crtc_timings] crtc timings: 361310 3200 3248 3280 3316 1800 1802 1807 1816, type: 0x48 flags: 0xa
>[  156.302568] [drm:intel_dump_pipe_config] port clock: 540000
>[  156.302570] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
>[  156.302572] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  156.302574] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  156.302576] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  156.302577] [drm:intel_dump_pipe_config] ips: 0
>[  156.302579] [drm:intel_dump_pipe_config] double wide: 0
>[  156.302581] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  156.302582] [drm:intel_dump_pipe_config] planes on this crtc
>[  156.302587] [drm:intel_dump_pipe_config] STANDARD PLANE:18 plane: 0.0 idx: 0 enabled
>[  156.302591] [drm:intel_dump_pipe_config] 	FB:58, fb = 3200x1800 format = 0x34325258
>[  156.302591] [drm:intel_dump_pipe_config] 	scaler:-1 src (0, 0) 3200x1800 dst (0, 0) 3200x1800
>[  156.302594] [drm:intel_dump_pipe_config] CURSOR PLANE:20 plane: 0.1 idx: 1 disabled, scaler_id = -1
>[  156.302596] [drm:intel_dump_pipe_config] STANDARD PLANE:22 plane: 0.1 idx: 2 disabled, scaler_id = -1
>[  156.302598] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 0.2 idx: 3 disabled, scaler_id = -1
>[  156.302632] [drm:intel_connector_check_state] [CONNECTOR:35:eDP-1]
>[  156.302635] [drm:check_encoder_state] [ENCODER:34:TMDS-34]
>[  156.302637] [drm:check_encoder_state] [ENCODER:43:TMDS-43]
>[  156.302639] [drm:check_encoder_state] [ENCODER:45:DP MST-45]
>[  156.302640] [drm:check_encoder_state] [ENCODER:46:DP MST-46]
>[  156.302642] [drm:check_encoder_state] [ENCODER:47:DP MST-47]
>[  156.302643] [drm:check_encoder_state] [ENCODER:50:TMDS-50]
>[  156.302645] [drm:check_encoder_state] [ENCODER:52:DP MST-52]
>[  156.302646] [drm:check_encoder_state] [ENCODER:53:DP MST-53]
>[  156.302648] [drm:check_encoder_state] [ENCODER:54:DP MST-54]
>[  156.302649] [drm:check_crtc_state] [CRTC:21]
>[  156.302662] [drm:check_crtc_state] [CRTC:26]
>[  156.302663] [drm:check_crtc_state] [CRTC:31]
>[  156.302665] [drm:check_shared_dpll_state] DPLL 1
>[  156.302666] [drm:check_shared_dpll_state] DPLL 2
>[  156.302668] [drm:check_shared_dpll_state] DPLL 3
>[  156.334979] [drm:intel_atomic_setup_scalers] crtc_state = ffff88016320dc00 need = 0 avail = 2 scaler_users = 0x0
>[  156.334998] [drm:skl_detach_scalers] CRTC:21 Disabled scaler id 0.0
>[  156.335010] [drm:skl_detach_scalers] CRTC:21 Disabled scaler id 0.1
>[  156.335062] [drm:skl_detach_scalers] CRTC:26 Disabled scaler id 1.0
>[  156.335067] [drm:skl_detach_scalers] CRTC:26 Disabled scaler id 1.1
>[  156.335093] [drm:skl_detach_scalers] CRTC:31 Disabled scaler id 2.0
>[  156.335116] [drm:intel_crtc_set_config] [CRTC:21] [FB:58] #connectors=1 (x y) (0 0)
>[  156.335123] [drm:intel_modeset_stage_output_state] [CONNECTOR:35:eDP-1] to [CRTC:21]
>[  156.335134] [drm:connected_sink_compute_bpp] [CONNECTOR:35:eDP-1] checking for sink bpp constrains
>[  156.335138] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  156.335145] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 361310KHz
>[  156.335149] [drm:intel_dp_compute_config] clamping bpp for eDP panel to BIOS-provided 18
>[  156.335154] [drm:intel_dp_compute_config] DP link bw 14 lane count 4 clock 540000 bpp 18
>[  156.335159] [drm:intel_dp_compute_config] DP link bw required 650358 available 1728000
>[  156.335165] [drm:intel_crtc_compute_config] intel_crtc = ffff880168597000 drm_state (pipe_config->base.state) = ffff8801677e1de0
>[  156.335170] [drm:intel_atomic_setup_scalers] crtc_state = ffff88016320dc00 need = 0 avail = 2 scaler_users = 0x0
>[  156.335175] [drm:intel_modeset_pipe_config] plane bpp: 36, pipe bpp: 18, dithering: 1
>[  156.335180] [drm:intel_dump_pipe_config] [CRTC:21][modeset] config ffff88016320dc00 for pipe A
>[  156.335183] [drm:intel_dump_pipe_config] cpu_transcoder: D
>[  156.335187] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
>[  156.335204] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  156.335210] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 3157174, gmch_n: 8388608, link_m: 701594, link_n: 1048576, tu: 64
>[  156.335215] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  156.335219] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  156.335222] [drm:intel_dump_pipe_config] requested mode:
>[  156.335230] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 361310 3200 3248 3280 3316 1800 1802 1807 1816 0x48 0xa
>[  156.335234] [drm:intel_dump_pipe_config] adjusted mode:
>[  156.335241] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 361310 3200 3248 3280 3316 1800 1802 1807 1816 0x48 0xa
>[  156.335248] [drm:intel_dump_crtc_timings] crtc timings: 361310 3200 3248 3280 3316 1800 1802 1807 1816, type: 0x48 flags: 0xa
>[  156.335251] [drm:intel_dump_pipe_config] port clock: 540000
>[  156.335256] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
>[  156.335260] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  156.335265] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  156.335269] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  156.335273] [drm:intel_dump_pipe_config] ips: 0
>[  156.335276] [drm:intel_dump_pipe_config] double wide: 0
>[  156.335281] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  156.335285] [drm:intel_dump_pipe_config] planes on this crtc
>[  156.335308] [drm:intel_dump_pipe_config] STANDARD PLANE:18 plane: 0.0 idx: 0 enabled
>[  156.335314] [drm:intel_dump_pipe_config] 	FB:58, fb = 3200x1800 format = 0x34325258<7>[  156.335337] [drm:intel_dump_pipe_config] 	scaler:-1 src (0, 0) 3200x1800 dst (0, 0) 3200x1800
>[  156.335342] [drm:intel_dump_pipe_config] CURSOR PLANE:20 plane: 0.1 idx: 1 disabled, scaler_id = -1
>[  156.335348] [drm:intel_dump_pipe_config] STANDARD PLANE:22 plane: 0.1 idx: 2 disabled, scaler_id = -1
>[  156.335353] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 0.2 idx: 3 disabled, scaler_id = -1
>[  156.335413] [drm:intel_connector_check_state] [CONNECTOR:35:eDP-1]
>[  156.335428] [drm:check_encoder_state] [ENCODER:34:TMDS-34]
>[  156.335442] [drm:check_encoder_state] [ENCODER:43:TMDS-43]
>[  156.335455] [drm:check_encoder_state] [ENCODER:45:DP MST-45]
>[  156.335468] [drm:check_encoder_state] [ENCODER:46:DP MST-46]
>[  156.335480] [drm:check_encoder_state] [ENCODER:47:DP MST-47]
>[  156.335493] [drm:check_encoder_state] [ENCODER:50:TMDS-50]
>[  156.335506] [drm:check_encoder_state] [ENCODER:52:DP MST-52]
>[  156.335519] [drm:check_encoder_state] [ENCODER:53:DP MST-53]
>[  156.335527] [drm:check_encoder_state] [ENCODER:54:DP MST-54]
>[  156.335532] [drm:check_crtc_state] [CRTC:21]
>[  156.335549] [drm:check_crtc_state] [CRTC:26]
>[  156.335554] [drm:check_crtc_state] [CRTC:31]
>[  156.335558] [drm:check_shared_dpll_state] DPLL 1
>[  156.335563] [drm:check_shared_dpll_state] DPLL 2
>[  156.335567] [drm:check_shared_dpll_state] DPLL 3
>[  156.335573] [drm:intel_crtc_set_config] [CRTC:26] [NOFB]
>[  156.335602] [drm:intel_connector_check_state] [CONNECTOR:35:eDP-1]
>[  156.335608] [drm:check_encoder_state] [ENCODER:34:TMDS-34]
>[  156.335614] [drm:check_encoder_state] [ENCODER:43:TMDS-43]
>[  156.335618] [drm:check_encoder_state] [ENCODER:45:DP MST-45]
>[  156.335622] [drm:check_encoder_state] [ENCODER:46:DP MST-46]
>[  156.335626] [drm:check_encoder_state] [ENCODER:47:DP MST-47]
>[  156.335630] [drm:check_encoder_state] [ENCODER:50:TMDS-50]
>[  156.335634] [drm:check_encoder_state] [ENCODER:52:DP MST-52]
>[  156.335638] [drm:check_encoder_state] [ENCODER:53:DP MST-53]
>[  156.335642] [drm:check_encoder_state] [ENCODER:54:DP MST-54]
>[  156.335646] [drm:check_crtc_state] [CRTC:21]
>[  156.335661] [drm:check_crtc_state] [CRTC:26]
>[  156.335665] [drm:check_crtc_state] [CRTC:31]
>[  156.335670] [drm:check_shared_dpll_state] DPLL 1
>[  156.335674] [drm:check_shared_dpll_state] DPLL 2
>[  156.335678] [drm:check_shared_dpll_state] DPLL 3
>[  156.335683] [drm:intel_crtc_set_config] [CRTC:31] [NOFB]
>[  156.335710] [drm:intel_connector_check_state] [CONNECTOR:35:eDP-1]
>[  156.335716] [drm:check_encoder_state] [ENCODER:34:TMDS-34]
>[  156.335721] [drm:check_encoder_state] [ENCODER:43:TMDS-43]
>[  156.335725] [drm:check_encoder_state] [ENCODER:45:DP MST-45]
>[  156.335729] [drm:check_encoder_state] [ENCODER:46:DP MST-46]
>[  156.335733] [drm:check_encoder_state] [ENCODER:47:DP MST-47]
>[  156.335737] [drm:check_encoder_state] [ENCODER:50:TMDS-50]
>[  156.335741] [drm:check_encoder_state] [ENCODER:52:DP MST-52]
>[  156.335745] [drm:check_encoder_state] [ENCODER:53:DP MST-53]
>[  156.335750] [drm:check_encoder_state] [ENCODER:54:DP MST-54]
>[  156.335754] [drm:check_crtc_state] [CRTC:21]
>[  156.335770] [drm:check_crtc_state] [CRTC:26]
>[  156.335783] [drm:check_crtc_state] [CRTC:31]
>[  156.335795] [drm:check_shared_dpll_state] DPLL 1
>[  156.335807] [drm:check_shared_dpll_state] DPLL 2
>[  156.335819] [drm:check_shared_dpll_state] DPLL 3
>[  159.309604] [drm:edp_panel_vdd_off_sync] Turning eDP port A VDD off
>[  159.309670] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0007
>[  756.762808] [drm:intel_edp_backlight_off] 
>[  756.963799] [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[  756.972373] [drm:skylake_pfit_update] for crtc_state = ffff88016320dc00
>[  756.972379] [drm:intel_atomic_setup_scalers] crtc_state = ffff88016320dc00 need = 0 avail = 2 scaler_users = 0x0
>[  756.972383] [drm:skl_detach_scalers] CRTC:21 Disabled scaler id 0.0
>[  756.972386] [drm:skl_detach_scalers] CRTC:21 Disabled scaler id 0.1
>[  756.972416] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[  756.972482] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
>[  756.972692] [drm:edp_panel_off] Turn eDP port A panel power off
>[  756.972725] [drm:wait_panel_off] Wait for panel power off time
>[  756.972749] [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control abcd0000
>[  757.033403] [drm:wait_panel_status] Wait complete
>[  757.033441] [drm:intel_display_power_put] disabling DDI A/E power well
>[  757.033444] [drm:skl_set_power_well] Disabling DDI A/E power well
>[  757.033459] [drm:check_encoder_state] [ENCODER:34:TMDS-34]
>[  757.033462] [drm:check_encoder_state] [ENCODER:43:TMDS-43]
>[  757.033464] [drm:check_encoder_state] [ENCODER:45:DP MST-45]
>[  757.033466] [drm:check_encoder_state] [ENCODER:46:DP MST-46]
>[  757.033468] [drm:check_encoder_state] [ENCODER:47:DP MST-47]
>[  757.033469] [drm:check_encoder_state] [ENCODER:50:TMDS-50]
>[  757.033471] [drm:check_encoder_state] [ENCODER:52:DP MST-52]
>[  757.033473] [drm:check_encoder_state] [ENCODER:53:DP MST-53]
>[  757.033475] [drm:check_encoder_state] [ENCODER:54:DP MST-54]
>[  757.033477] [drm:check_crtc_state] [CRTC:21]
>[  757.033481] [drm:check_crtc_state] [CRTC:26]
>[  757.033483] [drm:check_crtc_state] [CRTC:31]
>[  757.033485] [drm:check_shared_dpll_state] DPLL 1
>[  757.033488] [drm:check_shared_dpll_state] DPLL 2
>[  757.033491] [drm:check_shared_dpll_state] DPLL 3

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Attachments on bug 90863: 116308 | 122823

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