Attachment 117556 Details for Bug 90237 – log suspend to disck

log suspend to disck

Log-suspend-to-disck (text/plain), 78.65 KB, created by Rami on 2015-08-06 09:33:18 UTC

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Description:

Filename:

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Creator: Rami

Created: 2015-08-06 09:33:18 UTC

Size: 78.65 KB

patch

obsolete

>[  415.359231] [drm:check_encoder_state] [ENCODER:50:DP MST-50]
>[  415.359234] [drm:check_encoder_state] [ENCODER:51:DP MST-51]
>[  415.359238] [drm:check_crtc_state] [CRTC:21]
>[  415.359245] [drm:check_crtc_state] [CRTC:25]
>[  415.359252] [drm:check_crtc_state] [CRTC:29]
>[  415.359259] [drm:check_shared_dpll_state] DPLL 1
>[  415.359265] [drm:check_shared_dpll_state] DPLL 2
>[  415.359269] [drm:check_shared_dpll_state] DPLL 3
>[  415.359888] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[5] ENCODERS[9]
>[  415.359895] [drm:drm_mode_getresources] [CRTC:21]
>[  415.359898] [drm:drm_mode_getresources] [CRTC:25]
>[  415.359901] [drm:drm_mode_getresources] [CRTC:29]
>[  415.359904] [drm:drm_mode_getresources] [ENCODER:31:TMDS-31]
>[  415.359908] [drm:drm_mode_getresources] [ENCODER:40:TMDS-40]
>[  415.359911] [drm:drm_mode_getresources] [ENCODER:42:DP MST-42]
>[  415.359914] [drm:drm_mode_getresources] [ENCODER:43:DP MST-43]
>[  415.359917] [drm:drm_mode_getresources] [ENCODER:44:DP MST-44]
>[  415.359920] [drm:drm_mode_getresources] [ENCODER:47:TMDS-47]
>[  415.359923] [drm:drm_mode_getresources] [ENCODER:49:DP MST-49]
>[  415.359926] [drm:drm_mode_getresources] [ENCODER:50:DP MST-50]
>[  415.359929] [drm:drm_mode_getresources] [ENCODER:51:DP MST-51]
>[  415.359932] [drm:drm_mode_getresources] [CONNECTOR:32:eDP-1]
>[  415.359935] [drm:drm_mode_getresources] [CONNECTOR:41:DP-1]
>[  415.359938] [drm:drm_mode_getresources] [CONNECTOR:45:HDMI-A-1]
>[  415.359941] [drm:drm_mode_getresources] [CONNECTOR:48:DP-2]
>[  415.359944] [drm:drm_mode_getresources] [CONNECTOR:52:HDMI-A-2]
>[  415.359948] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[5] ENCODERS[9]
>[  415.359955] [drm:drm_mode_getconnector] [CONNECTOR:52:?]
>[  415.359963] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:52:HDMI-A-2]
>[  415.359966] [drm:intel_hdmi_detect] [CONNECTOR:52:HDMI-A-2]
>[  415.360014] [drm:intel_display_power_get] enabling DDI C power well
>[  415.360028] [drm:skl_set_power_well] Enabling DDI C power well
>[  415.360303] [drm:gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  415.360310] [drm:gmbus_xfer] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  415.360564] [drm:gmbus_xfer] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  415.360569] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  415.360574] [drm:intel_display_power_put] disabling DDI C power well
>[  415.360581] [drm:skl_set_power_well] Disabling DDI C power well
>[  415.360585] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:52:HDMI-A-2] disconnected
>[  415.360594] [drm:drm_mode_getconnector] [CONNECTOR:52:?]
>[  415.361390] (null): exiting, ret=0
>[  415.361584] [drm:drm_atomic_state_init] Allocated atomic state ffff88016c37fe00
>[  415.361590] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8800872299c0 state to ffff88016c37fe00
>[  415.361592] [drm:drm_atomic_check_only] checking ffff88016c37fe00
>[  415.361597] [drm:drm_atomic_commit] commiting ffff88016c37fe00
>[  415.361602] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88016c37fe00
>[  415.361605] [drm:drm_atomic_state_free] Freeing atomic state ffff88016c37fe00
>[  415.361611] [drm:drm_atomic_state_init] Allocated atomic state ffff88016c37fe00
>[  415.361615] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff880087229780 state to ffff88016c37fe00
>[  415.361616] [drm:drm_atomic_check_only] checking ffff88016c37fe00
>[  415.361618] [drm:drm_atomic_commit] commiting ffff88016c37fe00
>[  415.361621] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88016c37fe00
>[  415.361623] [drm:drm_atomic_state_free] Freeing atomic state ffff88016c37fe00
>[  415.361629] [drm:drm_atomic_state_init] Allocated atomic state ffff88016c37fe00
>[  415.361632] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff880087229480 state to ffff88016c37fe00
>[  415.361634] [drm:drm_atomic_check_only] checking ffff88016c37fe00
>[  415.361636] [drm:drm_atomic_commit] commiting ffff88016c37fe00
>[  415.361639] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88016c37fe00
>[  415.361641] [drm:drm_atomic_state_free] Freeing atomic state ffff88016c37fe00
>[  415.361646] [drm:drm_atomic_state_init] Allocated atomic state ffff88016c37fe00
>[  415.361650] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8800872296c0 state to ffff88016c37fe00
>[  415.361654] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880086c69000 state to ffff88016c37fe00
>[  415.361655] [drm:drm_atomic_check_only] checking ffff88016c37fe00
>[  415.361661] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23] scaler_user index 1.3
>[  415.361666] [drm:intel_atomic_setup_scalers] crtc_state = ffff880086c69000 need = 0 avail = 2 scaler_users = 0x0
>[  415.361668] [drm:drm_atomic_commit] commiting ffff88016c37fe00
>[  415.361681] [drm:skl_detach_scaler] CRTC:25 Disabled scaler id 1.0
>[  415.361685] [drm:skl_detach_scaler] CRTC:25 Disabled scaler id 1.1
>[  415.361693] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88016c37fe00
>[  415.361697] [drm:drm_atomic_state_free] Freeing atomic state ffff88016c37fe00
>[  415.361702] [drm:drm_atomic_state_init] Allocated atomic state ffff88016c37fe00
>[  415.361706] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff880087229e40 state to ffff88016c37fe00
>[  415.361707] [drm:drm_atomic_check_only] checking ffff88016c37fe00
>[  415.361709] [drm:drm_atomic_commit] commiting ffff88016c37fe00
>[  415.361712] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88016c37fe00
>[  415.361714] [drm:drm_atomic_state_free] Freeing atomic state ffff88016c37fe00
>[  415.361720] [drm:drm_atomic_state_init] Allocated atomic state ffff88016c37fe00
>[  415.361723] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff880087229540 state to ffff88016c37fe00
>[  415.361725] [drm:drm_atomic_check_only] checking ffff88016c37fe00
>[  415.361726] [drm:drm_atomic_commit] commiting ffff88016c37fe00
>[  415.361729] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88016c37fe00
>[  415.361731] [drm:drm_atomic_state_free] Freeing atomic state ffff88016c37fe00
>[  415.361737] [drm:drm_atomic_state_init] Allocated atomic state ffff88016c37fe00
>[  415.361740] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff880087229b40 state to ffff88016c37fe00
>[  415.361741] [drm:drm_atomic_check_only] checking ffff88016c37fe00
>[  415.361743] [drm:drm_atomic_commit] commiting ffff88016c37fe00
>[  415.361746] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88016c37fe00
>[  415.361748] [drm:drm_atomic_state_free] Freeing atomic state ffff88016c37fe00
>[  415.361753] [drm:drm_atomic_state_init] Allocated atomic state ffff88016c37fe00
>[  415.361756] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff880087229600 state to ffff88016c37fe00
>[  415.361758] [drm:drm_atomic_check_only] checking ffff88016c37fe00
>[  415.361760] [drm:drm_atomic_commit] commiting ffff88016c37fe00
>[  415.361762] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88016c37fe00
>[  415.361764] [drm:drm_atomic_state_free] Freeing atomic state ffff88016c37fe00
>[  415.361770] [drm:drm_atomic_state_init] Allocated atomic state ffff88016c37fe00
>[  415.361773] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff880087229000 state to ffff88016c37fe00
>[  415.361774] [drm:drm_atomic_check_only] checking ffff88016c37fe00
>[  415.361776] [drm:drm_atomic_commit] commiting ffff88016c37fe00
>[  415.361779] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88016c37fe00
>[  415.361781] [drm:drm_atomic_state_free] Freeing atomic state ffff88016c37fe00
>[  415.361787] [drm:drm_atomic_state_init] Allocated atomic state ffff88016c37fe00
>[  415.361790] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff880086c6c400 state to ffff88016c37fe00
>[  415.361794] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8800872290c0 state to ffff88016c37fe00
>[  415.361801] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffff880086c6c400
>[  415.361803] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800872290c0 to [CRTC:21]
>[  415.361805] [drm:drm_atomic_set_fb_for_plane] Set [FB:85] for plane state ffff8800872290c0
>[  415.361810] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:32] ffff88016afddb00 state to ffff88016c37fe00
>[  415.361813] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:21] to ffff88016c37fe00
>[  415.361815] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88016afddb00 to [CRTC:21]
>[  415.361817] [drm:drm_atomic_check_only] checking ffff88016c37fe00
>[  415.361820] [drm:drm_atomic_helper_check_modeset] [CRTC:21] mode changed
>[  415.361822] [drm:drm_atomic_helper_check_modeset] [CRTC:21] enable changed
>[  415.361824] [drm:update_connector_routing] Updating routing for [CONNECTOR:32:eDP-1]
>[  415.361828] [drm:update_connector_routing] [CONNECTOR:32:eDP-1] using [ENCODER:31:TMDS-31] on [CRTC:21]
>[  415.361829] [drm:drm_atomic_helper_check_modeset] [CRTC:21] active changed
>[  415.361832] [drm:drm_atomic_helper_check_modeset] [CRTC:21] needs all connectors, enable: y, active: y
>[  415.361835] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:21] to ffff88016c37fe00
>[  415.361838] [drm:drm_atomic_connectors_for_crtc] State ffff88016c37fe00 has 1 connectors for [CRTC:21]
>[  415.361842] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:21] to ffff88016c37fe00
>[  415.361844] [drm:connected_sink_compute_bpp] [CONNECTOR:32:eDP-1] checking for sink bpp constrains
>[  415.361846] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  415.361852] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:21] scaler_user index 0.31
>[  415.361855] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 540000 pixel clock 361310KHz
>[  415.361857] [drm:intel_dp_compute_config] clamping bpp for eDP panel to BIOS-provided 18
>[  415.361860] [drm:intel_dp_compute_config] DP link bw 14 lane count 4 clock 540000 bpp 18
>[  415.361862] [drm:intel_dp_compute_config] DP link bw required 650358 available 1728000
>[  415.361866] [drm:intel_modeset_pipe_config] plane bpp: 36, pipe bpp: 18, dithering: 1
>[  415.361869] [drm:intel_dump_pipe_config] [CRTC:21][modeset] config ffff880086c6c400 for pipe A
>[  415.361870] [drm:intel_dump_pipe_config] cpu_transcoder: D
>[  415.361872] [drm:intel_dump_pipe_config] pipe bpp: 18, dithering: 1
>[  415.361875] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  415.361879] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 3157174, gmch_n: 8388608, link_m: 701594, link_n: 1048576, tu: 64
>[  415.361881] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  415.361883] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  415.361885] [drm:intel_dump_pipe_config] requested mode:
>[  415.361890] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 361310 3200 3248 3280 3316 1800 1802 1807 1816 0x48 0xa
>[  415.361891] [drm:intel_dump_pipe_config] adjusted mode:
>[  415.361895] [drm:drm_mode_debug_printmodeline] Modeline 0:"3200x1800" 60 361310 3200 3248 3280 3316 1800 1802 1807 1816 0x48 0xa
>[  415.361899] [drm:intel_dump_crtc_timings] crtc timings: 361310 3200 3248 3280 3316 1800 1802 1807 1816, type: 0x48 flags: 0xa
>[  415.361901] [drm:intel_dump_pipe_config] port clock: 540000
>[  415.361902] [drm:intel_dump_pipe_config] pipe src size: 3200x1800
>[  415.361905] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  415.361907] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  415.361909] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  415.361911] [drm:intel_dump_pipe_config] ips: 0
>[  415.361912] [drm:intel_dump_pipe_config] double wide: 0
>[  415.361915] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  415.361916] [drm:intel_dump_pipe_config] planes on this crtc
>[  415.361920] [drm:intel_dump_pipe_config] STANDARD PLANE:18 plane: 0.0 idx: 0 disabled, scaler_id = -1
>[  415.361922] [drm:intel_dump_pipe_config] CURSOR PLANE:20 plane: 0.1 idx: 1 disabled, scaler_id = -1
>[  415.361925] [drm:intel_dump_pipe_config] STANDARD PLANE:22 plane: 0.1 idx: 2 disabled, scaler_id = -1
>[  415.361928] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:18] scaler_user index 0.0
>[  415.361931] [drm:intel_plane_atomic_calc_changes] [CRTC:21] has [PLANE:18] with fb 85
>[  415.361934] [drm:intel_plane_atomic_calc_changes] [PLANE:18] visible 0 -> 1, off 0, on 1, ms 1
>[  415.361938] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:21] scaler_user index 0.31
>[  415.361941] [drm:intel_atomic_setup_scalers] crtc_state = ffff880086c6c400 need = 0 avail = 2 scaler_users = 0x0
>[  415.361943] [drm:drm_atomic_commit] commiting ffff88016c37fe00
>[  415.362020] [drm:intel_display_power_get] enabling DDI A/E power well
>[  415.362041] [drm:skl_set_power_well] Enabling DDI A/E power well
>[  415.362116] [drm:edp_panel_on] Turn eDP port A panel power on
>[  415.362126] [drm:wait_panel_power_cycle] Wait for panel power cycle
>[  415.362145] [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control abcd0000
>[  415.362155] [drm:wait_panel_status] Wait complete
>[  415.362180] [drm:wait_panel_on] Wait for panel power on
>[  415.362197] [drm:wait_panel_status] mask b000000f value 80000008 status 9000000a control abcd0003
>[  415.564376] [drm:wait_panel_status] Wait complete
>[  415.564505] [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[  415.564554] [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd000b
>[  415.565849] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  415.565852] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  415.565855] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.566633] [drm:intel_dp_set_signal_levels] Using signal levels 04000000
>[  415.566635] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[  415.566638] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.567403] [drm:intel_dp_set_signal_levels] Using signal levels 07000000
>[  415.567405] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[  415.567408] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.568176] [drm:intel_dp_set_signal_levels] Using signal levels 09000000
>[  415.568178] [drm:intel_dp_set_signal_levels] Using vswing level 3
>[  415.568181] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.568947] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  415.568949] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  415.568952] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.569726] [drm:intel_dp_set_signal_levels] Using signal levels 04000000
>[  415.569728] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[  415.569731] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.570495] [drm:intel_dp_set_signal_levels] Using signal levels 07000000
>[  415.570497] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[  415.570500] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.571264] [drm:intel_dp_set_signal_levels] Using signal levels 09000000
>[  415.571267] [drm:intel_dp_set_signal_levels] Using vswing level 3
>[  415.571269] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.572031] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  415.572034] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  415.572036] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.572808] [drm:intel_dp_set_signal_levels] Using signal levels 04000000
>[  415.572810] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[  415.572813] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.573576] [drm:intel_dp_set_signal_levels] Using signal levels 07000000
>[  415.573579] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[  415.573581] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.574347] [drm:intel_dp_set_signal_levels] Using signal levels 09000000
>[  415.574350] [drm:intel_dp_set_signal_levels] Using vswing level 3
>[  415.574352] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.575139] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  415.575142] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  415.575144] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.575936] [drm:intel_dp_set_signal_levels] Using signal levels 04000000
>[  415.575939] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[  415.575941] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.576702] [drm:intel_dp_set_signal_levels] Using signal levels 07000000
>[  415.576705] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[  415.576707] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.577471] [drm:intel_dp_set_signal_levels] Using signal levels 09000000
>[  415.577474] [drm:intel_dp_set_signal_levels] Using vswing level 3
>[  415.577476] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.578241] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  415.578243] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  415.578246] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.579021] [drm:intel_dp_set_signal_levels] Using signal levels 04000000
>[  415.579024] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[  415.579026] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.579786] [drm:intel_dp_set_signal_levels] Using signal levels 07000000
>[  415.579788] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[  415.579791] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.580561] [drm:intel_dp_set_signal_levels] Using signal levels 09000000
>[  415.580564] [drm:intel_dp_set_signal_levels] Using vswing level 3
>[  415.580566] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.581400] [drm:intel_dp_start_link_train [i915]] *ERROR* too many full retries, give up
>[  415.583500] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  415.583502] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  415.583505] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.584280] [drm:intel_dp_set_signal_levels] Using signal levels 04000000
>[  415.584283] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[  415.584285] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.585048] [drm:intel_dp_set_signal_levels] Using signal levels 07000000
>[  415.585050] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[  415.585053] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.585813] [drm:intel_dp_set_signal_levels] Using signal levels 09000000
>[  415.585815] [drm:intel_dp_set_signal_levels] Using vswing level 3
>[  415.585818] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.586578] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  415.586580] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  415.586582] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.587388] [drm:intel_dp_set_signal_levels] Using signal levels 04000000
>[  415.587391] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[  415.587393] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.588159] [drm:intel_dp_set_signal_levels] Using signal levels 07000000
>[  415.588161] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[  415.588164] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.588927] [drm:intel_dp_set_signal_levels] Using signal levels 09000000
>[  415.588929] [drm:intel_dp_set_signal_levels] Using vswing level 3
>[  415.588932] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.589693] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  415.589695] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  415.589698] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.590473] [drm:intel_dp_set_signal_levels] Using signal levels 04000000
>[  415.590475] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[  415.590477] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.591244] [drm:intel_dp_set_signal_levels] Using signal levels 07000000
>[  415.591246] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[  415.591249] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.592012] [drm:intel_dp_set_signal_levels] Using signal levels 09000000
>[  415.592015] [drm:intel_dp_set_signal_levels] Using vswing level 3
>[  415.592017] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.592779] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  415.592781] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  415.592783] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.593558] [drm:intel_dp_set_signal_levels] Using signal levels 04000000
>[  415.593561] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[  415.593563] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.594335] [drm:intel_dp_set_signal_levels] Using signal levels 07000000
>[  415.594337] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[  415.594340] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.595120] [drm:intel_dp_set_signal_levels] Using signal levels 09000000
>[  415.595124] [drm:intel_dp_set_signal_levels] Using vswing level 3
>[  415.595126] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.595923] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  415.595926] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  415.595929] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.596716] [drm:intel_dp_set_signal_levels] Using signal levels 04000000
>[  415.596719] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[  415.596721] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.597486] [drm:intel_dp_set_signal_levels] Using signal levels 07000000
>[  415.597489] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[  415.597491] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.598255] [drm:intel_dp_set_signal_levels] Using signal levels 09000000
>[  415.598258] [drm:intel_dp_set_signal_levels] Using vswing level 3
>[  415.598260] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.599065] [drm:intel_dp_start_link_train [i915]] *ERROR* too many full retries, give up
>[  415.601185] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  415.601188] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  415.601190] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.601963] [drm:intel_dp_set_signal_levels] Using signal levels 04000000
>[  415.601966] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[  415.601968] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.602729] [drm:intel_dp_set_signal_levels] Using signal levels 07000000
>[  415.602731] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[  415.602734] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.603497] [drm:intel_dp_set_signal_levels] Using signal levels 09000000
>[  415.603499] [drm:intel_dp_set_signal_levels] Using vswing level 3
>[  415.603502] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.604264] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  415.604267] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  415.604269] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.605042] [drm:intel_dp_set_signal_levels] Using signal levels 04000000
>[  415.605045] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[  415.605047] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.605808] [drm:intel_dp_set_signal_levels] Using signal levels 07000000
>[  415.605810] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[  415.605813] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.606575] [drm:intel_dp_set_signal_levels] Using signal levels 09000000
>[  415.606577] [drm:intel_dp_set_signal_levels] Using vswing level 3
>[  415.606580] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.607340] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  415.607342] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  415.607345] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.608134] [drm:intel_dp_set_signal_levels] Using signal levels 04000000
>[  415.608136] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[  415.608139] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.608917] [drm:intel_dp_set_signal_levels] Using signal levels 07000000
>[  415.608919] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[  415.608922] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.609683] [drm:intel_dp_set_signal_levels] Using signal levels 09000000
>[  415.609685] [drm:intel_dp_set_signal_levels] Using vswing level 3
>[  415.609688] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.610451] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  415.610453] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  415.610456] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.611229] [drm:intel_dp_set_signal_levels] Using signal levels 04000000
>[  415.611231] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[  415.611234] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.611997] [drm:intel_dp_set_signal_levels] Using signal levels 07000000
>[  415.612000] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[  415.612002] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.612763] [drm:intel_dp_set_signal_levels] Using signal levels 09000000
>[  415.612766] [drm:intel_dp_set_signal_levels] Using vswing level 3
>[  415.612769] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.613531] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  415.613534] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  415.613536] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.614324] [drm:intel_dp_set_signal_levels] Using signal levels 04000000
>[  415.614327] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[  415.614329] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.615089] [drm:intel_dp_set_signal_levels] Using signal levels 07000000
>[  415.615092] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[  415.615094] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.615857] [drm:intel_dp_set_signal_levels] Using signal levels 09000000
>[  415.615859] [drm:intel_dp_set_signal_levels] Using vswing level 3
>[  415.615862] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.616689] [drm:intel_dp_start_link_train [i915]] *ERROR* too many full retries, give up
>[  415.618790] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  415.618793] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  415.618795] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.619569] [drm:intel_dp_set_signal_levels] Using signal levels 04000000
>[  415.619571] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[  415.619574] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.620335] [drm:intel_dp_set_signal_levels] Using signal levels 07000000
>[  415.620337] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[  415.620339] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.621118] [drm:intel_dp_set_signal_levels] Using signal levels 09000000
>[  415.621121] [drm:intel_dp_set_signal_levels] Using vswing level 3
>[  415.621123] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.621902] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  415.621904] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  415.621905] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.622675] [drm:intel_dp_set_signal_levels] Using signal levels 04000000
>[  415.622678] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[  415.622680] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.623442] [drm:intel_dp_set_signal_levels] Using signal levels 07000000
>[  415.623445] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[  415.623447] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.624211] [drm:intel_dp_set_signal_levels] Using signal levels 09000000
>[  415.624213] [drm:intel_dp_set_signal_levels] Using vswing level 3
>[  415.624216] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.624979] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  415.624981] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  415.624984] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.625755] [drm:intel_dp_set_signal_levels] Using signal levels 04000000
>[  415.625758] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[  415.625760] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.626524] [drm:intel_dp_set_signal_levels] Using signal levels 07000000
>[  415.626527] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[  415.626529] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.627312] [drm:intel_dp_set_signal_levels] Using signal levels 09000000
>[  415.627314] [drm:intel_dp_set_signal_levels] Using vswing level 3
>[  415.627317] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.628077] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  415.628079] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  415.628082] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.628852] [drm:intel_dp_set_signal_levels] Using signal levels 04000000
>[  415.628855] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[  415.628858] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.629634] [drm:intel_dp_set_signal_levels] Using signal levels 07000000
>[  415.629636] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[  415.629638] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.630399] [drm:intel_dp_set_signal_levels] Using signal levels 09000000
>[  415.630401] [drm:intel_dp_set_signal_levels] Using vswing level 3
>[  415.630404] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.631166] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  415.631169] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  415.631171] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.631944] [drm:intel_dp_set_signal_levels] Using signal levels 04000000
>[  415.631946] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[  415.631949] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.632712] [drm:intel_dp_set_signal_levels] Using signal levels 07000000
>[  415.632714] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[  415.632717] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.633481] [drm:intel_dp_set_signal_levels] Using signal levels 09000000
>[  415.633483] [drm:intel_dp_set_signal_levels] Using vswing level 3
>[  415.633486] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.634294] [drm:intel_dp_start_link_train [i915]] *ERROR* too many full retries, give up
>[  415.636392] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  415.636394] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  415.636396] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.637171] [drm:intel_dp_set_signal_levels] Using signal levels 04000000
>[  415.637173] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[  415.637176] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.637938] [drm:intel_dp_set_signal_levels] Using signal levels 07000000
>[  415.637941] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[  415.637944] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.638704] [drm:intel_dp_set_signal_levels] Using signal levels 09000000
>[  415.638706] [drm:intel_dp_set_signal_levels] Using vswing level 3
>[  415.638709] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.639471] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  415.639474] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  415.639476] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.640250] [drm:intel_dp_set_signal_levels] Using signal levels 04000000
>[  415.640252] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[  415.640255] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.641017] [drm:intel_dp_set_signal_levels] Using signal levels 07000000
>[  415.641019] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[  415.641022] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.641783] [drm:intel_dp_set_signal_levels] Using signal levels 09000000
>[  415.641785] [drm:intel_dp_set_signal_levels] Using vswing level 3
>[  415.641788] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.642551] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  415.642553] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  415.642556] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.643327] [drm:intel_dp_set_signal_levels] Using signal levels 04000000
>[  415.643330] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[  415.643332] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.644110] [drm:intel_dp_set_signal_levels] Using signal levels 07000000
>[  415.644113] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[  415.644115] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.644897] [drm:intel_dp_set_signal_levels] Using signal levels 09000000
>[  415.644899] [drm:intel_dp_set_signal_levels] Using vswing level 3
>[  415.644901] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.645661] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  415.645663] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  415.645666] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.646440] [drm:intel_dp_set_signal_levels] Using signal levels 04000000
>[  415.646442] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[  415.646444] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.647206] [drm:intel_dp_set_signal_levels] Using signal levels 07000000
>[  415.647209] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[  415.647211] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.647974] [drm:intel_dp_set_signal_levels] Using signal levels 09000000
>[  415.647977] [drm:intel_dp_set_signal_levels] Using vswing level 3
>[  415.647979] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.648739] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  415.648741] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  415.648744] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.649517] [drm:intel_dp_set_signal_levels] Using signal levels 04000000
>[  415.649519] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[  415.649522] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.650305] [drm:intel_dp_set_signal_levels] Using signal levels 07000000
>[  415.650308] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[  415.650310] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.651070] [drm:intel_dp_set_signal_levels] Using signal levels 09000000
>[  415.651072] [drm:intel_dp_set_signal_levels] Using vswing level 3
>[  415.651075] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.651881] [drm:intel_dp_start_link_train [i915]] *ERROR* too many full retries, give up
>[  415.654000] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  415.654002] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  415.654005] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.654776] [drm:intel_dp_set_signal_levels] Using signal levels 04000000
>[  415.654778] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[  415.654781] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.655543] [drm:intel_dp_set_signal_levels] Using signal levels 07000000
>[  415.655545] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[  415.655548] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.656318] [drm:intel_dp_set_signal_levels] Using signal levels 09000000
>[  415.656320] [drm:intel_dp_set_signal_levels] Using vswing level 3
>[  415.656323] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.657103] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  415.657106] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  415.657108] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.657897] [drm:intel_dp_set_signal_levels] Using signal levels 04000000
>[  415.657900] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[  415.657902] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.658662] [drm:intel_dp_set_signal_levels] Using signal levels 07000000
>[  415.658665] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[  415.658667] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.659430] [drm:intel_dp_set_signal_levels] Using signal levels 09000000
>[  415.659433] [drm:intel_dp_set_signal_levels] Using vswing level 3
>[  415.659435] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.660198] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  415.660200] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  415.660203] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.660977] [drm:intel_dp_set_signal_levels] Using signal levels 04000000
>[  415.660979] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[  415.660982] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.661742] [drm:intel_dp_set_signal_levels] Using signal levels 07000000
>[  415.661745] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[  415.661747] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.662510] [drm:intel_dp_set_signal_levels] Using signal levels 09000000
>[  415.662512] [drm:intel_dp_set_signal_levels] Using vswing level 3
>[  415.662515] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.663297] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  415.663299] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  415.663301] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.664072] [drm:intel_dp_set_signal_levels] Using signal levels 04000000
>[  415.664075] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[  415.664077] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.664837] [drm:intel_dp_set_signal_levels] Using signal levels 07000000
>[  415.664839] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[  415.664842] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.665623] [drm:intel_dp_set_signal_levels] Using signal levels 09000000
>[  415.665625] [drm:intel_dp_set_signal_levels] Using vswing level 3
>[  415.665628] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.666388] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  415.666390] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  415.666393] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.667166] [drm:intel_dp_set_signal_levels] Using signal levels 04000000
>[  415.667169] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[  415.667171] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.667936] [drm:intel_dp_set_signal_levels] Using signal levels 07000000
>[  415.667938] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[  415.667941] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.668701] [drm:intel_dp_set_signal_levels] Using signal levels 09000000
>[  415.668703] [drm:intel_dp_set_signal_levels] Using vswing level 3
>[  415.668706] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.669513] [drm:intel_dp_start_link_train [i915]] *ERROR* too many full retries, give up
>[  415.671610] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  415.671612] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  415.671615] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.672387] [drm:intel_dp_set_signal_levels] Using signal levels 04000000
>[  415.672389] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[  415.672391] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.673155] [drm:intel_dp_set_signal_levels] Using signal levels 07000000
>[  415.673157] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[  415.673160] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.673923] [drm:intel_dp_set_signal_levels] Using signal levels 09000000
>[  415.673925] [drm:intel_dp_set_signal_levels] Using vswing level 3
>[  415.673928] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.674687] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  415.674690] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  415.674692] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.675466] [drm:intel_dp_set_signal_levels] Using signal levels 04000000
>[  415.675469] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[  415.675471] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.676233] [drm:intel_dp_set_signal_levels] Using signal levels 07000000
>[  415.676235] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[  415.676238] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.677000] [drm:intel_dp_set_signal_levels] Using signal levels 09000000
>[  415.677002] [drm:intel_dp_set_signal_levels] Using vswing level 3
>[  415.677005] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.677765] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  415.677767] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  415.677770] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.678543] [drm:intel_dp_set_signal_levels] Using signal levels 04000000
>[  415.678546] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[  415.678548] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.679309] [drm:intel_dp_set_signal_levels] Using signal levels 07000000
>[  415.679312] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[  415.679314] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.680095] [drm:intel_dp_set_signal_levels] Using signal levels 09000000
>[  415.680098] [drm:intel_dp_set_signal_levels] Using vswing level 3
>[  415.680100] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.680882] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  415.680884] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  415.680885] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.681657] [drm:intel_dp_set_signal_levels] Using signal levels 04000000
>[  415.681659] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[  415.681661] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.682425] [drm:intel_dp_set_signal_levels] Using signal levels 07000000
>[  415.682427] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[  415.682429] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.683192] [drm:intel_dp_set_signal_levels] Using signal levels 09000000
>[  415.683195] [drm:intel_dp_set_signal_levels] Using vswing level 3
>[  415.683197] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.683959] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  415.683962] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  415.683964] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.684738] [drm:intel_dp_set_signal_levels] Using signal levels 04000000
>[  415.684740] [drm:intel_dp_set_signal_levels] Using vswing level 1
>[  415.684743] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.685506] [drm:intel_dp_set_signal_levels] Using signal levels 07000000
>[  415.685509] [drm:intel_dp_set_signal_levels] Using vswing level 2
>[  415.685511] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.686290] [drm:intel_dp_set_signal_levels] Using signal levels 09000000
>[  415.686293] [drm:intel_dp_set_signal_levels] Using vswing level 3
>[  415.686295] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.687103] [drm:intel_dp_start_link_train [i915]] *ERROR* too many full retries, give up
>[  415.687388] [drm:intel_dp_complete_link_train [i915]] *ERROR* failed to train DP, aborting
>[  415.687598] [drm:skylake_pfit_enable] for crtc_state = ffff880086c6c400
>[  415.687845] [drm:skl_wm_flush_pipe] flush pipe A (pass 3)
>[  415.687870] [drm:intel_enable_pipe] enabling pipe A
>[  415.687897] [drm:intel_edp_backlight_on] 
>[  415.687900] [drm:intel_panel_enable_backlight] pipe A
>[  415.687960] [drm:intel_panel_actually_set_backlight] set backlight PWM = 937
>[  415.688006] [drm:intel_psr_match_conditions] PSR disable by flag
>[  415.688009] [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[  415.721267] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88016c37fe00
>[  415.721273] [drm:drm_atomic_state_free] Freeing atomic state ffff88016c37fe00
>[  415.721294] [drm:intel_connector_check_state] [CONNECTOR:32:eDP-1]
>[  415.721305] [drm:check_encoder_state] [ENCODER:31:TMDS-31]
>[  415.721310] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[  415.721314] [drm:check_encoder_state] [ENCODER:42:DP MST-42]
>[  415.721316] [drm:check_encoder_state] [ENCODER:43:DP MST-43]
>[  415.721317] [drm:check_encoder_state] [ENCODER:44:DP MST-44]
>[  415.721319] [drm:check_encoder_state] [ENCODER:47:TMDS-47]
>[  415.721322] [drm:check_encoder_state] [ENCODER:49:DP MST-49]
>[  415.721324] [drm:check_encoder_state] [ENCODER:50:DP MST-50]
>[  415.721325] [drm:check_encoder_state] [ENCODER:51:DP MST-51]
>[  415.721327] [drm:check_crtc_state] [CRTC:21]
>[  415.721362] [drm:check_crtc_state] [CRTC:25]
>[  415.721368] [drm:check_crtc_state] [CRTC:29]
>[  415.721374] [drm:check_shared_dpll_state] DPLL 1
>[  415.721378] [drm:check_shared_dpll_state] DPLL 2
>[  415.721382] [drm:check_shared_dpll_state] DPLL 3
>[  415.721391] [drm:drm_atomic_state_init] Allocated atomic state ffff88016c37fe00
>[  415.721397] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880086c68800 state to ffff88016c37fe00
>[  415.721401] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8800872299c0 state to ffff88016c37fe00
>[  415.721409] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff880086c68800
>[  415.721412] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800872299c0 to [CRTC:25]
>[  415.721415] [drm:drm_atomic_set_fb_for_plane] Set [FB:85] for plane state ffff8800872299c0
>[  415.721419] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:48] ffff88016afddb20 state to ffff88016c37fe00
>[  415.721422] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88016c37fe00
>[  415.721424] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88016afddb20 to [CRTC:25]
>[  415.721426] [drm:drm_atomic_check_only] checking ffff88016c37fe00
>[  415.721430] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  415.721432] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  415.721434] [drm:update_connector_routing] Updating routing for [CONNECTOR:48:DP-2]
>[  415.721437] [drm:update_connector_routing] [CONNECTOR:48:DP-2] using [ENCODER:47:TMDS-47] on [CRTC:25]
>[  415.721439] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  415.721441] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  415.721444] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88016c37fe00
>[  415.721448] [drm:drm_atomic_connectors_for_crtc] State ffff88016c37fe00 has 1 connectors for [CRTC:25]
>[  415.721452] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88016c37fe00
>[  415.721455] [drm:connected_sink_compute_bpp] [CONNECTOR:48:DP-2] checking for sink bpp constrains
>[  415.721457] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
>[  415.721462] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[  415.721467] [drm:intel_dp_compute_config] DP link bw 06 lane count 4 clock 162000 bpp 24
>[  415.721470] [drm:intel_dp_compute_config] DP link bw required 356400 available 518400
>[  415.721473] [drm:intel_modeset_pipe_config] plane bpp: 36, pipe bpp: 24, dithering: 1
>[  415.721477] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff880086c68800 for pipe B
>[  415.721479] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  415.721480] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 1
>[  415.721484] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  415.721487] [drm:intel_dump_pipe_config] dp: 1, gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[  415.721490] [drm:intel_dump_pipe_config] dp: 1, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  415.721491] [drm:intel_dump_pipe_config] audio: 1, infoframes: 0
>[  415.721493] [drm:intel_dump_pipe_config] requested mode:
>[  415.721498] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  415.721499] [drm:intel_dump_pipe_config] adjusted mode:
>[  415.721503] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  415.721507] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  415.721509] [drm:intel_dump_pipe_config] port clock: 162000
>[  415.721511] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
>[  415.721513] [drm:intel_dump_pipe_config] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  415.721516] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  415.721518] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  415.721519] [drm:intel_dump_pipe_config] ips: 0
>[  415.721521] [drm:intel_dump_pipe_config] double wide: 0
>[  415.721523] [drm:intel_dump_pipe_config] ddi_pll_sel: 1; dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  415.721525] [drm:intel_dump_pipe_config] planes on this crtc
>[  415.721531] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 enabled
>[  415.721534] [drm:intel_dump_pipe_config] 	FB:85, fb = 3200x1800 format = 0x34325258
>[  415.721534] [drm:intel_dump_pipe_config] 	scaler:-1 src (0, 0) 0x0 dst (0, 0) 0x0
>[  415.721537] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = -1
>[  415.721540] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = -1
>[  415.721545] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23] scaler_user index 1.3
>[  415.721548] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 85
>[  415.721551] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  415.721555] [drm:intel_get_shared_dpll] CRTC:25 allocated DPLL 1
>[  415.721557] [drm:intel_get_shared_dpll] using DPLL 1 for pipe B
>[  415.721559] [drm:skl_update_scaler_crtc] Updating scaler for [CRTC:25] scaler_user index 1.31
>[  415.721563] [drm:intel_atomic_setup_scalers] crtc_state = ffff880086c68800 need = 0 avail = 2 scaler_users = 0x0
>[  415.721565] [drm:drm_atomic_commit] commiting ffff88016c37fe00
>[  415.721586] [drm:intel_display_power_get] enabling DDI C power well
>[  415.721591] [drm:skl_set_power_well] Enabling DDI C power well
>[  415.721597] [drm:intel_enable_shared_dpll] enable DPLL 1 (active 0, on? 0) for crtc 25
>[  415.721600] [drm:intel_enable_shared_dpll] enabling DPLL 1
>[  415.724902] [drm:intel_dp_set_signal_levels] Using signal levels 01000000
>[  415.724904] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  415.724907] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[  415.725792] [drm:intel_dp_start_link_train] clock recovery OK
>[  415.726950] [drm:intel_dp_set_signal_levels] Using signal levels 02000000
>[  415.726952] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  415.726955] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 2
>[  415.728091] [drm:intel_dp_set_signal_levels] Using signal levels 01000000
>[  415.728093] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  415.728096] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[  415.729261] [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[  415.729264] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  415.729266] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[  415.730421] [drm:intel_dp_set_signal_levels] Using signal levels 01000000
>[  415.730424] [drm:intel_dp_set_signal_levels] Using vswing level 0
>[  415.730426] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1
>[  415.733636] [drm:intel_dp_complete_link_train] Channel EQ done. DP Training successful
>[  415.733828] [drm:skylake_pfit_enable] for crtc_state = ffff880086c68800
>[  415.734060] ------------[ cut here ]------------
>[  415.734093] WARNING: CPU: 0 PID: 2912 at drivers/gpu/drm/i915/intel_pm.c:3666 skl_update_other_pipe_wm+0x12e/0x16e [i915]()
>[  415.734096] WARN_ON(!wm_changed)
>[  415.734157] Modules linked in: snd_hda_codec_hdmi snd_hda_codec_realtek snd_hda_codec_generic snd_hda_intel snd_hda_codec snd_hda_core snd_hwdep snd_pcm_oss snd_mixer_oss x86_pkg_temp_thermal snd_pcm coretemp kvm_intel snd_seq_dummy kvm snd_seq_oss microcode snd_seq_midi asix usbnet serio_raw joydev input_leds snd_rawmidi snd_seq_midi_event snd_seq snd_seq_device snd_timer snd i915 soundcore drm_kms_helper syscopyarea sysfillrect sysimgblt fb_sys_fops drm shpchp wmi ipv6 bnep rfcomm bluetooth battery rfkill video ac parport_pc button acpi_cpufreq ppdev lp parport sdhci_pci sdhci led_class mmc_core
>[  415.734162] CPU: 0 PID: 2912 Comm: testdisplay Tainted: G        W       4.2.0-rc4-drm-intel-nightly-ww32+ #1
>[  415.734164] Hardware name: Intel Corporation Skylake Client platform/Skylake Y LPDDR3 RVP3, BIOS SKLSE2R1.R00.X093.B02.1507222151 07/22/2015
>[  415.734171]  0000000000000009 ffff88016adb73c8 ffffffff81896b51 0000000000000000
>[  415.734175]  ffff88016adb7418 ffff88016adb7408 ffffffff810467c3 ffff88016adb75e5
>[  415.734179]  ffffffffa0315e0e ffff88016cb2d000 ffff880086ff4000 ffff88016cb2c000
>[  415.734180] Call Trace:
>[  415.734190]  [<ffffffff81896b51>] dump_stack+0x45/0x57
>[  415.734196]  [<ffffffff810467c3>] warn_slowpath_common+0xa1/0xbb
>[  415.734226]  [<ffffffffa0315e0e>] ? skl_update_other_pipe_wm+0x12e/0x16e [i915]
>[  415.734230]  [<ffffffff81046823>] warn_slowpath_fmt+0x46/0x48
>[  415.734259]  [<ffffffffa0315e0e>] skl_update_other_pipe_wm+0x12e/0x16e [i915]
>[  415.734289]  [<ffffffffa0315fa2>] skl_update_wm+0x154/0x6d1 [i915]
>[  415.734295]  [<ffffffff81086adf>] ? mark_held_locks+0x58/0x6e
>[  415.734300]  [<ffffffff8189f621>] ? retint_kernel+0x10/0x10
>[  415.734331]  [<ffffffffa03172a8>] intel_update_watermarks+0x1e/0x20 [i915]
>[  415.734381]  [<ffffffffa036890d>] haswell_crtc_enable+0x5c9/0xaaa [i915]
>[  415.734426]  [<ffffffffa036d595>] intel_atomic_commit+0x411/0x5cd [i915]
>[  415.734460]  [<ffffffffa027699c>] drm_atomic_commit+0x4d/0x52 [drm]
>[  415.734474]  [<ffffffffa02e39f2>] drm_atomic_helper_set_config+0x316/0x371 [drm_kms_helper]
>[  415.734486]  [<ffffffffa02e3b64>] ? drm_atomic_helper_plane_set_property+0x6c/0xab [drm_kms_helper]
>[  415.734511]  [<ffffffffa02682e0>] drm_mode_set_config_internal+0x5c/0xf7 [drm]
>[  415.734523]  [<ffffffffa02e5408>] restore_fbdev_mode+0xbb/0xd5 [drm_kms_helper]
>[  415.734535]  [<ffffffffa02e6a3e>] drm_fb_helper_restore_fbdev_mode_unlocked+0x27/0x5e [drm_kms_helper]
>[  415.734545]  [<ffffffffa02e6ab4>] drm_fb_helper_set_par+0x3f/0x4b [drm_kms_helper]
>[  415.734590]  [<ffffffffa037a203>] intel_fbdev_set_par+0x1a/0x5c [i915]
>[  415.734597]  [<ffffffff8141cc03>] fb_set_var+0x2aa/0x3a0
>[  415.734603]  [<ffffffff81414d61>] fbcon_blank+0x89/0x251
>[  415.734609]  [<ffffffff81086adf>] ? mark_held_locks+0x58/0x6e
>[  415.734615]  [<ffffffff814741ed>] do_unblank_screen+0xfa/0x173
>[  415.734620]  [<ffffffff8146bd3b>] vt_ioctl+0x546/0x10f3
>[  415.734625]  [<ffffffff814615ae>] tty_ioctl+0xbe7/0xc63
>[  415.734630]  [<ffffffff81172896>] ? __fd_install+0x19a/0x1bf
>[  415.734634]  [<ffffffff8114fe6a>] ? kmem_cache_free+0xeb/0x1ba
>[  415.734637]  [<ffffffff81164fae>] ? putname+0x4a/0x4e
>[  415.734642]  [<ffffffff81086c63>] ? trace_hardirqs_on_caller+0x16e/0x18a
>[  415.734646]  [<ffffffff811681e8>] do_vfs_ioctl+0x41c/0x4e7
>[  415.734649]  [<ffffffff81164fae>] ? putname+0x4a/0x4e
>[  415.734652]  [<ffffffff811720c9>] ? __fget_light+0x50/0x75
>[  415.734655]  [<ffffffff81168306>] SyS_ioctl+0x53/0x81
>[  415.734660]  [<ffffffff8189ea97>] entry_SYSCALL_64_fastpath+0x12/0x6f
>[  415.734663] ---[ end trace 23e364efca4427fa ]---
>[  415.734720] [drm:skl_wm_flush_pipe] flush pipe A (pass 1)
>[  415.738052] [drm:skl_wm_flush_pipe] flush pipe B (pass 3)
>[  415.738065] [drm:intel_enable_pipe] enabling pipe B
>[  415.738091] [drm:intel_audio_codec_enable] ELD on [CONNECTOR:48:DP-2], [ENCODER:47:TMDS-47]
>[  415.738095] [drm:hsw_audio_codec_enable] Enable audio codec on pipe B, 36 bytes ELD
>[  415.754885] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88016c37fe00
>[  415.754893] [drm:drm_atomic_state_free] Freeing atomic state ffff88016c37fe00
>[  415.754915] [drm:intel_connector_check_state] [CONNECTOR:32:eDP-1]
>[  415.754929] [drm:intel_connector_check_state] [CONNECTOR:48:DP-2]
>[  415.754941] [drm:check_encoder_state] [ENCODER:31:TMDS-31]
>[  415.754946] [drm:check_encoder_state] [ENCODER:40:TMDS-40]
>[  415.754949] [drm:check_encoder_state] [ENCODER:42:DP MST-42]
>[  415.754951] [drm:check_encoder_state] [ENCODER:43:DP MST-43]
>[  415.754952] [drm:check_encoder_state] [ENCODER:44:DP MST-44]
>[  415.754954] [drm:check_encoder_state] [ENCODER:47:TMDS-47]
>[  415.754960] [drm:check_encoder_state] [ENCODER:49:DP MST-49]
>[  415.754962] [drm:check_encoder_state] [ENCODER:50:DP MST-50]
>[  415.754963] [drm:check_encoder_state] [ENCODER:51:DP MST-51]
>[  415.754965] [drm:check_crtc_state] [CRTC:21]
>[  415.755000] [drm:check_crtc_state] [CRTC:25]
>[  415.755044] [drm:check_crtc_state] [CRTC:29]
>[  415.755050] [drm:check_shared_dpll_state] DPLL 1
>[  415.755055] [drm:check_shared_dpll_state] DPLL 2
>[  415.755059] [drm:check_shared_dpll_state] DPLL 3
>[  415.755067] [drm:drm_atomic_state_init] Allocated atomic state ffff88016c37fe00
>[  415.755074] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff880086c69000 state to ffff88016c37fe00
>[  415.755078] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8800872296c0 state to ffff88016c37fe00
>[  415.755080] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff880086c69000
>[  415.755082] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800872296c0 to [NOCRTC]
>[  415.755084] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8800872296c0
>[  415.755088] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:29] to ffff88016c37fe00
>[  415.755091] [drm:drm_atomic_check_only] checking ffff88016c37fe00
>[  415.755097] [drm:intel_atomic_setup_scalers] crtc_state = ffff880086c69000 need = 0 avail = 1 scaler_users = 0x0
>[  415.755100] [drm:drm_atomic_commit] commiting ffff88016c37fe00
>[  415.755109] [drm:skl_detach_scaler] CRTC:29 Disabled scaler id 2.0
>[  415.755114] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88016c37fe00
>[  415.755118] [drm:drm_atomic_state_free] Freeing atomic state ffff88016c37fe00
>[  415.755148] [drm:drm_atomic_state_init] Allocated atomic state ffff88016c37fe00
>[  415.755152] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff880086c69800 state to ffff88016c37fe00
>[  415.755155] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff880087229b40 state to ffff88016c37fe00
>[  415.755163] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffff880086c69800
>[  415.755166] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880087229b40 to [CRTC:21]
>[  415.755168] [drm:drm_atomic_set_fb_for_plane] Set [FB:85] for plane state ffff880087229b40
>[  415.755172] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:32] ffff88016afddb40 state to ffff88016c37fe00
>[  415.755175] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:21] to ffff88016c37fe00
>[  415.755178] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88016afddb40 to [NOCRTC]
>[  415.755180] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88016afddb40 to [CRTC:21]
>[  415.755182] [drm:drm_atomic_check_only] checking ffff88016c37fe00
>[  415.755193] [drm:update_connector_routing] Updating routing for [CONNECTOR:32:eDP-1]
>[  415.755197] [drm:update_connector_routing] [CONNECTOR:32:eDP-1] keeps [ENCODER:31:TMDS-31], now on [CRTC:21]
>[  415.755203] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:18] scaler_user index 0.0
>[  415.755206] [drm:intel_plane_atomic_calc_changes] [CRTC:21] has [PLANE:18] with fb 85
>[  415.755209] [drm:intel_plane_atomic_calc_changes] [PLANE:18] visible 1 -> 1, off 0, on 0, ms 0
>[  415.755212] [drm:intel_atomic_setup_scalers] crtc_state = ffff880086c69800 need = 0 avail = 2 scaler_users = 0x0
>[  415.755214] [drm:drm_atomic_commit] commiting ffff88016c37fe00
>[  415.755244] [drm:skl_detach_scaler] CRTC:21 Disabled scaler id 0.0
>[  415.755248] [drm:skl_detach_scaler] CRTC:21 Disabled scaler id 0.1
>[  415.755265] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88016c37fe00
>[  415.755272] [drm:drm_atomic_state_free] Freeing atomic state ffff88016c37fe00
>[  415.755278] [drm:drm_atomic_state_init] Allocated atomic state ffff88016c37fe00
>[  415.755281] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880086c6c400 state to ffff88016c37fe00
>[  415.755284] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8800872290c0 state to ffff88016c37fe00
>[  415.755290] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff880086c6c400
>[  415.755292] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800872290c0 to [CRTC:25]
>[  415.755294] [drm:drm_atomic_set_fb_for_plane] Set [FB:85] for plane state ffff8800872290c0
>[  415.755298] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:48] ffff88016afddb00 state to ffff88016c37fe00
>[  415.755301] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88016c37fe00
>[  415.755304] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88016afddb00 to [NOCRTC]
>[  415.755306] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88016afddb00 to [CRTC:25]
>[  415.755308] [drm:drm_atomic_check_only] checking ffff88016c37fe00
>[  415.755311] [drm:update_connector_routing] Updating routing for [CONNECTOR:48:DP-2]
>[  415.755314] [drm:update_connector_routing] [CONNECTOR:48:DP-2] keeps [ENCODER:47:TMDS-47], now on [CRTC:25]
>[  415.755317] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23] scaler_user index 1.3
>[  415.755320] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 85
>[  415.755322] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 1, off 0, on 0, ms 0
>[  415.755325] [drm:intel_atomic_setup_scalers] crtc_state = ffff880086c6c400 need = 0 avail = 2 scaler_users = 0x0
>[  415.755327] [drm:drm_atomic_commit] commiting ffff88016c37fe00
>[  415.755351] [drm:skl_detach_scaler] CRTC:25 Disabled scaler id 1.0
>[  415.755355] [drm:skl_detach_scaler] CRTC:25 Disabled scaler id 1.1
>[  415.755369] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88016c37fe00
>[  415.755374] [drm:drm_atomic_state_free] Freeing atomic state ffff88016c37fe00
>[  415.755420] [drm:drm_atomic_state_init] Allocated atomic state ffff88016c37fe00
>[  415.755423] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff880086c68800 state to ffff88016c37fe00
>[  415.755426] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8800872299c0 state to ffff88016c37fe00
>[  415.755432] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffff880086c68800
>[  415.755434] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800872299c0 to [CRTC:21]
>[  415.755436] [drm:drm_atomic_set_fb_for_plane] Set [FB:85] for plane state ffff8800872299c0
>[  415.755440] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:32] ffff88016afddb20 state to ffff88016c37fe00
>[  415.755443] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:21] to ffff88016c37fe00
>[  415.755445] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88016afddb20 to [NOCRTC]
>[  415.755447] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88016afddb20 to [CRTC:21]
>[  415.755449] [drm:drm_atomic_check_only] checking ffff88016c37fe00
>[  415.755451] [drm:update_connector_routing] Updating routing for [CONNECTOR:32:eDP-1]
>[  415.755454] [drm:update_connector_routing] [CONNECTOR:32:eDP-1] keeps [ENCODER:31:TMDS-31], now on [CRTC:21]
>[  415.755457] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:18] scaler_user index 0.0
>[  415.755459] [drm:intel_plane_atomic_calc_changes] [CRTC:21] has [PLANE:18] with fb 85
>[  415.755462] [drm:intel_plane_atomic_calc_changes] [PLANE:18] visible 1 -> 1, off 0, on 0, ms 0
>[  415.755464] [drm:intel_atomic_setup_scalers] crtc_state = ffff880086c68800 need = 0 avail = 2 scaler_users = 0x0
>[  415.755466] [drm:drm_atomic_commit] commiting ffff88016c37fe00
>[  415.755490] [drm:skl_detach_scaler] CRTC:21 Disabled scaler id 0.0
>[  415.755493] [drm:skl_detach_scaler] CRTC:21 Disabled scaler id 0.1
>[  415.755507] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88016c37fe00
>[  415.755513] [drm:drm_atomic_state_free] Freeing atomic state ffff88016c37fe00
>[  415.755519] [drm:drm_atomic_state_init] Allocated atomic state ffff88016c37fe00
>[  415.755522] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880086c69800 state to ffff88016c37fe00
>[  415.755525] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff880087229b40 state to ffff88016c37fe00
>[  415.755530] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff880086c69800
>[  415.755532] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880087229b40 to [CRTC:25]
>[  415.755534] [drm:drm_atomic_set_fb_for_plane] Set [FB:85] for plane state ffff880087229b40
>[  415.755538] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:48] ffff88016afddb40 state to ffff88016c37fe00
>[  415.755541] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88016c37fe00
>[  415.755544] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88016afddb40 to [NOCRTC]
>[  415.755546] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88016afddb40 to [CRTC:25]
>[  415.755547] [drm:drm_atomic_check_only] checking ffff88016c37fe00
>[  415.755550] [drm:update_connector_routing] Updating routing for [CONNECTOR:48:DP-2]
>[  415.755552] [drm:update_connector_routing] [CONNECTOR:48:DP-2] keeps [ENCODER:47:TMDS-47], now on [CRTC:25]
>[  415.755555] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23] scaler_user index 1.3
>[  415.755557] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 85
>[  415.755560] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 1, off 0, on 0, ms 0
>[  415.755562] [drm:intel_atomic_setup_scalers] crtc_state = ffff880086c69800 need = 0 avail = 2 scaler_users = 0x0
>[  415.755564] [drm:drm_atomic_commit] commiting ffff88016c37fe00
>[  415.755587] [drm:skl_detach_scaler] CRTC:25 Disabled scaler id 1.0
>[  415.755590] [drm:skl_detach_scaler] CRTC:25 Disabled scaler id 1.1
>[  415.755604] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88016c37fe00
>[  415.755609] [drm:drm_atomic_state_free] Freeing atomic state ffff88016c37fe00
>[  415.812997] [drm:drm_atomic_state_init] Allocated atomic state ffff88016c37fe00
>[  415.813007] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff880087229300 state to ffff88016c37fe00
>[  415.813013] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff880086c6a400 state to ffff88016c37fe00
>[  415.813017] [drm:drm_atomic_check_only] checking ffff88016c37fe00
>[  415.813024] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:18] scaler_user index 0.0
>[  415.813028] [drm:intel_plane_atomic_calc_changes] [CRTC:21] has [PLANE:18] with fb 85
>[  415.813033] [drm:intel_plane_atomic_calc_changes] [PLANE:18] visible 1 -> 1, off 0, on 0, ms 0
>[  415.813038] [drm:intel_atomic_setup_scalers] crtc_state = ffff880086c6a400 need = 0 avail = 2 scaler_users = 0x0
>[  415.813042] [drm:drm_atomic_commit] commiting ffff88016c37fe00
>[  415.813089] [drm:skl_detach_scaler] CRTC:21 Disabled scaler id 0.0
>[  415.813095] [drm:skl_detach_scaler] CRTC:21 Disabled scaler id 0.1
>[  415.813115] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88016c37fe00
>[  415.813121] [drm:drm_atomic_state_free] Freeing atomic state ffff88016c37fe00
>[  415.813129] [drm:drm_atomic_state_init] Allocated atomic state ffff88016c37fe00
>[  415.813134] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8800872299c0 state to ffff88016c37fe00
>[  415.813138] [drm:drm_atomic_check_only] checking ffff88016c37fe00
>[  415.813142] [drm:drm_atomic_commit] commiting ffff88016c37fe00
>[  415.813147] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88016c37fe00
>[  415.813151] [drm:drm_atomic_state_free] Freeing atomic state ffff88016c37fe00
>[  415.813158] [drm:drm_atomic_state_init] Allocated atomic state ffff88016c37fe00
>[  415.813163] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff880087229780 state to ffff88016c37fe00
>[  415.813166] [drm:drm_atomic_check_only] checking ffff88016c37fe00
>[  415.813170] [drm:drm_atomic_commit] commiting ffff88016c37fe00
>[  415.813174] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88016c37fe00
>[  415.813178] [drm:drm_atomic_state_free] Freeing atomic state ffff88016c37fe00
>[  415.813193] [drm:drm_atomic_state_init] Allocated atomic state ffff88016c37fe00
>[  415.813206] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff880087229480 state to ffff88016c37fe00
>[  415.813217] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880086c68800 state to ffff88016c37fe00
>[  415.813226] [drm:drm_atomic_check_only] checking ffff88016c37fe00
>[  415.813238] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23] scaler_user index 1.3
>[  415.813248] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 85
>[  415.813258] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 1, off 0, on 0, ms 0
>[  415.813268] [drm:intel_atomic_setup_scalers] crtc_state = ffff880086c68800 need = 0 avail = 2 scaler_users = 0x0
>[  415.813277] [drm:drm_atomic_commit] commiting ffff88016c37fe00
>[  415.813309] [drm:skl_detach_scaler] CRTC:25 Disabled scaler id 1.0
>[  415.813319] [drm:skl_detach_scaler] CRTC:25 Disabled scaler id 1.1
>[  415.813339] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88016c37fe00
>[  415.813348] [drm:drm_atomic_state_free] Freeing atomic state ffff88016c37fe00
>[  415.813360] [drm:drm_atomic_state_init] Allocated atomic state ffff88016c37fe00
>[  415.813373] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff880087229b40 state to ffff88016c37fe00
>[  415.813382] [drm:drm_atomic_check_only] checking ffff88016c37fe00
>[  415.813394] [drm:drm_atomic_commit] commiting ffff88016c37fe00
>[  415.813406] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88016c37fe00
>[  415.813418] [drm:drm_atomic_state_free] Freeing atomic state ffff88016c37fe00
>[  415.813433] [drm:drm_atomic_state_init] Allocated atomic state ffff88016c37fe00
>[  415.813442] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff880087229e40 state to ffff88016c37fe00
>[  415.813451] [drm:drm_atomic_check_only] checking ffff88016c37fe00
>[  415.813463] [drm:drm_atomic_commit] commiting ffff88016c37fe00
>[  415.813475] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88016c37fe00
>[  415.813487] [drm:drm_atomic_state_free] Freeing atomic state ffff88016c37fe00
>[  415.813499] [drm:drm_atomic_state_init] Allocated atomic state ffff88016c37fe00
>[  415.813511] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff880087229540 state to ffff88016c37fe00
>[  415.813520] [drm:drm_atomic_check_only] checking ffff88016c37fe00
>[  415.813531] [drm:drm_atomic_commit] commiting ffff88016c37fe00
>[  415.813543] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88016c37fe00
>[  415.813555] [drm:drm_atomic_state_free] Freeing atomic state ffff88016c37fe00
>[  415.813562] [drm:drm_atomic_state_init] Allocated atomic state ffff88016c37fe00
>[  415.813567] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8800872296c0 state to ffff88016c37fe00
>[  415.813570] [drm:drm_atomic_check_only] checking ffff88016c37fe00
>[  415.813573] [drm:drm_atomic_commit] commiting ffff88016c37fe00
>[  415.813577] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88016c37fe00
>[  415.813581] [drm:drm_atomic_state_free] Freeing atomic state ffff88016c37fe00
>[  415.813588] [drm:drm_atomic_state_init] Allocated atomic state ffff88016c37fe00
>[  415.813593] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff880087229600 state to ffff88016c37fe00
>[  415.813596] [drm:drm_atomic_check_only] checking ffff88016c37fe00
>[  415.813599] [drm:drm_atomic_commit] commiting ffff88016c37fe00
>[  415.813603] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88016c37fe00
>[  415.813607] [drm:drm_atomic_state_free] Freeing atomic state ffff88016c37fe00
>[  415.813614] [drm:drm_atomic_state_init] Allocated atomic state ffff88016c37fe00
>[  415.813619] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff880086c69800 state to ffff88016c37fe00
>[  415.813624] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff880087229000 state to ffff88016c37fe00
>[  415.813632] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:3200x1800] for CRTC state ffff880086c69800
>[  415.813636] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880087229000 to [CRTC:21]
>[  415.813640] [drm:drm_atomic_set_fb_for_plane] Set [FB:85] for plane state ffff880087229000
>[  415.813645] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:32] ffff88016afddac0 state to ffff88016c37fe00
>[  415.813650] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:21] to ffff88016c37fe00
>[  415.813655] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88016afddac0 to [NOCRTC]
>[  415.813658] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88016afddac0 to [CRTC:21]
>[  415.813662] [drm:drm_atomic_check_only] checking ffff88016c37fe00
>[  415.813666] [drm:update_connector_routing] Updating routing for [CONNECTOR:32:eDP-1]
>[  415.813671] [drm:update_connector_routing] [CONNECTOR:32:eDP-1] keeps [ENCODER:31:TMDS-31], now on [CRTC:21]
>[  415.813675] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:18] scaler_user index 0.0
>[  415.813679] [drm:intel_plane_atomic_calc_changes] [CRTC:21] has [PLANE:18] with fb 85
>[  415.813683] [drm:intel_plane_atomic_calc_changes] [PLANE:18] visible 1 -> 1, off 0, on 0, ms 0
>[  415.813688] [drm:intel_atomic_setup_scalers] crtc_state = ffff880086c69800 need = 0 avail = 2 scaler_users = 0x0
>[  415.813691] [drm:drm_atomic_commit] commiting ffff88016c37fe00
>[  415.813717] [drm:skl_detach_scaler] CRTC:21 Disabled scaler id 0.0
>[  415.813722] [drm:skl_detach_scaler] CRTC:21 Disabled scaler id 0.1
>[  415.813738] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88016c37fe00
>[  415.813746] [drm:drm_atomic_state_free] Freeing atomic state ffff88016c37fe00
>[  415.813754] [drm:drm_atomic_state_init] Allocated atomic state ffff88016c37fe00
>[  415.813767] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880086c6a400 state to ffff88016c37fe00
>[  415.813779] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff880087229300 state to ffff88016c37fe00
>[  415.813793] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff880086c6a400
>[  415.813803] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880087229300 to [CRTC:25]
>[  415.813822] [drm:drm_atomic_set_fb_for_plane] Set [FB:85] for plane state ffff880087229300
>[  415.813827] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:48] ffff88016afddb20 state to ffff88016c37fe00
>[  415.813840] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88016c37fe00
>[  415.813852] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88016afddb20 to [NOCRTC]
>[  415.813862] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88016afddb20 to [CRTC:25]
>[  415.813870] [drm:drm_atomic_check_only] checking ffff88016c37fe00
>[  415.813882] [drm:update_connector_routing] Updating routing for [CONNECTOR:48:DP-2]
>[  415.813893] [drm:update_connector_routing] [CONNECTOR:48:DP-2] keeps [ENCODER:47:TMDS-47], now on [CRTC:25]
>[  415.813906] [drm:skl_update_scaler_plane] Updating scaler for [PLANE:23] scaler_user index 1.3
>[  415.813916] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 85
>[  415.813925] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 1, off 0, on 0, ms 0
>[  415.813935] [drm:intel_atomic_setup_scalers] crtc_state = ffff880086c6a400 need = 0 avail = 2 scaler_users = 0x0
>[  415.813945] [drm:drm_atomic_commit] commiting ffff88016c37fe00
>[  415.813979] [drm:skl_detach_scaler] CRTC:25 Disabled scaler id 1.0
>[  415.813991] [drm:skl_detach_scaler] CRTC:25 Disabled scaler id 1.1
>[  415.814015] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88016c37fe00
>[  415.814027] [drm:drm_atomic_state_free] Freeing atomic state ffff88016c37fe00
>[  415.814042] [drm:drm_atomic_state_init] Allocated atomic state ffff88016c37fe00
>[  415.814055] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff880086c68800 state to ffff88016c37fe00
>[  415.814067] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff880087229480 state to ffff88016c37fe00
>[  415.814079] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff880086c68800
>[  415.814089] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880087229480 to [NOCRTC]
>[  415.814098] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880087229480
>[  415.814110] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:29] to ffff88016c37fe00
>[  415.814119] [drm:drm_atomic_check_only] checking ffff88016c37fe00
>[  415.814131] [drm:intel_atomic_setup_scalers] crtc_state = ffff880086c68800 need = 0 avail = 1 scaler_users = 0x0
>[  415.814139] [drm:drm_atomic_commit] commiting ffff88016c37fe00
>[  415.814154] [drm:skl_detach_scaler] CRTC:29 Disabled scaler id 2.0
>[  415.814170] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88016c37fe00
>[  415.814176] [drm:drm_atomic_state_free] Freeing atomic state ffff88016c37fe00
>[  418.694127] [drm:edp_panel_vdd_off_sync] Turning eDP port A VDD off
>[  418.694175] [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0xabcd0007

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Attachments on bug 90237: 115446 | 116866 | 117541 | 117542 | 117556

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