Attachment 118020 Details for Bug 91828 – Log of running Xonotic with R600_DEBUG=llvm,ps,vs. The last shader causes assertion.

Log of running Xonotic with R600_DEBUG=llvm,ps,vs. The last shader causes assertion.

xonotic.r600.llvm.ps.vs.txt (text/plain), 352.05 KB, created by iive on 2015-08-31 20:23:15 UTC

(hide)

Description:

Filename:

MIME Type:

Creator: iive

Created: 2015-08-31 20:23:15 UTC

Size: 352.05 KB

patch

obsolete

>Game is Xonotic using base gamedir data
>gamename for server filtering: Xonotic
>Xonotic Linux 02:07:41 Aug 25 2015 - release
>Current nice level is below the soft limit - cannot use niceness
>Skeletal animation uses SSE code path
>DPSOFTRAST available (SSE2 instructions detected)
>execing quake.rc
>execing default.cfg
>execing defaultXonotic.cfg
>execing sRGB-disable.cfg
>menu: program is not loaded
>execing weapons.cfg
>execing binds-xonotic.cfg
>execing cdtracks.cfg
>execing balance-xonotic.cfg
>execing bal-wep-xonotic.cfg
>execing effects-normal.cfg
>execing physicsX.cfg
>execing turrets.cfg
>execing unit_machinegun.cfg
>execing unit_hk.cfg
>execing unit_hellion.cfg
>execing unit_mlrs.cfg
>execing unit_flac.cfg
>execing unit_fusreac.cfg
>execing unit_plasma.cfg
>execing unit_plasma2.cfg
>execing unit_tesla.cfg
>execing unit_phaser.cfg
>execing unit_walker.cfg
>execing unit_ewheel.cfg
>execing vehicles.cfg
>execing vehicle_racer.cfg
>execing vehicle_raptor.cfg
>execing vehicle_spiderbot.cfg
>execing vehicle_bumblebee.cfg
>execing crosshairs.cfg
>execing gamemodes.cfg
>execing ctfscoring-samual.cfg
>execing mutators.cfg
>execing notifications.cfg
>execing monsters.cfg
>execing physics.cfg
>execing commands.cfg
>execing _hud_common.cfg
>execing _hud_descriptions.cfg
>execing hud_luma.cfg
>execing config.cfg
>"maxplayers" set to "16"
>execing data/campaign.cfg
>execing config_update.cfg
>execing font-xolonium.cfg
>client: program is not loaded
>execing autoexec/empty.cfg
>execing autoexec.cfg
>Loaded public key key_0.d0pk (fingerprint: Xon//KssdlzGkFKdnnN4sgg8H+koTbBn5JTi37BAW1Q=)
>Loaded private ID key_0.d0si for key_0.d0pk (public key fingerprint: 8Zy9h8bUlYB0IG0UG6fHIfTohxj2i2KLvhUPbmLdYY4=)
>there is already a signed private key for 0
>execing post-config.cfg
>Client using an automatically assigned port
>Client opened a socket on address 0.0.0.0:0
>Client opened a socket on address [0:0:0:0:0:0:0:0]:0
>Loading OpenGL driver libGL.so.1
>ATTENTION: default value of option force_s3tc_enable overridden by environment.
>ATTENTION: default value of option vblank_mode overridden by environment.
>Mesa: Mesa GL_VERSION = 3.0 Mesa 11.1.0-devel (git-16ad1d2)
>Mesa: Mesa GL_RENDERER = Gallium 0.4 on AMD REDWOOD (DRM 2.42.0, LLVM 3.6.2)
>Mesa: Mesa GL_VENDOR = X.Org
>Mesa: Mesa GL_EXTENSIONS = GL_ARB_multisample GL_EXT_abgr GL_EXT_bgra GL_EXT_blend_color GL_EXT_blend_minmax GL_EXT_blend_subtract GL_EXT_copy_texture GL_EXT_polygon_offset GL_EXT_subtexture GL_EXT_texture_object GL_EXT_vertex_array GL_EXT_compiled_vertex_array GL_EXT_texture GL_EXT_texture3D GL_IBM_rasterpos_clip GL_ARB_point_parameters GL_EXT_draw_range_elements GL_EXT_packed_pixels GL_EXT_point_parameters GL_EXT_rescale_normal GL_EXT_separate_specular_color GL_EXT_texture_edge_clamp GL_SGIS_generate_mipmap GL_SGIS_texture_border_clamp GL_SGIS_texture_edge_clamp GL_SGIS_texture_lod GL_ARB_framebuffer_sRGB GL_ARB_multitexture GL_EXT_framebuffer_sRGB GL_IBM_multimode_draw_arrays GL_IBM_texture_mirrored_repeat GL_ARB_texture_cube_map GL_ARB_texture_env_add GL_ARB_transpose_matrix GL_EXT_blend_func_separate GL_EXT_fog_coord GL_EXT_multi_draw_arrays GL_EXT_secondary_color GL_EXT_texture_env_add GL_EXT_texture_filter_anisotropic GL_EXT_texture_lod_bias GL_INGR_blend_func_separate GL_NV_blend_square GL_NV_light_max_exponent GL_NV_texgen_reflection GL_NV_texture_env_combine4 GL_S3_s3tc GL_SUN_multi_draw_arrays GL_ARB_texture_border_clamp GL_ARB_texture_compression GL_EXT_framebuffer_object GL_EXT_texture_compression_s3tc GL_EXT_texture_env_combine GL_EXT_texture_env_dot3 GL_MESA_window_pos GL_NV_packed_depth_stencil GL_NV_texture_rectangle GL_ARB_depth_texture GL_ARB_occlusion_query GL_ARB_shadow GL_ARB_texture_env_combine GL_ARB_texture_env_crossbar GL_ARB_texture_env_dot3 GL_ARB_texture_mirrored_repeat GL_ARB_window_pos GL_EXT_stencil_two_side GL_EXT_texture_cube_map GL_NV_depth_clamp GL_NV_fog_distance GL_APPLE_packed_pixels GL_APPLE_vertex_array_object GL_ARB_draw_buffers GL_ARB_fragment_program GL_ARB_fragment_shader GL_ARB_shader_objects GL_ARB_vertex_program GL_ARB_vertex_shader GL_ATI_draw_buffers GL_ATI_texture_env_combine3 GL_ATI_texture_float GL_EXT_shadow_funcs GL_EXT_stencil_wrap GL_MESA_pack_invert GL_NV_primitive_restart GL_ARB_depth_clamp GL_ARB_fragment_program_shadow GL_ARB_half_float_pixel GL_ARB_occlusion_query2 GL_ARB_point_sprite GL_ARB_shading_language_100 GL_ARB_sync GL_ARB_texture_non_power_of_two GL_ARB_vertex_buffer_object GL_ATI_blend_equation_separate GL_EXT_blend_equation_separate GL_OES_read_format GL_ARB_color_buffer_float GL_ARB_pixel_buffer_object GL_ARB_texture_compression_rgtc GL_ARB_texture_float GL_ARB_texture_rectangle GL_ATI_texture_compression_3dc GL_EXT_packed_float GL_EXT_pixel_buffer_object GL_EXT_texture_compression_dxt1 GL_EXT_texture_compression_rgtc GL_EXT_texture_mirror_clamp GL_EXT_texture_rectangle GL_EXT_texture_sRGB GL_EXT_texture_shared_exponent GL_ARB_framebuffer_object GL_EXT_framebuffer_blit GL_EXT_framebuffer_multisample GL_EXT_packed_depth_stencil GL_ARB_vertex_array_object GL_ATI_separate_stencil GL_ATI_texture_mirror_once GL_EXT_draw_buffers2 GL_EXT_draw_instanced GL_EXT_gpu_program_parameters GL_EXT_texture_array GL_EXT_texture_compression_latc GL_EXT_texture_integer GL_EXT_texture_sRGB_decode GL_EXT_timer_query GL_OES_EGL_image GL_ARB_copy_buffer GL_ARB_depth_buffer_float GL_ARB_draw_instanced GL_ARB_half_float_vertex GL_ARB_instanced_arrays GL_ARB_map_buffer_range GL_ARB_texture_rg GL_ARB_texture_swizzle GL_ARB_vertex_array_bgra GL_EXT_texture_swizzle GL_EXT_vertex_array_bgra GL_NV_conditional_render GL_AMD_conservative_depth GL_AMD_draw_buffers_blend GL_AMD_seamless_cubemap_per_texture GL_AMD_shader_stencil_export GL_ARB_ES2_compatibility GL_ARB_blend_func_extended GL_ARB_debug_output GL_ARB_draw_buffers_blend GL_ARB_draw_elements_base_vertex GL_ARB_explicit_attrib_location GL_ARB_fragment_coord_conventions GL_ARB_provoking_vertex GL_ARB_sample_shading GL_ARB_sampler_objects GL_ARB_seamless_cube_map GL_ARB_shader_stencil_export GL_ARB_shader_texture_lod GL_ARB_texture_cube_map_array GL_ARB_texture_gather GL_ARB_texture_multisample GL_ARB_texture_query_lod GL_ARB_texture_rgb10_a2ui GL_ARB_uniform_buffer_object GL_ARB_vertex_type_2_10_10_10_rev GL_EXT_provoking_vertex GL_EXT_texture_snorm GL_MESA_texture_signed_rgba GL_NV_texture_barrier GL_ARB_get_program_binary GL_ARBMesa: Mesa x86-optimized: YES
>Mesa: Mesa sparc-optimized: NO
>GL_VENDOR: X.Org
>GL_RENDERER: Gallium 0.4 on AMD REDWOOD (DRM 2.42.0, LLVM 3.6.2)
>GL_VERSION: 3.0 Mesa 11.1.0-devel (git-16ad1d2)
>vid.support.arb_multisample 1
>vid.support.gl20shaders 1
>NOTE: requested 1x AA, got 0x AA
>Video Mode: fullscreen 1024x768x32x0.00hz
>--------------------------------------------------------------
>FRAG
>DCL IN[0], GENERIC[0], LINEAR
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SVIEW[0], 2D, FLOAT
>  0: TEX OUT[0], IN[0], SAMP[0], 2D
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main(<4 x float> inreg, <4 x float> inreg) #0 {
>main_body:
>  %2 = extractelement <4 x float> %0, i32 0
>  %3 = extractelement <4 x float> %0, i32 1
>  %4 = call <2 x float> @llvm.R600.interp.xy(i32 0, float %2, float %3)
>  %5 = call <2 x float> @llvm.R600.interp.zw(i32 0, float %2, float %3)
>  %6 = shufflevector <2 x float> %4, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
>  %7 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %6, i32 16, i32 0, i32 2)
>  call void @llvm.R600.store.swizzle(<4 x float> %7, i32 0, i32 0)
>  ret void
>}
>
>; Function Attrs: readnone
>declare <2 x float> @llvm.R600.interp.xy(i32, float, float) #1
>
>; Function Attrs: readnone
>declare <2 x float> @llvm.R600.interp.zw(i32, float, float) #1
>
>; Function Attrs: readnone
>declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32, i32) #1
>
>declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { readnone }
>
>===== SHADER #11 ==================================== PS/REDWOOD/EVERGREEN =====
>===== 20 dw ===== 1 gprs ===== 0 stack =========================================
>0000  00000006 a00c0000 ALU 4 @12
> 0012  00380400 00146b10     1      x: INTERP_XY          R0.x,  R0.y, Param0.x         VEC_210
> 0014  00380000 20146b10            y: INTERP_XY          R0.y,  R0.x, Param0.x         VEC_210
> 0016  00380400 40146b00            z: INTERP_XY          __.z,  R0.y, Param0.x         VEC_210
> 0018  80380000 60146b00            w: INTERP_XY          __.w,  R0.x, Param0.x         VEC_210
>0002  00000004 80400000 TEX 1 @8
> 0008  00001010 f00d1000 fc800000 SAMPLE              R0.xyzw, R0.xy__,   RID:16, SID:0 CT:NNNN
>0004  c0000000 95200688 EXPORT_DONE        PIXEL 0     R0.xyzw  EOP
>===== SHADER_END ===============================================================
>
>
>===== SHADER #11 OPT ================================ PS/REDWOOD/EVERGREEN =====
>===== 20 dw ===== 1 gprs ===== 0 stack =========================================
>0000  00000003 a00c0000 ALU 4 @6
> 0006  00380400 00146b10     1      x: INTERP_XY          R0.x,  R0.y, Param0.x         VEC_210
> 0008  00b80000 20146b10            y: INTERP_XY          R0.y,  R0.x, Param0.y         VEC_210
> 0010  01380400 40146b00            z: INTERP_XY          __.z,  R0.y, Param0.z         VEC_210
> 0012  81b80000 60146b00            w: INTERP_XY          __.w,  R0.x, Param0.w         VEC_210
>0002  00000008 80400000 TEX 1 @16
> 0016  00001010 f00d1000 fc800000 SAMPLE              R0.xyzw, R0.xy__,   RID:16, SID:0 CT:NNNN
>0004  c0000000 95200688 EXPORT_DONE        PIXEL 0     R0.xyzw  EOP
>===== SHADER_END ===============================================================
>
>--------------------------------------------------------------
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[0]
>  0: MOV OUT[0], IN[0]
>  1: MOV OUT[1], IN[1]
>  2: END
>; ModuleID = 'tgsi'
>
>define void @main(<4 x float> inreg, <4 x float> inreg, <4 x float> inreg) #0 {
>main_body:
>  call void @llvm.R600.store.swizzle(<4 x float> %1, i32 60, i32 1)
>  call void @llvm.R600.store.swizzle(<4 x float> %2, i32 0, i32 2)
>  ret void
>}
>
>declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
>
>attributes #0 = { "ShaderType"="1" }
>
>===== SHADER #12 ==================================== VS/REDWOOD/EVERGREEN =====
>===== 8 dw ===== 3 gprs ===== 1 stack ==========================================
>0000  00000000 84c00000 CALL_FS @0
>0002  c000a03c 95000688 EXPORT_DONE        POS   60    R1.xyzw
>0004  c0014000 95200688 EXPORT_DONE        PARAM 0     R2.xyzw  EOP
>===== SHADER_END ===============================================================
>
>
>===== SHADER #12 OPT ================================ VS/REDWOOD/EVERGREEN =====
>===== 6 dw ===== 3 gprs ===== 1 stack ==========================================
>0000  00000000 84c00000 CALL_FS @0
>0002  c0014000 95000688 EXPORT_DONE        PARAM 0     R2.xyzw
>0004  c000a03c 95200688 EXPORT_DONE        POS   60    R1.xyzw  EOP
>===== SHADER_END ===============================================================
>
>--------------------------------------------------------------
>FRAG
>DCL IN[0], GENERIC[9], PERSPECTIVE
>DCL IN[1], GENERIC[10], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SVIEW[0], 2D, FLOAT
>DCL TEMP[0], LOCAL
>  0: MOV TEMP[0].xy, IN[1].xyyy
>  1: TEX TEMP[0], TEMP[0], SAMP[0], 2D
>  2: MUL TEMP[0], IN[0], TEMP[0]
>  3: MOV OUT[0], TEMP[0]
>  4: END
>; ModuleID = 'tgsi'
>
>define void @main(<4 x float> inreg, <4 x float> inreg, <4 x float> inreg) #0 {
>main_body:
>  %3 = extractelement <4 x float> %0, i32 0
>  %4 = extractelement <4 x float> %0, i32 1
>  %5 = call <2 x float> @llvm.R600.interp.xy(i32 0, float %3, float %4)
>  %6 = call <2 x float> @llvm.R600.interp.zw(i32 0, float %3, float %4)
>  %7 = extractelement <2 x float> %5, i32 0
>  %8 = extractelement <2 x float> %5, i32 1
>  %9 = extractelement <2 x float> %6, i32 0
>  %10 = extractelement <2 x float> %6, i32 1
>  %11 = extractelement <4 x float> %0, i32 0
>  %12 = extractelement <4 x float> %0, i32 1
>  %13 = call <2 x float> @llvm.R600.interp.xy(i32 1, float %11, float %12)
>  %14 = call <2 x float> @llvm.R600.interp.zw(i32 1, float %11, float %12)
>  %15 = shufflevector <2 x float> %13, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
>  %16 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %15, i32 16, i32 0, i32 2)
>  %17 = extractelement <4 x float> %16, i32 0
>  %18 = extractelement <4 x float> %16, i32 1
>  %19 = extractelement <4 x float> %16, i32 2
>  %20 = extractelement <4 x float> %16, i32 3
>  %21 = fmul float %7, %17
>  %22 = fmul float %8, %18
>  %23 = fmul float %9, %19
>  %24 = fmul float %10, %20
>  %25 = insertelement <4 x float> undef, float %21, i32 0
>  %26 = insertelement <4 x float> %25, float %22, i32 1
>  %27 = insertelement <4 x float> %26, float %23, i32 2
>  %28 = insertelement <4 x float> %27, float %24, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %28, i32 0, i32 0)
>  ret void
>}
>
>; Function Attrs: readnone
>declare <2 x float> @llvm.R600.interp.xy(i32, float, float) #1
>
>; Function Attrs: readnone
>declare <2 x float> @llvm.R600.interp.zw(i32, float, float) #1
>
>; Function Attrs: readnone
>declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32, i32) #1
>
>declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { readnone }
>
>===== SHADER #14 ==================================== PS/REDWOOD/EVERGREEN =====
>===== 48 dw ===== 3 gprs ===== 0 stack =========================================
>0000  00000008 a02c0000 ALU 12 @16
> 0016  00380400 00346b10     1      x: INTERP_XY          R1.x,  R0.y, Param0.x         VEC_210
> 0018  00380000 20346b10            y: INTERP_XY          R1.y,  R0.x, Param0.x         VEC_210
> 0020  00380400 40146b00            z: INTERP_XY          __.z,  R0.y, Param0.x         VEC_210
> 0022  80380000 60146b00            w: INTERP_XY          __.w,  R0.x, Param0.x         VEC_210
> 0024  00380400 00146b80     2      x: INTERP_ZW          __.x,  R0.y, Param0.x         VEC_210
> 0026  00380000 20146b80            y: INTERP_ZW          __.y,  R0.x, Param0.x         VEC_210
> 0028  00380400 40346b90            z: INTERP_ZW          R1.z,  R0.y, Param0.x         VEC_210
> 0030  80380000 60346b90            w: INTERP_ZW          R1.w,  R0.x, Param0.x         VEC_210
> 0032  00382400 00146b10     3      x: INTERP_XY          R0.x,  R0.y, Param1.x         VEC_210
> 0034  00382000 20146b10            y: INTERP_XY          R0.y,  R0.x, Param1.x         VEC_210
> 0036  00382400 40146b00            z: INTERP_XY          __.z,  R0.y, Param1.x         VEC_210
> 0038  80382000 60146b00            w: INTERP_XY          __.w,  R0.x, Param1.x         VEC_210
>0002  00000006 80400000 TEX 1 @12
> 0012  00001010 f00d1000 fc800000 SAMPLE              R0.xyzw, R0.xy__,   RID:16, SID:0 CT:NNNN
>0004  00000014 a00c0000 ALU 4 @40
> 0040  00000001 00400110     4      x: MUL_IEEE           R2.x,  R1.x, R0.x
> 0042  00800401 20400110            y: MUL_IEEE           R2.y,  R1.y, R0.y
> 0044  01000801 40400110            z: MUL_IEEE           R2.z,  R1.z, R0.z
> 0046  81800c01 60400110            w: MUL_IEEE           R2.w,  R1.w, R0.w
>0006  c0010000 95200688 EXPORT_DONE        PIXEL 0     R2.xyzw  EOP
>===== SHADER_END ===============================================================
>
>
>===== SHADER #14 OPT ================================ PS/REDWOOD/EVERGREEN =====
>===== 44 dw ===== 2 gprs ===== 0 stack =========================================
>0000  00000004 a00c0000 ALU 4 @8
> 0008  00382400 00346b10     1      x: INTERP_XY          R1.x,  R0.y, Param1.x         VEC_210
> 0010  00b82000 20346b10            y: INTERP_XY          R1.y,  R0.x, Param1.y         VEC_210
> 0012  01382400 40146b00            z: INTERP_XY          __.z,  R0.y, Param1.z         VEC_210
> 0014  81b82000 60146b00            w: INTERP_XY          __.w,  R0.x, Param1.w         VEC_210
>0002  00000008 80400000 TEX 1 @16
> 0016  00011010 f00d1001 fc800000 SAMPLE              R1.xyzw, R1.xy__,   RID:16, SID:0 CT:NNNN
>0004  0000000a a02c0000 ALU 12 @20
> 0020  00380400 00146b80     2      x: INTERP_ZW          __.x,  R0.y, Param0.x         VEC_210
> 0022  00b80000 20146b80            y: INTERP_ZW          __.y,  R0.x, Param0.y         VEC_210
> 0024  01380400 4f946b90            z: INTERP_ZW          T0.z,  R0.y, Param0.z         VEC_210
> 0026  81b80000 6f946b90            w: INTERP_ZW          T0.w,  R0.x, Param0.w         VEC_210
> 0028  00380400 0f946b10     3      x: INTERP_XY          T0.x,  R0.y, Param0.x         VEC_210
> 0030  00b80000 2f946b10            y: INTERP_XY          T0.y,  R0.x, Param0.y         VEC_210
> 0032  01380400 40146b00            z: INTERP_XY          __.z,  R0.y, Param0.z         VEC_210
> 0034  81b80000 60146b00            w: INTERP_XY          __.w,  R0.x, Param0.w         VEC_210
> 0036  0000207c 00000110     4      x: MUL_IEEE           R0.x,  T0.x, R1.x
> 0038  0080247c 20000110            y: MUL_IEEE           R0.y,  T0.y, R1.y
> 0040  0100287c 40000110            z: MUL_IEEE           R0.z,  T0.z, R1.z
> 0042  81802c7c 60000110            w: MUL_IEEE           R0.w,  T0.w, R1.w
>0006  c0000000 95200688 EXPORT_DONE        PIXEL 0     R0.xyzw  EOP
>===== SHADER_END ===============================================================
>
>--------------------------------------------------------------
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[9]
>DCL OUT[2], GENERIC[10]
>DCL CONST[0..3]
>DCL TEMP[0..1], LOCAL
>  0: MUL TEMP[0], CONST[0], IN[0].xxxx
>  1: MAD TEMP[0], CONST[1], IN[0].yyyy, TEMP[0]
>  2: MAD TEMP[0], CONST[2], IN[0].zzzz, TEMP[0]
>  3: MAD TEMP[0], CONST[3], IN[0].wwww, TEMP[0]
>  4: MOV TEMP[1].xy, IN[2].xyxx
>  5: MOV OUT[2], TEMP[1]
>  6: MOV OUT[1], IN[1]
>  7: MOV OUT[0], TEMP[0]
>  8: END
>; ModuleID = 'tgsi'
>
>define void @main(<4 x float> inreg, <4 x float> inreg, <4 x float> inreg, <4 x float> inreg) #0 {
>main_body:
>  %4 = extractelement <4 x float> %1, i32 0
>  %5 = extractelement <4 x float> %1, i32 1
>  %6 = extractelement <4 x float> %1, i32 2
>  %7 = extractelement <4 x float> %1, i32 3
>  %8 = extractelement <4 x float> %3, i32 0
>  %9 = extractelement <4 x float> %3, i32 1
>  %10 = load <4 x float> addrspace(8)* null
>  %11 = extractelement <4 x float> %10, i32 0
>  %12 = fmul float %11, %4
>  %13 = extractelement <4 x float> %10, i32 1
>  %14 = fmul float %13, %4
>  %15 = extractelement <4 x float> %10, i32 2
>  %16 = fmul float %15, %4
>  %17 = load <4 x float> addrspace(8)* null
>  %18 = extractelement <4 x float> %17, i32 3
>  %19 = fmul float %18, %4
>  %20 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
>  %21 = extractelement <4 x float> %20, i32 0
>  %22 = fmul float %21, %5
>  %23 = fadd float %22, %12
>  %24 = extractelement <4 x float> %20, i32 1
>  %25 = fmul float %24, %5
>  %26 = fadd float %25, %14
>  %27 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
>  %28 = extractelement <4 x float> %27, i32 2
>  %29 = fmul float %28, %5
>  %30 = fadd float %29, %16
>  %31 = extractelement <4 x float> %27, i32 3
>  %32 = fmul float %31, %5
>  %33 = fadd float %32, %19
>  %34 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
>  %35 = extractelement <4 x float> %34, i32 0
>  %36 = fmul float %35, %6
>  %37 = fadd float %36, %23
>  %38 = extractelement <4 x float> %34, i32 1
>  %39 = fmul float %38, %6
>  %40 = fadd float %39, %26
>  %41 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
>  %42 = extractelement <4 x float> %41, i32 2
>  %43 = fmul float %42, %6
>  %44 = fadd float %43, %30
>  %45 = extractelement <4 x float> %41, i32 3
>  %46 = fmul float %45, %6
>  %47 = fadd float %46, %33
>  %48 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
>  %49 = extractelement <4 x float> %48, i32 0
>  %50 = fmul float %49, %7
>  %51 = fadd float %50, %37
>  %52 = extractelement <4 x float> %48, i32 1
>  %53 = fmul float %52, %7
>  %54 = fadd float %53, %40
>  %55 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
>  %56 = extractelement <4 x float> %55, i32 2
>  %57 = fmul float %56, %7
>  %58 = fadd float %57, %44
>  %59 = extractelement <4 x float> %55, i32 3
>  %60 = fmul float %59, %7
>  %61 = fadd float %60, %47
>  %62 = insertelement <4 x float> undef, float %51, i32 0
>  %63 = insertelement <4 x float> %62, float %54, i32 1
>  %64 = insertelement <4 x float> %63, float %58, i32 2
>  %65 = insertelement <4 x float> %64, float %61, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %65, i32 60, i32 1)
>  call void @llvm.R600.store.swizzle(<4 x float> %2, i32 0, i32 2)
>  %66 = insertelement <4 x float> undef, float %8, i32 0
>  %67 = insertelement <4 x float> %66, float %9, i32 1
>  %68 = insertelement <4 x float> %67, float 0.000000e+00, i32 2
>  %69 = insertelement <4 x float> %68, float 0.000000e+00, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %69, i32 1, i32 2)
>  ret void
>}
>
>declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
>
>attributes #0 = { "ShaderType"="1" }
>
>===== SHADER #15 ==================================== VS/REDWOOD/EVERGREEN =====
>===== 44 dw ===== 6 gprs ===== 1 stack =========================================
>0000  00000000 84c00000 CALL_FS @0
>0002  80000006 a03c0000 ALU 16 @12 KC0[CB0:0-31]
> 0012  80002080 60000110     1      w: MUL_IEEE           R0.w,  KC0[0].x, R1.x
> 0014  00802081 60030cfe     2      w: MULADD_IEEE        R0.w,  KC0[1].x, R1.y, PV.w
> 0016  80002480 60800110            t: MUL_IEEE           R4.w,  KC0[0].y, R1.x
> 0018  81002082 60030cfe     3      w: MULADD_IEEE        R0.w,  KC0[2].x, R1.z, PV.w
> 0020  01802083 00030cfe     4      x: MULADD_IEEE        R0.x,  KC0[3].x, R1.w, PV.w
> 0022  80802481 60830c04            w: MULADD_IEEE        R4.w,  KC0[1].y, R1.y, R4.w
> 0024  80002880 60a00110     5      w: MUL_IEEE           R5.w,  KC0[0].z, R1.x
> 0026  00802881 40830cfe     6      z: MULADD_IEEE        R4.z,  KC0[1].z, R1.y, PV.w
> 0028  80002c80 60a00110            w: MUL_IEEE           R5.w,  KC0[0].w, R1.x
> 0030  81002482 60830c04     7      w: MULADD_IEEE        R4.w,  KC0[2].y, R1.z, R4.w
> 0032  01802483 20030cfe     8      y: MULADD_IEEE        R0.y,  KC0[3].y, R1.w, PV.w
> 0034  80802c81 60830c05            w: MULADD_IEEE        R4.w,  KC0[1].w, R1.y, R5.w
> 0036  81002882 60a30804     9      w: MULADD_IEEE        R5.w,  KC0[2].z, R1.z, R4.z
> 0038  01802883 40030cfe    10      z: MULADD_IEEE        R0.z,  KC0[3].z, R1.w, PV.w
> 0040  81002c82 60830c04            w: MULADD_IEEE        R4.w,  KC0[2].w, R1.z, R4.w
> 0042  81802c83 60030cfe    11      w: MULADD_IEEE        R0.w,  KC0[3].w, R1.w, PV.w
>0004  c000203c 95000688 EXPORT_DONE        POS   60    R0.xyzw
>0006  c0014000 94c00688 EXPORT             PARAM 0     R2.xyzw
>0008  c001c001 95200908 EXPORT_DONE        PARAM 1     R3.xy00  EOP
>===== SHADER_END ===============================================================
>
>
>===== SHADER #15 OPT ================================ VS/REDWOOD/EVERGREEN =====
>===== 42 dw ===== 4 gprs ===== 1 stack =========================================
>0000  00000000 84c00000 CALL_FS @0
>0002  40000005 a03c0000 ALU 16 @10 KC0[CB0:0-15]
> 0010  00002c80 0f800110     1      x: MUL_IEEE           T0.x,  KC0[0].w, R1.x
> 0012  80002880 2f800110            y: MUL_IEEE           T0.y,  KC0[0].z, R1.x
> 0014  00802c81 0f83007c     2      x: MULADD_IEEE        T0.x,  KC0[1].w, R1.y, T0.x
> 0016  00802881 2f83047c            y: MULADD_IEEE        T0.y,  KC0[1].z, R1.y, T0.y
> 0018  00002480 4f800110            z: MUL_IEEE           T0.z,  KC0[0].y, R1.x
> 0020  80002080 6f800110            w: MUL_IEEE           T0.w,  KC0[0].x, R1.x
> 0022  01002c82 0fa3007c     3      x: MULADD_IEEE        T1.x,  KC0[2].w, R1.z, T0.x
> 0024  00802481 4f83087c            z: MULADD_IEEE        T0.z,  KC0[1].y, R1.y, T0.z
> 0026  80802081 6f830c7c            w: MULADD_IEEE        T0.w,  KC0[1].x, R1.y, T0.w
> 0028  01002482 0f83087c     4      x: MULADD_IEEE        T0.x,  KC0[2].y, R1.z, T0.z
> 0030  01002082 2f830c7c            y: MULADD_IEEE        T0.y,  KC0[2].x, R1.z, T0.w
> 0032  81002882 2fab047c            t: MULADD_IEEE        T1.y,  KC0[2].z, R1.z, T0.y   SCL_212
> 0034  01802083 0003047c     5      x: MULADD_IEEE        R0.x,  KC0[3].x, R1.w, T0.y
> 0036  01802483 2003007c            y: MULADD_IEEE        R0.y,  KC0[3].y, R1.w, T0.x
> 0038  01802883 4007047d            z: MULADD_IEEE        R0.z,  KC0[3].z, R1.w, T1.y   VEC_021
> 0040  81802c83 6007007d            w: MULADD_IEEE        R0.w,  KC0[3].w, R1.w, T1.x   VEC_021
>0004  c000203c 95000688 EXPORT_DONE        POS   60    R0.xyzw
>0006  c001c001 94c00908 EXPORT             PARAM 1     R3.xy00
>0008  c0014000 95200688 EXPORT_DONE        PARAM 0     R2.xyzw  EOP
>===== SHADER_END ===============================================================
>
>--------------------------------------------------------------
>FRAG
>DCL IN[0], GENERIC[0], CONSTANT
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main(<4 x float> inreg, <4 x float> inreg) #0 {
>main_body:
>  %2 = call <4 x float> @llvm.R600.interp.const(i32 0)
>  call void @llvm.R600.store.swizzle(<4 x float> %2, i32 0, i32 0)
>  ret void
>}
>
>; Function Attrs: readnone
>declare <4 x float> @llvm.R600.interp.const(i32) #1
>
>declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { readnone }
>
>===== SHADER #16 ==================================== PS/REDWOOD/EVERGREEN =====
>===== 16 dw ===== 1 gprs ===== 0 stack =========================================
>0000  00000004 a00c0000 ALU 4 @8
> 0008  000001c0 00007010     1      x: INTERP_LOAD_P0     R0.x,  Param0.x
> 0010  000001c0 20007010            y: INTERP_LOAD_P0     R0.y,  Param0.x
> 0012  000001c0 40007010            z: INTERP_LOAD_P0     R0.z,  Param0.x
> 0014  800001c0 60007010            w: INTERP_LOAD_P0     R0.w,  Param0.x
>0002  c0000000 95200688 EXPORT_DONE        PIXEL 0     R0.xyzw  EOP
>===== SHADER_END ===============================================================
>
>
>===== SHADER #16 OPT ================================ PS/REDWOOD/EVERGREEN =====
>===== 12 dw ===== 1 gprs ===== 0 stack =========================================
>0000  00000002 a00c0000 ALU 4 @4
> 0004  000001c0 00007010     1      x: INTERP_LOAD_P0     R0.x,  Param0.x
> 0006  000005c0 20007010            y: INTERP_LOAD_P0     R0.y,  Param0.y
> 0008  000009c0 40007010            z: INTERP_LOAD_P0     R0.z,  Param0.z
> 0010  80000dc0 60007010            w: INTERP_LOAD_P0     R0.w,  Param0.w
>0002  c0000000 95200688 EXPORT_DONE        PIXEL 0     R0.xyzw  EOP
>===== SHADER_END ===============================================================
>
>S_Startup: initializing sound output format: 48000Hz, 16 bit, 2 channels...
>SndSys_Init: using the ALSA module
>SndSys_Init: PCM device is "default"
>Sound format: 48000Hz, 2 channels, 16 bits per sample
>CDAudio_SysStartup: open of "/dev/cdrom" failed (2)
>CDAudio_Init: No CD in player.
>Can't get initial CD volume
>CD Audio Initialized
>--------------------------------------------------------------
>FRAG
>DCL IN[0], GENERIC[9], PERSPECTIVE
>DCL IN[1], GENERIC[10], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SVIEW[0], 2D, FLOAT
>DCL TEMP[0], LOCAL
>  0: MOV TEMP[0].xy, IN[1].xyyy
>  1: TEX TEMP[0], TEMP[0], SAMP[0], 2D
>  2: MUL TEMP[0], IN[0], TEMP[0]
>  3: MOV OUT[0], TEMP[0]
>  4: END
>; ModuleID = 'tgsi'
>
>define void @main(<4 x float> inreg, <4 x float> inreg, <4 x float> inreg) #0 {
>main_body:
>  %3 = extractelement <4 x float> %0, i32 0
>  %4 = extractelement <4 x float> %0, i32 1
>  %5 = call <2 x float> @llvm.R600.interp.xy(i32 0, float %3, float %4)
>  %6 = call <2 x float> @llvm.R600.interp.zw(i32 0, float %3, float %4)
>  %7 = extractelement <2 x float> %5, i32 0
>  %8 = extractelement <2 x float> %5, i32 1
>  %9 = extractelement <2 x float> %6, i32 0
>  %10 = extractelement <2 x float> %6, i32 1
>  %11 = extractelement <4 x float> %0, i32 0
>  %12 = extractelement <4 x float> %0, i32 1
>  %13 = call <2 x float> @llvm.R600.interp.xy(i32 1, float %11, float %12)
>  %14 = call <2 x float> @llvm.R600.interp.zw(i32 1, float %11, float %12)
>  %15 = shufflevector <2 x float> %13, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
>  %16 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %15, i32 16, i32 0, i32 2)
>  %17 = extractelement <4 x float> %16, i32 0
>  %18 = extractelement <4 x float> %16, i32 1
>  %19 = extractelement <4 x float> %16, i32 2
>  %20 = extractelement <4 x float> %16, i32 3
>  %21 = fmul float %7, %17
>  %22 = fmul float %8, %18
>  %23 = fmul float %9, %19
>  %24 = fmul float %10, %20
>  %25 = insertelement <4 x float> undef, float %21, i32 0
>  %26 = insertelement <4 x float> %25, float %22, i32 1
>  %27 = insertelement <4 x float> %26, float %23, i32 2
>  %28 = insertelement <4 x float> %27, float %24, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %28, i32 0, i32 0)
>  ret void
>}
>
>; Function Attrs: readnone
>declare <2 x float> @llvm.R600.interp.xy(i32, float, float) #1
>
>; Function Attrs: readnone
>declare <2 x float> @llvm.R600.interp.zw(i32, float, float) #1
>
>; Function Attrs: readnone
>declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32, i32) #1
>
>declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { readnone }
>
>===== SHADER #17 ==================================== PS/REDWOOD/EVERGREEN =====
>===== 48 dw ===== 3 gprs ===== 0 stack =========================================
>0000  00000008 a02c0000 ALU 12 @16
> 0016  00380400 00346b10     1      x: INTERP_XY          R1.x,  R0.y, Param0.x         VEC_210
> 0018  00380000 20346b10            y: INTERP_XY          R1.y,  R0.x, Param0.x         VEC_210
> 0020  00380400 40146b00            z: INTERP_XY          __.z,  R0.y, Param0.x         VEC_210
> 0022  80380000 60146b00            w: INTERP_XY          __.w,  R0.x, Param0.x         VEC_210
> 0024  00380400 00146b80     2      x: INTERP_ZW          __.x,  R0.y, Param0.x         VEC_210
> 0026  00380000 20146b80            y: INTERP_ZW          __.y,  R0.x, Param0.x         VEC_210
> 0028  00380400 40346b90            z: INTERP_ZW          R1.z,  R0.y, Param0.x         VEC_210
> 0030  80380000 60346b90            w: INTERP_ZW          R1.w,  R0.x, Param0.x         VEC_210
> 0032  00382400 00146b10     3      x: INTERP_XY          R0.x,  R0.y, Param1.x         VEC_210
> 0034  00382000 20146b10            y: INTERP_XY          R0.y,  R0.x, Param1.x         VEC_210
> 0036  00382400 40146b00            z: INTERP_XY          __.z,  R0.y, Param1.x         VEC_210
> 0038  80382000 60146b00            w: INTERP_XY          __.w,  R0.x, Param1.x         VEC_210
>0002  00000006 80400000 TEX 1 @12
> 0012  00001010 f00d1000 fc800000 SAMPLE              R0.xyzw, R0.xy__,   RID:16, SID:0 CT:NNNN
>0004  00000014 a00c0000 ALU 4 @40
> 0040  00000001 00400110     4      x: MUL_IEEE           R2.x,  R1.x, R0.x
> 0042  00800401 20400110            y: MUL_IEEE           R2.y,  R1.y, R0.y
> 0044  01000801 40400110            z: MUL_IEEE           R2.z,  R1.z, R0.z
> 0046  81800c01 60400110            w: MUL_IEEE           R2.w,  R1.w, R0.w
>0006  c0010000 95200688 EXPORT_DONE        PIXEL 0     R2.xyzw  EOP
>===== SHADER_END ===============================================================
>
>
>===== SHADER #17 OPT ================================ PS/REDWOOD/EVERGREEN =====
>===== 44 dw ===== 2 gprs ===== 0 stack =========================================
>0000  00000004 a00c0000 ALU 4 @8
> 0008  00382400 00346b10     1      x: INTERP_XY          R1.x,  R0.y, Param1.x         VEC_210
> 0010  00b82000 20346b10            y: INTERP_XY          R1.y,  R0.x, Param1.y         VEC_210
> 0012  01382400 40146b00            z: INTERP_XY          __.z,  R0.y, Param1.z         VEC_210
> 0014  81b82000 60146b00            w: INTERP_XY          __.w,  R0.x, Param1.w         VEC_210
>0002  00000008 80400000 TEX 1 @16
> 0016  00011010 f00d1001 fc800000 SAMPLE              R1.xyzw, R1.xy__,   RID:16, SID:0 CT:NNNN
>0004  0000000a a02c0000 ALU 12 @20
> 0020  00380400 00146b80     2      x: INTERP_ZW          __.x,  R0.y, Param0.x         VEC_210
> 0022  00b80000 20146b80            y: INTERP_ZW          __.y,  R0.x, Param0.y         VEC_210
> 0024  01380400 4f946b90            z: INTERP_ZW          T0.z,  R0.y, Param0.z         VEC_210
> 0026  81b80000 6f946b90            w: INTERP_ZW          T0.w,  R0.x, Param0.w         VEC_210
> 0028  00380400 0f946b10     3      x: INTERP_XY          T0.x,  R0.y, Param0.x         VEC_210
> 0030  00b80000 2f946b10            y: INTERP_XY          T0.y,  R0.x, Param0.y         VEC_210
> 0032  01380400 40146b00            z: INTERP_XY          __.z,  R0.y, Param0.z         VEC_210
> 0034  81b80000 60146b00            w: INTERP_XY          __.w,  R0.x, Param0.w         VEC_210
> 0036  0000207c 00000110     4      x: MUL_IEEE           R0.x,  T0.x, R1.x
> 0038  0080247c 20000110            y: MUL_IEEE           R0.y,  T0.y, R1.y
> 0040  0100287c 40000110            z: MUL_IEEE           R0.z,  T0.z, R1.z
> 0042  81802c7c 60000110            w: MUL_IEEE           R0.w,  T0.w, R1.w
>0006  c0000000 95200688 EXPORT_DONE        PIXEL 0     R0.xyzw  EOP
>===== SHADER_END ===============================================================
>
>--------------------------------------------------------------
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[9]
>DCL OUT[2], GENERIC[10]
>DCL CONST[0..3]
>DCL TEMP[0..1], LOCAL
>  0: MUL TEMP[0], CONST[0], IN[0].xxxx
>  1: MAD TEMP[0], CONST[1], IN[0].yyyy, TEMP[0]
>  2: MAD TEMP[0], CONST[2], IN[0].zzzz, TEMP[0]
>  3: MAD TEMP[0], CONST[3], IN[0].wwww, TEMP[0]
>  4: MOV TEMP[1].xy, IN[2].xyxx
>  5: MOV OUT[2], TEMP[1]
>  6: MOV OUT[1], IN[1]
>  7: MOV OUT[0], TEMP[0]
>  8: END
>; ModuleID = 'tgsi'
>
>define void @main(<4 x float> inreg, <4 x float> inreg, <4 x float> inreg, <4 x float> inreg) #0 {
>main_body:
>  %4 = extractelement <4 x float> %1, i32 0
>  %5 = extractelement <4 x float> %1, i32 1
>  %6 = extractelement <4 x float> %1, i32 2
>  %7 = extractelement <4 x float> %1, i32 3
>  %8 = extractelement <4 x float> %3, i32 0
>  %9 = extractelement <4 x float> %3, i32 1
>  %10 = load <4 x float> addrspace(8)* null
>  %11 = extractelement <4 x float> %10, i32 0
>  %12 = fmul float %11, %4
>  %13 = extractelement <4 x float> %10, i32 1
>  %14 = fmul float %13, %4
>  %15 = extractelement <4 x float> %10, i32 2
>  %16 = fmul float %15, %4
>  %17 = load <4 x float> addrspace(8)* null
>  %18 = extractelement <4 x float> %17, i32 3
>  %19 = fmul float %18, %4
>  %20 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
>  %21 = extractelement <4 x float> %20, i32 0
>  %22 = fmul float %21, %5
>  %23 = fadd float %22, %12
>  %24 = extractelement <4 x float> %20, i32 1
>  %25 = fmul float %24, %5
>  %26 = fadd float %25, %14
>  %27 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
>  %28 = extractelement <4 x float> %27, i32 2
>  %29 = fmul float %28, %5
>  %30 = fadd float %29, %16
>  %31 = extractelement <4 x float> %27, i32 3
>  %32 = fmul float %31, %5
>  %33 = fadd float %32, %19
>  %34 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
>  %35 = extractelement <4 x float> %34, i32 0
>  %36 = fmul float %35, %6
>  %37 = fadd float %36, %23
>  %38 = extractelement <4 x float> %34, i32 1
>  %39 = fmul float %38, %6
>  %40 = fadd float %39, %26
>  %41 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
>  %42 = extractelement <4 x float> %41, i32 2
>  %43 = fmul float %42, %6
>  %44 = fadd float %43, %30
>  %45 = extractelement <4 x float> %41, i32 3
>  %46 = fmul float %45, %6
>  %47 = fadd float %46, %33
>  %48 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
>  %49 = extractelement <4 x float> %48, i32 0
>  %50 = fmul float %49, %7
>  %51 = fadd float %50, %37
>  %52 = extractelement <4 x float> %48, i32 1
>  %53 = fmul float %52, %7
>  %54 = fadd float %53, %40
>  %55 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
>  %56 = extractelement <4 x float> %55, i32 2
>  %57 = fmul float %56, %7
>  %58 = fadd float %57, %44
>  %59 = extractelement <4 x float> %55, i32 3
>  %60 = fmul float %59, %7
>  %61 = fadd float %60, %47
>  %62 = insertelement <4 x float> undef, float %51, i32 0
>  %63 = insertelement <4 x float> %62, float %54, i32 1
>  %64 = insertelement <4 x float> %63, float %58, i32 2
>  %65 = insertelement <4 x float> %64, float %61, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %65, i32 60, i32 1)
>  call void @llvm.R600.store.swizzle(<4 x float> %2, i32 0, i32 2)
>  %66 = insertelement <4 x float> undef, float %8, i32 0
>  %67 = insertelement <4 x float> %66, float %9, i32 1
>  %68 = insertelement <4 x float> %67, float 0.000000e+00, i32 2
>  %69 = insertelement <4 x float> %68, float 0.000000e+00, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %69, i32 1, i32 2)
>  ret void
>}
>
>declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
>
>attributes #0 = { "ShaderType"="1" }
>
>===== SHADER #18 ==================================== VS/REDWOOD/EVERGREEN =====
>===== 44 dw ===== 6 gprs ===== 1 stack =========================================
>0000  00000000 84c00000 CALL_FS @0
>0002  80000006 a03c0000 ALU 16 @12 KC0[CB0:0-31]
> 0012  80002080 60000110     1      w: MUL_IEEE           R0.w,  KC0[0].x, R1.x
> 0014  00802081 60030cfe     2      w: MULADD_IEEE        R0.w,  KC0[1].x, R1.y, PV.w
> 0016  80002480 60800110            t: MUL_IEEE           R4.w,  KC0[0].y, R1.x
> 0018  81002082 60030cfe     3      w: MULADD_IEEE        R0.w,  KC0[2].x, R1.z, PV.w
> 0020  01802083 00030cfe     4      x: MULADD_IEEE        R0.x,  KC0[3].x, R1.w, PV.w
> 0022  80802481 60830c04            w: MULADD_IEEE        R4.w,  KC0[1].y, R1.y, R4.w
> 0024  80002880 60a00110     5      w: MUL_IEEE           R5.w,  KC0[0].z, R1.x
> 0026  00802881 40830cfe     6      z: MULADD_IEEE        R4.z,  KC0[1].z, R1.y, PV.w
> 0028  80002c80 60a00110            w: MUL_IEEE           R5.w,  KC0[0].w, R1.x
> 0030  81002482 60830c04     7      w: MULADD_IEEE        R4.w,  KC0[2].y, R1.z, R4.w
> 0032  01802483 20030cfe     8      y: MULADD_IEEE        R0.y,  KC0[3].y, R1.w, PV.w
> 0034  80802c81 60830c05            w: MULADD_IEEE        R4.w,  KC0[1].w, R1.y, R5.w
> 0036  81002882 60a30804     9      w: MULADD_IEEE        R5.w,  KC0[2].z, R1.z, R4.z
> 0038  01802883 40030cfe    10      z: MULADD_IEEE        R0.z,  KC0[3].z, R1.w, PV.w
> 0040  81002c82 60830c04            w: MULADD_IEEE        R4.w,  KC0[2].w, R1.z, R4.w
> 0042  81802c83 60030cfe    11      w: MULADD_IEEE        R0.w,  KC0[3].w, R1.w, PV.w
>0004  c000203c 95000688 EXPORT_DONE        POS   60    R0.xyzw
>0006  c0014000 94c00688 EXPORT             PARAM 0     R2.xyzw
>0008  c001c001 95200908 EXPORT_DONE        PARAM 1     R3.xy00  EOP
>===== SHADER_END ===============================================================
>
>
>===== SHADER #18 OPT ================================ VS/REDWOOD/EVERGREEN =====
>===== 42 dw ===== 4 gprs ===== 1 stack =========================================
>0000  00000000 84c00000 CALL_FS @0
>0002  40000005 a03c0000 ALU 16 @10 KC0[CB0:0-15]
> 0010  00002c80 0f800110     1      x: MUL_IEEE           T0.x,  KC0[0].w, R1.x
> 0012  80002880 2f800110            y: MUL_IEEE           T0.y,  KC0[0].z, R1.x
> 0014  00802c81 0f83007c     2      x: MULADD_IEEE        T0.x,  KC0[1].w, R1.y, T0.x
> 0016  00802881 2f83047c            y: MULADD_IEEE        T0.y,  KC0[1].z, R1.y, T0.y
> 0018  00002480 4f800110            z: MUL_IEEE           T0.z,  KC0[0].y, R1.x
> 0020  80002080 6f800110            w: MUL_IEEE           T0.w,  KC0[0].x, R1.x
> 0022  01002c82 0fa3007c     3      x: MULADD_IEEE        T1.x,  KC0[2].w, R1.z, T0.x
> 0024  00802481 4f83087c            z: MULADD_IEEE        T0.z,  KC0[1].y, R1.y, T0.z
> 0026  80802081 6f830c7c            w: MULADD_IEEE        T0.w,  KC0[1].x, R1.y, T0.w
> 0028  01002482 0f83087c     4      x: MULADD_IEEE        T0.x,  KC0[2].y, R1.z, T0.z
> 0030  01002082 2f830c7c            y: MULADD_IEEE        T0.y,  KC0[2].x, R1.z, T0.w
> 0032  81002882 2fab047c            t: MULADD_IEEE        T1.y,  KC0[2].z, R1.z, T0.y   SCL_212
> 0034  01802083 0003047c     5      x: MULADD_IEEE        R0.x,  KC0[3].x, R1.w, T0.y
> 0036  01802483 2003007c            y: MULADD_IEEE        R0.y,  KC0[3].y, R1.w, T0.x
> 0038  01802883 4007047d            z: MULADD_IEEE        R0.z,  KC0[3].z, R1.w, T1.y   VEC_021
> 0040  81802c83 6007007d            w: MULADD_IEEE        R0.w,  KC0[3].w, R1.w, T1.x   VEC_021
>0004  c000203c 95000688 EXPORT_DONE        POS   60    R0.xyzw
>0006  c001c001 94c00908 EXPORT             PARAM 1     R3.xy00
>0008  c0014000 95200688 EXPORT_DONE        PARAM 0     R2.xyzw  EOP
>===== SHADER_END ===============================================================
>
>NetWM fullscreen: actually using resolution 1920x1080
>--------------------------------------------------------------
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[0], CONSTANT
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main(<4 x float> inreg, <4 x float> inreg) #0 {
>main_body:
>  %2 = call <4 x float> @llvm.R600.interp.const(i32 0)
>  call void @llvm.R600.store.swizzle(<4 x float> %2, i32 0, i32 0)
>  ret void
>}
>
>; Function Attrs: readnone
>declare <4 x float> @llvm.R600.interp.const(i32) #1
>
>declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { readnone }
>
>===== SHADER #19 ==================================== PS/REDWOOD/EVERGREEN =====
>===== 16 dw ===== 1 gprs ===== 0 stack =========================================
>0000  00000004 a00c0000 ALU 4 @8
> 0008  000001c0 00007010     1      x: INTERP_LOAD_P0     R0.x,  Param0.x
> 0010  000001c0 20007010            y: INTERP_LOAD_P0     R0.y,  Param0.x
> 0012  000001c0 40007010            z: INTERP_LOAD_P0     R0.z,  Param0.x
> 0014  800001c0 60007010            w: INTERP_LOAD_P0     R0.w,  Param0.x
>0002  c0000000 95200688 EXPORT_DONE        PIXEL 0     R0.xyzw  EOP
>===== SHADER_END ===============================================================
>
>
>===== SHADER #19 OPT ================================ PS/REDWOOD/EVERGREEN =====
>===== 12 dw ===== 1 gprs ===== 0 stack =========================================
>0000  00000002 a00c0000 ALU 4 @4
> 0004  000001c0 00007010     1      x: INTERP_LOAD_P0     R0.x,  Param0.x
> 0006  000005c0 20007010            y: INTERP_LOAD_P0     R0.y,  Param0.y
> 0008  000009c0 40007010            z: INTERP_LOAD_P0     R0.z,  Param0.z
> 0010  80000dc0 60007010            w: INTERP_LOAD_P0     R0.w,  Param0.w
>0002  c0000000 95200688 EXPORT_DONE        PIXEL 0     R0.xyzw  EOP
>===== SHADER_END ===============================================================
>
>PlayerStats_PlayerDetail_Handler(): Receiving player stats failed: -404
>--------------------------------------------------------------
>FRAG
>DCL IN[0], GENERIC[9], PERSPECTIVE
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main(<4 x float> inreg, <4 x float> inreg) #0 {
>main_body:
>  %2 = extractelement <4 x float> %0, i32 0
>  %3 = extractelement <4 x float> %0, i32 1
>  %4 = call <2 x float> @llvm.R600.interp.xy(i32 0, float %2, float %3)
>  %5 = call <2 x float> @llvm.R600.interp.zw(i32 0, float %2, float %3)
>  %6 = shufflevector <2 x float> %4, <2 x float> %5, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
>  call void @llvm.R600.store.swizzle(<4 x float> %6, i32 0, i32 0)
>  ret void
>}
>
>; Function Attrs: readnone
>declare <2 x float> @llvm.R600.interp.xy(i32, float, float) #1
>
>; Function Attrs: readnone
>declare <2 x float> @llvm.R600.interp.zw(i32, float, float) #1
>
>declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { readnone }
>
>===== SHADER #21 ==================================== PS/REDWOOD/EVERGREEN =====
>===== 24 dw ===== 2 gprs ===== 0 stack =========================================
>0000  00000004 a01c0000 ALU 8 @8
> 0008  00380400 00346b10     1      x: INTERP_XY          R1.x,  R0.y, Param0.x         VEC_210
> 0010  00380000 20346b10            y: INTERP_XY          R1.y,  R0.x, Param0.x         VEC_210
> 0012  00380400 40146b00            z: INTERP_XY          __.z,  R0.y, Param0.x         VEC_210
> 0014  80380000 60146b00            w: INTERP_XY          __.w,  R0.x, Param0.x         VEC_210
> 0016  00380400 00146b80     2      x: INTERP_ZW          __.x,  R0.y, Param0.x         VEC_210
> 0018  00380000 20146b80            y: INTERP_ZW          __.y,  R0.x, Param0.x         VEC_210
> 0020  00380400 40346b90            z: INTERP_ZW          R1.z,  R0.y, Param0.x         VEC_210
> 0022  80380000 60346b90            w: INTERP_ZW          R1.w,  R0.x, Param0.x         VEC_210
>0002  c0008000 95200688 EXPORT_DONE        PIXEL 0     R1.xyzw  EOP
>===== SHADER_END ===============================================================
>
>
>===== SHADER #21 OPT ================================ PS/REDWOOD/EVERGREEN =====
>===== 20 dw ===== 1 gprs ===== 0 stack =========================================
>0000  00000002 a01c0000 ALU 8 @4
> 0004  00380400 00146b80     1      x: INTERP_ZW          __.x,  R0.y, Param0.x         VEC_210
> 0006  00b80000 20146b80            y: INTERP_ZW          __.y,  R0.x, Param0.y         VEC_210
> 0008  01380400 40146b90            z: INTERP_ZW          R0.z,  R0.y, Param0.z         VEC_210
> 0010  81b80000 60146b90            w: INTERP_ZW          R0.w,  R0.x, Param0.w         VEC_210
> 0012  00380400 00146b10     2      x: INTERP_XY          R0.x,  R0.y, Param0.x         VEC_210
> 0014  00b80000 20146b10            y: INTERP_XY          R0.y,  R0.x, Param0.y         VEC_210
> 0016  01380400 40146b00            z: INTERP_XY          __.z,  R0.y, Param0.z         VEC_210
> 0018  81b80000 60146b00            w: INTERP_XY          __.w,  R0.x, Param0.w         VEC_210
>0002  c0000000 95200688 EXPORT_DONE        PIXEL 0     R0.xyzw  EOP
>===== SHADER_END ===============================================================
>
>--------------------------------------------------------------
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[9]
>DCL CONST[0..3]
>DCL TEMP[0], LOCAL
>  0: MUL TEMP[0], CONST[0], IN[0].xxxx
>  1: MAD TEMP[0], CONST[1], IN[0].yyyy, TEMP[0]
>  2: MAD TEMP[0], CONST[2], IN[0].zzzz, TEMP[0]
>  3: MAD TEMP[0], CONST[3], IN[0].wwww, TEMP[0]
>  4: MOV OUT[1], IN[1]
>  5: MOV OUT[0], TEMP[0]
>  6: END
>; ModuleID = 'tgsi'
>
>define void @main(<4 x float> inreg, <4 x float> inreg, <4 x float> inreg) #0 {
>main_body:
>  %3 = extractelement <4 x float> %1, i32 0
>  %4 = extractelement <4 x float> %1, i32 1
>  %5 = extractelement <4 x float> %1, i32 2
>  %6 = extractelement <4 x float> %1, i32 3
>  %7 = load <4 x float> addrspace(8)* null
>  %8 = extractelement <4 x float> %7, i32 0
>  %9 = fmul float %8, %3
>  %10 = extractelement <4 x float> %7, i32 1
>  %11 = fmul float %10, %3
>  %12 = extractelement <4 x float> %7, i32 2
>  %13 = fmul float %12, %3
>  %14 = load <4 x float> addrspace(8)* null
>  %15 = extractelement <4 x float> %14, i32 3
>  %16 = fmul float %15, %3
>  %17 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
>  %18 = extractelement <4 x float> %17, i32 0
>  %19 = fmul float %18, %4
>  %20 = fadd float %19, %9
>  %21 = extractelement <4 x float> %17, i32 1
>  %22 = fmul float %21, %4
>  %23 = fadd float %22, %11
>  %24 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
>  %25 = extractelement <4 x float> %24, i32 2
>  %26 = fmul float %25, %4
>  %27 = fadd float %26, %13
>  %28 = extractelement <4 x float> %24, i32 3
>  %29 = fmul float %28, %4
>  %30 = fadd float %29, %16
>  %31 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
>  %32 = extractelement <4 x float> %31, i32 0
>  %33 = fmul float %32, %5
>  %34 = fadd float %33, %20
>  %35 = extractelement <4 x float> %31, i32 1
>  %36 = fmul float %35, %5
>  %37 = fadd float %36, %23
>  %38 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
>  %39 = extractelement <4 x float> %38, i32 2
>  %40 = fmul float %39, %5
>  %41 = fadd float %40, %27
>  %42 = extractelement <4 x float> %38, i32 3
>  %43 = fmul float %42, %5
>  %44 = fadd float %43, %30
>  %45 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
>  %46 = extractelement <4 x float> %45, i32 0
>  %47 = fmul float %46, %6
>  %48 = fadd float %47, %34
>  %49 = extractelement <4 x float> %45, i32 1
>  %50 = fmul float %49, %6
>  %51 = fadd float %50, %37
>  %52 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
>  %53 = extractelement <4 x float> %52, i32 2
>  %54 = fmul float %53, %6
>  %55 = fadd float %54, %41
>  %56 = extractelement <4 x float> %52, i32 3
>  %57 = fmul float %56, %6
>  %58 = fadd float %57, %44
>  %59 = insertelement <4 x float> undef, float %48, i32 0
>  %60 = insertelement <4 x float> %59, float %51, i32 1
>  %61 = insertelement <4 x float> %60, float %55, i32 2
>  %62 = insertelement <4 x float> %61, float %58, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %62, i32 60, i32 1)
>  call void @llvm.R600.store.swizzle(<4 x float> %2, i32 0, i32 2)
>  ret void
>}
>
>declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
>
>attributes #0 = { "ShaderType"="1" }
>
>===== SHADER #22 ==================================== VS/REDWOOD/EVERGREEN =====
>===== 44 dw ===== 5 gprs ===== 1 stack =========================================
>0000  00000000 84c00000 CALL_FS @0
>0002  80000006 a03c0000 ALU 16 @12 KC0[CB0:0-31]
> 0012  80002080 60000110     1      w: MUL_IEEE           R0.w,  KC0[0].x, R1.x
> 0014  00802081 60030cfe     2      w: MULADD_IEEE        R0.w,  KC0[1].x, R1.y, PV.w
> 0016  80002480 60600110            t: MUL_IEEE           R3.w,  KC0[0].y, R1.x
> 0018  81002082 60030cfe     3      w: MULADD_IEEE        R0.w,  KC0[2].x, R1.z, PV.w
> 0020  01802083 00030cfe     4      x: MULADD_IEEE        R0.x,  KC0[3].x, R1.w, PV.w
> 0022  80802481 60630c03            w: MULADD_IEEE        R3.w,  KC0[1].y, R1.y, R3.w
> 0024  80002880 60800110     5      w: MUL_IEEE           R4.w,  KC0[0].z, R1.x
> 0026  00802881 40630cfe     6      z: MULADD_IEEE        R3.z,  KC0[1].z, R1.y, PV.w
> 0028  80002c80 60800110            w: MUL_IEEE           R4.w,  KC0[0].w, R1.x
> 0030  81002482 60630c03     7      w: MULADD_IEEE        R3.w,  KC0[2].y, R1.z, R3.w
> 0032  01802483 20030cfe     8      y: MULADD_IEEE        R0.y,  KC0[3].y, R1.w, PV.w
> 0034  80802c81 60630c04            w: MULADD_IEEE        R3.w,  KC0[1].w, R1.y, R4.w
> 0036  81002882 60830803     9      w: MULADD_IEEE        R4.w,  KC0[2].z, R1.z, R3.z
> 0038  01802883 40030cfe    10      z: MULADD_IEEE        R0.z,  KC0[3].z, R1.w, PV.w
> 0040  81002c82 60630c03            w: MULADD_IEEE        R3.w,  KC0[2].w, R1.z, R3.w
> 0042  81802c83 60030cfe    11      w: MULADD_IEEE        R0.w,  KC0[3].w, R1.w, PV.w
>0004  c000203c 95000688 EXPORT_DONE        POS   60    R0.xyzw
>0006  c0014000 95200688 EXPORT_DONE        PARAM 0     R2.xyzw  EOP
>===== SHADER_END ===============================================================
>
>
>===== SHADER #22 OPT ================================ VS/REDWOOD/EVERGREEN =====
>===== 40 dw ===== 3 gprs ===== 1 stack =========================================
>0000  00000000 84c00000 CALL_FS @0
>0002  40000004 a03c0000 ALU 16 @8 KC0[CB0:0-15]
> 0008  00002c80 0f800110     1      x: MUL_IEEE           T0.x,  KC0[0].w, R1.x
> 0010  80002880 2f800110            y: MUL_IEEE           T0.y,  KC0[0].z, R1.x
> 0012  00802c81 0f83007c     2      x: MULADD_IEEE        T0.x,  KC0[1].w, R1.y, T0.x
> 0014  00802881 2f83047c            y: MULADD_IEEE        T0.y,  KC0[1].z, R1.y, T0.y
> 0016  00002480 4f800110            z: MUL_IEEE           T0.z,  KC0[0].y, R1.x
> 0018  80002080 6f800110            w: MUL_IEEE           T0.w,  KC0[0].x, R1.x
> 0020  01002c82 0fa3007c     3      x: MULADD_IEEE        T1.x,  KC0[2].w, R1.z, T0.x
> 0022  00802481 4f83087c            z: MULADD_IEEE        T0.z,  KC0[1].y, R1.y, T0.z
> 0024  80802081 6f830c7c            w: MULADD_IEEE        T0.w,  KC0[1].x, R1.y, T0.w
> 0026  01002482 0f83087c     4      x: MULADD_IEEE        T0.x,  KC0[2].y, R1.z, T0.z
> 0028  01002082 2f830c7c            y: MULADD_IEEE        T0.y,  KC0[2].x, R1.z, T0.w
> 0030  81002882 2fab047c            t: MULADD_IEEE        T1.y,  KC0[2].z, R1.z, T0.y   SCL_212
> 0032  01802083 0003047c     5      x: MULADD_IEEE        R0.x,  KC0[3].x, R1.w, T0.y
> 0034  01802483 2003007c            y: MULADD_IEEE        R0.y,  KC0[3].y, R1.w, T0.x
> 0036  01802883 4007047d            z: MULADD_IEEE        R0.z,  KC0[3].z, R1.w, T1.y   VEC_021
> 0038  81802c83 6007007d            w: MULADD_IEEE        R0.w,  KC0[3].w, R1.w, T1.x   VEC_021
>0004  c000203c 95000688 EXPORT_DONE        POS   60    R0.xyzw
>0006  c0014000 95200688 EXPORT_DONE        PARAM 0     R2.xyzw  EOP
>===== SHADER_END ===============================================================
>
>libGL: FPS = 5.8
>libGL: FPS = 54.7
>libGL: FPS = 60.0
>libGL: FPS = 60.0
>libGL: FPS = 60.0
>libGL: FPS = 60.0
>libGL: FPS = 60.0
>libGL: FPS = 60.0
>--------------------------------------------------------------
>FRAG
>DCL IN[0], GENERIC[0], LINEAR
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SVIEW[0], 2D, UINT
>  0: TEX OUT[0], IN[0], SAMP[0], 2D
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main(<4 x float> inreg, <4 x float> inreg) #0 {
>main_body:
>  %2 = extractelement <4 x float> %0, i32 0
>  %3 = extractelement <4 x float> %0, i32 1
>  %4 = call <2 x float> @llvm.R600.interp.xy(i32 0, float %2, float %3)
>  %5 = call <2 x float> @llvm.R600.interp.zw(i32 0, float %2, float %3)
>  %6 = shufflevector <2 x float> %4, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
>  %7 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %6, i32 16, i32 0, i32 2)
>  call void @llvm.R600.store.swizzle(<4 x float> %7, i32 0, i32 0)
>  ret void
>}
>
>; Function Attrs: readnone
>declare <2 x float> @llvm.R600.interp.xy(i32, float, float) #1
>
>; Function Attrs: readnone
>declare <2 x float> @llvm.R600.interp.zw(i32, float, float) #1
>
>; Function Attrs: readnone
>declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32, i32) #1
>
>declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { readnone }
>
>===== SHADER #23 ==================================== PS/REDWOOD/EVERGREEN =====
>===== 20 dw ===== 1 gprs ===== 0 stack =========================================
>0000  00000006 a00c0000 ALU 4 @12
> 0012  00380400 00146b10     1      x: INTERP_XY          R0.x,  R0.y, Param0.x         VEC_210
> 0014  00380000 20146b10            y: INTERP_XY          R0.y,  R0.x, Param0.x         VEC_210
> 0016  00380400 40146b00            z: INTERP_XY          __.z,  R0.y, Param0.x         VEC_210
> 0018  80380000 60146b00            w: INTERP_XY          __.w,  R0.x, Param0.x         VEC_210
>0002  00000004 80400000 TEX 1 @8
> 0008  00001010 f00d1000 fc800000 SAMPLE              R0.xyzw, R0.xy__,   RID:16, SID:0 CT:NNNN
>0004  c0000000 95200688 EXPORT_DONE        PIXEL 0     R0.xyzw  EOP
>===== SHADER_END ===============================================================
>
>
>===== SHADER #23 OPT ================================ PS/REDWOOD/EVERGREEN =====
>===== 20 dw ===== 1 gprs ===== 0 stack =========================================
>0000  00000003 a00c0000 ALU 4 @6
> 0006  00380400 00146b10     1      x: INTERP_XY          R0.x,  R0.y, Param0.x         VEC_210
> 0008  00b80000 20146b10            y: INTERP_XY          R0.y,  R0.x, Param0.y         VEC_210
> 0010  01380400 40146b00            z: INTERP_XY          __.z,  R0.y, Param0.z         VEC_210
> 0012  81b80000 60146b00            w: INTERP_XY          __.w,  R0.x, Param0.w         VEC_210
>0002  00000008 80400000 TEX 1 @16
> 0016  00001010 f00d1000 fc800000 SAMPLE              R0.xyzw, R0.xy__,   RID:16, SID:0 CT:NNNN
>0004  c0000000 95200688 EXPORT_DONE        PIXEL 0     R0.xyzw  EOP
>===== SHADER_END ===============================================================
>
>Server using port 26000
>Server listening on address 0.0.0.0:26000
>Server listening on address [0:0:0:0:0:0:0:0]:26000
>Beginning notification initialization on SVQC program...
>Notification initialization successful!
>libGL: FPS = 2.3
>libGL: FPS = 5.9
>[1;31mmodels/weapons/g_ok_hmg.md3:[m could not load texture [1;33m"overkillbullet"[m
>[1;31mmodels/weapons/v_ok_hmg.md3:[m could not load texture [1;33m"overkillbullet"[m
>[1;31mmodels/weapons/h_ok_hmg.iqm:[m could not load texture [1;33m"overkillbullet"[m
>libGL: FPS = 5.6
>libGL: FPS = 5.1
>libGL: FPS = 5.6
>libGL: FPS = 0.8
>Authenticated connection to local:2 has been established: client is 8Zy9h8bUlYB0IG0UG6fHIfTohxj2i2KLvhUPbmLdYY4=@Xon//Ks, I am 8Zy9h8b@Xon//Ks
>Authenticated connection to local:1 has been established: server is 8Zy9h8bUlYB0IG0UG6fHIfTohxj2i2KLvhUPbmLdYY4=@Xon//Ks, I am 8Zy9h8b@Xon//Ks
>Connection accepted to local:1
><-- server to client keepalive
>
>Server: Xonotic build 02:07:41 Aug 25 2015 - release (progs 29911 crc)
>
><===================================>
>
>[1;33m[m
>libGL: FPS = 17.7
>libGL: FPS = 0.4
>Beginning notification initialization on CSQC program...
>Notification initialization successful!
>libGL: FPS = 2.8
><-- server to client keepalive
>unconnected changed name to [BOT]Pegasus
>unconnected changed name to [BOT]Scorcher
>[1;34mSVQC Build information: [1;31mxonotic-v0.8.0-984-gf0d7836[m
>[1;33m[msnejko[1;34m connected[m
>[1;33m[m[BOT]Pegasus[1;34m connected[m
>[1;33m[m[BOT]Scorcher[1;34m connected[m
>--------------------------------------------------------------
>FRAG
>DCL IN[0], GENERIC[9], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SVIEW[0], 2D, FLOAT
>DCL CONST[1..2]
>DCL TEMP[0..1], LOCAL
>  0: MOV TEMP[0].xy, IN[0].xyyy
>  1: TEX TEMP[0], TEMP[0], SAMP[0], 2D
>  2: MUL TEMP[1].x, TEMP[0].wwww, CONST[2].xxxx
>  3: MOV TEMP[1].w, TEMP[1].xxxx
>  4: MUL TEMP[1].xyz, TEMP[0].xyzz, CONST[1].xyzz
>  5: MOV OUT[0], TEMP[1]
>  6: END
>; ModuleID = 'tgsi'
>
>define void @main(<4 x float> inreg, <4 x float> inreg) #0 {
>main_body:
>  %2 = extractelement <4 x float> %0, i32 0
>  %3 = extractelement <4 x float> %0, i32 1
>  %4 = call <2 x float> @llvm.R600.interp.xy(i32 0, float %2, float %3)
>  %5 = call <2 x float> @llvm.R600.interp.zw(i32 0, float %2, float %3)
>  %6 = shufflevector <2 x float> %4, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
>  %7 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %6, i32 16, i32 0, i32 2)
>  %8 = extractelement <4 x float> %7, i32 0
>  %9 = extractelement <4 x float> %7, i32 1
>  %10 = extractelement <4 x float> %7, i32 2
>  %11 = extractelement <4 x float> %7, i32 3
>  %12 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
>  %13 = extractelement <4 x float> %12, i32 0
>  %14 = fmul float %11, %13
>  %15 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
>  %16 = extractelement <4 x float> %15, i32 0
>  %17 = fmul float %8, %16
>  %18 = extractelement <4 x float> %15, i32 1
>  %19 = fmul float %9, %18
>  %20 = extractelement <4 x float> %15, i32 2
>  %21 = fmul float %10, %20
>  %22 = insertelement <4 x float> undef, float %17, i32 0
>  %23 = insertelement <4 x float> %22, float %19, i32 1
>  %24 = insertelement <4 x float> %23, float %21, i32 2
>  %25 = insertelement <4 x float> %24, float %14, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %25, i32 0, i32 0)
>  ret void
>}
>
>; Function Attrs: readnone
>declare <2 x float> @llvm.R600.interp.xy(i32, float, float) #1
>
>; Function Attrs: readnone
>declare <2 x float> @llvm.R600.interp.zw(i32, float, float) #1
>
>; Function Attrs: readnone
>declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32, i32) #1
>
>declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { readnone }
>
>===== SHADER #25 ==================================== PS/REDWOOD/EVERGREEN =====
>===== 32 dw ===== 2 gprs ===== 0 stack =========================================
>0000  00000008 a00c0000 ALU 4 @16
> 0016  00380400 00146b10     1      x: INTERP_XY          R0.x,  R0.y, Param0.x         VEC_210
> 0018  00380000 20146b10            y: INTERP_XY          R0.y,  R0.x, Param0.x         VEC_210
> 0020  00380400 40146b00            z: INTERP_XY          __.z,  R0.y, Param0.x         VEC_210
> 0022  80380000 60146b00            w: INTERP_XY          __.w,  R0.x, Param0.x         VEC_210
>0002  00000006 80400000 TEX 1 @12
> 0012  00001010 f00d1000 fc800000 SAMPLE              R0.xyzw, R0.xy__,   RID:16, SID:0 CT:NNNN
>0004  8000000c a00c0000 ALU 4 @24 KC0[CB0:0-31]
> 0024  80104c00 60200110     2      w: MUL_IEEE           R1.w,  R0.w, KC0[2].x
> 0026  00102000 00200110     3      x: MUL_IEEE           R1.x,  R0.x, KC0[1].x
> 0028  00902400 20200110            y: MUL_IEEE           R1.y,  R0.y, KC0[1].y
> 0030  81102800 40200110            z: MUL_IEEE           R1.z,  R0.z, KC0[1].z
>0006  c0008000 95200688 EXPORT_DONE        PIXEL 0     R1.xyzw  EOP
>===== SHADER_END ===============================================================
>
>
>===== SHADER #25 OPT ================================ PS/REDWOOD/EVERGREEN =====
>===== 28 dw ===== 1 gprs ===== 0 stack =========================================
>0000  00000004 a00c0000 ALU 4 @8
> 0008  00380400 00146b10     1      x: INTERP_XY          R0.x,  R0.y, Param0.x         VEC_210
> 0010  00b80000 20146b10            y: INTERP_XY          R0.y,  R0.x, Param0.y         VEC_210
> 0012  01380400 40146b00            z: INTERP_XY          __.z,  R0.y, Param0.z         VEC_210
> 0014  81b80000 60146b00            w: INTERP_XY          __.w,  R0.x, Param0.w         VEC_210
>0002  00000008 80400000 TEX 1 @16
> 0016  00001010 f00d1000 fc800000 SAMPLE              R0.xyzw, R0.xy__,   RID:16, SID:0 CT:NNNN
>0004  4000000a a00c0000 ALU 4 @20 KC0[CB0:0-15]
> 0020  80104c00 60000110     2      w: MUL_IEEE           R0.w,  R0.w, KC0[2].x
> 0022  00102000 00000110     3      x: MUL_IEEE           R0.x,  R0.x, KC0[1].x
> 0024  00902400 20000110            y: MUL_IEEE           R0.y,  R0.y, KC0[1].y
> 0026  81102800 40000110            z: MUL_IEEE           R0.z,  R0.z, KC0[1].z
>0006  c0000000 95200688 EXPORT_DONE        PIXEL 0     R0.xyzw  EOP
>===== SHADER_END ===============================================================
>
>--------------------------------------------------------------
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[9]
>DCL CONST[0..7]
>DCL TEMP[0..1], LOCAL
>IMM[0] FLT32 {    0.0000,     0.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].zw, IMM[0].xxxx
>  1: MUL TEMP[1], CONST[4], IN[1].xxxx
>  2: MAD TEMP[1], CONST[5], IN[1].yyyy, TEMP[1]
>  3: MAD TEMP[1], CONST[6], IN[1].zzzz, TEMP[1]
>  4: MAD TEMP[1].xy, CONST[7], IN[1].wwww, TEMP[1]
>  5: MOV TEMP[0].xy, TEMP[1].xyxx
>  6: MUL TEMP[1], CONST[0], IN[0].xxxx
>  7: MAD TEMP[1], CONST[1], IN[0].yyyy, TEMP[1]
>  8: MAD TEMP[1], CONST[2], IN[0].zzzz, TEMP[1]
>  9: MAD TEMP[1], CONST[3], IN[0].wwww, TEMP[1]
> 10: MOV OUT[0], TEMP[1]
> 11: MOV OUT[1], TEMP[0]
> 12: END
>; ModuleID = 'tgsi'
>
>define void @main(<4 x float> inreg, <4 x float> inreg, <4 x float> inreg) #0 {
>main_body:
>  %3 = extractelement <4 x float> %1, i32 0
>  %4 = extractelement <4 x float> %1, i32 1
>  %5 = extractelement <4 x float> %1, i32 2
>  %6 = extractelement <4 x float> %1, i32 3
>  %7 = extractelement <4 x float> %2, i32 0
>  %8 = extractelement <4 x float> %2, i32 1
>  %9 = extractelement <4 x float> %2, i32 2
>  %10 = extractelement <4 x float> %2, i32 3
>  %11 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4)
>  %12 = extractelement <4 x float> %11, i32 0
>  %13 = fmul float %12, %7
>  %14 = extractelement <4 x float> %11, i32 1
>  %15 = fmul float %14, %7
>  %16 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5)
>  %17 = extractelement <4 x float> %16, i32 0
>  %18 = fmul float %17, %8
>  %19 = fadd float %18, %13
>  %20 = extractelement <4 x float> %16, i32 1
>  %21 = fmul float %20, %8
>  %22 = fadd float %21, %15
>  %23 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6)
>  %24 = extractelement <4 x float> %23, i32 0
>  %25 = fmul float %24, %9
>  %26 = fadd float %25, %19
>  %27 = extractelement <4 x float> %23, i32 1
>  %28 = fmul float %27, %9
>  %29 = fadd float %28, %22
>  %30 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7)
>  %31 = extractelement <4 x float> %30, i32 0
>  %32 = fmul float %31, %10
>  %33 = fadd float %32, %26
>  %34 = extractelement <4 x float> %30, i32 1
>  %35 = fmul float %34, %10
>  %36 = fadd float %35, %29
>  %37 = load <4 x float> addrspace(8)* null
>  %38 = extractelement <4 x float> %37, i32 0
>  %39 = fmul float %38, %3
>  %40 = extractelement <4 x float> %37, i32 1
>  %41 = fmul float %40, %3
>  %42 = extractelement <4 x float> %37, i32 2
>  %43 = fmul float %42, %3
>  %44 = load <4 x float> addrspace(8)* null
>  %45 = extractelement <4 x float> %44, i32 3
>  %46 = fmul float %45, %3
>  %47 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
>  %48 = extractelement <4 x float> %47, i32 0
>  %49 = fmul float %48, %4
>  %50 = fadd float %49, %39
>  %51 = extractelement <4 x float> %47, i32 1
>  %52 = fmul float %51, %4
>  %53 = fadd float %52, %41
>  %54 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
>  %55 = extractelement <4 x float> %54, i32 2
>  %56 = fmul float %55, %4
>  %57 = fadd float %56, %43
>  %58 = extractelement <4 x float> %54, i32 3
>  %59 = fmul float %58, %4
>  %60 = fadd float %59, %46
>  %61 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
>  %62 = extractelement <4 x float> %61, i32 0
>  %63 = fmul float %62, %5
>  %64 = fadd float %63, %50
>  %65 = extractelement <4 x float> %61, i32 1
>  %66 = fmul float %65, %5
>  %67 = fadd float %66, %53
>  %68 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
>  %69 = extractelement <4 x float> %68, i32 2
>  %70 = fmul float %69, %5
>  %71 = fadd float %70, %57
>  %72 = extractelement <4 x float> %68, i32 3
>  %73 = fmul float %72, %5
>  %74 = fadd float %73, %60
>  %75 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
>  %76 = extractelement <4 x float> %75, i32 0
>  %77 = fmul float %76, %6
>  %78 = fadd float %77, %64
>  %79 = extractelement <4 x float> %75, i32 1
>  %80 = fmul float %79, %6
>  %81 = fadd float %80, %67
>  %82 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
>  %83 = extractelement <4 x float> %82, i32 2
>  %84 = fmul float %83, %6
>  %85 = fadd float %84, %71
>  %86 = extractelement <4 x float> %82, i32 3
>  %87 = fmul float %86, %6
>  %88 = fadd float %87, %74
>  %89 = insertelement <4 x float> undef, float %78, i32 0
>  %90 = insertelement <4 x float> %89, float %81, i32 1
>  %91 = insertelement <4 x float> %90, float %85, i32 2
>  %92 = insertelement <4 x float> %91, float %88, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %92, i32 60, i32 1)
>  %93 = insertelement <4 x float> undef, float %33, i32 0
>  %94 = insertelement <4 x float> %93, float %36, i32 1
>  %95 = insertelement <4 x float> %94, float 0.000000e+00, i32 2
>  %96 = insertelement <4 x float> %95, float 0.000000e+00, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %96, i32 0, i32 2)
>  ret void
>}
>
>declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
>
>attributes #0 = { "ShaderType"="1" }
>
>===== SHADER #26 ==================================== VS/REDWOOD/EVERGREEN =====
>===== 60 dw ===== 6 gprs ===== 1 stack =========================================
>0000  00000000 84c00000 CALL_FS @0
>0002  80000006 a05c0000 ALU 24 @12 KC0[CB0:0-31]
> 0012  80002080 60000110     1      w: MUL_IEEE           R0.w,  KC0[0].x, R1.x
> 0014  00802081 40030cfe     2      z: MULADD_IEEE        R0.z,  KC0[1].x, R1.y, PV.w
> 0016  80002480 60000110            w: MUL_IEEE           R0.w,  KC0[0].y, R1.x
> 0018  80004084 60600110     3      w: MUL_IEEE           R3.w,  KC0[4].x, R2.x
> 0020  00804085 40630cfe     4      z: MULADD_IEEE        R3.z,  KC0[5].x, R2.y, PV.w
> 0022  80802481 60070c00            w: MULADD_IEEE        R0.w,  KC0[1].y, R1.y, R0.w   VEC_021
> 0024  81002082 60630800     5      w: MULADD_IEEE        R3.w,  KC0[2].x, R1.z, R0.z
> 0026  01802083 00830cfe     6      x: MULADD_IEEE        R4.x,  KC0[3].x, R1.w, PV.w
> 0028  81002482 60030c00            w: MULADD_IEEE        R0.w,  KC0[2].y, R1.z, R0.w
> 0030  81004086 60630803     7      w: MULADD_IEEE        R3.w,  KC0[6].x, R2.z, R3.z
> 0032  01804087 00630cfe     8      x: MULADD_IEEE        R3.x,  KC0[7].x, R2.w, PV.w
> 0034  81802483 208b0c00            y: MULADD_IEEE        R4.y,  KC0[3].y, R1.w, R0.w   VEC_120
> 0036  80002880 60000110     9      w: MUL_IEEE           R0.w,  KC0[0].z, R1.x
> 0038  00802881 40030cfe    10      z: MULADD_IEEE        R0.z,  KC0[1].z, R1.y, PV.w
> 0040  80002c80 60000110            w: MUL_IEEE           R0.w,  KC0[0].w, R1.x
> 0042  80004484 60a00110    11      w: MUL_IEEE           R5.w,  KC0[4].y, R2.x
> 0044  00804485 40a30cfe    12      z: MULADD_IEEE        R5.z,  KC0[5].y, R2.y, PV.w
> 0046  80802c81 60070c00            w: MULADD_IEEE        R0.w,  KC0[1].w, R1.y, R0.w   VEC_021
> 0048  81002882 60a30800    13      w: MULADD_IEEE        R5.w,  KC0[2].z, R1.z, R0.z
> 0050  01802883 40830cfe    14      z: MULADD_IEEE        R4.z,  KC0[3].z, R1.w, PV.w
> 0052  81002c82 60030c00            w: MULADD_IEEE        R0.w,  KC0[2].w, R1.z, R0.w
> 0054  81004486 60a30805    15      w: MULADD_IEEE        R5.w,  KC0[6].y, R2.z, R5.z
> 0056  01804487 20630cfe    16      y: MULADD_IEEE        R3.y,  KC0[7].y, R2.w, PV.w
> 0058  81802c83 608b0c00            w: MULADD_IEEE        R4.w,  KC0[3].w, R1.w, R0.w   VEC_120
>0004  c002203c 95000688 EXPORT_DONE        POS   60    R4.xyzw
>0006  c001c000 95200908 EXPORT_DONE        PARAM 0     R3.xy00  EOP
>===== SHADER_END ===============================================================
>
>
>===== SHADER #26 OPT ================================ VS/REDWOOD/EVERGREEN =====
>===== 56 dw ===== 3 gprs ===== 1 stack =========================================
>0000  00000000 84c00000 CALL_FS @0
>0002  40000004 a05c0000 ALU 24 @8 KC0[CB0:0-15]
> 0008  00002c80 0f800110     1      x: MUL_IEEE           T0.x,  KC0[0].w, R1.x
> 0010  80002880 2f800110            y: MUL_IEEE           T0.y,  KC0[0].z, R1.x
> 0012  00004084 0fc00110     2      x: MUL_IEEE           T2.x,  KC0[4].x, R2.x
> 0014  00002480 4f840110            z: MUL_IEEE           T0.z,  KC0[0].y, R1.x         VEC_021
> 0016  80002080 6f840110            w: MUL_IEEE           T0.w,  KC0[0].x, R1.x         VEC_021
> 0018  00802c81 0f83007c     3      x: MULADD_IEEE        T0.x,  KC0[1].w, R1.y, T0.x
> 0020  00802881 2fa3047c            y: MULADD_IEEE        T1.y,  KC0[1].z, R1.y, T0.y
> 0022  80004484 0fa00110            t: MUL_IEEE           T1.x,  KC0[4].y, R2.x
> 0024  00804085 2f83007e     4      y: MULADD_IEEE        T0.y,  KC0[5].x, R2.y, T2.x
> 0026  00802481 4f87087c            z: MULADD_IEEE        T0.z,  KC0[1].y, R1.y, T0.z   VEC_021
> 0028  80802081 6f870c7c            w: MULADD_IEEE        T0.w,  KC0[1].x, R1.y, T0.w   VEC_021
> 0030  01002c82 0fc3007c     5      x: MULADD_IEEE        T2.x,  KC0[2].w, R1.z, T0.x
> 0032  01002882 2fa7047d            y: MULADD_IEEE        T1.y,  KC0[2].z, R1.z, T1.y   VEC_021
> 0034  80804485 0f8f007d            t: MULADD_IEEE        T0.x,  KC0[5].y, R2.y, T1.x   SCL_221
> 0036  01004486 0f8f007c     6      x: MULADD_IEEE        T0.x,  KC0[6].y, R2.z, T0.x   VEC_102
> 0038  01004086 2f8f047c            y: MULADD_IEEE        T0.y,  KC0[6].x, R2.z, T0.y   VEC_102
> 0040  01002082 4f830c7c            z: MULADD_IEEE        T0.z,  KC0[2].x, R1.z, T0.w
> 0042  81002482 0fab087c            t: MULADD_IEEE        T1.x,  KC0[2].y, R1.z, T0.z   SCL_212
> 0044  01802483 2003007d     7      y: MULADD_IEEE        R0.y,  KC0[3].y, R1.w, T1.x
> 0046  01802883 4003047d            z: MULADD_IEEE        R0.z,  KC0[3].z, R1.w, T1.y
> 0048  81802c83 6007007e            w: MULADD_IEEE        R0.w,  KC0[3].w, R1.w, T2.x   VEC_021
> 0050  01804087 0023047c     8      x: MULADD_IEEE        R1.x,  KC0[7].x, R2.w, T0.y
> 0052  01804487 2023007c            y: MULADD_IEEE        R1.y,  KC0[7].y, R2.w, T0.x
> 0054  81802083 0007087c            t: MULADD_IEEE        R0.x,  KC0[3].x, R1.w, T0.z   SCL_122
>0004  c000c000 95000908 EXPORT_DONE        PARAM 0     R1.xy00
>0006  c000203c 95200688 EXPORT_DONE        POS   60    R0.xyzw  EOP
>===== SHADER_END ===============================================================
>
>--------------------------------------------------------------
>FRAG
>DCL OUT[0], COLOR
>IMM[0] FLT32 {    1.0000,     0.0000,     0.0000,     0.0000}
>  0: MOV OUT[0], IMM[0].xxxx
>  1: END
>; ModuleID = 'tgsi'
>
>define void @main(<4 x float> inreg) #0 {
>main_body:
>  call void @llvm.R600.store.swizzle(<4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>, i32 0, i32 0)
>  ret void
>}
>
>declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
>
>attributes #0 = { "ShaderType"="0" }
>
>===== SHADER #28 ==================================== PS/REDWOOD/EVERGREEN =====
>===== 4 dw ===== 1 gprs ===== 0 stack ==========================================
>0000  c0000000 95200b6d EXPORT_DONE        PIXEL 0     R0.1111  EOP
>===== SHADER_END ===============================================================
>
>
>===== SHADER #28 OPT ================================ PS/REDWOOD/EVERGREEN =====
>===== 2 dw ===== 0 gprs ===== 0 stack ==========================================
>0000  c0000000 95200b6d EXPORT_DONE        PIXEL 0     R0.1111  EOP
>===== SHADER_END ===============================================================
>
>--------------------------------------------------------------
>VERT
>DCL IN[0]
>DCL OUT[0], POSITION
>DCL CONST[0..3]
>DCL TEMP[0], LOCAL
>  0: MUL TEMP[0], CONST[0], IN[0].xxxx
>  1: MAD TEMP[0], CONST[1], IN[0].yyyy, TEMP[0]
>  2: MAD TEMP[0], CONST[2], IN[0].zzzz, TEMP[0]
>  3: MAD TEMP[0], CONST[3], IN[0].wwww, TEMP[0]
>  4: MOV OUT[0], TEMP[0]
>  5: END
>; ModuleID = 'tgsi'
>
>define void @main(<4 x float> inreg, <4 x float> inreg) #0 {
>main_body:
>  %2 = extractelement <4 x float> %1, i32 0
>  %3 = extractelement <4 x float> %1, i32 1
>  %4 = extractelement <4 x float> %1, i32 2
>  %5 = extractelement <4 x float> %1, i32 3
>  %6 = load <4 x float> addrspace(8)* null
>  %7 = extractelement <4 x float> %6, i32 0
>  %8 = fmul float %7, %2
>  %9 = extractelement <4 x float> %6, i32 1
>  %10 = fmul float %9, %2
>  %11 = extractelement <4 x float> %6, i32 2
>  %12 = fmul float %11, %2
>  %13 = load <4 x float> addrspace(8)* null
>  %14 = extractelement <4 x float> %13, i32 3
>  %15 = fmul float %14, %2
>  %16 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
>  %17 = extractelement <4 x float> %16, i32 0
>  %18 = fmul float %17, %3
>  %19 = fadd float %18, %8
>  %20 = extractelement <4 x float> %16, i32 1
>  %21 = fmul float %20, %3
>  %22 = fadd float %21, %10
>  %23 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
>  %24 = extractelement <4 x float> %23, i32 2
>  %25 = fmul float %24, %3
>  %26 = fadd float %25, %12
>  %27 = extractelement <4 x float> %23, i32 3
>  %28 = fmul float %27, %3
>  %29 = fadd float %28, %15
>  %30 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
>  %31 = extractelement <4 x float> %30, i32 0
>  %32 = fmul float %31, %4
>  %33 = fadd float %32, %19
>  %34 = extractelement <4 x float> %30, i32 1
>  %35 = fmul float %34, %4
>  %36 = fadd float %35, %22
>  %37 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
>  %38 = extractelement <4 x float> %37, i32 2
>  %39 = fmul float %38, %4
>  %40 = fadd float %39, %26
>  %41 = extractelement <4 x float> %37, i32 3
>  %42 = fmul float %41, %4
>  %43 = fadd float %42, %29
>  %44 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
>  %45 = extractelement <4 x float> %44, i32 0
>  %46 = fmul float %45, %5
>  %47 = fadd float %46, %33
>  %48 = extractelement <4 x float> %44, i32 1
>  %49 = fmul float %48, %5
>  %50 = fadd float %49, %36
>  %51 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
>  %52 = extractelement <4 x float> %51, i32 2
>  %53 = fmul float %52, %5
>  %54 = fadd float %53, %40
>  %55 = extractelement <4 x float> %51, i32 3
>  %56 = fmul float %55, %5
>  %57 = fadd float %56, %43
>  %58 = insertelement <4 x float> undef, float %47, i32 0
>  %59 = insertelement <4 x float> %58, float %50, i32 1
>  %60 = insertelement <4 x float> %59, float %54, i32 2
>  %61 = insertelement <4 x float> %60, float %57, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %61, i32 60, i32 1)
>  call void @llvm.R600.store.dummy(i32 2)
>  ret void
>}
>
>declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
>
>declare void @llvm.R600.store.dummy(i32)
>
>attributes #0 = { "ShaderType"="1" }
>
>===== SHADER #29 ==================================== VS/REDWOOD/EVERGREEN =====
>===== 44 dw ===== 4 gprs ===== 1 stack =========================================
>0000  00000000 84c00000 CALL_FS @0
>0002  80000006 a03c0000 ALU 16 @12 KC0[CB0:0-31]
> 0012  80002080 60000110     1      w: MUL_IEEE           R0.w,  KC0[0].x, R1.x
> 0014  00802081 60030cfe     2      w: MULADD_IEEE        R0.w,  KC0[1].x, R1.y, PV.w
> 0016  80002480 60400110            t: MUL_IEEE           R2.w,  KC0[0].y, R1.x
> 0018  81002082 60030cfe     3      w: MULADD_IEEE        R0.w,  KC0[2].x, R1.z, PV.w
> 0020  01802083 00030cfe     4      x: MULADD_IEEE        R0.x,  KC0[3].x, R1.w, PV.w
> 0022  80802481 60430c02            w: MULADD_IEEE        R2.w,  KC0[1].y, R1.y, R2.w
> 0024  80002880 60600110     5      w: MUL_IEEE           R3.w,  KC0[0].z, R1.x
> 0026  00802881 40430cfe     6      z: MULADD_IEEE        R2.z,  KC0[1].z, R1.y, PV.w
> 0028  80002c80 60600110            w: MUL_IEEE           R3.w,  KC0[0].w, R1.x
> 0030  81002482 60430c02     7      w: MULADD_IEEE        R2.w,  KC0[2].y, R1.z, R2.w
> 0032  01802483 20030cfe     8      y: MULADD_IEEE        R0.y,  KC0[3].y, R1.w, PV.w
> 0034  80802c81 60430c03            w: MULADD_IEEE        R2.w,  KC0[1].w, R1.y, R3.w
> 0036  81002882 60630802     9      w: MULADD_IEEE        R3.w,  KC0[2].z, R1.z, R2.z
> 0038  01802883 40030cfe    10      z: MULADD_IEEE        R0.z,  KC0[3].z, R1.w, PV.w
> 0040  81002c82 60430c02            w: MULADD_IEEE        R2.w,  KC0[2].w, R1.z, R2.w
> 0042  81802c83 60030cfe    11      w: MULADD_IEEE        R0.w,  KC0[3].w, R1.w, PV.w
>0004  c000203c 95000688 EXPORT_DONE        POS   60    R0.xyzw
>0006  c0004000 95200fff EXPORT_DONE        PARAM 0     R0.____  EOP
>===== SHADER_END ===============================================================
>
>
>===== SHADER #29 OPT ================================ VS/REDWOOD/EVERGREEN =====
>===== 40 dw ===== 2 gprs ===== 1 stack =========================================
>0000  00000000 84c00000 CALL_FS @0
>0002  40000004 a03c0000 ALU 16 @8 KC0[CB0:0-15]
> 0008  00002c80 0f800110     1      x: MUL_IEEE           T0.x,  KC0[0].w, R1.x
> 0010  80002880 2f800110            y: MUL_IEEE           T0.y,  KC0[0].z, R1.x
> 0012  00802c81 0f83007c     2      x: MULADD_IEEE        T0.x,  KC0[1].w, R1.y, T0.x
> 0014  00802881 2f83047c            y: MULADD_IEEE        T0.y,  KC0[1].z, R1.y, T0.y
> 0016  00002480 4f800110            z: MUL_IEEE           T0.z,  KC0[0].y, R1.x
> 0018  80002080 6f800110            w: MUL_IEEE           T0.w,  KC0[0].x, R1.x
> 0020  01002c82 0fa3007c     3      x: MULADD_IEEE        T1.x,  KC0[2].w, R1.z, T0.x
> 0022  00802481 4f83087c            z: MULADD_IEEE        T0.z,  KC0[1].y, R1.y, T0.z
> 0024  80802081 6f830c7c            w: MULADD_IEEE        T0.w,  KC0[1].x, R1.y, T0.w
> 0026  01002482 0f83087c     4      x: MULADD_IEEE        T0.x,  KC0[2].y, R1.z, T0.z
> 0028  01002082 2f830c7c            y: MULADD_IEEE        T0.y,  KC0[2].x, R1.z, T0.w
> 0030  81002882 2fab047c            t: MULADD_IEEE        T1.y,  KC0[2].z, R1.z, T0.y   SCL_212
> 0032  01802083 0003047c     5      x: MULADD_IEEE        R0.x,  KC0[3].x, R1.w, T0.y
> 0034  01802483 2003007c            y: MULADD_IEEE        R0.y,  KC0[3].y, R1.w, T0.x
> 0036  01802883 4007047d            z: MULADD_IEEE        R0.z,  KC0[3].z, R1.w, T1.y   VEC_021
> 0038  81802c83 6007007d            w: MULADD_IEEE        R0.w,  KC0[3].w, R1.w, T1.x   VEC_021
>0004  c000203c 95000688 EXPORT_DONE        POS   60    R0.xyzw
>0006  c0004000 95200fff EXPORT_DONE        PARAM 0     R0.____  EOP
>===== SHADER_END ===============================================================
>
>--------------------------------------------------------------
>FRAG
>DCL IN[0], GENERIC[9], PERSPECTIVE
>DCL IN[1], GENERIC[10], PERSPECTIVE
>DCL IN[2], GENERIC[11], PERSPECTIVE
>DCL IN[3], GENERIC[12], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SAMP[1]
>DCL SAMP[2]
>DCL SAMP[3]
>DCL SVIEW[0], 2D, FLOAT
>DCL SVIEW[1], 2D, FLOAT
>DCL SVIEW[2], 2D, FLOAT
>DCL SVIEW[3], 2D, FLOAT
>DCL CONST[4..6]
>DCL TEMP[0..5], LOCAL
>IMM[0] FLT32 {   -0.5000,     2.0000,    -1.0000,     0.0000}
>IMM[1] FLT32 {    0.2500,     0.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].xy, IN[0].xyyy
>  1: TEX TEMP[0], TEMP[0], SAMP[1], 2D
>  2: MUL TEMP[1].x, TEMP[0].wwww, CONST[6].xxxx
>  3: MOV TEMP[1].w, TEMP[1].xxxx
>  4: MOV TEMP[2].xy, IN[0].xyyy
>  5: TEX TEMP[2].xyz, TEMP[2], SAMP[0], 2D
>  6: ADD TEMP[2].xyz, TEMP[2].xyzz, IMM[0].xxxx
>  7: MOV TEMP[3].xy, IN[0].zwww
>  8: TEX TEMP[3].xyz, TEMP[3], SAMP[3], 2D
>  9: MAD TEMP[3].xyz, TEMP[3].xyzz, IMM[0].yyyy, IMM[0].zzzz
> 10: DP3 TEMP[4].x, TEMP[3].xyzz, IN[2].xyzz
> 11: DP3 TEMP[5].x, TEMP[3].xyzz, IN[3].xyzz
> 12: MOV TEMP[4].y, TEMP[5].xxxx
> 13: DP3 TEMP[3].x, TEMP[3].xyzz, IN[1].xyzz
> 14: MOV TEMP[4].z, TEMP[3].xxxx
> 15: DP3 TEMP[3].x, TEMP[4].xyzz, TEMP[4].xyzz
> 16: RSQ TEMP[3].x, TEMP[3].xxxx
> 17: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[3].xxxx
> 18: DP3 TEMP[4].x, TEMP[2].xyzz, TEMP[2].xyzz
> 19: RSQ TEMP[4].x, TEMP[4].xxxx
> 20: MUL TEMP[2].xyz, TEMP[2].xyzz, TEMP[4].xxxx
> 21: DP3 TEMP[2].x, TEMP[2].xyzz, TEMP[3].xyzz
> 22: MAX TEMP[2].x, TEMP[2].xxxx, IMM[0].wwww
> 23: MUL TEMP[2].xyz, CONST[5].xyzz, TEMP[2].xxxx
> 24: MOV TEMP[4].xy, IN[0].zwww
> 25: TEX TEMP[4].xyz, TEMP[4], SAMP[2], 2D
> 26: MAX TEMP[3].x, IMM[1].xxxx, TEMP[3].zzzz
> 27: RCP TEMP[3].x, TEMP[3].xxxx
> 28: MUL TEMP[3].xyz, TEMP[4].xyzz, TEMP[3].xxxx
> 29: MAD TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xyzz, CONST[4].xyzz
> 30: MUL TEMP[1].xyz, TEMP[0].xyzz, TEMP[2].xyzz
> 31: MOV OUT[0], TEMP[1]
> 32: END
>; ModuleID = 'tgsi'
>
>define void @main(<4 x float> inreg, <4 x float> inreg, <4 x float> inreg, <4 x float> inreg, <4 x float> inreg) #0 {
>main_body:
>  %5 = extractelement <4 x float> %0, i32 0
>  %6 = extractelement <4 x float> %0, i32 1
>  %7 = call <2 x float> @llvm.R600.interp.xy(i32 0, float %5, float %6)
>  %8 = call <2 x float> @llvm.R600.interp.zw(i32 0, float %5, float %6)
>  %9 = extractelement <4 x float> %0, i32 0
>  %10 = extractelement <4 x float> %0, i32 1
>  %11 = call <2 x float> @llvm.R600.interp.xy(i32 1, float %9, float %10)
>  %12 = call <2 x float> @llvm.R600.interp.zw(i32 1, float %9, float %10)
>  %13 = extractelement <2 x float> %11, i32 0
>  %14 = extractelement <2 x float> %11, i32 1
>  %15 = extractelement <2 x float> %12, i32 0
>  %16 = extractelement <4 x float> %0, i32 0
>  %17 = extractelement <4 x float> %0, i32 1
>  %18 = call <2 x float> @llvm.R600.interp.xy(i32 2, float %16, float %17)
>  %19 = call <2 x float> @llvm.R600.interp.zw(i32 2, float %16, float %17)
>  %20 = extractelement <2 x float> %18, i32 0
>  %21 = extractelement <2 x float> %18, i32 1
>  %22 = extractelement <2 x float> %19, i32 0
>  %23 = extractelement <4 x float> %0, i32 0
>  %24 = extractelement <4 x float> %0, i32 1
>  %25 = call <2 x float> @llvm.R600.interp.xy(i32 3, float %23, float %24)
>  %26 = call <2 x float> @llvm.R600.interp.zw(i32 3, float %23, float %24)
>  %27 = extractelement <2 x float> %25, i32 0
>  %28 = extractelement <2 x float> %25, i32 1
>  %29 = extractelement <2 x float> %26, i32 0
>  %30 = shufflevector <2 x float> %7, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
>  %31 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %30, i32 17, i32 1, i32 2)
>  %32 = extractelement <4 x float> %31, i32 0
>  %33 = extractelement <4 x float> %31, i32 1
>  %34 = extractelement <4 x float> %31, i32 2
>  %35 = extractelement <4 x float> %31, i32 3
>  %36 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6)
>  %37 = extractelement <4 x float> %36, i32 0
>  %38 = fmul float %35, %37
>  %39 = shufflevector <2 x float> %7, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
>  %40 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %39, i32 16, i32 0, i32 2)
>  %41 = extractelement <4 x float> %40, i32 0
>  %42 = extractelement <4 x float> %40, i32 1
>  %43 = extractelement <4 x float> %40, i32 2
>  %44 = fadd float %41, -5.000000e-01
>  %45 = fadd float %42, -5.000000e-01
>  %46 = fadd float %43, -5.000000e-01
>  %47 = shufflevector <2 x float> %8, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
>  %48 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %47, i32 19, i32 3, i32 2)
>  %49 = extractelement <4 x float> %48, i32 0
>  %50 = extractelement <4 x float> %48, i32 1
>  %51 = extractelement <4 x float> %48, i32 2
>  %52 = fmul float %49, 2.000000e+00
>  %53 = fadd float %52, -1.000000e+00
>  %54 = fmul float %50, 2.000000e+00
>  %55 = fadd float %54, -1.000000e+00
>  %56 = fmul float %51, 2.000000e+00
>  %57 = fadd float %56, -1.000000e+00
>  %58 = insertelement <4 x float> undef, float %53, i32 0
>  %59 = insertelement <4 x float> %58, float %55, i32 1
>  %60 = insertelement <4 x float> %59, float %57, i32 2
>  %61 = insertelement <4 x float> %60, float 0.000000e+00, i32 3
>  %62 = insertelement <4 x float> undef, float %20, i32 0
>  %63 = insertelement <4 x float> %62, float %21, i32 1
>  %64 = insertelement <4 x float> %63, float %22, i32 2
>  %65 = insertelement <4 x float> %64, float 0.000000e+00, i32 3
>  %66 = call float @llvm.AMDGPU.dp4(<4 x float> %61, <4 x float> %65)
>  %67 = insertelement <4 x float> undef, float %53, i32 0
>  %68 = insertelement <4 x float> %67, float %55, i32 1
>  %69 = insertelement <4 x float> %68, float %57, i32 2
>  %70 = insertelement <4 x float> %69, float 0.000000e+00, i32 3
>  %71 = insertelement <4 x float> undef, float %27, i32 0
>  %72 = insertelement <4 x float> %71, float %28, i32 1
>  %73 = insertelement <4 x float> %72, float %29, i32 2
>  %74 = insertelement <4 x float> %73, float 0.000000e+00, i32 3
>  %75 = call float @llvm.AMDGPU.dp4(<4 x float> %70, <4 x float> %74)
>  %76 = insertelement <4 x float> undef, float %53, i32 0
>  %77 = insertelement <4 x float> %76, float %55, i32 1
>  %78 = insertelement <4 x float> %77, float %57, i32 2
>  %79 = insertelement <4 x float> %78, float 0.000000e+00, i32 3
>  %80 = insertelement <4 x float> undef, float %13, i32 0
>  %81 = insertelement <4 x float> %80, float %14, i32 1
>  %82 = insertelement <4 x float> %81, float %15, i32 2
>  %83 = insertelement <4 x float> %82, float 0.000000e+00, i32 3
>  %84 = call float @llvm.AMDGPU.dp4(<4 x float> %79, <4 x float> %83)
>  %85 = insertelement <4 x float> undef, float %66, i32 0
>  %86 = insertelement <4 x float> %85, float %75, i32 1
>  %87 = insertelement <4 x float> %86, float %84, i32 2
>  %88 = insertelement <4 x float> %87, float 0.000000e+00, i32 3
>  %89 = insertelement <4 x float> undef, float %66, i32 0
>  %90 = insertelement <4 x float> %89, float %75, i32 1
>  %91 = insertelement <4 x float> %90, float %84, i32 2
>  %92 = insertelement <4 x float> %91, float 0.000000e+00, i32 3
>  %93 = call float @llvm.AMDGPU.dp4(<4 x float> %88, <4 x float> %92)
>  %94 = call float @llvm.AMDGPU.rsq.clamped.f32(float %93)
>  %95 = fmul float %66, %94
>  %96 = fmul float %75, %94
>  %97 = fmul float %84, %94
>  %98 = insertelement <4 x float> undef, float %44, i32 0
>  %99 = insertelement <4 x float> %98, float %45, i32 1
>  %100 = insertelement <4 x float> %99, float %46, i32 2
>  %101 = insertelement <4 x float> %100, float 0.000000e+00, i32 3
>  %102 = insertelement <4 x float> undef, float %44, i32 0
>  %103 = insertelement <4 x float> %102, float %45, i32 1
>  %104 = insertelement <4 x float> %103, float %46, i32 2
>  %105 = insertelement <4 x float> %104, float 0.000000e+00, i32 3
>  %106 = call float @llvm.AMDGPU.dp4(<4 x float> %101, <4 x float> %105)
>  %107 = call float @llvm.AMDGPU.rsq.clamped.f32(float %106)
>  %108 = fmul float %44, %107
>  %109 = fmul float %45, %107
>  %110 = fmul float %46, %107
>  %111 = insertelement <4 x float> undef, float %108, i32 0
>  %112 = insertelement <4 x float> %111, float %109, i32 1
>  %113 = insertelement <4 x float> %112, float %110, i32 2
>  %114 = insertelement <4 x float> %113, float 0.000000e+00, i32 3
>  %115 = insertelement <4 x float> undef, float %95, i32 0
>  %116 = insertelement <4 x float> %115, float %96, i32 1
>  %117 = insertelement <4 x float> %116, float %97, i32 2
>  %118 = insertelement <4 x float> %117, float 0.000000e+00, i32 3
>  %119 = call float @llvm.AMDGPU.dp4(<4 x float> %114, <4 x float> %118)
>  %.inv = fcmp olt float %119, 0.000000e+00
>  %120 = select i1 %.inv, float 0.000000e+00, float %119
>  %121 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5)
>  %122 = extractelement <4 x float> %121, i32 0
>  %123 = fmul float %122, %120
>  %124 = extractelement <4 x float> %121, i32 1
>  %125 = fmul float %124, %120
>  %126 = extractelement <4 x float> %121, i32 2
>  %127 = fmul float %126, %120
>  %128 = shufflevector <2 x float> %8, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
>  %129 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %128, i32 18, i32 2, i32 2)
>  %130 = extractelement <4 x float> %129, i32 0
>  %131 = extractelement <4 x float> %129, i32 1
>  %132 = extractelement <4 x float> %129, i32 2
>  %.inv24 = fcmp ogt float %97, 2.500000e-01
>  %.op = fdiv float 1.000000e+00, %97
>  %133 = select i1 %.inv24, float %.op, float 4.000000e+00
>  %134 = fmul float %130, %133
>  %135 = fmul float %131, %133
>  %136 = fmul float %132, %133
>  %137 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4)
>  %138 = extractelement <4 x float> %137, i32 0
>  %139 = fmul float %123, %134
>  %140 = fadd float %139, %138
>  %141 = extractelement <4 x float> %137, i32 1
>  %142 = fmul float %125, %135
>  %143 = fadd float %142, %141
>  %144 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4)
>  %145 = extractelement <4 x float> %144, i32 2
>  %146 = fmul float %127, %136
>  %147 = fadd float %146, %145
>  %148 = fmul float %32, %140
>  %149 = fmul float %33, %143
>  %150 = fmul float %34, %147
>  %151 = insertelement <4 x float> undef, float %148, i32 0
>  %152 = insertelement <4 x float> %151, float %149, i32 1
>  %153 = insertelement <4 x float> %152, float %150, i32 2
>  %154 = insertelement <4 x float> %153, float %38, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %154, i32 0, i32 0)
>  ret void
>}
>
>; Function Attrs: readnone
>declare <2 x float> @llvm.R600.interp.xy(i32, float, float) #1
>
>; Function Attrs: readnone
>declare <2 x float> @llvm.R600.interp.zw(i32, float, float) #1
>
>; Function Attrs: readnone
>declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.AMDGPU.rsq.clamped.f32(float) #2
>
>declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { readnone }
>attributes #2 = { nounwind readnone }
>
>===== SHADER #31 ==================================== PS/REDWOOD/EVERGREEN =====
>===== 220 dw ===== 8 gprs ===== 0 stack ========================================
>0000  0000000e a0240000 ALU 10 @28
> 0028  00380400 00346b10     1      x: INTERP_XY          R1.x,  R0.y, Param0.x         VEC_210
> 0030  00380000 20346b10            y: INTERP_XY          R1.y,  R0.x, Param0.x         VEC_210
> 0032  00380400 40146b00            z: INTERP_XY          __.z,  R0.y, Param0.x         VEC_210
> 0034  80380000 60146b00            w: INTERP_XY          __.w,  R0.x, Param0.x         VEC_210
> 0036  00380400 00146b80     2      x: INTERP_ZW          __.x,  R0.y, Param0.x         VEC_210
> 0038  00380000 20146b80            y: INTERP_ZW          __.y,  R0.x, Param0.x         VEC_210
> 0040  00380400 40546b90            z: INTERP_ZW          R2.z,  R0.y, Param0.x         VEC_210
> 0042  80380000 60546b90            w: INTERP_ZW          R2.w,  R0.x, Param0.x         VEC_210
> 0044  000008fe 00600c90     3      x: MOV                R3.x,  PV.z
> 0046  80000cfe 20600c90            y: MOV                R3.y,  PV.w
>0002  00000006 80400c00 TEX 4 @12
> 0012  00011110 f00d1002 fc808000 SAMPLE              R2.xyzw, R1.xy__,   RID:17, SID:1 CT:NNNN
> 0016  00031210 f00d1004 fc810000 SAMPLE              R4.xyzw, R3.xy__,   RID:18, SID:2 CT:NNNN
> 0020  00011010 f00d1001 fc800000 SAMPLE              R1.xyzw, R1.xy__,   RID:16, SID:0 CT:NNNN
> 0024  00031310 f00d1003 fc818000 SAMPLE              R3.xyzw, R3.xy__,   RID:19, SID:3 CT:NNNN
>0004  80000018 a1540000 ALU 86 @48 KC0[CB0:0-31]
> 0048  81006803 60a00010     4      w: ADD                R5.w,  R3.z, R3.z
> 0050  001fa001 00a00010     5      x: ADD                R5.x,  R1.x, [0xbf000000 -0.5].x
> 0052  001fa401 20a00010            y: ADD                R5.y,  R1.y, [0xbf000000 -0.5].x
> 0054  001fa801 40200010            z: ADD                R1.z,  R1.z, [0xbf000000 -0.5].x
> 0056  00806403 60280010            w: ADD                R1.w,  R3.y, R3.y             VEC_120
> 0058  80006003 60600010            t: ADD                R3.w,  R3.x, R3.x
> 0060  bf000000 
> 0062  001fa0ff 00200010     6      x: ADD                R1.x,  PS, [0xbf800000 -1].x
> 0064  001facfe 20200010            y: ADD                R1.y,  PV.w, [0xbf800000 -1].x
> 0066  801fac05 40600010            z: ADD                R3.z,  R5.w, [0xbf800000 -1].x
> 0068  bf800000 
> 0070  00382400 00746b10     7      x: INTERP_XY          R3.x,  R0.y, Param1.x         VEC_210
> 0072  00382000 20746b10            y: INTERP_XY          R3.y,  R0.x, Param1.x         VEC_210
> 0074  00382400 40146b00            z: INTERP_XY          __.z,  R0.y, Param1.x         VEC_210
> 0076  80382000 60146b00            w: INTERP_XY          __.w,  R0.x, Param1.x         VEC_210
> 0078  00382400 00146b80     8      x: INTERP_ZW          __.x,  R0.y, Param1.x         VEC_210
> 0080  00382000 20146b80            y: INTERP_ZW          __.y,  R0.x, Param1.x         VEC_210
> 0082  00382400 40b46b90            z: INTERP_ZW          R5.z,  R0.y, Param1.x         VEC_210
> 0084  80382000 60346b90            w: INTERP_ZW          R1.w,  R0.x, Param1.x         VEC_210
> 0086  00384400 00d46b10     9      x: INTERP_XY          R6.x,  R0.y, Param2.x         VEC_210
> 0088  00384000 20d46b10            y: INTERP_XY          R6.y,  R0.x, Param2.x         VEC_210
> 0090  00384400 40146b00            z: INTERP_XY          __.z,  R0.y, Param2.x         VEC_210
> 0092  80384000 60146b00            w: INTERP_XY          __.w,  R0.x, Param2.x         VEC_210
> 0094  00384400 00146b80    10      x: INTERP_ZW          __.x,  R0.y, Param2.x         VEC_210
> 0096  00384000 20146b80            y: INTERP_ZW          __.y,  R0.x, Param2.x         VEC_210
> 0098  00384400 40d46b90            z: INTERP_ZW          R6.z,  R0.y, Param2.x         VEC_210
> 0100  80384000 60346b90            w: INTERP_ZW          R1.w,  R0.x, Param2.x         VEC_210
> 0102  0000c001 00c05f10    11      x: DOT4               R6.x,  R1.x, R6.x
> 0104  0080c401 20c05f00            y: DOT4               __.y,  R1.y, R6.y
> 0106  0100c803 40c05f00            z: DOT4               __.z,  R3.z, R6.z
> 0108  801f00f8 60c05f00            w: DOT4               __.w,  0, 0
> 0110  00386400 00f46b10    12      x: INTERP_XY          R7.x,  R0.y, Param3.x         VEC_210
> 0112  00386000 20d46b10            y: INTERP_XY          R6.y,  R0.x, Param3.x         VEC_210
> 0114  00386400 40146b00            z: INTERP_XY          __.z,  R0.y, Param3.x         VEC_210
> 0116  80386000 60146b00            w: INTERP_XY          __.w,  R0.x, Param3.x         VEC_210
> 0118  00386400 00146b80    13      x: INTERP_ZW          __.x,  R0.y, Param3.x         VEC_210
> 0120  00386000 20146b80            y: INTERP_ZW          __.y,  R0.x, Param3.x         VEC_210
> 0122  00386400 40146b90            z: INTERP_ZW          R0.z,  R0.y, Param3.x         VEC_210
> 0124  80386000 60146b90            w: INTERP_ZW          R0.w,  R0.x, Param3.x         VEC_210
> 0126  0000e001 00005f00    14      x: DOT4               __.x,  R1.x, R7.x
> 0128  0080c401 20005f10            y: DOT4               R0.y,  R1.y, R6.y
> 0130  01000803 40005f00            z: DOT4               __.z,  R3.z, R0.z
> 0132  801f00f8 60005f00            w: DOT4               __.w,  0, 0
> 0134  00006001 00005f00    15      x: DOT4               __.x,  R1.x, R3.x
> 0136  00806401 20005f00            y: DOT4               __.y,  R1.y, R3.y
> 0138  0100a803 40005f10            z: DOT4               R0.z,  R3.z, R5.z
> 0140  801f00f8 60005f00            w: DOT4               __.w,  0, 0
> 0142  0000a005 00005f10    16      x: DOT4               R0.x,  R5.x, R5.x
> 0144  0080a405 20005f00            y: DOT4               __.y,  R5.y, R5.y
> 0146  01002801 40005f00            z: DOT4               __.z,  R1.z, R1.z
> 0148  801f00f8 60005f00            w: DOT4               __.w,  0, 0
> 0150  800000fe 00004390    17      t: RECIPSQRT_CLAMPED  R0.x,  PV.x
> 0152  0000c006 00005f00    18      x: DOT4               __.x,  R6.x, R6.x
> 0154  00800400 20005f00            y: DOT4               __.y,  R0.y, R0.y
> 0156  01000800 40005f00            z: DOT4               __.z,  R0.z, R0.z
> 0158  801f00f8 60005f10            w: DOT4               R0.w,  0, 0
> 0160  800000fe 60004390    19      t: RECIPSQRT_CLAMPED  R0.w,  PV.x
> 0162  001fe006 00200110    20      x: MUL_IEEE           R1.x,  R6.x, PS
> 0164  00000405 20200110            y: MUL_IEEE           R1.y,  R5.y, R0.x
> 0166  001fe800 40000110            z: MUL_IEEE           R0.z,  R0.z, PS
> 0168  80000005 00600110            t: MUL_IEEE           R3.x,  R5.x, R0.x
> 0170  01800400 20000110    21      y: MUL_IEEE           R0.y,  R0.y, R0.w
> 0172  00000801 40200110            z: MUL_IEEE           R1.z,  R1.z, R0.x
> 0174  001fa8fe 60000490            w: SETGT              R0.w,  PV.z, [0x3e800000 0.25].x
> 0176  800008fe 00004310            t: RECIP_IEEE         R0.x,  PV.z
> 0178  3e800000 
> 0180  00002003 00005f00    22      x: DOT4               __.x,  R3.x, R1.x
> 0182  00800401 20005f10            y: DOT4               R0.y,  R1.y, R0.y
> 0184  01000801 40005f00            z: DOT4               __.z,  R1.z, R0.z
> 0186  801f00f8 60005f00            w: DOT4               __.w,  0, 0
> 0188  001fac00 60032000    23      w: CNDE               R0.w,  R0.w, [0x40800000 4].x, R0.x
> 0190  801fc0f8 60200190            t: MAX                R1.w,  0, PV.x
> 0192  40800000 
> 0194  001fe085 60600110    24      w: MUL_IEEE           R3.w,  KC0[5].x, PS
> 0196  819fc004 60a00110            t: MUL_IEEE           R5.w,  R4.x, PV.w
> 0198  01802485 20000110    25      y: MUL_IEEE           R0.y,  KC0[5].y, R1.w
> 0200  01800404 40040110            z: MUL_IEEE           R0.z,  R4.y, R0.w             VEC_021
> 0202  801fecfe 60630084            w: MULADD_IEEE        R3.w,  PV.w, PS, KC0[4].x
> 0204  8010cc02 60a00110    26      w: MUL_IEEE           R5.w,  R2.w, KC0[6].x
> 0206  01806002 00a00110    27      x: MUL_IEEE           R5.x,  R2.x, R3.w
> 0208  01802885 40240110            z: MUL_IEEE           R1.z,  KC0[5].z, R1.w         VEC_021
> 0210  01800804 60100110            w: MUL_IEEE           R0.w,  R4.z, R0.w             VEC_201
> 0212  81000400 60230484            t: MULADD_IEEE        R1.w,  R0.y, R0.z, KC0[4].y
> 0214  001fe402 20a00110    28      y: MUL_IEEE           R5.y,  R2.y, PS
> 0216  819fc8fe 60030884            w: MULADD_IEEE        R0.w,  PV.z, PV.w, KC0[4].z
> 0218  819fc802 40a00110    29      z: MUL_IEEE           R5.z,  R2.z, PV.w
>0006  c0028000 95200688 EXPORT_DONE        PIXEL 0     R5.xyzw  EOP
>===== SHADER_END ===============================================================
>
>
>===== SHADER #31 OPT ================================ PS/REDWOOD/EVERGREEN =====
>===== 210 dw ===== 5 gprs ===== 0 stack ========================================
>0000  00000004 a01c0000 ALU 8 @8
> 0008  00380400 00346b10     1      x: INTERP_XY          R1.x,  R0.y, Param0.x         VEC_210
> 0010  00b80000 20346b10            y: INTERP_XY          R1.y,  R0.x, Param0.y         VEC_210
> 0012  01380400 40146b00            z: INTERP_XY          __.z,  R0.y, Param0.z         VEC_210
> 0014  81b80000 60146b00            w: INTERP_XY          __.w,  R0.x, Param0.w         VEC_210
> 0016  00380400 00146b80     2      x: INTERP_ZW          __.x,  R0.y, Param0.x         VEC_210
> 0018  00b80000 20146b80            y: INTERP_ZW          __.y,  R0.x, Param0.y         VEC_210
> 0020  01380400 40146b90            z: INTERP_ZW          R0.z,  R0.y, Param0.z         VEC_210
> 0022  81b80000 60146b90            w: INTERP_ZW          R0.w,  R0.x, Param0.w         VEC_210
>0002  0000000c 80400c00 TEX 4 @24
> 0024  00001310 f01d1002 fda18000 SAMPLE              R2.xyz_, R0.zw__,   RID:19, SID:3 CT:NNNN
> 0028  00011010 f01d1003 fc800000 SAMPLE              R3.xyz_, R1.xy__,   RID:16, SID:0 CT:NNNN
> 0032  00001210 f01d1004 fda10000 SAMPLE              R4.xyz_, R0.zw__,   RID:18, SID:2 CT:NNNN
> 0036  00011110 f00d1001 fc808000 SAMPLE              R1.xyzw, R1.xy__,   RID:17, SID:1 CT:NNNN
>0004  40000014 a1500000 ALU 85 @40 KC0[CB0:0-15]
> 0040  00382400 00146b80     3      x: INTERP_ZW          __.x,  R0.y, Param1.x         VEC_210
> 0042  00b82000 20146b80            y: INTERP_ZW          __.y,  R0.x, Param1.y         VEC_210
> 0044  01382400 40146b90            z: INTERP_ZW          R0.z,  R0.y, Param1.z         VEC_210
> 0046  81b82000 60146b80            w: INTERP_ZW          __.w,  R0.x, Param1.w         VEC_210
> 0048  00382400 0fd46b10     4      x: INTERP_XY          T2.x,  R0.y, Param1.x         VEC_210
> 0050  00b82000 2fd46b10            y: INTERP_XY          T2.y,  R0.x, Param1.y         VEC_210
> 0052  01382400 40146b00            z: INTERP_XY          __.z,  R0.y, Param1.z         VEC_210
> 0054  81b82000 60146b00            w: INTERP_XY          __.w,  R0.x, Param1.w         VEC_210
> 0056  001fa002 4f8284fd     5      z: MULADD             T0.z,  R2.x, [0x40000000 2].x, [0xbf800000 -1].y
> 0058  801fa402 6f8284fd            w: MULADD             T0.w,  R2.y, [0x40000000 2].x, [0xbf800000 -1].y
> 0060  40000000 
> 0061  bf800000 
> 0062  00386400 00146b80     6      x: INTERP_ZW          __.x,  R0.y, Param3.x         VEC_210
> 0064  00b86000 20146b80            y: INTERP_ZW          __.y,  R0.x, Param3.y         VEC_210
> 0066  01386400 4ff46b90            z: INTERP_ZW          T3.z,  R0.y, Param3.z         VEC_210
> 0068  81b86000 60146b80            w: INTERP_ZW          __.w,  R0.x, Param3.w         VEC_210
> 0070  00386400 0fb46b10     7      x: INTERP_XY          T1.x,  R0.y, Param3.x         VEC_210
> 0072  00b86000 2fb46b10            y: INTERP_XY          T1.y,  R0.x, Param3.y         VEC_210
> 0074  01386400 40146b00            z: INTERP_XY          __.z,  R0.y, Param3.z         VEC_210
> 0076  81b86000 60146b00            w: INTERP_XY          __.w,  R0.x, Param3.w         VEC_210
> 0078  00384400 00146b80     8      x: INTERP_ZW          __.x,  R0.y, Param2.x         VEC_210
> 0080  00b84000 20146b80            y: INTERP_ZW          __.y,  R0.x, Param2.y         VEC_210
> 0082  01384400 4fd46b90            z: INTERP_ZW          T2.z,  R0.y, Param2.z         VEC_210
> 0084  81b84000 60146b80            w: INTERP_ZW          __.w,  R0.x, Param2.w         VEC_210
> 0086  00384400 0f946b10     9      x: INTERP_XY          T0.x,  R0.y, Param2.x         VEC_210
> 0088  00b84000 2f946b10            y: INTERP_XY          T0.y,  R0.x, Param2.y         VEC_210
> 0090  01384400 40146b00            z: INTERP_XY          __.z,  R0.y, Param2.z         VEC_210
> 0092  01b84000 60146b00            w: INTERP_XY          __.w,  R0.x, Param2.w         VEC_210
> 0094  801fa802 4fa284fd            t: MULADD             T1.z,  R2.z, [0x40000000 2].x, [0xbf800000 -1].y
> 0096  40000000 
> 0097  bf800000 
> 0098  000fc87c 0fc05f10    10      x: DOT4               T2.x,  T0.z, T2.x
> 0100  008fcc7c 20005f00            y: DOT4               __.y,  T0.w, T2.y
> 0102  0100087d 40085f00            z: DOT4               __.z,  T1.z, R0.z             VEC_120
> 0104  801f00f8 60005f00            w: DOT4               __.w,  0, 0
> 0106  000fa87c 00005f00    11      x: DOT4               __.x,  T0.z, T1.x
> 0108  008fac7c 2fc05f10            y: DOT4               T2.y,  T0.w, T1.y
> 0110  010fe87d 40085f00            z: DOT4               __.z,  T1.z, T3.z             VEC_120
> 0112  801f00f8 60005f00            w: DOT4               __.w,  0, 0
> 0114  000f887c 0fa05f10    12      x: DOT4               T1.x,  T0.z, T0.x
> 0116  008f8c7c 20005f00            y: DOT4               __.y,  T0.w, T0.y
> 0118  010fc87d 40085f00            z: DOT4               __.z,  T1.z, T2.z             VEC_120
> 0120  801f00f8 60005f00            w: DOT4               __.w,  0, 0
> 0122  001fa403 4fa00010    13      z: ADD                T1.z,  R3.y, [0xbf000000 -0.5].x
> 0124  801fa803 6fa00010            w: ADD                T1.w,  R3.z, [0xbf000000 -0.5].x
> 0126  bf000000 
> 0128  000fa07d 00005f00    14      x: DOT4               __.x,  T1.x, T1.x
> 0130  008fc47e 2f805f10            y: DOT4               T0.y,  T2.y, T2.y
> 0132  000fc07e 40085f00            z: DOT4               __.z,  T2.x, T2.x             VEC_120
> 0134  001f00f8 60005f00            w: DOT4               __.w,  0, 0
> 0136  801fa003 4f800010            t: ADD                T0.z,  R3.x, [0xbf000000 -0.5].x
> 0138  bf000000 
> 0140  010f887c 00005f00    15      x: DOT4               __.x,  T0.z, T0.z
> 0142  010fa87d 20085f00            y: DOT4               __.y,  T1.z, T1.z             VEC_120
> 0144  018fac7d 40005f00            z: DOT4               __.z,  T1.w, T1.w
> 0146  001f00f8 6f805f10            w: DOT4               T0.w,  0, 0
> 0148  8000047c 0f804390            t: RECIPSQRT_CLAMPED  T0.x,  T0.y
> 0150  80000c7c 6f804390    16      t: RECIPSQRT_CLAMPED  T0.w,  T0.w
> 0152  018f8c7d 0fa00110    17      x: MUL_IEEE           T1.x,  T1.w, T0.w
> 0154  000f807d 2f800110            y: MUL_IEEE           T0.y,  T1.x, T0.x
> 0156  800f807e 2fa00110            t: MUL_IEEE           T1.y,  T2.x, T0.x
> 0158  018f887c 0f800110    18      x: MUL_IEEE           T0.x,  T0.z, T0.w
> 0160  001fa47d 2fc00490            y: SETGT              T2.y,  T1.y, [0x3e800000 0.25].x
> 0162  018f887d 4f880110            z: MUL_IEEE           T0.z,  T1.z, T0.w             VEC_120
> 0164  000f847e 6f880110            w: MUL_IEEE           T0.w,  T2.y, T0.x             VEC_120
> 0166  8000047d 4fa04310            t: RECIP_IEEE         T1.z,  T1.y
> 0168  3e800000 
> 0170  008f807c 0f805f10    19      x: DOT4               T0.x,  T0.x, T0.y
> 0172  018f887c 20005f00            y: DOT4               __.y,  T0.z, T0.w
> 0174  008fa07d 400c5f00            z: DOT4               __.z,  T1.x, T1.y             VEC_102
> 0176  001f00f8 60005f00            w: DOT4               __.w,  0, 0
> 0178  801fa47e 2f8b287d            t: CNDE               T0.y,  T2.y, [0x40800000 4].x, T1.z  SCL_212
> 0180  40800000 
> 0182  001f007c 0f800190    20      x: MAX                T0.x,  T0.x, 0
> 0184  808f8404 2fa00110            y: MUL_IEEE           T1.y,  R4.y, T0.y
> 0186  000f8085 0f800110    21      x: MUL_IEEE           T0.x,  KC0[5].x, T0.x
> 0188  008f8004 2f800110            y: MUL_IEEE           T0.y,  R4.x, T0.y
> 0190  000f8885 4f800110            z: MUL_IEEE           T0.z,  KC0[5].z, T0.x
> 0192  008f8804 6f800110            w: MUL_IEEE           T0.w,  R4.z, T0.y
> 0194  800f8485 0fa00110            t: MUL_IEEE           T1.x,  KC0[5].y, T0.x
> 0196  008f807c 0f830084    22      x: MULADD_IEEE        T0.x,  T0.x, T0.y, KC0[4].x
> 0198  018f887c 4f830884            z: MULADD_IEEE        T0.z,  T0.z, T0.w, KC0[4].z
> 0200  808fa07d 0fa70484            t: MULADD_IEEE        T1.x,  T1.x, T1.y, KC0[4].y   SCL_122
> 0202  000f8001 00000110    23      x: MUL_IEEE           R0.x,  R1.x, T0.x
> 0204  000fa401 20040110            y: MUL_IEEE           R0.y,  R1.y, T1.x             VEC_021
> 0206  010f8801 40000110            z: MUL_IEEE           R0.z,  R1.z, T0.z
> 0208  8010cc01 60000110            w: MUL_IEEE           R0.w,  R1.w, KC0[6].x
>0006  c0000000 95200688 EXPORT_DONE        PIXEL 0     R0.xyzw  EOP
>===== SHADER_END ===============================================================
>
>--------------------------------------------------------------
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL IN[4]
>DCL IN[5]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[9]
>DCL OUT[2], GENERIC[10]
>DCL OUT[3], GENERIC[11]
>DCL OUT[4], GENERIC[12]
>DCL CONST[0..7]
>DCL TEMP[0..4], LOCAL
>IMM[0] FLT32 {    0.0000,     0.0000,     0.0000,     0.0000}
>  0: MUL TEMP[0], CONST[4], IN[1].xxxx
>  1: MAD TEMP[0], CONST[5], IN[1].yyyy, TEMP[0]
>  2: MAD TEMP[0], CONST[6], IN[1].zzzz, TEMP[0]
>  3: MAD TEMP[0].xy, CONST[7], IN[1].wwww, TEMP[0]
>  4: MOV TEMP[0].xy, TEMP[0].xyxx
>  5: MOV TEMP[0].zw, IN[5].yyxy
>  6: MOV TEMP[1].w, IMM[0].xxxx
>  7: MOV TEMP[1].xyz, IN[2].xyzx
>  8: MOV TEMP[2].w, IMM[0].xxxx
>  9: MOV TEMP[2].xyz, IN[3].xyzx
> 10: MOV TEMP[3].w, IMM[0].xxxx
> 11: MOV TEMP[3].xyz, IN[4].xyzx
> 12: MUL TEMP[4], CONST[0], IN[0].xxxx
> 13: MAD TEMP[4], CONST[1], IN[0].yyyy, TEMP[4]
> 14: MAD TEMP[4], CONST[2], IN[0].zzzz, TEMP[4]
> 15: MAD TEMP[4], CONST[3], IN[0].wwww, TEMP[4]
> 16: MOV OUT[2], TEMP[3]
> 17: MOV OUT[3], TEMP[1]
> 18: MOV OUT[0], TEMP[4]
> 19: MOV OUT[4], TEMP[2]
> 20: MOV OUT[1], TEMP[0]
> 21: END
>; ModuleID = 'tgsi'
>
>define void @main(<4 x float> inreg, <4 x float> inreg, <4 x float> inreg, <4 x float> inreg, <4 x float> inreg, <4 x float> inreg, <4 x float> inreg) #0 {
>main_body:
>  %7 = extractelement <4 x float> %1, i32 0
>  %8 = extractelement <4 x float> %1, i32 1
>  %9 = extractelement <4 x float> %1, i32 2
>  %10 = extractelement <4 x float> %1, i32 3
>  %11 = extractelement <4 x float> %2, i32 0
>  %12 = extractelement <4 x float> %2, i32 1
>  %13 = extractelement <4 x float> %2, i32 2
>  %14 = extractelement <4 x float> %2, i32 3
>  %15 = extractelement <4 x float> %3, i32 0
>  %16 = extractelement <4 x float> %3, i32 1
>  %17 = extractelement <4 x float> %3, i32 2
>  %18 = extractelement <4 x float> %4, i32 0
>  %19 = extractelement <4 x float> %4, i32 1
>  %20 = extractelement <4 x float> %4, i32 2
>  %21 = extractelement <4 x float> %5, i32 0
>  %22 = extractelement <4 x float> %5, i32 1
>  %23 = extractelement <4 x float> %5, i32 2
>  %24 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4)
>  %25 = extractelement <4 x float> %24, i32 0
>  %26 = fmul float %25, %11
>  %27 = extractelement <4 x float> %24, i32 1
>  %28 = fmul float %27, %11
>  %29 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5)
>  %30 = extractelement <4 x float> %29, i32 0
>  %31 = fmul float %30, %12
>  %32 = fadd float %31, %26
>  %33 = extractelement <4 x float> %29, i32 1
>  %34 = fmul float %33, %12
>  %35 = fadd float %34, %28
>  %36 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6)
>  %37 = extractelement <4 x float> %36, i32 0
>  %38 = fmul float %37, %13
>  %39 = fadd float %38, %32
>  %40 = extractelement <4 x float> %36, i32 1
>  %41 = fmul float %40, %13
>  %42 = fadd float %41, %35
>  %43 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7)
>  %44 = extractelement <4 x float> %43, i32 0
>  %45 = fmul float %44, %14
>  %46 = fadd float %45, %39
>  %47 = extractelement <4 x float> %43, i32 1
>  %48 = fmul float %47, %14
>  %49 = fadd float %48, %42
>  %50 = load <4 x float> addrspace(8)* null
>  %51 = extractelement <4 x float> %50, i32 0
>  %52 = fmul float %51, %7
>  %53 = extractelement <4 x float> %50, i32 1
>  %54 = fmul float %53, %7
>  %55 = extractelement <4 x float> %50, i32 2
>  %56 = fmul float %55, %7
>  %57 = load <4 x float> addrspace(8)* null
>  %58 = extractelement <4 x float> %57, i32 3
>  %59 = fmul float %58, %7
>  %60 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
>  %61 = extractelement <4 x float> %60, i32 0
>  %62 = fmul float %61, %8
>  %63 = fadd float %62, %52
>  %64 = extractelement <4 x float> %60, i32 1
>  %65 = fmul float %64, %8
>  %66 = fadd float %65, %54
>  %67 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
>  %68 = extractelement <4 x float> %67, i32 2
>  %69 = fmul float %68, %8
>  %70 = fadd float %69, %56
>  %71 = extractelement <4 x float> %67, i32 3
>  %72 = fmul float %71, %8
>  %73 = fadd float %72, %59
>  %74 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
>  %75 = extractelement <4 x float> %74, i32 0
>  %76 = fmul float %75, %9
>  %77 = fadd float %76, %63
>  %78 = extractelement <4 x float> %74, i32 1
>  %79 = fmul float %78, %9
>  %80 = fadd float %79, %66
>  %81 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
>  %82 = extractelement <4 x float> %81, i32 2
>  %83 = fmul float %82, %9
>  %84 = fadd float %83, %70
>  %85 = extractelement <4 x float> %81, i32 3
>  %86 = fmul float %85, %9
>  %87 = fadd float %86, %73
>  %88 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
>  %89 = extractelement <4 x float> %88, i32 0
>  %90 = fmul float %89, %10
>  %91 = fadd float %90, %77
>  %92 = extractelement <4 x float> %88, i32 1
>  %93 = fmul float %92, %10
>  %94 = fadd float %93, %80
>  %95 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
>  %96 = extractelement <4 x float> %95, i32 2
>  %97 = fmul float %96, %10
>  %98 = fadd float %97, %84
>  %99 = extractelement <4 x float> %95, i32 3
>  %100 = fmul float %99, %10
>  %101 = fadd float %100, %87
>  %102 = insertelement <4 x float> undef, float %91, i32 0
>  %103 = insertelement <4 x float> %102, float %94, i32 1
>  %104 = insertelement <4 x float> %103, float %98, i32 2
>  %105 = insertelement <4 x float> %104, float %101, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %105, i32 60, i32 1)
>  %106 = insertelement <4 x float> undef, float %46, i32 0
>  %107 = insertelement <4 x float> %106, float %49, i32 1
>  %108 = shufflevector <4 x float> %107, <4 x float> %6, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
>  call void @llvm.R600.store.swizzle(<4 x float> %108, i32 0, i32 2)
>  %109 = insertelement <4 x float> undef, float %21, i32 0
>  %110 = insertelement <4 x float> %109, float %22, i32 1
>  %111 = insertelement <4 x float> %110, float %23, i32 2
>  %112 = insertelement <4 x float> %111, float 0.000000e+00, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %112, i32 1, i32 2)
>  %113 = insertelement <4 x float> undef, float %15, i32 0
>  %114 = insertelement <4 x float> %113, float %16, i32 1
>  %115 = insertelement <4 x float> %114, float %17, i32 2
>  %116 = insertelement <4 x float> %115, float 0.000000e+00, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %116, i32 2, i32 2)
>  %117 = insertelement <4 x float> undef, float %18, i32 0
>  %118 = insertelement <4 x float> %117, float %19, i32 1
>  %119 = insertelement <4 x float> %118, float %20, i32 2
>  %120 = insertelement <4 x float> %119, float 0.000000e+00, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %120, i32 3, i32 2)
>  ret void
>}
>
>declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
>
>attributes #0 = { "ShaderType"="1" }
>
>===== SHADER #32 ==================================== VS/REDWOOD/EVERGREEN =====
>===== 64 dw ===== 9 gprs ===== 1 stack =========================================
>0000  00000000 84c00000 CALL_FS @0
>0002  80000008 a05c0000 ALU 24 @16 KC0[CB0:0-31]
> 0016  80002080 60000110     1      w: MUL_IEEE           R0.w,  KC0[0].x, R1.x
> 0018  00802081 60030cfe     2      w: MULADD_IEEE        R0.w,  KC0[1].x, R1.y, PV.w
> 0020  80002480 60e00110            t: MUL_IEEE           R7.w,  KC0[0].y, R1.x
> 0022  00802481 60e300ff     3      w: MULADD_IEEE        R7.w,  KC0[1].y, R1.y, PS
> 0024  81002082 60070cfe            t: MULADD_IEEE        R0.w,  KC0[2].x, R1.z, PV.w   SCL_122
> 0026  01802083 000300ff     4      x: MULADD_IEEE        R0.x,  KC0[3].x, R1.w, PS
> 0028  81002482 60e30cfe            w: MULADD_IEEE        R7.w,  KC0[2].y, R1.z, PV.w
> 0030  01802483 20030cfe     5      y: MULADD_IEEE        R0.y,  KC0[3].y, R1.w, PV.w
> 0032  80002880 60e00110            w: MUL_IEEE           R7.w,  KC0[0].z, R1.x
> 0034  00802881 40e30cfe     6      z: MULADD_IEEE        R7.z,  KC0[1].z, R1.y, PV.w
> 0036  00004084 60e00110            w: MUL_IEEE           R7.w,  KC0[4].x, R2.x
> 0038  80004484 61000110            t: MUL_IEEE           R8.w,  KC0[4].y, R2.x
> 0040  00804485 20e300ff     7      y: MULADD_IEEE        R7.y,  KC0[5].y, R2.y, PS
> 0042  00804085 41030cfe            z: MULADD_IEEE        R8.z,  KC0[5].x, R2.y, PV.w
> 0044  80002c80 60e00110            w: MUL_IEEE           R7.w,  KC0[0].w, R1.x
> 0046  81002882 61030807     8      w: MULADD_IEEE        R8.w,  KC0[2].z, R1.z, R7.z
> 0048  01802883 40030cfe     9      z: MULADD_IEEE        R0.z,  KC0[3].z, R1.w, PV.w
> 0050  80802c81 60e30c07            w: MULADD_IEEE        R7.w,  KC0[1].w, R1.y, R7.w
> 0052  81004086 61030808    10      w: MULADD_IEEE        R8.w,  KC0[6].x, R2.z, R8.z
> 0054  01804087 40c30cfe    11      z: MULADD_IEEE        R6.z,  KC0[7].x, R2.w, PV.w
> 0056  81002c82 60e30c07            w: MULADD_IEEE        R7.w,  KC0[2].w, R1.z, R7.w
> 0058  81004486 61030407    12      w: MULADD_IEEE        R8.w,  KC0[6].y, R2.z, R7.y
> 0060  01804487 60cf0cfe    13      w: MULADD_IEEE        R6.w,  KC0[7].y, R2.w, PV.w   VEC_102
> 0062  81802c83 600b0c07            t: MULADD_IEEE        R0.w,  KC0[3].w, R1.w, R7.w   SCL_212
>0004  c000203c 95000688 EXPORT_DONE        POS   60    R0.xyzw
>0006  c0034000 94c0021a EXPORT             PARAM 0     R6.zwxy
>0008  c002c001 94c00888 EXPORT             PARAM 1     R5.xyz0
>0010  c001c002 94c00888 EXPORT             PARAM 2     R3.xyz0
>0012  c0024003 95200888 EXPORT_DONE        PARAM 3     R4.xyz0  EOP
>===== SHADER_END ===============================================================
>
>
>===== SHADER #32 OPT ================================ VS/REDWOOD/EVERGREEN =====
>===== 62 dw ===== 7 gprs ===== 1 stack =========================================
>0000  00000000 84c00000 CALL_FS @0
>0002  40000007 a05c0000 ALU 24 @14 KC0[CB0:0-15]
> 0014  00004084 0fc00110     1      x: MUL_IEEE           T2.x,  KC0[4].x, R2.x
> 0016  00002880 2f840110            y: MUL_IEEE           T0.y,  KC0[0].z, R1.x         VEC_021
> 0018  80002c80 0f840110            t: MUL_IEEE           T0.x,  KC0[0].w, R1.x         SCL_122
> 0020  00802c81 0f83007c     2      x: MULADD_IEEE        T0.x,  KC0[1].w, R1.y, T0.x
> 0022  00802881 2fa3047c            y: MULADD_IEEE        T1.y,  KC0[1].z, R1.y, T0.y
> 0024  80004484 0fa00110            t: MUL_IEEE           T1.x,  KC0[4].y, R2.x
> 0026  00804085 2f83007e     3      y: MULADD_IEEE        T0.y,  KC0[5].x, R2.y, T2.x
> 0028  00002480 4f800110            z: MUL_IEEE           T0.z,  KC0[0].y, R1.x
> 0030  80002080 6f800110            w: MUL_IEEE           T0.w,  KC0[0].x, R1.x
> 0032  01002c82 0f83007c     4      x: MULADD_IEEE        T0.x,  KC0[2].w, R1.z, T0.x
> 0034  01002882 2fa7047d            y: MULADD_IEEE        T1.y,  KC0[2].z, R1.z, T1.y   VEC_021
> 0036  80804485 0faf007d            t: MULADD_IEEE        T1.x,  KC0[5].y, R2.y, T1.x   SCL_221
> 0038  01004486 0fa3007d     5      x: MULADD_IEEE        T1.x,  KC0[6].y, R2.z, T1.x
> 0040  01004086 2f83047c            y: MULADD_IEEE        T0.y,  KC0[6].x, R2.z, T0.y
> 0042  00802481 4f83087c            z: MULADD_IEEE        T0.z,  KC0[1].y, R1.y, T0.z
> 0044  80802081 6f830c7c            w: MULADD_IEEE        T0.w,  KC0[1].x, R1.y, T0.w
> 0046  01002482 0f87087c     6      x: MULADD_IEEE        T0.x,  KC0[2].y, R1.z, T0.z   VEC_021
> 0048  01802883 4003047d            z: MULADD_IEEE        R0.z,  KC0[3].z, R1.w, T1.y
> 0050  01802c83 6003007c            w: MULADD_IEEE        R0.w,  KC0[3].w, R1.w, T0.x
> 0052  81002082 4f870c7c            t: MULADD_IEEE        T0.z,  KC0[2].x, R1.z, T0.w   SCL_122
> 0054  01802083 0007087c     7      x: MULADD_IEEE        R0.x,  KC0[3].x, R1.w, T0.z   VEC_021
> 0056  01802483 2007007c            y: MULADD_IEEE        R0.y,  KC0[3].y, R1.w, T0.x   VEC_021
> 0058  01804087 40c3047c            z: MULADD_IEEE        R6.z,  KC0[7].x, R2.w, T0.y
> 0060  81804487 60c3007d            w: MULADD_IEEE        R6.w,  KC0[7].y, R2.w, T1.x
>0004  c0034000 94c0021a EXPORT             PARAM 0     R6.zwxy
>0006  c000203c 95000688 EXPORT_DONE        POS   60    R0.xyzw
>0008  c002c001 94c00888 EXPORT             PARAM 1     R5.xyz0
>0010  c0024003 94c00888 EXPORT             PARAM 3     R4.xyz0
>0012  c001c002 95200888 EXPORT_DONE        PARAM 2     R3.xyz0  EOP
>===== SHADER_END ===============================================================
>
>--------------------------------------------------------------
>FRAG
>DCL IN[0], GENERIC[9], PERSPECTIVE
>DCL IN[1], GENERIC[10], PERSPECTIVE
>DCL IN[2], GENERIC[11], PERSPECTIVE
>DCL IN[3], GENERIC[12], PERSPECTIVE
>DCL IN[4], GENERIC[13], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SAMP[1]
>DCL SAMP[2]
>DCL SAMP[3]
>DCL SAMP[4]
>DCL SAMP[5]
>DCL SVIEW[0], 2D, FLOAT
>DCL SVIEW[1], 2D, FLOAT
>DCL SVIEW[2], 2D, FLOAT
>DCL SVIEW[3], 2D, FLOAT
>DCL SVIEW[4], 2D, FLOAT
>DCL SVIEW[5], 2D, FLOAT
>DCL CONST[6..11]
>DCL TEMP[0..7], LOCAL
>IMM[0] FLT32 {   -0.5000,     2.0000,    -1.0000,     0.0000}
>IMM[1] FLT32 {    1.0000,     0.2500,     0.0000,     0.0000}
>  0: MOV TEMP[0].xy, IN[1].xyyy
>  1: TEX TEMP[0], TEMP[0], SAMP[1], 2D
>  2: MUL TEMP[1].x, TEMP[0].wwww, CONST[11].xxxx
>  3: MOV TEMP[1].w, TEMP[1].xxxx
>  4: MOV TEMP[2].xy, IN[1].xyyy
>  5: TEX TEMP[2].xyz, TEMP[2], SAMP[0], 2D
>  6: ADD TEMP[2].xyz, TEMP[2].xyzz, IMM[0].xxxx
>  7: DP3 TEMP[3].x, TEMP[2].xyzz, TEMP[2].xyzz
>  8: RSQ TEMP[3].x, TEMP[3].xxxx
>  9: MUL TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xxxx
> 10: MOV TEMP[3].xy, IN[1].xyyy
> 11: TEX TEMP[3], TEMP[3], SAMP[2], 2D
> 12: MOV TEMP[4].xy, IN[1].zwww
> 13: TEX TEMP[4].xyz, TEMP[4], SAMP[5], 2D
> 14: MAD TEMP[4].xyz, TEMP[4].xyzz, IMM[0].yyyy, IMM[0].zzzz
> 15: DP3 TEMP[5].x, TEMP[4].xyzz, IN[3].xyzz
> 16: DP3 TEMP[6].x, TEMP[4].xyzz, IN[4].xyzz
> 17: MOV TEMP[5].y, TEMP[6].xxxx
> 18: DP3 TEMP[4].x, TEMP[4].xyzz, IN[2].xyzz
> 19: MOV TEMP[5].z, TEMP[4].xxxx
> 20: DP3 TEMP[4].x, TEMP[5].xyzz, TEMP[5].xyzz
> 21: RSQ TEMP[4].x, TEMP[4].xxxx
> 22: MUL TEMP[4].xyz, TEMP[5].xyzz, TEMP[4].xxxx
> 23: MUL TEMP[5].xyz, TEMP[3].xyzz, CONST[8].xyzz
> 24: DP3 TEMP[6].x, TEMP[2].xyzz, TEMP[4].xyzz
> 25: MUL TEMP[6].xyz, TEMP[6].xxxx, TEMP[2].xyzz
> 26: MUL TEMP[6].xyz, IMM[0].yyyy, TEMP[6].xyzz
> 27: ADD TEMP[6].xyz, TEMP[4].xyzz, -TEMP[6].xyzz
> 28: DP3 TEMP[7].x, IN[0].xyzz, IN[0].xyzz
> 29: RSQ TEMP[7].x, TEMP[7].xxxx
> 30: MUL TEMP[7].xyz, IN[0].xyzz, TEMP[7].xxxx
> 31: DP3 TEMP[6].x, TEMP[6].xyzz, TEMP[7].xyzz
> 32: MAX TEMP[6].x, -TEMP[6].xxxx, IMM[0].wwww
> 33: MAD TEMP[3].x, CONST[9].xxxx, TEMP[3].wwww, IMM[1].xxxx
> 34: POW TEMP[3].x, TEMP[6].xxxx, TEMP[3].xxxx
> 35: MUL TEMP[6].xyz, TEMP[0].xyzz, CONST[7].xyzz
> 36: DP3 TEMP[2].x, TEMP[2].xyzz, TEMP[4].xyzz
> 37: MAX TEMP[2].x, TEMP[2].xxxx, IMM[0].wwww
> 38: MUL TEMP[2].xyz, TEMP[6].xyzz, TEMP[2].xxxx
> 39: MAD TEMP[2].xyz, TEMP[5].xyzz, TEMP[3].xxxx, TEMP[2].xyzz
> 40: MOV TEMP[3].xy, IN[1].zwww
> 41: TEX TEMP[3].xyz, TEMP[3], SAMP[4], 2D
> 42: MAX TEMP[4].x, IMM[1].yyyy, TEMP[4].zzzz
> 43: RCP TEMP[4].x, TEMP[4].xxxx
> 44: MUL TEMP[3].xyz, TEMP[3].xyzz, TEMP[4].xxxx
> 45: MUL TEMP[0].xyz, TEMP[0].xyzz, CONST[6].xyzz
> 46: MAD TEMP[1].xyz, TEMP[2].xyzz, TEMP[3].xyzz, TEMP[0].xyzz
> 47: MOV TEMP[0].xy, IN[1].xyyy
> 48: TEX TEMP[0].xyz, TEMP[0], SAMP[3], 2D
> 49: MAD TEMP[1].xyz, TEMP[0].xyzz, CONST[10].xyzz, TEMP[1].xyzz
> 50: MOV OUT[0], TEMP[1]
> 51: END
>; ModuleID = 'tgsi'
>
>define void @main(<4 x float> inreg, <4 x float> inreg, <4 x float> inreg, <4 x float> inreg, <4 x float> inreg, <4 x float> inreg) #0 {
>main_body:
>  %6 = extractelement <4 x float> %0, i32 0
>  %7 = extractelement <4 x float> %0, i32 1
>  %8 = call <2 x float> @llvm.R600.interp.xy(i32 0, float %6, float %7)
>  %9 = call <2 x float> @llvm.R600.interp.zw(i32 0, float %6, float %7)
>  %10 = extractelement <2 x float> %8, i32 0
>  %11 = extractelement <2 x float> %8, i32 1
>  %12 = extractelement <2 x float> %9, i32 0
>  %13 = extractelement <4 x float> %0, i32 0
>  %14 = extractelement <4 x float> %0, i32 1
>  %15 = call <2 x float> @llvm.R600.interp.xy(i32 1, float %13, float %14)
>  %16 = call <2 x float> @llvm.R600.interp.zw(i32 1, float %13, float %14)
>  %17 = extractelement <4 x float> %0, i32 0
>  %18 = extractelement <4 x float> %0, i32 1
>  %19 = call <2 x float> @llvm.R600.interp.xy(i32 2, float %17, float %18)
>  %20 = call <2 x float> @llvm.R600.interp.zw(i32 2, float %17, float %18)
>  %21 = extractelement <2 x float> %19, i32 0
>  %22 = extractelement <2 x float> %19, i32 1
>  %23 = extractelement <2 x float> %20, i32 0
>  %24 = extractelement <4 x float> %0, i32 0
>  %25 = extractelement <4 x float> %0, i32 1
>  %26 = call <2 x float> @llvm.R600.interp.xy(i32 3, float %24, float %25)
>  %27 = call <2 x float> @llvm.R600.interp.zw(i32 3, float %24, float %25)
>  %28 = extractelement <2 x float> %26, i32 0
>  %29 = extractelement <2 x float> %26, i32 1
>  %30 = extractelement <2 x float> %27, i32 0
>  %31 = extractelement <4 x float> %0, i32 0
>  %32 = extractelement <4 x float> %0, i32 1
>  %33 = call <2 x float> @llvm.R600.interp.xy(i32 4, float %31, float %32)
>  %34 = call <2 x float> @llvm.R600.interp.zw(i32 4, float %31, float %32)
>  %35 = extractelement <2 x float> %33, i32 0
>  %36 = extractelement <2 x float> %33, i32 1
>  %37 = extractelement <2 x float> %34, i32 0
>  %38 = shufflevector <2 x float> %15, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
>  %39 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %38, i32 17, i32 1, i32 2)
>  %40 = extractelement <4 x float> %39, i32 0
>  %41 = extractelement <4 x float> %39, i32 1
>  %42 = extractelement <4 x float> %39, i32 2
>  %43 = extractelement <4 x float> %39, i32 3
>  %44 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11)
>  %45 = extractelement <4 x float> %44, i32 0
>  %46 = fmul float %43, %45
>  %47 = shufflevector <2 x float> %15, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
>  %48 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %47, i32 16, i32 0, i32 2)
>  %49 = extractelement <4 x float> %48, i32 0
>  %50 = extractelement <4 x float> %48, i32 1
>  %51 = extractelement <4 x float> %48, i32 2
>  %52 = fadd float %49, -5.000000e-01
>  %53 = fadd float %50, -5.000000e-01
>  %54 = fadd float %51, -5.000000e-01
>  %55 = insertelement <4 x float> undef, float %52, i32 0
>  %56 = insertelement <4 x float> %55, float %53, i32 1
>  %57 = insertelement <4 x float> %56, float %54, i32 2
>  %58 = insertelement <4 x float> %57, float 0.000000e+00, i32 3
>  %59 = insertelement <4 x float> undef, float %52, i32 0
>  %60 = insertelement <4 x float> %59, float %53, i32 1
>  %61 = insertelement <4 x float> %60, float %54, i32 2
>  %62 = insertelement <4 x float> %61, float 0.000000e+00, i32 3
>  %63 = call float @llvm.AMDGPU.dp4(<4 x float> %58, <4 x float> %62)
>  %64 = call float @llvm.AMDGPU.rsq.clamped.f32(float %63)
>  %65 = fmul float %52, %64
>  %66 = fmul float %53, %64
>  %67 = fmul float %54, %64
>  %68 = shufflevector <2 x float> %15, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
>  %69 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %68, i32 18, i32 2, i32 2)
>  %70 = extractelement <4 x float> %69, i32 0
>  %71 = extractelement <4 x float> %69, i32 1
>  %72 = extractelement <4 x float> %69, i32 2
>  %73 = extractelement <4 x float> %69, i32 3
>  %74 = shufflevector <2 x float> %16, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
>  %75 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %74, i32 21, i32 5, i32 2)
>  %76 = extractelement <4 x float> %75, i32 0
>  %77 = extractelement <4 x float> %75, i32 1
>  %78 = extractelement <4 x float> %75, i32 2
>  %79 = fmul float %76, 2.000000e+00
>  %80 = fadd float %79, -1.000000e+00
>  %81 = fmul float %77, 2.000000e+00
>  %82 = fadd float %81, -1.000000e+00
>  %83 = fmul float %78, 2.000000e+00
>  %84 = fadd float %83, -1.000000e+00
>  %85 = insertelement <4 x float> undef, float %80, i32 0
>  %86 = insertelement <4 x float> %85, float %82, i32 1
>  %87 = insertelement <4 x float> %86, float %84, i32 2
>  %88 = insertelement <4 x float> %87, float 0.000000e+00, i32 3
>  %89 = insertelement <4 x float> undef, float %28, i32 0
>  %90 = insertelement <4 x float> %89, float %29, i32 1
>  %91 = insertelement <4 x float> %90, float %30, i32 2
>  %92 = insertelement <4 x float> %91, float 0.000000e+00, i32 3
>  %93 = call float @llvm.AMDGPU.dp4(<4 x float> %88, <4 x float> %92)
>  %94 = insertelement <4 x float> undef, float %80, i32 0
>  %95 = insertelement <4 x float> %94, float %82, i32 1
>  %96 = insertelement <4 x float> %95, float %84, i32 2
>  %97 = insertelement <4 x float> %96, float 0.000000e+00, i32 3
>  %98 = insertelement <4 x float> undef, float %35, i32 0
>  %99 = insertelement <4 x float> %98, float %36, i32 1
>  %100 = insertelement <4 x float> %99, float %37, i32 2
>  %101 = insertelement <4 x float> %100, float 0.000000e+00, i32 3
>  %102 = call float @llvm.AMDGPU.dp4(<4 x float> %97, <4 x float> %101)
>  %103 = insertelement <4 x float> undef, float %80, i32 0
>  %104 = insertelement <4 x float> %103, float %82, i32 1
>  %105 = insertelement <4 x float> %104, float %84, i32 2
>  %106 = insertelement <4 x float> %105, float 0.000000e+00, i32 3
>  %107 = insertelement <4 x float> undef, float %21, i32 0
>  %108 = insertelement <4 x float> %107, float %22, i32 1
>  %109 = insertelement <4 x float> %108, float %23, i32 2
>  %110 = insertelement <4 x float> %109, float 0.000000e+00, i32 3
>  %111 = call float @llvm.AMDGPU.dp4(<4 x float> %106, <4 x float> %110)
>  %112 = insertelement <4 x float> undef, float %93, i32 0
>  %113 = insertelement <4 x float> %112, float %102, i32 1
>  %114 = insertelement <4 x float> %113, float %111, i32 2
>  %115 = insertelement <4 x float> %114, float 0.000000e+00, i32 3
>  %116 = insertelement <4 x float> undef, float %93, i32 0
>  %117 = insertelement <4 x float> %116, float %102, i32 1
>  %118 = insertelement <4 x float> %117, float %111, i32 2
>  %119 = insertelement <4 x float> %118, float 0.000000e+00, i32 3
>  %120 = call float @llvm.AMDGPU.dp4(<4 x float> %115, <4 x float> %119)
>  %121 = call float @llvm.AMDGPU.rsq.clamped.f32(float %120)
>  %122 = fmul float %93, %121
>  %123 = fmul float %102, %121
>  %124 = fmul float %111, %121
>  %125 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8)
>  %126 = extractelement <4 x float> %125, i32 0
>  %127 = fmul float %70, %126
>  %128 = extractelement <4 x float> %125, i32 1
>  %129 = fmul float %71, %128
>  %130 = extractelement <4 x float> %125, i32 2
>  %131 = fmul float %72, %130
>  %132 = insertelement <4 x float> undef, float %65, i32 0
>  %133 = insertelement <4 x float> %132, float %66, i32 1
>  %134 = insertelement <4 x float> %133, float %67, i32 2
>  %135 = insertelement <4 x float> %134, float 0.000000e+00, i32 3
>  %136 = insertelement <4 x float> undef, float %122, i32 0
>  %137 = insertelement <4 x float> %136, float %123, i32 1
>  %138 = insertelement <4 x float> %137, float %124, i32 2
>  %139 = insertelement <4 x float> %138, float 0.000000e+00, i32 3
>  %140 = call float @llvm.AMDGPU.dp4(<4 x float> %135, <4 x float> %139)
>  %141 = fmul float %140, %65
>  %142 = fmul float %140, %66
>  %143 = fmul float %140, %67
>  %144 = fmul float %141, 2.000000e+00
>  %145 = fmul float %142, 2.000000e+00
>  %146 = fmul float %143, 2.000000e+00
>  %147 = fsub float %122, %144
>  %148 = fsub float %123, %145
>  %149 = fsub float %124, %146
>  %150 = insertelement <4 x float> undef, float %10, i32 0
>  %151 = insertelement <4 x float> %150, float %11, i32 1
>  %152 = insertelement <4 x float> %151, float %12, i32 2
>  %153 = insertelement <4 x float> %152, float 0.000000e+00, i32 3
>  %154 = insertelement <4 x float> undef, float %10, i32 0
>  %155 = insertelement <4 x float> %154, float %11, i32 1
>  %156 = insertelement <4 x float> %155, float %12, i32 2
>  %157 = insertelement <4 x float> %156, float 0.000000e+00, i32 3
>  %158 = call float @llvm.AMDGPU.dp4(<4 x float> %153, <4 x float> %157)
>  %159 = call float @llvm.AMDGPU.rsq.clamped.f32(float %158)
>  %160 = fmul float %10, %159
>  %161 = fmul float %11, %159
>  %162 = fmul float %12, %159
>  %163 = insertelement <4 x float> undef, float %147, i32 0
>  %164 = insertelement <4 x float> %163, float %148, i32 1
>  %165 = insertelement <4 x float> %164, float %149, i32 2
>  %166 = insertelement <4 x float> %165, float 0.000000e+00, i32 3
>  %167 = insertelement <4 x float> undef, float %160, i32 0
>  %168 = insertelement <4 x float> %167, float %161, i32 1
>  %169 = insertelement <4 x float> %168, float %162, i32 2
>  %170 = insertelement <4 x float> %169, float 0.000000e+00, i32 3
>  %171 = call float @llvm.AMDGPU.dp4(<4 x float> %166, <4 x float> %170)
>  %172 = fsub float -0.000000e+00, %171
>  %173 = fcmp ule float %171, -0.000000e+00
>  %174 = select i1 %173, float %172, float 0.000000e+00
>  %175 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9)
>  %176 = extractelement <4 x float> %175, i32 0
>  %177 = fmul float %176, %73
>  %178 = fadd float %177, 1.000000e+00
>  %179 = call float @llvm.pow.f32(float %174, float %178)
>  %180 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7)
>  %181 = extractelement <4 x float> %180, i32 0
>  %182 = fmul float %40, %181
>  %183 = extractelement <4 x float> %180, i32 1
>  %184 = fmul float %41, %183
>  %185 = extractelement <4 x float> %180, i32 2
>  %186 = fmul float %42, %185
>  %187 = insertelement <4 x float> undef, float %65, i32 0
>  %188 = insertelement <4 x float> %187, float %66, i32 1
>  %189 = insertelement <4 x float> %188, float %67, i32 2
>  %190 = insertelement <4 x float> %189, float 0.000000e+00, i32 3
>  %191 = insertelement <4 x float> undef, float %122, i32 0
>  %192 = insertelement <4 x float> %191, float %123, i32 1
>  %193 = insertelement <4 x float> %192, float %124, i32 2
>  %194 = insertelement <4 x float> %193, float 0.000000e+00, i32 3
>  %195 = call float @llvm.AMDGPU.dp4(<4 x float> %190, <4 x float> %194)
>  %.inv = fcmp olt float %195, 0.000000e+00
>  %196 = select i1 %.inv, float 0.000000e+00, float %195
>  %197 = fmul float %182, %196
>  %198 = fmul float %184, %196
>  %199 = fmul float %186, %196
>  %200 = fmul float %127, %179
>  %201 = fadd float %200, %197
>  %202 = fmul float %129, %179
>  %203 = fadd float %202, %198
>  %204 = fmul float %131, %179
>  %205 = fadd float %204, %199
>  %206 = shufflevector <2 x float> %16, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
>  %207 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %206, i32 20, i32 4, i32 2)
>  %208 = extractelement <4 x float> %207, i32 0
>  %209 = extractelement <4 x float> %207, i32 1
>  %210 = extractelement <4 x float> %207, i32 2
>  %.inv32 = fcmp ogt float %124, 2.500000e-01
>  %.op = fdiv float 1.000000e+00, %124
>  %211 = select i1 %.inv32, float %.op, float 4.000000e+00
>  %212 = fmul float %208, %211
>  %213 = fmul float %209, %211
>  %214 = fmul float %210, %211
>  %215 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6)
>  %216 = extractelement <4 x float> %215, i32 0
>  %217 = fmul float %40, %216
>  %218 = extractelement <4 x float> %215, i32 1
>  %219 = fmul float %41, %218
>  %220 = extractelement <4 x float> %215, i32 2
>  %221 = fmul float %42, %220
>  %222 = fmul float %201, %212
>  %223 = fadd float %222, %217
>  %224 = fmul float %203, %213
>  %225 = fadd float %224, %219
>  %226 = fmul float %205, %214
>  %227 = fadd float %226, %221
>  %228 = shufflevector <2 x float> %15, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
>  %229 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %228, i32 19, i32 3, i32 2)
>  %230 = extractelement <4 x float> %229, i32 0
>  %231 = extractelement <4 x float> %229, i32 1
>  %232 = extractelement <4 x float> %229, i32 2
>  %233 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10)
>  %234 = extractelement <4 x float> %233, i32 0
>  %235 = fmul float %230, %234
>  %236 = fadd float %235, %223
>  %237 = extractelement <4 x float> %233, i32 1
>  %238 = fmul float %231, %237
>  %239 = fadd float %238, %225
>  %240 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10)
>  %241 = extractelement <4 x float> %240, i32 2
>  %242 = fmul float %232, %241
>  %243 = fadd float %242, %227
>  %244 = insertelement <4 x float> undef, float %236, i32 0
>  %245 = insertelement <4 x float> %244, float %239, i32 1
>  %246 = insertelement <4 x float> %245, float %243, i32 2
>  %247 = insertelement <4 x float> %246, float %46, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %247, i32 0, i32 0)
>  ret void
>}
>
>; Function Attrs: readnone
>declare <2 x float> @llvm.R600.interp.xy(i32, float, float) #1
>
>; Function Attrs: readnone
>declare <2 x float> @llvm.R600.interp.zw(i32, float, float) #1
>
>; Function Attrs: readnone
>declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.AMDGPU.rsq.clamped.f32(float) #2
>
>; Function Attrs: nounwind readnone
>declare float @llvm.pow.f32(float, float) #2
>
>declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { readnone }
>attributes #2 = { nounwind readnone }
>
>===== SHADER #33 ==================================== PS/REDWOOD/EVERGREEN =====
>===== 326 dw ===== 11 gprs ===== 0 stack =======================================
>0000  00000014 a0440000 ALU 18 @40
> 0040  00380400 00346b10     1      x: INTERP_XY          R1.x,  R0.y, Param0.x         VEC_210
> 0042  00380000 20346b10            y: INTERP_XY          R1.y,  R0.x, Param0.x         VEC_210
> 0044  00380400 40146b00            z: INTERP_XY          __.z,  R0.y, Param0.x         VEC_210
> 0046  80380000 60146b00            w: INTERP_XY          __.w,  R0.x, Param0.x         VEC_210
> 0048  00380400 00146b80     2      x: INTERP_ZW          __.x,  R0.y, Param0.x         VEC_210
> 0050  00380000 20146b80            y: INTERP_ZW          __.y,  R0.x, Param0.x         VEC_210
> 0052  00380400 40346b90            z: INTERP_ZW          R1.z,  R0.y, Param0.x         VEC_210
> 0054  80380000 60346b90            w: INTERP_ZW          R1.w,  R0.x, Param0.x         VEC_210
> 0056  00382400 00546b10     3      x: INTERP_XY          R2.x,  R0.y, Param1.x         VEC_210
> 0058  00382000 20546b10            y: INTERP_XY          R2.y,  R0.x, Param1.x         VEC_210
> 0060  00382400 40146b00            z: INTERP_XY          __.z,  R0.y, Param1.x         VEC_210
> 0062  80382000 60146b00            w: INTERP_XY          __.w,  R0.x, Param1.x         VEC_210
> 0064  00382400 00146b80     4      x: INTERP_ZW          __.x,  R0.y, Param1.x         VEC_210
> 0066  00382000 20146b80            y: INTERP_ZW          __.y,  R0.x, Param1.x         VEC_210
> 0068  00382400 40746b90            z: INTERP_ZW          R3.z,  R0.y, Param1.x         VEC_210
> 0070  80382000 60346b90            w: INTERP_ZW          R1.w,  R0.x, Param1.x         VEC_210
> 0072  000008fe 00600c90     5      x: MOV                R3.x,  PV.z
> 0074  80000cfe 20600c90            y: MOV                R3.y,  PV.w
>0002  00000008 80400400 TEX 2 @16
> 0016  00031510 f00d1004 fc828000 SAMPLE              R4.xyzw, R3.xy__,   RID:21, SID:5 CT:NNNN
> 0020  00021010 f00d1005 fc800000 SAMPLE              R5.xyzw, R2.xy__,   RID:16, SID:0 CT:NNNN
>0004  00000026 a0240000 ALU 10 @76
> 0076  001fa005 00c00010     6      x: ADD                R6.x,  R5.x, [0xbf000000 -0.5].x
> 0078  001fa405 20c00010            y: ADD                R6.y,  R5.y, [0xbf000000 -0.5].x
> 0080  00808404 60280010            w: ADD                R1.w,  R4.y, R4.y             VEC_120
> 0082  80008004 60c00010            t: ADD                R6.w,  R4.x, R4.x
> 0084  bf000000 
> 0086  001fa0ff 00e00010     7      x: ADD                R7.x,  PS, [0xbf800000 -1].x
> 0088  001facfe 20e00010            y: ADD                R7.y,  PV.w, [0xbf800000 -1].x
> 0090  009fa805 40a00010            z: ADD                R5.z,  R5.z, [0xbf000000 -0.5].y
> 0092  81008804 60280010            w: ADD                R1.w,  R4.z, R4.z             VEC_120
> 0094  bf800000 
> 0095  bf000000 
>0006  0000000c 80400c00 TEX 4 @24
> 0024  00021310 f00d1004 fc818000 SAMPLE              R4.xyzw, R2.xy__,   RID:19, SID:3 CT:NNNN
> 0028  00031410 f00d1003 fc820000 SAMPLE              R3.xyzw, R3.xy__,   RID:20, SID:4 CT:NNNN
> 0032  00021110 f00d1008 fc808000 SAMPLE              R8.xyzw, R2.xy__,   RID:17, SID:1 CT:NNNN
> 0036  00021210 f00d1002 fc810000 SAMPLE              R2.xyzw, R2.xy__,   RID:18, SID:2 CT:NNNN
>0008  80000030 a1c80000 ALU 115 @96 KC0[CB0:0-31]
> 0096  801fac01 40c00010     8      z: ADD                R6.z,  R1.w, [0xbf800000 -1].x
> 0098  bf800000 
> 0100  00384400 00b46b10     9      x: INTERP_XY          R5.x,  R0.y, Param2.x         VEC_210
> 0102  00384000 20b46b10            y: INTERP_XY          R5.y,  R0.x, Param2.x         VEC_210
> 0104  00384400 40146b00            z: INTERP_XY          __.z,  R0.y, Param2.x         VEC_210
> 0106  80384000 60146b00            w: INTERP_XY          __.w,  R0.x, Param2.x         VEC_210
> 0108  00384400 00146b80    10      x: INTERP_ZW          __.x,  R0.y, Param2.x         VEC_210
> 0110  00384000 20146b80            y: INTERP_ZW          __.y,  R0.x, Param2.x         VEC_210
> 0112  00384400 40f46b90            z: INTERP_ZW          R7.z,  R0.y, Param2.x         VEC_210
> 0114  80384000 60346b90            w: INTERP_ZW          R1.w,  R0.x, Param2.x         VEC_210
> 0116  00386400 01346b10    11      x: INTERP_XY          R9.x,  R0.y, Param3.x         VEC_210
> 0118  00386000 21346b10            y: INTERP_XY          R9.y,  R0.x, Param3.x         VEC_210
> 0120  00386400 40146b00            z: INTERP_XY          __.z,  R0.y, Param3.x         VEC_210
> 0122  80386000 60146b00            w: INTERP_XY          __.w,  R0.x, Param3.x         VEC_210
> 0124  00386400 00146b80    12      x: INTERP_ZW          __.x,  R0.y, Param3.x         VEC_210
> 0126  00386000 20146b80            y: INTERP_ZW          __.y,  R0.x, Param3.x         VEC_210
> 0128  00386400 41346b90            z: INTERP_ZW          R9.z,  R0.y, Param3.x         VEC_210
> 0130  80386000 60346b90            w: INTERP_ZW          R1.w,  R0.x, Param3.x         VEC_210
> 0132  00012007 01205f10    13      x: DOT4               R9.x,  R7.x, R9.x
> 0134  00812407 21205f00            y: DOT4               __.y,  R7.y, R9.y
> 0136  01012806 41205f00            z: DOT4               __.z,  R6.z, R9.z
> 0138  801f00f8 61205f00            w: DOT4               __.w,  0, 0
> 0140  00388400 01546b10    14      x: INTERP_XY          R10.x,  R0.y, Param4.x        VEC_210
> 0142  00388000 21346b10            y: INTERP_XY          R9.y,  R0.x, Param4.x         VEC_210
> 0144  00388400 40146b00            z: INTERP_XY          __.z,  R0.y, Param4.x         VEC_210
> 0146  80388000 60146b00            w: INTERP_XY          __.w,  R0.x, Param4.x         VEC_210
> 0148  00388400 00146b80    15      x: INTERP_ZW          __.x,  R0.y, Param4.x         VEC_210
> 0150  00388000 20146b80            y: INTERP_ZW          __.y,  R0.x, Param4.x         VEC_210
> 0152  00388400 40146b90            z: INTERP_ZW          R0.z,  R0.y, Param4.x         VEC_210
> 0154  80388000 60146b90            w: INTERP_ZW          R0.w,  R0.x, Param4.x         VEC_210
> 0156  00014007 00005f00    16      x: DOT4               __.x,  R7.x, R10.x
> 0158  00812407 20005f10            y: DOT4               R0.y,  R7.y, R9.y
> 0160  01000806 40005f00            z: DOT4               __.z,  R6.z, R0.z
> 0162  801f00f8 60005f00            w: DOT4               __.w,  0, 0
> 0164  0000a007 00005f00    17      x: DOT4               __.x,  R7.x, R5.x
> 0166  0080a407 20005f00            y: DOT4               __.y,  R7.y, R5.y
> 0168  0100e806 40005f10            z: DOT4               R0.z,  R6.z, R7.z
> 0170  801f00f8 60005f00            w: DOT4               __.w,  0, 0
> 0172  0000c006 00005f10    18      x: DOT4               R0.x,  R6.x, R6.x
> 0174  0080c406 20005f00            y: DOT4               __.y,  R6.y, R6.y
> 0176  0100a805 40005f00            z: DOT4               __.z,  R5.z, R5.z
> 0178  801f00f8 60005f00            w: DOT4               __.w,  0, 0
> 0180  800000fe 00004390    19      t: RECIPSQRT_CLAMPED  R0.x,  PV.x
> 0182  00012009 00005f00    20      x: DOT4               __.x,  R9.x, R9.x
> 0184  00800400 20005f00            y: DOT4               __.y,  R0.y, R0.y
> 0186  01000800 40005f00            z: DOT4               __.z,  R0.z, R0.z
> 0188  801f00f8 60005f10            w: DOT4               R0.w,  0, 0
> 0190  800000fe 60004390    21      t: RECIPSQRT_CLAMPED  R0.w,  PV.x
> 0192  001fe009 00a00110    22      x: MUL_IEEE           R5.x,  R9.x, PS
> 0194  00000406 20a00110            y: MUL_IEEE           R5.y,  R6.y, R0.x
> 0196  001fe800 40c00110            z: MUL_IEEE           R6.z,  R0.z, PS
> 0198  80000006 00c00110            t: MUL_IEEE           R6.x,  R6.x, R0.x
> 0200  01800400 20c00110    23      y: MUL_IEEE           R6.y,  R0.y, R0.w
> 0202  80000805 40a00110            z: MUL_IEEE           R5.z,  R5.z, R0.x
> 0204  0000a006 00005f10    24      x: DOT4               R0.x,  R6.x, R5.x
> 0206  0080c405 20005f00            y: DOT4               __.y,  R5.y, R6.y
> 0208  0100c805 40005f00            z: DOT4               __.z,  R5.z, R6.z
> 0210  801f00f8 60005f00            w: DOT4               __.w,  0, 0
> 0212  0080a0fe 60200110    25      w: MUL_IEEE           R1.w,  PV.x, R5.y
> 0214  8100a0fe 60a00110            t: MUL_IEEE           R5.w,  PV.x, R5.z
> 0216  0100a000 40a300ff    26      z: MULADD_IEEE        R5.z,  R0.x, R5.z, PS
> 0218  0080a000 60230cfe            w: MULADD_IEEE        R1.w,  R0.x, R5.y, PV.w
> 0220  8000c000 60a00110            t: MUL_IEEE           R5.w,  R0.x, R6.x
> 0222  8000c000 60a300ff    27      w: MULADD_IEEE        R5.w,  R0.x, R6.x, PS
> 0224  00002001 00a05f10    28      x: DOT4               R5.x,  R1.x, R1.x
> 0226  00802401 20a05f00            y: DOT4               __.y,  R1.y, R1.y
> 0228  01002801 40a05f00            z: DOT4               __.z,  R1.z, R1.z
> 0230  801f00f8 60a05f00            w: DOT4               __.w,  0, 0
> 0232  01800009 00c31c05    29      x: MULADD_IEEE        R6.x,  R9.x, R0.w, -R5.w
> 0234  01800400 20171c01            y: MULADD_IEEE        R0.y,  R0.y, R0.w, -R1.w      VEC_210
> 0236  01800800 40031805            z: MULADD_IEEE        R0.z,  R0.z, R0.w, -R5.z
> 0238  800000fe 60004390            t: RECIPSQRT_CLAMPED  R0.w,  PV.x
> 0240  001fe001 00200110    30      x: MUL_IEEE           R1.x,  R1.x, PS
> 0242  001fe401 20200110            y: MUL_IEEE           R1.y,  R1.y, PS
> 0244  801fe801 40200110            z: MUL_IEEE           R1.z,  R1.z, PS
> 0246  00002006 00005f00    31      x: DOT4               __.x,  R6.x, R1.x
> 0248  00802400 20005f10            y: DOT4               R0.y,  R0.y, R1.y
> 0250  01002800 40005f00            z: DOT4               __.z,  R0.z, R1.z
> 0252  801f00f8 60005f00            w: DOT4               __.w,  0, 0
> 0254  001f00fe 600350fe    32      w: CNDGT              R0.w,  PV.x, 0, -PV.x
> 0256  81804089 602700f9            t: MULADD_IEEE        R1.w,  KC0[9].x, R2.w, 1.0    SCL_122
> 0258  80000cfe 20004190    33      t: LOG_IEEE           R0.y,  PV.w
> 0260  001fec01 20000090    34      y: MUL                R0.y,  R1.w, PS
> 0262  000000f8 40000190            z: MAX                R0.z,  0, R0.x
> 0264  0090e408 60000110            w: MUL_IEEE           R0.w,  R8.y, KC0[7].y
> 0266  80000806 00004310            t: RECIP_IEEE         R0.x,  R6.z
> 0268  001fa806 00200490    35      x: SETGT              R1.x,  R6.z, [0x3e800000 0.25].x
> 0270  0010e008 20200110            y: MUL_IEEE           R1.y,  R8.x, KC0[7].x
> 0272  011fccfe 40200110            z: MUL_IEEE           R1.z,  PV.w, PV.z
> 0274  00910402 60000110            w: MUL_IEEE           R0.w,  R2.y, KC0[8].y
> 0276  800004fe 20004090            t: EXP_IEEE           R0.y,  PV.y
> 0278  3e800000 
> 0280  001fecfe 20a308fe    36      y: MULADD_IEEE        R5.y,  PV.w, PS, PV.z
> 0282  010004fe 40200110            z: MUL_IEEE           R1.z,  PV.y, R0.z
> 0284  00110002 60000110            w: MUL_IEEE           R0.w,  R2.x, KC0[8].x
> 0286  801fa0fe 60272000            t: CNDE               R1.w,  PV.x, [0x40800000 4].x, R0.x  SCL_122
> 0288  40800000 
> 0290  001fe403 00000110    37      x: MUL_IEEE           R0.x,  R3.y, PS
> 0292  00800cfe 202308fe            y: MULADD_IEEE        R1.y,  PV.w, R0.y, PV.z
> 0294  001fe003 40200110            z: MUL_IEEE           R1.z,  R3.x, PS
> 0296  0010c008 60080110            w: MUL_IEEE           R0.w,  R8.x, KC0[6].x         VEC_120
> 0298  8110e808 60a00110            t: MUL_IEEE           R5.w,  R8.z, KC0[7].z
> 0300  0090c408 00200110    38      x: MUL_IEEE           R1.x,  R8.y, KC0[6].y
> 0302  010000ff 20c00110            y: MUL_IEEE           R6.y,  PS, R0.z
> 0304  01110802 40000110            z: MUL_IEEE           R0.z,  R2.z, KC0[8].z
> 0306  811fc4fe 60030cfe            w: MULADD_IEEE        R0.w,  PV.y, PV.z, PV.w
> 0308  80116c08 60400110    39      w: MUL_IEEE           R2.w,  R8.w, KC0[11].x
> 0310  00114004 00530c00    40      x: MULADD_IEEE        R2.x,  R4.x, KC0[10].x, R0.w  VEC_201
> 0312  00800800 20130406            y: MULADD_IEEE        R0.y,  R0.z, R0.y, R6.y       VEC_201
> 0314  01802803 40040110            z: MUL_IEEE           R0.z,  R3.z, R1.w             VEC_021
> 0316  0110c808 60080110            w: MUL_IEEE           R0.w,  R8.z, KC0[6].z         VEC_120
> 0318  80000405 60230001            t: MULADD_IEEE        R1.w,  R5.y, R0.x, R1.x
> 0320  00914404 204300ff    41      y: MULADD_IEEE        R2.y,  R4.y, KC0[10].y, PS
> 0322  811fc4fe 60030cfe            w: MULADD_IEEE        R0.w,  PV.y, PV.z, PV.w
> 0324  81114804 40430cfe    42      z: MULADD_IEEE        R2.z,  R4.z, KC0[10].z, PV.w
>0010  c0010000 95200688 EXPORT_DONE        PIXEL 0     R2.xyzw  EOP
>===== SHADER_END ===============================================================
>
>
>===== SHADER #33 OPT ================================ PS/REDWOOD/EVERGREEN =====
>===== 322 dw ===== 8 gprs ===== 0 stack ========================================
>0000  00000005 a01c0000 ALU 8 @10
> 0010  00382400 00346b10     1      x: INTERP_XY          R1.x,  R0.y, Param1.x         VEC_210
> 0012  00b82000 20346b10            y: INTERP_XY          R1.y,  R0.x, Param1.y         VEC_210
> 0014  01382400 40146b00            z: INTERP_XY          __.z,  R0.y, Param1.z         VEC_210
> 0016  81b82000 60146b00            w: INTERP_XY          __.w,  R0.x, Param1.w         VEC_210
> 0018  00382400 00146b80     2      x: INTERP_ZW          __.x,  R0.y, Param1.x         VEC_210
> 0020  00b82000 20146b80            y: INTERP_ZW          __.y,  R0.x, Param1.y         VEC_210
> 0022  01382400 40146b90            z: INTERP_ZW          R0.z,  R0.y, Param1.z         VEC_210
> 0024  81b82000 60146b90            w: INTERP_ZW          R0.w,  R0.x, Param1.w         VEC_210
>0002  0000000e 80401400 TEX 6 @28
> 0028  00001510 f01d1006 fda28000 SAMPLE              R6.xyz_, R0.zw__,   RID:21, SID:5 CT:NNNN
> 0032  00011010 f01d1005 fc800000 SAMPLE              R5.xyz_, R1.xy__,   RID:16, SID:0 CT:NNNN
> 0036  00011210 f00d1002 fc810000 SAMPLE              R2.xyzw, R1.xy__,   RID:18, SID:2 CT:NNNN
> 0040  00011110 f00d1003 fc808000 SAMPLE              R3.xyzw, R1.xy__,   RID:17, SID:1 CT:NNNN
> 0044  00001410 f01d1004 fda20000 SAMPLE              R4.xyz_, R0.zw__,   RID:20, SID:4 CT:NNNN
> 0048  00011310 f01d1001 fc818000 SAMPLE              R1.xyz_, R1.xy__,   RID:19, SID:3 CT:NNNN
>0004  0000001a a01c0000 ALU 8 @52
> 0052  00384400 00146b80     3      x: INTERP_ZW          __.x,  R0.y, Param2.x         VEC_210
> 0054  00b84000 20146b80            y: INTERP_ZW          __.y,  R0.x, Param2.y         VEC_210
> 0056  01384400 40146b90            z: INTERP_ZW          R0.z,  R0.y, Param2.z         VEC_210
> 0058  81b84000 60146b80            w: INTERP_ZW          __.w,  R0.x, Param2.w         VEC_210
> 0060  00384400 00f46b10     4      x: INTERP_XY          R7.x,  R0.y, Param2.x         VEC_210
> 0062  00b84000 20f46b10            y: INTERP_XY          R7.y,  R0.x, Param2.y         VEC_210
> 0064  01384400 40146b00            z: INTERP_XY          __.z,  R0.y, Param2.z         VEC_210
> 0066  81b84000 60146b00            w: INTERP_XY          __.w,  R0.x, Param2.w         VEC_210
>0006  40000022 a1f80000 ALU 127 @68 KC0[CB0:0-15]
> 0068  001fa006 4f8284fd     5      z: MULADD             T0.z,  R6.x, [0x40000000 2].x, [0xbf800000 -1].y
> 0070  801fa406 6fa284fd            w: MULADD             T1.w,  R6.y, [0x40000000 2].x, [0xbf800000 -1].y
> 0072  40000000 
> 0073  bf800000 
> 0074  00388400 00146b80     6      x: INTERP_ZW          __.x,  R0.y, Param4.x         VEC_210
> 0076  00b88000 20146b80            y: INTERP_ZW          __.y,  R0.x, Param4.y         VEC_210
> 0078  01388400 4fd46b90            z: INTERP_ZW          T2.z,  R0.y, Param4.z         VEC_210
> 0080  81b88000 60146b80            w: INTERP_ZW          __.w,  R0.x, Param4.w         VEC_210
> 0082  00388400 0fb46b10     7      x: INTERP_XY          T1.x,  R0.y, Param4.x         VEC_210
> 0084  00b88000 2fb46b10            y: INTERP_XY          T1.y,  R0.x, Param4.y         VEC_210
> 0086  01388400 40146b00            z: INTERP_XY          __.z,  R0.y, Param4.z         VEC_210
> 0088  81b88000 60146b00            w: INTERP_XY          __.w,  R0.x, Param4.w         VEC_210
> 0090  00386400 00146b80     8      x: INTERP_ZW          __.x,  R0.y, Param3.x         VEC_210
> 0092  00b86000 20146b80            y: INTERP_ZW          __.y,  R0.x, Param3.y         VEC_210
> 0094  01386400 4fb46b90            z: INTERP_ZW          T1.z,  R0.y, Param3.z         VEC_210
> 0096  81b86000 60146b80            w: INTERP_ZW          __.w,  R0.x, Param3.w         VEC_210
> 0098  00386400 0f946b10     9      x: INTERP_XY          T0.x,  R0.y, Param3.x         VEC_210
> 0100  00b86000 2f946b10            y: INTERP_XY          T0.y,  R0.x, Param3.y         VEC_210
> 0102  01386400 40146b00            z: INTERP_XY          __.z,  R0.y, Param3.z         VEC_210
> 0104  01b86000 60146b00            w: INTERP_XY          __.w,  R0.x, Param3.w         VEC_210
> 0106  801fa806 6fe284fd            t: MULADD             T3.w,  R6.z, [0x40000000 2].x, [0xbf800000 -1].y
> 0108  40000000 
> 0109  bf800000 
> 0110  0000e87c 00005f00    10      x: DOT4               __.x,  T0.z, R7.x
> 0112  0080ec7d 2fc05f10            y: DOT4               T2.y,  T1.w, R7.y
> 0114  01000c7f 40085f00            z: DOT4               __.z,  T3.w, R0.z             VEC_120
> 0116  001f00f8 60005f00            w: DOT4               __.w,  0, 0
> 0118  801fa805 6fc40010            t: ADD                T2.w,  R5.z, [0xbf000000 -0.5].x  SCL_122
> 0120  bf000000 
> 0122  000fa87c 0fe05f10    11      x: DOT4               T3.x,  T0.z, T1.x
> 0124  008fac7d 20005f00            y: DOT4               __.y,  T1.w, T1.y
> 0126  010fcc7f 40085f00            z: DOT4               __.z,  T3.w, T2.z             VEC_120
> 0128  001f00f8 60005f00            w: DOT4               __.w,  0, 0
> 0130  801fa405 6f800010            t: ADD                T0.w,  R5.y, [0xbf000000 -0.5].x
> 0132  bf000000 
> 0134  000f887c 00005f00    12      x: DOT4               __.x,  T0.z, T0.x
> 0136  008f8c7d 20005f00            y: DOT4               __.y,  T1.w, T0.y
> 0138  010fac7f 40085f00            z: DOT4               __.z,  T3.w, T1.z             VEC_120
> 0140  001f00f8 60005f10            w: DOT4               R0.w,  0, 0
> 0142  801fa005 6fe00010            t: ADD                T3.w,  R5.x, [0xbf000000 -0.5].x
> 0144  bf000000 
> 0146  018fec7f 0f805f10    13      x: DOT4               T0.x,  T3.w, T3.w
> 0148  018f8c7c 20085f00            y: DOT4               __.y,  T0.w, T0.w             VEC_120
> 0150  018fcc7e 40105f00            z: DOT4               __.z,  T2.w, T2.w             VEC_201
> 0152  801f00f8 60005f00            w: DOT4               __.w,  0, 0
> 0154  01800c00 00005f00    14      x: DOT4               __.x,  R0.w, R0.w
> 0156  000fe07f 20005f00            y: DOT4               __.y,  T3.x, T3.x
> 0158  008fc47e 4fa05f10            z: DOT4               T1.z,  T2.y, T2.y
> 0160  801f00f8 60005f00            w: DOT4               __.w,  0, 0
> 0162  00380400 00146b80    15      x: INTERP_ZW          __.x,  R0.y, Param0.x         VEC_210
> 0164  00b80000 20146b80            y: INTERP_ZW          __.y,  R0.x, Param0.y         VEC_210
> 0166  01380400 4f946b90            z: INTERP_ZW          T0.z,  R0.y, Param0.z         VEC_210
> 0168  81b80000 60146b80            w: INTERP_ZW          __.w,  R0.x, Param0.w         VEC_210
> 0170  00380400 0fd46b10    16      x: INTERP_XY          T2.x,  R0.y, Param0.x         VEC_210
> 0172  00b80000 2fb46b10            y: INTERP_XY          T1.y,  R0.x, Param0.y         VEC_210
> 0174  01380400 40146b00            z: INTERP_XY          __.z,  R0.y, Param0.z         VEC_210
> 0176  01b80000 60146b00            w: INTERP_XY          __.w,  R0.x, Param0.w         VEC_210
> 0178  8000007c 6fa44390            t: RECIPSQRT_CLAMPED  T1.w,  T0.x                   SCL_122
> 0180  018fac7e 2f800110    17      y: MUL_IEEE           T0.y,  T2.w, T1.w
> 0182  8000087d 4fc04390            t: RECIPSQRT_CLAMPED  T2.z,  T1.z
> 0184  010fc07f 0f800110    18      x: MUL_IEEE           T0.x,  T3.x, T2.z
> 0186  010fc47e 4fa00110            z: MUL_IEEE           T1.z,  T2.y, T2.z
> 0188  010fcc00 6f800110            w: MUL_IEEE           T0.w,  R0.w, T2.z
> 0190  818fac7c 6fc00110            t: MUL_IEEE           T2.w,  T0.w, T1.w
> 0192  000fc07e 00005f00    19      x: DOT4               __.x,  T2.x, T2.x
> 0194  008fa47d 20005f00            y: DOT4               __.y,  T1.y, T1.y
> 0196  010f887c 40005f00            z: DOT4               __.z,  T0.z, T0.z
> 0198  001f00f8 6fe05f10            w: DOT4               T3.w,  0, 0
> 0200  818fac7f 6fa00110            t: MUL_IEEE           T1.w,  T3.w, T1.w
> 0202  018f8c7d 0fa05f10    20      x: DOT4               T1.x,  T1.w, T0.w
> 0204  000f8c7e 20105f00            y: DOT4               __.y,  T2.w, T0.x             VEC_201
> 0206  010fa47c 40005f00            z: DOT4               __.z,  T0.y, T1.z
> 0208  001f00f8 60005f00            w: DOT4               __.w,  0, 0
> 0210  801fa47c 6f800090            t: MUL                T0.w,  T0.y, [0x40000000 2].x
> 0212  40000000 
> 0214  001fac7e 6fc00090    21      w: MUL                T2.w,  T2.w, [0x40000000 2].x
> 0216  80000c7f 2f804390            t: RECIPSQRT_CLAMPED  T0.y,  T3.w
> 0218  40000000 
> 0220  018f807d 6fa00110    22      w: MUL_IEEE           T1.w,  T1.x, T0.w
> 0222  801fac7d 6f800090            t: MUL                T0.w,  T1.w, [0x40000000 2].x
> 0224  40000000 
> 0226  018f807d 0f800110    23      x: MUL_IEEE           T0.x,  T1.x, T0.w
> 0228  008f887c 6fc00110            w: MUL_IEEE           T2.w,  T0.z, T0.y
> 0230  818fc07d 6f840110            t: MUL_IEEE           T0.w,  T1.x, T2.w             SCL_122
> 0232  010fcc00 0f83107c    24      x: MULADD_IEEE        T0.x,  R0.w, T2.z, -T0.x
> 0234  008f807e 2f800110            y: MUL_IEEE           T0.y,  T2.x, T0.y
> 0236  010fc07f 4f8f1c7c            z: MULADD_IEEE        T0.z,  T3.x, T2.z, -T0.w      VEC_102
> 0238  008f847d 6f800110            w: MUL_IEEE           T0.w,  T1.y, T0.y
> 0240  810fc47e 6faf1c7d            t: MULADD_IEEE        T1.w,  T2.y, T2.z, -T1.w      SCL_221
> 0242  008f807c 0f805f10    25      x: DOT4               T0.x,  T0.x, T0.y
> 0244  018f887c 20005f00            y: DOT4               __.y,  T0.z, T0.w
> 0246  018fcc7d 40045f00            z: DOT4               __.z,  T1.w, T2.w             VEC_021
> 0248  801f00f8 60005f00            w: DOT4               __.w,  0, 0
> 0250  001f007c 0f83507c    26      x: CNDGT              T0.x,  T0.x, 0, -T0.x
> 0252  8000087d 6fa04310            t: RECIP_IEEE         T1.w,  T1.z
> 0254  01804089 2f8300f9    27      y: MULADD_IEEE        T0.y,  KC0[9].x, R2.w, 1.0
> 0256  001fa87d 6f800490            w: SETGT              T0.w,  T1.z, [0x3e800000 0.25].x
> 0258  8000007c 0f804190            t: LOG_IEEE           T0.x,  T0.x
> 0260  3e800000 
> 0262  000f847c 0f880090    28      x: MUL                T0.x,  T0.y, T0.x             VEC_120
> 0264  0110e803 2f800110            y: MUL_IEEE           T0.y,  R3.z, KC0[7].z
> 0266  001f007d 4fc00190            z: MAX                T2.z,  T1.x, 0
> 0268  0090e403 6f800110            w: MUL_IEEE           T0.w,  R3.y, KC0[7].y
> 0270  801fac7c 6fe72c7d            t: CNDE               T3.w,  T0.w, [0x40800000 4].x, T1.w  SCL_122
> 0272  40800000 
> 0274  010fc47c 2f800110    29      y: MUL_IEEE           T0.y,  T0.y, T2.z
> 0276  01110802 4f800110            z: MUL_IEEE           T0.z,  R2.z, KC0[8].z
> 0278  0010e003 6fa00110            w: MUL_IEEE           T1.w,  R3.x, KC0[7].x
> 0280  8000007c 0fa04090            t: EXP_IEEE           T1.x,  T0.x
> 0282  010fcc7c 2fa40110    30      y: MUL_IEEE           T1.y,  T0.w, T2.z             VEC_021
> 0284  018fe804 4fa00110            z: MUL_IEEE           T1.z,  R4.z, T3.w
> 0286  0110c803 6f880110            w: MUL_IEEE           T0.w,  R3.z, KC0[6].z         VEC_120
> 0288  80910402 6fc00110            t: MUL_IEEE           T2.w,  R2.y, KC0[8].y
> 0290  00110002 0f880110    31      x: MUL_IEEE           T0.x,  R2.x, KC0[8].x         VEC_120
> 0292  0090c403 2fc00110            y: MUL_IEEE           T2.y,  R3.y, KC0[6].y
> 0294  010fcc7d 4f800110            z: MUL_IEEE           T0.z,  T1.w, T2.z
> 0296  0010c003 6fa00110            w: MUL_IEEE           T1.w,  R3.x, KC0[6].x
> 0298  800fa87c 2f8f047c            t: MULADD_IEEE        T0.y,  T0.z, T1.x, T0.y       SCL_221
> 0300  000fa07c 0f87087c    32      x: MULADD_IEEE        T0.x,  T0.x, T1.x, T0.z       VEC_021
> 0302  010fa47c 2f870c7c            y: MULADD_IEEE        T0.y,  T0.y, T1.z, T0.w       VEC_021
> 0304  018fe004 4f880110            z: MUL_IEEE           T0.z,  R4.x, T3.w             VEC_120
> 0306  000fac7e 6f87047d            w: MULADD_IEEE        T0.w,  T2.w, T1.x, T1.y       VEC_021
> 0308  818fe404 2fac0110            t: MUL_IEEE           T1.y,  R4.y, T3.w             SCL_221
> 0310  010f807c 0f870c7d    33      x: MULADD_IEEE        T0.x,  T0.x, T0.z, T1.w       VEC_021
> 0312  00116c03 60000110            w: MUL_IEEE           R0.w,  R3.w, KC0[11].x
> 0314  808fac7c 6f83047e            t: MULADD_IEEE        T0.w,  T0.w, T1.y, T2.y
> 0316  00114001 0003007c    34      x: MULADD_IEEE        R0.x,  R1.x, KC0[10].x, T0.x
> 0318  00914401 20030c7c            y: MULADD_IEEE        R0.y,  R1.y, KC0[10].y, T0.w
> 0320  81114801 4003047c            z: MULADD_IEEE        R0.z,  R1.z, KC0[10].z, T0.y
>0008  c0000000 95200688 EXPORT_DONE        PIXEL 0     R0.xyzw  EOP
>===== SHADER_END ===============================================================
>
>--------------------------------------------------------------
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL IN[4]
>DCL IN[5]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[9]
>DCL OUT[2], GENERIC[10]
>DCL OUT[3], GENERIC[11]
>DCL OUT[4], GENERIC[12]
>DCL OUT[5], GENERIC[13]
>DCL CONST[0..8]
>DCL TEMP[0..5], LOCAL
>IMM[0] FLT32 {    0.0000,     0.0000,     0.0000,     0.0000}
>  0: MUL TEMP[0], CONST[5], IN[1].xxxx
>  1: MAD TEMP[0], CONST[6], IN[1].yyyy, TEMP[0]
>  2: MAD TEMP[0], CONST[7], IN[1].zzzz, TEMP[0]
>  3: MAD TEMP[0].xy, CONST[8], IN[1].wwww, TEMP[0]
>  4: MOV TEMP[0].xy, TEMP[0].xyxx
>  5: MOV TEMP[0].zw, IN[5].yyxy
>  6: ADD TEMP[1].xyz, CONST[4].xyzz, -IN[0].xyzz
>  7: DP3 TEMP[2].x, TEMP[1].xyzz, IN[2].xyzz
>  8: DP3 TEMP[3].x, TEMP[1].xyzz, IN[3].xyzz
>  9: MOV TEMP[2].y, TEMP[3].xxxx
> 10: DP3 TEMP[1].x, TEMP[1].xyzz, IN[4].xyzz
> 11: MOV TEMP[2].z, TEMP[1].xxxx
> 12: MOV TEMP[2].w, IMM[0].xxxx
> 13: MOV TEMP[1].w, IMM[0].xxxx
> 14: MOV TEMP[1].xyz, IN[2].xyzx
> 15: MOV TEMP[3].w, IMM[0].xxxx
> 16: MOV TEMP[3].xyz, IN[3].xyzx
> 17: MOV TEMP[4].w, IMM[0].xxxx
> 18: MOV TEMP[4].xyz, IN[4].xyzx
> 19: MUL TEMP[5], CONST[0], IN[0].xxxx
> 20: MAD TEMP[5], CONST[1], IN[0].yyyy, TEMP[5]
> 21: MAD TEMP[5], CONST[2], IN[0].zzzz, TEMP[5]
> 22: MAD TEMP[5], CONST[3], IN[0].wwww, TEMP[5]
> 23: MOV OUT[3], TEMP[4]
> 24: MOV OUT[4], TEMP[1]
> 25: MOV OUT[0], TEMP[5]
> 26: MOV OUT[5], TEMP[3]
> 27: MOV OUT[1], TEMP[2]
> 28: MOV OUT[2], TEMP[0]
> 29: END
>; ModuleID = 'tgsi'
>
>define void @main(<4 x float> inreg, <4 x float> inreg, <4 x float> inreg, <4 x float> inreg, <4 x float> inreg, <4 x float> inreg, <4 x float> inreg) #0 {
>main_body:
>  %7 = extractelement <4 x float> %1, i32 0
>  %8 = extractelement <4 x float> %1, i32 1
>  %9 = extractelement <4 x float> %1, i32 2
>  %10 = extractelement <4 x float> %1, i32 3
>  %11 = extractelement <4 x float> %2, i32 0
>  %12 = extractelement <4 x float> %2, i32 1
>  %13 = extractelement <4 x float> %2, i32 2
>  %14 = extractelement <4 x float> %2, i32 3
>  %15 = extractelement <4 x float> %3, i32 0
>  %16 = extractelement <4 x float> %3, i32 1
>  %17 = extractelement <4 x float> %3, i32 2
>  %18 = extractelement <4 x float> %4, i32 0
>  %19 = extractelement <4 x float> %4, i32 1
>  %20 = extractelement <4 x float> %4, i32 2
>  %21 = extractelement <4 x float> %5, i32 0
>  %22 = extractelement <4 x float> %5, i32 1
>  %23 = extractelement <4 x float> %5, i32 2
>  %24 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5)
>  %25 = extractelement <4 x float> %24, i32 0
>  %26 = fmul float %25, %11
>  %27 = extractelement <4 x float> %24, i32 1
>  %28 = fmul float %27, %11
>  %29 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6)
>  %30 = extractelement <4 x float> %29, i32 0
>  %31 = fmul float %30, %12
>  %32 = fadd float %31, %26
>  %33 = extractelement <4 x float> %29, i32 1
>  %34 = fmul float %33, %12
>  %35 = fadd float %34, %28
>  %36 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7)
>  %37 = extractelement <4 x float> %36, i32 0
>  %38 = fmul float %37, %13
>  %39 = fadd float %38, %32
>  %40 = extractelement <4 x float> %36, i32 1
>  %41 = fmul float %40, %13
>  %42 = fadd float %41, %35
>  %43 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8)
>  %44 = extractelement <4 x float> %43, i32 0
>  %45 = fmul float %44, %14
>  %46 = fadd float %45, %39
>  %47 = extractelement <4 x float> %43, i32 1
>  %48 = fmul float %47, %14
>  %49 = fadd float %48, %42
>  %50 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4)
>  %51 = extractelement <4 x float> %50, i32 0
>  %52 = fsub float %51, %7
>  %53 = extractelement <4 x float> %50, i32 1
>  %54 = fsub float %53, %8
>  %55 = extractelement <4 x float> %50, i32 2
>  %56 = fsub float %55, %9
>  %57 = insertelement <4 x float> undef, float %52, i32 0
>  %58 = insertelement <4 x float> %57, float %54, i32 1
>  %59 = insertelement <4 x float> %58, float %56, i32 2
>  %60 = insertelement <4 x float> %59, float 0.000000e+00, i32 3
>  %61 = insertelement <4 x float> undef, float %15, i32 0
>  %62 = insertelement <4 x float> %61, float %16, i32 1
>  %63 = insertelement <4 x float> %62, float %17, i32 2
>  %64 = insertelement <4 x float> %63, float 0.000000e+00, i32 3
>  %65 = call float @llvm.AMDGPU.dp4(<4 x float> %60, <4 x float> %64)
>  %66 = insertelement <4 x float> undef, float %52, i32 0
>  %67 = insertelement <4 x float> %66, float %54, i32 1
>  %68 = insertelement <4 x float> %67, float %56, i32 2
>  %69 = insertelement <4 x float> %68, float 0.000000e+00, i32 3
>  %70 = insertelement <4 x float> undef, float %18, i32 0
>  %71 = insertelement <4 x float> %70, float %19, i32 1
>  %72 = insertelement <4 x float> %71, float %20, i32 2
>  %73 = insertelement <4 x float> %72, float 0.000000e+00, i32 3
>  %74 = call float @llvm.AMDGPU.dp4(<4 x float> %69, <4 x float> %73)
>  %75 = insertelement <4 x float> undef, float %52, i32 0
>  %76 = insertelement <4 x float> %75, float %54, i32 1
>  %77 = insertelement <4 x float> %76, float %56, i32 2
>  %78 = insertelement <4 x float> %77, float 0.000000e+00, i32 3
>  %79 = insertelement <4 x float> undef, float %21, i32 0
>  %80 = insertelement <4 x float> %79, float %22, i32 1
>  %81 = insertelement <4 x float> %80, float %23, i32 2
>  %82 = insertelement <4 x float> %81, float 0.000000e+00, i32 3
>  %83 = call float @llvm.AMDGPU.dp4(<4 x float> %78, <4 x float> %82)
>  %84 = load <4 x float> addrspace(8)* null
>  %85 = extractelement <4 x float> %84, i32 0
>  %86 = fmul float %85, %7
>  %87 = extractelement <4 x float> %84, i32 1
>  %88 = fmul float %87, %7
>  %89 = extractelement <4 x float> %84, i32 2
>  %90 = fmul float %89, %7
>  %91 = load <4 x float> addrspace(8)* null
>  %92 = extractelement <4 x float> %91, i32 3
>  %93 = fmul float %92, %7
>  %94 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
>  %95 = extractelement <4 x float> %94, i32 0
>  %96 = fmul float %95, %8
>  %97 = fadd float %96, %86
>  %98 = extractelement <4 x float> %94, i32 1
>  %99 = fmul float %98, %8
>  %100 = fadd float %99, %88
>  %101 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
>  %102 = extractelement <4 x float> %101, i32 2
>  %103 = fmul float %102, %8
>  %104 = fadd float %103, %90
>  %105 = extractelement <4 x float> %101, i32 3
>  %106 = fmul float %105, %8
>  %107 = fadd float %106, %93
>  %108 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
>  %109 = extractelement <4 x float> %108, i32 0
>  %110 = fmul float %109, %9
>  %111 = fadd float %110, %97
>  %112 = extractelement <4 x float> %108, i32 1
>  %113 = fmul float %112, %9
>  %114 = fadd float %113, %100
>  %115 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
>  %116 = extractelement <4 x float> %115, i32 2
>  %117 = fmul float %116, %9
>  %118 = fadd float %117, %104
>  %119 = extractelement <4 x float> %115, i32 3
>  %120 = fmul float %119, %9
>  %121 = fadd float %120, %107
>  %122 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
>  %123 = extractelement <4 x float> %122, i32 0
>  %124 = fmul float %123, %10
>  %125 = fadd float %124, %111
>  %126 = extractelement <4 x float> %122, i32 1
>  %127 = fmul float %126, %10
>  %128 = fadd float %127, %114
>  %129 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
>  %130 = extractelement <4 x float> %129, i32 2
>  %131 = fmul float %130, %10
>  %132 = fadd float %131, %118
>  %133 = extractelement <4 x float> %129, i32 3
>  %134 = fmul float %133, %10
>  %135 = fadd float %134, %121
>  %136 = insertelement <4 x float> undef, float %125, i32 0
>  %137 = insertelement <4 x float> %136, float %128, i32 1
>  %138 = insertelement <4 x float> %137, float %132, i32 2
>  %139 = insertelement <4 x float> %138, float %135, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %139, i32 60, i32 1)
>  %140 = insertelement <4 x float> undef, float %65, i32 0
>  %141 = insertelement <4 x float> %140, float %74, i32 1
>  %142 = insertelement <4 x float> %141, float %83, i32 2
>  %143 = insertelement <4 x float> %142, float 0.000000e+00, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %143, i32 0, i32 2)
>  %144 = insertelement <4 x float> undef, float %46, i32 0
>  %145 = insertelement <4 x float> %144, float %49, i32 1
>  %146 = shufflevector <4 x float> %145, <4 x float> %6, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
>  call void @llvm.R600.store.swizzle(<4 x float> %146, i32 1, i32 2)
>  %147 = insertelement <4 x float> undef, float %21, i32 0
>  %148 = insertelement <4 x float> %147, float %22, i32 1
>  %149 = insertelement <4 x float> %148, float %23, i32 2
>  %150 = insertelement <4 x float> %149, float 0.000000e+00, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %150, i32 2, i32 2)
>  %151 = insertelement <4 x float> undef, float %15, i32 0
>  %152 = insertelement <4 x float> %151, float %16, i32 1
>  %153 = insertelement <4 x float> %152, float %17, i32 2
>  %154 = insertelement <4 x float> %153, float 0.000000e+00, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %154, i32 3, i32 2)
>  %155 = insertelement <4 x float> undef, float %18, i32 0
>  %156 = insertelement <4 x float> %155, float %19, i32 1
>  %157 = insertelement <4 x float> %156, float %20, i32 2
>  %158 = insertelement <4 x float> %157, float 0.000000e+00, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %158, i32 4, i32 2)
>  ret void
>}
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1
>
>declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { readnone }
>
>===== SHADER #34 ==================================== VS/REDWOOD/EVERGREEN =====
>===== 98 dw ===== 10 gprs ===== 1 stack ========================================
>0000  00000000 84c00000 CALL_FS @0
>0002  8000000a a0980000 ALU 39 @20 KC0[CB0:0-31]
> 0020  80002080 60000110     1      w: MUL_IEEE           R0.w,  KC0[0].x, R1.x
> 0022  80802081 60030cfe     2      w: MULADD_IEEE        R0.w,  KC0[1].x, R1.y, PV.w
> 0024  81002082 60030cfe     3      w: MULADD_IEEE        R0.w,  KC0[2].x, R1.z, PV.w
> 0026  01802083 00030cfe     4      x: MULADD_IEEE        R0.x,  KC0[3].x, R1.w, PV.w
> 0028  80002480 60e00110            w: MUL_IEEE           R7.w,  KC0[0].y, R1.x
> 0030  02002084 00e00010     5      x: ADD                R7.x,  KC0[4].x, -R1.x
> 0032  02802484 20e00010            y: ADD                R7.y,  KC0[4].y, -R1.y
> 0034  80802481 60e30cfe            w: MULADD_IEEE        R7.w,  KC0[1].y, R1.y, PV.w
> 0036  80002880 61000110     6      w: MUL_IEEE           R8.w,  KC0[0].z, R1.x
> 0038  00802881 40e30cfe     7      z: MULADD_IEEE        R7.z,  KC0[1].z, R1.y, PV.w
> 0040  80004085 61000110            w: MUL_IEEE           R8.w,  KC0[5].x, R2.x
> 0042  81002482 60e30c07     8      w: MULADD_IEEE        R7.w,  KC0[2].y, R1.z, R7.w
> 0044  01802483 20030cfe     9      y: MULADD_IEEE        R0.y,  KC0[3].y, R1.w, PV.w
> 0046  80804086 60e30c08            w: MULADD_IEEE        R7.w,  KC0[6].x, R2.y, R8.w
> 0048  81002882 61030807    10      w: MULADD_IEEE        R8.w,  KC0[2].z, R1.z, R7.z
> 0050  01802883 40030cfe    11      z: MULADD_IEEE        R0.z,  KC0[3].z, R1.w, PV.w
> 0052  80002c80 61000110            w: MUL_IEEE           R8.w,  KC0[0].w, R1.x
> 0054  81004087 60e30c07    12      w: MULADD_IEEE        R7.w,  KC0[7].x, R2.z, R7.w
> 0056  01804088 40c30cfe    13      z: MULADD_IEEE        R6.z,  KC0[8].x, R2.w, PV.w
> 0058  80004485 60e00110            w: MUL_IEEE           R7.w,  KC0[5].y, R2.x
> 0060  80802c81 61030c08    14      w: MULADD_IEEE        R8.w,  KC0[1].w, R1.y, R8.w
> 0062  03002884 40e00010    15      z: ADD                R7.z,  KC0[4].z, -R1.z
> 0064  81002c82 61030cfe            w: MULADD_IEEE        R8.w,  KC0[2].w, R1.z, PV.w
> 0066  80804486 60e30c07    16      w: MULADD_IEEE        R7.w,  KC0[6].y, R2.y, R7.w
> 0068  81004487 60e30cfe    17      w: MULADD_IEEE        R7.w,  KC0[7].y, R2.z, PV.w
> 0070  00006007 01205f10    18      x: DOT4               R9.x,  R7.x, R3.x
> 0072  00806407 21205f00            y: DOT4               __.y,  R7.y, R3.y
> 0074  01006807 41205f00            z: DOT4               __.z,  R7.z, R3.z
> 0076  801f00f8 61205f00            w: DOT4               __.w,  0, 0
> 0078  81804488 60c30c07    19      w: MULADD_IEEE        R6.w,  KC0[8].y, R2.w, R7.w
> 0080  00008007 01205f00    20      x: DOT4               __.x,  R7.x, R4.x
> 0082  00808407 21205f10            y: DOT4               R9.y,  R7.y, R4.y
> 0084  01008807 41205f00            z: DOT4               __.z,  R7.z, R4.z
> 0086  801f00f8 61205f00            w: DOT4               __.w,  0, 0
> 0088  81802c83 60030c08    21      w: MULADD_IEEE        R0.w,  KC0[3].w, R1.w, R8.w
> 0090  0000a007 01205f00    22      x: DOT4               __.x,  R7.x, R5.x
> 0092  0080a407 21205f00            y: DOT4               __.y,  R7.y, R5.y
> 0094  0100a807 41205f10            z: DOT4               R9.z,  R7.z, R5.z
> 0096  801f00f8 61205f00            w: DOT4               __.w,  0, 0
>0004  c000203c 95000688 EXPORT_DONE        POS   60    R0.xyzw
>0006  c004c000 94c00888 EXPORT             PARAM 0     R9.xyz0
>0008  c0034001 94c0021a EXPORT             PARAM 1     R6.zwxy
>0010  c002c002 94c00888 EXPORT             PARAM 2     R5.xyz0
>0012  c001c003 94c00888 EXPORT             PARAM 3     R3.xyz0
>0014  c0024004 95200888 EXPORT_DONE        PARAM 4     R4.xyz0  EOP
>===== SHADER_END ===============================================================
>
>
>===== SHADER #34 OPT ================================ VS/REDWOOD/EVERGREEN =====
>===== 94 dw ===== 7 gprs ===== 1 stack =========================================
>0000  00000000 84c00000 CALL_FS @0
>0002  40000008 a0980000 ALU 39 @16 KC0[CB0:0-15]
> 0016  00002480 4f800110     1      z: MUL_IEEE           T0.z,  KC0[0].y, R1.x
> 0018  80002080 6fa00110            w: MUL_IEEE           T1.w,  KC0[0].x, R1.x
> 0020  00004085 0fa00110     2      x: MUL_IEEE           T1.x,  KC0[5].x, R2.x
> 0022  00002880 2fa40110            y: MUL_IEEE           T1.y,  KC0[0].z, R1.x         VEC_021
> 0024  00004485 6f800110            w: MUL_IEEE           T0.w,  KC0[5].y, R2.x
> 0026  80002c80 0f840110            t: MUL_IEEE           T0.x,  KC0[0].w, R1.x         SCL_122
> 0028  00802481 4fa3087c     3      z: MULADD_IEEE        T1.z,  KC0[1].y, R1.y, T0.z
> 0030  00802c81 6fc3007c            w: MULADD_IEEE        T2.w,  KC0[1].w, R1.y, T0.x
> 0032  80802081 6fe70c7d            t: MULADD_IEEE        T3.w,  KC0[1].x, R1.y, T1.w   SCL_122
> 0034  02002084 0f800010     4      x: ADD                T0.x,  KC0[4].x, -R1.x
> 0036  02802484 2f800010            y: ADD                T0.y,  KC0[4].y, -R1.y
> 0038  83002884 4f800010            z: ADD                T0.z,  KC0[4].z, -R1.z
> 0040  00804086 0faf007d     5      x: MULADD_IEEE        T1.x,  KC0[6].x, R2.y, T1.x   VEC_102
> 0042  00804486 6f8f0c7c            w: MULADD_IEEE        T0.w,  KC0[6].y, R2.y, T0.w   VEC_102
> 0044  80802881 6fab047d            t: MULADD_IEEE        T1.w,  KC0[1].z, R1.y, T1.y   SCL_212
> 0046  01002c82 2fa30c7e     6      y: MULADD_IEEE        T1.y,  KC0[2].w, R1.z, T2.w
> 0048  01002082 4fb30c7f            z: MULADD_IEEE        T1.z,  KC0[2].x, R1.z, T3.w   VEC_201
> 0050  81002482 6fc3087d            w: MULADD_IEEE        T2.w,  KC0[2].y, R1.z, T1.z
> 0052  0000a07c 00005f00     7      x: DOT4               __.x,  T0.x, R5.x
> 0054  0080a47c 20005f00            y: DOT4               __.y,  T0.y, R5.y
> 0056  0100a87c 40205f10            z: DOT4               R1.z,  T0.z, R5.z
> 0058  001f00f8 60005f00            w: DOT4               __.w,  0, 0
> 0060  81002882 6fa70c7d            t: MULADD_IEEE        T1.w,  KC0[2].z, R1.z, T1.w   SCL_122
> 0062  0000807c 00005f00     8      x: DOT4               __.x,  T0.x, R4.x
> 0064  0080847c 20205f10            y: DOT4               R1.y,  T0.y, R4.y
> 0066  0100887c 40005f00            z: DOT4               __.z,  T0.z, R4.z
> 0068  001f00f8 60005f00            w: DOT4               __.w,  0, 0
> 0070  81004487 6f870c7c            t: MULADD_IEEE        T0.w,  KC0[7].y, R2.z, T0.w   SCL_122
> 0072  0000607c 00205f10     9      x: DOT4               R1.x,  T0.x, R3.x
> 0074  0080647c 20005f00            y: DOT4               __.y,  T0.y, R3.y
> 0076  0100687c 40005f00            z: DOT4               __.z,  T0.z, R3.z
> 0078  001f00f8 60005f00            w: DOT4               __.w,  0, 0
> 0080  81004087 0f87007d            t: MULADD_IEEE        T0.x,  KC0[7].x, R2.z, T1.x   SCL_122
> 0082  01802483 20030c7e    10      y: MULADD_IEEE        R0.y,  KC0[3].y, R1.w, T2.w
> 0084  01802883 40170c7d            z: MULADD_IEEE        R0.z,  KC0[3].z, R1.w, T1.w   VEC_210
> 0086  81802c83 6003047d            w: MULADD_IEEE        R0.w,  KC0[3].w, R1.w, T1.y
> 0088  01802083 000f087d    11      x: MULADD_IEEE        R0.x,  KC0[3].x, R1.w, T1.z   VEC_102
> 0090  01804088 40c3007c            z: MULADD_IEEE        R6.z,  KC0[8].x, R2.w, T0.x
> 0092  81804488 60c30c7c            w: MULADD_IEEE        R6.w,  KC0[8].y, R2.w, T0.w
>0004  c0034001 94c0021a EXPORT             PARAM 1     R6.zwxy
>0006  c000203c 95000688 EXPORT_DONE        POS   60    R0.xyzw
>0008  c000c000 94c00888 EXPORT             PARAM 0     R1.xyz0
>0010  c002c002 94c00888 EXPORT             PARAM 2     R5.xyz0
>0012  c0024004 94c00888 EXPORT             PARAM 4     R4.xyz0
>0014  c001c003 95200888 EXPORT_DONE        PARAM 3     R3.xyz0  EOP
>===== SHADER_END ===============================================================
>
>--------------------------------------------------------------
>FRAG
>DCL IN[0], GENERIC[9], PERSPECTIVE
>DCL IN[1], GENERIC[10], PERSPECTIVE
>DCL IN[2], GENERIC[11], PERSPECTIVE
>DCL IN[3], GENERIC[12], PERSPECTIVE
>DCL IN[4], GENERIC[13], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SAMP[1]
>DCL SAMP[2]
>DCL SAMP[3]
>DCL SAMP[4]
>DCL SVIEW[0], 2D, FLOAT
>DCL SVIEW[1], 2D, FLOAT
>DCL SVIEW[2], 2D, FLOAT
>DCL SVIEW[3], 2D, FLOAT
>DCL SVIEW[4], 2D, FLOAT
>DCL CONST[5..9]
>DCL TEMP[0..7], LOCAL
>IMM[0] FLT32 {   -0.5000,     2.0000,    -1.0000,     0.0000}
>IMM[1] FLT32 {    1.0000,     0.2500,     0.0000,     0.0000}
>  0: MOV TEMP[0].xy, IN[1].xyyy
>  1: TEX TEMP[0], TEMP[0], SAMP[1], 2D
>  2: MUL TEMP[1].x, TEMP[0].wwww, CONST[9].xxxx
>  3: MOV TEMP[1].w, TEMP[1].xxxx
>  4: MOV TEMP[2].xy, IN[1].xyyy
>  5: TEX TEMP[2].xyz, TEMP[2], SAMP[0], 2D
>  6: ADD TEMP[2].xyz, TEMP[2].xyzz, IMM[0].xxxx
>  7: DP3 TEMP[3].x, TEMP[2].xyzz, TEMP[2].xyzz
>  8: RSQ TEMP[3].x, TEMP[3].xxxx
>  9: MUL TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xxxx
> 10: MOV TEMP[3].xy, IN[1].xyyy
> 11: TEX TEMP[3], TEMP[3], SAMP[2], 2D
> 12: MOV TEMP[4].xy, IN[1].zwww
> 13: TEX TEMP[4].xyz, TEMP[4], SAMP[4], 2D
> 14: MAD TEMP[4].xyz, TEMP[4].xyzz, IMM[0].yyyy, IMM[0].zzzz
> 15: DP3 TEMP[5].x, TEMP[4].xyzz, IN[3].xyzz
> 16: DP3 TEMP[6].x, TEMP[4].xyzz, IN[4].xyzz
> 17: MOV TEMP[5].y, TEMP[6].xxxx
> 18: DP3 TEMP[4].x, TEMP[4].xyzz, IN[2].xyzz
> 19: MOV TEMP[5].z, TEMP[4].xxxx
> 20: DP3 TEMP[4].x, TEMP[5].xyzz, TEMP[5].xyzz
> 21: RSQ TEMP[4].x, TEMP[4].xxxx
> 22: MUL TEMP[4].xyz, TEMP[5].xyzz, TEMP[4].xxxx
> 23: MUL TEMP[5].xyz, TEMP[3].xyzz, CONST[7].xyzz
> 24: DP3 TEMP[6].x, TEMP[2].xyzz, TEMP[4].xyzz
> 25: MUL TEMP[6].xyz, TEMP[6].xxxx, TEMP[2].xyzz
> 26: MUL TEMP[6].xyz, IMM[0].yyyy, TEMP[6].xyzz
> 27: ADD TEMP[6].xyz, TEMP[4].xyzz, -TEMP[6].xyzz
> 28: DP3 TEMP[7].x, IN[0].xyzz, IN[0].xyzz
> 29: RSQ TEMP[7].x, TEMP[7].xxxx
> 30: MUL TEMP[7].xyz, IN[0].xyzz, TEMP[7].xxxx
> 31: DP3 TEMP[6].x, TEMP[6].xyzz, TEMP[7].xyzz
> 32: MAX TEMP[6].x, -TEMP[6].xxxx, IMM[0].wwww
> 33: MAD TEMP[3].x, CONST[8].xxxx, TEMP[3].wwww, IMM[1].xxxx
> 34: POW TEMP[3].x, TEMP[6].xxxx, TEMP[3].xxxx
> 35: MUL TEMP[6].xyz, TEMP[0].xyzz, CONST[6].xyzz
> 36: DP3 TEMP[2].x, TEMP[2].xyzz, TEMP[4].xyzz
> 37: MAX TEMP[2].x, TEMP[2].xxxx, IMM[0].wwww
> 38: MUL TEMP[2].xyz, TEMP[6].xyzz, TEMP[2].xxxx
> 39: MAD TEMP[2].xyz, TEMP[5].xyzz, TEMP[3].xxxx, TEMP[2].xyzz
> 40: MOV TEMP[3].xy, IN[1].zwww
> 41: TEX TEMP[3].xyz, TEMP[3], SAMP[3], 2D
> 42: MAX TEMP[4].x, IMM[1].yyyy, TEMP[4].zzzz
> 43: RCP TEMP[4].x, TEMP[4].xxxx
> 44: MUL TEMP[3].xyz, TEMP[3].xyzz, TEMP[4].xxxx
> 45: MUL TEMP[0].xyz, TEMP[0].xyzz, CONST[5].xyzz
> 46: MAD TEMP[1].xyz, TEMP[2].xyzz, TEMP[3].xyzz, TEMP[0].xyzz
> 47: MOV OUT[0], TEMP[1]
> 48: END
>; ModuleID = 'tgsi'
>
>define void @main(<4 x float> inreg, <4 x float> inreg, <4 x float> inreg, <4 x float> inreg, <4 x float> inreg, <4 x float> inreg) #0 {
>main_body:
>  %6 = extractelement <4 x float> %0, i32 0
>  %7 = extractelement <4 x float> %0, i32 1
>  %8 = call <2 x float> @llvm.R600.interp.xy(i32 0, float %6, float %7)
>  %9 = call <2 x float> @llvm.R600.interp.zw(i32 0, float %6, float %7)
>  %10 = extractelement <2 x float> %8, i32 0
>  %11 = extractelement <2 x float> %8, i32 1
>  %12 = extractelement <2 x float> %9, i32 0
>  %13 = extractelement <4 x float> %0, i32 0
>  %14 = extractelement <4 x float> %0, i32 1
>  %15 = call <2 x float> @llvm.R600.interp.xy(i32 1, float %13, float %14)
>  %16 = call <2 x float> @llvm.R600.interp.zw(i32 1, float %13, float %14)
>  %17 = extractelement <4 x float> %0, i32 0
>  %18 = extractelement <4 x float> %0, i32 1
>  %19 = call <2 x float> @llvm.R600.interp.xy(i32 2, float %17, float %18)
>  %20 = call <2 x float> @llvm.R600.interp.zw(i32 2, float %17, float %18)
>  %21 = extractelement <2 x float> %19, i32 0
>  %22 = extractelement <2 x float> %19, i32 1
>  %23 = extractelement <2 x float> %20, i32 0
>  %24 = extractelement <4 x float> %0, i32 0
>  %25 = extractelement <4 x float> %0, i32 1
>  %26 = call <2 x float> @llvm.R600.interp.xy(i32 3, float %24, float %25)
>  %27 = call <2 x float> @llvm.R600.interp.zw(i32 3, float %24, float %25)
>  %28 = extractelement <2 x float> %26, i32 0
>  %29 = extractelement <2 x float> %26, i32 1
>  %30 = extractelement <2 x float> %27, i32 0
>  %31 = extractelement <4 x float> %0, i32 0
>  %32 = extractelement <4 x float> %0, i32 1
>  %33 = call <2 x float> @llvm.R600.interp.xy(i32 4, float %31, float %32)
>  %34 = call <2 x float> @llvm.R600.interp.zw(i32 4, float %31, float %32)
>  %35 = extractelement <2 x float> %33, i32 0
>  %36 = extractelement <2 x float> %33, i32 1
>  %37 = extractelement <2 x float> %34, i32 0
>  %38 = shufflevector <2 x float> %15, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
>  %39 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %38, i32 17, i32 1, i32 2)
>  %40 = extractelement <4 x float> %39, i32 0
>  %41 = extractelement <4 x float> %39, i32 1
>  %42 = extractelement <4 x float> %39, i32 2
>  %43 = extractelement <4 x float> %39, i32 3
>  %44 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9)
>  %45 = extractelement <4 x float> %44, i32 0
>  %46 = fmul float %43, %45
>  %47 = shufflevector <2 x float> %15, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
>  %48 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %47, i32 16, i32 0, i32 2)
>  %49 = extractelement <4 x float> %48, i32 0
>  %50 = extractelement <4 x float> %48, i32 1
>  %51 = extractelement <4 x float> %48, i32 2
>  %52 = fadd float %49, -5.000000e-01
>  %53 = fadd float %50, -5.000000e-01
>  %54 = fadd float %51, -5.000000e-01
>  %55 = insertelement <4 x float> undef, float %52, i32 0
>  %56 = insertelement <4 x float> %55, float %53, i32 1
>  %57 = insertelement <4 x float> %56, float %54, i32 2
>  %58 = insertelement <4 x float> %57, float 0.000000e+00, i32 3
>  %59 = insertelement <4 x float> undef, float %52, i32 0
>  %60 = insertelement <4 x float> %59, float %53, i32 1
>  %61 = insertelement <4 x float> %60, float %54, i32 2
>  %62 = insertelement <4 x float> %61, float 0.000000e+00, i32 3
>  %63 = call float @llvm.AMDGPU.dp4(<4 x float> %58, <4 x float> %62)
>  %64 = call float @llvm.AMDGPU.rsq.clamped.f32(float %63)
>  %65 = fmul float %52, %64
>  %66 = fmul float %53, %64
>  %67 = fmul float %54, %64
>  %68 = shufflevector <2 x float> %15, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
>  %69 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %68, i32 18, i32 2, i32 2)
>  %70 = extractelement <4 x float> %69, i32 0
>  %71 = extractelement <4 x float> %69, i32 1
>  %72 = extractelement <4 x float> %69, i32 2
>  %73 = extractelement <4 x float> %69, i32 3
>  %74 = shufflevector <2 x float> %16, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
>  %75 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %74, i32 20, i32 4, i32 2)
>  %76 = extractelement <4 x float> %75, i32 0
>  %77 = extractelement <4 x float> %75, i32 1
>  %78 = extractelement <4 x float> %75, i32 2
>  %79 = fmul float %76, 2.000000e+00
>  %80 = fadd float %79, -1.000000e+00
>  %81 = fmul float %77, 2.000000e+00
>  %82 = fadd float %81, -1.000000e+00
>  %83 = fmul float %78, 2.000000e+00
>  %84 = fadd float %83, -1.000000e+00
>  %85 = insertelement <4 x float> undef, float %80, i32 0
>  %86 = insertelement <4 x float> %85, float %82, i32 1
>  %87 = insertelement <4 x float> %86, float %84, i32 2
>  %88 = insertelement <4 x float> %87, float 0.000000e+00, i32 3
>  %89 = insertelement <4 x float> undef, float %28, i32 0
>  %90 = insertelement <4 x float> %89, float %29, i32 1
>  %91 = insertelement <4 x float> %90, float %30, i32 2
>  %92 = insertelement <4 x float> %91, float 0.000000e+00, i32 3
>  %93 = call float @llvm.AMDGPU.dp4(<4 x float> %88, <4 x float> %92)
>  %94 = insertelement <4 x float> undef, float %80, i32 0
>  %95 = insertelement <4 x float> %94, float %82, i32 1
>  %96 = insertelement <4 x float> %95, float %84, i32 2
>  %97 = insertelement <4 x float> %96, float 0.000000e+00, i32 3
>  %98 = insertelement <4 x float> undef, float %35, i32 0
>  %99 = insertelement <4 x float> %98, float %36, i32 1
>  %100 = insertelement <4 x float> %99, float %37, i32 2
>  %101 = insertelement <4 x float> %100, float 0.000000e+00, i32 3
>  %102 = call float @llvm.AMDGPU.dp4(<4 x float> %97, <4 x float> %101)
>  %103 = insertelement <4 x float> undef, float %80, i32 0
>  %104 = insertelement <4 x float> %103, float %82, i32 1
>  %105 = insertelement <4 x float> %104, float %84, i32 2
>  %106 = insertelement <4 x float> %105, float 0.000000e+00, i32 3
>  %107 = insertelement <4 x float> undef, float %21, i32 0
>  %108 = insertelement <4 x float> %107, float %22, i32 1
>  %109 = insertelement <4 x float> %108, float %23, i32 2
>  %110 = insertelement <4 x float> %109, float 0.000000e+00, i32 3
>  %111 = call float @llvm.AMDGPU.dp4(<4 x float> %106, <4 x float> %110)
>  %112 = insertelement <4 x float> undef, float %93, i32 0
>  %113 = insertelement <4 x float> %112, float %102, i32 1
>  %114 = insertelement <4 x float> %113, float %111, i32 2
>  %115 = insertelement <4 x float> %114, float 0.000000e+00, i32 3
>  %116 = insertelement <4 x float> undef, float %93, i32 0
>  %117 = insertelement <4 x float> %116, float %102, i32 1
>  %118 = insertelement <4 x float> %117, float %111, i32 2
>  %119 = insertelement <4 x float> %118, float 0.000000e+00, i32 3
>  %120 = call float @llvm.AMDGPU.dp4(<4 x float> %115, <4 x float> %119)
>  %121 = call float @llvm.AMDGPU.rsq.clamped.f32(float %120)
>  %122 = fmul float %93, %121
>  %123 = fmul float %102, %121
>  %124 = fmul float %111, %121
>  %125 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7)
>  %126 = extractelement <4 x float> %125, i32 0
>  %127 = fmul float %70, %126
>  %128 = extractelement <4 x float> %125, i32 1
>  %129 = fmul float %71, %128
>  %130 = extractelement <4 x float> %125, i32 2
>  %131 = fmul float %72, %130
>  %132 = insertelement <4 x float> undef, float %65, i32 0
>  %133 = insertelement <4 x float> %132, float %66, i32 1
>  %134 = insertelement <4 x float> %133, float %67, i32 2
>  %135 = insertelement <4 x float> %134, float 0.000000e+00, i32 3
>  %136 = insertelement <4 x float> undef, float %122, i32 0
>  %137 = insertelement <4 x float> %136, float %123, i32 1
>  %138 = insertelement <4 x float> %137, float %124, i32 2
>  %139 = insertelement <4 x float> %138, float 0.000000e+00, i32 3
>  %140 = call float @llvm.AMDGPU.dp4(<4 x float> %135, <4 x float> %139)
>  %141 = fmul float %140, %65
>  %142 = fmul float %140, %66
>  %143 = fmul float %140, %67
>  %144 = fmul float %141, 2.000000e+00
>  %145 = fmul float %142, 2.000000e+00
>  %146 = fmul float %143, 2.000000e+00
>  %147 = fsub float %122, %144
>  %148 = fsub float %123, %145
>  %149 = fsub float %124, %146
>  %150 = insertelement <4 x float> undef, float %10, i32 0
>  %151 = insertelement <4 x float> %150, float %11, i32 1
>  %152 = insertelement <4 x float> %151, float %12, i32 2
>  %153 = insertelement <4 x float> %152, float 0.000000e+00, i32 3
>  %154 = insertelement <4 x float> undef, float %10, i32 0
>  %155 = insertelement <4 x float> %154, float %11, i32 1
>  %156 = insertelement <4 x float> %155, float %12, i32 2
>  %157 = insertelement <4 x float> %156, float 0.000000e+00, i32 3
>  %158 = call float @llvm.AMDGPU.dp4(<4 x float> %153, <4 x float> %157)
>  %159 = call float @llvm.AMDGPU.rsq.clamped.f32(float %158)
>  %160 = fmul float %10, %159
>  %161 = fmul float %11, %159
>  %162 = fmul float %12, %159
>  %163 = insertelement <4 x float> undef, float %147, i32 0
>  %164 = insertelement <4 x float> %163, float %148, i32 1
>  %165 = insertelement <4 x float> %164, float %149, i32 2
>  %166 = insertelement <4 x float> %165, float 0.000000e+00, i32 3
>  %167 = insertelement <4 x float> undef, float %160, i32 0
>  %168 = insertelement <4 x float> %167, float %161, i32 1
>  %169 = insertelement <4 x float> %168, float %162, i32 2
>  %170 = insertelement <4 x float> %169, float 0.000000e+00, i32 3
>  %171 = call float @llvm.AMDGPU.dp4(<4 x float> %166, <4 x float> %170)
>  %172 = fsub float -0.000000e+00, %171
>  %173 = fcmp ule float %171, -0.000000e+00
>  %174 = select i1 %173, float %172, float 0.000000e+00
>  %175 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8)
>  %176 = extractelement <4 x float> %175, i32 0
>  %177 = fmul float %176, %73
>  %178 = fadd float %177, 1.000000e+00
>  %179 = call float @llvm.pow.f32(float %174, float %178)
>  %180 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6)
>  %181 = extractelement <4 x float> %180, i32 0
>  %182 = fmul float %40, %181
>  %183 = extractelement <4 x float> %180, i32 1
>  %184 = fmul float %41, %183
>  %185 = extractelement <4 x float> %180, i32 2
>  %186 = fmul float %42, %185
>  %187 = insertelement <4 x float> undef, float %65, i32 0
>  %188 = insertelement <4 x float> %187, float %66, i32 1
>  %189 = insertelement <4 x float> %188, float %67, i32 2
>  %190 = insertelement <4 x float> %189, float 0.000000e+00, i32 3
>  %191 = insertelement <4 x float> undef, float %122, i32 0
>  %192 = insertelement <4 x float> %191, float %123, i32 1
>  %193 = insertelement <4 x float> %192, float %124, i32 2
>  %194 = insertelement <4 x float> %193, float 0.000000e+00, i32 3
>  %195 = call float @llvm.AMDGPU.dp4(<4 x float> %190, <4 x float> %194)
>  %.inv = fcmp olt float %195, 0.000000e+00
>  %196 = select i1 %.inv, float 0.000000e+00, float %195
>  %197 = fmul float %182, %196
>  %198 = fmul float %184, %196
>  %199 = fmul float %186, %196
>  %200 = fmul float %127, %179
>  %201 = fadd float %200, %197
>  %202 = fmul float %129, %179
>  %203 = fadd float %202, %198
>  %204 = fmul float %131, %179
>  %205 = fadd float %204, %199
>  %206 = shufflevector <2 x float> %16, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
>  %207 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %206, i32 19, i32 3, i32 2)
>  %208 = extractelement <4 x float> %207, i32 0
>  %209 = extractelement <4 x float> %207, i32 1
>  %210 = extractelement <4 x float> %207, i32 2
>  %.inv32 = fcmp ogt float %124, 2.500000e-01
>  %.op = fdiv float 1.000000e+00, %124
>  %211 = select i1 %.inv32, float %.op, float 4.000000e+00
>  %212 = fmul float %208, %211
>  %213 = fmul float %209, %211
>  %214 = fmul float %210, %211
>  %215 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5)
>  %216 = extractelement <4 x float> %215, i32 0
>  %217 = fmul float %40, %216
>  %218 = extractelement <4 x float> %215, i32 1
>  %219 = fmul float %41, %218
>  %220 = extractelement <4 x float> %215, i32 2
>  %221 = fmul float %42, %220
>  %222 = fmul float %201, %212
>  %223 = fadd float %222, %217
>  %224 = fmul float %203, %213
>  %225 = fadd float %224, %219
>  %226 = fmul float %205, %214
>  %227 = fadd float %226, %221
>  %228 = insertelement <4 x float> undef, float %223, i32 0
>  %229 = insertelement <4 x float> %228, float %225, i32 1
>  %230 = insertelement <4 x float> %229, float %227, i32 2
>  %231 = insertelement <4 x float> %230, float %46, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %231, i32 0, i32 0)
>  ret void
>}
>
>; Function Attrs: readnone
>declare <2 x float> @llvm.R600.interp.xy(i32, float, float) #1
>
>; Function Attrs: readnone
>declare <2 x float> @llvm.R600.interp.zw(i32, float, float) #1
>
>; Function Attrs: readnone
>declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32, i32) #1
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.AMDGPU.rsq.clamped.f32(float) #2
>
>; Function Attrs: nounwind readnone
>declare float @llvm.pow.f32(float, float) #2
>
>declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { readnone }
>attributes #2 = { nounwind readnone }
>
>===== SHADER #35 ==================================== PS/REDWOOD/EVERGREEN =====
>===== 314 dw ===== 10 gprs ===== 0 stack =======================================
>0000  00000012 a0440000 ALU 18 @36
> 0036  00380400 00346b10     1      x: INTERP_XY          R1.x,  R0.y, Param0.x         VEC_210
> 0038  00380000 20346b10            y: INTERP_XY          R1.y,  R0.x, Param0.x         VEC_210
> 0040  00380400 40146b00            z: INTERP_XY          __.z,  R0.y, Param0.x         VEC_210
> 0042  80380000 60146b00            w: INTERP_XY          __.w,  R0.x, Param0.x         VEC_210
> 0044  00380400 00146b80     2      x: INTERP_ZW          __.x,  R0.y, Param0.x         VEC_210
> 0046  00380000 20146b80            y: INTERP_ZW          __.y,  R0.x, Param0.x         VEC_210
> 0048  00380400 40346b90            z: INTERP_ZW          R1.z,  R0.y, Param0.x         VEC_210
> 0050  80380000 60346b90            w: INTERP_ZW          R1.w,  R0.x, Param0.x         VEC_210
> 0052  00382400 00546b10     3      x: INTERP_XY          R2.x,  R0.y, Param1.x         VEC_210
> 0054  00382000 20546b10            y: INTERP_XY          R2.y,  R0.x, Param1.x         VEC_210
> 0056  00382400 40146b00            z: INTERP_XY          __.z,  R0.y, Param1.x         VEC_210
> 0058  80382000 60146b00            w: INTERP_XY          __.w,  R0.x, Param1.x         VEC_210
> 0060  00382400 00146b80     4      x: INTERP_ZW          __.x,  R0.y, Param1.x         VEC_210
> 0062  00382000 20146b80            y: INTERP_ZW          __.y,  R0.x, Param1.x         VEC_210
> 0064  00382400 40746b90            z: INTERP_ZW          R3.z,  R0.y, Param1.x         VEC_210
> 0066  80382000 60346b90            w: INTERP_ZW          R1.w,  R0.x, Param1.x         VEC_210
> 0068  000008fe 00600c90     5      x: MOV                R3.x,  PV.z
> 0070  80000cfe 20600c90            y: MOV                R3.y,  PV.w
>0002  00000008 80400400 TEX 2 @16
> 0016  00021010 f00d1004 fc800000 SAMPLE              R4.xyzw, R2.xy__,   RID:16, SID:0 CT:NNNN
> 0020  00031410 f00d1005 fc820000 SAMPLE              R5.xyzw, R3.xy__,   RID:20, SID:4 CT:NNNN
>0004  00000024 a0180000 ALU 7 @72
> 0072  8100a805 60200010     6      w: ADD                R1.w,  R5.z, R5.z
> 0074  001fa004 00c00010     7      x: ADD                R6.x,  R4.x, [0xbf000000 -0.5].x
> 0076  001fa404 20c00010            y: ADD                R6.y,  R4.y, [0xbf000000 -0.5].x
> 0078  001fa804 40800010            z: ADD                R4.z,  R4.z, [0xbf000000 -0.5].x
> 0080  0080a405 60880010            w: ADD                R4.w,  R5.y, R5.y             VEC_120
> 0082  8000a005 60a00010            t: ADD                R5.w,  R5.x, R5.x
> 0084  bf000000 
>0006  0000000c 80400800 TEX 3 @24
> 0024  00031310 f00d1003 fc818000 SAMPLE              R3.xyzw, R3.xy__,   RID:19, SID:3 CT:NNNN
> 0028  00021210 f00d1007 fc810000 SAMPLE              R7.xyzw, R2.xy__,   RID:18, SID:2 CT:NNNN
> 0032  00021110 f00d1002 fc808000 SAMPLE              R2.xyzw, R2.xy__,   RID:17, SID:1 CT:NNNN
>0008  8000002b a1c40000 ALU 114 @86 KC0[CB0:0-31]
> 0086  001fac05 00800010     8      x: ADD                R4.x,  R5.w, [0xbf800000 -1].x
> 0088  001fac04 20880010            y: ADD                R4.y,  R4.w, [0xbf800000 -1].x  VEC_120
> 0090  801fac01 40b00010            z: ADD                R5.z,  R1.w, [0xbf800000 -1].x  VEC_201
> 0092  bf800000 
> 0094  00384400 00b46b10     9      x: INTERP_XY          R5.x,  R0.y, Param2.x         VEC_210
> 0096  00384000 20b46b10            y: INTERP_XY          R5.y,  R0.x, Param2.x         VEC_210
> 0098  00384400 40146b00            z: INTERP_XY          __.z,  R0.y, Param2.x         VEC_210
> 0100  80384000 60146b00            w: INTERP_XY          __.w,  R0.x, Param2.x         VEC_210
> 0102  00384400 00146b80    10      x: INTERP_ZW          __.x,  R0.y, Param2.x         VEC_210
> 0104  00384000 20146b80            y: INTERP_ZW          __.y,  R0.x, Param2.x         VEC_210
> 0106  00384400 40d46b90            z: INTERP_ZW          R6.z,  R0.y, Param2.x         VEC_210
> 0108  80384000 60346b90            w: INTERP_ZW          R1.w,  R0.x, Param2.x         VEC_210
> 0110  00386400 01146b10    11      x: INTERP_XY          R8.x,  R0.y, Param3.x         VEC_210
> 0112  00386000 21146b10            y: INTERP_XY          R8.y,  R0.x, Param3.x         VEC_210
> 0114  00386400 40146b00            z: INTERP_XY          __.z,  R0.y, Param3.x         VEC_210
> 0116  80386000 60146b00            w: INTERP_XY          __.w,  R0.x, Param3.x         VEC_210
> 0118  00386400 00146b80    12      x: INTERP_ZW          __.x,  R0.y, Param3.x         VEC_210
> 0120  00386000 20146b80            y: INTERP_ZW          __.y,  R0.x, Param3.x         VEC_210
> 0122  00386400 41146b90            z: INTERP_ZW          R8.z,  R0.y, Param3.x         VEC_210
> 0124  80386000 60346b90            w: INTERP_ZW          R1.w,  R0.x, Param3.x         VEC_210
> 0126  00010004 01005f10    13      x: DOT4               R8.x,  R4.x, R8.x
> 0128  00810404 21005f00            y: DOT4               __.y,  R4.y, R8.y
> 0130  01010805 41005f00            z: DOT4               __.z,  R5.z, R8.z
> 0132  801f00f8 61005f00            w: DOT4               __.w,  0, 0
> 0134  00388400 01346b10    14      x: INTERP_XY          R9.x,  R0.y, Param4.x         VEC_210
> 0136  00388000 21146b10            y: INTERP_XY          R8.y,  R0.x, Param4.x         VEC_210
> 0138  00388400 40146b00            z: INTERP_XY          __.z,  R0.y, Param4.x         VEC_210
> 0140  80388000 60146b00            w: INTERP_XY          __.w,  R0.x, Param4.x         VEC_210
> 0142  00388400 00146b80    15      x: INTERP_ZW          __.x,  R0.y, Param4.x         VEC_210
> 0144  00388000 20146b80            y: INTERP_ZW          __.y,  R0.x, Param4.x         VEC_210
> 0146  00388400 40146b90            z: INTERP_ZW          R0.z,  R0.y, Param4.x         VEC_210
> 0148  80388000 60146b90            w: INTERP_ZW          R0.w,  R0.x, Param4.x         VEC_210
> 0150  00012004 00005f00    16      x: DOT4               __.x,  R4.x, R9.x
> 0152  00810404 20005f10            y: DOT4               R0.y,  R4.y, R8.y
> 0154  01000805 40005f00            z: DOT4               __.z,  R5.z, R0.z
> 0156  801f00f8 60005f00            w: DOT4               __.w,  0, 0
> 0158  0000a004 00005f00    17      x: DOT4               __.x,  R4.x, R5.x
> 0160  0080a404 20005f00            y: DOT4               __.y,  R4.y, R5.y
> 0162  0100c805 40005f10            z: DOT4               R0.z,  R5.z, R6.z
> 0164  801f00f8 60005f00            w: DOT4               __.w,  0, 0
> 0166  0000c006 00005f10    18      x: DOT4               R0.x,  R6.x, R6.x
> 0168  0080c406 20005f00            y: DOT4               __.y,  R6.y, R6.y
> 0170  01008804 40005f00            z: DOT4               __.z,  R4.z, R4.z
> 0172  801f00f8 60005f00            w: DOT4               __.w,  0, 0
> 0174  800000fe 00004390    19      t: RECIPSQRT_CLAMPED  R0.x,  PV.x
> 0176  00010008 00005f00    20      x: DOT4               __.x,  R8.x, R8.x
> 0178  00800400 20005f00            y: DOT4               __.y,  R0.y, R0.y
> 0180  01000800 40005f00            z: DOT4               __.z,  R0.z, R0.z
> 0182  801f00f8 60005f10            w: DOT4               R0.w,  0, 0
> 0184  800000fe 60004390    21      t: RECIPSQRT_CLAMPED  R0.w,  PV.x
> 0186  001fe008 00800110    22      x: MUL_IEEE           R4.x,  R8.x, PS
> 0188  00000406 20800110            y: MUL_IEEE           R4.y,  R6.y, R0.x
> 0190  001fe800 40a00110            z: MUL_IEEE           R5.z,  R0.z, PS
> 0192  80000006 00a00110            t: MUL_IEEE           R5.x,  R6.x, R0.x
> 0194  01800400 20a00110    23      y: MUL_IEEE           R5.y,  R0.y, R0.w
> 0196  80000804 40800110            z: MUL_IEEE           R4.z,  R4.z, R0.x
> 0198  00008005 00005f10    24      x: DOT4               R0.x,  R5.x, R4.x
> 0200  0080a404 20005f00            y: DOT4               __.y,  R4.y, R5.y
> 0202  0100a804 40005f00            z: DOT4               __.z,  R4.z, R5.z
> 0204  801f00f8 60005f00            w: DOT4               __.w,  0, 0
> 0206  008080fe 60200110    25      w: MUL_IEEE           R1.w,  PV.x, R4.y
> 0208  810080fe 60800110            t: MUL_IEEE           R4.w,  PV.x, R4.z
> 0210  01008000 408300ff    26      z: MULADD_IEEE        R4.z,  R0.x, R4.z, PS
> 0212  00808000 60230cfe            w: MULADD_IEEE        R1.w,  R0.x, R4.y, PV.w
> 0214  8000a000 60800110            t: MUL_IEEE           R4.w,  R0.x, R5.x
> 0216  8000a000 608300ff    27      w: MULADD_IEEE        R4.w,  R0.x, R5.x, PS
> 0218  00002001 00805f10    28      x: DOT4               R4.x,  R1.x, R1.x
> 0220  00802401 20805f00            y: DOT4               __.y,  R1.y, R1.y
> 0222  01002801 40805f00            z: DOT4               __.z,  R1.z, R1.z
> 0224  801f00f8 60805f00            w: DOT4               __.w,  0, 0
> 0226  01800008 00a31c04    29      x: MULADD_IEEE        R5.x,  R8.x, R0.w, -R4.w
> 0228  01800400 20171c01            y: MULADD_IEEE        R0.y,  R0.y, R0.w, -R1.w      VEC_210
> 0230  01800800 40031804            z: MULADD_IEEE        R0.z,  R0.z, R0.w, -R4.z
> 0232  800000fe 60004390            t: RECIPSQRT_CLAMPED  R0.w,  PV.x
> 0234  001fe001 00200110    30      x: MUL_IEEE           R1.x,  R1.x, PS
> 0236  001fe401 20200110            y: MUL_IEEE           R1.y,  R1.y, PS
> 0238  801fe801 40200110            z: MUL_IEEE           R1.z,  R1.z, PS
> 0240  00002005 00005f00    31      x: DOT4               __.x,  R5.x, R1.x
> 0242  00802400 20005f10            y: DOT4               R0.y,  R0.y, R1.y
> 0244  01002800 40005f00            z: DOT4               __.z,  R0.z, R1.z
> 0246  801f00f8 60005f00            w: DOT4               __.w,  0, 0
> 0248  001f00fe 400350fe    32      z: CNDGT              R0.z,  PV.x, 0, -PV.x
> 0250  000000f8 60000190            w: MAX                R0.w,  0, R0.x
> 0252  8110c802 60200110            t: MUL_IEEE           R1.w,  R2.z, KC0[6].z
> 0254  019fc0ff 40200110    33      z: MUL_IEEE           R1.z,  PS, PV.w
> 0256  0180e088 602300f9            w: MULADD_IEEE        R1.w,  KC0[8].x, R7.w, 1.0
> 0258  800008fe 00004190            t: LOG_IEEE           R0.x,  PV.z
> 0260  001fecfe 00000090    34      x: MUL                R0.x,  PV.w, PS
> 0262  0010c002 20000110            y: MUL_IEEE           R0.y,  R2.x, KC0[6].x
> 0264  001fa805 40000490            z: SETGT              R0.z,  R5.z, [0x3e800000 0.25].x
> 0266  0090c402 60200110            w: MUL_IEEE           R1.w,  R2.y, KC0[6].y
> 0268  80000805 00204310            t: RECIP_IEEE         R1.x,  R5.z
> 0270  3e800000 
> 0272  01800cfe 00800110    35      x: MUL_IEEE           R4.x,  PV.w, R0.w
> 0274  001fa8fe 202320ff            y: CNDE               R1.y,  PV.z, [0x40800000 4].x, PS
> 0276  018004fe 40000110            z: MUL_IEEE           R0.z,  PV.y, R0.w
> 0278  0010e007 60000110            w: MUL_IEEE           R0.w,  R7.x, KC0[7].x
> 0280  800000fe 00004090            t: EXP_IEEE           R0.x,  PV.x
> 0282  40800000 
> 0284  0090e407 00200110    36      x: MUL_IEEE           R1.x,  R7.y, KC0[7].y
> 0286  001fecfe 200308fe            y: MULADD_IEEE        R0.y,  PV.w, PS, PV.z
> 0288  009fc003 40000110            z: MUL_IEEE           R0.z,  R3.x, PV.y
> 0290  8010a002 60080110            w: MUL_IEEE           R0.w,  R2.x, KC0[5].x         VEC_120
> 0292  80112c02 60a00110    37      w: MUL_IEEE           R5.w,  R2.w, KC0[9].x
> 0294  01000400 00a30c00    38      x: MULADD_IEEE        R5.x,  R0.y, R0.z, R0.w
> 0296  0110e807 20000110            y: MUL_IEEE           R0.y,  R7.z, KC0[7].z
> 0298  00000001 40030004            z: MULADD_IEEE        R0.z,  R1.x, R0.x, R4.x
> 0300  80802403 60080110            w: MUL_IEEE           R0.w,  R3.y, R1.y             VEC_120
> 0302  8090a402 60200110    39      w: MUL_IEEE           R1.w,  R2.y, KC0[5].y
> 0304  01800800 20a30cfe    40      y: MULADD_IEEE        R5.y,  R0.z, R0.w, PV.w
> 0306  00000400 40030801            z: MULADD_IEEE        R0.z,  R0.y, R0.x, R1.z
> 0308  80802803 60080110            w: MUL_IEEE           R0.w,  R3.z, R1.y             VEC_120
> 0310  8110a802 60200110    41      w: MUL_IEEE           R1.w,  R2.z, KC0[5].z
> 0312  81800800 40a30cfe    42      z: MULADD_IEEE        R5.z,  R0.z, R0.w, PV.w
>0010  c0028000 95200688 EXPORT_DONE        PIXEL 0     R5.xyzw  EOP
>===== SHADER_END ===============================================================
>
>
>===== SHADER #35 OPT ================================ PS/REDWOOD/EVERGREEN =====
>===== 308 dw ===== 6 gprs ===== 0 stack ========================================
>0000  00000005 a01c0000 ALU 8 @10
> 0010  00382400 00146b80     1      x: INTERP_ZW          __.x,  R0.y, Param1.x         VEC_210
> 0012  00b82000 20146b80            y: INTERP_ZW          __.y,  R0.x, Param1.y         VEC_210
> 0014  01382400 40146b90            z: INTERP_ZW          R0.z,  R0.y, Param1.z         VEC_210
> 0016  81b82000 60146b90            w: INTERP_ZW          R0.w,  R0.x, Param1.w         VEC_210
> 0018  00382400 00346b10     2      x: INTERP_XY          R1.x,  R0.y, Param1.x         VEC_210
> 0020  00b82000 20346b10            y: INTERP_XY          R1.y,  R0.x, Param1.y         VEC_210
> 0022  01382400 40146b00            z: INTERP_XY          __.z,  R0.y, Param1.z         VEC_210
> 0024  81b82000 60146b00            w: INTERP_XY          __.w,  R0.x, Param1.w         VEC_210
>0002  0000000e 80401000 TEX 5 @28
> 0028  00001410 f01d1004 fda20000 SAMPLE              R4.xyz_, R0.zw__,   RID:20, SID:4 CT:NNNN
> 0032  00011010 f01d1005 fc800000 SAMPLE              R5.xyz_, R1.xy__,   RID:16, SID:0 CT:NNNN
> 0036  00011210 f00d1002 fc810000 SAMPLE              R2.xyzw, R1.xy__,   RID:18, SID:2 CT:NNNN
> 0040  00011110 f00d1001 fc808000 SAMPLE              R1.xyzw, R1.xy__,   RID:17, SID:1 CT:NNNN
> 0044  00001310 f01d1003 fda18000 SAMPLE              R3.xyz_, R0.zw__,   RID:19, SID:3 CT:NNNN
>0004  00000018 a00c0000 ALU 4 @48
> 0048  00384400 00146b80     3      x: INTERP_ZW          __.x,  R0.y, Param2.x         VEC_210
> 0050  00b84000 20146b80            y: INTERP_ZW          __.y,  R0.x, Param2.y         VEC_210
> 0052  01384400 40146b90            z: INTERP_ZW          R0.z,  R0.y, Param2.z         VEC_210
> 0054  81b84000 60146b80            w: INTERP_ZW          __.w,  R0.x, Param2.w         VEC_210
>0006  4000001c a1f40000 ALU 126 @56 KC0[CB0:0-15]
> 0056  00384400 0fd46b10     4      x: INTERP_XY          T2.x,  R0.y, Param2.x         VEC_210
> 0058  00b84000 2fd46b10            y: INTERP_XY          T2.y,  R0.x, Param2.y         VEC_210
> 0060  01384400 40146b00            z: INTERP_XY          __.z,  R0.y, Param2.z         VEC_210
> 0062  81b84000 60146b00            w: INTERP_XY          __.w,  R0.x, Param2.w         VEC_210
> 0064  001fa004 4f8284fd     5      z: MULADD             T0.z,  R4.x, [0x40000000 2].x, [0xbf800000 -1].y
> 0066  801fa404 6f8284fd            w: MULADD             T0.w,  R4.y, [0x40000000 2].x, [0xbf800000 -1].y
> 0068  40000000 
> 0069  bf800000 
> 0070  00388400 00146b80     6      x: INTERP_ZW          __.x,  R0.y, Param4.x         VEC_210
> 0072  00b88000 20146b80            y: INTERP_ZW          __.y,  R0.x, Param4.y         VEC_210
> 0074  01388400 4fd46b90            z: INTERP_ZW          T2.z,  R0.y, Param4.z         VEC_210
> 0076  81b88000 60146b80            w: INTERP_ZW          __.w,  R0.x, Param4.w         VEC_210
> 0078  00388400 0fb46b10     7      x: INTERP_XY          T1.x,  R0.y, Param4.x         VEC_210
> 0080  00b88000 2fb46b10            y: INTERP_XY          T1.y,  R0.x, Param4.y         VEC_210
> 0082  01388400 40146b00            z: INTERP_XY          __.z,  R0.y, Param4.z         VEC_210
> 0084  81b88000 60146b00            w: INTERP_XY          __.w,  R0.x, Param4.w         VEC_210
> 0086  00386400 00146b80     8      x: INTERP_ZW          __.x,  R0.y, Param3.x         VEC_210
> 0088  00b86000 20146b80            y: INTERP_ZW          __.y,  R0.x, Param3.y         VEC_210
> 0090  01386400 4fb46b90            z: INTERP_ZW          T1.z,  R0.y, Param3.z         VEC_210
> 0092  81b86000 60146b80            w: INTERP_ZW          __.w,  R0.x, Param3.w         VEC_210
> 0094  00386400 0f946b10     9      x: INTERP_XY          T0.x,  R0.y, Param3.x         VEC_210
> 0096  00b86000 2f946b10            y: INTERP_XY          T0.y,  R0.x, Param3.y         VEC_210
> 0098  01386400 40146b00            z: INTERP_XY          __.z,  R0.y, Param3.z         VEC_210
> 0100  01b86000 60146b00            w: INTERP_XY          __.w,  R0.x, Param3.w         VEC_210
> 0102  801fa804 6fa284fd            t: MULADD             T1.w,  R4.z, [0x40000000 2].x, [0xbf800000 -1].y
> 0104  40000000 
> 0105  bf800000 
> 0106  000fc87c 00005f00    10      x: DOT4               __.x,  T0.z, T2.x
> 0108  008fcc7c 20805f10            y: DOT4               R4.y,  T0.w, T2.y
> 0110  01000c7d 40085f00            z: DOT4               __.z,  T1.w, R0.z             VEC_120
> 0112  801f00f8 60005f00            w: DOT4               __.w,  0, 0
> 0114  000fa87c 00805f10    11      x: DOT4               R4.x,  T0.z, T1.x
> 0116  008fac7c 20005f00            y: DOT4               __.y,  T0.w, T1.y
> 0118  010fcc7d 40085f00            z: DOT4               __.z,  T1.w, T2.z             VEC_120
> 0120  801f00f8 60005f00            w: DOT4               __.w,  0, 0
> 0122  000f887c 00005f00    12      x: DOT4               __.x,  T0.z, T0.x
> 0124  008f8c7c 20005f00            y: DOT4               __.y,  T0.w, T0.y
> 0126  010fac7d 40085f00            z: DOT4               __.z,  T1.w, T1.z             VEC_120
> 0128  801f00f8 6fe05f10            w: DOT4               T3.w,  0, 0
> 0130  001fa805 0f800010    13      x: ADD                T0.x,  R5.z, [0xbf000000 -0.5].x
> 0132  801fa405 6fa00010            w: ADD                T1.w,  R5.y, [0xbf000000 -0.5].x
> 0134  bf000000 
> 0136  018fec7f 00005f00    14      x: DOT4               __.x,  T3.w, T3.w
> 0138  00008004 20005f00            y: DOT4               __.y,  R4.x, R4.x
> 0140  00808404 4f805f10            z: DOT4               T0.z,  R4.y, R4.y
> 0142  001f00f8 60005f00            w: DOT4               __.w,  0, 0
> 0144  801fa005 6f800010            t: ADD                T0.w,  R5.x, [0xbf000000 -0.5].x
> 0146  bf000000 
> 0148  018f8c7c 00005f00    15      x: DOT4               __.x,  T0.w, T0.w
> 0150  018fac7d 2f885f10            y: DOT4               T0.y,  T1.w, T1.w             VEC_120
> 0152  000f807c 40005f00            z: DOT4               __.z,  T0.x, T0.x
> 0154  801f00f8 60005f00            w: DOT4               __.w,  0, 0
> 0156  00380400 00146b80    16      x: INTERP_ZW          __.x,  R0.y, Param0.x         VEC_210
> 0158  00b80000 20146b80            y: INTERP_ZW          __.y,  R0.x, Param0.y         VEC_210
> 0160  01380400 4fd46b90            z: INTERP_ZW          T2.z,  R0.y, Param0.z         VEC_210
> 0162  01b80000 60146b80            w: INTERP_ZW          __.w,  R0.x, Param0.w         VEC_210
> 0164  8000087c 0fe04390            t: RECIPSQRT_CLAMPED  T3.x,  T0.z
> 0166  00380400 0fd46b10    17      x: INTERP_XY          T2.x,  R0.y, Param0.x         VEC_210
> 0168  00b80000 2ff46b10            y: INTERP_XY          T3.y,  R0.x, Param0.y         VEC_210
> 0170  01380400 40146b00            z: INTERP_XY          __.z,  R0.y, Param0.z         VEC_210
> 0172  01b80000 60146b00            w: INTERP_XY          __.w,  R0.x, Param0.w         VEC_210
> 0174  8000047c 2fa44390            t: RECIPSQRT_CLAMPED  T1.y,  T0.y                   SCL_122
> 0176  008fac7d 0f800110    18      x: MUL_IEEE           T0.x,  T1.w, T1.y
> 0178  000fe004 2f800110            y: MUL_IEEE           T0.y,  R4.x, T3.x
> 0180  008fa07c 4f900110            z: MUL_IEEE           T0.z,  T0.x, T1.y             VEC_201
> 0182  000fec7f 6fb40110            w: MUL_IEEE           T1.w,  T3.w, T3.x             VEC_210
> 0184  800fe404 6fc00110            t: MUL_IEEE           T2.w,  R4.y, T3.x
> 0186  000fc07e 00005f00    19      x: DOT4               __.x,  T2.x, T2.x
> 0188  008fe47f 2fc05f10            y: DOT4               T2.y,  T3.y, T3.y
> 0190  010fc87e 40005f00            z: DOT4               __.z,  T2.z, T2.z
> 0192  001f00f8 60005f00            w: DOT4               __.w,  0, 0
> 0194  808fac7c 6f800110            t: MUL_IEEE           T0.w,  T0.w, T1.y
> 0196  018fac7c 00005f00    20      x: DOT4               __.x,  T0.w, T1.w
> 0198  008f807c 2fa05f10            y: DOT4               T1.y,  T0.x, T0.y
> 0200  018fc87c 40045f00            z: DOT4               __.z,  T0.z, T2.w             VEC_021
> 0202  001f00f8 60005f00            w: DOT4               __.w,  0, 0
> 0204  801fa87c 6fa00090            t: MUL                T1.w,  T0.z, [0x40000000 2].x
> 0206  40000000 
> 0208  001fa07c 0f800090    21      x: MUL                T0.x,  T0.x, [0x40000000 2].x
> 0210  001fac7c 6f800090            w: MUL                T0.w,  T0.w, [0x40000000 2].x
> 0212  8000047e 4fa04390            t: RECIPSQRT_CLAMPED  T1.z,  T2.y
> 0214  40000000 
> 0216  010fa87e 0fa00110    22      x: MUL_IEEE           T1.x,  T2.z, T1.z
> 0218  000f847d 2f800110            y: MUL_IEEE           T0.y,  T1.y, T0.x
> 0220  018f847d 4f800110            z: MUL_IEEE           T0.z,  T1.y, T0.w
> 0222  818fa47d 6f840110            w: MUL_IEEE           T0.w,  T1.y, T1.w             VEC_021
> 0224  000fec7f 0f83187c    23      x: MULADD_IEEE        T0.x,  T3.w, T3.x, -T0.z
> 0226  010fa07e 2f800110            y: MUL_IEEE           T0.y,  T2.x, T1.z
> 0228  000fe004 4f97147c            z: MULADD_IEEE        T0.z,  R4.x, T3.x, -T0.y      VEC_210
> 0230  010fa47f 6f8c0110            w: MUL_IEEE           T0.w,  T3.y, T1.z             VEC_102
> 0232  800fe404 6fab1c7c            t: MULADD_IEEE        T1.w,  R4.y, T3.x, -T0.w      SCL_212
> 0234  008f807c 0f805f10    24      x: DOT4               T0.x,  T0.x, T0.y
> 0236  018f887c 20005f00            y: DOT4               __.y,  T0.z, T0.w
> 0238  000fac7d 40005f00            z: DOT4               __.z,  T1.w, T1.x
> 0240  801f00f8 60005f00            w: DOT4               __.w,  0, 0
> 0242  801f007c 0f83507c    25      x: CNDGT              T0.x,  T0.x, 0, -T0.x
> 0244  01804088 2f8300f9    26      y: MULADD_IEEE        T0.y,  KC0[8].x, R2.w, 1.0
> 0246  8000007c 0f804190            t: LOG_IEEE           T0.x,  T0.x
> 0248  000f847c 0f880090    27      x: MUL                T0.x,  T0.y, T0.x             VEC_120
> 0250  0110c801 2f800110            y: MUL_IEEE           T0.y,  R1.z, KC0[6].z
> 0252  001f047d 4fc00190            z: MAX                T2.z,  T1.y, 0
> 0254  80000c7e 6fa04310            t: RECIP_IEEE         T1.w,  T2.w
> 0256  0010c001 0f800110    28      x: MUL_IEEE           T0.x,  R1.x, KC0[6].x
> 0258  010fc47c 2fa00110            y: MUL_IEEE           T1.y,  T0.y, T2.z
> 0260  0110e802 4fa00110            z: MUL_IEEE           T1.z,  R2.z, KC0[7].z
> 0262  001fac7e 6f800490            w: SETGT              T0.w,  T2.w, [0x3e800000 0.25].x
> 0264  8000007c 0fa04090            t: EXP_IEEE           T1.x,  T0.x
> 0266  3e800000 
> 0268  0010e002 0f800110    29      x: MUL_IEEE           T0.x,  R2.x, KC0[7].x
> 0270  0090e402 2f800110            y: MUL_IEEE           T0.y,  R2.y, KC0[7].y
> 0272  010fc07c 4f880110            z: MUL_IEEE           T0.z,  T0.x, T2.z             VEC_120
> 0274  001fac7c 6fa32c7d            w: CNDE               T1.w,  T0.w, [0x40800000 4].x, T1.w
> 0276  8090c401 6f800110            t: MUL_IEEE           T0.w,  R1.y, KC0[6].y
> 0278  40800000 
> 0280  0010a001 0fc00110    30      x: MUL_IEEE           T2.x,  R1.x, KC0[5].x
> 0282  0090a401 2fa00110            y: MUL_IEEE           T1.y,  R1.y, KC0[5].y
> 0284  0110a801 4fa00110            z: MUL_IEEE           T1.z,  R1.z, KC0[5].z
> 0286  010fcc7c 6f840110            w: MUL_IEEE           T0.w,  T0.w, T2.z             VEC_021
> 0288  800fa87d 2fc7047d            t: MULADD_IEEE        T2.y,  T1.z, T1.x, T1.y       SCL_122
> 0290  000fa07c 0f83087c    31      x: MULADD_IEEE        T0.x,  T0.x, T1.x, T0.z
> 0292  000fa47c 2f830c7c            y: MULADD_IEEE        T0.y,  T0.y, T1.x, T0.w
> 0294  018fa803 4f800110            z: MUL_IEEE           T0.z,  R3.z, T1.w
> 0296  018fa403 6f8c0110            w: MUL_IEEE           T0.w,  R3.y, T1.w             VEC_102
> 0298  818fa003 0fa00110            t: MUL_IEEE           T1.x,  R3.x, T1.w
> 0300  000fa07c 0003007e    32      x: MULADD_IEEE        R0.x,  T0.x, T1.x, T2.x
> 0302  018f847c 2003047d            y: MULADD_IEEE        R0.y,  T0.y, T0.w, T1.y
> 0304  010f847e 400b087d            z: MULADD_IEEE        R0.z,  T2.y, T0.z, T1.z       VEC_120
> 0306  80112c01 60000110            w: MUL_IEEE           R0.w,  R1.w, KC0[9].x
>0008  c0000000 95200688 EXPORT_DONE        PIXEL 0     R0.xyzw  EOP
>===== SHADER_END ===============================================================
>
>--------------------------------------------------------------
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL IN[4]
>DCL IN[5]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[9]
>DCL OUT[2], GENERIC[10]
>DCL OUT[3], GENERIC[11]
>DCL OUT[4], GENERIC[12]
>DCL OUT[5], GENERIC[13]
>DCL CONST[0..8]
>DCL TEMP[0..5], LOCAL
>IMM[0] FLT32 {    0.0000,     0.0000,     0.0000,     0.0000}
>  0: MUL TEMP[0], CONST[5], IN[1].xxxx
>  1: MAD TEMP[0], CONST[6], IN[1].yyyy, TEMP[0]
>  2: MAD TEMP[0], CONST[7], IN[1].zzzz, TEMP[0]
>  3: MAD TEMP[0].xy, CONST[8], IN[1].wwww, TEMP[0]
>  4: MOV TEMP[0].xy, TEMP[0].xyxx
>  5: MOV TEMP[0].zw, IN[5].yyxy
>  6: ADD TEMP[1].xyz, CONST[4].xyzz, -IN[0].xyzz
>  7: DP3 TEMP[2].x, TEMP[1].xyzz, IN[2].xyzz
>  8: DP3 TEMP[3].x, TEMP[1].xyzz, IN[3].xyzz
>  9: MOV TEMP[2].y, TEMP[3].xxxx
> 10: DP3 TEMP[1].x, TEMP[1].xyzz, IN[4].xyzz
> 11: MOV TEMP[2].z, TEMP[1].xxxx
> 12: MOV TEMP[2].w, IMM[0].xxxx
> 13: MOV TEMP[1].w, IMM[0].xxxx
> 14: MOV TEMP[1].xyz, IN[2].xyzx
> 15: MOV TEMP[3].w, IMM[0].xxxx
> 16: MOV TEMP[3].xyz, IN[3].xyzx
> 17: MOV TEMP[4].w, IMM[0].xxxx
> 18: MOV TEMP[4].xyz, IN[4].xyzx
> 19: MUL TEMP[5], CONST[0], IN[0].xxxx
> 20: MAD TEMP[5], CONST[1], IN[0].yyyy, TEMP[5]
> 21: MAD TEMP[5], CONST[2], IN[0].zzzz, TEMP[5]
> 22: MAD TEMP[5], CONST[3], IN[0].wwww, TEMP[5]
> 23: MOV OUT[3], TEMP[4]
> 24: MOV OUT[4], TEMP[1]
> 25: MOV OUT[0], TEMP[5]
> 26: MOV OUT[5], TEMP[3]
> 27: MOV OUT[1], TEMP[2]
> 28: MOV OUT[2], TEMP[0]
> 29: END
>; ModuleID = 'tgsi'
>
>define void @main(<4 x float> inreg, <4 x float> inreg, <4 x float> inreg, <4 x float> inreg, <4 x float> inreg, <4 x float> inreg, <4 x float> inreg) #0 {
>main_body:
>  %7 = extractelement <4 x float> %1, i32 0
>  %8 = extractelement <4 x float> %1, i32 1
>  %9 = extractelement <4 x float> %1, i32 2
>  %10 = extractelement <4 x float> %1, i32 3
>  %11 = extractelement <4 x float> %2, i32 0
>  %12 = extractelement <4 x float> %2, i32 1
>  %13 = extractelement <4 x float> %2, i32 2
>  %14 = extractelement <4 x float> %2, i32 3
>  %15 = extractelement <4 x float> %3, i32 0
>  %16 = extractelement <4 x float> %3, i32 1
>  %17 = extractelement <4 x float> %3, i32 2
>  %18 = extractelement <4 x float> %4, i32 0
>  %19 = extractelement <4 x float> %4, i32 1
>  %20 = extractelement <4 x float> %4, i32 2
>  %21 = extractelement <4 x float> %5, i32 0
>  %22 = extractelement <4 x float> %5, i32 1
>  %23 = extractelement <4 x float> %5, i32 2
>  %24 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5)
>  %25 = extractelement <4 x float> %24, i32 0
>  %26 = fmul float %25, %11
>  %27 = extractelement <4 x float> %24, i32 1
>  %28 = fmul float %27, %11
>  %29 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6)
>  %30 = extractelement <4 x float> %29, i32 0
>  %31 = fmul float %30, %12
>  %32 = fadd float %31, %26
>  %33 = extractelement <4 x float> %29, i32 1
>  %34 = fmul float %33, %12
>  %35 = fadd float %34, %28
>  %36 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7)
>  %37 = extractelement <4 x float> %36, i32 0
>  %38 = fmul float %37, %13
>  %39 = fadd float %38, %32
>  %40 = extractelement <4 x float> %36, i32 1
>  %41 = fmul float %40, %13
>  %42 = fadd float %41, %35
>  %43 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8)
>  %44 = extractelement <4 x float> %43, i32 0
>  %45 = fmul float %44, %14
>  %46 = fadd float %45, %39
>  %47 = extractelement <4 x float> %43, i32 1
>  %48 = fmul float %47, %14
>  %49 = fadd float %48, %42
>  %50 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4)
>  %51 = extractelement <4 x float> %50, i32 0
>  %52 = fsub float %51, %7
>  %53 = extractelement <4 x float> %50, i32 1
>  %54 = fsub float %53, %8
>  %55 = extractelement <4 x float> %50, i32 2
>  %56 = fsub float %55, %9
>  %57 = insertelement <4 x float> undef, float %52, i32 0
>  %58 = insertelement <4 x float> %57, float %54, i32 1
>  %59 = insertelement <4 x float> %58, float %56, i32 2
>  %60 = insertelement <4 x float> %59, float 0.000000e+00, i32 3
>  %61 = insertelement <4 x float> undef, float %15, i32 0
>  %62 = insertelement <4 x float> %61, float %16, i32 1
>  %63 = insertelement <4 x float> %62, float %17, i32 2
>  %64 = insertelement <4 x float> %63, float 0.000000e+00, i32 3
>  %65 = call float @llvm.AMDGPU.dp4(<4 x float> %60, <4 x float> %64)
>  %66 = insertelement <4 x float> undef, float %52, i32 0
>  %67 = insertelement <4 x float> %66, float %54, i32 1
>  %68 = insertelement <4 x float> %67, float %56, i32 2
>  %69 = insertelement <4 x float> %68, float 0.000000e+00, i32 3
>  %70 = insertelement <4 x float> undef, float %18, i32 0
>  %71 = insertelement <4 x float> %70, float %19, i32 1
>  %72 = insertelement <4 x float> %71, float %20, i32 2
>  %73 = insertelement <4 x float> %72, float 0.000000e+00, i32 3
>  %74 = call float @llvm.AMDGPU.dp4(<4 x float> %69, <4 x float> %73)
>  %75 = insertelement <4 x float> undef, float %52, i32 0
>  %76 = insertelement <4 x float> %75, float %54, i32 1
>  %77 = insertelement <4 x float> %76, float %56, i32 2
>  %78 = insertelement <4 x float> %77, float 0.000000e+00, i32 3
>  %79 = insertelement <4 x float> undef, float %21, i32 0
>  %80 = insertelement <4 x float> %79, float %22, i32 1
>  %81 = insertelement <4 x float> %80, float %23, i32 2
>  %82 = insertelement <4 x float> %81, float 0.000000e+00, i32 3
>  %83 = call float @llvm.AMDGPU.dp4(<4 x float> %78, <4 x float> %82)
>  %84 = load <4 x float> addrspace(8)* null
>  %85 = extractelement <4 x float> %84, i32 0
>  %86 = fmul float %85, %7
>  %87 = extractelement <4 x float> %84, i32 1
>  %88 = fmul float %87, %7
>  %89 = extractelement <4 x float> %84, i32 2
>  %90 = fmul float %89, %7
>  %91 = load <4 x float> addrspace(8)* null
>  %92 = extractelement <4 x float> %91, i32 3
>  %93 = fmul float %92, %7
>  %94 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
>  %95 = extractelement <4 x float> %94, i32 0
>  %96 = fmul float %95, %8
>  %97 = fadd float %96, %86
>  %98 = extractelement <4 x float> %94, i32 1
>  %99 = fmul float %98, %8
>  %100 = fadd float %99, %88
>  %101 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
>  %102 = extractelement <4 x float> %101, i32 2
>  %103 = fmul float %102, %8
>  %104 = fadd float %103, %90
>  %105 = extractelement <4 x float> %101, i32 3
>  %106 = fmul float %105, %8
>  %107 = fadd float %106, %93
>  %108 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
>  %109 = extractelement <4 x float> %108, i32 0
>  %110 = fmul float %109, %9
>  %111 = fadd float %110, %97
>  %112 = extractelement <4 x float> %108, i32 1
>  %113 = fmul float %112, %9
>  %114 = fadd float %113, %100
>  %115 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
>  %116 = extractelement <4 x float> %115, i32 2
>  %117 = fmul float %116, %9
>  %118 = fadd float %117, %104
>  %119 = extractelement <4 x float> %115, i32 3
>  %120 = fmul float %119, %9
>  %121 = fadd float %120, %107
>  %122 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
>  %123 = extractelement <4 x float> %122, i32 0
>  %124 = fmul float %123, %10
>  %125 = fadd float %124, %111
>  %126 = extractelement <4 x float> %122, i32 1
>  %127 = fmul float %126, %10
>  %128 = fadd float %127, %114
>  %129 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
>  %130 = extractelement <4 x float> %129, i32 2
>  %131 = fmul float %130, %10
>  %132 = fadd float %131, %118
>  %133 = extractelement <4 x float> %129, i32 3
>  %134 = fmul float %133, %10
>  %135 = fadd float %134, %121
>  %136 = insertelement <4 x float> undef, float %125, i32 0
>  %137 = insertelement <4 x float> %136, float %128, i32 1
>  %138 = insertelement <4 x float> %137, float %132, i32 2
>  %139 = insertelement <4 x float> %138, float %135, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %139, i32 60, i32 1)
>  %140 = insertelement <4 x float> undef, float %65, i32 0
>  %141 = insertelement <4 x float> %140, float %74, i32 1
>  %142 = insertelement <4 x float> %141, float %83, i32 2
>  %143 = insertelement <4 x float> %142, float 0.000000e+00, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %143, i32 0, i32 2)
>  %144 = insertelement <4 x float> undef, float %46, i32 0
>  %145 = insertelement <4 x float> %144, float %49, i32 1
>  %146 = shufflevector <4 x float> %145, <4 x float> %6, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
>  call void @llvm.R600.store.swizzle(<4 x float> %146, i32 1, i32 2)
>  %147 = insertelement <4 x float> undef, float %21, i32 0
>  %148 = insertelement <4 x float> %147, float %22, i32 1
>  %149 = insertelement <4 x float> %148, float %23, i32 2
>  %150 = insertelement <4 x float> %149, float 0.000000e+00, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %150, i32 2, i32 2)
>  %151 = insertelement <4 x float> undef, float %15, i32 0
>  %152 = insertelement <4 x float> %151, float %16, i32 1
>  %153 = insertelement <4 x float> %152, float %17, i32 2
>  %154 = insertelement <4 x float> %153, float 0.000000e+00, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %154, i32 3, i32 2)
>  %155 = insertelement <4 x float> undef, float %18, i32 0
>  %156 = insertelement <4 x float> %155, float %19, i32 1
>  %157 = insertelement <4 x float> %156, float %20, i32 2
>  %158 = insertelement <4 x float> %157, float 0.000000e+00, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %158, i32 4, i32 2)
>  ret void
>}
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1
>
>declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { readnone }
>
>===== SHADER #36 ==================================== VS/REDWOOD/EVERGREEN =====
>===== 98 dw ===== 10 gprs ===== 1 stack ========================================
>0000  00000000 84c00000 CALL_FS @0
>0002  8000000a a0980000 ALU 39 @20 KC0[CB0:0-31]
> 0020  80002080 60000110     1      w: MUL_IEEE           R0.w,  KC0[0].x, R1.x
> 0022  80802081 60030cfe     2      w: MULADD_IEEE        R0.w,  KC0[1].x, R1.y, PV.w
> 0024  81002082 60030cfe     3      w: MULADD_IEEE        R0.w,  KC0[2].x, R1.z, PV.w
> 0026  01802083 00030cfe     4      x: MULADD_IEEE        R0.x,  KC0[3].x, R1.w, PV.w
> 0028  80002480 60e00110            w: MUL_IEEE           R7.w,  KC0[0].y, R1.x
> 0030  02002084 00e00010     5      x: ADD                R7.x,  KC0[4].x, -R1.x
> 0032  02802484 20e00010            y: ADD                R7.y,  KC0[4].y, -R1.y
> 0034  80802481 60e30cfe            w: MULADD_IEEE        R7.w,  KC0[1].y, R1.y, PV.w
> 0036  80002880 61000110     6      w: MUL_IEEE           R8.w,  KC0[0].z, R1.x
> 0038  00802881 40e30cfe     7      z: MULADD_IEEE        R7.z,  KC0[1].z, R1.y, PV.w
> 0040  80004085 61000110            w: MUL_IEEE           R8.w,  KC0[5].x, R2.x
> 0042  81002482 60e30c07     8      w: MULADD_IEEE        R7.w,  KC0[2].y, R1.z, R7.w
> 0044  01802483 20030cfe     9      y: MULADD_IEEE        R0.y,  KC0[3].y, R1.w, PV.w
> 0046  80804086 60e30c08            w: MULADD_IEEE        R7.w,  KC0[6].x, R2.y, R8.w
> 0048  81002882 61030807    10      w: MULADD_IEEE        R8.w,  KC0[2].z, R1.z, R7.z
> 0050  01802883 40030cfe    11      z: MULADD_IEEE        R0.z,  KC0[3].z, R1.w, PV.w
> 0052  80002c80 61000110            w: MUL_IEEE           R8.w,  KC0[0].w, R1.x
> 0054  81004087 60e30c07    12      w: MULADD_IEEE        R7.w,  KC0[7].x, R2.z, R7.w
> 0056  01804088 40c30cfe    13      z: MULADD_IEEE        R6.z,  KC0[8].x, R2.w, PV.w
> 0058  80004485 60e00110            w: MUL_IEEE           R7.w,  KC0[5].y, R2.x
> 0060  80802c81 61030c08    14      w: MULADD_IEEE        R8.w,  KC0[1].w, R1.y, R8.w
> 0062  03002884 40e00010    15      z: ADD                R7.z,  KC0[4].z, -R1.z
> 0064  81002c82 61030cfe            w: MULADD_IEEE        R8.w,  KC0[2].w, R1.z, PV.w
> 0066  80804486 60e30c07    16      w: MULADD_IEEE        R7.w,  KC0[6].y, R2.y, R7.w
> 0068  81004487 60e30cfe    17      w: MULADD_IEEE        R7.w,  KC0[7].y, R2.z, PV.w
> 0070  00006007 01205f10    18      x: DOT4               R9.x,  R7.x, R3.x
> 0072  00806407 21205f00            y: DOT4               __.y,  R7.y, R3.y
> 0074  01006807 41205f00            z: DOT4               __.z,  R7.z, R3.z
> 0076  801f00f8 61205f00            w: DOT4               __.w,  0, 0
> 0078  81804488 60c30c07    19      w: MULADD_IEEE        R6.w,  KC0[8].y, R2.w, R7.w
> 0080  00008007 01205f00    20      x: DOT4               __.x,  R7.x, R4.x
> 0082  00808407 21205f10            y: DOT4               R9.y,  R7.y, R4.y
> 0084  01008807 41205f00            z: DOT4               __.z,  R7.z, R4.z
> 0086  801f00f8 61205f00            w: DOT4               __.w,  0, 0
> 0088  81802c83 60030c08    21      w: MULADD_IEEE        R0.w,  KC0[3].w, R1.w, R8.w
> 0090  0000a007 01205f00    22      x: DOT4               __.x,  R7.x, R5.x
> 0092  0080a407 21205f00            y: DOT4               __.y,  R7.y, R5.y
> 0094  0100a807 41205f10            z: DOT4               R9.z,  R7.z, R5.z
> 0096  801f00f8 61205f00            w: DOT4               __.w,  0, 0
>0004  c000203c 95000688 EXPORT_DONE        POS   60    R0.xyzw
>0006  c004c000 94c00888 EXPORT             PARAM 0     R9.xyz0
>0008  c0034001 94c0021a EXPORT             PARAM 1     R6.zwxy
>0010  c002c002 94c00888 EXPORT             PARAM 2     R5.xyz0
>0012  c001c003 94c00888 EXPORT             PARAM 3     R3.xyz0
>0014  c0024004 95200888 EXPORT_DONE        PARAM 4     R4.xyz0  EOP
>===== SHADER_END ===============================================================
>
>
>===== SHADER #36 OPT ================================ VS/REDWOOD/EVERGREEN =====
>===== 94 dw ===== 7 gprs ===== 1 stack =========================================
>0000  00000000 84c00000 CALL_FS @0
>0002  40000008 a0980000 ALU 39 @16 KC0[CB0:0-15]
> 0016  00002480 4f800110     1      z: MUL_IEEE           T0.z,  KC0[0].y, R1.x
> 0018  80002080 6fa00110            w: MUL_IEEE           T1.w,  KC0[0].x, R1.x
> 0020  00004085 0fa00110     2      x: MUL_IEEE           T1.x,  KC0[5].x, R2.x
> 0022  00002880 2fa40110            y: MUL_IEEE           T1.y,  KC0[0].z, R1.x         VEC_021
> 0024  00004485 6f800110            w: MUL_IEEE           T0.w,  KC0[5].y, R2.x
> 0026  80002c80 0f840110            t: MUL_IEEE           T0.x,  KC0[0].w, R1.x         SCL_122
> 0028  00802481 4fa3087c     3      z: MULADD_IEEE        T1.z,  KC0[1].y, R1.y, T0.z
> 0030  00802c81 6fc3007c            w: MULADD_IEEE        T2.w,  KC0[1].w, R1.y, T0.x
> 0032  80802081 6fe70c7d            t: MULADD_IEEE        T3.w,  KC0[1].x, R1.y, T1.w   SCL_122
> 0034  02002084 0f800010     4      x: ADD                T0.x,  KC0[4].x, -R1.x
> 0036  02802484 2f800010            y: ADD                T0.y,  KC0[4].y, -R1.y
> 0038  83002884 4f800010            z: ADD                T0.z,  KC0[4].z, -R1.z
> 0040  00804086 0faf007d     5      x: MULADD_IEEE        T1.x,  KC0[6].x, R2.y, T1.x   VEC_102
> 0042  00804486 6f8f0c7c            w: MULADD_IEEE        T0.w,  KC0[6].y, R2.y, T0.w   VEC_102
> 0044  80802881 6fab047d            t: MULADD_IEEE        T1.w,  KC0[1].z, R1.y, T1.y   SCL_212
> 0046  01002c82 2fa30c7e     6      y: MULADD_IEEE        T1.y,  KC0[2].w, R1.z, T2.w
> 0048  01002082 4fb30c7f            z: MULADD_IEEE        T1.z,  KC0[2].x, R1.z, T3.w   VEC_201
> 0050  81002482 6fc3087d            w: MULADD_IEEE        T2.w,  KC0[2].y, R1.z, T1.z
> 0052  0000a07c 00005f00     7      x: DOT4               __.x,  T0.x, R5.x
> 0054  0080a47c 20005f00            y: DOT4               __.y,  T0.y, R5.y
> 0056  0100a87c 40205f10            z: DOT4               R1.z,  T0.z, R5.z
> 0058  001f00f8 60005f00            w: DOT4               __.w,  0, 0
> 0060  81002882 6fa70c7d            t: MULADD_IEEE        T1.w,  KC0[2].z, R1.z, T1.w   SCL_122
> 0062  0000807c 00005f00     8      x: DOT4               __.x,  T0.x, R4.x
> 0064  0080847c 20205f10            y: DOT4               R1.y,  T0.y, R4.y
> 0066  0100887c 40005f00            z: DOT4               __.z,  T0.z, R4.z
> 0068  001f00f8 60005f00            w: DOT4               __.w,  0, 0
> 0070  81004487 6f870c7c            t: MULADD_IEEE        T0.w,  KC0[7].y, R2.z, T0.w   SCL_122
> 0072  0000607c 00205f10     9      x: DOT4               R1.x,  T0.x, R3.x
> 0074  0080647c 20005f00            y: DOT4               __.y,  T0.y, R3.y
> 0076  0100687c 40005f00            z: DOT4               __.z,  T0.z, R3.z
> 0078  001f00f8 60005f00            w: DOT4               __.w,  0, 0
> 0080  81004087 0f87007d            t: MULADD_IEEE        T0.x,  KC0[7].x, R2.z, T1.x   SCL_122
> 0082  01802483 20030c7e    10      y: MULADD_IEEE        R0.y,  KC0[3].y, R1.w, T2.w
> 0084  01802883 40170c7d            z: MULADD_IEEE        R0.z,  KC0[3].z, R1.w, T1.w   VEC_210
> 0086  81802c83 6003047d            w: MULADD_IEEE        R0.w,  KC0[3].w, R1.w, T1.y
> 0088  01802083 000f087d    11      x: MULADD_IEEE        R0.x,  KC0[3].x, R1.w, T1.z   VEC_102
> 0090  01804088 40c3007c            z: MULADD_IEEE        R6.z,  KC0[8].x, R2.w, T0.x
> 0092  81804488 60c30c7c            w: MULADD_IEEE        R6.w,  KC0[8].y, R2.w, T0.w
>0004  c0034001 94c0021a EXPORT             PARAM 1     R6.zwxy
>0006  c000203c 95000688 EXPORT_DONE        POS   60    R0.xyzw
>0008  c000c000 94c00888 EXPORT             PARAM 0     R1.xyz0
>0010  c002c002 94c00888 EXPORT             PARAM 2     R5.xyz0
>0012  c0024004 94c00888 EXPORT             PARAM 4     R4.xyz0
>0014  c001c003 95200888 EXPORT_DONE        PARAM 3     R3.xyz0  EOP
>===== SHADER_END ===============================================================
>
>--------------------------------------------------------------
>FRAG
>DCL IN[0], GENERIC[9], PERSPECTIVE
>DCL IN[1], GENERIC[10], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SAMP[1]
>DCL SVIEW[0], 2D, FLOAT
>DCL SVIEW[1], 2D, FLOAT
>DCL CONST[2..5]
>DCL TEMP[0..2], LOCAL
>  0: MOV TEMP[0].xy, IN[0].xyyy
>  1: TEX TEMP[0], TEMP[0], SAMP[0], 2D
>  2: MUL TEMP[1].x, TEMP[0].wwww, CONST[5].xxxx
>  3: MOV TEMP[1].w, TEMP[1].xxxx
>  4: MAD TEMP[2].xyz, IN[1].xyzz, CONST[3].xyzz, CONST[2].xyzz
>  5: MUL TEMP[1].xyz, TEMP[0].xyzz, TEMP[2].xyzz
>  6: MOV TEMP[0].xy, IN[0].xyyy
>  7: TEX TEMP[0].xyz, TEMP[0], SAMP[1], 2D
>  8: MAD TEMP[1].xyz, TEMP[0].xyzz, CONST[4].xyzz, TEMP[1].xyzz
>  9: MOV OUT[0], TEMP[1]
> 10: END
>; ModuleID = 'tgsi'
>
>define void @main(<4 x float> inreg, <4 x float> inreg, <4 x float> inreg) #0 {
>main_body:
>  %3 = extractelement <4 x float> %0, i32 0
>  %4 = extractelement <4 x float> %0, i32 1
>  %5 = call <2 x float> @llvm.R600.interp.xy(i32 0, float %3, float %4)
>  %6 = call <2 x float> @llvm.R600.interp.zw(i32 0, float %3, float %4)
>  %7 = extractelement <4 x float> %0, i32 0
>  %8 = extractelement <4 x float> %0, i32 1
>  %9 = call <2 x float> @llvm.R600.interp.xy(i32 1, float %7, float %8)
>  %10 = call <2 x float> @llvm.R600.interp.zw(i32 1, float %7, float %8)
>  %11 = extractelement <2 x float> %9, i32 0
>  %12 = extractelement <2 x float> %9, i32 1
>  %13 = extractelement <2 x float> %10, i32 0
>  %14 = shufflevector <2 x float> %5, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
>  %15 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %14, i32 16, i32 0, i32 2)
>  %16 = extractelement <4 x float> %15, i32 0
>  %17 = extractelement <4 x float> %15, i32 1
>  %18 = extractelement <4 x float> %15, i32 2
>  %19 = extractelement <4 x float> %15, i32 3
>  %20 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5)
>  %21 = extractelement <4 x float> %20, i32 0
>  %22 = fmul float %19, %21
>  %23 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
>  %24 = extractelement <4 x float> %23, i32 0
>  %25 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
>  %26 = extractelement <4 x float> %25, i32 0
>  %27 = fmul float %11, %24
>  %28 = fadd float %27, %26
>  %29 = extractelement <4 x float> %23, i32 1
>  %30 = extractelement <4 x float> %25, i32 1
>  %31 = fmul float %12, %29
>  %32 = fadd float %31, %30
>  %33 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
>  %34 = extractelement <4 x float> %33, i32 2
>  %35 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
>  %36 = extractelement <4 x float> %35, i32 2
>  %37 = fmul float %13, %34
>  %38 = fadd float %37, %36
>  %39 = fmul float %16, %28
>  %40 = fmul float %17, %32
>  %41 = fmul float %18, %38
>  %42 = shufflevector <2 x float> %5, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
>  %43 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %42, i32 17, i32 1, i32 2)
>  %44 = extractelement <4 x float> %43, i32 0
>  %45 = extractelement <4 x float> %43, i32 1
>  %46 = extractelement <4 x float> %43, i32 2
>  %47 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4)
>  %48 = extractelement <4 x float> %47, i32 0
>  %49 = fmul float %44, %48
>  %50 = fadd float %49, %39
>  %51 = extractelement <4 x float> %47, i32 1
>  %52 = fmul float %45, %51
>  %53 = fadd float %52, %40
>  %54 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4)
>  %55 = extractelement <4 x float> %54, i32 2
>  %56 = fmul float %46, %55
>  %57 = fadd float %56, %41
>  %58 = insertelement <4 x float> undef, float %50, i32 0
>  %59 = insertelement <4 x float> %58, float %53, i32 1
>  %60 = insertelement <4 x float> %59, float %57, i32 2
>  %61 = insertelement <4 x float> %60, float %22, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %61, i32 0, i32 0)
>  ret void
>}
>
>; Function Attrs: readnone
>declare <2 x float> @llvm.R600.interp.xy(i32, float, float) #1
>
>; Function Attrs: readnone
>declare <2 x float> @llvm.R600.interp.zw(i32, float, float) #1
>
>; Function Attrs: readnone
>declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32, i32) #1
>
>declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { readnone }
>
>===== SHADER #37 ==================================== PS/REDWOOD/EVERGREEN =====
>===== 64 dw ===== 5 gprs ===== 0 stack =========================================
>0000  0000000a a00c0000 ALU 4 @20
> 0020  00380400 00346b10     1      x: INTERP_XY          R1.x,  R0.y, Param0.x         VEC_210
> 0022  00380000 20346b10            y: INTERP_XY          R1.y,  R0.x, Param0.x         VEC_210
> 0024  00380400 40146b00            z: INTERP_XY          __.z,  R0.y, Param0.x         VEC_210
> 0026  80380000 60146b00            w: INTERP_XY          __.w,  R0.x, Param0.x         VEC_210
>0002  00000006 80400400 TEX 2 @12
> 0012  00011110 f00d1002 fc808000 SAMPLE              R2.xyzw, R1.xy__,   RID:17, SID:1 CT:NNNN
> 0016  00011010 f00d1001 fc800000 SAMPLE              R1.xyzw, R1.xy__,   RID:16, SID:0 CT:NNNN
>0004  8000000e a0440000 ALU 18 @28 KC0[CB0:0-31]
> 0028  00382400 00746b10     2      x: INTERP_XY          R3.x,  R0.y, Param1.x         VEC_210
> 0030  00382000 20746b10            y: INTERP_XY          R3.y,  R0.x, Param1.x         VEC_210
> 0032  00382400 40146b00            z: INTERP_XY          __.z,  R0.y, Param1.x         VEC_210
> 0034  80382000 60146b00            w: INTERP_XY          __.w,  R0.x, Param1.x         VEC_210
> 0036  801060fe 60630082     3      w: MULADD_IEEE        R3.w,  PV.x, KC0[3].x, KC0[2].x
> 0038  019fc001 60600110     4      w: MUL_IEEE           R3.w,  R1.x, PV.w
> 0040  8010ac01 60800110            t: MUL_IEEE           R4.w,  R1.w, KC0[5].x
> 0042  80108002 00830cfe     5      x: MULADD_IEEE        R4.x,  R2.x, KC0[4].x, PV.w
> 0044  80906403 60630482     6      w: MULADD_IEEE        R3.w,  R3.y, KC0[3].y, KC0[2].y
> 0046  00382400 00146b80     7      x: INTERP_ZW          __.x,  R0.y, Param1.x         VEC_210
> 0048  00382000 20146b80            y: INTERP_ZW          __.y,  R0.x, Param1.x         VEC_210
> 0050  00382400 40146b90            z: INTERP_ZW          R0.z,  R0.y, Param1.x         VEC_210
> 0052  80382000 60146b90            w: INTERP_ZW          R0.w,  R0.x, Param1.x         VEC_210
> 0054  011068fe 60030882     8      w: MULADD_IEEE        R0.w,  PV.z, KC0[3].z, KC0[2].z
> 0056  81806401 60600110            t: MUL_IEEE           R3.w,  R1.y, R3.w
> 0058  00908402 208300ff     9      y: MULADD_IEEE        R4.y,  R2.y, KC0[4].y, PS
> 0060  819fc801 60000110            w: MUL_IEEE           R0.w,  R1.z, PV.w
> 0062  81108802 40830cfe    10      z: MULADD_IEEE        R4.z,  R2.z, KC0[4].z, PV.w
>0006  c0020000 95200688 EXPORT_DONE        PIXEL 0     R4.xyzw  EOP
>===== SHADER_END ===============================================================
>
>
>===== SHADER #37 OPT ================================ PS/REDWOOD/EVERGREEN =====
>===== 60 dw ===== 3 gprs ===== 0 stack =========================================
>0000  00000004 a00c0000 ALU 4 @8
> 0008  00380400 00346b10     1      x: INTERP_XY          R1.x,  R0.y, Param0.x         VEC_210
> 0010  00b80000 20346b10            y: INTERP_XY          R1.y,  R0.x, Param0.y         VEC_210
> 0012  01380400 40146b00            z: INTERP_XY          __.z,  R0.y, Param0.z         VEC_210
> 0014  81b80000 60146b00            w: INTERP_XY          __.w,  R0.x, Param0.w         VEC_210
>0002  00000008 80400400 TEX 2 @16
> 0016  00011010 f00d1002 fc800000 SAMPLE              R2.xyzw, R1.xy__,   RID:16, SID:0 CT:NNNN
> 0020  00011110 f01d1001 fc808000 SAMPLE              R1.xyz_, R1.xy__,   RID:17, SID:1 CT:NNNN
>0004  4000000c a0440000 ALU 18 @24 KC0[CB0:0-15]
> 0024  00382400 00146b80     2      x: INTERP_ZW          __.x,  R0.y, Param1.x         VEC_210
> 0026  00b82000 20146b80            y: INTERP_ZW          __.y,  R0.x, Param1.y         VEC_210
> 0028  01382400 4f946b90            z: INTERP_ZW          T0.z,  R0.y, Param1.z         VEC_210
> 0030  81b82000 60146b80            w: INTERP_ZW          __.w,  R0.x, Param1.w         VEC_210
> 0032  00382400 0f946b10     3      x: INTERP_XY          T0.x,  R0.y, Param1.x         VEC_210
> 0034  00b82000 2f946b10            y: INTERP_XY          T0.y,  R0.x, Param1.y         VEC_210
> 0036  01382400 40146b00            z: INTERP_XY          __.z,  R0.y, Param1.z         VEC_210
> 0038  81b82000 60146b00            w: INTERP_XY          __.w,  R0.x, Param1.w         VEC_210
> 0040  8110687c 4f830882     4      z: MULADD_IEEE        T0.z,  T0.z, KC0[3].z, KC0[2].z
> 0042  0010607c 0f830082     5      x: MULADD_IEEE        T0.x,  T0.x, KC0[3].x, KC0[2].x
> 0044  8090647c 2f830482            y: MULADD_IEEE        T0.y,  T0.y, KC0[3].y, KC0[2].y
> 0046  000f8002 0f800110     6      x: MUL_IEEE           T0.x,  R2.x, T0.x
> 0048  008f8402 2f800110            y: MUL_IEEE           T0.y,  R2.y, T0.y
> 0050  010f8802 4f800110            z: MUL_IEEE           T0.z,  R2.z, T0.z
> 0052  8010ac02 60000110            w: MUL_IEEE           R0.w,  R2.w, KC0[5].x
> 0054  00108001 0003007c     7      x: MULADD_IEEE        R0.x,  R1.x, KC0[4].x, T0.x
> 0056  00908401 2003047c            y: MULADD_IEEE        R0.y,  R1.y, KC0[4].y, T0.y
> 0058  81108801 4003087c            z: MULADD_IEEE        R0.z,  R1.z, KC0[4].z, T0.z
>0006  c0000000 95200688 EXPORT_DONE        PIXEL 0     R0.xyzw  EOP
>===== SHADER_END ===============================================================
>
>--------------------------------------------------------------
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[9]
>DCL OUT[2], GENERIC[10]
>DCL CONST[0..7]
>DCL TEMP[0..1], LOCAL
>IMM[0] FLT32 {    0.0000,     0.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].zw, IMM[0].xxxx
>  1: MUL TEMP[1], CONST[4], IN[2].xxxx
>  2: MAD TEMP[1], CONST[5], IN[2].yyyy, TEMP[1]
>  3: MAD TEMP[1], CONST[6], IN[2].zzzz, TEMP[1]
>  4: MAD TEMP[1].xy, CONST[7], IN[2].wwww, TEMP[1]
>  5: MOV TEMP[0].xy, TEMP[1].xyxx
>  6: MUL TEMP[1], CONST[0], IN[0].xxxx
>  7: MAD TEMP[1], CONST[1], IN[0].yyyy, TEMP[1]
>  8: MAD TEMP[1], CONST[2], IN[0].zzzz, TEMP[1]
>  9: MAD TEMP[1], CONST[3], IN[0].wwww, TEMP[1]
> 10: MOV OUT[2], IN[1]
> 11: MOV OUT[0], TEMP[1]
> 12: MOV OUT[1], TEMP[0]
> 13: END
>; ModuleID = 'tgsi'
>
>define void @main(<4 x float> inreg, <4 x float> inreg, <4 x float> inreg, <4 x float> inreg) #0 {
>main_body:
>  %4 = extractelement <4 x float> %1, i32 0
>  %5 = extractelement <4 x float> %1, i32 1
>  %6 = extractelement <4 x float> %1, i32 2
>  %7 = extractelement <4 x float> %1, i32 3
>  %8 = extractelement <4 x float> %3, i32 0
>  %9 = extractelement <4 x float> %3, i32 1
>  %10 = extractelement <4 x float> %3, i32 2
>  %11 = extractelement <4 x float> %3, i32 3
>  %12 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4)
>  %13 = extractelement <4 x float> %12, i32 0
>  %14 = fmul float %13, %8
>  %15 = extractelement <4 x float> %12, i32 1
>  %16 = fmul float %15, %8
>  %17 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5)
>  %18 = extractelement <4 x float> %17, i32 0
>  %19 = fmul float %18, %9
>  %20 = fadd float %19, %14
>  %21 = extractelement <4 x float> %17, i32 1
>  %22 = fmul float %21, %9
>  %23 = fadd float %22, %16
>  %24 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6)
>  %25 = extractelement <4 x float> %24, i32 0
>  %26 = fmul float %25, %10
>  %27 = fadd float %26, %20
>  %28 = extractelement <4 x float> %24, i32 1
>  %29 = fmul float %28, %10
>  %30 = fadd float %29, %23
>  %31 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7)
>  %32 = extractelement <4 x float> %31, i32 0
>  %33 = fmul float %32, %11
>  %34 = fadd float %33, %27
>  %35 = extractelement <4 x float> %31, i32 1
>  %36 = fmul float %35, %11
>  %37 = fadd float %36, %30
>  %38 = load <4 x float> addrspace(8)* null
>  %39 = extractelement <4 x float> %38, i32 0
>  %40 = fmul float %39, %4
>  %41 = extractelement <4 x float> %38, i32 1
>  %42 = fmul float %41, %4
>  %43 = extractelement <4 x float> %38, i32 2
>  %44 = fmul float %43, %4
>  %45 = load <4 x float> addrspace(8)* null
>  %46 = extractelement <4 x float> %45, i32 3
>  %47 = fmul float %46, %4
>  %48 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
>  %49 = extractelement <4 x float> %48, i32 0
>  %50 = fmul float %49, %5
>  %51 = fadd float %50, %40
>  %52 = extractelement <4 x float> %48, i32 1
>  %53 = fmul float %52, %5
>  %54 = fadd float %53, %42
>  %55 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
>  %56 = extractelement <4 x float> %55, i32 2
>  %57 = fmul float %56, %5
>  %58 = fadd float %57, %44
>  %59 = extractelement <4 x float> %55, i32 3
>  %60 = fmul float %59, %5
>  %61 = fadd float %60, %47
>  %62 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
>  %63 = extractelement <4 x float> %62, i32 0
>  %64 = fmul float %63, %6
>  %65 = fadd float %64, %51
>  %66 = extractelement <4 x float> %62, i32 1
>  %67 = fmul float %66, %6
>  %68 = fadd float %67, %54
>  %69 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
>  %70 = extractelement <4 x float> %69, i32 2
>  %71 = fmul float %70, %6
>  %72 = fadd float %71, %58
>  %73 = extractelement <4 x float> %69, i32 3
>  %74 = fmul float %73, %6
>  %75 = fadd float %74, %61
>  %76 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
>  %77 = extractelement <4 x float> %76, i32 0
>  %78 = fmul float %77, %7
>  %79 = fadd float %78, %65
>  %80 = extractelement <4 x float> %76, i32 1
>  %81 = fmul float %80, %7
>  %82 = fadd float %81, %68
>  %83 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
>  %84 = extractelement <4 x float> %83, i32 2
>  %85 = fmul float %84, %7
>  %86 = fadd float %85, %72
>  %87 = extractelement <4 x float> %83, i32 3
>  %88 = fmul float %87, %7
>  %89 = fadd float %88, %75
>  %90 = insertelement <4 x float> undef, float %79, i32 0
>  %91 = insertelement <4 x float> %90, float %82, i32 1
>  %92 = insertelement <4 x float> %91, float %86, i32 2
>  %93 = insertelement <4 x float> %92, float %89, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %93, i32 60, i32 1)
>  %94 = insertelement <4 x float> undef, float %34, i32 0
>  %95 = insertelement <4 x float> %94, float %37, i32 1
>  %96 = insertelement <4 x float> %95, float 0.000000e+00, i32 2
>  %97 = insertelement <4 x float> %96, float 0.000000e+00, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %97, i32 0, i32 2)
>  call void @llvm.R600.store.swizzle(<4 x float> %2, i32 1, i32 2)
>  ret void
>}
>
>declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
>
>attributes #0 = { "ShaderType"="1" }
>
>===== SHADER #38 ==================================== VS/REDWOOD/EVERGREEN =====
>===== 60 dw ===== 7 gprs ===== 1 stack =========================================
>0000  00000000 84c00000 CALL_FS @0
>0002  80000006 a05c0000 ALU 24 @12 KC0[CB0:0-31]
> 0012  80002080 60000110     1      w: MUL_IEEE           R0.w,  KC0[0].x, R1.x
> 0014  00802081 40030cfe     2      z: MULADD_IEEE        R0.z,  KC0[1].x, R1.y, PV.w
> 0016  80002480 60000110            w: MUL_IEEE           R0.w,  KC0[0].y, R1.x
> 0018  80006084 60800110     3      w: MUL_IEEE           R4.w,  KC0[4].x, R3.x
> 0020  00806085 40830cfe     4      z: MULADD_IEEE        R4.z,  KC0[5].x, R3.y, PV.w
> 0022  80802481 60070c00            w: MULADD_IEEE        R0.w,  KC0[1].y, R1.y, R0.w   VEC_021
> 0024  81002082 60830800     5      w: MULADD_IEEE        R4.w,  KC0[2].x, R1.z, R0.z
> 0026  01802083 00a30cfe     6      x: MULADD_IEEE        R5.x,  KC0[3].x, R1.w, PV.w
> 0028  81002482 60030c00            w: MULADD_IEEE        R0.w,  KC0[2].y, R1.z, R0.w
> 0030  81006086 60830804     7      w: MULADD_IEEE        R4.w,  KC0[6].x, R3.z, R4.z
> 0032  01806087 00830cfe     8      x: MULADD_IEEE        R4.x,  KC0[7].x, R3.w, PV.w
> 0034  81802483 20ab0c00            y: MULADD_IEEE        R5.y,  KC0[3].y, R1.w, R0.w   VEC_120
> 0036  80002880 60000110     9      w: MUL_IEEE           R0.w,  KC0[0].z, R1.x
> 0038  00802881 40030cfe    10      z: MULADD_IEEE        R0.z,  KC0[1].z, R1.y, PV.w
> 0040  80002c80 60000110            w: MUL_IEEE           R0.w,  KC0[0].w, R1.x
> 0042  80006484 60c00110    11      w: MUL_IEEE           R6.w,  KC0[4].y, R3.x
> 0044  00806485 40c30cfe    12      z: MULADD_IEEE        R6.z,  KC0[5].y, R3.y, PV.w
> 0046  80802c81 60070c00            w: MULADD_IEEE        R0.w,  KC0[1].w, R1.y, R0.w   VEC_021
> 0048  81002882 60c30800    13      w: MULADD_IEEE        R6.w,  KC0[2].z, R1.z, R0.z
> 0050  01802883 40a30cfe    14      z: MULADD_IEEE        R5.z,  KC0[3].z, R1.w, PV.w
> 0052  81002c82 60030c00            w: MULADD_IEEE        R0.w,  KC0[2].w, R1.z, R0.w
> 0054  81006486 60c30806    15      w: MULADD_IEEE        R6.w,  KC0[6].y, R3.z, R6.z
> 0056  01806487 20830cfe    16      y: MULADD_IEEE        R4.y,  KC0[7].y, R3.w, PV.w
> 0058  81802c83 60ab0c00            w: MULADD_IEEE        R5.w,  KC0[3].w, R1.w, R0.w   VEC_120
>0004  c002a03c 95000688 EXPORT_DONE        POS   60    R5.xyzw
>0006  c0024000 94c00908 EXPORT             PARAM 0     R4.xy00
>0008  c0014001 95200688 EXPORT_DONE        PARAM 1     R2.xyzw  EOP
>===== SHADER_END ===============================================================
>
>
>===== SHADER #38 OPT ================================ VS/REDWOOD/EVERGREEN =====
>===== 58 dw ===== 4 gprs ===== 1 stack =========================================
>0000  00000000 84c00000 CALL_FS @0
>0002  40000005 a05c0000 ALU 24 @10 KC0[CB0:0-15]
> 0010  00002c80 0f800110     1      x: MUL_IEEE           T0.x,  KC0[0].w, R1.x
> 0012  80002880 2f800110            y: MUL_IEEE           T0.y,  KC0[0].z, R1.x
> 0014  00006084 0fc00110     2      x: MUL_IEEE           T2.x,  KC0[4].x, R3.x
> 0016  00002480 4f840110            z: MUL_IEEE           T0.z,  KC0[0].y, R1.x         VEC_021
> 0018  80002080 6f840110            w: MUL_IEEE           T0.w,  KC0[0].x, R1.x         VEC_021
> 0020  00802c81 0f83007c     3      x: MULADD_IEEE        T0.x,  KC0[1].w, R1.y, T0.x
> 0022  00802881 2fa3047c            y: MULADD_IEEE        T1.y,  KC0[1].z, R1.y, T0.y
> 0024  80006484 0fa00110            t: MUL_IEEE           T1.x,  KC0[4].y, R3.x
> 0026  00806085 2f83007e     4      y: MULADD_IEEE        T0.y,  KC0[5].x, R3.y, T2.x
> 0028  00802481 4f87087c            z: MULADD_IEEE        T0.z,  KC0[1].y, R1.y, T0.z   VEC_021
> 0030  80802081 6f870c7c            w: MULADD_IEEE        T0.w,  KC0[1].x, R1.y, T0.w   VEC_021
> 0032  01002c82 0fc3007c     5      x: MULADD_IEEE        T2.x,  KC0[2].w, R1.z, T0.x
> 0034  01002882 2fa7047d            y: MULADD_IEEE        T1.y,  KC0[2].z, R1.z, T1.y   VEC_021
> 0036  80806485 0f8f007d            t: MULADD_IEEE        T0.x,  KC0[5].y, R3.y, T1.x   SCL_221
> 0038  01006486 0f8f007c     6      x: MULADD_IEEE        T0.x,  KC0[6].y, R3.z, T0.x   VEC_102
> 0040  01006086 2f8f047c            y: MULADD_IEEE        T0.y,  KC0[6].x, R3.z, T0.y   VEC_102
> 0042  01002082 4f830c7c            z: MULADD_IEEE        T0.z,  KC0[2].x, R1.z, T0.w
> 0044  81002482 0fab087c            t: MULADD_IEEE        T1.x,  KC0[2].y, R1.z, T0.z   SCL_212
> 0046  01802483 2003007d     7      y: MULADD_IEEE        R0.y,  KC0[3].y, R1.w, T1.x
> 0048  01802883 4003047d            z: MULADD_IEEE        R0.z,  KC0[3].z, R1.w, T1.y
> 0050  81802c83 6007007e            w: MULADD_IEEE        R0.w,  KC0[3].w, R1.w, T2.x   VEC_021
> 0052  01806087 0023047c     8      x: MULADD_IEEE        R1.x,  KC0[7].x, R3.w, T0.y
> 0054  01806487 2023007c            y: MULADD_IEEE        R1.y,  KC0[7].y, R3.w, T0.x
> 0056  81802083 0007087c            t: MULADD_IEEE        R0.x,  KC0[3].x, R1.w, T0.z   SCL_122
>0004  c000c000 94c00908 EXPORT             PARAM 0     R1.xy00
>0006  c000203c 95000688 EXPORT_DONE        POS   60    R0.xyzw
>0008  c0014001 95200688 EXPORT_DONE        PARAM 1     R2.xyzw  EOP
>===== SHADER_END ===============================================================
>
>--------------------------------------------------------------
>FRAG
>DCL IN[0], GENERIC[9], PERSPECTIVE
>DCL IN[1], GENERIC[10], PERSPECTIVE
>DCL IN[2], GENERIC[11], PERSPECTIVE
>DCL IN[3], GENERIC[12], PERSPECTIVE
>DCL IN[4], GENERIC[13], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SAMP[1]
>DCL SAMP[2]
>DCL SAMP[3]
>DCL SAMP[4]
>DCL SVIEW[0], 2D, FLOAT
>DCL SVIEW[1], 2D, FLOAT
>DCL SVIEW[2], 2D, FLOAT
>DCL SVIEW[3], 2D, FLOAT
>DCL SVIEW[4], 2D, FLOAT
>DCL CONST[5..9]
>DCL TEMP[0..7], LOCAL
>IMM[0] FLT32 {    0.5000,     1.0000,    -0.5000,     2.0000}
>IMM[1] FLT32 {   -1.0000,     0.0000,     0.2500,     0.0000}
>  0: MOV TEMP[0].xy, IN[1].xyyy
>  1: TEX TEMP[0], TEMP[0], SAMP[1], 2D
>  2: FSLT TEMP[1].x, TEMP[0].wwww, IMM[0].xxxx
>  3: AND TEMP[2].x, TEMP[1].xxxx, IMM[0].yyyy
>  4: KILL_IF -TEMP[2].xxxx
>  5: MUL TEMP[2].x, TEMP[0].wwww, CONST[9].xxxx
>  6: MOV TEMP[1].w, TEMP[2].xxxx
>  7: MOV TEMP[2].xy, IN[1].xyyy
>  8: TEX TEMP[2].xyz, TEMP[2], SAMP[0], 2D
>  9: ADD TEMP[2].xyz, TEMP[2].xyzz, IMM[0].zzzz
> 10: DP3 TEMP[3].x, TEMP[2].xyzz, TEMP[2].xyzz
> 11: RSQ TEMP[3].x, TEMP[3].xxxx
> 12: MUL TEMP[2].xyz, TEMP[2].xyzz, TEMP[3].xxxx
> 13: MOV TEMP[3].xy, IN[1].xyyy
> 14: TEX TEMP[3], TEMP[3], SAMP[2], 2D
> 15: MOV TEMP[4].xy, IN[1].zwww
> 16: TEX TEMP[4].xyz, TEMP[4], SAMP[4], 2D
> 17: MAD TEMP[4].xyz, TEMP[4].xyzz, IMM[0].wwww, IMM[1].xxxx
> 18: DP3 TEMP[5].x, TEMP[4].xyzz, IN[3].xyzz
> 19: DP3 TEMP[6].x, TEMP[4].xyzz, IN[4].xyzz
> 20: MOV TEMP[5].y, TEMP[6].xxxx
> 21: DP3 TEMP[4].x, TEMP[4].xyzz, IN[2].xyzz
> 22: MOV TEMP[5].z, TEMP[4].xxxx
> 23: DP3 TEMP[4].x, TEMP[5].xyzz, TEMP[5].xyzz
> 24: RSQ TEMP[4].x, TEMP[4].xxxx
> 25: MUL TEMP[4].xyz, TEMP[5].xyzz, TEMP[4].xxxx
> 26: MUL TEMP[5].xyz, TEMP[3].xyzz, CONST[7].xyzz
> 27: DP3 TEMP[6].x, TEMP[2].xyzz, TEMP[4].xyzz
> 28: MUL TEMP[6].xyz, TEMP[6].xxxx, TEMP[2].xyzz
> 29: MUL TEMP[6].xyz, IMM[0].wwww, TEMP[6].xyzz
> 30: ADD TEMP[6].xyz, TEMP[4].xyzz, -TEMP[6].xyzz
> 31: DP3 TEMP[7].x, IN[0].xyzz, IN[0].xyzz
> 32: RSQ TEMP[7].x, TEMP[7].xxxx
> 33: MUL TEMP[7].xyz, IN[0].xyzz, TEMP[7].xxxx
> 34: DP3 TEMP[6].x, TEMP[6].xyzz, TEMP[7].xyzz
> 35: MAX TEMP[6].x, -TEMP[6].xxxx, IMM[1].yyyy
> 36: MAD TEMP[3].x, CONST[8].xxxx, TEMP[3].wwww, IMM[0].yyyy
> 37: POW TEMP[3].x, TEMP[6].xxxx, TEMP[3].xxxx
> 38: MUL TEMP[6].xyz, TEMP[0].xyzz, CONST[6].xyzz
> 39: DP3 TEMP[2].x, TEMP[2].xyzz, TEMP[4].xyzz
> 40: MAX TEMP[2].x, TEMP[2].xxxx, IMM[1].yyyy
> 41: MUL TEMP[2].xyz, TEMP[6].xyzz, TEMP[2].xxxx
> 42: MAD TEMP[2].xyz, TEMP[5].xyzz, TEMP[3].xxxx, TEMP[2].xyzz
> 43: MOV TEMP[3].xy, IN[1].zwww
> 44: TEX TEMP[3].xyz, TEMP[3], SAMP[3], 2D
> 45: MAX TEMP[4].x, IMM[1].zzzz, TEMP[4].zzzz
> 46: RCP TEMP[4].x, TEMP[4].xxxx
> 47: MUL TEMP[3].xyz, TEMP[3].xyzz, TEMP[4].xxxx
> 48: MUL TEMP[0].xyz, TEMP[0].xyzz, CONST[5].xyzz
> 49: MAD TEMP[1].xyz, TEMP[2].xyzz, TEMP[3].xyzz, TEMP[0].xyzz
> 50: MOV OUT[0], TEMP[1]
> 51: END
>; ModuleID = 'tgsi'
>
>define void @main(<4 x float> inreg, <4 x float> inreg, <4 x float> inreg, <4 x float> inreg, <4 x float> inreg, <4 x float> inreg) #0 {
>main_body:
>  %6 = extractelement <4 x float> %0, i32 0
>  %7 = extractelement <4 x float> %0, i32 1
>  %8 = call <2 x float> @llvm.R600.interp.xy(i32 0, float %6, float %7)
>  %9 = call <2 x float> @llvm.R600.interp.zw(i32 0, float %6, float %7)
>  %10 = extractelement <2 x float> %8, i32 0
>  %11 = extractelement <2 x float> %8, i32 1
>  %12 = extractelement <2 x float> %9, i32 0
>  %13 = extractelement <4 x float> %0, i32 0
>  %14 = extractelement <4 x float> %0, i32 1
>  %15 = call <2 x float> @llvm.R600.interp.xy(i32 1, float %13, float %14)
>  %16 = call <2 x float> @llvm.R600.interp.zw(i32 1, float %13, float %14)
>  %17 = extractelement <4 x float> %0, i32 0
>  %18 = extractelement <4 x float> %0, i32 1
>  %19 = call <2 x float> @llvm.R600.interp.xy(i32 2, float %17, float %18)
>  %20 = call <2 x float> @llvm.R600.interp.zw(i32 2, float %17, float %18)
>  %21 = extractelement <2 x float> %19, i32 0
>  %22 = extractelement <2 x float> %19, i32 1
>  %23 = extractelement <2 x float> %20, i32 0
>  %24 = extractelement <4 x float> %0, i32 0
>  %25 = extractelement <4 x float> %0, i32 1
>  %26 = call <2 x float> @llvm.R600.interp.xy(i32 3, float %24, float %25)
>  %27 = call <2 x float> @llvm.R600.interp.zw(i32 3, float %24, float %25)
>  %28 = extractelement <2 x float> %26, i32 0
>  %29 = extractelement <2 x float> %26, i32 1
>  %30 = extractelement <2 x float> %27, i32 0
>  %31 = extractelement <4 x float> %0, i32 0
>  %32 = extractelement <4 x float> %0, i32 1
>  %33 = call <2 x float> @llvm.R600.interp.xy(i32 4, float %31, float %32)
>  %34 = call <2 x float> @llvm.R600.interp.zw(i32 4, float %31, float %32)
>  %35 = extractelement <2 x float> %33, i32 0
>  %36 = extractelement <2 x float> %33, i32 1
>  %37 = extractelement <2 x float> %34, i32 0
>  %38 = shufflevector <2 x float> %15, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
>  %39 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %38, i32 17, i32 1, i32 2)
>  %40 = extractelement <4 x float> %39, i32 0
>  %41 = extractelement <4 x float> %39, i32 1
>  %42 = extractelement <4 x float> %39, i32 2
>  %43 = extractelement <4 x float> %39, i32 3
>  %44 = fcmp olt float %43, 5.000000e-01
>  %45 = select i1 %44, float -1.000000e+00, float 0.000000e+00
>  call void @llvm.AMDGPU.kill(float %45)
>  %46 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9)
>  %47 = extractelement <4 x float> %46, i32 0
>  %48 = fmul float %43, %47
>  %49 = shufflevector <2 x float> %15, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
>  %50 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %49, i32 16, i32 0, i32 2)
>  %51 = extractelement <4 x float> %50, i32 0
>  %52 = extractelement <4 x float> %50, i32 1
>  %53 = extractelement <4 x float> %50, i32 2
>  %54 = fadd float %51, -5.000000e-01
>  %55 = fadd float %52, -5.000000e-01
>  %56 = fadd float %53, -5.000000e-01
>  %57 = insertelement <4 x float> undef, float %54, i32 0
>  %58 = insertelement <4 x float> %57, float %55, i32 1
>  %59 = insertelement <4 x float> %58, float %56, i32 2
>  %60 = insertelement <4 x float> %59, float 0.000000e+00, i32 3
>  %61 = insertelement <4 x float> undef, float %54, i32 0
>  %62 = insertelement <4 x float> %61, float %55, i32 1
>  %63 = insertelement <4 x float> %62, float %56, i32 2
>  %64 = insertelement <4 x float> %63, float 0.000000e+00, i32 3
>  %65 = call float @llvm.AMDGPU.dp4(<4 x float> %60, <4 x float> %64)
>  %66 = call float @llvm.AMDGPU.rsq.clamped.f32(float %65)
>  %67 = fmul float %54, %66
>  %68 = fmul float %55, %66
>  %69 = fmul float %56, %66
>  %70 = shufflevector <2 x float> %15, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
>  %71 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %70, i32 18, i32 2, i32 2)
>  %72 = extractelement <4 x float> %71, i32 0
>  %73 = extractelement <4 x float> %71, i32 1
>  %74 = extractelement <4 x float> %71, i32 2
>  %75 = extractelement <4 x float> %71, i32 3
>  %76 = shufflevector <2 x float> %16, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
>  %77 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %76, i32 20, i32 4, i32 2)
>  %78 = extractelement <4 x float> %77, i32 0
>  %79 = extractelement <4 x float> %77, i32 1
>  %80 = extractelement <4 x float> %77, i32 2
>  %81 = fmul float %78, 2.000000e+00
>  %82 = fadd float %81, -1.000000e+00
>  %83 = fmul float %79, 2.000000e+00
>  %84 = fadd float %83, -1.000000e+00
>  %85 = fmul float %80, 2.000000e+00
>  %86 = fadd float %85, -1.000000e+00
>  %87 = insertelement <4 x float> undef, float %82, i32 0
>  %88 = insertelement <4 x float> %87, float %84, i32 1
>  %89 = insertelement <4 x float> %88, float %86, i32 2
>  %90 = insertelement <4 x float> %89, float 0.000000e+00, i32 3
>  %91 = insertelement <4 x float> undef, float %28, i32 0
>  %92 = insertelement <4 x float> %91, float %29, i32 1
>  %93 = insertelement <4 x float> %92, float %30, i32 2
>  %94 = insertelement <4 x float> %93, float 0.000000e+00, i32 3
>  %95 = call float @llvm.AMDGPU.dp4(<4 x float> %90, <4 x float> %94)
>  %96 = insertelement <4 x float> undef, float %82, i32 0
>  %97 = insertelement <4 x float> %96, float %84, i32 1
>  %98 = insertelement <4 x float> %97, float %86, i32 2
>  %99 = insertelement <4 x float> %98, float 0.000000e+00, i32 3
>  %100 = insertelement <4 x float> undef, float %35, i32 0
>  %101 = insertelement <4 x float> %100, float %36, i32 1
>  %102 = insertelement <4 x float> %101, float %37, i32 2
>  %103 = insertelement <4 x float> %102, float 0.000000e+00, i32 3
>  %104 = call float @llvm.AMDGPU.dp4(<4 x float> %99, <4 x float> %103)
>  %105 = insertelement <4 x float> undef, float %82, i32 0
>  %106 = insertelement <4 x float> %105, float %84, i32 1
>  %107 = insertelement <4 x float> %106, float %86, i32 2
>  %108 = insertelement <4 x float> %107, float 0.000000e+00, i32 3
>  %109 = insertelement <4 x float> undef, float %21, i32 0
>  %110 = insertelement <4 x float> %109, float %22, i32 1
>  %111 = insertelement <4 x float> %110, float %23, i32 2
>  %112 = insertelement <4 x float> %111, float 0.000000e+00, i32 3
>  %113 = call float @llvm.AMDGPU.dp4(<4 x float> %108, <4 x float> %112)
>  %114 = insertelement <4 x float> undef, float %95, i32 0
>  %115 = insertelement <4 x float> %114, float %104, i32 1
>  %116 = insertelement <4 x float> %115, float %113, i32 2
>  %117 = insertelement <4 x float> %116, float 0.000000e+00, i32 3
>  %118 = insertelement <4 x float> undef, float %95, i32 0
>  %119 = insertelement <4 x float> %118, float %104, i32 1
>  %120 = insertelement <4 x float> %119, float %113, i32 2
>  %121 = insertelement <4 x float> %120, float 0.000000e+00, i32 3
>  %122 = call float @llvm.AMDGPU.dp4(<4 x float> %117, <4 x float> %121)
>  %123 = call float @llvm.AMDGPU.rsq.clamped.f32(float %122)
>  %124 = fmul float %95, %123
>  %125 = fmul float %104, %123
>  %126 = fmul float %113, %123
>  %127 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7)
>  %128 = extractelement <4 x float> %127, i32 0
>  %129 = fmul float %72, %128
>  %130 = extractelement <4 x float> %127, i32 1
>  %131 = fmul float %73, %130
>  %132 = extractelement <4 x float> %127, i32 2
>  %133 = fmul float %74, %132
>  %134 = insertelement <4 x float> undef, float %67, i32 0
>  %135 = insertelement <4 x float> %134, float %68, i32 1
>  %136 = insertelement <4 x float> %135, float %69, i32 2
>  %137 = insertelement <4 x float> %136, float 0.000000e+00, i32 3
>  %138 = insertelement <4 x float> undef, float %124, i32 0
>  %139 = insertelement <4 x float> %138, float %125, i32 1
>  %140 = insertelement <4 x float> %139, float %126, i32 2
>  %141 = insertelement <4 x float> %140, float 0.000000e+00, i32 3
>  %142 = call float @llvm.AMDGPU.dp4(<4 x float> %137, <4 x float> %141)
>  %143 = fmul float %142, %67
>  %144 = fmul float %142, %68
>  %145 = fmul float %142, %69
>  %146 = fmul float %143, 2.000000e+00
>  %147 = fmul float %144, 2.000000e+00
>  %148 = fmul float %145, 2.000000e+00
>  %149 = fsub float %124, %146
>  %150 = fsub float %125, %147
>  %151 = fsub float %126, %148
>  %152 = insertelement <4 x float> undef, float %10, i32 0
>  %153 = insertelement <4 x float> %152, float %11, i32 1
>  %154 = insertelement <4 x float> %153, float %12, i32 2
>  %155 = insertelement <4 x float> %154, float 0.000000e+00, i32 3
>  %156 = insertelement <4 x float> undef, float %10, i32 0
>  %157 = insertelement <4 x float> %156, float %11, i32 1
>  %158 = insertelement <4 x float> %157, float %12, i32 2
>  %159 = insertelement <4 x float> %158, float 0.000000e+00, i32 3
>  %160 = call float @llvm.AMDGPU.dp4(<4 x float> %155, <4 x float> %159)
>  %161 = call float @llvm.AMDGPU.rsq.clamped.f32(float %160)
>  %162 = fmul float %10, %161
>  %163 = fmul float %11, %161
>  %164 = fmul float %12, %161
>  %165 = insertelement <4 x float> undef, float %149, i32 0
>  %166 = insertelement <4 x float> %165, float %150, i32 1
>  %167 = insertelement <4 x float> %166, float %151, i32 2
>  %168 = insertelement <4 x float> %167, float 0.000000e+00, i32 3
>  %169 = insertelement <4 x float> undef, float %162, i32 0
>  %170 = insertelement <4 x float> %169, float %163, i32 1
>  %171 = insertelement <4 x float> %170, float %164, i32 2
>  %172 = insertelement <4 x float> %171, float 0.000000e+00, i32 3
>  %173 = call float @llvm.AMDGPU.dp4(<4 x float> %168, <4 x float> %172)
>  %174 = fsub float -0.000000e+00, %173
>  %175 = fcmp ule float %173, -0.000000e+00
>  %176 = select i1 %175, float %174, float 0.000000e+00
>  %177 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8)
>  %178 = extractelement <4 x float> %177, i32 0
>  %179 = fmul float %178, %75
>  %180 = fadd float %179, 1.000000e+00
>  %181 = call float @llvm.pow.f32(float %176, float %180)
>  %182 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6)
>  %183 = extractelement <4 x float> %182, i32 0
>  %184 = fmul float %40, %183
>  %185 = extractelement <4 x float> %182, i32 1
>  %186 = fmul float %41, %185
>  %187 = extractelement <4 x float> %182, i32 2
>  %188 = fmul float %42, %187
>  %189 = insertelement <4 x float> undef, float %67, i32 0
>  %190 = insertelement <4 x float> %189, float %68, i32 1
>  %191 = insertelement <4 x float> %190, float %69, i32 2
>  %192 = insertelement <4 x float> %191, float 0.000000e+00, i32 3
>  %193 = insertelement <4 x float> undef, float %124, i32 0
>  %194 = insertelement <4 x float> %193, float %125, i32 1
>  %195 = insertelement <4 x float> %194, float %126, i32 2
>  %196 = insertelement <4 x float> %195, float 0.000000e+00, i32 3
>  %197 = call float @llvm.AMDGPU.dp4(<4 x float> %192, <4 x float> %196)
>  %.inv = fcmp olt float %197, 0.000000e+00
>  %198 = select i1 %.inv, float 0.000000e+00, float %197
>  %199 = fmul float %184, %198
>  %200 = fmul float %186, %198
>  %201 = fmul float %188, %198
>  %202 = fmul float %129, %181
>  %203 = fadd float %202, %199
>  %204 = fmul float %131, %181
>  %205 = fadd float %204, %200
>  %206 = fmul float %133, %181
>  %207 = fadd float %206, %201
>  %208 = shufflevector <2 x float> %16, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
>  %209 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %208, i32 19, i32 3, i32 2)
>  %210 = extractelement <4 x float> %209, i32 0
>  %211 = extractelement <4 x float> %209, i32 1
>  %212 = extractelement <4 x float> %209, i32 2
>  %.inv32 = fcmp ogt float %126, 2.500000e-01
>  %.op = fdiv float 1.000000e+00, %126
>  %213 = select i1 %.inv32, float %.op, float 4.000000e+00
>  %214 = fmul float %210, %213
>  %215 = fmul float %211, %213
>  %216 = fmul float %212, %213
>  %217 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5)
>  %218 = extractelement <4 x float> %217, i32 0
>  %219 = fmul float %40, %218
>  %220 = extractelement <4 x float> %217, i32 1
>  %221 = fmul float %41, %220
>  %222 = extractelement <4 x float> %217, i32 2
>  %223 = fmul float %42, %222
>  %224 = fmul float %203, %214
>  %225 = fadd float %224, %219
>  %226 = fmul float %205, %215
>  %227 = fadd float %226, %221
>  %228 = fmul float %207, %216
>  %229 = fadd float %228, %223
>  %230 = insertelement <4 x float> undef, float %225, i32 0
>  %231 = insertelement <4 x float> %230, float %227, i32 1
>  %232 = insertelement <4 x float> %231, float %229, i32 2
>  %233 = insertelement <4 x float> %232, float %48, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %233, i32 0, i32 0)
>  ret void
>}
>
>; Function Attrs: readnone
>declare <2 x float> @llvm.R600.interp.xy(i32, float, float) #1
>
>; Function Attrs: readnone
>declare <2 x float> @llvm.R600.interp.zw(i32, float, float) #1
>
>; Function Attrs: readnone
>declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32, i32) #1
>
>declare void @llvm.AMDGPU.kill(float)
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.AMDGPU.rsq.clamped.f32(float) #2
>
>; Function Attrs: nounwind readnone
>declare float @llvm.pow.f32(float, float) #2
>
>declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { readnone }
>attributes #2 = { nounwind readnone }
>
>===== SHADER #39 ==================================== PS/REDWOOD/EVERGREEN =====
>===== 324 dw ===== 10 gprs ===== 0 stack =======================================
>0000  00000012 a0440000 ALU 18 @36
> 0036  00380400 00346b10     1      x: INTERP_XY          R1.x,  R0.y, Param0.x         VEC_210
> 0038  00380000 20346b10            y: INTERP_XY          R1.y,  R0.x, Param0.x         VEC_210
> 0040  00380400 40146b00            z: INTERP_XY          __.z,  R0.y, Param0.x         VEC_210
> 0042  80380000 60146b00            w: INTERP_XY          __.w,  R0.x, Param0.x         VEC_210
> 0044  00380400 00146b80     2      x: INTERP_ZW          __.x,  R0.y, Param0.x         VEC_210
> 0046  00380000 20146b80            y: INTERP_ZW          __.y,  R0.x, Param0.x         VEC_210
> 0048  00380400 40346b90            z: INTERP_ZW          R1.z,  R0.y, Param0.x         VEC_210
> 0050  80380000 60346b90            w: INTERP_ZW          R1.w,  R0.x, Param0.x         VEC_210
> 0052  00382400 00546b10     3      x: INTERP_XY          R2.x,  R0.y, Param1.x         VEC_210
> 0054  00382000 20546b10            y: INTERP_XY          R2.y,  R0.x, Param1.x         VEC_210
> 0056  00382400 40146b00            z: INTERP_XY          __.z,  R0.y, Param1.x         VEC_210
> 0058  80382000 60146b00            w: INTERP_XY          __.w,  R0.x, Param1.x         VEC_210
> 0060  00382400 00146b80     4      x: INTERP_ZW          __.x,  R0.y, Param1.x         VEC_210
> 0062  00382000 20146b80            y: INTERP_ZW          __.y,  R0.x, Param1.x         VEC_210
> 0064  00382400 40746b90            z: INTERP_ZW          R3.z,  R0.y, Param1.x         VEC_210
> 0066  80382000 60346b90            w: INTERP_ZW          R1.w,  R0.x, Param1.x         VEC_210
> 0068  000008fe 00600c90     5      x: MOV                R3.x,  PV.z
> 0070  80000cfe 20600c90            y: MOV                R3.y,  PV.w
>0002  00000008 80400400 TEX 2 @16
> 0016  00031410 f00d1004 fc820000 SAMPLE              R4.xyzw, R3.xy__,   RID:20, SID:4 CT:NNNN
> 0020  00021010 f00d1005 fc800000 SAMPLE              R5.xyzw, R2.xy__,   RID:16, SID:0 CT:NNNN
>0004  00000024 a0240000 ALU 10 @72
> 0072  001fa005 00c00010     6      x: ADD                R6.x,  R5.x, [0xbf000000 -0.5].x
> 0074  001fa405 20c00010            y: ADD                R6.y,  R5.y, [0xbf000000 -0.5].x
> 0076  00808404 60280010            w: ADD                R1.w,  R4.y, R4.y             VEC_120
> 0078  80008004 60c00010            t: ADD                R6.w,  R4.x, R4.x
> 0080  bf000000 
> 0082  001fa0ff 00e00010     7      x: ADD                R7.x,  PS, [0xbf800000 -1].x
> 0084  001facfe 20e00010            y: ADD                R7.y,  PV.w, [0xbf800000 -1].x
> 0086  009fa805 40a00010            z: ADD                R5.z,  R5.z, [0xbf000000 -0.5].y
> 0088  81008804 60280010            w: ADD                R1.w,  R4.z, R4.z             VEC_120
> 0090  bf800000 
> 0091  bf000000 
>0006  0000000c 80400800 TEX 3 @24
> 0024  00031310 f00d1003 fc818000 SAMPLE              R3.xyzw, R3.xy__,   RID:19, SID:3 CT:NNNN
> 0028  00021210 f00d1004 fc810000 SAMPLE              R4.xyzw, R2.xy__,   RID:18, SID:2 CT:NNNN
> 0032  00021110 f00d1002 fc808000 SAMPLE              R2.xyzw, R2.xy__,   RID:17, SID:1 CT:NNNN
>0008  8000002e a1cc0000 ALU 116 @92 KC0[CB0:0-31]
> 0092  801fac01 40c00010     8      z: ADD                R6.z,  R1.w, [0xbf800000 -1].x
> 0094  bf800000 
> 0096  00384400 00b46b10     9      x: INTERP_XY          R5.x,  R0.y, Param2.x         VEC_210
> 0098  00384000 20b46b10            y: INTERP_XY          R5.y,  R0.x, Param2.x         VEC_210
> 0100  00384400 40146b00            z: INTERP_XY          __.z,  R0.y, Param2.x         VEC_210
> 0102  80384000 60146b00            w: INTERP_XY          __.w,  R0.x, Param2.x         VEC_210
> 0104  00384400 00146b80    10      x: INTERP_ZW          __.x,  R0.y, Param2.x         VEC_210
> 0106  00384000 20146b80            y: INTERP_ZW          __.y,  R0.x, Param2.x         VEC_210
> 0108  00384400 40f46b90            z: INTERP_ZW          R7.z,  R0.y, Param2.x         VEC_210
> 0110  80384000 60346b90            w: INTERP_ZW          R1.w,  R0.x, Param2.x         VEC_210
> 0112  00386400 01146b10    11      x: INTERP_XY          R8.x,  R0.y, Param3.x         VEC_210
> 0114  00386000 21146b10            y: INTERP_XY          R8.y,  R0.x, Param3.x         VEC_210
> 0116  00386400 40146b00            z: INTERP_XY          __.z,  R0.y, Param3.x         VEC_210
> 0118  80386000 60146b00            w: INTERP_XY          __.w,  R0.x, Param3.x         VEC_210
> 0120  00386400 00146b80    12      x: INTERP_ZW          __.x,  R0.y, Param3.x         VEC_210
> 0122  00386000 20146b80            y: INTERP_ZW          __.y,  R0.x, Param3.x         VEC_210
> 0124  00386400 41146b90            z: INTERP_ZW          R8.z,  R0.y, Param3.x         VEC_210
> 0126  80386000 60346b90            w: INTERP_ZW          R1.w,  R0.x, Param3.x         VEC_210
> 0128  00010007 01005f10    13      x: DOT4               R8.x,  R7.x, R8.x
> 0130  00810407 21005f00            y: DOT4               __.y,  R7.y, R8.y
> 0132  01010806 41005f00            z: DOT4               __.z,  R6.z, R8.z
> 0134  801f00f8 61005f00            w: DOT4               __.w,  0, 0
> 0136  00388400 01346b10    14      x: INTERP_XY          R9.x,  R0.y, Param4.x         VEC_210
> 0138  00388000 21146b10            y: INTERP_XY          R8.y,  R0.x, Param4.x         VEC_210
> 0140  00388400 40146b00            z: INTERP_XY          __.z,  R0.y, Param4.x         VEC_210
> 0142  80388000 60146b00            w: INTERP_XY          __.w,  R0.x, Param4.x         VEC_210
> 0144  00388400 00146b80    15      x: INTERP_ZW          __.x,  R0.y, Param4.x         VEC_210
> 0146  00388000 20146b80            y: INTERP_ZW          __.y,  R0.x, Param4.x         VEC_210
> 0148  00388400 40146b90            z: INTERP_ZW          R0.z,  R0.y, Param4.x         VEC_210
> 0150  80388000 60146b90            w: INTERP_ZW          R0.w,  R0.x, Param4.x         VEC_210
> 0152  00012007 00005f00    16      x: DOT4               __.x,  R7.x, R9.x
> 0154  00810407 20005f10            y: DOT4               R0.y,  R7.y, R8.y
> 0156  01000806 40005f00            z: DOT4               __.z,  R6.z, R0.z
> 0158  801f00f8 60005f00            w: DOT4               __.w,  0, 0
> 0160  0000a007 00005f00    17      x: DOT4               __.x,  R7.x, R5.x
> 0162  0080a407 20005f00            y: DOT4               __.y,  R7.y, R5.y
> 0164  0100e806 40005f10            z: DOT4               R0.z,  R6.z, R7.z
> 0166  801f00f8 60005f00            w: DOT4               __.w,  0, 0
> 0168  0000c006 00005f10    18      x: DOT4               R0.x,  R6.x, R6.x
> 0170  0080c406 20005f00            y: DOT4               __.y,  R6.y, R6.y
> 0172  0100a805 40005f00            z: DOT4               __.z,  R5.z, R5.z
> 0174  801f00f8 60005f00            w: DOT4               __.w,  0, 0
> 0176  800000fe 00004390    19      t: RECIPSQRT_CLAMPED  R0.x,  PV.x
> 0178  00010008 00005f00    20      x: DOT4               __.x,  R8.x, R8.x
> 0180  00800400 20005f00            y: DOT4               __.y,  R0.y, R0.y
> 0182  01000800 40005f00            z: DOT4               __.z,  R0.z, R0.z
> 0184  801f00f8 60005f10            w: DOT4               R0.w,  0, 0
> 0186  800000fe 60004390    21      t: RECIPSQRT_CLAMPED  R0.w,  PV.x
> 0188  001fe008 00a00110    22      x: MUL_IEEE           R5.x,  R8.x, PS
> 0190  00000406 20a00110            y: MUL_IEEE           R5.y,  R6.y, R0.x
> 0192  001fe800 40c00110            z: MUL_IEEE           R6.z,  R0.z, PS
> 0194  80000006 00c00110            t: MUL_IEEE           R6.x,  R6.x, R0.x
> 0196  01800400 20c00110    23      y: MUL_IEEE           R6.y,  R0.y, R0.w
> 0198  80000805 40a00110            z: MUL_IEEE           R5.z,  R5.z, R0.x
> 0200  0000a006 00005f10    24      x: DOT4               R0.x,  R6.x, R5.x
> 0202  0080c405 20005f00            y: DOT4               __.y,  R5.y, R6.y
> 0204  0100c805 40005f00            z: DOT4               __.z,  R5.z, R6.z
> 0206  801f00f8 60005f00            w: DOT4               __.w,  0, 0
> 0208  0080a0fe 60200110    25      w: MUL_IEEE           R1.w,  PV.x, R5.y
> 0210  8100a0fe 60a00110            t: MUL_IEEE           R5.w,  PV.x, R5.z
> 0212  0100a000 40a300ff    26      z: MULADD_IEEE        R5.z,  R0.x, R5.z, PS
> 0214  0080a000 60230cfe            w: MULADD_IEEE        R1.w,  R0.x, R5.y, PV.w
> 0216  8000c000 60a00110            t: MUL_IEEE           R5.w,  R0.x, R6.x
> 0218  8000c000 60a300ff    27      w: MULADD_IEEE        R5.w,  R0.x, R6.x, PS
> 0220  00002001 00a05f10    28      x: DOT4               R5.x,  R1.x, R1.x
> 0222  00802401 20a05f00            y: DOT4               __.y,  R1.y, R1.y
> 0224  01002801 40a05f00            z: DOT4               __.z,  R1.z, R1.z
> 0226  801f00f8 60a05f00            w: DOT4               __.w,  0, 0
> 0228  01800008 00c31c05    29      x: MULADD_IEEE        R6.x,  R8.x, R0.w, -R5.w
> 0230  01800400 20171c01            y: MULADD_IEEE        R0.y,  R0.y, R0.w, -R1.w      VEC_210
> 0232  01800800 40031805            z: MULADD_IEEE        R0.z,  R0.z, R0.w, -R5.z
> 0234  800000fe 60004390            t: RECIPSQRT_CLAMPED  R0.w,  PV.x
> 0236  001fe001 00200110    30      x: MUL_IEEE           R1.x,  R1.x, PS
> 0238  001fe401 20200110            y: MUL_IEEE           R1.y,  R1.y, PS
> 0240  801fe801 40200110            z: MUL_IEEE           R1.z,  R1.z, PS
> 0242  00002006 00005f00    31      x: DOT4               __.x,  R6.x, R1.x
> 0244  00802400 20005f10            y: DOT4               R0.y,  R0.y, R1.y
> 0246  01002800 40005f00            z: DOT4               __.z,  R0.z, R1.z
> 0248  801f00f8 60005f00            w: DOT4               __.w,  0, 0
> 0250  001f00fe 400350fe    32      z: CNDGT              R0.z,  PV.x, 0, -PV.x
> 0252  000000f8 60000190            w: MAX                R0.w,  0, R0.x
> 0254  8110c802 60200110            t: MUL_IEEE           R1.w,  R2.z, KC0[6].z
> 0256  019fc0ff 20000110    33      y: MUL_IEEE           R0.y,  PS, PV.w
> 0258  0110e804 40200110            z: MUL_IEEE           R1.z,  R4.z, KC0[7].z
> 0260  01808088 602300f9            w: MULADD_IEEE        R1.w,  KC0[8].x, R4.w, 1.0
> 0262  800008fe 00004190            t: LOG_IEEE           R0.x,  PV.z
> 0264  001fecfe 00000090    34      x: MUL                R0.x,  PV.w, PS
> 0266  0010c002 20200110            y: MUL_IEEE           R1.y,  R2.x, KC0[6].x
> 0268  001fa806 40000490            z: SETGT              R0.z,  R6.z, [0x3e800000 0.25].x
> 0270  0090c402 60200110            w: MUL_IEEE           R1.w,  R2.y, KC0[6].y
> 0272  80000806 00204310            t: RECIP_IEEE         R1.x,  R6.z
> 0274  3e800000 
> 0276  01800cfe 00a00110    35      x: MUL_IEEE           R5.x,  PV.w, R0.w
> 0278  001fa8fe 20a320ff            y: CNDE               R5.y,  PV.z, [0x40800000 4].x, PS
> 0280  018004fe 40000110            z: MUL_IEEE           R0.z,  PV.y, R0.w
> 0282  0010e004 60000110            w: MUL_IEEE           R0.w,  R4.x, KC0[7].x
> 0284  800000fe 00004090            t: EXP_IEEE           R0.x,  PV.x
> 0286  40800000 
> 0288  0090e404 00200110    36      x: MUL_IEEE           R1.x,  R4.y, KC0[7].y
> 0290  001fecfe 202308fe            y: MULADD_IEEE        R1.y,  PV.w, PS, PV.z
> 0292  009fc003 40000110            z: MUL_IEEE           R0.z,  R3.x, PV.y
> 0294  8010a002 60080110            w: MUL_IEEE           R0.w,  R2.x, KC0[5].x         VEC_120
> 0296  80112c02 60800110    37      w: MUL_IEEE           R4.w,  R2.w, KC0[9].x
> 0298  01000401 00830c00    38      x: MULADD_IEEE        R4.x,  R1.y, R0.z, R0.w
> 0300  00000001 20230005            y: MULADD_IEEE        R1.y,  R1.x, R0.x, R5.x
> 0302  8080a403 40080110            z: MUL_IEEE           R0.z,  R3.y, R5.y             VEC_120
> 0304  0090a402 60000110    39      w: MUL_IEEE           R0.w,  R2.y, KC0[5].y
> 0306  818040fc 60200490            t: SETGT              R1.w,  0.5, R2.w
> 0308  001f00ff 002320fd    40      x: CNDE               R1.x,  PS, 0, [0xbf800000 -1].x
> 0310  01000401 20830cfe            y: MULADD_IEEE        R4.y,  R1.y, R0.z, PV.w
> 0312  00000801 40030400            z: MULADD_IEEE        R0.z,  R1.z, R0.x, R0.y
> 0314  8080a803 60140110            w: MUL_IEEE           R0.w,  R3.z, R5.y             VEC_210
> 0316  bf800000 
> 0318  8110a802 60200110    41      w: MUL_IEEE           R1.w,  R2.z, KC0[5].z
> 0320  01800800 40830cfe    42      z: MULADD_IEEE        R4.z,  R0.z, R0.w, PV.w
> 0322  800020f8 60001680            w: KILLGT             __.w,  0, R1.x
>0010  c0020000 95200688 EXPORT_DONE        PIXEL 0     R4.xyzw  EOP
>===== SHADER_END ===============================================================
>
>
>===== SHADER #39 OPT ================================ PS/REDWOOD/EVERGREEN =====
>===== 320 dw ===== 6 gprs ===== 0 stack ========================================
>0000  00000007 a00c0000 ALU 4 @14
> 0014  00382400 00346b10     1      x: INTERP_XY          R1.x,  R0.y, Param1.x         VEC_210
> 0016  00b82000 20346b10            y: INTERP_XY          R1.y,  R0.x, Param1.y         VEC_210
> 0018  01382400 40146b00            z: INTERP_XY          __.z,  R0.y, Param1.z         VEC_210
> 0020  81b82000 60146b00            w: INTERP_XY          __.w,  R0.x, Param1.w         VEC_210
>0002  0000000c 80400000 TEX 1 @24
> 0024  00011110 f00d1002 fc808000 SAMPLE              R2.xyzw, R1.xy__,   RID:17, SID:1 CT:NNNN
>0004  0000000e a01c0000 ALU 8 @28
> 0028  818040fc 4f800490     2      z: SETGT              T0.z,  0.5, R2.w
> 0030  00382400 00146b80     3      x: INTERP_ZW          __.x,  R0.y, Param1.x         VEC_210
> 0032  00b82000 20146b80            y: INTERP_ZW          __.y,  R0.x, Param1.y         VEC_210
> 0034  01382400 40146b90            z: INTERP_ZW          R0.z,  R0.y, Param1.z         VEC_210
> 0036  01b82000 60146b90            w: INTERP_ZW          R0.w,  R0.x, Param1.w         VEC_210
> 0038  801f087c 4f8320fd            t: CNDE               T0.z,  T0.z, 0, [0xbf800000 -1].x
> 0040  bf800000 
> 0042  810f80f8 00001680     4      x: KILLGT             __.x,  0, T0.z
>0006  00000016 80400c00 TEX 4 @44
> 0044  00001410 f01d1005 fda20000 SAMPLE              R5.xyz_, R0.zw__,   RID:20, SID:4 CT:NNNN
> 0048  00011010 f01d1004 fc800000 SAMPLE              R4.xyz_, R1.xy__,   RID:16, SID:0 CT:NNNN
> 0052  00011210 f00d1001 fc810000 SAMPLE              R1.xyzw, R1.xy__,   RID:18, SID:2 CT:NNNN
> 0056  00001310 f01d1003 fda18000 SAMPLE              R3.xyz_, R0.zw__,   RID:19, SID:3 CT:NNNN
>0008  0000001e a00c0000 ALU 4 @60
> 0060  00384400 00146b80     5      x: INTERP_ZW          __.x,  R0.y, Param2.x         VEC_210
> 0062  00b84000 20146b80            y: INTERP_ZW          __.y,  R0.x, Param2.y         VEC_210
> 0064  01384400 40146b90            z: INTERP_ZW          R0.z,  R0.y, Param2.z         VEC_210
> 0066  81b84000 60146b80            w: INTERP_ZW          __.w,  R0.x, Param2.w         VEC_210
>0010  40000022 a1f40000 ALU 126 @68 KC0[CB0:0-15]
> 0068  00384400 0fd46b10     6      x: INTERP_XY          T2.x,  R0.y, Param2.x         VEC_210
> 0070  00b84000 2fd46b10            y: INTERP_XY          T2.y,  R0.x, Param2.y         VEC_210
> 0072  01384400 40146b00            z: INTERP_XY          __.z,  R0.y, Param2.z         VEC_210
> 0074  81b84000 60146b00            w: INTERP_XY          __.w,  R0.x, Param2.w         VEC_210
> 0076  001fa005 4f8284fd     7      z: MULADD             T0.z,  R5.x, [0x40000000 2].x, [0xbf800000 -1].y
> 0078  801fa405 6f8284fd            w: MULADD             T0.w,  R5.y, [0x40000000 2].x, [0xbf800000 -1].y
> 0080  40000000 
> 0081  bf800000 
> 0082  00388400 00146b80     8      x: INTERP_ZW          __.x,  R0.y, Param4.x         VEC_210
> 0084  00b88000 20146b80            y: INTERP_ZW          __.y,  R0.x, Param4.y         VEC_210
> 0086  01388400 4ff46b90            z: INTERP_ZW          T3.z,  R0.y, Param4.z         VEC_210
> 0088  81b88000 60146b80            w: INTERP_ZW          __.w,  R0.x, Param4.w         VEC_210
> 0090  00388400 0fb46b10     9      x: INTERP_XY          T1.x,  R0.y, Param4.x         VEC_210
> 0092  00b88000 2fb46b10            y: INTERP_XY          T1.y,  R0.x, Param4.y         VEC_210
> 0094  01388400 40146b00            z: INTERP_XY          __.z,  R0.y, Param4.z         VEC_210
> 0096  81b88000 60146b00            w: INTERP_XY          __.w,  R0.x, Param4.w         VEC_210
> 0098  00386400 00146b80    10      x: INTERP_ZW          __.x,  R0.y, Param3.x         VEC_210
> 0100  00b86000 20146b80            y: INTERP_ZW          __.y,  R0.x, Param3.y         VEC_210
> 0102  01386400 4fb46b90            z: INTERP_ZW          T1.z,  R0.y, Param3.z         VEC_210
> 0104  81b86000 60146b80            w: INTERP_ZW          __.w,  R0.x, Param3.w         VEC_210
> 0106  00386400 0f946b10    11      x: INTERP_XY          T0.x,  R0.y, Param3.x         VEC_210
> 0108  00b86000 2f946b10            y: INTERP_XY          T0.y,  R0.x, Param3.y         VEC_210
> 0110  01386400 40146b00            z: INTERP_XY          __.z,  R0.y, Param3.z         VEC_210
> 0112  01b86000 60146b00            w: INTERP_XY          __.w,  R0.x, Param3.w         VEC_210
> 0114  801fa805 6fa284fd            t: MULADD             T1.w,  R5.z, [0x40000000 2].x, [0xbf800000 -1].y
> 0116  40000000 
> 0117  bf800000 
> 0118  000fc87c 00005f00    12      x: DOT4               __.x,  T0.z, T2.x
> 0120  008fcc7c 20005f00            y: DOT4               __.y,  T0.w, T2.y
> 0122  01000c7d 4fc85f10            z: DOT4               T2.z,  T1.w, R0.z             VEC_120
> 0124  801f00f8 60005f00            w: DOT4               __.w,  0, 0
> 0126  000fa87c 00005f00    13      x: DOT4               __.x,  T0.z, T1.x
> 0128  008fac7c 2fe05f10            y: DOT4               T3.y,  T0.w, T1.y
> 0130  010fec7d 40085f00            z: DOT4               __.z,  T1.w, T3.z             VEC_120
> 0132  801f00f8 60005f00            w: DOT4               __.w,  0, 0
> 0134  000f887c 0fe05f10    14      x: DOT4               T3.x,  T0.z, T0.x
> 0136  008f8c7c 20005f00            y: DOT4               __.y,  T0.w, T0.y
> 0138  010fac7d 40085f00            z: DOT4               __.z,  T1.w, T1.z             VEC_120
> 0140  801f00f8 60005f00            w: DOT4               __.w,  0, 0
> 0142  001fa804 4f800010    15      z: ADD                T0.z,  R4.z, [0xbf000000 -0.5].x
> 0144  801fa404 6fa00010            w: ADD                T1.w,  R4.y, [0xbf000000 -0.5].x
> 0146  bf000000 
> 0148  000fe07f 00005f00    16      x: DOT4               __.x,  T3.x, T3.x
> 0150  008fe47f 20005f00            y: DOT4               __.y,  T3.y, T3.y
> 0152  010fc87e 4fa05f10            z: DOT4               T1.z,  T2.z, T2.z
> 0154  001f00f8 60005f00            w: DOT4               __.w,  0, 0
> 0156  801fa004 6f800010            t: ADD                T0.w,  R4.x, [0xbf000000 -0.5].x
> 0158  bf000000 
> 0160  018f8c7c 0f805f10    17      x: DOT4               T0.x,  T0.w, T0.w
> 0162  018fac7d 20085f00            y: DOT4               __.y,  T1.w, T1.w             VEC_120
> 0164  010f887c 40005f00            z: DOT4               __.z,  T0.z, T0.z
> 0166  801f00f8 60005f00            w: DOT4               __.w,  0, 0
> 0168  00380400 00146b80    18      x: INTERP_ZW          __.x,  R0.y, Param0.x         VEC_210
> 0170  00b80000 20146b80            y: INTERP_ZW          __.y,  R0.x, Param0.y         VEC_210
> 0172  01380400 4fb46b90            z: INTERP_ZW          T1.z,  R0.y, Param0.z         VEC_210
> 0174  01b80000 60146b80            w: INTERP_ZW          __.w,  R0.x, Param0.w         VEC_210
> 0176  8000087d 6fe04390            t: RECIPSQRT_CLAMPED  T3.w,  T1.z
> 0178  00380400 0fd46b10    19      x: INTERP_XY          T2.x,  R0.y, Param0.x         VEC_210
> 0180  00b80000 2fd46b10            y: INTERP_XY          T2.y,  R0.x, Param0.y         VEC_210
> 0182  01380400 40146b00            z: INTERP_XY          __.z,  R0.y, Param0.z         VEC_210
> 0184  01b80000 60146b00            w: INTERP_XY          __.w,  R0.x, Param0.w         VEC_210
> 0186  8000007c 0fa44390            t: RECIPSQRT_CLAMPED  T1.x,  T0.x                   SCL_122
> 0188  000fac7d 0f800110    20      x: MUL_IEEE           T0.x,  T1.w, T1.x
> 0190  018fe47f 2f800110            y: MUL_IEEE           T0.y,  T3.y, T3.w
> 0192  000fa87c 4f800110            z: MUL_IEEE           T0.z,  T0.z, T1.x
> 0194  018fe07f 6fa00110            w: MUL_IEEE           T1.w,  T3.x, T3.w
> 0196  818fe87e 6fc00110            t: MUL_IEEE           T2.w,  T2.z, T3.w
> 0198  000fc07e 0fa05f10    21      x: DOT4               T1.x,  T2.x, T2.x
> 0200  008fc47e 20005f00            y: DOT4               __.y,  T2.y, T2.y
> 0202  010fa87d 40005f00            z: DOT4               __.z,  T1.z, T1.z
> 0204  001f00f8 60005f00            w: DOT4               __.w,  0, 0
> 0206  800fac7c 6f800110            t: MUL_IEEE           T0.w,  T0.w, T1.x
> 0208  018fac7c 00005f00    22      x: DOT4               __.x,  T0.w, T1.w
> 0210  008f807c 2fa05f10            y: DOT4               T1.y,  T0.x, T0.y
> 0212  018fc87c 40045f00            z: DOT4               __.z,  T0.z, T2.w             VEC_021
> 0214  801f00f8 60005f00            w: DOT4               __.w,  0, 0
> 0216  801fa87c 6fa00090    23      w: MUL                T1.w,  T0.z, [0x40000000 2].x
> 0218  40000000 
> 0220  001fa07c 0f800090    24      x: MUL                T0.x,  T0.x, [0x40000000 2].x
> 0222  001fac7c 6f800090            w: MUL                T0.w,  T0.w, [0x40000000 2].x
> 0224  8000007d 4f804390            t: RECIPSQRT_CLAMPED  T0.z,  T1.x
> 0226  40000000 
> 0228  010f887d 0fa00110    25      x: MUL_IEEE           T1.x,  T1.z, T0.z
> 0230  018f847d 2f800110            y: MUL_IEEE           T0.y,  T1.y, T0.w
> 0232  018fa47d 6f840110            w: MUL_IEEE           T0.w,  T1.y, T1.w             VEC_021
> 0234  800f847d 0f800110            t: MUL_IEEE           T0.x,  T1.y, T0.x
> 0236  018fe07f 0f83147c    26      x: MULADD_IEEE        T0.x,  T3.x, T3.w, -T0.y
> 0238  010f807e 2f8c0110            y: MUL_IEEE           T0.y,  T2.x, T0.z             VEC_102
> 0240  018fe47f 4f83107c            z: MULADD_IEEE        T0.z,  T3.y, T3.w, -T0.x
> 0242  010f847e 6f8c0110            w: MUL_IEEE           T0.w,  T2.y, T0.z             VEC_102
> 0244  818fe87e 6fa31c7c            t: MULADD_IEEE        T1.w,  T2.z, T3.w, -T0.w
> 0246  008f807c 0f805f10    27      x: DOT4               T0.x,  T0.x, T0.y
> 0248  018f887c 20005f00            y: DOT4               __.y,  T0.z, T0.w
> 0250  000fac7d 40005f00            z: DOT4               __.z,  T1.w, T1.x
> 0252  801f00f8 60005f00            w: DOT4               __.w,  0, 0
> 0254  801f007c 0f83507c    28      x: CNDGT              T0.x,  T0.x, 0, -T0.x
> 0256  01802088 2f8300f9    29      y: MULADD_IEEE        T0.y,  KC0[8].x, R1.w, 1.0
> 0258  8000007c 0f804190            t: LOG_IEEE           T0.x,  T0.x
> 0260  000f847c 0f880090    30      x: MUL                T0.x,  T0.y, T0.x             VEC_120
> 0262  0110c802 2f800110            y: MUL_IEEE           T0.y,  R2.z, KC0[6].z
> 0264  001f047d 4fc00190            z: MAX                T2.z,  T1.y, 0
> 0266  80000c7e 6fa04310            t: RECIP_IEEE         T1.w,  T2.w
> 0268  0010c002 0f800110    31      x: MUL_IEEE           T0.x,  R2.x, KC0[6].x
> 0270  010fc47c 2fa00110            y: MUL_IEEE           T1.y,  T0.y, T2.z
> 0272  0110e801 4fa00110            z: MUL_IEEE           T1.z,  R1.z, KC0[7].z
> 0274  001fac7e 6f800490            w: SETGT              T0.w,  T2.w, [0x3e800000 0.25].x
> 0276  8000007c 0fa04090            t: EXP_IEEE           T1.x,  T0.x
> 0278  3e800000 
> 0280  0010e001 0f800110    32      x: MUL_IEEE           T0.x,  R1.x, KC0[7].x
> 0282  0090e401 2f800110            y: MUL_IEEE           T0.y,  R1.y, KC0[7].y
> 0284  010fc07c 4f880110            z: MUL_IEEE           T0.z,  T0.x, T2.z             VEC_120
> 0286  001fac7c 6fa32c7d            w: CNDE               T1.w,  T0.w, [0x40800000 4].x, T1.w
> 0288  8090c402 6f800110            t: MUL_IEEE           T0.w,  R2.y, KC0[6].y
> 0290  40800000 
> 0292  0010a002 0fc00110    33      x: MUL_IEEE           T2.x,  R2.x, KC0[5].x
> 0294  0090a402 2fa00110            y: MUL_IEEE           T1.y,  R2.y, KC0[5].y
> 0296  0110a802 4fa00110            z: MUL_IEEE           T1.z,  R2.z, KC0[5].z
> 0298  010fcc7c 6f840110            w: MUL_IEEE           T0.w,  T0.w, T2.z             VEC_021
> 0300  800fa87d 2fc7047d            t: MULADD_IEEE        T2.y,  T1.z, T1.x, T1.y       SCL_122
> 0302  000fa07c 0f83087c    34      x: MULADD_IEEE        T0.x,  T0.x, T1.x, T0.z
> 0304  000fa47c 2f830c7c            y: MULADD_IEEE        T0.y,  T0.y, T1.x, T0.w
> 0306  018fa803 4f800110            z: MUL_IEEE           T0.z,  R3.z, T1.w
> 0308  018fa403 6f8c0110            w: MUL_IEEE           T0.w,  R3.y, T1.w             VEC_102
> 0310  818fa003 0fa00110            t: MUL_IEEE           T1.x,  R3.x, T1.w
> 0312  000fa07c 0003007e    35      x: MULADD_IEEE        R0.x,  T0.x, T1.x, T2.x
> 0314  018f847c 2003047d            y: MULADD_IEEE        R0.y,  T0.y, T0.w, T1.y
> 0316  010f847e 400b087d            z: MULADD_IEEE        R0.z,  T2.y, T0.z, T1.z       VEC_120
> 0318  80112c02 60000110            w: MUL_IEEE           R0.w,  R2.w, KC0[9].x
>0012  c0000000 95200688 EXPORT_DONE        PIXEL 0     R0.xyzw  EOP
>===== SHADER_END ===============================================================
>
>--------------------------------------------------------------
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL IN[4]
>DCL IN[5]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[9]
>DCL OUT[2], GENERIC[10]
>DCL OUT[3], GENERIC[11]
>DCL OUT[4], GENERIC[12]
>DCL OUT[5], GENERIC[13]
>DCL CONST[0..8]
>DCL TEMP[0..5], LOCAL
>IMM[0] FLT32 {    0.0000,     0.0000,     0.0000,     0.0000}
>  0: MUL TEMP[0], CONST[5], IN[1].xxxx
>  1: MAD TEMP[0], CONST[6], IN[1].yyyy, TEMP[0]
>  2: MAD TEMP[0], CONST[7], IN[1].zzzz, TEMP[0]
>  3: MAD TEMP[0].xy, CONST[8], IN[1].wwww, TEMP[0]
>  4: MOV TEMP[0].xy, TEMP[0].xyxx
>  5: MOV TEMP[0].zw, IN[5].yyxy
>  6: ADD TEMP[1].xyz, CONST[4].xyzz, -IN[0].xyzz
>  7: DP3 TEMP[2].x, TEMP[1].xyzz, IN[2].xyzz
>  8: DP3 TEMP[3].x, TEMP[1].xyzz, IN[3].xyzz
>  9: MOV TEMP[2].y, TEMP[3].xxxx
> 10: DP3 TEMP[1].x, TEMP[1].xyzz, IN[4].xyzz
> 11: MOV TEMP[2].z, TEMP[1].xxxx
> 12: MOV TEMP[2].w, IMM[0].xxxx
> 13: MOV TEMP[1].w, IMM[0].xxxx
> 14: MOV TEMP[1].xyz, IN[2].xyzx
> 15: MOV TEMP[3].w, IMM[0].xxxx
> 16: MOV TEMP[3].xyz, IN[3].xyzx
> 17: MOV TEMP[4].w, IMM[0].xxxx
> 18: MOV TEMP[4].xyz, IN[4].xyzx
> 19: MUL TEMP[5], CONST[0], IN[0].xxxx
> 20: MAD TEMP[5], CONST[1], IN[0].yyyy, TEMP[5]
> 21: MAD TEMP[5], CONST[2], IN[0].zzzz, TEMP[5]
> 22: MAD TEMP[5], CONST[3], IN[0].wwww, TEMP[5]
> 23: MOV OUT[3], TEMP[4]
> 24: MOV OUT[4], TEMP[1]
> 25: MOV OUT[0], TEMP[5]
> 26: MOV OUT[5], TEMP[3]
> 27: MOV OUT[1], TEMP[2]
> 28: MOV OUT[2], TEMP[0]
> 29: END
>; ModuleID = 'tgsi'
>
>define void @main(<4 x float> inreg, <4 x float> inreg, <4 x float> inreg, <4 x float> inreg, <4 x float> inreg, <4 x float> inreg, <4 x float> inreg) #0 {
>main_body:
>  %7 = extractelement <4 x float> %1, i32 0
>  %8 = extractelement <4 x float> %1, i32 1
>  %9 = extractelement <4 x float> %1, i32 2
>  %10 = extractelement <4 x float> %1, i32 3
>  %11 = extractelement <4 x float> %2, i32 0
>  %12 = extractelement <4 x float> %2, i32 1
>  %13 = extractelement <4 x float> %2, i32 2
>  %14 = extractelement <4 x float> %2, i32 3
>  %15 = extractelement <4 x float> %3, i32 0
>  %16 = extractelement <4 x float> %3, i32 1
>  %17 = extractelement <4 x float> %3, i32 2
>  %18 = extractelement <4 x float> %4, i32 0
>  %19 = extractelement <4 x float> %4, i32 1
>  %20 = extractelement <4 x float> %4, i32 2
>  %21 = extractelement <4 x float> %5, i32 0
>  %22 = extractelement <4 x float> %5, i32 1
>  %23 = extractelement <4 x float> %5, i32 2
>  %24 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5)
>  %25 = extractelement <4 x float> %24, i32 0
>  %26 = fmul float %25, %11
>  %27 = extractelement <4 x float> %24, i32 1
>  %28 = fmul float %27, %11
>  %29 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6)
>  %30 = extractelement <4 x float> %29, i32 0
>  %31 = fmul float %30, %12
>  %32 = fadd float %31, %26
>  %33 = extractelement <4 x float> %29, i32 1
>  %34 = fmul float %33, %12
>  %35 = fadd float %34, %28
>  %36 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7)
>  %37 = extractelement <4 x float> %36, i32 0
>  %38 = fmul float %37, %13
>  %39 = fadd float %38, %32
>  %40 = extractelement <4 x float> %36, i32 1
>  %41 = fmul float %40, %13
>  %42 = fadd float %41, %35
>  %43 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8)
>  %44 = extractelement <4 x float> %43, i32 0
>  %45 = fmul float %44, %14
>  %46 = fadd float %45, %39
>  %47 = extractelement <4 x float> %43, i32 1
>  %48 = fmul float %47, %14
>  %49 = fadd float %48, %42
>  %50 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4)
>  %51 = extractelement <4 x float> %50, i32 0
>  %52 = fsub float %51, %7
>  %53 = extractelement <4 x float> %50, i32 1
>  %54 = fsub float %53, %8
>  %55 = extractelement <4 x float> %50, i32 2
>  %56 = fsub float %55, %9
>  %57 = insertelement <4 x float> undef, float %52, i32 0
>  %58 = insertelement <4 x float> %57, float %54, i32 1
>  %59 = insertelement <4 x float> %58, float %56, i32 2
>  %60 = insertelement <4 x float> %59, float 0.000000e+00, i32 3
>  %61 = insertelement <4 x float> undef, float %15, i32 0
>  %62 = insertelement <4 x float> %61, float %16, i32 1
>  %63 = insertelement <4 x float> %62, float %17, i32 2
>  %64 = insertelement <4 x float> %63, float 0.000000e+00, i32 3
>  %65 = call float @llvm.AMDGPU.dp4(<4 x float> %60, <4 x float> %64)
>  %66 = insertelement <4 x float> undef, float %52, i32 0
>  %67 = insertelement <4 x float> %66, float %54, i32 1
>  %68 = insertelement <4 x float> %67, float %56, i32 2
>  %69 = insertelement <4 x float> %68, float 0.000000e+00, i32 3
>  %70 = insertelement <4 x float> undef, float %18, i32 0
>  %71 = insertelement <4 x float> %70, float %19, i32 1
>  %72 = insertelement <4 x float> %71, float %20, i32 2
>  %73 = insertelement <4 x float> %72, float 0.000000e+00, i32 3
>  %74 = call float @llvm.AMDGPU.dp4(<4 x float> %69, <4 x float> %73)
>  %75 = insertelement <4 x float> undef, float %52, i32 0
>  %76 = insertelement <4 x float> %75, float %54, i32 1
>  %77 = insertelement <4 x float> %76, float %56, i32 2
>  %78 = insertelement <4 x float> %77, float 0.000000e+00, i32 3
>  %79 = insertelement <4 x float> undef, float %21, i32 0
>  %80 = insertelement <4 x float> %79, float %22, i32 1
>  %81 = insertelement <4 x float> %80, float %23, i32 2
>  %82 = insertelement <4 x float> %81, float 0.000000e+00, i32 3
>  %83 = call float @llvm.AMDGPU.dp4(<4 x float> %78, <4 x float> %82)
>  %84 = load <4 x float> addrspace(8)* null
>  %85 = extractelement <4 x float> %84, i32 0
>  %86 = fmul float %85, %7
>  %87 = extractelement <4 x float> %84, i32 1
>  %88 = fmul float %87, %7
>  %89 = extractelement <4 x float> %84, i32 2
>  %90 = fmul float %89, %7
>  %91 = load <4 x float> addrspace(8)* null
>  %92 = extractelement <4 x float> %91, i32 3
>  %93 = fmul float %92, %7
>  %94 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
>  %95 = extractelement <4 x float> %94, i32 0
>  %96 = fmul float %95, %8
>  %97 = fadd float %96, %86
>  %98 = extractelement <4 x float> %94, i32 1
>  %99 = fmul float %98, %8
>  %100 = fadd float %99, %88
>  %101 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
>  %102 = extractelement <4 x float> %101, i32 2
>  %103 = fmul float %102, %8
>  %104 = fadd float %103, %90
>  %105 = extractelement <4 x float> %101, i32 3
>  %106 = fmul float %105, %8
>  %107 = fadd float %106, %93
>  %108 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
>  %109 = extractelement <4 x float> %108, i32 0
>  %110 = fmul float %109, %9
>  %111 = fadd float %110, %97
>  %112 = extractelement <4 x float> %108, i32 1
>  %113 = fmul float %112, %9
>  %114 = fadd float %113, %100
>  %115 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
>  %116 = extractelement <4 x float> %115, i32 2
>  %117 = fmul float %116, %9
>  %118 = fadd float %117, %104
>  %119 = extractelement <4 x float> %115, i32 3
>  %120 = fmul float %119, %9
>  %121 = fadd float %120, %107
>  %122 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
>  %123 = extractelement <4 x float> %122, i32 0
>  %124 = fmul float %123, %10
>  %125 = fadd float %124, %111
>  %126 = extractelement <4 x float> %122, i32 1
>  %127 = fmul float %126, %10
>  %128 = fadd float %127, %114
>  %129 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
>  %130 = extractelement <4 x float> %129, i32 2
>  %131 = fmul float %130, %10
>  %132 = fadd float %131, %118
>  %133 = extractelement <4 x float> %129, i32 3
>  %134 = fmul float %133, %10
>  %135 = fadd float %134, %121
>  %136 = insertelement <4 x float> undef, float %125, i32 0
>  %137 = insertelement <4 x float> %136, float %128, i32 1
>  %138 = insertelement <4 x float> %137, float %132, i32 2
>  %139 = insertelement <4 x float> %138, float %135, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %139, i32 60, i32 1)
>  %140 = insertelement <4 x float> undef, float %65, i32 0
>  %141 = insertelement <4 x float> %140, float %74, i32 1
>  %142 = insertelement <4 x float> %141, float %83, i32 2
>  %143 = insertelement <4 x float> %142, float 0.000000e+00, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %143, i32 0, i32 2)
>  %144 = insertelement <4 x float> undef, float %46, i32 0
>  %145 = insertelement <4 x float> %144, float %49, i32 1
>  %146 = shufflevector <4 x float> %145, <4 x float> %6, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
>  call void @llvm.R600.store.swizzle(<4 x float> %146, i32 1, i32 2)
>  %147 = insertelement <4 x float> undef, float %21, i32 0
>  %148 = insertelement <4 x float> %147, float %22, i32 1
>  %149 = insertelement <4 x float> %148, float %23, i32 2
>  %150 = insertelement <4 x float> %149, float 0.000000e+00, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %150, i32 2, i32 2)
>  %151 = insertelement <4 x float> undef, float %15, i32 0
>  %152 = insertelement <4 x float> %151, float %16, i32 1
>  %153 = insertelement <4 x float> %152, float %17, i32 2
>  %154 = insertelement <4 x float> %153, float 0.000000e+00, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %154, i32 3, i32 2)
>  %155 = insertelement <4 x float> undef, float %18, i32 0
>  %156 = insertelement <4 x float> %155, float %19, i32 1
>  %157 = insertelement <4 x float> %156, float %20, i32 2
>  %158 = insertelement <4 x float> %157, float 0.000000e+00, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %158, i32 4, i32 2)
>  ret void
>}
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1
>
>declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
>
>attributes #0 = { "ShaderType"="1" }
>attributes #1 = { readnone }
>
>===== SHADER #40 ==================================== VS/REDWOOD/EVERGREEN =====
>===== 98 dw ===== 10 gprs ===== 1 stack ========================================
>0000  00000000 84c00000 CALL_FS @0
>0002  8000000a a0980000 ALU 39 @20 KC0[CB0:0-31]
> 0020  80002080 60000110     1      w: MUL_IEEE           R0.w,  KC0[0].x, R1.x
> 0022  80802081 60030cfe     2      w: MULADD_IEEE        R0.w,  KC0[1].x, R1.y, PV.w
> 0024  81002082 60030cfe     3      w: MULADD_IEEE        R0.w,  KC0[2].x, R1.z, PV.w
> 0026  01802083 00030cfe     4      x: MULADD_IEEE        R0.x,  KC0[3].x, R1.w, PV.w
> 0028  80002480 60e00110            w: MUL_IEEE           R7.w,  KC0[0].y, R1.x
> 0030  02002084 00e00010     5      x: ADD                R7.x,  KC0[4].x, -R1.x
> 0032  02802484 20e00010            y: ADD                R7.y,  KC0[4].y, -R1.y
> 0034  80802481 60e30cfe            w: MULADD_IEEE        R7.w,  KC0[1].y, R1.y, PV.w
> 0036  80002880 61000110     6      w: MUL_IEEE           R8.w,  KC0[0].z, R1.x
> 0038  00802881 40e30cfe     7      z: MULADD_IEEE        R7.z,  KC0[1].z, R1.y, PV.w
> 0040  80004085 61000110            w: MUL_IEEE           R8.w,  KC0[5].x, R2.x
> 0042  81002482 60e30c07     8      w: MULADD_IEEE        R7.w,  KC0[2].y, R1.z, R7.w
> 0044  01802483 20030cfe     9      y: MULADD_IEEE        R0.y,  KC0[3].y, R1.w, PV.w
> 0046  80804086 60e30c08            w: MULADD_IEEE        R7.w,  KC0[6].x, R2.y, R8.w
> 0048  81002882 61030807    10      w: MULADD_IEEE        R8.w,  KC0[2].z, R1.z, R7.z
> 0050  01802883 40030cfe    11      z: MULADD_IEEE        R0.z,  KC0[3].z, R1.w, PV.w
> 0052  80002c80 61000110            w: MUL_IEEE           R8.w,  KC0[0].w, R1.x
> 0054  81004087 60e30c07    12      w: MULADD_IEEE        R7.w,  KC0[7].x, R2.z, R7.w
> 0056  01804088 40c30cfe    13      z: MULADD_IEEE        R6.z,  KC0[8].x, R2.w, PV.w
> 0058  80004485 60e00110            w: MUL_IEEE           R7.w,  KC0[5].y, R2.x
> 0060  80802c81 61030c08    14      w: MULADD_IEEE        R8.w,  KC0[1].w, R1.y, R8.w
> 0062  03002884 40e00010    15      z: ADD                R7.z,  KC0[4].z, -R1.z
> 0064  81002c82 61030cfe            w: MULADD_IEEE        R8.w,  KC0[2].w, R1.z, PV.w
> 0066  80804486 60e30c07    16      w: MULADD_IEEE        R7.w,  KC0[6].y, R2.y, R7.w
> 0068  81004487 60e30cfe    17      w: MULADD_IEEE        R7.w,  KC0[7].y, R2.z, PV.w
> 0070  00006007 01205f10    18      x: DOT4               R9.x,  R7.x, R3.x
> 0072  00806407 21205f00            y: DOT4               __.y,  R7.y, R3.y
> 0074  01006807 41205f00            z: DOT4               __.z,  R7.z, R3.z
> 0076  801f00f8 61205f00            w: DOT4               __.w,  0, 0
> 0078  81804488 60c30c07    19      w: MULADD_IEEE        R6.w,  KC0[8].y, R2.w, R7.w
> 0080  00008007 01205f00    20      x: DOT4               __.x,  R7.x, R4.x
> 0082  00808407 21205f10            y: DOT4               R9.y,  R7.y, R4.y
> 0084  01008807 41205f00            z: DOT4               __.z,  R7.z, R4.z
> 0086  801f00f8 61205f00            w: DOT4               __.w,  0, 0
> 0088  81802c83 60030c08    21      w: MULADD_IEEE        R0.w,  KC0[3].w, R1.w, R8.w
> 0090  0000a007 01205f00    22      x: DOT4               __.x,  R7.x, R5.x
> 0092  0080a407 21205f00            y: DOT4               __.y,  R7.y, R5.y
> 0094  0100a807 41205f10            z: DOT4               R9.z,  R7.z, R5.z
> 0096  801f00f8 61205f00            w: DOT4               __.w,  0, 0
>0004  c000203c 95000688 EXPORT_DONE        POS   60    R0.xyzw
>0006  c004c000 94c00888 EXPORT             PARAM 0     R9.xyz0
>0008  c0034001 94c0021a EXPORT             PARAM 1     R6.zwxy
>0010  c002c002 94c00888 EXPORT             PARAM 2     R5.xyz0
>0012  c001c003 94c00888 EXPORT             PARAM 3     R3.xyz0
>0014  c0024004 95200888 EXPORT_DONE        PARAM 4     R4.xyz0  EOP
>===== SHADER_END ===============================================================
>
>
>===== SHADER #40 OPT ================================ VS/REDWOOD/EVERGREEN =====
>===== 94 dw ===== 7 gprs ===== 1 stack =========================================
>0000  00000000 84c00000 CALL_FS @0
>0002  40000008 a0980000 ALU 39 @16 KC0[CB0:0-15]
> 0016  00002480 4f800110     1      z: MUL_IEEE           T0.z,  KC0[0].y, R1.x
> 0018  80002080 6fa00110            w: MUL_IEEE           T1.w,  KC0[0].x, R1.x
> 0020  00004085 0fa00110     2      x: MUL_IEEE           T1.x,  KC0[5].x, R2.x
> 0022  00002880 2fa40110            y: MUL_IEEE           T1.y,  KC0[0].z, R1.x         VEC_021
> 0024  00004485 6f800110            w: MUL_IEEE           T0.w,  KC0[5].y, R2.x
> 0026  80002c80 0f840110            t: MUL_IEEE           T0.x,  KC0[0].w, R1.x         SCL_122
> 0028  00802481 4fa3087c     3      z: MULADD_IEEE        T1.z,  KC0[1].y, R1.y, T0.z
> 0030  00802c81 6fc3007c            w: MULADD_IEEE        T2.w,  KC0[1].w, R1.y, T0.x
> 0032  80802081 6fe70c7d            t: MULADD_IEEE        T3.w,  KC0[1].x, R1.y, T1.w   SCL_122
> 0034  02002084 0f800010     4      x: ADD                T0.x,  KC0[4].x, -R1.x
> 0036  02802484 2f800010            y: ADD                T0.y,  KC0[4].y, -R1.y
> 0038  83002884 4f800010            z: ADD                T0.z,  KC0[4].z, -R1.z
> 0040  00804086 0faf007d     5      x: MULADD_IEEE        T1.x,  KC0[6].x, R2.y, T1.x   VEC_102
> 0042  00804486 6f8f0c7c            w: MULADD_IEEE        T0.w,  KC0[6].y, R2.y, T0.w   VEC_102
> 0044  80802881 6fab047d            t: MULADD_IEEE        T1.w,  KC0[1].z, R1.y, T1.y   SCL_212
> 0046  01002c82 2fa30c7e     6      y: MULADD_IEEE        T1.y,  KC0[2].w, R1.z, T2.w
> 0048  01002082 4fb30c7f            z: MULADD_IEEE        T1.z,  KC0[2].x, R1.z, T3.w   VEC_201
> 0050  81002482 6fc3087d            w: MULADD_IEEE        T2.w,  KC0[2].y, R1.z, T1.z
> 0052  0000a07c 00005f00     7      x: DOT4               __.x,  T0.x, R5.x
> 0054  0080a47c 20005f00            y: DOT4               __.y,  T0.y, R5.y
> 0056  0100a87c 40205f10            z: DOT4               R1.z,  T0.z, R5.z
> 0058  001f00f8 60005f00            w: DOT4               __.w,  0, 0
> 0060  81002882 6fa70c7d            t: MULADD_IEEE        T1.w,  KC0[2].z, R1.z, T1.w   SCL_122
> 0062  0000807c 00005f00     8      x: DOT4               __.x,  T0.x, R4.x
> 0064  0080847c 20205f10            y: DOT4               R1.y,  T0.y, R4.y
> 0066  0100887c 40005f00            z: DOT4               __.z,  T0.z, R4.z
> 0068  001f00f8 60005f00            w: DOT4               __.w,  0, 0
> 0070  81004487 6f870c7c            t: MULADD_IEEE        T0.w,  KC0[7].y, R2.z, T0.w   SCL_122
> 0072  0000607c 00205f10     9      x: DOT4               R1.x,  T0.x, R3.x
> 0074  0080647c 20005f00            y: DOT4               __.y,  T0.y, R3.y
> 0076  0100687c 40005f00            z: DOT4               __.z,  T0.z, R3.z
> 0078  001f00f8 60005f00            w: DOT4               __.w,  0, 0
> 0080  81004087 0f87007d            t: MULADD_IEEE        T0.x,  KC0[7].x, R2.z, T1.x   SCL_122
> 0082  01802483 20030c7e    10      y: MULADD_IEEE        R0.y,  KC0[3].y, R1.w, T2.w
> 0084  01802883 40170c7d            z: MULADD_IEEE        R0.z,  KC0[3].z, R1.w, T1.w   VEC_210
> 0086  81802c83 6003047d            w: MULADD_IEEE        R0.w,  KC0[3].w, R1.w, T1.y
> 0088  01802083 000f087d    11      x: MULADD_IEEE        R0.x,  KC0[3].x, R1.w, T1.z   VEC_102
> 0090  01804088 40c3007c            z: MULADD_IEEE        R6.z,  KC0[8].x, R2.w, T0.x
> 0092  81804488 60c30c7c            w: MULADD_IEEE        R6.w,  KC0[8].y, R2.w, T0.w
>0004  c0034001 94c0021a EXPORT             PARAM 1     R6.zwxy
>0006  c000203c 95000688 EXPORT_DONE        POS   60    R0.xyzw
>0008  c000c000 94c00888 EXPORT             PARAM 0     R1.xyz0
>0010  c002c002 94c00888 EXPORT             PARAM 2     R5.xyz0
>0012  c0024004 94c00888 EXPORT             PARAM 4     R4.xyz0
>0014  c001c003 95200888 EXPORT_DONE        PARAM 3     R3.xyz0  EOP
>===== SHADER_END ===============================================================
>
>--------------------------------------------------------------
>FRAG
>DCL IN[0], GENERIC[9], PERSPECTIVE
>DCL IN[1], GENERIC[10], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SVIEW[0], 2D, FLOAT
>DCL CONST[1..3]
>DCL TEMP[0..2], LOCAL
>  0: MOV TEMP[0].xy, IN[0].xyyy
>  1: TEX TEMP[0], TEMP[0], SAMP[0], 2D
>  2: MUL TEMP[1].x, TEMP[0].wwww, CONST[3].xxxx
>  3: MOV TEMP[1].w, TEMP[1].xxxx
>  4: MAD TEMP[2].xyz, IN[1].xyzz, CONST[2].xyzz, CONST[1].xyzz
>  5: MUL TEMP[1].xyz, TEMP[0].xyzz, TEMP[2].xyzz
>  6: MOV OUT[0], TEMP[1]
>  7: END
>; ModuleID = 'tgsi'
>
>define void @main(<4 x float> inreg, <4 x float> inreg, <4 x float> inreg) #0 {
>main_body:
>  %3 = extractelement <4 x float> %0, i32 0
>  %4 = extractelement <4 x float> %0, i32 1
>  %5 = call <2 x float> @llvm.R600.interp.xy(i32 0, float %3, float %4)
>  %6 = call <2 x float> @llvm.R600.interp.zw(i32 0, float %3, float %4)
>  %7 = extractelement <4 x float> %0, i32 0
>  %8 = extractelement <4 x float> %0, i32 1
>  %9 = call <2 x float> @llvm.R600.interp.xy(i32 1, float %7, float %8)
>  %10 = call <2 x float> @llvm.R600.interp.zw(i32 1, float %7, float %8)
>  %11 = extractelement <2 x float> %9, i32 0
>  %12 = extractelement <2 x float> %9, i32 1
>  %13 = extractelement <2 x float> %10, i32 0
>  %14 = shufflevector <2 x float> %5, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
>  %15 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %14, i32 16, i32 0, i32 2)
>  %16 = extractelement <4 x float> %15, i32 0
>  %17 = extractelement <4 x float> %15, i32 1
>  %18 = extractelement <4 x float> %15, i32 2
>  %19 = extractelement <4 x float> %15, i32 3
>  %20 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
>  %21 = extractelement <4 x float> %20, i32 0
>  %22 = fmul float %19, %21
>  %23 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
>  %24 = extractelement <4 x float> %23, i32 0
>  %25 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
>  %26 = extractelement <4 x float> %25, i32 0
>  %27 = fmul float %11, %24
>  %28 = fadd float %27, %26
>  %29 = extractelement <4 x float> %23, i32 1
>  %30 = extractelement <4 x float> %25, i32 1
>  %31 = fmul float %12, %29
>  %32 = fadd float %31, %30
>  %33 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
>  %34 = extractelement <4 x float> %33, i32 2
>  %35 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
>  %36 = extractelement <4 x float> %35, i32 2
>  %37 = fmul float %13, %34
>  %38 = fadd float %37, %36
>  %39 = fmul float %16, %28
>  %40 = fmul float %17, %32
>  %41 = fmul float %18, %38
>  %42 = insertelement <4 x float> undef, float %39, i32 0
>  %43 = insertelement <4 x float> %42, float %40, i32 1
>  %44 = insertelement <4 x float> %43, float %41, i32 2
>  %45 = insertelement <4 x float> %44, float %22, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %45, i32 0, i32 0)
>  ret void
>}
>
>; Function Attrs: readnone
>declare <2 x float> @llvm.R600.interp.xy(i32, float, float) #1
>
>; Function Attrs: readnone
>declare <2 x float> @llvm.R600.interp.zw(i32, float, float) #1
>
>; Function Attrs: readnone
>declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32, i32) #1
>
>declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { readnone }
>
>===== SHADER #41 ==================================== PS/REDWOOD/EVERGREEN =====
>===== 54 dw ===== 4 gprs ===== 0 stack =========================================
>0000  00000008 a00c0000 ALU 4 @16
> 0016  00380400 00346b10     1      x: INTERP_XY          R1.x,  R0.y, Param0.x         VEC_210
> 0018  00380000 20346b10            y: INTERP_XY          R1.y,  R0.x, Param0.x         VEC_210
> 0020  00380400 40146b00            z: INTERP_XY          __.z,  R0.y, Param0.x         VEC_210
> 0022  80380000 60146b00            w: INTERP_XY          __.w,  R0.x, Param0.x         VEC_210
>0002  00000006 80400000 TEX 1 @12
> 0012  00011010 f00d1001 fc800000 SAMPLE              R1.xyzw, R1.xy__,   RID:16, SID:0 CT:NNNN
>0004  8000000c a0380000 ALU 15 @24 KC0[CB0:0-31]
> 0024  00382400 00546b10     2      x: INTERP_XY          R2.x,  R0.y, Param1.x         VEC_210
> 0026  00382000 20546b10            y: INTERP_XY          R2.y,  R0.x, Param1.x         VEC_210
> 0028  00382400 40146b00            z: INTERP_XY          __.z,  R0.y, Param1.x         VEC_210
> 0030  80382000 60146b00            w: INTERP_XY          __.w,  R0.x, Param1.x         VEC_210
> 0032  801040fe 60430081     3      w: MULADD_IEEE        R2.w,  PV.x, KC0[2].x, KC0[1].x
> 0034  80106c01 60600110     4      w: MUL_IEEE           R3.w,  R1.w, KC0[3].x
> 0036  01804001 00600110     5      x: MUL_IEEE           R3.x,  R1.x, R2.w
> 0038  80904402 60430481            w: MULADD_IEEE        R2.w,  R2.y, KC0[2].y, KC0[1].y
> 0040  00382400 00146b80     6      x: INTERP_ZW          __.x,  R0.y, Param1.x         VEC_210
> 0042  00382000 20146b80            y: INTERP_ZW          __.y,  R0.x, Param1.x         VEC_210
> 0044  00382400 40146b90            z: INTERP_ZW          R0.z,  R0.y, Param1.x         VEC_210
> 0046  80382000 60146b90            w: INTERP_ZW          R0.w,  R0.x, Param1.x         VEC_210
> 0048  01804401 20600110     7      y: MUL_IEEE           R3.y,  R1.y, R2.w
> 0050  811048fe 60030881            w: MULADD_IEEE        R0.w,  PV.z, KC0[2].z, KC0[1].z
> 0052  819fc801 40600110     8      z: MUL_IEEE           R3.z,  R1.z, PV.w
>0006  c0018000 95200688 EXPORT_DONE        PIXEL 0     R3.xyzw  EOP
>===== SHADER_END ===============================================================
>
>
>===== SHADER #41 OPT ================================ PS/REDWOOD/EVERGREEN =====
>===== 50 dw ===== 2 gprs ===== 0 stack =========================================
>0000  00000004 a00c0000 ALU 4 @8
> 0008  00380400 00346b10     1      x: INTERP_XY          R1.x,  R0.y, Param0.x         VEC_210
> 0010  00b80000 20346b10            y: INTERP_XY          R1.y,  R0.x, Param0.y         VEC_210
> 0012  01380400 40146b00            z: INTERP_XY          __.z,  R0.y, Param0.z         VEC_210
> 0014  81b80000 60146b00            w: INTERP_XY          __.w,  R0.x, Param0.w         VEC_210
>0002  00000008 80400000 TEX 1 @16
> 0016  00011010 f00d1001 fc800000 SAMPLE              R1.xyzw, R1.xy__,   RID:16, SID:0 CT:NNNN
>0004  4000000a a0380000 ALU 15 @20 KC0[CB0:0-15]
> 0020  00382400 00146b80     2      x: INTERP_ZW          __.x,  R0.y, Param1.x         VEC_210
> 0022  00b82000 20146b80            y: INTERP_ZW          __.y,  R0.x, Param1.y         VEC_210
> 0024  01382400 4f946b90            z: INTERP_ZW          T0.z,  R0.y, Param1.z         VEC_210
> 0026  81b82000 60146b80            w: INTERP_ZW          __.w,  R0.x, Param1.w         VEC_210
> 0028  00382400 0f946b10     3      x: INTERP_XY          T0.x,  R0.y, Param1.x         VEC_210
> 0030  00b82000 2f946b10            y: INTERP_XY          T0.y,  R0.x, Param1.y         VEC_210
> 0032  01382400 40146b00            z: INTERP_XY          __.z,  R0.y, Param1.z         VEC_210
> 0034  81b82000 60146b00            w: INTERP_XY          __.w,  R0.x, Param1.w         VEC_210
> 0036  8110487c 4f830881     4      z: MULADD_IEEE        T0.z,  T0.z, KC0[2].z, KC0[1].z
> 0038  0010407c 0f830081     5      x: MULADD_IEEE        T0.x,  T0.x, KC0[2].x, KC0[1].x
> 0040  8090447c 2f830481            y: MULADD_IEEE        T0.y,  T0.y, KC0[2].y, KC0[1].y
> 0042  000f8001 00000110     6      x: MUL_IEEE           R0.x,  R1.x, T0.x
> 0044  008f8401 20000110            y: MUL_IEEE           R0.y,  R1.y, T0.y
> 0046  010f8801 40000110            z: MUL_IEEE           R0.z,  R1.z, T0.z
> 0048  80106c01 60000110            w: MUL_IEEE           R0.w,  R1.w, KC0[3].x
>0006  c0000000 95200688 EXPORT_DONE        PIXEL 0     R0.xyzw  EOP
>===== SHADER_END ===============================================================
>
>--------------------------------------------------------------
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[9]
>DCL OUT[2], GENERIC[10]
>DCL CONST[0..7]
>DCL TEMP[0..1], LOCAL
>IMM[0] FLT32 {    0.0000,     0.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].zw, IMM[0].xxxx
>  1: MUL TEMP[1], CONST[4], IN[2].xxxx
>  2: MAD TEMP[1], CONST[5], IN[2].yyyy, TEMP[1]
>  3: MAD TEMP[1], CONST[6], IN[2].zzzz, TEMP[1]
>  4: MAD TEMP[1].xy, CONST[7], IN[2].wwww, TEMP[1]
>  5: MOV TEMP[0].xy, TEMP[1].xyxx
>  6: MUL TEMP[1], CONST[0], IN[0].xxxx
>  7: MAD TEMP[1], CONST[1], IN[0].yyyy, TEMP[1]
>  8: MAD TEMP[1], CONST[2], IN[0].zzzz, TEMP[1]
>  9: MAD TEMP[1], CONST[3], IN[0].wwww, TEMP[1]
> 10: MOV OUT[2], IN[1]
> 11: MOV OUT[0], TEMP[1]
> 12: MOV OUT[1], TEMP[0]
> 13: END
>; ModuleID = 'tgsi'
>
>define void @main(<4 x float> inreg, <4 x float> inreg, <4 x float> inreg, <4 x float> inreg) #0 {
>main_body:
>  %4 = extractelement <4 x float> %1, i32 0
>  %5 = extractelement <4 x float> %1, i32 1
>  %6 = extractelement <4 x float> %1, i32 2
>  %7 = extractelement <4 x float> %1, i32 3
>  %8 = extractelement <4 x float> %3, i32 0
>  %9 = extractelement <4 x float> %3, i32 1
>  %10 = extractelement <4 x float> %3, i32 2
>  %11 = extractelement <4 x float> %3, i32 3
>  %12 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4)
>  %13 = extractelement <4 x float> %12, i32 0
>  %14 = fmul float %13, %8
>  %15 = extractelement <4 x float> %12, i32 1
>  %16 = fmul float %15, %8
>  %17 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5)
>  %18 = extractelement <4 x float> %17, i32 0
>  %19 = fmul float %18, %9
>  %20 = fadd float %19, %14
>  %21 = extractelement <4 x float> %17, i32 1
>  %22 = fmul float %21, %9
>  %23 = fadd float %22, %16
>  %24 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6)
>  %25 = extractelement <4 x float> %24, i32 0
>  %26 = fmul float %25, %10
>  %27 = fadd float %26, %20
>  %28 = extractelement <4 x float> %24, i32 1
>  %29 = fmul float %28, %10
>  %30 = fadd float %29, %23
>  %31 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7)
>  %32 = extractelement <4 x float> %31, i32 0
>  %33 = fmul float %32, %11
>  %34 = fadd float %33, %27
>  %35 = extractelement <4 x float> %31, i32 1
>  %36 = fmul float %35, %11
>  %37 = fadd float %36, %30
>  %38 = load <4 x float> addrspace(8)* null
>  %39 = extractelement <4 x float> %38, i32 0
>  %40 = fmul float %39, %4
>  %41 = extractelement <4 x float> %38, i32 1
>  %42 = fmul float %41, %4
>  %43 = extractelement <4 x float> %38, i32 2
>  %44 = fmul float %43, %4
>  %45 = load <4 x float> addrspace(8)* null
>  %46 = extractelement <4 x float> %45, i32 3
>  %47 = fmul float %46, %4
>  %48 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
>  %49 = extractelement <4 x float> %48, i32 0
>  %50 = fmul float %49, %5
>  %51 = fadd float %50, %40
>  %52 = extractelement <4 x float> %48, i32 1
>  %53 = fmul float %52, %5
>  %54 = fadd float %53, %42
>  %55 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
>  %56 = extractelement <4 x float> %55, i32 2
>  %57 = fmul float %56, %5
>  %58 = fadd float %57, %44
>  %59 = extractelement <4 x float> %55, i32 3
>  %60 = fmul float %59, %5
>  %61 = fadd float %60, %47
>  %62 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
>  %63 = extractelement <4 x float> %62, i32 0
>  %64 = fmul float %63, %6
>  %65 = fadd float %64, %51
>  %66 = extractelement <4 x float> %62, i32 1
>  %67 = fmul float %66, %6
>  %68 = fadd float %67, %54
>  %69 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
>  %70 = extractelement <4 x float> %69, i32 2
>  %71 = fmul float %70, %6
>  %72 = fadd float %71, %58
>  %73 = extractelement <4 x float> %69, i32 3
>  %74 = fmul float %73, %6
>  %75 = fadd float %74, %61
>  %76 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
>  %77 = extractelement <4 x float> %76, i32 0
>  %78 = fmul float %77, %7
>  %79 = fadd float %78, %65
>  %80 = extractelement <4 x float> %76, i32 1
>  %81 = fmul float %80, %7
>  %82 = fadd float %81, %68
>  %83 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
>  %84 = extractelement <4 x float> %83, i32 2
>  %85 = fmul float %84, %7
>  %86 = fadd float %85, %72
>  %87 = extractelement <4 x float> %83, i32 3
>  %88 = fmul float %87, %7
>  %89 = fadd float %88, %75
>  %90 = insertelement <4 x float> undef, float %79, i32 0
>  %91 = insertelement <4 x float> %90, float %82, i32 1
>  %92 = insertelement <4 x float> %91, float %86, i32 2
>  %93 = insertelement <4 x float> %92, float %89, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %93, i32 60, i32 1)
>  %94 = insertelement <4 x float> undef, float %34, i32 0
>  %95 = insertelement <4 x float> %94, float %37, i32 1
>  %96 = insertelement <4 x float> %95, float 0.000000e+00, i32 2
>  %97 = insertelement <4 x float> %96, float 0.000000e+00, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %97, i32 0, i32 2)
>  call void @llvm.R600.store.swizzle(<4 x float> %2, i32 1, i32 2)
>  ret void
>}
>
>declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
>
>attributes #0 = { "ShaderType"="1" }
>
>===== SHADER #42 ==================================== VS/REDWOOD/EVERGREEN =====
>===== 60 dw ===== 7 gprs ===== 1 stack =========================================
>0000  00000000 84c00000 CALL_FS @0
>0002  80000006 a05c0000 ALU 24 @12 KC0[CB0:0-31]
> 0012  80002080 60000110     1      w: MUL_IEEE           R0.w,  KC0[0].x, R1.x
> 0014  00802081 40030cfe     2      z: MULADD_IEEE        R0.z,  KC0[1].x, R1.y, PV.w
> 0016  80002480 60000110            w: MUL_IEEE           R0.w,  KC0[0].y, R1.x
> 0018  80006084 60800110     3      w: MUL_IEEE           R4.w,  KC0[4].x, R3.x
> 0020  00806085 40830cfe     4      z: MULADD_IEEE        R4.z,  KC0[5].x, R3.y, PV.w
> 0022  80802481 60070c00            w: MULADD_IEEE        R0.w,  KC0[1].y, R1.y, R0.w   VEC_021
> 0024  81002082 60830800     5      w: MULADD_IEEE        R4.w,  KC0[2].x, R1.z, R0.z
> 0026  01802083 00a30cfe     6      x: MULADD_IEEE        R5.x,  KC0[3].x, R1.w, PV.w
> 0028  81002482 60030c00            w: MULADD_IEEE        R0.w,  KC0[2].y, R1.z, R0.w
> 0030  81006086 60830804     7      w: MULADD_IEEE        R4.w,  KC0[6].x, R3.z, R4.z
> 0032  01806087 00830cfe     8      x: MULADD_IEEE        R4.x,  KC0[7].x, R3.w, PV.w
> 0034  81802483 20ab0c00            y: MULADD_IEEE        R5.y,  KC0[3].y, R1.w, R0.w   VEC_120
> 0036  80002880 60000110     9      w: MUL_IEEE           R0.w,  KC0[0].z, R1.x
> 0038  00802881 40030cfe    10      z: MULADD_IEEE        R0.z,  KC0[1].z, R1.y, PV.w
> 0040  80002c80 60000110            w: MUL_IEEE           R0.w,  KC0[0].w, R1.x
> 0042  80006484 60c00110    11      w: MUL_IEEE           R6.w,  KC0[4].y, R3.x
> 0044  00806485 40c30cfe    12      z: MULADD_IEEE        R6.z,  KC0[5].y, R3.y, PV.w
> 0046  80802c81 60070c00            w: MULADD_IEEE        R0.w,  KC0[1].w, R1.y, R0.w   VEC_021
> 0048  81002882 60c30800    13      w: MULADD_IEEE        R6.w,  KC0[2].z, R1.z, R0.z
> 0050  01802883 40a30cfe    14      z: MULADD_IEEE        R5.z,  KC0[3].z, R1.w, PV.w
> 0052  81002c82 60030c00            w: MULADD_IEEE        R0.w,  KC0[2].w, R1.z, R0.w
> 0054  81006486 60c30806    15      w: MULADD_IEEE        R6.w,  KC0[6].y, R3.z, R6.z
> 0056  01806487 20830cfe    16      y: MULADD_IEEE        R4.y,  KC0[7].y, R3.w, PV.w
> 0058  81802c83 60ab0c00            w: MULADD_IEEE        R5.w,  KC0[3].w, R1.w, R0.w   VEC_120
>0004  c002a03c 95000688 EXPORT_DONE        POS   60    R5.xyzw
>0006  c0024000 94c00908 EXPORT             PARAM 0     R4.xy00
>0008  c0014001 95200688 EXPORT_DONE        PARAM 1     R2.xyzw  EOP
>===== SHADER_END ===============================================================
>
>
>===== SHADER #42 OPT ================================ VS/REDWOOD/EVERGREEN =====
>===== 58 dw ===== 4 gprs ===== 1 stack =========================================
>0000  00000000 84c00000 CALL_FS @0
>0002  40000005 a05c0000 ALU 24 @10 KC0[CB0:0-15]
> 0010  00002c80 0f800110     1      x: MUL_IEEE           T0.x,  KC0[0].w, R1.x
> 0012  80002880 2f800110            y: MUL_IEEE           T0.y,  KC0[0].z, R1.x
> 0014  00006084 0fc00110     2      x: MUL_IEEE           T2.x,  KC0[4].x, R3.x
> 0016  00002480 4f840110            z: MUL_IEEE           T0.z,  KC0[0].y, R1.x         VEC_021
> 0018  80002080 6f840110            w: MUL_IEEE           T0.w,  KC0[0].x, R1.x         VEC_021
> 0020  00802c81 0f83007c     3      x: MULADD_IEEE        T0.x,  KC0[1].w, R1.y, T0.x
> 0022  00802881 2fa3047c            y: MULADD_IEEE        T1.y,  KC0[1].z, R1.y, T0.y
> 0024  80006484 0fa00110            t: MUL_IEEE           T1.x,  KC0[4].y, R3.x
> 0026  00806085 2f83007e     4      y: MULADD_IEEE        T0.y,  KC0[5].x, R3.y, T2.x
> 0028  00802481 4f87087c            z: MULADD_IEEE        T0.z,  KC0[1].y, R1.y, T0.z   VEC_021
> 0030  80802081 6f870c7c            w: MULADD_IEEE        T0.w,  KC0[1].x, R1.y, T0.w   VEC_021
> 0032  01002c82 0fc3007c     5      x: MULADD_IEEE        T2.x,  KC0[2].w, R1.z, T0.x
> 0034  01002882 2fa7047d            y: MULADD_IEEE        T1.y,  KC0[2].z, R1.z, T1.y   VEC_021
> 0036  80806485 0f8f007d            t: MULADD_IEEE        T0.x,  KC0[5].y, R3.y, T1.x   SCL_221
> 0038  01006486 0f8f007c     6      x: MULADD_IEEE        T0.x,  KC0[6].y, R3.z, T0.x   VEC_102
> 0040  01006086 2f8f047c            y: MULADD_IEEE        T0.y,  KC0[6].x, R3.z, T0.y   VEC_102
> 0042  01002082 4f830c7c            z: MULADD_IEEE        T0.z,  KC0[2].x, R1.z, T0.w
> 0044  81002482 0fab087c            t: MULADD_IEEE        T1.x,  KC0[2].y, R1.z, T0.z   SCL_212
> 0046  01802483 2003007d     7      y: MULADD_IEEE        R0.y,  KC0[3].y, R1.w, T1.x
> 0048  01802883 4003047d            z: MULADD_IEEE        R0.z,  KC0[3].z, R1.w, T1.y
> 0050  81802c83 6007007e            w: MULADD_IEEE        R0.w,  KC0[3].w, R1.w, T2.x   VEC_021
> 0052  01806087 0023047c     8      x: MULADD_IEEE        R1.x,  KC0[7].x, R3.w, T0.y
> 0054  01806487 2023007c            y: MULADD_IEEE        R1.y,  KC0[7].y, R3.w, T0.x
> 0056  81802083 0007087c            t: MULADD_IEEE        R0.x,  KC0[3].x, R1.w, T0.z   SCL_122
>0004  c000c000 94c00908 EXPORT             PARAM 0     R1.xy00
>0006  c000203c 95000688 EXPORT_DONE        POS   60    R0.xyzw
>0008  c0014001 95200688 EXPORT_DONE        PARAM 1     R2.xyzw  EOP
>===== SHADER_END ===============================================================
>
>--------------------------------------------------------------
>FRAG
>DCL IN[0], GENERIC[9], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SAMP[1]
>DCL SVIEW[0], 2D, FLOAT
>DCL SVIEW[1], 2D, FLOAT
>DCL CONST[2..4]
>DCL TEMP[0..1], LOCAL
>  0: MOV TEMP[0].xy, IN[0].xyyy
>  1: TEX TEMP[0], TEMP[0], SAMP[0], 2D
>  2: MUL TEMP[1].x, TEMP[0].wwww, CONST[4].xxxx
>  3: MOV TEMP[1].w, TEMP[1].xxxx
>  4: MUL TEMP[1].xyz, TEMP[0].xyzz, CONST[2].xyzz
>  5: MOV TEMP[0].xy, IN[0].xyyy
>  6: TEX TEMP[0].xyz, TEMP[0], SAMP[1], 2D
>  7: MAD TEMP[1].xyz, TEMP[0].xyzz, CONST[3].xyzz, TEMP[1].xyzz
>  8: MOV OUT[0], TEMP[1]
>  9: END
>; ModuleID = 'tgsi'
>
>define void @main(<4 x float> inreg, <4 x float> inreg) #0 {
>main_body:
>  %2 = extractelement <4 x float> %0, i32 0
>  %3 = extractelement <4 x float> %0, i32 1
>  %4 = call <2 x float> @llvm.R600.interp.xy(i32 0, float %2, float %3)
>  %5 = call <2 x float> @llvm.R600.interp.zw(i32 0, float %2, float %3)
>  %6 = shufflevector <2 x float> %4, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
>  %7 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %6, i32 16, i32 0, i32 2)
>  %8 = extractelement <4 x float> %7, i32 0
>  %9 = extractelement <4 x float> %7, i32 1
>  %10 = extractelement <4 x float> %7, i32 2
>  %11 = extractelement <4 x float> %7, i32 3
>  %12 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4)
>  %13 = extractelement <4 x float> %12, i32 0
>  %14 = fmul float %11, %13
>  %15 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
>  %16 = extractelement <4 x float> %15, i32 0
>  %17 = fmul float %8, %16
>  %18 = extractelement <4 x float> %15, i32 1
>  %19 = fmul float %9, %18
>  %20 = extractelement <4 x float> %15, i32 2
>  %21 = fmul float %10, %20
>  %22 = shufflevector <2 x float> %4, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
>  %23 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %22, i32 17, i32 1, i32 2)
>  %24 = extractelement <4 x float> %23, i32 0
>  %25 = extractelement <4 x float> %23, i32 1
>  %26 = extractelement <4 x float> %23, i32 2
>  %27 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
>  %28 = extractelement <4 x float> %27, i32 0
>  %29 = fmul float %24, %28
>  %30 = fadd float %29, %17
>  %31 = extractelement <4 x float> %27, i32 1
>  %32 = fmul float %25, %31
>  %33 = fadd float %32, %19
>  %34 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
>  %35 = extractelement <4 x float> %34, i32 2
>  %36 = fmul float %26, %35
>  %37 = fadd float %36, %21
>  %38 = insertelement <4 x float> undef, float %30, i32 0
>  %39 = insertelement <4 x float> %38, float %33, i32 1
>  %40 = insertelement <4 x float> %39, float %37, i32 2
>  %41 = insertelement <4 x float> %40, float %14, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %41, i32 0, i32 0)
>  ret void
>}
>
>; Function Attrs: readnone
>declare <2 x float> @llvm.R600.interp.xy(i32, float, float) #1
>
>; Function Attrs: readnone
>declare <2 x float> @llvm.R600.interp.zw(i32, float, float) #1
>
>; Function Attrs: readnone
>declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32, i32) #1
>
>declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
>
>attributes #0 = { "ShaderType"="0" }
>attributes #1 = { readnone }
>
>===== SHADER #43 ==================================== PS/REDWOOD/EVERGREEN =====
>===== 42 dw ===== 4 gprs ===== 0 stack =========================================
>0000  0000000a a00c0000 ALU 4 @20
> 0020  00380400 00146b10     1      x: INTERP_XY          R0.x,  R0.y, Param0.x         VEC_210
> 0022  00380000 20146b10            y: INTERP_XY          R0.y,  R0.x, Param0.x         VEC_210
> 0024  00380400 40146b00            z: INTERP_XY          __.z,  R0.y, Param0.x         VEC_210
> 0026  80380000 60146b00            w: INTERP_XY          __.w,  R0.x, Param0.x         VEC_210
>0002  00000006 80400400 TEX 2 @12
> 0012  00001110 f00d1001 fc808000 SAMPLE              R1.xyzw, R0.xy__,   RID:17, SID:1 CT:NNNN
> 0016  00001010 f00d1000 fc800000 SAMPLE              R0.xyzw, R0.xy__,   RID:16, SID:0 CT:NNNN
>0004  8000000e a0180000 ALU 7 @28 KC0[CB0:0-31]
> 0028  00104000 60400110     2      w: MUL_IEEE           R2.w,  R0.x, KC0[2].x
> 0030  80108c00 60600110            t: MUL_IEEE           R3.w,  R0.w, KC0[4].x
> 0032  00106001 00630cfe     3      x: MULADD_IEEE        R3.x,  R1.x, KC0[3].x, PV.w
> 0034  80904400 60400110            w: MUL_IEEE           R2.w,  R0.y, KC0[2].y
> 0036  00906401 20630cfe     4      y: MULADD_IEEE        R3.y,  R1.y, KC0[3].y, PV.w
> 0038  81104800 60000110            w: MUL_IEEE           R0.w,  R0.z, KC0[2].z
> 0040  81106801 40630cfe     5      z: MULADD_IEEE        R3.z,  R1.z, KC0[3].z, PV.w
>0006  c0018000 95200688 EXPORT_DONE        PIXEL 0     R3.xyzw  EOP
>===== SHADER_END ===============================================================
>
>
>===== SHADER #43 OPT ================================ PS/REDWOOD/EVERGREEN =====
>===== 38 dw ===== 2 gprs ===== 0 stack =========================================
>0000  00000004 a00c0000 ALU 4 @8
> 0008  00380400 00146b10     1      x: INTERP_XY          R0.x,  R0.y, Param0.x         VEC_210
> 0010  00b80000 20146b10            y: INTERP_XY          R0.y,  R0.x, Param0.y         VEC_210
> 0012  01380400 40146b00            z: INTERP_XY          __.z,  R0.y, Param0.z         VEC_210
> 0014  81b80000 60146b00            w: INTERP_XY          __.w,  R0.x, Param0.w         VEC_210
>0002  00000008 80400400 TEX 2 @16
> 0016  00001010 f00d1001 fc800000 SAMPLE              R1.xyzw, R0.xy__,   RID:16, SID:0 CT:NNNN
> 0020  00001110 f01d1000 fc808000 SAMPLE              R0.xyz_, R0.xy__,   RID:17, SID:1 CT:NNNN
>0004  4000000c a0180000 ALU 7 @24 KC0[CB0:0-15]
> 0024  81104801 4f800110     2      z: MUL_IEEE           T0.z,  R1.z, KC0[2].z
> 0026  00104001 0f800110     3      x: MUL_IEEE           T0.x,  R1.x, KC0[2].x
> 0028  00904401 2f800110            y: MUL_IEEE           T0.y,  R1.y, KC0[2].y
> 0030  80108c01 60000110            w: MUL_IEEE           R0.w,  R1.w, KC0[4].x
> 0032  00106000 0003007c     4      x: MULADD_IEEE        R0.x,  R0.x, KC0[3].x, T0.x
> 0034  00906400 2003047c            y: MULADD_IEEE        R0.y,  R0.y, KC0[3].y, T0.y
> 0036  81106800 4003087c            z: MULADD_IEEE        R0.z,  R0.z, KC0[3].z, T0.z
>0006  c0000000 95200688 EXPORT_DONE        PIXEL 0     R0.xyzw  EOP
>===== SHADER_END ===============================================================
>
>--------------------------------------------------------------
>VERT
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[9]
>DCL CONST[0..7]
>DCL TEMP[0..1], LOCAL
>IMM[0] FLT32 {    0.0000,     0.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].zw, IMM[0].xxxx
>  1: MUL TEMP[1], CONST[4], IN[1].xxxx
>  2: MAD TEMP[1], CONST[5], IN[1].yyyy, TEMP[1]
>  3: MAD TEMP[1], CONST[6], IN[1].zzzz, TEMP[1]
>  4: MAD TEMP[1].xy, CONST[7], IN[1].wwww, TEMP[1]
>  5: MOV TEMP[0].xy, TEMP[1].xyxx
>  6: MUL TEMP[1], CONST[0], IN[0].xxxx
>  7: MAD TEMP[1], CONST[1], IN[0].yyyy, TEMP[1]
>  8: MAD TEMP[1], CONST[2], IN[0].zzzz, TEMP[1]
>  9: MAD TEMP[1], CONST[3], IN[0].wwww, TEMP[1]
> 10: MOV OUT[0], TEMP[1]
> 11: MOV OUT[1], TEMP[0]
> 12: END
>; ModuleID = 'tgsi'
>
>define void @main(<4 x float> inreg, <4 x float> inreg, <4 x float> inreg) #0 {
>main_body:
>  %3 = extractelement <4 x float> %1, i32 0
>  %4 = extractelement <4 x float> %1, i32 1
>  %5 = extractelement <4 x float> %1, i32 2
>  %6 = extractelement <4 x float> %1, i32 3
>  %7 = extractelement <4 x float> %2, i32 0
>  %8 = extractelement <4 x float> %2, i32 1
>  %9 = extractelement <4 x float> %2, i32 2
>  %10 = extractelement <4 x float> %2, i32 3
>  %11 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4)
>  %12 = extractelement <4 x float> %11, i32 0
>  %13 = fmul float %12, %7
>  %14 = extractelement <4 x float> %11, i32 1
>  %15 = fmul float %14, %7
>  %16 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5)
>  %17 = extractelement <4 x float> %16, i32 0
>  %18 = fmul float %17, %8
>  %19 = fadd float %18, %13
>  %20 = extractelement <4 x float> %16, i32 1
>  %21 = fmul float %20, %8
>  %22 = fadd float %21, %15
>  %23 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6)
>  %24 = extractelement <4 x float> %23, i32 0
>  %25 = fmul float %24, %9
>  %26 = fadd float %25, %19
>  %27 = extractelement <4 x float> %23, i32 1
>  %28 = fmul float %27, %9
>  %29 = fadd float %28, %22
>  %30 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7)
>  %31 = extractelement <4 x float> %30, i32 0
>  %32 = fmul float %31, %10
>  %33 = fadd float %32, %26
>  %34 = extractelement <4 x float> %30, i32 1
>  %35 = fmul float %34, %10
>  %36 = fadd float %35, %29
>  %37 = load <4 x float> addrspace(8)* null
>  %38 = extractelement <4 x float> %37, i32 0
>  %39 = fmul float %38, %3
>  %40 = extractelement <4 x float> %37, i32 1
>  %41 = fmul float %40, %3
>  %42 = extractelement <4 x float> %37, i32 2
>  %43 = fmul float %42, %3
>  %44 = load <4 x float> addrspace(8)* null
>  %45 = extractelement <4 x float> %44, i32 3
>  %46 = fmul float %45, %3
>  %47 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
>  %48 = extractelement <4 x float> %47, i32 0
>  %49 = fmul float %48, %4
>  %50 = fadd float %49, %39
>  %51 = extractelement <4 x float> %47, i32 1
>  %52 = fmul float %51, %4
>  %53 = fadd float %52, %41
>  %54 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
>  %55 = extractelement <4 x float> %54, i32 2
>  %56 = fmul float %55, %4
>  %57 = fadd float %56, %43
>  %58 = extractelement <4 x float> %54, i32 3
>  %59 = fmul float %58, %4
>  %60 = fadd float %59, %46
>  %61 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
>  %62 = extractelement <4 x float> %61, i32 0
>  %63 = fmul float %62, %5
>  %64 = fadd float %63, %50
>  %65 = extractelement <4 x float> %61, i32 1
>  %66 = fmul float %65, %5
>  %67 = fadd float %66, %53
>  %68 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
>  %69 = extractelement <4 x float> %68, i32 2
>  %70 = fmul float %69, %5
>  %71 = fadd float %70, %57
>  %72 = extractelement <4 x float> %68, i32 3
>  %73 = fmul float %72, %5
>  %74 = fadd float %73, %60
>  %75 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
>  %76 = extractelement <4 x float> %75, i32 0
>  %77 = fmul float %76, %6
>  %78 = fadd float %77, %64
>  %79 = extractelement <4 x float> %75, i32 1
>  %80 = fmul float %79, %6
>  %81 = fadd float %80, %67
>  %82 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
>  %83 = extractelement <4 x float> %82, i32 2
>  %84 = fmul float %83, %6
>  %85 = fadd float %84, %71
>  %86 = extractelement <4 x float> %82, i32 3
>  %87 = fmul float %86, %6
>  %88 = fadd float %87, %74
>  %89 = insertelement <4 x float> undef, float %78, i32 0
>  %90 = insertelement <4 x float> %89, float %81, i32 1
>  %91 = insertelement <4 x float> %90, float %85, i32 2
>  %92 = insertelement <4 x float> %91, float %88, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %92, i32 60, i32 1)
>  %93 = insertelement <4 x float> undef, float %33, i32 0
>  %94 = insertelement <4 x float> %93, float %36, i32 1
>  %95 = insertelement <4 x float> %94, float 0.000000e+00, i32 2
>  %96 = insertelement <4 x float> %95, float 0.000000e+00, i32 3
>  call void @llvm.R600.store.swizzle(<4 x float> %96, i32 0, i32 2)
>  ret void
>}
>
>declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
>
>attributes #0 = { "ShaderType"="1" }
>
>===== SHADER #44 ==================================== VS/REDWOOD/EVERGREEN =====
>===== 60 dw ===== 6 gprs ===== 1 stack =========================================
>0000  00000000 84c00000 CALL_FS @0
>0002  80000006 a05c0000 ALU 24 @12 KC0[CB0:0-31]
> 0012  80002080 60000110     1      w: MUL_IEEE           R0.w,  KC0[0].x, R1.x
> 0014  00802081 40030cfe     2      z: MULADD_IEEE        R0.z,  KC0[1].x, R1.y, PV.w
> 0016  80002480 60000110            w: MUL_IEEE           R0.w,  KC0[0].y, R1.x
> 0018  80004084 60600110     3      w: MUL_IEEE           R3.w,  KC0[4].x, R2.x
> 0020  00804085 40630cfe     4      z: MULADD_IEEE        R3.z,  KC0[5].x, R2.y, PV.w
> 0022  80802481 60070c00            w: MULADD_IEEE        R0.w,  KC0[1].y, R1.y, R0.w   VEC_021
> 0024  81002082 60630800     5      w: MULADD_IEEE        R3.w,  KC0[2].x, R1.z, R0.z
> 0026  01802083 00830cfe     6      x: MULADD_IEEE        R4.x,  KC0[3].x, R1.w, PV.w
> 0028  81002482 60030c00            w: MULADD_IEEE        R0.w,  KC0[2].y, R1.z, R0.w
> 0030  81004086 60630803     7      w: MULADD_IEEE        R3.w,  KC0[6].x, R2.z, R3.z
> 0032  01804087 00630cfe     8      x: MULADD_IEEE        R3.x,  KC0[7].x, R2.w, PV.w
> 0034  81802483 208b0c00            y: MULADD_IEEE        R4.y,  KC0[3].y, R1.w, R0.w   VEC_120
> 0036  80002880 60000110     9      w: MUL_IEEE           R0.w,  KC0[0].z, R1.x
> 0038  00802881 40030cfe    10      z: MULADD_IEEE        R0.z,  KC0[1].z, R1.y, PV.w
> 0040  80002c80 60000110            w: MUL_IEEE           R0.w,  KC0[0].w, R1.x
> 0042  80004484 60a00110    11      w: MUL_IEEE           R5.w,  KC0[4].y, R2.x
> 0044  00804485 40a30cfe    12      z: MULADD_IEEE        R5.z,  KC0[5].y, R2.y, PV.w
> 0046  80802c81 60070c00            w: MULADD_IEEE        R0.w,  KC0[1].w, R1.y, R0.w   VEC_021
> 0048  81002882 60a30800    13      w: MULADD_IEEE        R5.w,  KC0[2].z, R1.z, R0.z
> 0050  01802883 40830cfe    14      z: MULADD_IEEE        R4.z,  KC0[3].z, R1.w, PV.w
> 0052  81002c82 60030c00            w: MULADD_IEEE        R0.w,  KC0[2].w, R1.z, R0.w
> 0054  81004486 60a30805    15      w: MULADD_IEEE        R5.w,  KC0[6].y, R2.z, R5.z
> 0056  01804487 20630cfe    16      y: MULADD_IEEE        R3.y,  KC0[7].y, R2.w, PV.w
> 0058  81802c83 608b0c00            w: MULADD_IEEE        R4.w,  KC0[3].w, R1.w, R0.w   VEC_120
>0004  c002203c 95000688 EXPORT_DONE        POS   60    R4.xyzw
>0006  c001c000 95200908 EXPORT_DONE        PARAM 0     R3.xy00  EOP
>===== SHADER_END ===============================================================
>
>
>===== SHADER #44 OPT ================================ VS/REDWOOD/EVERGREEN =====
>===== 56 dw ===== 3 gprs ===== 1 stack =========================================
>0000  00000000 84c00000 CALL_FS @0
>0002  40000004 a05c0000 ALU 24 @8 KC0[CB0:0-15]
> 0008  00002c80 0f800110     1      x: MUL_IEEE           T0.x,  KC0[0].w, R1.x
> 0010  80002880 2f800110            y: MUL_IEEE           T0.y,  KC0[0].z, R1.x
> 0012  00004084 0fc00110     2      x: MUL_IEEE           T2.x,  KC0[4].x, R2.x
> 0014  00002480 4f840110            z: MUL_IEEE           T0.z,  KC0[0].y, R1.x         VEC_021
> 0016  80002080 6f840110            w: MUL_IEEE           T0.w,  KC0[0].x, R1.x         VEC_021
> 0018  00802c81 0f83007c     3      x: MULADD_IEEE        T0.x,  KC0[1].w, R1.y, T0.x
> 0020  00802881 2fa3047c            y: MULADD_IEEE        T1.y,  KC0[1].z, R1.y, T0.y
> 0022  80004484 0fa00110            t: MUL_IEEE           T1.x,  KC0[4].y, R2.x
> 0024  00804085 2f83007e     4      y: MULADD_IEEE        T0.y,  KC0[5].x, R2.y, T2.x
> 0026  00802481 4f87087c            z: MULADD_IEEE        T0.z,  KC0[1].y, R1.y, T0.z   VEC_021
> 0028  80802081 6f870c7c            w: MULADD_IEEE        T0.w,  KC0[1].x, R1.y, T0.w   VEC_021
> 0030  01002c82 0fc3007c     5      x: MULADD_IEEE        T2.x,  KC0[2].w, R1.z, T0.x
> 0032  01002882 2fa7047d            y: MULADD_IEEE        T1.y,  KC0[2].z, R1.z, T1.y   VEC_021
> 0034  80804485 0f8f007d            t: MULADD_IEEE        T0.x,  KC0[5].y, R2.y, T1.x   SCL_221
> 0036  01004486 0f8f007c     6      x: MULADD_IEEE        T0.x,  KC0[6].y, R2.z, T0.x   VEC_102
> 0038  01004086 2f8f047c            y: MULADD_IEEE        T0.y,  KC0[6].x, R2.z, T0.y   VEC_102
> 0040  01002082 4f830c7c            z: MULADD_IEEE        T0.z,  KC0[2].x, R1.z, T0.w
> 0042  81002482 0fab087c            t: MULADD_IEEE        T1.x,  KC0[2].y, R1.z, T0.z   SCL_212
> 0044  01802483 2003007d     7      y: MULADD_IEEE        R0.y,  KC0[3].y, R1.w, T1.x
> 0046  01802883 4003047d            z: MULADD_IEEE        R0.z,  KC0[3].z, R1.w, T1.y
> 0048  81802c83 6007007e            w: MULADD_IEEE        R0.w,  KC0[3].w, R1.w, T2.x   VEC_021
> 0050  01804087 0023047c     8      x: MULADD_IEEE        R1.x,  KC0[7].x, R2.w, T0.y
> 0052  01804487 2023007c            y: MULADD_IEEE        R1.y,  KC0[7].y, R2.w, T0.x
> 0054  81802083 0007087c            t: MULADD_IEEE        R0.x,  KC0[3].x, R1.w, T0.z   SCL_122
>0004  c000c000 95000908 EXPORT_DONE        PARAM 0     R1.xy00
>0006  c000203c 95200688 EXPORT_DONE        POS   60    R0.xyzw  EOP
>===== SHADER_END ===============================================================
>
>Receiving player stats failed: -404
>--------------------------------------------------------------
>FRAG
>DCL IN[0], GENERIC[9], PERSPECTIVE
>DCL IN[1], GENERIC[10], PERSPECTIVE
>DCL IN[2], GENERIC[11], PERSPECTIVE
>DCL IN[3], GENERIC[12], PERSPECTIVE
>DCL IN[4], GENERIC[13], PERSPECTIVE
>DCL IN[5], GENERIC[14], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SAMP[1]
>DCL SAMP[2]
>DCL SAMP[3]
>DCL SAMP[4]
>DCL SAMP[5]
>DCL SAMP[6]
>DCL SAMP[7]
>DCL SVIEW[0], 2D, FLOAT
>DCL SVIEW[1], 2D, FLOAT
>DCL SVIEW[2], 2D, FLOAT
>DCL SVIEW[3], 2D, FLOAT
>DCL SVIEW[4], 2D, FLOAT
>DCL SVIEW[5], 2D, FLOAT
>DCL SVIEW[6], 2D, FLOAT
>DCL SVIEW[7], CUBE, FLOAT
>DCL CONST[6..17]
>DCL CONST[20]
>DCL TEMP[0..7], LOCAL
>IMM[0] FLT32 {   -0.5000,     2.0000,     0.0000,     1.0000}
>  0: MOV TEMP[0].xy, IN[1].xyyy
>  1: TEX TEMP[0], TEMP[0], SAMP[1], 2D
>  2: MUL TEMP[1].x, TEMP[0].wwww, CONST[13].xxxx
>  3: MOV TEMP[1].w, TEMP[1].xxxx
>  4: MOV TEMP[2].xy, IN[1].xyyy
>  5: TEX TEMP[2].xyz, TEMP[2], SAMP[5], 2D
>  6: MOV TEMP[3].xy, IN[1].xyyy
>  7: TEX TEMP[3].xyz, TEMP[3], SAMP[4], 2D
>  8: MUL TEMP[3].xyz, TEMP[3].xyzz, CONST[6].xyzz
>  9: MAD TEMP[2].xyz, TEMP[2].xyzz, CONST[7].xyzz, TEMP[3].xyzz
> 10: ADD TEMP[1].xyz, TEMP[0].xyzz, TEMP[2].xyzz
> 11: MOV TEMP[0].xy, IN[1].xyyy
> 12: TEX TEMP[0].xyz, TEMP[0], SAMP[0], 2D
> 13: ADD TEMP[0].xyz, TEMP[0].xyzz, IMM[0].xxxx
> 14: DP3 TEMP[2].x, TEMP[0].xyzz, TEMP[0].xyzz
> 15: RSQ TEMP[2].x, TEMP[2].xxxx
> 16: MUL TEMP[0].xyz, TEMP[0].xyzz, TEMP[2].xxxx
> 17: MOV TEMP[2].xy, IN[1].xyyy
> 18: TEX TEMP[2], TEMP[2], SAMP[2], 2D
> 19: MOV TEMP[3].xyz, -IN[0].xyzx
> 20: DP3 TEMP[4].x, TEMP[0].xyzz, TEMP[3].xyzz
> 21: MUL TEMP[4].xyz, TEMP[4].xxxx, TEMP[0].xyzz
> 22: MUL TEMP[4].xyz, IMM[0].yyyy, TEMP[4].xyzz
> 23: ADD TEMP[3].xyz, TEMP[3].xyzz, -TEMP[4].xyzz
> 24: MUL TEMP[4].xyz, TEMP[3].xxxx, IN[3].xyzz
> 25: MAD TEMP[4].xyz, TEMP[3].yyyy, IN[4].xyzz, TEMP[4].xyzz
> 26: MAD TEMP[3].xyz, TEMP[3].zzzz, IN[2].xyzz, TEMP[4].xyzz
> 27: MOV TEMP[4].xy, IN[1].xyyy
> 28: TEX TEMP[4].xyz, TEMP[4], SAMP[6], 2D
> 29: MUL TEMP[5], CONST[14], TEMP[3].xxxx
> 30: MAD TEMP[5], CONST[15], TEMP[3].yyyy, TEMP[5]
> 31: MAD TEMP[3].xyz, CONST[16], TEMP[3].zzzz, TEMP[5]
> 32: MOV TEMP[3].xyz, TEMP[3].xyzz
> 33: TEX TEMP[3].xyz, TEMP[3], SAMP[7], CUBE
> 34: MAD TEMP[3].xyz, TEMP[4].xyzz, TEMP[3].xyzz, TEMP[1].xyzz
> 35: DP3 TEMP[4].x, IN[5].xyzz, IN[5].xyzz
> 36: RSQ TEMP[4].x, TEMP[4].xxxx
> 37: MUL TEMP[4].xyz, IN[5].xyzz, TEMP[4].xxxx
> 38: MUL TEMP[5].xyz, TEMP[2].xyzz, CONST[10].xyzz
> 39: DP3 TEMP[6].x, TEMP[0].xyzz, TEMP[4].xyzz
> 40: MUL TEMP[6].xyz, TEMP[6].xxxx, TEMP[0].xyzz
> 41: MUL TEMP[6].xyz, IMM[0].yyyy, TEMP[6].xyzz
> 42: ADD TEMP[6].xyz, TEMP[4].xyzz, -TEMP[6].xyzz
> 43: DP3 TEMP[7].x, IN[0].xyzz, IN[0].xyzz
> 44: RSQ TEMP[7].x, TEMP[7].xxxx
> 45: MUL TEMP[7].xyz, IN[0].xyzz, TEMP[7].xxxx
> 46: DP3 TEMP[6].x, TEMP[6].xyzz, TEMP[7].xyzz
> 47: MAX TEMP[6].x, -TEMP[6].xxxx, IMM[0].zzzz
> 48: MAD TEMP[2].x, CONST[11].xxxx, TEMP[2].wwww, IMM[0].wwww
> 49: POW TEMP[2].x, TEMP[6].xxxx, TEMP[2].xxxx
> 50: MUL TEMP[6].xyz, TEMP[3].xyzz, CONST[9].xyzz
> 51: DP3 TEMP[0].x, TEMP[0].xyzz, TEMP[4].xyzz
> 52: MAX TEMP[0].x, TEMP[0].xxxx, IMM[0].zzzz
> 53: MUL TEMP[0].xyz, TEMP[6].xyzz, TEMP[0].xxxx
> 54: MAD TEMP[0].xyz, TEMP[5].xyzz, TEMP[2].xxxx, TEMP[0].xyzz
> 55: MUL TEMP[2].xyz, TEMP[3].xyzz, CONST[8].xyzz
> 56: MAD TEMP[1].xyz, TEMP[0].xyzz, CONST[20].xyzz, TEMP[2].xyzz
> 57: MOV TEMP[0].xy, IN[1].xyyy
> 58: TEX TEMP[0].xyz, TEMP[0], SAMP[3], 2D
> 59: MAD TEMP[1].xyz, TEMP[0].xyzz, CONST[12].xyzz, TEMP[1].xyzz
> 60: MOV OUT[0], TEMP[1]
> 61: END
>xonotic-linux32-glx: Instructions.cpp:1499: llvm::InsertElementInst::InsertElementInst(llvm::Value *, llvm::Value *, llvm::Value *, const llvm::Twine &, llvm::Instruction *): Assertion `isValidOperands(Vec, Elt, Index) && "Invalid insertelement instruction operands!"' failed.
>Received signal 6, exiting...
>Saving persistent data...
>done!
>Client "snejko" dropped
>Client "[BOT]Pegasus" dropped
>Client "[BOT]Scorcher" dropped
>Player stats writing failed: -2

Actions: View

Attachments on bug 91828: 118020

Use of freedesktop.org services, including Bugzilla, is subject to our Code of Conduct. How we collect and use information is described in our Privacy Policy.