Attachment 118174 Details for Bug 91952 – Revert "drm/i915: get rid of primary_enabled and use atomic state"

[patch] Revert "drm/i915: get rid of primary_enabled and use atomic state"

0001-Revert-drm-i915-get-rid-of-primary_enabled-and-use-a.patch (text/plain), 8.29 KB, created by João Paulo Rechi Vita on 2015-09-10 01:25:39 UTC

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Creator: João Paulo Rechi Vita

Created: 2015-09-10 01:25:39 UTC

Size: 8.29 KB

patch

obsolete

>From 97dd64d2196babee92ab565a43f50ac1f659c96d Mon Sep 17 00:00:00 2001
>From: =?UTF-8?q?Jo=C3=A3o=20Paulo=20Rechi=20Vita?= <jprvita@endlessm.com>
>Date: Wed, 9 Sep 2015 13:51:16 -0400
>Subject: [PATCH 1/2] Revert "drm/i915: get rid of primary_enabled and use
> atomic state"
>MIME-Version: 1.0
>Content-Type: text/plain; charset=UTF-8
>Content-Transfer-Encoding: 8bit
>
>This reverts commit b70709a6f0e9176c2bc7ecf44acf015c7362ddc6.
>
>This is needed to allow reverting "drm/i915: Use the disable callback
>for disabling planes." (27321ae88c70104df1ade701e079932b54360885).
>
>Signed-off-by: JoÃ£o Paulo Rechi Vita <jprvita@endlessm.com>
>
>Conflicts:
>	drivers/gpu/drm/i915/intel_display.c
>---
> drivers/gpu/drm/i915/intel_display.c | 41 ++++++++++++++++++------------------
> drivers/gpu/drm/i915/intel_drv.h     |  1 +
> drivers/gpu/drm/i915/intel_fbc.c     |  2 +-
> 3 files changed, 23 insertions(+), 21 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>index 87476ff..0ec2d99 100644
>--- a/drivers/gpu/drm/i915/intel_display.c
>+++ b/drivers/gpu/drm/i915/intel_display.c
>@@ -2227,7 +2227,11 @@ static void intel_enable_primary_hw_plane(struct drm_plane *plane,
> 
> 	/* If the pipe isn't enabled, we can't pump pixels and may hang */
> 	assert_pipe_enabled(dev_priv, intel_crtc->pipe);
>-	to_intel_plane_state(plane->state)->visible = true;
>+
>+	if (intel_crtc->primary_enabled)
>+		return;
>+
>+	intel_crtc->primary_enabled = true;
> 
> 	dev_priv->display.update_primary_plane(crtc, plane->fb,
> 					       crtc->x, crtc->y);
>@@ -2640,8 +2644,6 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
> 	struct drm_device *dev = crtc->dev;
> 	struct drm_i915_private *dev_priv = dev->dev_private;
> 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>-	struct drm_plane *primary = crtc->primary;
>-	bool visible = to_intel_plane_state(primary->state)->visible;
> 	struct drm_i915_gem_object *obj;
> 	int plane = intel_crtc->plane;
> 	unsigned long linear_offset;
>@@ -2649,7 +2651,7 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
> 	u32 reg = DSPCNTR(plane);
> 	int pixel_size;
> 
>-	if (!visible || !fb) {
>+	if (!intel_crtc->primary_enabled || !fb) {
> 		I915_WRITE(reg, 0);
> 		if (INTEL_INFO(dev)->gen >= 4)
> 			I915_WRITE(DSPSURF(plane), 0);
>@@ -2766,8 +2768,6 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
> 	struct drm_device *dev = crtc->dev;
> 	struct drm_i915_private *dev_priv = dev->dev_private;
> 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>-	struct drm_plane *primary = crtc->primary;
>-	bool visible = to_intel_plane_state(primary->state)->visible;
> 	struct drm_i915_gem_object *obj;
> 	int plane = intel_crtc->plane;
> 	unsigned long linear_offset;
>@@ -2775,7 +2775,7 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
> 	u32 reg = DSPCNTR(plane);
> 	int pixel_size;
> 
>-	if (!visible || !fb) {
>+	if (!intel_crtc->primary_enabled || !fb) {
> 		I915_WRITE(reg, 0);
> 		I915_WRITE(DSPSURF(plane), 0);
> 		POSTING_READ(reg);
>@@ -3021,8 +3021,6 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc,
> 	struct drm_device *dev = crtc->dev;
> 	struct drm_i915_private *dev_priv = dev->dev_private;
> 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>-	struct drm_plane *plane = crtc->primary;
>-	bool visible = to_intel_plane_state(plane->state)->visible;
> 	struct drm_i915_gem_object *obj;
> 	int pipe = intel_crtc->pipe;
> 	u32 plane_ctl, stride_div, stride;
>@@ -3030,15 +3028,17 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc,
> 	unsigned int rotation;
> 	int x_offset, y_offset;
> 	unsigned long surf_addr;
>+	struct drm_plane *plane;
> 	struct intel_crtc_state *crtc_state = intel_crtc->config;
> 	struct intel_plane_state *plane_state;
> 	int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
> 	int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
> 	int scaler_id = -1;
> 
>+	plane = crtc->primary;
> 	plane_state = to_intel_plane_state(plane->state);
> 
>-	if (!visible || !fb) {
>+	if (!intel_crtc->primary_enabled || !fb) {
> 		I915_WRITE(PLANE_CTL(pipe, 0), 0);
> 		I915_WRITE(PLANE_SURF(pipe, 0), 0);
> 		POSTING_READ(PLANE_CTL(pipe, 0));
>@@ -4862,6 +4862,7 @@ static void intel_crtc_disable_planes(struct drm_crtc *crtc)
> 	intel_pre_disable_primary(crtc);
> 
> 	intel_crtc_dpms_overlay_disable(intel_crtc);
>+	intel_crtc->primary_enabled = false;
> 	for_each_intel_plane(dev, intel_plane) {
> 		if (intel_plane->pipe == pipe) {
> 			struct drm_crtc *from = intel_plane->base.crtc;
>@@ -12937,6 +12938,7 @@ static int intel_crtc_set_config(struct drm_mode_set *set)
> 	intel_update_pipe_size(to_intel_crtc(set->crtc));
> 
> 	ret = intel_set_mode_with_config(set->crtc, pipe_config, true);
>+	intel_modeset_check_state(set->crtc->dev);
> 
> 	if (ret) {
> 		DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
>@@ -13253,20 +13255,20 @@ intel_check_primary_plane(struct drm_plane *plane,
> 		 * one is done too late. We eventually need to unify
> 		 * this.
> 		 */
>-		if (state->visible &&
>+		if (intel_crtc->primary_enabled &&
> 		    INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
> 		    dev_priv->fbc.crtc == intel_crtc &&
> 		    state->base.rotation != BIT(DRM_ROTATE_0)) {
> 			intel_crtc->atomic.disable_fbc = true;
> 		}
> 
>-		if (state->visible && !old_state->visible) {
>+		if (state->visible) {
> 			/*
> 			 * BDW signals flip done immediately if the plane
> 			 * is disabled, even if the plane enable is already
> 			 * armed to occur at the next vblank :(
> 			 */
>-			if (IS_BROADWELL(dev))
>+			if (IS_BROADWELL(dev) && !intel_crtc->primary_enabled)
> 				intel_crtc->atomic.wait_vblank = true;
> 
> 			if (crtc_state)
>@@ -13325,6 +13327,8 @@ intel_commit_primary_plane(struct drm_plane *plane,
> 	crtc->y = src->y1 >> 16;
> 
> 	if (intel_crtc->active) {
>+		intel_crtc->primary_enabled = state->visible;
>+
> 		if (state->visible)
> 			/* FIXME: kill this fastboot hack */
> 			intel_update_pipe_size(intel_crtc);
>@@ -13342,6 +13346,9 @@ intel_disable_primary_plane(struct drm_plane *plane,
> 	struct drm_device *dev = plane->dev;
> 	struct drm_i915_private *dev_priv = dev->dev_private;
> 
>+	if (!force)
>+		to_intel_crtc(crtc)->primary_enabled = false;
>+
> 	dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
> }
> 
>@@ -14819,7 +14826,6 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc)
> 		 * Temporarily change the plane mapping and disable everything
> 		 * ...  */
> 		plane = crtc->plane;
>-		to_intel_plane_state(crtc->base.primary->state)->visible = true;
> 		crtc->plane = !plane;
> 		intel_crtc_disable_planes(&crtc->base);
> 		dev_priv->display.crtc_disable(&crtc->base);
>@@ -15000,9 +15006,6 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
> 	int i;
> 
> 	for_each_intel_crtc(dev, crtc) {
>-		struct drm_plane *primary = crtc->base.primary;
>-		struct intel_plane_state *plane_state;
>-
> 		memset(crtc->config, 0, sizeof(*crtc->config));
> 		crtc->config->base.crtc = &crtc->base;
> 
>@@ -15014,9 +15017,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
> 		crtc->base.state->enable = crtc->active;
> 		crtc->base.state->active = crtc->active;
> 		crtc->base.enabled = crtc->active;
>-
>-		plane_state = to_intel_plane_state(primary->state);
>-		plane_state->visible = primary_get_hw_state(crtc);
>+		crtc->primary_enabled = primary_get_hw_state(crtc);
> 
> 		DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
> 			      crtc->base.base.id,
>diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
>index 1059283..3075b1f 100644
>--- a/drivers/gpu/drm/i915/intel_drv.h
>+++ b/drivers/gpu/drm/i915/intel_drv.h
>@@ -510,6 +510,7 @@ struct intel_crtc {
> 	 */
> 	bool active;
> 	unsigned long enabled_power_domains;
>+	bool primary_enabled; /* is the primary plane (partially) visible? */
> 	bool lowfreq_avail;
> 	struct intel_overlay *overlay;
> 	struct intel_unpin_work *unpin_work;
>diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
>index 6abb834..4165ce0 100644
>--- a/drivers/gpu/drm/i915/intel_fbc.c
>+++ b/drivers/gpu/drm/i915/intel_fbc.c
>@@ -457,7 +457,7 @@ static struct drm_crtc *intel_fbc_find_crtc(struct drm_i915_private *dev_priv)
> 		tmp_crtc = dev_priv->pipe_to_crtc_mapping[pipe];
> 
> 		if (intel_crtc_active(tmp_crtc) &&
>-		    to_intel_plane_state(tmp_crtc->primary->state)->visible) {
>+		    to_intel_crtc(tmp_crtc)->primary_enabled) {
> 			if (one_pipe_only && crtc) {
> 				if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
> 					DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
>-- 
>2.1.4
>

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