Attachment 120322 Details for Bug 92957 – This patch completely rewrites VIASave and VIARestore functions

[patch] This patch completely rewrites VIASave and VIARestore functions

0002-Completely-rewrites-VIASave-and-VIARestore-functions.patch (text/plain), 39.94 KB, created by Kevin Brace on 2015-12-04 05:28:33 UTC

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Creator: Kevin Brace

Created: 2015-12-04 05:28:33 UTC

Size: 39.94 KB

patch

obsolete

>From 761f94e675cc071f5881758c4396465ca82f312f Mon Sep 17 00:00:00 2001
>From: Kevin Brace <kevinbrace@gmx.com>
>Date: Sat, 14 Nov 2015 20:35:49 -0800
>Subject: [PATCH 02/10] Completely rewrites VIASave and VIARestore functions
> inside via_vgahw.c. It now saves and restores
> virtually all VIA Technologies defined extended VGA
> registers. The previous code did not save all
> extended VGA registers, so many registers were not
> being restored at all. That being said, Chrome 9 HD
> HDMI or DisplayPort registers are not being saved or
> restored since they cannot be accessed via VGA I/O
> ports.     The compiled device driver was tested on
> the following computer.
>
> - Epic 1314 laptop (MSI VR321 laptop equivalent, VN896 chipset)
>   with Lubuntu 12.04 i386
>---
> src/via_driver.h |   40 ++-
> src/via_vgahw.c  |  950 ++++++++++++++++++++++++++++++++++++++++++++----------
> 2 files changed, 799 insertions(+), 191 deletions(-)
>
>diff --git a/src/via_driver.h b/src/via_driver.h
>index be0e73d..81618e3 100644
>--- a/src/via_driver.h
>+++ b/src/via_driver.h
>@@ -1,4 +1,5 @@
> /*
>+ * Copyright 2015 Kevin Brace
>  * Copyright 2004-2005 The Unichrome Project  [unichrome.sf.net]
>  * Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved.
>  * Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved.
>@@ -130,25 +131,32 @@ typedef struct {
>     CARD8   SR08, SR0A, SR0F;
> 
>     /*   extended Sequencer registers */
>-    CARD8   SR10, SR11, SR12, SR13,SR14,SR15,SR16;
>-    CARD8   SR17, SR18, SR19, SR1A,SR1B,SR1C,SR1D,SR1E;
>-    CARD8   SR1F, SR20, SR21, SR22,SR23,SR24,SR25,SR26;
>-    CARD8   SR27, SR28, SR29, SR2A,SR2B,SR2C,SR2D,SR2E;
>-    CARD8   SR2F, SR30, SR31, SR32,SR33,SR34,SR40,SR41;
>-    CARD8   SR42, SR43, SR44, SR45,SR46,SR47,SR48,SR49;
>-    CARD8   SR4A, SR4B, SR4C, SR4D;
>+    CARD8   SR10, SR11, SR12, SR13, SR14, SR15, SR16, SR17;
>+    CARD8   SR18, SR19, SR1A, SR1B, SR1C, SR1D, SR1E, SR1F;
>+    CARD8   SR20, SR21, SR22, SR23, SR24, SR25, SR26, SR27;
>+    CARD8   SR28, SR29, SR2A, SR2B, SR2C, SR2D, SR2E, SR2F;
>+    CARD8   SR30, SR31, SR32, SR33, SR34;
>+    CARD8   SR40, SR41, SR42, SR43, SR44, SR45, SR46, SR47;
>+    CARD8   SR48, SR49, SR4A, SR4B, SR4C, SR4D, SR4E, SR4F;
> 
>     /*   extended CRTC registers */
>     CARD8   CR0C, CR0D;
>-    CARD8   CR13, CR30, CR31, CR32, CR33, CR34, CR35, CR36;
>-    CARD8   CR37, CR38, CR39, CR3A, CR40, CR41, CR42, CR43;
>-    CARD8   CR44, CR45, CR46, CR47, CR48, CR49, CR4A;
>-    CARD8   CR97, CR99, CR9B, CR9F, CRA0, CRA1, CRA2;
>-    CARD8   CRTCRegs[68];
>-/*    CARD8   LCDRegs[0x40];*/
>-
>-    /* TMDS/LVDS Control */
>-    CARD8   CRD2;
>+    CARD8   CR13;
>+    CARD8   CR30, CR31, CR32, CR33, CR34, CR35, CR36, CR37;
>+    CARD8   CR38, CR39, CR3A, CR3B, CR3C, CR3D, CR3E, CR3F;
>+    CARD8   CR40, CR41, CR42, CR43, CR44, CR45, CR46, CR47;
>+    CARD8   CR48;
>+    CARD8   CR97, CR99, CR9B, CR9F;
>+    CARD8   CRA0, CRA1, CRA2;
>+/* TMDS/LVDS Control */
>+/*  CARD8   CRD2; */
>+
>+/*  CARD8   CRTCRegs[68]; */
>+/*  CARD8   LCDRegs[0x40];*/
>+    CARD8   EXCR[0xfd - 0x50 + 1];
>+
>+
>+
> } VIARegRec, *VIARegPtr;
> 
> /*
>diff --git a/src/via_vgahw.c b/src/via_vgahw.c
>index 1e0f808..b6aaf25 100644
>--- a/src/via_vgahw.c
>+++ b/src/via_vgahw.c
>@@ -1,4 +1,5 @@
> /*
>+ * Copyright 2015 Kevin Brace
>  * Copyright 2004-2005 The Unichrome Project  [unichrome.sf.net]
>  *
>  * Permission is hereby granted, free of charge, to any person obtaining a
>@@ -40,8 +41,7 @@
> #define PIOOFFSET 0
> #endif
> 
>-CARD8
>-ViaVgahwIn(vgaHWPtr hwp, int address)
>+CARD8 ViaVgahwIn(vgaHWPtr hwp, int address)
> {
>     if (hwp->MMIOBase)
>         return MMIO_IN8(hwp->MMIOBase, hwp->MMIOOffset + address);
>@@ -49,8 +49,7 @@ ViaVgahwIn(vgaHWPtr hwp, int address)
>         return inb(PIOOFFSET + address);
> }
> 
>-static void
>-ViaVgahwOut(vgaHWPtr hwp, int address, CARD8 value)
>+static void ViaVgahwOut(vgaHWPtr hwp, int address, CARD8 value)
> {
>     if (hwp->MMIOBase)
>         MMIO_OUT8(hwp->MMIOBase, hwp->MMIOOffset + address, value);
>@@ -61,8 +60,7 @@ ViaVgahwOut(vgaHWPtr hwp, int address, CARD8 value)
> /*
>  * An indexed read.
>  */
>-static CARD8
>-ViaVgahwRead(vgaHWPtr hwp, int indexaddress, CARD8 index, int valueaddress)
>+static CARD8 ViaVgahwRead(vgaHWPtr hwp, int indexaddress, CARD8 index, int valueaddress)
> {
>     ViaVgahwOut(hwp, indexaddress, index);
>     return ViaVgahwIn(hwp, valueaddress);
>@@ -71,8 +69,7 @@ ViaVgahwRead(vgaHWPtr hwp, int indexaddress, CARD8 index, int valueaddress)
> /*
>  * An indexed write.
>  */
>-void
>-ViaVgahwWrite(vgaHWPtr hwp, int indexaddress, CARD8 index,
>+void ViaVgahwWrite(vgaHWPtr hwp, int indexaddress, CARD8 index,
>               int valueaddress, CARD8 value)
> {
>     ViaVgahwOut(hwp, indexaddress, index);
>@@ -80,8 +77,7 @@ ViaVgahwWrite(vgaHWPtr hwp, int indexaddress, CARD8 index,
> }
> 
> 
>-void
>-ViaVgahwMask(vgaHWPtr hwp, int indexaddress, CARD8 index,
>+void ViaVgahwMask(vgaHWPtr hwp, int indexaddress, CARD8 index,
>              int valueaddress, CARD8 value, CARD8 mask)
> {
>     CARD8 tmp;
>@@ -93,8 +89,7 @@ ViaVgahwMask(vgaHWPtr hwp, int indexaddress, CARD8 index,
>     ViaVgahwWrite(hwp, indexaddress, index, valueaddress, tmp);
> }
> 
>-void
>-ViaCrtcMask(vgaHWPtr hwp, CARD8 index, CARD8 value, CARD8 mask)
>+void ViaCrtcMask(vgaHWPtr hwp, CARD8 index, CARD8 value, CARD8 mask)
> {
>     CARD8 tmp;
> 
>@@ -105,8 +100,7 @@ ViaCrtcMask(vgaHWPtr hwp, CARD8 index, CARD8 value, CARD8 mask)
>     hwp->writeCrtc(hwp, index, tmp);
> }
> 
>-void
>-ViaSeqMask(vgaHWPtr hwp, CARD8 index, CARD8 value, CARD8 mask)
>+void ViaSeqMask(vgaHWPtr hwp, CARD8 index, CARD8 value, CARD8 mask)
> {
>     CARD8 tmp;
> 
>@@ -117,8 +111,7 @@ ViaSeqMask(vgaHWPtr hwp, CARD8 index, CARD8 value, CARD8 mask)
>     hwp->writeSeq(hwp, index, tmp);
> }
> 
>-void
>-ViaGrMask(vgaHWPtr hwp, CARD8 index, CARD8 value, CARD8 mask)
>+void ViaGrMask(vgaHWPtr hwp, CARD8 index, CARD8 value, CARD8 mask)
> {
>     CARD8 tmp;
> 
>@@ -129,8 +122,7 @@ ViaGrMask(vgaHWPtr hwp, CARD8 index, CARD8 value, CARD8 mask)
>     hwp->writeGr(hwp, index, tmp);
> }
> 
>-void
>-VIASave(ScrnInfoPtr pScrn)
>+void VIASave(ScrnInfoPtr pScrn)
> {
>     vgaHWPtr hwp = VGAHWPTR(pScrn);
>     VIAPtr pVia = VIAPTR(pScrn);
>@@ -138,7 +130,7 @@ VIASave(ScrnInfoPtr pScrn)
>     VIARegPtr Regs = &pVia->SavedReg;
>     int i;
> 
>-    DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO, "VIASave\n"));
>+    DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Entered VIASave.\n"));
> 
>     if (pVia->IsSecondary) {
>         DevUnion *pPriv;
>@@ -168,7 +160,11 @@ VIASave(ScrnInfoPtr pScrn)
>             DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
>                   "Non-Primary Adapter! saving VGA_SR_MODE only !!\n"));
>         }
>-        /* Unlock and save extended registers. */
>+ 
>+
>+        DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Saving sequencer registers.\n"));
>+
>+/* Unlock and save extended registers. */
>         hwp->writeSeq(hwp, 0x10, 0x01);
> 
>         Regs->SR14 = hwp->readSeq(hwp, 0x14);
>@@ -177,117 +173,393 @@ VIASave(ScrnInfoPtr pScrn)
>         Regs->SR17 = hwp->readSeq(hwp, 0x17);
>         Regs->SR18 = hwp->readSeq(hwp, 0x18);
>         Regs->SR19 = hwp->readSeq(hwp, 0x19);
>-        /* PCI Bus Control */
>-        Regs->SR1A = hwp->readSeq(hwp, 0x1A);
> 
>-        Regs->SR1B = hwp->readSeq(hwp, 0x1B);
>-        Regs->SR1C = hwp->readSeq(hwp, 0x1C);
>-        Regs->SR1D = hwp->readSeq(hwp, 0x1D);
>-        Regs->SR1E = hwp->readSeq(hwp, 0x1E);
>-        Regs->SR1F = hwp->readSeq(hwp, 0x1F);
>+/* PCI Bus Control */
>+        Regs->SR1A = hwp->readSeq(hwp, 0x1a);
>+
>+        Regs->SR1B = hwp->readSeq(hwp, 0x1b);
>+        Regs->SR1C = hwp->readSeq(hwp, 0x1c);
>+        Regs->SR1D = hwp->readSeq(hwp, 0x1d);
>+        Regs->SR1E = hwp->readSeq(hwp, 0x1e);
>+        Regs->SR1F = hwp->readSeq(hwp, 0x1f);
> 
>         Regs->SR22 = hwp->readSeq(hwp, 0x22);
>-        Regs->SR23 = hwp->readSeq(hwp, 0x23);
>-        Regs->SR24 = hwp->readSeq(hwp, 0x24);
>-        Regs->SR25 = hwp->readSeq(hwp, 0x25);
>+
>+/* Registers 0x3c5.0x23 through 0x3c5.0x25 are not used by */
>+/* Chrome 9. */
>+/* Registers 0x3c5.0x27 through 0x3c5.0x29 are not used by */
>+/* Chrome 9. */
>+        switch (pVia->Chipset) {
>+            case VIA_CLE266:
>+            case VIA_KM400:
>+            case VIA_PM800:
>+            case VIA_K8M800:
>+            case VIA_P4M800PRO:
>+            case VIA_CX700:
>+            case VIA_P4M890:
>+
>+                Regs->SR23 = hwp->readSeq(hwp, 0x23);
>+                Regs->SR24 = hwp->readSeq(hwp, 0x24);
>+                Regs->SR25 = hwp->readSeq(hwp, 0x25);
>+
>+                Regs->SR27 = hwp->readSeq(hwp, 0x27);
>+                Regs->SR28 = hwp->readSeq(hwp, 0x28);
>+                Regs->SR29 = hwp->readSeq(hwp, 0x29);
>+                break;
>+        }
>+
>         Regs->SR26 = hwp->readSeq(hwp, 0x26);
>-        Regs->SR27 = hwp->readSeq(hwp, 0x27);
>-        Regs->SR28 = hwp->readSeq(hwp, 0x28);
>-        Regs->SR29 = hwp->readSeq(hwp, 0x29);
>-        Regs->SR2A = hwp->readSeq(hwp, 0x2A);
>-        Regs->SR2B = hwp->readSeq(hwp, 0x2B);
> 
>-        Regs->SR2E = hwp->readSeq(hwp, 0x2E);
>+        Regs->SR2A = hwp->readSeq(hwp, 0x2a);
>+        Regs->SR2B = hwp->readSeq(hwp, 0x2b);
>+
>+/* Saving the content of register 0x3c5.0x2d was missing */
>+/* from the code obtained around July 2015. */
>+        Regs->SR2D = hwp->readSeq(hwp, 0x2d);
>+        Regs->SR2E = hwp->readSeq(hwp, 0x2e);
>+
>+/* Save PCI Configuration Memory Base Shadow 0 and 1 */
>+/* These registers are available only in UniChrome, UniChrome Pro, */
>+/* and UniChrome Pro II. */
>+        switch (pVia->Chipset) {
>+            case VIA_CLE266:
>+            case VIA_KM400:
>+            case VIA_PM800:
>+            case VIA_K8M800:
>+            case VIA_P4M800PRO:
>+            case VIA_CX700:
>+            case VIA_P4M890:
>+
>+                Regs->SR2F = hwp->readSeq(hwp, 0x2f);
>+                Regs->SR30 = hwp->readSeq(hwp, 0x30);
>+                break;
>+        }
>+
>+/* Save PLL settings and several miscellaneous registers */
>+/* For UniChrome, register 0x3c5.0x44 through 0x4b are */
>+/* saved. */
>+/* For UniChrome Pro and Chrome 9, register 0x3c5.0x44 */
>+/* through 0x4c are saved. */
> 
>-        /*=* Save VCK, LCDCK and ECK  *=*/
>-        /* Primary Display (VCK) (description for Chipset >= K8M800): */
>         Regs->SR44 = hwp->readSeq(hwp, 0x44);
>         Regs->SR45 = hwp->readSeq(hwp, 0x45);
>         Regs->SR46 = hwp->readSeq(hwp, 0x46);
>-
>-        /* ECK Clock Synthesizer (description for Chipset >= K8M800): */
>         Regs->SR47 = hwp->readSeq(hwp, 0x47);
>         Regs->SR48 = hwp->readSeq(hwp, 0x48);
>         Regs->SR49 = hwp->readSeq(hwp, 0x49);
>+        Regs->SR4A = hwp->readSeq(hwp, 0x4a);
>+        Regs->SR4B = hwp->readSeq(hwp, 0x4b);
> 
>         switch (pVia->Chipset) {
>-            case VIA_CLE266:
>-            case VIA_KM400:
>-                break;
>-            default:
>-                /* Secondary Display (LCDCK): */
>-                Regs->SR4A = hwp->readSeq(hwp, 0x4A);
>-                Regs->SR4B = hwp->readSeq(hwp, 0x4B);
>-                Regs->SR4C = hwp->readSeq(hwp, 0x4C);
>+            case VIA_PM800:
>+            case VIA_K8M800:
>+            case VIA_P4M800PRO:
>+            case VIA_CX700:
>+            case VIA_P4M890:
>+            case VIA_K8M890:
>+            case VIA_P4M900:
>+            case VIA_VX800:
>+            case VIA_VX855:
>+            case VIA_VX900:
>+
>+                Regs->SR4C = hwp->readSeq(hwp, 0x4c);
>+
>+/* Save register 0x3c5.0x4d. */
>+/* According to CX700 (UniChrome Pro II) documentation, this register */
>+/* is called Dual Channel Memory Control. */
>+/* According to VX800 / VX855 / VX900 (Chrome 9 HC3 / HCM / HD) */
>+/* documentations, this register is called Preemptive Arbiter Control. */
>+/* It is likely that this register is also supported in UniChrome Pro. */
>+                Regs->SR4D = hwp->readSeq(hwp, 0x4d);
>+
>+                Regs->SR4E = hwp->readSeq(hwp, 0x4e);
>+                Regs->SR4F = hwp->readSeq(hwp, 0x4f);
>                 break;
>-        }
>+	}
>+
>+        DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Finished saving sequencer registers.\n"));
> 
>-        /* Save Preemptive Arbiter Control Register */
>-        Regs->SR4D = hwp->readSeq(hwp, 0x4D);
>-        DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Crtc...\n"));
>+        DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Saving CRTC registers.\n"));
> 
>+/* Register 0x3X5.0x13 is not listed in any of the VIA Technologies *
>+/* graphics documentations. */
>+/* If so, why is this device driver reading this register? */
>+/* Perhaps, the most likely scenario is that the device driver */
>+/* developer meant CR31, not CR13. */
>+/*
>         Regs->CR13 = hwp->readCrtc(hwp, 0x13);
>+*/
>+
>+/* UniChrome Pro or later */
>+	switch (pVia->Chipset) {
>+            case VIA_PM800:
>+            case VIA_K8M800:
>+            case VIA_P4M800PRO:
>+            case VIA_CX700:
>+            case VIA_P4M890:
>+            case VIA_K8M890:
>+            case VIA_P4M900:
>+            case VIA_VX800:
>+            case VIA_VX855:
>+            case VIA_VX900:
>+
>+/* Display Fetch Blocking Control */
>+                Regs->CR30 = hwp->readCrtc(hwp, 0x30);
>+
>+/* Half Line Position */
>+                Regs->CR31 = hwp->readCrtc(hwp, 0x31);
>+                break;
>+        }
> 
>         Regs->CR32 = hwp->readCrtc(hwp, 0x32);
>         Regs->CR33 = hwp->readCrtc(hwp, 0x33);
>-
>         Regs->CR35 = hwp->readCrtc(hwp, 0x35);
>         Regs->CR36 = hwp->readCrtc(hwp, 0x36);
> 
>-        /* Starting Address */
>-        /* Start Address High */
>-        Regs->CR0C = hwp->readCrtc(hwp, 0x0C);
>-        /* Start Address Low */
>-        Regs->CR0D = hwp->readCrtc(hwp, 0x0D);
>-        /* Starting Address Overflow Bits[28:24] */
>-        Regs->CR48 = hwp->readCrtc(hwp, 0x48);
>-        /* CR34 are fire bits. Must be written after CR0C CR0D CR48.  */
>-        /* Starting Address Overflow Bits[23:16] */
>-        Regs->CR34 = hwp->readCrtc(hwp, 0x34);
>+/* UniChrome Pro or later */
>+        switch (pVia->Chipset) {
>+            case VIA_PM800:
>+            case VIA_K8M800:
>+            case VIA_P4M800PRO:
>+            case VIA_CX700:
>+            case VIA_P4M890:
>+            case VIA_K8M890:
>+            case VIA_P4M900:
>+            case VIA_VX800:
>+            case VIA_VX855:
>+            case VIA_VX900:
> 
>-        Regs->CR49 = hwp->readCrtc(hwp, 0x49);
>+/* DAC control Register */
>+                Regs->CR37 = hwp->readCrtc(hwp, 0x37);
>+                break;
>+        }
> 
>-        DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO, "TVSave...\n"));
>-        if (pBIOSInfo->TVI2CDev)
>-            ViaTVSave(pScrn);
>+        Regs->CR38 = hwp->readCrtc(hwp, 0x38);
>+        Regs->CR39 = hwp->readCrtc(hwp, 0x39);
>+        Regs->CR3A = hwp->readCrtc(hwp, 0x3a);
>+        Regs->CR3B = hwp->readCrtc(hwp, 0x3b);
>+        Regs->CR3C = hwp->readCrtc(hwp, 0x3c);
>+        Regs->CR3D = hwp->readCrtc(hwp, 0x3d);
>+        Regs->CR3E = hwp->readCrtc(hwp, 0x3e);
>+        Regs->CR3F = hwp->readCrtc(hwp, 0x3f);
> 
>-        /* Save LCD control registers (from CR 0x50 to 0x93). */
>-        for (i = 0; i < 68; i++)
>-            Regs->CRTCRegs[i] = hwp->readCrtc(hwp, i + 0x50);
>-
>-        if (pVia->Chipset != VIA_CLE266 && pVia->Chipset != VIA_KM400) {
>-            /* LVDS Channel 2 Function Select 0 / DVI Function Select */
>-            Regs->CR97 = hwp->readCrtc(hwp, 0x97);
>-            /* LVDS Channel 1 Function Select 0 */
>-            Regs->CR99 = hwp->readCrtc(hwp, 0x99);
>-            /* Digital Video Port 1 Function Select 0 */
>-            Regs->CR9B = hwp->readCrtc(hwp, 0x9B);
>-            /* Power Now Control 4 */
>-            Regs->CR9F = hwp->readCrtc(hwp, 0x9F);
>-
>-            /* Horizontal Scaling Initial Value */
>-            Regs->CRA0 = hwp->readCrtc(hwp, 0xA0);
>-            /* Vertical Scaling Initial Value */
>-            Regs->CRA1 = hwp->readCrtc(hwp, 0xA1);
>-            /* Scaling Enable Bit */
>-            Regs->CRA2 = hwp->readCrtc(hwp, 0xA2);
>+        Regs->CR40 = hwp->readCrtc(hwp, 0x40);
>+
>+/* UniChrome Pro or later */
>+        switch (pVia->Chipset) {
>+            case VIA_PM800:
>+            case VIA_K8M800:
>+            case VIA_P4M800PRO:
>+            case VIA_CX700:
>+            case VIA_P4M890:
>+            case VIA_K8M890:
>+            case VIA_P4M900:
>+            case VIA_VX800:
>+            case VIA_VX855:
>+            case VIA_VX900:
>+
>+                Regs->CR43 = hwp->readCrtc(hwp, 0x43);
>+                Regs->CR45 = hwp->readCrtc(hwp, 0x45);
>+                break;
>         }
> 
>-        /* Save TMDS status */
>+        Regs->CR46 = hwp->readCrtc(hwp, 0x46);
>+        Regs->CR47 = hwp->readCrtc(hwp, 0x47);
>+
>+/* Starting Address */
>+/* Start Address High */
>+        Regs->CR0C = hwp->readCrtc(hwp, 0x0c);
>+/* Start Address Low */
>+        Regs->CR0D = hwp->readCrtc(hwp, 0x0d);
>+
>+/* UniChrome Pro or later */
>+        switch (pVia->Chipset) {
>+            case VIA_PM800:
>+            case VIA_K8M800:
>+            case VIA_P4M800PRO:
>+            case VIA_CX700:
>+            case VIA_P4M890:
>+            case VIA_K8M890:
>+            case VIA_P4M900:
>+            case VIA_VX800:
>+            case VIA_VX855:
>+            case VIA_VX900:
>+
>+/* Starting Address Overflow[28:24] */
>+                Regs->CR48 = hwp->readCrtc(hwp, 0x48);
>+                break;
>+        }
>+
>+/* Starting Address Overflow[23:16] */
>+        Regs->CR34 = hwp->readCrtc(hwp, 0x34);
>+
>+/* Register 0x3X5.0x49 is not listed in any of the VIA Technologies *
>+/* graphics documentations. */
>+/* The line will be commented out. */
>+/*
>+        Regs->CR49 = hwp->readCrtc(hwp, 0x49);
>+*/
>+
>+        DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Finished saving CRTC registers.\n"));
>+
>+/* UniChrome Pro or later */
>         switch (pVia->Chipset) {
>+            case VIA_PM800:
>+            case VIA_K8M800:
>+            case VIA_P4M800PRO:
>             case VIA_CX700:
>+            case VIA_P4M890:
>+            case VIA_K8M890:
>+            case VIA_P4M900:
>             case VIA_VX800:
>             case VIA_VX855:
>             case VIA_VX900:
>-                Regs->CRD2 = hwp->readCrtc(hwp, 0xD2);
>+
>+                DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Saving extended CRTC registers.\n"));
>+
>+                for (i = 0; i < (0x88 - 0x50 + 1); i++) {
>+                    Regs->EXCR[i + (0x50 - 0x50)] = hwp->readCrtc(hwp, i + 0x50);
>+
>+                }
>+
>+                for (i = 0; i < (0x92 - 0x8a + 1); i++) {
>+                    Regs->EXCR[i + (0x8a - 0x50)] = hwp->readCrtc(hwp, i + 0x8a);
>+
>+                }
>+
>+                for (i = 0; i < (0xa3 - 0x94 + 1); i++) {
>+                    Regs->EXCR[i + (0x94 - 0x50)] = hwp->readCrtc(hwp, i + 0x94);
>+
>+                }
>+
>+/* UniChrome Pro and UniChrome Pro II */
>+                switch (pVia->Chipset) {
>+                    case VIA_PM800:
>+                    case VIA_K8M800:
>+                    case VIA_P4M800PRO:
>+                    case VIA_CX700:
>+                    case VIA_P4M890:
>+
>+                        Regs->EXCR[0xa4 - 0x50] = hwp->readCrtc(hwp, 0xa4);
>+                        break;
>+                }
>+
>+                for (i = 0; i < (0xac - 0xa5 + 1); i++) {
>+                    Regs->EXCR[i + (0xa5 - 0x50)] = hwp->readCrtc(hwp, i + 0xa5);
>+
>+                }
>+
>+/* Chrome 9 */
>+                switch (pVia->Chipset) {
>+                    case VIA_K8M890:
>+                    case VIA_P4M900:
>+                    case VIA_VX800:
>+                    case VIA_VX855:
>+                    case VIA_VX900:
>+
>+                        Regs->EXCR[0xaf - 0x50] = hwp->readCrtc(hwp, 0xaf);
>+                        break;
>+                }
>+
>+/* Chrome 9, Chrome 9 HC, and Chrome 9 HC3 */
>+                switch (pVia->Chipset) {
>+                    case VIA_K8M890:
>+                    case VIA_P4M900:
>+                    case VIA_VX800:
>+
>+                        for (i = 0; i < (0xcd - 0xb0 + 1); i++) {
>+                            Regs->EXCR[i + (0xb0 - 0x50)] = hwp->readCrtc(hwp, i + 0xb0);
>+
>+                        }
>+
>+                        break;
>+                }
>+
>+                switch (pVia->Chipset) {
>+
>+/* UniChrome Pro and UniChrome Pro II */
>+                    case VIA_PM800:
>+                    case VIA_K8M800:
>+                    case VIA_P4M800PRO:
>+                    case VIA_CX700:
>+                    case VIA_P4M890:
>+
>+                        for (i = 0; i < (0xd7 - 0xd0 + 1); i++) {
>+                            Regs->EXCR[i + (0xd0 - 0x50)] = hwp->readCrtc(hwp, i + 0xd0);
>+
>+                        }
>+
>+                        break;
>+
>+/* Chrome 9 */
>+                    case VIA_K8M890:
>+                    case VIA_P4M900:
>+                    case VIA_VX800:
>+                    case VIA_VX855:
>+                    case VIA_VX900:
>+
>+                        for (i = 0; i < (0xec - 0xd0 + 1); i++) {
>+                        Regs->EXCR[i + (0xd0 - 0x50)] = hwp->readCrtc(hwp, i + 0xd0);
>+
>+                        }
>+
>+                        break;
>+                }
>+
>+/* Chrome 9 */
>+                switch (pVia->Chipset) {
>+                    case VIA_K8M890:
>+                    case VIA_P4M900:
>+                    case VIA_VX800:
>+                    case VIA_VX855:
>+                    case VIA_VX900:
>+
>+                        for (i = 0; i < (0xf5 - 0xf0 + 1); i++) {
>+                            Regs->EXCR[i + (0xf0 - 0x50)] = hwp->readCrtc(hwp, i + 0xf0);
>+
>+                        }
>+
>+                        break;
>+                }
>+
>+/* Chrome 9 HCM and Chrome 9 HD */
>+                if ((pVia->Chipset == VIA_VX855) || (pVia->Chipset == VIA_VX900)) {
>+                    for (i = 0; i < (0xfc - 0xf6 + 1); i++) {
>+                        Regs->EXCR[i + (0xf6 - 0x50)] = hwp->readCrtc(hwp, i + 0xf6);
>+
>+                    }
>+                }
>+
>+/* Chrome 9 HD */
>+                if (pVia->Chipset == VIA_VX900) {
>+                    Regs->EXCR[0xfd - 0x50] = hwp->readCrtc(hwp, 0xfd);
>+
>+                }
>+
>+                DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Finished saving extended CRTC registers.\n"));
>                 break;
>         }
>+
>+        if (pBIOSInfo->TVI2CDev) {
>+            DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Saving TV registers.\n"));
>+            ViaTVSave(pScrn);
>+            DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Finished saving TV registers.\n"));
>+
>+        }
>+
>+#ifdef DEBUG
>+        ViaVgahwPrint(hwp);
>+
>+#endif
>+
>         vgaHWProtect(pScrn, FALSE);
>+
>+        DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Exiting VIASave.\n"));
>+
>     }
> }
> 
>-void
>-VIARestore(ScrnInfoPtr pScrn)
>+void VIARestore(ScrnInfoPtr pScrn)
> {
>     vgaHWPtr hwp = VGAHWPTR(pScrn);
>     VIAPtr pVia = VIAPTR(pScrn);
>@@ -296,10 +568,9 @@ VIARestore(ScrnInfoPtr pScrn)
>     int i;
>     CARD8 tmp;
> 
>-    DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO, "VIARestore\n"));
>+    DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Entered VIARestore.\n"));
> 
>     /* Secondary? */
>-
>     vgaHWProtect(pScrn, TRUE);
> 
>     /* Unlock extended registers. */
>@@ -321,145 +592,474 @@ VIARestore(ScrnInfoPtr pScrn)
>     if (xf86IsPrimaryPci(pVia->PciInfo))
>         vgaHWRestore(pScrn, &hwp->SavedReg, VGA_SR_ALL);
>     else
>-        vgaHWRestore(pScrn, &hwp->SavedReg, VGA_SR_MODE);
>+        VgaHWRestore(pScrn, &hwp->SavedReg, VGA_SR_MODE);
> 
>-    /* Restore extended registers. */
>+    DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Restoring sequencer registers.\n"));
>+
>+/* Restore extended registers. */
>     hwp->writeSeq(hwp, 0x14, Regs->SR14);
>     hwp->writeSeq(hwp, 0x15, Regs->SR15);
>     hwp->writeSeq(hwp, 0x16, Regs->SR16);
>     hwp->writeSeq(hwp, 0x17, Regs->SR17);
>     hwp->writeSeq(hwp, 0x18, Regs->SR18);
>     hwp->writeSeq(hwp, 0x19, Regs->SR19);
>-    hwp->writeSeq(hwp, 0x1A, Regs->SR1A);
>-    hwp->writeSeq(hwp, 0x1B, Regs->SR1B);
>-    hwp->writeSeq(hwp, 0x1C, Regs->SR1C);
>-    hwp->writeSeq(hwp, 0x1D, Regs->SR1D);
>-    hwp->writeSeq(hwp, 0x1E, Regs->SR1E);
>-    hwp->writeSeq(hwp, 0x1F, Regs->SR1F);
>+
>+/* PCI Bus Control */
>+    hwp->writeSeq(hwp, 0x1a, Regs->SR1A);
>+
>+    hwp->writeSeq(hwp, 0x1b, Regs->SR1B);
>+    hwp->writeSeq(hwp, 0x1c, Regs->SR1C);
>+    hwp->writeSeq(hwp, 0x1d, Regs->SR1D);
>+    hwp->writeSeq(hwp, 0x1e, Regs->SR1E);
>+    hwp->writeSeq(hwp, 0x1f, Regs->SR1F);
> 
>     hwp->writeSeq(hwp, 0x22, Regs->SR22);
>-    hwp->writeSeq(hwp, 0x23, Regs->SR23);
>-    hwp->writeSeq(hwp, 0x24, Regs->SR24);
>-    hwp->writeSeq(hwp, 0x25, Regs->SR25);
>-    hwp->writeSeq(hwp, 0x26, Regs->SR26);
>-    hwp->writeSeq(hwp, 0x27, Regs->SR27);
>-    hwp->writeSeq(hwp, 0x28, Regs->SR28);
>-    hwp->writeSeq(hwp, 0x29, Regs->SR29);
>-    hwp->writeSeq(hwp, 0x2A, Regs->SR2A);
>-    hwp->writeSeq(hwp, 0x2B, Regs->SR2B);
> 
>-    hwp->writeSeq(hwp, 0x2E, Regs->SR2E);
>+/* Registers 0x3c5.0x23 through 0x3c5.0x25 are not used by */
>+/* Chrome 9. */
>+/* Registers 0x3c5.0x27 through 0x3c5.0x29 are not used by */
>+/* Chrome 9. */
>+    switch (pVia->Chipset) {
>+        case VIA_CLE266:
>+        case VIA_KM400:
>+        case VIA_PM800:
>+        case VIA_K8M800:
>+        case VIA_P4M800PRO:
>+        case VIA_CX700:
>+        case VIA_P4M890:
>+
>+            hwp->writeSeq(hwp, 0x23, Regs->SR23);
>+            hwp->writeSeq(hwp, 0x24, Regs->SR24);
>+            hwp->writeSeq(hwp, 0x25, Regs->SR25);
> 
>-    /*=* restore VCK, LCDCK and ECK *=*/
>-    /* Primary Display (VCK): */
>-    hwp->writeSeq(hwp, 0x44, Regs->SR44);
>-    hwp->writeSeq(hwp, 0x45, Regs->SR45);
>-    hwp->writeSeq(hwp, 0x46, Regs->SR46);
>+            hwp->writeSeq(hwp, 0x27, Regs->SR27);
>+            hwp->writeSeq(hwp, 0x28, Regs->SR28);
>+            hwp->writeSeq(hwp, 0x29, Regs->SR29);
>+            break;
>+    }
> 
>-    /* Reset VCK PLL */
>-    hwp->writeSeq(hwp, 0x40, hwp->readSeq(hwp, 0x40) | 0x02); /* Set SR40[1] to 1 */
>-    hwp->writeSeq(hwp, 0x40, hwp->readSeq(hwp, 0x40) & 0xFD); /* Set SR40[1] to 0 */
>+    hwp->writeSeq(hwp, 0x26, Regs->SR26);
> 
>-    /* ECK Clock Synthesizer: */
>-    hwp->writeSeq(hwp, 0x47, Regs->SR47);
>-    hwp->writeSeq(hwp, 0x48, Regs->SR48);
>-    hwp->writeSeq(hwp, 0x49, Regs->SR49);
>+    hwp->writeSeq(hwp, 0x2a, Regs->SR2A);
>+    hwp->writeSeq(hwp, 0x2b, Regs->SR2B);
> 
>-    /* Reset ECK PLL */
>-    hwp->writeSeq(hwp, 0x40, hwp->readSeq(hwp, 0x40) | 0x01); /* Set SR40[0] to 1 */
>-    hwp->writeSeq(hwp, 0x40, hwp->readSeq(hwp, 0x40) & 0xFE); /* Set SR40[0] to 0 */
>+/* Restoring the content of register 0x3c5.0x2d was missing */
>+/* from the code obtained around July 2015. */
>+    hwp->writeSeq(hwp, 0x2d, Regs->SR2D);
>+    hwp->writeSeq(hwp, 0x2e, Regs->SR2E);
> 
>+/* Restore PCI Configuration Memory Base Shadow 0 and 1. */
>+/* These registers are available only in UniChrome, UniChrome Pro, */
>+/* and UniChrome Pro II. */
>     switch (pVia->Chipset) {
>         case VIA_CLE266:
>         case VIA_KM400:
>+        case VIA_PM800:
>+        case VIA_K8M800:
>+        case VIA_P4M800PRO:
>+        case VIA_CX700:
>+        case VIA_P4M890:
>+
>+            hwp->writeSeq(hwp, 0x2f, Regs->SR2F);
>+            hwp->writeSeq(hwp, 0x30, Regs->SR30);
>             break;
>+    }
>+
>+/* Restore PLL settings and several miscellaneous registers. */
>+/* For UniChrome, register 0x3c5.0x44 through 0x4b are restored. */
>+/* For UniChrome Pro and Chrome 9, register 0x3c5.0x44 */
>+/* through 0x4c are restored. */
>+    switch (pVia->Chipset) {
>+        case VIA_CLE266:
>+        case VIA_KM400:
>+
>+/* Engine Clock (ECK) PLL settings */
>+            hwp->writeSeq(hwp, 0x48, Regs->SR48);
>+            hwp->writeSeq(hwp, 0x49, Regs->SR49);
>+
>+/* Memory Clock (MCK) PLL settings */
>+            hwp->writeSeq(hwp, 0x4a, Regs->SR4A);
>+            hwp->writeSeq(hwp, 0x4b, Regs->SR4B);
>+
>+/* Primary Display Clock (VCK) PLL settings */
>+            hwp->writeSeq(hwp, 0x46, Regs->SR46);
>+            hwp->writeSeq(hwp, 0x47, Regs->SR47);
>+
>+/* Secondary Display Clock (LCDCK) PLL settings */
>+            hwp->writeSeq(hwp, 0x44, Regs->SR44);
>+            hwp->writeSeq(hwp, 0x45, Regs->SR45);
>+            break;
>+
>         default:
>-            /* Secondary Display (LCDCK): */
>-            hwp->writeSeq(hwp, 0x4A, Regs->SR4A);
>-            hwp->writeSeq(hwp, 0x4B, Regs->SR4B);
>-            hwp->writeSeq(hwp, 0x4C, Regs->SR4C);
> 
>-            /* Reset LCK PLL */
>+/* Engine Clock (ECK) PLL settings */
>+            hwp->writeSeq(hwp, 0x47, Regs->SR47);
>+            hwp->writeSeq(hwp, 0x48, Regs->SR48);
>+            hwp->writeSeq(hwp, 0x49, Regs->SR49);
>+
>+/* Reset ECK PLL. */
>+            hwp->writeSeq(hwp, 0x40, hwp->readSeq(hwp, 0x40) | 0x01); /* Set SR40[0] to 1 */
>+            hwp->writeSeq(hwp, 0x40, hwp->readSeq(hwp, 0x40) & (~0x01)); /* Set SR40[0] to 0 */
>+
>+
>+/* Primary Display Clock (VCK) PLL settings */
>+            hwp->writeSeq(hwp, 0x44, Regs->SR44);
>+            hwp->writeSeq(hwp, 0x45, Regs->SR45);
>+            hwp->writeSeq(hwp, 0x46, Regs->SR46);
>+
>+/* Reset VCK PLL. */
>+            hwp->writeSeq(hwp, 0x40, hwp->readSeq(hwp, 0x40) | 0x02); /* Set SR40[1] to 1 */
>+            hwp->writeSeq(hwp, 0x40, hwp->readSeq(hwp, 0x40) & (~0x02)); /* Set SR40[1] to 0 */
>+
>+
>+/* Secondary Display Clock (LCDCK) PLL settings */
>+            hwp->writeSeq(hwp, 0x4a, Regs->SR4A);
>+            hwp->writeSeq(hwp, 0x4b, Regs->SR4B);
>+            hwp->writeSeq(hwp, 0x4c, Regs->SR4C);
>+
>+/* Reset LCDCK PLL. */
>             hwp->writeSeq(hwp, 0x40, hwp->readSeq(hwp, 0x40) | 0x04); /* Set SR40[2] to 1 */
>-            hwp->writeSeq(hwp, 0x40, hwp->readSeq(hwp, 0x40) & 0xFB); /* Set SR40[2] to 0 */
>+            hwp->writeSeq(hwp, 0x40, hwp->readSeq(hwp, 0x40) & (~0x04)); /* Set SR40[2] to 0 */
>             break;
>     }
> 
>-    /* Restore Preemptive Arbiter Control Register
>-     * VX800 and VX855 should restore this register too,
>-     * but I don't do that for I don't want to affect any
>-     * chips now.
>-     */
>-    if (pVia->Chipset == VIA_VX900) {
>-        hwp->writeSeq(hwp, 0x4D, Regs->SR4D);
>+    switch (pVia->Chipset) {
>+        case VIA_PM800:
>+        case VIA_K8M800:
>+        case VIA_P4M800PRO:
>+        case VIA_CX700:
>+        case VIA_P4M890:
>+        case VIA_K8M890:
>+        case VIA_P4M900:
>+        case VIA_VX800:
>+        case VIA_VX855:
>+        case VIA_VX900:
>+
>+/* Restore register 0x3c5.0x4d. */
>+/* According to CX700 (UniChrome Pro II) documentation, this register */
>+/* is called Dual Channel Memory Control. */
>+/* According to VX800 / VX855 / VX900 (Chrome 9 HC3 / HCM / HD) */
>+/* documentations, this register is called Preemptive Arbiter Control. */
>+/* It is likely that this register is also supported in UniChrome Pro. */
>+            hwp->writeSeq(hwp, 0x4d, Regs->SR4D);
>+
>+            hwp->writeSeq(hwp, 0x4e, Regs->SR4E);
>+            hwp->writeSeq(hwp, 0x4f, Regs->SR4F);
>+            break;
>     }
> 
>-    /* Reset dotclocks. */
>+    DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Finished restoring sequencer registers.\n"));
>+
>+/* Reset dot clocks. */
>     ViaSeqMask(hwp, 0x40, 0x06, 0x06);
>     ViaSeqMask(hwp, 0x40, 0x00, 0x06);
> 
>-    /* Integrated LVDS Mode Select */
>+    DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Restoring CRTC registers.\n"));
>+
>+/* Register 0x3X5.0x13 is not listed in any of the VIA Technologies */
>+/* graphics documentations. */
>+/* If so, why is the device driver writing into this register? */
>+/* Perhaps, the most likely scenario is that the device driver */
>+/* developer meant CR31, not CR13. */
>+/*
>     hwp->writeCrtc(hwp, 0x13, Regs->CR13);
>+*/
> 
>-    /*=* Restore CRTC controller extended regs: *=*/
>-    /* Mode Control */
>+/* UniChrome Pro or later */
>+    switch (pVia->Chipset) {
>+        case VIA_PM800:
>+        case VIA_K8M800:
>+        case VIA_P4M800PRO:
>+        case VIA_CX700:
>+        case VIA_P4M890:
>+        case VIA_K8M890:
>+        case VIA_P4M900:
>+        case VIA_VX800:
>+        case VIA_VX855:
>+        case VIA_VX900:
>+
>+/* Display Fetch Blocking Control */
>+            hwp->writeCrtc(hwp, 0x30, Regs->CR30);
>+
>+/* Half Line Position */
>+            hwp->writeCrtc(hwp, 0x31, Regs->CR31);
>+            break;
>+    }
>+
>+/* Restore CRTC controller extended registers. */
>+/* Mode Control */
>     hwp->writeCrtc(hwp, 0x32, Regs->CR32);
>-    /* HSYNCH Adjuster */
>+/* HSYNCH Adjuster */
>     hwp->writeCrtc(hwp, 0x33, Regs->CR33);
>-    /* Extended Overflow */
>+/* Extended Overflow */
>     hwp->writeCrtc(hwp, 0x35, Regs->CR35);
>-    /*Power Management 3 (Monitor Control) */
>+/* Power Management 3 (Monitor Control) */
>     hwp->writeCrtc(hwp, 0x36, Regs->CR36);
> 
>-    /* Starting Address */
>-    /* Start Address High */
>-    hwp->writeCrtc(hwp, 0x0C, Regs->CR0C);
>-    /* Start Address Low */
>-    hwp->writeCrtc(hwp, 0x0D, Regs->CR0D);
>-    /* Starting Address Overflow Bits[28:24] */
>-    hwp->writeCrtc(hwp, 0x48, Regs->CR48);
>-    /* CR34 are fire bits. Must be written after CR0C CR0D CR48.  */
>-    /* Starting Address Overflow Bits[23:16] */
>+/* UniChrome Pro or later */
>+    switch (pVia->Chipset) {
>+        case VIA_PM800:
>+        case VIA_K8M800:
>+        case VIA_P4M800PRO:
>+        case VIA_CX700:
>+        case VIA_P4M890:
>+        case VIA_K8M890:
>+        case VIA_P4M900:
>+        case VIA_VX800:
>+        case VIA_VX855:
>+        case VIA_VX900:
>+
>+/* DAC control Register */
>+            hwp->writeCrtc(hwp, 0x37, Regs->CR37);
>+
>+            break;
>+    }
>+
>+    hwp->writeCrtc(hwp, 0x38, Regs->CR38);
>+    hwp->writeCrtc(hwp, 0x39, Regs->CR39);
>+    hwp->writeCrtc(hwp, 0x3a, Regs->CR3A);
>+    hwp->writeCrtc(hwp, 0x3b, Regs->CR3B);
>+    hwp->writeCrtc(hwp, 0x3c, Regs->CR3C);
>+    hwp->writeCrtc(hwp, 0x3d, Regs->CR3D);
>+    hwp->writeCrtc(hwp, 0x3e, Regs->CR3E);
>+    hwp->writeCrtc(hwp, 0x3f, Regs->CR3F);
>+
>+    hwp->writeCrtc(hwp, 0x40, Regs->CR40);
>+
>+/* UniChrome Pro or later */
>+    switch (pVia->Chipset) {
>+        case VIA_PM800:
>+        case VIA_K8M800:
>+        case VIA_P4M800PRO:
>+        case VIA_CX700:
>+        case VIA_P4M890:
>+        case VIA_K8M890:
>+        case VIA_P4M900:
>+        case VIA_VX800:
>+        case VIA_VX855:
>+        case VIA_VX900:
>+
>+            hwp->writeCrtc(hwp, 0x43, Regs->CR43);
>+            hwp->writeCrtc(hwp, 0x45, Regs->CR45);
>+            break;
>+    }
>+
>+    hwp->writeCrtc(hwp, 0x46, Regs->CR46);
>+    hwp->writeCrtc(hwp, 0x47, Regs->CR47);
>+
>+/* Starting Address */
>+/* Start Address High */
>+    hwp->writeCrtc(hwp, 0x0c, Regs->CR0C);
>+/* Start Address Low */
>+    hwp->writeCrtc(hwp, 0x0d, Regs->CR0D);
>+
>+/* UniChrome Pro or later */
>+    switch (pVia->Chipset) {
>+        case VIA_PM800:
>+        case VIA_K8M800:
>+        case VIA_P4M800PRO:
>+        case VIA_CX700:
>+        case VIA_P4M890:
>+        case VIA_K8M890:
>+        case VIA_P4M900:
>+        case VIA_VX800:
>+        case VIA_VX855:
>+        case VIA_VX900:
>+
>+/* Starting Address Overflow[28:24] */
>+            hwp->writeCrtc(hwp, 0x48, Regs->CR48);
>+            break;
>+    }
>+
>+/* CR34 are fire bits. Must be written after CR0C CR0D CR48. */
>+/* Starting Address Overflow[23:16] */
>     hwp->writeCrtc(hwp, 0x34, Regs->CR34);
>+
>+/* Register 0x3X5.0x49 is not listed in any of the VIA Technologies *
>+/* graphics documentations. */
>+/* The line will be commented out. */
>+/*
>     hwp->writeCrtc(hwp, 0x49, Regs->CR49);
>+*/
> 
>-    /* Restore LCD control registers. */
>-    for (i = 0; i < 68; i++)
>-        hwp->writeCrtc(hwp, i + 0x50, Regs->CRTCRegs[i]);
>-
>-    if (pVia->Chipset != VIA_CLE266 && pVia->Chipset != VIA_KM400) {
>-        /* Scaling Initial values */
>-        hwp->writeCrtc(hwp, 0xA0, Regs->CRA0);
>-        hwp->writeCrtc(hwp, 0xA1, Regs->CRA1);
>-        hwp->writeCrtc(hwp, 0xA2, Regs->CRA2);
>-
>-        /* LVDS Channels Functions Selection */
>-        hwp->writeCrtc(hwp, 0x97, Regs->CR97);
>-        hwp->writeCrtc(hwp, 0x99, Regs->CR99);
>-        hwp->writeCrtc(hwp, 0x9B, Regs->CR9B);
>-        hwp->writeCrtc(hwp, 0x9F, Regs->CR9F);
>-    }
>+    DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Finished restoring CRTC registers.\n"));
> 
>-    /* Restore TMDS status */
>+    DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Restoring extended CRTC registers.\n"));
>+
>+/* UniChrome Pro or later */
>     switch (pVia->Chipset) {
>+        case VIA_PM800:
>+        case VIA_K8M800:
>+        case VIA_P4M800PRO:
>         case VIA_CX700:
>+        case VIA_P4M890:
>+        case VIA_K8M890:
>+        case VIA_P4M900:
>         case VIA_VX800:
>         case VIA_VX855:
>         case VIA_VX900:
>-            /* LVDS Control Register */
>-            hwp->writeCrtc(hwp, 0xD2, Regs->CRD2);
>+
>+            for (i = 0; i < (0x5f - 0x50 + 1); i++) {
>+                hwp->writeCrtc(hwp, i + 0x50, Regs->EXCR[i + (0x50 - 0x50)]);
>+
>+            }
>+
>+/*
>+            for (i = 0; i < (0x88 - 0x62 + 1); i++) {
>+                hwp->writeCrtc(hwp, i + 0x62, Regs->EXCR[i + (0x62 - 0x50)]);
>+
>+            }
>+*/
>+
>+            for (i = 0; i < (0x69 - 0x62 + 1); i++) {
>+                hwp->writeCrtc(hwp, i + 0x62, Regs->EXCR[i + (0x62 - 0x50)]);
>+
>+            }
>+
>+            for (i = 0; i < (0x88 - 0x6d + 1); i++) {
>+                hwp->writeCrtc(hwp, i + 0x6d, Regs->EXCR[i + (0x6d - 0x50)]);
>+
>+            }
>+
>+            for (i = 0; i < (0x92 - 0x8a + 1); i++) {
>+                hwp->writeCrtc(hwp, i + 0x8a, Regs->EXCR[i + (0x8a - 0x50)]);
>+
>+            }
>+
>+            for (i = 0; i < (0xa3 - 0x94 + 1); i++) {
>+                hwp->writeCrtc(hwp, i + 0x94, Regs->EXCR[i + (0x94 - 0x50)]);
>+
>+            }
>+
>+/* UniChrome Pro and UniChrome Pro II */
>+            switch (pVia->Chipset) {
>+                case VIA_PM800:
>+                case VIA_K8M800:
>+                case VIA_P4M800PRO:
>+                case VIA_CX700:
>+                case VIA_P4M890:
>+
>+                    hwp->writeCrtc(hwp, 0xa4, Regs->EXCR[0xa4 - 0x50]);
>+                    break;
>+            }
>+
>+            for (i = 0; i < (0xac - 0xa5 + 1); i++) {
>+                hwp->writeCrtc(hwp, i + 0xa5, Regs->EXCR[i + (0xa5 - 0x50)]);
>+
>+            }
>+
>+/* Chrome 9 */
>+            switch (pVia->Chipset) {
>+                case VIA_K8M890:
>+                case VIA_P4M900:
>+                case VIA_VX800:
>+                case VIA_VX855:
>+                case VIA_VX900:
>+
>+                    hwp->writeCrtc(hwp, 0xaf, Regs->EXCR[0xaf - 0x50]);
>+                    break;
>+            }
>+
>+/* Chrome 9, Chrome 9 HC, and Chrome 9 HC3 */
>+            switch (pVia->Chipset) {
>+                case VIA_K8M890:
>+                case VIA_P4M900:
>+                case VIA_VX800:
>+
>+                    for (i = 0; i < (0xcd - 0xb0 + 1); i++) {
>+                        hwp->writeCrtc(hwp, i + 0xb0, Regs->EXCR[i + (0xb0 - 0x50)]);
>+
>+                    }
>+
>+                    break;
>+            }
>+
>+            switch (pVia->Chipset) {
>+
>+/* UniChrome Pro and UniChrome Pro II */
>+                case VIA_PM800:
>+                case VIA_K8M800:
>+                case VIA_P4M800PRO:
>+                case VIA_CX700:
>+                case VIA_P4M890:
>+
>+                    for (i = 0; i < (0xd7 - 0xd0 + 1); i++) {
>+                        hwp->writeCrtc(hwp, i + 0xd0, Regs->EXCR[i + (0xd0 - 0x50)]);
>+
>+                    }
>+
>+                    break;
>+
>+/* Chrome 9 */
>+                case VIA_K8M890:
>+                case VIA_P4M900:
>+                case VIA_VX800:
>+                case VIA_VX855:
>+                case VIA_VX900:
>+
>+                    for (i = 0; i < (0xec - 0xd0 + 1); i++) {
>+                        hwp->writeCrtc(hwp, i + 0xd0, Regs->EXCR[i + (0xd0 - 0x50)]);
>+
>+                    }
>+
>+                    break;
>+            }
>+
>+/* Chrome 9 */
>+            switch (pVia->Chipset) {
>+                case VIA_K8M890:
>+                case VIA_P4M900:
>+                case VIA_VX800:
>+                case VIA_VX855:
>+                case VIA_VX900:
>+
>+                    for (i = 0; i < (0xf5 - 0xf0 + 1); i++) {
>+                        hwp->writeCrtc(hwp, i + 0xf0, Regs->EXCR[i + (0xf0 - 0x50)]);
>+
>+                    }
>+
>+                    break;
>+            }
>+
>+/* Chrome 9 HCM and Chrome 9 HD */
>+            if ((pVia->Chipset == VIA_VX855) || (pVia->Chipset == VIA_VX900)) {
>+                for (i = 0; i < (0xfc - 0xf6 + 1); i++) {
>+                    hwp->writeCrtc(hwp, i + 0xf6, Regs->EXCR[i + (0xf6 - 0x50)]);
>+
>+                }
>+            }
>+
>+/* Chrome 9 HD */
>+            if (pVia->Chipset == VIA_VX900) {
>+                hwp->writeCrtc(hwp, 0xfd, Regs->EXCR[0xfd - 0x50]);
>+
>+            }
>+
>             break;
>+
>     }
> 
>+    DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Finished restoring extended CRTC registers.\n"));
>+
>+#ifdef DEBUG
>+    ViaVgahwPrint(hwp);
>+
>+#endif
>+
>+
>     ViaDisablePrimaryFIFO(pScrn);
> 
>-    /* Reset clock. */
>+/* Reset clock. */
>     tmp = hwp->readMiscOut(hwp);
>     hwp->writeMiscOut(hwp, tmp);
> 
>     vgaHWProtect(pScrn, FALSE);
>+
>+    DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Exiting VIARestore.\n"));
>+
> }
> 
>+
> #ifdef HAVE_DEBUG
> void
> ViaVgahwPrint(vgaHWPtr hwp)
>-- 
>1.7.9.5
>

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Attachments on bug 92957: 119669 | 120322

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