Attachment 120391 Details for Bug 87579 – /var/log/dmesg-hsw

/var/log/dmesg-hsw

dmesg (text/plain), 1008.11 KB, created by Marius Vlad on 2015-12-07 16:12:53 UTC

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Description:

Filename:

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Creator: Marius Vlad

Created: 2015-12-07 16:12:53 UTC

Size: 1008.11 KB

patch

obsolete

>[  504.387776] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8800c78d4300 state to ffff880026bfa000
>[  504.387777] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff880025a41000
>[  504.387778] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800c78d4300 to [NOCRTC]
>[  504.387779] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8800c78d4300
>[  504.387780] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfa000
>[  504.387781] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8801f442d700 state to ffff880026bfa000
>[  504.387782] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f442d700 to [NOCRTC]
>[  504.387783] [drm:drm_atomic_check_only] checking ffff880026bfa000
>[  504.387784] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  504.387785] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  504.387786] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  504.387787] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  504.387788] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  504.387789] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  504.387790] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfa000
>[  504.387791] [drm:drm_atomic_connectors_for_crtc] State ffff880026bfa000 has 0 connectors for [CRTC:25]
>[  504.387794] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  504.387795] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  504.387797] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8800c78d4b40 state to ffff880026bfa000
>[  504.387798] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8800c78d40c0 state to ffff880026bfa000
>[  504.387800] [drm:drm_atomic_commit] commiting ffff880026bfa000
>[  504.404377] [drm:intel_disable_pipe] disabling pipe B
>[  504.438696] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  504.438699] [drm:intel_disable_shared_dpll] disabling SPLL
>[  504.438707] [drm:intel_power_well_disable] disabling display
>[  504.438709] [drm:hsw_set_power_well] Requesting to disable the power well
>[  504.438710] [drm:intel_power_well_disable] disabling always-on
>[  504.438711] [drm:intel_power_well_enable] enabling display
>[  504.438712] [drm:hsw_set_power_well] Enabling power well
>[  504.440782] [drm:intel_power_well_disable] disabling display
>[  504.440786] [drm:hsw_set_power_well] Requesting to disable the power well
>[  504.440791] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  504.440793] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  504.440794] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  504.440797] [drm:check_crtc_state] [CRTC:25]
>[  504.440799] [drm:check_shared_dpll_state] WRPLL 1
>[  504.440800] [drm:check_shared_dpll_state] WRPLL 2
>[  504.440801] [drm:check_shared_dpll_state] SPLL
>[  504.440803] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bfa000
>[  504.440805] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bfa000
>[  504.440833] [drm:drm_mode_setcrtc] [CRTC:25]
>[  504.440837] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  504.440839] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bf2400
>[  504.440841] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880215be5c00 state to ffff880026bf2400
>[  504.440842] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8800d6c35780 state to ffff880026bf2400
>[  504.440843] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff880215be5c00
>[  504.440844] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800d6c35780 to [CRTC:25]
>[  504.440845] [drm:drm_atomic_set_fb_for_plane] Set [FB:49] for plane state ffff8800d6c35780
>[  504.440847] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c0132860 state to ffff880026bf2400
>[  504.440848] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf2400
>[  504.440849] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c0132860 to [CRTC:25]
>[  504.440850] [drm:drm_atomic_check_only] checking ffff880026bf2400
>[  504.440851] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  504.440852] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  504.440854] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  504.440855] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  504.440856] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  504.440857] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  504.440858] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf2400
>[  504.440859] [drm:drm_atomic_connectors_for_crtc] State ffff880026bf2400 has 1 connectors for [CRTC:25]
>[  504.440860] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf2400
>[  504.440862] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  504.440863] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  504.440864] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  504.440865] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  504.440866] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff880215be5c00 for pipe B
>[  504.440867] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  504.440868] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  504.440869] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  504.440870] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  504.440871] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  504.440872] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  504.440873] [drm:intel_dump_pipe_config] requested mode:
>[  504.440874] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  504.440875] [drm:intel_dump_pipe_config] adjusted mode:
>[  504.440876] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  504.440878] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  504.440878] [drm:intel_dump_pipe_config] port clock: 270000
>[  504.440879] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  504.440880] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  504.440881] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  504.440882] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  504.440883] [drm:intel_dump_pipe_config] ips: 0
>[  504.440883] [drm:intel_dump_pipe_config] double wide: 0
>[  504.440884] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  504.440885] [drm:intel_dump_pipe_config] planes on this crtc
>[  504.440886] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  504.440887] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  504.440888] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  504.440890] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff880215be4400 state to ffff880026bf2400
>[  504.440891] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff880215be4800 state to ffff880026bf2400
>[  504.440893] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 49
>[  504.440894] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  504.440896] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8800d6c35a80 state to ffff880026bf2400
>[  504.440897] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8800d6c35540 state to ffff880026bf2400
>[  504.440899] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8800d6c35180 state to ffff880026bf2400
>[  504.440901] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8800d6c35000 state to ffff880026bf2400
>[  504.440902] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8800d6c35e40 state to ffff880026bf2400
>[  504.440904] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8800d6c35d80 state to ffff880026bf2400
>[  504.440905] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8800d6c356c0 state to ffff880026bf2400
>[  504.440906] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8800d6c35480 state to ffff880026bf2400
>[  504.440907] [drm:drm_atomic_commit] commiting ffff880026bf2400
>[  504.440912] [drm:intel_power_well_enable] enabling display
>[  504.440913] [drm:hsw_set_power_well] Enabling power well
>[  504.442981] [drm:intel_power_well_enable] enabling always-on
>[  504.442992] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  504.442993] [drm:intel_enable_shared_dpll] enabling SPLL
>[  504.443882] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  504.443953] [drm:intel_enable_pipe] enabling pipe B
>[  504.443966] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  504.510803] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  504.510807] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  504.510809] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  504.510810] [drm:check_crtc_state] [CRTC:25]
>[  504.510821] [drm:check_shared_dpll_state] WRPLL 1
>[  504.510822] [drm:check_shared_dpll_state] WRPLL 2
>[  504.510823] [drm:check_shared_dpll_state] SPLL
>[  504.510825] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bf2400
>[  504.510828] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bf2400
>[  504.510855] [drm:drm_mode_setcrtc] [CRTC:25]
>[  504.510857] [drm:drm_atomic_state_init] Allocated atomic state ffff88020103c600
>[  504.510860] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5326400 state to ffff88020103c600
>[  504.510861] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f55af900 state to ffff88020103c600
>[  504.510863] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f5326400
>[  504.510863] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55af900 to [NOCRTC]
>[  504.510865] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f55af900
>[  504.510866] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103c600
>[  504.510867] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c909b000 state to ffff88020103c600
>[  504.510868] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c909b000 to [NOCRTC]
>[  504.510869] [drm:drm_atomic_check_only] checking ffff88020103c600
>[  504.510871] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  504.510871] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  504.510872] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  504.510873] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  504.510874] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  504.510875] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  504.510876] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103c600
>[  504.510877] [drm:drm_atomic_connectors_for_crtc] State ffff88020103c600 has 0 connectors for [CRTC:25]
>[  504.510880] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  504.510881] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  504.510883] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f55aff00 state to ffff88020103c600
>[  504.510884] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f55af9c0 state to ffff88020103c600
>[  504.510886] [drm:drm_atomic_commit] commiting ffff88020103c600
>[  504.527497] [drm:intel_disable_pipe] disabling pipe B
>[  504.562608] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  504.562611] [drm:intel_disable_shared_dpll] disabling SPLL
>[  504.562620] [drm:intel_power_well_disable] disabling display
>[  504.562621] [drm:hsw_set_power_well] Requesting to disable the power well
>[  504.562622] [drm:intel_power_well_disable] disabling always-on
>[  504.562624] [drm:intel_power_well_enable] enabling display
>[  504.562625] [drm:hsw_set_power_well] Enabling power well
>[  504.564694] [drm:intel_power_well_disable] disabling display
>[  504.564698] [drm:hsw_set_power_well] Requesting to disable the power well
>[  504.564703] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  504.564705] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  504.564706] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  504.564709] [drm:check_crtc_state] [CRTC:25]
>[  504.564711] [drm:check_shared_dpll_state] WRPLL 1
>[  504.564712] [drm:check_shared_dpll_state] WRPLL 2
>[  504.564713] [drm:check_shared_dpll_state] SPLL
>[  504.564715] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88020103c600
>[  504.564717] [drm:drm_atomic_state_free] Freeing atomic state ffff88020103c600
>[  504.564745] [drm:drm_mode_setcrtc] [CRTC:25]
>[  504.564748] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  504.564750] [drm:drm_atomic_state_init] Allocated atomic state ffff88020103c600
>[  504.564752] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5325000 state to ffff88020103c600
>[  504.564753] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f55af0c0 state to ffff88020103c600
>[  504.564755] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f5325000
>[  504.564756] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55af0c0 to [CRTC:25]
>[  504.564757] [drm:drm_atomic_set_fb_for_plane] Set [FB:51] for plane state ffff8801f55af0c0
>[  504.564758] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c909b440 state to ffff88020103c600
>[  504.564759] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103c600
>[  504.564760] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c909b440 to [CRTC:25]
>[  504.564761] [drm:drm_atomic_check_only] checking ffff88020103c600
>[  504.564763] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  504.564763] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  504.564764] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  504.564766] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  504.564767] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  504.564767] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  504.564768] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103c600
>[  504.564769] [drm:drm_atomic_connectors_for_crtc] State ffff88020103c600 has 1 connectors for [CRTC:25]
>[  504.564771] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103c600
>[  504.564772] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  504.564773] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  504.564775] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  504.564776] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  504.564777] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff8801f5325000 for pipe B
>[  504.564778] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  504.564778] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  504.564780] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  504.564781] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  504.564782] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  504.564783] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  504.564783] [drm:intel_dump_pipe_config] requested mode:
>[  504.564785] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  504.564786] [drm:intel_dump_pipe_config] adjusted mode:
>[  504.564787] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  504.564788] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  504.564789] [drm:intel_dump_pipe_config] port clock: 270000
>[  504.564790] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  504.564791] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  504.564792] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  504.564793] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  504.564793] [drm:intel_dump_pipe_config] ips: 0
>[  504.564794] [drm:intel_dump_pipe_config] double wide: 0
>[  504.564795] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  504.564796] [drm:intel_dump_pipe_config] planes on this crtc
>[  504.564797] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  504.564798] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  504.564799] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  504.564801] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff8801f5327800 state to ffff88020103c600
>[  504.564802] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff8801f5324400 state to ffff88020103c600
>[  504.564804] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 51
>[  504.564805] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  504.564807] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8801f55af000 state to ffff88020103c600
>[  504.564808] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8801f55afb40 state to ffff88020103c600
>[  504.564809] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8801f55af6c0 state to ffff88020103c600
>[  504.564811] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f55af540 state to ffff88020103c600
>[  504.564812] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f55af480 state to ffff88020103c600
>[  504.564814] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8801f55af300 state to ffff88020103c600
>[  504.564815] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8801f55af840 state to ffff88020103c600
>[  504.564816] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8801f55af780 state to ffff88020103c600
>[  504.564818] [drm:drm_atomic_commit] commiting ffff88020103c600
>[  504.564822] [drm:intel_power_well_enable] enabling display
>[  504.564824] [drm:hsw_set_power_well] Enabling power well
>[  504.566893] [drm:intel_power_well_enable] enabling always-on
>[  504.566904] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  504.566905] [drm:intel_enable_shared_dpll] enabling SPLL
>[  504.567794] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  504.567858] [drm:intel_enable_pipe] enabling pipe B
>[  504.567872] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  504.634710] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  504.634715] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  504.634716] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  504.634718] [drm:check_crtc_state] [CRTC:25]
>[  504.634729] [drm:check_shared_dpll_state] WRPLL 1
>[  504.634730] [drm:check_shared_dpll_state] WRPLL 2
>[  504.634731] [drm:check_shared_dpll_state] SPLL
>[  504.634733] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88020103c600
>[  504.634736] [drm:drm_atomic_state_free] Freeing atomic state ffff88020103c600
>[  504.634762] [drm:drm_mode_setcrtc] [CRTC:25]
>[  504.634764] [drm:drm_atomic_state_init] Allocated atomic state ffff88020103c600
>[  504.634766] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5326400 state to ffff88020103c600
>[  504.634767] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f55af9c0 state to ffff88020103c600
>[  504.634768] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f5326400
>[  504.634769] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55af9c0 to [NOCRTC]
>[  504.634770] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f55af9c0
>[  504.634771] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103c600
>[  504.634772] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c909b000 state to ffff88020103c600
>[  504.634773] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c909b000 to [NOCRTC]
>[  504.634774] [drm:drm_atomic_check_only] checking ffff88020103c600
>[  504.634776] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  504.634776] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  504.634777] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  504.634778] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  504.634779] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  504.634780] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  504.634781] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103c600
>[  504.634782] [drm:drm_atomic_connectors_for_crtc] State ffff88020103c600 has 0 connectors for [CRTC:25]
>[  504.634785] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  504.634786] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  504.634788] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f55aff00 state to ffff88020103c600
>[  504.634789] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f55af900 state to ffff88020103c600
>[  504.634791] [drm:drm_atomic_commit] commiting ffff88020103c600
>[  504.651403] [drm:intel_disable_pipe] disabling pipe B
>[  504.686136] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  504.686139] [drm:intel_disable_shared_dpll] disabling SPLL
>[  504.686147] [drm:intel_power_well_disable] disabling display
>[  504.686149] [drm:hsw_set_power_well] Requesting to disable the power well
>[  504.686150] [drm:intel_power_well_disable] disabling always-on
>[  504.686151] [drm:intel_power_well_enable] enabling display
>[  504.686152] [drm:hsw_set_power_well] Enabling power well
>[  504.688221] [drm:intel_power_well_disable] disabling display
>[  504.688225] [drm:hsw_set_power_well] Requesting to disable the power well
>[  504.688230] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  504.688232] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  504.688233] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  504.688236] [drm:check_crtc_state] [CRTC:25]
>[  504.688237] [drm:check_shared_dpll_state] WRPLL 1
>[  504.688238] [drm:check_shared_dpll_state] WRPLL 2
>[  504.688239] [drm:check_shared_dpll_state] SPLL
>[  504.688241] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88020103c600
>[  504.688243] [drm:drm_atomic_state_free] Freeing atomic state ffff88020103c600
>[  504.688271] [drm:drm_mode_setcrtc] [CRTC:25]
>[  504.688274] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  504.688276] [drm:drm_atomic_state_init] Allocated atomic state ffff88020103c600
>[  504.688277] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5325000 state to ffff88020103c600
>[  504.688279] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f55af480 state to ffff88020103c600
>[  504.688280] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f5325000
>[  504.688281] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55af480 to [CRTC:25]
>[  504.688282] [drm:drm_atomic_set_fb_for_plane] Set [FB:49] for plane state ffff8801f55af480
>[  504.688283] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c909b440 state to ffff88020103c600
>[  504.688285] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103c600
>[  504.688286] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c909b440 to [CRTC:25]
>[  504.688286] [drm:drm_atomic_check_only] checking ffff88020103c600
>[  504.688288] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  504.688289] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  504.688290] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  504.688291] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  504.688292] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  504.688293] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  504.688294] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103c600
>[  504.688295] [drm:drm_atomic_connectors_for_crtc] State ffff88020103c600 has 1 connectors for [CRTC:25]
>[  504.688296] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103c600
>[  504.688298] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  504.688299] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  504.688300] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  504.688301] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  504.688302] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff8801f5325000 for pipe B
>[  504.688303] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  504.688304] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  504.688305] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  504.688306] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  504.688307] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  504.688308] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  504.688309] [drm:intel_dump_pipe_config] requested mode:
>[  504.688310] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  504.688311] [drm:intel_dump_pipe_config] adjusted mode:
>[  504.688312] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  504.688314] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  504.688314] [drm:intel_dump_pipe_config] port clock: 270000
>[  504.688315] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  504.688316] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  504.688317] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  504.688318] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  504.688319] [drm:intel_dump_pipe_config] ips: 0
>[  504.688319] [drm:intel_dump_pipe_config] double wide: 0
>[  504.688320] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  504.688321] [drm:intel_dump_pipe_config] planes on this crtc
>[  504.688322] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  504.688323] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  504.688324] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  504.688326] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff8801f5324000 state to ffff88020103c600
>[  504.688327] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff8801f5326000 state to ffff88020103c600
>[  504.688329] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 49
>[  504.688330] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  504.688332] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8801f55af0c0 state to ffff88020103c600
>[  504.688333] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8801f55af180 state to ffff88020103c600
>[  504.688334] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8801f55af3c0 state to ffff88020103c600
>[  504.688336] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f55af600 state to ffff88020103c600
>[  504.688338] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f55af240 state to ffff88020103c600
>[  504.688339] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8801f55afcc0 state to ffff88020103c600
>[  504.688340] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8801f55afc00 state to ffff88020103c600
>[  504.688341] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8801f55afa80 state to ffff88020103c600
>[  504.688342] [drm:drm_atomic_commit] commiting ffff88020103c600
>[  504.688347] [drm:intel_power_well_enable] enabling display
>[  504.688348] [drm:hsw_set_power_well] Enabling power well
>[  504.689620] [drm:intel_power_well_enable] enabling always-on
>[  504.689631] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  504.689633] [drm:intel_enable_shared_dpll] enabling SPLL
>[  504.690522] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  504.690586] [drm:intel_enable_pipe] enabling pipe B
>[  504.690600] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  504.757466] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  504.757470] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  504.757472] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  504.757473] [drm:check_crtc_state] [CRTC:25]
>[  504.757485] [drm:check_shared_dpll_state] WRPLL 1
>[  504.757486] [drm:check_shared_dpll_state] WRPLL 2
>[  504.757487] [drm:check_shared_dpll_state] SPLL
>[  504.757489] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88020103c600
>[  504.757492] [drm:drm_atomic_state_free] Freeing atomic state ffff88020103c600
>[  504.757519] [drm:drm_mode_setcrtc] [CRTC:25]
>[  504.757521] [drm:drm_atomic_state_init] Allocated atomic state ffff880210d7b000
>[  504.757524] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5493800 state to ffff880210d7b000
>[  504.757525] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f5fdeb40 state to ffff880210d7b000
>[  504.757545] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f5493800
>[  504.757546] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f5fdeb40 to [NOCRTC]
>[  504.757547] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f5fdeb40
>[  504.757548] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b000
>[  504.757550] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800d3bbad80 state to ffff880210d7b000
>[  504.757551] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800d3bbad80 to [NOCRTC]
>[  504.757552] [drm:drm_atomic_check_only] checking ffff880210d7b000
>[  504.757553] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  504.757554] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  504.757555] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  504.757556] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  504.757557] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  504.757558] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  504.757559] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b000
>[  504.757561] [drm:drm_atomic_connectors_for_crtc] State ffff880210d7b000 has 0 connectors for [CRTC:25]
>[  504.757564] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  504.757565] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  504.757567] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f5fde780 state to ffff880210d7b000
>[  504.757569] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f5fdec00 state to ffff880210d7b000
>[  504.757571] [drm:drm_atomic_commit] commiting ffff880210d7b000
>[  504.774135] [drm:intel_disable_pipe] disabling pipe B
>[  504.808621] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  504.808624] [drm:intel_disable_shared_dpll] disabling SPLL
>[  504.808632] [drm:intel_power_well_disable] disabling display
>[  504.808634] [drm:hsw_set_power_well] Requesting to disable the power well
>[  504.808635] [drm:intel_power_well_disable] disabling always-on
>[  504.808636] [drm:intel_power_well_enable] enabling display
>[  504.808637] [drm:hsw_set_power_well] Enabling power well
>[  504.810706] [drm:intel_power_well_disable] disabling display
>[  504.810710] [drm:hsw_set_power_well] Requesting to disable the power well
>[  504.810715] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  504.810717] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  504.810719] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  504.810721] [drm:check_crtc_state] [CRTC:25]
>[  504.810723] [drm:check_shared_dpll_state] WRPLL 1
>[  504.810724] [drm:check_shared_dpll_state] WRPLL 2
>[  504.810725] [drm:check_shared_dpll_state] SPLL
>[  504.810727] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880210d7b000
>[  504.810729] [drm:drm_atomic_state_free] Freeing atomic state ffff880210d7b000
>[  504.810758] [drm:drm_mode_setcrtc] [CRTC:25]
>[  504.810761] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  504.810763] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bf2600
>[  504.810765] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880215be4000 state to ffff880026bf2600
>[  504.810766] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8800d6c35b40 state to ffff880026bf2600
>[  504.810768] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff880215be4000
>[  504.810769] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800d6c35b40 to [CRTC:25]
>[  504.810770] [drm:drm_atomic_set_fb_for_plane] Set [FB:51] for plane state ffff8800d6c35b40
>[  504.810771] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c01321e0 state to ffff880026bf2600
>[  504.810772] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf2600
>[  504.810773] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c01321e0 to [CRTC:25]
>[  504.810774] [drm:drm_atomic_check_only] checking ffff880026bf2600
>[  504.810775] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  504.810776] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  504.810777] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  504.810778] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  504.810779] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  504.810780] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  504.810781] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf2600
>[  504.810782] [drm:drm_atomic_connectors_for_crtc] State ffff880026bf2600 has 1 connectors for [CRTC:25]
>[  504.810784] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf2600
>[  504.810785] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  504.810786] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  504.810788] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  504.810789] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  504.810790] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff880215be4000 for pipe B
>[  504.810791] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  504.810792] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  504.810793] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  504.810794] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  504.810795] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  504.810796] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  504.810796] [drm:intel_dump_pipe_config] requested mode:
>[  504.810798] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  504.810799] [drm:intel_dump_pipe_config] adjusted mode:
>[  504.810800] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  504.810801] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  504.810802] [drm:intel_dump_pipe_config] port clock: 270000
>[  504.810803] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  504.810804] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  504.810805] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  504.810806] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  504.810806] [drm:intel_dump_pipe_config] ips: 0
>[  504.810807] [drm:intel_dump_pipe_config] double wide: 0
>[  504.810808] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  504.810809] [drm:intel_dump_pipe_config] planes on this crtc
>[  504.810810] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  504.810811] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  504.810812] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  504.810814] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff880215be6400 state to ffff880026bf2600
>[  504.810815] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff880215be5000 state to ffff880026bf2600
>[  504.810817] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 51
>[  504.810818] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  504.810819] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8800d6c35240 state to ffff880026bf2600
>[  504.810821] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8800d6c359c0 state to ffff880026bf2600
>[  504.810822] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8800d6c35f00 state to ffff880026bf2600
>[  504.810824] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8800d6c35900 state to ffff880026bf2600
>[  504.810825] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8800d6c35600 state to ffff880026bf2600
>[  504.810827] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8800d6c35480 state to ffff880026bf2600
>[  504.810828] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8800d6c356c0 state to ffff880026bf2600
>[  504.810829] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8800d6c35d80 state to ffff880026bf2600
>[  504.810831] [drm:drm_atomic_commit] commiting ffff880026bf2600
>[  504.810835] [drm:intel_power_well_enable] enabling display
>[  504.810837] [drm:hsw_set_power_well] Enabling power well
>[  504.812907] [drm:intel_power_well_enable] enabling always-on
>[  504.812918] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  504.812919] [drm:intel_enable_shared_dpll] enabling SPLL
>[  504.813808] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  504.813874] [drm:intel_enable_pipe] enabling pipe B
>[  504.813888] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  504.847701] [drm:intel_print_rc6_info] Enabling RC6 states: RC6 on
>[  504.851586] [drm:gen6_enable_rps] Overclocking supported. Max: 1100MHz, Overclock max: 1100MHz
>[  504.880754] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  504.880759] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  504.880760] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  504.880762] [drm:check_crtc_state] [CRTC:25]
>[  504.880773] [drm:check_shared_dpll_state] WRPLL 1
>[  504.880774] [drm:check_shared_dpll_state] WRPLL 2
>[  504.880775] [drm:check_shared_dpll_state] SPLL
>[  504.880777] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bf2600
>[  504.880780] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bf2600
>[  504.880807] [drm:drm_mode_setcrtc] [CRTC:25]
>[  504.880809] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bf2600
>[  504.880811] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880215be4800 state to ffff880026bf2600
>[  504.880813] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8800d6c35180 state to ffff880026bf2600
>[  504.880814] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff880215be4800
>[  504.880815] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800d6c35180 to [NOCRTC]
>[  504.880816] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8800d6c35180
>[  504.880817] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf2600
>[  504.880818] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c0132fe0 state to ffff880026bf2600
>[  504.880819] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c0132fe0 to [NOCRTC]
>[  504.880820] [drm:drm_atomic_check_only] checking ffff880026bf2600
>[  504.880821] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  504.880822] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  504.880823] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  504.880824] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  504.880824] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  504.880825] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  504.880826] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf2600
>[  504.880828] [drm:drm_atomic_connectors_for_crtc] State ffff880026bf2600 has 0 connectors for [CRTC:25]
>[  504.880830] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  504.880831] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  504.880833] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8800d6c35540 state to ffff880026bf2600
>[  504.880834] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8800d6c35a80 state to ffff880026bf2600
>[  504.880836] [drm:drm_atomic_commit] commiting ffff880026bf2600
>[  504.897421] [drm:intel_disable_pipe] disabling pipe B
>[  504.932178] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  504.932182] [drm:intel_disable_shared_dpll] disabling SPLL
>[  504.932189] [drm:intel_power_well_disable] disabling display
>[  504.932191] [drm:hsw_set_power_well] Requesting to disable the power well
>[  504.932192] [drm:intel_power_well_disable] disabling always-on
>[  504.932200] [drm:intel_runtime_suspend] Suspending device
>[  504.932300] [drm:hsw_enable_pc8] Enabling package C8+
>[  504.945581] [drm:intel_runtime_suspend] Device suspended
>[  504.953600] [drm:intel_runtime_resume] Resuming device
>[  504.955669] [drm:hsw_disable_pc8] Disabling package C8+
>[  504.959569] [drm:intel_update_cdclk] Current CD clock rate: 540000 kHz
>[  505.071656] [drm:intel_runtime_resume] Device resumed
>[  505.071660] [drm:intel_power_well_enable] enabling display
>[  505.071661] [drm:hsw_set_power_well] Enabling power well
>[  505.073588] [drm:intel_power_well_disable] disabling display
>[  505.073593] [drm:hsw_set_power_well] Requesting to disable the power well
>[  505.073599] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  505.073601] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  505.073603] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  505.073606] [drm:check_crtc_state] [CRTC:25]
>[  505.073607] [drm:check_shared_dpll_state] WRPLL 1
>[  505.073609] [drm:check_shared_dpll_state] WRPLL 2
>[  505.073610] [drm:check_shared_dpll_state] SPLL
>[  505.073612] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bf2600
>[  505.073614] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bf2600
>[  505.073639] [drm:drm_mode_setcrtc] [CRTC:25]
>[  505.073642] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  505.073644] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bf2600
>[  505.073646] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880215be4000 state to ffff880026bf2600
>[  505.073648] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8800d6c35600 state to ffff880026bf2600
>[  505.073650] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff880215be4000
>[  505.073651] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800d6c35600 to [CRTC:25]
>[  505.073652] [drm:drm_atomic_set_fb_for_plane] Set [FB:49] for plane state ffff8800d6c35600
>[  505.073654] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c01321e0 state to ffff880026bf2600
>[  505.073655] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf2600
>[  505.073656] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c01321e0 to [CRTC:25]
>[  505.073657] [drm:drm_atomic_check_only] checking ffff880026bf2600
>[  505.073659] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  505.073661] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  505.073662] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  505.073664] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  505.073664] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  505.073666] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  505.073667] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf2600
>[  505.073669] [drm:drm_atomic_connectors_for_crtc] State ffff880026bf2600 has 1 connectors for [CRTC:25]
>[  505.073670] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf2600
>[  505.073671] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  505.073672] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  505.073674] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  505.073675] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  505.073677] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff880215be4000 for pipe B
>[  505.073678] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  505.073679] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  505.073680] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  505.073682] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  505.073684] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  505.073684] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  505.073686] [drm:intel_dump_pipe_config] requested mode:
>[  505.073687] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  505.073688] [drm:intel_dump_pipe_config] adjusted mode:
>[  505.073690] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  505.073692] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  505.073693] [drm:intel_dump_pipe_config] port clock: 270000
>[  505.073694] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  505.073695] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  505.073696] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  505.073697] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  505.073698] [drm:intel_dump_pipe_config] ips: 0
>[  505.073699] [drm:intel_dump_pipe_config] double wide: 0
>[  505.073700] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  505.073701] [drm:intel_dump_pipe_config] planes on this crtc
>[  505.073702] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  505.073703] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  505.073704] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  505.073706] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff880215be4400 state to ffff880026bf2600
>[  505.073707] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff880215be5c00 state to ffff880026bf2600
>[  505.073709] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 49
>[  505.073710] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  505.073712] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8800d6c35b40 state to ffff880026bf2600
>[  505.073713] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8800d6c35840 state to ffff880026bf2600
>[  505.073714] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8800d6c35e40 state to ffff880026bf2600
>[  505.073717] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8800d6c35000 state to ffff880026bf2600
>[  505.073718] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8800d6c35780 state to ffff880026bf2600
>[  505.073720] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8800d6c35300 state to ffff880026bf2600
>[  505.073721] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff880215028480 state to ffff880026bf2600
>[  505.073723] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff880215028780 state to ffff880026bf2600
>[  505.073724] [drm:drm_atomic_commit] commiting ffff880026bf2600
>[  505.073729] [drm:intel_power_well_enable] enabling display
>[  505.073730] [drm:hsw_set_power_well] Enabling power well
>[  505.075798] [drm:intel_power_well_enable] enabling always-on
>[  505.075808] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  505.075809] [drm:intel_enable_shared_dpll] enabling SPLL
>[  505.076699] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  505.076763] [drm:intel_enable_pipe] enabling pipe B
>[  505.076776] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  505.143654] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  505.143658] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  505.143659] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  505.143661] [drm:check_crtc_state] [CRTC:25]
>[  505.143672] [drm:check_shared_dpll_state] WRPLL 1
>[  505.143673] [drm:check_shared_dpll_state] WRPLL 2
>[  505.143674] [drm:check_shared_dpll_state] SPLL
>[  505.143676] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bf2600
>[  505.143679] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bf2600
>[  505.143706] [drm:drm_mode_setcrtc] [CRTC:25]
>[  505.143708] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bf2600
>[  505.143710] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880215be5000 state to ffff880026bf2600
>[  505.143712] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff880215028900 state to ffff880026bf2600
>[  505.143713] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff880215be5000
>[  505.143713] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880215028900 to [NOCRTC]
>[  505.143714] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880215028900
>[  505.143716] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf2600
>[  505.143717] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c0132fe0 state to ffff880026bf2600
>[  505.143717] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c0132fe0 to [NOCRTC]
>[  505.143718] [drm:drm_atomic_check_only] checking ffff880026bf2600
>[  505.143720] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  505.143721] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  505.143722] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  505.143723] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  505.143723] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  505.143724] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  505.143725] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf2600
>[  505.143726] [drm:drm_atomic_connectors_for_crtc] State ffff880026bf2600 has 0 connectors for [CRTC:25]
>[  505.143729] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  505.143730] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  505.143732] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff880215028b40 state to ffff880026bf2600
>[  505.143733] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff880215028e40 state to ffff880026bf2600
>[  505.143735] [drm:drm_atomic_commit] commiting ffff880026bf2600
>[  505.160320] [drm:intel_disable_pipe] disabling pipe B
>[  505.194643] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  505.194647] [drm:intel_disable_shared_dpll] disabling SPLL
>[  505.194654] [drm:intel_power_well_disable] disabling display
>[  505.194656] [drm:hsw_set_power_well] Requesting to disable the power well
>[  505.194657] [drm:intel_power_well_disable] disabling always-on
>[  505.194658] [drm:intel_power_well_enable] enabling display
>[  505.194659] [drm:hsw_set_power_well] Enabling power well
>[  505.196728] [drm:intel_power_well_disable] disabling display
>[  505.196732] [drm:hsw_set_power_well] Requesting to disable the power well
>[  505.196737] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  505.196740] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  505.196741] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  505.196744] [drm:check_crtc_state] [CRTC:25]
>[  505.196745] [drm:check_shared_dpll_state] WRPLL 1
>[  505.196746] [drm:check_shared_dpll_state] WRPLL 2
>[  505.196747] [drm:check_shared_dpll_state] SPLL
>[  505.196749] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bf2600
>[  505.196751] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bf2600
>[  505.196779] [drm:drm_mode_setcrtc] [CRTC:25]
>[  505.196783] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  505.196784] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bfa800
>[  505.196786] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880025a41c00 state to ffff880026bfa800
>[  505.196788] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8800c78d4480 state to ffff880026bfa800
>[  505.196790] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff880025a41c00
>[  505.196791] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800c78d4480 to [CRTC:25]
>[  505.196792] [drm:drm_atomic_set_fb_for_plane] Set [FB:51] for plane state ffff8800c78d4480
>[  505.196793] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8801f442d0a0 state to ffff880026bfa800
>[  505.196794] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfa800
>[  505.196795] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f442d0a0 to [CRTC:25]
>[  505.196796] [drm:drm_atomic_check_only] checking ffff880026bfa800
>[  505.196797] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  505.196798] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  505.196799] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  505.196800] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  505.196801] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  505.196802] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  505.196803] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfa800
>[  505.196804] [drm:drm_atomic_connectors_for_crtc] State ffff880026bfa800 has 1 connectors for [CRTC:25]
>[  505.196806] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfa800
>[  505.196807] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  505.196808] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  505.196809] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  505.196810] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  505.196812] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff880025a41c00 for pipe B
>[  505.196812] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  505.196813] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  505.196814] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  505.196815] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  505.196816] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  505.196817] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  505.196818] [drm:intel_dump_pipe_config] requested mode:
>[  505.196819] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  505.196820] [drm:intel_dump_pipe_config] adjusted mode:
>[  505.196822] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  505.196823] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  505.196824] [drm:intel_dump_pipe_config] port clock: 270000
>[  505.196824] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  505.196825] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  505.196826] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  505.196827] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  505.196828] [drm:intel_dump_pipe_config] ips: 0
>[  505.196828] [drm:intel_dump_pipe_config] double wide: 0
>[  505.196829] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  505.196830] [drm:intel_dump_pipe_config] planes on this crtc
>[  505.196831] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  505.196832] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  505.196833] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  505.196835] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff880025a42c00 state to ffff880026bfa800
>[  505.196837] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff880025a41000 state to ffff880026bfa800
>[  505.196839] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 51
>[  505.196840] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  505.196841] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8800c78d4840 state to ffff880026bfa800
>[  505.196842] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8800c78d4180 state to ffff880026bfa800
>[  505.196843] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8800c78d4000 state to ffff880026bfa800
>[  505.196846] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8800c78d4cc0 state to ffff880026bfa800
>[  505.196847] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8800c78d49c0 state to ffff880026bfa800
>[  505.196849] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8800c78d4240 state to ffff880026bfa800
>[  505.196850] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8800c78d4a80 state to ffff880026bfa800
>[  505.196851] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8800c78d40c0 state to ffff880026bfa800
>[  505.196853] [drm:drm_atomic_commit] commiting ffff880026bfa800
>[  505.196857] [drm:intel_power_well_enable] enabling display
>[  505.196858] [drm:hsw_set_power_well] Enabling power well
>[  505.198927] [drm:intel_power_well_enable] enabling always-on
>[  505.198938] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  505.198939] [drm:intel_enable_shared_dpll] enabling SPLL
>[  505.199828] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  505.199893] [drm:intel_enable_pipe] enabling pipe B
>[  505.199907] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  505.266775] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  505.266779] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  505.266781] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  505.266782] [drm:check_crtc_state] [CRTC:25]
>[  505.266794] [drm:check_shared_dpll_state] WRPLL 1
>[  505.266795] [drm:check_shared_dpll_state] WRPLL 2
>[  505.266796] [drm:check_shared_dpll_state] SPLL
>[  505.266798] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bfa800
>[  505.266802] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bfa800
>[  505.266831] [drm:drm_mode_setcrtc] [CRTC:25]
>[  505.266833] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bfa800
>[  505.266835] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880025a41800 state to ffff880026bfa800
>[  505.266836] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8800c78d4b40 state to ffff880026bfa800
>[  505.266837] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff880025a41800
>[  505.266838] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800c78d4b40 to [NOCRTC]
>[  505.266839] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8800c78d4b40
>[  505.266840] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfa800
>[  505.266841] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8801f442d920 state to ffff880026bfa800
>[  505.266842] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f442d920 to [NOCRTC]
>[  505.266843] [drm:drm_atomic_check_only] checking ffff880026bfa800
>[  505.266845] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  505.266845] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  505.266847] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  505.266847] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  505.266848] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  505.266849] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  505.266850] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfa800
>[  505.266852] [drm:drm_atomic_connectors_for_crtc] State ffff880026bfa800 has 0 connectors for [CRTC:25]
>[  505.266855] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  505.266856] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  505.266858] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8800c78d4300 state to ffff880026bfa800
>[  505.266859] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8800c78d4e40 state to ffff880026bfa800
>[  505.266861] [drm:drm_atomic_commit] commiting ffff880026bfa800
>[  505.283441] [drm:intel_disable_pipe] disabling pipe B
>[  505.318557] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  505.318560] [drm:intel_disable_shared_dpll] disabling SPLL
>[  505.318568] [drm:intel_power_well_disable] disabling display
>[  505.318570] [drm:hsw_set_power_well] Requesting to disable the power well
>[  505.318571] [drm:intel_power_well_disable] disabling always-on
>[  505.318572] [drm:intel_power_well_enable] enabling display
>[  505.318573] [drm:hsw_set_power_well] Enabling power well
>[  505.320640] [drm:intel_power_well_disable] disabling display
>[  505.320644] [drm:hsw_set_power_well] Requesting to disable the power well
>[  505.320649] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  505.320651] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  505.320652] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  505.320655] [drm:check_crtc_state] [CRTC:25]
>[  505.320656] [drm:check_shared_dpll_state] WRPLL 1
>[  505.320658] [drm:check_shared_dpll_state] WRPLL 2
>[  505.320658] [drm:check_shared_dpll_state] SPLL
>[  505.320660] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bfa800
>[  505.320662] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bfa800
>[  505.320690] [drm:drm_mode_setcrtc] [CRTC:25]
>[  505.320693] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  505.320695] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bfa800
>[  505.320697] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880025a41c00 state to ffff880026bfa800
>[  505.320698] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8800c78d49c0 state to ffff880026bfa800
>[  505.320700] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff880025a41c00
>[  505.320701] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800c78d49c0 to [CRTC:25]
>[  505.320702] [drm:drm_atomic_set_fb_for_plane] Set [FB:49] for plane state ffff8800c78d49c0
>[  505.320703] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8801f442d0a0 state to ffff880026bfa800
>[  505.320704] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfa800
>[  505.320705] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f442d0a0 to [CRTC:25]
>[  505.320706] [drm:drm_atomic_check_only] checking ffff880026bfa800
>[  505.320708] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  505.320708] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  505.320709] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  505.320711] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  505.320712] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  505.320712] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  505.320713] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfa800
>[  505.320715] [drm:drm_atomic_connectors_for_crtc] State ffff880026bfa800 has 1 connectors for [CRTC:25]
>[  505.320716] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfa800
>[  505.320717] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  505.320718] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  505.320720] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  505.320721] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  505.320722] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff880025a41c00 for pipe B
>[  505.320723] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  505.320724] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  505.320725] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  505.320726] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  505.320727] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  505.320728] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  505.320728] [drm:intel_dump_pipe_config] requested mode:
>[  505.320730] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  505.320731] [drm:intel_dump_pipe_config] adjusted mode:
>[  505.320732] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  505.320733] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  505.320734] [drm:intel_dump_pipe_config] port clock: 270000
>[  505.320735] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  505.320736] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  505.320736] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  505.320737] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  505.320738] [drm:intel_dump_pipe_config] ips: 0
>[  505.320739] [drm:intel_dump_pipe_config] double wide: 0
>[  505.320740] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  505.320741] [drm:intel_dump_pipe_config] planes on this crtc
>[  505.320742] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  505.320743] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  505.320744] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  505.320745] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff880025a43000 state to ffff880026bfa800
>[  505.320747] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff880025a42000 state to ffff880026bfa800
>[  505.320749] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 49
>[  505.320750] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  505.320751] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8800c78d4480 state to ffff880026bfa800
>[  505.320752] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8800c78d4540 state to ffff880026bfa800
>[  505.320753] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8800c78d46c0 state to ffff880026bfa800
>[  505.320756] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8800c78d4900 state to ffff880026bfa800
>[  505.320757] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8800c78d4600 state to ffff880026bfa800
>[  505.320758] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8800c78d4780 state to ffff880026bfa800
>[  505.320760] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8800c78d4d80 state to ffff880026bfa800
>[  505.320761] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8800c78d4c00 state to ffff880026bfa800
>[  505.320762] [drm:drm_atomic_commit] commiting ffff880026bfa800
>[  505.320767] [drm:intel_power_well_enable] enabling display
>[  505.320768] [drm:hsw_set_power_well] Enabling power well
>[  505.322836] [drm:intel_power_well_enable] enabling always-on
>[  505.322846] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  505.322847] [drm:intel_enable_shared_dpll] enabling SPLL
>[  505.323737] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  505.323801] [drm:intel_enable_pipe] enabling pipe B
>[  505.323815] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  505.390683] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  505.390687] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  505.390689] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  505.390690] [drm:check_crtc_state] [CRTC:25]
>[  505.390702] [drm:check_shared_dpll_state] WRPLL 1
>[  505.390703] [drm:check_shared_dpll_state] WRPLL 2
>[  505.390704] [drm:check_shared_dpll_state] SPLL
>[  505.390706] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bfa800
>[  505.390709] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bfa800
>[  505.390736] [drm:drm_mode_setcrtc] [CRTC:25]
>[  505.390738] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bfa800
>[  505.390739] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880025a41000 state to ffff880026bfa800
>[  505.390741] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8800c78d40c0 state to ffff880026bfa800
>[  505.390742] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff880025a41000
>[  505.390743] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800c78d40c0 to [NOCRTC]
>[  505.390744] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8800c78d40c0
>[  505.390745] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfa800
>[  505.390746] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8801f442d920 state to ffff880026bfa800
>[  505.390747] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f442d920 to [NOCRTC]
>[  505.390748] [drm:drm_atomic_check_only] checking ffff880026bfa800
>[  505.390749] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  505.390750] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  505.390751] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  505.390752] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  505.390752] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  505.390753] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  505.390754] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfa800
>[  505.390756] [drm:drm_atomic_connectors_for_crtc] State ffff880026bfa800 has 0 connectors for [CRTC:25]
>[  505.390758] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  505.390759] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  505.390761] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8800c78d4a80 state to ffff880026bfa800
>[  505.390762] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8800c78d4240 state to ffff880026bfa800
>[  505.390764] [drm:drm_atomic_commit] commiting ffff880026bfa800
>[  505.407348] [drm:intel_disable_pipe] disabling pipe B
>[  505.442201] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  505.442204] [drm:intel_disable_shared_dpll] disabling SPLL
>[  505.442212] [drm:intel_power_well_disable] disabling display
>[  505.442214] [drm:hsw_set_power_well] Requesting to disable the power well
>[  505.442215] [drm:intel_power_well_disable] disabling always-on
>[  505.442216] [drm:intel_power_well_enable] enabling display
>[  505.442217] [drm:hsw_set_power_well] Enabling power well
>[  505.444287] [drm:intel_power_well_disable] disabling display
>[  505.444290] [drm:hsw_set_power_well] Requesting to disable the power well
>[  505.444295] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  505.444297] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  505.444299] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  505.444301] [drm:check_crtc_state] [CRTC:25]
>[  505.444303] [drm:check_shared_dpll_state] WRPLL 1
>[  505.444304] [drm:check_shared_dpll_state] WRPLL 2
>[  505.444305] [drm:check_shared_dpll_state] SPLL
>[  505.444307] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bfa800
>[  505.444309] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bfa800
>[  505.444337] [drm:drm_mode_setcrtc] [CRTC:25]
>[  505.444340] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  505.444342] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bfa800
>[  505.444344] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880025a41c00 state to ffff880026bfa800
>[  505.444345] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8800c78d4600 state to ffff880026bfa800
>[  505.444346] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff880025a41c00
>[  505.444347] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800c78d4600 to [CRTC:25]
>[  505.444348] [drm:drm_atomic_set_fb_for_plane] Set [FB:51] for plane state ffff8800c78d4600
>[  505.444350] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8801f442d0a0 state to ffff880026bfa800
>[  505.444351] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfa800
>[  505.444352] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f442d0a0 to [CRTC:25]
>[  505.444353] [drm:drm_atomic_check_only] checking ffff880026bfa800
>[  505.444354] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  505.444355] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  505.444356] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  505.444358] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  505.444358] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  505.444359] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  505.444360] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfa800
>[  505.444361] [drm:drm_atomic_connectors_for_crtc] State ffff880026bfa800 has 1 connectors for [CRTC:25]
>[  505.444363] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfa800
>[  505.444364] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  505.444365] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  505.444367] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  505.444368] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  505.444369] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff880025a41c00 for pipe B
>[  505.444370] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  505.444371] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  505.444372] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  505.444373] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  505.444374] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  505.444375] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  505.444375] [drm:intel_dump_pipe_config] requested mode:
>[  505.444377] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  505.444378] [drm:intel_dump_pipe_config] adjusted mode:
>[  505.444379] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  505.444380] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  505.444381] [drm:intel_dump_pipe_config] port clock: 270000
>[  505.444382] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  505.444383] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  505.444384] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  505.444385] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  505.444385] [drm:intel_dump_pipe_config] ips: 0
>[  505.444386] [drm:intel_dump_pipe_config] double wide: 0
>[  505.444387] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  505.444388] [drm:intel_dump_pipe_config] planes on this crtc
>[  505.444389] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  505.444390] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  505.444391] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  505.444393] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff880025a41800 state to ffff880026bfa800
>[  505.444394] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff880025a42c00 state to ffff880026bfa800
>[  505.444396] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 51
>[  505.444397] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  505.444399] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8800c78d49c0 state to ffff880026bfa800
>[  505.444400] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8800c78d4cc0 state to ffff880026bfa800
>[  505.444401] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8800c78d4e40 state to ffff880026bfa800
>[  505.444403] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8800c78d4300 state to ffff880026bfa800
>[  505.444404] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8800c78d4b40 state to ffff880026bfa800
>[  505.444406] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8800c78d4000 state to ffff880026bfa800
>[  505.444407] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8800c78d4180 state to ffff880026bfa800
>[  505.444408] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8800c78d4840 state to ffff880026bfa800
>[  505.444409] [drm:drm_atomic_commit] commiting ffff880026bfa800
>[  505.444414] [drm:intel_power_well_enable] enabling display
>[  505.444415] [drm:hsw_set_power_well] Enabling power well
>[  505.445554] [drm:intel_power_well_enable] enabling always-on
>[  505.445566] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  505.445568] [drm:intel_enable_shared_dpll] enabling SPLL
>[  505.446457] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  505.446522] [drm:intel_enable_pipe] enabling pipe B
>[  505.446536] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  505.513374] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  505.513378] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  505.513379] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  505.513381] [drm:check_crtc_state] [CRTC:25]
>[  505.513393] [drm:check_shared_dpll_state] WRPLL 1
>[  505.513394] [drm:check_shared_dpll_state] WRPLL 2
>[  505.513395] [drm:check_shared_dpll_state] SPLL
>[  505.513396] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bfa800
>[  505.513400] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bfa800
>[  505.513427] [drm:drm_mode_setcrtc] [CRTC:25]
>[  505.513429] [drm:drm_atomic_state_init] Allocated atomic state ffff88020103d400
>[  505.513431] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5327c00 state to ffff88020103d400
>[  505.513433] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f55afe40 state to ffff88020103d400
>[  505.513434] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f5327c00
>[  505.513435] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55afe40 to [NOCRTC]
>[  505.513436] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f55afe40
>[  505.513437] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103d400
>[  505.513438] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c909b020 state to ffff88020103d400
>[  505.513439] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c909b020 to [NOCRTC]
>[  505.513440] [drm:drm_atomic_check_only] checking ffff88020103d400
>[  505.513441] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  505.513442] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  505.513443] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  505.513444] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  505.513445] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  505.513446] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  505.513446] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103d400
>[  505.513448] [drm:drm_atomic_connectors_for_crtc] State ffff88020103d400 has 0 connectors for [CRTC:25]
>[  505.513450] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  505.513451] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  505.513454] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f55afa80 state to ffff88020103d400
>[  505.513455] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f55afc00 state to ffff88020103d400
>[  505.513457] [drm:drm_atomic_commit] commiting ffff88020103d400
>[  505.530068] [drm:intel_disable_pipe] disabling pipe B
>[  505.564542] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  505.564545] [drm:intel_disable_shared_dpll] disabling SPLL
>[  505.564553] [drm:intel_power_well_disable] disabling display
>[  505.564555] [drm:hsw_set_power_well] Requesting to disable the power well
>[  505.564556] [drm:intel_power_well_disable] disabling always-on
>[  505.564557] [drm:intel_power_well_enable] enabling display
>[  505.564558] [drm:hsw_set_power_well] Enabling power well
>[  505.566628] [drm:intel_power_well_disable] disabling display
>[  505.566632] [drm:hsw_set_power_well] Requesting to disable the power well
>[  505.566637] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  505.566639] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  505.566640] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  505.566643] [drm:check_crtc_state] [CRTC:25]
>[  505.566644] [drm:check_shared_dpll_state] WRPLL 1
>[  505.566646] [drm:check_shared_dpll_state] WRPLL 2
>[  505.566646] [drm:check_shared_dpll_state] SPLL
>[  505.566648] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88020103d400
>[  505.566651] [drm:drm_atomic_state_free] Freeing atomic state ffff88020103d400
>[  505.566679] [drm:drm_mode_setcrtc] [CRTC:25]
>[  505.566682] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  505.566684] [drm:drm_atomic_state_init] Allocated atomic state ffff880210d7b000
>[  505.566687] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5493800 state to ffff880210d7b000
>[  505.566688] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f5fde180 state to ffff880210d7b000
>[  505.566689] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f5493800
>[  505.566690] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f5fde180 to [CRTC:25]
>[  505.566691] [drm:drm_atomic_set_fb_for_plane] Set [FB:49] for plane state ffff8801f5fde180
>[  505.566693] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800d3bbac80 state to ffff880210d7b000
>[  505.566694] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b000
>[  505.566695] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800d3bbac80 to [CRTC:25]
>[  505.566695] [drm:drm_atomic_check_only] checking ffff880210d7b000
>[  505.566697] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  505.566698] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  505.566699] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  505.566700] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  505.566701] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  505.566702] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  505.566703] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b000
>[  505.566704] [drm:drm_atomic_connectors_for_crtc] State ffff880210d7b000 has 1 connectors for [CRTC:25]
>[  505.566705] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b000
>[  505.566707] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  505.566707] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  505.566709] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  505.566710] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  505.566712] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff8801f5493800 for pipe B
>[  505.566713] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  505.566713] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  505.566715] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  505.566716] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  505.566717] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  505.566718] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  505.566718] [drm:intel_dump_pipe_config] requested mode:
>[  505.566720] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  505.566721] [drm:intel_dump_pipe_config] adjusted mode:
>[  505.566722] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  505.566723] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  505.566724] [drm:intel_dump_pipe_config] port clock: 270000
>[  505.566725] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  505.566725] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  505.566726] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  505.566727] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  505.566728] [drm:intel_dump_pipe_config] ips: 0
>[  505.566729] [drm:intel_dump_pipe_config] double wide: 0
>[  505.566730] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  505.566730] [drm:intel_dump_pipe_config] planes on this crtc
>[  505.566732] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  505.566733] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  505.566734] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  505.566735] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff8801f5491c00 state to ffff880210d7b000
>[  505.566737] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff8801f5493400 state to ffff880210d7b000
>[  505.566739] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 49
>[  505.566740] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  505.566741] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8801f5fde600 state to ffff880210d7b000
>[  505.566742] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8801f5fde840 state to ffff880210d7b000
>[  505.566744] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8801f5fde480 state to ffff880210d7b000
>[  505.566746] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f5fde0c0 state to ffff880210d7b000
>[  505.566747] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f5fdecc0 state to ffff880210d7b000
>[  505.566749] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8801f5fdee40 state to ffff880210d7b000
>[  505.566750] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8801f5fde3c0 state to ffff880210d7b000
>[  505.566751] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8801f5fde540 state to ffff880210d7b000
>[  505.566752] [drm:drm_atomic_commit] commiting ffff880210d7b000
>[  505.566757] [drm:intel_power_well_enable] enabling display
>[  505.566758] [drm:hsw_set_power_well] Enabling power well
>[  505.568826] [drm:intel_power_well_enable] enabling always-on
>[  505.568836] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  505.568837] [drm:intel_enable_shared_dpll] enabling SPLL
>[  505.569735] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  505.569799] [drm:intel_enable_pipe] enabling pipe B
>[  505.569813] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  505.636649] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  505.636653] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  505.636655] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  505.636656] [drm:check_crtc_state] [CRTC:25]
>[  505.636668] [drm:check_shared_dpll_state] WRPLL 1
>[  505.636669] [drm:check_shared_dpll_state] WRPLL 2
>[  505.636670] [drm:check_shared_dpll_state] SPLL
>[  505.636671] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880210d7b000
>[  505.636675] [drm:drm_atomic_state_free] Freeing atomic state ffff880210d7b000
>[  505.636702] [drm:drm_mode_setcrtc] [CRTC:25]
>[  505.636705] [drm:drm_atomic_state_init] Allocated atomic state ffff88020103d400
>[  505.636706] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5327c00 state to ffff88020103d400
>[  505.636708] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f55afc00 state to ffff88020103d400
>[  505.636709] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f5327c00
>[  505.636710] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55afc00 to [NOCRTC]
>[  505.636711] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f55afc00
>[  505.636712] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103d400
>[  505.636713] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c909bac0 state to ffff88020103d400
>[  505.636714] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c909bac0 to [NOCRTC]
>[  505.636715] [drm:drm_atomic_check_only] checking ffff88020103d400
>[  505.636716] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  505.636717] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  505.636718] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  505.636719] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  505.636720] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  505.636721] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  505.636722] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103d400
>[  505.636723] [drm:drm_atomic_connectors_for_crtc] State ffff88020103d400 has 0 connectors for [CRTC:25]
>[  505.636726] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  505.636727] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  505.636729] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f55afa80 state to ffff88020103d400
>[  505.636730] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f55afe40 state to ffff88020103d400
>[  505.636732] [drm:drm_atomic_commit] commiting ffff88020103d400
>[  505.653341] [drm:intel_disable_pipe] disabling pipe B
>[  505.687832] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  505.687836] [drm:intel_disable_shared_dpll] disabling SPLL
>[  505.687843] [drm:intel_power_well_disable] disabling display
>[  505.687845] [drm:hsw_set_power_well] Requesting to disable the power well
>[  505.687846] [drm:intel_power_well_disable] disabling always-on
>[  505.687847] [drm:intel_power_well_enable] enabling display
>[  505.687848] [drm:hsw_set_power_well] Enabling power well
>[  505.689501] [drm:intel_power_well_disable] disabling display
>[  505.689504] [drm:hsw_set_power_well] Requesting to disable the power well
>[  505.689508] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  505.689511] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  505.689513] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  505.689515] [drm:check_crtc_state] [CRTC:25]
>[  505.689517] [drm:check_shared_dpll_state] WRPLL 1
>[  505.689518] [drm:check_shared_dpll_state] WRPLL 2
>[  505.689520] [drm:check_shared_dpll_state] SPLL
>[  505.689522] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88020103d400
>[  505.689525] [drm:drm_atomic_state_free] Freeing atomic state ffff88020103d400
>[  505.689550] [drm:drm_mode_setcrtc] [CRTC:25]
>[  505.689553] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  505.689555] [drm:drm_atomic_state_init] Allocated atomic state ffff880210d7b800
>[  505.689558] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5493800 state to ffff880210d7b800
>[  505.689559] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f5fdecc0 state to ffff880210d7b800
>[  505.689561] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f5493800
>[  505.689562] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f5fdecc0 to [CRTC:25]
>[  505.689563] [drm:drm_atomic_set_fb_for_plane] Set [FB:51] for plane state ffff8801f5fdecc0
>[  505.689565] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800d3bba580 state to ffff880210d7b800
>[  505.689566] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b800
>[  505.689567] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800d3bba580 to [CRTC:25]
>[  505.689569] [drm:drm_atomic_check_only] checking ffff880210d7b800
>[  505.689570] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  505.689571] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  505.689572] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  505.689574] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  505.689575] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  505.689576] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  505.689577] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b800
>[  505.689579] [drm:drm_atomic_connectors_for_crtc] State ffff880210d7b800 has 1 connectors for [CRTC:25]
>[  505.689581] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b800
>[  505.689582] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  505.689583] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  505.689585] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  505.689586] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  505.689588] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff8801f5493800 for pipe B
>[  505.689589] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  505.689590] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  505.689592] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  505.689593] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  505.689595] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  505.689595] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  505.689597] [drm:intel_dump_pipe_config] requested mode:
>[  505.689599] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  505.689600] [drm:intel_dump_pipe_config] adjusted mode:
>[  505.689601] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  505.689603] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  505.689604] [drm:intel_dump_pipe_config] port clock: 270000
>[  505.689606] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  505.689607] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  505.689608] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  505.689609] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  505.689610] [drm:intel_dump_pipe_config] ips: 0
>[  505.689611] [drm:intel_dump_pipe_config] double wide: 0
>[  505.689612] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  505.689613] [drm:intel_dump_pipe_config] planes on this crtc
>[  505.689614] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  505.689615] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  505.689616] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  505.689618] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff8801f5490c00 state to ffff880210d7b800
>[  505.689619] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff8801f5490800 state to ffff880210d7b800
>[  505.689622] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 51
>[  505.689623] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  505.689624] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8801f5fde180 state to ffff880210d7b800
>[  505.689625] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8801f5fde900 state to ffff880210d7b800
>[  505.689627] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8801f5fde000 state to ffff880210d7b800
>[  505.689629] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f5fded80 state to ffff880210d7b800
>[  505.689630] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f5fdea80 state to ffff880210d7b800
>[  505.689632] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8801f5fdef00 state to ffff880210d7b800
>[  505.689633] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8801f5fde9c0 state to ffff880210d7b800
>[  505.689634] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8801f5fde6c0 state to ffff880210d7b800
>[  505.689636] [drm:drm_atomic_commit] commiting ffff880210d7b800
>[  505.689641] [drm:intel_power_well_enable] enabling display
>[  505.689642] [drm:hsw_set_power_well] Enabling power well
>[  505.691709] [drm:intel_power_well_enable] enabling always-on
>[  505.691719] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  505.691720] [drm:intel_enable_shared_dpll] enabling SPLL
>[  505.692610] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  505.692674] [drm:intel_enable_pipe] enabling pipe B
>[  505.692687] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  505.759562] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  505.759566] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  505.759567] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  505.759569] [drm:check_crtc_state] [CRTC:25]
>[  505.759580] [drm:check_shared_dpll_state] WRPLL 1
>[  505.759581] [drm:check_shared_dpll_state] WRPLL 2
>[  505.759582] [drm:check_shared_dpll_state] SPLL
>[  505.759584] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880210d7b800
>[  505.759587] [drm:drm_atomic_state_free] Freeing atomic state ffff880210d7b800
>[  505.759614] [drm:drm_mode_setcrtc] [CRTC:25]
>[  505.759617] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bf2800
>[  505.759619] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880215be4800 state to ffff880026bf2800
>[  505.759620] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff880215028a80 state to ffff880026bf2800
>[  505.759621] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff880215be4800
>[  505.759622] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880215028a80 to [NOCRTC]
>[  505.759623] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880215028a80
>[  505.759624] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf2800
>[  505.759625] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c0132c60 state to ffff880026bf2800
>[  505.759626] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c0132c60 to [NOCRTC]
>[  505.759627] [drm:drm_atomic_check_only] checking ffff880026bf2800
>[  505.759629] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  505.759629] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  505.759630] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  505.759631] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  505.759632] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  505.759633] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  505.759634] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf2800
>[  505.759635] [drm:drm_atomic_connectors_for_crtc] State ffff880026bf2800 has 0 connectors for [CRTC:25]
>[  505.759638] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  505.759639] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  505.759641] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff880215028600 state to ffff880026bf2800
>[  505.759642] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff880215028240 state to ffff880026bf2800
>[  505.759644] [drm:drm_atomic_commit] commiting ffff880026bf2800
>[  505.776231] [drm:intel_disable_pipe] disabling pipe B
>[  505.810585] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  505.810588] [drm:intel_disable_shared_dpll] disabling SPLL
>[  505.810596] [drm:intel_power_well_disable] disabling display
>[  505.810598] [drm:hsw_set_power_well] Requesting to disable the power well
>[  505.810599] [drm:intel_power_well_disable] disabling always-on
>[  505.810600] [drm:intel_power_well_enable] enabling display
>[  505.810601] [drm:hsw_set_power_well] Enabling power well
>[  505.812671] [drm:intel_power_well_disable] disabling display
>[  505.812675] [drm:hsw_set_power_well] Requesting to disable the power well
>[  505.812680] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  505.812682] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  505.812683] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  505.812686] [drm:check_crtc_state] [CRTC:25]
>[  505.812687] [drm:check_shared_dpll_state] WRPLL 1
>[  505.812688] [drm:check_shared_dpll_state] WRPLL 2
>[  505.812689] [drm:check_shared_dpll_state] SPLL
>[  505.812691] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bf2800
>[  505.812694] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bf2800
>[  505.812722] [drm:drm_mode_setcrtc] [CRTC:25]
>[  505.812725] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  505.812727] [drm:drm_atomic_state_init] Allocated atomic state ffff88020103c600
>[  505.812729] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5326000 state to ffff88020103c600
>[  505.812730] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f55afcc0 state to ffff88020103c600
>[  505.812732] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f5326000
>[  505.812733] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55afcc0 to [CRTC:25]
>[  505.812734] [drm:drm_atomic_set_fb_for_plane] Set [FB:49] for plane state ffff8801f55afcc0
>[  505.812735] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c909b4c0 state to ffff88020103c600
>[  505.812736] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103c600
>[  505.812737] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c909b4c0 to [CRTC:25]
>[  505.812738] [drm:drm_atomic_check_only] checking ffff88020103c600
>[  505.812739] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  505.812740] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  505.812741] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  505.812743] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  505.812743] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  505.812744] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  505.812745] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103c600
>[  505.812746] [drm:drm_atomic_connectors_for_crtc] State ffff88020103c600 has 1 connectors for [CRTC:25]
>[  505.812748] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103c600
>[  505.812749] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  505.812750] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  505.812751] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  505.812752] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  505.812754] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff8801f5326000 for pipe B
>[  505.812754] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  505.812755] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  505.812756] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  505.812758] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  505.812759] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  505.812759] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  505.812760] [drm:intel_dump_pipe_config] requested mode:
>[  505.812762] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  505.812762] [drm:intel_dump_pipe_config] adjusted mode:
>[  505.812764] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  505.812765] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  505.812766] [drm:intel_dump_pipe_config] port clock: 270000
>[  505.812766] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  505.812767] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  505.812768] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  505.812769] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  505.812770] [drm:intel_dump_pipe_config] ips: 0
>[  505.812771] [drm:intel_dump_pipe_config] double wide: 0
>[  505.812772] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  505.812772] [drm:intel_dump_pipe_config] planes on this crtc
>[  505.812774] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  505.812775] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  505.812776] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  505.812777] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff8801f5324000 state to ffff88020103c600
>[  505.812779] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff8801f5325000 state to ffff88020103c600
>[  505.812781] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 49
>[  505.812782] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  505.812783] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8801f55af180 state to ffff88020103c600
>[  505.812784] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8801f55af0c0 state to ffff88020103c600
>[  505.812785] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8801f55af240 state to ffff88020103c600
>[  505.812788] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f55af600 state to ffff88020103c600
>[  505.812789] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f55af480 state to ffff88020103c600
>[  505.812791] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8801f55af540 state to ffff88020103c600
>[  505.812792] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8801f55af780 state to ffff88020103c600
>[  505.812793] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8801f55af840 state to ffff88020103c600
>[  505.812794] [drm:drm_atomic_commit] commiting ffff88020103c600
>[  505.812799] [drm:intel_power_well_enable] enabling display
>[  505.812800] [drm:hsw_set_power_well] Enabling power well
>[  505.814868] [drm:intel_power_well_enable] enabling always-on
>[  505.814878] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  505.814879] [drm:intel_enable_shared_dpll] enabling SPLL
>[  505.815769] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  505.815833] [drm:intel_enable_pipe] enabling pipe B
>[  505.815847] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  505.882692] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  505.882697] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  505.882698] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  505.882700] [drm:check_crtc_state] [CRTC:25]
>[  505.882711] [drm:check_shared_dpll_state] WRPLL 1
>[  505.882712] [drm:check_shared_dpll_state] WRPLL 2
>[  505.882713] [drm:check_shared_dpll_state] SPLL
>[  505.882715] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88020103c600
>[  505.882719] [drm:drm_atomic_state_free] Freeing atomic state ffff88020103c600
>[  505.882745] [drm:drm_mode_setcrtc] [CRTC:25]
>[  505.882747] [drm:drm_atomic_state_init] Allocated atomic state ffff88020103c600
>[  505.882749] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5324400 state to ffff88020103c600
>[  505.882750] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f55af300 state to ffff88020103c600
>[  505.882751] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f5324400
>[  505.882752] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55af300 to [NOCRTC]
>[  505.882753] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f55af300
>[  505.882755] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103c600
>[  505.882756] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c909b3a0 state to ffff88020103c600
>[  505.882757] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c909b3a0 to [NOCRTC]
>[  505.882758] [drm:drm_atomic_check_only] checking ffff88020103c600
>[  505.882759] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  505.882760] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  505.882761] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  505.882762] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  505.882763] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  505.882764] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  505.882765] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103c600
>[  505.882766] [drm:drm_atomic_connectors_for_crtc] State ffff88020103c600 has 0 connectors for [CRTC:25]
>[  505.882769] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  505.882770] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  505.882771] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f55af900 state to ffff88020103c600
>[  505.882772] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f55aff00 state to ffff88020103c600
>[  505.882774] [drm:drm_atomic_commit] commiting ffff88020103c600
>[  505.899387] [drm:intel_disable_pipe] disabling pipe B
>[  505.934505] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  505.934508] [drm:intel_disable_shared_dpll] disabling SPLL
>[  505.934517] [drm:intel_power_well_disable] disabling display
>[  505.934518] [drm:hsw_set_power_well] Requesting to disable the power well
>[  505.934519] [drm:intel_power_well_disable] disabling always-on
>[  505.934521] [drm:intel_power_well_enable] enabling display
>[  505.934522] [drm:hsw_set_power_well] Enabling power well
>[  505.936590] [drm:intel_power_well_disable] disabling display
>[  505.936594] [drm:hsw_set_power_well] Requesting to disable the power well
>[  505.936599] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  505.936602] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  505.936603] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  505.936605] [drm:check_crtc_state] [CRTC:25]
>[  505.936607] [drm:check_shared_dpll_state] WRPLL 1
>[  505.936608] [drm:check_shared_dpll_state] WRPLL 2
>[  505.936609] [drm:check_shared_dpll_state] SPLL
>[  505.936611] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88020103c600
>[  505.936613] [drm:drm_atomic_state_free] Freeing atomic state ffff88020103c600
>[  505.936641] [drm:drm_mode_setcrtc] [CRTC:25]
>[  505.936644] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  505.936646] [drm:drm_atomic_state_init] Allocated atomic state ffff88020103c600
>[  505.936647] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5326000 state to ffff88020103c600
>[  505.936649] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f55af480 state to ffff88020103c600
>[  505.936650] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f5326000
>[  505.936651] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55af480 to [CRTC:25]
>[  505.936652] [drm:drm_atomic_set_fb_for_plane] Set [FB:51] for plane state ffff8801f55af480
>[  505.936653] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c909b4c0 state to ffff88020103c600
>[  505.936654] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103c600
>[  505.936655] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c909b4c0 to [CRTC:25]
>[  505.936656] [drm:drm_atomic_check_only] checking ffff88020103c600
>[  505.936658] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  505.936659] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  505.936660] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  505.936661] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  505.936662] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  505.936663] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  505.936664] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103c600
>[  505.936665] [drm:drm_atomic_connectors_for_crtc] State ffff88020103c600 has 1 connectors for [CRTC:25]
>[  505.936666] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103c600
>[  505.936668] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  505.936668] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  505.936670] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  505.936671] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  505.936672] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff8801f5326000 for pipe B
>[  505.936673] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  505.936674] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  505.936675] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  505.936676] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  505.936677] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  505.936678] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  505.936678] [drm:intel_dump_pipe_config] requested mode:
>[  505.936680] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  505.936681] [drm:intel_dump_pipe_config] adjusted mode:
>[  505.936682] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  505.936683] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  505.936684] [drm:intel_dump_pipe_config] port clock: 270000
>[  505.936685] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  505.936686] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  505.936687] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  505.936688] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  505.936688] [drm:intel_dump_pipe_config] ips: 0
>[  505.936689] [drm:intel_dump_pipe_config] double wide: 0
>[  505.936690] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  505.936691] [drm:intel_dump_pipe_config] planes on this crtc
>[  505.936692] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  505.936693] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  505.936694] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  505.936696] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff8801f5326400 state to ffff88020103c600
>[  505.936697] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff8801f5327800 state to ffff88020103c600
>[  505.936699] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 51
>[  505.936700] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  505.936701] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8801f55afcc0 state to ffff88020103c600
>[  505.936702] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8801f55af3c0 state to ffff88020103c600
>[  505.936703] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8801f55af9c0 state to ffff88020103c600
>[  505.936706] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f55af6c0 state to ffff88020103c600
>[  505.936707] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f55afb40 state to ffff88020103c600
>[  505.936709] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8801f55af000 state to ffff88020103c600
>[  505.936710] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8801f55afe40 state to ffff88020103c600
>[  505.936711] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8801f55afa80 state to ffff88020103c600
>[  505.936712] [drm:drm_atomic_commit] commiting ffff88020103c600
>[  505.936717] [drm:intel_power_well_enable] enabling display
>[  505.936718] [drm:hsw_set_power_well] Enabling power well
>[  505.938787] [drm:intel_power_well_enable] enabling always-on
>[  505.938798] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  505.938799] [drm:intel_enable_shared_dpll] enabling SPLL
>[  505.939689] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  505.939753] [drm:intel_enable_pipe] enabling pipe B
>[  505.939767] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  506.006610] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  506.006615] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  506.006616] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  506.006618] [drm:check_crtc_state] [CRTC:25]
>[  506.006629] [drm:check_shared_dpll_state] WRPLL 1
>[  506.006630] [drm:check_shared_dpll_state] WRPLL 2
>[  506.006631] [drm:check_shared_dpll_state] SPLL
>[  506.006633] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88020103c600
>[  506.006636] [drm:drm_atomic_state_free] Freeing atomic state ffff88020103c600
>[  506.006662] [drm:drm_mode_setcrtc] [CRTC:25]
>[  506.006664] [drm:drm_atomic_state_init] Allocated atomic state ffff88020103c600
>[  506.006666] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5325000 state to ffff88020103c600
>[  506.006668] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f55af840 state to ffff88020103c600
>[  506.006669] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f5325000
>[  506.006669] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55af840 to [NOCRTC]
>[  506.006670] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f55af840
>[  506.006672] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103c600
>[  506.006673] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c909b3a0 state to ffff88020103c600
>[  506.006674] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c909b3a0 to [NOCRTC]
>[  506.006675] [drm:drm_atomic_check_only] checking ffff88020103c600
>[  506.006676] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  506.006677] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  506.006678] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  506.006679] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  506.006679] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  506.006680] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  506.006681] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103c600
>[  506.006683] [drm:drm_atomic_connectors_for_crtc] State ffff88020103c600 has 0 connectors for [CRTC:25]
>[  506.006685] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  506.006686] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  506.006688] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f55af780 state to ffff88020103c600
>[  506.006689] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f55af540 state to ffff88020103c600
>[  506.006691] [drm:drm_atomic_commit] commiting ffff88020103c600
>[  506.023310] [drm:intel_disable_pipe] disabling pipe B
>[  506.058223] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  506.058227] [drm:intel_disable_shared_dpll] disabling SPLL
>[  506.058238] [drm:intel_power_well_disable] disabling display
>[  506.058241] [drm:hsw_set_power_well] Requesting to disable the power well
>[  506.058242] [drm:intel_power_well_disable] disabling always-on
>[  506.058244] [drm:intel_power_well_enable] enabling display
>[  506.058246] [drm:hsw_set_power_well] Enabling power well
>[  506.060323] [drm:intel_power_well_disable] disabling display
>[  506.060327] [drm:hsw_set_power_well] Requesting to disable the power well
>[  506.060334] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  506.060337] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  506.060339] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  506.060343] [drm:check_crtc_state] [CRTC:25]
>[  506.060344] [drm:check_shared_dpll_state] WRPLL 1
>[  506.060346] [drm:check_shared_dpll_state] WRPLL 2
>[  506.060348] [drm:check_shared_dpll_state] SPLL
>[  506.060351] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88020103c600
>[  506.060354] [drm:drm_atomic_state_free] Freeing atomic state ffff88020103c600
>[  506.060389] [drm:drm_mode_setcrtc] [CRTC:25]
>[  506.060394] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  506.060396] [drm:drm_atomic_state_init] Allocated atomic state ffff88020103c600
>[  506.060399] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5326000 state to ffff88020103c600
>[  506.060401] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f55afb40 state to ffff88020103c600
>[  506.060404] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f5326000
>[  506.060405] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55afb40 to [CRTC:25]
>[  506.060407] [drm:drm_atomic_set_fb_for_plane] Set [FB:49] for plane state ffff8801f55afb40
>[  506.060409] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c909b4c0 state to ffff88020103c600
>[  506.060410] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103c600
>[  506.060412] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c909b4c0 to [CRTC:25]
>[  506.060414] [drm:drm_atomic_check_only] checking ffff88020103c600
>[  506.060416] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  506.060417] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  506.060419] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  506.060421] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  506.060422] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  506.060423] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  506.060425] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103c600
>[  506.060427] [drm:drm_atomic_connectors_for_crtc] State ffff88020103c600 has 1 connectors for [CRTC:25]
>[  506.060429] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103c600
>[  506.060431] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  506.060433] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  506.060435] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  506.060437] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  506.060439] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff8801f5326000 for pipe B
>[  506.060440] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  506.060441] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  506.060443] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  506.060445] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  506.060447] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  506.060449] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  506.060450] [drm:intel_dump_pipe_config] requested mode:
>[  506.060452] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  506.060453] [drm:intel_dump_pipe_config] adjusted mode:
>[  506.060456] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  506.060458] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  506.060459] [drm:intel_dump_pipe_config] port clock: 270000
>[  506.060460] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  506.060462] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  506.060463] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  506.060465] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  506.060466] [drm:intel_dump_pipe_config] ips: 0
>[  506.060467] [drm:intel_dump_pipe_config] double wide: 0
>[  506.060469] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  506.060470] [drm:intel_dump_pipe_config] planes on this crtc
>[  506.060472] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  506.060474] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  506.060475] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  506.060478] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff8801f5324400 state to ffff88020103c600
>[  506.060480] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff8801f5324000 state to ffff88020103c600
>[  506.060483] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 49
>[  506.060485] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  506.060487] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8801f55af480 state to ffff88020103c600
>[  506.060489] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8801f55af600 state to ffff88020103c600
>[  506.060491] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8801f55aff00 state to ffff88020103c600
>[  506.060494] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f55af900 state to ffff88020103c600
>[  506.060496] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f55af300 state to ffff88020103c600
>[  506.060499] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8801f55af240 state to ffff88020103c600
>[  506.060500] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8801f55af0c0 state to ffff88020103c600
>[  506.060502] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8801f55af180 state to ffff88020103c600
>[  506.060504] [drm:drm_atomic_commit] commiting ffff88020103c600
>[  506.060511] [drm:intel_power_well_enable] enabling display
>[  506.060512] [drm:hsw_set_power_well] Enabling power well
>[  506.062554] [drm:intel_power_well_enable] enabling always-on
>[  506.062566] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  506.062568] [drm:intel_enable_shared_dpll] enabling SPLL
>[  506.063461] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  506.063545] [drm:intel_enable_pipe] enabling pipe B
>[  506.063560] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  506.130409] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  506.130414] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  506.130416] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  506.130418] [drm:check_crtc_state] [CRTC:25]
>[  506.130432] [drm:check_shared_dpll_state] WRPLL 1
>[  506.130433] [drm:check_shared_dpll_state] WRPLL 2
>[  506.130435] [drm:check_shared_dpll_state] SPLL
>[  506.130437] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88020103c600
>[  506.130441] [drm:drm_atomic_state_free] Freeing atomic state ffff88020103c600
>[  506.130474] [drm:drm_mode_setcrtc] [CRTC:25]
>[  506.130476] [drm:drm_atomic_state_init] Allocated atomic state ffff88020103c600
>[  506.130479] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5327800 state to ffff88020103c600
>[  506.130481] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f55afa80 state to ffff88020103c600
>[  506.130482] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f5327800
>[  506.130484] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55afa80 to [NOCRTC]
>[  506.130485] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f55afa80
>[  506.130487] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103c600
>[  506.130489] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c909b3a0 state to ffff88020103c600
>[  506.130490] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c909b3a0 to [NOCRTC]
>[  506.130492] [drm:drm_atomic_check_only] checking ffff88020103c600
>[  506.130493] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  506.130494] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  506.130496] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  506.130497] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  506.130498] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  506.130500] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  506.130501] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103c600
>[  506.130503] [drm:drm_atomic_connectors_for_crtc] State ffff88020103c600 has 0 connectors for [CRTC:25]
>[  506.130507] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  506.130508] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  506.130511] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f55afe40 state to ffff88020103c600
>[  506.130513] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f55af000 state to ffff88020103c600
>[  506.130515] [drm:drm_atomic_commit] commiting ffff88020103c600
>[  506.147100] [drm:intel_disable_pipe] disabling pipe B
>[  506.182028] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  506.182032] [drm:intel_disable_shared_dpll] disabling SPLL
>[  506.182041] [drm:intel_power_well_disable] disabling display
>[  506.182043] [drm:hsw_set_power_well] Requesting to disable the power well
>[  506.182044] [drm:intel_power_well_disable] disabling always-on
>[  506.182046] [drm:intel_power_well_enable] enabling display
>[  506.182048] [drm:hsw_set_power_well] Enabling power well
>[  506.184120] [drm:intel_power_well_disable] disabling display
>[  506.184125] [drm:hsw_set_power_well] Requesting to disable the power well
>[  506.184130] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  506.184133] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  506.184135] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  506.184138] [drm:check_crtc_state] [CRTC:25]
>[  506.184140] [drm:check_shared_dpll_state] WRPLL 1
>[  506.184141] [drm:check_shared_dpll_state] WRPLL 2
>[  506.184142] [drm:check_shared_dpll_state] SPLL
>[  506.184144] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88020103c600
>[  506.184147] [drm:drm_atomic_state_free] Freeing atomic state ffff88020103c600
>[  506.184179] [drm:drm_mode_setcrtc] [CRTC:25]
>[  506.184183] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  506.184185] [drm:drm_atomic_state_init] Allocated atomic state ffff88020103c600
>[  506.184187] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5326000 state to ffff88020103c600
>[  506.184189] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f55af300 state to ffff88020103c600
>[  506.184191] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f5326000
>[  506.184192] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55af300 to [CRTC:25]
>[  506.184193] [drm:drm_atomic_set_fb_for_plane] Set [FB:51] for plane state ffff8801f55af300
>[  506.184195] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c909b4c0 state to ffff88020103c600
>[  506.184196] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103c600
>[  506.184197] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c909b4c0 to [CRTC:25]
>[  506.184199] [drm:drm_atomic_check_only] checking ffff88020103c600
>[  506.184201] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  506.184201] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  506.184203] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  506.184205] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  506.184206] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  506.184207] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  506.184208] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103c600
>[  506.184210] [drm:drm_atomic_connectors_for_crtc] State ffff88020103c600 has 1 connectors for [CRTC:25]
>[  506.184211] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103c600
>[  506.184213] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  506.184214] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  506.184216] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  506.184217] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  506.184219] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff8801f5326000 for pipe B
>[  506.184220] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  506.184221] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  506.184223] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  506.184224] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  506.184226] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  506.184227] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  506.184227] [drm:intel_dump_pipe_config] requested mode:
>[  506.184230] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  506.184231] [drm:intel_dump_pipe_config] adjusted mode:
>[  506.184232] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  506.184234] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  506.184235] [drm:intel_dump_pipe_config] port clock: 270000
>[  506.184236] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  506.184237] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  506.184238] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  506.184240] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  506.184241] [drm:intel_dump_pipe_config] ips: 0
>[  506.184241] [drm:intel_dump_pipe_config] double wide: 0
>[  506.184243] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  506.184244] [drm:intel_dump_pipe_config] planes on this crtc
>[  506.184245] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  506.184247] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  506.184248] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  506.184251] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff8801f5325000 state to ffff88020103c600
>[  506.184252] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff8801f5326400 state to ffff88020103c600
>[  506.184255] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 51
>[  506.184256] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  506.184258] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8801f55afb40 state to ffff88020103c600
>[  506.184260] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8801f55af6c0 state to ffff88020103c600
>[  506.184261] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8801f55af540 state to ffff88020103c600
>[  506.184264] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f55af780 state to ffff88020103c600
>[  506.184266] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f55af840 state to ffff88020103c600
>[  506.184268] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8801f55af9c0 state to ffff88020103c600
>[  506.184269] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8801f55af3c0 state to ffff88020103c600
>[  506.184270] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8801f55afcc0 state to ffff88020103c600
>[  506.184272] [drm:drm_atomic_commit] commiting ffff88020103c600
>[  506.184278] [drm:intel_power_well_enable] enabling display
>[  506.184279] [drm:hsw_set_power_well] Enabling power well
>[  506.185502] [drm:intel_power_well_enable] enabling always-on
>[  506.185514] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  506.185516] [drm:intel_enable_shared_dpll] enabling SPLL
>[  506.186408] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  506.186481] [drm:intel_enable_pipe] enabling pipe B
>[  506.186496] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  506.253364] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  506.253369] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  506.253370] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  506.253372] [drm:check_crtc_state] [CRTC:25]
>[  506.253383] [drm:check_shared_dpll_state] WRPLL 1
>[  506.253384] [drm:check_shared_dpll_state] WRPLL 2
>[  506.253385] [drm:check_shared_dpll_state] SPLL
>[  506.253387] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88020103c600
>[  506.253390] [drm:drm_atomic_state_free] Freeing atomic state ffff88020103c600
>[  506.253456] [drm:drm_mode_setcrtc] [CRTC:25]
>[  506.253459] [drm:drm_atomic_state_init] Allocated atomic state ffff880210d7b400
>[  506.253461] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5492c00 state to ffff880210d7b400
>[  506.253463] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f5fde6c0 state to ffff880210d7b400
>[  506.253465] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f5492c00
>[  506.253466] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f5fde6c0 to [NOCRTC]
>[  506.253468] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f5fde6c0
>[  506.253469] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b400
>[  506.253471] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800d3bba100 state to ffff880210d7b400
>[  506.253472] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800d3bba100 to [NOCRTC]
>[  506.253474] [drm:drm_atomic_check_only] checking ffff880210d7b400
>[  506.253475] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  506.253476] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  506.253478] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  506.253479] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  506.253480] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  506.253482] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  506.253484] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b400
>[  506.253486] [drm:drm_atomic_connectors_for_crtc] State ffff880210d7b400 has 0 connectors for [CRTC:25]
>[  506.253489] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  506.253491] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  506.253493] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f5fde9c0 state to ffff880210d7b400
>[  506.253495] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f5fdef00 state to ffff880210d7b400
>[  506.253498] [drm:drm_atomic_commit] commiting ffff880210d7b400
>[  506.270041] [drm:intel_disable_pipe] disabling pipe B
>[  506.304503] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  506.304507] [drm:intel_disable_shared_dpll] disabling SPLL
>[  506.304516] [drm:intel_power_well_disable] disabling display
>[  506.304517] [drm:hsw_set_power_well] Requesting to disable the power well
>[  506.304518] [drm:intel_power_well_disable] disabling always-on
>[  506.304520] [drm:intel_power_well_enable] enabling display
>[  506.304521] [drm:hsw_set_power_well] Enabling power well
>[  506.306592] [drm:intel_power_well_disable] disabling display
>[  506.306596] [drm:hsw_set_power_well] Requesting to disable the power well
>[  506.306602] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  506.306604] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  506.306606] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  506.306609] [drm:check_crtc_state] [CRTC:25]
>[  506.306610] [drm:check_shared_dpll_state] WRPLL 1
>[  506.306611] [drm:check_shared_dpll_state] WRPLL 2
>[  506.306612] [drm:check_shared_dpll_state] SPLL
>[  506.306615] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880210d7b400
>[  506.306617] [drm:drm_atomic_state_free] Freeing atomic state ffff880210d7b400
>[  506.306647] [drm:drm_mode_setcrtc] [CRTC:25]
>[  506.306651] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  506.306653] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bf3800
>[  506.306655] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880215be6400 state to ffff880026bf3800
>[  506.306657] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8802150283c0 state to ffff880026bf3800
>[  506.306659] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff880215be6400
>[  506.306660] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8802150283c0 to [CRTC:25]
>[  506.306661] [drm:drm_atomic_set_fb_for_plane] Set [FB:49] for plane state ffff8802150283c0
>[  506.306662] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c01322c0 state to ffff880026bf3800
>[  506.306664] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3800
>[  506.306665] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c01322c0 to [CRTC:25]
>[  506.306666] [drm:drm_atomic_check_only] checking ffff880026bf3800
>[  506.306668] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  506.306668] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  506.306670] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  506.306671] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  506.306672] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  506.306673] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  506.306674] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3800
>[  506.306675] [drm:drm_atomic_connectors_for_crtc] State ffff880026bf3800 has 1 connectors for [CRTC:25]
>[  506.306677] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3800
>[  506.306679] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  506.306680] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  506.306681] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  506.306682] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  506.306684] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff880215be6400 for pipe B
>[  506.306685] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  506.306686] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  506.306687] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  506.306688] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  506.306690] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  506.306690] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  506.306691] [drm:intel_dump_pipe_config] requested mode:
>[  506.306693] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  506.306694] [drm:intel_dump_pipe_config] adjusted mode:
>[  506.306695] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  506.306697] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  506.306698] [drm:intel_dump_pipe_config] port clock: 270000
>[  506.306698] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  506.306699] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  506.306700] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  506.306702] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  506.306702] [drm:intel_dump_pipe_config] ips: 0
>[  506.306703] [drm:intel_dump_pipe_config] double wide: 0
>[  506.306704] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  506.306705] [drm:intel_dump_pipe_config] planes on this crtc
>[  506.306707] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  506.306708] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  506.306709] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  506.306711] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff880215be4800 state to ffff880026bf3800
>[  506.306712] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff880215be5c00 state to ffff880026bf3800
>[  506.306714] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 49
>[  506.306716] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  506.306717] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff880215028240 state to ffff880026bf3800
>[  506.306719] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff880215028600 state to ffff880026bf3800
>[  506.306720] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff880215028a80 state to ffff880026bf3800
>[  506.306723] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff880215028780 state to ffff880026bf3800
>[  506.306724] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff880215028480 state to ffff880026bf3800
>[  506.306726] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff880215028e40 state to ffff880026bf3800
>[  506.306727] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff880215028b40 state to ffff880026bf3800
>[  506.306728] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff880215028900 state to ffff880026bf3800
>[  506.306730] [drm:drm_atomic_commit] commiting ffff880026bf3800
>[  506.306735] [drm:intel_power_well_enable] enabling display
>[  506.306736] [drm:hsw_set_power_well] Enabling power well
>[  506.308806] [drm:intel_power_well_enable] enabling always-on
>[  506.308816] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  506.308818] [drm:intel_enable_shared_dpll] enabling SPLL
>[  506.309708] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  506.309778] [drm:intel_enable_pipe] enabling pipe B
>[  506.309793] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  506.376662] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  506.376667] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  506.376668] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  506.376670] [drm:check_crtc_state] [CRTC:25]
>[  506.376681] [drm:check_shared_dpll_state] WRPLL 1
>[  506.376682] [drm:check_shared_dpll_state] WRPLL 2
>[  506.376683] [drm:check_shared_dpll_state] SPLL
>[  506.376685] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bf3800
>[  506.376688] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bf3800
>[  506.376715] [drm:drm_mode_setcrtc] [CRTC:25]
>[  506.376717] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bf3800
>[  506.376719] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880215be5000 state to ffff880026bf3800
>[  506.376721] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8800d6c35300 state to ffff880026bf3800
>[  506.376722] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff880215be5000
>[  506.376723] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800d6c35300 to [NOCRTC]
>[  506.376724] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8800d6c35300
>[  506.376726] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3800
>[  506.376727] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c0132280 state to ffff880026bf3800
>[  506.376727] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c0132280 to [NOCRTC]
>[  506.376728] [drm:drm_atomic_check_only] checking ffff880026bf3800
>[  506.376730] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  506.376730] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  506.376732] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  506.376732] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  506.376733] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  506.376734] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  506.376735] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3800
>[  506.376736] [drm:drm_atomic_connectors_for_crtc] State ffff880026bf3800 has 0 connectors for [CRTC:25]
>[  506.376739] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  506.376740] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  506.376742] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8800d6c35e40 state to ffff880026bf3800
>[  506.376743] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8800d6c35840 state to ffff880026bf3800
>[  506.376745] [drm:drm_atomic_commit] commiting ffff880026bf3800
>[  506.393329] [drm:intel_disable_pipe] disabling pipe B
>[  506.428175] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  506.428178] [drm:intel_disable_shared_dpll] disabling SPLL
>[  506.428186] [drm:intel_power_well_disable] disabling display
>[  506.428187] [drm:hsw_set_power_well] Requesting to disable the power well
>[  506.428188] [drm:intel_power_well_disable] disabling always-on
>[  506.428189] [drm:intel_power_well_enable] enabling display
>[  506.428191] [drm:hsw_set_power_well] Enabling power well
>[  506.429468] [drm:intel_power_well_disable] disabling display
>[  506.429471] [drm:hsw_set_power_well] Requesting to disable the power well
>[  506.429477] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  506.429480] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  506.429482] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  506.429485] [drm:check_crtc_state] [CRTC:25]
>[  506.429487] [drm:check_shared_dpll_state] WRPLL 1
>[  506.429488] [drm:check_shared_dpll_state] WRPLL 2
>[  506.429489] [drm:check_shared_dpll_state] SPLL
>[  506.429492] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bf3800
>[  506.429495] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bf3800
>[  506.429520] [drm:drm_mode_setcrtc] [CRTC:25]
>[  506.429523] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  506.429525] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bfba00
>[  506.429528] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880025a40800 state to ffff880026bfba00
>[  506.429530] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8800c78d4840 state to ffff880026bfba00
>[  506.429532] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff880025a40800
>[  506.429533] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800c78d4840 to [CRTC:25]
>[  506.429534] [drm:drm_atomic_set_fb_for_plane] Set [FB:51] for plane state ffff8800c78d4840
>[  506.429535] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8801f442d1a0 state to ffff880026bfba00
>[  506.429537] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfba00
>[  506.429538] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f442d1a0 to [CRTC:25]
>[  506.429540] [drm:drm_atomic_check_only] checking ffff880026bfba00
>[  506.429541] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  506.429542] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  506.429543] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  506.429545] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  506.429546] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  506.429547] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  506.429548] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfba00
>[  506.429549] [drm:drm_atomic_connectors_for_crtc] State ffff880026bfba00 has 1 connectors for [CRTC:25]
>[  506.429551] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfba00
>[  506.429552] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  506.429554] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  506.429556] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  506.429557] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  506.429559] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff880025a40800 for pipe B
>[  506.429559] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  506.429561] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  506.429562] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  506.429563] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  506.429565] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  506.429566] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  506.429567] [drm:intel_dump_pipe_config] requested mode:
>[  506.429569] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  506.429570] [drm:intel_dump_pipe_config] adjusted mode:
>[  506.429572] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  506.429573] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  506.429574] [drm:intel_dump_pipe_config] port clock: 270000
>[  506.429576] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  506.429577] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  506.429578] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  506.429579] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  506.429580] [drm:intel_dump_pipe_config] ips: 0
>[  506.429580] [drm:intel_dump_pipe_config] double wide: 0
>[  506.429581] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  506.429582] [drm:intel_dump_pipe_config] planes on this crtc
>[  506.429584] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  506.429585] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  506.429586] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  506.429587] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff880025a42800 state to ffff880026bfba00
>[  506.429589] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff880025a43c00 state to ffff880026bfba00
>[  506.429591] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 51
>[  506.429592] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  506.429594] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8800c78d4000 state to ffff880026bfba00
>[  506.429595] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8800c78d4e40 state to ffff880026bfba00
>[  506.429596] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8800c78d4cc0 state to ffff880026bfba00
>[  506.429599] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8800c78d49c0 state to ffff880026bfba00
>[  506.429600] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8800c78d4b40 state to ffff880026bfba00
>[  506.429601] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8800c78d4300 state to ffff880026bfba00
>[  506.429603] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8800c78d4600 state to ffff880026bfba00
>[  506.429604] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8800c78d4900 state to ffff880026bfba00
>[  506.429605] [drm:drm_atomic_commit] commiting ffff880026bfba00
>[  506.429610] [drm:intel_power_well_enable] enabling display
>[  506.429611] [drm:hsw_set_power_well] Enabling power well
>[  506.431679] [drm:intel_power_well_enable] enabling always-on
>[  506.431689] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  506.431690] [drm:intel_enable_shared_dpll] enabling SPLL
>[  506.432580] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  506.432644] [drm:intel_enable_pipe] enabling pipe B
>[  506.432658] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  506.499525] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  506.499530] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  506.499531] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  506.499532] [drm:check_crtc_state] [CRTC:25]
>[  506.499543] [drm:check_shared_dpll_state] WRPLL 1
>[  506.499544] [drm:check_shared_dpll_state] WRPLL 2
>[  506.499545] [drm:check_shared_dpll_state] SPLL
>[  506.499547] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bfba00
>[  506.499551] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bfba00
>[  506.499578] [drm:drm_mode_setcrtc] [CRTC:25]
>[  506.499580] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bfba00
>[  506.499582] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880025a43400 state to ffff880026bfba00
>[  506.499584] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8800c78d4c00 state to ffff880026bfba00
>[  506.499584] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff880025a43400
>[  506.499585] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800c78d4c00 to [NOCRTC]
>[  506.499586] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8800c78d4c00
>[  506.499588] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfba00
>[  506.499589] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8801f442d080 state to ffff880026bfba00
>[  506.499590] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f442d080 to [NOCRTC]
>[  506.499591] [drm:drm_atomic_check_only] checking ffff880026bfba00
>[  506.499592] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  506.499593] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  506.499594] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  506.499595] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  506.499596] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  506.499597] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  506.499597] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfba00
>[  506.499599] [drm:drm_atomic_connectors_for_crtc] State ffff880026bfba00 has 0 connectors for [CRTC:25]
>[  506.499601] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  506.499603] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  506.499604] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8800c78d4d80 state to ffff880026bfba00
>[  506.499605] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8800c78d4780 state to ffff880026bfba00
>[  506.499607] [drm:drm_atomic_commit] commiting ffff880026bfba00
>[  506.516191] [drm:intel_disable_pipe] disabling pipe B
>[  506.550272] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  506.550275] [drm:intel_disable_shared_dpll] disabling SPLL
>[  506.550283] [drm:intel_power_well_disable] disabling display
>[  506.550285] [drm:hsw_set_power_well] Requesting to disable the power well
>[  506.550286] [drm:intel_power_well_disable] disabling always-on
>[  506.550287] [drm:intel_power_well_enable] enabling display
>[  506.550288] [drm:hsw_set_power_well] Enabling power well
>[  506.552357] [drm:intel_power_well_disable] disabling display
>[  506.552360] [drm:hsw_set_power_well] Requesting to disable the power well
>[  506.552365] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  506.552368] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  506.552369] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  506.552372] [drm:check_crtc_state] [CRTC:25]
>[  506.552373] [drm:check_shared_dpll_state] WRPLL 1
>[  506.552374] [drm:check_shared_dpll_state] WRPLL 2
>[  506.552375] [drm:check_shared_dpll_state] SPLL
>[  506.552377] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bfba00
>[  506.552379] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bfba00
>[  506.552408] [drm:drm_mode_setcrtc] [CRTC:25]
>[  506.552411] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  506.552413] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bf3c00
>[  506.552415] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880215be4400 state to ffff880026bf3c00
>[  506.552417] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8800d6c35b40 state to ffff880026bf3c00
>[  506.552418] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff880215be4400
>[  506.552419] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800d6c35b40 to [CRTC:25]
>[  506.552420] [drm:drm_atomic_set_fb_for_plane] Set [FB:49] for plane state ffff8800d6c35b40
>[  506.552421] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c0132a20 state to ffff880026bf3c00
>[  506.552422] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3c00
>[  506.552423] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c0132a20 to [CRTC:25]
>[  506.552424] [drm:drm_atomic_check_only] checking ffff880026bf3c00
>[  506.552426] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  506.552426] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  506.552428] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  506.552429] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  506.552430] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  506.552431] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  506.552431] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3c00
>[  506.552433] [drm:drm_atomic_connectors_for_crtc] State ffff880026bf3c00 has 1 connectors for [CRTC:25]
>[  506.552434] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3c00
>[  506.552435] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  506.552436] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  506.552438] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  506.552439] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  506.552440] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff880215be4400 for pipe B
>[  506.552441] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  506.552442] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  506.552443] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  506.552444] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  506.552445] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  506.552446] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  506.552446] [drm:intel_dump_pipe_config] requested mode:
>[  506.552448] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  506.552449] [drm:intel_dump_pipe_config] adjusted mode:
>[  506.552450] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  506.552451] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  506.552452] [drm:intel_dump_pipe_config] port clock: 270000
>[  506.552453] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  506.552454] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  506.552455] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  506.552455] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  506.552456] [drm:intel_dump_pipe_config] ips: 0
>[  506.552457] [drm:intel_dump_pipe_config] double wide: 0
>[  506.552458] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  506.552459] [drm:intel_dump_pipe_config] planes on this crtc
>[  506.552460] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  506.552461] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  506.552462] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  506.552463] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff880215be4000 state to ffff880026bf3c00
>[  506.552465] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff880215be5c00 state to ffff880026bf3c00
>[  506.552467] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 49
>[  506.552468] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  506.552469] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8800d6c35000 state to ffff880026bf3c00
>[  506.552471] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8800d6c35600 state to ffff880026bf3c00
>[  506.552472] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8800d6c35900 state to ffff880026bf3c00
>[  506.552474] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8800d6c35d80 state to ffff880026bf3c00
>[  506.552476] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8800d6c356c0 state to ffff880026bf3c00
>[  506.552477] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8800d6c35480 state to ffff880026bf3c00
>[  506.552478] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8800d6c35a80 state to ffff880026bf3c00
>[  506.552479] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8800d6c35540 state to ffff880026bf3c00
>[  506.552481] [drm:drm_atomic_commit] commiting ffff880026bf3c00
>[  506.552486] [drm:intel_power_well_enable] enabling display
>[  506.552487] [drm:hsw_set_power_well] Enabling power well
>[  506.554554] [drm:intel_power_well_enable] enabling always-on
>[  506.554565] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  506.554566] [drm:intel_enable_shared_dpll] enabling SPLL
>[  506.555455] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  506.555519] [drm:intel_enable_pipe] enabling pipe B
>[  506.555533] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  506.624304] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  506.624308] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  506.624309] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  506.624311] [drm:check_crtc_state] [CRTC:25]
>[  506.624321] [drm:check_shared_dpll_state] WRPLL 1
>[  506.624322] [drm:check_shared_dpll_state] WRPLL 2
>[  506.624323] [drm:check_shared_dpll_state] SPLL
>[  506.624325] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bf3c00
>[  506.624328] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bf3c00
>[  506.624355] [drm:drm_mode_setcrtc] [CRTC:25]
>[  506.624357] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bfb400
>[  506.624359] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880025a43c00 state to ffff880026bfb400
>[  506.624361] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8800c78d4900 state to ffff880026bfb400
>[  506.624362] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff880025a43c00
>[  506.624363] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800c78d4900 to [NOCRTC]
>[  506.624364] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8800c78d4900
>[  506.624365] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfb400
>[  506.624366] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8801f442d040 state to ffff880026bfb400
>[  506.624367] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f442d040 to [NOCRTC]
>[  506.624368] [drm:drm_atomic_check_only] checking ffff880026bfb400
>[  506.624369] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  506.624370] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  506.624371] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  506.624372] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  506.624373] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  506.624374] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  506.624375] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfb400
>[  506.624376] [drm:drm_atomic_connectors_for_crtc] State ffff880026bfb400 has 0 connectors for [CRTC:25]
>[  506.624379] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  506.624380] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  506.624381] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8800c78d4600 state to ffff880026bfb400
>[  506.624382] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8800c78d4300 state to ffff880026bfb400
>[  506.624384] [drm:drm_atomic_commit] commiting ffff880026bfb400
>[  506.640969] [drm:intel_disable_pipe] disabling pipe B
>[  506.676100] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  506.676103] [drm:intel_disable_shared_dpll] disabling SPLL
>[  506.676111] [drm:intel_power_well_disable] disabling display
>[  506.676113] [drm:hsw_set_power_well] Requesting to disable the power well
>[  506.676114] [drm:intel_power_well_disable] disabling always-on
>[  506.676115] [drm:intel_power_well_enable] enabling display
>[  506.676116] [drm:hsw_set_power_well] Enabling power well
>[  506.677446] [drm:intel_power_well_disable] disabling display
>[  506.677450] [drm:hsw_set_power_well] Requesting to disable the power well
>[  506.677456] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  506.677459] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  506.677460] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  506.677463] [drm:check_crtc_state] [CRTC:25]
>[  506.677465] [drm:check_shared_dpll_state] WRPLL 1
>[  506.677467] [drm:check_shared_dpll_state] WRPLL 2
>[  506.677468] [drm:check_shared_dpll_state] SPLL
>[  506.677470] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bfb400
>[  506.677472] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bfb400
>[  506.677497] [drm:drm_mode_setcrtc] [CRTC:25]
>[  506.677501] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  506.677503] [drm:drm_atomic_state_init] Allocated atomic state ffff880210d7b400
>[  506.677506] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5492c00 state to ffff880210d7b400
>[  506.677507] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f5fde000 state to ffff880210d7b400
>[  506.677509] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f5492c00
>[  506.677510] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f5fde000 to [CRTC:25]
>[  506.677511] [drm:drm_atomic_set_fb_for_plane] Set [FB:51] for plane state ffff8801f5fde000
>[  506.677513] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800d3bba980 state to ffff880210d7b400
>[  506.677514] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b400
>[  506.677516] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800d3bba980 to [CRTC:25]
>[  506.677516] [drm:drm_atomic_check_only] checking ffff880210d7b400
>[  506.677518] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  506.677519] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  506.677521] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  506.677522] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  506.677523] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  506.677524] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  506.677525] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b400
>[  506.677528] [drm:drm_atomic_connectors_for_crtc] State ffff880210d7b400 has 1 connectors for [CRTC:25]
>[  506.677529] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b400
>[  506.677530] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  506.677532] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  506.677533] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  506.677535] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  506.677537] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff8801f5492c00 for pipe B
>[  506.677538] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  506.677538] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  506.677540] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  506.677542] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  506.677543] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  506.677544] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  506.677545] [drm:intel_dump_pipe_config] requested mode:
>[  506.677546] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  506.677548] [drm:intel_dump_pipe_config] adjusted mode:
>[  506.677549] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  506.677551] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  506.677552] [drm:intel_dump_pipe_config] port clock: 270000
>[  506.677553] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  506.677554] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  506.677555] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  506.677556] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  506.677558] [drm:intel_dump_pipe_config] ips: 0
>[  506.677559] [drm:intel_dump_pipe_config] double wide: 0
>[  506.677560] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  506.677560] [drm:intel_dump_pipe_config] planes on this crtc
>[  506.677561] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  506.677562] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  506.677564] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  506.677566] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff8801f5490800 state to ffff880210d7b400
>[  506.677567] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff8801f5490c00 state to ffff880210d7b400
>[  506.677569] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 51
>[  506.677570] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  506.677571] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8801f5fde180 state to ffff880210d7b400
>[  506.677573] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8801f5fdea80 state to ffff880210d7b400
>[  506.677574] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8801f5fded80 state to ffff880210d7b400
>[  506.677577] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f5fdecc0 state to ffff880210d7b400
>[  506.677578] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f5fde0c0 state to ffff880210d7b400
>[  506.677580] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8801f5fde540 state to ffff880210d7b400
>[  506.677581] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8801f5fde3c0 state to ffff880210d7b400
>[  506.677582] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8801f5fdee40 state to ffff880210d7b400
>[  506.677583] [drm:drm_atomic_commit] commiting ffff880210d7b400
>[  506.677588] [drm:intel_power_well_enable] enabling display
>[  506.677589] [drm:hsw_set_power_well] Enabling power well
>[  506.679656] [drm:intel_power_well_enable] enabling always-on
>[  506.679667] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  506.679668] [drm:intel_enable_shared_dpll] enabling SPLL
>[  506.680557] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  506.680621] [drm:intel_enable_pipe] enabling pipe B
>[  506.680635] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  506.747501] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  506.747506] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  506.747507] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  506.747509] [drm:check_crtc_state] [CRTC:25]
>[  506.747520] [drm:check_shared_dpll_state] WRPLL 1
>[  506.747521] [drm:check_shared_dpll_state] WRPLL 2
>[  506.747522] [drm:check_shared_dpll_state] SPLL
>[  506.747524] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880210d7b400
>[  506.747528] [drm:drm_atomic_state_free] Freeing atomic state ffff880210d7b400
>[  506.747555] [drm:drm_mode_setcrtc] [CRTC:25]
>[  506.747556] [drm:drm_atomic_state_init] Allocated atomic state ffff880210d7b400
>[  506.747559] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5493800 state to ffff880210d7b400
>[  506.747560] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f5fde480 state to ffff880210d7b400
>[  506.747561] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f5493800
>[  506.747562] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f5fde480 to [NOCRTC]
>[  506.747563] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f5fde480
>[  506.747564] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b400
>[  506.747565] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800d3bba940 state to ffff880210d7b400
>[  506.747566] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800d3bba940 to [NOCRTC]
>[  506.747567] [drm:drm_atomic_check_only] checking ffff880210d7b400
>[  506.747568] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  506.747569] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  506.747570] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  506.747571] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  506.747572] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  506.747573] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  506.747574] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b400
>[  506.747575] [drm:drm_atomic_connectors_for_crtc] State ffff880210d7b400 has 0 connectors for [CRTC:25]
>[  506.747578] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  506.747579] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  506.747581] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f5fde840 state to ffff880210d7b400
>[  506.747582] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f5fde600 state to ffff880210d7b400
>[  506.747584] [drm:drm_atomic_commit] commiting ffff880210d7b400
>[  506.764168] [drm:intel_disable_pipe] disabling pipe B
>[  506.798502] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  506.798504] [drm:intel_disable_shared_dpll] disabling SPLL
>[  506.798513] [drm:intel_power_well_disable] disabling display
>[  506.798514] [drm:hsw_set_power_well] Requesting to disable the power well
>[  506.798515] [drm:intel_power_well_disable] disabling always-on
>[  506.798517] [drm:intel_power_well_enable] enabling display
>[  506.798518] [drm:hsw_set_power_well] Enabling power well
>[  506.800587] [drm:intel_power_well_disable] disabling display
>[  506.800591] [drm:hsw_set_power_well] Requesting to disable the power well
>[  506.800596] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  506.800599] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  506.800600] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  506.800603] [drm:check_crtc_state] [CRTC:25]
>[  506.800604] [drm:check_shared_dpll_state] WRPLL 1
>[  506.800605] [drm:check_shared_dpll_state] WRPLL 2
>[  506.800606] [drm:check_shared_dpll_state] SPLL
>[  506.800608] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880210d7b400
>[  506.800611] [drm:drm_atomic_state_free] Freeing atomic state ffff880210d7b400
>[  506.800639] [drm:drm_mode_setcrtc] [CRTC:25]
>[  506.800642] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  506.800645] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bf3c00
>[  506.800647] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880215be5000 state to ffff880026bf3c00
>[  506.800648] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8800d6c35180 state to ffff880026bf3c00
>[  506.800649] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff880215be5000
>[  506.800650] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800d6c35180 to [CRTC:25]
>[  506.800652] [drm:drm_atomic_set_fb_for_plane] Set [FB:49] for plane state ffff8800d6c35180
>[  506.800653] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c0132d60 state to ffff880026bf3c00
>[  506.800654] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3c00
>[  506.800655] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c0132d60 to [CRTC:25]
>[  506.800656] [drm:drm_atomic_check_only] checking ffff880026bf3c00
>[  506.800658] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  506.800658] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  506.800659] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  506.800661] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  506.800661] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  506.800662] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  506.800663] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3c00
>[  506.800664] [drm:drm_atomic_connectors_for_crtc] State ffff880026bf3c00 has 1 connectors for [CRTC:25]
>[  506.800666] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3c00
>[  506.800667] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  506.800668] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  506.800670] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  506.800671] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  506.800672] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff880215be5000 for pipe B
>[  506.800673] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  506.800673] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  506.800675] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  506.800676] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  506.800677] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  506.800678] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  506.800678] [drm:intel_dump_pipe_config] requested mode:
>[  506.800680] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  506.800681] [drm:intel_dump_pipe_config] adjusted mode:
>[  506.800682] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  506.800683] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  506.800684] [drm:intel_dump_pipe_config] port clock: 270000
>[  506.800685] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  506.800685] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  506.800686] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  506.800688] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  506.800688] [drm:intel_dump_pipe_config] ips: 0
>[  506.800689] [drm:intel_dump_pipe_config] double wide: 0
>[  506.800690] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  506.800691] [drm:intel_dump_pipe_config] planes on this crtc
>[  506.800692] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  506.800693] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  506.800694] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  506.800696] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff880215be4800 state to ffff880026bf3c00
>[  506.800697] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff880215be6400 state to ffff880026bf3c00
>[  506.800699] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 49
>[  506.800700] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  506.800701] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8800d6c359c0 state to ffff880026bf3c00
>[  506.800703] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8800d6c35240 state to ffff880026bf3c00
>[  506.800704] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8800d6c35540 state to ffff880026bf3c00
>[  506.800707] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8800d6c35a80 state to ffff880026bf3c00
>[  506.800708] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8800d6c35480 state to ffff880026bf3c00
>[  506.800709] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8800d6c35900 state to ffff880026bf3c00
>[  506.800711] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8800d6c35600 state to ffff880026bf3c00
>[  506.800712] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8800d6c35000 state to ffff880026bf3c00
>[  506.800713] [drm:drm_atomic_commit] commiting ffff880026bf3c00
>[  506.800718] [drm:intel_power_well_enable] enabling display
>[  506.800719] [drm:hsw_set_power_well] Enabling power well
>[  506.802787] [drm:intel_power_well_enable] enabling always-on
>[  506.802797] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  506.802798] [drm:intel_enable_shared_dpll] enabling SPLL
>[  506.803688] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  506.803752] [drm:intel_enable_pipe] enabling pipe B
>[  506.803766] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  506.870639] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  506.870644] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  506.870646] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  506.870648] [drm:check_crtc_state] [CRTC:25]
>[  506.870660] [drm:check_shared_dpll_state] WRPLL 1
>[  506.870661] [drm:check_shared_dpll_state] WRPLL 2
>[  506.870662] [drm:check_shared_dpll_state] SPLL
>[  506.870665] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bf3c00
>[  506.870669] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bf3c00
>[  506.870699] [drm:drm_mode_setcrtc] [CRTC:25]
>[  506.870702] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bf3c00
>[  506.870704] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880215be5c00 state to ffff880026bf3c00
>[  506.870706] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8800d6c356c0 state to ffff880026bf3c00
>[  506.870707] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff880215be5c00
>[  506.870708] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800d6c356c0 to [NOCRTC]
>[  506.870710] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8800d6c356c0
>[  506.870711] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3c00
>[  506.870712] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c0132e20 state to ffff880026bf3c00
>[  506.870714] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c0132e20 to [NOCRTC]
>[  506.870715] [drm:drm_atomic_check_only] checking ffff880026bf3c00
>[  506.870716] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  506.870717] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  506.870719] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  506.870720] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  506.870721] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  506.870722] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  506.870723] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3c00
>[  506.870725] [drm:drm_atomic_connectors_for_crtc] State ffff880026bf3c00 has 0 connectors for [CRTC:25]
>[  506.870728] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  506.870729] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  506.870731] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8800d6c35d80 state to ffff880026bf3c00
>[  506.870733] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8800d6c35b40 state to ffff880026bf3c00
>[  506.870735] [drm:drm_atomic_commit] commiting ffff880026bf3c00
>[  506.883525] [drm:intel_print_rc6_info] Enabling RC6 states: RC6 on
>[  506.887293] [drm:intel_disable_pipe] disabling pipe B
>[  506.887381] [drm:gen6_enable_rps] Overclocking supported. Max: 1100MHz, Overclock max: 1100MHz
>[  506.921667] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  506.921670] [drm:intel_disable_shared_dpll] disabling SPLL
>[  506.921678] [drm:intel_power_well_disable] disabling display
>[  506.921679] [drm:hsw_set_power_well] Requesting to disable the power well
>[  506.921680] [drm:intel_power_well_disable] disabling always-on
>[  506.921682] [drm:intel_power_well_enable] enabling display
>[  506.921683] [drm:hsw_set_power_well] Enabling power well
>[  506.923752] [drm:intel_power_well_disable] disabling display
>[  506.923755] [drm:hsw_set_power_well] Requesting to disable the power well
>[  506.923761] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  506.923763] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  506.923764] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  506.923767] [drm:check_crtc_state] [CRTC:25]
>[  506.923768] [drm:check_shared_dpll_state] WRPLL 1
>[  506.923769] [drm:check_shared_dpll_state] WRPLL 2
>[  506.923770] [drm:check_shared_dpll_state] SPLL
>[  506.923772] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bf3c00
>[  506.923774] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bf3c00
>[  506.923802] [drm:drm_mode_setcrtc] [CRTC:25]
>[  506.923805] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  506.923807] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bf3c00
>[  506.923808] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880215be5000 state to ffff880026bf3c00
>[  506.923810] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8800d6c35480 state to ffff880026bf3c00
>[  506.923811] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff880215be5000
>[  506.923812] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800d6c35480 to [CRTC:25]
>[  506.923813] [drm:drm_atomic_set_fb_for_plane] Set [FB:51] for plane state ffff8800d6c35480
>[  506.923814] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c0132d60 state to ffff880026bf3c00
>[  506.923815] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3c00
>[  506.923816] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c0132d60 to [CRTC:25]
>[  506.923817] [drm:drm_atomic_check_only] checking ffff880026bf3c00
>[  506.923819] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  506.923819] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  506.923820] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  506.923822] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  506.923822] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  506.923823] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  506.923824] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3c00
>[  506.923826] [drm:drm_atomic_connectors_for_crtc] State ffff880026bf3c00 has 1 connectors for [CRTC:25]
>[  506.923827] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3c00
>[  506.923828] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  506.923829] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  506.923831] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  506.923832] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  506.923833] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff880215be5000 for pipe B
>[  506.923834] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  506.923835] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  506.923836] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  506.923837] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  506.923838] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  506.923839] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  506.923839] [drm:intel_dump_pipe_config] requested mode:
>[  506.923841] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  506.923842] [drm:intel_dump_pipe_config] adjusted mode:
>[  506.923843] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  506.923844] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  506.923845] [drm:intel_dump_pipe_config] port clock: 270000
>[  506.923846] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  506.923847] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  506.923847] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  506.923849] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  506.923849] [drm:intel_dump_pipe_config] ips: 0
>[  506.923850] [drm:intel_dump_pipe_config] double wide: 0
>[  506.923851] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  506.923852] [drm:intel_dump_pipe_config] planes on this crtc
>[  506.923853] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  506.923854] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  506.923855] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  506.923857] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff880215be4000 state to ffff880026bf3c00
>[  506.923858] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff880215be4400 state to ffff880026bf3c00
>[  506.923860] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 51
>[  506.923861] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  506.923862] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8800d6c35180 state to ffff880026bf3c00
>[  506.923863] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8800d6c35f00 state to ffff880026bf3c00
>[  506.923865] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8800d6c35780 state to ffff880026bf3c00
>[  506.923867] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8800d6c35840 state to ffff880026bf3c00
>[  506.923868] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8800d6c35e40 state to ffff880026bf3c00
>[  506.923870] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8800d6c35300 state to ffff880026bf3c00
>[  506.923871] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff880201584600 state to ffff880026bf3c00
>[  506.923873] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff880201584d80 state to ffff880026bf3c00
>[  506.923874] [drm:drm_atomic_commit] commiting ffff880026bf3c00
>[  506.923879] [drm:intel_power_well_enable] enabling display
>[  506.923880] [drm:hsw_set_power_well] Enabling power well
>[  506.925424] [drm:intel_power_well_enable] enabling always-on
>[  506.925435] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  506.925437] [drm:intel_enable_shared_dpll] enabling SPLL
>[  506.926326] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  506.926390] [drm:intel_enable_pipe] enabling pipe B
>[  506.926403] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  506.993271] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  506.993275] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  506.993277] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  506.993278] [drm:check_crtc_state] [CRTC:25]
>[  506.993289] [drm:check_shared_dpll_state] WRPLL 1
>[  506.993290] [drm:check_shared_dpll_state] WRPLL 2
>[  506.993291] [drm:check_shared_dpll_state] SPLL
>[  506.993293] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bf3c00
>[  506.993297] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bf3c00
>[  506.993325] [drm:drm_mode_setcrtc] [CRTC:25]
>[  506.993347] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bfa400
>[  506.993349] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880025a43400 state to ffff880026bfa400
>[  506.993351] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8800c78d4780 state to ffff880026bfa400
>[  506.993352] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff880025a43400
>[  506.993353] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800c78d4780 to [NOCRTC]
>[  506.993354] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8800c78d4780
>[  506.993355] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfa400
>[  506.993357] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8801f442d0c0 state to ffff880026bfa400
>[  506.993358] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f442d0c0 to [NOCRTC]
>[  506.993358] [drm:drm_atomic_check_only] checking ffff880026bfa400
>[  506.993361] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  506.993361] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  506.993362] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  506.993363] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  506.993365] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  506.993366] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  506.993367] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfa400
>[  506.993368] [drm:drm_atomic_connectors_for_crtc] State ffff880026bfa400 has 0 connectors for [CRTC:25]
>[  506.993371] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  506.993372] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  506.993374] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8800c78d4d80 state to ffff880026bfa400
>[  506.993375] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8800c78d4c00 state to ffff880026bfa400
>[  506.993377] [drm:drm_atomic_commit] commiting ffff880026bfa400
>[  507.009939] [drm:intel_disable_pipe] disabling pipe B
>[  507.044407] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  507.044410] [drm:intel_disable_shared_dpll] disabling SPLL
>[  507.044418] [drm:intel_power_well_disable] disabling display
>[  507.044420] [drm:hsw_set_power_well] Requesting to disable the power well
>[  507.044421] [drm:intel_power_well_disable] disabling always-on
>[  507.044429] [drm:intel_runtime_suspend] Suspending device
>[  507.044528] [drm:hsw_enable_pc8] Enabling package C8+
>[  507.059030] [drm:intel_runtime_suspend] Device suspended
>[  507.065414] [drm:intel_runtime_resume] Resuming device
>[  507.067483] [drm:hsw_disable_pc8] Disabling package C8+
>[  507.071420] [drm:intel_update_cdclk] Current CD clock rate: 540000 kHz
>[  507.184660] [drm:intel_runtime_resume] Device resumed
>[  507.184664] [drm:intel_power_well_enable] enabling display
>[  507.184666] [drm:hsw_set_power_well] Enabling power well
>[  507.186735] [drm:intel_power_well_disable] disabling display
>[  507.186739] [drm:hsw_set_power_well] Requesting to disable the power well
>[  507.186744] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  507.186746] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  507.186748] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  507.186750] [drm:check_crtc_state] [CRTC:25]
>[  507.186752] [drm:check_shared_dpll_state] WRPLL 1
>[  507.186753] [drm:check_shared_dpll_state] WRPLL 2
>[  507.186754] [drm:check_shared_dpll_state] SPLL
>[  507.186756] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bfa400
>[  507.186758] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bfa400
>[  507.186786] [drm:drm_mode_setcrtc] [CRTC:25]
>[  507.186789] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  507.186791] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bf3800
>[  507.186793] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880215be5000 state to ffff880026bf3800
>[  507.186795] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8800260d4a80 state to ffff880026bf3800
>[  507.186797] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff880215be5000
>[  507.186798] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800260d4a80 to [CRTC:25]
>[  507.186799] [drm:drm_atomic_set_fb_for_plane] Set [FB:49] for plane state ffff8800260d4a80
>[  507.186800] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c01327a0 state to ffff880026bf3800
>[  507.186801] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3800
>[  507.186802] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c01327a0 to [CRTC:25]
>[  507.186803] [drm:drm_atomic_check_only] checking ffff880026bf3800
>[  507.186805] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  507.186805] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  507.186806] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  507.186808] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  507.186808] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  507.186809] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  507.186810] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3800
>[  507.186811] [drm:drm_atomic_connectors_for_crtc] State ffff880026bf3800 has 1 connectors for [CRTC:25]
>[  507.186813] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3800
>[  507.186814] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  507.186815] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  507.186816] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  507.186817] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  507.186819] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff880215be5000 for pipe B
>[  507.186820] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  507.186820] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  507.186822] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  507.186823] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  507.186824] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  507.186825] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  507.186825] [drm:intel_dump_pipe_config] requested mode:
>[  507.186827] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  507.186828] [drm:intel_dump_pipe_config] adjusted mode:
>[  507.186829] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  507.186830] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  507.186831] [drm:intel_dump_pipe_config] port clock: 270000
>[  507.186832] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  507.186833] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  507.186833] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  507.186834] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  507.186835] [drm:intel_dump_pipe_config] ips: 0
>[  507.186836] [drm:intel_dump_pipe_config] double wide: 0
>[  507.186837] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  507.186838] [drm:intel_dump_pipe_config] planes on this crtc
>[  507.186839] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  507.186840] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  507.186841] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  507.186842] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff880215be6400 state to ffff880026bf3800
>[  507.186844] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff880215be5c00 state to ffff880026bf3800
>[  507.186846] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 49
>[  507.186847] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  507.186848] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8800260d4900 state to ffff880026bf3800
>[  507.186849] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8800260d4d80 state to ffff880026bf3800
>[  507.186851] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff880201486900 state to ffff880026bf3800
>[  507.186853] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff880201486a80 state to ffff880026bf3800
>[  507.186854] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8802014863c0 state to ffff880026bf3800
>[  507.186856] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8802014860c0 state to ffff880026bf3800
>[  507.186857] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8801f550ccc0 state to ffff880026bf3800
>[  507.186859] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8801f550ce40 state to ffff880026bf3800
>[  507.186860] [drm:drm_atomic_commit] commiting ffff880026bf3800
>[  507.186864] [drm:intel_power_well_enable] enabling display
>[  507.186866] [drm:hsw_set_power_well] Enabling power well
>[  507.188935] [drm:intel_power_well_enable] enabling always-on
>[  507.188946] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  507.188947] [drm:intel_enable_shared_dpll] enabling SPLL
>[  507.189836] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  507.189900] [drm:intel_enable_pipe] enabling pipe B
>[  507.189913] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  507.256781] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  507.256785] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  507.256786] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  507.256788] [drm:check_crtc_state] [CRTC:25]
>[  507.256800] [drm:check_shared_dpll_state] WRPLL 1
>[  507.256801] [drm:check_shared_dpll_state] WRPLL 2
>[  507.256801] [drm:check_shared_dpll_state] SPLL
>[  507.256803] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bf3800
>[  507.256807] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bf3800
>[  507.256834] [drm:drm_mode_setcrtc] [CRTC:25]
>[  507.256835] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bf3800
>[  507.256837] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880215be4400 state to ffff880026bf3800
>[  507.256839] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f550ca80 state to ffff880026bf3800
>[  507.256840] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff880215be4400
>[  507.256841] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f550ca80 to [NOCRTC]
>[  507.256842] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f550ca80
>[  507.256843] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3800
>[  507.256844] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c0132900 state to ffff880026bf3800
>[  507.256845] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c0132900 to [NOCRTC]
>[  507.256846] [drm:drm_atomic_check_only] checking ffff880026bf3800
>[  507.256847] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  507.256848] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  507.256849] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  507.256850] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  507.256850] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  507.256851] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  507.256852] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3800
>[  507.256854] [drm:drm_atomic_connectors_for_crtc] State ffff880026bf3800 has 0 connectors for [CRTC:25]
>[  507.256856] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  507.256857] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  507.256859] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f550c780 state to ffff880026bf3800
>[  507.256860] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f550c3c0 state to ffff880026bf3800
>[  507.256862] [drm:drm_atomic_commit] commiting ffff880026bf3800
>[  507.273448] [drm:intel_disable_pipe] disabling pipe B
>[  507.308369] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  507.308372] [drm:intel_disable_shared_dpll] disabling SPLL
>[  507.308380] [drm:intel_power_well_disable] disabling display
>[  507.308382] [drm:hsw_set_power_well] Requesting to disable the power well
>[  507.308383] [drm:intel_power_well_disable] disabling always-on
>[  507.308384] [drm:intel_power_well_enable] enabling display
>[  507.308385] [drm:hsw_set_power_well] Enabling power well
>[  507.310455] [drm:intel_power_well_disable] disabling display
>[  507.310459] [drm:hsw_set_power_well] Requesting to disable the power well
>[  507.310464] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  507.310467] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  507.310468] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  507.310471] [drm:check_crtc_state] [CRTC:25]
>[  507.310472] [drm:check_shared_dpll_state] WRPLL 1
>[  507.310473] [drm:check_shared_dpll_state] WRPLL 2
>[  507.310474] [drm:check_shared_dpll_state] SPLL
>[  507.310476] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bf3800
>[  507.310479] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bf3800
>[  507.310507] [drm:drm_mode_setcrtc] [CRTC:25]
>[  507.310510] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  507.310512] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bfa200
>[  507.310514] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880025a42800 state to ffff880026bfa200
>[  507.310515] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8800c78d4cc0 state to ffff880026bfa200
>[  507.310517] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff880025a42800
>[  507.310518] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800c78d4cc0 to [CRTC:25]
>[  507.310519] [drm:drm_atomic_set_fb_for_plane] Set [FB:51] for plane state ffff8800c78d4cc0
>[  507.310520] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8801f442d520 state to ffff880026bfa200
>[  507.310521] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfa200
>[  507.310522] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f442d520 to [CRTC:25]
>[  507.310523] [drm:drm_atomic_check_only] checking ffff880026bfa200
>[  507.310525] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  507.310525] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  507.310526] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  507.310528] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  507.310529] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  507.310530] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  507.310530] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfa200
>[  507.310532] [drm:drm_atomic_connectors_for_crtc] State ffff880026bfa200 has 1 connectors for [CRTC:25]
>[  507.310533] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfa200
>[  507.310534] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  507.310535] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  507.310537] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  507.310538] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  507.310539] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff880025a42800 for pipe B
>[  507.310540] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  507.310541] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  507.310542] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  507.310543] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  507.310544] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  507.310545] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  507.310545] [drm:intel_dump_pipe_config] requested mode:
>[  507.310547] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  507.310548] [drm:intel_dump_pipe_config] adjusted mode:
>[  507.310549] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  507.310550] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  507.310551] [drm:intel_dump_pipe_config] port clock: 270000
>[  507.310552] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  507.310552] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  507.310553] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  507.310555] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  507.310555] [drm:intel_dump_pipe_config] ips: 0
>[  507.310556] [drm:intel_dump_pipe_config] double wide: 0
>[  507.310557] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  507.310558] [drm:intel_dump_pipe_config] planes on this crtc
>[  507.310559] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  507.310560] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  507.310561] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  507.310563] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff880025a40c00 state to ffff880026bfa200
>[  507.310564] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff880025a43400 state to ffff880026bfa200
>[  507.310566] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 51
>[  507.310567] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  507.310569] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8800c78d4000 state to ffff880026bfa200
>[  507.310570] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8800c78d4240 state to ffff880026bfa200
>[  507.310571] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8800c78d4a80 state to ffff880026bfa200
>[  507.310574] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8800c78d40c0 state to ffff880026bfa200
>[  507.310575] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8800c78d46c0 state to ffff880026bfa200
>[  507.310577] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8800c78d4540 state to ffff880026bfa200
>[  507.310578] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8800c78d4480 state to ffff880026bfa200
>[  507.310579] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8800c78d4c00 state to ffff880026bfa200
>[  507.310580] [drm:drm_atomic_commit] commiting ffff880026bfa200
>[  507.310585] [drm:intel_power_well_enable] enabling display
>[  507.310586] [drm:hsw_set_power_well] Enabling power well
>[  507.312654] [drm:intel_power_well_enable] enabling always-on
>[  507.312664] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  507.312666] [drm:intel_enable_shared_dpll] enabling SPLL
>[  507.313556] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  507.313621] [drm:intel_enable_pipe] enabling pipe B
>[  507.313635] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  507.380503] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  507.380507] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  507.380508] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  507.380510] [drm:check_crtc_state] [CRTC:25]
>[  507.380522] [drm:check_shared_dpll_state] WRPLL 1
>[  507.380523] [drm:check_shared_dpll_state] WRPLL 2
>[  507.380524] [drm:check_shared_dpll_state] SPLL
>[  507.380525] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bfa200
>[  507.380529] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bfa200
>[  507.380556] [drm:drm_mode_setcrtc] [CRTC:25]
>[  507.380558] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bfa200
>[  507.380560] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880025a43c00 state to ffff880026bfa200
>[  507.380561] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8800c78d4d80 state to ffff880026bfa200
>[  507.380562] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff880025a43c00
>[  507.380563] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800c78d4d80 to [NOCRTC]
>[  507.380564] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8800c78d4d80
>[  507.380566] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfa200
>[  507.380567] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8801f442d220 state to ffff880026bfa200
>[  507.380568] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f442d220 to [NOCRTC]
>[  507.380569] [drm:drm_atomic_check_only] checking ffff880026bfa200
>[  507.380570] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  507.380571] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  507.380572] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  507.380573] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  507.380574] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  507.380575] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  507.380576] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfa200
>[  507.380577] [drm:drm_atomic_connectors_for_crtc] State ffff880026bfa200 has 0 connectors for [CRTC:25]
>[  507.380580] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  507.380581] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  507.380583] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8800c78d4780 state to ffff880026bfa200
>[  507.380584] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8800c78d4300 state to ffff880026bfa200
>[  507.380586] [drm:drm_atomic_commit] commiting ffff880026bfa200
>[  507.397168] [drm:intel_disable_pipe] disabling pipe B
>[  507.431961] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  507.431965] [drm:intel_disable_shared_dpll] disabling SPLL
>[  507.431973] [drm:intel_power_well_disable] disabling display
>[  507.431975] [drm:hsw_set_power_well] Requesting to disable the power well
>[  507.431976] [drm:intel_power_well_disable] disabling always-on
>[  507.431977] [drm:intel_power_well_enable] enabling display
>[  507.431978] [drm:hsw_set_power_well] Enabling power well
>[  507.433379] [drm:intel_power_well_disable] disabling display
>[  507.433383] [drm:hsw_set_power_well] Requesting to disable the power well
>[  507.433389] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  507.433392] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  507.433393] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  507.433396] [drm:check_crtc_state] [CRTC:25]
>[  507.433398] [drm:check_shared_dpll_state] WRPLL 1
>[  507.433399] [drm:check_shared_dpll_state] WRPLL 2
>[  507.433400] [drm:check_shared_dpll_state] SPLL
>[  507.433402] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bfa200
>[  507.433405] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bfa200
>[  507.433431] [drm:drm_mode_setcrtc] [CRTC:25]
>[  507.433434] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  507.433436] [drm:drm_atomic_state_init] Allocated atomic state ffff88020103ce00
>[  507.433439] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5326400 state to ffff88020103ce00
>[  507.433441] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f55afc00 state to ffff88020103ce00
>[  507.433443] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f5326400
>[  507.433444] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55afc00 to [CRTC:25]
>[  507.433446] [drm:drm_atomic_set_fb_for_plane] Set [FB:49] for plane state ffff8801f55afc00
>[  507.433447] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c909b360 state to ffff88020103ce00
>[  507.433449] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103ce00
>[  507.433450] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c909b360 to [CRTC:25]
>[  507.433451] [drm:drm_atomic_check_only] checking ffff88020103ce00
>[  507.433453] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  507.433455] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  507.433456] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  507.433457] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  507.433458] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  507.433459] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  507.433460] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103ce00
>[  507.433462] [drm:drm_atomic_connectors_for_crtc] State ffff88020103ce00 has 1 connectors for [CRTC:25]
>[  507.433464] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103ce00
>[  507.433465] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  507.433466] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  507.433468] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  507.433469] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  507.433471] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff8801f5326400 for pipe B
>[  507.433472] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  507.433473] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  507.433474] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  507.433477] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  507.433478] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  507.433479] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  507.433479] [drm:intel_dump_pipe_config] requested mode:
>[  507.433481] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  507.433482] [drm:intel_dump_pipe_config] adjusted mode:
>[  507.433484] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  507.433485] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  507.433486] [drm:intel_dump_pipe_config] port clock: 270000
>[  507.433487] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  507.433488] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  507.433489] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  507.433490] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  507.433491] [drm:intel_dump_pipe_config] ips: 0
>[  507.433492] [drm:intel_dump_pipe_config] double wide: 0
>[  507.433493] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  507.433493] [drm:intel_dump_pipe_config] planes on this crtc
>[  507.433495] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  507.433496] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  507.433497] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  507.433499] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff8801f5325000 state to ffff88020103ce00
>[  507.433500] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff8801f5326000 state to ffff88020103ce00
>[  507.433502] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 49
>[  507.433504] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  507.433505] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8801f55af3c0 state to ffff88020103ce00
>[  507.433506] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8801f55af9c0 state to ffff88020103ce00
>[  507.433508] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8801f55af540 state to ffff88020103ce00
>[  507.433510] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f55af6c0 state to ffff88020103ce00
>[  507.433511] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f55afb40 state to ffff88020103ce00
>[  507.433513] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8801f55af840 state to ffff88020103ce00
>[  507.433514] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8801f55af780 state to ffff88020103ce00
>[  507.433515] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8801f55af300 state to ffff88020103ce00
>[  507.433516] [drm:drm_atomic_commit] commiting ffff88020103ce00
>[  507.433522] [drm:intel_power_well_enable] enabling display
>[  507.433523] [drm:hsw_set_power_well] Enabling power well
>[  507.435592] [drm:intel_power_well_enable] enabling always-on
>[  507.435602] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  507.435603] [drm:intel_enable_shared_dpll] enabling SPLL
>[  507.436493] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  507.436557] [drm:intel_enable_pipe] enabling pipe B
>[  507.436571] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  507.503408] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  507.503413] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  507.503414] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  507.503415] [drm:check_crtc_state] [CRTC:25]
>[  507.503427] [drm:check_shared_dpll_state] WRPLL 1
>[  507.503428] [drm:check_shared_dpll_state] WRPLL 2
>[  507.503429] [drm:check_shared_dpll_state] SPLL
>[  507.503430] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88020103ce00
>[  507.503434] [drm:drm_atomic_state_free] Freeing atomic state ffff88020103ce00
>[  507.503461] [drm:drm_mode_setcrtc] [CRTC:25]
>[  507.503462] [drm:drm_atomic_state_init] Allocated atomic state ffff88020103ce00
>[  507.503464] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5324000 state to ffff88020103ce00
>[  507.503466] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f55af900 state to ffff88020103ce00
>[  507.503467] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f5324000
>[  507.503468] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55af900 to [NOCRTC]
>[  507.503469] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f55af900
>[  507.503470] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103ce00
>[  507.503471] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c909b900 state to ffff88020103ce00
>[  507.503472] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c909b900 to [NOCRTC]
>[  507.503473] [drm:drm_atomic_check_only] checking ffff88020103ce00
>[  507.503474] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  507.503475] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  507.503476] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  507.503477] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  507.503477] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  507.503478] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  507.503479] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103ce00
>[  507.503481] [drm:drm_atomic_connectors_for_crtc] State ffff88020103ce00 has 0 connectors for [CRTC:25]
>[  507.503483] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  507.503484] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  507.503486] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f55af180 state to ffff88020103ce00
>[  507.503487] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f55af0c0 state to ffff88020103ce00
>[  507.503489] [drm:drm_atomic_commit] commiting ffff88020103ce00
>[  507.520103] [drm:intel_disable_pipe] disabling pipe B
>[  507.553996] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  507.553999] [drm:intel_disable_shared_dpll] disabling SPLL
>[  507.554007] [drm:intel_power_well_disable] disabling display
>[  507.554009] [drm:hsw_set_power_well] Requesting to disable the power well
>[  507.554010] [drm:intel_power_well_disable] disabling always-on
>[  507.554011] [drm:intel_power_well_enable] enabling display
>[  507.554012] [drm:hsw_set_power_well] Enabling power well
>[  507.556081] [drm:intel_power_well_disable] disabling display
>[  507.556085] [drm:hsw_set_power_well] Requesting to disable the power well
>[  507.556090] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  507.556093] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  507.556094] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  507.556097] [drm:check_crtc_state] [CRTC:25]
>[  507.556098] [drm:check_shared_dpll_state] WRPLL 1
>[  507.556099] [drm:check_shared_dpll_state] WRPLL 2
>[  507.556100] [drm:check_shared_dpll_state] SPLL
>[  507.556102] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88020103ce00
>[  507.556104] [drm:drm_atomic_state_free] Freeing atomic state ffff88020103ce00
>[  507.556132] [drm:drm_mode_setcrtc] [CRTC:25]
>[  507.556136] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  507.556138] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bfa200
>[  507.556140] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880025a40800 state to ffff880026bfa200
>[  507.556142] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8800c78d4600 state to ffff880026bfa200
>[  507.556143] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff880025a40800
>[  507.556144] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800c78d4600 to [CRTC:25]
>[  507.556145] [drm:drm_atomic_set_fb_for_plane] Set [FB:51] for plane state ffff8800c78d4600
>[  507.556146] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8801f442de80 state to ffff880026bfa200
>[  507.556147] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfa200
>[  507.556148] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f442de80 to [CRTC:25]
>[  507.556149] [drm:drm_atomic_check_only] checking ffff880026bfa200
>[  507.556151] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  507.556152] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  507.556153] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  507.556154] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  507.556155] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  507.556156] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  507.556157] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfa200
>[  507.556158] [drm:drm_atomic_connectors_for_crtc] State ffff880026bfa200 has 1 connectors for [CRTC:25]
>[  507.556160] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfa200
>[  507.556161] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  507.556162] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  507.556164] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  507.556165] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  507.556166] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff880025a40800 for pipe B
>[  507.556167] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  507.556168] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  507.556169] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  507.556170] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  507.556171] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  507.556172] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  507.556172] [drm:intel_dump_pipe_config] requested mode:
>[  507.556174] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  507.556175] [drm:intel_dump_pipe_config] adjusted mode:
>[  507.556176] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  507.556177] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  507.556178] [drm:intel_dump_pipe_config] port clock: 270000
>[  507.556179] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  507.556180] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  507.556181] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  507.556182] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  507.556182] [drm:intel_dump_pipe_config] ips: 0
>[  507.556183] [drm:intel_dump_pipe_config] double wide: 0
>[  507.556184] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  507.556185] [drm:intel_dump_pipe_config] planes on this crtc
>[  507.556186] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  507.556187] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  507.556188] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  507.556190] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff880025a42c00 state to ffff880026bfa200
>[  507.556191] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff880025a41800 state to ffff880026bfa200
>[  507.556193] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 51
>[  507.556194] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  507.556195] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8800c78d4b40 state to ffff880026bfa200
>[  507.556197] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8800c78d49c0 state to ffff880026bfa200
>[  507.556198] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8800c78d4840 state to ffff880026bfa200
>[  507.556200] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8800c78d4180 state to ffff880026bfa200
>[  507.556202] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8800c78d4c00 state to ffff880026bfa200
>[  507.556203] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8800c78d4480 state to ffff880026bfa200
>[  507.556204] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8800c78d4540 state to ffff880026bfa200
>[  507.556206] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8800c78d4300 state to ffff880026bfa200
>[  507.556207] [drm:drm_atomic_commit] commiting ffff880026bfa200
>[  507.556212] [drm:intel_power_well_enable] enabling display
>[  507.556213] [drm:hsw_set_power_well] Enabling power well
>[  507.557367] [drm:intel_power_well_enable] enabling always-on
>[  507.557379] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  507.557381] [drm:intel_enable_shared_dpll] enabling SPLL
>[  507.558271] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  507.558335] [drm:intel_enable_pipe] enabling pipe B
>[  507.558349] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  507.625187] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  507.625191] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  507.625192] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  507.625194] [drm:check_crtc_state] [CRTC:25]
>[  507.625205] [drm:check_shared_dpll_state] WRPLL 1
>[  507.625206] [drm:check_shared_dpll_state] WRPLL 2
>[  507.625207] [drm:check_shared_dpll_state] SPLL
>[  507.625209] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bfa200
>[  507.625212] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bfa200
>[  507.625239] [drm:drm_mode_setcrtc] [CRTC:25]
>[  507.625241] [drm:drm_atomic_state_init] Allocated atomic state ffff88020103da00
>[  507.625243] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5326000 state to ffff88020103da00
>[  507.625245] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f55af300 state to ffff88020103da00
>[  507.625246] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f5326000
>[  507.625247] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55af300 to [NOCRTC]
>[  507.625247] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f55af300
>[  507.625249] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103da00
>[  507.625250] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c909b420 state to ffff88020103da00
>[  507.625251] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c909b420 to [NOCRTC]
>[  507.625252] [drm:drm_atomic_check_only] checking ffff88020103da00
>[  507.625253] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  507.625254] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  507.625255] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  507.625256] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  507.625256] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  507.625257] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  507.625258] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103da00
>[  507.625259] [drm:drm_atomic_connectors_for_crtc] State ffff88020103da00 has 0 connectors for [CRTC:25]
>[  507.625262] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  507.625263] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  507.625265] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f55af780 state to ffff88020103da00
>[  507.625266] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f55af840 state to ffff88020103da00
>[  507.625268] [drm:drm_atomic_commit] commiting ffff88020103da00
>[  507.641879] [drm:intel_disable_pipe] disabling pipe B
>[  507.676328] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  507.676331] [drm:intel_disable_shared_dpll] disabling SPLL
>[  507.676339] [drm:intel_power_well_disable] disabling display
>[  507.676341] [drm:hsw_set_power_well] Requesting to disable the power well
>[  507.676341] [drm:intel_power_well_disable] disabling always-on
>[  507.676343] [drm:intel_power_well_enable] enabling display
>[  507.676344] [drm:hsw_set_power_well] Enabling power well
>[  507.678413] [drm:intel_power_well_disable] disabling display
>[  507.678417] [drm:hsw_set_power_well] Requesting to disable the power well
>[  507.678423] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  507.678425] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  507.678426] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  507.678429] [drm:check_crtc_state] [CRTC:25]
>[  507.678430] [drm:check_shared_dpll_state] WRPLL 1
>[  507.678432] [drm:check_shared_dpll_state] WRPLL 2
>[  507.678432] [drm:check_shared_dpll_state] SPLL
>[  507.678434] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88020103da00
>[  507.678437] [drm:drm_atomic_state_free] Freeing atomic state ffff88020103da00
>[  507.678465] [drm:drm_mode_setcrtc] [CRTC:25]
>[  507.678469] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  507.678471] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bf2800
>[  507.678473] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880215be4000 state to ffff880026bf2800
>[  507.678475] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f550c180 state to ffff880026bf2800
>[  507.678476] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff880215be4000
>[  507.678477] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f550c180 to [CRTC:25]
>[  507.678478] [drm:drm_atomic_set_fb_for_plane] Set [FB:49] for plane state ffff8801f550c180
>[  507.678479] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c01327e0 state to ffff880026bf2800
>[  507.678480] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf2800
>[  507.678481] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c01327e0 to [CRTC:25]
>[  507.678482] [drm:drm_atomic_check_only] checking ffff880026bf2800
>[  507.678484] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  507.678485] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  507.678486] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  507.678487] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  507.678488] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  507.678489] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  507.678490] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf2800
>[  507.678491] [drm:drm_atomic_connectors_for_crtc] State ffff880026bf2800 has 1 connectors for [CRTC:25]
>[  507.678492] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf2800
>[  507.678494] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  507.678495] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  507.678496] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  507.678497] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  507.678499] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff880215be4000 for pipe B
>[  507.678499] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  507.678500] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  507.678501] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  507.678502] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  507.678503] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  507.678504] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  507.678505] [drm:intel_dump_pipe_config] requested mode:
>[  507.678506] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  507.678507] [drm:intel_dump_pipe_config] adjusted mode:
>[  507.678508] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  507.678510] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  507.678510] [drm:intel_dump_pipe_config] port clock: 270000
>[  507.678511] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  507.678512] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  507.678513] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  507.678514] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  507.678515] [drm:intel_dump_pipe_config] ips: 0
>[  507.678515] [drm:intel_dump_pipe_config] double wide: 0
>[  507.678516] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  507.678517] [drm:intel_dump_pipe_config] planes on this crtc
>[  507.678518] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  507.678519] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  507.678520] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  507.678522] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff880215be4800 state to ffff880026bf2800
>[  507.678524] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff880215be5c00 state to ffff880026bf2800
>[  507.678526] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 49
>[  507.678527] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  507.678528] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8801f550c840 state to ffff880026bf2800
>[  507.678529] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8801f550cc00 state to ffff880026bf2800
>[  507.678531] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8801f550c300 state to ffff880026bf2800
>[  507.678533] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f550c240 state to ffff880026bf2800
>[  507.678534] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f550ce40 state to ffff880026bf2800
>[  507.678536] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8801f550ccc0 state to ffff880026bf2800
>[  507.678537] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8801f550c3c0 state to ffff880026bf2800
>[  507.678538] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8801f550c780 state to ffff880026bf2800
>[  507.678540] [drm:drm_atomic_commit] commiting ffff880026bf2800
>[  507.678544] [drm:intel_power_well_enable] enabling display
>[  507.678545] [drm:hsw_set_power_well] Enabling power well
>[  507.680613] [drm:intel_power_well_enable] enabling always-on
>[  507.680624] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  507.680625] [drm:intel_enable_shared_dpll] enabling SPLL
>[  507.681523] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  507.681587] [drm:intel_enable_pipe] enabling pipe B
>[  507.681601] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  507.748471] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  507.748476] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  507.748477] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  507.748479] [drm:check_crtc_state] [CRTC:25]
>[  507.748490] [drm:check_shared_dpll_state] WRPLL 1
>[  507.748491] [drm:check_shared_dpll_state] WRPLL 2
>[  507.748492] [drm:check_shared_dpll_state] SPLL
>[  507.748494] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bf2800
>[  507.748497] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bf2800
>[  507.748524] [drm:drm_mode_setcrtc] [CRTC:25]
>[  507.748526] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bf2800
>[  507.748527] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880215be4400 state to ffff880026bf2800
>[  507.748529] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f550ca80 state to ffff880026bf2800
>[  507.748530] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff880215be4400
>[  507.748531] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f550ca80 to [NOCRTC]
>[  507.748532] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f550ca80
>[  507.748533] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf2800
>[  507.748534] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c0132360 state to ffff880026bf2800
>[  507.748535] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c0132360 to [NOCRTC]
>[  507.748536] [drm:drm_atomic_check_only] checking ffff880026bf2800
>[  507.748537] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  507.748538] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  507.748539] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  507.748540] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  507.748541] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  507.748542] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  507.748543] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf2800
>[  507.748544] [drm:drm_atomic_connectors_for_crtc] State ffff880026bf2800 has 0 connectors for [CRTC:25]
>[  507.748547] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  507.748548] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  507.748550] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff880201584d80 state to ffff880026bf2800
>[  507.748552] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff880201584600 state to ffff880026bf2800
>[  507.748554] [drm:drm_atomic_commit] commiting ffff880026bf2800
>[  507.765131] [drm:intel_disable_pipe] disabling pipe B
>[  507.800080] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  507.800084] [drm:intel_disable_shared_dpll] disabling SPLL
>[  507.800092] [drm:intel_power_well_disable] disabling display
>[  507.800093] [drm:hsw_set_power_well] Requesting to disable the power well
>[  507.800094] [drm:intel_power_well_disable] disabling always-on
>[  507.800096] [drm:intel_power_well_enable] enabling display
>[  507.800097] [drm:hsw_set_power_well] Enabling power well
>[  507.801347] [drm:intel_power_well_disable] disabling display
>[  507.801351] [drm:hsw_set_power_well] Requesting to disable the power well
>[  507.801357] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  507.801360] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  507.801361] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  507.801365] [drm:check_crtc_state] [CRTC:25]
>[  507.801367] [drm:check_shared_dpll_state] WRPLL 1
>[  507.801368] [drm:check_shared_dpll_state] WRPLL 2
>[  507.801369] [drm:check_shared_dpll_state] SPLL
>[  507.801371] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bf2800
>[  507.801374] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bf2800
>[  507.801399] [drm:drm_mode_setcrtc] [CRTC:25]
>[  507.801403] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  507.801405] [drm:drm_atomic_state_init] Allocated atomic state ffff880210d7b800
>[  507.801407] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5493400 state to ffff880210d7b800
>[  507.801409] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f5fdec00 state to ffff880210d7b800
>[  507.801411] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f5493400
>[  507.801412] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f5fdec00 to [CRTC:25]
>[  507.801414] [drm:drm_atomic_set_fb_for_plane] Set [FB:51] for plane state ffff8801f5fdec00
>[  507.801415] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800d3bba7c0 state to ffff880210d7b800
>[  507.801417] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b800
>[  507.801418] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800d3bba7c0 to [CRTC:25]
>[  507.801419] [drm:drm_atomic_check_only] checking ffff880210d7b800
>[  507.801421] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  507.801422] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  507.801423] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  507.801425] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  507.801426] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  507.801427] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  507.801429] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b800
>[  507.801430] [drm:drm_atomic_connectors_for_crtc] State ffff880210d7b800 has 1 connectors for [CRTC:25]
>[  507.801432] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b800
>[  507.801434] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  507.801435] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  507.801437] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  507.801439] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  507.801441] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff8801f5493400 for pipe B
>[  507.801442] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  507.801443] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  507.801445] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  507.801446] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  507.801448] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  507.801449] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  507.801451] [drm:intel_dump_pipe_config] requested mode:
>[  507.801453] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  507.801454] [drm:intel_dump_pipe_config] adjusted mode:
>[  507.801455] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  507.801457] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  507.801458] [drm:intel_dump_pipe_config] port clock: 270000
>[  507.801459] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  507.801460] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  507.801461] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  507.801462] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  507.801463] [drm:intel_dump_pipe_config] ips: 0
>[  507.801464] [drm:intel_dump_pipe_config] double wide: 0
>[  507.801465] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  507.801466] [drm:intel_dump_pipe_config] planes on this crtc
>[  507.801467] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  507.801469] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  507.801470] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  507.801471] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff8801f5491c00 state to ffff880210d7b800
>[  507.801473] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff8801f5490c00 state to ffff880210d7b800
>[  507.801475] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 51
>[  507.801476] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  507.801478] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8801f5fdeb40 state to ffff880210d7b800
>[  507.801480] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8801f5fdee40 state to ffff880210d7b800
>[  507.801481] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8801f5fde3c0 state to ffff880210d7b800
>[  507.801484] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f5fde540 state to ffff880210d7b800
>[  507.801485] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f5fde600 state to ffff880210d7b800
>[  507.801487] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8801f5fde840 state to ffff880210d7b800
>[  507.801488] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8801f5fde480 state to ffff880210d7b800
>[  507.801490] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8801f5fded80 state to ffff880210d7b800
>[  507.801491] [drm:drm_atomic_commit] commiting ffff880210d7b800
>[  507.801496] [drm:intel_power_well_enable] enabling display
>[  507.801497] [drm:hsw_set_power_well] Enabling power well
>[  507.803567] [drm:intel_power_well_enable] enabling always-on
>[  507.803578] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  507.803579] [drm:intel_enable_shared_dpll] enabling SPLL
>[  507.804477] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  507.804540] [drm:intel_enable_pipe] enabling pipe B
>[  507.804554] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  507.871420] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  507.871425] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  507.871426] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  507.871428] [drm:check_crtc_state] [CRTC:25]
>[  507.871439] [drm:check_shared_dpll_state] WRPLL 1
>[  507.871440] [drm:check_shared_dpll_state] WRPLL 2
>[  507.871441] [drm:check_shared_dpll_state] SPLL
>[  507.871443] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880210d7b800
>[  507.871446] [drm:drm_atomic_state_free] Freeing atomic state ffff880210d7b800
>[  507.871474] [drm:drm_mode_setcrtc] [CRTC:25]
>[  507.871476] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bf2600
>[  507.871478] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880215be5c00 state to ffff880026bf2600
>[  507.871479] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff880201584600 state to ffff880026bf2600
>[  507.871480] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff880215be5c00
>[  507.871481] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880201584600 to [NOCRTC]
>[  507.871482] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880201584600
>[  507.871483] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf2600
>[  507.871485] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c0132700 state to ffff880026bf2600
>[  507.871485] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c0132700 to [NOCRTC]
>[  507.871486] [drm:drm_atomic_check_only] checking ffff880026bf2600
>[  507.871488] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  507.871489] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  507.871490] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  507.871490] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  507.871491] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  507.871492] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  507.871493] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf2600
>[  507.871494] [drm:drm_atomic_connectors_for_crtc] State ffff880026bf2600 has 0 connectors for [CRTC:25]
>[  507.871497] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  507.871498] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  507.871500] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff880201584d80 state to ffff880026bf2600
>[  507.871501] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff880216138b40 state to ffff880026bf2600
>[  507.871503] [drm:drm_atomic_commit] commiting ffff880026bf2600
>[  507.888088] [drm:intel_disable_pipe] disabling pipe B
>[  507.922402] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  507.922405] [drm:intel_disable_shared_dpll] disabling SPLL
>[  507.922413] [drm:intel_power_well_disable] disabling display
>[  507.922415] [drm:hsw_set_power_well] Requesting to disable the power well
>[  507.922415] [drm:intel_power_well_disable] disabling always-on
>[  507.922417] [drm:intel_power_well_enable] enabling display
>[  507.922418] [drm:hsw_set_power_well] Enabling power well
>[  507.924487] [drm:intel_power_well_disable] disabling display
>[  507.924491] [drm:hsw_set_power_well] Requesting to disable the power well
>[  507.924496] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  507.924498] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  507.924500] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  507.924502] [drm:check_crtc_state] [CRTC:25]
>[  507.924504] [drm:check_shared_dpll_state] WRPLL 1
>[  507.924505] [drm:check_shared_dpll_state] WRPLL 2
>[  507.924506] [drm:check_shared_dpll_state] SPLL
>[  507.924508] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bf2600
>[  507.924510] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bf2600
>[  507.924538] [drm:drm_mode_setcrtc] [CRTC:25]
>[  507.924541] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  507.924543] [drm:drm_atomic_state_init] Allocated atomic state ffff88020103d800
>[  507.924545] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5324000 state to ffff88020103d800
>[  507.924547] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f55af0c0 state to ffff88020103d800
>[  507.924548] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f5324000
>[  507.924549] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55af0c0 to [CRTC:25]
>[  507.924550] [drm:drm_atomic_set_fb_for_plane] Set [FB:49] for plane state ffff8801f55af0c0
>[  507.924552] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c909bae0 state to ffff88020103d800
>[  507.924553] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103d800
>[  507.924554] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c909bae0 to [CRTC:25]
>[  507.924555] [drm:drm_atomic_check_only] checking ffff88020103d800
>[  507.924556] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  507.924557] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  507.924558] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  507.924559] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  507.924560] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  507.924561] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  507.924562] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103d800
>[  507.924563] [drm:drm_atomic_connectors_for_crtc] State ffff88020103d800 has 1 connectors for [CRTC:25]
>[  507.924565] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103d800
>[  507.924566] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  507.924567] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  507.924568] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  507.924569] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  507.924571] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff8801f5324000 for pipe B
>[  507.924572] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  507.924572] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  507.924573] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  507.924575] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  507.924576] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  507.924576] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  507.924577] [drm:intel_dump_pipe_config] requested mode:
>[  507.924579] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  507.924580] [drm:intel_dump_pipe_config] adjusted mode:
>[  507.924581] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  507.924582] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  507.924583] [drm:intel_dump_pipe_config] port clock: 270000
>[  507.924584] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  507.924585] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  507.924586] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  507.924587] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  507.924587] [drm:intel_dump_pipe_config] ips: 0
>[  507.924588] [drm:intel_dump_pipe_config] double wide: 0
>[  507.924589] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  507.924590] [drm:intel_dump_pipe_config] planes on this crtc
>[  507.924591] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  507.924592] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  507.924593] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  507.924595] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff8801f5325000 state to ffff88020103d800
>[  507.924596] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff8801f5327800 state to ffff88020103d800
>[  507.924598] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 49
>[  507.924599] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  507.924601] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8801f55af900 state to ffff88020103d800
>[  507.924602] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8801f55af540 state to ffff88020103d800
>[  507.924603] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8801f55af9c0 state to ffff88020103d800
>[  507.924606] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f55af3c0 state to ffff88020103d800
>[  507.924607] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f55af240 state to ffff88020103d800
>[  507.924609] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8801f55af000 state to ffff88020103d800
>[  507.924610] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8801f55afe40 state to ffff88020103d800
>[  507.924611] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8801f55afa80 state to ffff88020103d800
>[  507.924612] [drm:drm_atomic_commit] commiting ffff88020103d800
>[  507.924616] [drm:intel_power_well_enable] enabling display
>[  507.924618] [drm:hsw_set_power_well] Enabling power well
>[  507.926686] [drm:intel_power_well_enable] enabling always-on
>[  507.926696] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  507.926697] [drm:intel_enable_shared_dpll] enabling SPLL
>[  507.927586] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  507.927649] [drm:intel_enable_pipe] enabling pipe B
>[  507.927662] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  507.996172] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  507.996176] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  507.996178] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  507.996179] [drm:check_crtc_state] [CRTC:25]
>[  507.996191] [drm:check_shared_dpll_state] WRPLL 1
>[  507.996192] [drm:check_shared_dpll_state] WRPLL 2
>[  507.996193] [drm:check_shared_dpll_state] SPLL
>[  507.996194] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88020103d800
>[  507.996198] [drm:drm_atomic_state_free] Freeing atomic state ffff88020103d800
>[  507.996219] [drm:drm_mode_setcrtc] [CRTC:25]
>[  507.996221] [drm:drm_atomic_state_init] Allocated atomic state ffff880210d7b000
>[  507.996223] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5490c00 state to ffff880210d7b000
>[  507.996225] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f5fded80 state to ffff880210d7b000
>[  507.996226] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f5490c00
>[  507.996227] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f5fded80 to [NOCRTC]
>[  507.996228] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f5fded80
>[  507.996229] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b000
>[  507.996230] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800d3bba8a0 state to ffff880210d7b000
>[  507.996231] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800d3bba8a0 to [NOCRTC]
>[  507.996232] [drm:drm_atomic_check_only] checking ffff880210d7b000
>[  507.996233] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  507.996234] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  507.996235] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  507.996236] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  507.996237] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  507.996237] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  507.996238] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b000
>[  507.996240] [drm:drm_atomic_connectors_for_crtc] State ffff880210d7b000 has 0 connectors for [CRTC:25]
>[  507.996242] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  507.996243] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  507.996245] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f5fde480 state to ffff880210d7b000
>[  507.996246] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f5fde840 state to ffff880210d7b000
>[  507.996248] [drm:drm_atomic_commit] commiting ffff880210d7b000
>[  508.012839] [drm:intel_disable_pipe] disabling pipe B
>[  508.047960] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  508.047963] [drm:intel_disable_shared_dpll] disabling SPLL
>[  508.047971] [drm:intel_power_well_disable] disabling display
>[  508.047972] [drm:hsw_set_power_well] Requesting to disable the power well
>[  508.047973] [drm:intel_power_well_disable] disabling always-on
>[  508.047975] [drm:intel_power_well_enable] enabling display
>[  508.047976] [drm:hsw_set_power_well] Enabling power well
>[  508.049324] [drm:intel_power_well_disable] disabling display
>[  508.049328] [drm:hsw_set_power_well] Requesting to disable the power well
>[  508.049334] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  508.049337] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  508.049338] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  508.049342] [drm:check_crtc_state] [CRTC:25]
>[  508.049343] [drm:check_shared_dpll_state] WRPLL 1
>[  508.049344] [drm:check_shared_dpll_state] WRPLL 2
>[  508.049345] [drm:check_shared_dpll_state] SPLL
>[  508.049348] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880210d7b000
>[  508.049350] [drm:drm_atomic_state_free] Freeing atomic state ffff880210d7b000
>[  508.049376] [drm:drm_mode_setcrtc] [CRTC:25]
>[  508.049379] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  508.049381] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bf2400
>[  508.049383] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880215be4400 state to ffff880026bf2400
>[  508.049386] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff880216138b40 state to ffff880026bf2400
>[  508.049388] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff880215be4400
>[  508.049389] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880216138b40 to [CRTC:25]
>[  508.049390] [drm:drm_atomic_set_fb_for_plane] Set [FB:51] for plane state ffff880216138b40
>[  508.049392] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c0132340 state to ffff880026bf2400
>[  508.049393] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf2400
>[  508.049394] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c0132340 to [CRTC:25]
>[  508.049395] [drm:drm_atomic_check_only] checking ffff880026bf2400
>[  508.049397] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  508.049398] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  508.049400] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  508.049401] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  508.049402] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  508.049403] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  508.049404] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf2400
>[  508.049406] [drm:drm_atomic_connectors_for_crtc] State ffff880026bf2400 has 1 connectors for [CRTC:25]
>[  508.049408] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf2400
>[  508.049409] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  508.049410] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  508.049412] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  508.049413] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  508.049415] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff880215be4400 for pipe B
>[  508.049416] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  508.049417] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  508.049418] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  508.049420] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  508.049421] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  508.049423] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  508.049423] [drm:intel_dump_pipe_config] requested mode:
>[  508.049425] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  508.049427] [drm:intel_dump_pipe_config] adjusted mode:
>[  508.049428] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  508.049430] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  508.049430] [drm:intel_dump_pipe_config] port clock: 270000
>[  508.049431] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  508.049432] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  508.049433] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  508.049435] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  508.049436] [drm:intel_dump_pipe_config] ips: 0
>[  508.049436] [drm:intel_dump_pipe_config] double wide: 0
>[  508.049437] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  508.049438] [drm:intel_dump_pipe_config] planes on this crtc
>[  508.049439] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  508.049441] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  508.049442] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  508.049444] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff880215be4800 state to ffff880026bf2400
>[  508.049445] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff880215be6400 state to ffff880026bf2400
>[  508.049447] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 51
>[  508.049448] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  508.049450] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8801f4ced840 state to ffff880026bf2400
>[  508.049451] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8801f4ced480 state to ffff880026bf2400
>[  508.049452] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8801f4ced6c0 state to ffff880026bf2400
>[  508.049455] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f4ced180 state to ffff880026bf2400
>[  508.049457] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f4ced9c0 state to ffff880026bf2400
>[  508.049458] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8801f4ced900 state to ffff880026bf2400
>[  508.049459] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8801f4ced780 state to ffff880026bf2400
>[  508.049460] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8801f4ced3c0 state to ffff880026bf2400
>[  508.049462] [drm:drm_atomic_commit] commiting ffff880026bf2400
>[  508.049466] [drm:intel_power_well_enable] enabling display
>[  508.049468] [drm:hsw_set_power_well] Enabling power well
>[  508.051535] [drm:intel_power_well_enable] enabling always-on
>[  508.051546] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  508.051547] [drm:intel_enable_shared_dpll] enabling SPLL
>[  508.052436] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  508.052500] [drm:intel_enable_pipe] enabling pipe B
>[  508.052514] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  508.119381] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  508.119385] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  508.119387] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  508.119388] [drm:check_crtc_state] [CRTC:25]
>[  508.119400] [drm:check_shared_dpll_state] WRPLL 1
>[  508.119401] [drm:check_shared_dpll_state] WRPLL 2
>[  508.119402] [drm:check_shared_dpll_state] SPLL
>[  508.119403] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bf2400
>[  508.119407] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bf2400
>[  508.119434] [drm:drm_mode_setcrtc] [CRTC:25]
>[  508.119435] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bf2400
>[  508.119438] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880215be5000 state to ffff880026bf2400
>[  508.119439] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f4ceda80 state to ffff880026bf2400
>[  508.119440] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff880215be5000
>[  508.119441] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f4ceda80 to [NOCRTC]
>[  508.119442] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f4ceda80
>[  508.119443] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf2400
>[  508.119444] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c01325c0 state to ffff880026bf2400
>[  508.119445] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c01325c0 to [NOCRTC]
>[  508.119446] [drm:drm_atomic_check_only] checking ffff880026bf2400
>[  508.119448] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  508.119448] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  508.119449] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  508.119450] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  508.119451] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  508.119452] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  508.119453] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf2400
>[  508.119454] [drm:drm_atomic_connectors_for_crtc] State ffff880026bf2400 has 0 connectors for [CRTC:25]
>[  508.119457] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  508.119458] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  508.119460] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f4ced240 state to ffff880026bf2400
>[  508.119461] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f4ced540 state to ffff880026bf2400
>[  508.119463] [drm:drm_atomic_commit] commiting ffff880026bf2400
>[  508.136048] [drm:intel_disable_pipe] disabling pipe B
>[  508.169525] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  508.169528] [drm:intel_disable_shared_dpll] disabling SPLL
>[  508.169536] [drm:intel_power_well_disable] disabling display
>[  508.169538] [drm:hsw_set_power_well] Requesting to disable the power well
>[  508.169539] [drm:intel_power_well_disable] disabling always-on
>[  508.169540] [drm:intel_power_well_enable] enabling display
>[  508.169541] [drm:hsw_set_power_well] Enabling power well
>[  508.171609] [drm:intel_power_well_disable] disabling display
>[  508.171613] [drm:hsw_set_power_well] Requesting to disable the power well
>[  508.171618] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  508.171620] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  508.171621] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  508.171624] [drm:check_crtc_state] [CRTC:25]
>[  508.171625] [drm:check_shared_dpll_state] WRPLL 1
>[  508.171627] [drm:check_shared_dpll_state] WRPLL 2
>[  508.171627] [drm:check_shared_dpll_state] SPLL
>[  508.171629] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bf2400
>[  508.171632] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bf2400
>[  508.171660] [drm:drm_mode_setcrtc] [CRTC:25]
>[  508.171663] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  508.171666] [drm:drm_atomic_state_init] Allocated atomic state ffff880210d7b000
>[  508.171668] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5491c00 state to ffff880210d7b000
>[  508.171669] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f5fde3c0 state to ffff880210d7b000
>[  508.171671] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f5491c00
>[  508.171672] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f5fde3c0 to [CRTC:25]
>[  508.171673] [drm:drm_atomic_set_fb_for_plane] Set [FB:49] for plane state ffff8801f5fde3c0
>[  508.171674] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800d3bba3c0 state to ffff880210d7b000
>[  508.171675] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b000
>[  508.171676] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800d3bba3c0 to [CRTC:25]
>[  508.171677] [drm:drm_atomic_check_only] checking ffff880210d7b000
>[  508.171679] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  508.171679] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  508.171680] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  508.171682] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  508.171682] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  508.171683] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  508.171684] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b000
>[  508.171685] [drm:drm_atomic_connectors_for_crtc] State ffff880210d7b000 has 1 connectors for [CRTC:25]
>[  508.171687] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b000
>[  508.171688] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  508.171689] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  508.171691] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  508.171692] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  508.171693] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff8801f5491c00 for pipe B
>[  508.171694] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  508.171695] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  508.171696] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  508.171697] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  508.171699] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  508.171699] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  508.171700] [drm:intel_dump_pipe_config] requested mode:
>[  508.171702] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  508.171702] [drm:intel_dump_pipe_config] adjusted mode:
>[  508.171704] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  508.171705] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  508.171706] [drm:intel_dump_pipe_config] port clock: 270000
>[  508.171706] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  508.171707] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  508.171708] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  508.171709] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  508.171710] [drm:intel_dump_pipe_config] ips: 0
>[  508.171711] [drm:intel_dump_pipe_config] double wide: 0
>[  508.171712] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  508.171712] [drm:intel_dump_pipe_config] planes on this crtc
>[  508.171714] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  508.171715] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  508.171716] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  508.171717] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff8801f5493800 state to ffff880210d7b000
>[  508.171718] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff8801f5490800 state to ffff880210d7b000
>[  508.171720] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 49
>[  508.171721] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  508.171723] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8801f5fdeb40 state to ffff880210d7b000
>[  508.171724] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8801f5fde180 state to ffff880210d7b000
>[  508.171725] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8801f5fde0c0 state to ffff880210d7b000
>[  508.171728] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f5fdecc0 state to ffff880210d7b000
>[  508.171729] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f5fde000 state to ffff880210d7b000
>[  508.171731] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8801f5fde900 state to ffff880210d7b000
>[  508.171732] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8801f5fdef00 state to ffff880210d7b000
>[  508.171733] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8801f5fde9c0 state to ffff880210d7b000
>[  508.171734] [drm:drm_atomic_commit] commiting ffff880210d7b000
>[  508.171739] [drm:intel_power_well_enable] enabling display
>[  508.171740] [drm:hsw_set_power_well] Enabling power well
>[  508.173314] [drm:intel_power_well_enable] enabling always-on
>[  508.173325] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  508.173326] [drm:intel_enable_shared_dpll] enabling SPLL
>[  508.174216] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  508.174280] [drm:intel_enable_pipe] enabling pipe B
>[  508.174293] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  508.241160] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  508.241164] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  508.241166] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  508.241167] [drm:check_crtc_state] [CRTC:25]
>[  508.241179] [drm:check_shared_dpll_state] WRPLL 1
>[  508.241180] [drm:check_shared_dpll_state] WRPLL 2
>[  508.241180] [drm:check_shared_dpll_state] SPLL
>[  508.241182] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880210d7b000
>[  508.241185] [drm:drm_atomic_state_free] Freeing atomic state ffff880210d7b000
>[  508.241215] [drm:drm_mode_setcrtc] [CRTC:25]
>[  508.241238] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bf3000
>[  508.241240] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880215be6400 state to ffff880026bf3000
>[  508.241242] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f4ced3c0 state to ffff880026bf3000
>[  508.241243] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff880215be6400
>[  508.241244] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f4ced3c0 to [NOCRTC]
>[  508.241245] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f4ced3c0
>[  508.241246] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3000
>[  508.241247] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c0132100 state to ffff880026bf3000
>[  508.241248] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c0132100 to [NOCRTC]
>[  508.241249] [drm:drm_atomic_check_only] checking ffff880026bf3000
>[  508.241251] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  508.241253] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  508.241254] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  508.241256] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  508.241257] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  508.241258] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  508.241259] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3000
>[  508.241260] [drm:drm_atomic_connectors_for_crtc] State ffff880026bf3000 has 0 connectors for [CRTC:25]
>[  508.241263] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  508.241264] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  508.241266] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f4ced780 state to ffff880026bf3000
>[  508.241267] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f4ced900 state to ffff880026bf3000
>[  508.241269] [drm:drm_atomic_commit] commiting ffff880026bf3000
>[  508.257829] [drm:intel_disable_pipe] disabling pipe B
>[  508.292123] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  508.292126] [drm:intel_disable_shared_dpll] disabling SPLL
>[  508.292134] [drm:intel_power_well_disable] disabling display
>[  508.292135] [drm:hsw_set_power_well] Requesting to disable the power well
>[  508.292136] [drm:intel_power_well_disable] disabling always-on
>[  508.292138] [drm:intel_power_well_enable] enabling display
>[  508.292139] [drm:hsw_set_power_well] Enabling power well
>[  508.293302] [drm:intel_power_well_disable] disabling display
>[  508.293307] [drm:hsw_set_power_well] Requesting to disable the power well
>[  508.293313] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  508.293316] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  508.293317] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  508.293321] [drm:check_crtc_state] [CRTC:25]
>[  508.293322] [drm:check_shared_dpll_state] WRPLL 1
>[  508.293324] [drm:check_shared_dpll_state] WRPLL 2
>[  508.293325] [drm:check_shared_dpll_state] SPLL
>[  508.293327] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bf3000
>[  508.293329] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bf3000
>[  508.293354] [drm:drm_mode_setcrtc] [CRTC:25]
>[  508.293358] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  508.293359] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bf3000
>[  508.293363] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880215be5000 state to ffff880026bf3000
>[  508.293364] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f4ced540 state to ffff880026bf3000
>[  508.293366] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff880215be5000
>[  508.293367] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f4ced540 to [CRTC:25]
>[  508.293369] [drm:drm_atomic_set_fb_for_plane] Set [FB:51] for plane state ffff8801f4ced540
>[  508.293370] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c0132b60 state to ffff880026bf3000
>[  508.293371] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3000
>[  508.293373] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c0132b60 to [CRTC:25]
>[  508.293374] [drm:drm_atomic_check_only] checking ffff880026bf3000
>[  508.293376] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  508.293377] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  508.293378] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  508.293380] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  508.293381] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  508.293382] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  508.293383] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3000
>[  508.293384] [drm:drm_atomic_connectors_for_crtc] State ffff880026bf3000 has 1 connectors for [CRTC:25]
>[  508.293386] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3000
>[  508.293387] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  508.293388] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  508.293390] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  508.293392] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  508.293393] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff880215be5000 for pipe B
>[  508.293395] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  508.293395] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  508.293396] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  508.293399] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  508.293400] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  508.293401] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  508.293402] [drm:intel_dump_pipe_config] requested mode:
>[  508.293403] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  508.293405] [drm:intel_dump_pipe_config] adjusted mode:
>[  508.293406] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  508.293408] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  508.293409] [drm:intel_dump_pipe_config] port clock: 270000
>[  508.293410] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  508.293411] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  508.293412] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  508.293414] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  508.293415] [drm:intel_dump_pipe_config] ips: 0
>[  508.293415] [drm:intel_dump_pipe_config] double wide: 0
>[  508.293417] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  508.293417] [drm:intel_dump_pipe_config] planes on this crtc
>[  508.293418] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  508.293419] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  508.293421] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  508.293423] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff880215be4800 state to ffff880026bf3000
>[  508.293424] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff880215be4400 state to ffff880026bf3000
>[  508.293426] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 51
>[  508.293427] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  508.293429] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8801f4ceda80 state to ffff880026bf3000
>[  508.293430] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8801f4ced6c0 state to ffff880026bf3000
>[  508.293432] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8801f4ced480 state to ffff880026bf3000
>[  508.293434] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f4ced840 state to ffff880026bf3000
>[  508.293435] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f4ced000 state to ffff880026bf3000
>[  508.293437] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8801f4cedb40 state to ffff880026bf3000
>[  508.293439] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8801f4ced600 state to ffff880026bf3000
>[  508.293440] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8801f4cedc00 state to ffff880026bf3000
>[  508.293441] [drm:drm_atomic_commit] commiting ffff880026bf3000
>[  508.293446] [drm:intel_power_well_enable] enabling display
>[  508.293447] [drm:hsw_set_power_well] Enabling power well
>[  508.295514] [drm:intel_power_well_enable] enabling always-on
>[  508.295525] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  508.295526] [drm:intel_enable_shared_dpll] enabling SPLL
>[  508.296415] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  508.296479] [drm:intel_enable_pipe] enabling pipe B
>[  508.296493] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  508.363342] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  508.363346] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  508.363348] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  508.363350] [drm:check_crtc_state] [CRTC:25]
>[  508.363362] [drm:check_shared_dpll_state] WRPLL 1
>[  508.363363] [drm:check_shared_dpll_state] WRPLL 2
>[  508.363364] [drm:check_shared_dpll_state] SPLL
>[  508.363366] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bf3000
>[  508.363369] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bf3000
>[  508.363396] [drm:drm_mode_setcrtc] [CRTC:25]
>[  508.363397] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bf3000
>[  508.363399] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880215be6400 state to ffff880026bf3000
>[  508.363400] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f4ced900 state to ffff880026bf3000
>[  508.363401] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff880215be6400
>[  508.363402] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f4ced900 to [NOCRTC]
>[  508.363403] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f4ced900
>[  508.363404] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3000
>[  508.363406] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c0132100 state to ffff880026bf3000
>[  508.363406] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c0132100 to [NOCRTC]
>[  508.363407] [drm:drm_atomic_check_only] checking ffff880026bf3000
>[  508.363409] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  508.363410] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  508.363411] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  508.363412] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  508.363412] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  508.363413] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  508.363414] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3000
>[  508.363416] [drm:drm_atomic_connectors_for_crtc] State ffff880026bf3000 has 0 connectors for [CRTC:25]
>[  508.363418] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  508.363419] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  508.363421] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f4ced780 state to ffff880026bf3000
>[  508.363422] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f4ced3c0 state to ffff880026bf3000
>[  508.363424] [drm:drm_atomic_commit] commiting ffff880026bf3000
>[  508.380030] [drm:intel_disable_pipe] disabling pipe B
>[  508.414350] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  508.414353] [drm:intel_disable_shared_dpll] disabling SPLL
>[  508.414360] [drm:intel_power_well_disable] disabling display
>[  508.414362] [drm:hsw_set_power_well] Requesting to disable the power well
>[  508.414363] [drm:intel_power_well_disable] disabling always-on
>[  508.414364] [drm:intel_power_well_enable] enabling display
>[  508.414365] [drm:hsw_set_power_well] Enabling power well
>[  508.416434] [drm:intel_power_well_disable] disabling display
>[  508.416438] [drm:hsw_set_power_well] Requesting to disable the power well
>[  508.416443] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  508.416445] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  508.416447] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  508.416449] [drm:check_crtc_state] [CRTC:25]
>[  508.416451] [drm:check_shared_dpll_state] WRPLL 1
>[  508.416452] [drm:check_shared_dpll_state] WRPLL 2
>[  508.416453] [drm:check_shared_dpll_state] SPLL
>[  508.416455] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bf3000
>[  508.416457] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bf3000
>[  508.416486] [drm:drm_mode_setcrtc] [CRTC:25]
>[  508.416489] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  508.416491] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bfa400
>[  508.416493] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880025a41c00 state to ffff880026bfa400
>[  508.416494] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8800c78d4780 state to ffff880026bfa400
>[  508.416496] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff880025a41c00
>[  508.416497] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800c78d4780 to [CRTC:25]
>[  508.416498] [drm:drm_atomic_set_fb_for_plane] Set [FB:49] for plane state ffff8800c78d4780
>[  508.416499] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8801f442d9e0 state to ffff880026bfa400
>[  508.416500] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfa400
>[  508.416501] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f442d9e0 to [CRTC:25]
>[  508.416502] [drm:drm_atomic_check_only] checking ffff880026bfa400
>[  508.416503] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  508.416504] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  508.416505] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  508.416507] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  508.416507] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  508.416508] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  508.416509] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfa400
>[  508.416510] [drm:drm_atomic_connectors_for_crtc] State ffff880026bfa400 has 1 connectors for [CRTC:25]
>[  508.416512] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfa400
>[  508.416513] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  508.416514] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  508.416516] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  508.416517] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  508.416518] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff880025a41c00 for pipe B
>[  508.416519] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  508.416520] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  508.416521] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  508.416522] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  508.416523] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  508.416524] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  508.416524] [drm:intel_dump_pipe_config] requested mode:
>[  508.416526] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  508.416527] [drm:intel_dump_pipe_config] adjusted mode:
>[  508.416528] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  508.416529] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  508.416530] [drm:intel_dump_pipe_config] port clock: 270000
>[  508.416531] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  508.416531] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  508.416532] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  508.416533] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  508.416534] [drm:intel_dump_pipe_config] ips: 0
>[  508.416535] [drm:intel_dump_pipe_config] double wide: 0
>[  508.416536] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  508.416537] [drm:intel_dump_pipe_config] planes on this crtc
>[  508.416538] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  508.416539] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  508.416540] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  508.416541] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff880025a42000 state to ffff880026bfa400
>[  508.416543] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff880025a41000 state to ffff880026bfa400
>[  508.416545] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 49
>[  508.416545] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  508.416547] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8800c78d4a80 state to ffff880026bfa400
>[  508.416548] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8800c78d4240 state to ffff880026bfa400
>[  508.416549] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8800c78d4000 state to ffff880026bfa400
>[  508.416552] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8800c78d46c0 state to ffff880026bfa400
>[  508.416553] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8800c78d40c0 state to ffff880026bfa400
>[  508.416555] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8800c78d4cc0 state to ffff880026bfa400
>[  508.416556] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8800c78d4e40 state to ffff880026bfa400
>[  508.416558] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8800c78d4300 state to ffff880026bfa400
>[  508.416559] [drm:drm_atomic_commit] commiting ffff880026bfa400
>[  508.416564] [drm:intel_power_well_enable] enabling display
>[  508.416565] [drm:hsw_set_power_well] Enabling power well
>[  508.418633] [drm:intel_power_well_enable] enabling always-on
>[  508.418643] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  508.418644] [drm:intel_enable_shared_dpll] enabling SPLL
>[  508.419533] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  508.419597] [drm:intel_enable_pipe] enabling pipe B
>[  508.419610] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  508.486478] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  508.486482] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  508.486484] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  508.486485] [drm:check_crtc_state] [CRTC:25]
>[  508.486497] [drm:check_shared_dpll_state] WRPLL 1
>[  508.486498] [drm:check_shared_dpll_state] WRPLL 2
>[  508.486499] [drm:check_shared_dpll_state] SPLL
>[  508.486500] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bfa400
>[  508.486504] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bfa400
>[  508.486531] [drm:drm_mode_setcrtc] [CRTC:25]
>[  508.486533] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bfa400
>[  508.486535] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880025a43000 state to ffff880026bfa400
>[  508.486536] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8800c78d4540 state to ffff880026bfa400
>[  508.486537] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff880025a43000
>[  508.486538] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800c78d4540 to [NOCRTC]
>[  508.486539] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8800c78d4540
>[  508.486540] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfa400
>[  508.486541] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8801f442d100 state to ffff880026bfa400
>[  508.486542] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f442d100 to [NOCRTC]
>[  508.486543] [drm:drm_atomic_check_only] checking ffff880026bfa400
>[  508.486545] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  508.486545] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  508.486546] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  508.486547] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  508.486548] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  508.486549] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  508.486550] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfa400
>[  508.486551] [drm:drm_atomic_connectors_for_crtc] State ffff880026bfa400 has 0 connectors for [CRTC:25]
>[  508.486554] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  508.486555] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  508.486557] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8800c78d4480 state to ffff880026bfa400
>[  508.486558] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8800c78d4840 state to ffff880026bfa400
>[  508.486560] [drm:drm_atomic_commit] commiting ffff880026bfa400
>[  508.503148] [drm:intel_disable_pipe] disabling pipe B
>[  508.538268] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  508.538271] [drm:intel_disable_shared_dpll] disabling SPLL
>[  508.538279] [drm:intel_power_well_disable] disabling display
>[  508.538281] [drm:hsw_set_power_well] Requesting to disable the power well
>[  508.538281] [drm:intel_power_well_disable] disabling always-on
>[  508.538283] [drm:intel_power_well_enable] enabling display
>[  508.538284] [drm:hsw_set_power_well] Enabling power well
>[  508.540354] [drm:intel_power_well_disable] disabling display
>[  508.540357] [drm:hsw_set_power_well] Requesting to disable the power well
>[  508.540362] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  508.540364] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  508.540366] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  508.540368] [drm:check_crtc_state] [CRTC:25]
>[  508.540370] [drm:check_shared_dpll_state] WRPLL 1
>[  508.540371] [drm:check_shared_dpll_state] WRPLL 2
>[  508.540372] [drm:check_shared_dpll_state] SPLL
>[  508.540374] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bfa400
>[  508.540376] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bfa400
>[  508.540404] [drm:drm_mode_setcrtc] [CRTC:25]
>[  508.540407] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  508.540408] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bfa400
>[  508.540410] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880025a41c00 state to ffff880026bfa400
>[  508.540412] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8800c78d40c0 state to ffff880026bfa400
>[  508.540413] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff880025a41c00
>[  508.540414] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800c78d40c0 to [CRTC:25]
>[  508.540415] [drm:drm_atomic_set_fb_for_plane] Set [FB:51] for plane state ffff8800c78d40c0
>[  508.540416] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8801f442d9e0 state to ffff880026bfa400
>[  508.540417] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfa400
>[  508.540418] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f442d9e0 to [CRTC:25]
>[  508.540419] [drm:drm_atomic_check_only] checking ffff880026bfa400
>[  508.540421] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  508.540421] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  508.540422] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  508.540424] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  508.540425] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  508.540425] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  508.540426] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfa400
>[  508.540428] [drm:drm_atomic_connectors_for_crtc] State ffff880026bfa400 has 1 connectors for [CRTC:25]
>[  508.540429] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfa400
>[  508.540430] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  508.540431] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  508.540433] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  508.540434] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  508.540435] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff880025a41c00 for pipe B
>[  508.540436] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  508.540437] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  508.540438] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  508.540439] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  508.540440] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  508.540441] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  508.540441] [drm:intel_dump_pipe_config] requested mode:
>[  508.540443] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  508.540444] [drm:intel_dump_pipe_config] adjusted mode:
>[  508.540445] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  508.540447] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  508.540447] [drm:intel_dump_pipe_config] port clock: 270000
>[  508.540448] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  508.540449] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  508.540450] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  508.540451] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  508.540452] [drm:intel_dump_pipe_config] ips: 0
>[  508.540452] [drm:intel_dump_pipe_config] double wide: 0
>[  508.540453] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  508.540454] [drm:intel_dump_pipe_config] planes on this crtc
>[  508.540455] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  508.540456] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  508.540457] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  508.540459] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff880025a41800 state to ffff880026bfa400
>[  508.540460] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff880025a42c00 state to ffff880026bfa400
>[  508.540462] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 51
>[  508.540463] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  508.540465] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8800c78d4780 state to ffff880026bfa400
>[  508.540466] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8800c78d4d80 state to ffff880026bfa400
>[  508.540467] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8800c78d49c0 state to ffff880026bfa400
>[  508.540470] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8800c78d4b40 state to ffff880026bfa400
>[  508.540471] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8800c78d4c00 state to ffff880026bfa400
>[  508.540472] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8800c78d4180 state to ffff880026bfa400
>[  508.540473] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8800c78d4600 state to ffff880026bfa400
>[  508.540474] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8800c78d4900 state to ffff880026bfa400
>[  508.540476] [drm:drm_atomic_commit] commiting ffff880026bfa400
>[  508.540481] [drm:intel_power_well_enable] enabling display
>[  508.540482] [drm:hsw_set_power_well] Enabling power well
>[  508.542550] [drm:intel_power_well_enable] enabling always-on
>[  508.542561] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  508.542562] [drm:intel_enable_shared_dpll] enabling SPLL
>[  508.543451] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  508.543515] [drm:intel_enable_pipe] enabling pipe B
>[  508.543529] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  508.610399] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  508.610403] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  508.610405] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  508.610406] [drm:check_crtc_state] [CRTC:25]
>[  508.610418] [drm:check_shared_dpll_state] WRPLL 1
>[  508.610419] [drm:check_shared_dpll_state] WRPLL 2
>[  508.610419] [drm:check_shared_dpll_state] SPLL
>[  508.610421] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bfa400
>[  508.610424] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bfa400
>[  508.610451] [drm:drm_mode_setcrtc] [CRTC:25]
>[  508.610453] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bfa400
>[  508.610455] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880025a41000 state to ffff880026bfa400
>[  508.610456] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8800c78d4300 state to ffff880026bfa400
>[  508.610457] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff880025a41000
>[  508.610458] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800c78d4300 to [NOCRTC]
>[  508.610459] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8800c78d4300
>[  508.610460] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfa400
>[  508.610462] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8801f442d100 state to ffff880026bfa400
>[  508.610463] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f442d100 to [NOCRTC]
>[  508.610464] [drm:drm_atomic_check_only] checking ffff880026bfa400
>[  508.610465] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  508.610466] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  508.610467] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  508.610468] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  508.610468] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  508.610469] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  508.610470] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfa400
>[  508.610472] [drm:drm_atomic_connectors_for_crtc] State ffff880026bfa400 has 0 connectors for [CRTC:25]
>[  508.610474] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  508.610475] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  508.610477] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8800c78d4e40 state to ffff880026bfa400
>[  508.610478] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8800c78d4cc0 state to ffff880026bfa400
>[  508.610480] [drm:drm_atomic_commit] commiting ffff880026bfa400
>[  508.627061] [drm:intel_disable_pipe] disabling pipe B
>[  508.661921] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  508.661924] [drm:intel_disable_shared_dpll] disabling SPLL
>[  508.661931] [drm:intel_power_well_disable] disabling display
>[  508.661933] [drm:hsw_set_power_well] Requesting to disable the power well
>[  508.661934] [drm:intel_power_well_disable] disabling always-on
>[  508.661935] [drm:intel_power_well_enable] enabling display
>[  508.661936] [drm:hsw_set_power_well] Enabling power well
>[  508.663882] [drm:intel_power_well_disable] disabling display
>[  508.663886] [drm:hsw_set_power_well] Requesting to disable the power well
>[  508.663891] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  508.663893] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  508.663895] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  508.663898] [drm:check_crtc_state] [CRTC:25]
>[  508.663899] [drm:check_shared_dpll_state] WRPLL 1
>[  508.663901] [drm:check_shared_dpll_state] WRPLL 2
>[  508.663902] [drm:check_shared_dpll_state] SPLL
>[  508.663904] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bfa400
>[  508.663906] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bfa400
>[  508.663934] [drm:drm_mode_setcrtc] [CRTC:25]
>[  508.663937] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  508.663939] [drm:drm_atomic_state_init] Allocated atomic state ffff88020103c400
>[  508.663941] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5324400 state to ffff88020103c400
>[  508.663943] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f55aff00 state to ffff88020103c400
>[  508.663944] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f5324400
>[  508.663945] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55aff00 to [CRTC:25]
>[  508.663946] [drm:drm_atomic_set_fb_for_plane] Set [FB:49] for plane state ffff8801f55aff00
>[  508.663947] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c909b0a0 state to ffff88020103c400
>[  508.663948] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103c400
>[  508.663949] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c909b0a0 to [CRTC:25]
>[  508.663950] [drm:drm_atomic_check_only] checking ffff88020103c400
>[  508.663952] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  508.663952] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  508.663953] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  508.663955] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  508.663956] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  508.663957] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  508.663957] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103c400
>[  508.663959] [drm:drm_atomic_connectors_for_crtc] State ffff88020103c400 has 1 connectors for [CRTC:25]
>[  508.663960] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103c400
>[  508.663962] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  508.663962] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  508.663964] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  508.663965] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  508.663966] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff8801f5324400 for pipe B
>[  508.663967] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  508.663968] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  508.663969] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  508.663970] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  508.663971] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  508.663972] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  508.663973] [drm:intel_dump_pipe_config] requested mode:
>[  508.663974] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  508.663975] [drm:intel_dump_pipe_config] adjusted mode:
>[  508.663976] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  508.663978] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  508.663978] [drm:intel_dump_pipe_config] port clock: 270000
>[  508.663979] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  508.663980] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  508.663981] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  508.663982] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  508.663983] [drm:intel_dump_pipe_config] ips: 0
>[  508.663983] [drm:intel_dump_pipe_config] double wide: 0
>[  508.663984] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  508.663985] [drm:intel_dump_pipe_config] planes on this crtc
>[  508.663986] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  508.663987] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  508.663988] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  508.663990] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff8801f5327c00 state to ffff88020103c400
>[  508.663991] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff8801f5327800 state to ffff88020103c400
>[  508.663993] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 49
>[  508.663994] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  508.663996] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8801f55af480 state to ffff88020103c400
>[  508.663997] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8801f55afa80 state to ffff88020103c400
>[  508.663998] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8801f55afe40 state to ffff88020103c400
>[  508.664001] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f55af000 state to ffff88020103c400
>[  508.664002] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f55af9c0 state to ffff88020103c400
>[  508.664004] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8801f55af540 state to ffff88020103c400
>[  508.664005] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8801f55af900 state to ffff88020103c400
>[  508.664006] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8801f55af240 state to ffff88020103c400
>[  508.664007] [drm:drm_atomic_commit] commiting ffff88020103c400
>[  508.664012] [drm:intel_power_well_enable] enabling display
>[  508.664013] [drm:hsw_set_power_well] Enabling power well
>[  508.665271] [drm:intel_power_well_enable] enabling always-on
>[  508.665282] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  508.665283] [drm:intel_enable_shared_dpll] enabling SPLL
>[  508.666173] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  508.666237] [drm:intel_enable_pipe] enabling pipe B
>[  508.666251] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  508.733121] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  508.733126] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  508.733127] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  508.733129] [drm:check_crtc_state] [CRTC:25]
>[  508.733140] [drm:check_shared_dpll_state] WRPLL 1
>[  508.733141] [drm:check_shared_dpll_state] WRPLL 2
>[  508.733142] [drm:check_shared_dpll_state] SPLL
>[  508.733144] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88020103c400
>[  508.733148] [drm:drm_atomic_state_free] Freeing atomic state ffff88020103c400
>[  508.733194] [drm:drm_mode_setcrtc] [CRTC:25]
>[  508.733196] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bf3200
>[  508.733198] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880215be5c00 state to ffff880026bf3200
>[  508.733200] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f4cedd80 state to ffff880026bf3200
>[  508.733201] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff880215be5c00
>[  508.733202] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f4cedd80 to [NOCRTC]
>[  508.733203] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f4cedd80
>[  508.733205] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3200
>[  508.733206] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c0132660 state to ffff880026bf3200
>[  508.733208] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c0132660 to [NOCRTC]
>[  508.733209] [drm:drm_atomic_check_only] checking ffff880026bf3200
>[  508.733211] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  508.733212] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  508.733213] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  508.733214] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  508.733215] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  508.733216] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  508.733217] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3200
>[  508.733218] [drm:drm_atomic_connectors_for_crtc] State ffff880026bf3200 has 0 connectors for [CRTC:25]
>[  508.733221] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  508.733222] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  508.733224] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f4cedc00 state to ffff880026bf3200
>[  508.733225] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f4ced600 state to ffff880026bf3200
>[  508.733227] [drm:drm_atomic_commit] commiting ffff880026bf3200
>[  508.749787] [drm:intel_disable_pipe] disabling pipe B
>[  508.784259] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  508.784262] [drm:intel_disable_shared_dpll] disabling SPLL
>[  508.784270] [drm:intel_power_well_disable] disabling display
>[  508.784272] [drm:hsw_set_power_well] Requesting to disable the power well
>[  508.784273] [drm:intel_power_well_disable] disabling always-on
>[  508.784274] [drm:intel_power_well_enable] enabling display
>[  508.784275] [drm:hsw_set_power_well] Enabling power well
>[  508.786345] [drm:intel_power_well_disable] disabling display
>[  508.786349] [drm:hsw_set_power_well] Requesting to disable the power well
>[  508.786354] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  508.786356] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  508.786357] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  508.786360] [drm:check_crtc_state] [CRTC:25]
>[  508.786361] [drm:check_shared_dpll_state] WRPLL 1
>[  508.786363] [drm:check_shared_dpll_state] WRPLL 2
>[  508.786363] [drm:check_shared_dpll_state] SPLL
>[  508.786365] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bf3200
>[  508.786368] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bf3200
>[  508.786396] [drm:drm_mode_setcrtc] [CRTC:25]
>[  508.786399] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  508.786401] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bfb400
>[  508.786403] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880025a43000 state to ffff880026bfb400
>[  508.786405] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8800c78d4840 state to ffff880026bfb400
>[  508.786406] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff880025a43000
>[  508.786407] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800c78d4840 to [CRTC:25]
>[  508.786408] [drm:drm_atomic_set_fb_for_plane] Set [FB:51] for plane state ffff8800c78d4840
>[  508.786409] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8801f442dce0 state to ffff880026bfb400
>[  508.786410] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfb400
>[  508.786412] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f442dce0 to [CRTC:25]
>[  508.786413] [drm:drm_atomic_check_only] checking ffff880026bfb400
>[  508.786414] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  508.786415] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  508.786416] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  508.786418] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  508.786419] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  508.786420] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  508.786421] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfb400
>[  508.786422] [drm:drm_atomic_connectors_for_crtc] State ffff880026bfb400 has 1 connectors for [CRTC:25]
>[  508.786423] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfb400
>[  508.786425] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  508.786426] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  508.786428] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  508.786429] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  508.786430] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff880025a43000 for pipe B
>[  508.786431] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  508.786432] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  508.786433] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  508.786434] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  508.786435] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  508.786436] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  508.786437] [drm:intel_dump_pipe_config] requested mode:
>[  508.786439] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  508.786439] [drm:intel_dump_pipe_config] adjusted mode:
>[  508.786441] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  508.786442] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  508.786443] [drm:intel_dump_pipe_config] port clock: 270000
>[  508.786444] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  508.786445] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  508.786446] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  508.786447] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  508.786448] [drm:intel_dump_pipe_config] ips: 0
>[  508.786449] [drm:intel_dump_pipe_config] double wide: 0
>[  508.786450] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  508.786451] [drm:intel_dump_pipe_config] planes on this crtc
>[  508.786452] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  508.786453] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  508.786454] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  508.786456] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff880025a42000 state to ffff880026bfb400
>[  508.786458] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff880025a40800 state to ffff880026bfb400
>[  508.786460] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 51
>[  508.786461] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  508.786463] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8800c78d4540 state to ffff880026bfb400
>[  508.786464] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8800c78d4000 state to ffff880026bfb400
>[  508.786465] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8800c78d4240 state to ffff880026bfb400
>[  508.786468] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8800c78d4a80 state to ffff880026bfb400
>[  508.786470] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8800c78d4900 state to ffff880026bfb400
>[  508.786471] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8800c78d4600 state to ffff880026bfb400
>[  508.786473] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8800c78d4180 state to ffff880026bfb400
>[  508.786474] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8800c78d4cc0 state to ffff880026bfb400
>[  508.786475] [drm:drm_atomic_commit] commiting ffff880026bfb400
>[  508.786480] [drm:intel_power_well_enable] enabling display
>[  508.786481] [drm:hsw_set_power_well] Enabling power well
>[  508.788549] [drm:intel_power_well_enable] enabling always-on
>[  508.788560] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  508.788561] [drm:intel_enable_shared_dpll] enabling SPLL
>[  508.789451] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  508.789516] [drm:intel_enable_pipe] enabling pipe B
>[  508.789530] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  508.856398] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  508.856402] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  508.856403] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  508.856405] [drm:check_crtc_state] [CRTC:25]
>[  508.856416] [drm:check_shared_dpll_state] WRPLL 1
>[  508.856417] [drm:check_shared_dpll_state] WRPLL 2
>[  508.856418] [drm:check_shared_dpll_state] SPLL
>[  508.856420] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bfb400
>[  508.856424] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bfb400
>[  508.856451] [drm:drm_mode_setcrtc] [CRTC:25]
>[  508.856453] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bfb400
>[  508.856455] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880025a43400 state to ffff880026bfb400
>[  508.856456] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8800c78d4e40 state to ffff880026bfb400
>[  508.856457] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff880025a43400
>[  508.856458] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800c78d4e40 to [NOCRTC]
>[  508.856459] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8800c78d4e40
>[  508.856460] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfb400
>[  508.856461] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8801f442dee0 state to ffff880026bfb400
>[  508.856462] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f442dee0 to [NOCRTC]
>[  508.856463] [drm:drm_atomic_check_only] checking ffff880026bfb400
>[  508.856464] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  508.856465] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  508.856466] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  508.856467] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  508.856468] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  508.856469] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  508.856470] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfb400
>[  508.856471] [drm:drm_atomic_connectors_for_crtc] State ffff880026bfb400 has 0 connectors for [CRTC:25]
>[  508.856474] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  508.856475] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  508.856477] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8800c78d4300 state to ffff880026bfb400
>[  508.856478] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8800c78d49c0 state to ffff880026bfb400
>[  508.856480] [drm:drm_atomic_commit] commiting ffff880026bfb400
>[  508.857317] [drm:intel_print_rc6_info] Enabling RC6 states: RC6 on
>[  508.861200] [drm:gen6_enable_rps] Overclocking supported. Max: 1100MHz, Overclock max: 1100MHz
>[  508.873061] [drm:intel_disable_pipe] disabling pipe B
>[  508.907821] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  508.907824] [drm:intel_disable_shared_dpll] disabling SPLL
>[  508.907832] [drm:intel_power_well_disable] disabling display
>[  508.907834] [drm:hsw_set_power_well] Requesting to disable the power well
>[  508.907835] [drm:intel_power_well_disable] disabling always-on
>[  508.907842] [drm:intel_runtime_suspend] Suspending device
>[  508.907943] [drm:hsw_enable_pc8] Enabling package C8+
>[  508.919297] [drm:intel_runtime_suspend] Device suspended
>[  508.925249] [drm:intel_runtime_resume] Resuming device
>[  508.927315] [drm:hsw_disable_pc8] Disabling package C8+
>[  508.931258] [drm:intel_update_cdclk] Current CD clock rate: 540000 kHz
>[  509.044393] [drm:intel_runtime_resume] Device resumed
>[  509.044397] [drm:intel_power_well_enable] enabling display
>[  509.044399] [drm:hsw_set_power_well] Enabling power well
>[  509.046468] [drm:intel_power_well_disable] disabling display
>[  509.046471] [drm:hsw_set_power_well] Requesting to disable the power well
>[  509.046476] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  509.046478] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  509.046480] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  509.046483] [drm:check_crtc_state] [CRTC:25]
>[  509.046484] [drm:check_shared_dpll_state] WRPLL 1
>[  509.046485] [drm:check_shared_dpll_state] WRPLL 2
>[  509.046486] [drm:check_shared_dpll_state] SPLL
>[  509.046488] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bfb400
>[  509.046490] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bfb400
>[  509.046519] [drm:drm_mode_setcrtc] [CRTC:25]
>[  509.046522] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  509.046524] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bf3600
>[  509.046526] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880215be4000 state to ffff880026bf3600
>[  509.046528] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f4cedb40 state to ffff880026bf3600
>[  509.046529] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff880215be4000
>[  509.046530] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f4cedb40 to [CRTC:25]
>[  509.046531] [drm:drm_atomic_set_fb_for_plane] Set [FB:49] for plane state ffff8801f4cedb40
>[  509.046532] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c01320c0 state to ffff880026bf3600
>[  509.046533] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3600
>[  509.046534] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c01320c0 to [CRTC:25]
>[  509.046535] [drm:drm_atomic_check_only] checking ffff880026bf3600
>[  509.046537] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  509.046537] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  509.046539] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  509.046540] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  509.046541] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  509.046542] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  509.046542] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3600
>[  509.046544] [drm:drm_atomic_connectors_for_crtc] State ffff880026bf3600 has 1 connectors for [CRTC:25]
>[  509.046545] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3600
>[  509.046546] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  509.046547] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  509.046549] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  509.046550] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  509.046551] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff880215be4000 for pipe B
>[  509.046552] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  509.046553] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  509.046554] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  509.046555] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  509.046556] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  509.046557] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  509.046557] [drm:intel_dump_pipe_config] requested mode:
>[  509.046559] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  509.046560] [drm:intel_dump_pipe_config] adjusted mode:
>[  509.046561] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  509.046563] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  509.046563] [drm:intel_dump_pipe_config] port clock: 270000
>[  509.046564] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  509.046565] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  509.046566] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  509.046567] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  509.046567] [drm:intel_dump_pipe_config] ips: 0
>[  509.046568] [drm:intel_dump_pipe_config] double wide: 0
>[  509.046569] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  509.046570] [drm:intel_dump_pipe_config] planes on this crtc
>[  509.046571] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  509.046572] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  509.046573] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  509.046575] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff880215be5c00 state to ffff880026bf3600
>[  509.046576] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff880215be4400 state to ffff880026bf3600
>[  509.046578] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 49
>[  509.046579] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  509.046581] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8801f4ced780 state to ffff880026bf3600
>[  509.046582] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8801f4ced900 state to ffff880026bf3600
>[  509.046583] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8801f4ced480 state to ffff880026bf3600
>[  509.046585] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f4ced6c0 state to ffff880026bf3600
>[  509.046587] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f4ceda80 state to ffff880026bf3600
>[  509.046588] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8801f4ced000 state to ffff880026bf3600
>[  509.046589] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8801f4ced840 state to ffff880026bf3600
>[  509.046591] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8801f4ced540 state to ffff880026bf3600
>[  509.046592] [drm:drm_atomic_commit] commiting ffff880026bf3600
>[  509.046597] [drm:intel_power_well_enable] enabling display
>[  509.046598] [drm:hsw_set_power_well] Enabling power well
>[  509.048666] [drm:intel_power_well_enable] enabling always-on
>[  509.048676] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  509.048677] [drm:intel_enable_shared_dpll] enabling SPLL
>[  509.049567] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  509.049631] [drm:intel_enable_pipe] enabling pipe B
>[  509.049644] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  509.116515] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  509.116520] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  509.116521] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  509.116523] [drm:check_crtc_state] [CRTC:25]
>[  509.116534] [drm:check_shared_dpll_state] WRPLL 1
>[  509.116535] [drm:check_shared_dpll_state] WRPLL 2
>[  509.116536] [drm:check_shared_dpll_state] SPLL
>[  509.116538] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bf3600
>[  509.116542] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bf3600
>[  509.116568] [drm:drm_mode_setcrtc] [CRTC:25]
>[  509.116570] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bf3600
>[  509.116572] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880215be6400 state to ffff880026bf3600
>[  509.116574] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f4ced240 state to ffff880026bf3600
>[  509.116575] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff880215be6400
>[  509.116576] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f4ced240 to [NOCRTC]
>[  509.116577] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f4ced240
>[  509.116578] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3600
>[  509.116579] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c0132760 state to ffff880026bf3600
>[  509.116580] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c0132760 to [NOCRTC]
>[  509.116581] [drm:drm_atomic_check_only] checking ffff880026bf3600
>[  509.116582] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  509.116583] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  509.116584] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  509.116585] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  509.116586] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  509.116587] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  509.116588] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3600
>[  509.116589] [drm:drm_atomic_connectors_for_crtc] State ffff880026bf3600 has 0 connectors for [CRTC:25]
>[  509.116592] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  509.116593] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  509.116594] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f4ced9c0 state to ffff880026bf3600
>[  509.116596] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f4ced180 state to ffff880026bf3600
>[  509.116598] [drm:drm_atomic_commit] commiting ffff880026bf3600
>[  509.133181] [drm:intel_disable_pipe] disabling pipe B
>[  509.168198] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  509.168201] [drm:intel_disable_shared_dpll] disabling SPLL
>[  509.168209] [drm:intel_power_well_disable] disabling display
>[  509.168210] [drm:hsw_set_power_well] Requesting to disable the power well
>[  509.168211] [drm:intel_power_well_disable] disabling always-on
>[  509.168213] [drm:intel_power_well_enable] enabling display
>[  509.168214] [drm:hsw_set_power_well] Enabling power well
>[  509.170284] [drm:intel_power_well_disable] disabling display
>[  509.170288] [drm:hsw_set_power_well] Requesting to disable the power well
>[  509.170293] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  509.170295] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  509.170296] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  509.170299] [drm:check_crtc_state] [CRTC:25]
>[  509.170301] [drm:check_shared_dpll_state] WRPLL 1
>[  509.170302] [drm:check_shared_dpll_state] WRPLL 2
>[  509.170303] [drm:check_shared_dpll_state] SPLL
>[  509.170305] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bf3600
>[  509.170307] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bf3600
>[  509.170335] [drm:drm_mode_setcrtc] [CRTC:25]
>[  509.170338] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  509.170340] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bfba00
>[  509.170342] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880025a43c00 state to ffff880026bfba00
>[  509.170344] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8800c78d4d80 state to ffff880026bfba00
>[  509.170345] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff880025a43c00
>[  509.170346] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800c78d4d80 to [CRTC:25]
>[  509.170347] [drm:drm_atomic_set_fb_for_plane] Set [FB:51] for plane state ffff8800c78d4d80
>[  509.170348] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8801f442d1c0 state to ffff880026bfba00
>[  509.170349] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfba00
>[  509.170350] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f442d1c0 to [CRTC:25]
>[  509.170351] [drm:drm_atomic_check_only] checking ffff880026bfba00
>[  509.170353] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  509.170354] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  509.170355] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  509.170356] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  509.170357] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  509.170358] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  509.170359] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfba00
>[  509.170360] [drm:drm_atomic_connectors_for_crtc] State ffff880026bfba00 has 1 connectors for [CRTC:25]
>[  509.170362] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfba00
>[  509.170363] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  509.170364] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  509.170366] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  509.170366] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  509.170368] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff880025a43c00 for pipe B
>[  509.170369] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  509.170369] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  509.170371] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  509.170372] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  509.170373] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  509.170374] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  509.170374] [drm:intel_dump_pipe_config] requested mode:
>[  509.170376] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  509.170377] [drm:intel_dump_pipe_config] adjusted mode:
>[  509.170378] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  509.170379] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  509.170380] [drm:intel_dump_pipe_config] port clock: 270000
>[  509.170381] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  509.170381] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  509.170382] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  509.170383] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  509.170384] [drm:intel_dump_pipe_config] ips: 0
>[  509.170385] [drm:intel_dump_pipe_config] double wide: 0
>[  509.170386] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  509.170386] [drm:intel_dump_pipe_config] planes on this crtc
>[  509.170388] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  509.170389] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  509.170390] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  509.170391] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff880025a40c00 state to ffff880026bfba00
>[  509.170393] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff880025a42800 state to ffff880026bfba00
>[  509.170395] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 51
>[  509.170396] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  509.170397] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8800c78d4c00 state to ffff880026bfba00
>[  509.170398] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8800c78d4b40 state to ffff880026bfba00
>[  509.170400] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8800c78d40c0 state to ffff880026bfba00
>[  509.170402] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8800c78d46c0 state to ffff880026bfba00
>[  509.170404] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8800c78d4cc0 state to ffff880026bfba00
>[  509.170405] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8800c78d4180 state to ffff880026bfba00
>[  509.170406] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8800c78d4600 state to ffff880026bfba00
>[  509.170408] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8800c78d49c0 state to ffff880026bfba00
>[  509.170409] [drm:drm_atomic_commit] commiting ffff880026bfba00
>[  509.170414] [drm:intel_power_well_enable] enabling display
>[  509.170415] [drm:hsw_set_power_well] Enabling power well
>[  509.172483] [drm:intel_power_well_enable] enabling always-on
>[  509.172493] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  509.172495] [drm:intel_enable_shared_dpll] enabling SPLL
>[  509.173384] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  509.173449] [drm:intel_enable_pipe] enabling pipe B
>[  509.173464] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  509.240308] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  509.240312] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  509.240313] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  509.240315] [drm:check_crtc_state] [CRTC:25]
>[  509.240326] [drm:check_shared_dpll_state] WRPLL 1
>[  509.240327] [drm:check_shared_dpll_state] WRPLL 2
>[  509.240328] [drm:check_shared_dpll_state] SPLL
>[  509.240330] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bfba00
>[  509.240334] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bfba00
>[  509.240361] [drm:drm_mode_setcrtc] [CRTC:25]
>[  509.240364] [drm:drm_atomic_state_init] Allocated atomic state ffff88020103c200
>[  509.240366] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5325000 state to ffff88020103c200
>[  509.240367] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f55af3c0 state to ffff88020103c200
>[  509.240369] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f5325000
>[  509.240369] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55af3c0 to [NOCRTC]
>[  509.240371] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f55af3c0
>[  509.240372] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103c200
>[  509.240373] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c909b0c0 state to ffff88020103c200
>[  509.240374] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c909b0c0 to [NOCRTC]
>[  509.240375] [drm:drm_atomic_check_only] checking ffff88020103c200
>[  509.240376] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  509.240377] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  509.240378] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  509.240379] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  509.240379] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  509.240380] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  509.240381] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103c200
>[  509.240383] [drm:drm_atomic_connectors_for_crtc] State ffff88020103c200 has 0 connectors for [CRTC:25]
>[  509.240385] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  509.240386] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  509.240388] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f55af0c0 state to ffff88020103c200
>[  509.240389] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f55af180 state to ffff88020103c200
>[  509.240391] [drm:drm_atomic_commit] commiting ffff88020103c200
>[  509.257000] [drm:intel_disable_pipe] disabling pipe B
>[  509.291793] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  509.291796] [drm:intel_disable_shared_dpll] disabling SPLL
>[  509.291804] [drm:intel_power_well_disable] disabling display
>[  509.291806] [drm:hsw_set_power_well] Requesting to disable the power well
>[  509.291807] [drm:intel_power_well_disable] disabling always-on
>[  509.291808] [drm:intel_power_well_enable] enabling display
>[  509.291809] [drm:hsw_set_power_well] Enabling power well
>[  509.293212] [drm:intel_power_well_disable] disabling display
>[  509.293216] [drm:hsw_set_power_well] Requesting to disable the power well
>[  509.293222] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  509.293224] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  509.293226] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  509.293230] [drm:check_crtc_state] [CRTC:25]
>[  509.293232] [drm:check_shared_dpll_state] WRPLL 1
>[  509.293233] [drm:check_shared_dpll_state] WRPLL 2
>[  509.293234] [drm:check_shared_dpll_state] SPLL
>[  509.293236] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88020103c200
>[  509.293239] [drm:drm_atomic_state_free] Freeing atomic state ffff88020103c200
>[  509.293264] [drm:drm_mode_setcrtc] [CRTC:25]
>[  509.293267] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  509.293269] [drm:drm_atomic_state_init] Allocated atomic state ffff880210d7b800
>[  509.293273] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5492c00 state to ffff880210d7b800
>[  509.293275] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f5fde6c0 state to ffff880210d7b800
>[  509.293277] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f5492c00
>[  509.293278] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f5fde6c0 to [CRTC:25]
>[  509.293280] [drm:drm_atomic_set_fb_for_plane] Set [FB:49] for plane state ffff8801f5fde6c0
>[  509.293281] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800d3bbacc0 state to ffff880210d7b800
>[  509.293283] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b800
>[  509.293283] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800d3bbacc0 to [CRTC:25]
>[  509.293285] [drm:drm_atomic_check_only] checking ffff880210d7b800
>[  509.293287] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  509.293288] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  509.293289] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  509.293290] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  509.293291] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  509.293292] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  509.293293] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b800
>[  509.293295] [drm:drm_atomic_connectors_for_crtc] State ffff880210d7b800 has 1 connectors for [CRTC:25]
>[  509.293297] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b800
>[  509.293299] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  509.293299] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  509.293301] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  509.293302] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  509.293304] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff8801f5492c00 for pipe B
>[  509.293305] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  509.293306] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  509.293308] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  509.293310] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  509.293311] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  509.293311] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  509.293312] [drm:intel_dump_pipe_config] requested mode:
>[  509.293314] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  509.293315] [drm:intel_dump_pipe_config] adjusted mode:
>[  509.293317] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  509.293319] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  509.293320] [drm:intel_dump_pipe_config] port clock: 270000
>[  509.293320] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  509.293321] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  509.293322] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  509.293324] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  509.293325] [drm:intel_dump_pipe_config] ips: 0
>[  509.293325] [drm:intel_dump_pipe_config] double wide: 0
>[  509.293326] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  509.293327] [drm:intel_dump_pipe_config] planes on this crtc
>[  509.293328] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  509.293329] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  509.293330] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  509.293332] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff8801f5490800 state to ffff880210d7b800
>[  509.293333] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff8801f5493800 state to ffff880210d7b800
>[  509.293335] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 49
>[  509.293336] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  509.293338] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8801f5fdef00 state to ffff880210d7b800
>[  509.293339] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8801f5fde900 state to ffff880210d7b800
>[  509.293340] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8801f5fde0c0 state to ffff880210d7b800
>[  509.293343] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f5fde180 state to ffff880210d7b800
>[  509.293345] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f5fdeb40 state to ffff880210d7b800
>[  509.293346] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8801f5fde000 state to ffff880210d7b800
>[  509.293347] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8801f5fdecc0 state to ffff880210d7b800
>[  509.293349] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8801f5fde3c0 state to ffff880210d7b800
>[  509.293350] [drm:drm_atomic_commit] commiting ffff880210d7b800
>[  509.293355] [drm:intel_power_well_enable] enabling display
>[  509.293356] [drm:hsw_set_power_well] Enabling power well
>[  509.295424] [drm:intel_power_well_enable] enabling always-on
>[  509.295434] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  509.295435] [drm:intel_enable_shared_dpll] enabling SPLL
>[  509.296324] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  509.296395] [drm:intel_enable_pipe] enabling pipe B
>[  509.296409] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  509.363275] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  509.363280] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  509.363281] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  509.363283] [drm:check_crtc_state] [CRTC:25]
>[  509.363294] [drm:check_shared_dpll_state] WRPLL 1
>[  509.363295] [drm:check_shared_dpll_state] WRPLL 2
>[  509.363296] [drm:check_shared_dpll_state] SPLL
>[  509.363298] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880210d7b800
>[  509.363302] [drm:drm_atomic_state_free] Freeing atomic state ffff880210d7b800
>[  509.363329] [drm:drm_mode_setcrtc] [CRTC:25]
>[  509.363331] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bf3600
>[  509.363334] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880215be4800 state to ffff880026bf3600
>[  509.363335] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f4ced0c0 state to ffff880026bf3600
>[  509.363336] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff880215be4800
>[  509.363337] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f4ced0c0 to [NOCRTC]
>[  509.363338] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f4ced0c0
>[  509.363340] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3600
>[  509.363341] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c0132f40 state to ffff880026bf3600
>[  509.363341] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c0132f40 to [NOCRTC]
>[  509.363342] [drm:drm_atomic_check_only] checking ffff880026bf3600
>[  509.363344] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  509.363344] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  509.363346] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  509.363346] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  509.363347] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  509.363348] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  509.363349] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3600
>[  509.363350] [drm:drm_atomic_connectors_for_crtc] State ffff880026bf3600 has 0 connectors for [CRTC:25]
>[  509.363353] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  509.363354] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  509.363356] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f4ced540 state to ffff880026bf3600
>[  509.363357] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f4ced840 state to ffff880026bf3600
>[  509.363359] [drm:drm_atomic_commit] commiting ffff880026bf3600
>[  509.379938] [drm:intel_disable_pipe] disabling pipe B
>[  509.414264] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  509.414267] [drm:intel_disable_shared_dpll] disabling SPLL
>[  509.414274] [drm:intel_power_well_disable] disabling display
>[  509.414276] [drm:hsw_set_power_well] Requesting to disable the power well
>[  509.414277] [drm:intel_power_well_disable] disabling always-on
>[  509.414278] [drm:intel_power_well_enable] enabling display
>[  509.414279] [drm:hsw_set_power_well] Enabling power well
>[  509.416347] [drm:intel_power_well_disable] disabling display
>[  509.416351] [drm:hsw_set_power_well] Requesting to disable the power well
>[  509.416356] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  509.416358] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  509.416359] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  509.416362] [drm:check_crtc_state] [CRTC:25]
>[  509.416363] [drm:check_shared_dpll_state] WRPLL 1
>[  509.416364] [drm:check_shared_dpll_state] WRPLL 2
>[  509.416365] [drm:check_shared_dpll_state] SPLL
>[  509.416367] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bf3600
>[  509.416369] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bf3600
>[  509.416398] [drm:drm_mode_setcrtc] [CRTC:25]
>[  509.416401] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  509.416403] [drm:drm_atomic_state_init] Allocated atomic state ffff880210d7b400
>[  509.416405] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5492c00 state to ffff880210d7b400
>[  509.416406] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f5fdeb40 state to ffff880210d7b400
>[  509.416408] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f5492c00
>[  509.416409] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f5fdeb40 to [CRTC:25]
>[  509.416410] [drm:drm_atomic_set_fb_for_plane] Set [FB:51] for plane state ffff8801f5fdeb40
>[  509.416411] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800d3bba580 state to ffff880210d7b400
>[  509.416412] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b400
>[  509.416413] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800d3bba580 to [CRTC:25]
>[  509.416414] [drm:drm_atomic_check_only] checking ffff880210d7b400
>[  509.416415] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  509.416416] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  509.416417] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  509.416419] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  509.416419] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  509.416420] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  509.416421] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b400
>[  509.416422] [drm:drm_atomic_connectors_for_crtc] State ffff880210d7b400 has 1 connectors for [CRTC:25]
>[  509.416424] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b400
>[  509.416425] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  509.416426] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  509.416428] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  509.416429] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  509.416430] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff8801f5492c00 for pipe B
>[  509.416431] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  509.416432] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  509.416433] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  509.416434] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  509.416435] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  509.416436] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  509.416437] [drm:intel_dump_pipe_config] requested mode:
>[  509.416438] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  509.416439] [drm:intel_dump_pipe_config] adjusted mode:
>[  509.416440] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  509.416442] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  509.416442] [drm:intel_dump_pipe_config] port clock: 270000
>[  509.416443] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  509.416444] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  509.416445] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  509.416446] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  509.416447] [drm:intel_dump_pipe_config] ips: 0
>[  509.416447] [drm:intel_dump_pipe_config] double wide: 0
>[  509.416448] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  509.416449] [drm:intel_dump_pipe_config] planes on this crtc
>[  509.416450] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  509.416451] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  509.416452] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  509.416454] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff8801f5491c00 state to ffff880210d7b400
>[  509.416455] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff8801f5490c00 state to ffff880210d7b400
>[  509.416457] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 51
>[  509.416458] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  509.416460] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8801f5fde6c0 state to ffff880210d7b400
>[  509.416461] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8801f5fde9c0 state to ffff880210d7b400
>[  509.416462] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8801f5fdee40 state to ffff880210d7b400
>[  509.416464] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f5fde840 state to ffff880210d7b400
>[  509.416465] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f5fde480 state to ffff880210d7b400
>[  509.416467] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8801f5fded80 state to ffff880210d7b400
>[  509.416468] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8801f5fdea80 state to ffff880210d7b400
>[  509.416469] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8801f5fde600 state to ffff880210d7b400
>[  509.416471] [drm:drm_atomic_commit] commiting ffff880210d7b400
>[  509.416475] [drm:intel_power_well_enable] enabling display
>[  509.416477] [drm:hsw_set_power_well] Enabling power well
>[  509.418544] [drm:intel_power_well_enable] enabling always-on
>[  509.418555] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  509.418556] [drm:intel_enable_shared_dpll] enabling SPLL
>[  509.419454] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  509.419516] [drm:intel_enable_pipe] enabling pipe B
>[  509.419529] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  509.486367] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  509.486372] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  509.486373] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  509.486375] [drm:check_crtc_state] [CRTC:25]
>[  509.486386] [drm:check_shared_dpll_state] WRPLL 1
>[  509.486387] [drm:check_shared_dpll_state] WRPLL 2
>[  509.486388] [drm:check_shared_dpll_state] SPLL
>[  509.486390] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880210d7b400
>[  509.486393] [drm:drm_atomic_state_free] Freeing atomic state ffff880210d7b400
>[  509.486421] [drm:drm_mode_setcrtc] [CRTC:25]
>[  509.486424] [drm:drm_atomic_state_init] Allocated atomic state ffff88020103c000
>[  509.486426] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5324000 state to ffff88020103c000
>[  509.486427] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f55af840 state to ffff88020103c000
>[  509.486428] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f5324000
>[  509.486429] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55af840 to [NOCRTC]
>[  509.486430] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f55af840
>[  509.486431] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103c000
>[  509.486432] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c909bb80 state to ffff88020103c000
>[  509.486433] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c909bb80 to [NOCRTC]
>[  509.486434] [drm:drm_atomic_check_only] checking ffff88020103c000
>[  509.486436] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  509.486436] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  509.486437] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  509.486438] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  509.486439] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  509.486440] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  509.486441] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103c000
>[  509.486442] [drm:drm_atomic_connectors_for_crtc] State ffff88020103c000 has 0 connectors for [CRTC:25]
>[  509.486445] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  509.486446] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  509.486448] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f55af780 state to ffff88020103c000
>[  509.486449] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f55af300 state to ffff88020103c000
>[  509.486451] [drm:drm_atomic_commit] commiting ffff88020103c000
>[  509.503055] [drm:intel_disable_pipe] disabling pipe B
>[  509.537233] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  509.537236] [drm:intel_disable_shared_dpll] disabling SPLL
>[  509.537244] [drm:intel_power_well_disable] disabling display
>[  509.537246] [drm:hsw_set_power_well] Requesting to disable the power well
>[  509.537247] [drm:intel_power_well_disable] disabling always-on
>[  509.537248] [drm:intel_power_well_enable] enabling display
>[  509.537249] [drm:hsw_set_power_well] Enabling power well
>[  509.539318] [drm:intel_power_well_disable] disabling display
>[  509.539322] [drm:hsw_set_power_well] Requesting to disable the power well
>[  509.539327] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  509.539329] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  509.539331] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  509.539333] [drm:check_crtc_state] [CRTC:25]
>[  509.539334] [drm:check_shared_dpll_state] WRPLL 1
>[  509.539336] [drm:check_shared_dpll_state] WRPLL 2
>[  509.539336] [drm:check_shared_dpll_state] SPLL
>[  509.539338] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88020103c000
>[  509.539341] [drm:drm_atomic_state_free] Freeing atomic state ffff88020103c000
>[  509.539369] [drm:drm_mode_setcrtc] [CRTC:25]
>[  509.539372] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  509.539374] [drm:drm_atomic_state_init] Allocated atomic state ffff880210d7b400
>[  509.539376] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5492c00 state to ffff880210d7b400
>[  509.539377] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f5fde480 state to ffff880210d7b400
>[  509.539379] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f5492c00
>[  509.539380] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f5fde480 to [CRTC:25]
>[  509.539381] [drm:drm_atomic_set_fb_for_plane] Set [FB:49] for plane state ffff8801f5fde480
>[  509.539382] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800d3bbac80 state to ffff880210d7b400
>[  509.539383] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b400
>[  509.539384] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800d3bbac80 to [CRTC:25]
>[  509.539385] [drm:drm_atomic_check_only] checking ffff880210d7b400
>[  509.539386] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  509.539387] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  509.539388] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  509.539389] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  509.539390] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  509.539391] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  509.539392] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b400
>[  509.539393] [drm:drm_atomic_connectors_for_crtc] State ffff880210d7b400 has 1 connectors for [CRTC:25]
>[  509.539395] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b400
>[  509.539396] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  509.539397] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  509.539399] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  509.539400] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  509.539401] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff8801f5492c00 for pipe B
>[  509.539402] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  509.539403] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  509.539404] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  509.539405] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  509.539406] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  509.539407] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  509.539407] [drm:intel_dump_pipe_config] requested mode:
>[  509.539409] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  509.539410] [drm:intel_dump_pipe_config] adjusted mode:
>[  509.539411] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  509.539412] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  509.539413] [drm:intel_dump_pipe_config] port clock: 270000
>[  509.539414] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  509.539415] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  509.539416] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  509.539417] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  509.539417] [drm:intel_dump_pipe_config] ips: 0
>[  509.539418] [drm:intel_dump_pipe_config] double wide: 0
>[  509.539419] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  509.539420] [drm:intel_dump_pipe_config] planes on this crtc
>[  509.539421] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  509.539422] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  509.539423] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  509.539425] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff8801f5493400 state to ffff880210d7b400
>[  509.539426] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff8801f5493800 state to ffff880210d7b400
>[  509.539428] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 49
>[  509.539429] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  509.539430] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8801f5fdeb40 state to ffff880210d7b400
>[  509.539432] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8801f5fde180 state to ffff880210d7b400
>[  509.539433] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8801f5fde540 state to ffff880210d7b400
>[  509.539435] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f5fdec00 state to ffff880210d7b400
>[  509.539436] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f5fde780 state to ffff880210d7b400
>[  509.539438] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8801f5fde3c0 state to ffff880210d7b400
>[  509.539439] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8801f5fdecc0 state to ffff880210d7b400
>[  509.539440] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8801f5fde000 state to ffff880210d7b400
>[  509.539441] [drm:drm_atomic_commit] commiting ffff880210d7b400
>[  509.539446] [drm:intel_power_well_enable] enabling display
>[  509.539447] [drm:hsw_set_power_well] Enabling power well
>[  509.541193] [drm:intel_power_well_enable] enabling always-on
>[  509.541204] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  509.541206] [drm:intel_enable_shared_dpll] enabling SPLL
>[  509.542096] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  509.542160] [drm:intel_enable_pipe] enabling pipe B
>[  509.542173] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  509.609041] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  509.609046] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  509.609047] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  509.609049] [drm:check_crtc_state] [CRTC:25]
>[  509.609060] [drm:check_shared_dpll_state] WRPLL 1
>[  509.609061] [drm:check_shared_dpll_state] WRPLL 2
>[  509.609062] [drm:check_shared_dpll_state] SPLL
>[  509.609064] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880210d7b400
>[  509.609067] [drm:drm_atomic_state_free] Freeing atomic state ffff880210d7b400
>[  509.609094] [drm:drm_mode_setcrtc] [CRTC:25]
>[  509.609115] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bf3200
>[  509.609117] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880215be5000 state to ffff880026bf3200
>[  509.609119] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f4ced000 state to ffff880026bf3200
>[  509.609120] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff880215be5000
>[  509.609121] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f4ced000 to [NOCRTC]
>[  509.609122] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f4ced000
>[  509.609124] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3200
>[  509.609125] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c0132440 state to ffff880026bf3200
>[  509.609126] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c0132440 to [NOCRTC]
>[  509.609127] [drm:drm_atomic_check_only] checking ffff880026bf3200
>[  509.609128] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  509.609130] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  509.609131] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  509.609133] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  509.609134] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  509.609135] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  509.609136] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3200
>[  509.609137] [drm:drm_atomic_connectors_for_crtc] State ffff880026bf3200 has 0 connectors for [CRTC:25]
>[  509.609140] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  509.609141] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  509.609143] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f4ced180 state to ffff880026bf3200
>[  509.609144] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f4ced9c0 state to ffff880026bf3200
>[  509.609146] [drm:drm_atomic_commit] commiting ffff880026bf3200
>[  509.625716] [drm:intel_disable_pipe] disabling pipe B
>[  509.660218] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  509.660221] [drm:intel_disable_shared_dpll] disabling SPLL
>[  509.660229] [drm:intel_power_well_disable] disabling display
>[  509.660231] [drm:hsw_set_power_well] Requesting to disable the power well
>[  509.660232] [drm:intel_power_well_disable] disabling always-on
>[  509.660233] [drm:intel_power_well_enable] enabling display
>[  509.660234] [drm:hsw_set_power_well] Enabling power well
>[  509.662303] [drm:intel_power_well_disable] disabling display
>[  509.662307] [drm:hsw_set_power_well] Requesting to disable the power well
>[  509.662312] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  509.662314] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  509.662316] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  509.662318] [drm:check_crtc_state] [CRTC:25]
>[  509.662320] [drm:check_shared_dpll_state] WRPLL 1
>[  509.662321] [drm:check_shared_dpll_state] WRPLL 2
>[  509.662322] [drm:check_shared_dpll_state] SPLL
>[  509.662324] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bf3200
>[  509.662326] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bf3200
>[  509.662354] [drm:drm_mode_setcrtc] [CRTC:25]
>[  509.662357] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  509.662359] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bf3200
>[  509.662361] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880215be4800 state to ffff880026bf3200
>[  509.662362] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f4ced240 state to ffff880026bf3200
>[  509.662364] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff880215be4800
>[  509.662365] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f4ced240 to [CRTC:25]
>[  509.662366] [drm:drm_atomic_set_fb_for_plane] Set [FB:51] for plane state ffff8801f4ced240
>[  509.662367] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c0132820 state to ffff880026bf3200
>[  509.662368] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3200
>[  509.662369] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c0132820 to [CRTC:25]
>[  509.662370] [drm:drm_atomic_check_only] checking ffff880026bf3200
>[  509.662372] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  509.662372] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  509.662373] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  509.662375] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  509.662376] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  509.662376] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  509.662377] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3200
>[  509.662379] [drm:drm_atomic_connectors_for_crtc] State ffff880026bf3200 has 1 connectors for [CRTC:25]
>[  509.662380] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3200
>[  509.662381] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  509.662382] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  509.662384] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  509.662385] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  509.662386] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff880215be4800 for pipe B
>[  509.662387] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  509.662388] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  509.662389] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  509.662390] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  509.662391] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  509.662392] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  509.662393] [drm:intel_dump_pipe_config] requested mode:
>[  509.662394] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  509.662395] [drm:intel_dump_pipe_config] adjusted mode:
>[  509.662396] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  509.662398] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  509.662398] [drm:intel_dump_pipe_config] port clock: 270000
>[  509.662399] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  509.662400] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  509.662401] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  509.662402] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  509.662403] [drm:intel_dump_pipe_config] ips: 0
>[  509.662403] [drm:intel_dump_pipe_config] double wide: 0
>[  509.662404] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  509.662405] [drm:intel_dump_pipe_config] planes on this crtc
>[  509.662406] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  509.662407] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  509.662408] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  509.662410] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff880215be4400 state to ffff880026bf3200
>[  509.662411] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff880215be6400 state to ffff880026bf3200
>[  509.662413] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 51
>[  509.662414] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  509.662416] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8801f4ced900 state to ffff880026bf3200
>[  509.662417] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8801f4ced780 state to ffff880026bf3200
>[  509.662418] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8801f4ceda80 state to ffff880026bf3200
>[  509.662421] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f4ced6c0 state to ffff880026bf3200
>[  509.662422] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f4cedb40 state to ffff880026bf3200
>[  509.662423] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8801f4ced3c0 state to ffff880026bf3200
>[  509.662425] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8801f4ced600 state to ffff880026bf3200
>[  509.662426] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8801f4cedc00 state to ffff880026bf3200
>[  509.662427] [drm:drm_atomic_commit] commiting ffff880026bf3200
>[  509.662432] [drm:intel_power_well_enable] enabling display
>[  509.662433] [drm:hsw_set_power_well] Enabling power well
>[  509.664501] [drm:intel_power_well_enable] enabling always-on
>[  509.664512] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  509.664513] [drm:intel_enable_shared_dpll] enabling SPLL
>[  509.665403] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  509.665469] [drm:intel_enable_pipe] enabling pipe B
>[  509.665482] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  509.732319] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  509.732324] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  509.732325] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  509.732327] [drm:check_crtc_state] [CRTC:25]
>[  509.732338] [drm:check_shared_dpll_state] WRPLL 1
>[  509.732339] [drm:check_shared_dpll_state] WRPLL 2
>[  509.732340] [drm:check_shared_dpll_state] SPLL
>[  509.732341] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bf3200
>[  509.732345] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bf3200
>[  509.732373] [drm:drm_mode_setcrtc] [CRTC:25]
>[  509.732375] [drm:drm_atomic_state_init] Allocated atomic state ffff88020103d200
>[  509.732377] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5326000 state to ffff88020103d200
>[  509.732379] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f55afb40 state to ffff88020103d200
>[  509.732380] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f5326000
>[  509.732381] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55afb40 to [NOCRTC]
>[  509.732382] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f55afb40
>[  509.732383] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103d200
>[  509.732384] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c909b8c0 state to ffff88020103d200
>[  509.732385] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c909b8c0 to [NOCRTC]
>[  509.732386] [drm:drm_atomic_check_only] checking ffff88020103d200
>[  509.732387] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  509.732388] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  509.732389] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  509.732390] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  509.732390] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  509.732391] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  509.732392] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103d200
>[  509.732394] [drm:drm_atomic_connectors_for_crtc] State ffff88020103d200 has 0 connectors for [CRTC:25]
>[  509.732396] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  509.732398] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  509.732399] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f55af6c0 state to ffff88020103d200
>[  509.732400] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f55afc00 state to ffff88020103d200
>[  509.732402] [drm:drm_atomic_commit] commiting ffff88020103d200
>[  509.749010] [drm:intel_disable_pipe] disabling pipe B
>[  509.783751] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  509.783754] [drm:intel_disable_shared_dpll] disabling SPLL
>[  509.783762] [drm:intel_power_well_disable] disabling display
>[  509.783764] [drm:hsw_set_power_well] Requesting to disable the power well
>[  509.783765] [drm:intel_power_well_disable] disabling always-on
>[  509.783766] [drm:intel_power_well_enable] enabling display
>[  509.783767] [drm:hsw_set_power_well] Enabling power well
>[  509.785171] [drm:intel_power_well_disable] disabling display
>[  509.785175] [drm:hsw_set_power_well] Requesting to disable the power well
>[  509.785181] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  509.785183] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  509.785185] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  509.785187] [drm:check_crtc_state] [CRTC:25]
>[  509.785189] [drm:check_shared_dpll_state] WRPLL 1
>[  509.785190] [drm:check_shared_dpll_state] WRPLL 2
>[  509.785191] [drm:check_shared_dpll_state] SPLL
>[  509.785193] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88020103d200
>[  509.785195] [drm:drm_atomic_state_free] Freeing atomic state ffff88020103d200
>[  509.785220] [drm:drm_mode_setcrtc] [CRTC:25]
>[  509.785224] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  509.785227] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bf3000
>[  509.785229] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880215be4800 state to ffff880026bf3000
>[  509.785230] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f4cedb40 state to ffff880026bf3000
>[  509.785232] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff880215be4800
>[  509.785234] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f4cedb40 to [CRTC:25]
>[  509.785236] [drm:drm_atomic_set_fb_for_plane] Set [FB:49] for plane state ffff8801f4cedb40
>[  509.785237] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c0132880 state to ffff880026bf3000
>[  509.785238] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3000
>[  509.785239] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c0132880 to [CRTC:25]
>[  509.785241] [drm:drm_atomic_check_only] checking ffff880026bf3000
>[  509.785243] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  509.785244] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  509.785245] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  509.785247] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  509.785247] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  509.785248] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  509.785250] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3000
>[  509.785252] [drm:drm_atomic_connectors_for_crtc] State ffff880026bf3000 has 1 connectors for [CRTC:25]
>[  509.785253] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3000
>[  509.785255] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  509.785256] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  509.785258] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  509.785259] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  509.785261] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff880215be4800 for pipe B
>[  509.785262] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  509.785263] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  509.785264] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  509.785266] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  509.785267] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  509.785268] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  509.785269] [drm:intel_dump_pipe_config] requested mode:
>[  509.785271] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  509.785273] [drm:intel_dump_pipe_config] adjusted mode:
>[  509.785274] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  509.785276] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  509.785276] [drm:intel_dump_pipe_config] port clock: 270000
>[  509.785278] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  509.785279] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  509.785280] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  509.785281] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  509.785282] [drm:intel_dump_pipe_config] ips: 0
>[  509.785282] [drm:intel_dump_pipe_config] double wide: 0
>[  509.785284] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  509.785284] [drm:intel_dump_pipe_config] planes on this crtc
>[  509.785286] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  509.785287] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  509.785288] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  509.785290] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff880215be5c00 state to ffff880026bf3000
>[  509.785291] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff880215be4000 state to ffff880026bf3000
>[  509.785293] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 49
>[  509.785294] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  509.785296] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8801f4ced240 state to ffff880026bf3000
>[  509.785297] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8801f4ced480 state to ffff880026bf3000
>[  509.785299] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8801f4cedd80 state to ffff880026bf3000
>[  509.785302] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f4ced9c0 state to ffff880026bf3000
>[  509.785303] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f4ced180 state to ffff880026bf3000
>[  509.785305] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8801f4ced000 state to ffff880026bf3000
>[  509.785306] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8801f4ced840 state to ffff880026bf3000
>[  509.785307] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8801f4ced540 state to ffff880026bf3000
>[  509.785308] [drm:drm_atomic_commit] commiting ffff880026bf3000
>[  509.785313] [drm:intel_power_well_enable] enabling display
>[  509.785314] [drm:hsw_set_power_well] Enabling power well
>[  509.787382] [drm:intel_power_well_enable] enabling always-on
>[  509.787392] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  509.787393] [drm:intel_enable_shared_dpll] enabling SPLL
>[  509.788282] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  509.788346] [drm:intel_enable_pipe] enabling pipe B
>[  509.788360] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  509.857291] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  509.857296] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  509.857297] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  509.857299] [drm:check_crtc_state] [CRTC:25]
>[  509.857310] [drm:check_shared_dpll_state] WRPLL 1
>[  509.857311] [drm:check_shared_dpll_state] WRPLL 2
>[  509.857312] [drm:check_shared_dpll_state] SPLL
>[  509.857314] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bf3000
>[  509.857318] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bf3000
>[  509.857345] [drm:drm_mode_setcrtc] [CRTC:25]
>[  509.857347] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bf3000
>[  509.857349] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880215be6400 state to ffff880026bf3000
>[  509.857350] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f4cedc00 state to ffff880026bf3000
>[  509.857351] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff880215be6400
>[  509.857352] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f4cedc00 to [NOCRTC]
>[  509.857353] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f4cedc00
>[  509.857354] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3000
>[  509.857355] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c0132d40 state to ffff880026bf3000
>[  509.857356] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c0132d40 to [NOCRTC]
>[  509.857357] [drm:drm_atomic_check_only] checking ffff880026bf3000
>[  509.857358] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  509.857359] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  509.857360] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  509.857361] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  509.857362] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  509.857362] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  509.857363] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3000
>[  509.857365] [drm:drm_atomic_connectors_for_crtc] State ffff880026bf3000 has 0 connectors for [CRTC:25]
>[  509.857368] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  509.857369] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  509.857370] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f4ced600 state to ffff880026bf3000
>[  509.857371] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f4ced3c0 state to ffff880026bf3000
>[  509.857373] [drm:drm_atomic_commit] commiting ffff880026bf3000
>[  509.873960] [drm:intel_disable_pipe] disabling pipe B
>[  509.908144] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  509.908147] [drm:intel_disable_shared_dpll] disabling SPLL
>[  509.908155] [drm:intel_power_well_disable] disabling display
>[  509.908157] [drm:hsw_set_power_well] Requesting to disable the power well
>[  509.908158] [drm:intel_power_well_disable] disabling always-on
>[  509.908159] [drm:intel_power_well_enable] enabling display
>[  509.908160] [drm:hsw_set_power_well] Enabling power well
>[  509.910232] [drm:intel_power_well_disable] disabling display
>[  509.910236] [drm:hsw_set_power_well] Requesting to disable the power well
>[  509.910241] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  509.910243] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  509.910244] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  509.910247] [drm:check_crtc_state] [CRTC:25]
>[  509.910248] [drm:check_shared_dpll_state] WRPLL 1
>[  509.910249] [drm:check_shared_dpll_state] WRPLL 2
>[  509.910250] [drm:check_shared_dpll_state] SPLL
>[  509.910252] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bf3000
>[  509.910254] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bf3000
>[  509.910283] [drm:drm_mode_setcrtc] [CRTC:25]
>[  509.910286] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  509.910288] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bfa800
>[  509.910290] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880025a42800 state to ffff880026bfa800
>[  509.910292] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8800c78d4300 state to ffff880026bfa800
>[  509.910293] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff880025a42800
>[  509.910294] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800c78d4300 to [CRTC:25]
>[  509.910295] [drm:drm_atomic_set_fb_for_plane] Set [FB:51] for plane state ffff8800c78d4300
>[  509.910296] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8801f442d280 state to ffff880026bfa800
>[  509.910298] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfa800
>[  509.910299] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f442d280 to [CRTC:25]
>[  509.910300] [drm:drm_atomic_check_only] checking ffff880026bfa800
>[  509.910301] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  509.910302] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  509.910303] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  509.910304] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  509.910305] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  509.910306] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  509.910307] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfa800
>[  509.910308] [drm:drm_atomic_connectors_for_crtc] State ffff880026bfa800 has 1 connectors for [CRTC:25]
>[  509.910310] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfa800
>[  509.910311] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  509.910312] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  509.910314] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  509.910315] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  509.910316] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff880025a42800 for pipe B
>[  509.910317] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  509.910317] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  509.910319] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  509.910320] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  509.910321] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  509.910322] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  509.910322] [drm:intel_dump_pipe_config] requested mode:
>[  509.910324] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  509.910325] [drm:intel_dump_pipe_config] adjusted mode:
>[  509.910326] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  509.910327] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  509.910328] [drm:intel_dump_pipe_config] port clock: 270000
>[  509.910329] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  509.910329] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  509.910330] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  509.910331] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  509.910332] [drm:intel_dump_pipe_config] ips: 0
>[  509.910333] [drm:intel_dump_pipe_config] double wide: 0
>[  509.910334] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  509.910334] [drm:intel_dump_pipe_config] planes on this crtc
>[  509.910336] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  509.910337] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  509.910338] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  509.910339] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff880025a40c00 state to ffff880026bfa800
>[  509.910341] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff880025a43c00 state to ffff880026bfa800
>[  509.910343] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 51
>[  509.910344] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  509.910345] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8800c78d4240 state to ffff880026bfa800
>[  509.910347] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8800c78d4000 state to ffff880026bfa800
>[  509.910348] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8800c78d4540 state to ffff880026bfa800
>[  509.910350] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8800c78d4900 state to ffff880026bfa800
>[  509.910351] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8800c78d4a80 state to ffff880026bfa800
>[  509.910353] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8800c78d4840 state to ffff880026bfa800
>[  509.910354] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8800c78d4480 state to ffff880026bfa800
>[  509.910356] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8800c78d49c0 state to ffff880026bfa800
>[  509.910357] [drm:drm_atomic_commit] commiting ffff880026bfa800
>[  509.910361] [drm:intel_power_well_enable] enabling display
>[  509.910363] [drm:hsw_set_power_well] Enabling power well
>[  509.912432] [drm:intel_power_well_enable] enabling always-on
>[  509.912442] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  509.912443] [drm:intel_enable_shared_dpll] enabling SPLL
>[  509.913334] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  509.913398] [drm:intel_enable_pipe] enabling pipe B
>[  509.913413] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  509.980251] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  509.980256] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  509.980257] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  509.980259] [drm:check_crtc_state] [CRTC:25]
>[  509.980270] [drm:check_shared_dpll_state] WRPLL 1
>[  509.980271] [drm:check_shared_dpll_state] WRPLL 2
>[  509.980272] [drm:check_shared_dpll_state] SPLL
>[  509.980274] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bfa800
>[  509.980278] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bfa800
>[  509.980307] [drm:drm_mode_setcrtc] [CRTC:25]
>[  509.980310] [drm:drm_atomic_state_init] Allocated atomic state ffff88020103d200
>[  509.980312] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5326400 state to ffff88020103d200
>[  509.980313] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f55afcc0 state to ffff88020103d200
>[  509.980315] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f5326400
>[  509.980315] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55afcc0 to [NOCRTC]
>[  509.980316] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f55afcc0
>[  509.980318] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103d200
>[  509.980319] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c909b640 state to ffff88020103d200
>[  509.980320] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c909b640 to [NOCRTC]
>[  509.980321] [drm:drm_atomic_check_only] checking ffff88020103d200
>[  509.980322] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  509.980323] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  509.980324] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  509.980325] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  509.980325] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  509.980326] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  509.980327] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103d200
>[  509.980329] [drm:drm_atomic_connectors_for_crtc] State ffff88020103d200 has 0 connectors for [CRTC:25]
>[  509.980332] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  509.980333] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  509.980335] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f55afc00 state to ffff88020103d200
>[  509.980336] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f55af6c0 state to ffff88020103d200
>[  509.980338] [drm:drm_atomic_commit] commiting ffff88020103d200
>[  509.996938] [drm:intel_disable_pipe] disabling pipe B
>[  510.031729] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  510.031732] [drm:intel_disable_shared_dpll] disabling SPLL
>[  510.031741] [drm:intel_power_well_disable] disabling display
>[  510.031742] [drm:hsw_set_power_well] Requesting to disable the power well
>[  510.031743] [drm:intel_power_well_disable] disabling always-on
>[  510.031745] [drm:intel_power_well_enable] enabling display
>[  510.031746] [drm:hsw_set_power_well] Enabling power well
>[  510.033147] [drm:intel_power_well_disable] disabling display
>[  510.033152] [drm:hsw_set_power_well] Requesting to disable the power well
>[  510.033158] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  510.033161] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  510.033162] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  510.033165] [drm:check_crtc_state] [CRTC:25]
>[  510.033166] [drm:check_shared_dpll_state] WRPLL 1
>[  510.033168] [drm:check_shared_dpll_state] WRPLL 2
>[  510.033168] [drm:check_shared_dpll_state] SPLL
>[  510.033171] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88020103d200
>[  510.033174] [drm:drm_atomic_state_free] Freeing atomic state ffff88020103d200
>[  510.033198] [drm:drm_mode_setcrtc] [CRTC:25]
>[  510.033202] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  510.033204] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bf2400
>[  510.033207] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880215be4400 state to ffff880026bf2400
>[  510.033209] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f4ceda80 state to ffff880026bf2400
>[  510.033210] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff880215be4400
>[  510.033212] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f4ceda80 to [CRTC:25]
>[  510.033213] [drm:drm_atomic_set_fb_for_plane] Set [FB:49] for plane state ffff8801f4ceda80
>[  510.033215] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c0132420 state to ffff880026bf2400
>[  510.033216] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf2400
>[  510.033217] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c0132420 to [CRTC:25]
>[  510.033218] [drm:drm_atomic_check_only] checking ffff880026bf2400
>[  510.033220] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  510.033221] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  510.033222] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  510.033224] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  510.033225] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  510.033226] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  510.033227] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf2400
>[  510.033229] [drm:drm_atomic_connectors_for_crtc] State ffff880026bf2400 has 1 connectors for [CRTC:25]
>[  510.033230] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf2400
>[  510.033231] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  510.033233] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  510.033235] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  510.033236] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  510.033237] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff880215be4400 for pipe B
>[  510.033239] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  510.033239] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  510.033241] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  510.033242] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  510.033243] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  510.033244] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  510.033245] [drm:intel_dump_pipe_config] requested mode:
>[  510.033247] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  510.033249] [drm:intel_dump_pipe_config] adjusted mode:
>[  510.033250] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  510.033252] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  510.033252] [drm:intel_dump_pipe_config] port clock: 270000
>[  510.033253] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  510.033254] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  510.033256] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  510.033257] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  510.033258] [drm:intel_dump_pipe_config] ips: 0
>[  510.033258] [drm:intel_dump_pipe_config] double wide: 0
>[  510.033259] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  510.033260] [drm:intel_dump_pipe_config] planes on this crtc
>[  510.033261] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  510.033263] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  510.033264] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  510.033266] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff880215be4000 state to ffff880026bf2400
>[  510.033267] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff880215be6400 state to ffff880026bf2400
>[  510.033269] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 49
>[  510.033270] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  510.033272] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8801f4ced900 state to ffff880026bf2400
>[  510.033273] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8801f4ced0c0 state to ffff880026bf2400
>[  510.033275] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8801f4ced540 state to ffff880026bf2400
>[  510.033278] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f4ced840 state to ffff880026bf2400
>[  510.033279] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f4ced000 state to ffff880026bf2400
>[  510.033281] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8801f4ced3c0 state to ffff880026bf2400
>[  510.033282] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8801f4ced600 state to ffff880026bf2400
>[  510.033283] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8801f4cedc00 state to ffff880026bf2400
>[  510.033284] [drm:drm_atomic_commit] commiting ffff880026bf2400
>[  510.033289] [drm:intel_power_well_enable] enabling display
>[  510.033290] [drm:hsw_set_power_well] Enabling power well
>[  510.035357] [drm:intel_power_well_enable] enabling always-on
>[  510.035368] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  510.035369] [drm:intel_enable_shared_dpll] enabling SPLL
>[  510.036265] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  510.036327] [drm:intel_enable_pipe] enabling pipe B
>[  510.036341] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  510.105272] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  510.105277] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  510.105278] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  510.105280] [drm:check_crtc_state] [CRTC:25]
>[  510.105291] [drm:check_shared_dpll_state] WRPLL 1
>[  510.105292] [drm:check_shared_dpll_state] WRPLL 2
>[  510.105293] [drm:check_shared_dpll_state] SPLL
>[  510.105295] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bf2400
>[  510.105298] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bf2400
>[  510.105325] [drm:drm_mode_setcrtc] [CRTC:25]
>[  510.105327] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bf2400
>[  510.105329] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880215be5c00 state to ffff880026bf2400
>[  510.105330] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f4cedd80 state to ffff880026bf2400
>[  510.105332] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff880215be5c00
>[  510.105332] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f4cedd80 to [NOCRTC]
>[  510.105333] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f4cedd80
>[  510.105335] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf2400
>[  510.105336] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c01328e0 state to ffff880026bf2400
>[  510.105337] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c01328e0 to [NOCRTC]
>[  510.105338] [drm:drm_atomic_check_only] checking ffff880026bf2400
>[  510.105339] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  510.105340] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  510.105341] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  510.105342] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  510.105342] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  510.105343] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  510.105344] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf2400
>[  510.105346] [drm:drm_atomic_connectors_for_crtc] State ffff880026bf2400 has 0 connectors for [CRTC:25]
>[  510.105348] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  510.105349] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  510.105351] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f4ced480 state to ffff880026bf2400
>[  510.105352] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f4ced240 state to ffff880026bf2400
>[  510.105354] [drm:drm_atomic_commit] commiting ffff880026bf2400
>[  510.121940] [drm:intel_disable_pipe] disabling pipe B
>[  510.156134] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  510.156137] [drm:intel_disable_shared_dpll] disabling SPLL
>[  510.156145] [drm:intel_power_well_disable] disabling display
>[  510.156146] [drm:hsw_set_power_well] Requesting to disable the power well
>[  510.156147] [drm:intel_power_well_disable] disabling always-on
>[  510.156149] [drm:intel_power_well_enable] enabling display
>[  510.156150] [drm:hsw_set_power_well] Enabling power well
>[  510.158219] [drm:intel_power_well_disable] disabling display
>[  510.158224] [drm:hsw_set_power_well] Requesting to disable the power well
>[  510.158229] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  510.158231] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  510.158232] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  510.158235] [drm:check_crtc_state] [CRTC:25]
>[  510.158237] [drm:check_shared_dpll_state] WRPLL 1
>[  510.158238] [drm:check_shared_dpll_state] WRPLL 2
>[  510.158239] [drm:check_shared_dpll_state] SPLL
>[  510.158240] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bf2400
>[  510.158243] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bf2400
>[  510.158271] [drm:drm_mode_setcrtc] [CRTC:25]
>[  510.158274] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  510.158276] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bfa000
>[  510.158278] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880025a40800 state to ffff880026bfa000
>[  510.158279] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8800c78d4600 state to ffff880026bfa000
>[  510.158281] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff880025a40800
>[  510.158282] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800c78d4600 to [CRTC:25]
>[  510.158283] [drm:drm_atomic_set_fb_for_plane] Set [FB:51] for plane state ffff8800c78d4600
>[  510.158284] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8801f442d3e0 state to ffff880026bfa000
>[  510.158285] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfa000
>[  510.158286] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f442d3e0 to [CRTC:25]
>[  510.158287] [drm:drm_atomic_check_only] checking ffff880026bfa000
>[  510.158289] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  510.158290] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  510.158291] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  510.158292] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  510.158293] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  510.158294] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  510.158294] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfa000
>[  510.158296] [drm:drm_atomic_connectors_for_crtc] State ffff880026bfa000 has 1 connectors for [CRTC:25]
>[  510.158297] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfa000
>[  510.158299] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  510.158299] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  510.158301] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  510.158302] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  510.158303] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff880025a40800 for pipe B
>[  510.158304] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  510.158305] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  510.158306] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  510.158307] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  510.158308] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  510.158309] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  510.158309] [drm:intel_dump_pipe_config] requested mode:
>[  510.158311] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  510.158312] [drm:intel_dump_pipe_config] adjusted mode:
>[  510.158313] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  510.158314] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  510.158315] [drm:intel_dump_pipe_config] port clock: 270000
>[  510.158316] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  510.158317] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  510.158318] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  510.158319] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  510.158319] [drm:intel_dump_pipe_config] ips: 0
>[  510.158320] [drm:intel_dump_pipe_config] double wide: 0
>[  510.158321] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  510.158322] [drm:intel_dump_pipe_config] planes on this crtc
>[  510.158323] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  510.158324] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  510.158325] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  510.158326] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff880025a43400 state to ffff880026bfa000
>[  510.158328] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff880025a42000 state to ffff880026bfa000
>[  510.158330] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 51
>[  510.158331] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  510.158332] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8800c78d40c0 state to ffff880026bfa000
>[  510.158334] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8800c78d4b40 state to ffff880026bfa000
>[  510.158335] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8800c78d4c00 state to ffff880026bfa000
>[  510.158337] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8800c78d4cc0 state to ffff880026bfa000
>[  510.158338] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8800c78d46c0 state to ffff880026bfa000
>[  510.158340] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8800c78d4d80 state to ffff880026bfa000
>[  510.158341] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8800c78d4780 state to ffff880026bfa000
>[  510.158342] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8800c78d49c0 state to ffff880026bfa000
>[  510.158344] [drm:drm_atomic_commit] commiting ffff880026bfa000
>[  510.158348] [drm:intel_power_well_enable] enabling display
>[  510.158349] [drm:hsw_set_power_well] Enabling power well
>[  510.160416] [drm:intel_power_well_enable] enabling always-on
>[  510.160427] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  510.160428] [drm:intel_enable_shared_dpll] enabling SPLL
>[  510.161318] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  510.161390] [drm:intel_enable_pipe] enabling pipe B
>[  510.161404] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  510.228270] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  510.228274] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  510.228276] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  510.228278] [drm:check_crtc_state] [CRTC:25]
>[  510.228289] [drm:check_shared_dpll_state] WRPLL 1
>[  510.228290] [drm:check_shared_dpll_state] WRPLL 2
>[  510.228291] [drm:check_shared_dpll_state] SPLL
>[  510.228293] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bfa000
>[  510.228296] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bfa000
>[  510.228324] [drm:drm_mode_setcrtc] [CRTC:25]
>[  510.228325] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bfa000
>[  510.228327] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880025a43000 state to ffff880026bfa000
>[  510.228329] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8800c78d4480 state to ffff880026bfa000
>[  510.228330] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff880025a43000
>[  510.228331] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800c78d4480 to [NOCRTC]
>[  510.228332] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8800c78d4480
>[  510.228333] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfa000
>[  510.228334] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8801f442d160 state to ffff880026bfa000
>[  510.228335] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f442d160 to [NOCRTC]
>[  510.228336] [drm:drm_atomic_check_only] checking ffff880026bfa000
>[  510.228337] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  510.228338] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  510.228339] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  510.228340] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  510.228341] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  510.228342] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  510.228342] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfa000
>[  510.228344] [drm:drm_atomic_connectors_for_crtc] State ffff880026bfa000 has 0 connectors for [CRTC:25]
>[  510.228346] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  510.228347] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  510.228349] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8800c78d4840 state to ffff880026bfa000
>[  510.228350] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8800c78d4540 state to ffff880026bfa000
>[  510.228352] [drm:drm_atomic_commit] commiting ffff880026bfa000
>[  510.244934] [drm:intel_disable_pipe] disabling pipe B
>[  510.279022] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  510.279025] [drm:intel_disable_shared_dpll] disabling SPLL
>[  510.279033] [drm:intel_power_well_disable] disabling display
>[  510.279035] [drm:hsw_set_power_well] Requesting to disable the power well
>[  510.279036] [drm:intel_power_well_disable] disabling always-on
>[  510.279037] [drm:intel_power_well_enable] enabling display
>[  510.279038] [drm:hsw_set_power_well] Enabling power well
>[  510.281128] [drm:intel_power_well_disable] disabling display
>[  510.281132] [drm:hsw_set_power_well] Requesting to disable the power well
>[  510.281137] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  510.281140] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  510.281141] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  510.281144] [drm:check_crtc_state] [CRTC:25]
>[  510.281146] [drm:check_shared_dpll_state] WRPLL 1
>[  510.281147] [drm:check_shared_dpll_state] WRPLL 2
>[  510.281148] [drm:check_shared_dpll_state] SPLL
>[  510.281150] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bfa000
>[  510.281153] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bfa000
>[  510.281177] [drm:drm_mode_setcrtc] [CRTC:25]
>[  510.281181] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  510.281183] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bfa000
>[  510.281185] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880025a40800 state to ffff880026bfa000
>[  510.281186] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8800c78d46c0 state to ffff880026bfa000
>[  510.281188] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff880025a40800
>[  510.281189] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800c78d46c0 to [CRTC:25]
>[  510.281190] [drm:drm_atomic_set_fb_for_plane] Set [FB:49] for plane state ffff8800c78d46c0
>[  510.281192] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8801f442d3e0 state to ffff880026bfa000
>[  510.281193] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfa000
>[  510.281194] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f442d3e0 to [CRTC:25]
>[  510.281195] [drm:drm_atomic_check_only] checking ffff880026bfa000
>[  510.281197] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  510.281198] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  510.281199] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  510.281202] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  510.281203] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  510.281203] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  510.281205] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfa000
>[  510.281206] [drm:drm_atomic_connectors_for_crtc] State ffff880026bfa000 has 1 connectors for [CRTC:25]
>[  510.281207] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfa000
>[  510.281209] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  510.281211] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  510.281212] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  510.281214] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  510.281216] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff880025a40800 for pipe B
>[  510.281217] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  510.281218] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  510.281219] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  510.281221] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  510.281222] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  510.281223] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  510.281224] [drm:intel_dump_pipe_config] requested mode:
>[  510.281226] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  510.281227] [drm:intel_dump_pipe_config] adjusted mode:
>[  510.281228] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  510.281231] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  510.281232] [drm:intel_dump_pipe_config] port clock: 270000
>[  510.281233] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  510.281234] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  510.281235] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  510.281236] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  510.281238] [drm:intel_dump_pipe_config] ips: 0
>[  510.281239] [drm:intel_dump_pipe_config] double wide: 0
>[  510.281240] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  510.281240] [drm:intel_dump_pipe_config] planes on this crtc
>[  510.281242] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  510.281243] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  510.281244] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  510.281245] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff880025a42c00 state to ffff880026bfa000
>[  510.281247] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff880025a41000 state to ffff880026bfa000
>[  510.281248] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 49
>[  510.281249] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  510.281251] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8800c78d4600 state to ffff880026bfa000
>[  510.281253] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8800c78d4180 state to ffff880026bfa000
>[  510.281254] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8800c78d4000 state to ffff880026bfa000
>[  510.281256] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8800c78d4240 state to ffff880026bfa000
>[  510.281257] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8800c78d4a80 state to ffff880026bfa000
>[  510.281259] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8800c78d4900 state to ffff880026bfa000
>[  510.281261] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8800c78d4300 state to ffff880026bfa000
>[  510.281262] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8800c78d4e40 state to ffff880026bfa000
>[  510.281263] [drm:drm_atomic_commit] commiting ffff880026bfa000
>[  510.281268] [drm:intel_power_well_enable] enabling display
>[  510.281269] [drm:hsw_set_power_well] Enabling power well
>[  510.283337] [drm:intel_power_well_enable] enabling always-on
>[  510.283347] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  510.283348] [drm:intel_enable_shared_dpll] enabling SPLL
>[  510.284237] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  510.284302] [drm:intel_enable_pipe] enabling pipe B
>[  510.284315] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  510.351182] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  510.351186] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  510.351188] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  510.351189] [drm:check_crtc_state] [CRTC:25]
>[  510.351200] [drm:check_shared_dpll_state] WRPLL 1
>[  510.351201] [drm:check_shared_dpll_state] WRPLL 2
>[  510.351202] [drm:check_shared_dpll_state] SPLL
>[  510.351204] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bfa000
>[  510.351207] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bfa000
>[  510.351234] [drm:drm_mode_setcrtc] [CRTC:25]
>[  510.351236] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bfa000
>[  510.351238] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880025a42000 state to ffff880026bfa000
>[  510.351239] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8800c78d49c0 state to ffff880026bfa000
>[  510.351240] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff880025a42000
>[  510.351241] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800c78d49c0 to [NOCRTC]
>[  510.351242] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8800c78d49c0
>[  510.351243] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfa000
>[  510.351244] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8801f442d160 state to ffff880026bfa000
>[  510.351245] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f442d160 to [NOCRTC]
>[  510.351246] [drm:drm_atomic_check_only] checking ffff880026bfa000
>[  510.351248] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  510.351248] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  510.351249] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  510.351250] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  510.351251] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  510.351252] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  510.351253] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfa000
>[  510.351254] [drm:drm_atomic_connectors_for_crtc] State ffff880026bfa000 has 0 connectors for [CRTC:25]
>[  510.351257] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  510.351258] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  510.351259] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8800c78d4780 state to ffff880026bfa000
>[  510.351261] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8800c78d4d80 state to ffff880026bfa000
>[  510.351262] [drm:drm_atomic_commit] commiting ffff880026bfa000
>[  510.367849] [drm:intel_disable_pipe] disabling pipe B
>[  510.402181] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  510.402184] [drm:intel_disable_shared_dpll] disabling SPLL
>[  510.402192] [drm:intel_power_well_disable] disabling display
>[  510.402194] [drm:hsw_set_power_well] Requesting to disable the power well
>[  510.402195] [drm:intel_power_well_disable] disabling always-on
>[  510.402196] [drm:intel_power_well_enable] enabling display
>[  510.402197] [drm:hsw_set_power_well] Enabling power well
>[  510.404266] [drm:intel_power_well_disable] disabling display
>[  510.404270] [drm:hsw_set_power_well] Requesting to disable the power well
>[  510.404275] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  510.404277] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  510.404279] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  510.404281] [drm:check_crtc_state] [CRTC:25]
>[  510.404283] [drm:check_shared_dpll_state] WRPLL 1
>[  510.404284] [drm:check_shared_dpll_state] WRPLL 2
>[  510.404285] [drm:check_shared_dpll_state] SPLL
>[  510.404287] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bfa000
>[  510.404289] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bfa000
>[  510.404317] [drm:drm_mode_setcrtc] [CRTC:25]
>[  510.404320] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  510.404322] [drm:drm_atomic_state_init] Allocated atomic state ffff88020103c000
>[  510.404325] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5326400 state to ffff88020103c000
>[  510.404326] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f55afb40 state to ffff88020103c000
>[  510.404327] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f5326400
>[  510.404328] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55afb40 to [CRTC:25]
>[  510.404329] [drm:drm_atomic_set_fb_for_plane] Set [FB:51] for plane state ffff8801f55afb40
>[  510.404331] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c909b700 state to ffff88020103c000
>[  510.404332] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103c000
>[  510.404333] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c909b700 to [CRTC:25]
>[  510.404334] [drm:drm_atomic_check_only] checking ffff88020103c000
>[  510.404335] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  510.404336] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  510.404337] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  510.404338] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  510.404339] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  510.404340] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  510.404341] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103c000
>[  510.404342] [drm:drm_atomic_connectors_for_crtc] State ffff88020103c000 has 1 connectors for [CRTC:25]
>[  510.404343] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103c000
>[  510.404345] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  510.404346] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  510.404347] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  510.404348] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  510.404349] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff8801f5326400 for pipe B
>[  510.404350] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  510.404351] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  510.404352] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  510.404353] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  510.404354] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  510.404355] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  510.404356] [drm:intel_dump_pipe_config] requested mode:
>[  510.404357] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  510.404358] [drm:intel_dump_pipe_config] adjusted mode:
>[  510.404359] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  510.404361] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  510.404361] [drm:intel_dump_pipe_config] port clock: 270000
>[  510.404362] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  510.404363] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  510.404364] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  510.404365] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  510.404366] [drm:intel_dump_pipe_config] ips: 0
>[  510.404367] [drm:intel_dump_pipe_config] double wide: 0
>[  510.404368] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  510.404368] [drm:intel_dump_pipe_config] planes on this crtc
>[  510.404369] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  510.404371] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  510.404371] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  510.404373] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff8801f5326000 state to ffff88020103c000
>[  510.404375] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff8801f5324000 state to ffff88020103c000
>[  510.404376] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 51
>[  510.404377] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  510.404379] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8801f55af780 state to ffff88020103c000
>[  510.404380] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8801f55af840 state to ffff88020103c000
>[  510.404381] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8801f55af180 state to ffff88020103c000
>[  510.404384] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f55af0c0 state to ffff88020103c000
>[  510.404385] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f55af3c0 state to ffff88020103c000
>[  510.404387] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8801f55af240 state to ffff88020103c000
>[  510.404388] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8801f55af900 state to ffff88020103c000
>[  510.404389] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8801f55af540 state to ffff88020103c000
>[  510.404390] [drm:drm_atomic_commit] commiting ffff88020103c000
>[  510.404395] [drm:intel_power_well_enable] enabling display
>[  510.404396] [drm:hsw_set_power_well] Enabling power well
>[  510.406464] [drm:intel_power_well_enable] enabling always-on
>[  510.406474] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  510.406475] [drm:intel_enable_shared_dpll] enabling SPLL
>[  510.407365] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  510.407429] [drm:intel_enable_pipe] enabling pipe B
>[  510.407442] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  510.474278] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  510.474283] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  510.474284] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  510.474286] [drm:check_crtc_state] [CRTC:25]
>[  510.474297] [drm:check_shared_dpll_state] WRPLL 1
>[  510.474298] [drm:check_shared_dpll_state] WRPLL 2
>[  510.474299] [drm:check_shared_dpll_state] SPLL
>[  510.474301] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88020103c000
>[  510.474305] [drm:drm_atomic_state_free] Freeing atomic state ffff88020103c000
>[  510.474331] [drm:drm_mode_setcrtc] [CRTC:25]
>[  510.474333] [drm:drm_atomic_state_init] Allocated atomic state ffff88020103c000
>[  510.474335] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5325000 state to ffff88020103c000
>[  510.474337] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f55afe40 state to ffff88020103c000
>[  510.474338] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f5325000
>[  510.474338] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55afe40 to [NOCRTC]
>[  510.474340] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f55afe40
>[  510.474341] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103c000
>[  510.474342] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c909b6a0 state to ffff88020103c000
>[  510.474343] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c909b6a0 to [NOCRTC]
>[  510.474344] [drm:drm_atomic_check_only] checking ffff88020103c000
>[  510.474345] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  510.474346] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  510.474347] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  510.474348] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  510.474348] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  510.474349] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  510.474350] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103c000
>[  510.474352] [drm:drm_atomic_connectors_for_crtc] State ffff88020103c000 has 0 connectors for [CRTC:25]
>[  510.474354] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  510.474355] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  510.474357] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f55afa80 state to ffff88020103c000
>[  510.474358] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f55af480 state to ffff88020103c000
>[  510.474360] [drm:drm_atomic_commit] commiting ffff88020103c000
>[  510.490971] [drm:intel_disable_pipe] disabling pipe B
>[  510.525865] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  510.525868] [drm:intel_disable_shared_dpll] disabling SPLL
>[  510.525877] [drm:intel_power_well_disable] disabling display
>[  510.525879] [drm:hsw_set_power_well] Requesting to disable the power well
>[  510.525880] [drm:intel_power_well_disable] disabling always-on
>[  510.525881] [drm:intel_power_well_enable] enabling display
>[  510.525882] [drm:hsw_set_power_well] Enabling power well
>[  510.527951] [drm:intel_power_well_disable] disabling display
>[  510.527955] [drm:hsw_set_power_well] Requesting to disable the power well
>[  510.527960] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  510.527962] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  510.527963] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  510.527966] [drm:check_crtc_state] [CRTC:25]
>[  510.527967] [drm:check_shared_dpll_state] WRPLL 1
>[  510.527968] [drm:check_shared_dpll_state] WRPLL 2
>[  510.527969] [drm:check_shared_dpll_state] SPLL
>[  510.527971] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88020103c000
>[  510.527974] [drm:drm_atomic_state_free] Freeing atomic state ffff88020103c000
>[  510.528001] [drm:drm_mode_setcrtc] [CRTC:25]
>[  510.528005] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  510.528007] [drm:drm_atomic_state_init] Allocated atomic state ffff880210d7b800
>[  510.528009] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5490800 state to ffff880210d7b800
>[  510.528011] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f5fde900 state to ffff880210d7b800
>[  510.528012] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f5490800
>[  510.528013] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f5fde900 to [CRTC:25]
>[  510.528014] [drm:drm_atomic_set_fb_for_plane] Set [FB:49] for plane state ffff8801f5fde900
>[  510.528015] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800d3bbad80 state to ffff880210d7b800
>[  510.528016] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b800
>[  510.528017] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800d3bbad80 to [CRTC:25]
>[  510.528018] [drm:drm_atomic_check_only] checking ffff880210d7b800
>[  510.528020] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  510.528020] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  510.528021] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  510.528023] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  510.528024] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  510.528024] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  510.528025] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b800
>[  510.528027] [drm:drm_atomic_connectors_for_crtc] State ffff880210d7b800 has 1 connectors for [CRTC:25]
>[  510.528028] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b800
>[  510.528029] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  510.528030] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  510.528032] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  510.528033] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  510.528034] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff8801f5490800 for pipe B
>[  510.528035] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  510.528036] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  510.528037] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  510.528039] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  510.528040] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  510.528040] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  510.528041] [drm:intel_dump_pipe_config] requested mode:
>[  510.528043] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  510.528043] [drm:intel_dump_pipe_config] adjusted mode:
>[  510.528045] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  510.528046] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  510.528047] [drm:intel_dump_pipe_config] port clock: 270000
>[  510.528047] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  510.528048] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  510.528049] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  510.528050] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  510.528051] [drm:intel_dump_pipe_config] ips: 0
>[  510.528052] [drm:intel_dump_pipe_config] double wide: 0
>[  510.528053] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  510.528053] [drm:intel_dump_pipe_config] planes on this crtc
>[  510.528054] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  510.528055] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  510.528056] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  510.528058] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff8801f5493800 state to ffff880210d7b800
>[  510.528059] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff8801f5493400 state to ffff880210d7b800
>[  510.528061] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 49
>[  510.528062] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  510.528064] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8801f5fde0c0 state to ffff880210d7b800
>[  510.528065] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8801f5fde000 state to ffff880210d7b800
>[  510.528066] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8801f5fdecc0 state to ffff880210d7b800
>[  510.528069] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f5fde3c0 state to ffff880210d7b800
>[  510.528070] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f5fde540 state to ffff880210d7b800
>[  510.528072] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8801f5fde180 state to ffff880210d7b800
>[  510.528073] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8801f5fdeb40 state to ffff880210d7b800
>[  510.528074] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8801f5fde780 state to ffff880210d7b800
>[  510.528075] [drm:drm_atomic_commit] commiting ffff880210d7b800
>[  510.528080] [drm:intel_power_well_enable] enabling display
>[  510.528081] [drm:hsw_set_power_well] Enabling power well
>[  510.530122] [drm:intel_power_well_enable] enabling always-on
>[  510.530132] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  510.530133] [drm:intel_enable_shared_dpll] enabling SPLL
>[  510.531022] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  510.531086] [drm:intel_enable_pipe] enabling pipe B
>[  510.531099] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  510.597937] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  510.597942] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  510.597943] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  510.597945] [drm:check_crtc_state] [CRTC:25]
>[  510.597956] [drm:check_shared_dpll_state] WRPLL 1
>[  510.597957] [drm:check_shared_dpll_state] WRPLL 2
>[  510.597958] [drm:check_shared_dpll_state] SPLL
>[  510.597960] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880210d7b800
>[  510.597963] [drm:drm_atomic_state_free] Freeing atomic state ffff880210d7b800
>[  510.597990] [drm:drm_mode_setcrtc] [CRTC:25]
>[  510.597992] [drm:drm_atomic_state_init] Allocated atomic state ffff88020103c200
>[  510.597994] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5324000 state to ffff88020103c200
>[  510.597996] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f55af540 state to ffff88020103c200
>[  510.597997] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f5324000
>[  510.597998] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55af540 to [NOCRTC]
>[  510.597999] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f55af540
>[  510.598000] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103c200
>[  510.598001] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c909b620 state to ffff88020103c200
>[  510.598002] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c909b620 to [NOCRTC]
>[  510.598003] [drm:drm_atomic_check_only] checking ffff88020103c200
>[  510.598004] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  510.598005] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  510.598006] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  510.598007] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  510.598008] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  510.598009] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  510.598010] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103c200
>[  510.598011] [drm:drm_atomic_connectors_for_crtc] State ffff88020103c200 has 0 connectors for [CRTC:25]
>[  510.598014] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  510.598015] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  510.598016] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f55af900 state to ffff88020103c200
>[  510.598018] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f55af240 state to ffff88020103c200
>[  510.598020] [drm:drm_atomic_commit] commiting ffff88020103c200
>[  510.614625] [drm:intel_disable_pipe] disabling pipe B
>[  510.649741] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  510.649744] [drm:intel_disable_shared_dpll] disabling SPLL
>[  510.649752] [drm:intel_power_well_disable] disabling display
>[  510.649754] [drm:hsw_set_power_well] Requesting to disable the power well
>[  510.649754] [drm:intel_power_well_disable] disabling always-on
>[  510.649756] [drm:intel_power_well_enable] enabling display
>[  510.649757] [drm:hsw_set_power_well] Enabling power well
>[  510.651826] [drm:intel_power_well_disable] disabling display
>[  510.651830] [drm:hsw_set_power_well] Requesting to disable the power well
>[  510.651835] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  510.651837] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  510.651838] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  510.651841] [drm:check_crtc_state] [CRTC:25]
>[  510.651842] [drm:check_shared_dpll_state] WRPLL 1
>[  510.651843] [drm:check_shared_dpll_state] WRPLL 2
>[  510.651844] [drm:check_shared_dpll_state] SPLL
>[  510.651846] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88020103c200
>[  510.651849] [drm:drm_atomic_state_free] Freeing atomic state ffff88020103c200
>[  510.651876] [drm:drm_mode_setcrtc] [CRTC:25]
>[  510.651879] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  510.651881] [drm:drm_atomic_state_init] Allocated atomic state ffff88020103c200
>[  510.651883] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5325000 state to ffff88020103c200
>[  510.651884] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f55af480 state to ffff88020103c200
>[  510.651885] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f5325000
>[  510.651886] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55af480 to [CRTC:25]
>[  510.651888] [drm:drm_atomic_set_fb_for_plane] Set [FB:51] for plane state ffff8801f55af480
>[  510.651889] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c909b600 state to ffff88020103c200
>[  510.651890] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103c200
>[  510.651891] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c909b600 to [CRTC:25]
>[  510.651891] [drm:drm_atomic_check_only] checking ffff88020103c200
>[  510.651893] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  510.651894] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  510.651895] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  510.651897] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  510.651897] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  510.651898] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  510.651899] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103c200
>[  510.651900] [drm:drm_atomic_connectors_for_crtc] State ffff88020103c200 has 1 connectors for [CRTC:25]
>[  510.651902] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103c200
>[  510.651903] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  510.651904] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  510.651906] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  510.651907] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  510.651908] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff8801f5325000 for pipe B
>[  510.651909] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  510.651910] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  510.651911] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  510.651912] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  510.651913] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  510.651914] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  510.651915] [drm:intel_dump_pipe_config] requested mode:
>[  510.651916] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  510.651917] [drm:intel_dump_pipe_config] adjusted mode:
>[  510.651918] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  510.651920] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  510.651920] [drm:intel_dump_pipe_config] port clock: 270000
>[  510.651921] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  510.651922] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  510.651923] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  510.651924] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  510.651925] [drm:intel_dump_pipe_config] ips: 0
>[  510.651925] [drm:intel_dump_pipe_config] double wide: 0
>[  510.651927] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  510.651927] [drm:intel_dump_pipe_config] planes on this crtc
>[  510.651929] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  510.651929] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  510.651930] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  510.651932] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff8801f5326000 state to ffff88020103c200
>[  510.651933] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff8801f5327800 state to ffff88020103c200
>[  510.651935] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 51
>[  510.651936] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  510.651938] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8801f55afe40 state to ffff88020103c200
>[  510.651939] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8801f55af180 state to ffff88020103c200
>[  510.651940] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8801f55af840 state to ffff88020103c200
>[  510.651943] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f55af780 state to ffff88020103c200
>[  510.651944] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f55af9c0 state to ffff88020103c200
>[  510.651945] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8801f55af000 state to ffff88020103c200
>[  510.651947] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8801f55aff00 state to ffff88020103c200
>[  510.651948] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8801f55af600 state to ffff88020103c200
>[  510.651949] [drm:drm_atomic_commit] commiting ffff88020103c200
>[  510.651954] [drm:intel_power_well_enable] enabling display
>[  510.651955] [drm:hsw_set_power_well] Enabling power well
>[  510.653093] [drm:intel_power_well_enable] enabling always-on
>[  510.653104] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  510.653106] [drm:intel_enable_shared_dpll] enabling SPLL
>[  510.653996] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  510.654059] [drm:intel_enable_pipe] enabling pipe B
>[  510.654073] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  510.720940] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  510.720944] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  510.720945] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  510.720947] [drm:check_crtc_state] [CRTC:25]
>[  510.720958] [drm:check_shared_dpll_state] WRPLL 1
>[  510.720959] [drm:check_shared_dpll_state] WRPLL 2
>[  510.720960] [drm:check_shared_dpll_state] SPLL
>[  510.720962] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88020103c200
>[  510.720966] [drm:drm_atomic_state_free] Freeing atomic state ffff88020103c200
>[  510.720986] [drm:drm_mode_setcrtc] [CRTC:25]
>[  510.720988] [drm:drm_atomic_state_init] Allocated atomic state ffff880210d7b000
>[  510.720990] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5493400 state to ffff880210d7b000
>[  510.720992] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f5fde780 state to ffff880210d7b000
>[  510.720993] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f5493400
>[  510.720993] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f5fde780 to [NOCRTC]
>[  510.720995] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f5fde780
>[  510.720996] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b000
>[  510.721018] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800d3bba4a0 state to ffff880210d7b000
>[  510.721019] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800d3bba4a0 to [NOCRTC]
>[  510.721020] [drm:drm_atomic_check_only] checking ffff880210d7b000
>[  510.721022] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  510.721022] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  510.721023] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  510.721024] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  510.721025] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  510.721026] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  510.721027] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b000
>[  510.721028] [drm:drm_atomic_connectors_for_crtc] State ffff880210d7b000 has 0 connectors for [CRTC:25]
>[  510.721031] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  510.721033] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  510.721035] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f5fdeb40 state to ffff880210d7b000
>[  510.721037] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f5fde180 state to ffff880210d7b000
>[  510.721039] [drm:drm_atomic_commit] commiting ffff880210d7b000
>[  510.737608] [drm:intel_disable_pipe] disabling pipe B
>[  510.772055] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  510.772058] [drm:intel_disable_shared_dpll] disabling SPLL
>[  510.772066] [drm:intel_power_well_disable] disabling display
>[  510.772068] [drm:hsw_set_power_well] Requesting to disable the power well
>[  510.772069] [drm:intel_power_well_disable] disabling always-on
>[  510.772070] [drm:intel_power_well_enable] enabling display
>[  510.772071] [drm:hsw_set_power_well] Enabling power well
>[  510.774140] [drm:intel_power_well_disable] disabling display
>[  510.774144] [drm:hsw_set_power_well] Requesting to disable the power well
>[  510.774149] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  510.774151] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  510.774153] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  510.774156] [drm:check_crtc_state] [CRTC:25]
>[  510.774157] [drm:check_shared_dpll_state] WRPLL 1
>[  510.774158] [drm:check_shared_dpll_state] WRPLL 2
>[  510.774159] [drm:check_shared_dpll_state] SPLL
>[  510.774161] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880210d7b000
>[  510.774163] [drm:drm_atomic_state_free] Freeing atomic state ffff880210d7b000
>[  510.774191] [drm:drm_mode_setcrtc] [CRTC:25]
>[  510.774194] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  510.774197] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bf2600
>[  510.774199] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880215be4800 state to ffff880026bf2600
>[  510.774200] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f4ced180 state to ffff880026bf2600
>[  510.774202] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff880215be4800
>[  510.774203] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f4ced180 to [CRTC:25]
>[  510.774204] [drm:drm_atomic_set_fb_for_plane] Set [FB:49] for plane state ffff8801f4ced180
>[  510.774205] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c01324a0 state to ffff880026bf2600
>[  510.774206] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf2600
>[  510.774207] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c01324a0 to [CRTC:25]
>[  510.774208] [drm:drm_atomic_check_only] checking ffff880026bf2600
>[  510.774209] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  510.774210] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  510.774211] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  510.774212] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  510.774213] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  510.774214] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  510.774215] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf2600
>[  510.774216] [drm:drm_atomic_connectors_for_crtc] State ffff880026bf2600 has 1 connectors for [CRTC:25]
>[  510.774218] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf2600
>[  510.774219] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  510.774220] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  510.774222] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  510.774222] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  510.774224] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff880215be4800 for pipe B
>[  510.774225] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  510.774225] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  510.774227] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  510.774228] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  510.774229] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  510.774230] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  510.774230] [drm:intel_dump_pipe_config] requested mode:
>[  510.774232] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  510.774233] [drm:intel_dump_pipe_config] adjusted mode:
>[  510.774234] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  510.774235] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  510.774236] [drm:intel_dump_pipe_config] port clock: 270000
>[  510.774237] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  510.774238] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  510.774239] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  510.774240] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  510.774241] [drm:intel_dump_pipe_config] ips: 0
>[  510.774241] [drm:intel_dump_pipe_config] double wide: 0
>[  510.774242] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  510.774243] [drm:intel_dump_pipe_config] planes on this crtc
>[  510.774244] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  510.774246] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  510.774247] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  510.774248] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff880215be5000 state to ffff880026bf2600
>[  510.774250] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff880215be6400 state to ffff880026bf2600
>[  510.774252] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 49
>[  510.774252] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  510.774254] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8801f4cedb40 state to ffff880026bf2600
>[  510.774255] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8801f4ced6c0 state to ffff880026bf2600
>[  510.774257] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8801f4cedc00 state to ffff880026bf2600
>[  510.774259] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f4ced600 state to ffff880026bf2600
>[  510.774261] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f4ced3c0 state to ffff880026bf2600
>[  510.774262] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8801f4ced240 state to ffff880026bf2600
>[  510.774263] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8801f4ced480 state to ffff880026bf2600
>[  510.774264] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8801f4cedd80 state to ffff880026bf2600
>[  510.774266] [drm:drm_atomic_commit] commiting ffff880026bf2600
>[  510.774270] [drm:intel_power_well_enable] enabling display
>[  510.774271] [drm:hsw_set_power_well] Enabling power well
>[  510.776340] [drm:intel_power_well_enable] enabling always-on
>[  510.776350] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  510.776351] [drm:intel_enable_shared_dpll] enabling SPLL
>[  510.777241] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  510.777306] [drm:intel_enable_pipe] enabling pipe B
>[  510.777319] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  510.846247] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  510.846251] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  510.846253] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  510.846254] [drm:check_crtc_state] [CRTC:25]
>[  510.846266] [drm:check_shared_dpll_state] WRPLL 1
>[  510.846267] [drm:check_shared_dpll_state] WRPLL 2
>[  510.846268] [drm:check_shared_dpll_state] SPLL
>[  510.846269] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bf2600
>[  510.846273] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bf2600
>[  510.846300] [drm:drm_mode_setcrtc] [CRTC:25]
>[  510.846301] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bf2600
>[  510.846303] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880215be5c00 state to ffff880026bf2600
>[  510.846305] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f4ced540 state to ffff880026bf2600
>[  510.846306] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff880215be5c00
>[  510.846307] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f4ced540 to [NOCRTC]
>[  510.846308] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f4ced540
>[  510.846309] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf2600
>[  510.846310] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c0132680 state to ffff880026bf2600
>[  510.846311] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c0132680 to [NOCRTC]
>[  510.846312] [drm:drm_atomic_check_only] checking ffff880026bf2600
>[  510.846314] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  510.846314] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  510.846315] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  510.846316] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  510.846317] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  510.846318] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  510.846319] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf2600
>[  510.846320] [drm:drm_atomic_connectors_for_crtc] State ffff880026bf2600 has 0 connectors for [CRTC:25]
>[  510.846323] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  510.846324] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  510.846326] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f4ced0c0 state to ffff880026bf2600
>[  510.846327] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f4ced900 state to ffff880026bf2600
>[  510.846329] [drm:drm_atomic_commit] commiting ffff880026bf2600
>[  510.857133] [drm:intel_print_rc6_info] Enabling RC6 states: RC6 on
>[  510.859171] [drm:gen6_enable_rps] Overclocking supported. Max: 1100MHz, Overclock max: 1100MHz
>[  510.862937] [drm:intel_disable_pipe] disabling pipe B
>[  510.897948] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  510.897951] [drm:intel_disable_shared_dpll] disabling SPLL
>[  510.897959] [drm:intel_power_well_disable] disabling display
>[  510.897961] [drm:hsw_set_power_well] Requesting to disable the power well
>[  510.897961] [drm:intel_power_well_disable] disabling always-on
>[  510.897963] [drm:intel_power_well_enable] enabling display
>[  510.897964] [drm:hsw_set_power_well] Enabling power well
>[  510.900033] [drm:intel_power_well_disable] disabling display
>[  510.900037] [drm:hsw_set_power_well] Requesting to disable the power well
>[  510.900045] [drm:intel_runtime_suspend] Suspending device
>[  510.900146] [drm:hsw_enable_pc8] Enabling package C8+
>[  510.900156] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  510.900158] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  510.900160] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  510.900162] [drm:check_crtc_state] [CRTC:25]
>[  510.900164] [drm:check_shared_dpll_state] WRPLL 1
>[  510.900165] [drm:check_shared_dpll_state] WRPLL 2
>[  510.900166] [drm:check_shared_dpll_state] SPLL
>[  510.900168] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bf2600
>[  510.900170] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bf2600
>[  510.900197] [drm:drm_mode_setcrtc] [CRTC:25]
>[  510.900201] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  510.900203] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bfae00
>[  510.900205] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880025a43000 state to ffff880026bfae00
>[  510.900206] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8800c78d4540 state to ffff880026bfae00
>[  510.900208] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff880025a43000
>[  510.900208] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800c78d4540 to [CRTC:25]
>[  510.900210] [drm:drm_atomic_set_fb_for_plane] Set [FB:51] for plane state ffff8800c78d4540
>[  510.900211] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8801f442dfa0 state to ffff880026bfae00
>[  510.900212] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfae00
>[  510.900213] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f442dfa0 to [CRTC:25]
>[  510.900214] [drm:drm_atomic_check_only] checking ffff880026bfae00
>[  510.900215] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  510.900216] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  510.900217] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  510.900218] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  510.900219] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  510.900220] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  510.900221] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfae00
>[  510.900222] [drm:drm_atomic_connectors_for_crtc] State ffff880026bfae00 has 1 connectors for [CRTC:25]
>[  510.900223] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfae00
>[  510.900225] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  510.900226] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  510.900227] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  510.900228] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  510.900229] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff880025a43000 for pipe B
>[  510.900230] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  510.900231] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  510.900232] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  510.900233] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  510.900234] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  510.900235] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  510.900236] [drm:intel_dump_pipe_config] requested mode:
>[  510.900237] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  510.900238] [drm:intel_dump_pipe_config] adjusted mode:
>[  510.900239] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  510.900241] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  510.900241] [drm:intel_dump_pipe_config] port clock: 270000
>[  510.900242] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  510.900243] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  510.900244] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  510.900245] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  510.900245] [drm:intel_dump_pipe_config] ips: 0
>[  510.900246] [drm:intel_dump_pipe_config] double wide: 0
>[  510.900247] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  510.900248] [drm:intel_dump_pipe_config] planes on this crtc
>[  510.900249] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  510.900250] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  510.900251] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  510.900253] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff880025a43400 state to ffff880026bfae00
>[  510.900254] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff880025a41800 state to ffff880026bfae00
>[  510.900256] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 51
>[  510.900257] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  510.900258] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8800c78d4480 state to ffff880026bfae00
>[  510.900259] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8800c78d4c00 state to ffff880026bfae00
>[  510.900261] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8800c78d4b40 state to ffff880026bfae00
>[  510.900263] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8800c78d40c0 state to ffff880026bfae00
>[  510.900264] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8800c78d4e40 state to ffff880026bfae00
>[  510.900266] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8800c78d4300 state to ffff880026bfae00
>[  510.900268] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8800c78d4900 state to ffff880026bfae00
>[  510.900269] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8800c78d4d80 state to ffff880026bfae00
>[  510.900270] [drm:drm_atomic_commit] commiting ffff880026bfae00
>[  510.912580] [drm:intel_runtime_suspend] Device suspended
>[  510.917074] [drm:intel_runtime_resume] Resuming device
>[  510.919142] [drm:hsw_disable_pc8] Disabling package C8+
>[  510.923080] [drm:intel_update_cdclk] Current CD clock rate: 540000 kHz
>[  511.036144] [drm:intel_runtime_resume] Device resumed
>[  511.036154] [drm:intel_power_well_enable] enabling display
>[  511.036156] [drm:hsw_set_power_well] Enabling power well
>[  511.038225] [drm:intel_power_well_enable] enabling always-on
>[  511.038235] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  511.038236] [drm:intel_enable_shared_dpll] enabling SPLL
>[  511.039125] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  511.039189] [drm:intel_enable_pipe] enabling pipe B
>[  511.039202] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  511.107906] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  511.107910] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  511.107911] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  511.107913] [drm:check_crtc_state] [CRTC:25]
>[  511.107924] [drm:check_shared_dpll_state] WRPLL 1
>[  511.107925] [drm:check_shared_dpll_state] WRPLL 2
>[  511.107926] [drm:check_shared_dpll_state] SPLL
>[  511.107928] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bfae00
>[  511.107931] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bfae00
>[  511.107958] [drm:drm_mode_setcrtc] [CRTC:25]
>[  511.107960] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bfae00
>[  511.107962] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880025a41c00 state to ffff880026bfae00
>[  511.107964] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8800c78d4780 state to ffff880026bfae00
>[  511.107965] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff880025a41c00
>[  511.107966] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800c78d4780 to [NOCRTC]
>[  511.107967] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8800c78d4780
>[  511.107968] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfae00
>[  511.107969] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8801f442dd80 state to ffff880026bfae00
>[  511.107970] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f442dd80 to [NOCRTC]
>[  511.107971] [drm:drm_atomic_check_only] checking ffff880026bfae00
>[  511.107972] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  511.107973] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  511.107974] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  511.107975] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  511.107975] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  511.107976] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  511.107977] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfae00
>[  511.107979] [drm:drm_atomic_connectors_for_crtc] State ffff880026bfae00 has 0 connectors for [CRTC:25]
>[  511.107981] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  511.107982] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  511.107984] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8800c78d49c0 state to ffff880026bfae00
>[  511.107985] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8800c78d4000 state to ffff880026bfae00
>[  511.107987] [drm:drm_atomic_commit] commiting ffff880026bfae00
>[  511.124572] [drm:intel_disable_pipe] disabling pipe B
>[  511.159702] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  511.159705] [drm:intel_disable_shared_dpll] disabling SPLL
>[  511.159713] [drm:intel_power_well_disable] disabling display
>[  511.159715] [drm:hsw_set_power_well] Requesting to disable the power well
>[  511.159716] [drm:intel_power_well_disable] disabling always-on
>[  511.159717] [drm:intel_power_well_enable] enabling display
>[  511.159719] [drm:hsw_set_power_well] Enabling power well
>[  511.161048] [drm:intel_power_well_disable] disabling display
>[  511.161052] [drm:hsw_set_power_well] Requesting to disable the power well
>[  511.161058] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  511.161060] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  511.161062] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  511.161066] [drm:check_crtc_state] [CRTC:25]
>[  511.161067] [drm:check_shared_dpll_state] WRPLL 1
>[  511.161069] [drm:check_shared_dpll_state] WRPLL 2
>[  511.161070] [drm:check_shared_dpll_state] SPLL
>[  511.161072] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bfae00
>[  511.161075] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bfae00
>[  511.161100] [drm:drm_mode_setcrtc] [CRTC:25]
>[  511.161103] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  511.161106] [drm:drm_atomic_state_init] Allocated atomic state ffff880210d7b000
>[  511.161109] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5493800 state to ffff880210d7b000
>[  511.161110] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f5fdecc0 state to ffff880210d7b000
>[  511.161112] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f5493800
>[  511.161113] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f5fdecc0 to [CRTC:25]
>[  511.161114] [drm:drm_atomic_set_fb_for_plane] Set [FB:49] for plane state ffff8801f5fdecc0
>[  511.161115] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800d3bba200 state to ffff880210d7b000
>[  511.161117] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b000
>[  511.161118] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800d3bba200 to [CRTC:25]
>[  511.161119] [drm:drm_atomic_check_only] checking ffff880210d7b000
>[  511.161121] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  511.161122] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  511.161124] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  511.161126] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  511.161126] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  511.161127] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  511.161128] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b000
>[  511.161130] [drm:drm_atomic_connectors_for_crtc] State ffff880210d7b000 has 1 connectors for [CRTC:25]
>[  511.161131] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b000
>[  511.161134] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  511.161135] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  511.161137] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  511.161138] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  511.161140] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff8801f5493800 for pipe B
>[  511.161141] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  511.161142] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  511.161143] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  511.161145] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  511.161146] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  511.161148] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  511.161148] [drm:intel_dump_pipe_config] requested mode:
>[  511.161151] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  511.161151] [drm:intel_dump_pipe_config] adjusted mode:
>[  511.161153] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  511.161155] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  511.161156] [drm:intel_dump_pipe_config] port clock: 270000
>[  511.161157] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  511.161158] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  511.161159] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  511.161160] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  511.161161] [drm:intel_dump_pipe_config] ips: 0
>[  511.161161] [drm:intel_dump_pipe_config] double wide: 0
>[  511.161162] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  511.161163] [drm:intel_dump_pipe_config] planes on this crtc
>[  511.161165] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  511.161166] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  511.161167] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  511.161169] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff8801f5492c00 state to ffff880210d7b000
>[  511.161170] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff8801f5490c00 state to ffff880210d7b000
>[  511.161172] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 49
>[  511.161173] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  511.161174] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8801f5fde0c0 state to ffff880210d7b000
>[  511.161176] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8801f5fdec00 state to ffff880210d7b000
>[  511.161177] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8801f5fde480 state to ffff880210d7b000
>[  511.161180] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f5fde840 state to ffff880210d7b000
>[  511.161181] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f5fde600 state to ffff880210d7b000
>[  511.161182] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8801f5fdea80 state to ffff880210d7b000
>[  511.161184] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8801f5fded80 state to ffff880210d7b000
>[  511.161185] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8801f5fdee40 state to ffff880210d7b000
>[  511.161186] [drm:drm_atomic_commit] commiting ffff880210d7b000
>[  511.161191] [drm:intel_power_well_enable] enabling display
>[  511.161193] [drm:hsw_set_power_well] Enabling power well
>[  511.163260] [drm:intel_power_well_enable] enabling always-on
>[  511.163270] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  511.163271] [drm:intel_enable_shared_dpll] enabling SPLL
>[  511.164164] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  511.164226] [drm:intel_enable_pipe] enabling pipe B
>[  511.164240] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  511.231106] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  511.231111] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  511.231112] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  511.231114] [drm:check_crtc_state] [CRTC:25]
>[  511.231125] [drm:check_shared_dpll_state] WRPLL 1
>[  511.231126] [drm:check_shared_dpll_state] WRPLL 2
>[  511.231127] [drm:check_shared_dpll_state] SPLL
>[  511.231129] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880210d7b000
>[  511.231132] [drm:drm_atomic_state_free] Freeing atomic state ffff880210d7b000
>[  511.231160] [drm:drm_mode_setcrtc] [CRTC:25]
>[  511.231161] [drm:drm_atomic_state_init] Allocated atomic state ffff880210d7b000
>[  511.231163] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5491c00 state to ffff880210d7b000
>[  511.231165] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f5fde9c0 state to ffff880210d7b000
>[  511.231166] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f5491c00
>[  511.231167] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f5fde9c0 to [NOCRTC]
>[  511.231168] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f5fde9c0
>[  511.231169] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b000
>[  511.231170] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800d3bba060 state to ffff880210d7b000
>[  511.231171] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800d3bba060 to [NOCRTC]
>[  511.231172] [drm:drm_atomic_check_only] checking ffff880210d7b000
>[  511.231173] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  511.231174] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  511.231175] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  511.231176] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  511.231177] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  511.231178] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  511.231178] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b000
>[  511.231180] [drm:drm_atomic_connectors_for_crtc] State ffff880210d7b000 has 0 connectors for [CRTC:25]
>[  511.231182] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  511.231183] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  511.231185] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f5fde6c0 state to ffff880210d7b000
>[  511.231187] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f5fde180 state to ffff880210d7b000
>[  511.231189] [drm:drm_atomic_commit] commiting ffff880210d7b000
>[  511.247771] [drm:intel_disable_pipe] disabling pipe B
>[  511.282089] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  511.282092] [drm:intel_disable_shared_dpll] disabling SPLL
>[  511.282100] [drm:intel_power_well_disable] disabling display
>[  511.282102] [drm:hsw_set_power_well] Requesting to disable the power well
>[  511.282103] [drm:intel_power_well_disable] disabling always-on
>[  511.282104] [drm:intel_power_well_enable] enabling display
>[  511.282105] [drm:hsw_set_power_well] Enabling power well
>[  511.284175] [drm:intel_power_well_disable] disabling display
>[  511.284178] [drm:hsw_set_power_well] Requesting to disable the power well
>[  511.284183] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  511.284186] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  511.284187] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  511.284190] [drm:check_crtc_state] [CRTC:25]
>[  511.284191] [drm:check_shared_dpll_state] WRPLL 1
>[  511.284192] [drm:check_shared_dpll_state] WRPLL 2
>[  511.284193] [drm:check_shared_dpll_state] SPLL
>[  511.284195] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880210d7b000
>[  511.284197] [drm:drm_atomic_state_free] Freeing atomic state ffff880210d7b000
>[  511.284226] [drm:drm_mode_setcrtc] [CRTC:25]
>[  511.284229] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  511.284231] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bf2800
>[  511.284233] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880215be4000 state to ffff880026bf2800
>[  511.284234] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f4ced000 state to ffff880026bf2800
>[  511.284236] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff880215be4000
>[  511.284237] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f4ced000 to [CRTC:25]
>[  511.284238] [drm:drm_atomic_set_fb_for_plane] Set [FB:51] for plane state ffff8801f4ced000
>[  511.284239] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c01321a0 state to ffff880026bf2800
>[  511.284240] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf2800
>[  511.284241] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c01321a0 to [CRTC:25]
>[  511.284242] [drm:drm_atomic_check_only] checking ffff880026bf2800
>[  511.284244] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  511.284244] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  511.284245] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  511.284247] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  511.284247] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  511.284248] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  511.284249] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf2800
>[  511.284250] [drm:drm_atomic_connectors_for_crtc] State ffff880026bf2800 has 1 connectors for [CRTC:25]
>[  511.284252] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf2800
>[  511.284253] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  511.284254] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  511.284255] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  511.284256] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  511.284258] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff880215be4000 for pipe B
>[  511.284259] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  511.284259] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  511.284261] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  511.284262] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  511.284263] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  511.284264] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  511.284264] [drm:intel_dump_pipe_config] requested mode:
>[  511.284266] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  511.284267] [drm:intel_dump_pipe_config] adjusted mode:
>[  511.284268] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  511.284269] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  511.284270] [drm:intel_dump_pipe_config] port clock: 270000
>[  511.284271] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  511.284272] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  511.284273] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  511.284274] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  511.284274] [drm:intel_dump_pipe_config] ips: 0
>[  511.284275] [drm:intel_dump_pipe_config] double wide: 0
>[  511.284276] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  511.284277] [drm:intel_dump_pipe_config] planes on this crtc
>[  511.284278] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  511.284279] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  511.284280] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  511.284282] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff880215be4400 state to ffff880026bf2800
>[  511.284283] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff880215be6400 state to ffff880026bf2800
>[  511.284285] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 51
>[  511.284286] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  511.284288] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8801f4ceda80 state to ffff880026bf2800
>[  511.284289] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8801f4ced780 state to ffff880026bf2800
>[  511.284290] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8801f4cedd80 state to ffff880026bf2800
>[  511.284293] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f4ced480 state to ffff880026bf2800
>[  511.284294] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f4ced240 state to ffff880026bf2800
>[  511.284295] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8801f4ced900 state to ffff880026bf2800
>[  511.284296] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8801f4ced0c0 state to ffff880026bf2800
>[  511.284298] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8801f4ced540 state to ffff880026bf2800
>[  511.284299] [drm:drm_atomic_commit] commiting ffff880026bf2800
>[  511.284304] [drm:intel_power_well_enable] enabling display
>[  511.284305] [drm:hsw_set_power_well] Enabling power well
>[  511.286374] [drm:intel_power_well_enable] enabling always-on
>[  511.286384] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  511.286385] [drm:intel_enable_shared_dpll] enabling SPLL
>[  511.287274] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  511.287338] [drm:intel_enable_pipe] enabling pipe B
>[  511.287352] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  511.354228] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  511.354232] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  511.354234] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  511.354235] [drm:check_crtc_state] [CRTC:25]
>[  511.354247] [drm:check_shared_dpll_state] WRPLL 1
>[  511.354248] [drm:check_shared_dpll_state] WRPLL 2
>[  511.354249] [drm:check_shared_dpll_state] SPLL
>[  511.354250] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bf2800
>[  511.354254] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bf2800
>[  511.354281] [drm:drm_mode_setcrtc] [CRTC:25]
>[  511.354283] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bf2800
>[  511.354285] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880215be5c00 state to ffff880026bf2800
>[  511.354286] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f4cedc00 state to ffff880026bf2800
>[  511.354287] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff880215be5c00
>[  511.354288] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f4cedc00 to [NOCRTC]
>[  511.354289] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f4cedc00
>[  511.354290] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf2800
>[  511.354292] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c0132f20 state to ffff880026bf2800
>[  511.354293] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c0132f20 to [NOCRTC]
>[  511.354294] [drm:drm_atomic_check_only] checking ffff880026bf2800
>[  511.354295] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  511.354296] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  511.354297] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  511.354298] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  511.354298] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  511.354299] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  511.354300] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf2800
>[  511.354302] [drm:drm_atomic_connectors_for_crtc] State ffff880026bf2800 has 0 connectors for [CRTC:25]
>[  511.354304] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  511.354305] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  511.354307] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f4ced6c0 state to ffff880026bf2800
>[  511.354308] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f4cedb40 state to ffff880026bf2800
>[  511.354310] [drm:drm_atomic_commit] commiting ffff880026bf2800
>[  511.370896] [drm:intel_disable_pipe] disabling pipe B
>[  511.406003] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  511.406006] [drm:intel_disable_shared_dpll] disabling SPLL
>[  511.406014] [drm:intel_power_well_disable] disabling display
>[  511.406016] [drm:hsw_set_power_well] Requesting to disable the power well
>[  511.406017] [drm:intel_power_well_disable] disabling always-on
>[  511.406019] [drm:intel_power_well_enable] enabling display
>[  511.406020] [drm:hsw_set_power_well] Enabling power well
>[  511.408086] [drm:intel_power_well_disable] disabling display
>[  511.408090] [drm:hsw_set_power_well] Requesting to disable the power well
>[  511.408095] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  511.408097] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  511.408099] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  511.408101] [drm:check_crtc_state] [CRTC:25]
>[  511.408102] [drm:check_shared_dpll_state] WRPLL 1
>[  511.408104] [drm:check_shared_dpll_state] WRPLL 2
>[  511.408105] [drm:check_shared_dpll_state] SPLL
>[  511.408106] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bf2800
>[  511.408109] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bf2800
>[  511.408136] [drm:drm_mode_setcrtc] [CRTC:25]
>[  511.408140] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  511.408141] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bf2800
>[  511.408143] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880215be4000 state to ffff880026bf2800
>[  511.408145] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f4ced240 state to ffff880026bf2800
>[  511.408146] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff880215be4000
>[  511.408147] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f4ced240 to [CRTC:25]
>[  511.408148] [drm:drm_atomic_set_fb_for_plane] Set [FB:49] for plane state ffff8801f4ced240
>[  511.408149] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c01321a0 state to ffff880026bf2800
>[  511.408150] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf2800
>[  511.408151] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c01321a0 to [CRTC:25]
>[  511.408152] [drm:drm_atomic_check_only] checking ffff880026bf2800
>[  511.408154] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  511.408154] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  511.408156] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  511.408157] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  511.408158] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  511.408159] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  511.408159] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf2800
>[  511.408161] [drm:drm_atomic_connectors_for_crtc] State ffff880026bf2800 has 1 connectors for [CRTC:25]
>[  511.408162] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf2800
>[  511.408164] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  511.408164] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  511.408166] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  511.408167] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  511.408168] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff880215be4000 for pipe B
>[  511.408169] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  511.408170] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  511.408171] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  511.408172] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  511.408173] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  511.408174] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  511.408175] [drm:intel_dump_pipe_config] requested mode:
>[  511.408176] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  511.408177] [drm:intel_dump_pipe_config] adjusted mode:
>[  511.408178] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  511.408180] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  511.408180] [drm:intel_dump_pipe_config] port clock: 270000
>[  511.408181] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  511.408182] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  511.408183] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  511.408184] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  511.408185] [drm:intel_dump_pipe_config] ips: 0
>[  511.408185] [drm:intel_dump_pipe_config] double wide: 0
>[  511.408186] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  511.408187] [drm:intel_dump_pipe_config] planes on this crtc
>[  511.408188] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  511.408189] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  511.408190] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  511.408192] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff880215be5000 state to ffff880026bf2800
>[  511.408193] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff880215be4800 state to ffff880026bf2800
>[  511.408195] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 49
>[  511.408196] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  511.408198] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8801f4ced000 state to ffff880026bf2800
>[  511.408199] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8801f4ced840 state to ffff880026bf2800
>[  511.408200] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8801f4ced3c0 state to ffff880026bf2800
>[  511.408202] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f4ced600 state to ffff880026bf2800
>[  511.408204] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f4ced180 state to ffff880026bf2800
>[  511.408205] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8801f4ced9c0 state to ffff880026bf2800
>[  511.408207] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff880026901d80 state to ffff880026bf2800
>[  511.408208] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff880026901cc0 state to ffff880026bf2800
>[  511.408209] [drm:drm_atomic_commit] commiting ffff880026bf2800
>[  511.408214] [drm:intel_power_well_enable] enabling display
>[  511.408215] [drm:hsw_set_power_well] Enabling power well
>[  511.410263] [drm:intel_power_well_enable] enabling always-on
>[  511.410275] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  511.410277] [drm:intel_enable_shared_dpll] enabling SPLL
>[  511.411170] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  511.411256] [drm:intel_enable_pipe] enabling pipe B
>[  511.411273] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  511.478157] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  511.478163] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  511.478165] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  511.478168] [drm:check_crtc_state] [CRTC:25]
>[  511.478182] [drm:check_shared_dpll_state] WRPLL 1
>[  511.478183] [drm:check_shared_dpll_state] WRPLL 2
>[  511.478185] [drm:check_shared_dpll_state] SPLL
>[  511.478187] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bf2800
>[  511.478192] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bf2800
>[  511.478226] [drm:drm_mode_setcrtc] [CRTC:25]
>[  511.478229] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bf2800
>[  511.478231] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880215be6400 state to ffff880026bf2800
>[  511.478234] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8800269013c0 state to ffff880026bf2800
>[  511.478235] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff880215be6400
>[  511.478237] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800269013c0 to [NOCRTC]
>[  511.478238] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8800269013c0
>[  511.478240] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf2800
>[  511.478242] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c0132f20 state to ffff880026bf2800
>[  511.478243] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c0132f20 to [NOCRTC]
>[  511.478245] [drm:drm_atomic_check_only] checking ffff880026bf2800
>[  511.478246] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  511.478248] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  511.478249] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  511.478251] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  511.478252] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  511.478253] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  511.478255] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf2800
>[  511.478257] [drm:drm_atomic_connectors_for_crtc] State ffff880026bf2800 has 0 connectors for [CRTC:25]
>[  511.478261] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  511.478262] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  511.478265] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff880026901480 state to ffff880026bf2800
>[  511.478267] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff880026901540 state to ffff880026bf2800
>[  511.478269] [drm:drm_atomic_commit] commiting ffff880026bf2800
>[  511.494807] [drm:intel_disable_pipe] disabling pipe B
>[  511.528963] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  511.528967] [drm:intel_disable_shared_dpll] disabling SPLL
>[  511.528974] [drm:intel_power_well_disable] disabling display
>[  511.528976] [drm:hsw_set_power_well] Requesting to disable the power well
>[  511.528977] [drm:intel_power_well_disable] disabling always-on
>[  511.528978] [drm:intel_power_well_enable] enabling display
>[  511.528979] [drm:hsw_set_power_well] Enabling power well
>[  511.531048] [drm:intel_power_well_disable] disabling display
>[  511.531052] [drm:hsw_set_power_well] Requesting to disable the power well
>[  511.531057] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  511.531059] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  511.531060] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  511.531063] [drm:check_crtc_state] [CRTC:25]
>[  511.531064] [drm:check_shared_dpll_state] WRPLL 1
>[  511.531065] [drm:check_shared_dpll_state] WRPLL 2
>[  511.531066] [drm:check_shared_dpll_state] SPLL
>[  511.531068] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bf2800
>[  511.531071] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bf2800
>[  511.531098] [drm:drm_mode_setcrtc] [CRTC:25]
>[  511.531102] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  511.531104] [drm:drm_atomic_state_init] Allocated atomic state ffff880210d7b800
>[  511.531106] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5490c00 state to ffff880210d7b800
>[  511.531108] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f5fdeb40 state to ffff880210d7b800
>[  511.531109] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f5490c00
>[  511.531110] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f5fdeb40 to [CRTC:25]
>[  511.531111] [drm:drm_atomic_set_fb_for_plane] Set [FB:51] for plane state ffff8801f5fdeb40
>[  511.531113] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800d3bba080 state to ffff880210d7b800
>[  511.531114] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b800
>[  511.531115] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800d3bba080 to [CRTC:25]
>[  511.531115] [drm:drm_atomic_check_only] checking ffff880210d7b800
>[  511.531117] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  511.531118] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  511.531119] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  511.531120] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  511.531121] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  511.531122] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  511.531123] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b800
>[  511.531124] [drm:drm_atomic_connectors_for_crtc] State ffff880210d7b800 has 1 connectors for [CRTC:25]
>[  511.531125] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b800
>[  511.531127] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  511.531128] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  511.531129] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  511.531130] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  511.531132] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff8801f5490c00 for pipe B
>[  511.531133] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  511.531133] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  511.531135] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  511.531136] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  511.531137] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  511.531138] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  511.531138] [drm:intel_dump_pipe_config] requested mode:
>[  511.531140] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  511.531141] [drm:intel_dump_pipe_config] adjusted mode:
>[  511.531142] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  511.531143] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  511.531144] [drm:intel_dump_pipe_config] port clock: 270000
>[  511.531145] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  511.531146] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  511.531147] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  511.531148] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  511.531148] [drm:intel_dump_pipe_config] ips: 0
>[  511.531149] [drm:intel_dump_pipe_config] double wide: 0
>[  511.531150] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  511.531151] [drm:intel_dump_pipe_config] planes on this crtc
>[  511.531152] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  511.531153] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  511.531154] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  511.531156] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff8801f5491c00 state to ffff880210d7b800
>[  511.531157] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff8801f5492c00 state to ffff880210d7b800
>[  511.531159] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 51
>[  511.531160] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  511.531162] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8801f5fde540 state to ffff880210d7b800
>[  511.531163] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8801f5fde3c0 state to ffff880210d7b800
>[  511.531164] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8801f5fde900 state to ffff880210d7b800
>[  511.531167] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f5fdef00 state to ffff880210d7b800
>[  511.531168] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f5fdee40 state to ffff880210d7b800
>[  511.531170] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8801f5fded80 state to ffff880210d7b800
>[  511.531171] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8801f5fdea80 state to ffff880210d7b800
>[  511.531172] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8801f5fde180 state to ffff880210d7b800
>[  511.531173] [drm:drm_atomic_commit] commiting ffff880210d7b800
>[  511.531178] [drm:intel_power_well_enable] enabling display
>[  511.531179] [drm:hsw_set_power_well] Enabling power well
>[  511.533016] [drm:intel_power_well_enable] enabling always-on
>[  511.533027] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  511.533028] [drm:intel_enable_shared_dpll] enabling SPLL
>[  511.534562] [drm:hsw_fdi_link_train] FDI link training done on step 1
>[  511.534626] [drm:intel_enable_pipe] enabling pipe B
>[  511.534640] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  511.601486] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  511.601490] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  511.601491] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  511.601493] [drm:check_crtc_state] [CRTC:25]
>[  511.601504] [drm:check_shared_dpll_state] WRPLL 1
>[  511.601505] [drm:check_shared_dpll_state] WRPLL 2
>[  511.601506] [drm:check_shared_dpll_state] SPLL
>[  511.601508] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880210d7b800
>[  511.601511] [drm:drm_atomic_state_free] Freeing atomic state ffff880210d7b800
>[  511.601538] [drm:drm_mode_setcrtc] [CRTC:25]
>[  511.601541] [drm:drm_atomic_state_init] Allocated atomic state ffff88020103c400
>[  511.601543] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5327c00 state to ffff88020103c400
>[  511.601545] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f55af600 state to ffff88020103c400
>[  511.601546] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f5327c00
>[  511.601547] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55af600 to [NOCRTC]
>[  511.601548] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f55af600
>[  511.601549] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103c400
>[  511.601550] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c909b1a0 state to ffff88020103c400
>[  511.601551] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c909b1a0 to [NOCRTC]
>[  511.601552] [drm:drm_atomic_check_only] checking ffff88020103c400
>[  511.601553] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  511.601554] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  511.601555] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  511.601556] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  511.601557] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  511.601558] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  511.601559] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103c400
>[  511.601560] [drm:drm_atomic_connectors_for_crtc] State ffff88020103c400 has 0 connectors for [CRTC:25]
>[  511.601563] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  511.601564] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  511.601565] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f55aff00 state to ffff88020103c400
>[  511.601567] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f55af000 state to ffff88020103c400
>[  511.601569] [drm:drm_atomic_commit] commiting ffff88020103c400
>[  511.618177] [drm:intel_disable_pipe] disabling pipe B
>[  511.653297] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  511.653299] [drm:intel_disable_shared_dpll] disabling SPLL
>[  511.653308] [drm:intel_power_well_disable] disabling display
>[  511.653309] [drm:hsw_set_power_well] Requesting to disable the power well
>[  511.653310] [drm:intel_power_well_disable] disabling always-on
>[  511.653312] [drm:intel_power_well_enable] enabling display
>[  511.653313] [drm:hsw_set_power_well] Enabling power well
>[  511.655381] [drm:intel_power_well_disable] disabling display
>[  511.655385] [drm:hsw_set_power_well] Requesting to disable the power well
>[  511.655390] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  511.655392] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  511.655394] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  511.655396] [drm:check_crtc_state] [CRTC:25]
>[  511.655398] [drm:check_shared_dpll_state] WRPLL 1
>[  511.655399] [drm:check_shared_dpll_state] WRPLL 2
>[  511.655400] [drm:check_shared_dpll_state] SPLL
>[  511.655402] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88020103c400
>[  511.655404] [drm:drm_atomic_state_free] Freeing atomic state ffff88020103c400
>[  511.655432] [drm:drm_mode_setcrtc] [CRTC:25]
>[  511.655435] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  511.655437] [drm:drm_atomic_state_init] Allocated atomic state ffff88020103c400
>[  511.655439] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5324400 state to ffff88020103c400
>[  511.655440] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f55af840 state to ffff88020103c400
>[  511.655442] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f5324400
>[  511.655443] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55af840 to [CRTC:25]
>[  511.655444] [drm:drm_atomic_set_fb_for_plane] Set [FB:49] for plane state ffff8801f55af840
>[  511.655445] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c909b140 state to ffff88020103c400
>[  511.655446] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103c400
>[  511.655447] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c909b140 to [CRTC:25]
>[  511.655448] [drm:drm_atomic_check_only] checking ffff88020103c400
>[  511.655450] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  511.655450] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  511.655451] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  511.655453] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  511.655453] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  511.655454] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  511.655455] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103c400
>[  511.655457] [drm:drm_atomic_connectors_for_crtc] State ffff88020103c400 has 1 connectors for [CRTC:25]
>[  511.655458] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103c400
>[  511.655459] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  511.655460] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  511.655462] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  511.655463] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  511.655464] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff8801f5324400 for pipe B
>[  511.655465] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  511.655465] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  511.655467] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  511.655468] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  511.655469] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  511.655470] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  511.655470] [drm:intel_dump_pipe_config] requested mode:
>[  511.655472] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  511.655473] [drm:intel_dump_pipe_config] adjusted mode:
>[  511.655474] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  511.655475] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  511.655476] [drm:intel_dump_pipe_config] port clock: 270000
>[  511.655477] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  511.655478] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  511.655478] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  511.655479] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  511.655480] [drm:intel_dump_pipe_config] ips: 0
>[  511.655481] [drm:intel_dump_pipe_config] double wide: 0
>[  511.655482] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  511.655483] [drm:intel_dump_pipe_config] planes on this crtc
>[  511.655484] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  511.655485] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  511.655486] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  511.655488] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff8801f5327800 state to ffff88020103c400
>[  511.655489] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff8801f5326000 state to ffff88020103c400
>[  511.655491] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 49
>[  511.655492] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  511.655494] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8801f55afe40 state to ffff88020103c400
>[  511.655495] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8801f55af9c0 state to ffff88020103c400
>[  511.655496] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8801f55af780 state to ffff88020103c400
>[  511.655498] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f55af480 state to ffff88020103c400
>[  511.655500] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f55afa80 state to ffff88020103c400
>[  511.655501] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8801f55af240 state to ffff88020103c400
>[  511.655502] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8801f55af900 state to ffff88020103c400
>[  511.655503] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8801f55af540 state to ffff88020103c400
>[  511.655505] [drm:drm_atomic_commit] commiting ffff88020103c400
>[  511.655509] [drm:intel_power_well_enable] enabling display
>[  511.655511] [drm:hsw_set_power_well] Enabling power well
>[  511.657003] [drm:intel_power_well_enable] enabling always-on
>[  511.657015] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  511.657016] [drm:intel_enable_shared_dpll] enabling SPLL
>[  511.657906] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  511.657970] [drm:intel_enable_pipe] enabling pipe B
>[  511.657984] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  511.724852] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  511.724856] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  511.724858] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  511.724859] [drm:check_crtc_state] [CRTC:25]
>[  511.724871] [drm:check_shared_dpll_state] WRPLL 1
>[  511.724872] [drm:check_shared_dpll_state] WRPLL 2
>[  511.724873] [drm:check_shared_dpll_state] SPLL
>[  511.724874] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88020103c400
>[  511.724878] [drm:drm_atomic_state_free] Freeing atomic state ffff88020103c400
>[  511.724906] [drm:drm_mode_setcrtc] [CRTC:25]
>[  511.724926] [drm:drm_atomic_state_init] Allocated atomic state ffff880210d7b400
>[  511.724929] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5492c00 state to ffff880210d7b400
>[  511.724930] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f5fde180 state to ffff880210d7b400
>[  511.724931] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f5492c00
>[  511.724932] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f5fde180 to [NOCRTC]
>[  511.724933] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f5fde180
>[  511.724934] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b400
>[  511.724935] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800d3bbad00 state to ffff880210d7b400
>[  511.724936] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800d3bbad00 to [NOCRTC]
>[  511.724937] [drm:drm_atomic_check_only] checking ffff880210d7b400
>[  511.724939] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  511.724939] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  511.724941] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  511.724943] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  511.724943] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  511.724944] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  511.724946] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b400
>[  511.724948] [drm:drm_atomic_connectors_for_crtc] State ffff880210d7b400 has 0 connectors for [CRTC:25]
>[  511.724951] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  511.724952] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  511.724953] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f5fdea80 state to ffff880210d7b400
>[  511.724954] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f5fded80 state to ffff880210d7b400
>[  511.724957] [drm:drm_atomic_commit] commiting ffff880210d7b400
>[  511.741521] [drm:intel_disable_pipe] disabling pipe B
>[  511.775988] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  511.775991] [drm:intel_disable_shared_dpll] disabling SPLL
>[  511.775999] [drm:intel_power_well_disable] disabling display
>[  511.776001] [drm:hsw_set_power_well] Requesting to disable the power well
>[  511.776002] [drm:intel_power_well_disable] disabling always-on
>[  511.776003] [drm:intel_power_well_enable] enabling display
>[  511.776004] [drm:hsw_set_power_well] Enabling power well
>[  511.778074] [drm:intel_power_well_disable] disabling display
>[  511.778078] [drm:hsw_set_power_well] Requesting to disable the power well
>[  511.778083] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  511.778085] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  511.778087] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  511.778089] [drm:check_crtc_state] [CRTC:25]
>[  511.778091] [drm:check_shared_dpll_state] WRPLL 1
>[  511.778092] [drm:check_shared_dpll_state] WRPLL 2
>[  511.778093] [drm:check_shared_dpll_state] SPLL
>[  511.778095] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880210d7b400
>[  511.778097] [drm:drm_atomic_state_free] Freeing atomic state ffff880210d7b400
>[  511.778125] [drm:drm_mode_setcrtc] [CRTC:25]
>[  511.778128] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  511.778130] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bf3800
>[  511.778132] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880215be5c00 state to ffff880026bf3800
>[  511.778134] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff880026901600 state to ffff880026bf3800
>[  511.778135] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff880215be5c00
>[  511.778136] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880026901600 to [CRTC:25]
>[  511.778137] [drm:drm_atomic_set_fb_for_plane] Set [FB:51] for plane state ffff880026901600
>[  511.778138] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c0132a80 state to ffff880026bf3800
>[  511.778139] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3800
>[  511.778140] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c0132a80 to [CRTC:25]
>[  511.778141] [drm:drm_atomic_check_only] checking ffff880026bf3800
>[  511.778143] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  511.778143] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  511.778144] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  511.778146] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  511.778147] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  511.778147] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  511.778148] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3800
>[  511.778150] [drm:drm_atomic_connectors_for_crtc] State ffff880026bf3800 has 1 connectors for [CRTC:25]
>[  511.778151] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3800
>[  511.778152] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  511.778153] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  511.778155] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  511.778156] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  511.778157] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff880215be5c00 for pipe B
>[  511.778158] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  511.778159] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  511.778160] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  511.778161] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  511.778162] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  511.778163] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  511.778164] [drm:intel_dump_pipe_config] requested mode:
>[  511.778165] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  511.778166] [drm:intel_dump_pipe_config] adjusted mode:
>[  511.778168] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  511.778169] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  511.778170] [drm:intel_dump_pipe_config] port clock: 270000
>[  511.778170] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  511.778171] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  511.778172] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  511.778173] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  511.778174] [drm:intel_dump_pipe_config] ips: 0
>[  511.778175] [drm:intel_dump_pipe_config] double wide: 0
>[  511.778176] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  511.778177] [drm:intel_dump_pipe_config] planes on this crtc
>[  511.778178] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  511.778179] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  511.778180] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  511.778181] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff880215be4400 state to ffff880026bf3800
>[  511.778183] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff880215be4800 state to ffff880026bf3800
>[  511.778185] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 51
>[  511.778186] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  511.778187] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff880026901780 state to ffff880026bf3800
>[  511.778189] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff880026901840 state to ffff880026bf3800
>[  511.778190] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff880026901900 state to ffff880026bf3800
>[  511.778192] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8800269019c0 state to ffff880026bf3800
>[  511.778193] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8800269016c0 state to ffff880026bf3800
>[  511.778195] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff880026901cc0 state to ffff880026bf3800
>[  511.778196] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff880026901d80 state to ffff880026bf3800
>[  511.778197] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff880026901540 state to ffff880026bf3800
>[  511.778198] [drm:drm_atomic_commit] commiting ffff880026bf3800
>[  511.778203] [drm:intel_power_well_enable] enabling display
>[  511.778204] [drm:hsw_set_power_well] Enabling power well
>[  511.780272] [drm:intel_power_well_enable] enabling always-on
>[  511.780281] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  511.780283] [drm:intel_enable_shared_dpll] enabling SPLL
>[  511.781172] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  511.781237] [drm:intel_enable_pipe] enabling pipe B
>[  511.781251] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  511.850180] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  511.850185] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  511.850186] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  511.850188] [drm:check_crtc_state] [CRTC:25]
>[  511.850199] [drm:check_shared_dpll_state] WRPLL 1
>[  511.850200] [drm:check_shared_dpll_state] WRPLL 2
>[  511.850201] [drm:check_shared_dpll_state] SPLL
>[  511.850203] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bf3800
>[  511.850207] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bf3800
>[  511.850233] [drm:drm_mode_setcrtc] [CRTC:25]
>[  511.850235] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bf3800
>[  511.850237] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880215be6400 state to ffff880026bf3800
>[  511.850239] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff880026901480 state to ffff880026bf3800
>[  511.850240] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff880215be6400
>[  511.850240] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880026901480 to [NOCRTC]
>[  511.850241] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880026901480
>[  511.850243] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3800
>[  511.850244] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c01323c0 state to ffff880026bf3800
>[  511.850244] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c01323c0 to [NOCRTC]
>[  511.850245] [drm:drm_atomic_check_only] checking ffff880026bf3800
>[  511.850247] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  511.850247] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  511.850249] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  511.850249] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  511.850250] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  511.850251] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  511.850252] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3800
>[  511.850253] [drm:drm_atomic_connectors_for_crtc] State ffff880026bf3800 has 0 connectors for [CRTC:25]
>[  511.850256] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  511.850257] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  511.850259] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8800269013c0 state to ffff880026bf3800
>[  511.850260] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f4ced9c0 state to ffff880026bf3800
>[  511.850262] [drm:drm_atomic_commit] commiting ffff880026bf3800
>[  511.866848] [drm:intel_disable_pipe] disabling pipe B
>[  511.901879] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  511.901882] [drm:intel_disable_shared_dpll] disabling SPLL
>[  511.901890] [drm:intel_power_well_disable] disabling display
>[  511.901892] [drm:hsw_set_power_well] Requesting to disable the power well
>[  511.901892] [drm:intel_power_well_disable] disabling always-on
>[  511.901894] [drm:intel_power_well_enable] enabling display
>[  511.901895] [drm:hsw_set_power_well] Enabling power well
>[  511.903964] [drm:intel_power_well_disable] disabling display
>[  511.903968] [drm:hsw_set_power_well] Requesting to disable the power well
>[  511.903973] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  511.903975] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  511.903976] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  511.903979] [drm:check_crtc_state] [CRTC:25]
>[  511.903981] [drm:check_shared_dpll_state] WRPLL 1
>[  511.903982] [drm:check_shared_dpll_state] WRPLL 2
>[  511.903983] [drm:check_shared_dpll_state] SPLL
>[  511.903985] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bf3800
>[  511.903987] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bf3800
>[  511.904015] [drm:drm_mode_setcrtc] [CRTC:25]
>[  511.904018] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  511.904020] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bf3800
>[  511.904021] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880215be5c00 state to ffff880026bf3800
>[  511.904023] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f4ced3c0 state to ffff880026bf3800
>[  511.904024] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff880215be5c00
>[  511.904025] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f4ced3c0 to [CRTC:25]
>[  511.904026] [drm:drm_atomic_set_fb_for_plane] Set [FB:49] for plane state ffff8801f4ced3c0
>[  511.904027] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c0132a80 state to ffff880026bf3800
>[  511.904028] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3800
>[  511.904029] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c0132a80 to [CRTC:25]
>[  511.904030] [drm:drm_atomic_check_only] checking ffff880026bf3800
>[  511.904032] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  511.904033] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  511.904034] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  511.904035] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  511.904036] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  511.904037] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  511.904038] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3800
>[  511.904039] [drm:drm_atomic_connectors_for_crtc] State ffff880026bf3800 has 1 connectors for [CRTC:25]
>[  511.904040] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3800
>[  511.904042] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  511.904043] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  511.904044] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  511.904045] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  511.904047] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff880215be5c00 for pipe B
>[  511.904048] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  511.904048] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  511.904050] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  511.904051] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  511.904052] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  511.904052] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  511.904053] [drm:intel_dump_pipe_config] requested mode:
>[  511.904055] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  511.904055] [drm:intel_dump_pipe_config] adjusted mode:
>[  511.904057] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  511.904058] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  511.904059] [drm:intel_dump_pipe_config] port clock: 270000
>[  511.904059] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  511.904060] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  511.904061] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  511.904062] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  511.904063] [drm:intel_dump_pipe_config] ips: 0
>[  511.904064] [drm:intel_dump_pipe_config] double wide: 0
>[  511.904065] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  511.904066] [drm:intel_dump_pipe_config] planes on this crtc
>[  511.904067] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  511.904068] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  511.904069] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  511.904071] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff880215be5000 state to ffff880026bf3800
>[  511.904072] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff880215be4000 state to ffff880026bf3800
>[  511.904074] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 49
>[  511.904075] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  511.904077] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8801f4ced000 state to ffff880026bf3800
>[  511.904078] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8801f4ced180 state to ffff880026bf3800
>[  511.904079] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8801f4ced600 state to ffff880026bf3800
>[  511.904081] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f4ced240 state to ffff880026bf3800
>[  511.904082] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f4ced480 state to ffff880026bf3800
>[  511.904084] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8801f4ced540 state to ffff880026bf3800
>[  511.904085] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8801f4ced0c0 state to ffff880026bf3800
>[  511.904086] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8801f4ced900 state to ffff880026bf3800
>[  511.904087] [drm:drm_atomic_commit] commiting ffff880026bf3800
>[  511.904092] [drm:intel_power_well_enable] enabling display
>[  511.904093] [drm:hsw_set_power_well] Enabling power well
>[  511.906161] [drm:intel_power_well_enable] enabling always-on
>[  511.906173] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  511.906174] [drm:intel_enable_shared_dpll] enabling SPLL
>[  511.907063] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  511.907135] [drm:intel_enable_pipe] enabling pipe B
>[  511.907148] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  511.974015] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  511.974019] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  511.974021] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  511.974022] [drm:check_crtc_state] [CRTC:25]
>[  511.974033] [drm:check_shared_dpll_state] WRPLL 1
>[  511.974034] [drm:check_shared_dpll_state] WRPLL 2
>[  511.974035] [drm:check_shared_dpll_state] SPLL
>[  511.974037] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bf3800
>[  511.974041] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bf3800
>[  511.974067] [drm:drm_mode_setcrtc] [CRTC:25]
>[  511.974069] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bf3800
>[  511.974071] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880215be4800 state to ffff880026bf3800
>[  511.974072] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f4ced9c0 state to ffff880026bf3800
>[  511.974073] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff880215be4800
>[  511.974074] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f4ced9c0 to [NOCRTC]
>[  511.974075] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f4ced9c0
>[  511.974077] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3800
>[  511.974078] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c01323c0 state to ffff880026bf3800
>[  511.974079] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c01323c0 to [NOCRTC]
>[  511.974079] [drm:drm_atomic_check_only] checking ffff880026bf3800
>[  511.974081] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  511.974081] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  511.974083] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  511.974083] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  511.974084] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  511.974085] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  511.974086] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3800
>[  511.974087] [drm:drm_atomic_connectors_for_crtc] State ffff880026bf3800 has 0 connectors for [CRTC:25]
>[  511.974090] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  511.974091] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  511.974093] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f4cedb40 state to ffff880026bf3800
>[  511.974094] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f4ced6c0 state to ffff880026bf3800
>[  511.974096] [drm:drm_atomic_commit] commiting ffff880026bf3800
>[  511.990683] [drm:intel_disable_pipe] disabling pipe B
>[  512.025483] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  512.025486] [drm:intel_disable_shared_dpll] disabling SPLL
>[  512.025494] [drm:intel_power_well_disable] disabling display
>[  512.025496] [drm:hsw_set_power_well] Requesting to disable the power well
>[  512.025497] [drm:intel_power_well_disable] disabling always-on
>[  512.025498] [drm:intel_power_well_enable] enabling display
>[  512.025499] [drm:hsw_set_power_well] Enabling power well
>[  512.027568] [drm:intel_power_well_disable] disabling display
>[  512.027571] [drm:hsw_set_power_well] Requesting to disable the power well
>[  512.027577] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  512.027579] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  512.027580] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  512.027583] [drm:check_crtc_state] [CRTC:25]
>[  512.027584] [drm:check_shared_dpll_state] WRPLL 1
>[  512.027585] [drm:check_shared_dpll_state] WRPLL 2
>[  512.027586] [drm:check_shared_dpll_state] SPLL
>[  512.027588] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bf3800
>[  512.027590] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bf3800
>[  512.027618] [drm:drm_mode_setcrtc] [CRTC:25]
>[  512.027621] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  512.027623] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bf3800
>[  512.027625] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880215be5c00 state to ffff880026bf3800
>[  512.027626] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f4ced480 state to ffff880026bf3800
>[  512.027627] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff880215be5c00
>[  512.027628] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f4ced480 to [CRTC:25]
>[  512.027629] [drm:drm_atomic_set_fb_for_plane] Set [FB:51] for plane state ffff8801f4ced480
>[  512.027630] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c0132a80 state to ffff880026bf3800
>[  512.027631] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3800
>[  512.027632] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c0132a80 to [CRTC:25]
>[  512.027633] [drm:drm_atomic_check_only] checking ffff880026bf3800
>[  512.027635] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  512.027636] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  512.027637] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  512.027638] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  512.027639] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  512.027640] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  512.027641] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3800
>[  512.027642] [drm:drm_atomic_connectors_for_crtc] State ffff880026bf3800 has 1 connectors for [CRTC:25]
>[  512.027643] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3800
>[  512.027645] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  512.027646] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  512.027647] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  512.027648] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  512.027650] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff880215be5c00 for pipe B
>[  512.027650] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  512.027651] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  512.027652] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  512.027653] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  512.027654] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  512.027655] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  512.027656] [drm:intel_dump_pipe_config] requested mode:
>[  512.027657] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  512.027658] [drm:intel_dump_pipe_config] adjusted mode:
>[  512.027659] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  512.027661] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  512.027661] [drm:intel_dump_pipe_config] port clock: 270000
>[  512.027662] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  512.027663] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  512.027664] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  512.027665] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  512.027666] [drm:intel_dump_pipe_config] ips: 0
>[  512.027666] [drm:intel_dump_pipe_config] double wide: 0
>[  512.027667] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  512.027668] [drm:intel_dump_pipe_config] planes on this crtc
>[  512.027670] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  512.027671] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  512.027671] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  512.027673] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff880215be6400 state to ffff880026bf3800
>[  512.027674] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff880215be4400 state to ffff880026bf3800
>[  512.027676] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 51
>[  512.027677] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  512.027679] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8801f4ced3c0 state to ffff880026bf3800
>[  512.027680] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8801f4ced840 state to ffff880026bf3800
>[  512.027681] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8801f4cedc00 state to ffff880026bf3800
>[  512.027684] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f4cedd80 state to ffff880026bf3800
>[  512.027685] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f4ced780 state to ffff880026bf3800
>[  512.027686] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8801f4ceda80 state to ffff880026bf3800
>[  512.027688] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff880026901540 state to ffff880026bf3800
>[  512.027689] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff880026901d80 state to ffff880026bf3800
>[  512.027691] [drm:drm_atomic_commit] commiting ffff880026bf3800
>[  512.027696] [drm:intel_power_well_enable] enabling display
>[  512.027697] [drm:hsw_set_power_well] Enabling power well
>[  512.028975] [drm:intel_power_well_enable] enabling always-on
>[  512.028986] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  512.028988] [drm:intel_enable_shared_dpll] enabling SPLL
>[  512.029877] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  512.029941] [drm:intel_enable_pipe] enabling pipe B
>[  512.029955] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  512.096823] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  512.096827] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  512.096828] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  512.096830] [drm:check_crtc_state] [CRTC:25]
>[  512.096841] [drm:check_shared_dpll_state] WRPLL 1
>[  512.096842] [drm:check_shared_dpll_state] WRPLL 2
>[  512.096843] [drm:check_shared_dpll_state] SPLL
>[  512.096845] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bf3800
>[  512.096849] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bf3800
>[  512.096911] [drm:drm_mode_setcrtc] [CRTC:25]
>[  512.096915] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bfb200
>[  512.096918] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880025a41800 state to ffff880026bfb200
>[  512.096923] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8800c78d4600 state to ffff880026bfb200
>[  512.096925] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff880025a41800
>[  512.096926] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800c78d4600 to [NOCRTC]
>[  512.096928] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8800c78d4600
>[  512.096931] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfb200
>[  512.096933] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8801f442db20 state to ffff880026bfb200
>[  512.096935] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f442db20 to [NOCRTC]
>[  512.096936] [drm:drm_atomic_check_only] checking ffff880026bfb200
>[  512.096938] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  512.096939] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  512.096941] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  512.096942] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  512.096944] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  512.096945] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  512.096947] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfb200
>[  512.096949] [drm:drm_atomic_connectors_for_crtc] State ffff880026bfb200 has 0 connectors for [CRTC:25]
>[  512.096954] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  512.096956] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  512.096959] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8800c78d4a80 state to ffff880026bfb200
>[  512.096962] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8800c78d4240 state to ffff880026bfb200
>[  512.096966] [drm:drm_atomic_commit] commiting ffff880026bfb200
>[  512.113504] [drm:intel_disable_pipe] disabling pipe B
>[  512.148052] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  512.148057] [drm:intel_disable_shared_dpll] disabling SPLL
>[  512.148067] [drm:intel_power_well_disable] disabling display
>[  512.148070] [drm:hsw_set_power_well] Requesting to disable the power well
>[  512.148071] [drm:intel_power_well_disable] disabling always-on
>[  512.148073] [drm:intel_power_well_enable] enabling display
>[  512.148074] [drm:hsw_set_power_well] Enabling power well
>[  512.150150] [drm:intel_power_well_disable] disabling display
>[  512.150154] [drm:hsw_set_power_well] Requesting to disable the power well
>[  512.150160] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  512.150163] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  512.150165] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  512.150169] [drm:check_crtc_state] [CRTC:25]
>[  512.150170] [drm:check_shared_dpll_state] WRPLL 1
>[  512.150172] [drm:check_shared_dpll_state] WRPLL 2
>[  512.150173] [drm:check_shared_dpll_state] SPLL
>[  512.150176] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bfb200
>[  512.150179] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bfb200
>[  512.150213] [drm:drm_mode_setcrtc] [CRTC:25]
>[  512.150217] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  512.150220] [drm:drm_atomic_state_init] Allocated atomic state ffff88020103d800
>[  512.150222] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5325000 state to ffff88020103d800
>[  512.150224] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f55af3c0 state to ffff88020103d800
>[  512.150227] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f5325000
>[  512.150228] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55af3c0 to [CRTC:25]
>[  512.150230] [drm:drm_atomic_set_fb_for_plane] Set [FB:49] for plane state ffff8801f55af3c0
>[  512.150231] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c909bc60 state to ffff88020103d800
>[  512.150233] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103d800
>[  512.150235] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c909bc60 to [CRTC:25]
>[  512.150236] [drm:drm_atomic_check_only] checking ffff88020103d800
>[  512.150238] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  512.150239] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  512.150241] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  512.150243] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  512.150244] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  512.150245] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  512.150246] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103d800
>[  512.150248] [drm:drm_atomic_connectors_for_crtc] State ffff88020103d800 has 1 connectors for [CRTC:25]
>[  512.150250] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103d800
>[  512.150252] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  512.150253] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  512.150256] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  512.150257] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  512.150259] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff8801f5325000 for pipe B
>[  512.150260] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  512.150261] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  512.150263] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  512.150265] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  512.150267] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  512.150268] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  512.150269] [drm:intel_dump_pipe_config] requested mode:
>[  512.150272] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  512.150273] [drm:intel_dump_pipe_config] adjusted mode:
>[  512.150275] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  512.150277] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  512.150278] [drm:intel_dump_pipe_config] port clock: 270000
>[  512.150279] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  512.150280] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  512.150282] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  512.150283] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  512.150284] [drm:intel_dump_pipe_config] ips: 0
>[  512.150285] [drm:intel_dump_pipe_config] double wide: 0
>[  512.150287] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  512.150288] [drm:intel_dump_pipe_config] planes on this crtc
>[  512.150290] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  512.150291] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  512.150292] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  512.150295] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff8801f5324000 state to ffff88020103d800
>[  512.150297] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff8801f5326400 state to ffff88020103d800
>[  512.150299] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 49
>[  512.150301] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  512.150303] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8801f55afb40 state to ffff88020103d800
>[  512.150305] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8801f55af300 state to ffff88020103d800
>[  512.150306] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8801f55af6c0 state to ffff88020103d800
>[  512.150310] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f55afc00 state to ffff88020103d800
>[  512.150311] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f55afcc0 state to ffff88020103d800
>[  512.150314] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8801f55af540 state to ffff88020103d800
>[  512.150316] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8801f55af900 state to ffff88020103d800
>[  512.150318] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8801f55af240 state to ffff88020103d800
>[  512.150320] [drm:drm_atomic_commit] commiting ffff88020103d800
>[  512.150326] [drm:intel_power_well_enable] enabling display
>[  512.150327] [drm:hsw_set_power_well] Enabling power well
>[  512.152402] [drm:intel_power_well_enable] enabling always-on
>[  512.152414] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  512.152415] [drm:intel_enable_shared_dpll] enabling SPLL
>[  512.153309] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  512.153393] [drm:intel_enable_pipe] enabling pipe B
>[  512.153409] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  512.220238] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  512.220242] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  512.220244] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  512.220245] [drm:check_crtc_state] [CRTC:25]
>[  512.220256] [drm:check_shared_dpll_state] WRPLL 1
>[  512.220257] [drm:check_shared_dpll_state] WRPLL 2
>[  512.220258] [drm:check_shared_dpll_state] SPLL
>[  512.220259] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88020103d800
>[  512.220263] [drm:drm_atomic_state_free] Freeing atomic state ffff88020103d800
>[  512.220285] [drm:drm_mode_setcrtc] [CRTC:25]
>[  512.220286] [drm:drm_atomic_state_init] Allocated atomic state ffff88020103d800
>[  512.220288] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5326000 state to ffff88020103d800
>[  512.220290] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f55af780 state to ffff88020103d800
>[  512.220291] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f5326000
>[  512.220292] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55af780 to [NOCRTC]
>[  512.220293] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f55af780
>[  512.220294] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103d800
>[  512.220295] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c909b1c0 state to ffff88020103d800
>[  512.220296] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c909b1c0 to [NOCRTC]
>[  512.220297] [drm:drm_atomic_check_only] checking ffff88020103d800
>[  512.220298] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  512.220299] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  512.220300] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  512.220301] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  512.220302] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  512.220303] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  512.220303] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103d800
>[  512.220305] [drm:drm_atomic_connectors_for_crtc] State ffff88020103d800 has 0 connectors for [CRTC:25]
>[  512.220307] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  512.220308] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  512.220310] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f55af9c0 state to ffff88020103d800
>[  512.220311] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f55afe40 state to ffff88020103d800
>[  512.220313] [drm:drm_atomic_commit] commiting ffff88020103d800
>[  512.236925] [drm:intel_disable_pipe] disabling pipe B
>[  512.271878] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  512.271881] [drm:intel_disable_shared_dpll] disabling SPLL
>[  512.271889] [drm:intel_power_well_disable] disabling display
>[  512.271891] [drm:hsw_set_power_well] Requesting to disable the power well
>[  512.271892] [drm:intel_power_well_disable] disabling always-on
>[  512.271893] [drm:intel_power_well_enable] enabling display
>[  512.271894] [drm:hsw_set_power_well] Enabling power well
>[  512.272949] [drm:intel_power_well_disable] disabling display
>[  512.272953] [drm:hsw_set_power_well] Requesting to disable the power well
>[  512.272959] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  512.272962] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  512.272963] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  512.272966] [drm:check_crtc_state] [CRTC:25]
>[  512.272968] [drm:check_shared_dpll_state] WRPLL 1
>[  512.272969] [drm:check_shared_dpll_state] WRPLL 2
>[  512.272970] [drm:check_shared_dpll_state] SPLL
>[  512.272972] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88020103d800
>[  512.272975] [drm:drm_atomic_state_free] Freeing atomic state ffff88020103d800
>[  512.272999] [drm:drm_mode_setcrtc] [CRTC:25]
>[  512.273003] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  512.273004] [drm:drm_atomic_state_init] Allocated atomic state ffff88020103d800
>[  512.273006] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5325000 state to ffff88020103d800
>[  512.273009] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f55afcc0 state to ffff88020103d800
>[  512.273010] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f5325000
>[  512.273011] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55afcc0 to [CRTC:25]
>[  512.273012] [drm:drm_atomic_set_fb_for_plane] Set [FB:51] for plane state ffff8801f55afcc0
>[  512.273014] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c909bc60 state to ffff88020103d800
>[  512.273015] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103d800
>[  512.273017] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c909bc60 to [CRTC:25]
>[  512.273018] [drm:drm_atomic_check_only] checking ffff88020103d800
>[  512.273020] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  512.273021] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  512.273022] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  512.273024] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  512.273025] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  512.273026] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  512.273027] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103d800
>[  512.273028] [drm:drm_atomic_connectors_for_crtc] State ffff88020103d800 has 1 connectors for [CRTC:25]
>[  512.273030] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103d800
>[  512.273032] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  512.273033] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  512.273035] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  512.273036] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  512.273038] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff8801f5325000 for pipe B
>[  512.273038] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  512.273039] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  512.273042] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  512.273043] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  512.273044] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  512.273045] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  512.273046] [drm:intel_dump_pipe_config] requested mode:
>[  512.273048] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  512.273049] [drm:intel_dump_pipe_config] adjusted mode:
>[  512.273050] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  512.273052] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  512.273053] [drm:intel_dump_pipe_config] port clock: 270000
>[  512.273054] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  512.273055] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  512.273056] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  512.273057] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  512.273058] [drm:intel_dump_pipe_config] ips: 0
>[  512.273059] [drm:intel_dump_pipe_config] double wide: 0
>[  512.273060] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  512.273061] [drm:intel_dump_pipe_config] planes on this crtc
>[  512.273062] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  512.273063] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  512.273064] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  512.273066] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff8801f5327800 state to ffff88020103d800
>[  512.273067] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff8801f5324400 state to ffff88020103d800
>[  512.273069] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 51
>[  512.273070] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  512.273072] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8801f55af3c0 state to ffff88020103d800
>[  512.273073] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8801f55af0c0 state to ffff88020103d800
>[  512.273074] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8801f55afa80 state to ffff88020103d800
>[  512.273077] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f55af480 state to ffff88020103d800
>[  512.273078] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f55af840 state to ffff88020103d800
>[  512.273079] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8801f55af180 state to ffff88020103d800
>[  512.273081] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8801f55af000 state to ffff88020103d800
>[  512.273082] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8801f55aff00 state to ffff88020103d800
>[  512.273083] [drm:drm_atomic_commit] commiting ffff88020103d800
>[  512.273088] [drm:intel_power_well_enable] enabling display
>[  512.273089] [drm:hsw_set_power_well] Enabling power well
>[  512.275157] [drm:intel_power_well_enable] enabling always-on
>[  512.275167] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  512.275168] [drm:intel_enable_shared_dpll] enabling SPLL
>[  512.276057] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  512.276121] [drm:intel_enable_pipe] enabling pipe B
>[  512.276135] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  512.342975] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  512.342979] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  512.342980] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  512.342982] [drm:check_crtc_state] [CRTC:25]
>[  512.342994] [drm:check_shared_dpll_state] WRPLL 1
>[  512.342995] [drm:check_shared_dpll_state] WRPLL 2
>[  512.342995] [drm:check_shared_dpll_state] SPLL
>[  512.342997] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88020103d800
>[  512.343001] [drm:drm_atomic_state_free] Freeing atomic state ffff88020103d800
>[  512.343028] [drm:drm_mode_setcrtc] [CRTC:25]
>[  512.343030] [drm:drm_atomic_state_init] Allocated atomic state ffff88020103d800
>[  512.343032] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5326400 state to ffff88020103d800
>[  512.343033] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f55af240 state to ffff88020103d800
>[  512.343034] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f5326400
>[  512.343035] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55af240 to [NOCRTC]
>[  512.343036] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f55af240
>[  512.343037] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103d800
>[  512.343038] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c909b1c0 state to ffff88020103d800
>[  512.343039] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c909b1c0 to [NOCRTC]
>[  512.343040] [drm:drm_atomic_check_only] checking ffff88020103d800
>[  512.343041] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  512.343042] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  512.343043] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  512.343044] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  512.343045] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  512.343046] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  512.343047] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103d800
>[  512.343048] [drm:drm_atomic_connectors_for_crtc] State ffff88020103d800 has 0 connectors for [CRTC:25]
>[  512.343051] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  512.343052] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  512.343054] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f55af900 state to ffff88020103d800
>[  512.343055] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f55af540 state to ffff88020103d800
>[  512.343057] [drm:drm_atomic_commit] commiting ffff88020103d800
>[  512.359668] [drm:intel_disable_pipe] disabling pipe B
>[  512.393996] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  512.393999] [drm:intel_disable_shared_dpll] disabling SPLL
>[  512.394007] [drm:intel_power_well_disable] disabling display
>[  512.394008] [drm:hsw_set_power_well] Requesting to disable the power well
>[  512.394009] [drm:intel_power_well_disable] disabling always-on
>[  512.394011] [drm:intel_power_well_enable] enabling display
>[  512.394012] [drm:hsw_set_power_well] Enabling power well
>[  512.396081] [drm:intel_power_well_disable] disabling display
>[  512.396085] [drm:hsw_set_power_well] Requesting to disable the power well
>[  512.396090] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  512.396092] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  512.396093] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  512.396096] [drm:check_crtc_state] [CRTC:25]
>[  512.396098] [drm:check_shared_dpll_state] WRPLL 1
>[  512.396099] [drm:check_shared_dpll_state] WRPLL 2
>[  512.396100] [drm:check_shared_dpll_state] SPLL
>[  512.396102] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88020103d800
>[  512.396104] [drm:drm_atomic_state_free] Freeing atomic state ffff88020103d800
>[  512.396132] [drm:drm_mode_setcrtc] [CRTC:25]
>[  512.396135] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  512.396137] [drm:drm_atomic_state_init] Allocated atomic state ffff880210d7b400
>[  512.396139] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5491c00 state to ffff880210d7b400
>[  512.396141] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f5fde900 state to ffff880210d7b400
>[  512.396142] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f5491c00
>[  512.396143] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f5fde900 to [CRTC:25]
>[  512.396144] [drm:drm_atomic_set_fb_for_plane] Set [FB:49] for plane state ffff8801f5fde900
>[  512.396146] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800d3bbaee0 state to ffff880210d7b400
>[  512.396147] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b400
>[  512.396148] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800d3bbaee0 to [CRTC:25]
>[  512.396149] [drm:drm_atomic_check_only] checking ffff880210d7b400
>[  512.396150] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  512.396151] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  512.396152] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  512.396153] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  512.396154] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  512.396155] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  512.396156] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b400
>[  512.396157] [drm:drm_atomic_connectors_for_crtc] State ffff880210d7b400 has 1 connectors for [CRTC:25]
>[  512.396158] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b400
>[  512.396160] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  512.396160] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  512.396162] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  512.396163] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  512.396165] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff8801f5491c00 for pipe B
>[  512.396166] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  512.396166] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  512.396168] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  512.396169] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  512.396170] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  512.396170] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  512.396171] [drm:intel_dump_pipe_config] requested mode:
>[  512.396173] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  512.396173] [drm:intel_dump_pipe_config] adjusted mode:
>[  512.396175] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  512.396176] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  512.396177] [drm:intel_dump_pipe_config] port clock: 270000
>[  512.396177] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  512.396178] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  512.396179] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  512.396180] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  512.396181] [drm:intel_dump_pipe_config] ips: 0
>[  512.396181] [drm:intel_dump_pipe_config] double wide: 0
>[  512.396182] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  512.396183] [drm:intel_dump_pipe_config] planes on this crtc
>[  512.396184] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  512.396185] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  512.396186] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  512.396188] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff8801f5493800 state to ffff880210d7b400
>[  512.396189] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff8801f5493400 state to ffff880210d7b400
>[  512.396191] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 49
>[  512.396192] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  512.396194] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8801f5fde540 state to ffff880210d7b400
>[  512.396195] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8801f5fde6c0 state to ffff880210d7b400
>[  512.396196] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8801f5fde9c0 state to ffff880210d7b400
>[  512.396199] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f5fde480 state to ffff880210d7b400
>[  512.396200] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f5fdec00 state to ffff880210d7b400
>[  512.396201] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8801f5fde0c0 state to ffff880210d7b400
>[  512.396202] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8801f5fde600 state to ffff880210d7b400
>[  512.396204] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8801f5fde840 state to ffff880210d7b400
>[  512.396205] [drm:drm_atomic_commit] commiting ffff880210d7b400
>[  512.396210] [drm:intel_power_well_enable] enabling display
>[  512.396211] [drm:hsw_set_power_well] Enabling power well
>[  512.398252] [drm:intel_power_well_enable] enabling always-on
>[  512.398262] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  512.398263] [drm:intel_enable_shared_dpll] enabling SPLL
>[  512.399152] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  512.399223] [drm:intel_enable_pipe] enabling pipe B
>[  512.399237] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  512.467786] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  512.467790] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  512.467792] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  512.467793] [drm:check_crtc_state] [CRTC:25]
>[  512.467805] [drm:check_shared_dpll_state] WRPLL 1
>[  512.467806] [drm:check_shared_dpll_state] WRPLL 2
>[  512.467807] [drm:check_shared_dpll_state] SPLL
>[  512.467809] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880210d7b400
>[  512.467812] [drm:drm_atomic_state_free] Freeing atomic state ffff880210d7b400
>[  512.467839] [drm:drm_mode_setcrtc] [CRTC:25]
>[  512.467841] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bfbc00
>[  512.467844] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880025a41c00 state to ffff880026bfbc00
>[  512.467845] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8800c78d46c0 state to ffff880026bfbc00
>[  512.467846] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff880025a41c00
>[  512.467847] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800c78d46c0 to [NOCRTC]
>[  512.467848] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8800c78d46c0
>[  512.467849] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfbc00
>[  512.467851] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8801f442de60 state to ffff880026bfbc00
>[  512.467852] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f442de60 to [NOCRTC]
>[  512.467852] [drm:drm_atomic_check_only] checking ffff880026bfbc00
>[  512.467854] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  512.467855] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  512.467856] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  512.467857] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  512.467857] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  512.467858] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  512.467859] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfbc00
>[  512.467860] [drm:drm_atomic_connectors_for_crtc] State ffff880026bfbc00 has 0 connectors for [CRTC:25]
>[  512.467863] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  512.467864] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  512.467866] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8800c78d4cc0 state to ffff880026bfbc00
>[  512.467867] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8800c78d4240 state to ffff880026bfbc00
>[  512.467869] [drm:drm_atomic_commit] commiting ffff880026bfbc00
>[  512.484453] [drm:intel_disable_pipe] disabling pipe B
>[  512.519582] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  512.519585] [drm:intel_disable_shared_dpll] disabling SPLL
>[  512.519593] [drm:intel_power_well_disable] disabling display
>[  512.519595] [drm:hsw_set_power_well] Requesting to disable the power well
>[  512.519596] [drm:intel_power_well_disable] disabling always-on
>[  512.519597] [drm:intel_power_well_enable] enabling display
>[  512.519598] [drm:hsw_set_power_well] Enabling power well
>[  512.520927] [drm:intel_power_well_disable] disabling display
>[  512.520931] [drm:hsw_set_power_well] Requesting to disable the power well
>[  512.520937] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  512.520939] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  512.520941] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  512.520944] [drm:check_crtc_state] [CRTC:25]
>[  512.520946] [drm:check_shared_dpll_state] WRPLL 1
>[  512.520947] [drm:check_shared_dpll_state] WRPLL 2
>[  512.520948] [drm:check_shared_dpll_state] SPLL
>[  512.520951] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bfbc00
>[  512.520953] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bfbc00
>[  512.520977] [drm:drm_mode_setcrtc] [CRTC:25]
>[  512.520981] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  512.520983] [drm:drm_atomic_state_init] Allocated atomic state ffff88020103da00
>[  512.520986] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5326000 state to ffff88020103da00
>[  512.520987] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f55afe40 state to ffff88020103da00
>[  512.520989] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f5326000
>[  512.520990] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55afe40 to [CRTC:25]
>[  512.520991] [drm:drm_atomic_set_fb_for_plane] Set [FB:51] for plane state ffff8801f55afe40
>[  512.520993] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c909bce0 state to ffff88020103da00
>[  512.520994] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103da00
>[  512.520996] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c909bce0 to [CRTC:25]
>[  512.520997] [drm:drm_atomic_check_only] checking ffff88020103da00
>[  512.520999] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  512.521000] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  512.521001] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  512.521003] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  512.521003] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  512.521004] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  512.521005] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103da00
>[  512.521006] [drm:drm_atomic_connectors_for_crtc] State ffff88020103da00 has 1 connectors for [CRTC:25]
>[  512.521008] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103da00
>[  512.521010] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  512.521011] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  512.521013] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  512.521014] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  512.521016] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff8801f5326000 for pipe B
>[  512.521017] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  512.521018] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  512.521020] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  512.521021] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  512.521023] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  512.521023] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  512.521025] [drm:intel_dump_pipe_config] requested mode:
>[  512.521027] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  512.521028] [drm:intel_dump_pipe_config] adjusted mode:
>[  512.521029] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  512.521031] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  512.521033] [drm:intel_dump_pipe_config] port clock: 270000
>[  512.521034] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  512.521035] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  512.521036] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  512.521037] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  512.521037] [drm:intel_dump_pipe_config] ips: 0
>[  512.521038] [drm:intel_dump_pipe_config] double wide: 0
>[  512.521039] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  512.521040] [drm:intel_dump_pipe_config] planes on this crtc
>[  512.521041] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  512.521042] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  512.521043] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  512.521045] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff8801f5324000 state to ffff88020103da00
>[  512.521046] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff8801f5327c00 state to ffff88020103da00
>[  512.521049] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 51
>[  512.521050] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  512.521051] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8801f55af780 state to ffff88020103da00
>[  512.521053] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8801f55af6c0 state to ffff88020103da00
>[  512.521054] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8801f55af300 state to ffff88020103da00
>[  512.521056] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f55afb40 state to ffff88020103da00
>[  512.521058] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f55af600 state to ffff88020103da00
>[  512.521060] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8801f55aff00 state to ffff88020103da00
>[  512.521061] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8801f55af000 state to ffff88020103da00
>[  512.521062] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8801f55af180 state to ffff88020103da00
>[  512.521064] [drm:drm_atomic_commit] commiting ffff88020103da00
>[  512.521069] [drm:intel_power_well_enable] enabling display
>[  512.521070] [drm:hsw_set_power_well] Enabling power well
>[  512.523139] [drm:intel_power_well_enable] enabling always-on
>[  512.523150] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  512.523151] [drm:intel_enable_shared_dpll] enabling SPLL
>[  512.524040] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  512.524105] [drm:intel_enable_pipe] enabling pipe B
>[  512.524118] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  512.593020] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  512.593024] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  512.593026] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  512.593027] [drm:check_crtc_state] [CRTC:25]
>[  512.593039] [drm:check_shared_dpll_state] WRPLL 1
>[  512.593040] [drm:check_shared_dpll_state] WRPLL 2
>[  512.593041] [drm:check_shared_dpll_state] SPLL
>[  512.593043] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88020103da00
>[  512.593046] [drm:drm_atomic_state_free] Freeing atomic state ffff88020103da00
>[  512.593073] [drm:drm_mode_setcrtc] [CRTC:25]
>[  512.593074] [drm:drm_atomic_state_init] Allocated atomic state ffff88020103da00
>[  512.593077] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5324400 state to ffff88020103da00
>[  512.593078] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f55af540 state to ffff88020103da00
>[  512.593079] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f5324400
>[  512.593080] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55af540 to [NOCRTC]
>[  512.593081] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f55af540
>[  512.593083] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103da00
>[  512.593084] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c909bc00 state to ffff88020103da00
>[  512.593085] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c909bc00 to [NOCRTC]
>[  512.593086] [drm:drm_atomic_check_only] checking ffff88020103da00
>[  512.593087] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  512.593088] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  512.593089] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  512.593090] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  512.593091] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  512.593092] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  512.593093] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103da00
>[  512.593095] [drm:drm_atomic_connectors_for_crtc] State ffff88020103da00 has 0 connectors for [CRTC:25]
>[  512.593098] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  512.593099] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  512.593101] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f55af900 state to ffff88020103da00
>[  512.593102] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f55af240 state to ffff88020103da00
>[  512.593104] [drm:drm_atomic_commit] commiting ffff88020103da00
>[  512.609713] [drm:intel_disable_pipe] disabling pipe B
>[  512.643911] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  512.643914] [drm:intel_disable_shared_dpll] disabling SPLL
>[  512.643922] [drm:intel_power_well_disable] disabling display
>[  512.643924] [drm:hsw_set_power_well] Requesting to disable the power well
>[  512.643925] [drm:intel_power_well_disable] disabling always-on
>[  512.643926] [drm:intel_power_well_enable] enabling display
>[  512.643927] [drm:hsw_set_power_well] Enabling power well
>[  512.645996] [drm:intel_power_well_disable] disabling display
>[  512.645999] [drm:hsw_set_power_well] Requesting to disable the power well
>[  512.646005] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  512.646007] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  512.646008] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  512.646011] [drm:check_crtc_state] [CRTC:25]
>[  512.646012] [drm:check_shared_dpll_state] WRPLL 1
>[  512.646013] [drm:check_shared_dpll_state] WRPLL 2
>[  512.646014] [drm:check_shared_dpll_state] SPLL
>[  512.646016] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88020103da00
>[  512.646019] [drm:drm_atomic_state_free] Freeing atomic state ffff88020103da00
>[  512.646047] [drm:drm_mode_setcrtc] [CRTC:25]
>[  512.646050] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  512.646052] [drm:drm_atomic_state_init] Allocated atomic state ffff880210d7b800
>[  512.646054] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5490800 state to ffff880210d7b800
>[  512.646056] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f5fdecc0 state to ffff880210d7b800
>[  512.646057] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f5490800
>[  512.646058] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f5fdecc0 to [CRTC:25]
>[  512.646059] [drm:drm_atomic_set_fb_for_plane] Set [FB:49] for plane state ffff8801f5fdecc0
>[  512.646060] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800d3bbaec0 state to ffff880210d7b800
>[  512.646061] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b800
>[  512.646062] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800d3bbaec0 to [CRTC:25]
>[  512.646063] [drm:drm_atomic_check_only] checking ffff880210d7b800
>[  512.646065] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  512.646065] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  512.646066] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  512.646068] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  512.646069] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  512.646069] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  512.646070] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b800
>[  512.646072] [drm:drm_atomic_connectors_for_crtc] State ffff880210d7b800 has 1 connectors for [CRTC:25]
>[  512.646073] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b800
>[  512.646075] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  512.646075] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  512.646077] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  512.646078] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  512.646080] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff8801f5490800 for pipe B
>[  512.646081] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  512.646081] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  512.646082] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  512.646084] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  512.646085] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  512.646085] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  512.646086] [drm:intel_dump_pipe_config] requested mode:
>[  512.646087] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  512.646088] [drm:intel_dump_pipe_config] adjusted mode:
>[  512.646089] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  512.646091] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  512.646092] [drm:intel_dump_pipe_config] port clock: 270000
>[  512.646092] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  512.646093] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  512.646094] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  512.646095] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  512.646096] [drm:intel_dump_pipe_config] ips: 0
>[  512.646096] [drm:intel_dump_pipe_config] double wide: 0
>[  512.646097] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  512.646098] [drm:intel_dump_pipe_config] planes on this crtc
>[  512.646099] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  512.646100] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  512.646101] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  512.646103] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff8801f5493400 state to ffff880210d7b800
>[  512.646105] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff8801f5493800 state to ffff880210d7b800
>[  512.646106] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 49
>[  512.646107] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  512.646109] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8801f5fde840 state to ffff880210d7b800
>[  512.646110] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8801f5fde600 state to ffff880210d7b800
>[  512.646112] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8801f5fde0c0 state to ffff880210d7b800
>[  512.646114] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f5fde9c0 state to ffff880210d7b800
>[  512.646115] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f5fde6c0 state to ffff880210d7b800
>[  512.646117] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8801f5fde540 state to ffff880210d7b800
>[  512.646118] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8801f5fdec00 state to ffff880210d7b800
>[  512.646119] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8801f5fde480 state to ffff880210d7b800
>[  512.646120] [drm:drm_atomic_commit] commiting ffff880210d7b800
>[  512.646125] [drm:intel_power_well_enable] enabling display
>[  512.646126] [drm:hsw_set_power_well] Enabling power well
>[  512.648194] [drm:intel_power_well_enable] enabling always-on
>[  512.648205] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  512.648206] [drm:intel_enable_shared_dpll] enabling SPLL
>[  512.649095] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  512.649160] [drm:intel_enable_pipe] enabling pipe B
>[  512.649175] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  512.716040] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  512.716045] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  512.716046] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  512.716048] [drm:check_crtc_state] [CRTC:25]
>[  512.716059] [drm:check_shared_dpll_state] WRPLL 1
>[  512.716060] [drm:check_shared_dpll_state] WRPLL 2
>[  512.716061] [drm:check_shared_dpll_state] SPLL
>[  512.716063] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880210d7b800
>[  512.716066] [drm:drm_atomic_state_free] Freeing atomic state ffff880210d7b800
>[  512.716093] [drm:drm_mode_setcrtc] [CRTC:25]
>[  512.716095] [drm:drm_atomic_state_init] Allocated atomic state ffff880210d7b800
>[  512.716097] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5491c00 state to ffff880210d7b800
>[  512.716098] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f5fde900 state to ffff880210d7b800
>[  512.716099] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f5491c00
>[  512.716100] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f5fde900 to [NOCRTC]
>[  512.716101] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f5fde900
>[  512.716102] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b800
>[  512.716104] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800d3bbae80 state to ffff880210d7b800
>[  512.716104] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800d3bbae80 to [NOCRTC]
>[  512.716105] [drm:drm_atomic_check_only] checking ffff880210d7b800
>[  512.716107] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  512.716108] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  512.716109] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  512.716109] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  512.716110] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  512.716111] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  512.716112] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b800
>[  512.716113] [drm:drm_atomic_connectors_for_crtc] State ffff880210d7b800 has 0 connectors for [CRTC:25]
>[  512.716116] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  512.716117] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  512.716119] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f5fde3c0 state to ffff880210d7b800
>[  512.716120] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f5fded80 state to ffff880210d7b800
>[  512.716122] [drm:drm_atomic_commit] commiting ffff880210d7b800
>[  512.732710] [drm:intel_disable_pipe] disabling pipe B
>[  512.767479] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  512.767482] [drm:intel_disable_shared_dpll] disabling SPLL
>[  512.767490] [drm:intel_power_well_disable] disabling display
>[  512.767491] [drm:hsw_set_power_well] Requesting to disable the power well
>[  512.767492] [drm:intel_power_well_disable] disabling always-on
>[  512.767494] [drm:intel_power_well_enable] enabling display
>[  512.767495] [drm:hsw_set_power_well] Enabling power well
>[  512.768905] [drm:intel_power_well_disable] disabling display
>[  512.768908] [drm:hsw_set_power_well] Requesting to disable the power well
>[  512.768914] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  512.768917] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  512.768919] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  512.768922] [drm:check_crtc_state] [CRTC:25]
>[  512.768923] [drm:check_shared_dpll_state] WRPLL 1
>[  512.768925] [drm:check_shared_dpll_state] WRPLL 2
>[  512.768926] [drm:check_shared_dpll_state] SPLL
>[  512.768928] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880210d7b800
>[  512.768931] [drm:drm_atomic_state_free] Freeing atomic state ffff880210d7b800
>[  512.768956] [drm:drm_mode_setcrtc] [CRTC:25]
>[  512.768959] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  512.768961] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bf3c00
>[  512.768964] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880215be4400 state to ffff880026bf3c00
>[  512.768966] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff880026901cc0 state to ffff880026bf3c00
>[  512.768968] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff880215be4400
>[  512.768969] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880026901cc0 to [CRTC:25]
>[  512.768970] [drm:drm_atomic_set_fb_for_plane] Set [FB:51] for plane state ffff880026901cc0
>[  512.768972] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c01325a0 state to ffff880026bf3c00
>[  512.768973] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3c00
>[  512.768974] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c01325a0 to [CRTC:25]
>[  512.768975] [drm:drm_atomic_check_only] checking ffff880026bf3c00
>[  512.768977] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  512.768978] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  512.768979] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  512.768981] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  512.768982] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  512.768983] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  512.768984] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3c00
>[  512.768985] [drm:drm_atomic_connectors_for_crtc] State ffff880026bf3c00 has 1 connectors for [CRTC:25]
>[  512.768987] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3c00
>[  512.768989] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  512.768990] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  512.768991] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  512.768993] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  512.768995] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff880215be4400 for pipe B
>[  512.768996] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  512.768997] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  512.768998] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  512.769000] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  512.769001] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  512.769002] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  512.769003] [drm:intel_dump_pipe_config] requested mode:
>[  512.769005] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  512.769006] [drm:intel_dump_pipe_config] adjusted mode:
>[  512.769008] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  512.769009] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  512.769010] [drm:intel_dump_pipe_config] port clock: 270000
>[  512.769011] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  512.769013] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  512.769014] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  512.769015] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  512.769016] [drm:intel_dump_pipe_config] ips: 0
>[  512.769017] [drm:intel_dump_pipe_config] double wide: 0
>[  512.769018] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  512.769019] [drm:intel_dump_pipe_config] planes on this crtc
>[  512.769020] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  512.769021] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  512.769022] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  512.769024] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff880215be6400 state to ffff880026bf3c00
>[  512.769026] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff880215be5c00 state to ffff880026bf3c00
>[  512.769027] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 51
>[  512.769028] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  512.769030] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff880026901480 state to ffff880026bf3c00
>[  512.769032] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff880026901900 state to ffff880026bf3c00
>[  512.769033] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff880026901840 state to ffff880026bf3c00
>[  512.769035] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff880026901780 state to ffff880026bf3c00
>[  512.769037] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8800269016c0 state to ffff880026bf3c00
>[  512.769039] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8800269019c0 state to ffff880026bf3c00
>[  512.769040] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff880026901600 state to ffff880026bf3c00
>[  512.769041] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff880026901300 state to ffff880026bf3c00
>[  512.769042] [drm:drm_atomic_commit] commiting ffff880026bf3c00
>[  512.769048] [drm:intel_power_well_enable] enabling display
>[  512.769050] [drm:hsw_set_power_well] Enabling power well
>[  512.771116] [drm:intel_power_well_enable] enabling always-on
>[  512.771127] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  512.771128] [drm:intel_enable_shared_dpll] enabling SPLL
>[  512.772017] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  512.772081] [drm:intel_enable_pipe] enabling pipe B
>[  512.772095] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  512.838963] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  512.838967] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  512.838969] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  512.838970] [drm:check_crtc_state] [CRTC:25]
>[  512.838982] [drm:check_shared_dpll_state] WRPLL 1
>[  512.838983] [drm:check_shared_dpll_state] WRPLL 2
>[  512.838984] [drm:check_shared_dpll_state] SPLL
>[  512.838985] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bf3c00
>[  512.838989] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bf3c00
>[  512.839017] [drm:drm_mode_setcrtc] [CRTC:25]
>[  512.839019] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bf3c00
>[  512.839021] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880215be4000 state to ffff880026bf3c00
>[  512.839022] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff880026901d80 state to ffff880026bf3c00
>[  512.839023] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff880215be4000
>[  512.839024] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880026901d80 to [NOCRTC]
>[  512.839025] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880026901d80
>[  512.839026] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3c00
>[  512.839027] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c0132580 state to ffff880026bf3c00
>[  512.839028] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c0132580 to [NOCRTC]
>[  512.839029] [drm:drm_atomic_check_only] checking ffff880026bf3c00
>[  512.839031] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  512.839031] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  512.839032] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  512.839033] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  512.839034] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  512.839035] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  512.839036] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3c00
>[  512.839037] [drm:drm_atomic_connectors_for_crtc] State ffff880026bf3c00 has 0 connectors for [CRTC:25]
>[  512.839040] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  512.839041] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  512.839043] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff880026901540 state to ffff880026bf3c00
>[  512.839045] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8800d3b00240 state to ffff880026bf3c00
>[  512.839047] [drm:drm_atomic_commit] commiting ffff880026bf3c00
>[  512.855629] [drm:intel_disable_pipe] disabling pipe B
>[  512.859003] [drm:intel_print_rc6_info] Enabling RC6 states: RC6 on
>[  512.862877] [drm:gen6_enable_rps] Overclocking supported. Max: 1100MHz, Overclock max: 1100MHz
>[  512.889378] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  512.889381] [drm:intel_disable_shared_dpll] disabling SPLL
>[  512.889389] [drm:intel_power_well_disable] disabling display
>[  512.889391] [drm:hsw_set_power_well] Requesting to disable the power well
>[  512.889392] [drm:intel_power_well_disable] disabling always-on
>[  512.889393] [drm:intel_power_well_enable] enabling display
>[  512.889394] [drm:hsw_set_power_well] Enabling power well
>[  512.891463] [drm:intel_power_well_disable] disabling display
>[  512.891467] [drm:hsw_set_power_well] Requesting to disable the power well
>[  512.891472] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  512.891474] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  512.891475] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  512.891478] [drm:check_crtc_state] [CRTC:25]
>[  512.891480] [drm:check_shared_dpll_state] WRPLL 1
>[  512.891481] [drm:check_shared_dpll_state] WRPLL 2
>[  512.891482] [drm:check_shared_dpll_state] SPLL
>[  512.891484] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bf3c00
>[  512.891486] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bf3c00
>[  512.891513] [drm:drm_mode_setcrtc] [CRTC:25]
>[  512.891516] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  512.891518] [drm:drm_atomic_state_init] Allocated atomic state ffff880210d7b000
>[  512.891520] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5492c00 state to ffff880210d7b000
>[  512.891522] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f5fdea80 state to ffff880210d7b000
>[  512.891523] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f5492c00
>[  512.891524] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f5fdea80 to [CRTC:25]
>[  512.891525] [drm:drm_atomic_set_fb_for_plane] Set [FB:49] for plane state ffff8801f5fdea80
>[  512.891526] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800d3bbae40 state to ffff880210d7b000
>[  512.891527] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b000
>[  512.891528] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800d3bbae40 to [CRTC:25]
>[  512.891529] [drm:drm_atomic_check_only] checking ffff880210d7b000
>[  512.891531] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  512.891531] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  512.891533] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  512.891534] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  512.891535] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  512.891536] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  512.891536] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b000
>[  512.891538] [drm:drm_atomic_connectors_for_crtc] State ffff880210d7b000 has 1 connectors for [CRTC:25]
>[  512.891539] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b000
>[  512.891540] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  512.891541] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  512.891543] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  512.891544] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  512.891546] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff8801f5492c00 for pipe B
>[  512.891546] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  512.891547] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  512.891548] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  512.891550] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  512.891551] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  512.891551] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  512.891552] [drm:intel_dump_pipe_config] requested mode:
>[  512.891554] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  512.891554] [drm:intel_dump_pipe_config] adjusted mode:
>[  512.891556] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  512.891557] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  512.891558] [drm:intel_dump_pipe_config] port clock: 270000
>[  512.891558] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  512.891559] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  512.891560] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  512.891561] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  512.891562] [drm:intel_dump_pipe_config] ips: 0
>[  512.891563] [drm:intel_dump_pipe_config] double wide: 0
>[  512.891564] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  512.891564] [drm:intel_dump_pipe_config] planes on this crtc
>[  512.891566] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  512.891567] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  512.891568] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  512.891569] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff8801f5490c00 state to ffff880210d7b000
>[  512.891571] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff8801f5493800 state to ffff880210d7b000
>[  512.891573] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 49
>[  512.891574] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  512.891575] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8801f5fdee40 state to ffff880210d7b000
>[  512.891576] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8801f5fdef00 state to ffff880210d7b000
>[  512.891578] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8801f5fdeb40 state to ffff880210d7b000
>[  512.891580] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f5fde780 state to ffff880210d7b000
>[  512.891581] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f5fde480 state to ffff880210d7b000
>[  512.891583] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8801f5fdec00 state to ffff880210d7b000
>[  512.891584] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8801f5fde540 state to ffff880210d7b000
>[  512.891585] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8801f5fded80 state to ffff880210d7b000
>[  512.891587] [drm:drm_atomic_commit] commiting ffff880210d7b000
>[  512.891591] [drm:intel_power_well_enable] enabling display
>[  512.891592] [drm:hsw_set_power_well] Enabling power well
>[  512.892899] [drm:intel_power_well_enable] enabling always-on
>[  512.892909] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  512.892910] [drm:intel_enable_shared_dpll] enabling SPLL
>[  512.893800] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  512.893864] [drm:intel_enable_pipe] enabling pipe B
>[  512.893878] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  512.960712] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  512.960716] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  512.960718] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  512.960719] [drm:check_crtc_state] [CRTC:25]
>[  512.960731] [drm:check_shared_dpll_state] WRPLL 1
>[  512.960732] [drm:check_shared_dpll_state] WRPLL 2
>[  512.960733] [drm:check_shared_dpll_state] SPLL
>[  512.960734] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880210d7b000
>[  512.960738] [drm:drm_atomic_state_free] Freeing atomic state ffff880210d7b000
>[  512.960765] [drm:drm_mode_setcrtc] [CRTC:25]
>[  512.960767] [drm:drm_atomic_state_init] Allocated atomic state ffff88020103c400
>[  512.960769] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5326400 state to ffff88020103c400
>[  512.960771] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f55afa80 state to ffff88020103c400
>[  512.960772] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f5326400
>[  512.960773] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55afa80 to [NOCRTC]
>[  512.960773] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f55afa80
>[  512.960775] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103c400
>[  512.960776] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c909bbc0 state to ffff88020103c400
>[  512.960777] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c909bbc0 to [NOCRTC]
>[  512.960778] [drm:drm_atomic_check_only] checking ffff88020103c400
>[  512.960779] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  512.960780] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  512.960781] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  512.960782] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  512.960782] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  512.960783] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  512.960784] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103c400
>[  512.960786] [drm:drm_atomic_connectors_for_crtc] State ffff88020103c400 has 0 connectors for [CRTC:25]
>[  512.960788] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  512.960789] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  512.960791] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f55af0c0 state to ffff88020103c400
>[  512.960792] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f55af3c0 state to ffff88020103c400
>[  512.960794] [drm:drm_atomic_commit] commiting ffff88020103c400
>[  512.977409] [drm:intel_disable_pipe] disabling pipe B
>[  513.011872] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  513.011875] [drm:intel_disable_shared_dpll] disabling SPLL
>[  513.011884] [drm:intel_power_well_disable] disabling display
>[  513.011885] [drm:hsw_set_power_well] Requesting to disable the power well
>[  513.011886] [drm:intel_power_well_disable] disabling always-on
>[  513.011894] [drm:intel_runtime_suspend] Suspending device
>[  513.011994] [drm:hsw_enable_pc8] Enabling package C8+
>[  513.026492] [drm:intel_runtime_suspend] Device suspended
>[  513.032886] [drm:intel_runtime_resume] Resuming device
>[  513.034953] [drm:hsw_disable_pc8] Disabling package C8+
>[  513.038892] [drm:intel_update_cdclk] Current CD clock rate: 540000 kHz
>[  513.152120] [drm:intel_runtime_resume] Device resumed
>[  513.152124] [drm:intel_power_well_enable] enabling display
>[  513.152125] [drm:hsw_set_power_well] Enabling power well
>[  513.154196] [drm:intel_power_well_disable] disabling display
>[  513.154199] [drm:hsw_set_power_well] Requesting to disable the power well
>[  513.154204] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  513.154207] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  513.154208] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  513.154211] [drm:check_crtc_state] [CRTC:25]
>[  513.154212] [drm:check_shared_dpll_state] WRPLL 1
>[  513.154213] [drm:check_shared_dpll_state] WRPLL 2
>[  513.154214] [drm:check_shared_dpll_state] SPLL
>[  513.154216] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88020103c400
>[  513.154219] [drm:drm_atomic_state_free] Freeing atomic state ffff88020103c400
>[  513.154247] [drm:drm_mode_setcrtc] [CRTC:25]
>[  513.154250] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  513.154252] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bfb800
>[  513.154254] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880025a43400 state to ffff880026bfb800
>[  513.154255] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8800c78d4a80 state to ffff880026bfb800
>[  513.154257] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff880025a43400
>[  513.154258] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800c78d4a80 to [CRTC:25]
>[  513.154259] [drm:drm_atomic_set_fb_for_plane] Set [FB:51] for plane state ffff8800c78d4a80
>[  513.154260] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8801f442dca0 state to ffff880026bfb800
>[  513.154261] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfb800
>[  513.154262] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f442dca0 to [CRTC:25]
>[  513.154263] [drm:drm_atomic_check_only] checking ffff880026bfb800
>[  513.154265] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  513.154266] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  513.154267] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  513.154268] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  513.154269] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  513.154270] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  513.154271] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfb800
>[  513.154272] [drm:drm_atomic_connectors_for_crtc] State ffff880026bfb800 has 1 connectors for [CRTC:25]
>[  513.154273] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfb800
>[  513.154275] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  513.154276] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  513.154277] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  513.154278] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  513.154279] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff880025a43400 for pipe B
>[  513.154280] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  513.154281] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  513.154282] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  513.154283] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  513.154284] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  513.154285] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  513.154286] [drm:intel_dump_pipe_config] requested mode:
>[  513.154288] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  513.154288] [drm:intel_dump_pipe_config] adjusted mode:
>[  513.154290] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  513.154291] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  513.154292] [drm:intel_dump_pipe_config] port clock: 270000
>[  513.154292] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  513.154293] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  513.154294] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  513.154295] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  513.154296] [drm:intel_dump_pipe_config] ips: 0
>[  513.154297] [drm:intel_dump_pipe_config] double wide: 0
>[  513.154298] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  513.154299] [drm:intel_dump_pipe_config] planes on this crtc
>[  513.154300] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  513.154301] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  513.154302] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  513.154303] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff880025a43000 state to ffff880026bfb800
>[  513.154305] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff880025a41000 state to ffff880026bfb800
>[  513.154307] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 51
>[  513.154308] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  513.154309] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8800c78d4180 state to ffff880026bfb800
>[  513.154310] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8800c78d4d80 state to ffff880026bfb800
>[  513.154312] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8800c78d4900 state to ffff880026bfb800
>[  513.154314] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8800c78d4300 state to ffff880026bfb800
>[  513.154315] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8800c78d4000 state to ffff880026bfb800
>[  513.154317] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8800c78d49c0 state to ffff880026bfb800
>[  513.154318] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8800c78d4780 state to ffff880026bfb800
>[  513.154319] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8800c78d4b40 state to ffff880026bfb800
>[  513.154320] [drm:drm_atomic_commit] commiting ffff880026bfb800
>[  513.154325] [drm:intel_power_well_enable] enabling display
>[  513.154326] [drm:hsw_set_power_well] Enabling power well
>[  513.156395] [drm:intel_power_well_enable] enabling always-on
>[  513.156405] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  513.156406] [drm:intel_enable_shared_dpll] enabling SPLL
>[  513.157295] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  513.157360] [drm:intel_enable_pipe] enabling pipe B
>[  513.157374] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  513.224240] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  513.224244] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  513.224245] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  513.224247] [drm:check_crtc_state] [CRTC:25]
>[  513.224258] [drm:check_shared_dpll_state] WRPLL 1
>[  513.224259] [drm:check_shared_dpll_state] WRPLL 2
>[  513.224260] [drm:check_shared_dpll_state] SPLL
>[  513.224262] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bfb800
>[  513.224266] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bfb800
>[  513.224293] [drm:drm_mode_setcrtc] [CRTC:25]
>[  513.224294] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bfb800
>[  513.224297] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880025a42000 state to ffff880026bfb800
>[  513.224298] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8800c78d4c00 state to ffff880026bfb800
>[  513.224299] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff880025a42000
>[  513.224300] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800c78d4c00 to [NOCRTC]
>[  513.224301] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8800c78d4c00
>[  513.224302] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfb800
>[  513.224304] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8801f442d980 state to ffff880026bfb800
>[  513.224304] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f442d980 to [NOCRTC]
>[  513.224305] [drm:drm_atomic_check_only] checking ffff880026bfb800
>[  513.224307] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  513.224307] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  513.224309] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  513.224309] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  513.224310] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  513.224311] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  513.224312] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfb800
>[  513.224313] [drm:drm_atomic_connectors_for_crtc] State ffff880026bfb800 has 0 connectors for [CRTC:25]
>[  513.224316] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  513.224317] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  513.224319] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8800c78d4480 state to ffff880026bfb800
>[  513.224320] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8800c78d4e40 state to ffff880026bfb800
>[  513.224322] [drm:drm_atomic_commit] commiting ffff880026bfb800
>[  513.240909] [drm:intel_disable_pipe] disabling pipe B
>[  513.275836] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  513.275839] [drm:intel_disable_shared_dpll] disabling SPLL
>[  513.275847] [drm:intel_power_well_disable] disabling display
>[  513.275849] [drm:hsw_set_power_well] Requesting to disable the power well
>[  513.275849] [drm:intel_power_well_disable] disabling always-on
>[  513.275851] [drm:intel_power_well_enable] enabling display
>[  513.275852] [drm:hsw_set_power_well] Enabling power well
>[  513.277921] [drm:intel_power_well_disable] disabling display
>[  513.277925] [drm:hsw_set_power_well] Requesting to disable the power well
>[  513.277930] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  513.277932] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  513.277934] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  513.277936] [drm:check_crtc_state] [CRTC:25]
>[  513.277938] [drm:check_shared_dpll_state] WRPLL 1
>[  513.277939] [drm:check_shared_dpll_state] WRPLL 2
>[  513.277940] [drm:check_shared_dpll_state] SPLL
>[  513.277942] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bfb800
>[  513.277944] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bfb800
>[  513.277972] [drm:drm_mode_setcrtc] [CRTC:25]
>[  513.277976] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  513.277978] [drm:drm_atomic_state_init] Allocated atomic state ffff88020103d400
>[  513.277980] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5327800 state to ffff88020103d400
>[  513.277981] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f55af840 state to ffff88020103d400
>[  513.277983] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f5327800
>[  513.277984] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55af840 to [CRTC:25]
>[  513.277985] [drm:drm_atomic_set_fb_for_plane] Set [FB:49] for plane state ffff8801f55af840
>[  513.277986] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c909be00 state to ffff88020103d400
>[  513.277987] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103d400
>[  513.277988] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c909be00 to [CRTC:25]
>[  513.277989] [drm:drm_atomic_check_only] checking ffff88020103d400
>[  513.277991] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  513.277991] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  513.277992] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  513.277994] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  513.277994] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  513.277995] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  513.277996] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103d400
>[  513.277998] [drm:drm_atomic_connectors_for_crtc] State ffff88020103d400 has 1 connectors for [CRTC:25]
>[  513.277999] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103d400
>[  513.278000] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  513.278001] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  513.278003] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  513.278004] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  513.278005] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff8801f5327800 for pipe B
>[  513.278006] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  513.278007] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  513.278008] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  513.278009] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  513.278010] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  513.278011] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  513.278012] [drm:intel_dump_pipe_config] requested mode:
>[  513.278013] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  513.278014] [drm:intel_dump_pipe_config] adjusted mode:
>[  513.278015] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  513.278016] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  513.278017] [drm:intel_dump_pipe_config] port clock: 270000
>[  513.278018] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  513.278019] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  513.278020] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  513.278021] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  513.278021] [drm:intel_dump_pipe_config] ips: 0
>[  513.278022] [drm:intel_dump_pipe_config] double wide: 0
>[  513.278023] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  513.278024] [drm:intel_dump_pipe_config] planes on this crtc
>[  513.278025] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  513.278026] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  513.278027] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  513.278028] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff8801f5325000 state to ffff88020103d400
>[  513.278030] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff8801f5327c00 state to ffff88020103d400
>[  513.278032] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 49
>[  513.278033] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  513.278034] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8801f55afcc0 state to ffff88020103d400
>[  513.278036] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8801f55afc00 state to ffff88020103d400
>[  513.278037] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8801f55af3c0 state to ffff88020103d400
>[  513.278040] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f55af0c0 state to ffff88020103d400
>[  513.278041] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f55afa80 state to ffff88020103d400
>[  513.278042] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8801f55af180 state to ffff88020103d400
>[  513.278043] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8801f55af000 state to ffff88020103d400
>[  513.278045] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8801f55aff00 state to ffff88020103d400
>[  513.278046] [drm:drm_atomic_commit] commiting ffff88020103d400
>[  513.278050] [drm:intel_power_well_enable] enabling display
>[  513.278052] [drm:hsw_set_power_well] Enabling power well
>[  513.280118] [drm:intel_power_well_enable] enabling always-on
>[  513.280129] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  513.280130] [drm:intel_enable_shared_dpll] enabling SPLL
>[  513.281020] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  513.281084] [drm:intel_enable_pipe] enabling pipe B
>[  513.281099] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  513.347936] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  513.347941] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  513.347942] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  513.347943] [drm:check_crtc_state] [CRTC:25]
>[  513.347955] [drm:check_shared_dpll_state] WRPLL 1
>[  513.347956] [drm:check_shared_dpll_state] WRPLL 2
>[  513.347957] [drm:check_shared_dpll_state] SPLL
>[  513.347958] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88020103d400
>[  513.347962] [drm:drm_atomic_state_free] Freeing atomic state ffff88020103d400
>[  513.347989] [drm:drm_mode_setcrtc] [CRTC:25]
>[  513.347991] [drm:drm_atomic_state_init] Allocated atomic state ffff88020103d400
>[  513.347993] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5324400 state to ffff88020103d400
>[  513.347994] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f55af240 state to ffff88020103d400
>[  513.347995] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f5324400
>[  513.347996] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55af240 to [NOCRTC]
>[  513.347997] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f55af240
>[  513.347999] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103d400
>[  513.348000] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c909bfe0 state to ffff88020103d400
>[  513.348001] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c909bfe0 to [NOCRTC]
>[  513.348001] [drm:drm_atomic_check_only] checking ffff88020103d400
>[  513.348003] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  513.348004] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  513.348005] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  513.348005] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  513.348006] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  513.348007] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  513.348008] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103d400
>[  513.348009] [drm:drm_atomic_connectors_for_crtc] State ffff88020103d400 has 0 connectors for [CRTC:25]
>[  513.348012] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  513.348013] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  513.348015] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f55af900 state to ffff88020103d400
>[  513.348016] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f55af540 state to ffff88020103d400
>[  513.348018] [drm:drm_atomic_commit] commiting ffff88020103d400
>[  513.364631] [drm:intel_disable_pipe] disabling pipe B
>[  513.399422] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  513.399425] [drm:intel_disable_shared_dpll] disabling SPLL
>[  513.399434] [drm:intel_power_well_disable] disabling display
>[  513.399436] [drm:hsw_set_power_well] Requesting to disable the power well
>[  513.399436] [drm:intel_power_well_disable] disabling always-on
>[  513.399438] [drm:intel_power_well_enable] enabling display
>[  513.399439] [drm:hsw_set_power_well] Enabling power well
>[  513.400848] [drm:intel_power_well_disable] disabling display
>[  513.400852] [drm:hsw_set_power_well] Requesting to disable the power well
>[  513.400858] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  513.400861] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  513.400862] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  513.400866] [drm:check_crtc_state] [CRTC:25]
>[  513.400867] [drm:check_shared_dpll_state] WRPLL 1
>[  513.400869] [drm:check_shared_dpll_state] WRPLL 2
>[  513.400870] [drm:check_shared_dpll_state] SPLL
>[  513.400872] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88020103d400
>[  513.400875] [drm:drm_atomic_state_free] Freeing atomic state ffff88020103d400
>[  513.400899] [drm:drm_mode_setcrtc] [CRTC:25]
>[  513.400903] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  513.400906] [drm:drm_atomic_state_init] Allocated atomic state ffff880210d7b000
>[  513.400909] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5491c00 state to ffff880210d7b000
>[  513.400911] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f5fde3c0 state to ffff880210d7b000
>[  513.400913] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f5491c00
>[  513.400914] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f5fde3c0 to [CRTC:25]
>[  513.400916] [drm:drm_atomic_set_fb_for_plane] Set [FB:51] for plane state ffff8801f5fde3c0
>[  513.400917] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800d3bba000 state to ffff880210d7b000
>[  513.400919] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b000
>[  513.400920] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800d3bba000 to [CRTC:25]
>[  513.400922] [drm:drm_atomic_check_only] checking ffff880210d7b000
>[  513.400923] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  513.400924] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  513.400925] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  513.400927] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  513.400928] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  513.400929] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  513.400930] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b000
>[  513.400932] [drm:drm_atomic_connectors_for_crtc] State ffff880210d7b000 has 1 connectors for [CRTC:25]
>[  513.400933] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b000
>[  513.400936] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  513.400936] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  513.400938] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  513.400939] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  513.400941] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff8801f5491c00 for pipe B
>[  513.400941] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  513.400942] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  513.400944] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  513.400945] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  513.400947] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  513.400948] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  513.400949] [drm:intel_dump_pipe_config] requested mode:
>[  513.400951] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  513.400952] [drm:intel_dump_pipe_config] adjusted mode:
>[  513.400954] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  513.400956] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  513.400956] [drm:intel_dump_pipe_config] port clock: 270000
>[  513.400957] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  513.400958] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  513.400959] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  513.400960] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  513.400961] [drm:intel_dump_pipe_config] ips: 0
>[  513.400962] [drm:intel_dump_pipe_config] double wide: 0
>[  513.400963] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  513.400964] [drm:intel_dump_pipe_config] planes on this crtc
>[  513.400965] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  513.400966] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  513.400967] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  513.400969] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff8801f5493400 state to ffff880210d7b000
>[  513.400970] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff8801f5490800 state to ffff880210d7b000
>[  513.400972] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 51
>[  513.400973] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  513.400975] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8801f5fde0c0 state to ffff880210d7b000
>[  513.400976] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8801f5fde600 state to ffff880210d7b000
>[  513.400977] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8801f5fde840 state to ffff880210d7b000
>[  513.400980] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f5fde6c0 state to ffff880210d7b000
>[  513.400981] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f5fde9c0 state to ffff880210d7b000
>[  513.400983] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8801f5fdecc0 state to ffff880210d7b000
>[  513.400984] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8801f5fde000 state to ffff880210d7b000
>[  513.400985] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8801f5fded80 state to ffff880210d7b000
>[  513.400987] [drm:drm_atomic_commit] commiting ffff880210d7b000
>[  513.400992] [drm:intel_power_well_enable] enabling display
>[  513.400994] [drm:hsw_set_power_well] Enabling power well
>[  513.403060] [drm:intel_power_well_enable] enabling always-on
>[  513.403071] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  513.403072] [drm:intel_enable_shared_dpll] enabling SPLL
>[  513.403961] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  513.404025] [drm:intel_enable_pipe] enabling pipe B
>[  513.404039] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  513.470914] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  513.470918] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  513.470920] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  513.470921] [drm:check_crtc_state] [CRTC:25]
>[  513.470933] [drm:check_shared_dpll_state] WRPLL 1
>[  513.470934] [drm:check_shared_dpll_state] WRPLL 2
>[  513.470935] [drm:check_shared_dpll_state] SPLL
>[  513.470937] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880210d7b000
>[  513.470940] [drm:drm_atomic_state_free] Freeing atomic state ffff880210d7b000
>[  513.470968] [drm:drm_mode_setcrtc] [CRTC:25]
>[  513.470969] [drm:drm_atomic_state_init] Allocated atomic state ffff880210d7b000
>[  513.470972] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5493800 state to ffff880210d7b000
>[  513.470973] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f5fde540 state to ffff880210d7b000
>[  513.470974] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f5493800
>[  513.470975] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f5fde540 to [NOCRTC]
>[  513.470976] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f5fde540
>[  513.470977] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b000
>[  513.470979] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800d3bbaac0 state to ffff880210d7b000
>[  513.470979] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800d3bbaac0 to [NOCRTC]
>[  513.470980] [drm:drm_atomic_check_only] checking ffff880210d7b000
>[  513.470982] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  513.470982] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  513.470984] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  513.470984] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  513.470985] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  513.470986] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  513.470987] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b000
>[  513.470988] [drm:drm_atomic_connectors_for_crtc] State ffff880210d7b000 has 0 connectors for [CRTC:25]
>[  513.470991] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  513.470992] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  513.470994] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f5fdec00 state to ffff880210d7b000
>[  513.470995] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f5fdeb40 state to ffff880210d7b000
>[  513.470997] [drm:drm_atomic_commit] commiting ffff880210d7b000
>[  513.487581] [drm:intel_disable_pipe] disabling pipe B
>[  513.521901] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  513.521904] [drm:intel_disable_shared_dpll] disabling SPLL
>[  513.521912] [drm:intel_power_well_disable] disabling display
>[  513.521914] [drm:hsw_set_power_well] Requesting to disable the power well
>[  513.521914] [drm:intel_power_well_disable] disabling always-on
>[  513.521916] [drm:intel_power_well_enable] enabling display
>[  513.521917] [drm:hsw_set_power_well] Enabling power well
>[  513.523987] [drm:intel_power_well_disable] disabling display
>[  513.523991] [drm:hsw_set_power_well] Requesting to disable the power well
>[  513.523996] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  513.523998] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  513.523999] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  513.524002] [drm:check_crtc_state] [CRTC:25]
>[  513.524003] [drm:check_shared_dpll_state] WRPLL 1
>[  513.524004] [drm:check_shared_dpll_state] WRPLL 2
>[  513.524005] [drm:check_shared_dpll_state] SPLL
>[  513.524007] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880210d7b000
>[  513.524010] [drm:drm_atomic_state_free] Freeing atomic state ffff880210d7b000
>[  513.524038] [drm:drm_mode_setcrtc] [CRTC:25]
>[  513.524041] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  513.524043] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bfb800
>[  513.524045] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880025a42c00 state to ffff880026bfb800
>[  513.524047] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8800c78d40c0 state to ffff880026bfb800
>[  513.524048] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff880025a42c00
>[  513.524049] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800c78d40c0 to [CRTC:25]
>[  513.524050] [drm:drm_atomic_set_fb_for_plane] Set [FB:49] for plane state ffff8800c78d40c0
>[  513.524052] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8801f442dfc0 state to ffff880026bfb800
>[  513.524053] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfb800
>[  513.524054] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f442dfc0 to [CRTC:25]
>[  513.524055] [drm:drm_atomic_check_only] checking ffff880026bfb800
>[  513.524056] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  513.524057] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  513.524058] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  513.524060] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  513.524060] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  513.524061] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  513.524062] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfb800
>[  513.524063] [drm:drm_atomic_connectors_for_crtc] State ffff880026bfb800 has 1 connectors for [CRTC:25]
>[  513.524065] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfb800
>[  513.524066] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  513.524067] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  513.524068] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  513.524069] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  513.524071] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff880025a42c00 for pipe B
>[  513.524072] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  513.524072] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  513.524074] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  513.524075] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  513.524076] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  513.524076] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  513.524077] [drm:intel_dump_pipe_config] requested mode:
>[  513.524079] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  513.524079] [drm:intel_dump_pipe_config] adjusted mode:
>[  513.524081] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  513.524082] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  513.524083] [drm:intel_dump_pipe_config] port clock: 270000
>[  513.524084] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  513.524084] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  513.524085] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  513.524086] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  513.524087] [drm:intel_dump_pipe_config] ips: 0
>[  513.524088] [drm:intel_dump_pipe_config] double wide: 0
>[  513.524089] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  513.524089] [drm:intel_dump_pipe_config] planes on this crtc
>[  513.524091] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  513.524092] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  513.524093] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  513.524094] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff880025a40800 state to ffff880026bfb800
>[  513.524095] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff880025a43c00 state to ffff880026bfb800
>[  513.524097] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 49
>[  513.524098] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  513.524100] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8800c78d4840 state to ffff880026bfb800
>[  513.524101] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8800c78d4b40 state to ffff880026bfb800
>[  513.524103] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8800c78d4780 state to ffff880026bfb800
>[  513.524105] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8800c78d49c0 state to ffff880026bfb800
>[  513.524106] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8800c78d4e40 state to ffff880026bfb800
>[  513.524108] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8800c78d4480 state to ffff880026bfb800
>[  513.524109] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8800c78d4c00 state to ffff880026bfb800
>[  513.524111] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8800c78d4900 state to ffff880026bfb800
>[  513.524112] [drm:drm_atomic_commit] commiting ffff880026bfb800
>[  513.524117] [drm:intel_power_well_enable] enabling display
>[  513.524118] [drm:hsw_set_power_well] Enabling power well
>[  513.526186] [drm:intel_power_well_enable] enabling always-on
>[  513.526196] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  513.526197] [drm:intel_enable_shared_dpll] enabling SPLL
>[  513.527087] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  513.527158] [drm:intel_enable_pipe] enabling pipe B
>[  513.527172] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  513.594009] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  513.594013] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  513.594014] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  513.594016] [drm:check_crtc_state] [CRTC:25]
>[  513.594027] [drm:check_shared_dpll_state] WRPLL 1
>[  513.594028] [drm:check_shared_dpll_state] WRPLL 2
>[  513.594029] [drm:check_shared_dpll_state] SPLL
>[  513.594031] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bfb800
>[  513.594034] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bfb800
>[  513.594061] [drm:drm_mode_setcrtc] [CRTC:25]
>[  513.594064] [drm:drm_atomic_state_init] Allocated atomic state ffff88020103c600
>[  513.594066] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5324000 state to ffff88020103c600
>[  513.594067] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f55af300 state to ffff88020103c600
>[  513.594068] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f5324000
>[  513.594069] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55af300 to [NOCRTC]
>[  513.594070] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f55af300
>[  513.594071] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103c600
>[  513.594073] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c909bfe0 state to ffff88020103c600
>[  513.594074] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c909bfe0 to [NOCRTC]
>[  513.594075] [drm:drm_atomic_check_only] checking ffff88020103c600
>[  513.594076] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  513.594077] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  513.594078] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  513.594079] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  513.594080] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  513.594081] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  513.594081] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103c600
>[  513.594083] [drm:drm_atomic_connectors_for_crtc] State ffff88020103c600 has 0 connectors for [CRTC:25]
>[  513.594086] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  513.594087] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  513.594088] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f55af6c0 state to ffff88020103c600
>[  513.594089] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f55af780 state to ffff88020103c600
>[  513.594091] [drm:drm_atomic_commit] commiting ffff88020103c600
>[  513.610702] [drm:intel_disable_pipe] disabling pipe B
>[  513.645820] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  513.645823] [drm:intel_disable_shared_dpll] disabling SPLL
>[  513.645831] [drm:intel_power_well_disable] disabling display
>[  513.645833] [drm:hsw_set_power_well] Requesting to disable the power well
>[  513.645834] [drm:intel_power_well_disable] disabling always-on
>[  513.645835] [drm:intel_power_well_enable] enabling display
>[  513.645836] [drm:hsw_set_power_well] Enabling power well
>[  513.647905] [drm:intel_power_well_disable] disabling display
>[  513.647909] [drm:hsw_set_power_well] Requesting to disable the power well
>[  513.647914] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  513.647916] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  513.647917] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  513.647920] [drm:check_crtc_state] [CRTC:25]
>[  513.647921] [drm:check_shared_dpll_state] WRPLL 1
>[  513.647922] [drm:check_shared_dpll_state] WRPLL 2
>[  513.647923] [drm:check_shared_dpll_state] SPLL
>[  513.647925] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88020103c600
>[  513.647928] [drm:drm_atomic_state_free] Freeing atomic state ffff88020103c600
>[  513.647955] [drm:drm_mode_setcrtc] [CRTC:25]
>[  513.647958] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  513.647960] [drm:drm_atomic_state_init] Allocated atomic state ffff88020103c600
>[  513.647962] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5326000 state to ffff88020103c600
>[  513.647963] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f55af600 state to ffff88020103c600
>[  513.647965] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f5326000
>[  513.647966] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55af600 to [CRTC:25]
>[  513.647967] [drm:drm_atomic_set_fb_for_plane] Set [FB:51] for plane state ffff8801f55af600
>[  513.647968] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c909be20 state to ffff88020103c600
>[  513.647969] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103c600
>[  513.647970] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c909be20 to [CRTC:25]
>[  513.647971] [drm:drm_atomic_check_only] checking ffff88020103c600
>[  513.647972] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  513.647973] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  513.647974] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  513.647976] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  513.647976] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  513.647977] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  513.647978] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103c600
>[  513.647980] [drm:drm_atomic_connectors_for_crtc] State ffff88020103c600 has 1 connectors for [CRTC:25]
>[  513.647981] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103c600
>[  513.647983] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  513.647983] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  513.647985] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  513.647986] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  513.647987] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff8801f5326000 for pipe B
>[  513.647988] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  513.647989] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  513.647990] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  513.647991] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  513.647992] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  513.647993] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  513.647994] [drm:intel_dump_pipe_config] requested mode:
>[  513.647995] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  513.647996] [drm:intel_dump_pipe_config] adjusted mode:
>[  513.647997] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  513.647999] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  513.647999] [drm:intel_dump_pipe_config] port clock: 270000
>[  513.648000] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  513.648001] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  513.648002] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  513.648003] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  513.648004] [drm:intel_dump_pipe_config] ips: 0
>[  513.648004] [drm:intel_dump_pipe_config] double wide: 0
>[  513.648006] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  513.648006] [drm:intel_dump_pipe_config] planes on this crtc
>[  513.648007] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  513.648008] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  513.648009] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  513.648011] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff8801f5327c00 state to ffff88020103c600
>[  513.648013] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff8801f5324400 state to ffff88020103c600
>[  513.648015] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 51
>[  513.648016] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  513.648017] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8801f55afe40 state to ffff88020103c600
>[  513.648018] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8801f55af9c0 state to ffff88020103c600
>[  513.648020] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8801f55aff00 state to ffff88020103c600
>[  513.648022] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f55af000 state to ffff88020103c600
>[  513.648023] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f55af180 state to ffff88020103c600
>[  513.648025] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8801f55af540 state to ffff88020103c600
>[  513.648026] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8801f55af900 state to ffff88020103c600
>[  513.648027] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8801f55af240 state to ffff88020103c600
>[  513.648028] [drm:drm_atomic_commit] commiting ffff88020103c600
>[  513.648033] [drm:intel_power_well_enable] enabling display
>[  513.648034] [drm:hsw_set_power_well] Enabling power well
>[  513.650102] [drm:intel_power_well_enable] enabling always-on
>[  513.650113] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  513.650114] [drm:intel_enable_shared_dpll] enabling SPLL
>[  513.651003] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  513.651068] [drm:intel_enable_pipe] enabling pipe B
>[  513.651082] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  513.717920] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  513.717925] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  513.717926] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  513.717928] [drm:check_crtc_state] [CRTC:25]
>[  513.717938] [drm:check_shared_dpll_state] WRPLL 1
>[  513.717939] [drm:check_shared_dpll_state] WRPLL 2
>[  513.717940] [drm:check_shared_dpll_state] SPLL
>[  513.717942] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88020103c600
>[  513.717946] [drm:drm_atomic_state_free] Freeing atomic state ffff88020103c600
>[  513.717972] [drm:drm_mode_setcrtc] [CRTC:25]
>[  513.717974] [drm:drm_atomic_state_init] Allocated atomic state ffff88020103c600
>[  513.717976] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5324000 state to ffff88020103c600
>[  513.717977] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f55af780 state to ffff88020103c600
>[  513.717978] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f5324000
>[  513.717979] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55af780 to [NOCRTC]
>[  513.717980] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f55af780
>[  513.717981] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103c600
>[  513.717983] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c909bfe0 state to ffff88020103c600
>[  513.717984] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c909bfe0 to [NOCRTC]
>[  513.717984] [drm:drm_atomic_check_only] checking ffff88020103c600
>[  513.717986] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  513.717987] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  513.717988] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  513.717988] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  513.717989] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  513.717990] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  513.717991] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103c600
>[  513.717992] [drm:drm_atomic_connectors_for_crtc] State ffff88020103c600 has 0 connectors for [CRTC:25]
>[  513.717995] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  513.717996] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  513.717998] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f55af6c0 state to ffff88020103c600
>[  513.717999] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f55af300 state to ffff88020103c600
>[  513.718001] [drm:drm_atomic_commit] commiting ffff88020103c600
>[  513.734613] [drm:intel_disable_pipe] disabling pipe B
>[  513.769460] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  513.769463] [drm:intel_disable_shared_dpll] disabling SPLL
>[  513.769471] [drm:intel_power_well_disable] disabling display
>[  513.769473] [drm:hsw_set_power_well] Requesting to disable the power well
>[  513.769473] [drm:intel_power_well_disable] disabling always-on
>[  513.769475] [drm:intel_power_well_enable] enabling display
>[  513.769476] [drm:hsw_set_power_well] Enabling power well
>[  513.771545] [drm:intel_power_well_disable] disabling display
>[  513.771548] [drm:hsw_set_power_well] Requesting to disable the power well
>[  513.771553] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  513.771555] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  513.771557] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  513.771559] [drm:check_crtc_state] [CRTC:25]
>[  513.771561] [drm:check_shared_dpll_state] WRPLL 1
>[  513.771562] [drm:check_shared_dpll_state] WRPLL 2
>[  513.771562] [drm:check_shared_dpll_state] SPLL
>[  513.771565] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88020103c600
>[  513.771567] [drm:drm_atomic_state_free] Freeing atomic state ffff88020103c600
>[  513.771594] [drm:drm_mode_setcrtc] [CRTC:25]
>[  513.771597] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  513.771599] [drm:drm_atomic_state_init] Allocated atomic state ffff88020103c600
>[  513.771601] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5326000 state to ffff88020103c600
>[  513.771602] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f55af180 state to ffff88020103c600
>[  513.771603] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f5326000
>[  513.771604] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55af180 to [CRTC:25]
>[  513.771605] [drm:drm_atomic_set_fb_for_plane] Set [FB:49] for plane state ffff8801f55af180
>[  513.771606] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c909be20 state to ffff88020103c600
>[  513.771608] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103c600
>[  513.771609] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c909be20 to [CRTC:25]
>[  513.771609] [drm:drm_atomic_check_only] checking ffff88020103c600
>[  513.771611] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  513.771612] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  513.771613] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  513.771614] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  513.771615] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  513.771616] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  513.771617] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103c600
>[  513.771618] [drm:drm_atomic_connectors_for_crtc] State ffff88020103c600 has 1 connectors for [CRTC:25]
>[  513.771619] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103c600
>[  513.771621] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  513.771621] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  513.771623] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  513.771624] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  513.771625] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff8801f5326000 for pipe B
>[  513.771626] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  513.771627] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  513.771628] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  513.771629] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  513.771630] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  513.771631] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  513.771632] [drm:intel_dump_pipe_config] requested mode:
>[  513.771633] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  513.771634] [drm:intel_dump_pipe_config] adjusted mode:
>[  513.771635] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  513.771637] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  513.771637] [drm:intel_dump_pipe_config] port clock: 270000
>[  513.771638] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  513.771639] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  513.771640] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  513.771641] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  513.771641] [drm:intel_dump_pipe_config] ips: 0
>[  513.771642] [drm:intel_dump_pipe_config] double wide: 0
>[  513.771643] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  513.771644] [drm:intel_dump_pipe_config] planes on this crtc
>[  513.771645] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  513.771646] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  513.771647] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  513.771649] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff8801f5325000 state to ffff88020103c600
>[  513.771650] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff8801f5327800 state to ffff88020103c600
>[  513.771652] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 49
>[  513.771653] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  513.771655] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8801f55af600 state to ffff88020103c600
>[  513.771656] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8801f55afb40 state to ffff88020103c600
>[  513.771657] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8801f55af3c0 state to ffff88020103c600
>[  513.771659] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f55afc00 state to ffff88020103c600
>[  513.771660] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f55afcc0 state to ffff88020103c600
>[  513.771662] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8801f55afa80 state to ffff88020103c600
>[  513.771663] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8801f55af0c0 state to ffff88020103c600
>[  513.771664] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8801f55af840 state to ffff88020103c600
>[  513.771666] [drm:drm_atomic_commit] commiting ffff88020103c600
>[  513.771670] [drm:intel_power_well_enable] enabling display
>[  513.771671] [drm:hsw_set_power_well] Enabling power well
>[  513.772817] [drm:intel_power_well_enable] enabling always-on
>[  513.772828] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  513.772830] [drm:intel_enable_shared_dpll] enabling SPLL
>[  513.773719] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  513.773783] [drm:intel_enable_pipe] enabling pipe B
>[  513.773797] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  513.840664] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  513.840669] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  513.840670] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  513.840672] [drm:check_crtc_state] [CRTC:25]
>[  513.840683] [drm:check_shared_dpll_state] WRPLL 1
>[  513.840684] [drm:check_shared_dpll_state] WRPLL 2
>[  513.840685] [drm:check_shared_dpll_state] SPLL
>[  513.840687] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88020103c600
>[  513.840690] [drm:drm_atomic_state_free] Freeing atomic state ffff88020103c600
>[  513.840718] [drm:drm_mode_setcrtc] [CRTC:25]
>[  513.840739] [drm:drm_atomic_state_init] Allocated atomic state ffff880210d7b800
>[  513.840742] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5490c00 state to ffff880210d7b800
>[  513.840743] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f5fdef00 state to ffff880210d7b800
>[  513.840744] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f5490c00
>[  513.840745] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f5fdef00 to [NOCRTC]
>[  513.840746] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f5fdef00
>[  513.840747] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b800
>[  513.840749] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800d3bba240 state to ffff880210d7b800
>[  513.840750] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800d3bba240 to [NOCRTC]
>[  513.840751] [drm:drm_atomic_check_only] checking ffff880210d7b800
>[  513.840752] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  513.840753] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  513.840755] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  513.840756] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  513.840758] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  513.840759] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  513.840760] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b800
>[  513.840761] [drm:drm_atomic_connectors_for_crtc] State ffff880210d7b800 has 0 connectors for [CRTC:25]
>[  513.840764] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  513.840765] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  513.840767] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f5fdee40 state to ffff880210d7b800
>[  513.840768] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f5fde480 state to ffff880210d7b800
>[  513.840770] [drm:drm_atomic_commit] commiting ffff880210d7b800
>[  513.857332] [drm:intel_disable_pipe] disabling pipe B
>[  513.891216] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  513.891220] [drm:intel_disable_shared_dpll] disabling SPLL
>[  513.891228] [drm:intel_power_well_disable] disabling display
>[  513.891229] [drm:hsw_set_power_well] Requesting to disable the power well
>[  513.891230] [drm:intel_power_well_disable] disabling always-on
>[  513.891232] [drm:intel_power_well_enable] enabling display
>[  513.891233] [drm:hsw_set_power_well] Enabling power well
>[  513.892807] [drm:intel_power_well_disable] disabling display
>[  513.892811] [drm:hsw_set_power_well] Requesting to disable the power well
>[  513.892817] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  513.892820] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  513.892821] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  513.892824] [drm:check_crtc_state] [CRTC:25]
>[  513.892826] [drm:check_shared_dpll_state] WRPLL 1
>[  513.892827] [drm:check_shared_dpll_state] WRPLL 2
>[  513.892828] [drm:check_shared_dpll_state] SPLL
>[  513.892830] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880210d7b800
>[  513.892832] [drm:drm_atomic_state_free] Freeing atomic state ffff880210d7b800
>[  513.892856] [drm:drm_mode_setcrtc] [CRTC:25]
>[  513.892860] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  513.892862] [drm:drm_atomic_state_init] Allocated atomic state ffff88020103ce00
>[  513.892864] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5326000 state to ffff88020103ce00
>[  513.892865] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f55afcc0 state to ffff88020103ce00
>[  513.892867] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f5326000
>[  513.892868] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55afcc0 to [CRTC:25]
>[  513.892870] [drm:drm_atomic_set_fb_for_plane] Set [FB:51] for plane state ffff8801f55afcc0
>[  513.892871] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c909be00 state to ffff88020103ce00
>[  513.892873] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103ce00
>[  513.892874] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c909be00 to [CRTC:25]
>[  513.892875] [drm:drm_atomic_check_only] checking ffff88020103ce00
>[  513.892877] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  513.892878] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  513.892880] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  513.892882] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  513.892883] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  513.892884] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  513.892885] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103ce00
>[  513.892886] [drm:drm_atomic_connectors_for_crtc] State ffff88020103ce00 has 1 connectors for [CRTC:25]
>[  513.892888] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103ce00
>[  513.892889] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  513.892890] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  513.892892] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  513.892893] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  513.892895] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff8801f5326000 for pipe B
>[  513.892896] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  513.892897] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  513.892899] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  513.892901] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  513.892902] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  513.892903] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  513.892904] [drm:intel_dump_pipe_config] requested mode:
>[  513.892905] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  513.892907] [drm:intel_dump_pipe_config] adjusted mode:
>[  513.892908] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  513.892910] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  513.892911] [drm:intel_dump_pipe_config] port clock: 270000
>[  513.892912] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  513.892913] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  513.892915] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  513.892916] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  513.892917] [drm:intel_dump_pipe_config] ips: 0
>[  513.892917] [drm:intel_dump_pipe_config] double wide: 0
>[  513.892919] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  513.892919] [drm:intel_dump_pipe_config] planes on this crtc
>[  513.892920] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  513.892921] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  513.892922] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  513.892924] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff8801f5326400 state to ffff88020103ce00
>[  513.892926] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff8801f5324400 state to ffff88020103ce00
>[  513.892928] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 51
>[  513.892929] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  513.892931] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8801f55af180 state to ffff88020103ce00
>[  513.892932] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8801f55af000 state to ffff88020103ce00
>[  513.892933] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8801f55af480 state to ffff88020103ce00
>[  513.892936] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f55af240 state to ffff88020103ce00
>[  513.892937] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f55af900 state to ffff88020103ce00
>[  513.892939] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8801f55af540 state to ffff88020103ce00
>[  513.892940] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8801f55af300 state to ffff88020103ce00
>[  513.892941] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8801f55af6c0 state to ffff88020103ce00
>[  513.892942] [drm:drm_atomic_commit] commiting ffff88020103ce00
>[  513.892947] [drm:intel_power_well_enable] enabling display
>[  513.892948] [drm:hsw_set_power_well] Enabling power well
>[  513.895016] [drm:intel_power_well_enable] enabling always-on
>[  513.895027] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  513.895028] [drm:intel_enable_shared_dpll] enabling SPLL
>[  513.895917] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  513.895981] [drm:intel_enable_pipe] enabling pipe B
>[  513.895995] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  513.962832] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  513.962837] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  513.962838] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  513.962840] [drm:check_crtc_state] [CRTC:25]
>[  513.962850] [drm:check_shared_dpll_state] WRPLL 1
>[  513.962851] [drm:check_shared_dpll_state] WRPLL 2
>[  513.962852] [drm:check_shared_dpll_state] SPLL
>[  513.962854] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88020103ce00
>[  513.962858] [drm:drm_atomic_state_free] Freeing atomic state ffff88020103ce00
>[  513.962884] [drm:drm_mode_setcrtc] [CRTC:25]
>[  513.962886] [drm:drm_atomic_state_init] Allocated atomic state ffff88020103ce00
>[  513.962888] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5327800 state to ffff88020103ce00
>[  513.962890] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f55af840 state to ffff88020103ce00
>[  513.962891] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f5327800
>[  513.962892] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55af840 to [NOCRTC]
>[  513.962893] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f55af840
>[  513.962894] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103ce00
>[  513.962895] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c909bbc0 state to ffff88020103ce00
>[  513.962896] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c909bbc0 to [NOCRTC]
>[  513.962897] [drm:drm_atomic_check_only] checking ffff88020103ce00
>[  513.962898] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  513.962899] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  513.962900] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  513.962901] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  513.962901] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  513.962902] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  513.962903] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103ce00
>[  513.962905] [drm:drm_atomic_connectors_for_crtc] State ffff88020103ce00 has 0 connectors for [CRTC:25]
>[  513.962907] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  513.962908] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  513.962910] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f55af0c0 state to ffff88020103ce00
>[  513.962911] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f55afa80 state to ffff88020103ce00
>[  513.962913] [drm:drm_atomic_commit] commiting ffff88020103ce00
>[  513.979522] [drm:intel_disable_pipe] disabling pipe B
>[  514.013852] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  514.013855] [drm:intel_disable_shared_dpll] disabling SPLL
>[  514.013863] [drm:intel_power_well_disable] disabling display
>[  514.013864] [drm:hsw_set_power_well] Requesting to disable the power well
>[  514.013865] [drm:intel_power_well_disable] disabling always-on
>[  514.013867] [drm:intel_power_well_enable] enabling display
>[  514.013868] [drm:hsw_set_power_well] Enabling power well
>[  514.015937] [drm:intel_power_well_disable] disabling display
>[  514.015941] [drm:hsw_set_power_well] Requesting to disable the power well
>[  514.015946] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  514.015948] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  514.015949] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  514.015952] [drm:check_crtc_state] [CRTC:25]
>[  514.015953] [drm:check_shared_dpll_state] WRPLL 1
>[  514.015955] [drm:check_shared_dpll_state] WRPLL 2
>[  514.015956] [drm:check_shared_dpll_state] SPLL
>[  514.015957] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88020103ce00
>[  514.015960] [drm:drm_atomic_state_free] Freeing atomic state ffff88020103ce00
>[  514.015987] [drm:drm_mode_setcrtc] [CRTC:25]
>[  514.015991] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  514.015993] [drm:drm_atomic_state_init] Allocated atomic state ffff880210d7b400
>[  514.015995] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5492c00 state to ffff880210d7b400
>[  514.015996] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f5fde780 state to ffff880210d7b400
>[  514.015998] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f5492c00
>[  514.015999] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f5fde780 to [CRTC:25]
>[  514.016000] [drm:drm_atomic_set_fb_for_plane] Set [FB:49] for plane state ffff8801f5fde780
>[  514.016001] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800d3bba160 state to ffff880210d7b400
>[  514.016002] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b400
>[  514.016003] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800d3bba160 to [CRTC:25]
>[  514.016004] [drm:drm_atomic_check_only] checking ffff880210d7b400
>[  514.016006] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  514.016006] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  514.016007] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  514.016009] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  514.016010] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  514.016011] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  514.016011] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b400
>[  514.016013] [drm:drm_atomic_connectors_for_crtc] State ffff880210d7b400 has 1 connectors for [CRTC:25]
>[  514.016014] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b400
>[  514.016015] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  514.016016] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  514.016018] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  514.016019] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  514.016021] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff8801f5492c00 for pipe B
>[  514.016021] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  514.016022] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  514.016023] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  514.016025] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  514.016026] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  514.016026] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  514.016027] [drm:intel_dump_pipe_config] requested mode:
>[  514.016029] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  514.016029] [drm:intel_dump_pipe_config] adjusted mode:
>[  514.016031] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  514.016032] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  514.016033] [drm:intel_dump_pipe_config] port clock: 270000
>[  514.016033] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  514.016034] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  514.016035] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  514.016036] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  514.016037] [drm:intel_dump_pipe_config] ips: 0
>[  514.016038] [drm:intel_dump_pipe_config] double wide: 0
>[  514.016039] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  514.016039] [drm:intel_dump_pipe_config] planes on this crtc
>[  514.016041] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  514.016042] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  514.016043] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  514.016044] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff8801f5490c00 state to ffff880210d7b400
>[  514.016046] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff8801f5490800 state to ffff880210d7b400
>[  514.016048] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 49
>[  514.016049] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  514.016050] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8801f5fde180 state to ffff880210d7b400
>[  514.016052] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8801f5fde480 state to ffff880210d7b400
>[  514.016053] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8801f5fdee40 state to ffff880210d7b400
>[  514.016055] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f5fdef00 state to ffff880210d7b400
>[  514.016057] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f5fded80 state to ffff880210d7b400
>[  514.016058] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8801f5fde000 state to ffff880210d7b400
>[  514.016059] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8801f5fdecc0 state to ffff880210d7b400
>[  514.016060] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8801f5fdeb40 state to ffff880210d7b400
>[  514.016062] [drm:drm_atomic_commit] commiting ffff880210d7b400
>[  514.016066] [drm:intel_power_well_enable] enabling display
>[  514.016067] [drm:hsw_set_power_well] Enabling power well
>[  514.018135] [drm:intel_power_well_enable] enabling always-on
>[  514.018146] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  514.018147] [drm:intel_enable_shared_dpll] enabling SPLL
>[  514.019036] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  514.019100] [drm:intel_enable_pipe] enabling pipe B
>[  514.019113] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  514.085981] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  514.085985] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  514.085986] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  514.085988] [drm:check_crtc_state] [CRTC:25]
>[  514.085999] [drm:check_shared_dpll_state] WRPLL 1
>[  514.086001] [drm:check_shared_dpll_state] WRPLL 2
>[  514.086001] [drm:check_shared_dpll_state] SPLL
>[  514.086003] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880210d7b400
>[  514.086007] [drm:drm_atomic_state_free] Freeing atomic state ffff880210d7b400
>[  514.086034] [drm:drm_mode_setcrtc] [CRTC:25]
>[  514.086035] [drm:drm_atomic_state_init] Allocated atomic state ffff880210d7b400
>[  514.086038] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5493800 state to ffff880210d7b400
>[  514.086039] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f5fdec00 state to ffff880210d7b400
>[  514.086040] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f5493800
>[  514.086041] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f5fdec00 to [NOCRTC]
>[  514.086042] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f5fdec00
>[  514.086043] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b400
>[  514.086044] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800d3bbae00 state to ffff880210d7b400
>[  514.086045] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800d3bbae00 to [NOCRTC]
>[  514.086046] [drm:drm_atomic_check_only] checking ffff880210d7b400
>[  514.086048] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  514.086048] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  514.086049] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  514.086050] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  514.086051] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  514.086052] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  514.086053] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b400
>[  514.086054] [drm:drm_atomic_connectors_for_crtc] State ffff880210d7b400 has 0 connectors for [CRTC:25]
>[  514.086057] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  514.086058] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  514.086059] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f5fde540 state to ffff880210d7b400
>[  514.086061] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f5fde840 state to ffff880210d7b400
>[  514.086063] [drm:drm_atomic_commit] commiting ffff880210d7b400
>[  514.102660] [drm:intel_disable_pipe] disabling pipe B
>[  514.137807] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  514.137811] [drm:intel_disable_shared_dpll] disabling SPLL
>[  514.137819] [drm:intel_power_well_disable] disabling display
>[  514.137821] [drm:hsw_set_power_well] Requesting to disable the power well
>[  514.137822] [drm:intel_power_well_disable] disabling always-on
>[  514.137823] [drm:intel_power_well_enable] enabling display
>[  514.137825] [drm:hsw_set_power_well] Enabling power well
>[  514.139895] [drm:intel_power_well_disable] disabling display
>[  514.139899] [drm:hsw_set_power_well] Requesting to disable the power well
>[  514.139904] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  514.139906] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  514.139908] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  514.139910] [drm:check_crtc_state] [CRTC:25]
>[  514.139912] [drm:check_shared_dpll_state] WRPLL 1
>[  514.139913] [drm:check_shared_dpll_state] WRPLL 2
>[  514.139914] [drm:check_shared_dpll_state] SPLL
>[  514.139916] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880210d7b400
>[  514.139919] [drm:drm_atomic_state_free] Freeing atomic state ffff880210d7b400
>[  514.139948] [drm:drm_mode_setcrtc] [CRTC:25]
>[  514.139951] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  514.139953] [drm:drm_atomic_state_init] Allocated atomic state ffff880210d7b400
>[  514.139955] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5492c00 state to ffff880210d7b400
>[  514.139956] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f5fded80 state to ffff880210d7b400
>[  514.139958] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f5492c00
>[  514.139959] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f5fded80 to [CRTC:25]
>[  514.139960] [drm:drm_atomic_set_fb_for_plane] Set [FB:51] for plane state ffff8801f5fded80
>[  514.139962] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800d3bba160 state to ffff880210d7b400
>[  514.139963] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b400
>[  514.139964] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800d3bba160 to [CRTC:25]
>[  514.139965] [drm:drm_atomic_check_only] checking ffff880210d7b400
>[  514.139967] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  514.139968] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  514.139969] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  514.139971] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  514.139971] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  514.139972] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  514.139973] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b400
>[  514.139975] [drm:drm_atomic_connectors_for_crtc] State ffff880210d7b400 has 1 connectors for [CRTC:25]
>[  514.139976] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b400
>[  514.139978] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  514.139979] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  514.139981] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  514.139982] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  514.139984] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff8801f5492c00 for pipe B
>[  514.139985] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  514.139986] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  514.139987] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  514.139989] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  514.139990] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  514.139991] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  514.139991] [drm:intel_dump_pipe_config] requested mode:
>[  514.139993] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  514.139994] [drm:intel_dump_pipe_config] adjusted mode:
>[  514.139996] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  514.139997] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  514.139998] [drm:intel_dump_pipe_config] port clock: 270000
>[  514.139999] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  514.140000] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  514.140001] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  514.140002] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  514.140003] [drm:intel_dump_pipe_config] ips: 0
>[  514.140004] [drm:intel_dump_pipe_config] double wide: 0
>[  514.140005] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  514.140006] [drm:intel_dump_pipe_config] planes on this crtc
>[  514.140007] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  514.140008] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  514.140009] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  514.140011] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff8801f5493400 state to ffff880210d7b400
>[  514.140013] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff8801f5491c00 state to ffff880210d7b400
>[  514.140015] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 51
>[  514.140016] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  514.140018] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8801f5fde780 state to ffff880210d7b400
>[  514.140019] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8801f5fdea80 state to ffff880210d7b400
>[  514.140021] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8801f5fde600 state to ffff880210d7b400
>[  514.140024] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f5fde0c0 state to ffff880210d7b400
>[  514.140025] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f5fde9c0 state to ffff880210d7b400
>[  514.140027] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8801f5fde6c0 state to ffff880210d7b400
>[  514.140028] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8801f5fde3c0 state to ffff880210d7b400
>[  514.140029] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8801f5fde900 state to ffff880210d7b400
>[  514.140031] [drm:drm_atomic_commit] commiting ffff880210d7b400
>[  514.140036] [drm:intel_power_well_enable] enabling display
>[  514.140037] [drm:hsw_set_power_well] Enabling power well
>[  514.142106] [drm:intel_power_well_enable] enabling always-on
>[  514.142117] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  514.142118] [drm:intel_enable_shared_dpll] enabling SPLL
>[  514.143008] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  514.143077] [drm:intel_enable_pipe] enabling pipe B
>[  514.143091] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  514.209957] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  514.209962] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  514.209963] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  514.209965] [drm:check_crtc_state] [CRTC:25]
>[  514.209976] [drm:check_shared_dpll_state] WRPLL 1
>[  514.209977] [drm:check_shared_dpll_state] WRPLL 2
>[  514.209978] [drm:check_shared_dpll_state] SPLL
>[  514.209980] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880210d7b400
>[  514.209983] [drm:drm_atomic_state_free] Freeing atomic state ffff880210d7b400
>[  514.210010] [drm:drm_mode_setcrtc] [CRTC:25]
>[  514.210011] [drm:drm_atomic_state_init] Allocated atomic state ffff880210d7b400
>[  514.210013] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5490800 state to ffff880210d7b400
>[  514.210015] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f5fdeb40 state to ffff880210d7b400
>[  514.210016] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f5490800
>[  514.210016] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f5fdeb40 to [NOCRTC]
>[  514.210018] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f5fdeb40
>[  514.210019] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b400
>[  514.210020] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800d3bbae00 state to ffff880210d7b400
>[  514.210021] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800d3bbae00 to [NOCRTC]
>[  514.210022] [drm:drm_atomic_check_only] checking ffff880210d7b400
>[  514.210023] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  514.210024] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  514.210025] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  514.210026] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  514.210026] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  514.210027] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  514.210028] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b400
>[  514.210030] [drm:drm_atomic_connectors_for_crtc] State ffff880210d7b400 has 0 connectors for [CRTC:25]
>[  514.210032] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  514.210033] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  514.210035] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f5fdecc0 state to ffff880210d7b400
>[  514.210036] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f5fde000 state to ffff880210d7b400
>[  514.210038] [drm:drm_atomic_commit] commiting ffff880210d7b400
>[  514.226637] [drm:intel_disable_pipe] disabling pipe B
>[  514.261852] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  514.261857] [drm:intel_disable_shared_dpll] disabling SPLL
>[  514.261868] [drm:intel_power_well_disable] disabling display
>[  514.261870] [drm:hsw_set_power_well] Requesting to disable the power well
>[  514.261872] [drm:intel_power_well_disable] disabling always-on
>[  514.261874] [drm:intel_power_well_enable] enabling display
>[  514.261875] [drm:hsw_set_power_well] Enabling power well
>[  514.263952] [drm:intel_power_well_disable] disabling display
>[  514.263957] [drm:hsw_set_power_well] Requesting to disable the power well
>[  514.263963] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  514.263966] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  514.263968] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  514.263972] [drm:check_crtc_state] [CRTC:25]
>[  514.263973] [drm:check_shared_dpll_state] WRPLL 1
>[  514.263975] [drm:check_shared_dpll_state] WRPLL 2
>[  514.263977] [drm:check_shared_dpll_state] SPLL
>[  514.263979] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880210d7b400
>[  514.263982] [drm:drm_atomic_state_free] Freeing atomic state ffff880210d7b400
>[  514.264017] [drm:drm_mode_setcrtc] [CRTC:25]
>[  514.264021] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  514.264023] [drm:drm_atomic_state_init] Allocated atomic state ffff880210d7b400
>[  514.264026] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5492c00 state to ffff880210d7b400
>[  514.264028] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f5fde9c0 state to ffff880210d7b400
>[  514.264030] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f5492c00
>[  514.264031] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f5fde9c0 to [CRTC:25]
>[  514.264033] [drm:drm_atomic_set_fb_for_plane] Set [FB:49] for plane state ffff8801f5fde9c0
>[  514.264035] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800d3bba160 state to ffff880210d7b400
>[  514.264036] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b400
>[  514.264038] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800d3bba160 to [CRTC:25]
>[  514.264039] [drm:drm_atomic_check_only] checking ffff880210d7b400
>[  514.264041] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  514.264043] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  514.264044] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  514.264046] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  514.264047] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  514.264049] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  514.264050] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b400
>[  514.264052] [drm:drm_atomic_connectors_for_crtc] State ffff880210d7b400 has 1 connectors for [CRTC:25]
>[  514.264054] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b400
>[  514.264056] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  514.264058] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  514.264060] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  514.264061] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  514.264064] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff8801f5492c00 for pipe B
>[  514.264065] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  514.264067] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  514.264069] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  514.264070] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  514.264072] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  514.264073] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  514.264074] [drm:intel_dump_pipe_config] requested mode:
>[  514.264077] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  514.264078] [drm:intel_dump_pipe_config] adjusted mode:
>[  514.264080] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  514.264082] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  514.264084] [drm:intel_dump_pipe_config] port clock: 270000
>[  514.264085] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  514.264086] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  514.264087] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  514.264089] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  514.264090] [drm:intel_dump_pipe_config] ips: 0
>[  514.264091] [drm:intel_dump_pipe_config] double wide: 0
>[  514.264093] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  514.264094] [drm:intel_dump_pipe_config] planes on this crtc
>[  514.264096] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  514.264097] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  514.264099] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  514.264101] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff8801f5493800 state to ffff880210d7b400
>[  514.264103] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff8801f5490c00 state to ffff880210d7b400
>[  514.264106] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 49
>[  514.264108] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  514.264110] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8801f5fded80 state to ffff880210d7b400
>[  514.264112] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8801f5fdef00 state to ffff880210d7b400
>[  514.264113] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8801f5fde840 state to ffff880210d7b400
>[  514.264117] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f5fde540 state to ffff880210d7b400
>[  514.264119] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f5fdec00 state to ffff880210d7b400
>[  514.264121] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8801f5fdee40 state to ffff880210d7b400
>[  514.264123] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8801f5fde480 state to ffff880210d7b400
>[  514.264124] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8801f5fde180 state to ffff880210d7b400
>[  514.264126] [drm:drm_atomic_commit] commiting ffff880210d7b400
>[  514.264133] [drm:intel_power_well_enable] enabling display
>[  514.264134] [drm:hsw_set_power_well] Enabling power well
>[  514.266211] [drm:intel_power_well_enable] enabling always-on
>[  514.266223] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  514.266225] [drm:intel_enable_shared_dpll] enabling SPLL
>[  514.267120] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  514.267205] [drm:intel_enable_pipe] enabling pipe B
>[  514.267222] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  514.334095] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  514.334099] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  514.334101] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  514.334102] [drm:check_crtc_state] [CRTC:25]
>[  514.334114] [drm:check_shared_dpll_state] WRPLL 1
>[  514.334115] [drm:check_shared_dpll_state] WRPLL 2
>[  514.334116] [drm:check_shared_dpll_state] SPLL
>[  514.334118] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880210d7b400
>[  514.334121] [drm:drm_atomic_state_free] Freeing atomic state ffff880210d7b400
>[  514.334149] [drm:drm_mode_setcrtc] [CRTC:25]
>[  514.334151] [drm:drm_atomic_state_init] Allocated atomic state ffff880210d7b400
>[  514.334153] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5491c00 state to ffff880210d7b400
>[  514.334154] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f5fde900 state to ffff880210d7b400
>[  514.334155] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f5491c00
>[  514.334156] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f5fde900 to [NOCRTC]
>[  514.334157] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f5fde900
>[  514.334159] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b400
>[  514.334160] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800d3bbae00 state to ffff880210d7b400
>[  514.334161] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800d3bbae00 to [NOCRTC]
>[  514.334161] [drm:drm_atomic_check_only] checking ffff880210d7b400
>[  514.334163] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  514.334164] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  514.334165] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  514.334166] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  514.334166] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  514.334167] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  514.334168] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b400
>[  514.334170] [drm:drm_atomic_connectors_for_crtc] State ffff880210d7b400 has 0 connectors for [CRTC:25]
>[  514.334172] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  514.334173] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  514.334175] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f5fde3c0 state to ffff880210d7b400
>[  514.334176] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f5fde6c0 state to ffff880210d7b400
>[  514.334178] [drm:drm_atomic_commit] commiting ffff880210d7b400
>[  514.350771] [drm:intel_disable_pipe] disabling pipe B
>[  514.385917] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  514.385921] [drm:intel_disable_shared_dpll] disabling SPLL
>[  514.385931] [drm:intel_power_well_disable] disabling display
>[  514.385934] [drm:hsw_set_power_well] Requesting to disable the power well
>[  514.385935] [drm:intel_power_well_disable] disabling always-on
>[  514.385937] [drm:intel_power_well_enable] enabling display
>[  514.385938] [drm:hsw_set_power_well] Enabling power well
>[  514.388013] [drm:intel_power_well_disable] disabling display
>[  514.388018] [drm:hsw_set_power_well] Requesting to disable the power well
>[  514.388024] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  514.388027] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  514.388028] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  514.388032] [drm:check_crtc_state] [CRTC:25]
>[  514.388034] [drm:check_shared_dpll_state] WRPLL 1
>[  514.388035] [drm:check_shared_dpll_state] WRPLL 2
>[  514.388036] [drm:check_shared_dpll_state] SPLL
>[  514.388039] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880210d7b400
>[  514.388043] [drm:drm_atomic_state_free] Freeing atomic state ffff880210d7b400
>[  514.388077] [drm:drm_mode_setcrtc] [CRTC:25]
>[  514.388082] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  514.388085] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bf3c00
>[  514.388087] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880215be4800 state to ffff880026bf3c00
>[  514.388089] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8800d3b009c0 state to ffff880026bf3c00
>[  514.388092] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff880215be4800
>[  514.388093] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800d3b009c0 to [CRTC:25]
>[  514.388095] [drm:drm_atomic_set_fb_for_plane] Set [FB:51] for plane state ffff8800d3b009c0
>[  514.388096] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c0132e00 state to ffff880026bf3c00
>[  514.388098] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3c00
>[  514.388099] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c0132e00 to [CRTC:25]
>[  514.388101] [drm:drm_atomic_check_only] checking ffff880026bf3c00
>[  514.388103] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  514.388104] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  514.388105] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  514.388107] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  514.388108] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  514.388110] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  514.388111] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3c00
>[  514.388113] [drm:drm_atomic_connectors_for_crtc] State ffff880026bf3c00 has 1 connectors for [CRTC:25]
>[  514.388115] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3c00
>[  514.388117] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  514.388118] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  514.388120] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  514.388122] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  514.388124] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff880215be4800 for pipe B
>[  514.388125] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  514.388126] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  514.388128] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  514.388130] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  514.388131] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  514.388132] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  514.388133] [drm:intel_dump_pipe_config] requested mode:
>[  514.388136] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  514.388137] [drm:intel_dump_pipe_config] adjusted mode:
>[  514.388139] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  514.388141] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  514.388142] [drm:intel_dump_pipe_config] port clock: 270000
>[  514.388143] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  514.388144] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  514.388145] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  514.388147] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  514.388148] [drm:intel_dump_pipe_config] ips: 0
>[  514.388149] [drm:intel_dump_pipe_config] double wide: 0
>[  514.388151] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  514.388152] [drm:intel_dump_pipe_config] planes on this crtc
>[  514.388154] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  514.388156] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  514.388157] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  514.388159] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff880215be5000 state to ffff880026bf3c00
>[  514.388161] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff880215be5c00 state to ffff880026bf3c00
>[  514.388164] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 51
>[  514.388166] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  514.388168] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8800d3b00900 state to ffff880026bf3c00
>[  514.388170] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8800d3b003c0 state to ffff880026bf3c00
>[  514.388171] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8800d3b00780 state to ffff880026bf3c00
>[  514.388175] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8800d3b00b40 state to ffff880026bf3c00
>[  514.388176] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8800d3b00300 state to ffff880026bf3c00
>[  514.388179] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8800d3b00c00 state to ffff880026bf3c00
>[  514.388181] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8800d3b00480 state to ffff880026bf3c00
>[  514.388182] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8800d3b00000 state to ffff880026bf3c00
>[  514.388184] [drm:drm_atomic_commit] commiting ffff880026bf3c00
>[  514.388191] [drm:intel_power_well_enable] enabling display
>[  514.388192] [drm:hsw_set_power_well] Enabling power well
>[  514.390235] [drm:intel_power_well_enable] enabling always-on
>[  514.390246] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  514.390248] [drm:intel_enable_shared_dpll] enabling SPLL
>[  514.391140] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  514.391220] [drm:intel_enable_pipe] enabling pipe B
>[  514.391236] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  514.458105] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  514.458109] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  514.458110] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  514.458112] [drm:check_crtc_state] [CRTC:25]
>[  514.458124] [drm:check_shared_dpll_state] WRPLL 1
>[  514.458125] [drm:check_shared_dpll_state] WRPLL 2
>[  514.458126] [drm:check_shared_dpll_state] SPLL
>[  514.458127] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bf3c00
>[  514.458131] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bf3c00
>[  514.458158] [drm:drm_mode_setcrtc] [CRTC:25]
>[  514.458160] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bf3c00
>[  514.458162] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880215be4000 state to ffff880026bf3c00
>[  514.458164] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8800d3b00f00 state to ffff880026bf3c00
>[  514.458165] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff880215be4000
>[  514.458166] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800d3b00f00 to [NOCRTC]
>[  514.458167] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8800d3b00f00
>[  514.458168] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3c00
>[  514.458169] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c0132480 state to ffff880026bf3c00
>[  514.458170] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c0132480 to [NOCRTC]
>[  514.458171] [drm:drm_atomic_check_only] checking ffff880026bf3c00
>[  514.458173] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  514.458173] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  514.458175] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  514.458176] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  514.458177] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  514.458178] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  514.458179] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3c00
>[  514.458180] [drm:drm_atomic_connectors_for_crtc] State ffff880026bf3c00 has 0 connectors for [CRTC:25]
>[  514.458183] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  514.458184] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  514.458186] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8800d3b00cc0 state to ffff880026bf3c00
>[  514.458187] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8800d3b00e40 state to ffff880026bf3c00
>[  514.458189] [drm:drm_atomic_commit] commiting ffff880026bf3c00
>[  514.474785] [drm:intel_disable_pipe] disabling pipe B
>[  514.509902] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  514.509906] [drm:intel_disable_shared_dpll] disabling SPLL
>[  514.509916] [drm:intel_power_well_disable] disabling display
>[  514.509919] [drm:hsw_set_power_well] Requesting to disable the power well
>[  514.509920] [drm:intel_power_well_disable] disabling always-on
>[  514.509922] [drm:intel_power_well_enable] enabling display
>[  514.509923] [drm:hsw_set_power_well] Enabling power well
>[  514.511998] [drm:intel_power_well_disable] disabling display
>[  514.512003] [drm:hsw_set_power_well] Requesting to disable the power well
>[  514.512009] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  514.512012] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  514.512014] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  514.512017] [drm:check_crtc_state] [CRTC:25]
>[  514.512019] [drm:check_shared_dpll_state] WRPLL 1
>[  514.512021] [drm:check_shared_dpll_state] WRPLL 2
>[  514.512022] [drm:check_shared_dpll_state] SPLL
>[  514.512024] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bf3c00
>[  514.512027] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bf3c00
>[  514.512061] [drm:drm_mode_setcrtc] [CRTC:25]
>[  514.512065] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  514.512068] [drm:drm_atomic_state_init] Allocated atomic state ffff88020103c200
>[  514.512071] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5325000 state to ffff88020103c200
>[  514.512073] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f55af3c0 state to ffff88020103c200
>[  514.512075] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f5325000
>[  514.512076] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55af3c0 to [CRTC:25]
>[  514.512078] [drm:drm_atomic_set_fb_for_plane] Set [FB:49] for plane state ffff8801f55af3c0
>[  514.512080] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c909bc00 state to ffff88020103c200
>[  514.512081] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103c200
>[  514.512083] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c909bc00 to [CRTC:25]
>[  514.512084] [drm:drm_atomic_check_only] checking ffff88020103c200
>[  514.512086] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  514.512087] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  514.512089] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  514.512091] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  514.512092] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  514.512093] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  514.512094] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103c200
>[  514.512096] [drm:drm_atomic_connectors_for_crtc] State ffff88020103c200 has 1 connectors for [CRTC:25]
>[  514.512098] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103c200
>[  514.512100] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  514.512102] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  514.512104] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  514.512105] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  514.512107] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff8801f5325000 for pipe B
>[  514.512108] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  514.512110] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  514.512111] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  514.512113] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  514.512115] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  514.512116] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  514.512117] [drm:intel_dump_pipe_config] requested mode:
>[  514.512119] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  514.512120] [drm:intel_dump_pipe_config] adjusted mode:
>[  514.512122] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  514.512124] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  514.512125] [drm:intel_dump_pipe_config] port clock: 270000
>[  514.512126] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  514.512128] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  514.512129] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  514.512130] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  514.512132] [drm:intel_dump_pipe_config] ips: 0
>[  514.512133] [drm:intel_dump_pipe_config] double wide: 0
>[  514.512134] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  514.512135] [drm:intel_dump_pipe_config] planes on this crtc
>[  514.512137] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  514.512138] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  514.512140] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  514.512142] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff8801f5324000 state to ffff88020103c200
>[  514.512144] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff8801f5327c00 state to ffff88020103c200
>[  514.512147] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 49
>[  514.512148] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  514.512150] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8801f55af600 state to ffff88020103c200
>[  514.512152] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8801f55af780 state to ffff88020103c200
>[  514.512154] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8801f55aff00 state to ffff88020103c200
>[  514.512158] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f55af9c0 state to ffff88020103c200
>[  514.512159] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f55afe40 state to ffff88020103c200
>[  514.512162] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8801f55af6c0 state to ffff88020103c200
>[  514.512164] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8801f55af300 state to ffff88020103c200
>[  514.512166] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8801f55af540 state to ffff88020103c200
>[  514.512168] [drm:drm_atomic_commit] commiting ffff88020103c200
>[  514.512174] [drm:intel_power_well_enable] enabling display
>[  514.512176] [drm:hsw_set_power_well] Enabling power well
>[  514.514247] [drm:intel_power_well_enable] enabling always-on
>[  514.514259] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  514.514261] [drm:intel_enable_shared_dpll] enabling SPLL
>[  514.515154] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  514.515235] [drm:intel_enable_pipe] enabling pipe B
>[  514.515250] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  514.582091] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  514.582096] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  514.582097] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  514.582099] [drm:check_crtc_state] [CRTC:25]
>[  514.582110] [drm:check_shared_dpll_state] WRPLL 1
>[  514.582111] [drm:check_shared_dpll_state] WRPLL 2
>[  514.582112] [drm:check_shared_dpll_state] SPLL
>[  514.582114] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88020103c200
>[  514.582117] [drm:drm_atomic_state_free] Freeing atomic state ffff88020103c200
>[  514.582144] [drm:drm_mode_setcrtc] [CRTC:25]
>[  514.582146] [drm:drm_atomic_state_init] Allocated atomic state ffff88020103c200
>[  514.582148] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5324400 state to ffff88020103c200
>[  514.582150] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f55afa80 state to ffff88020103c200
>[  514.582151] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f5324400
>[  514.582152] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55afa80 to [NOCRTC]
>[  514.582153] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f55afa80
>[  514.582154] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103c200
>[  514.582155] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c909b160 state to ffff88020103c200
>[  514.582156] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c909b160 to [NOCRTC]
>[  514.582157] [drm:drm_atomic_check_only] checking ffff88020103c200
>[  514.582158] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  514.582159] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  514.582160] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  514.582161] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  514.582161] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  514.582162] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  514.582163] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103c200
>[  514.582165] [drm:drm_atomic_connectors_for_crtc] State ffff88020103c200 has 0 connectors for [CRTC:25]
>[  514.582167] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  514.582168] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  514.582170] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f55af0c0 state to ffff88020103c200
>[  514.582171] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f55af840 state to ffff88020103c200
>[  514.582173] [drm:drm_atomic_commit] commiting ffff88020103c200
>[  514.598792] [drm:intel_disable_pipe] disabling pipe B
>[  514.633912] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  514.633917] [drm:intel_disable_shared_dpll] disabling SPLL
>[  514.633927] [drm:intel_power_well_disable] disabling display
>[  514.633930] [drm:hsw_set_power_well] Requesting to disable the power well
>[  514.633931] [drm:intel_power_well_disable] disabling always-on
>[  514.633933] [drm:intel_power_well_enable] enabling display
>[  514.633935] [drm:hsw_set_power_well] Enabling power well
>[  514.636008] [drm:intel_power_well_disable] disabling display
>[  514.636013] [drm:hsw_set_power_well] Requesting to disable the power well
>[  514.636020] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  514.636023] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  514.636024] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  514.636028] [drm:check_crtc_state] [CRTC:25]
>[  514.636030] [drm:check_shared_dpll_state] WRPLL 1
>[  514.636031] [drm:check_shared_dpll_state] WRPLL 2
>[  514.636033] [drm:check_shared_dpll_state] SPLL
>[  514.636036] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88020103c200
>[  514.636039] [drm:drm_atomic_state_free] Freeing atomic state ffff88020103c200
>[  514.636074] [drm:drm_mode_setcrtc] [CRTC:25]
>[  514.636078] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  514.636081] [drm:drm_atomic_state_init] Allocated atomic state ffff880210d7b400
>[  514.636084] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5490800 state to ffff880210d7b400
>[  514.636086] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f5fde000 state to ffff880210d7b400
>[  514.636089] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f5490800
>[  514.636090] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f5fde000 to [CRTC:25]
>[  514.636092] [drm:drm_atomic_set_fb_for_plane] Set [FB:51] for plane state ffff8801f5fde000
>[  514.636094] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800d3bba1e0 state to ffff880210d7b400
>[  514.636095] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b400
>[  514.636097] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800d3bba1e0 to [CRTC:25]
>[  514.636098] [drm:drm_atomic_check_only] checking ffff880210d7b400
>[  514.636100] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  514.636101] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  514.636103] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  514.636105] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  514.636106] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  514.636108] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  514.636109] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b400
>[  514.636111] [drm:drm_atomic_connectors_for_crtc] State ffff880210d7b400 has 1 connectors for [CRTC:25]
>[  514.636113] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b400
>[  514.636115] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  514.636116] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  514.636119] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  514.636121] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  514.636123] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff8801f5490800 for pipe B
>[  514.636124] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  514.636125] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  514.636127] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  514.636129] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  514.636131] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  514.636132] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  514.636133] [drm:intel_dump_pipe_config] requested mode:
>[  514.636136] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  514.636137] [drm:intel_dump_pipe_config] adjusted mode:
>[  514.636139] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  514.636141] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  514.636142] [drm:intel_dump_pipe_config] port clock: 270000
>[  514.636144] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  514.636145] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  514.636146] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  514.636148] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  514.636149] [drm:intel_dump_pipe_config] ips: 0
>[  514.636150] [drm:intel_dump_pipe_config] double wide: 0
>[  514.636152] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  514.636153] [drm:intel_dump_pipe_config] planes on this crtc
>[  514.636155] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  514.636157] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  514.636158] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  514.636160] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff8801f5493400 state to ffff880210d7b400
>[  514.636163] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff8801f5490c00 state to ffff880210d7b400
>[  514.636166] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 51
>[  514.636167] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  514.636170] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8801f5fdeb40 state to ffff880210d7b400
>[  514.636171] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8801f5fde600 state to ffff880210d7b400
>[  514.636173] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8801f5fdea80 state to ffff880210d7b400
>[  514.636177] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f5fde780 state to ffff880210d7b400
>[  514.636179] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f5fde180 state to ffff880210d7b400
>[  514.636181] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8801f5fde480 state to ffff880210d7b400
>[  514.636183] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8801f5fdee40 state to ffff880210d7b400
>[  514.636185] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8801f5fde6c0 state to ffff880210d7b400
>[  514.636187] [drm:drm_atomic_commit] commiting ffff880210d7b400
>[  514.636193] [drm:intel_power_well_enable] enabling display
>[  514.636195] [drm:hsw_set_power_well] Enabling power well
>[  514.638269] [drm:intel_power_well_enable] enabling always-on
>[  514.638281] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  514.638283] [drm:intel_enable_shared_dpll] enabling SPLL
>[  514.639175] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  514.639258] [drm:intel_enable_pipe] enabling pipe B
>[  514.639274] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  514.706112] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  514.706117] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  514.706118] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  514.706120] [drm:check_crtc_state] [CRTC:25]
>[  514.706131] [drm:check_shared_dpll_state] WRPLL 1
>[  514.706132] [drm:check_shared_dpll_state] WRPLL 2
>[  514.706133] [drm:check_shared_dpll_state] SPLL
>[  514.706135] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880210d7b400
>[  514.706138] [drm:drm_atomic_state_free] Freeing atomic state ffff880210d7b400
>[  514.706165] [drm:drm_mode_setcrtc] [CRTC:25]
>[  514.706167] [drm:drm_atomic_state_init] Allocated atomic state ffff88020103c000
>[  514.706169] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5327c00 state to ffff88020103c000
>[  514.706170] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f55af540 state to ffff88020103c000
>[  514.706171] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f5327c00
>[  514.706172] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55af540 to [NOCRTC]
>[  514.706173] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f55af540
>[  514.706174] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103c000
>[  514.706175] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c909bce0 state to ffff88020103c000
>[  514.706176] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c909bce0 to [NOCRTC]
>[  514.706177] [drm:drm_atomic_check_only] checking ffff88020103c000
>[  514.706179] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  514.706179] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  514.706180] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  514.706181] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  514.706182] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  514.706183] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  514.706184] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103c000
>[  514.706185] [drm:drm_atomic_connectors_for_crtc] State ffff88020103c000 has 0 connectors for [CRTC:25]
>[  514.706188] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  514.706189] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  514.706191] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f55af300 state to ffff88020103c000
>[  514.706192] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f55af6c0 state to ffff88020103c000
>[  514.706194] [drm:drm_atomic_commit] commiting ffff88020103c000
>[  514.722805] [drm:intel_disable_pipe] disabling pipe B
>[  514.757790] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  514.757793] [drm:intel_disable_shared_dpll] disabling SPLL
>[  514.757801] [drm:intel_power_well_disable] disabling display
>[  514.757803] [drm:hsw_set_power_well] Requesting to disable the power well
>[  514.757804] [drm:intel_power_well_disable] disabling always-on
>[  514.757805] [drm:intel_power_well_enable] enabling display
>[  514.757806] [drm:hsw_set_power_well] Enabling power well
>[  514.759875] [drm:intel_power_well_disable] disabling display
>[  514.759879] [drm:hsw_set_power_well] Requesting to disable the power well
>[  514.759884] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  514.759886] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  514.759888] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  514.759890] [drm:check_crtc_state] [CRTC:25]
>[  514.759892] [drm:check_shared_dpll_state] WRPLL 1
>[  514.759893] [drm:check_shared_dpll_state] WRPLL 2
>[  514.759894] [drm:check_shared_dpll_state] SPLL
>[  514.759896] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88020103c000
>[  514.759898] [drm:drm_atomic_state_free] Freeing atomic state ffff88020103c000
>[  514.759926] [drm:drm_mode_setcrtc] [CRTC:25]
>[  514.759929] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  514.759931] [drm:drm_atomic_state_init] Allocated atomic state ffff880210d7b800
>[  514.759933] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5490800 state to ffff880210d7b800
>[  514.759934] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f5fde180 state to ffff880210d7b800
>[  514.759935] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f5490800
>[  514.759937] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f5fde180 to [CRTC:25]
>[  514.759938] [drm:drm_atomic_set_fb_for_plane] Set [FB:49] for plane state ffff8801f5fde180
>[  514.759939] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800d3bba780 state to ffff880210d7b800
>[  514.759940] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b800
>[  514.759941] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800d3bba780 to [CRTC:25]
>[  514.759942] [drm:drm_atomic_check_only] checking ffff880210d7b800
>[  514.759943] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  514.759944] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  514.759945] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  514.759947] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  514.759947] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  514.759948] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  514.759949] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b800
>[  514.759950] [drm:drm_atomic_connectors_for_crtc] State ffff880210d7b800 has 1 connectors for [CRTC:25]
>[  514.759952] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880210d7b800
>[  514.759953] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  514.759954] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  514.759956] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  514.759957] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  514.759958] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff8801f5490800 for pipe B
>[  514.759959] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  514.759960] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  514.759961] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  514.759962] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  514.759963] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  514.759964] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  514.759965] [drm:intel_dump_pipe_config] requested mode:
>[  514.759966] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  514.759967] [drm:intel_dump_pipe_config] adjusted mode:
>[  514.759968] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  514.759970] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  514.759970] [drm:intel_dump_pipe_config] port clock: 270000
>[  514.759971] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  514.759972] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  514.759973] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  514.759974] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  514.759974] [drm:intel_dump_pipe_config] ips: 0
>[  514.759975] [drm:intel_dump_pipe_config] double wide: 0
>[  514.759976] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  514.759977] [drm:intel_dump_pipe_config] planes on this crtc
>[  514.759978] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  514.759979] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  514.759980] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  514.759982] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff8801f5491c00 state to ffff880210d7b800
>[  514.759983] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff8801f5493800 state to ffff880210d7b800
>[  514.759985] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 49
>[  514.759986] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  514.759988] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8801f5fde000 state to ffff880210d7b800
>[  514.759989] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8801f5fdecc0 state to ffff880210d7b800
>[  514.759990] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8801f5fde3c0 state to ffff880210d7b800
>[  514.759992] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f5fde900 state to ffff880210d7b800
>[  514.759993] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f5fde840 state to ffff880210d7b800
>[  514.759995] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8801f5fdef00 state to ffff880210d7b800
>[  514.759996] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8801f5fded80 state to ffff880210d7b800
>[  514.759997] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8801f5fdec00 state to ffff880210d7b800
>[  514.759998] [drm:drm_atomic_commit] commiting ffff880210d7b800
>[  514.760003] [drm:intel_power_well_enable] enabling display
>[  514.760004] [drm:hsw_set_power_well] Enabling power well
>[  514.761728] [drm:intel_power_well_enable] enabling always-on
>[  514.761738] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  514.761739] [drm:intel_enable_shared_dpll] enabling SPLL
>[  514.762629] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  514.762693] [drm:intel_enable_pipe] enabling pipe B
>[  514.762706] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  514.829574] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  514.829578] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  514.829579] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  514.829581] [drm:check_crtc_state] [CRTC:25]
>[  514.829593] [drm:check_shared_dpll_state] WRPLL 1
>[  514.829594] [drm:check_shared_dpll_state] WRPLL 2
>[  514.829595] [drm:check_shared_dpll_state] SPLL
>[  514.829596] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880210d7b800
>[  514.829600] [drm:drm_atomic_state_free] Freeing atomic state ffff880210d7b800
>[  514.829627] [drm:drm_mode_setcrtc] [CRTC:25]
>[  514.829629] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bf3800
>[  514.829631] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880215be6400 state to ffff880026bf3800
>[  514.829633] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8800d3b00a80 state to ffff880026bf3800
>[  514.829634] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff880215be6400
>[  514.829634] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800d3b00a80 to [NOCRTC]
>[  514.829635] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8800d3b00a80
>[  514.829637] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3800
>[  514.829638] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c0132220 state to ffff880026bf3800
>[  514.829639] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c0132220 to [NOCRTC]
>[  514.829639] [drm:drm_atomic_check_only] checking ffff880026bf3800
>[  514.829641] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  514.829641] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  514.829643] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  514.829643] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  514.829644] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  514.829645] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  514.829646] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3800
>[  514.829647] [drm:drm_atomic_connectors_for_crtc] State ffff880026bf3800 has 0 connectors for [CRTC:25]
>[  514.829650] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  514.829651] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  514.829653] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8800d3b000c0 state to ffff880026bf3800
>[  514.829654] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8800d3b00000 state to ffff880026bf3800
>[  514.829656] [drm:drm_atomic_commit] commiting ffff880026bf3800
>[  514.846248] [drm:intel_disable_pipe] disabling pipe B
>[  514.846806] [drm:intel_print_rc6_info] Enabling RC6 states: RC6 on
>[  514.850702] [drm:gen6_enable_rps] Overclocking supported. Max: 1100MHz, Overclock max: 1100MHz
>[  514.881086] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  514.881088] [drm:intel_disable_shared_dpll] disabling SPLL
>[  514.881096] [drm:intel_power_well_disable] disabling display
>[  514.881098] [drm:hsw_set_power_well] Requesting to disable the power well
>[  514.881099] [drm:intel_power_well_disable] disabling always-on
>[  514.881100] [drm:intel_power_well_enable] enabling display
>[  514.881101] [drm:hsw_set_power_well] Enabling power well
>[  514.883141] [drm:intel_power_well_disable] disabling display
>[  514.883144] [drm:hsw_set_power_well] Requesting to disable the power well
>[  514.883149] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  514.883151] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  514.883153] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  514.883155] [drm:check_crtc_state] [CRTC:25]
>[  514.883157] [drm:check_shared_dpll_state] WRPLL 1
>[  514.883158] [drm:check_shared_dpll_state] WRPLL 2
>[  514.883159] [drm:check_shared_dpll_state] SPLL
>[  514.883161] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bf3800
>[  514.883163] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bf3800
>[  514.883190] [drm:drm_mode_setcrtc] [CRTC:25]
>[  514.883194] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  514.883195] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bf3800
>[  514.883197] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880215be4400 state to ffff880026bf3800
>[  514.883199] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8800d3b00480 state to ffff880026bf3800
>[  514.883200] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff880215be4400
>[  514.883201] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800d3b00480 to [CRTC:25]
>[  514.883202] [drm:drm_atomic_set_fb_for_plane] Set [FB:51] for plane state ffff8800d3b00480
>[  514.883203] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c01326a0 state to ffff880026bf3800
>[  514.883204] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3800
>[  514.883205] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c01326a0 to [CRTC:25]
>[  514.883206] [drm:drm_atomic_check_only] checking ffff880026bf3800
>[  514.883208] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  514.883208] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  514.883209] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  514.883211] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  514.883211] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  514.883212] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  514.883213] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3800
>[  514.883214] [drm:drm_atomic_connectors_for_crtc] State ffff880026bf3800 has 1 connectors for [CRTC:25]
>[  514.883216] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3800
>[  514.883217] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  514.883218] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  514.883220] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  514.883221] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  514.883222] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff880215be4400 for pipe B
>[  514.883223] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  514.883224] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  514.883225] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  514.883226] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  514.883227] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  514.883228] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  514.883228] [drm:intel_dump_pipe_config] requested mode:
>[  514.883230] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  514.883231] [drm:intel_dump_pipe_config] adjusted mode:
>[  514.883232] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  514.883233] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  514.883234] [drm:intel_dump_pipe_config] port clock: 270000
>[  514.883235] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  514.883236] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  514.883237] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  514.883238] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  514.883238] [drm:intel_dump_pipe_config] ips: 0
>[  514.883239] [drm:intel_dump_pipe_config] double wide: 0
>[  514.883240] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  514.883241] [drm:intel_dump_pipe_config] planes on this crtc
>[  514.883242] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  514.883243] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  514.883244] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  514.883246] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff880215be5c00 state to ffff880026bf3800
>[  514.883247] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff880215be4000 state to ffff880026bf3800
>[  514.883249] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 51
>[  514.883250] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  514.883252] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8800d3b00e40 state to ffff880026bf3800
>[  514.883253] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8800d3b00cc0 state to ffff880026bf3800
>[  514.883254] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8800d3b00f00 state to ffff880026bf3800
>[  514.883256] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8800d3b00780 state to ffff880026bf3800
>[  514.883257] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8800d3b003c0 state to ffff880026bf3800
>[  514.883259] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8800d3b00900 state to ffff880026bf3800
>[  514.883260] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8800d3b00300 state to ffff880026bf3800
>[  514.883261] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8800d3b00b40 state to ffff880026bf3800
>[  514.883263] [drm:drm_atomic_commit] commiting ffff880026bf3800
>[  514.883267] [drm:intel_power_well_enable] enabling display
>[  514.883268] [drm:hsw_set_power_well] Enabling power well
>[  514.884719] [drm:intel_power_well_enable] enabling always-on
>[  514.884730] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  514.884732] [drm:intel_enable_shared_dpll] enabling SPLL
>[  514.885622] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  514.885687] [drm:intel_enable_pipe] enabling pipe B
>[  514.885707] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  514.952575] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  514.952579] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  514.952581] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  514.952582] [drm:check_crtc_state] [CRTC:25]
>[  514.952594] [drm:check_shared_dpll_state] WRPLL 1
>[  514.952595] [drm:check_shared_dpll_state] WRPLL 2
>[  514.952596] [drm:check_shared_dpll_state] SPLL
>[  514.952597] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bf3800
>[  514.952602] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bf3800
>[  514.952649] [drm:drm_mode_setcrtc] [CRTC:25]
>[  514.952652] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bfbc00
>[  514.952654] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880025a40c00 state to ffff880026bfbc00
>[  514.952655] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8800c78d4d80 state to ffff880026bfbc00
>[  514.952656] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff880025a40c00
>[  514.952658] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800c78d4d80 to [NOCRTC]
>[  514.952659] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8800c78d4d80
>[  514.952662] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfbc00
>[  514.952663] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8801f442d1e0 state to ffff880026bfbc00
>[  514.952664] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f442d1e0 to [NOCRTC]
>[  514.952664] [drm:drm_atomic_check_only] checking ffff880026bfbc00
>[  514.952666] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  514.952667] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  514.952668] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  514.952669] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  514.952669] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  514.952670] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  514.952671] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfbc00
>[  514.952673] [drm:drm_atomic_connectors_for_crtc] State ffff880026bfbc00 has 0 connectors for [CRTC:25]
>[  514.952675] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  514.952676] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  514.952678] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8800c78d4180 state to ffff880026bfbc00
>[  514.952679] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8800c78d4000 state to ffff880026bfbc00
>[  514.952681] [drm:drm_atomic_commit] commiting ffff880026bfbc00
>[  514.969244] [drm:intel_disable_pipe] disabling pipe B
>[  515.002889] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  515.002892] [drm:intel_disable_shared_dpll] disabling SPLL
>[  515.002900] [drm:intel_power_well_disable] disabling display
>[  515.002902] [drm:hsw_set_power_well] Requesting to disable the power well
>[  515.002903] [drm:intel_power_well_disable] disabling always-on
>[  515.002911] [drm:intel_runtime_suspend] Suspending device
>[  515.003011] [drm:hsw_enable_pc8] Enabling package C8+
>[  515.014755] [drm:intel_runtime_suspend] Device suspended
>[  515.020710] [drm:intel_runtime_resume] Resuming device
>[  515.022778] [drm:hsw_disable_pc8] Disabling package C8+
>[  515.026717] [drm:intel_update_cdclk] Current CD clock rate: 540000 kHz
>[  515.139846] [drm:intel_runtime_resume] Device resumed
>[  515.139850] [drm:intel_power_well_enable] enabling display
>[  515.139852] [drm:hsw_set_power_well] Enabling power well
>[  515.141921] [drm:intel_power_well_disable] disabling display
>[  515.141925] [drm:hsw_set_power_well] Requesting to disable the power well
>[  515.141930] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  515.141932] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  515.141934] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  515.141936] [drm:check_crtc_state] [CRTC:25]
>[  515.141938] [drm:check_shared_dpll_state] WRPLL 1
>[  515.141939] [drm:check_shared_dpll_state] WRPLL 2
>[  515.141940] [drm:check_shared_dpll_state] SPLL
>[  515.141942] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bfbc00
>[  515.141944] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bfbc00
>[  515.141972] [drm:drm_mode_setcrtc] [CRTC:25]
>[  515.141976] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  515.141977] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bf2800
>[  515.141979] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880215be4400 state to ffff880026bf2800
>[  515.141981] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8800d3b003c0 state to ffff880026bf2800
>[  515.141982] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff880215be4400
>[  515.141983] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800d3b003c0 to [CRTC:25]
>[  515.141984] [drm:drm_atomic_set_fb_for_plane] Set [FB:49] for plane state ffff8800d3b003c0
>[  515.141985] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c01320e0 state to ffff880026bf2800
>[  515.141986] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf2800
>[  515.141987] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c01320e0 to [CRTC:25]
>[  515.141988] [drm:drm_atomic_check_only] checking ffff880026bf2800
>[  515.141990] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  515.141990] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  515.141992] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  515.141993] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  515.141994] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  515.141995] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  515.141995] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf2800
>[  515.141997] [drm:drm_atomic_connectors_for_crtc] State ffff880026bf2800 has 1 connectors for [CRTC:25]
>[  515.141998] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf2800
>[  515.142000] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  515.142000] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  515.142002] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  515.142003] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  515.142004] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff880215be4400 for pipe B
>[  515.142005] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  515.142006] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  515.142007] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  515.142008] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  515.142009] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  515.142010] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  515.142011] [drm:intel_dump_pipe_config] requested mode:
>[  515.142012] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  515.142013] [drm:intel_dump_pipe_config] adjusted mode:
>[  515.142015] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  515.142016] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  515.142017] [drm:intel_dump_pipe_config] port clock: 270000
>[  515.142017] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  515.142018] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  515.142019] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  515.142020] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  515.142021] [drm:intel_dump_pipe_config] ips: 0
>[  515.142022] [drm:intel_dump_pipe_config] double wide: 0
>[  515.142023] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  515.142023] [drm:intel_dump_pipe_config] planes on this crtc
>[  515.142025] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  515.142026] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  515.142027] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  515.142028] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff880215be5000 state to ffff880026bf2800
>[  515.142030] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff880215be4800 state to ffff880026bf2800
>[  515.142032] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 49
>[  515.142033] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  515.142034] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8800d3b00480 state to ffff880026bf2800
>[  515.142035] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8800d3b00c00 state to ffff880026bf2800
>[  515.142036] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8800d3b009c0 state to ffff880026bf2800
>[  515.142039] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8800d3b006c0 state to ffff880026bf2800
>[  515.142040] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8800d3b00180 state to ffff880026bf2800
>[  515.142041] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8800d3b00240 state to ffff880026bf2800
>[  515.142043] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8800d3b00000 state to ffff880026bf2800
>[  515.142044] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8800d3b000c0 state to ffff880026bf2800
>[  515.142045] [drm:drm_atomic_commit] commiting ffff880026bf2800
>[  515.142050] [drm:intel_power_well_enable] enabling display
>[  515.142051] [drm:hsw_set_power_well] Enabling power well
>[  515.144119] [drm:intel_power_well_enable] enabling always-on
>[  515.144129] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  515.144130] [drm:intel_enable_shared_dpll] enabling SPLL
>[  515.145020] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  515.145085] [drm:intel_enable_pipe] enabling pipe B
>[  515.145100] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  515.211969] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  515.211974] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  515.211975] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  515.211977] [drm:check_crtc_state] [CRTC:25]
>[  515.211988] [drm:check_shared_dpll_state] WRPLL 1
>[  515.211989] [drm:check_shared_dpll_state] WRPLL 2
>[  515.211990] [drm:check_shared_dpll_state] SPLL
>[  515.211992] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bf2800
>[  515.211996] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bf2800
>[  515.212022] [drm:drm_mode_setcrtc] [CRTC:25]
>[  515.212024] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bf2800
>[  515.212026] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880215be4000 state to ffff880026bf2800
>[  515.212027] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8800d3b00b40 state to ffff880026bf2800
>[  515.212028] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff880215be4000
>[  515.212029] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800d3b00b40 to [NOCRTC]
>[  515.212030] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8800d3b00b40
>[  515.212031] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf2800
>[  515.212032] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c01326c0 state to ffff880026bf2800
>[  515.212033] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c01326c0 to [NOCRTC]
>[  515.212034] [drm:drm_atomic_check_only] checking ffff880026bf2800
>[  515.212036] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  515.212036] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  515.212037] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  515.212038] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  515.212039] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  515.212040] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  515.212041] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf2800
>[  515.212042] [drm:drm_atomic_connectors_for_crtc] State ffff880026bf2800 has 0 connectors for [CRTC:25]
>[  515.212045] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  515.212046] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  515.212048] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8800d3b00300 state to ffff880026bf2800
>[  515.212049] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8800d3b00900 state to ffff880026bf2800
>[  515.212051] [drm:drm_atomic_commit] commiting ffff880026bf2800
>[  515.228634] [drm:intel_disable_pipe] disabling pipe B
>[  515.263682] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  515.263685] [drm:intel_disable_shared_dpll] disabling SPLL
>[  515.263693] [drm:intel_power_well_disable] disabling display
>[  515.263694] [drm:hsw_set_power_well] Requesting to disable the power well
>[  515.263695] [drm:intel_power_well_disable] disabling always-on
>[  515.263697] [drm:intel_power_well_enable] enabling display
>[  515.263698] [drm:hsw_set_power_well] Enabling power well
>[  515.265767] [drm:intel_power_well_disable] disabling display
>[  515.265771] [drm:hsw_set_power_well] Requesting to disable the power well
>[  515.265776] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  515.265778] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  515.265780] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  515.265783] [drm:check_crtc_state] [CRTC:25]
>[  515.265784] [drm:check_shared_dpll_state] WRPLL 1
>[  515.265785] [drm:check_shared_dpll_state] WRPLL 2
>[  515.265786] [drm:check_shared_dpll_state] SPLL
>[  515.265788] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bf2800
>[  515.265791] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bf2800
>[  515.265818] [drm:drm_mode_setcrtc] [CRTC:25]
>[  515.265822] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  515.265824] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bfb200
>[  515.265826] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880025a42800 state to ffff880026bfb200
>[  515.265828] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8800c78d4300 state to ffff880026bfb200
>[  515.265829] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff880025a42800
>[  515.265830] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800c78d4300 to [CRTC:25]
>[  515.265831] [drm:drm_atomic_set_fb_for_plane] Set [FB:51] for plane state ffff8800c78d4300
>[  515.265833] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8801f442dc60 state to ffff880026bfb200
>[  515.265834] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfb200
>[  515.265835] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f442dc60 to [CRTC:25]
>[  515.265836] [drm:drm_atomic_check_only] checking ffff880026bfb200
>[  515.265837] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  515.265838] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  515.265839] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  515.265840] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  515.265841] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  515.265842] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  515.265843] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfb200
>[  515.265844] [drm:drm_atomic_connectors_for_crtc] State ffff880026bfb200 has 1 connectors for [CRTC:25]
>[  515.265846] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfb200
>[  515.265847] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  515.265848] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  515.265849] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  515.265850] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  515.265852] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff880025a42800 for pipe B
>[  515.265852] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  515.265853] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  515.265854] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  515.265855] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  515.265856] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  515.265857] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  515.265858] [drm:intel_dump_pipe_config] requested mode:
>[  515.265859] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  515.265860] [drm:intel_dump_pipe_config] adjusted mode:
>[  515.265861] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  515.265863] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  515.265863] [drm:intel_dump_pipe_config] port clock: 270000
>[  515.265864] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  515.265865] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  515.265866] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  515.265867] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  515.265868] [drm:intel_dump_pipe_config] ips: 0
>[  515.265868] [drm:intel_dump_pipe_config] double wide: 0
>[  515.265869] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  515.265870] [drm:intel_dump_pipe_config] planes on this crtc
>[  515.265871] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  515.265872] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  515.265873] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  515.265875] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff880025a40c00 state to ffff880026bfb200
>[  515.265876] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff880025a43c00 state to ffff880026bfb200
>[  515.265878] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 51
>[  515.265879] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  515.265881] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8800c78d4600 state to ffff880026bfb200
>[  515.265882] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8800c78d4240 state to ffff880026bfb200
>[  515.265883] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8800c78d4cc0 state to ffff880026bfb200
>[  515.265886] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8800c78d46c0 state to ffff880026bfb200
>[  515.265887] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8800c78d4000 state to ffff880026bfb200
>[  515.265889] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8800c78d4180 state to ffff880026bfb200
>[  515.265890] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8800c78d4d80 state to ffff880026bfb200
>[  515.265891] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8800c78d4900 state to ffff880026bfb200
>[  515.265892] [drm:drm_atomic_commit] commiting ffff880026bfb200
>[  515.265897] [drm:intel_power_well_enable] enabling display
>[  515.265898] [drm:hsw_set_power_well] Enabling power well
>[  515.267967] [drm:intel_power_well_enable] enabling always-on
>[  515.267978] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  515.267979] [drm:intel_enable_shared_dpll] enabling SPLL
>[  515.268869] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  515.268934] [drm:intel_enable_pipe] enabling pipe B
>[  515.268948] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  515.335816] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  515.335820] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  515.335821] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  515.335823] [drm:check_crtc_state] [CRTC:25]
>[  515.335834] [drm:check_shared_dpll_state] WRPLL 1
>[  515.335836] [drm:check_shared_dpll_state] WRPLL 2
>[  515.335837] [drm:check_shared_dpll_state] SPLL
>[  515.335838] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bfb200
>[  515.335842] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bfb200
>[  515.335869] [drm:drm_mode_setcrtc] [CRTC:25]
>[  515.335871] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bfb200
>[  515.335873] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880025a40800 state to ffff880026bfb200
>[  515.335875] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8800c78d4c00 state to ffff880026bfb200
>[  515.335875] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff880025a40800
>[  515.335876] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800c78d4c00 to [NOCRTC]
>[  515.335877] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8800c78d4c00
>[  515.335879] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfb200
>[  515.335880] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8801f442da20 state to ffff880026bfb200
>[  515.335881] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f442da20 to [NOCRTC]
>[  515.335881] [drm:drm_atomic_check_only] checking ffff880026bfb200
>[  515.335883] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  515.335884] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  515.335885] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  515.335886] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  515.335886] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  515.335887] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  515.335888] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfb200
>[  515.335890] [drm:drm_atomic_connectors_for_crtc] State ffff880026bfb200 has 0 connectors for [CRTC:25]
>[  515.335892] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  515.335893] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  515.335895] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8800c78d4480 state to ffff880026bfb200
>[  515.335896] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8800c78d4780 state to ffff880026bfb200
>[  515.335898] [drm:drm_atomic_commit] commiting ffff880026bfb200
>[  515.352480] [drm:intel_disable_pipe] disabling pipe B
>[  515.387254] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  515.387257] [drm:intel_disable_shared_dpll] disabling SPLL
>[  515.387265] [drm:intel_power_well_disable] disabling display
>[  515.387267] [drm:hsw_set_power_well] Requesting to disable the power well
>[  515.387268] [drm:intel_power_well_disable] disabling always-on
>[  515.387269] [drm:intel_power_well_enable] enabling display
>[  515.387270] [drm:hsw_set_power_well] Enabling power well
>[  515.388674] [drm:intel_power_well_disable] disabling display
>[  515.388678] [drm:hsw_set_power_well] Requesting to disable the power well
>[  515.388684] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  515.388687] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  515.388688] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  515.388691] [drm:check_crtc_state] [CRTC:25]
>[  515.388693] [drm:check_shared_dpll_state] WRPLL 1
>[  515.388694] [drm:check_shared_dpll_state] WRPLL 2
>[  515.388695] [drm:check_shared_dpll_state] SPLL
>[  515.388697] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bfb200
>[  515.388700] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bfb200
>[  515.388725] [drm:drm_mode_setcrtc] [CRTC:25]
>[  515.388728] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  515.388730] [drm:drm_atomic_state_init] Allocated atomic state ffff88020103d200
>[  515.388733] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5324400 state to ffff88020103d200
>[  515.388735] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f55af840 state to ffff88020103d200
>[  515.388737] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f5324400
>[  515.388738] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55af840 to [CRTC:25]
>[  515.388739] [drm:drm_atomic_set_fb_for_plane] Set [FB:49] for plane state ffff8801f55af840
>[  515.388740] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c909b180 state to ffff88020103d200
>[  515.388742] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103d200
>[  515.388743] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c909b180 to [CRTC:25]
>[  515.388745] [drm:drm_atomic_check_only] checking ffff88020103d200
>[  515.388746] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  515.388747] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  515.388748] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  515.388750] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  515.388751] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  515.388751] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  515.388752] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103d200
>[  515.388754] [drm:drm_atomic_connectors_for_crtc] State ffff88020103d200 has 1 connectors for [CRTC:25]
>[  515.388755] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103d200
>[  515.388757] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  515.388758] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  515.388760] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  515.388761] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  515.388763] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff8801f5324400 for pipe B
>[  515.388764] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  515.388765] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  515.388766] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  515.388768] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  515.388769] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  515.388771] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  515.388771] [drm:intel_dump_pipe_config] requested mode:
>[  515.388773] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  515.388774] [drm:intel_dump_pipe_config] adjusted mode:
>[  515.388776] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  515.388778] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  515.388779] [drm:intel_dump_pipe_config] port clock: 270000
>[  515.388780] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  515.388781] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  515.388782] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  515.388783] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  515.388784] [drm:intel_dump_pipe_config] ips: 0
>[  515.388785] [drm:intel_dump_pipe_config] double wide: 0
>[  515.388786] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  515.388787] [drm:intel_dump_pipe_config] planes on this crtc
>[  515.388788] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  515.388789] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  515.388790] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  515.388792] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff8801f5324000 state to ffff88020103d200
>[  515.388793] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff8801f5327800 state to ffff88020103d200
>[  515.388795] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 49
>[  515.388796] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  515.388798] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8801f55afa80 state to ffff88020103d200
>[  515.388799] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8801f55aff00 state to ffff88020103d200
>[  515.388800] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8801f55af780 state to ffff88020103d200
>[  515.388803] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f55af600 state to ffff88020103d200
>[  515.388804] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f55af480 state to ffff88020103d200
>[  515.388806] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8801f55af000 state to ffff88020103d200
>[  515.388807] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8801f55af180 state to ffff88020103d200
>[  515.388808] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8801f55af900 state to ffff88020103d200
>[  515.388810] [drm:drm_atomic_commit] commiting ffff88020103d200
>[  515.388815] [drm:intel_power_well_enable] enabling display
>[  515.388816] [drm:hsw_set_power_well] Enabling power well
>[  515.390884] [drm:intel_power_well_enable] enabling always-on
>[  515.390894] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  515.390895] [drm:intel_enable_shared_dpll] enabling SPLL
>[  515.391785] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  515.391849] [drm:intel_enable_pipe] enabling pipe B
>[  515.391863] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  515.458701] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  515.458705] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  515.458707] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  515.458708] [drm:check_crtc_state] [CRTC:25]
>[  515.458720] [drm:check_shared_dpll_state] WRPLL 1
>[  515.458721] [drm:check_shared_dpll_state] WRPLL 2
>[  515.458722] [drm:check_shared_dpll_state] SPLL
>[  515.458724] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88020103d200
>[  515.458727] [drm:drm_atomic_state_free] Freeing atomic state ffff88020103d200
>[  515.458754] [drm:drm_mode_setcrtc] [CRTC:25]
>[  515.458756] [drm:drm_atomic_state_init] Allocated atomic state ffff88020103d200
>[  515.458758] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5326400 state to ffff88020103d200
>[  515.458759] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f55af240 state to ffff88020103d200
>[  515.458760] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f5326400
>[  515.458761] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55af240 to [NOCRTC]
>[  515.458762] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f55af240
>[  515.458763] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103d200
>[  515.458764] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c909bc60 state to ffff88020103d200
>[  515.458765] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c909bc60 to [NOCRTC]
>[  515.458766] [drm:drm_atomic_check_only] checking ffff88020103d200
>[  515.458768] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  515.458768] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  515.458769] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  515.458770] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  515.458771] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  515.458772] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  515.458773] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103d200
>[  515.458774] [drm:drm_atomic_connectors_for_crtc] State ffff88020103d200 has 0 connectors for [CRTC:25]
>[  515.458777] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  515.458778] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  515.458780] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f55afcc0 state to ffff88020103d200
>[  515.458781] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f55afc00 state to ffff88020103d200
>[  515.458783] [drm:drm_atomic_commit] commiting ffff88020103d200
>[  515.475394] [drm:intel_disable_pipe] disabling pipe B
>[  515.509721] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  515.509724] [drm:intel_disable_shared_dpll] disabling SPLL
>[  515.509732] [drm:intel_power_well_disable] disabling display
>[  515.509733] [drm:hsw_set_power_well] Requesting to disable the power well
>[  515.509734] [drm:intel_power_well_disable] disabling always-on
>[  515.509736] [drm:intel_power_well_enable] enabling display
>[  515.509737] [drm:hsw_set_power_well] Enabling power well
>[  515.511806] [drm:intel_power_well_disable] disabling display
>[  515.511810] [drm:hsw_set_power_well] Requesting to disable the power well
>[  515.511815] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  515.511817] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  515.511818] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  515.511821] [drm:check_crtc_state] [CRTC:25]
>[  515.511822] [drm:check_shared_dpll_state] WRPLL 1
>[  515.511824] [drm:check_shared_dpll_state] WRPLL 2
>[  515.511825] [drm:check_shared_dpll_state] SPLL
>[  515.511827] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88020103d200
>[  515.511829] [drm:drm_atomic_state_free] Freeing atomic state ffff88020103d200
>[  515.511857] [drm:drm_mode_setcrtc] [CRTC:25]
>[  515.511860] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  515.511862] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bf2600
>[  515.511864] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880215be5c00 state to ffff880026bf2600
>[  515.511866] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8800d3b00f00 state to ffff880026bf2600
>[  515.511867] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff880215be5c00
>[  515.511868] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800d3b00f00 to [CRTC:25]
>[  515.511869] [drm:drm_atomic_set_fb_for_plane] Set [FB:51] for plane state ffff8800d3b00f00
>[  515.511871] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c0132840 state to ffff880026bf2600
>[  515.511872] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf2600
>[  515.511873] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c0132840 to [CRTC:25]
>[  515.511874] [drm:drm_atomic_check_only] checking ffff880026bf2600
>[  515.511875] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  515.511876] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  515.511877] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  515.511878] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  515.511879] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  515.511880] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  515.511881] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf2600
>[  515.511882] [drm:drm_atomic_connectors_for_crtc] State ffff880026bf2600 has 1 connectors for [CRTC:25]
>[  515.511883] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf2600
>[  515.511885] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  515.511886] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  515.511887] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  515.511888] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  515.511890] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff880215be5c00 for pipe B
>[  515.511891] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  515.511891] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  515.511892] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  515.511894] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  515.511895] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  515.511895] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  515.511896] [drm:intel_dump_pipe_config] requested mode:
>[  515.511898] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  515.511899] [drm:intel_dump_pipe_config] adjusted mode:
>[  515.511900] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  515.511901] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  515.511902] [drm:intel_dump_pipe_config] port clock: 270000
>[  515.511903] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  515.511903] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  515.511904] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  515.511905] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  515.511906] [drm:intel_dump_pipe_config] ips: 0
>[  515.511907] [drm:intel_dump_pipe_config] double wide: 0
>[  515.511908] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  515.511909] [drm:intel_dump_pipe_config] planes on this crtc
>[  515.511910] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  515.511911] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  515.511912] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  515.511914] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff880215be4800 state to ffff880026bf2600
>[  515.511915] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff880215be4000 state to ffff880026bf2600
>[  515.511917] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 51
>[  515.511918] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  515.511920] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8800d3b00e40 state to ffff880026bf2600
>[  515.511921] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8800d3b00a80 state to ffff880026bf2600
>[  515.511922] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8800d3b000c0 state to ffff880026bf2600
>[  515.511925] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8800d3b00000 state to ffff880026bf2600
>[  515.511926] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8800d3b00240 state to ffff880026bf2600
>[  515.511928] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8800d3b00900 state to ffff880026bf2600
>[  515.511929] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8800d3b00300 state to ffff880026bf2600
>[  515.511930] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8800d3b00b40 state to ffff880026bf2600
>[  515.511931] [drm:drm_atomic_commit] commiting ffff880026bf2600
>[  515.511936] [drm:intel_power_well_enable] enabling display
>[  515.511937] [drm:hsw_set_power_well] Enabling power well
>[  515.514005] [drm:intel_power_well_enable] enabling always-on
>[  515.514016] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  515.514017] [drm:intel_enable_shared_dpll] enabling SPLL
>[  515.515557] [drm:hsw_fdi_link_train] FDI link training done on step 1
>[  515.515619] [drm:intel_enable_pipe] enabling pipe B
>[  515.515632] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  515.582468] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  515.582473] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  515.582474] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  515.582476] [drm:check_crtc_state] [CRTC:25]
>[  515.582487] [drm:check_shared_dpll_state] WRPLL 1
>[  515.582488] [drm:check_shared_dpll_state] WRPLL 2
>[  515.582489] [drm:check_shared_dpll_state] SPLL
>[  515.582491] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bf2600
>[  515.582493] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bf2600
>[  515.582521] [drm:drm_mode_setcrtc] [CRTC:25]
>[  515.582523] [drm:drm_atomic_state_init] Allocated atomic state ffff88020103d200
>[  515.582525] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5327800 state to ffff88020103d200
>[  515.582526] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f55af900 state to ffff88020103d200
>[  515.582528] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f5327800
>[  515.582528] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55af900 to [NOCRTC]
>[  515.582529] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f55af900
>[  515.582531] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103d200
>[  515.582532] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c909b120 state to ffff88020103d200
>[  515.582533] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c909b120 to [NOCRTC]
>[  515.582534] [drm:drm_atomic_check_only] checking ffff88020103d200
>[  515.582535] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  515.582536] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  515.582537] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  515.582538] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  515.582538] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  515.582539] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  515.582540] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103d200
>[  515.582541] [drm:drm_atomic_connectors_for_crtc] State ffff88020103d200 has 0 connectors for [CRTC:25]
>[  515.582544] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  515.582545] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  515.582547] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f55af180 state to ffff88020103d200
>[  515.582548] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f55af000 state to ffff88020103d200
>[  515.582550] [drm:drm_atomic_commit] commiting ffff88020103d200
>[  515.599161] [drm:intel_disable_pipe] disabling pipe B
>[  515.633688] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  515.633691] [drm:intel_disable_shared_dpll] disabling SPLL
>[  515.633699] [drm:intel_power_well_disable] disabling display
>[  515.633701] [drm:hsw_set_power_well] Requesting to disable the power well
>[  515.633702] [drm:intel_power_well_disable] disabling always-on
>[  515.633703] [drm:intel_power_well_enable] enabling display
>[  515.633704] [drm:hsw_set_power_well] Enabling power well
>[  515.635774] [drm:intel_power_well_disable] disabling display
>[  515.635778] [drm:hsw_set_power_well] Requesting to disable the power well
>[  515.635783] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  515.635785] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  515.635786] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  515.635789] [drm:check_crtc_state] [CRTC:25]
>[  515.635790] [drm:check_shared_dpll_state] WRPLL 1
>[  515.635792] [drm:check_shared_dpll_state] WRPLL 2
>[  515.635792] [drm:check_shared_dpll_state] SPLL
>[  515.635794] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88020103d200
>[  515.635797] [drm:drm_atomic_state_free] Freeing atomic state ffff88020103d200
>[  515.635825] [drm:drm_mode_setcrtc] [CRTC:25]
>[  515.635828] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  515.635830] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bf2400
>[  515.635832] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880215be5c00 state to ffff880026bf2400
>[  515.635833] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8800d3b00240 state to ffff880026bf2400
>[  515.635835] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff880215be5c00
>[  515.635836] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800d3b00240 to [CRTC:25]
>[  515.635837] [drm:drm_atomic_set_fb_for_plane] Set [FB:49] for plane state ffff8800d3b00240
>[  515.635838] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c0132c00 state to ffff880026bf2400
>[  515.635839] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf2400
>[  515.635840] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c0132c00 to [CRTC:25]
>[  515.635841] [drm:drm_atomic_check_only] checking ffff880026bf2400
>[  515.635842] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  515.635843] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  515.635844] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  515.635846] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  515.635846] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  515.635847] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  515.635848] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf2400
>[  515.635849] [drm:drm_atomic_connectors_for_crtc] State ffff880026bf2400 has 1 connectors for [CRTC:25]
>[  515.635851] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf2400
>[  515.635852] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  515.635853] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  515.635855] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  515.635856] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  515.635857] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff880215be5c00 for pipe B
>[  515.635858] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  515.635858] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  515.635860] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  515.635861] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  515.635862] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  515.635863] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  515.635863] [drm:intel_dump_pipe_config] requested mode:
>[  515.635865] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  515.635866] [drm:intel_dump_pipe_config] adjusted mode:
>[  515.635867] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  515.635868] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  515.635869] [drm:intel_dump_pipe_config] port clock: 270000
>[  515.635870] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  515.635870] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  515.635871] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  515.635872] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  515.635873] [drm:intel_dump_pipe_config] ips: 0
>[  515.635874] [drm:intel_dump_pipe_config] double wide: 0
>[  515.635875] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  515.635876] [drm:intel_dump_pipe_config] planes on this crtc
>[  515.635877] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  515.635878] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  515.635879] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  515.635880] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff880215be5000 state to ffff880026bf2400
>[  515.635881] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff880215be4400 state to ffff880026bf2400
>[  515.635883] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 49
>[  515.635884] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  515.635886] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8800d3b00f00 state to ffff880026bf2400
>[  515.635887] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8800d3b00cc0 state to ffff880026bf2400
>[  515.635888] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8800d3b009c0 state to ffff880026bf2400
>[  515.635891] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8800d3b00c00 state to ffff880026bf2400
>[  515.635892] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8800d3b00480 state to ffff880026bf2400
>[  515.635893] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8800d3b00180 state to ffff880026bf2400
>[  515.635895] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8800d3b006c0 state to ffff880026bf2400
>[  515.635896] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8800d3b003c0 state to ffff880026bf2400
>[  515.635897] [drm:drm_atomic_commit] commiting ffff880026bf2400
>[  515.635902] [drm:intel_power_well_enable] enabling display
>[  515.635903] [drm:hsw_set_power_well] Enabling power well
>[  515.637973] [drm:intel_power_well_enable] enabling always-on
>[  515.637983] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  515.637984] [drm:intel_enable_shared_dpll] enabling SPLL
>[  515.638873] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  515.638937] [drm:intel_enable_pipe] enabling pipe B
>[  515.638950] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  515.705787] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  515.705792] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  515.705793] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  515.705795] [drm:check_crtc_state] [CRTC:25]
>[  515.705806] [drm:check_shared_dpll_state] WRPLL 1
>[  515.705807] [drm:check_shared_dpll_state] WRPLL 2
>[  515.705808] [drm:check_shared_dpll_state] SPLL
>[  515.705810] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bf2400
>[  515.705813] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bf2400
>[  515.705840] [drm:drm_mode_setcrtc] [CRTC:25]
>[  515.705842] [drm:drm_atomic_state_init] Allocated atomic state ffff88020103c000
>[  515.705844] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5327800 state to ffff88020103c000
>[  515.705845] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f55af000 state to ffff88020103c000
>[  515.705846] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f5327800
>[  515.705847] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55af000 to [NOCRTC]
>[  515.705848] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f55af000
>[  515.705849] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103c000
>[  515.705850] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c909b1a0 state to ffff88020103c000
>[  515.705851] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c909b1a0 to [NOCRTC]
>[  515.705852] [drm:drm_atomic_check_only] checking ffff88020103c000
>[  515.705854] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  515.705854] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  515.705855] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  515.705856] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  515.705857] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  515.705858] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  515.705859] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103c000
>[  515.705860] [drm:drm_atomic_connectors_for_crtc] State ffff88020103c000 has 0 connectors for [CRTC:25]
>[  515.705863] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  515.705864] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  515.705866] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f55af180 state to ffff88020103c000
>[  515.705867] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f55af900 state to ffff88020103c000
>[  515.705869] [drm:drm_atomic_commit] commiting ffff88020103c000
>[  515.722478] [drm:intel_disable_pipe] disabling pipe B
>[  515.756960] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  515.756963] [drm:intel_disable_shared_dpll] disabling SPLL
>[  515.756971] [drm:intel_power_well_disable] disabling display
>[  515.756972] [drm:hsw_set_power_well] Requesting to disable the power well
>[  515.756973] [drm:intel_power_well_disable] disabling always-on
>[  515.756975] [drm:intel_power_well_enable] enabling display
>[  515.756976] [drm:hsw_set_power_well] Enabling power well
>[  515.759045] [drm:intel_power_well_disable] disabling display
>[  515.759049] [drm:hsw_set_power_well] Requesting to disable the power well
>[  515.759054] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  515.759056] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  515.759057] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  515.759060] [drm:check_crtc_state] [CRTC:25]
>[  515.759061] [drm:check_shared_dpll_state] WRPLL 1
>[  515.759063] [drm:check_shared_dpll_state] WRPLL 2
>[  515.759063] [drm:check_shared_dpll_state] SPLL
>[  515.759065] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88020103c000
>[  515.759068] [drm:drm_atomic_state_free] Freeing atomic state ffff88020103c000
>[  515.759095] [drm:drm_mode_setcrtc] [CRTC:25]
>[  515.759099] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  515.759100] [drm:drm_atomic_state_init] Allocated atomic state ffff88020103c000
>[  515.759102] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5326400 state to ffff88020103c000
>[  515.759104] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f55afc00 state to ffff88020103c000
>[  515.759105] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f5326400
>[  515.759106] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55afc00 to [CRTC:25]
>[  515.759107] [drm:drm_atomic_set_fb_for_plane] Set [FB:51] for plane state ffff8801f55afc00
>[  515.759108] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c909b600 state to ffff88020103c000
>[  515.759109] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103c000
>[  515.759110] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c909b600 to [CRTC:25]
>[  515.759111] [drm:drm_atomic_check_only] checking ffff88020103c000
>[  515.759113] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  515.759113] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  515.759114] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  515.759116] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:25]
>[  515.759117] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  515.759117] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: y, active: y
>[  515.759118] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103c000
>[  515.759120] [drm:drm_atomic_connectors_for_crtc] State ffff88020103c000 has 1 connectors for [CRTC:25]
>[  515.759121] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff88020103c000
>[  515.759122] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  515.759123] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  515.759125] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe B, lanes 2
>[  515.759126] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  515.759127] [drm:intel_dump_pipe_config] [CRTC:25][modeset] config ffff8801f5326400 for pipe B
>[  515.759128] [drm:intel_dump_pipe_config] cpu_transcoder: B
>[  515.759129] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  515.759130] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  515.759132] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  515.759133] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  515.759133] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  515.759134] [drm:intel_dump_pipe_config] requested mode:
>[  515.759136] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  515.759136] [drm:intel_dump_pipe_config] adjusted mode:
>[  515.759138] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  515.759139] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  515.759140] [drm:intel_dump_pipe_config] port clock: 270000
>[  515.759141] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  515.759141] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  515.759142] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  515.759143] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  515.759144] [drm:intel_dump_pipe_config] ips: 0
>[  515.759145] [drm:intel_dump_pipe_config] double wide: 0
>[  515.759146] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  515.759146] [drm:intel_dump_pipe_config] planes on this crtc
>[  515.759148] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
>[  515.759149] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
>[  515.759150] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
>[  515.759151] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff8801f5324000 state to ffff88020103c000
>[  515.759153] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff8801f5326000 state to ffff88020103c000
>[  515.759155] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb 51
>[  515.759156] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 0 -> 1, off 0, on 1, ms 1
>[  515.759157] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8801f55af240 state to ffff88020103c000
>[  515.759158] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8801f55af780 state to ffff88020103c000
>[  515.759160] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8801f55aff00 state to ffff88020103c000
>[  515.759162] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f55afa80 state to ffff88020103c000
>[  515.759164] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f55af480 state to ffff88020103c000
>[  515.759166] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8801f55af600 state to ffff88020103c000
>[  515.759167] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8801f55af840 state to ffff88020103c000
>[  515.759168] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8801f55af0c0 state to ffff88020103c000
>[  515.759169] [drm:drm_atomic_commit] commiting ffff88020103c000
>[  515.759174] [drm:intel_power_well_enable] enabling display
>[  515.759175] [drm:hsw_set_power_well] Enabling power well
>[  515.760583] [drm:intel_power_well_enable] enabling always-on
>[  515.760593] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 25
>[  515.760595] [drm:intel_enable_shared_dpll] enabling SPLL
>[  515.761484] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  515.761555] [drm:intel_enable_pipe] enabling pipe B
>[  515.761569] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  515.828437] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  515.828442] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  515.828443] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  515.828445] [drm:check_crtc_state] [CRTC:25]
>[  515.828455] [drm:check_shared_dpll_state] WRPLL 1
>[  515.828456] [drm:check_shared_dpll_state] WRPLL 2
>[  515.828457] [drm:check_shared_dpll_state] SPLL
>[  515.828459] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88020103c000
>[  515.828463] [drm:drm_atomic_state_free] Freeing atomic state ffff88020103c000
>[  515.828491] [drm:drm_mode_setcrtc] [CRTC:25]
>[  515.828493] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bf3000
>[  515.828495] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880215be4400 state to ffff880026bf3000
>[  515.828496] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8800d3b003c0 state to ffff880026bf3000
>[  515.828497] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff880215be4400
>[  515.828498] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800d3b003c0 to [NOCRTC]
>[  515.828499] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8800d3b003c0
>[  515.828500] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3000
>[  515.828501] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c01326e0 state to ffff880026bf3000
>[  515.828502] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c01326e0 to [NOCRTC]
>[  515.828503] [drm:drm_atomic_check_only] checking ffff880026bf3000
>[  515.828505] [drm:drm_atomic_helper_check_modeset] [CRTC:25] mode changed
>[  515.828505] [drm:drm_atomic_helper_check_modeset] [CRTC:25] enable changed
>[  515.828506] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  515.828507] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  515.828508] [drm:drm_atomic_helper_check_modeset] [CRTC:25] active changed
>[  515.828509] [drm:drm_atomic_helper_check_modeset] [CRTC:25] needs all connectors, enable: n, active: n
>[  515.828510] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bf3000
>[  515.828511] [drm:drm_atomic_connectors_for_crtc] State ffff880026bf3000 has 0 connectors for [CRTC:25]
>[  515.828514] [drm:intel_plane_atomic_calc_changes] [CRTC:25] has [PLANE:23] with fb -1
>[  515.828515] [drm:intel_plane_atomic_calc_changes] [PLANE:23] visible 1 -> 0, off 1, on 0, ms 1
>[  515.828517] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8800d3b006c0 state to ffff880026bf3000
>[  515.828518] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8800d3b00180 state to ffff880026bf3000
>[  515.828520] [drm:drm_atomic_commit] commiting ffff880026bf3000
>[  515.845106] [drm:intel_disable_pipe] disabling pipe B
>[  515.879603] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 25
>[  515.879606] [drm:intel_disable_shared_dpll] disabling SPLL
>[  515.879614] [drm:intel_power_well_disable] disabling display
>[  515.879616] [drm:hsw_set_power_well] Requesting to disable the power well
>[  515.879617] [drm:intel_power_well_disable] disabling always-on
>[  515.879618] [drm:intel_power_well_enable] enabling display
>[  515.879619] [drm:hsw_set_power_well] Enabling power well
>[  515.881688] [drm:intel_power_well_disable] disabling display
>[  515.881692] [drm:hsw_set_power_well] Requesting to disable the power well
>[  515.881697] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  515.881699] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  515.881700] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  515.881703] [drm:check_crtc_state] [CRTC:25]
>[  515.881704] [drm:check_shared_dpll_state] WRPLL 1
>[  515.881705] [drm:check_shared_dpll_state] WRPLL 2
>[  515.881706] [drm:check_shared_dpll_state] SPLL
>[  515.881708] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bf3000
>[  515.881711] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bf3000
>[  515.883839] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[2] ENCODERS[2]
>[  515.883842] [drm:drm_mode_getresources] [CRTC:21]
>[  515.883843] [drm:drm_mode_getresources] [CRTC:25]
>[  515.883843] [drm:drm_mode_getresources] [CRTC:29]
>[  515.883844] [drm:drm_mode_getresources] [ENCODER:32:DAC-32]
>[  515.883845] [drm:drm_mode_getresources] [ENCODER:33:TMDS-33]
>[  515.883846] [drm:drm_mode_getresources] [CONNECTOR:31:VGA-1]
>[  515.883846] [drm:drm_mode_getresources] [CONNECTOR:34:HDMI-A-1]
>[  515.883847] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[2] ENCODERS[2]
>[  515.883849] [drm:drm_mode_getconnector] [CONNECTOR:31:?]
>[  515.883852] [drm:drm_mode_getconnector] [CONNECTOR:31:?]
>[  515.883871] [drm:drm_mode_addfb2] [FB:49]
>[  515.883875] [drm:drm_mode_addfb2] [FB:51]
>[  515.883880] [drm:drm_mode_addfb2] [FB:53]
>[  515.913751] [drm:drm_mode_setcrtc] [CRTC:21]
>[  515.913756] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bfae00
>[  515.913759] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff880025a41000 state to ffff880026bfae00
>[  515.913761] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8800c78d49c0 state to ffff880026bfae00
>[  515.913762] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff880025a41000
>[  515.913763] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800c78d49c0 to [NOCRTC]
>[  515.913764] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8800c78d49c0
>[  515.913765] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:21] to ffff880026bfae00
>[  515.913766] [drm:drm_atomic_check_only] checking ffff880026bfae00
>[  515.913770] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8800c78d40c0 state to ffff880026bfae00
>[  515.913771] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8800c78d4540 state to ffff880026bfae00
>[  515.913773] [drm:drm_atomic_commit] commiting ffff880026bfae00
>[  515.913776] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bfae00
>[  515.913777] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bfae00
>[  515.913780] [drm:drm_mode_setcrtc] [CRTC:25]
>[  515.913781] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bfae00
>[  515.913782] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880025a42000 state to ffff880026bfae00
>[  515.913783] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8800c78d4900 state to ffff880026bfae00
>[  515.913784] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff880025a42000
>[  515.913785] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800c78d4900 to [NOCRTC]
>[  515.913786] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8800c78d4900
>[  515.913787] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfae00
>[  515.913787] [drm:drm_atomic_check_only] checking ffff880026bfae00
>[  515.913789] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8800c78d4d80 state to ffff880026bfae00
>[  515.913790] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8800c78d4180 state to ffff880026bfae00
>[  515.913791] [drm:drm_atomic_commit] commiting ffff880026bfae00
>[  515.913793] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bfae00
>[  515.913794] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bfae00
>[  515.913795] [drm:drm_mode_setcrtc] [CRTC:29]
>[  515.913796] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bfae00
>[  515.913798] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff880025a43000 state to ffff880026bfae00
>[  515.913799] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8800c78d4780 state to ffff880026bfae00
>[  515.913799] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff880025a43000
>[  515.913800] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800c78d4780 to [NOCRTC]
>[  515.913801] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8800c78d4780
>[  515.913802] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:29] to ffff880026bfae00
>[  515.913802] [drm:drm_atomic_check_only] checking ffff880026bfae00
>[  515.913804] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8800c78d4480 state to ffff880026bfae00
>[  515.913805] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8800c78d4c00 state to ffff880026bfae00
>[  515.913806] [drm:drm_atomic_commit] commiting ffff880026bfae00
>[  515.913807] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bfae00
>[  515.913808] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bfae00
>[  515.913810] [drm:drm_mode_setcrtc] [CRTC:29]
>[  515.913814] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  515.913815] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bfae00
>[  515.913816] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff880025a43400 state to ffff880026bfae00
>[  515.913817] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8800c78d4cc0 state to ffff880026bfae00
>[  515.913818] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff880025a43400
>[  515.913819] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800c78d4cc0 to [CRTC:29]
>[  515.913820] [drm:drm_atomic_set_fb_for_plane] Set [FB:49] for plane state ffff8800c78d4cc0
>[  515.913821] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8801f442ddc0 state to ffff880026bfae00
>[  515.913822] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:29] to ffff880026bfae00
>[  515.913823] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f442ddc0 to [CRTC:29]
>[  515.913824] [drm:drm_atomic_check_only] checking ffff880026bfae00
>[  515.913825] [drm:drm_atomic_helper_check_modeset] [CRTC:29] mode changed
>[  515.913825] [drm:drm_atomic_helper_check_modeset] [CRTC:29] enable changed
>[  515.913826] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  515.913828] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:29]
>[  515.913829] [drm:drm_atomic_helper_check_modeset] [CRTC:29] active changed
>[  515.913830] [drm:drm_atomic_helper_check_modeset] [CRTC:29] needs all connectors, enable: y, active: y
>[  515.913830] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:29] to ffff880026bfae00
>[  515.913832] [drm:drm_atomic_connectors_for_crtc] State ffff880026bfae00 has 1 connectors for [CRTC:29]
>[  515.913833] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:29] to ffff880026bfae00
>[  515.913834] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  515.913835] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  515.913836] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe C, lanes 2
>[  515.913837] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  515.913839] [drm:intel_dump_pipe_config] [CRTC:29][modeset] config ffff880025a43400 for pipe C
>[  515.913839] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[  515.913840] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  515.913841] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  515.913842] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  515.913843] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  515.913844] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  515.913844] [drm:intel_dump_pipe_config] requested mode:
>[  515.913846] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  515.913847] [drm:intel_dump_pipe_config] adjusted mode:
>[  515.913848] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  515.913849] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  515.913850] [drm:intel_dump_pipe_config] port clock: 270000
>[  515.913850] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  515.913851] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  515.913852] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  515.913853] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  515.913854] [drm:intel_dump_pipe_config] ips: 0
>[  515.913854] [drm:intel_dump_pipe_config] double wide: 0
>[  515.913856] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  515.913856] [drm:intel_dump_pipe_config] planes on this crtc
>[  515.913857] [drm:intel_dump_pipe_config] STANDARD PLANE:27 plane: 2.0 idx: 6 disabled, scaler_id = 0
>[  515.913858] [drm:intel_dump_pipe_config] CURSOR PLANE:28 plane: 2.3 idx: 7 disabled, scaler_id = 0
>[  515.913859] [drm:intel_dump_pipe_config] STANDARD PLANE:30 plane: 2.1 idx: 8 disabled, scaler_id = 0
>[  515.913860] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff880025a41c00 state to ffff880026bfae00
>[  515.913861] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880025a41800 state to ffff880026bfae00
>[  515.913863] [drm:intel_plane_atomic_calc_changes] [CRTC:29] has [PLANE:27] with fb 49
>[  515.913864] [drm:intel_plane_atomic_calc_changes] [PLANE:27] visible 0 -> 1, off 0, on 1, ms 1
>[  515.913865] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8800c78d4600 state to ffff880026bfae00
>[  515.913866] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8800c78d4000 state to ffff880026bfae00
>[  515.913867] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8800c78d46c0 state to ffff880026bfae00
>[  515.913869] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8800c78d4300 state to ffff880026bfae00
>[  515.913869] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8800c78d4a80 state to ffff880026bfae00
>[  515.913871] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f4ceda80 state to ffff880026bfae00
>[  515.913873] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8801f4cedc00 state to ffff880026bfae00
>[  515.913874] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8801f4ced840 state to ffff880026bfae00
>[  515.913875] [drm:drm_atomic_commit] commiting ffff880026bfae00
>[  515.916197] [drm:intel_power_well_enable] enabling display
>[  515.916198] [drm:hsw_set_power_well] Enabling power well
>[  515.918269] [drm:intel_power_well_enable] enabling always-on
>[  515.918280] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 29
>[  515.918281] [drm:intel_enable_shared_dpll] enabling SPLL
>[  515.919170] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  515.919235] [drm:intel_enable_pipe] enabling pipe C
>[  515.919248] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  516.016588] ------------[ cut here ]------------
>[  516.016601] WARNING: CPU: 3 PID: 19361 at drivers/gpu/drm/drm_irq.c:1268 drm_wait_one_vblank+0x1b5/0x1c0 [drm]()
>[  516.016602] vblank wait timed out on crtc 2
>[  516.016603] Modules linked in: snd_hda_intel i915 drm_kms_helper drm msr bnep binfmt_misc arc4 ath9k ath9k_common ath9k_hw ath mac80211 intel_rapl iosf_mbi x86_pkg_temp_thermal snd_hda_codec_realtek intel_powerclamp snd_hda_codec_hdmi snd_hda_codec_generic coretemp kvm_intel snd_hda_codec kvm snd_hda_core ath3k snd_hwdep snd_pcm btusb joydev dcdbas dell_smm_hwmon input_leds btrtl snd_seq_midi cfg80211 btbcm btintel snd_seq_midi_event snd_rawmidi bluetooth snd_seq irqbypass crct10dif_pclmul snd_seq_device crc32_pclmul snd_timer mei_me aesni_intel aes_x86_64 lrw snd gf128mul mei glue_helper ablk_helper cryptd serio_raw shpchp soundcore lpc_ich mac_hid parport_pc ppdev lp parport autofs4 hid_generic usbhid hid i2c_algo_bit syscopyarea sysfillrect sysimgblt fb_sys_fops psmouse r8169 ahci libahci mii
>[  516.016634]  video [last unloaded: drm]
>[  516.016637] CPU: 3 PID: 19361 Comm: kms_flip Tainted: G     U  W       4.4.0-rc4+ #7
>[  516.016638] Hardware name: Dell Inc. Inspiron 3847/088DT1       , BIOS A06 01/15/2015
>[  516.016639]  0000000000000000 000000000abdae4b ffff880210d8fa38 ffffffff813c4b24
>[  516.016640]  ffff880210d8fa80 ffff880210d8fa70 ffffffff8107d6a2 ffff8800cbbc8000
>[  516.016642]  0000000000000002 0000000000000000 0000000000000004 ffff88002677b578
>[  516.016643] Call Trace:
>[  516.016648]  [<ffffffff813c4b24>] dump_stack+0x44/0x60
>[  516.016651]  [<ffffffff8107d6a2>] warn_slowpath_common+0x82/0xc0
>[  516.016652]  [<ffffffff8107d73c>] warn_slowpath_fmt+0x5c/0x80
>[  516.016656]  [<ffffffff810bf3c5>] ? finish_wait+0x55/0x70
>[  516.016661]  [<ffffffffc0142335>] drm_wait_one_vblank+0x1b5/0x1c0 [drm]
>[  516.016663]  [<ffffffff810bf860>] ? wake_atomic_t_function+0x60/0x60
>[  516.016680]  [<ffffffffc085f27b>] haswell_crtc_enable+0x75b/0x8f0 [i915]
>[  516.016691]  [<ffffffffc085a719>] intel_atomic_commit+0x739/0x1880 [i915]
>[  516.016697]  [<ffffffffc0143e8c>] ? drm_ut_debug_printk+0x6c/0x90 [drm]
>[  516.016706]  [<ffffffffc015b9f7>] drm_atomic_commit+0x37/0x60 [drm]
>[  516.016712]  [<ffffffffc00894d6>] drm_atomic_helper_set_config+0x76/0xb0 [drm_kms_helper]
>[  516.016719]  [<ffffffffc014abe2>] drm_mode_set_config_internal+0x62/0x100 [drm]
>[  516.016726]  [<ffffffffc014f102>] drm_mode_setcrtc+0x3d2/0x4f0 [drm]
>[  516.016730]  [<ffffffffc01407b2>] drm_ioctl+0x152/0x540 [drm]
>[  516.016733]  [<ffffffff8118e9a3>] ? free_pages+0x13/0x20
>[  516.016738]  [<ffffffffc014ed30>] ? drm_mode_setplane+0x1b0/0x1b0 [drm]
>[  516.016751]  [<ffffffffc06864a2>] ? ieee80211_fill_mesh_addresses+0x82/0x90 [mac80211]
>[  516.016754]  [<ffffffff812170e8>] do_vfs_ioctl+0x298/0x480
>[  516.016756]  [<ffffffff811bf9e9>] ? do_munmap+0x349/0x480
>[  516.016757]  [<ffffffff81217349>] SyS_ioctl+0x79/0x90
>[  516.016760]  [<ffffffff817f27b6>] entry_SYSCALL_64_fastpath+0x16/0x75
>[  516.016761] ---[ end trace 1c38b709f478dfe9 ]---
>[  516.116580] ------------[ cut here ]------------
>[  516.116594] WARNING: CPU: 3 PID: 19361 at drivers/gpu/drm/drm_irq.c:1268 drm_wait_one_vblank+0x1b5/0x1c0 [drm]()
>[  516.116595] vblank wait timed out on crtc 2
>[  516.116596] Modules linked in: snd_hda_intel i915 drm_kms_helper drm msr bnep binfmt_misc arc4 ath9k ath9k_common ath9k_hw ath mac80211 intel_rapl iosf_mbi x86_pkg_temp_thermal snd_hda_codec_realtek intel_powerclamp snd_hda_codec_hdmi snd_hda_codec_generic coretemp kvm_intel snd_hda_codec kvm snd_hda_core ath3k snd_hwdep snd_pcm btusb joydev dcdbas dell_smm_hwmon input_leds btrtl snd_seq_midi cfg80211 btbcm btintel snd_seq_midi_event snd_rawmidi bluetooth snd_seq irqbypass crct10dif_pclmul snd_seq_device crc32_pclmul snd_timer mei_me aesni_intel aes_x86_64 lrw snd gf128mul mei glue_helper ablk_helper cryptd serio_raw shpchp soundcore lpc_ich mac_hid parport_pc ppdev lp parport autofs4 hid_generic usbhid hid i2c_algo_bit syscopyarea sysfillrect sysimgblt fb_sys_fops psmouse r8169 ahci libahci mii
>[  516.116628]  video [last unloaded: drm]
>[  516.116630] CPU: 3 PID: 19361 Comm: kms_flip Tainted: G     U  W       4.4.0-rc4+ #7
>[  516.116631] Hardware name: Dell Inc. Inspiron 3847/088DT1       , BIOS A06 01/15/2015
>[  516.116632]  0000000000000000 000000000abdae4b ffff880210d8fa38 ffffffff813c4b24
>[  516.116634]  ffff880210d8fa80 ffff880210d8fa70 ffffffff8107d6a2 ffff8800cbbc8000
>[  516.116635]  0000000000000002 0000000000000000 0000000000000004 ffff88002677b578
>[  516.116637] Call Trace:
>[  516.116642]  [<ffffffff813c4b24>] dump_stack+0x44/0x60
>[  516.116645]  [<ffffffff8107d6a2>] warn_slowpath_common+0x82/0xc0
>[  516.116646]  [<ffffffff8107d73c>] warn_slowpath_fmt+0x5c/0x80
>[  516.116649]  [<ffffffff810bf3c5>] ? finish_wait+0x55/0x70
>[  516.116655]  [<ffffffffc0142335>] drm_wait_one_vblank+0x1b5/0x1c0 [drm]
>[  516.116657]  [<ffffffff810bf860>] ? wake_atomic_t_function+0x60/0x60
>[  516.116674]  [<ffffffffc085f285>] haswell_crtc_enable+0x765/0x8f0 [i915]
>[  516.116686]  [<ffffffffc085a719>] intel_atomic_commit+0x739/0x1880 [i915]
>[  516.116692]  [<ffffffffc0143e8c>] ? drm_ut_debug_printk+0x6c/0x90 [drm]
>[  516.116701]  [<ffffffffc015b9f7>] drm_atomic_commit+0x37/0x60 [drm]
>[  516.116707]  [<ffffffffc00894d6>] drm_atomic_helper_set_config+0x76/0xb0 [drm_kms_helper]
>[  516.116714]  [<ffffffffc014abe2>] drm_mode_set_config_internal+0x62/0x100 [drm]
>[  516.116721]  [<ffffffffc014f102>] drm_mode_setcrtc+0x3d2/0x4f0 [drm]
>[  516.116726]  [<ffffffffc01407b2>] drm_ioctl+0x152/0x540 [drm]
>[  516.116729]  [<ffffffff8118e9a3>] ? free_pages+0x13/0x20
>[  516.116734]  [<ffffffffc014ed30>] ? drm_mode_setplane+0x1b0/0x1b0 [drm]
>[  516.116747]  [<ffffffffc06864a2>] ? ieee80211_fill_mesh_addresses+0x82/0x90 [mac80211]
>[  516.116750]  [<ffffffff812170e8>] do_vfs_ioctl+0x298/0x480
>[  516.116752]  [<ffffffff811bf9e9>] ? do_munmap+0x349/0x480
>[  516.116754]  [<ffffffff81217349>] SyS_ioctl+0x79/0x90
>[  516.116757]  [<ffffffff817f27b6>] entry_SYSCALL_64_fastpath+0x16/0x75
>[  516.116758] ---[ end trace 1c38b709f478dfea ]---
>[  516.117921] [drm:intel_set_pch_fifo_underrun_reporting [i915]] *ERROR* uncleared pch fifo underrun on pch transcoder A
>[  516.120057] [drm:intel_pch_fifo_underrun_irq_handler [i915]] *ERROR* PCH transcoder A FIFO underrun
>[  516.216571] ------------[ cut here ]------------
>[  516.216585] WARNING: CPU: 3 PID: 19361 at drivers/gpu/drm/drm_irq.c:1268 drm_wait_one_vblank+0x1b5/0x1c0 [drm]()
>[  516.216586] vblank wait timed out on crtc 2
>[  516.216587] Modules linked in: snd_hda_intel i915 drm_kms_helper drm msr bnep binfmt_misc arc4 ath9k ath9k_common ath9k_hw ath mac80211 intel_rapl iosf_mbi x86_pkg_temp_thermal snd_hda_codec_realtek intel_powerclamp snd_hda_codec_hdmi snd_hda_codec_generic coretemp kvm_intel snd_hda_codec kvm snd_hda_core ath3k snd_hwdep snd_pcm btusb joydev dcdbas dell_smm_hwmon input_leds btrtl snd_seq_midi cfg80211 btbcm btintel snd_seq_midi_event snd_rawmidi bluetooth snd_seq irqbypass crct10dif_pclmul snd_seq_device crc32_pclmul snd_timer mei_me aesni_intel aes_x86_64 lrw snd gf128mul mei glue_helper ablk_helper cryptd serio_raw shpchp soundcore lpc_ich mac_hid parport_pc ppdev lp parport autofs4 hid_generic usbhid hid i2c_algo_bit syscopyarea sysfillrect sysimgblt fb_sys_fops psmouse r8169 ahci libahci mii
>[  516.216619]  video [last unloaded: drm]
>[  516.216622] CPU: 3 PID: 19361 Comm: kms_flip Tainted: G     U  W       4.4.0-rc4+ #7
>[  516.216623] Hardware name: Dell Inc. Inspiron 3847/088DT1       , BIOS A06 01/15/2015
>[  516.216624]  0000000000000000 000000000abdae4b ffff880210d8fab0 ffffffff813c4b24
>[  516.216625]  ffff880210d8faf8 ffff880210d8fae8 ffffffff8107d6a2 ffff8800cbbc8000
>[  516.216627]  0000000000000002 0000000000000000 0000000000000004 ffff88002677b578
>[  516.216628] Call Trace:
>[  516.216633]  [<ffffffff813c4b24>] dump_stack+0x44/0x60
>[  516.216636]  [<ffffffff8107d6a2>] warn_slowpath_common+0x82/0xc0
>[  516.216638]  [<ffffffff8107d73c>] warn_slowpath_fmt+0x5c/0x80
>[  516.216640]  [<ffffffff810bf3c5>] ? finish_wait+0x55/0x70
>[  516.216646]  [<ffffffffc0142335>] drm_wait_one_vblank+0x1b5/0x1c0 [drm]
>[  516.216648]  [<ffffffff810bf860>] ? wake_atomic_t_function+0x60/0x60
>[  516.216665]  [<ffffffffc085a6ef>] intel_atomic_commit+0x70f/0x1880 [i915]
>[  516.216671]  [<ffffffffc0143e8c>] ? drm_ut_debug_printk+0x6c/0x90 [drm]
>[  516.216680]  [<ffffffffc015b9f7>] drm_atomic_commit+0x37/0x60 [drm]
>[  516.216685]  [<ffffffffc00894d6>] drm_atomic_helper_set_config+0x76/0xb0 [drm_kms_helper]
>[  516.216692]  [<ffffffffc014abe2>] drm_mode_set_config_internal+0x62/0x100 [drm]
>[  516.216699]  [<ffffffffc014f102>] drm_mode_setcrtc+0x3d2/0x4f0 [drm]
>[  516.216704]  [<ffffffffc01407b2>] drm_ioctl+0x152/0x540 [drm]
>[  516.216707]  [<ffffffff8118e9a3>] ? free_pages+0x13/0x20
>[  516.216712]  [<ffffffffc014ed30>] ? drm_mode_setplane+0x1b0/0x1b0 [drm]
>[  516.216725]  [<ffffffffc06864a2>] ? ieee80211_fill_mesh_addresses+0x82/0x90 [mac80211]
>[  516.216728]  [<ffffffff812170e8>] do_vfs_ioctl+0x298/0x480
>[  516.216730]  [<ffffffff811bf9e9>] ? do_munmap+0x349/0x480
>[  516.216732]  [<ffffffff81217349>] SyS_ioctl+0x79/0x90
>[  516.216734]  [<ffffffff817f27b6>] entry_SYSCALL_64_fastpath+0x16/0x75
>[  516.216735] ---[ end trace 1c38b709f478dfeb ]---
>[  516.268908] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  516.268913] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  516.268914] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  516.268916] [drm:check_crtc_state] [CRTC:29]
>[  516.268917] ------------[ cut here ]------------
>[  516.268937] WARNING: CPU: 3 PID: 19361 at drivers/gpu/drm/i915/intel_display.c:12852 intel_atomic_commit+0xe68/0x1880 [i915]()
>[  516.268938] crtc active state doesn't match with hw state (expected 1, found 0)
>[  516.268938] Modules linked in: snd_hda_intel i915 drm_kms_helper drm msr bnep binfmt_misc arc4 ath9k ath9k_common ath9k_hw ath mac80211 intel_rapl iosf_mbi x86_pkg_temp_thermal snd_hda_codec_realtek intel_powerclamp snd_hda_codec_hdmi snd_hda_codec_generic coretemp kvm_intel snd_hda_codec kvm snd_hda_core ath3k snd_hwdep snd_pcm btusb joydev dcdbas dell_smm_hwmon input_leds btrtl snd_seq_midi cfg80211 btbcm btintel snd_seq_midi_event snd_rawmidi bluetooth snd_seq irqbypass crct10dif_pclmul snd_seq_device crc32_pclmul snd_timer mei_me aesni_intel aes_x86_64 lrw snd gf128mul mei glue_helper ablk_helper cryptd serio_raw shpchp soundcore lpc_ich mac_hid parport_pc ppdev lp parport autofs4 hid_generic usbhid hid i2c_algo_bit syscopyarea sysfillrect sysimgblt fb_sys_fops psmouse r8169 ahci libahci mii
>[  516.268969]  video [last unloaded: drm]
>[  516.268972] CPU: 3 PID: 19361 Comm: kms_flip Tainted: G     U  W       4.4.0-rc4+ #7
>[  516.268973] Hardware name: Dell Inc. Inspiron 3847/088DT1       , BIOS A06 01/15/2015
>[  516.268973]  0000000000000000 000000000abdae4b ffff880210d8fb18 ffffffff813c4b24
>[  516.268975]  ffff880210d8fb60 ffff880210d8fb50 ffffffff8107d6a2 ffff8800ce3d0000
>[  516.268977]  ffff880026bfae00 ffff88020f353000 ffff880025a43000 ffff8800cbbc8348
>[  516.268978] Call Trace:
>[  516.268983]  [<ffffffff813c4b24>] dump_stack+0x44/0x60
>[  516.268985]  [<ffffffff8107d6a2>] warn_slowpath_common+0x82/0xc0
>[  516.268987]  [<ffffffff8107d73c>] warn_slowpath_fmt+0x5c/0x80
>[  516.268997]  [<ffffffffc085ae48>] intel_atomic_commit+0xe68/0x1880 [i915]
>[  516.269005]  [<ffffffffc0143e8c>] ? drm_ut_debug_printk+0x6c/0x90 [drm]
>[  516.269013]  [<ffffffffc015b9f7>] drm_atomic_commit+0x37/0x60 [drm]
>[  516.269018]  [<ffffffffc00894d6>] drm_atomic_helper_set_config+0x76/0xb0 [drm_kms_helper]
>[  516.269025]  [<ffffffffc014abe2>] drm_mode_set_config_internal+0x62/0x100 [drm]
>[  516.269031]  [<ffffffffc014f102>] drm_mode_setcrtc+0x3d2/0x4f0 [drm]
>[  516.269035]  [<ffffffffc01407b2>] drm_ioctl+0x152/0x540 [drm]
>[  516.269038]  [<ffffffff8118e9a3>] ? free_pages+0x13/0x20
>[  516.269043]  [<ffffffffc014ed30>] ? drm_mode_setplane+0x1b0/0x1b0 [drm]
>[  516.269055]  [<ffffffffc06864a2>] ? ieee80211_fill_mesh_addresses+0x82/0x90 [mac80211]
>[  516.269057]  [<ffffffff812170e8>] do_vfs_ioctl+0x298/0x480
>[  516.269059]  [<ffffffff811bf9e9>] ? do_munmap+0x349/0x480
>[  516.269061]  [<ffffffff81217349>] SyS_ioctl+0x79/0x90
>[  516.269063]  [<ffffffff817f27b6>] entry_SYSCALL_64_fastpath+0x16/0x75
>[  516.269064] ---[ end trace 1c38b709f478dfec ]---
>[  516.269079] [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in has_pch_encoder (expected 1, found 0)
>[  516.271217] [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in fdi_lanes (expected 2, found 0)
>[  516.273348] [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in fdi_m_n (expected tu 64 gmch 7176920/8388608 link 299038/524288, found tu 0, gmch 0/0 link 0/0)
>[  516.276565] [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_hdisplay (expected 1920, found 0)
>[  516.276573] [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_htotal (expected 2080, found 0)
>[  516.276580] [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_hblank_start (expected 1920, found 0)
>[  516.276588] [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_hblank_end (expected 2080, found 0)
>[  516.276596] [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_hsync_start (expected 1968, found 0)
>[  516.276602] [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_hsync_end (expected 2000, found 0)
>[  516.276609] [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_vdisplay (expected 1200, found 0)
>[  516.276616] [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_vtotal (expected 1235, found 0)
>[  516.276622] [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_vblank_start (expected 1200, found 0)
>[  516.276629] [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_vblank_end (expected 1235, found 0)
>[  516.276635] [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_vsync_start (expected 1203, found 0)
>[  516.276642] [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_vsync_end (expected 1209, found 0)
>[  516.276648] [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in pixel_multiplier (expected 1, found 0)
>[  516.276655] [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in pipe_src_w (expected 1920, found 0)
>[  516.276661] [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in pipe_src_h (expected 1200, found 0)
>[  516.276667] [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in ddi_pll_sel (expected 0x60000000, found 0x00000000)
>[  516.276674] [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in shared_dpll (expected 2, found -1)
>[  516.276680] [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in dpll_hw_state.spll (expected 0x94000000, found 0x00000000)
>[  516.276687] [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_clock (expected 154000, found 540000)
>[  516.276693] [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in port_clock (expected 270000, found 540000)
>[  516.276693] ------------[ cut here ]------------
>[  516.276701] WARNING: CPU: 3 PID: 19361 at drivers/gpu/drm/i915/intel_display.c:12880 intel_atomic_commit+0x12b2/0x1880 [i915]()
>[  516.276702] pipe state doesn't match!
>[  516.276715] Modules linked in: snd_hda_intel i915 drm_kms_helper drm msr bnep binfmt_misc arc4 ath9k ath9k_common ath9k_hw ath mac80211 intel_rapl iosf_mbi x86_pkg_temp_thermal snd_hda_codec_realtek intel_powerclamp snd_hda_codec_hdmi snd_hda_codec_generic coretemp kvm_intel snd_hda_codec kvm snd_hda_core ath3k snd_hwdep snd_pcm btusb joydev dcdbas dell_smm_hwmon input_leds btrtl snd_seq_midi cfg80211 btbcm btintel snd_seq_midi_event snd_rawmidi bluetooth snd_seq irqbypass crct10dif_pclmul snd_seq_device crc32_pclmul snd_timer mei_me aesni_intel aes_x86_64 lrw snd gf128mul mei glue_helper ablk_helper cryptd serio_raw shpchp soundcore lpc_ich mac_hid parport_pc ppdev lp parport autofs4 hid_generic usbhid hid i2c_algo_bit syscopyarea sysfillrect sysimgblt fb_sys_fops psmouse r8169 ahci libahci mii
>[  516.276716]  video [last unloaded: drm]
>[  516.276717] CPU: 3 PID: 19361 Comm: kms_flip Tainted: G     U  W       4.4.0-rc4+ #7
>[  516.276717] Hardware name: Dell Inc. Inspiron 3847/088DT1       , BIOS A06 01/15/2015
>[  516.276719]  0000000000000000 000000000abdae4b ffff880210d8fb18 ffffffff813c4b24
>[  516.276719]  ffff880210d8fb60 ffff880210d8fb50 ffffffff8107d6a2 ffff880025a43400
>[  516.276720]  ffff880026bfae00 ffff88020f353000 ffff880025a43000 ffff8800cbbc8348
>[  516.276720] Call Trace:
>[  516.276722]  [<ffffffff813c4b24>] dump_stack+0x44/0x60
>[  516.276723]  [<ffffffff8107d6a2>] warn_slowpath_common+0x82/0xc0
>[  516.276724]  [<ffffffff8107d73c>] warn_slowpath_fmt+0x5c/0x80
>[  516.276732]  [<ffffffffc085b292>] intel_atomic_commit+0x12b2/0x1880 [i915]
>[  516.276737]  [<ffffffffc0143e8c>] ? drm_ut_debug_printk+0x6c/0x90 [drm]
>[  516.276744]  [<ffffffffc015b9f7>] drm_atomic_commit+0x37/0x60 [drm]
>[  516.276747]  [<ffffffffc00894d6>] drm_atomic_helper_set_config+0x76/0xb0 [drm_kms_helper]
>[  516.276753]  [<ffffffffc014abe2>] drm_mode_set_config_internal+0x62/0x100 [drm]
>[  516.276759]  [<ffffffffc014f102>] drm_mode_setcrtc+0x3d2/0x4f0 [drm]
>[  516.276763]  [<ffffffffc01407b2>] drm_ioctl+0x152/0x540 [drm]
>[  516.276764]  [<ffffffff8118e9a3>] ? free_pages+0x13/0x20
>[  516.276769]  [<ffffffffc014ed30>] ? drm_mode_setplane+0x1b0/0x1b0 [drm]
>[  516.276778]  [<ffffffffc06864a2>] ? ieee80211_fill_mesh_addresses+0x82/0x90 [mac80211]
>[  516.276780]  [<ffffffff812170e8>] do_vfs_ioctl+0x298/0x480
>[  516.276781]  [<ffffffff811bf9e9>] ? do_munmap+0x349/0x480
>[  516.276782]  [<ffffffff81217349>] SyS_ioctl+0x79/0x90
>[  516.276783]  [<ffffffff817f27b6>] entry_SYSCALL_64_fastpath+0x16/0x75
>[  516.276784] ---[ end trace 1c38b709f478dfed ]---
>[  516.276785] [drm:intel_dump_pipe_config] [CRTC:29][hw state] config ffff880025a43000 for pipe C
>[  516.276786] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[  516.276786] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  516.276787] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  516.276788] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  516.276788] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  516.276789] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  516.276789] [drm:intel_dump_pipe_config] requested mode:
>[  516.276790] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  516.276791] [drm:intel_dump_pipe_config] adjusted mode:
>[  516.276792] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x9
>[  516.276792] [drm:intel_dump_crtc_timings] crtc timings: 540000 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x9
>[  516.276793] [drm:intel_dump_pipe_config] port clock: 540000
>[  516.276793] [drm:intel_dump_pipe_config] pipe src size: 0x0
>[  516.276794] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  516.276795] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  516.276795] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  516.276795] [drm:intel_dump_pipe_config] ips: 0
>[  516.276796] [drm:intel_dump_pipe_config] double wide: 0
>[  516.276796] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: wrpll: 0x0 spll: 0x0
>[  516.276796] [drm:intel_dump_pipe_config] planes on this crtc
>[  516.276798] [drm:intel_dump_pipe_config] STANDARD PLANE:27 plane: 2.0 idx: 6 enabled
>[  516.276799] [drm:intel_dump_pipe_config] 	FB:49, fb = 1920x1200 format = 0x34325258
>[  516.276799] [drm:intel_dump_pipe_config] 	scaler:0 src (0, 0) 1920x1200 dst (0, 0) 1920x1200
>[  516.276800] [drm:intel_dump_pipe_config] CURSOR PLANE:28 plane: 2.3 idx: 7 disabled, scaler_id = 0
>[  516.276801] [drm:intel_dump_pipe_config] STANDARD PLANE:30 plane: 2.1 idx: 8 disabled, scaler_id = 0
>[  516.276801] [drm:intel_dump_pipe_config] [CRTC:29][sw state] config ffff880025a43400 for pipe C
>[  516.276802] [drm:intel_dump_pipe_config] cpu_transcoder: C
>[  516.276802] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  516.276803] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  516.276804] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  516.276804] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  516.276804] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  516.276805] [drm:intel_dump_pipe_config] requested mode:
>[  516.276806] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  516.276806] [drm:intel_dump_pipe_config] adjusted mode:
>[  516.276807] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  516.276808] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  516.276809] [drm:intel_dump_pipe_config] port clock: 270000
>[  516.276810] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  516.276810] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  516.276810] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  516.276811] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  516.276811] [drm:intel_dump_pipe_config] ips: 0
>[  516.276812] [drm:intel_dump_pipe_config] double wide: 0
>[  516.276812] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  516.276812] [drm:intel_dump_pipe_config] planes on this crtc
>[  516.276813] [drm:intel_dump_pipe_config] STANDARD PLANE:27 plane: 2.0 idx: 6 enabled
>[  516.276814] [drm:intel_dump_pipe_config] 	FB:49, fb = 1920x1200 format = 0x34325258
>[  516.276814] [drm:intel_dump_pipe_config] 	scaler:0 src (0, 0) 1920x1200 dst (0, 0) 1920x1200
>[  516.276815] [drm:intel_dump_pipe_config] CURSOR PLANE:28 plane: 2.3 idx: 7 disabled, scaler_id = 0
>[  516.276816] [drm:intel_dump_pipe_config] STANDARD PLANE:30 plane: 2.1 idx: 8 disabled, scaler_id = 0
>[  516.276816] [drm:check_shared_dpll_state] WRPLL 1
>[  516.276817] [drm:check_shared_dpll_state] WRPLL 2
>[  516.276818] [drm:check_shared_dpll_state] SPLL
>[  516.276820] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bfae00
>[  516.276823] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bfae00
>[  516.858638] [drm:intel_print_rc6_info] Enabling RC6 states: RC6 on
>[  516.860491] [drm:gen6_enable_rps] Overclocking supported. Max: 1100MHz, Overclock max: 1100MHz
>[  519.284130] kms_flip: exiting, ret=99
>[  519.284182] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bfae00
>[  519.284188] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff880025a43000 state to ffff880026bfae00
>[  519.284190] [drm:drm_atomic_check_only] checking ffff880026bfae00
>[  519.284197] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8801f4ced780 state to ffff880026bfae00
>[  519.284199] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8801f4cedd80 state to ffff880026bfae00
>[  519.284202] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8801f4ced480 state to ffff880026bfae00
>[  519.284206] [drm:drm_atomic_commit] commiting ffff880026bfae00
>[  579.275450] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bfae00
>[  579.275463] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bfae00
>[  579.275528] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bfae00
>[  579.275534] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8801f4cedc00 state to ffff880026bfae00
>[  579.275537] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8801f4ced600 state to ffff880026bfae00
>[  579.275540] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f4ced600 to [NOCRTC]
>[  579.275542] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f4ced600
>[  579.275544] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8801f4ced180 state to ffff880026bfae00
>[  579.275546] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f4ced180 to [NOCRTC]
>[  579.275548] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f4ced180
>[  579.275551] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f4ced000 state to ffff880026bfae00
>[  579.275555] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f4ced9c0 state to ffff880026bfae00
>[  579.275557] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f4ced9c0 to [NOCRTC]
>[  579.275558] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f4ced9c0
>[  579.275561] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f4cedb40 state to ffff880026bfae00
>[  579.275563] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f4cedb40 to [NOCRTC]
>[  579.275564] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f4cedb40
>[  579.275567] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8801f4ced6c0 state to ffff880026bfae00
>[  579.275571] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff880025a43400 state to ffff880026bfae00
>[  579.275575] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8801f4ced540 state to ffff880026bfae00
>[  579.275576] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f4ced540 to [NOCRTC]
>[  579.275577] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f4ced540
>[  579.275580] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8801f4ced0c0 state to ffff880026bfae00
>[  579.275582] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f4ced0c0 to [NOCRTC]
>[  579.275583] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f4ced0c0
>[  579.275587] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff880025a42000 state to ffff880026bfae00
>[  579.275592] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff880025a42000
>[  579.275594] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f4cedc00 to [CRTC:21]
>[  579.275597] [drm:drm_atomic_set_fb_for_plane] Set [FB:50] for plane state ffff8801f4cedc00
>[  579.275601] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8801f442db20 state to ffff880026bfae00
>[  579.275603] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:21] to ffff880026bfae00
>[  579.275606] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:29] to ffff880026bfae00
>[  579.275609] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f442db20 to [CRTC:21]
>[  579.275611] [drm:drm_atomic_connectors_for_crtc] State ffff880026bfae00 has 0 connectors for [CRTC:29]
>[  579.275613] [drm:drm_atomic_set_mode_prop_for_crtc] Set [NOMODE] for CRTC state ffff880025a43400
>[  579.275616] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880025a43c00 state to ffff880026bfae00
>[  579.275618] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff880025a43c00
>[  579.275620] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f4ced000 to [NOCRTC]
>[  579.275621] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f4ced000
>[  579.275623] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:21] to ffff880026bfae00
>[  579.275625] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfae00
>[  579.275627] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:29] to ffff880026bfae00
>[  579.275630] [drm:drm_atomic_connectors_for_crtc] State ffff880026bfae00 has 1 connectors for [CRTC:21]
>[  579.275631] [drm:drm_atomic_connectors_for_crtc] State ffff880026bfae00 has 0 connectors for [CRTC:29]
>[  579.275634] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff880025a43400
>[  579.275635] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f4ced6c0 to [NOCRTC]
>[  579.275637] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f4ced6c0
>[  579.275639] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:21] to ffff880026bfae00
>[  579.275641] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfae00
>[  579.275643] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:29] to ffff880026bfae00
>[  579.275645] [drm:drm_atomic_connectors_for_crtc] State ffff880026bfae00 has 1 connectors for [CRTC:21]
>[  579.275647] [drm:drm_atomic_connectors_for_crtc] State ffff880026bfae00 has 0 connectors for [CRTC:25]
>[  579.275648] [drm:drm_atomic_check_only] checking ffff880026bfae00
>[  579.275653] [drm:drm_atomic_helper_check_modeset] [CRTC:21] mode changed
>[  579.275654] [drm:drm_atomic_helper_check_modeset] [CRTC:21] enable changed
>[  579.275656] [drm:drm_atomic_helper_check_modeset] [CRTC:29] mode changed
>[  579.275657] [drm:drm_atomic_helper_check_modeset] [CRTC:29] enable changed
>[  579.275660] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  579.275664] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] keeps [ENCODER:32:DAC-32], now on [CRTC:21]
>[  579.275666] [drm:drm_atomic_helper_check_modeset] [CRTC:21] active changed
>[  579.275668] [drm:drm_atomic_helper_check_modeset] [CRTC:21] needs all connectors, enable: y, active: y
>[  579.275670] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:21] to ffff880026bfae00
>[  579.275673] [drm:drm_atomic_connectors_for_crtc] State ffff880026bfae00 has 1 connectors for [CRTC:21]
>[  579.275674] [drm:drm_atomic_helper_check_modeset] [CRTC:29] active changed
>[  579.275676] [drm:drm_atomic_helper_check_modeset] [CRTC:29] needs all connectors, enable: n, active: n
>[  579.275678] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:29] to ffff880026bfae00
>[  579.275681] [drm:drm_atomic_connectors_for_crtc] State ffff880026bfae00 has 0 connectors for [CRTC:29]
>[  579.275684] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:21] to ffff880026bfae00
>[  579.275687] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  579.275689] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  579.275693] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 2
>[  579.275695] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  579.275699] [drm:intel_dump_pipe_config] [CRTC:21][modeset] config ffff880025a42000 for pipe A
>[  579.275700] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[  579.275702] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  579.275705] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  579.275708] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  579.275711] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  579.275712] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  579.275714] [drm:intel_dump_pipe_config] requested mode:
>[  579.275719] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  579.275720] [drm:intel_dump_pipe_config] adjusted mode:
>[  579.275724] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  579.275727] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  579.275729] [drm:intel_dump_pipe_config] port clock: 270000
>[  579.275730] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  579.275732] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  579.275735] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  579.275737] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  579.275739] [drm:intel_dump_pipe_config] ips: 0
>[  579.275740] [drm:intel_dump_pipe_config] double wide: 0
>[  579.275743] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  579.275744] [drm:intel_dump_pipe_config] planes on this crtc
>[  579.275747] [drm:intel_dump_pipe_config] STANDARD PLANE:18 plane: 0.0 idx: 0 disabled, scaler_id = 0
>[  579.275749] [drm:intel_dump_pipe_config] CURSOR PLANE:20 plane: 0.1 idx: 1 disabled, scaler_id = 0
>[  579.275752] [drm:intel_dump_pipe_config] STANDARD PLANE:22 plane: 0.1 idx: 2 disabled, scaler_id = 0
>[  579.275759] [drm:intel_plane_atomic_calc_changes] [CRTC:21] has [PLANE:18] with fb 50
>[  579.275762] [drm:intel_plane_atomic_calc_changes] [PLANE:18] visible 0 -> 1, off 0, on 1, ms 1
>[  579.275765] [drm:intel_plane_atomic_calc_changes] [CRTC:29] has [PLANE:27] with fb -1
>[  579.275768] [drm:intel_plane_atomic_calc_changes] [PLANE:27] visible 1 -> 0, off 1, on 0, ms 1
>[  579.275780] [drm:drm_atomic_commit] commiting ffff880026bfae00
>[  579.276197] [drm:intel_disable_pipe] disabling pipe C
>[  579.280373] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 29
>[  579.280378] [drm:intel_disable_shared_dpll] disabling SPLL
>[  579.280410] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 21
>[  579.280412] [drm:intel_enable_shared_dpll] enabling SPLL
>[  579.281320] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  579.281471] [drm:intel_enable_pipe] enabling pipe A
>[  579.281493] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  579.348393] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  579.348399] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  579.348401] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  579.348404] [drm:check_crtc_state] [CRTC:21]
>[  579.348428] [drm:check_crtc_state] [CRTC:29]
>[  579.348431] [drm:check_shared_dpll_state] WRPLL 1
>[  579.348433] [drm:check_shared_dpll_state] WRPLL 2
>[  579.348435] [drm:check_shared_dpll_state] SPLL
>[  579.348439] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bfae00
>[  579.348445] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bfae00
>[  579.367710] [drm:drm_atomic_state_init] Allocated atomic state ffff880201187c00
>[  579.367718] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8801f55afe40 state to ffff880201187c00
>[  579.367722] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff8801f5324400 state to ffff880201187c00
>[  579.367725] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8801f55afb40 state to ffff880201187c00
>[  579.367728] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55afb40 to [NOCRTC]
>[  579.367731] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f55afb40
>[  579.367734] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8801f55af9c0 state to ffff880201187c00
>[  579.367736] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55af9c0 to [NOCRTC]
>[  579.367738] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f55af9c0
>[  579.367741] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f55af3c0 state to ffff880201187c00
>[  579.367744] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f55af540 state to ffff880201187c00
>[  579.367746] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55af540 to [NOCRTC]
>[  579.367748] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f55af540
>[  579.367751] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f55af6c0 state to ffff880201187c00
>[  579.367753] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55af6c0 to [NOCRTC]
>[  579.367755] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f55af6c0
>[  579.367758] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8801f55af300 state to ffff880201187c00
>[  579.367761] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8801f55af0c0 state to ffff880201187c00
>[  579.367763] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55af0c0 to [NOCRTC]
>[  579.367765] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f55af0c0
>[  579.367768] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8801f55af840 state to ffff880201187c00
>[  579.367771] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55af840 to [NOCRTC]
>[  579.367773] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f55af840
>[  579.367778] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f5324400
>[  579.367780] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55afe40 to [CRTC:21]
>[  579.367783] [drm:drm_atomic_set_fb_for_plane] Set [FB:50] for plane state ffff8801f55afe40
>[  579.367787] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c909b640 state to ffff880201187c00
>[  579.367790] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:21] to ffff880201187c00
>[  579.367793] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c909b640 to [NOCRTC]
>[  579.367796] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c909b640 to [CRTC:21]
>[  579.367799] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5327c00 state to ffff880201187c00
>[  579.367802] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f5327c00
>[  579.367804] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55af3c0 to [NOCRTC]
>[  579.367806] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f55af3c0
>[  579.367809] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:21] to ffff880201187c00
>[  579.367811] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880201187c00
>[  579.367815] [drm:drm_atomic_connectors_for_crtc] State ffff880201187c00 has 1 connectors for [CRTC:21]
>[  579.367818] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff8801f5325000 state to ffff880201187c00
>[  579.367820] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f5325000
>[  579.367822] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55af300 to [NOCRTC]
>[  579.367824] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f55af300
>[  579.367827] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:21] to ffff880201187c00
>[  579.367829] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880201187c00
>[  579.367832] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:29] to ffff880201187c00
>[  579.367835] [drm:drm_atomic_connectors_for_crtc] State ffff880201187c00 has 1 connectors for [CRTC:21]
>[  579.367837] [drm:drm_atomic_connectors_for_crtc] State ffff880201187c00 has 0 connectors for [CRTC:25]
>[  579.367839] [drm:drm_atomic_check_only] checking ffff880201187c00
>[  579.367844] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  579.367848] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] keeps [ENCODER:32:DAC-32], now on [CRTC:21]
>[  579.367854] [drm:intel_plane_atomic_calc_changes] [CRTC:21] has [PLANE:18] with fb 50
>[  579.367857] [drm:intel_plane_atomic_calc_changes] [PLANE:18] visible 1 -> 1, off 0, on 0, ms 0
>[  579.367866] [drm:drm_atomic_commit] commiting ffff880201187c00
>[  579.367890] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880201187c00
>[  579.367894] [drm:drm_atomic_state_free] Freeing atomic state ffff880201187c00
>[  579.613373] kms_addfb_basic: executing
>[  579.613411] [drm:i915_gem_open] 
>[  579.613560] [drm:i915_gem_open] 
>[  579.613572] [drm:drm_mode_addfb2] [FB:51]
>[  579.613584] kms_addfb_basic: starting subtest unused-pitches
>[  579.613593] [drm:framebuffer_check] non-zero pitch for unused plane 1
>[  579.613633] kms_addfb_basic: exiting, ret=0
>[  579.613692] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bfba00
>[  579.613695] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8800c78d4a80 state to ffff880026bfba00
>[  579.613696] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff880025a40800 state to ffff880026bfba00
>[  579.613697] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8800c78d4e40 state to ffff880026bfba00
>[  579.613698] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800c78d4e40 to [NOCRTC]
>[  579.613699] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8800c78d4e40
>[  579.613700] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8800c78d4b40 state to ffff880026bfba00
>[  579.613701] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800c78d4b40 to [NOCRTC]
>[  579.613702] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8800c78d4b40
>[  579.613703] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8800c78d4840 state to ffff880026bfba00
>[  579.613704] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8800c78d4300 state to ffff880026bfba00
>[  579.613705] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800c78d4300 to [NOCRTC]
>[  579.613706] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8800c78d4300
>[  579.613707] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8800c78d46c0 state to ffff880026bfba00
>[  579.613707] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800c78d46c0 to [NOCRTC]
>[  579.613708] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8800c78d46c0
>[  579.613709] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8800c78d4000 state to ffff880026bfba00
>[  579.613710] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8800c78d4600 state to ffff880026bfba00
>[  579.613711] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800c78d4600 to [NOCRTC]
>[  579.613711] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8800c78d4600
>[  579.613712] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8800c78d4240 state to ffff880026bfba00
>[  579.613713] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800c78d4240 to [NOCRTC]
>[  579.613714] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8800c78d4240
>[  579.613716] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff880025a40800
>[  579.613717] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800c78d4a80 to [CRTC:21]
>[  579.613718] [drm:drm_atomic_set_fb_for_plane] Set [FB:50] for plane state ffff8800c78d4a80
>[  579.613719] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8801f442dee0 state to ffff880026bfba00
>[  579.613720] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:21] to ffff880026bfba00
>[  579.613722] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f442dee0 to [NOCRTC]
>[  579.613723] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f442dee0 to [CRTC:21]
>[  579.613724] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880025a42800 state to ffff880026bfba00
>[  579.613725] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff880025a42800
>[  579.613725] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800c78d4840 to [NOCRTC]
>[  579.613726] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8800c78d4840
>[  579.613727] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:21] to ffff880026bfba00
>[  579.613728] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfba00
>[  579.613729] [drm:drm_atomic_connectors_for_crtc] State ffff880026bfba00 has 1 connectors for [CRTC:21]
>[  579.613730] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff880025a43400 state to ffff880026bfba00
>[  579.613731] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff880025a43400
>[  579.613732] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800c78d4000 to [NOCRTC]
>[  579.613732] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8800c78d4000
>[  579.613733] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:21] to ffff880026bfba00
>[  579.613734] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfba00
>[  579.613735] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:29] to ffff880026bfba00
>[  579.613736] [drm:drm_atomic_connectors_for_crtc] State ffff880026bfba00 has 1 connectors for [CRTC:21]
>[  579.613737] [drm:drm_atomic_connectors_for_crtc] State ffff880026bfba00 has 0 connectors for [CRTC:25]
>[  579.613738] [drm:drm_atomic_check_only] checking ffff880026bfba00
>[  579.613740] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  579.613742] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] keeps [ENCODER:32:DAC-32], now on [CRTC:21]
>[  579.613744] [drm:intel_plane_atomic_calc_changes] [CRTC:21] has [PLANE:18] with fb 50
>[  579.613745] [drm:intel_plane_atomic_calc_changes] [PLANE:18] visible 1 -> 1, off 0, on 0, ms 0
>[  579.613749] [drm:drm_atomic_commit] commiting ffff880026bfba00
>[  579.613760] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bfba00
>[  579.613762] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bfba00
>[  579.843656] kms_addfb_basic: executing
>[  579.843694] [drm:i915_gem_open] 
>[  579.843875] [drm:i915_gem_open] 
>[  579.843887] [drm:drm_mode_addfb2] [FB:49]
>[  579.843909] kms_addfb_basic: starting subtest bo-too-small-due-to-tiling
>[  579.843917] [drm:internal_framebuffer_create] could not create framebuffer
>[  579.843945] kms_addfb_basic: exiting, ret=0
>[  579.844006] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bfa000
>[  579.844009] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8801f4cedc00 state to ffff880026bfa000
>[  579.844011] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff880025a43c00 state to ffff880026bfa000
>[  579.844012] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8801f4ced600 state to ffff880026bfa000
>[  579.844013] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f4ced600 to [NOCRTC]
>[  579.844014] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f4ced600
>[  579.844015] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8801f4ced9c0 state to ffff880026bfa000
>[  579.844015] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f4ced9c0 to [NOCRTC]
>[  579.844016] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f4ced9c0
>[  579.844017] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f4ced180 state to ffff880026bfa000
>[  579.844018] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f4ced000 state to ffff880026bfa000
>[  579.844019] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f4ced000 to [NOCRTC]
>[  579.844019] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f4ced000
>[  579.844020] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f4cedb40 state to ffff880026bfa000
>[  579.844021] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f4cedb40 to [NOCRTC]
>[  579.844022] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f4cedb40
>[  579.844023] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8801f4ced6c0 state to ffff880026bfa000
>[  579.844024] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8801f4ced540 state to ffff880026bfa000
>[  579.844025] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f4ced540 to [NOCRTC]
>[  579.844025] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f4ced540
>[  579.844026] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8801f4ced0c0 state to ffff880026bfa000
>[  579.844027] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f4ced0c0 to [NOCRTC]
>[  579.844028] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f4ced0c0
>[  579.844030] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff880025a43c00
>[  579.844031] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f4cedc00 to [CRTC:21]
>[  579.844032] [drm:drm_atomic_set_fb_for_plane] Set [FB:50] for plane state ffff8801f4cedc00
>[  579.844033] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8801f442d380 state to ffff880026bfa000
>[  579.844034] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:21] to ffff880026bfa000
>[  579.844036] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f442d380 to [NOCRTC]
>[  579.844036] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f442d380 to [CRTC:21]
>[  579.844038] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880025a42000 state to ffff880026bfa000
>[  579.844039] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff880025a42000
>[  579.844039] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f4ced180 to [NOCRTC]
>[  579.844040] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f4ced180
>[  579.844041] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:21] to ffff880026bfa000
>[  579.844042] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfa000
>[  579.844043] [drm:drm_atomic_connectors_for_crtc] State ffff880026bfa000 has 1 connectors for [CRTC:21]
>[  579.844044] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff880025a42c00 state to ffff880026bfa000
>[  579.844045] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff880025a42c00
>[  579.844046] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f4ced6c0 to [NOCRTC]
>[  579.844046] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f4ced6c0
>[  579.844047] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:21] to ffff880026bfa000
>[  579.844048] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfa000
>[  579.844049] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:29] to ffff880026bfa000
>[  579.844050] [drm:drm_atomic_connectors_for_crtc] State ffff880026bfa000 has 1 connectors for [CRTC:21]
>[  579.844050] [drm:drm_atomic_connectors_for_crtc] State ffff880026bfa000 has 0 connectors for [CRTC:25]
>[  579.844051] [drm:drm_atomic_check_only] checking ffff880026bfa000
>[  579.844053] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  579.844055] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] keeps [ENCODER:32:DAC-32], now on [CRTC:21]
>[  579.844057] [drm:intel_plane_atomic_calc_changes] [CRTC:21] has [PLANE:18] with fb 50
>[  579.844058] [drm:intel_plane_atomic_calc_changes] [PLANE:18] visible 1 -> 1, off 0, on 0, ms 0
>[  579.844062] [drm:drm_atomic_commit] commiting ffff880026bfa000
>[  579.844074] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bfa000
>[  579.844075] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bfa000
>[  580.092924] gem_storedw_loop: executing
>[  580.092973] [drm:i915_gem_open] 
>[  580.093130] [drm:i915_gem_open] 
>[  580.093160] gem_storedw_loop: starting subtest basic-blt
>[  580.208775] gem_storedw_loop: exiting, ret=0
>[  580.208881] [drm:drm_atomic_state_init] Allocated atomic state ffff880201186600
>[  580.208884] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8801f55af300 state to ffff880201186600
>[  580.208886] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff8801f5325000 state to ffff880201186600
>[  580.208887] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8801f55af180 state to ffff880201186600
>[  580.208888] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55af180 to [NOCRTC]
>[  580.208889] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f55af180
>[  580.208890] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8801f55af0c0 state to ffff880201186600
>[  580.208891] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55af0c0 to [NOCRTC]
>[  580.208892] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f55af0c0
>[  580.208893] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f55af000 state to ffff880201186600
>[  580.208894] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f55af840 state to ffff880201186600
>[  580.208895] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55af840 to [NOCRTC]
>[  580.208895] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f55af840
>[  580.208896] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f55af900 state to ffff880201186600
>[  580.208897] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55af900 to [NOCRTC]
>[  580.208898] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f55af900
>[  580.208899] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8801f55afcc0 state to ffff880201186600
>[  580.208900] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8801f55afc00 state to ffff880201186600
>[  580.208901] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55afc00 to [NOCRTC]
>[  580.208902] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f55afc00
>[  580.208903] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8801f55afa80 state to ffff880201186600
>[  580.208903] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55afa80 to [NOCRTC]
>[  580.208904] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f55afa80
>[  580.208906] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f5325000
>[  580.208907] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55af300 to [CRTC:21]
>[  580.208908] [drm:drm_atomic_set_fb_for_plane] Set [FB:50] for plane state ffff8801f55af300
>[  580.208909] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c909b0c0 state to ffff880201186600
>[  580.208911] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:21] to ffff880201186600
>[  580.208911] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c909b0c0 to [NOCRTC]
>[  580.208912] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c909b0c0 to [CRTC:21]
>[  580.208914] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5324400 state to ffff880201186600
>[  580.208915] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f5324400
>[  580.208915] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55af000 to [NOCRTC]
>[  580.208916] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f55af000
>[  580.208917] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:21] to ffff880201186600
>[  580.208918] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880201186600
>[  580.208919] [drm:drm_atomic_connectors_for_crtc] State ffff880201186600 has 1 connectors for [CRTC:21]
>[  580.208920] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff8801f5327800 state to ffff880201186600
>[  580.208921] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f5327800
>[  580.208921] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55afcc0 to [NOCRTC]
>[  580.208922] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f55afcc0
>[  580.208923] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:21] to ffff880201186600
>[  580.208924] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880201186600
>[  580.208925] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:29] to ffff880201186600
>[  580.208925] [drm:drm_atomic_connectors_for_crtc] State ffff880201186600 has 1 connectors for [CRTC:21]
>[  580.208926] [drm:drm_atomic_connectors_for_crtc] State ffff880201186600 has 0 connectors for [CRTC:25]
>[  580.208927] [drm:drm_atomic_check_only] checking ffff880201186600
>[  580.208929] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  580.208930] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] keeps [ENCODER:32:DAC-32], now on [CRTC:21]
>[  580.208933] [drm:intel_plane_atomic_calc_changes] [CRTC:21] has [PLANE:18] with fb 50
>[  580.208934] [drm:intel_plane_atomic_calc_changes] [PLANE:18] visible 1 -> 1, off 0, on 0, ms 0
>[  580.208938] [drm:drm_atomic_commit] commiting ffff880201186600
>[  580.208950] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880201186600
>[  580.208952] [drm:drm_atomic_state_free] Freeing atomic state ffff880201186600
>[  580.435516] gem_mmap_gtt: executing
>[  580.435555] [drm:i915_gem_open] 
>[  580.435706] [drm:i915_gem_open] 
>[  580.435721] gem_mmap_gtt: starting subtest basic-copy
>[  580.585017] gem_mmap_gtt: exiting, ret=0
>[  580.585158] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bfb800
>[  580.585161] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8801f4ced180 state to ffff880026bfb800
>[  580.585163] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff880025a43400 state to ffff880026bfb800
>[  580.585164] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8801f4ced540 state to ffff880026bfb800
>[  580.585165] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f4ced540 to [NOCRTC]
>[  580.585166] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f4ced540
>[  580.585167] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8801f4cedb40 state to ffff880026bfb800
>[  580.585167] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f4cedb40 to [NOCRTC]
>[  580.585168] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f4cedb40
>[  580.585169] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f4ced6c0 state to ffff880026bfb800
>[  580.585170] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f4ced000 state to ffff880026bfb800
>[  580.585171] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f4ced000 to [NOCRTC]
>[  580.585172] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f4ced000
>[  580.585173] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f4ced0c0 state to ffff880026bfb800
>[  580.585173] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f4ced0c0 to [NOCRTC]
>[  580.585174] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f4ced0c0
>[  580.585175] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8801f4ceda80 state to ffff880026bfb800
>[  580.585176] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8801f4cedd80 state to ffff880026bfb800
>[  580.585177] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f4cedd80 to [NOCRTC]
>[  580.585177] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f4cedd80
>[  580.585178] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8801f4ced480 state to ffff880026bfb800
>[  580.585179] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f4ced480 to [NOCRTC]
>[  580.585180] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f4ced480
>[  580.585182] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff880025a43400
>[  580.585183] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f4ced180 to [CRTC:21]
>[  580.585184] [drm:drm_atomic_set_fb_for_plane] Set [FB:50] for plane state ffff8801f4ced180
>[  580.585186] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8801f442d1c0 state to ffff880026bfb800
>[  580.585187] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:21] to ffff880026bfb800
>[  580.585188] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f442d1c0 to [NOCRTC]
>[  580.585189] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f442d1c0 to [CRTC:21]
>[  580.585190] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880025a40800 state to ffff880026bfb800
>[  580.585191] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff880025a40800
>[  580.585192] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f4ced6c0 to [NOCRTC]
>[  580.585192] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f4ced6c0
>[  580.585193] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:21] to ffff880026bfb800
>[  580.585194] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfb800
>[  580.585195] [drm:drm_atomic_connectors_for_crtc] State ffff880026bfb800 has 1 connectors for [CRTC:21]
>[  580.585196] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff880025a40000 state to ffff880026bfb800
>[  580.585197] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff880025a40000
>[  580.585198] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f4ceda80 to [NOCRTC]
>[  580.585199] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f4ceda80
>[  580.585200] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:21] to ffff880026bfb800
>[  580.585200] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880026bfb800
>[  580.585201] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:29] to ffff880026bfb800
>[  580.585202] [drm:drm_atomic_connectors_for_crtc] State ffff880026bfb800 has 1 connectors for [CRTC:21]
>[  580.585203] [drm:drm_atomic_connectors_for_crtc] State ffff880026bfb800 has 0 connectors for [CRTC:25]
>[  580.585204] [drm:drm_atomic_check_only] checking ffff880026bfb800
>[  580.585206] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  580.585207] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] keeps [ENCODER:32:DAC-32], now on [CRTC:21]
>[  580.585210] [drm:intel_plane_atomic_calc_changes] [CRTC:21] has [PLANE:18] with fb 50
>[  580.585211] [drm:intel_plane_atomic_calc_changes] [PLANE:18] visible 1 -> 1, off 0, on 0, ms 0
>[  580.585214] [drm:drm_atomic_commit] commiting ffff880026bfb800
>[  580.585226] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bfb800
>[  580.585228] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bfb800
>[  580.790444] gem_ctx_param_basic: executing
>[  580.790480] [drm:i915_gem_open] 
>[  580.790491] [drm:i915_gem_open] 
>[  580.790656] [drm:i915_gem_context_create_ioctl] HW context 1 created
>[  580.790673] gem_ctx_param_basic: starting subtest invalid-ctx-set
>[  580.790702] gem_ctx_param_basic: exiting, ret=0
>[  580.790765] [drm:drm_atomic_state_init] Allocated atomic state ffff880201187c00
>[  580.790767] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8801f55af000 state to ffff880201187c00
>[  580.790769] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff8801f5326400 state to ffff880201187c00
>[  580.790770] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8801f55af0c0 state to ffff880201187c00
>[  580.790771] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55af0c0 to [NOCRTC]
>[  580.790772] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f55af0c0
>[  580.790773] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8801f55af480 state to ffff880201187c00
>[  580.790774] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55af480 to [NOCRTC]
>[  580.790774] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f55af480
>[  580.790776] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f55af180 state to ffff880201187c00
>[  580.790777] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f55af300 state to ffff880201187c00
>[  580.790777] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55af300 to [NOCRTC]
>[  580.790778] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f55af300
>[  580.790779] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f6888cc0 state to ffff880201187c00
>[  580.790780] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f6888cc0 to [NOCRTC]
>[  580.790780] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f6888cc0
>[  580.790781] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8801f6888900 state to ffff880201187c00
>[  580.790783] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8801f6888c00 state to ffff880201187c00
>[  580.790783] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f6888c00 to [NOCRTC]
>[  580.790784] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f6888c00
>[  580.790786] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8801f6888000 state to ffff880201187c00
>[  580.790786] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f6888000 to [NOCRTC]
>[  580.790830] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f6888000
>[  580.790832] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f5326400
>[  580.790833] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55af000 to [CRTC:21]
>[  580.790835] [drm:drm_atomic_set_fb_for_plane] Set [FB:50] for plane state ffff8801f55af000
>[  580.790837] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c909b660 state to ffff880201187c00
>[  580.790838] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:21] to ffff880201187c00
>[  580.790839] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c909b660 to [NOCRTC]
>[  580.790840] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c909b660 to [CRTC:21]
>[  580.790843] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5326000 state to ffff880201187c00
>[  580.790843] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f5326000
>[  580.790853] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55af180 to [NOCRTC]
>[  580.790854] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f55af180
>[  580.790856] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:21] to ffff880201187c00
>[  580.790857] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880201187c00
>[  580.790858] [drm:drm_atomic_connectors_for_crtc] State ffff880201187c00 has 1 connectors for [CRTC:21]
>[  580.790859] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff8801f5327800 state to ffff880201187c00
>[  580.790860] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f5327800
>[  580.790861] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f6888900 to [NOCRTC]
>[  580.790861] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f6888900
>[  580.790862] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:21] to ffff880201187c00
>[  580.790863] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880201187c00
>[  580.790864] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:29] to ffff880201187c00
>[  580.790865] [drm:drm_atomic_connectors_for_crtc] State ffff880201187c00 has 1 connectors for [CRTC:21]
>[  580.790866] [drm:drm_atomic_connectors_for_crtc] State ffff880201187c00 has 0 connectors for [CRTC:25]
>[  580.790867] [drm:drm_atomic_check_only] checking ffff880201187c00
>[  580.790869] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  580.790871] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] keeps [ENCODER:32:DAC-32], now on [CRTC:21]
>[  580.790874] [drm:intel_plane_atomic_calc_changes] [CRTC:21] has [PLANE:18] with fb 50
>[  580.790875] [drm:intel_plane_atomic_calc_changes] [PLANE:18] visible 1 -> 1, off 0, on 0, ms 0
>[  580.790879] [drm:drm_atomic_commit] commiting ffff880201187c00
>[  580.790891] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880201187c00
>[  580.790894] [drm:drm_atomic_state_free] Freeing atomic state ffff880201187c00
>[  581.003577] kms_pipe_crc_basic: executing
>[  581.003645] [drm:i915_gem_open] 
>[  581.003910] [drm:i915_gem_open] 
>[  581.003924] [drm:i915_gem_open] 
>[  581.003933] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[2] ENCODERS[2]
>[  581.003937] [drm:drm_mode_getresources] [CRTC:21]
>[  581.003938] [drm:drm_mode_getresources] [CRTC:25]
>[  581.003939] [drm:drm_mode_getresources] [CRTC:29]
>[  581.003941] [drm:drm_mode_getresources] [ENCODER:32:DAC-32]
>[  581.003942] [drm:drm_mode_getresources] [ENCODER:33:TMDS-33]
>[  581.003943] [drm:drm_mode_getresources] [CONNECTOR:31:VGA-1]
>[  581.003945] [drm:drm_mode_getresources] [CONNECTOR:34:HDMI-A-1]
>[  581.003946] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[2] ENCODERS[2]
>[  581.003952] [drm:drm_mode_getconnector] [CONNECTOR:31:?]
>[  581.003956] [drm:drm_mode_getconnector] [CONNECTOR:31:?]
>[  581.003962] [drm:drm_mode_getconnector] [CONNECTOR:34:?]
>[  581.003964] [drm:drm_mode_getconnector] [CONNECTOR:34:?]
>[  581.004019] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[2] ENCODERS[2]
>[  581.004022] [drm:drm_mode_getresources] [CRTC:21]
>[  581.004023] [drm:drm_mode_getresources] [CRTC:25]
>[  581.004024] [drm:drm_mode_getresources] [CRTC:29]
>[  581.004026] [drm:drm_mode_getresources] [ENCODER:32:DAC-32]
>[  581.004027] [drm:drm_mode_getresources] [ENCODER:33:TMDS-33]
>[  581.004028] [drm:drm_mode_getresources] [CONNECTOR:31:VGA-1]
>[  581.004030] [drm:drm_mode_getresources] [CONNECTOR:34:HDMI-A-1]
>[  581.004031] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[2] ENCODERS[2]
>[  581.004221] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[2] ENCODERS[2]
>[  581.004222] [drm:drm_mode_getresources] [CRTC:21]
>[  581.004223] [drm:drm_mode_getresources] [CRTC:25]
>[  581.004224] [drm:drm_mode_getresources] [CRTC:29]
>[  581.004226] [drm:drm_mode_getresources] [ENCODER:32:DAC-32]
>[  581.004227] [drm:drm_mode_getresources] [ENCODER:33:TMDS-33]
>[  581.004228] [drm:drm_mode_getresources] [CONNECTOR:31:VGA-1]
>[  581.004230] [drm:drm_mode_getresources] [CONNECTOR:34:HDMI-A-1]
>[  581.004231] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[2] ENCODERS[2]
>[  581.004233] [drm:drm_mode_getconnector] [CONNECTOR:31:?]
>[  581.004235] [drm:drm_mode_getconnector] [CONNECTOR:31:?]
>[  581.004256] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[2] ENCODERS[2]
>[  581.004258] [drm:drm_mode_getresources] [CRTC:21]
>[  581.004259] [drm:drm_mode_getresources] [CRTC:25]
>[  581.004260] [drm:drm_mode_getresources] [CRTC:29]
>[  581.004262] [drm:drm_mode_getresources] [ENCODER:32:DAC-32]
>[  581.004263] [drm:drm_mode_getresources] [ENCODER:33:TMDS-33]
>[  581.004264] [drm:drm_mode_getresources] [CONNECTOR:31:VGA-1]
>[  581.004265] [drm:drm_mode_getresources] [CONNECTOR:34:HDMI-A-1]
>[  581.004267] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[2] ENCODERS[2]
>[  581.004269] [drm:drm_mode_getconnector] [CONNECTOR:34:?]
>[  581.004271] [drm:drm_mode_getconnector] [CONNECTOR:34:?]
>[  581.004294] kms_pipe_crc_basic: starting subtest read-crc-pipe-A-frame-sequence
>[  581.004311] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[2] ENCODERS[2]
>[  581.004313] [drm:drm_mode_getresources] [CRTC:21]
>[  581.004314] [drm:drm_mode_getresources] [CRTC:25]
>[  581.004315] [drm:drm_mode_getresources] [CRTC:29]
>[  581.004317] [drm:drm_mode_getresources] [ENCODER:32:DAC-32]
>[  581.004318] [drm:drm_mode_getresources] [ENCODER:33:TMDS-33]
>[  581.004319] [drm:drm_mode_getresources] [CONNECTOR:31:VGA-1]
>[  581.004320] [drm:drm_mode_getresources] [CONNECTOR:34:HDMI-A-1]
>[  581.004322] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[2] ENCODERS[2]
>[  581.004324] [drm:drm_mode_getconnector] [CONNECTOR:31:?]
>[  581.004326] [drm:drm_mode_getconnector] [CONNECTOR:31:?]
>[  581.004334] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[2] ENCODERS[2]
>[  581.004336] [drm:drm_mode_getresources] [CRTC:21]
>[  581.004337] [drm:drm_mode_getresources] [CRTC:25]
>[  581.004338] [drm:drm_mode_getresources] [CRTC:29]
>[  581.004339] [drm:drm_mode_getresources] [ENCODER:32:DAC-32]
>[  581.004341] [drm:drm_mode_getresources] [ENCODER:33:TMDS-33]
>[  581.004342] [drm:drm_mode_getresources] [CONNECTOR:31:VGA-1]
>[  581.004343] [drm:drm_mode_getresources] [CONNECTOR:34:HDMI-A-1]
>[  581.004344] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[2] ENCODERS[2]
>[  581.004347] [drm:drm_mode_getconnector] [CONNECTOR:34:?]
>[  581.004348] [drm:drm_mode_getconnector] [CONNECTOR:34:?]
>[  581.004371] [drm:drm_mode_addfb2] [FB:49]
>[  581.008864] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[2] ENCODERS[2]
>[  581.008867] [drm:drm_mode_getresources] [CRTC:21]
>[  581.008868] [drm:drm_mode_getresources] [CRTC:25]
>[  581.008869] [drm:drm_mode_getresources] [CRTC:29]
>[  581.008870] [drm:drm_mode_getresources] [ENCODER:32:DAC-32]
>[  581.008871] [drm:drm_mode_getresources] [ENCODER:33:TMDS-33]
>[  581.008872] [drm:drm_mode_getresources] [CONNECTOR:31:VGA-1]
>[  581.008873] [drm:drm_mode_getresources] [CONNECTOR:34:HDMI-A-1]
>[  581.008874] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[2] ENCODERS[2]
>[  581.008877] [drm:drm_mode_getconnector] [CONNECTOR:31:?]
>[  581.008880] [drm:drm_mode_getconnector] [CONNECTOR:31:?]
>[  581.008889] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[2] ENCODERS[2]
>[  581.008891] [drm:drm_mode_getresources] [CRTC:21]
>[  581.008891] [drm:drm_mode_getresources] [CRTC:25]
>[  581.008892] [drm:drm_mode_getresources] [CRTC:29]
>[  581.008893] [drm:drm_mode_getresources] [ENCODER:32:DAC-32]
>[  581.008894] [drm:drm_mode_getresources] [ENCODER:33:TMDS-33]
>[  581.008895] [drm:drm_mode_getresources] [CONNECTOR:31:VGA-1]
>[  581.008896] [drm:drm_mode_getresources] [CONNECTOR:34:HDMI-A-1]
>[  581.008897] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[2] ENCODERS[2]
>[  581.008899] [drm:drm_mode_getconnector] [CONNECTOR:34:?]
>[  581.008900] [drm:drm_mode_getconnector] [CONNECTOR:34:?]
>[  581.008908] [drm:drm_mode_setcrtc] [CRTC:21]
>[  581.008912] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  581.008915] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bfb800
>[  581.008918] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff880025a41800 state to ffff880026bfb800
>[  581.008920] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8800c78d4300 state to ffff880026bfb800
>[  581.008922] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff880025a41800
>[  581.008924] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800c78d4300 to [CRTC:21]
>[  581.008925] [drm:drm_atomic_set_fb_for_plane] Set [FB:49] for plane state ffff8800c78d4300
>[  581.008927] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8801f442db60 state to ffff880026bfb800
>[  581.008928] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:21] to ffff880026bfb800
>[  581.008929] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f442db60 to [NOCRTC]
>[  581.008931] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f442db60 to [CRTC:21]
>[  581.008932] [drm:drm_atomic_check_only] checking ffff880026bfb800
>[  581.008934] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  581.008936] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] keeps [ENCODER:32:DAC-32], now on [CRTC:21]
>[  581.008939] [drm:intel_plane_atomic_calc_changes] [CRTC:21] has [PLANE:18] with fb 49
>[  581.008940] [drm:intel_plane_atomic_calc_changes] [PLANE:18] visible 1 -> 1, off 0, on 0, ms 0
>[  581.008943] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8800c78d4b40 state to ffff880026bfb800
>[  581.008944] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8800c78d4e40 state to ffff880026bfb800
>[  581.008947] [drm:drm_atomic_commit] commiting ffff880026bfb800
>[  581.016137] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bfb800
>[  581.016143] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bfb800
>[  581.032841] [drm:drm_atomic_state_init] Allocated atomic state ffff880201187c00
>[  581.032846] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff8801f5326400 state to ffff880201187c00
>[  581.032847] [drm:drm_atomic_check_only] checking ffff880201187c00
>[  581.032850] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8801f68883c0 state to ffff880201187c00
>[  581.032851] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8801f6888e40 state to ffff880201187c00
>[  581.032852] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8801f6888d80 state to ffff880201187c00
>[  581.032855] [drm:drm_atomic_commit] commiting ffff880201187c00
>[  581.032861] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880201187c00
>[  581.032863] [drm:drm_atomic_state_free] Freeing atomic state ffff880201187c00
>[  581.032865] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[  581.116262] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[  581.132881] [drm:drm_atomic_state_init] Allocated atomic state ffff880201187c00
>[  581.132886] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff8801f5324400 state to ffff880201187c00
>[  581.132888] [drm:drm_atomic_check_only] checking ffff880201187c00
>[  581.132891] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8801f6888b40 state to ffff880201187c00
>[  581.132892] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8801f68886c0 state to ffff880201187c00
>[  581.132894] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8801f6888300 state to ffff880201187c00
>[  581.132896] [drm:drm_atomic_commit] commiting ffff880201187c00
>[  581.132902] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880201187c00
>[  581.132904] [drm:drm_atomic_state_free] Freeing atomic state ffff880201187c00
>[  581.132943] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[2] ENCODERS[2]
>[  581.132945] [drm:drm_mode_getresources] [CRTC:21]
>[  581.132946] [drm:drm_mode_getresources] [CRTC:25]
>[  581.132947] [drm:drm_mode_getresources] [CRTC:29]
>[  581.132948] [drm:drm_mode_getresources] [ENCODER:32:DAC-32]
>[  581.132949] [drm:drm_mode_getresources] [ENCODER:33:TMDS-33]
>[  581.132950] [drm:drm_mode_getresources] [CONNECTOR:31:VGA-1]
>[  581.132950] [drm:drm_mode_getresources] [CONNECTOR:34:HDMI-A-1]
>[  581.132951] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[2] ENCODERS[2]
>[  581.132954] [drm:drm_mode_getconnector] [CONNECTOR:31:?]
>[  581.132957] [drm:drm_mode_getconnector] [CONNECTOR:31:?]
>[  581.132964] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[2] ENCODERS[2]
>[  581.132965] [drm:drm_mode_getresources] [CRTC:21]
>[  581.132966] [drm:drm_mode_getresources] [CRTC:25]
>[  581.132966] [drm:drm_mode_getresources] [CRTC:29]
>[  581.132967] [drm:drm_mode_getresources] [ENCODER:32:DAC-32]
>[  581.132968] [drm:drm_mode_getresources] [ENCODER:33:TMDS-33]
>[  581.132969] [drm:drm_mode_getresources] [CONNECTOR:31:VGA-1]
>[  581.132969] [drm:drm_mode_getresources] [CONNECTOR:34:HDMI-A-1]
>[  581.132970] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[2] ENCODERS[2]
>[  581.132971] [drm:drm_mode_getconnector] [CONNECTOR:34:?]
>[  581.132973] [drm:drm_mode_getconnector] [CONNECTOR:34:?]
>[  581.132977] [drm:drm_mode_setcrtc] [CRTC:21]
>[  581.132978] [drm:drm_atomic_state_init] Allocated atomic state ffff880201187c00
>[  581.132980] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff8801f5326400 state to ffff880201187c00
>[  581.132981] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8801f6888600 state to ffff880201187c00
>[  581.132982] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f5326400
>[  581.132983] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f6888600 to [NOCRTC]
>[  581.132984] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f6888600
>[  581.132985] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:21] to ffff880201187c00
>[  581.132986] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c909b6c0 state to ffff880201187c00
>[  581.132987] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c909b6c0 to [NOCRTC]
>[  581.132988] [drm:drm_atomic_check_only] checking ffff880201187c00
>[  581.132989] [drm:drm_atomic_helper_check_modeset] [CRTC:21] mode changed
>[  581.132990] [drm:drm_atomic_helper_check_modeset] [CRTC:21] enable changed
>[  581.132991] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  581.132991] [drm:update_connector_routing] Disabling [CONNECTOR:31:VGA-1]
>[  581.132992] [drm:drm_atomic_helper_check_modeset] [CRTC:21] active changed
>[  581.132993] [drm:drm_atomic_helper_check_modeset] [CRTC:21] needs all connectors, enable: n, active: n
>[  581.132994] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:21] to ffff880201187c00
>[  581.132995] [drm:drm_atomic_connectors_for_crtc] State ffff880201187c00 has 0 connectors for [CRTC:21]
>[  581.132998] [drm:intel_plane_atomic_calc_changes] [CRTC:21] has [PLANE:18] with fb -1
>[  581.132999] [drm:intel_plane_atomic_calc_changes] [PLANE:18] visible 1 -> 0, off 1, on 0, ms 1
>[  581.133000] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8801f6888d80 state to ffff880201187c00
>[  581.133001] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8801f6888e40 state to ffff880201187c00
>[  581.133003] [drm:drm_atomic_commit] commiting ffff880201187c00
>[  581.133015] [drm:intel_disable_pipe] disabling pipe A
>[  581.167915] [drm:intel_disable_shared_dpll] disable SPLL (active 1, on? 1) for crtc 21
>[  581.167918] [drm:intel_disable_shared_dpll] disabling SPLL
>[  581.167926] [drm:intel_power_well_disable] disabling display
>[  581.167927] [drm:hsw_set_power_well] Requesting to disable the power well
>[  581.167928] [drm:intel_power_well_disable] disabling always-on
>[  581.167937] [drm:intel_runtime_suspend] Suspending device
>[  581.167997] [drm:hsw_enable_pc8] Enabling package C8+
>[  581.182463] [drm:intel_runtime_suspend] Device suspended
>[  581.186847] [drm:intel_runtime_resume] Resuming device
>[  581.188917] [drm:hsw_disable_pc8] Disabling package C8+
>[  581.190821] [drm:intel_update_cdclk] Current CD clock rate: 540000 kHz
>[  581.301866] [drm:intel_runtime_resume] Device resumed
>[  581.301870] [drm:intel_power_well_enable] enabling display
>[  581.301871] [drm:hsw_set_power_well] Enabling power well
>[  581.303941] [drm:intel_power_well_disable] disabling display
>[  581.303945] [drm:hsw_set_power_well] Requesting to disable the power well
>[  581.303950] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  581.303952] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  581.303953] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  581.303956] [drm:check_crtc_state] [CRTC:21]
>[  581.303957] [drm:check_shared_dpll_state] WRPLL 1
>[  581.303958] [drm:check_shared_dpll_state] WRPLL 2
>[  581.303959] [drm:check_shared_dpll_state] SPLL
>[  581.303961] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880201187c00
>[  581.303964] [drm:drm_atomic_state_free] Freeing atomic state ffff880201187c00
>[  581.304622] [drm:drm_mode_addfb2] [FB:49]
>[  581.307427] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[2] ENCODERS[2]
>[  581.307430] [drm:drm_mode_getresources] [CRTC:21]
>[  581.307431] [drm:drm_mode_getresources] [CRTC:25]
>[  581.307431] [drm:drm_mode_getresources] [CRTC:29]
>[  581.307432] [drm:drm_mode_getresources] [ENCODER:32:DAC-32]
>[  581.307433] [drm:drm_mode_getresources] [ENCODER:33:TMDS-33]
>[  581.307434] [drm:drm_mode_getresources] [CONNECTOR:31:VGA-1]
>[  581.307435] [drm:drm_mode_getresources] [CONNECTOR:34:HDMI-A-1]
>[  581.307435] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[2] ENCODERS[2]
>[  581.307437] [drm:drm_mode_getconnector] [CONNECTOR:31:?]
>[  581.307440] [drm:drm_mode_getconnector] [CONNECTOR:31:?]
>[  581.307448] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[2] ENCODERS[2]
>[  581.307449] [drm:drm_mode_getresources] [CRTC:21]
>[  581.307450] [drm:drm_mode_getresources] [CRTC:25]
>[  581.307451] [drm:drm_mode_getresources] [CRTC:29]
>[  581.307451] [drm:drm_mode_getresources] [ENCODER:32:DAC-32]
>[  581.307452] [drm:drm_mode_getresources] [ENCODER:33:TMDS-33]
>[  581.307453] [drm:drm_mode_getresources] [CONNECTOR:31:VGA-1]
>[  581.307453] [drm:drm_mode_getresources] [CONNECTOR:34:HDMI-A-1]
>[  581.307454] [drm:drm_mode_getresources] CRTC[3] CONNECTORS[2] ENCODERS[2]
>[  581.307455] [drm:drm_mode_getconnector] [CONNECTOR:34:?]
>[  581.307457] [drm:drm_mode_getconnector] [CONNECTOR:34:?]
>[  581.307461] [drm:drm_mode_setcrtc] [CRTC:21]
>[  581.307464] [drm:drm_mode_setcrtc] [CONNECTOR:31:VGA-1]
>[  581.307467] [drm:drm_atomic_state_init] Allocated atomic state ffff880026bfa800
>[  581.307469] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff880025a41c00 state to ffff880026bfa800
>[  581.307470] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8800c78d4000 state to ffff880026bfa800
>[  581.307472] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff880025a41c00
>[  581.307473] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8800c78d4000 to [CRTC:21]
>[  581.307474] [drm:drm_atomic_set_fb_for_plane] Set [FB:49] for plane state ffff8800c78d4000
>[  581.307476] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8801f442d340 state to ffff880026bfa800
>[  581.307477] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:21] to ffff880026bfa800
>[  581.307478] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801f442d340 to [CRTC:21]
>[  581.307479] [drm:drm_atomic_check_only] checking ffff880026bfa800
>[  581.307480] [drm:drm_atomic_helper_check_modeset] [CRTC:21] mode changed
>[  581.307481] [drm:drm_atomic_helper_check_modeset] [CRTC:21] enable changed
>[  581.307482] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  581.307483] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] using [ENCODER:32:DAC-32] on [CRTC:21]
>[  581.307484] [drm:drm_atomic_helper_check_modeset] [CRTC:21] active changed
>[  581.307485] [drm:drm_atomic_helper_check_modeset] [CRTC:21] needs all connectors, enable: y, active: y
>[  581.307486] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:21] to ffff880026bfa800
>[  581.307487] [drm:drm_atomic_connectors_for_crtc] State ffff880026bfa800 has 1 connectors for [CRTC:21]
>[  581.307488] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:21] to ffff880026bfa800
>[  581.307489] [drm:connected_sink_compute_bpp] [CONNECTOR:31:VGA-1] checking for sink bpp constrains
>[  581.307490] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to default limit of 24
>[  581.307492] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 2
>[  581.307493] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  581.307494] [drm:intel_dump_pipe_config] [CRTC:21][modeset] config ffff880025a41c00 for pipe A
>[  581.307495] [drm:intel_dump_pipe_config] cpu_transcoder: A
>[  581.307496] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
>[  581.307497] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 7176920, gmch_n: 8388608, link_m: 299038, link_n: 524288, tu: 64
>[  581.307498] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
>[  581.307499] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
>[  581.307500] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[  581.307500] [drm:intel_dump_pipe_config] requested mode:
>[  581.307502] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  581.307503] [drm:intel_dump_pipe_config] adjusted mode:
>[  581.307504] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  581.307505] [drm:intel_dump_crtc_timings] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  581.307506] [drm:intel_dump_pipe_config] port clock: 270000
>[  581.307506] [drm:intel_dump_pipe_config] pipe src size: 1920x1200
>[  581.307507] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
>[  581.307508] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
>[  581.307509] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  581.307510] [drm:intel_dump_pipe_config] ips: 0
>[  581.307510] [drm:intel_dump_pipe_config] double wide: 0
>[  581.307511] [drm:intel_dump_pipe_config] ddi_pll_sel: 1610612736; dpll_hw_state: wrpll: 0x0 spll: 0x94000000
>[  581.307512] [drm:intel_dump_pipe_config] planes on this crtc
>[  581.307513] [drm:intel_dump_pipe_config] STANDARD PLANE:18 plane: 0.0 idx: 0 disabled, scaler_id = 0
>[  581.307514] [drm:intel_dump_pipe_config] CURSOR PLANE:20 plane: 0.1 idx: 1 disabled, scaler_id = 0
>[  581.307515] [drm:intel_dump_pipe_config] STANDARD PLANE:22 plane: 0.1 idx: 2 disabled, scaler_id = 0
>[  581.307517] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff880025a41000 state to ffff880026bfa800
>[  581.307518] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff880025a41800 state to ffff880026bfa800
>[  581.307520] [drm:intel_plane_atomic_calc_changes] [CRTC:21] has [PLANE:18] with fb 49
>[  581.307521] [drm:intel_plane_atomic_calc_changes] [PLANE:18] visible 0 -> 1, off 0, on 1, ms 1
>[  581.307524] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8800c78d4240 state to ffff880026bfa800
>[  581.307525] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8800c78d4780 state to ffff880026bfa800
>[  581.307527] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8800c78d4180 state to ffff880026bfa800
>[  581.307528] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8800c78d4d80 state to ffff880026bfa800
>[  581.307529] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8800c78d4480 state to ffff880026bfa800
>[  581.307530] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8800c78d4c00 state to ffff880026bfa800
>[  581.307532] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8800c78d4540 state to ffff880026bfa800
>[  581.307533] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8800c78d40c0 state to ffff880026bfa800
>[  581.307534] [drm:drm_atomic_commit] commiting ffff880026bfa800
>[  581.309919] [drm:intel_power_well_enable] enabling always-on
>[  581.309920] [drm:intel_power_well_enable] enabling display
>[  581.309922] [drm:hsw_set_power_well] Enabling power well
>[  581.311997] [drm:intel_enable_shared_dpll] enable SPLL (active 0, on? 0) for crtc 21
>[  581.312000] [drm:intel_enable_shared_dpll] enabling SPLL
>[  581.312889] [drm:hsw_fdi_link_train] FDI link training done on step 0
>[  581.312954] [drm:intel_enable_pipe] enabling pipe A
>[  581.312968] [drm:lpt_program_iclkip] iCLKIP clock: found settings for 154000KHz refresh rate: auxdiv=0, divsel=f, phasedir=0, phaseinc=22
>[  581.379806] [drm:intel_connector_check_state] [CONNECTOR:31:VGA-1]
>[  581.379810] [drm:check_encoder_state] [ENCODER:32:DAC-32]
>[  581.379811] [drm:check_encoder_state] [ENCODER:33:TMDS-33]
>[  581.379813] [drm:check_crtc_state] [CRTC:21]
>[  581.379825] [drm:check_shared_dpll_state] WRPLL 1
>[  581.379826] [drm:check_shared_dpll_state] WRPLL 2
>[  581.379827] [drm:check_shared_dpll_state] SPLL
>[  581.379828] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880026bfa800
>[  581.379832] [drm:drm_atomic_state_free] Freeing atomic state ffff880026bfa800
>[  581.396514] [drm:drm_atomic_state_init] Allocated atomic state ffff880201186600
>[  581.396518] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff8801f5327800 state to ffff880201186600
>[  581.396519] [drm:drm_atomic_check_only] checking ffff880201186600
>[  581.396523] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8801f6888c00 state to ffff880201186600
>[  581.396524] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8801f6888900 state to ffff880201186600
>[  581.396525] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8801f6888cc0 state to ffff880201186600
>[  581.396527] [drm:drm_atomic_commit] commiting ffff880201186600
>[  581.396533] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880201186600
>[  581.396535] [drm:drm_atomic_state_free] Freeing atomic state ffff880201186600
>[  581.396537] [drm:pipe_crc_set_source] collecting CRCs for pipe A, pf
>[  581.479934] [drm:pipe_crc_set_source] stopping CRCs for pipe A
>[  581.496554] [drm:drm_atomic_state_init] Allocated atomic state ffff880201186600
>[  581.496558] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff8801f5326000 state to ffff880201186600
>[  581.496560] [drm:drm_atomic_check_only] checking ffff880201186600
>[  581.496563] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8801f6888e40 state to ffff880201186600
>[  581.496565] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8801f6888d80 state to ffff880201186600
>[  581.496566] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8801f6888600 state to ffff880201186600
>[  581.496568] [drm:drm_atomic_commit] commiting ffff880201186600
>[  581.496574] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880201186600
>[  581.496576] [drm:drm_atomic_state_free] Freeing atomic state ffff880201186600
>[  581.496658] kms_pipe_crc_basic: exiting, ret=0
>[  581.496697] [drm:drm_atomic_state_init] Allocated atomic state ffff880201186600
>[  581.496698] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8801f6888cc0 state to ffff880201186600
>[  581.496699] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff8801f5327800 state to ffff880201186600
>[  581.496700] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8801f6888900 state to ffff880201186600
>[  581.496701] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f6888900 to [NOCRTC]
>[  581.496702] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f6888900
>[  581.496702] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8801f6888c00 state to ffff880201186600
>[  581.496703] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f6888c00 to [NOCRTC]
>[  581.496703] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f6888c00
>[  581.496704] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f68883c0 state to ffff880201186600
>[  581.496704] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f68889c0 state to ffff880201186600
>[  581.496705] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f68889c0 to [NOCRTC]
>[  581.496705] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f68889c0
>[  581.496706] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f6888f00 state to ffff880201186600
>[  581.496706] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f6888f00 to [NOCRTC]
>[  581.496707] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f6888f00
>[  581.496707] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8801f6888780 state to ffff880201186600
>[  581.496708] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8801f6888480 state to ffff880201186600
>[  581.496708] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f6888480 to [NOCRTC]
>[  581.496709] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f6888480
>[  581.496710] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8801f6888540 state to ffff880201186600
>[  581.496710] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f6888540 to [NOCRTC]
>[  581.496710] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f6888540
>[  581.496713] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f5327800
>[  581.496713] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f6888cc0 to [CRTC:21]
>[  581.496714] [drm:drm_atomic_set_fb_for_plane] Set [FB:50] for plane state ffff8801f6888cc0
>[  581.496715] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c909bb60 state to ffff880201186600
>[  581.496716] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:21] to ffff880201186600
>[  581.496717] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c909bb60 to [NOCRTC]
>[  581.496717] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c909bb60 to [CRTC:21]
>[  581.496718] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5326400 state to ffff880201186600
>[  581.496719] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f5326400
>[  581.496719] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f68883c0 to [NOCRTC]
>[  581.496720] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f68883c0
>[  581.496720] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:21] to ffff880201186600
>[  581.496721] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880201186600
>[  581.496722] [drm:drm_atomic_connectors_for_crtc] State ffff880201186600 has 1 connectors for [CRTC:21]
>[  581.496723] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff8801f5325000 state to ffff880201186600
>[  581.496723] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f5325000
>[  581.496724] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f6888780 to [NOCRTC]
>[  581.496724] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f6888780
>[  581.496725] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:21] to ffff880201186600
>[  581.496725] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880201186600
>[  581.496726] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:29] to ffff880201186600
>[  581.496726] [drm:drm_atomic_connectors_for_crtc] State ffff880201186600 has 1 connectors for [CRTC:21]
>[  581.496727] [drm:drm_atomic_connectors_for_crtc] State ffff880201186600 has 0 connectors for [CRTC:25]
>[  581.496727] [drm:drm_atomic_check_only] checking ffff880201186600
>[  581.496729] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  581.496730] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] keeps [ENCODER:32:DAC-32], now on [CRTC:21]
>[  581.496732] [drm:intel_plane_atomic_calc_changes] [CRTC:21] has [PLANE:18] with fb 50
>[  581.496733] [drm:intel_plane_atomic_calc_changes] [PLANE:18] visible 1 -> 1, off 0, on 0, ms 0
>[  581.496736] [drm:drm_atomic_commit] commiting ffff880201186600
>[  581.513230] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880201186600
>[  581.513235] [drm:drm_atomic_state_free] Freeing atomic state ffff880201186600
>[  581.517530] [drm:drm_atomic_state_init] Allocated atomic state ffff880201186600
>[  581.517533] [drm:drm_atomic_get_plane_state] Added [PLANE:18] ffff8801f6888000 state to ffff880201186600
>[  581.517535] [drm:drm_atomic_get_crtc_state] Added [CRTC:21] ffff8801f5327c00 state to ffff880201186600
>[  581.517536] [drm:drm_atomic_get_plane_state] Added [PLANE:20] ffff8801f6888d80 state to ffff880201186600
>[  581.517537] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f6888d80 to [NOCRTC]
>[  581.517538] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f6888d80
>[  581.517539] [drm:drm_atomic_get_plane_state] Added [PLANE:22] ffff8801f6888e40 state to ffff880201186600
>[  581.517540] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f6888e40 to [NOCRTC]
>[  581.517540] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f6888e40
>[  581.517541] [drm:drm_atomic_get_plane_state] Added [PLANE:23] ffff8801f6888600 state to ffff880201186600
>[  581.517542] [drm:drm_atomic_get_plane_state] Added [PLANE:24] ffff8801f68886c0 state to ffff880201186600
>[  581.517543] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f68886c0 to [NOCRTC]
>[  581.517544] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f68886c0
>[  581.517545] [drm:drm_atomic_get_plane_state] Added [PLANE:26] ffff8801f6888b40 state to ffff880201186600
>[  581.517545] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f6888b40 to [NOCRTC]
>[  581.517546] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f6888b40
>[  581.517547] [drm:drm_atomic_get_plane_state] Added [PLANE:27] ffff8801f55af300 state to ffff880201186600
>[  581.517549] [drm:drm_atomic_get_plane_state] Added [PLANE:28] ffff8801f55af180 state to ffff880201186600
>[  581.517549] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55af180 to [NOCRTC]
>[  581.517550] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f55af180
>[  581.517551] [drm:drm_atomic_get_plane_state] Added [PLANE:30] ffff8801f55af480 state to ffff880201186600
>[  581.517552] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55af480 to [NOCRTC]
>[  581.517553] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f55af480
>[  581.517555] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1200] for CRTC state ffff8801f5327c00
>[  581.517556] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f6888000 to [CRTC:21]
>[  581.517557] [drm:drm_atomic_set_fb_for_plane] Set [FB:50] for plane state ffff8801f6888000
>[  581.517559] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:31] ffff8800c909b8c0 state to ffff880201186600
>[  581.517560] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:21] to ffff880201186600
>[  581.517561] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c909b8c0 to [NOCRTC]
>[  581.517561] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8800c909b8c0 to [CRTC:21]
>[  581.517563] [drm:drm_atomic_get_crtc_state] Added [CRTC:25] ffff8801f5324000 state to ffff880201186600
>[  581.517564] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f5324000
>[  581.517564] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f6888600 to [NOCRTC]
>[  581.517565] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f6888600
>[  581.517566] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:21] to ffff880201186600
>[  581.517567] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880201186600
>[  581.517568] [drm:drm_atomic_connectors_for_crtc] State ffff880201186600 has 1 connectors for [CRTC:21]
>[  581.517569] [drm:drm_atomic_get_crtc_state] Added [CRTC:29] ffff8801f5324400 state to ffff880201186600
>[  581.517570] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8801f5324400
>[  581.517571] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801f55af300 to [NOCRTC]
>[  581.517572] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801f55af300
>[  581.517572] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:21] to ffff880201186600
>[  581.517573] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:25] to ffff880201186600
>[  581.517574] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:29] to ffff880201186600
>[  581.517575] [drm:drm_atomic_connectors_for_crtc] State ffff880201186600 has 1 connectors for [CRTC:21]
>[  581.517576] [drm:drm_atomic_connectors_for_crtc] State ffff880201186600 has 0 connectors for [CRTC:25]
>[  581.517577] [drm:drm_atomic_check_only] checking ffff880201186600
>[  581.517579] [drm:update_connector_routing] Updating routing for [CONNECTOR:31:VGA-1]
>[  581.517580] [drm:update_connector_routing] [CONNECTOR:31:VGA-1] keeps [ENCODER:32:DAC-32], now on [CRTC:21]
>[  581.517583] [drm:intel_plane_atomic_calc_changes] [CRTC:21] has [PLANE:18] with fb 50
>[  581.517584] [drm:intel_plane_atomic_calc_changes] [PLANE:18] visible 1 -> 1, off 0, on 0, ms 0
>[  581.517587] [drm:drm_atomic_commit] commiting ffff880201186600
>[  581.517598] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880201186600
>[  581.517600] [drm:drm_atomic_state_free] Freeing atomic state ffff880201186600
>[  582.840800] [drm:intel_print_rc6_info] Enabling RC6 states: RC6 on
>[  582.842721] [drm:gen6_enable_rps] Overclocking supported. Max: 1100MHz, Overclock max: 1100MHz

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Attachments on bug 87579: 116345 | 120390 | 120391 | 122144

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