Attachment 120421 Details for Bug 93264 – llvm-c0a189c.mesa-caf12bebd.run008.check_vm-dump

llvm-c0a189c.mesa-caf12bebd.run008.check_vm-dump

llvm-c0a189c.mesa-caf12bebd.run008.check_vm-dump (text/plain), 81.58 KB, created by Nicolai Hähnle on 2015-12-08 22:13:11 UTC

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Description:

Filename:

MIME Type:

Creator: Nicolai Hähnle

Created: 2015-12-08 22:13:11 UTC

Size: 81.58 KB

patch

obsolete

>VM fault report.
>
>Driver vendor: X.Org
>Device vendor: AMD
>Device name: AMD TONGA (DRM 3.1.0, LLVM 3.8.0)
>
>Failing VM page: 0x00126ac2
>
>Buffer list (in units of pages = 4kB):
>[1;33m        Size    VM start page         VM end page           Usage[0m
>          16    0x00000001003e8       0x00000001003f8       BORDER_COLORS
>       12812    -- hole --
>         256    0x0000000103604       0x0000000103704       CONST_BUFFER, DESCRIPTORS
>       18507    -- hole --
>           6    0x0000000107f4f       0x0000000107f55       VERTEX_BUFFER
>           5    0x0000000107f55       0x0000000107f5a       VERTEX_BUFFER
>       19704    -- hole --
>           1    0x000000010cc52       0x000000010cc53       CONST_BUFFER
>        4051    -- hole --
>           1    0x000000010dc26       0x000000010dc27       CONST_BUFFER
>        6681    -- hole --
>        4096    0x000000010f640       0x0000000110640       SAMPLER_TEXTURE
>        2048    0x0000000110640       0x0000000110e40       SAMPLER_TEXTURE
>        3654    -- hole --
>           2    0x0000000111c86       0x0000000111c88       SAMPLER_TEXTURE
>         628    -- hole --
>          16    0x0000000111efc       0x0000000111f0c       INDEX_BUFFER
>          36    0x0000000111f0c       0x0000000111f30       VERTEX_BUFFER
>          27    0x0000000111f30       0x0000000111f4b       VERTEX_BUFFER
>        4361    -- hole --
>         256    0x0000000113054       0x0000000113154       CONST_BUFFER, DESCRIPTORS
>        2129    -- hole --
>           1    0x00000001139a5       0x00000001139a6       CONST_BUFFER
>         245    -- hole --
>           1    0x0000000113a9b       0x0000000113a9c       USER_SHADER
>         268    -- hole --
>           1    0x0000000113ba8       0x0000000113ba9       SAMPLER_BUFFER
>        1391    -- hole --
>           7    0x0000000114118       0x000000011411f       DCC
>          22    -- hole --
>          32    0x0000000114135       0x0000000114155       HTILE
>           3    -- hole --
>        2240    0x0000000114158       0x0000000114a18       DEPTH_BUFFER
>       14728    -- hole --
>        1792    0x00000001183a0       0x0000000118aa0       COLOR_BUFFER
>           7    0x0000000118aa0       0x0000000118aa7       DCC
>           1    -- hole --
>           7    0x0000000118aa8       0x0000000118aaf       DCC
>           1    -- hole --
>           7    0x0000000118ab0       0x0000000118ab7       DCC
>           1    -- hole --
>           7    0x0000000118ab8       0x0000000118abf       DCC
>           1    -- hole --
>        1792    0x0000000118ac0       0x00000001191c0       COLOR_BUFFER
>        1792    0x00000001191c0       0x00000001198c0       COLOR_BUFFER
>        1792    0x00000001198c0       0x0000000119fc0       COLOR_BUFFER
>        1792    0x0000000119fc0       0x000000011a6c0       COLOR_BUFFER
>          14    0x000000011a6c0       0x000000011a6ce       DCC
>          35    -- hole --
>           1    0x000000011a6f1       0x000000011a6f2       IB2
>          14    -- hole --
>        3584    0x000000011a700       0x000000011b500       COLOR_BUFFER
>       13545    -- hole --
>         960    0x000000011e9e9       0x000000011eda9       RINGS_STREAMOUT
>         387    -- hole --
>         768    0x000000011ef2c       0x000000011f22c       RINGS_STREAMOUT
>        2305    -- hole --
>           1    0x000000011fb2d       0x000000011fb2e       CONST_BUFFER
>       28516    -- hole --
>          12    0x0000000126a92       0x0000000126a9e       SAMPLER_TEXTURE
>       11554    -- hole --
>        1367    0x00000001297c0       0x0000000129d17       SAMPLER_TEXTURE
>        6889    -- hole --
>        1367    0x000000012b800       0x000000012bd57       SAMPLER_TEXTURE
>        4073    -- hole --
>        1367    0x000000012cd40       0x000000012d297       SAMPLER_TEXTURE
>        4137    -- hole --
>        1367    0x000000012e2c0       0x000000012e817       SAMPLER_TEXTURE
>       19113    -- hole --
>        1367    0x00000001332c0       0x0000000133817       SAMPLER_TEXTURE
>        1385    -- hole --
>        1367    0x0000000133d80       0x00000001342d7       SAMPLER_TEXTURE
>        4137    -- hole --
>        1367    0x0000000135300       0x0000000135857       SAMPLER_TEXTURE
>        1385    -- hole --
>        1367    0x0000000135dc0       0x0000000136317       SAMPLER_TEXTURE
>       20585    -- hole --
>        1367    0x000000013b380       0x000000013b8d7       SAMPLER_TEXTURE
>       17833    -- hole --
>        1367    0x000000013fe80       0x00000001403d7       SAMPLER_TEXTURE
>       16489    -- hole --
>         172    0x0000000144440       0x00000001444ec       SAMPLER_TEXTURE
>        9172    -- hole --
>         172    0x00000001468c0       0x000000014696c       SAMPLER_TEXTURE
>      110420    -- hole --
>         343    0x00000001618c0       0x0000000161a17       SAMPLER_TEXTURE
>         425    -- hole --
>         343    0x0000000161bc0       0x0000000161d17       SAMPLER_TEXTURE
>       14812    -- hole --
>          12    0x00000001656f3       0x00000001656ff       SAMPLER_TEXTURE
>        5633    -- hole --
>         172    0x0000000166d00       0x0000000166dac       SAMPLER_TEXTURE
>       14826    -- hole --
>         256    0x000000016a796       0x000000016a896       CONST_BUFFER, DESCRIPTORS
>       12384    -- hole --
>         256    0x000000016d8f6       0x000000016d9f6       DESCRIPTORS
>        3904    -- hole --
>          16    0x000000016e936       0x000000016e946       SAMPLER_BUFFER
>         772    -- hole --
>          23    0x000000016ec4a       0x000000016ec61       SAMPLER_TEXTURE
>         375    -- hole --
>           1    0x000000016edd8       0x000000016edd9       CONST_BUFFER
>         564    -- hole --
>           2    0x000000016f00d       0x000000016f00f       USER_SHADER
>         145    -- hole --
>          43    0x000000016f0a0       0x000000016f0cb       SAMPLER_TEXTURE
>         479    -- hole --
>           1    0x000000016f2aa       0x000000016f2ab       CONST_BUFFER
>        1710    -- hole --
>           2    0x000000016f959       0x000000016f95b       SAMPLER_BUFFER
>        1796    -- hole --
>           1    0x000000017005f       0x0000000170060       CONST_BUFFER
>         281    -- hole --
>           2    0x0000000170179       0x000000017017b       TRACE
>        2588    -- hole --
>        6656    0x0000000170b97       0x0000000172597       SCRATCH_BUFFER
>
>Note: The holes represent memory not used by the IB.
>      Other buffers can still be allocated there.
>
>------------------ IB2: Init config begin ------------------
>[1;32mCONTEXT_CONTROL[0m:
>        0x80000000
>        0x80000000
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_HOS_MAX_TESS_LEVEL[0m <- 64.0f
>        [1;33mVGT_HOS_MIN_TESS_LEVEL[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_PER_ES[0m <- GS_PER_ES = 128
>        [1;33mVGT_ES_PER_GS[0m <- ES_PER_GS = 64
>        [1;33mVGT_GS_PER_VS[0m <- GS_PER_VS = 2
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_RESET[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_STRMOUT_DRAW_OPAQUE_OFFSET[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_STRMOUT_BUFFER_CONFIG[0m <- STREAM_0_BUFFER_EN = 0
>                                     STREAM_1_BUFFER_EN = 0
>                                     STREAM_2_BUFFER_EN = 0
>                                     STREAM_3_BUFFER_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_REUSE_OFF[0m <- REUSE_OFF = 0
>        [1;33mVGT_VTX_CNT_EN[0m <- VTX_CNT_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_CENTROID_PRIORITY_0[0m <- DISTANCE_0 = 0
>                                     DISTANCE_1 = 1
>                                     DISTANCE_2 = 2
>                                     DISTANCE_3 = 3
>                                     DISTANCE_4 = 4
>                                     DISTANCE_5 = 5
>                                     DISTANCE_6 = 6
>                                     DISTANCE_7 = 7
>        [1;33mPA_SC_CENTROID_PRIORITY_1[0m <- DISTANCE_8 = 8
>                                     DISTANCE_9 = 9
>                                     DISTANCE_10 = 10
>                                     DISTANCE_11 = 11
>                                     DISTANCE_12 = 12
>                                     DISTANCE_13 = 13
>                                     DISTANCE_14 = 14
>                                     DISTANCE_15 = 15
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_PRIM_FILTER_CNTL[0m <- TRIANGLE_FILTER_DISABLE = 0
>                                  LINE_FILTER_DISABLE = 0
>                                  POINT_FILTER_DISABLE = 0
>                                  RECTANGLE_FILTER_DISABLE = 0
>                                  TRIANGLE_EXPAND_ENA = 0
>                                  LINE_EXPAND_ENA = 0
>                                  POINT_EXPAND_ENA = 0
>                                  RECTANGLE_EXPAND_ENA = 0
>                                  PRIM_EXPAND_CONSTANT = 0
>                                  XMAX_RIGHT_EXCLUSION = 0
>                                  YMAX_BOTTOM_EXCLUSION = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_VPORT_ZMIN_0[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_0[0m <- 1.0f
>        [1;33mPA_SC_VPORT_ZMIN_1[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_1[0m <- 1.0f
>        [1;33mPA_SC_VPORT_ZMIN_2[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_2[0m <- 1.0f
>        [1;33mPA_SC_VPORT_ZMIN_3[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_3[0m <- 1.0f
>        [1;33mPA_SC_VPORT_ZMIN_4[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_4[0m <- 1.0f
>        [1;33mPA_SC_VPORT_ZMIN_5[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_5[0m <- 1.0f
>        [1;33mPA_SC_VPORT_ZMIN_6[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_6[0m <- 1.0f
>        [1;33mPA_SC_VPORT_ZMIN_7[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_7[0m <- 1.0f
>        [1;33mPA_SC_VPORT_ZMIN_8[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_8[0m <- 1.0f
>        [1;33mPA_SC_VPORT_ZMIN_9[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_9[0m <- 1.0f
>        [1;33mPA_SC_VPORT_ZMIN_10[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_10[0m <- 1.0f
>        [1;33mPA_SC_VPORT_ZMIN_11[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_11[0m <- 1.0f
>        [1;33mPA_SC_VPORT_ZMIN_12[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_12[0m <- 1.0f
>        [1;33mPA_SC_VPORT_ZMIN_13[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_13[0m <- 1.0f
>        [1;33mPA_SC_VPORT_ZMIN_14[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_14[0m <- 1.0f
>        [1;33mPA_SC_VPORT_ZMIN_15[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_15[0m <- 1.0f
>        [1;33mPA_SC_RASTER_CONFIG[0m <- RB_MAP_PKR0 = RASTER_CONFIG_RB_MAP_2
>                               RB_MAP_PKR1 = RASTER_CONFIG_RB_MAP_0
>                               RB_XSEL2 = RASTER_CONFIG_RB_XSEL2_1
>                               RB_XSEL = 0
>                               RB_YSEL = 0
>                               PKR_MAP = RASTER_CONFIG_PKR_MAP_0
>                               PKR_XSEL = RASTER_CONFIG_PKR_XSEL_0
>                               PKR_YSEL = RASTER_CONFIG_PKR_YSEL_0
>                               PKR_XSEL2 = RASTER_CONFIG_PKR_XSEL2_0
>                               SC_MAP = RASTER_CONFIG_SC_MAP_0
>                               SC_XSEL = RASTER_CONFIG_SC_XSEL_8_WIDE_TILE
>                               SC_YSEL = RASTER_CONFIG_SC_YSEL_8_WIDE_TILE
>                               SE_MAP = RASTER_CONFIG_SE_MAP_2
>                               SE_XSEL = RASTER_CONFIG_SE_XSEL_16_WIDE_TILE
>                               SE_YSEL = RASTER_CONFIG_SE_YSEL_16_WIDE_TILE
>        [1;33mPA_SC_RASTER_CONFIG_1[0m <- SE_PAIR_MAP = RASTER_CONFIG_SE_PAIR_MAP_2
>                                 SE_PAIR_XSEL = RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE
>                                 SE_PAIR_YSEL = RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_TL[0m <- TL_X = 0
>                                   TL_Y = 0
>                                   WINDOW_OFFSET_DISABLE = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_GENERIC_SCISSOR_TL[0m <- TL_X = 0
>                                    TL_Y = 0
>                                    WINDOW_OFFSET_DISABLE = 1
>        [1;33mPA_SC_GENERIC_SCISSOR_BR[0m <- BR_X = 16384
>                                    BR_Y = 16384
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_SCREEN_SCISSOR_TL[0m <- TL_X = 0
>                                   TL_Y = 0
>        [1;33mPA_SC_SCREEN_SCISSOR_BR[0m <- BR_X = 16384
>                                   BR_Y = 16384
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_CLIPRECT_RULE[0m <- CLIP_RULE = 0xffff
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_EDGERULE[0m <- ER_TRI = 10
>                          ER_POINT = 10
>                          ER_RECT = 10
>                          ER_LINE_LR = 42
>                          ER_LINE_RL = 42
>                          ER_LINE_TB = 10
>                          ER_LINE_BT = 10
>        [1;33mPA_SU_HARDWARE_SCREEN_OFFSET[0m <- HW_SCREEN_OFFSET_X = 0
>                                        HW_SCREEN_OFFSET_Y = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_NANINF_CNTL[0m <- VTE_XY_INF_DISCARD = 0
>                             VTE_Z_INF_DISCARD = 0
>                             VTE_W_INF_DISCARD = 0
>                             VTE_0XNANINF_IS_0 = 0
>                             VTE_XY_NAN_RETAIN = 0
>                             VTE_Z_NAN_RETAIN = 0
>                             VTE_W_NAN_RETAIN = 0
>                             VTE_W_RECIP_NAN_IS_0 = 0
>                             VS_XY_NAN_TO_INF = 0
>                             VS_XY_INF_RETAIN = 0
>                             VS_Z_NAN_TO_INF = 0
>                             VS_Z_INF_RETAIN = 0
>                             VS_W_NAN_TO_INF = 0
>                             VS_W_INF_RETAIN = 0
>                             VS_CLIP_DIST_INF_DISCARD = 0
>                             VTE_NO_OUTPUT_NEG_0 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_GB_VERT_CLIP_ADJ[0m <- 1.0f
>        [1;33mPA_CL_GB_VERT_DISC_ADJ[0m <- 1.0f
>        [1;33mPA_CL_GB_HORZ_CLIP_ADJ[0m <- 1.0f
>        [1;33mPA_CL_GB_HORZ_DISC_ADJ[0m <- 1.0f
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CLEAR[0m <- CLEAR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SRESULTS_COMPARE_STATE0[0m <- COMPAREFUNC0 = REF_NEVER
>                                      COMPAREVALUE0 = 0
>                                      COMPAREMASK0 = 0
>                                      ENABLE0 = 0
>        [1;33mDB_SRESULTS_COMPARE_STATE1[0m <- COMPAREFUNC1 = REF_NEVER
>                                      COMPAREVALUE1 = 0
>                                      COMPAREMASK1 = 0
>                                      ENABLE1 = 0
>        [1;33mDB_PRELOAD_CONTROL[0m <- START_X = 0
>                              START_Y = 0
>                              MAX_X = 0
>                              MAX_Y = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE[0m <- FORCE_HIZ_ENABLE = FORCE_OFF
>                              FORCE_HIS_ENABLE0 = FORCE_DISABLE
>                              FORCE_HIS_ENABLE1 = FORCE_DISABLE
>                              FORCE_SHADER_Z_ORDER = 0
>                              FAST_Z_DISABLE = 0
>                              FAST_STENCIL_DISABLE = 1
>                              NOOP_CULL_DISABLE = 0
>                              FORCE_COLOR_KILL = 0
>                              FORCE_Z_READ = 0
>                              FORCE_STENCIL_READ = 0
>                              FORCE_FULL_Z_RANGE = FORCE_OFF
>                              FORCE_QC_SMASK_CONFLICT = 0
>                              DISABLE_VIEWPORT_CLAMP = 0
>                              IGNORE_SC_ZRANGE = 0
>                              DISABLE_FULLY_COVERED = 0
>                              FORCE_Z_LIMIT_SUMM = FORCE_SUMM_OFF
>                              MAX_TILES_IN_DTT = 0
>                              DISABLE_TILE_RATE_TILES = 0
>                              FORCE_Z_DIRTY = 0
>                              FORCE_STENCIL_DIRTY = 0
>                              FORCE_Z_VALID = 0
>                              FORCE_STENCIL_VALID = 0
>                              PRESERVE_COMPRESSION = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_MAX_VTX_INDX[0m <- 0xffffffff
>        [1;33mVGT_MIN_VTX_INDX[0m <- 0
>        [1;33mVGT_INDX_OFFSET[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_RSRC3_LS[0m <- CU_EN = 0xfffc
>                                   WAVE_LIMIT = 0
>                                   LOCK_LOW_THRESHOLD = 0
>                                   GROUP_FIFO_DEPTH = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_RSRC3_HS[0m <- WAVE_LIMIT = 0
>                                   LOCK_LOW_THRESHOLD = 0
>                                   GROUP_FIFO_DEPTH = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_RSRC3_ES[0m <- CU_EN = 0xfffe
>                                   WAVE_LIMIT = 0
>                                   LOCK_LOW_THRESHOLD = 0
>                                   GROUP_FIFO_DEPTH = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_RSRC3_GS[0m <- CU_EN = 0xffff
>                                   WAVE_LIMIT = 0
>                                   LOCK_LOW_THRESHOLD = 0
>                                   GROUP_FIFO_DEPTH = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_RSRC3_VS[0m <- CU_EN = 0xffff
>                                   WAVE_LIMIT = 0
>                                   LOCK_LOW_THRESHOLD = 0
>        [1;33mSPI_SHADER_LATE_ALLOC_VS[0m <- LIMIT = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_RSRC3_PS[0m <- CU_EN = 0xffff
>                                   WAVE_LIMIT = 0
>                                   LOCK_LOW_THRESHOLD = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_DCC_CONTROL[0m <- OVERWRITE_COMBINER_DISABLE = 0
>                          OVERWRITE_COMBINER_MRT_SHARING_DISABLE = 1
>                          OVERWRITE_COMBINER_WATERMARK = 4
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_VERTEX_REUSE_BLOCK_CNTL[0m <- VTX_REUSE_DEPTH = 30
>        [1;33mVGT_OUT_DEALLOC_CNTL[0m <- DEALLOC_DIST = 32
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mTA_BC_BASE_ADDR[0m <- 0x01003e80
>        [1;33mTA_BC_BASE_ADDR_HI[0m <- ADDRESS = 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = VGT_FLUSH
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>------------------- IB2: Init config end -------------------
>
>------------------ IB2: Init GS rings begin ------------------
>[1;36mSET_UCONFIG_REG[1;36m:
>        [1;33mVGT_ESGS_RING_SIZE[0m <- 15360
>        [1;33mVGT_GSVS_RING_SIZE[0m <- 12288
>------------------- IB2: Init GS rings end -------------------
>
>------------------ IB begin ------------------
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x70179000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000001
>[1;32mNOP[0m:
>        [31mTrace point ID: 1
>        [31mThis trace point was reached by the CP.[0m
>[1;32mINDIRECT_BUFFER_CIK[0m:
>        0x1a6f1000
>        0x00000001
>        0x00000090
>[1;36mSET_UCONFIG_REG[1;36m:
>        [1;33mVGT_ESGS_RING_SIZE[0m <- 15360
>        [1;33mVGT_GSVS_RING_SIZE[0m <- 12288
>[1;32mEVENT_WRITE_EOP[0m:
>        0x0000052d
>        0x00000000
>        0x00000000
>        0x00000000
>        0x00000000
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 1
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 1
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 1
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_STRMOUT_BUFFER_CONFIG[0m <- STREAM_0_BUFFER_EN = 0
>                                     STREAM_1_BUFFER_EN = 0
>                                     STREAM_2_BUFFER_EN = 0
>                                     STREAM_3_BUFFER_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_STRMOUT_CONFIG[0m <- STREAMOUT_0_EN = 0
>                              STREAMOUT_1_EN = 0
>                              STREAMOUT_2_EN = 0
>                              STREAMOUT_3_EN = 0
>                              RAST_STREAM = 0
>                              RAST_STREAM_MASK = 0
>                              USE_RAST_STREAM_MASK = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_BASE[0m <- 0x011a7000
>        [1;33mCB_COLOR0_PITCH[0m <- TILE_MAX = 223
>                           FMASK_TILE_MAX = 223
>        [1;33mCB_COLOR0_SLICE[0m <- TILE_MAX = 28671
>        [1;33mCB_COLOR0_VIEW[0m <- SLICE_START = 0
>                          SLICE_MAX = 0
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_16_16_16_16
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_FLOAT
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 1
>                          CMASK_ADDR_TYPE = 0
>        [1;33mCB_COLOR0_ATTRIB[0m <- TILE_MODE_INDEX = 14
>                            FMASK_TILE_MODE_INDEX = 14
>                            FMASK_BANK_HEIGHT = 0
>                            NUM_SAMPLES = 0
>                            NUM_FRAGMENTS = 0
>                            FORCE_DST_ALPHA_1 = 0
>        [1;33mCB_COLOR0_DCC_CONTROL[0m <- OVERWRITE_COMBINER_DISABLE = 0
>                                 KEY_CLEAR_ENABLE = 0
>                                 MAX_UNCOMPRESSED_BLOCK_SIZE = 2
>                                 MIN_COMPRESSED_BLOCK_SIZE = 0
>                                 MAX_COMPRESSED_BLOCK_SIZE = 0
>                                 COLOR_TRANSFORM = 0
>                                 INDEPENDENT_64B_BLOCKS = 1
>                                 LOSSY_RGB_PRECISION = 0
>                                 LOSSY_ALPHA_PRECISION = 0
>        [1;33mCB_COLOR0_CMASK[0m <- 0x011a7000
>        [1;33mCB_COLOR0_CMASK_SLICE[0m <- TILE_MAX = 0
>        [1;33mCB_COLOR0_FMASK[0m <- 0x011a7000
>        [1;33mCB_COLOR0_FMASK_SLICE[0m <- TILE_MAX = 28671
>        [1;33mCB_COLOR0_CLEAR_WORD0[0m <- 0
>        [1;33mCB_COLOR0_CLEAR_WORD1[0m <- 0x3c000000
>        [1;33mCB_COLOR0_DCC_BASE[0m <- 0x011a6c00
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR1_BASE[0m <- 0x01183a00
>        [1;33mCB_COLOR1_PITCH[0m <- TILE_MAX = 223
>                           FMASK_TILE_MAX = 223
>        [1;33mCB_COLOR1_SLICE[0m <- TILE_MAX = 28671
>        [1;33mCB_COLOR1_VIEW[0m <- SLICE_START = 0
>                          SLICE_MAX = 0
>        [1;33mCB_COLOR1_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_2_10_10_10
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_ALT
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 1
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 1
>                          CMASK_ADDR_TYPE = 0
>        [1;33mCB_COLOR1_ATTRIB[0m <- TILE_MODE_INDEX = 14
>                            FMASK_TILE_MODE_INDEX = 14
>                            FMASK_BANK_HEIGHT = 0
>                            NUM_SAMPLES = 0
>                            NUM_FRAGMENTS = 0
>                            FORCE_DST_ALPHA_1 = 0
>        [1;33mCB_COLOR1_DCC_CONTROL[0m <- OVERWRITE_COMBINER_DISABLE = 0
>                                 KEY_CLEAR_ENABLE = 0
>                                 MAX_UNCOMPRESSED_BLOCK_SIZE = 2
>                                 MIN_COMPRESSED_BLOCK_SIZE = 0
>                                 MAX_COMPRESSED_BLOCK_SIZE = 0
>                                 COLOR_TRANSFORM = 0
>                                 INDEPENDENT_64B_BLOCKS = 1
>                                 LOSSY_RGB_PRECISION = 0
>                                 LOSSY_ALPHA_PRECISION = 0
>        [1;33mCB_COLOR1_CMASK[0m <- 0x01183a00
>        [1;33mCB_COLOR1_CMASK_SLICE[0m <- TILE_MAX = 0
>        [1;33mCB_COLOR1_FMASK[0m <- 0x01183a00
>        [1;33mCB_COLOR1_FMASK_SLICE[0m <- TILE_MAX = 28671
>        [1;33mCB_COLOR1_CLEAR_WORD0[0m <- 0
>        [1;33mCB_COLOR1_CLEAR_WORD1[0m <- 0
>        [1;33mCB_COLOR1_DCC_BASE[0m <- 0x01141180
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR2_BASE[0m <- 0x0118ac00
>        [1;33mCB_COLOR2_PITCH[0m <- TILE_MAX = 223
>                           FMASK_TILE_MAX = 223
>        [1;33mCB_COLOR2_SLICE[0m <- TILE_MAX = 28671
>        [1;33mCB_COLOR2_VIEW[0m <- SLICE_START = 0
>                          SLICE_MAX = 0
>        [1;33mCB_COLOR2_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_8_8_8_8
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_ALT
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 1
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 1
>                          CMASK_ADDR_TYPE = 0
>        [1;33mCB_COLOR2_ATTRIB[0m <- TILE_MODE_INDEX = 14
>                            FMASK_TILE_MODE_INDEX = 14
>                            FMASK_BANK_HEIGHT = 0
>                            NUM_SAMPLES = 0
>                            NUM_FRAGMENTS = 0
>                            FORCE_DST_ALPHA_1 = 0
>        [1;33mCB_COLOR2_DCC_CONTROL[0m <- OVERWRITE_COMBINER_DISABLE = 0
>                                 KEY_CLEAR_ENABLE = 0
>                                 MAX_UNCOMPRESSED_BLOCK_SIZE = 2
>                                 MIN_COMPRESSED_BLOCK_SIZE = 0
>                                 MAX_COMPRESSED_BLOCK_SIZE = 0
>                                 COLOR_TRANSFORM = 0
>                                 INDEPENDENT_64B_BLOCKS = 1
>                                 LOSSY_RGB_PRECISION = 0
>                                 LOSSY_ALPHA_PRECISION = 0
>        [1;33mCB_COLOR2_CMASK[0m <- 0x0118ac00
>        [1;33mCB_COLOR2_CMASK_SLICE[0m <- TILE_MAX = 0
>        [1;33mCB_COLOR2_FMASK[0m <- 0x0118ac00
>        [1;33mCB_COLOR2_FMASK_SLICE[0m <- TILE_MAX = 28671
>        [1;33mCB_COLOR2_CLEAR_WORD0[0m <- 0
>        [1;33mCB_COLOR2_CLEAR_WORD1[0m <- 0
>        [1;33mCB_COLOR2_DCC_BASE[0m <- 0x0118aa00
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR3_BASE[0m <- 0x01191c00
>        [1;33mCB_COLOR3_PITCH[0m <- TILE_MAX = 223
>                           FMASK_TILE_MAX = 223
>        [1;33mCB_COLOR3_SLICE[0m <- TILE_MAX = 28671
>        [1;33mCB_COLOR3_VIEW[0m <- SLICE_START = 0
>                          SLICE_MAX = 0
>        [1;33mCB_COLOR3_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_8_8_8_8
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_SRGB
>                          COMP_SWAP = SWAP_ALT
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 1
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 1
>                          CMASK_ADDR_TYPE = 0
>        [1;33mCB_COLOR3_ATTRIB[0m <- TILE_MODE_INDEX = 14
>                            FMASK_TILE_MODE_INDEX = 14
>                            FMASK_BANK_HEIGHT = 0
>                            NUM_SAMPLES = 0
>                            NUM_FRAGMENTS = 0
>                            FORCE_DST_ALPHA_1 = 0
>        [1;33mCB_COLOR3_DCC_CONTROL[0m <- OVERWRITE_COMBINER_DISABLE = 0
>                                 KEY_CLEAR_ENABLE = 0
>                                 MAX_UNCOMPRESSED_BLOCK_SIZE = 2
>                                 MIN_COMPRESSED_BLOCK_SIZE = 0
>                                 MAX_COMPRESSED_BLOCK_SIZE = 0
>                                 COLOR_TRANSFORM = 0
>                                 INDEPENDENT_64B_BLOCKS = 1
>                                 LOSSY_RGB_PRECISION = 0
>                                 LOSSY_ALPHA_PRECISION = 0
>        [1;33mCB_COLOR3_CMASK[0m <- 0x01191c00
>        [1;33mCB_COLOR3_CMASK_SLICE[0m <- TILE_MAX = 0
>        [1;33mCB_COLOR3_FMASK[0m <- 0x01191c00
>        [1;33mCB_COLOR3_FMASK_SLICE[0m <- TILE_MAX = 28671
>        [1;33mCB_COLOR3_CLEAR_WORD0[0m <- 0
>        [1;33mCB_COLOR3_CLEAR_WORD1[0m <- 0
>        [1;33mCB_COLOR3_DCC_BASE[0m <- 0x0118aa80
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR4_BASE[0m <- 0x01198c00
>        [1;33mCB_COLOR4_PITCH[0m <- TILE_MAX = 223
>                           FMASK_TILE_MAX = 223
>        [1;33mCB_COLOR4_SLICE[0m <- TILE_MAX = 28671
>        [1;33mCB_COLOR4_VIEW[0m <- SLICE_START = 0
>                          SLICE_MAX = 0
>        [1;33mCB_COLOR4_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_8_8_8_8
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_ALT
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 1
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 1
>                          CMASK_ADDR_TYPE = 0
>        [1;33mCB_COLOR4_ATTRIB[0m <- TILE_MODE_INDEX = 14
>                            FMASK_TILE_MODE_INDEX = 14
>                            FMASK_BANK_HEIGHT = 0
>                            NUM_SAMPLES = 0
>                            NUM_FRAGMENTS = 0
>                            FORCE_DST_ALPHA_1 = 0
>        [1;33mCB_COLOR4_DCC_CONTROL[0m <- OVERWRITE_COMBINER_DISABLE = 0
>                                 KEY_CLEAR_ENABLE = 0
>                                 MAX_UNCOMPRESSED_BLOCK_SIZE = 2
>                                 MIN_COMPRESSED_BLOCK_SIZE = 0
>                                 MAX_COMPRESSED_BLOCK_SIZE = 0
>                                 COLOR_TRANSFORM = 0
>                                 INDEPENDENT_64B_BLOCKS = 1
>                                 LOSSY_RGB_PRECISION = 0
>                                 LOSSY_ALPHA_PRECISION = 0
>        [1;33mCB_COLOR4_CMASK[0m <- 0x01198c00
>        [1;33mCB_COLOR4_CMASK_SLICE[0m <- TILE_MAX = 0
>        [1;33mCB_COLOR4_FMASK[0m <- 0x01198c00
>        [1;33mCB_COLOR4_FMASK_SLICE[0m <- TILE_MAX = 28671
>        [1;33mCB_COLOR4_CLEAR_WORD0[0m <- 0xff00ffff
>        [1;33mCB_COLOR4_CLEAR_WORD1[0m <- 0
>        [1;33mCB_COLOR4_DCC_BASE[0m <- 0x0118ab00
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR5_BASE[0m <- 0x0119fc00
>        [1;33mCB_COLOR5_PITCH[0m <- TILE_MAX = 223
>                           FMASK_TILE_MAX = 223
>        [1;33mCB_COLOR5_SLICE[0m <- TILE_MAX = 28671
>        [1;33mCB_COLOR5_VIEW[0m <- SLICE_START = 0
>                          SLICE_MAX = 0
>        [1;33mCB_COLOR5_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_8_8_8_8
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_ALT
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 1
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 1
>                          CMASK_ADDR_TYPE = 0
>        [1;33mCB_COLOR5_ATTRIB[0m <- TILE_MODE_INDEX = 14
>                            FMASK_TILE_MODE_INDEX = 14
>                            FMASK_BANK_HEIGHT = 0
>                            NUM_SAMPLES = 0
>                            NUM_FRAGMENTS = 0
>                            FORCE_DST_ALPHA_1 = 0
>        [1;33mCB_COLOR5_DCC_CONTROL[0m <- OVERWRITE_COMBINER_DISABLE = 0
>                                 KEY_CLEAR_ENABLE = 0
>                                 MAX_UNCOMPRESSED_BLOCK_SIZE = 2
>                                 MIN_COMPRESSED_BLOCK_SIZE = 0
>                                 MAX_COMPRESSED_BLOCK_SIZE = 0
>                                 COLOR_TRANSFORM = 0
>                                 INDEPENDENT_64B_BLOCKS = 1
>                                 LOSSY_RGB_PRECISION = 0
>                                 LOSSY_ALPHA_PRECISION = 0
>        [1;33mCB_COLOR5_CMASK[0m <- 0x0119fc00
>        [1;33mCB_COLOR5_CMASK_SLICE[0m <- TILE_MAX = 0
>        [1;33mCB_COLOR5_FMASK[0m <- 0x0119fc00
>        [1;33mCB_COLOR5_FMASK_SLICE[0m <- TILE_MAX = 28671
>        [1;33mCB_COLOR5_CLEAR_WORD0[0m <- 0xffffffff
>        [1;33mCB_COLOR5_CLEAR_WORD1[0m <- 0
>        [1;33mCB_COLOR5_DCC_BASE[0m <- 0x0118ab80
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR6_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_INVALID
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR7_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_INVALID
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_VIEW[0m <- SLICE_START = 0
>                         SLICE_MAX = 0
>                         Z_READ_ONLY = 0
>                         STENCIL_READ_ONLY = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_DATA_BASE[0m <- 0x01141350
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_INFO[0m <- ADDR5_SWIZZLE_MASK = 1
>                         ARRAY_MODE = ARRAY_2D_TILED_THIN1
>                         PIPE_CONFIG = X_ADDR_SURF_P8_32X32_16X16
>                         BANK_WIDTH = ADDR_SURF_BANK_WIDTH_1
>                         BANK_HEIGHT = ADDR_SURF_BANK_HEIGHT_4
>                         MACRO_TILE_ASPECT = ADDR_SURF_MACRO_ASPECT_4
>                         NUM_BANKS = ADDR_SURF_16_BANK
>        [1;33mDB_Z_INFO[0m <- FORMAT = Z_24
>                     NUM_SAMPLES = 0
>                     TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                     TILE_MODE_INDEX = 0
>                     DECOMPRESS_ON_N_ZPLANES = 0
>                     ALLOW_EXPCLEAR = 1
>                     READ_SIZE = 0
>                     TILE_SURFACE_ENABLE = 1
>                     CLEAR_DISALLOWED = 0
>                     ZRANGE_PRECISION = 0
>        [1;33mDB_STENCIL_INFO[0m <- FORMAT = STENCIL_8
>                           TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                           TILE_MODE_INDEX = 0
>                           ALLOW_EXPCLEAR = 0
>                           TILE_STENCIL_DISABLE = 1
>                           CLEAR_DISALLOWED = 0
>        [1;33mDB_Z_READ_BASE[0m <- 0x01141580
>        [1;33mDB_STENCIL_READ_BASE[0m <- 0x01148580
>        [1;33mDB_Z_WRITE_BASE[0m <- 0x01141580
>        [1;33mDB_STENCIL_WRITE_BASE[0m <- 0x01148580
>        [1;33mDB_DEPTH_SIZE[0m <- PITCH_TILE_MAX = 223
>                         HEIGHT_TILE_MAX = 127
>        [1;33mDB_DEPTH_SLICE[0m <- SLICE_TILE_MAX = 28671
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_HTILE_SURFACE[0m <- LINEAR = 0
>                            FULL_CACHE = 1
>                            HTILE_USES_PRELOAD_WIN = 0
>                            PRELOAD = 0
>                            PREFETCH_WIDTH = 0
>                            PREFETCH_HEIGHT = 0
>                            DST_OUTSIDE_ZERO_TO_ONE = 0
>                            TC_COMPATIBLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CLEAR[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_DB_FMT_CNTL[0m <- POLY_OFFSET_NEG_NUM_DB_BITS = 232
>                                         POLY_OFFSET_DB_IS_FLOAT_FMT = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 1600
>                                   BR_Y = 904
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0[0m <- S0_X = 14
>                                             S0_Y = 11
>                                             S1_X = 3
>                                             S1_Y = 12
>                                             S2_X = 15
>                                             S2_Y = 5
>                                             S3_X = 10
>                                             S3_Y = 14
>        [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1[0m <- S4_X = 6
>                                             S4_Y = 0
>                                             S5_X = 0
>                                             S5_Y = 0
>                                             S6_X = 11
>                                             S6_Y = 3
>                                             S7_X = 4
>                                             S7_Y = 4
>        [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2[0m <- S8_X = 0
>                                             S8_Y = 0
>                                             S9_X = 0
>                                             S9_Y = 0
>                                             S10_X = 0
>                                             S10_Y = 0
>                                             S11_X = 0
>                                             S11_Y = 0
>        [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3[0m <- S12_X = 0
>                                             S12_Y = 0
>                                             S13_X = 0
>                                             S13_Y = 0
>                                             S14_X = 0
>                                             S14_Y = 0
>                                             S15_X = 0
>                                             S15_Y = 0
>        [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0[0m <- S0_X = 14
>                                             S0_Y = 11
>                                             S1_X = 3
>                                             S1_Y = 12
>                                             S2_X = 15
>                                             S2_Y = 5
>                                             S3_X = 10
>                                             S3_Y = 14
>        [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1[0m <- S4_X = 6
>                                             S4_Y = 0
>                                             S5_X = 0
>                                             S5_Y = 0
>                                             S6_X = 11
>                                             S6_Y = 3
>                                             S7_X = 4
>                                             S7_Y = 4
>        [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2[0m <- S8_X = 0
>                                             S8_Y = 0
>                                             S9_X = 0
>                                             S9_Y = 0
>                                             S10_X = 0
>                                             S10_Y = 0
>                                             S11_X = 0
>                                             S11_Y = 0
>        [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3[0m <- S12_X = 0
>                                             S12_Y = 0
>                                             S13_X = 0
>                                             S13_Y = 0
>                                             S14_X = 0
>                                             S14_Y = 0
>                                             S15_X = 0
>                                             S15_Y = 0
>        [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0[0m <- S0_X = 14
>                                             S0_Y = 11
>                                             S1_X = 3
>                                             S1_Y = 12
>                                             S2_X = 15
>                                             S2_Y = 5
>                                             S3_X = 10
>                                             S3_Y = 14
>        [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1[0m <- S4_X = 6
>                                             S4_Y = 0
>                                             S5_X = 0
>                                             S5_Y = 0
>                                             S6_X = 11
>                                             S6_Y = 3
>                                             S7_X = 4
>                                             S7_Y = 4
>        [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2[0m <- S8_X = 0
>                                             S8_Y = 0
>                                             S9_X = 0
>                                             S9_Y = 0
>                                             S10_X = 0
>                                             S10_Y = 0
>                                             S11_X = 0
>                                             S11_Y = 0
>        [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3[0m <- S12_X = 0
>                                             S12_Y = 0
>                                             S13_X = 0
>                                             S13_Y = 0
>                                             S14_X = 0
>                                             S14_Y = 0
>                                             S15_X = 0
>                                             S15_Y = 0
>        [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0[0m <- S0_X = 14
>                                             S0_Y = 11
>                                             S1_X = 3
>                                             S1_Y = 12
>                                             S2_X = 15
>                                             S2_Y = 5
>                                             S3_X = 10
>                                             S3_Y = 14
>        [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1[0m <- S4_X = 6
>                                             S4_Y = 0
>                                             S5_X = 0
>                                             S5_Y = 0
>                                             S6_X = 11
>                                             S6_Y = 3
>                                             S7_X = 4
>                                             S7_Y = 4
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 0
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 1
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_LINE_CNTL[0m <- EXPAND_LINE_WIDTH = 0
>                           LAST_PIXEL = 1
>                           PERPENDICULAR_ENDCAP_ENA = 0
>                           DX10_DIAMOND_TEST_ENA = 0
>        [1;33mPA_SC_AA_CONFIG[0m <- MSAA_NUM_SAMPLES = 0
>                           AA_MASK_CENTROID_DTMN = 0
>                           MAX_SAMPLE_DIST = 0
>                           MSAA_EXPOSED_SAMPLES = 0
>                           DETAIL_TO_EXPOSED_MODE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_EQAA[0m <- MAX_ANCHOR_SAMPLES = 0
>                   PS_ITER_SAMPLES = 0
>                   MASK_EXPORT_NUM_SAMPLES = 0
>                   ALPHA_TO_MASK_NUM_SAMPLES = 0
>                   HIGH_QUALITY_INTERSECTIONS = 1
>                   INCOHERENT_EQAA_READS = 0
>                   INTERPOLATE_COMP_Z = 0
>                   INTERPOLATE_SRC_Z = 0
>                   STATIC_ANCHOR_ASSOCIATIONS = 1
>                   ALPHA_TO_MASK_EQAA_DISABLE = 0
>                   OVERRASTERIZATION_AMOUNT = 0
>                   ENABLE_POSTZ_OVERRASTERIZATION = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_1[0m <- WALK_SIZE = 0
>                             WALK_ALIGNMENT = 0
>                             WALK_ALIGN8_PRIM_FITS_ST = 0
>                             WALK_FENCE_ENABLE = 0
>                             WALK_FENCE_SIZE = 0
>                             SUPERTILE_WALK_ORDER_ENABLE = 0
>                             TILE_WALK_ORDER_ENABLE = 0
>                             TILE_COVER_DISABLE = 0
>                             TILE_COVER_NO_SCISSOR = 0
>                             ZMM_LINE_EXTENT = 0
>                             ZMM_LINE_OFFSET = 0
>                             ZMM_RECT_EXTENT = 0
>                             KILL_PIX_POST_HI_Z = 0
>                             KILL_PIX_POST_DETAIL_MASK = 0
>                             PS_ITER_SAMPLE = 0
>                             MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE = 0
>                             MULTI_GPU_SUPERTILE_ENABLE = 0
>                             GPU_ID_OVERRIDE_ENABLE = 0
>                             GPU_ID_OVERRIDE = 0
>                             MULTI_GPU_PRIM_DISCARD_ENABLE = 0
>                             FORCE_EOV_CNTDWN_ENABLE = 0
>                             FORCE_EOV_REZ_ENABLE = 0
>                             OUT_OF_ORDER_PRIMITIVE_ENABLE = 0
>                             OUT_OF_ORDER_WATER_MARK = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_AA_MASK_X0Y0_X1Y0[0m <- AA_MASK_X0Y0 = 0xffff
>                                   AA_MASK_X1Y0 = 0xffff
>        [1;33mPA_SC_AA_MASK_X0Y1_X1Y1[0m <- AA_MASK_X0Y1 = 0xffff
>                                   AA_MASK_X1Y1 = 0xffff
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15
>                          TARGET1_ENABLE = 15
>                          TARGET2_ENABLE = 15
>                          TARGET3_ENABLE = 15
>                          TARGET4_ENABLE = 15
>                          TARGET5_ENABLE = 15
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND_RED[0m <- 0
>        [1;33mCB_BLEND_GREEN[0m <- 0
>        [1;33mCB_BLEND_BLUE[0m <- 0
>        [1;33mCB_BLEND_ALPHA[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_UCP_0_X[0m <- 0
>        [1;33mPA_CL_UCP_0_Y[0m <- 0
>        [1;33mPA_CL_UCP_0_Z[0m <- 0
>        [1;33mPA_CL_UCP_0_W[0m <- 0
>        [1;33mPA_CL_UCP_1_X[0m <- 0
>        [1;33mPA_CL_UCP_1_Y[0m <- 0
>        [1;33mPA_CL_UCP_1_Z[0m <- 0
>        [1;33mPA_CL_UCP_1_W[0m <- 0
>        [1;33mPA_CL_UCP_2_X[0m <- 0
>        [1;33mPA_CL_UCP_2_Y[0m <- 0
>        [1;33mPA_CL_UCP_2_Z[0m <- 0
>        [1;33mPA_CL_UCP_2_W[0m <- 0
>        [1;33mPA_CL_UCP_3_X[0m <- 0
>        [1;33mPA_CL_UCP_3_Y[0m <- 0
>        [1;33mPA_CL_UCP_3_Z[0m <- 0
>        [1;33mPA_CL_UCP_3_W[0m <- 0
>        [1;33mPA_CL_UCP_4_X[0m <- 0
>        [1;33mPA_CL_UCP_4_Y[0m <- 0
>        [1;33mPA_CL_UCP_4_Z[0m <- 0
>        [1;33mPA_CL_UCP_4_W[0m <- 0
>        [1;33mPA_CL_UCP_5_X[0m <- 0
>        [1;33mPA_CL_UCP_5_Y[0m <- 0
>        [1;33mPA_CL_UCP_5_Z[0m <- 0
>        [1;33mPA_CL_UCP_5_W[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_0[0m <- 0x6a865e00
>        [1;33mSPI_SHADER_USER_DATA_VS_1[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x6a88c800
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_6[0m <- 0x6a860700
>        [1;33mSPI_SHADER_USER_DATA_VS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_4[0m <- 0x6a860c00
>        [1;33mSPI_SHADER_USER_DATA_VS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_0[0m <- 0x03604d00
>        [1;33mSPI_SHADER_USER_DATA_PS_1[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x6a88ca00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x6a88cc00
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x6a88d100
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_GS_0[0m <- 0x6d8fd300
>        [1;33mSPI_SHADER_USER_DATA_GS_1[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_GS_2[0m <- 0x6a88d300
>        [1;33mSPI_SHADER_USER_DATA_GS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_GS_6[0m <- 0x03605800
>        [1;33mSPI_SHADER_USER_DATA_GS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_GS_4[0m <- 0x03605d00
>        [1;33mSPI_SHADER_USER_DATA_GS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_HS_0[0m <- 0x03606100
>        [1;33mSPI_SHADER_USER_DATA_HS_1[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_HS_2[0m <- 0x13125000
>        [1;33mSPI_SHADER_USER_DATA_HS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_HS_6[0m <- 0x03606200
>        [1;33mSPI_SHADER_USER_DATA_HS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_HS_4[0m <- 0x03606700
>        [1;33mSPI_SHADER_USER_DATA_HS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x6a88d500
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_VPORT_SCISSOR_0_TL[0m <- TL_X = 0
>                                    TL_Y = 0
>                                    WINDOW_OFFSET_DISABLE = 1
>        [1;33mPA_SC_VPORT_SCISSOR_0_BR[0m <- BR_X = 1600
>                                    BR_Y = 904
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 800.0f
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 800.0f
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 450.0f
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 450.0f
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 0.5f
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0.5f
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCILREFMASK[0m <- STENCILTESTVAL = 0
>                             STENCILMASK = 0
>                             STENCILWRITEMASK = 0
>                             STENCILOPVAL = 1
>        [1;33mDB_STENCILREFMASK_BF[0m <- STENCILTESTVAL_BF = 0
>                                STENCILMASK_BF = 0
>                                STENCILWRITEMASK_BF = 0
>                                STENCILOPVAL_BF = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_2[0m <- OFFSET = 2
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_3[0m <- OFFSET = 3
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 1
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 0
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 0
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 0
>                             LINEAR_CENTER_ENA = 0
>                             LINEAR_CENTROID_ENA = 0
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 1
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 0
>                             POS_FIXED_PT_ENA = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DEGAMMA_ENABLE = 0
>                            MODE = CB_NORMAL
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 8
>                            WIDTH = 8
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 8
>                              MAX_SIZE = 8
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 8
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 0
>                              CULL_BACK = 0
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 0
>                              POLY_OFFSET_BACK_ENABLE = 0
>                              POLY_OFFSET_PARA_ENABLE = 0
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_12[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 0
>                            Z_ENABLE = 1
>                            Z_WRITE_ENABLE = 1
>                            DEPTH_BOUNDS_ENABLE = 0
>                            ZFUNC = FRAG_GEQUAL
>                            BACKFACE_ENABLE = 0
>                            STENCILFUNC = REF_NEVER
>                            STENCILFUNC_BF = REF_NEVER
>                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CONTROL[0m <- STENCILFAIL = STENCIL_KEEP
>                              STENCILZPASS = STENCIL_KEEP
>                              STENCILZFAIL = STENCIL_KEEP
>                              STENCILFAIL_BF = STENCIL_KEEP
>                              STENCILZPASS_BF = STENCIL_KEEP
>                              STENCILZFAIL_BF = STENCIL_KEEP
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_SHADER_STAGES_EN[0m <- LS_EN = LS_STAGE_OFF
>                                HS_EN = 0
>                                ES_EN = ES_STAGE_OFF
>                                GS_EN = 0
>                                VS_EN = VS_STAGE_REAL
>                                DYNAMIC_HS = 0
>                                DISPATCH_DRAW_EN = 0
>                                DIS_DEALLOC_ACCUM_0 = 0
>                                DIS_DEALLOC_ACCUM_1 = 0
>                                VS_WAVE_ID_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       CUT_MODE = GS_CUT_1024
>                       GS_C_PACK_EN = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 3
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x0113a9b0
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 6
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 0
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 13
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = X_CALCULATE_PER_PIXEL_FLOATING_POINT_POSITION_AT
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 4
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15
>                          OUTPUT1_ENABLE = 15
>                          OUTPUT2_ENABLE = 15
>                          OUTPUT3_ENABLE = 15
>                          OUTPUT4_ENABLE = 15
>                          OUTPUT5_ENABLE = 15
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x016f00d0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 15
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 0
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 1
>                                   USER_SGPR = 10
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_TMPRING_SIZE[0m <- WAVES = 1024
>                            WAVESIZE = 9
>[1;32mDRAW_PREAMBLE[0m:
>        [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_TRILIST
>        [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 127
>                              PARTIAL_VS_WAVE_ON = 0
>                              SWITCH_ON_EOP = 0
>                              PARTIAL_ES_WAVE_ON = 1
>                              SWITCH_ON_EOI = 1
>                              WD_SWITCH_ON_EOP = 0
>                              MAX_PRIMGRP_IN_WAVE = 2
>        [1;33mVGT_LS_HS_CONFIG[0m <- NUM_PATCHES = 0
>                            HS_NUM_INPUT_CP = 0
>                            HS_NUM_OUTPUT_CP = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_OUT_PRIM_TYPE[0m <- OUTPRIM_TYPE = OUTPRIM_TYPE_TRISTRIP
>                                OUTPRIM_TYPE_1 = 0
>                                OUTPRIM_TYPE_2 = 0
>                                OUTPRIM_TYPE_3 = 0
>                                UNIQUE_TYPE_PER_STREAM = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_MULTI_PRIM_IB_RESET_EN[0m <- RESET_EN = 0
>[1;32mINDEX_TYPE[0m:
>        [1;33mVGT_DMA_INDEX_TYPE[0m <- INDEX_TYPE = VGT_INDEX_16
>                              SWAP_MODE = VGT_DMA_SWAP_NONE
>                              BUF_TYPE = VGT_DMA_BUF_MEM
>                              RDREQ_POLICY = VGT_POLICY_LRU
>                              ATC = 0
>                              NOT_EOP = 0
>                              REQ_PATH = 0
>                              MTYPE = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_10[0m <- 0
>        [1;33mSPI_SHADER_USER_DATA_VS_11[0m <- 0
>[1;32mDRAW_INDEX_2[0m:
>        [1;33mVGT_DMA_MAX_SIZE[0m <- 31536
>        [1;33mVGT_DMA_BASE[0m <- 0x11efc000
>        [1;33mVGT_DMA_BASE_HI[0m <- BASE_ADDR = 1
>        [1;33mVGT_NUM_INDICES[0m <- 31536
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_DMA
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x70179000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000002
>[1;32mNOP[0m:
>        [31mTrace point ID: 2
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE_EOP[0m:
>        0x0000052d
>        0x00000000
>        0x00000000
>        0x00000000
>        0x00000000
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = PS_PARTIAL_FLUSH
>        [1;33mEVENT_INDEX[0m <- 4
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 1
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x70179000
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000003
>[1;32mNOP[0m:
>        [31mTrace point ID: 3
>        [31m!!!!! This is the last trace point that was reached by the CP !!!!![0m
>------------------- IB end -------------------
>

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Attachments on bug 93264: 120421 | 120422 | 120423 | 120424 | 120425 | 120426

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