Attachment 121533 Details for Bug 92936 – possible fix

[patch] possible fix

0001-drm-amd-powerplay-tonga-disable-uvd-pg.patch (text/plain), 3.08 KB, created by Alex Deucher on 2016-02-05 04:13:12 UTC

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Creator: Alex Deucher

Created: 2016-02-05 04:13:12 UTC

Size: 3.08 KB

patch

obsolete

>From a588aac71ac73c7813173dabcddd1e12edfb604e Mon Sep 17 00:00:00 2001
>From: Alex Deucher <alexander.deucher@amd.com>
>Date: Thu, 4 Feb 2016 23:11:55 -0500
>Subject: [PATCH] drm/amd/powerplay/tonga: disable uvd pg
>
>Not working reliably yet.
>
>bug:
>https://bugs.freedesktop.org/show_bug.cgi?id=92936
>
>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
>---
> .../amd/powerplay/hwmgr/tonga_clockpowergating.c   | 34 ++++++++++++----------
> drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c  |  2 ++
> drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.h  |  2 ++
> 3 files changed, 23 insertions(+), 15 deletions(-)
>
>diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_clockpowergating.c
>index e58d038..2868033 100644
>--- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_clockpowergating.c
>+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_clockpowergating.c
>@@ -111,23 +111,27 @@ int tonga_phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
> 	data->uvd_power_gated = bgate;
> 
> 	if (bgate) {
>-		cgs_set_clockgating_state(hwmgr->device,
>-						AMD_IP_BLOCK_TYPE_UVD,
>-						AMD_CG_STATE_UNGATE);
>-		cgs_set_powergating_state(hwmgr->device,
>-						AMD_IP_BLOCK_TYPE_UVD,
>-						AMD_PG_STATE_GATE);
>+		if (data->uvd_pg) {
>+			cgs_set_clockgating_state(hwmgr->device,
>+						  AMD_IP_BLOCK_TYPE_UVD,
>+						  AMD_CG_STATE_UNGATE);
>+			cgs_set_powergating_state(hwmgr->device,
>+						  AMD_IP_BLOCK_TYPE_UVD,
>+						  AMD_PG_STATE_GATE);
>+		}
> 		tonga_update_uvd_dpm(hwmgr, true);
>-		tonga_phm_powerdown_uvd(hwmgr);
>+		if (data->uvd_pg)
>+			tonga_phm_powerdown_uvd(hwmgr);
> 	} else {
>-		tonga_phm_powerup_uvd(hwmgr);
>-		cgs_set_powergating_state(hwmgr->device,
>-						AMD_IP_BLOCK_TYPE_UVD,
>-						AMD_PG_STATE_UNGATE);
>-		cgs_set_clockgating_state(hwmgr->device,
>-						AMD_IP_BLOCK_TYPE_UVD,
>-						AMD_PG_STATE_GATE);
>-
>+		if (data->uvd_pg) {
>+			tonga_phm_powerup_uvd(hwmgr);
>+			cgs_set_powergating_state(hwmgr->device,
>+						  AMD_IP_BLOCK_TYPE_UVD,
>+						  AMD_PG_STATE_UNGATE);
>+			cgs_set_clockgating_state(hwmgr->device,
>+						  AMD_IP_BLOCK_TYPE_UVD,
>+						  AMD_PG_STATE_GATE);
>+		}
> 		tonga_update_uvd_dpm(hwmgr, false);
> 	}
> 
>diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
>index f988fa7..4268293 100644
>--- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
>+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
>@@ -4653,6 +4653,8 @@ int tonga_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
> 		tonga_hwmgr_backend_fini(hwmgr);
> 	}
> 
>+	data->uvd_pg = false;
>+
> 	return result;
> }
> 
>diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.h
>index 49168d2..6a1d3f8 100644
>--- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.h
>+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.h
>@@ -352,6 +352,8 @@ struct tonga_hwmgr {
> 	bool                           acp_power_gated;  /* 1: gated, 0:not gated */
> 	bool                           pg_acp_init;
> 
>+	/* whether to enable uvd powergating */
>+	bool uvd_pg;
> };
> 
> typedef struct tonga_hwmgr tonga_hwmgr;
>-- 
>2.5.0
>

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