Attachment 121953 Details for Bug 93840 – Alien: Isolation GDB log with applied patch

Alien: Isolation GDB log with applied patch

backtrace2.log (text/plain), 224.97 KB, created by Darius Spitznagel on 2016-02-24 21:18:22 UTC

(hide)

Description:

Filename:

MIME Type:

Creator: Darius Spitznagel

Created: 2016-02-24 21:18:22 UTC

Size: 224.97 KB

patch

obsolete

>GNU gdb (Debian 7.7.1+dfsg-5) 7.7.1
>Copyright (C) 2014 Free Software Foundation, Inc.
>License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html>
>This is free software: you are free to change and redistribute it.
>There is NO WARRANTY, to the extent permitted by law.  Type "show copying"
>and "show warranty" for details.
>This GDB was configured as "x86_64-linux-gnu".
>Type "show configuration" for configuration details.
>For bug reporting instructions, please see:
><http://www.gnu.org/software/gdb/bugs/>.
>Find the GDB manual and other documentation resources online at:
><http://www.gnu.org/software/gdb/documentation/>.
>For help, type "help".
>Type "apropos word" to search for commands related to "word"...
>Reading symbols from ./AlienIsolation...(no debugging symbols found)...done.
>(gdb) run
>Starting program: /mnt/sdb/games/steamapps/common/Alien Isolation/bin/AlienIsolation 
>[Thread debugging using libthread_db enabled]
>Using host libthread_db library "/lib/x86_64-linux-gnu/libthread_db.so.1".
>[New Thread 0x7fffe9c15700 (LWP 26631)]
>[New Thread 0x7fffe2a4f700 (LWP 26632)]
>[Thread 0x7fffe2a4f700 (LWP 26632) exited]
>Setting breakpad minidump AppID = 214490
>Steam_SetMinidumpSteamID:  Caching Steam ID:  76561197970672496 [API loaded no]
>[S_API WARN] The loaded overlay DLL doesn't support ValveHookScreenshots
>[New Thread 0x7ffff7fab700 (LWP 26633)]
>[New Thread 0x7fffe2a4f700 (LWP 26634)]
>[New Thread 0x7fffe51c6700 (LWP 26635)]
>[New Thread 0x7fffe46cc700 (LWP 26636)]
>[New Thread 0x7fffa477c700 (LWP 26637)]
>[New Thread 0x7fffa3f7b700 (LWP 26638)]
>[New Thread 0x7fffe2ac8700 (LWP 26639)]
>[New Thread 0x7fffe024d700 (LWP 26640)]
>[New Thread 0x7fffe01fc700 (LWP 26641)]
>[New Thread 0x7fffa3b3a700 (LWP 26642)]
>[New Thread 0x7fffe01ab700 (LWP 26643)]
>[New Thread 0x7fffe015a700 (LWP 26644)]
>[New Thread 0x7fffe0109700 (LWP 26645)]
>[New Thread 0x7fffe2a76f00 (LWP 26646)]
>[New Thread 0x7fffa3339700 (LWP 26647)]
>[Thread 0x7fffa3339700 (LWP 26647) exited]
>[New Thread 0x7fffa3339700 (LWP 26648)]
>[Thread 0x7fffa3339700 (LWP 26648) exited]
>[New Thread 0x7fffa3339700 (LWP 26649)]
>[Thread 0x7fffa3339700 (LWP 26649) exited]
>[New Thread 0x7fffa3339700 (LWP 26650)]
>[Thread 0x7fffa3339700 (LWP 26650) exited]
>[New Thread 0x7fffa3339700 (LWP 26651)]
>[Thread 0x7fffa3339700 (LWP 26651) exited]
>[New Thread 0x7fffa3339700 (LWP 26652)]
>[Thread 0x7fffa3339700 (LWP 26652) exited]
>[New Thread 0x7fffa3339700 (LWP 26653)]
>[Thread 0x7fffa3339700 (LWP 26653) exited]
>[New Thread 0x7fffa3339700 (LWP 26654)]
>[Thread 0x7fffa3339700 (LWP 26654) exited]
>[New Thread 0x7fffa3339700 (LWP 26655)]
>[Thread 0x7fffa3339700 (LWP 26655) exited]
>[New Thread 0x7fffa3339700 (LWP 26656)]
>[Thread 0x7fffa3339700 (LWP 26656) exited]
>[New Thread 0x7fffa3339700 (LWP 26657)]
>[Thread 0x7fffa3339700 (LWP 26657) exited]
>[New Thread 0x7fffe00b8700 (LWP 26658)]
>[New Thread 0x7fffa29e8700 (LWP 26659)]
>[New Thread 0x7fffa29a0700 (LWP 26660)]
>[New Thread 0x7fffa293f700 (LWP 26661)]
>[New Thread 0x7fffa3339700 (LWP 26662)]
>[Thread 0x7fffa3339700 (LWP 26662) exited]
>[New Thread 0x7fffa3339700 (LWP 26663)]
>[Thread 0x7fffa3339700 (LWP 26663) exited]
>[New Thread 0x7fffa28c6700 (LWP 26664)]
>[New Thread 0x7fffa3339700 (LWP 26665)]
>[New Thread 0x7fffa2875700 (LWP 26666)]
>[New Thread 0x7fffa2824700 (LWP 26667)]
>[Thread 0x7fffa2824700 (LWP 26667) exited]
>[New Thread 0x7fffa2023700 (LWP 26668)]
>[Thread 0x7fffa3339700 (LWP 26665) exited]
>[New Thread 0x7fffa3339700 (LWP 26669)]
>[Thread 0x7fffa3339700 (LWP 26669) exited]
>[New Thread 0x7fffa3339700 (LWP 26670)]
>[Thread 0x7fffa3339700 (LWP 26670) exited]
>[New Thread 0x7fffa3339700 (LWP 26671)]
>[Thread 0x7fffa3339700 (LWP 26671) exited]
>[New Thread 0x7fffa3339700 (LWP 26672)]
>[New Thread 0x7fffa2824700 (LWP 26673)]
>[Thread 0x7fffa3339700 (LWP 26672) exited]
>[Thread 0x7fffa2824700 (LWP 26673) exited]
>[New Thread 0x7fffa3339700 (LWP 26674)]
>[Thread 0x7fffa3339700 (LWP 26674) exited]
>[New Thread 0x7fffa3339700 (LWP 26675)]
>[Thread 0x7fffa3339700 (LWP 26675) exited]
>[New Thread 0x7fffa2824700 (LWP 26676)]
>[Thread 0x7fffa2824700 (LWP 26676) exited]
>[New Thread 0x7fffa2824700 (LWP 26677)]
>[Thread 0x7fffa2824700 (LWP 26677) exited]
>[New Thread 0x7fffa2824700 (LWP 26678)]
>[Thread 0x7fffa2824700 (LWP 26678) exited]
>[New Thread 0x7fffa3339700 (LWP 26679)]
>[Thread 0x7fffa3339700 (LWP 26679) exited]
>[New Thread 0x7fffa2824700 (LWP 26680)]
>[Thread 0x7fffa2824700 (LWP 26680) exited]
>[New Thread 0x7fffa3339700 (LWP 26681)]
>[Thread 0x7fffa3339700 (LWP 26681) exited]
>[New Thread 0x7fffa3339700 (LWP 26682)]
>[Thread 0x7fffa3339700 (LWP 26682) exited]
>[New Thread 0x7fffa3339700 (LWP 26683)]
>[Thread 0x7fffa3339700 (LWP 26683) exited]
>[New Thread 0x7fffa3339700 (LWP 26684)]
>[Thread 0x7fffa3339700 (LWP 26684) exited]
>[New Thread 0x7fffa2824700 (LWP 26685)]
>[Thread 0x7fffa2824700 (LWP 26685) exited]
>[New Thread 0x7fffa3339700 (LWP 26686)]
>[Thread 0x7fffa3339700 (LWP 26686) exited]
>[New Thread 0x7fffa2824700 (LWP 26687)]
>[Thread 0x7fffa2824700 (LWP 26687) exited]
>[New Thread 0x7fffa2824700 (LWP 26688)]
>[Thread 0x7fffa2824700 (LWP 26688) exited]
>[New Thread 0x7fffa2824700 (LWP 26689)]
>[Thread 0x7fffa2824700 (LWP 26689) exited]
>[New Thread 0x7fffa2824700 (LWP 26690)]
>[Thread 0x7fffa2824700 (LWP 26690) exited]
>[New Thread 0x7fffa3339700 (LWP 26691)]
>[Thread 0x7fffa3339700 (LWP 26691) exited]
>[New Thread 0x7fffa2824700 (LWP 26692)]
>[Thread 0x7fffa2824700 (LWP 26692) exited]
>[New Thread 0x7fffa3339700 (LWP 26693)]
>[Thread 0x7fffa3339700 (LWP 26693) exited]
>[New Thread 0x7fffa3339700 (LWP 26694)]
>[Thread 0x7fffa3339700 (LWP 26694) exited]
>[New Thread 0x7fffa3339700 (LWP 26695)]
>[Thread 0x7fffa3339700 (LWP 26695) exited]
>[New Thread 0x7fffa3339700 (LWP 26696)]
>[Thread 0x7fffa3339700 (LWP 26696) exited]
>[New Thread 0x7fffa3339700 (LWP 26697)]
>[Thread 0x7fffa3339700 (LWP 26697) exited]
>[New Thread 0x7fffa3339700 (LWP 26698)]
>[Thread 0x7fffa3339700 (LWP 26698) exited]
>[New Thread 0x7fffa3339700 (LWP 26699)]
>[Thread 0x7fffa3339700 (LWP 26699) exited]
>[New Thread 0x7fffa3339700 (LWP 26700)]
>[Thread 0x7fffa3339700 (LWP 26700) exited]
>[New Thread 0x7fffa2824700 (LWP 26702)]
>[Thread 0x7fffa2824700 (LWP 26702) exited]
>[New Thread 0x7fffa3339700 (LWP 26703)]
>[Thread 0x7fffa3339700 (LWP 26703) exited]
>[New Thread 0x7fffa3339700 (LWP 26704)]
>[Thread 0x7fffa3339700 (LWP 26704) exited]
>[New Thread 0x7fffa3339700 (LWP 26705)]
>[Thread 0x7fffa3339700 (LWP 26705) exited]
>[New Thread 0x7fffa3339700 (LWP 26706)]
>[Thread 0x7fffa3339700 (LWP 26706) exited]
>[New Thread 0x7fffa3339700 (LWP 26707)]
>[Thread 0x7fffa3339700 (LWP 26707) exited]
>[New Thread 0x7fffa3339700 (LWP 26708)]
>[Thread 0x7fffa3339700 (LWP 26708) exited]
>[New Thread 0x7fffa2824700 (LWP 26709)]
>[Thread 0x7fffa2824700 (LWP 26709) exited]
>[New Thread 0x7fffa2824700 (LWP 26710)]
>[Thread 0x7fffa2824700 (LWP 26710) exited]
>[New Thread 0x7fffa2824700 (LWP 26711)]
>[Thread 0x7fffa2824700 (LWP 26711) exited]
>[New Thread 0x7fffa2824700 (LWP 26712)]
>[Thread 0x7fffa2824700 (LWP 26712) exited]
>[New Thread 0x7fffa2824700 (LWP 26713)]
>[Thread 0x7fffa2824700 (LWP 26713) exited]
>[New Thread 0x7fffa2824700 (LWP 26714)]
>[Thread 0x7fffa2824700 (LWP 26714) exited]
>[New Thread 0x7fffa3339700 (LWP 26715)]
>[Thread 0x7fffa3339700 (LWP 26715) exited]
>[New Thread 0x7fffa2824700 (LWP 26716)]
>[Thread 0x7fffa2824700 (LWP 26716) exited]
>[New Thread 0x7fffa3339700 (LWP 26717)]
>[Thread 0x7fffa3339700 (LWP 26717) exited]
>[New Thread 0x7fffa3339700 (LWP 26718)]
>[Thread 0x7fffa3339700 (LWP 26718) exited]
>[New Thread 0x7fffa3339700 (LWP 26719)]
>[Thread 0x7fffa3339700 (LWP 26719) exited]
>[New Thread 0x7fffa2824700 (LWP 26720)]
>[Thread 0x7fffa2824700 (LWP 26720) exited]
>[New Thread 0x7fffa3339700 (LWP 26721)]
>[Thread 0x7fffa3339700 (LWP 26721) exited]
>[New Thread 0x7fffa2824700 (LWP 26722)]
>[Thread 0x7fffa2824700 (LWP 26722) exited]
>[New Thread 0x7fffa2824700 (LWP 26723)]
>[Thread 0x7fffa2824700 (LWP 26723) exited]
>[New Thread 0x7fffa2824700 (LWP 26724)]
>[Thread 0x7fffa2824700 (LWP 26724) exited]
>[New Thread 0x7fffa2824700 (LWP 26725)]
>[Thread 0x7fffa2824700 (LWP 26725) exited]
>[New Thread 0x7fffa3339700 (LWP 26726)]
>[Thread 0x7fffa3339700 (LWP 26726) exited]
>[New Thread 0x7fffa2824700 (LWP 26727)]
>[Thread 0x7fffa2824700 (LWP 26727) exited]
>[New Thread 0x7fffa3339700 (LWP 26728)]
>[Thread 0x7fffa3339700 (LWP 26728) exited]
>[New Thread 0x7fffa3339700 (LWP 26729)]
>[Thread 0x7fffa3339700 (LWP 26729) exited]
>[New Thread 0x7fffa3339700 (LWP 26730)]
>[Thread 0x7fffa3339700 (LWP 26730) exited]
>[New Thread 0x7fffa3339700 (LWP 26731)]
>[Thread 0x7fffa3339700 (LWP 26731) exited]
>[New Thread 0x7fffa3339700 (LWP 26732)]
>[Thread 0x7fffa3339700 (LWP 26732) exited]
>[New Thread 0x7fffa3339700 (LWP 26733)]
>[Thread 0x7fffa3339700 (LWP 26733) exited]
>[New Thread 0x7fffa2824700 (LWP 26734)]
>[Thread 0x7fffa2824700 (LWP 26734) exited]
>[New Thread 0x7fffa3339700 (LWP 26735)]
>[Thread 0x7fffa3339700 (LWP 26735) exited]
>[New Thread 0x7fffa3339700 (LWP 26736)]
>[Thread 0x7fffa3339700 (LWP 26736) exited]
>[New Thread 0x7fffa2824700 (LWP 26737)]
>[Thread 0x7fffa2824700 (LWP 26737) exited]
>[New Thread 0x7fffa3339700 (LWP 26738)]
>[Thread 0x7fffa3339700 (LWP 26738) exited]
>[New Thread 0x7fffa3339700 (LWP 26739)]
>[Thread 0x7fffa3339700 (LWP 26739) exited]
>[New Thread 0x7fffa3339700 (LWP 26740)]
>[Thread 0x7fffa3339700 (LWP 26740) exited]
>[New Thread 0x7fffa2824700 (LWP 26741)]
>[Thread 0x7fffa2824700 (LWP 26741) exited]
>[New Thread 0x7fffa2824700 (LWP 26742)]
>[Thread 0x7fffa2824700 (LWP 26742) exited]
>[New Thread 0x7fffa2824700 (LWP 26743)]
>[Thread 0x7fffa2824700 (LWP 26743) exited]
>[New Thread 0x7fffa3339700 (LWP 26744)]
>[Thread 0x7fffa3339700 (LWP 26744) exited]
>[New Thread 0x7fffa2824700 (LWP 26745)]
>[Thread 0x7fffa2824700 (LWP 26745) exited]
>[New Thread 0x7fffa3339700 (LWP 26746)]
>[Thread 0x7fffa3339700 (LWP 26746) exited]
>[New Thread 0x7fffa3339700 (LWP 26747)]
>[Thread 0x7fffa3339700 (LWP 26747) exited]
>[New Thread 0x7fffa2824700 (LWP 26748)]
>[Thread 0x7fffa2824700 (LWP 26748) exited]
>[New Thread 0x7fffa3339700 (LWP 26749)]
>[Thread 0x7fffa3339700 (LWP 26749) exited]
>[New Thread 0x7fffa2824700 (LWP 26750)]
>[Thread 0x7fffa2824700 (LWP 26750) exited]
>[New Thread 0x7fffa2824700 (LWP 26751)]
>[Thread 0x7fffa2824700 (LWP 26751) exited]
>[New Thread 0x7fffa2824700 (LWP 26752)]
>[Thread 0x7fffa2824700 (LWP 26752) exited]
>[New Thread 0x7fffa3339700 (LWP 26753)]
>[Thread 0x7fffa3339700 (LWP 26753) exited]
>[New Thread 0x7fffa2824700 (LWP 26754)]
>[Thread 0x7fffa2824700 (LWP 26754) exited]
>[New Thread 0x7fffa2824700 (LWP 26755)]
>[Thread 0x7fffa2824700 (LWP 26755) exited]
>[New Thread 0x7fffa2824700 (LWP 26756)]
>[Thread 0x7fffa2824700 (LWP 26756) exited]
>[New Thread 0x7fffa2824700 (LWP 26757)]
>[Thread 0x7fffa2824700 (LWP 26757) exited]
>[New Thread 0x7fffa3339700 (LWP 26758)]
>[Thread 0x7fffa3339700 (LWP 26758) exited]
>[New Thread 0x7fffa2824700 (LWP 26759)]
>[Thread 0x7fffa2824700 (LWP 26759) exited]
>[New Thread 0x7fffa3339700 (LWP 26760)]
>[Thread 0x7fffa3339700 (LWP 26760) exited]
>[New Thread 0x7fffa3339700 (LWP 26761)]
>[Thread 0x7fffa3339700 (LWP 26761) exited]
>[New Thread 0x7fffa3339700 (LWP 26762)]
>[Thread 0x7fffa3339700 (LWP 26762) exited]
>[New Thread 0x7fffa3339700 (LWP 26763)]
>[Thread 0x7fffa3339700 (LWP 26763) exited]
>[New Thread 0x7fffa2824700 (LWP 26764)]
>[Thread 0x7fffa2824700 (LWP 26764) exited]
>[New Thread 0x7fffa2824700 (LWP 26765)]
>[Thread 0x7fffa2824700 (LWP 26765) exited]
>[New Thread 0x7fffa3339700 (LWP 26766)]
>[Thread 0x7fffa3339700 (LWP 26766) exited]
>[New Thread 0x7fffa2824700 (LWP 26767)]
>[Thread 0x7fffa2824700 (LWP 26767) exited]
>[New Thread 0x7fffa3339700 (LWP 26768)]
>[Thread 0x7fffa3339700 (LWP 26768) exited]
>[New Thread 0x7fffa3339700 (LWP 26769)]
>[Thread 0x7fffa3339700 (LWP 26769) exited]
>[New Thread 0x7fffa2824700 (LWP 26770)]
>[Thread 0x7fffa2824700 (LWP 26770) exited]
>[New Thread 0x7fffa3339700 (LWP 26771)]
>[Thread 0x7fffa3339700 (LWP 26771) exited]
>[New Thread 0x7fffa2824700 (LWP 26772)]
>[Thread 0x7fffa2824700 (LWP 26772) exited]
>[New Thread 0x7fffa2824700 (LWP 26773)]
>[Thread 0x7fffa2824700 (LWP 26773) exited]
>[New Thread 0x7fffa3339700 (LWP 26774)]
>[Thread 0x7fffa3339700 (LWP 26774) exited]
>[New Thread 0x7fffa2824700 (LWP 26775)]
>[Thread 0x7fffa2824700 (LWP 26775) exited]
>[New Thread 0x7fffa2824700 (LWP 26776)]
>[New Thread 0x7fffa3339700 (LWP 26777)]
>[Thread 0x7fffa2824700 (LWP 26776) exited]
>[Thread 0x7fffa3339700 (LWP 26777) exited]
>[New Thread 0x7fffa3339700 (LWP 26778)]
>[Thread 0x7fffa3339700 (LWP 26778) exited]
>[New Thread 0x7fffa3339700 (LWP 26779)]
>[Thread 0x7fffa3339700 (LWP 26779) exited]
>[New Thread 0x7fffa3339700 (LWP 26780)]
>[Thread 0x7fffa3339700 (LWP 26780) exited]
>[New Thread 0x7fffa3339700 (LWP 26781)]
>[Thread 0x7fffa3339700 (LWP 26781) exited]
>[New Thread 0x7fffa3339700 (LWP 26782)]
>[Thread 0x7fffa3339700 (LWP 26782) exited]
>[New Thread 0x7fffa2824700 (LWP 26783)]
>[Thread 0x7fffa2824700 (LWP 26783) exited]
>[New Thread 0x7fffa3339700 (LWP 26784)]
>[Thread 0x7fffa3339700 (LWP 26784) exited]
>[New Thread 0x7fffa3339700 (LWP 26785)]
>[Thread 0x7fffa3339700 (LWP 26785) exited]
>[New Thread 0x7fffa3339700 (LWP 26786)]
>[Thread 0x7fffa3339700 (LWP 26786) exited]
>[New Thread 0x7fffa3339700 (LWP 26787)]
>[Thread 0x7fffa3339700 (LWP 26787) exited]
>[New Thread 0x7fffa2824700 (LWP 26788)]
>[Thread 0x7fffa2824700 (LWP 26788) exited]
>[New Thread 0x7fffa3339700 (LWP 26789)]
>[Thread 0x7fffa3339700 (LWP 26789) exited]
>[New Thread 0x7fffa2824700 (LWP 26790)]
>[Thread 0x7fffa2824700 (LWP 26790) exited]
>[New Thread 0x7fffa3339700 (LWP 26791)]
>[Thread 0x7fffa3339700 (LWP 26791) exited]
>[New Thread 0x7fffa2824700 (LWP 26792)]
>[Thread 0x7fffa2824700 (LWP 26792) exited]
>[New Thread 0x7fffa2824700 (LWP 26793)]
>[Thread 0x7fffa2824700 (LWP 26793) exited]
>[New Thread 0x7fffa2824700 (LWP 26794)]
>[Thread 0x7fffa2824700 (LWP 26794) exited]
>[New Thread 0x7fffa3339700 (LWP 26795)]
>[Thread 0x7fffa3339700 (LWP 26795) exited]
>[New Thread 0x7fffa2824700 (LWP 26796)]
>[Thread 0x7fffa2824700 (LWP 26796) exited]
>[New Thread 0x7fffa2824700 (LWP 26797)]
>[Thread 0x7fffa2824700 (LWP 26797) exited]
>[New Thread 0x7fffa2824700 (LWP 26798)]
>[Thread 0x7fffa2824700 (LWP 26798) exited]
>[New Thread 0x7fffa3339700 (LWP 26799)]
>[Thread 0x7fffa3339700 (LWP 26799) exited]
>[New Thread 0x7fffa2824700 (LWP 26800)]
>[Thread 0x7fffa2824700 (LWP 26800) exited]
>[New Thread 0x7fffa2824700 (LWP 26801)]
>[Thread 0x7fffa2824700 (LWP 26801) exited]
>[New Thread 0x7fffa3339700 (LWP 26802)]
>[Thread 0x7fffa3339700 (LWP 26802) exited]
>[New Thread 0x7fffa2824700 (LWP 26803)]
>[Thread 0x7fffa2824700 (LWP 26803) exited]
>[New Thread 0x7fffa3339700 (LWP 26804)]
>[Thread 0x7fffa3339700 (LWP 26804) exited]
>[New Thread 0x7fffa3339700 (LWP 26805)]
>[Thread 0x7fffa3339700 (LWP 26805) exited]
>[New Thread 0x7fffa3339700 (LWP 26806)]
>[Thread 0x7fffa3339700 (LWP 26806) exited]
>[New Thread 0x7fffa2824700 (LWP 26808)]
>[Thread 0x7fffa2824700 (LWP 26808) exited]
>[New Thread 0x7fffa3339700 (LWP 26809)]
>[Thread 0x7fffa3339700 (LWP 26809) exited]
>[New Thread 0x7fffa3339700 (LWP 26810)]
>[Thread 0x7fffa3339700 (LWP 26810) exited]
>[New Thread 0x7fffa3339700 (LWP 26811)]
>[Thread 0x7fffa3339700 (LWP 26811) exited]
>[New Thread 0x7fffa2824700 (LWP 26812)]
>[Thread 0x7fffa2824700 (LWP 26812) exited]
>[New Thread 0x7fffa3339700 (LWP 26813)]
>[Thread 0x7fffa3339700 (LWP 26813) exited]
>[New Thread 0x7fffa3339700 (LWP 26814)]
>[Thread 0x7fffa3339700 (LWP 26814) exited]
>[New Thread 0x7fffa2824700 (LWP 26815)]
>[Thread 0x7fffa2824700 (LWP 26815) exited]
>[New Thread 0x7fffa3339700 (LWP 26816)]
>[Thread 0x7fffa3339700 (LWP 26816) exited]
>[New Thread 0x7fffa3339700 (LWP 26817)]
>[Thread 0x7fffa3339700 (LWP 26817) exited]
>[New Thread 0x7fffa3339700 (LWP 26818)]
>[Thread 0x7fffa3339700 (LWP 26818) exited]
>[New Thread 0x7fffa2824700 (LWP 26819)]
>[Thread 0x7fffa2824700 (LWP 26819) exited]
>[New Thread 0x7fffa3339700 (LWP 26821)]
>[Thread 0x7fffa3339700 (LWP 26821) exited]
>[New Thread 0x7fffa2824700 (LWP 26822)]
>[Thread 0x7fffa2824700 (LWP 26822) exited]
>[New Thread 0x7fffa3339700 (LWP 26823)]
>[Thread 0x7fffa3339700 (LWP 26823) exited]
>[New Thread 0x7fffa3339700 (LWP 26824)]
>[Thread 0x7fffa3339700 (LWP 26824) exited]
>[New Thread 0x7fffa2824700 (LWP 26825)]
>[Thread 0x7fffa2824700 (LWP 26825) exited]
>[New Thread 0x7fffa3339700 (LWP 26826)]
>[Thread 0x7fffa3339700 (LWP 26826) exited]
>[New Thread 0x7fffa3339700 (LWP 26827)]
>[Thread 0x7fffa3339700 (LWP 26827) exited]
>[New Thread 0x7fffa3339700 (LWP 26828)]
>[Thread 0x7fffa3339700 (LWP 26828) exited]
>[New Thread 0x7fffa3339700 (LWP 26829)]
>[Thread 0x7fffa3339700 (LWP 26829) exited]
>[New Thread 0x7fffa2824700 (LWP 26830)]
>[Thread 0x7fffa2824700 (LWP 26830) exited]
>[New Thread 0x7fffa3339700 (LWP 26831)]
>[Thread 0x7fffa3339700 (LWP 26831) exited]
>[New Thread 0x7fffa2824700 (LWP 26832)]
>[Thread 0x7fffa2824700 (LWP 26832) exited]
>[New Thread 0x7fffa2824700 (LWP 26833)]
>[Thread 0x7fffa2824700 (LWP 26833) exited]
>[New Thread 0x7fffa2824700 (LWP 26834)]
>[Thread 0x7fffa2824700 (LWP 26834) exited]
>[New Thread 0x7fffa3339700 (LWP 26835)]
>[Thread 0x7fffa3339700 (LWP 26835) exited]
>[New Thread 0x7fffa2824700 (LWP 26836)]
>[Thread 0x7fffa2824700 (LWP 26836) exited]
>[New Thread 0x7fffa3339700 (LWP 26837)]
>[Thread 0x7fffa3339700 (LWP 26837) exited]
>[New Thread 0x7fffa2824700 (LWP 26838)]
>[Thread 0x7fffa2824700 (LWP 26838) exited]
>[New Thread 0x7fffa3339700 (LWP 26839)]
>[Thread 0x7fffa3339700 (LWP 26839) exited]
>[New Thread 0x7fffa2824700 (LWP 26840)]
>[Thread 0x7fffa2824700 (LWP 26840) exited]
>[New Thread 0x7fffa3339700 (LWP 26841)]
>[Thread 0x7fffa3339700 (LWP 26841) exited]
>[New Thread 0x7fffa2824700 (LWP 26842)]
>[Thread 0x7fffa2824700 (LWP 26842) exited]
>[New Thread 0x7fffa3339700 (LWP 26843)]
>[Thread 0x7fffa3339700 (LWP 26843) exited]
>[New Thread 0x7fffa2824700 (LWP 26844)]
>[Thread 0x7fffa2824700 (LWP 26844) exited]
>[New Thread 0x7fffa3339700 (LWP 26845)]
>[Thread 0x7fffa3339700 (LWP 26845) exited]
>[New Thread 0x7fffa2824700 (LWP 26846)]
>[Thread 0x7fffa2824700 (LWP 26846) exited]
>[New Thread 0x7fffa3339700 (LWP 26847)]
>[Thread 0x7fffa3339700 (LWP 26847) exited]
>[New Thread 0x7fffa2824700 (LWP 26848)]
>[Thread 0x7fffa2824700 (LWP 26848) exited]
>[New Thread 0x7fffa3339700 (LWP 26849)]
>[Thread 0x7fffa3339700 (LWP 26849) exited]
>[New Thread 0x7fffa2824700 (LWP 26850)]
>[Thread 0x7fffa2824700 (LWP 26850) exited]
>[New Thread 0x7fffa3339700 (LWP 26851)]
>[Thread 0x7fffa3339700 (LWP 26851) exited]
>[New Thread 0x7fffa2824700 (LWP 26852)]
>[Thread 0x7fffa2824700 (LWP 26852) exited]
>[New Thread 0x7fffa3339700 (LWP 26853)]
>[Thread 0x7fffa3339700 (LWP 26853) exited]
>[New Thread 0x7fffa2824700 (LWP 26854)]
>[Thread 0x7fffa2824700 (LWP 26854) exited]
>[New Thread 0x7fffa3339700 (LWP 26855)]
>[Thread 0x7fffa3339700 (LWP 26855) exited]
>[New Thread 0x7fffa2824700 (LWP 26856)]
>[Thread 0x7fffa2824700 (LWP 26856) exited]
>[New Thread 0x7fffa3339700 (LWP 26857)]
>[Thread 0x7fffa3339700 (LWP 26857) exited]
>[New Thread 0x7fffa2824700 (LWP 26858)]
>[Thread 0x7fffa2824700 (LWP 26858) exited]
>[New Thread 0x7fffa3339700 (LWP 26859)]
>[Thread 0x7fffa3339700 (LWP 26859) exited]
>[New Thread 0x7fffa2824700 (LWP 26860)]
>[Thread 0x7fffa2824700 (LWP 26860) exited]
>[New Thread 0x7fffa3339700 (LWP 26861)]
>[Thread 0x7fffa3339700 (LWP 26861) exited]
>[New Thread 0x7fffa2824700 (LWP 26862)]
>[Thread 0x7fffa2824700 (LWP 26862) exited]
>[New Thread 0x7fffa3339700 (LWP 26863)]
>[Thread 0x7fffa3339700 (LWP 26863) exited]
>[New Thread 0x7fffa2824700 (LWP 26864)]
>[Thread 0x7fffa2824700 (LWP 26864) exited]
>[New Thread 0x7fffa3339700 (LWP 26865)]
>[Thread 0x7fffa3339700 (LWP 26865) exited]
>[New Thread 0x7fffa2824700 (LWP 26866)]
>[Thread 0x7fffa2824700 (LWP 26866) exited]
>[New Thread 0x7fffa3339700 (LWP 26867)]
>[Thread 0x7fffa3339700 (LWP 26867) exited]
>[New Thread 0x7fffa2824700 (LWP 26868)]
>[Thread 0x7fffa2824700 (LWP 26868) exited]
>[New Thread 0x7fffa3339700 (LWP 26869)]
>[Thread 0x7fffa3339700 (LWP 26869) exited]
>[New Thread 0x7fffa2824700 (LWP 26870)]
>[Thread 0x7fffa2824700 (LWP 26870) exited]
>[New Thread 0x7fffa3339700 (LWP 26871)]
>[Thread 0x7fffa3339700 (LWP 26871) exited]
>[New Thread 0x7fffa2824700 (LWP 26872)]
>[Thread 0x7fffa2824700 (LWP 26872) exited]
>[New Thread 0x7fffa3339700 (LWP 26873)]
>[Thread 0x7fffa3339700 (LWP 26873) exited]
>[New Thread 0x7fffa2824700 (LWP 26874)]
>[Thread 0x7fffa2824700 (LWP 26874) exited]
>[New Thread 0x7fffa3339700 (LWP 26875)]
>[Thread 0x7fffa3339700 (LWP 26875) exited]
>[New Thread 0x7fffa2824700 (LWP 26876)]
>[Thread 0x7fffa2824700 (LWP 26876) exited]
>[New Thread 0x7fffa3339700 (LWP 26877)]
>[Thread 0x7fffa3339700 (LWP 26877) exited]
>[New Thread 0x7fffa2824700 (LWP 26878)]
>[Thread 0x7fffa2824700 (LWP 26878) exited]
>[New Thread 0x7fffa3339700 (LWP 26879)]
>[Thread 0x7fffa3339700 (LWP 26879) exited]
>[New Thread 0x7fffa2824700 (LWP 26880)]
>[Thread 0x7fffa2824700 (LWP 26880) exited]
>[New Thread 0x7fffa3339700 (LWP 26881)]
>[Thread 0x7fffa3339700 (LWP 26881) exited]
>[New Thread 0x7fffa2824700 (LWP 26882)]
>[Thread 0x7fffa2824700 (LWP 26882) exited]
>[New Thread 0x7fffa3339700 (LWP 26883)]
>[Thread 0x7fffa3339700 (LWP 26883) exited]
>[New Thread 0x7fffa2824700 (LWP 26884)]
>[Thread 0x7fffa2824700 (LWP 26884) exited]
>[New Thread 0x7fffa3339700 (LWP 26885)]
>[Thread 0x7fffa3339700 (LWP 26885) exited]
>[New Thread 0x7fffa2824700 (LWP 26886)]
>[Thread 0x7fffa2824700 (LWP 26886) exited]
>[New Thread 0x7fffa3339700 (LWP 26887)]
>[Thread 0x7fffa3339700 (LWP 26887) exited]
>[New Thread 0x7fffa2824700 (LWP 26888)]
>[Thread 0x7fffa2824700 (LWP 26888) exited]
>[New Thread 0x7fffa3339700 (LWP 26889)]
>[Thread 0x7fffa3339700 (LWP 26889) exited]
>[New Thread 0x7fffa2824700 (LWP 26890)]
>[Thread 0x7fffa2824700 (LWP 26890) exited]
>[New Thread 0x7fffa3339700 (LWP 26891)]
>[Thread 0x7fffa3339700 (LWP 26891) exited]
>[New Thread 0x7fffa2824700 (LWP 26892)]
>[Thread 0x7fffa2824700 (LWP 26892) exited]
>[New Thread 0x7fffa3339700 (LWP 26893)]
>[Thread 0x7fffa3339700 (LWP 26893) exited]
>[New Thread 0x7fffa2824700 (LWP 26894)]
>[Thread 0x7fffa2824700 (LWP 26894) exited]
>[New Thread 0x7fffa3339700 (LWP 26895)]
>[Thread 0x7fffa3339700 (LWP 26895) exited]
>[New Thread 0x7fffa2824700 (LWP 26896)]
>[Thread 0x7fffa2824700 (LWP 26896) exited]
>[New Thread 0x7fffa3339700 (LWP 26897)]
>[Thread 0x7fffa3339700 (LWP 26897) exited]
>[New Thread 0x7fffa2824700 (LWP 26898)]
>[Thread 0x7fffa2824700 (LWP 26898) exited]
>[New Thread 0x7fffa3339700 (LWP 26899)]
>[Thread 0x7fffa3339700 (LWP 26899) exited]
>[New Thread 0x7fffa2824700 (LWP 26900)]
>[Thread 0x7fffa2824700 (LWP 26900) exited]
>[New Thread 0x7fffa3339700 (LWP 26901)]
>[Thread 0x7fffa3339700 (LWP 26901) exited]
>[New Thread 0x7fffa2824700 (LWP 26902)]
>[Thread 0x7fffa2824700 (LWP 26902) exited]
>[New Thread 0x7fffa3339700 (LWP 26903)]
>[Thread 0x7fffa3339700 (LWP 26903) exited]
>[New Thread 0x7fffa2824700 (LWP 26904)]
>[Thread 0x7fffa2824700 (LWP 26904) exited]
>[New Thread 0x7fffa3339700 (LWP 26905)]
>[Thread 0x7fffa3339700 (LWP 26905) exited]
>[New Thread 0x7fffa2824700 (LWP 26906)]
>[Thread 0x7fffa2824700 (LWP 26906) exited]
>[New Thread 0x7fffa3339700 (LWP 26907)]
>[Thread 0x7fffa3339700 (LWP 26907) exited]
>[New Thread 0x7fffa2824700 (LWP 26908)]
>[Thread 0x7fffa2824700 (LWP 26908) exited]
>[New Thread 0x7fffa3339700 (LWP 26909)]
>[Thread 0x7fffa3339700 (LWP 26909) exited]
>[New Thread 0x7fffa2824700 (LWP 26910)]
>[Thread 0x7fffa2824700 (LWP 26910) exited]
>[New Thread 0x7fffa3339700 (LWP 26911)]
>[Thread 0x7fffa3339700 (LWP 26911) exited]
>[New Thread 0x7fffa2824700 (LWP 26912)]
>[Thread 0x7fffa2824700 (LWP 26912) exited]
>[New Thread 0x7fffa3339700 (LWP 26913)]
>[Thread 0x7fffa3339700 (LWP 26913) exited]
>[New Thread 0x7fffa2824700 (LWP 26914)]
>[Thread 0x7fffa2824700 (LWP 26914) exited]
>[New Thread 0x7fffa3339700 (LWP 26915)]
>[Thread 0x7fffa3339700 (LWP 26915) exited]
>[New Thread 0x7fffa2824700 (LWP 26916)]
>[Thread 0x7fffa2824700 (LWP 26916) exited]
>[New Thread 0x7fffa3339700 (LWP 26917)]
>[Thread 0x7fffa3339700 (LWP 26917) exited]
>[New Thread 0x7fffa2824700 (LWP 26918)]
>[Thread 0x7fffa2824700 (LWP 26918) exited]
>[New Thread 0x7fffa3339700 (LWP 26919)]
>[Thread 0x7fffa3339700 (LWP 26919) exited]
>[New Thread 0x7fffa2824700 (LWP 26920)]
>[Thread 0x7fffa2824700 (LWP 26920) exited]
>[New Thread 0x7fffa3339700 (LWP 26921)]
>[Thread 0x7fffa3339700 (LWP 26921) exited]
>[New Thread 0x7fffa2824700 (LWP 26922)]
>[Thread 0x7fffa2824700 (LWP 26922) exited]
>[New Thread 0x7fffa3339700 (LWP 26923)]
>[Thread 0x7fffa3339700 (LWP 26923) exited]
>[New Thread 0x7fffa2824700 (LWP 26924)]
>[Thread 0x7fffa2824700 (LWP 26924) exited]
>[New Thread 0x7fffa3339700 (LWP 26925)]
>[Thread 0x7fffa3339700 (LWP 26925) exited]
>[New Thread 0x7fffa2824700 (LWP 26926)]
>[Thread 0x7fffa2824700 (LWP 26926) exited]
>[New Thread 0x7fffa3339700 (LWP 26927)]
>[Thread 0x7fffa3339700 (LWP 26927) exited]
>[New Thread 0x7fffa2824700 (LWP 26928)]
>[Thread 0x7fffa2824700 (LWP 26928) exited]
>[New Thread 0x7fffa3339700 (LWP 26929)]
>[Thread 0x7fffa3339700 (LWP 26929) exited]
>[New Thread 0x7fffa2824700 (LWP 26930)]
>[Thread 0x7fffa2824700 (LWP 26930) exited]
>[New Thread 0x7fffa3339700 (LWP 26931)]
>[Thread 0x7fffa3339700 (LWP 26931) exited]
>[New Thread 0x7fffa2824700 (LWP 26932)]
>[Thread 0x7fffa2824700 (LWP 26932) exited]
>[New Thread 0x7fffa3339700 (LWP 26933)]
>[Thread 0x7fffa3339700 (LWP 26933) exited]
>[New Thread 0x7fffa2824700 (LWP 26934)]
>[Thread 0x7fffa2824700 (LWP 26934) exited]
>[New Thread 0x7fffa3339700 (LWP 26935)]
>[Thread 0x7fffa3339700 (LWP 26935) exited]
>[New Thread 0x7fffa2824700 (LWP 26936)]
>[Thread 0x7fffa2824700 (LWP 26936) exited]
>[New Thread 0x7fffa3339700 (LWP 26937)]
>[Thread 0x7fffa3339700 (LWP 26937) exited]
>[New Thread 0x7fffa2824700 (LWP 26938)]
>[Thread 0x7fffa2824700 (LWP 26938) exited]
>[New Thread 0x7fffa3339700 (LWP 26939)]
>[Thread 0x7fffa3339700 (LWP 26939) exited]
>[New Thread 0x7fffa2824700 (LWP 26940)]
>[Thread 0x7fffa2824700 (LWP 26940) exited]
>[New Thread 0x7fffa3339700 (LWP 26941)]
>[Thread 0x7fffa3339700 (LWP 26941) exited]
>[New Thread 0x7fffa2824700 (LWP 26942)]
>[Thread 0x7fffa2824700 (LWP 26942) exited]
>[New Thread 0x7fffa3339700 (LWP 26943)]
>[Thread 0x7fffa3339700 (LWP 26943) exited]
>[New Thread 0x7fffa2824700 (LWP 26944)]
>[Thread 0x7fffa2824700 (LWP 26944) exited]
>[New Thread 0x7fffa3339700 (LWP 26945)]
>[Thread 0x7fffa3339700 (LWP 26945) exited]
>[New Thread 0x7fffa2824700 (LWP 26946)]
>[Thread 0x7fffa2824700 (LWP 26946) exited]
>[New Thread 0x7fffa3339700 (LWP 26947)]
>[Thread 0x7fffa3339700 (LWP 26947) exited]
>[New Thread 0x7fffa2824700 (LWP 26948)]
>[Thread 0x7fffa2824700 (LWP 26948) exited]
>[New Thread 0x7fffa3339700 (LWP 26949)]
>[Thread 0x7fffa3339700 (LWP 26949) exited]
>[New Thread 0x7fffa2824700 (LWP 26950)]
>[Thread 0x7fffa2824700 (LWP 26950) exited]
>[New Thread 0x7fffa3339700 (LWP 26951)]
>[Thread 0x7fffa3339700 (LWP 26951) exited]
>[New Thread 0x7fffa2824700 (LWP 26952)]
>[Thread 0x7fffa2824700 (LWP 26952) exited]
>[New Thread 0x7fffa3339700 (LWP 26953)]
>[Thread 0x7fffa3339700 (LWP 26953) exited]
>[New Thread 0x7fffa2824700 (LWP 26954)]
>[Thread 0x7fffa2824700 (LWP 26954) exited]
>[New Thread 0x7fffa3339700 (LWP 26955)]
>[Thread 0x7fffa3339700 (LWP 26955) exited]
>[New Thread 0x7fffa2824700 (LWP 26956)]
>[Thread 0x7fffa2824700 (LWP 26956) exited]
>[New Thread 0x7fffa3339700 (LWP 26957)]
>[Thread 0x7fffa3339700 (LWP 26957) exited]
>[New Thread 0x7fffa2824700 (LWP 26958)]
>[Thread 0x7fffa2824700 (LWP 26958) exited]
>[New Thread 0x7fffa3339700 (LWP 26959)]
>[Thread 0x7fffa3339700 (LWP 26959) exited]
>[New Thread 0x7fffa2824700 (LWP 26960)]
>[Thread 0x7fffa2824700 (LWP 26960) exited]
>[New Thread 0x7fffa3339700 (LWP 26961)]
>[Thread 0x7fffa3339700 (LWP 26961) exited]
>[New Thread 0x7fffa2824700 (LWP 26962)]
>[Thread 0x7fffa2824700 (LWP 26962) exited]
>[New Thread 0x7fffa3339700 (LWP 26963)]
>[Thread 0x7fffa3339700 (LWP 26963) exited]
>[New Thread 0x7fffa2824700 (LWP 26964)]
>[Thread 0x7fffa2824700 (LWP 26964) exited]
>[New Thread 0x7fffa3339700 (LWP 26965)]
>[Thread 0x7fffa3339700 (LWP 26965) exited]
>[New Thread 0x7fffa2824700 (LWP 26966)]
>[Thread 0x7fffa2824700 (LWP 26966) exited]
>[New Thread 0x7fffa3339700 (LWP 26967)]
>[Thread 0x7fffa3339700 (LWP 26967) exited]
>[New Thread 0x7fffa2824700 (LWP 26968)]
>[Thread 0x7fffa2824700 (LWP 26968) exited]
>[New Thread 0x7fffa3339700 (LWP 26969)]
>[Thread 0x7fffa3339700 (LWP 26969) exited]
>[New Thread 0x7fffa2824700 (LWP 26970)]
>[Thread 0x7fffa2824700 (LWP 26970) exited]
>[New Thread 0x7fffa3339700 (LWP 26971)]
>[Thread 0x7fffa3339700 (LWP 26971) exited]
>[New Thread 0x7fffa2824700 (LWP 26972)]
>[Thread 0x7fffa2824700 (LWP 26972) exited]
>[New Thread 0x7fffa3339700 (LWP 26973)]
>[Thread 0x7fffa3339700 (LWP 26973) exited]
>[New Thread 0x7fffa2824700 (LWP 26974)]
>[Thread 0x7fffa2824700 (LWP 26974) exited]
>[New Thread 0x7fffa3339700 (LWP 26975)]
>[Thread 0x7fffa3339700 (LWP 26975) exited]
>[New Thread 0x7fffa2824700 (LWP 26976)]
>[Thread 0x7fffa2824700 (LWP 26976) exited]
>[New Thread 0x7fffa3339700 (LWP 26977)]
>[Thread 0x7fffa3339700 (LWP 26977) exited]
>[New Thread 0x7fffa2824700 (LWP 26978)]
>[Thread 0x7fffa2824700 (LWP 26978) exited]
>[New Thread 0x7fffa3339700 (LWP 26979)]
>[Thread 0x7fffa3339700 (LWP 26979) exited]
>[New Thread 0x7fffa2824700 (LWP 26980)]
>[Thread 0x7fffa2824700 (LWP 26980) exited]
>[New Thread 0x7fffa3339700 (LWP 26981)]
>[Thread 0x7fffa3339700 (LWP 26981) exited]
>[New Thread 0x7fffa2824700 (LWP 26982)]
>[Thread 0x7fffa2824700 (LWP 26982) exited]
>[New Thread 0x7fffa3339700 (LWP 26983)]
>[Thread 0x7fffa3339700 (LWP 26983) exited]
>[New Thread 0x7fffa2824700 (LWP 26984)]
>[Thread 0x7fffa2824700 (LWP 26984) exited]
>[New Thread 0x7fffa3339700 (LWP 26985)]
>[Thread 0x7fffa3339700 (LWP 26985) exited]
>[New Thread 0x7fffa2824700 (LWP 26986)]
>[Thread 0x7fffa2824700 (LWP 26986) exited]
>[New Thread 0x7fffa3339700 (LWP 26987)]
>[Thread 0x7fffa3339700 (LWP 26987) exited]
>[New Thread 0x7fffa2824700 (LWP 26988)]
>[Thread 0x7fffa2824700 (LWP 26988) exited]
>[New Thread 0x7fffa3339700 (LWP 26989)]
>[Thread 0x7fffa3339700 (LWP 26989) exited]
>[New Thread 0x7fffa2824700 (LWP 26990)]
>[Thread 0x7fffa2824700 (LWP 26990) exited]
>[New Thread 0x7fffa3339700 (LWP 26991)]
>[Thread 0x7fffa3339700 (LWP 26991) exited]
>[New Thread 0x7fffa2824700 (LWP 26992)]
>[Thread 0x7fffa2824700 (LWP 26992) exited]
>[New Thread 0x7fffa3339700 (LWP 26993)]
>[Thread 0x7fffa3339700 (LWP 26993) exited]
>[New Thread 0x7fffa2824700 (LWP 26994)]
>[Thread 0x7fffa2824700 (LWP 26994) exited]
>[New Thread 0x7fffa3339700 (LWP 26995)]
>[Thread 0x7fffa3339700 (LWP 26995) exited]
>[New Thread 0x7fffa2824700 (LWP 26996)]
>[Thread 0x7fffa2824700 (LWP 26996) exited]
>[New Thread 0x7fffa3339700 (LWP 26997)]
>[Thread 0x7fffa3339700 (LWP 26997) exited]
>[New Thread 0x7fffa2824700 (LWP 26998)]
>[Thread 0x7fffa2824700 (LWP 26998) exited]
>[New Thread 0x7fffa3339700 (LWP 26999)]
>[Thread 0x7fffa3339700 (LWP 26999) exited]
>[New Thread 0x7fffa2824700 (LWP 27000)]
>[Thread 0x7fffa2824700 (LWP 27000) exited]
>[New Thread 0x7fffa3339700 (LWP 27001)]
>[Thread 0x7fffa3339700 (LWP 27001) exited]
>[New Thread 0x7fffa2824700 (LWP 27002)]
>[Thread 0x7fffa2824700 (LWP 27002) exited]
>[New Thread 0x7fffa3339700 (LWP 27003)]
>[Thread 0x7fffa3339700 (LWP 27003) exited]
>[New Thread 0x7fffa2824700 (LWP 27004)]
>[Thread 0x7fffa2824700 (LWP 27004) exited]
>[New Thread 0x7fffa3339700 (LWP 27005)]
>[Thread 0x7fffa3339700 (LWP 27005) exited]
>[New Thread 0x7fffa2824700 (LWP 27006)]
>[Thread 0x7fffa2824700 (LWP 27006) exited]
>[New Thread 0x7fffa3339700 (LWP 27007)]
>[Thread 0x7fffa3339700 (LWP 27007) exited]
>[New Thread 0x7fffa2824700 (LWP 27008)]
>[Thread 0x7fffa2824700 (LWP 27008) exited]
>[New Thread 0x7fffa3339700 (LWP 27009)]
>[Thread 0x7fffa3339700 (LWP 27009) exited]
>[New Thread 0x7fffa2824700 (LWP 27010)]
>[Thread 0x7fffa2824700 (LWP 27010) exited]
>[New Thread 0x7fffa3339700 (LWP 27011)]
>[Thread 0x7fffa3339700 (LWP 27011) exited]
>[New Thread 0x7fffa2824700 (LWP 27012)]
>[Thread 0x7fffa2824700 (LWP 27012) exited]
>[New Thread 0x7fffa3339700 (LWP 27013)]
>[Thread 0x7fffa3339700 (LWP 27013) exited]
>[New Thread 0x7fffa3339700 (LWP 27014)]
>[Thread 0x7fffa3339700 (LWP 27014) exited]
>[New Thread 0x7fffa3339700 (LWP 27015)]
>[Thread 0x7fffa3339700 (LWP 27015) exited]
>[New Thread 0x7fffa2824700 (LWP 27016)]
>[Thread 0x7fffa2824700 (LWP 27016) exited]
>[New Thread 0x7fffa3339700 (LWP 27017)]
>[Thread 0x7fffa3339700 (LWP 27017) exited]
>[New Thread 0x7fffa2824700 (LWP 27018)]
>[Thread 0x7fffa2824700 (LWP 27018) exited]
>[New Thread 0x7fffa3339700 (LWP 27019)]
>[Thread 0x7fffa3339700 (LWP 27019) exited]
>[New Thread 0x7fffa2824700 (LWP 27020)]
>[Thread 0x7fffa2824700 (LWP 27020) exited]
>[New Thread 0x7fffa3339700 (LWP 27021)]
>[Thread 0x7fffa3339700 (LWP 27021) exited]
>[New Thread 0x7fffa2824700 (LWP 27022)]
>[Thread 0x7fffa2824700 (LWP 27022) exited]
>[New Thread 0x7fffa3339700 (LWP 27023)]
>[Thread 0x7fffa3339700 (LWP 27023) exited]
>[New Thread 0x7fffa2824700 (LWP 27024)]
>[Thread 0x7fffa2824700 (LWP 27024) exited]
>[New Thread 0x7fffa3339700 (LWP 27025)]
>[Thread 0x7fffa3339700 (LWP 27025) exited]
>[New Thread 0x7fffa2824700 (LWP 27026)]
>[Thread 0x7fffa2824700 (LWP 27026) exited]
>[New Thread 0x7fffa3339700 (LWP 27027)]
>[Thread 0x7fffa3339700 (LWP 27027) exited]
>[New Thread 0x7fffa2824700 (LWP 27028)]
>[Thread 0x7fffa2824700 (LWP 27028) exited]
>[New Thread 0x7fffa3339700 (LWP 27029)]
>[Thread 0x7fffa3339700 (LWP 27029) exited]
>[New Thread 0x7fffa2824700 (LWP 27030)]
>[Thread 0x7fffa2824700 (LWP 27030) exited]
>[New Thread 0x7fffa3339700 (LWP 27031)]
>[Thread 0x7fffa3339700 (LWP 27031) exited]
>[New Thread 0x7fffa2824700 (LWP 27032)]
>[Thread 0x7fffa2824700 (LWP 27032) exited]
>[New Thread 0x7fffa3339700 (LWP 27033)]
>[Thread 0x7fffa3339700 (LWP 27033) exited]
>[New Thread 0x7fffa2824700 (LWP 27034)]
>[Thread 0x7fffa2824700 (LWP 27034) exited]
>[New Thread 0x7fffa3339700 (LWP 27035)]
>[Thread 0x7fffa3339700 (LWP 27035) exited]
>[New Thread 0x7fffa2824700 (LWP 27036)]
>[Thread 0x7fffa2824700 (LWP 27036) exited]
>[New Thread 0x7fffa3339700 (LWP 27037)]
>[Thread 0x7fffa3339700 (LWP 27037) exited]
>[New Thread 0x7fffa2824700 (LWP 27038)]
>[Thread 0x7fffa2824700 (LWP 27038) exited]
>[New Thread 0x7fffa3339700 (LWP 27039)]
>[Thread 0x7fffa3339700 (LWP 27039) exited]
>[New Thread 0x7fffa2824700 (LWP 27040)]
>[Thread 0x7fffa2824700 (LWP 27040) exited]
>[New Thread 0x7fffa3339700 (LWP 27041)]
>[Thread 0x7fffa3339700 (LWP 27041) exited]
>[New Thread 0x7fffa2824700 (LWP 27042)]
>[Thread 0x7fffa2824700 (LWP 27042) exited]
>[New Thread 0x7fffa3339700 (LWP 27043)]
>[Thread 0x7fffa3339700 (LWP 27043) exited]
>[New Thread 0x7fffa2824700 (LWP 27044)]
>[Thread 0x7fffa2824700 (LWP 27044) exited]
>[New Thread 0x7fffa3339700 (LWP 27045)]
>[Thread 0x7fffa3339700 (LWP 27045) exited]
>[New Thread 0x7fffa2824700 (LWP 27046)]
>[Thread 0x7fffa2824700 (LWP 27046) exited]
>[New Thread 0x7fffa3339700 (LWP 27047)]
>[Thread 0x7fffa3339700 (LWP 27047) exited]
>[New Thread 0x7fffa2824700 (LWP 27048)]
>[Thread 0x7fffa2824700 (LWP 27048) exited]
>[New Thread 0x7fffa3339700 (LWP 27049)]
>[Thread 0x7fffa3339700 (LWP 27049) exited]
>[New Thread 0x7fffa2824700 (LWP 27050)]
>[Thread 0x7fffa2824700 (LWP 27050) exited]
>[New Thread 0x7fffa3339700 (LWP 27051)]
>[Thread 0x7fffa3339700 (LWP 27051) exited]
>[New Thread 0x7fffa2824700 (LWP 27052)]
>[Thread 0x7fffa2824700 (LWP 27052) exited]
>[New Thread 0x7fffa3339700 (LWP 27053)]
>[Thread 0x7fffa3339700 (LWP 27053) exited]
>[New Thread 0x7fffa2824700 (LWP 27054)]
>[Thread 0x7fffa2824700 (LWP 27054) exited]
>[New Thread 0x7fffa3339700 (LWP 27055)]
>[Thread 0x7fffa3339700 (LWP 27055) exited]
>[New Thread 0x7fffa2824700 (LWP 27056)]
>[Thread 0x7fffa2824700 (LWP 27056) exited]
>[New Thread 0x7fffa3339700 (LWP 27057)]
>[Thread 0x7fffa3339700 (LWP 27057) exited]
>[New Thread 0x7fffa2824700 (LWP 27058)]
>[Thread 0x7fffa2824700 (LWP 27058) exited]
>[New Thread 0x7fffa3339700 (LWP 27059)]
>[Thread 0x7fffa3339700 (LWP 27059) exited]
>[New Thread 0x7fffa2824700 (LWP 27060)]
>[Thread 0x7fffa2824700 (LWP 27060) exited]
>[New Thread 0x7fffa3339700 (LWP 27061)]
>[Thread 0x7fffa3339700 (LWP 27061) exited]
>[New Thread 0x7fffa2824700 (LWP 27062)]
>[Thread 0x7fffa2824700 (LWP 27062) exited]
>[New Thread 0x7fffa3339700 (LWP 27063)]
>[Thread 0x7fffa3339700 (LWP 27063) exited]
>[New Thread 0x7fffa2824700 (LWP 27064)]
>[Thread 0x7fffa2824700 (LWP 27064) exited]
>[New Thread 0x7fffa3339700 (LWP 27065)]
>[Thread 0x7fffa3339700 (LWP 27065) exited]
>[New Thread 0x7fffa2824700 (LWP 27066)]
>[Thread 0x7fffa2824700 (LWP 27066) exited]
>[New Thread 0x7fffa3339700 (LWP 27067)]
>[Thread 0x7fffa3339700 (LWP 27067) exited]
>[New Thread 0x7fffa2824700 (LWP 27068)]
>[Thread 0x7fffa2824700 (LWP 27068) exited]
>[New Thread 0x7fffa3339700 (LWP 27069)]
>[Thread 0x7fffa3339700 (LWP 27069) exited]
>[New Thread 0x7fffa2824700 (LWP 27070)]
>[Thread 0x7fffa2824700 (LWP 27070) exited]
>[New Thread 0x7fffa3339700 (LWP 27071)]
>[Thread 0x7fffa3339700 (LWP 27071) exited]
>[New Thread 0x7fffa2824700 (LWP 27072)]
>[Thread 0x7fffa2824700 (LWP 27072) exited]
>[New Thread 0x7fffa3339700 (LWP 27073)]
>[Thread 0x7fffa3339700 (LWP 27073) exited]
>[New Thread 0x7fffa2824700 (LWP 27074)]
>[Thread 0x7fffa2824700 (LWP 27074) exited]
>[New Thread 0x7fffa3339700 (LWP 27075)]
>[Thread 0x7fffa3339700 (LWP 27075) exited]
>[New Thread 0x7fffa2824700 (LWP 27076)]
>[Thread 0x7fffa2824700 (LWP 27076) exited]
>[New Thread 0x7fffa3339700 (LWP 27077)]
>[Thread 0x7fffa3339700 (LWP 27077) exited]
>[New Thread 0x7fffa2824700 (LWP 27078)]
>[Thread 0x7fffa2824700 (LWP 27078) exited]
>[Thread 0x7fffe2a76f00 (LWP 26646) exited]
>
>Program received signal SIGSEGV, Segmentation fault.
>[Switching to Thread 0x7fffa29e8700 (LWP 26659)]
>memset () at ../sysdeps/x86_64/memset.S:93
>93	../sysdeps/x86_64/memset.S: No such file or directory.
>(gdb) bt
>#0  memset () at ../sysdeps/x86_64/memset.S:93
>#1  0x00007fffe790070e in memset (__len=471424, __ch=0, __dest=0x7fffa2972150) at /usr/include/x86_64-linux-gnu/bits/string3.h:84
>#2  fs_instruction_scheduler::calculate_deps (this=0x7fffa29e53e0) at ../../../../../../../src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp:935
>#3  0x00007fffe79016ba in instruction_scheduler::run (this=this@entry=0x7fffa29e53e0, cfg=0x7ffed30cd538)
>    at ../../../../../../../src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp:1653
>#4  0x00007fffe79018ea in fs_visitor::schedule_instructions (this=this@entry=0x7fffa29e55a0, mode=<optimized out>)
>    at ../../../../../../../src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp:1685
>#5  0x00007fffe78bd9e0 in fs_visitor::allocate_registers (this=this@entry=0x7fffa29e55a0) at ../../../../../../../src/mesa/drivers/dri/i965/brw_fs.cpp:5214
>#6  0x00007fffe78c0542 in fs_visitor::run_cs (this=0x7fffa29e55a0) at ../../../../../../../src/mesa/drivers/dri/i965/brw_fs.cpp:5490
>#7  0x00007fffe78c0666 in brw_compile_cs (compiler=0x4d090e8, log_data=log_data@entry=0x8491338, mem_ctx=mem_ctx@entry=0x7ffee2171278, 
>    key=key@entry=0x7fffa29e71b0, prog_data=prog_data@entry=0x7fffa29e70e0, src_shader=<optimized out>, shader_time_index=-1, 
>    final_assembly_size=0x7fffa29e70d4, error_str=0x7fffa29e70d8) at ../../../../../../../src/mesa/drivers/dri/i965/brw_fs.cpp:5743
>#8  0x00007fffe784ac54 in brw_codegen_cs_prog (brw=brw@entry=0x8491338, prog=prog@entry=0x7fff44135448, cp=cp@entry=0x7ffed27887b0, 
>    key=key@entry=0x7fffa29e71b0) at ../../../../../../../src/mesa/drivers/dri/i965/brw_cs.c:124
>#9  0x00007fffe784b0c3 in brw_cs_precompile (ctx=0x8491338, shader_prog=0x7fff44135448, prog=0x7ffed27887b0)
>    at ../../../../../../../src/mesa/drivers/dri/i965/brw_cs.c:239
>#10 0x00007fffe7852678 in brw_shader_precompile (sh_prog=<optimized out>, ctx=<optimized out>)
>    at ../../../../../../../src/mesa/drivers/dri/i965/brw_link.cpp:66
>#11 brw_link_shader (ctx=0x8491338, shProg=0x0) at ../../../../../../../src/mesa/drivers/dri/i965/brw_link.cpp:260
>#12 0x00007fffe76f0d86 in _mesa_glsl_link_shader (ctx=0x8491338, prog=0x7fff44135448) at ../../../../src/mesa/program/ir_to_mesa.cpp:3040
>#13 0x00007fffe7605d4a in link_program (ctx=0x8491338, program=<optimized out>) at ../../../../src/mesa/main/shaderapi.c:1048
>#14 0x00000000009fe30b in ?? ()
>#15 0x00000000009fbcfc in ?? ()
>#16 0x0000000001108b29 in ?? ()
>#17 0x00000000010fd25a in ?? ()
>#18 0x000000000181254d in ?? ()
>#19 0x00000000012395ec in ?? ()
>#20 0x0000000000ce8ef3 in ?? ()
>#21 0x0000000000ce9135 in ?? ()
>#22 0x000000000137c58d in ?? ()
>#23 0x000000000137c5b7 in ?? ()
>#24 0x0000000000923d69 in ?? ()
>#25 0x0000000000b1dbd7 in ?? ()
>#26 0x00007ffff6ed80a4 in start_thread (arg=0x7fffa29e8700) at pthread_create.c:309
>#27 0x00007ffff53b387d in clone () at ../sysdeps/unix/sysv/linux/x86_64/clone.S:111
>(gdb) bt full
>#0  memset () at ../sysdeps/x86_64/memset.S:93
>No locals.
>#1  0x00007fffe790070e in memset (__len=471424, __ch=0, __dest=0x7fffa2972150) at /usr/include/x86_64-linux-gnu/bits/string3.h:84
>No locals.
>#2  fs_instruction_scheduler::calculate_deps (this=0x7fffa29e53e0) at ../../../../../../../src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp:935
>        last_grf_write = 0x7fffa2972150
>        last_mrf_write = 0x7fffa29720c0
>        last_conditional_mod = {0x0, 0x0}
>        node = <optimized out>
>        last_accumulator_write = 0x0
>        last_fixed_grf_write = 0x0
>        prev = <optimized out>
>#3  0x00007fffe79016ba in instruction_scheduler::run (this=this@entry=0x7fffa29e53e0, cfg=0x7ffed30cd538)
>    at ../../../../../../../src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp:1653
>        block = 0x7ffed3dc28c8
>#4  0x00007fffe79018ea in fs_visitor::schedule_instructions (this=this@entry=0x7fffa29e55a0, mode=<optimized out>)
>    at ../../../../../../../src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp:1685
>        grf_count = 3683
>        sched = {<instruction_scheduler> = {_vptr.instruction_scheduler = 0x7fffe7d03310 <vtable for fs_instruction_scheduler+16>, mem_ctx = 0x7ffef293a348, 
>            post_reg_alloc = false, instructions_to_schedule = 15, grf_count = 3683, hw_reg_count = 5, time = 0, reg_pressure = 0, block_idx = -1566681696, 
>            instructions = {head = 0x7ffed3dd9278, tail = 0x0, tail_pred = 0x7ffed3e207b8}, bs = 0x7fffa29e55a0, mode = SCHEDULE_PRE, 
>            reg_pressure_in = 0x7ffed3df6a48, livein = 0x7ffed3dd9188, liveout = 0x7ffed3e188f8, hw_liveout = 0x7ffed3e1b7e8, written = 0x7ffed3e1b8d8, 
>            reads_remaining = 0x7ffed3e1c778, hw_reads_remaining = 0x7ffed26dc008}, v = 0x7fffa29e55a0}
>#5  0x00007fffe78bd9e0 in fs_visitor::allocate_registers (this=this@entry=0x7fffa29e55a0) at ../../../../../../../src/mesa/drivers/dri/i965/brw_fs.cpp:5214
>        i = <optimized out>
>        allocated_without_spills = false
>        pre_modes = {SCHEDULE_PRE, SCHEDULE_PRE_NON_LIFO, SCHEDULE_PRE_LIFO}
>#6  0x00007fffe78c0542 in fs_visitor::run_cs (this=0x7fffa29e55a0) at ../../../../../../../src/mesa/drivers/dri/i965/brw_fs.cpp:5490
>        this = 0x7fffa29e55a0
>#7  0x00007fffe78c0666 in brw_compile_cs (compiler=0x4d090e8, log_data=log_data@entry=0x8491338, mem_ctx=mem_ctx@entry=0x7ffee2171278, 
>    key=key@entry=0x7fffa29e71b0, prog_data=prog_data@entry=0x7fffa29e70e0, src_shader=<optimized out>, shader_time_index=-1, 
>    final_assembly_size=0x7fffa29e70d4, error_str=0x7fffa29e70d8) at ../../../../../../../src/mesa/drivers/dri/i965/brw_fs.cpp:5743
>        local_workgroup_size = 1024
>        fail_msg = 0x0
>        v8 = {<backend_shader> = {_vptr.backend_shader = 0x7fffe7d17010 <vtable for fs_visitor+16>, compiler = 0x4d090e8, log_data = 0x8491338, 
>            devinfo = 0x7fffe7a26800 <brw_device_info_hsw_gt3>, nir = 0x7ffed31b35d8, stage_prog_data = 0x7fffa29e70e0, mem_ctx = 0x7ffee2171278, 
>            instructions = {head = 0x7fffa29e55e0, tail = 0x0, tail_pred = 0x7fffa29e55d8}, cfg = 0x7ffed30cd538, stage = MESA_SHADER_COMPUTE, 
>            debug_enabled = false, stage_name = 0x7fffe7a119c5 "compute", stage_abbrev = 0x7fffe7a1f99c "CS", alloc = {sizes = 0x7ffed3d88fa0, 
>              offsets = 0x7ffed3d90fb0, count = 3683, total_size = 5371, capacity = 8192}}, key = 0x7fffa29e71b0, key_tex = 0x7fffa29e71b4, 
>          gs_compile = 0x0, prog_data = 0x7fffa29e70e0, prog = 0x0, input_vue_map = 0x0, param_size = 0x7ffed3be8a28, virtual_grf_start = 0x7ffed3dd2018, 
>          virtual_grf_end = 0x7ffed3de3488, live_intervals = 0x7ffed3dd1e18, regs_live_at_ip = 0x0, uniforms = 24, last_scratch = 0, 
>          pull_constant_loc = 0x7ffed3dc3988, push_constant_loc = 0x7ffed3dc3a18, frag_depth = {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                file = BAD_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, 
>                    vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, 
>            stride = 1 '\001'}, frag_stencil = {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BAD_FILE, negate = 0, abs = 0, 
>                address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, 
>                    pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}, 
>          sample_mask = {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BAD_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, 
>                subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, 
>                  ud = 0}}, reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}, outputs = {{<backend_reg> = {<brw_reg> = {
>                  type = BRW_REGISTER_TYPE_UD, file = BAD_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, 
>                      writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 0}, 
>              subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'} <repeats 58 times>}, output_components = {0 <repeats 58 times>}, 
>          dual_src_output = {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BAD_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, 
>                subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, 
>                  ud = 0}}, reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}, do_dual_src = false, first_non_payload_grf = 5, 
>          max_grf = 112, nir_locals = 0x7ffed3d20998, nir_ssa_values = 0x7ffed3d51ad8, nir_inputs = {<backend_reg> = {<brw_reg> = {
>                type = BRW_REGISTER_TYPE_UD, file = BAD_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, 
>                    writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 0}, 
>            subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}, nir_outputs = {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_F, 
>                file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 228, writemask = 15, 
>                    indirect_offset = 0, vstride = 4, width = 3, hstride = 1, pad1 = 0}, f = 7.27948604e-12, d = 754978788, ud = 754978788}}, 
>              reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}, nir_system_values = 0x7ffed3c572e8, failed = false, 
>          fail_msg = 0x150 <error: Cannot access memory at address 0x150>, simd16_unsupported = false, no16_msg = 0x0, 
>          result = {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_F, file = VGRF, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, 
>                nr = 155, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, 
>              reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}, payload = {source_depth_reg = 0 '\000', source_w_reg = 0 '\000', 
>            aa_dest_stencil_reg = 0 '\000', dest_depth_reg = 0 '\000', sample_pos_reg = 0 '\000', sample_mask_in_reg = 0 '\000', 
>            barycentric_coord_reg = "\000\000\000\000\000", local_invocation_id_reg = 1 '\001', num_regs = 4 '\004'}, source_depth_to_render_target = false, 
>          runtime_check_aads_emit = false, pixel_x = {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BAD_FILE, negate = 0, abs = 0, 
>                address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, 
>                    pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}, 
>          pixel_y = {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BAD_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, 
>                nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, 
>              reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}, wpos_w = {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                file = BAD_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, 
>                    vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, 
>            stride = 1 '\001'}, pixel_w = {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BAD_FILE, negate = 0, abs = 0, 
>                address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, 
>                    pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}, delta_xy = {
>            {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BAD_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, 
>                  {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, 
>                reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                  file = BAD_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, 
>                      vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, 
>              stride = 1 '\001'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BAD_FILE, negate = 0, abs = 0, address_mode = 0, 
>                  pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, 
>                    d = 0, ud = 0}}, reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}, {<backend_reg> = {<brw_reg> = {
>                  type = BRW_REGISTER_TYPE_UD, file = BAD_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, 
>                      writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 0}, 
>              subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BAD_FILE, negate = 0, 
>                  abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, 
>                      hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}, 
>            {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BAD_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, 
>                  {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, 
>                reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}}, shader_start_time = {<backend_reg> = {<brw_reg> = {
>                type = BRW_REGISTER_TYPE_UD, file = BAD_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, 
>                    writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 0}, 
>            subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}, userplane = {{<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BAD_FILE, 
>                  negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, 
>                      width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}, 
>            {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BAD_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, 
>                  {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, 
>                reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                  file = BAD_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, 
>                      vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, 
>              stride = 1 '\001'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BAD_FILE, negate = 0, abs = 0, address_mode = 0, 
>                  pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, 
>                    d = 0, ud = 0}}, reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}, {<backend_reg> = {<brw_reg> = {
>                  type = BRW_REGISTER_TYPE_UD, file = BAD_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, 
>                      writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 0}, 
>              subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BAD_FILE, negate = 0, 
>                  abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, 
>                      hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}, 
>            {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BAD_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, 
>                  {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, 
>                reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                  file = BAD_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, 
>                      vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, 
>              stride = 1 '\001'}}, final_gs_vertex_count = {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BAD_FILE, negate = 0, abs = 0, 
>                address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, 
>                    pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}, 
>          control_data_bits = {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BAD_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, 
>                subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, 
>                  ud = 0}}, reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}, grf_used = 3548886616, spilled_any_registers = false, 
>          dispatch_width = 8, min_dispatch_width = 16, shader_time_index = -1, promoted_constants = 43, bld = {shader = 0x7fffa29e55a0, block = 0x0, 
>            cursor = 0x0, _dispatch_width = 64, _group = 0, force_writemask_all = false, annotation = {str = 0x0, ir = 0x0}}}
>        v16 = {<backend_shader> = {_vptr.backend_shader = 0x7fffe7d17130 <vtable for backend_shader+16>, compiler = 0x4d090e8, log_data = 0x0, 
>            devinfo = 0x0, nir = 0x0, stage_prog_data = 0x7ffed387ba58, mem_ctx = 0x0, instructions = {head = 0x0, tail = 0x1, tail_pred = 0x7fffa29e6328}, 
>            cfg = 0x0, stage = MESA_SHADER_VERTEX, debug_enabled = false, stage_name = 0x0, stage_abbrev = 0x7ffed387aa58 "", alloc = {sizes = 0x0, 
>              offsets = 0x0, count = 1, total_size = 0, capacity = 2048}}, key = 0x0, key_tex = 0x0, gs_compile = 0x0, prog_data = 0x7ffed387ab48, 
>          prog = 0x0, input_vue_map = 0x0, param_size = 0x1, virtual_grf_start = 0x7ffed2844838, virtual_grf_end = 0x0, live_intervals = 0x0, 
>          regs_live_at_ip = 0x0, uniforms = 3548884024, last_scratch = 32766, pull_constant_loc = 0x0, push_constant_loc = 0x0, 
>          frag_depth = {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_D, file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, 
>                address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, 
>                    pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, stride = 0 '\000'}, 
>          frag_stencil = {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, 
>                address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, 
>                    pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 44328}, subreg_offset = 32766, reladdr = 0x0, stride = 0 '\000'}, 
>          sample_mask = {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_D, file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, 
>                address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, 
>                    pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}, outputs = {
>            {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BAD_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, 
>                  {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, 
>                reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, stride = 192 '\300'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                  file = BRW_IMMEDIATE_VALUE, negate = 1, abs = 1, address_mode = 1, pad0 = 0, subnr = 13, nr = 41630, {{swizzle = 255, writemask = 15, 
>                      indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59163468e-41, d = 32767, ud = 32767}}, reg_offset = 54120}, 
>              subreg_offset = 32767, reladdr = 0x0, stride = 238 '\356'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_D, 
>                  file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, 
>                      indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 27328}, 
>              subreg_offset = 32767, reladdr = 0x7, stride = 121 'y'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = VGRF, negate = 1, 
>                  abs = 0, address_mode = 1, pad0 = 0, subnr = 13, nr = 41630, {{swizzle = 255, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, 
>                      hstride = 0, pad1 = 0}, f = 4.59163468e-41, d = 32767, ud = 32767}}, reg_offset = 27312}, subreg_offset = 32767, 
>              reladdr = 0x7fffe7a07fa7, stride = 170 '\252'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                  file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, 
>                      indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 20329}, 
>              subreg_offset = 32767, reladdr = 0x0, stride = 1 '\001'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                  file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 1, address_mode = 1, pad0 = 0, subnr = 13, nr = 41630, {{swizzle = 255, 
>                      writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59163468e-41, d = 32767, ud = 32767}}, 
>                reg_offset = 27376}, subreg_offset = 32767, reladdr = 0x0, stride = 0 '\000'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                  file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, 
>                      indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 46680}, 
>              subreg_offset = 32766, reladdr = 0x0, stride = 0 '\000'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_D, 
>                  file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, 
>                      indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 32}, subreg_offset = 32767, 
>              reladdr = 0x1b0, stride = 1 '\001'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = UNIFORM, negate = 0, abs = 1, 
>                  address_mode = 1, pad0 = 1, subnr = 31, nr = 54157, {{swizzle = 254, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, 
>                      hstride = 0, pad1 = 0}, f = 4.59149455e-41, d = 32766, ud = 32766}}, reg_offset = 424}, subreg_offset = 0, reladdr = 0x7fff44000078, 
>              stride = 232 '\350'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_HF, file = BRW_GENERAL_REGISTER_FILE, negate = 0, abs = 0, 
>                  address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, 
>                      pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 464}, subreg_offset = 0, reladdr = 0x6, stride = 54 '6'}, 
>            {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, 
>                  pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, 
>                    d = 0, ud = 0}}, reg_offset = 91}, subreg_offset = 0, reladdr = 0x0, stride = 0 '\000'}, {<backend_reg> = {<brw_reg> = {type = 14, 
>                  file = UNIFORM, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 119, writemask = 0, indirect_offset = 0, 
>                      vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 1.66754517e-43, d = 119, ud = 119}}, reg_offset = 11778}, subreg_offset = 32767, 
>              reladdr = 0x7ffed3bb6168, stride = 128 '\200'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_V, file = UNIFORM, negate = 0, 
>                  abs = 1, address_mode = 0, pad0 = 0, subnr = 12, nr = 54203, {{swizzle = 254, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, 
>                      hstride = 0, pad1 = 0}, f = 4.59149455e-41, d = 32766, ud = 32766}}, reg_offset = 17419}, subreg_offset = 32767, 
>              reladdr = 0x7ffed3bb6168, stride = 128 '\200'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BRW_IMMEDIATE_VALUE, 
>                  negate = 0, abs = 1, address_mode = 0, pad0 = 0, subnr = 12, nr = 54203, {{swizzle = 254, writemask = 15, indirect_offset = 7, 
>                      vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59149455e-41, d = 32766, ud = 32766}}, reg_offset = 15616}, 
>              subreg_offset = 629676489, reladdr = 0x7ffed3bb6168, stride = 120 'x'}, {<backend_reg> = {<brw_reg> = {type = 15, 
>                  file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, 
>                      indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 17128}, 
>              subreg_offset = 32767, reladdr = 0x7fffe77c2ac0 <add_ssa_def_cb>, stride = 104 'h'}, {<backend_reg> = {<brw_reg> = {type = 15, 
>                  file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, 
>                      indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 15616}, 
>              subreg_offset = 629676489, reladdr = 0x7ffed3bb6168, stride = 181 '\265'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                  file = VGRF, negate = 1, abs = 0, address_mode = 1, pad0 = 0, subnr = 5, nr = 59260, {{swizzle = 255, writemask = 15, indirect_offset = 7, 
>                      vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59163468e-41, d = 32767, ud = 32767}}, reg_offset = 29088}, 
>              subreg_offset = 32767, reladdr = 0x7ffed3bb6168, stride = 83 'S'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                  file = BRW_IMMEDIATE_VALUE, negate = 1, abs = 1, address_mode = 1, pad0 = 1, subnr = 12, nr = 41630, {{swizzle = 255, writemask = 15, 
>                      indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59163468e-41, d = 32767, ud = 32767}}, reg_offset = 27816}, 
>              subreg_offset = 32767, reladdr = 0x7fffe7cfd6b8 <replace39_0+24>, stride = 49 '1'}, {<backend_reg> = {<brw_reg> = {
>                  type = BRW_REGISTER_TYPE_UD, file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{
>                      swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, 
>                reg_offset = 4536}, subreg_offset = 32766, reladdr = 0x7fffa29e6890, stride = 123 '{'}, {<backend_reg> = {<brw_reg> = {
>                  type = BRW_REGISTER_TYPE_D, file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{
>                      swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, 
>                reg_offset = 23896}, subreg_offset = 32766, reladdr = 0x7fffa29e6c60, stride = 0 '\000'}, {<backend_reg> = {<brw_reg> = {
>                  type = BRW_REGISTER_TYPE_UD, file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{
>                      swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, 
>                reg_offset = 24264}, subreg_offset = 32766, reladdr = 0x0, stride = 0 '\000'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_D, 
>                  file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, 
>                      indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 23784}, 
>              subreg_offset = 32767, reladdr = 0x0, stride = 1 '\001'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                  file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, 
>                      indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 24504}, 
>              subreg_offset = 32766, reladdr = 0x1, stride = 0 '\000'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_D, 
>                  file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, 
>                      indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 4}, subreg_offset = 0, 
>              reladdr = 0x0, stride = 188 '\274'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_D, file = BRW_ARCHITECTURE_REGISTER_FILE, 
>                  negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, 
>                      width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 336}, subreg_offset = 0, reladdr = 0x4, stride = 2 '\002'}, 
>            {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, 
>                  pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, 
>                    d = 0, ud = 0}}, reg_offset = 91}, subreg_offset = 0, reladdr = 0x1, stride = 0 '\000'}, {<backend_reg> = {<brw_reg> = {type = 14, 
>                  file = UNIFORM, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 119, writemask = 0, indirect_offset = 0, 
>                      vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 1.66754517e-43, d = 119, ud = 119}}, reg_offset = 11778}, subreg_offset = 32767, 
>              reladdr = 0x7ffed3be10f8, stride = 128 '\200'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                  file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 1, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, 
>                      indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 1}, subreg_offset = 0, 
>              reladdr = 0x7fffe7a0f380 <search38_1_1_1_0>, stride = 38 '&'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_V, file = VGRF, 
>                  negate = 0, abs = 1, address_mode = 0, pad0 = 1, subnr = 27, nr = 53880, {{swizzle = 254, writemask = 15, indirect_offset = 7, 
>                      vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59149455e-41, d = 32766, ud = 32766}}, reg_offset = 39280}, 
>              subreg_offset = 32766, reladdr = 0x7ffed2c09970, stride = 88 'X'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                  file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, 
>                      indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 0}, subreg_offset = 0, 
>              reladdr = 0x80, stride = 1 '\001'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BRW_ARCHITECTURE_REGISTER_FILE, 
>                  negate = 1, abs = 1, address_mode = 1, pad0 = 0, subnr = 30, nr = 59296, {{swizzle = 255, writemask = 15, indirect_offset = 7, 
>                      vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59163468e-41, d = 32767, ud = 32767}}, reg_offset = 40742}, 
>              subreg_offset = 32767, reladdr = 0x7ffed278dd48, stride = 144 '\220'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                  file = BRW_GENERAL_REGISTER_FILE, negate = 1, abs = 0, address_mode = 0, pad0 = 1, subnr = 19, nr = 53952, {{swizzle = 254, 
>                      writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59149455e-41, d = 32766, ud = 32766}}, 
>                reg_offset = 40056}, subreg_offset = 32766, reladdr = 0x0, stride = 0 '\000'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                  file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 1, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, 
>                      indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 1}, subreg_offset = 0, 
>              reladdr = 0x7fffe7a0f380 <search38_1_1_1_0>, stride = 38 '&'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_V, file = VGRF, 
>                  negate = 0, abs = 1, address_mode = 0, pad0 = 1, subnr = 27, nr = 53880, {{swizzle = 254, writemask = 15, indirect_offset = 7, 
>                      vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59149455e-41, d = 32766, ud = 32766}}, reg_offset = 40080}, 
>              subreg_offset = 32766, reladdr = 0x7ffed2c09c90, stride = 120 'x'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                  file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, 
>                      indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 0}, subreg_offset = 0, 
>              reladdr = 0x1, stride = 8 '\b'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BRW_ARCHITECTURE_REGISTER_FILE, 
>                  negate = 1, abs = 0, address_mode = 1, pad0 = 0, subnr = 29, nr = 53945, {{swizzle = 254, writemask = 15, indirect_offset = 7, 
>                      vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59149455e-41, d = 32766, ud = 32766}}, reg_offset = 4144}, 
>              subreg_offset = 32766, reladdr = 0x7ffed31d1018, stride = 0 '\000'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                  file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, 
>                      indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 1}, subreg_offset = 0, 
>              reladdr = 0x7fffa29e6b90, stride = 1 '\001'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = VGRF, negate = 1, abs = 0, 
>                  address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, 
>                      pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 1}, subreg_offset = 0, reladdr = 0x7fffe7a0f530 <search10_1_0>, stride = 38 '&'}, 
>            {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_V, file = ATTR, negate = 1, abs = 0, address_mode = 0, pad0 = 0, subnr = 17, nr = 53944, 
>                  {{swizzle = 254, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59149455e-41, d = 32766, 
>                    ud = 32766}}, reg_offset = 28576}, subreg_offset = 32766, reladdr = 0xc0, stride = 1 '\001'}, {<backend_reg> = {<brw_reg> = {
>                  type = BRW_REGISTER_TYPE_UD, file = VGRF, negate = 0, abs = 0, address_mode = 1, pad0 = 1, subnr = 31, nr = 59296, {{swizzle = 255, 
>                      writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59163468e-41, d = 32767, ud = 32767}}, 
>                reg_offset = 40742}, subreg_offset = 32767, reladdr = 0x7ffed2415428, stride = 32 ' '}, {<backend_reg> = {<brw_reg> = {
>                  type = BRW_REGISTER_TYPE_UD, file = UNIFORM, negate = 1, abs = 1, address_mode = 1, pad0 = 1, subnr = 12, nr = 53852, {{swizzle = 254, 
>                      writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59149455e-41, d = 32766, ud = 32766}}, 
>                reg_offset = 37896}, subreg_offset = 32766, reladdr = 0x0, stride = 0 '\000'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                  file = VGRF, negate = 1, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, 
>                      vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 1}, subreg_offset = 0, 
>              reladdr = 0x7fffe7a0fe40 <search11_1_0>, stride = 38 '&'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_V, 
>                  file = BRW_GENERAL_REGISTER_FILE, negate = 0, abs = 1, address_mode = 1, pad0 = 1, subnr = 12, nr = 53852, {{swizzle = 254, 
>                      writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59149455e-41, d = 32766, ud = 32766}}, 
>                reg_offset = 64472}, subreg_offset = 32766, reladdr = 0x7ffed319fbd8, stride = 192 '\300'}, {<backend_reg> = {<brw_reg> = {
>                  type = BRW_REGISTER_TYPE_UD, file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{
>                      swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, 
>                reg_offset = 0}, subreg_offset = 0, reladdr = 0x1, stride = 40 '('}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                  file = UNIFORM, negate = 0, abs = 1, address_mode = 1, pad0 = 0, subnr = 4, nr = 53932, {{swizzle = 254, writemask = 15, 
>                      indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59149455e-41, d = 32766, ud = 32766}}, reg_offset = 55496}, 
>              subreg_offset = 32766, reladdr = 0x7ffed28ad8b0, stride = 0 '\000'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                  file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, 
>                      indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 1}, subreg_offset = 0, 
>              reladdr = 0x7fffa29e6bc0, stride = 1 '\001'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                  file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, 
>                      indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 15616}, 
>              subreg_offset = 629676489, reladdr = 0x7ffed2415428, stride = 0 '\000'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                  file = BRW_IMMEDIATE_VALUE, negate = 1, abs = 0, address_mode = 1, pad0 = 0, subnr = 13, nr = 41630, {{swizzle = 255, writemask = 15, 
>                      indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59163468e-41, d = 32767, ud = 32767}}, reg_offset = 52000}, 
>              subreg_offset = 32767, reladdr = 0x7fffa29e6bc0, stride = 42 '*'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = VGRF, 
>                  negate = 1, abs = 1, address_mode = 1, pad0 = 0, subnr = 13, nr = 41630, {{swizzle = 255, writemask = 15, indirect_offset = 7, 
>                      vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59163468e-41, d = 32767, ud = 32767}}, reg_offset = 1}, subreg_offset = 3, 
>              reladdr = 0x0, stride = 0 '\000'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_V, file = BRW_MESSAGE_REGISTER_FILE, negate = 0, 
>                  abs = 0, address_mode = 0, pad0 = 1, subnr = 10, nr = 53825, {{swizzle = 254, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, 
>                      hstride = 0, pad1 = 0}, f = 4.59149455e-41, d = 32766, ud = 32766}}, reg_offset = 0}, subreg_offset = 0, reladdr = 0x7fffa29e6fd0, 
>              stride = 32 ' '}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = VGRF, negate = 1, abs = 1, address_mode = 1, pad0 = 0, 
>                  subnr = 13, nr = 41630, {{swizzle = 255, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, 
>                    f = 4.59163468e-41, d = 32767, ud = 32767}}, reg_offset = 39978}, subreg_offset = 32767, reladdr = 0x7fffa29e6bc0, stride = 1 '\001'}, 
>            {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_D, file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 1, address_mode = 1, 
>                  pad0 = 0, subnr = 13, nr = 41630, {{swizzle = 255, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, 
>                    f = 4.59163468e-41, d = 32767, ud = 32767}}, reg_offset = 21544}, subreg_offset = 32766, reladdr = 0x7ffed2415428, stride = 232 '\350'}, 
>            {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BRW_MESSAGE_REGISTER_FILE, negate = 1, abs = 0, address_mode = 1, pad0 = 0, 
>                  subnr = 28, nr = 59343, {{swizzle = 255, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, 
>                    f = 4.59163468e-41, d = 32767, ud = 32767}}, reg_offset = 27584}, subreg_offset = 32767, reladdr = 0x7fffe7cf2b48, stride = 163 '\243'}, 
>            {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_V, file = BRW_MESSAGE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 1, 
>                  subnr = 10, nr = 53825, {{swizzle = 254, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, 
>                    f = 4.59149455e-41, d = 32766, ud = 32766}}, reg_offset = 0}, subreg_offset = 0, reladdr = 0x7fffa29e6b80, stride = 32 ' '}, 
>            {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BRW_GENERAL_REGISTER_FILE, negate = 1, abs = 0, address_mode = 0, pad0 = 1, 
>                  subnr = 13, nr = 41630, {{swizzle = 255, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, 
>                    f = 4.59163468e-41, d = 32767, ud = 32767}}, reg_offset = 41002}, subreg_offset = 32767, reladdr = 0x7fffa29e6c90, stride = 1 '\001'}, 
>            {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, 
>                  pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, 
>                    d = 0, ud = 0}}, reg_offset = 15616}, subreg_offset = 629676489, reladdr = 0x7ffed2415428, stride = 0 '\000'}, 
>            {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BRW_MESSAGE_REGISTER_FILE, negate = 1, abs = 0, address_mode = 0, pad0 = 0, 
>                  subnr = 14, nr = 41630, {{swizzle = 255, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, 
>                    f = 4.59163468e-41, d = 32767, ud = 32767}}, reg_offset = 58144}, subreg_offset = 32767, reladdr = 0x7fff00000000, stride = 120 'x'}, 
>            {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BAD_FILE, negate = 1, abs = 0, address_mode = 0, pad0 = 0, subnr = 4, 
>                  nr = 53927, {{swizzle = 254, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59149455e-41, 
>                    d = 32766, ud = 32766}}, reg_offset = 8432}, subreg_offset = 32766, reladdr = 0x7ffed2a720d8, stride = 0 '\000'}}, output_components = {
>            1, 0, 3536052440, 32766, 3536079344, 32766, 3536079408, 32766, 3526009336, 32766, 0, 0, 0, 0, 3527496744, 32766, 3534496608, 32766, 3532314824, 
>            32766, 3532314800, 32766, 0, 0, 0, 0, 1, 0, 0, 0, 3529271064, 32766, 3527496880, 32766, 3535964016, 32766, 3539244040, 32766, 0, 0, 0, 0, 1, 0, 
>            131072, 0, 1, 0, 0, 0, 0, 0, 1, 0, 3536052440, 32766, 3536079344, 32766}, dual_src_output = {<backend_reg> = {<brw_reg> = {
>                type = BRW_REGISTER_TYPE_UD, file = BRW_IMMEDIATE_VALUE, negate = 0, abs = 0, address_mode = 1, pad0 = 0, subnr = 9, nr = 53956, {{
>                    swizzle = 254, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59149455e-41, d = 32766, 
>                  ud = 32766}}, reg_offset = 41464}, subreg_offset = 32766, reladdr = 0x0, stride = 0 '\000'}, do_dual_src = 40, 
>          first_non_payload_grf = 32766, max_grf = 3534496608, nir_locals = 0x7ffed28ad8c8, nir_ssa_values = 0x7ffed28ad8b0, 
>          nir_inputs = {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, 
>                address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, 
>                    pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 0}, subreg_offset = 0, reladdr = 0x1, stride = 0 '\000'}, 
>          nir_outputs = {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_V, file = BRW_GENERAL_REGISTER_FILE, negate = 0, abs = 1, address_mode = 1, 
>                pad0 = 1, subnr = 12, nr = 53852, {{swizzle = 254, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, 
>                  f = 4.59149455e-41, d = 32766, ud = 32766}}, reg_offset = 55696}, subreg_offset = 32766, reladdr = 0x7fffe77e66f5 <dead_cf_list+1221>, 
>            stride = 96 '`'}, nir_system_values = 0x0, failed = 16, fail_msg = 0x7ffed26c4be0 "", simd16_unsupported = false, 
>          no16_msg = 0x7ffed26c4bd8 "\330\062r\322\376\177", result = {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, 
>                    indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 8}, subreg_offset = 0, 
>            reladdr = 0x811e0, stride = 224 '\340'}, payload = {source_depth_reg = 80 'P', source_w_reg = 110 'n', aa_dest_stencil_reg = 158 '\236', 
>            dest_depth_reg = 162 '\242', sample_pos_reg = 255 '\377', sample_mask_in_reg = 127 '\177', barycentric_coord_reg = "\000\000\002\000\000", 
>            local_invocation_id_reg = 0 '\000', num_regs = 0 '\000'}, source_depth_to_render_target = false, runtime_check_aads_emit = false, 
>          pixel_x = {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, 
>                address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, 
>                    pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 8}, subreg_offset = 0, reladdr = 0x7fffa29e6e40, stride = 80 'P'}, 
>          pixel_y = {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BRW_MESSAGE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, 
>                pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, 
>                  d = 0, ud = 0}}, reg_offset = 28240}, subreg_offset = 32767, reladdr = 0x7fffe77cd020 <cmp_phi_src>, stride = 104 'h'}, 
>          wpos_w = {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_V, file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 1, abs = 1, address_mode = 0, 
>                pad0 = 1, subnr = 27, nr = 54039, {{swizzle = 254, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, 
>                  f = 4.59149455e-41, d = 32766, ud = 32766}}, reg_offset = 7601}, subreg_offset = 32767, reladdr = 0x0, stride = 8 '\b'}, 
>          pixel_w = {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BRW_MESSAGE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, 
>                pad0 = 0, subnr = 26, nr = 59260, {{swizzle = 255, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, 
>                  f = 4.59163468e-41, d = 32767, ud = 32767}}, reg_offset = 28256}, subreg_offset = 32767, reladdr = 0x7fffa29e6ed0, stride = 177 '\261'}, 
>          delta_xy = {{<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, 
>                  address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, 
>                      pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 8}, subreg_offset = 0, reladdr = 0x7fffa29e6ec0, stride = 144 '\220'}, 
>            {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 1, address_mode = 1, 
>                  pad0 = 1, subnr = 13, nr = 41630, {{swizzle = 255, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, 
>                    f = 4.59163468e-41, d = 32767, ud = 32767}}, reg_offset = 15616}, subreg_offset = 629676489, reladdr = 0x7ffed26c4b68, 
>              stride = 0 '\000'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, 
>                  address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, 
>                      pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 1}, subreg_offset = 0, reladdr = 0x7ffed26b74e8, stride = 16 '\020'}, 
>            {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_V, file = UNIFORM, negate = 0, abs = 1, address_mode = 1, pad0 = 0, subnr = 9, 
>                  nr = 53868, {{swizzle = 254, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59149455e-41, 
>                    d = 32766, ud = 32766}}, reg_offset = 26357}, subreg_offset = 32767, reladdr = 0x7fffa29e6eb0, stride = 160 '\240'}, 
>            {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = UNIFORM, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 14, 
>                  nr = 41630, {{swizzle = 255, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59163468e-41, 
>                    d = 32767, ud = 32767}}, reg_offset = 54064}, subreg_offset = 32766, reladdr = 0x1000, stride = 40 '('}, {<backend_reg> = {<brw_reg> = {
>                  type = BRW_REGISTER_TYPE_W, file = BRW_MESSAGE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{
>                      swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, 
>                reg_offset = 4}, subreg_offset = 0, reladdr = 0x7b00000091, stride = 0 '\000'}}, shader_start_time = {<backend_reg> = {<brw_reg> = {
>                type = BRW_REGISTER_TYPE_UQ, file = BAD_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, 
>                    writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 8}, 
>            subreg_offset = 0, reladdr = 0x7fffa29e6f80, stride = 32 ' '}, userplane = {{<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                  file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 1, address_mode = 0, pad0 = 1, subnr = 7, nr = 2, {{swizzle = 0, writemask = 0, 
>                      indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 13176}, subreg_offset = 0, 
>              reladdr = 0x7ffed3c18220, stride = 208 '\320'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UB, file = BRW_IMMEDIATE_VALUE, 
>                  negate = 0, abs = 1, address_mode = 1, pad0 = 0, subnr = 4, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, 
>                      width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 31196}, subreg_offset = 32767, reladdr = 0x20, 
>              stride = 24 '\030'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = ATTR, negate = 0, abs = 1, address_mode = 1, pad0 = 0, 
>                  subnr = 6, nr = 2, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, 
>                    ud = 0}}, reg_offset = 40008}, subreg_offset = 32766, reladdr = 0x7ffed322ac18, stride = 200 '\310'}, {<backend_reg> = {<brw_reg> = {
>                  type = BRW_REGISTER_TYPE_UD, file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 1, address_mode = 1, pad0 = 1, subnr = 13, 
>                  nr = 41630, {{swizzle = 255, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59163468e-41, 
>                    d = 32767, ud = 32767}}, reg_offset = 0}, subreg_offset = 0, reladdr = 0x7ffed2886c68, stride = 224 '\340'}, 
>            {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BRW_IMMEDIATE_VALUE, negate = 1, abs = 0, address_mode = 0, pad0 = 0, 
>                  subnr = 12, nr = 53771, {{swizzle = 254, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, 
>                    f = 4.59149455e-41, d = 32766, ud = 32766}}, reg_offset = 21065}, subreg_offset = 32767, reladdr = 0x7fffa29e6fa0, stride = 0 '\000'}, 
>            {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_V, file = BRW_IMMEDIATE_VALUE, negate = 1, abs = 0, address_mode = 1, pad0 = 0, 
>                  subnr = 26, nr = 53849, {{swizzle = 254, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, 
>                    f = 4.59149455e-41, d = 32766, ud = 32766}}, reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}, 
>            {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_V, file = UNIFORM, negate = 1, abs = 1, address_mode = 1, pad0 = 1, subnr = 12, 
>                  nr = 53934, {{swizzle = 254, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59149455e-41, 
>                    d = 32766, ud = 32766}}, reg_offset = 32}, subreg_offset = 32767, reladdr = 0x530, stride = 40 '('}, {<backend_reg> = {<brw_reg> = {
>                  type = BRW_REGISTER_TYPE_UD, file = BRW_MESSAGE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 1, pad0 = 0, subnr = 16, nr = 54209, {{
>                      swizzle = 254, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59149455e-41, d = 32766, 
>                    ud = 32766}}, reg_offset = 1320}, subreg_offset = 0, reladdr = 0x7ffed25c2828, stride = 152 '\230'}}, 
>          final_gs_vertex_count = {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_W, file = ATTR, negate = 0, abs = 0, address_mode = 0, pad0 = 0, 
>                subnr = 0, nr = 0, {{swizzle = 255, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59163468e-41, 
>                  d = 32767, ud = 32767}}, reg_offset = 1360}, subreg_offset = 0, reladdr = 0x14, stride = 68 'D'}, 
>          control_data_bits = {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UW, file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, 
>                address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, 
>                    pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 93}, subreg_offset = 629676489, reladdr = 0x0, stride = 0 '\000'}, grf_used = 110, 
>          spilled_any_registers = 119, dispatch_width = 0, min_dispatch_width = 0, shader_time_index = 124, promoted_constants = 32767, bld = {
>            shader = 0x7fffe77e5000 <constant_fold_block>, block = 0x7fffa29e70d0, cursor = 0x7fff44000020, _dispatch_width = 146912, _group = 0, 
>            force_writemask_all = 119, annotation = {str = 0x7ffed3c18220 "", ir = 0x7ffed2718ae8}}}
>        g = {compiler = 0x0, log_data = 0x0, devinfo = 0x0, p = 0x7ffed2f9f6d8, key = 0x0, prog_data = 0x0, dispatch_width = 1, discard_halt_patches = {
>            head = 0x7fffa29e5570, tail = 0x0, tail_pred = 0x7fffa29e5568}, promoted_constants = 18, runtime_check_aads_emit = false, debug_flag = false, 
>          shader_name = 0x1 <error: Cannot access memory at address 0x1>, stage = MESA_SHADER_COMPUTE, mem_ctx = 0x7ffed5e18c08}
>        shader = 0x7ffed31b35d8
>        max_cs_threads = 70
>        cfg = 0x0
>#8  0x00007fffe784ac54 in brw_codegen_cs_prog (brw=brw@entry=0x8491338, prog=prog@entry=0x7fff44135448, cp=cp@entry=0x7ffed27887b0, 
>    key=key@entry=0x7fffa29e71b0) at ../../../../../../../src/mesa/drivers/dri/i965/brw_cs.c:124
>        ctx = 0x8491338
>        program = <optimized out>
>        mem_ctx = 0x7ffee2171278
>        program_size = 0
>        prog_data = {base = {binding_table = {size_bytes = 24, pull_constants_start = 6, texture_start = 1, gather_texture_start = 3503345872, 
>              ubo_start = 2, ssbo_start = 5, abo_start = 3503345872, image_start = 5, shader_time_start = 3503345872}, nr_params = 1, nr_pull_params = 0, 
>            nr_image_params = 1, curb_read_length = 1, total_scratch = 0, total_shared = 25088, dispatch_grf_start_reg = 4, use_alt_mode = false, 
>            param = 0x7ffed3be1848, pull_param = 0x7ffed3be1d78, image_param = 0x7ffed323d898}, dispatch_grf_start_reg_16 = 0, local_size = {32, 32, 1}, 
>          simd_size = 0, uses_barrier = true, uses_num_work_groups = false, local_invocation_id_regs = 3, binding_table = {work_groups_start = 0}}
>        start_busy = false
>        start_time = 0
>        cs = 0x7ffed25c2828
>        param_count = <optimized out>
>        st_index = <optimized out>
>        error_str = 0x1 <error: Cannot access memory at address 0x1>
>#9  0x00007fffe784b0c3 in brw_cs_precompile (ctx=0x8491338, shader_prog=0x7fff44135448, prog=0x7ffed27887b0)
>    at ../../../../../../../src/mesa/drivers/dri/i965/brw_cs.c:239
>        key = {program_string_id = 548, tex = {swizzles = {1672, 0 <repeats 31 times>}, gl_clamp_mask = {0, 0, 0}, gather_channel_quirk_mask = 0, 
>            compressed_multisample_layout_mask = 0, msaa_16 = 0, gen6_gather_wa = {(unknown: 0) <repeats 32 times>}}}
>        cp = 0x7ffed27887b0
>        old_prog_offset = 0
>        old_prog_data = 0x0
>        success = <optimized out>
>#10 0x00007fffe7852678 in brw_shader_precompile (sh_prog=<optimized out>, ctx=<optimized out>)
>    at ../../../../../../../src/mesa/drivers/dri/i965/brw_link.cpp:66
>        gs = 0x0
>        cs = 0x7ffed25c2828
>        vs = 0x0
>        tcs = 0x0
>        tes = 0x0
>        fs = 0x7fffa2972150
>#11 brw_link_shader (ctx=0x8491338, shProg=0x0) at ../../../../../../../src/mesa/drivers/dri/i965/brw_link.cpp:260
>No locals.
>#12 0x00007fffe76f0d86 in _mesa_glsl_link_shader (ctx=0x8491338, prog=0x7fff44135448) at ../../../../src/mesa/program/ir_to_mesa.cpp:3040
>        i = <optimized out>
>#13 0x00007fffe7605d4a in link_program (ctx=0x8491338, program=<optimized out>) at ../../../../src/mesa/main/shaderapi.c:1048
>        shProg = 0x7fff44135448
>#14 0x00000000009fe30b in ?? ()
>No symbol table info available.
>#15 0x00000000009fbcfc in ?? ()
>No symbol table info available.
>#16 0x0000000001108b29 in ?? ()
>No symbol table info available.
>#17 0x00000000010fd25a in ?? ()
>No symbol table info available.
>#18 0x000000000181254d in ?? ()
>No symbol table info available.
>#19 0x00000000012395ec in ?? ()
>No symbol table info available.
>#20 0x0000000000ce8ef3 in ?? ()
>No symbol table info available.
>#21 0x0000000000ce9135 in ?? ()
>No symbol table info available.
>#22 0x000000000137c58d in ?? ()
>No symbol table info available.
>#23 0x000000000137c5b7 in ?? ()
>No symbol table info available.
>#24 0x0000000000923d69 in ?? ()
>No symbol table info available.
>#25 0x0000000000b1dbd7 in ?? ()
>No symbol table info available.
>#26 0x00007ffff6ed80a4 in start_thread (arg=0x7fffa29e8700) at pthread_create.c:309
>        __res = <optimized out>
>        pd = 0x7fffa29e8700
>        now = <optimized out>
>        unwind_buf = {cancel_jmp_buf = {{jmp_buf = {140735921686272, -7254062393839813134, 1, 140737354125408, 0, 140735921686272, 7253928541436804594, 
>                7254042759281147378}, mask_was_saved = 0}}, priv = {pad = {0x0, 0x0, 0x0, 0x0}, data = {prev = 0x0, cleanup = 0x0, canceltype = 0}}}
>        not_first_call = <optimized out>
>        pagesize_m1 = <optimized out>
>        sp = <optimized out>
>        freesize = <optimized out>
>        __PRETTY_FUNCTION__ = "start_thread"
>#27 0x00007ffff53b387d in clone () at ../sysdeps/unix/sysv/linux/x86_64/clone.S:111
>No locals.
>(gdb) c
>Continuing.
>
>Program received signal SIGSEGV, Segmentation fault.
>memset () at ../sysdeps/x86_64/memset.S:93
>93	in ../sysdeps/x86_64/memset.S
>(gdb) bt
>#0  memset () at ../sysdeps/x86_64/memset.S:93
>#1  0x00007fffe790070e in memset (__len=471424, __ch=0, __dest=0x7fffa2972150) at /usr/include/x86_64-linux-gnu/bits/string3.h:84
>#2  fs_instruction_scheduler::calculate_deps (this=0x7fffa29e53e0) at ../../../../../../../src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp:935
>#3  0x00007fffe79016ba in instruction_scheduler::run (this=this@entry=0x7fffa29e53e0, cfg=0x7ffed30cd538)
>    at ../../../../../../../src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp:1653
>#4  0x00007fffe79018ea in fs_visitor::schedule_instructions (this=this@entry=0x7fffa29e55a0, mode=<optimized out>)
>    at ../../../../../../../src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp:1685
>#5  0x00007fffe78bd9e0 in fs_visitor::allocate_registers (this=this@entry=0x7fffa29e55a0) at ../../../../../../../src/mesa/drivers/dri/i965/brw_fs.cpp:5214
>#6  0x00007fffe78c0542 in fs_visitor::run_cs (this=0x7fffa29e55a0) at ../../../../../../../src/mesa/drivers/dri/i965/brw_fs.cpp:5490
>#7  0x00007fffe78c0666 in brw_compile_cs (compiler=0x4d090e8, log_data=log_data@entry=0x8491338, mem_ctx=mem_ctx@entry=0x7ffee2171278, 
>    key=key@entry=0x7fffa29e71b0, prog_data=prog_data@entry=0x7fffa29e70e0, src_shader=<optimized out>, shader_time_index=-1, 
>    final_assembly_size=0x7fffa29e70d4, error_str=0x7fffa29e70d8) at ../../../../../../../src/mesa/drivers/dri/i965/brw_fs.cpp:5743
>#8  0x00007fffe784ac54 in brw_codegen_cs_prog (brw=brw@entry=0x8491338, prog=prog@entry=0x7fff44135448, cp=cp@entry=0x7ffed27887b0, 
>    key=key@entry=0x7fffa29e71b0) at ../../../../../../../src/mesa/drivers/dri/i965/brw_cs.c:124
>#9  0x00007fffe784b0c3 in brw_cs_precompile (ctx=0x8491338, shader_prog=0x7fff44135448, prog=0x7ffed27887b0)
>    at ../../../../../../../src/mesa/drivers/dri/i965/brw_cs.c:239
>#10 0x00007fffe7852678 in brw_shader_precompile (sh_prog=<optimized out>, ctx=<optimized out>)
>    at ../../../../../../../src/mesa/drivers/dri/i965/brw_link.cpp:66
>#11 brw_link_shader (ctx=0x8491338, shProg=0x0) at ../../../../../../../src/mesa/drivers/dri/i965/brw_link.cpp:260
>#12 0x00007fffe76f0d86 in _mesa_glsl_link_shader (ctx=0x8491338, prog=0x7fff44135448) at ../../../../src/mesa/program/ir_to_mesa.cpp:3040
>#13 0x00007fffe7605d4a in link_program (ctx=0x8491338, program=<optimized out>) at ../../../../src/mesa/main/shaderapi.c:1048
>#14 0x00000000009fe30b in ?? ()
>#15 0x00000000009fbcfc in ?? ()
>#16 0x0000000001108b29 in ?? ()
>#17 0x00000000010fd25a in ?? ()
>#18 0x000000000181254d in ?? ()
>#19 0x00000000012395ec in ?? ()
>#20 0x0000000000ce8ef3 in ?? ()
>#21 0x0000000000ce9135 in ?? ()
>#22 0x000000000137c58d in ?? ()
>#23 0x000000000137c5b7 in ?? ()
>#24 0x0000000000923d69 in ?? ()
>#25 0x0000000000b1dbd7 in ?? ()
>#26 0x00007ffff6ed80a4 in start_thread (arg=0x7fffa29e8700) at pthread_create.c:309
>#27 0x00007ffff53b387d in clone () at ../sysdeps/unix/sysv/linux/x86_64/clone.S:111
>(gdb) bt full
>#0  memset () at ../sysdeps/x86_64/memset.S:93
>No locals.
>#1  0x00007fffe790070e in memset (__len=471424, __ch=0, __dest=0x7fffa2972150) at /usr/include/x86_64-linux-gnu/bits/string3.h:84
>No locals.
>#2  fs_instruction_scheduler::calculate_deps (this=0x7fffa29e53e0) at ../../../../../../../src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp:935
>        last_grf_write = 0x7fffa2972150
>        last_mrf_write = 0x7fffa29720c0
>        last_conditional_mod = {0x0, 0x0}
>        node = <optimized out>
>        last_accumulator_write = 0x0
>        last_fixed_grf_write = 0x0
>        prev = <optimized out>
>#3  0x00007fffe79016ba in instruction_scheduler::run (this=this@entry=0x7fffa29e53e0, cfg=0x7ffed30cd538)
>    at ../../../../../../../src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp:1653
>        block = 0x7ffed3dc28c8
>#4  0x00007fffe79018ea in fs_visitor::schedule_instructions (this=this@entry=0x7fffa29e55a0, mode=<optimized out>)
>    at ../../../../../../../src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp:1685
>        grf_count = 3683
>        sched = {<instruction_scheduler> = {_vptr.instruction_scheduler = 0x7fffe7d03310 <vtable for fs_instruction_scheduler+16>, mem_ctx = 0x7ffef293a348, 
>            post_reg_alloc = false, instructions_to_schedule = 15, grf_count = 3683, hw_reg_count = 5, time = 0, reg_pressure = 0, block_idx = -1566681696, 
>            instructions = {head = 0x7ffed3dd9278, tail = 0x0, tail_pred = 0x7ffed3e207b8}, bs = 0x7fffa29e55a0, mode = SCHEDULE_PRE, 
>            reg_pressure_in = 0x7ffed3df6a48, livein = 0x7ffed3dd9188, liveout = 0x7ffed3e188f8, hw_liveout = 0x7ffed3e1b7e8, written = 0x7ffed3e1b8d8, 
>            reads_remaining = 0x7ffed3e1c778, hw_reads_remaining = 0x7ffed26dc008}, v = 0x7fffa29e55a0}
>#5  0x00007fffe78bd9e0 in fs_visitor::allocate_registers (this=this@entry=0x7fffa29e55a0) at ../../../../../../../src/mesa/drivers/dri/i965/brw_fs.cpp:5214
>        i = <optimized out>
>        allocated_without_spills = false
>        pre_modes = {SCHEDULE_PRE, SCHEDULE_PRE_NON_LIFO, SCHEDULE_PRE_LIFO}
>#6  0x00007fffe78c0542 in fs_visitor::run_cs (this=0x7fffa29e55a0) at ../../../../../../../src/mesa/drivers/dri/i965/brw_fs.cpp:5490
>        this = 0x7fffa29e55a0
>#7  0x00007fffe78c0666 in brw_compile_cs (compiler=0x4d090e8, log_data=log_data@entry=0x8491338, mem_ctx=mem_ctx@entry=0x7ffee2171278, 
>    key=key@entry=0x7fffa29e71b0, prog_data=prog_data@entry=0x7fffa29e70e0, src_shader=<optimized out>, shader_time_index=-1, 
>    final_assembly_size=0x7fffa29e70d4, error_str=0x7fffa29e70d8) at ../../../../../../../src/mesa/drivers/dri/i965/brw_fs.cpp:5743
>        local_workgroup_size = 1024
>        fail_msg = 0x0
>        v8 = {<backend_shader> = {_vptr.backend_shader = 0x7fffe7d17010 <vtable for fs_visitor+16>, compiler = 0x4d090e8, log_data = 0x8491338, 
>            devinfo = 0x7fffe7a26800 <brw_device_info_hsw_gt3>, nir = 0x7ffed31b35d8, stage_prog_data = 0x7fffa29e70e0, mem_ctx = 0x7ffee2171278, 
>            instructions = {head = 0x7fffa29e55e0, tail = 0x0, tail_pred = 0x7fffa29e55d8}, cfg = 0x7ffed30cd538, stage = MESA_SHADER_COMPUTE, 
>            debug_enabled = false, stage_name = 0x7fffe7a119c5 "compute", stage_abbrev = 0x7fffe7a1f99c "CS", alloc = {sizes = 0x7ffed3d88fa0, 
>              offsets = 0x7ffed3d90fb0, count = 3683, total_size = 5371, capacity = 8192}}, key = 0x7fffa29e71b0, key_tex = 0x7fffa29e71b4, 
>          gs_compile = 0x0, prog_data = 0x7fffa29e70e0, prog = 0x0, input_vue_map = 0x0, param_size = 0x7ffed3be8a28, virtual_grf_start = 0x7ffed3dd2018, 
>          virtual_grf_end = 0x7ffed3de3488, live_intervals = 0x7ffed3dd1e18, regs_live_at_ip = 0x0, uniforms = 24, last_scratch = 0, 
>          pull_constant_loc = 0x7ffed3dc3988, push_constant_loc = 0x7ffed3dc3a18, frag_depth = {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                file = BAD_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, 
>                    vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, 
>            stride = 1 '\001'}, frag_stencil = {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BAD_FILE, negate = 0, abs = 0, 
>                address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, 
>                    pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}, 
>          sample_mask = {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BAD_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, 
>                subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, 
>                  ud = 0}}, reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}, outputs = {{<backend_reg> = {<brw_reg> = {
>                  type = BRW_REGISTER_TYPE_UD, file = BAD_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, 
>                      writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 0}, 
>              subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'} <repeats 58 times>}, output_components = {0 <repeats 58 times>}, 
>          dual_src_output = {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BAD_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, 
>                subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, 
>                  ud = 0}}, reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}, do_dual_src = false, first_non_payload_grf = 5, 
>          max_grf = 112, nir_locals = 0x7ffed3d20998, nir_ssa_values = 0x7ffed3d51ad8, nir_inputs = {<backend_reg> = {<brw_reg> = {
>                type = BRW_REGISTER_TYPE_UD, file = BAD_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, 
>                    writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 0}, 
>            subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}, nir_outputs = {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_F, 
>                file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 228, writemask = 15, 
>                    indirect_offset = 0, vstride = 4, width = 3, hstride = 1, pad1 = 0}, f = 7.27948604e-12, d = 754978788, ud = 754978788}}, 
>              reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}, nir_system_values = 0x7ffed3c572e8, failed = false, 
>          fail_msg = 0x150 <error: Cannot access memory at address 0x150>, simd16_unsupported = false, no16_msg = 0x0, 
>          result = {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_F, file = VGRF, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, 
>                nr = 155, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, 
>              reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}, payload = {source_depth_reg = 0 '\000', source_w_reg = 0 '\000', 
>            aa_dest_stencil_reg = 0 '\000', dest_depth_reg = 0 '\000', sample_pos_reg = 0 '\000', sample_mask_in_reg = 0 '\000', 
>            barycentric_coord_reg = "\000\000\000\000\000", local_invocation_id_reg = 1 '\001', num_regs = 4 '\004'}, source_depth_to_render_target = false, 
>          runtime_check_aads_emit = false, pixel_x = {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BAD_FILE, negate = 0, abs = 0, 
>                address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, 
>                    pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}, 
>          pixel_y = {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BAD_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, 
>                nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, 
>              reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}, wpos_w = {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                file = BAD_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, 
>                    vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, 
>            stride = 1 '\001'}, pixel_w = {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BAD_FILE, negate = 0, abs = 0, 
>                address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, 
>                    pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}, delta_xy = {
>            {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BAD_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, 
>                  {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, 
>                reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                  file = BAD_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, 
>                      vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, 
>              stride = 1 '\001'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BAD_FILE, negate = 0, abs = 0, address_mode = 0, 
>                  pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, 
>                    d = 0, ud = 0}}, reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}, {<backend_reg> = {<brw_reg> = {
>                  type = BRW_REGISTER_TYPE_UD, file = BAD_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, 
>                      writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 0}, 
>              subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BAD_FILE, negate = 0, 
>                  abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, 
>                      hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}, 
>            {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BAD_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, 
>                  {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, 
>                reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}}, shader_start_time = {<backend_reg> = {<brw_reg> = {
>                type = BRW_REGISTER_TYPE_UD, file = BAD_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, 
>                    writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 0}, 
>            subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}, userplane = {{<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BAD_FILE, 
>                  negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, 
>                      width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}, 
>            {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BAD_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, 
>                  {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, 
>                reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                  file = BAD_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, 
>                      vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, 
>              stride = 1 '\001'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BAD_FILE, negate = 0, abs = 0, address_mode = 0, 
>                  pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, 
>                    d = 0, ud = 0}}, reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}, {<backend_reg> = {<brw_reg> = {
>                  type = BRW_REGISTER_TYPE_UD, file = BAD_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, 
>                      writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 0}, 
>              subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BAD_FILE, negate = 0, 
>                  abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, 
>                      hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}, 
>            {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BAD_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, 
>                  {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, 
>                reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                  file = BAD_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, 
>                      vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, 
>              stride = 1 '\001'}}, final_gs_vertex_count = {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BAD_FILE, negate = 0, abs = 0, 
>                address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, 
>                    pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}, 
>          control_data_bits = {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BAD_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, 
>                subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, 
>                  ud = 0}}, reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}, grf_used = 3548886616, spilled_any_registers = false, 
>          dispatch_width = 8, min_dispatch_width = 16, shader_time_index = -1, promoted_constants = 43, bld = {shader = 0x7fffa29e55a0, block = 0x0, 
>            cursor = 0x0, _dispatch_width = 64, _group = 0, force_writemask_all = false, annotation = {str = 0x0, ir = 0x0}}}
>        v16 = {<backend_shader> = {_vptr.backend_shader = 0x7fffe7d17130 <vtable for backend_shader+16>, compiler = 0x4d090e8, log_data = 0x0, 
>            devinfo = 0x0, nir = 0x0, stage_prog_data = 0x7ffed387ba58, mem_ctx = 0x0, instructions = {head = 0x0, tail = 0x1, tail_pred = 0x7fffa29e6328}, 
>            cfg = 0x0, stage = MESA_SHADER_VERTEX, debug_enabled = false, stage_name = 0x0, stage_abbrev = 0x7ffed387aa58 "", alloc = {sizes = 0x0, 
>              offsets = 0x0, count = 1, total_size = 0, capacity = 2048}}, key = 0x0, key_tex = 0x0, gs_compile = 0x0, prog_data = 0x7ffed387ab48, 
>          prog = 0x0, input_vue_map = 0x0, param_size = 0x1, virtual_grf_start = 0x7ffed2844838, virtual_grf_end = 0x0, live_intervals = 0x0, 
>          regs_live_at_ip = 0x0, uniforms = 3548884024, last_scratch = 32766, pull_constant_loc = 0x0, push_constant_loc = 0x0, 
>          frag_depth = {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_D, file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, 
>                address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, 
>                    pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, stride = 0 '\000'}, 
>          frag_stencil = {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, 
>                address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, 
>                    pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 44328}, subreg_offset = 32766, reladdr = 0x0, stride = 0 '\000'}, 
>          sample_mask = {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_D, file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, 
>                address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, 
>                    pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}, outputs = {
>            {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BAD_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, 
>                  {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, 
>                reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, stride = 192 '\300'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                  file = BRW_IMMEDIATE_VALUE, negate = 1, abs = 1, address_mode = 1, pad0 = 0, subnr = 13, nr = 41630, {{swizzle = 255, writemask = 15, 
>                      indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59163468e-41, d = 32767, ud = 32767}}, reg_offset = 54120}, 
>              subreg_offset = 32767, reladdr = 0x0, stride = 238 '\356'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_D, 
>                  file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, 
>                      indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 27328}, 
>              subreg_offset = 32767, reladdr = 0x7, stride = 121 'y'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = VGRF, negate = 1, 
>                  abs = 0, address_mode = 1, pad0 = 0, subnr = 13, nr = 41630, {{swizzle = 255, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, 
>                      hstride = 0, pad1 = 0}, f = 4.59163468e-41, d = 32767, ud = 32767}}, reg_offset = 27312}, subreg_offset = 32767, 
>              reladdr = 0x7fffe7a07fa7, stride = 170 '\252'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                  file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, 
>                      indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 20329}, 
>              subreg_offset = 32767, reladdr = 0x0, stride = 1 '\001'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                  file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 1, address_mode = 1, pad0 = 0, subnr = 13, nr = 41630, {{swizzle = 255, 
>                      writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59163468e-41, d = 32767, ud = 32767}}, 
>                reg_offset = 27376}, subreg_offset = 32767, reladdr = 0x0, stride = 0 '\000'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                  file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, 
>                      indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 46680}, 
>              subreg_offset = 32766, reladdr = 0x0, stride = 0 '\000'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_D, 
>                  file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, 
>                      indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 32}, subreg_offset = 32767, 
>              reladdr = 0x1b0, stride = 1 '\001'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = UNIFORM, negate = 0, abs = 1, 
>                  address_mode = 1, pad0 = 1, subnr = 31, nr = 54157, {{swizzle = 254, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, 
>                      hstride = 0, pad1 = 0}, f = 4.59149455e-41, d = 32766, ud = 32766}}, reg_offset = 424}, subreg_offset = 0, reladdr = 0x7fff44000078, 
>              stride = 232 '\350'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_HF, file = BRW_GENERAL_REGISTER_FILE, negate = 0, abs = 0, 
>                  address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, 
>                      pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 464}, subreg_offset = 0, reladdr = 0x6, stride = 54 '6'}, 
>            {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, 
>                  pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, 
>                    d = 0, ud = 0}}, reg_offset = 91}, subreg_offset = 0, reladdr = 0x0, stride = 0 '\000'}, {<backend_reg> = {<brw_reg> = {type = 14, 
>                  file = UNIFORM, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 119, writemask = 0, indirect_offset = 0, 
>                      vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 1.66754517e-43, d = 119, ud = 119}}, reg_offset = 11778}, subreg_offset = 32767, 
>              reladdr = 0x7ffed3bb6168, stride = 128 '\200'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_V, file = UNIFORM, negate = 0, 
>                  abs = 1, address_mode = 0, pad0 = 0, subnr = 12, nr = 54203, {{swizzle = 254, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, 
>                      hstride = 0, pad1 = 0}, f = 4.59149455e-41, d = 32766, ud = 32766}}, reg_offset = 17419}, subreg_offset = 32767, 
>              reladdr = 0x7ffed3bb6168, stride = 128 '\200'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BRW_IMMEDIATE_VALUE, 
>                  negate = 0, abs = 1, address_mode = 0, pad0 = 0, subnr = 12, nr = 54203, {{swizzle = 254, writemask = 15, indirect_offset = 7, 
>                      vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59149455e-41, d = 32766, ud = 32766}}, reg_offset = 15616}, 
>              subreg_offset = 629676489, reladdr = 0x7ffed3bb6168, stride = 120 'x'}, {<backend_reg> = {<brw_reg> = {type = 15, 
>                  file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, 
>                      indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 17128}, 
>              subreg_offset = 32767, reladdr = 0x7fffe77c2ac0 <add_ssa_def_cb>, stride = 104 'h'}, {<backend_reg> = {<brw_reg> = {type = 15, 
>                  file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, 
>                      indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 15616}, 
>              subreg_offset = 629676489, reladdr = 0x7ffed3bb6168, stride = 181 '\265'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                  file = VGRF, negate = 1, abs = 0, address_mode = 1, pad0 = 0, subnr = 5, nr = 59260, {{swizzle = 255, writemask = 15, indirect_offset = 7, 
>                      vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59163468e-41, d = 32767, ud = 32767}}, reg_offset = 29088}, 
>              subreg_offset = 32767, reladdr = 0x7ffed3bb6168, stride = 83 'S'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                  file = BRW_IMMEDIATE_VALUE, negate = 1, abs = 1, address_mode = 1, pad0 = 1, subnr = 12, nr = 41630, {{swizzle = 255, writemask = 15, 
>                      indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59163468e-41, d = 32767, ud = 32767}}, reg_offset = 27816}, 
>              subreg_offset = 32767, reladdr = 0x7fffe7cfd6b8 <replace39_0+24>, stride = 49 '1'}, {<backend_reg> = {<brw_reg> = {
>                  type = BRW_REGISTER_TYPE_UD, file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{
>                      swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, 
>                reg_offset = 4536}, subreg_offset = 32766, reladdr = 0x7fffa29e6890, stride = 123 '{'}, {<backend_reg> = {<brw_reg> = {
>                  type = BRW_REGISTER_TYPE_D, file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{
>                      swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, 
>                reg_offset = 23896}, subreg_offset = 32766, reladdr = 0x7fffa29e6c60, stride = 0 '\000'}, {<backend_reg> = {<brw_reg> = {
>                  type = BRW_REGISTER_TYPE_UD, file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{
>                      swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, 
>                reg_offset = 24264}, subreg_offset = 32766, reladdr = 0x0, stride = 0 '\000'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_D, 
>                  file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, 
>                      indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 23784}, 
>              subreg_offset = 32767, reladdr = 0x0, stride = 1 '\001'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                  file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, 
>                      indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 24504}, 
>              subreg_offset = 32766, reladdr = 0x1, stride = 0 '\000'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_D, 
>                  file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, 
>                      indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 4}, subreg_offset = 0, 
>              reladdr = 0x0, stride = 188 '\274'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_D, file = BRW_ARCHITECTURE_REGISTER_FILE, 
>                  negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, 
>                      width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 336}, subreg_offset = 0, reladdr = 0x4, stride = 2 '\002'}, 
>            {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, 
>                  pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, 
>                    d = 0, ud = 0}}, reg_offset = 91}, subreg_offset = 0, reladdr = 0x1, stride = 0 '\000'}, {<backend_reg> = {<brw_reg> = {type = 14, 
>                  file = UNIFORM, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 119, writemask = 0, indirect_offset = 0, 
>                      vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 1.66754517e-43, d = 119, ud = 119}}, reg_offset = 11778}, subreg_offset = 32767, 
>              reladdr = 0x7ffed3be10f8, stride = 128 '\200'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                  file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 1, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, 
>                      indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 1}, subreg_offset = 0, 
>              reladdr = 0x7fffe7a0f380 <search38_1_1_1_0>, stride = 38 '&'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_V, file = VGRF, 
>                  negate = 0, abs = 1, address_mode = 0, pad0 = 1, subnr = 27, nr = 53880, {{swizzle = 254, writemask = 15, indirect_offset = 7, 
>                      vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59149455e-41, d = 32766, ud = 32766}}, reg_offset = 39280}, 
>              subreg_offset = 32766, reladdr = 0x7ffed2c09970, stride = 88 'X'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                  file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, 
>                      indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 0}, subreg_offset = 0, 
>              reladdr = 0x80, stride = 1 '\001'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BRW_ARCHITECTURE_REGISTER_FILE, 
>                  negate = 1, abs = 1, address_mode = 1, pad0 = 0, subnr = 30, nr = 59296, {{swizzle = 255, writemask = 15, indirect_offset = 7, 
>                      vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59163468e-41, d = 32767, ud = 32767}}, reg_offset = 40742}, 
>              subreg_offset = 32767, reladdr = 0x7ffed278dd48, stride = 144 '\220'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                  file = BRW_GENERAL_REGISTER_FILE, negate = 1, abs = 0, address_mode = 0, pad0 = 1, subnr = 19, nr = 53952, {{swizzle = 254, 
>                      writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59149455e-41, d = 32766, ud = 32766}}, 
>                reg_offset = 40056}, subreg_offset = 32766, reladdr = 0x0, stride = 0 '\000'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                  file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 1, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, 
>                      indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 1}, subreg_offset = 0, 
>              reladdr = 0x7fffe7a0f380 <search38_1_1_1_0>, stride = 38 '&'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_V, file = VGRF, 
>                  negate = 0, abs = 1, address_mode = 0, pad0 = 1, subnr = 27, nr = 53880, {{swizzle = 254, writemask = 15, indirect_offset = 7, 
>                      vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59149455e-41, d = 32766, ud = 32766}}, reg_offset = 40080}, 
>              subreg_offset = 32766, reladdr = 0x7ffed2c09c90, stride = 120 'x'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                  file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, 
>                      indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 0}, subreg_offset = 0, 
>              reladdr = 0x1, stride = 8 '\b'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BRW_ARCHITECTURE_REGISTER_FILE, 
>                  negate = 1, abs = 0, address_mode = 1, pad0 = 0, subnr = 29, nr = 53945, {{swizzle = 254, writemask = 15, indirect_offset = 7, 
>                      vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59149455e-41, d = 32766, ud = 32766}}, reg_offset = 4144}, 
>              subreg_offset = 32766, reladdr = 0x7ffed31d1018, stride = 0 '\000'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                  file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, 
>                      indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 1}, subreg_offset = 0, 
>              reladdr = 0x7fffa29e6b90, stride = 1 '\001'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = VGRF, negate = 1, abs = 0, 
>                  address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, 
>                      pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 1}, subreg_offset = 0, reladdr = 0x7fffe7a0f530 <search10_1_0>, stride = 38 '&'}, 
>            {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_V, file = ATTR, negate = 1, abs = 0, address_mode = 0, pad0 = 0, subnr = 17, nr = 53944, 
>                  {{swizzle = 254, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59149455e-41, d = 32766, 
>                    ud = 32766}}, reg_offset = 28576}, subreg_offset = 32766, reladdr = 0xc0, stride = 1 '\001'}, {<backend_reg> = {<brw_reg> = {
>                  type = BRW_REGISTER_TYPE_UD, file = VGRF, negate = 0, abs = 0, address_mode = 1, pad0 = 1, subnr = 31, nr = 59296, {{swizzle = 255, 
>                      writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59163468e-41, d = 32767, ud = 32767}}, 
>                reg_offset = 40742}, subreg_offset = 32767, reladdr = 0x7ffed2415428, stride = 32 ' '}, {<backend_reg> = {<brw_reg> = {
>                  type = BRW_REGISTER_TYPE_UD, file = UNIFORM, negate = 1, abs = 1, address_mode = 1, pad0 = 1, subnr = 12, nr = 53852, {{swizzle = 254, 
>                      writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59149455e-41, d = 32766, ud = 32766}}, 
>                reg_offset = 37896}, subreg_offset = 32766, reladdr = 0x0, stride = 0 '\000'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                  file = VGRF, negate = 1, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, 
>                      vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 1}, subreg_offset = 0, 
>              reladdr = 0x7fffe7a0fe40 <search11_1_0>, stride = 38 '&'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_V, 
>                  file = BRW_GENERAL_REGISTER_FILE, negate = 0, abs = 1, address_mode = 1, pad0 = 1, subnr = 12, nr = 53852, {{swizzle = 254, 
>                      writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59149455e-41, d = 32766, ud = 32766}}, 
>                reg_offset = 64472}, subreg_offset = 32766, reladdr = 0x7ffed319fbd8, stride = 192 '\300'}, {<backend_reg> = {<brw_reg> = {
>                  type = BRW_REGISTER_TYPE_UD, file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{
>                      swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, 
>                reg_offset = 0}, subreg_offset = 0, reladdr = 0x1, stride = 40 '('}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                  file = UNIFORM, negate = 0, abs = 1, address_mode = 1, pad0 = 0, subnr = 4, nr = 53932, {{swizzle = 254, writemask = 15, 
>                      indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59149455e-41, d = 32766, ud = 32766}}, reg_offset = 55496}, 
>              subreg_offset = 32766, reladdr = 0x7ffed28ad8b0, stride = 0 '\000'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                  file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, 
>                      indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 1}, subreg_offset = 0, 
>              reladdr = 0x7fffa29e6bc0, stride = 1 '\001'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                  file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, 
>                      indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 15616}, 
>              subreg_offset = 629676489, reladdr = 0x7ffed2415428, stride = 0 '\000'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                  file = BRW_IMMEDIATE_VALUE, negate = 1, abs = 0, address_mode = 1, pad0 = 0, subnr = 13, nr = 41630, {{swizzle = 255, writemask = 15, 
>                      indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59163468e-41, d = 32767, ud = 32767}}, reg_offset = 52000}, 
>              subreg_offset = 32767, reladdr = 0x7fffa29e6bc0, stride = 42 '*'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = VGRF, 
>                  negate = 1, abs = 1, address_mode = 1, pad0 = 0, subnr = 13, nr = 41630, {{swizzle = 255, writemask = 15, indirect_offset = 7, 
>                      vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59163468e-41, d = 32767, ud = 32767}}, reg_offset = 1}, subreg_offset = 3, 
>              reladdr = 0x0, stride = 0 '\000'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_V, file = BRW_MESSAGE_REGISTER_FILE, negate = 0, 
>                  abs = 0, address_mode = 0, pad0 = 1, subnr = 10, nr = 53825, {{swizzle = 254, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, 
>                      hstride = 0, pad1 = 0}, f = 4.59149455e-41, d = 32766, ud = 32766}}, reg_offset = 0}, subreg_offset = 0, reladdr = 0x7fffa29e6fd0, 
>              stride = 32 ' '}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = VGRF, negate = 1, abs = 1, address_mode = 1, pad0 = 0, 
>                  subnr = 13, nr = 41630, {{swizzle = 255, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, 
>                    f = 4.59163468e-41, d = 32767, ud = 32767}}, reg_offset = 39978}, subreg_offset = 32767, reladdr = 0x7fffa29e6bc0, stride = 1 '\001'}, 
>            {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_D, file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 1, address_mode = 1, 
>                  pad0 = 0, subnr = 13, nr = 41630, {{swizzle = 255, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, 
>                    f = 4.59163468e-41, d = 32767, ud = 32767}}, reg_offset = 21544}, subreg_offset = 32766, reladdr = 0x7ffed2415428, stride = 232 '\350'}, 
>            {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BRW_MESSAGE_REGISTER_FILE, negate = 1, abs = 0, address_mode = 1, pad0 = 0, 
>                  subnr = 28, nr = 59343, {{swizzle = 255, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, 
>                    f = 4.59163468e-41, d = 32767, ud = 32767}}, reg_offset = 27584}, subreg_offset = 32767, reladdr = 0x7fffe7cf2b48, stride = 163 '\243'}, 
>            {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_V, file = BRW_MESSAGE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 1, 
>                  subnr = 10, nr = 53825, {{swizzle = 254, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, 
>                    f = 4.59149455e-41, d = 32766, ud = 32766}}, reg_offset = 0}, subreg_offset = 0, reladdr = 0x7fffa29e6b80, stride = 32 ' '}, 
>            {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BRW_GENERAL_REGISTER_FILE, negate = 1, abs = 0, address_mode = 0, pad0 = 1, 
>                  subnr = 13, nr = 41630, {{swizzle = 255, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, 
>                    f = 4.59163468e-41, d = 32767, ud = 32767}}, reg_offset = 41002}, subreg_offset = 32767, reladdr = 0x7fffa29e6c90, stride = 1 '\001'}, 
>            {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, 
>                  pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, 
>                    d = 0, ud = 0}}, reg_offset = 15616}, subreg_offset = 629676489, reladdr = 0x7ffed2415428, stride = 0 '\000'}, 
>            {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BRW_MESSAGE_REGISTER_FILE, negate = 1, abs = 0, address_mode = 0, pad0 = 0, 
>                  subnr = 14, nr = 41630, {{swizzle = 255, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, 
>                    f = 4.59163468e-41, d = 32767, ud = 32767}}, reg_offset = 58144}, subreg_offset = 32767, reladdr = 0x7fff00000000, stride = 120 'x'}, 
>            {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BAD_FILE, negate = 1, abs = 0, address_mode = 0, pad0 = 0, subnr = 4, 
>                  nr = 53927, {{swizzle = 254, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59149455e-41, 
>                    d = 32766, ud = 32766}}, reg_offset = 8432}, subreg_offset = 32766, reladdr = 0x7ffed2a720d8, stride = 0 '\000'}}, output_components = {
>            1, 0, 3536052440, 32766, 3536079344, 32766, 3536079408, 32766, 3526009336, 32766, 0, 0, 0, 0, 3527496744, 32766, 3534496608, 32766, 3532314824, 
>            32766, 3532314800, 32766, 0, 0, 0, 0, 1, 0, 0, 0, 3529271064, 32766, 3527496880, 32766, 3535964016, 32766, 3539244040, 32766, 0, 0, 0, 0, 1, 0, 
>            131072, 0, 1, 0, 0, 0, 0, 0, 1, 0, 3536052440, 32766, 3536079344, 32766}, dual_src_output = {<backend_reg> = {<brw_reg> = {
>                type = BRW_REGISTER_TYPE_UD, file = BRW_IMMEDIATE_VALUE, negate = 0, abs = 0, address_mode = 1, pad0 = 0, subnr = 9, nr = 53956, {{
>                    swizzle = 254, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59149455e-41, d = 32766, 
>                  ud = 32766}}, reg_offset = 41464}, subreg_offset = 32766, reladdr = 0x0, stride = 0 '\000'}, do_dual_src = 40, 
>          first_non_payload_grf = 32766, max_grf = 3534496608, nir_locals = 0x7ffed28ad8c8, nir_ssa_values = 0x7ffed28ad8b0, 
>          nir_inputs = {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, 
>                address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, 
>                    pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 0}, subreg_offset = 0, reladdr = 0x1, stride = 0 '\000'}, 
>          nir_outputs = {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_V, file = BRW_GENERAL_REGISTER_FILE, negate = 0, abs = 1, address_mode = 1, 
>                pad0 = 1, subnr = 12, nr = 53852, {{swizzle = 254, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, 
>                  f = 4.59149455e-41, d = 32766, ud = 32766}}, reg_offset = 55696}, subreg_offset = 32766, reladdr = 0x7fffe77e66f5 <dead_cf_list+1221>, 
>            stride = 96 '`'}, nir_system_values = 0x0, failed = 16, fail_msg = 0x7ffed26c4be0 "", simd16_unsupported = false, 
>          no16_msg = 0x7ffed26c4bd8 "\330\062r\322\376\177", result = {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, 
>                    indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 8}, subreg_offset = 0, 
>            reladdr = 0x811e0, stride = 224 '\340'}, payload = {source_depth_reg = 80 'P', source_w_reg = 110 'n', aa_dest_stencil_reg = 158 '\236', 
>            dest_depth_reg = 162 '\242', sample_pos_reg = 255 '\377', sample_mask_in_reg = 127 '\177', barycentric_coord_reg = "\000\000\002\000\000", 
>            local_invocation_id_reg = 0 '\000', num_regs = 0 '\000'}, source_depth_to_render_target = false, runtime_check_aads_emit = false, 
>          pixel_x = {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, 
>                address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, 
>                    pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 8}, subreg_offset = 0, reladdr = 0x7fffa29e6e40, stride = 80 'P'}, 
>          pixel_y = {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BRW_MESSAGE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, 
>                pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, 
>                  d = 0, ud = 0}}, reg_offset = 28240}, subreg_offset = 32767, reladdr = 0x7fffe77cd020 <cmp_phi_src>, stride = 104 'h'}, 
>          wpos_w = {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_V, file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 1, abs = 1, address_mode = 0, 
>                pad0 = 1, subnr = 27, nr = 54039, {{swizzle = 254, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, 
>                  f = 4.59149455e-41, d = 32766, ud = 32766}}, reg_offset = 7601}, subreg_offset = 32767, reladdr = 0x0, stride = 8 '\b'}, 
>          pixel_w = {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BRW_MESSAGE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, 
>                pad0 = 0, subnr = 26, nr = 59260, {{swizzle = 255, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, 
>                  f = 4.59163468e-41, d = 32767, ud = 32767}}, reg_offset = 28256}, subreg_offset = 32767, reladdr = 0x7fffa29e6ed0, stride = 177 '\261'}, 
>          delta_xy = {{<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, 
>                  address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, 
>                      pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 8}, subreg_offset = 0, reladdr = 0x7fffa29e6ec0, stride = 144 '\220'}, 
>            {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 1, address_mode = 1, 
>                  pad0 = 1, subnr = 13, nr = 41630, {{swizzle = 255, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, 
>                    f = 4.59163468e-41, d = 32767, ud = 32767}}, reg_offset = 15616}, subreg_offset = 629676489, reladdr = 0x7ffed26c4b68, 
>              stride = 0 '\000'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, 
>                  address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, 
>                      pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 1}, subreg_offset = 0, reladdr = 0x7ffed26b74e8, stride = 16 '\020'}, 
>            {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_V, file = UNIFORM, negate = 0, abs = 1, address_mode = 1, pad0 = 0, subnr = 9, 
>                  nr = 53868, {{swizzle = 254, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59149455e-41, 
>                    d = 32766, ud = 32766}}, reg_offset = 26357}, subreg_offset = 32767, reladdr = 0x7fffa29e6eb0, stride = 160 '\240'}, 
>            {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = UNIFORM, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 14, 
>                  nr = 41630, {{swizzle = 255, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59163468e-41, 
>                    d = 32767, ud = 32767}}, reg_offset = 54064}, subreg_offset = 32766, reladdr = 0x1000, stride = 40 '('}, {<backend_reg> = {<brw_reg> = {
>                  type = BRW_REGISTER_TYPE_W, file = BRW_MESSAGE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{
>                      swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, 
>                reg_offset = 4}, subreg_offset = 0, reladdr = 0x7b00000091, stride = 0 '\000'}}, shader_start_time = {<backend_reg> = {<brw_reg> = {
>                type = BRW_REGISTER_TYPE_UQ, file = BAD_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, 
>                    writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 8}, 
>            subreg_offset = 0, reladdr = 0x7fffa29e6f80, stride = 32 ' '}, userplane = {{<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                  file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 1, address_mode = 0, pad0 = 1, subnr = 7, nr = 2, {{swizzle = 0, writemask = 0, 
>                      indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 13176}, subreg_offset = 0, 
>              reladdr = 0x7ffed3c18220, stride = 208 '\320'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UB, file = BRW_IMMEDIATE_VALUE, 
>                  negate = 0, abs = 1, address_mode = 1, pad0 = 0, subnr = 4, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, 
>                      width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 31196}, subreg_offset = 32767, reladdr = 0x20, 
>              stride = 24 '\030'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = ATTR, negate = 0, abs = 1, address_mode = 1, pad0 = 0, 
>                  subnr = 6, nr = 2, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, 
>                    ud = 0}}, reg_offset = 40008}, subreg_offset = 32766, reladdr = 0x7ffed322ac18, stride = 200 '\310'}, {<backend_reg> = {<brw_reg> = {
>                  type = BRW_REGISTER_TYPE_UD, file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 1, address_mode = 1, pad0 = 1, subnr = 13, 
>                  nr = 41630, {{swizzle = 255, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59163468e-41, 
>                    d = 32767, ud = 32767}}, reg_offset = 0}, subreg_offset = 0, reladdr = 0x7ffed2886c68, stride = 224 '\340'}, 
>            {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BRW_IMMEDIATE_VALUE, negate = 1, abs = 0, address_mode = 0, pad0 = 0, 
>                  subnr = 12, nr = 53771, {{swizzle = 254, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, 
>                    f = 4.59149455e-41, d = 32766, ud = 32766}}, reg_offset = 21065}, subreg_offset = 32767, reladdr = 0x7fffa29e6fa0, stride = 0 '\000'}, 
>            {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_V, file = BRW_IMMEDIATE_VALUE, negate = 1, abs = 0, address_mode = 1, pad0 = 0, 
>                  subnr = 26, nr = 53849, {{swizzle = 254, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, 
>                    f = 4.59149455e-41, d = 32766, ud = 32766}}, reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}, 
>            {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_V, file = UNIFORM, negate = 1, abs = 1, address_mode = 1, pad0 = 1, subnr = 12, 
>                  nr = 53934, {{swizzle = 254, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59149455e-41, 
>                    d = 32766, ud = 32766}}, reg_offset = 32}, subreg_offset = 32767, reladdr = 0x530, stride = 40 '('}, {<backend_reg> = {<brw_reg> = {
>                  type = BRW_REGISTER_TYPE_UD, file = BRW_MESSAGE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 1, pad0 = 0, subnr = 16, nr = 54209, {{
>                      swizzle = 254, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59149455e-41, d = 32766, 
>                    ud = 32766}}, reg_offset = 1320}, subreg_offset = 0, reladdr = 0x7ffed25c2828, stride = 152 '\230'}}, 
>          final_gs_vertex_count = {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_W, file = ATTR, negate = 0, abs = 0, address_mode = 0, pad0 = 0, 
>                subnr = 0, nr = 0, {{swizzle = 255, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59163468e-41, 
>                  d = 32767, ud = 32767}}, reg_offset = 1360}, subreg_offset = 0, reladdr = 0x14, stride = 68 'D'}, 
>          control_data_bits = {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UW, file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, 
>                address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, 
>                    pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 93}, subreg_offset = 629676489, reladdr = 0x0, stride = 0 '\000'}, grf_used = 110, 
>          spilled_any_registers = 119, dispatch_width = 0, min_dispatch_width = 0, shader_time_index = 124, promoted_constants = 32767, bld = {
>            shader = 0x7fffe77e5000 <constant_fold_block>, block = 0x7fffa29e70d0, cursor = 0x7fff44000020, _dispatch_width = 146912, _group = 0, 
>            force_writemask_all = 119, annotation = {str = 0x7ffed3c18220 "", ir = 0x7ffed2718ae8}}}
>        g = {compiler = 0x0, log_data = 0x0, devinfo = 0x0, p = 0x7ffed2f9f6d8, key = 0x0, prog_data = 0x0, dispatch_width = 1, discard_halt_patches = {
>            head = 0x7fffa29e5570, tail = 0x0, tail_pred = 0x7fffa29e5568}, promoted_constants = 18, runtime_check_aads_emit = false, debug_flag = false, 
>          shader_name = 0x1 <error: Cannot access memory at address 0x1>, stage = MESA_SHADER_COMPUTE, mem_ctx = 0x7ffed5e18c08}
>        shader = 0x7ffed31b35d8
>        max_cs_threads = 70
>        cfg = 0x0
>#8  0x00007fffe784ac54 in brw_codegen_cs_prog (brw=brw@entry=0x8491338, prog=prog@entry=0x7fff44135448, cp=cp@entry=0x7ffed27887b0, 
>    key=key@entry=0x7fffa29e71b0) at ../../../../../../../src/mesa/drivers/dri/i965/brw_cs.c:124
>        ctx = 0x8491338
>        program = <optimized out>
>        mem_ctx = 0x7ffee2171278
>        program_size = 0
>        prog_data = {base = {binding_table = {size_bytes = 24, pull_constants_start = 6, texture_start = 1, gather_texture_start = 3503345872, 
>              ubo_start = 2, ssbo_start = 5, abo_start = 3503345872, image_start = 5, shader_time_start = 3503345872}, nr_params = 1, nr_pull_params = 0, 
>            nr_image_params = 1, curb_read_length = 1, total_scratch = 0, total_shared = 25088, dispatch_grf_start_reg = 4, use_alt_mode = false, 
>            param = 0x7ffed3be1848, pull_param = 0x7ffed3be1d78, image_param = 0x7ffed323d898}, dispatch_grf_start_reg_16 = 0, local_size = {32, 32, 1}, 
>          simd_size = 0, uses_barrier = true, uses_num_work_groups = false, local_invocation_id_regs = 3, binding_table = {work_groups_start = 0}}
>        start_busy = false
>        start_time = 0
>        cs = 0x7ffed25c2828
>        param_count = <optimized out>
>        st_index = <optimized out>
>        error_str = 0x1 <error: Cannot access memory at address 0x1>
>#9  0x00007fffe784b0c3 in brw_cs_precompile (ctx=0x8491338, shader_prog=0x7fff44135448, prog=0x7ffed27887b0)
>    at ../../../../../../../src/mesa/drivers/dri/i965/brw_cs.c:239
>        key = {program_string_id = 548, tex = {swizzles = {1672, 0 <repeats 31 times>}, gl_clamp_mask = {0, 0, 0}, gather_channel_quirk_mask = 0, 
>            compressed_multisample_layout_mask = 0, msaa_16 = 0, gen6_gather_wa = {(unknown: 0) <repeats 32 times>}}}
>        cp = 0x7ffed27887b0
>        old_prog_offset = 0
>        old_prog_data = 0x0
>        success = <optimized out>
>#10 0x00007fffe7852678 in brw_shader_precompile (sh_prog=<optimized out>, ctx=<optimized out>)
>    at ../../../../../../../src/mesa/drivers/dri/i965/brw_link.cpp:66
>        gs = 0x0
>        cs = 0x7ffed25c2828
>        vs = 0x0
>        tcs = 0x0
>        tes = 0x0
>        fs = 0x7fffa2972150
>#11 brw_link_shader (ctx=0x8491338, shProg=0x0) at ../../../../../../../src/mesa/drivers/dri/i965/brw_link.cpp:260
>No locals.
>#12 0x00007fffe76f0d86 in _mesa_glsl_link_shader (ctx=0x8491338, prog=0x7fff44135448) at ../../../../src/mesa/program/ir_to_mesa.cpp:3040
>        i = <optimized out>
>#13 0x00007fffe7605d4a in link_program (ctx=0x8491338, program=<optimized out>) at ../../../../src/mesa/main/shaderapi.c:1048
>        shProg = 0x7fff44135448
>#14 0x00000000009fe30b in ?? ()
>No symbol table info available.
>#15 0x00000000009fbcfc in ?? ()
>No symbol table info available.
>#16 0x0000000001108b29 in ?? ()
>No symbol table info available.
>#17 0x00000000010fd25a in ?? ()
>No symbol table info available.
>#18 0x000000000181254d in ?? ()
>No symbol table info available.
>#19 0x00000000012395ec in ?? ()
>No symbol table info available.
>#20 0x0000000000ce8ef3 in ?? ()
>No symbol table info available.
>#21 0x0000000000ce9135 in ?? ()
>No symbol table info available.
>#22 0x000000000137c58d in ?? ()
>No symbol table info available.
>#23 0x000000000137c5b7 in ?? ()
>No symbol table info available.
>#24 0x0000000000923d69 in ?? ()
>No symbol table info available.
>#25 0x0000000000b1dbd7 in ?? ()
>No symbol table info available.
>#26 0x00007ffff6ed80a4 in start_thread (arg=0x7fffa29e8700) at pthread_create.c:309
>        __res = <optimized out>
>        pd = 0x7fffa29e8700
>        now = <optimized out>
>        unwind_buf = {cancel_jmp_buf = {{jmp_buf = {140735921686272, -7254062393839813134, 1, 140737354125408, 0, 140735921686272, 7253928541436804594, 
>                7254042759281147378}, mask_was_saved = 0}}, priv = {pad = {0x0, 0x0, 0x0, 0x0}, data = {prev = 0x0, cleanup = 0x0, canceltype = 0}}}
>        not_first_call = <optimized out>
>        pagesize_m1 = <optimized out>
>        sp = <optimized out>
>        freesize = <optimized out>
>        __PRETTY_FUNCTION__ = "start_thread"
>#27 0x00007ffff53b387d in clone () at ../sysdeps/unix/sysv/linux/x86_64/clone.S:111
>No locals.
>(gdb) c
>Continuing.
>
>Program received signal SIGSEGV, Segmentation fault.
>memset () at ../sysdeps/x86_64/memset.S:93
>93	in ../sysdeps/x86_64/memset.S
>(gdb) bt
>#0  memset () at ../sysdeps/x86_64/memset.S:93
>#1  0x00007fffe790070e in memset (__len=471424, __ch=0, __dest=0x7fffa2972150) at /usr/include/x86_64-linux-gnu/bits/string3.h:84
>#2  fs_instruction_scheduler::calculate_deps (this=0x7fffa29e53e0) at ../../../../../../../src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp:935
>#3  0x00007fffe79016ba in instruction_scheduler::run (this=this@entry=0x7fffa29e53e0, cfg=0x7ffed30cd538)
>    at ../../../../../../../src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp:1653
>#4  0x00007fffe79018ea in fs_visitor::schedule_instructions (this=this@entry=0x7fffa29e55a0, mode=<optimized out>)
>    at ../../../../../../../src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp:1685
>#5  0x00007fffe78bd9e0 in fs_visitor::allocate_registers (this=this@entry=0x7fffa29e55a0) at ../../../../../../../src/mesa/drivers/dri/i965/brw_fs.cpp:5214
>#6  0x00007fffe78c0542 in fs_visitor::run_cs (this=0x7fffa29e55a0) at ../../../../../../../src/mesa/drivers/dri/i965/brw_fs.cpp:5490
>#7  0x00007fffe78c0666 in brw_compile_cs (compiler=0x4d090e8, log_data=log_data@entry=0x8491338, mem_ctx=mem_ctx@entry=0x7ffee2171278, 
>    key=key@entry=0x7fffa29e71b0, prog_data=prog_data@entry=0x7fffa29e70e0, src_shader=<optimized out>, shader_time_index=-1, 
>    final_assembly_size=0x7fffa29e70d4, error_str=0x7fffa29e70d8) at ../../../../../../../src/mesa/drivers/dri/i965/brw_fs.cpp:5743
>#8  0x00007fffe784ac54 in brw_codegen_cs_prog (brw=brw@entry=0x8491338, prog=prog@entry=0x7fff44135448, cp=cp@entry=0x7ffed27887b0, 
>    key=key@entry=0x7fffa29e71b0) at ../../../../../../../src/mesa/drivers/dri/i965/brw_cs.c:124
>#9  0x00007fffe784b0c3 in brw_cs_precompile (ctx=0x8491338, shader_prog=0x7fff44135448, prog=0x7ffed27887b0)
>    at ../../../../../../../src/mesa/drivers/dri/i965/brw_cs.c:239
>#10 0x00007fffe7852678 in brw_shader_precompile (sh_prog=<optimized out>, ctx=<optimized out>)
>    at ../../../../../../../src/mesa/drivers/dri/i965/brw_link.cpp:66
>#11 brw_link_shader (ctx=0x8491338, shProg=0x0) at ../../../../../../../src/mesa/drivers/dri/i965/brw_link.cpp:260
>#12 0x00007fffe76f0d86 in _mesa_glsl_link_shader (ctx=0x8491338, prog=0x7fff44135448) at ../../../../src/mesa/program/ir_to_mesa.cpp:3040
>#13 0x00007fffe7605d4a in link_program (ctx=0x8491338, program=<optimized out>) at ../../../../src/mesa/main/shaderapi.c:1048
>#14 0x00000000009fe30b in ?? ()
>#15 0x00000000009fbcfc in ?? ()
>#16 0x0000000001108b29 in ?? ()
>#17 0x00000000010fd25a in ?? ()
>#18 0x000000000181254d in ?? ()
>#19 0x00000000012395ec in ?? ()
>#20 0x0000000000ce8ef3 in ?? ()
>#21 0x0000000000ce9135 in ?? ()
>#22 0x000000000137c58d in ?? ()
>#23 0x000000000137c5b7 in ?? ()
>#24 0x0000000000923d69 in ?? ()
>#25 0x0000000000b1dbd7 in ?? ()
>#26 0x00007ffff6ed80a4 in start_thread (arg=0x7fffa29e8700) at pthread_create.c:309
>#27 0x00007ffff53b387d in clone () at ../sysdeps/unix/sysv/linux/x86_64/clone.S:111
>(gdb) bt full
>#0  memset () at ../sysdeps/x86_64/memset.S:93
>No locals.
>#1  0x00007fffe790070e in memset (__len=471424, __ch=0, __dest=0x7fffa2972150) at /usr/include/x86_64-linux-gnu/bits/string3.h:84
>No locals.
>#2  fs_instruction_scheduler::calculate_deps (this=0x7fffa29e53e0) at ../../../../../../../src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp:935
>        last_grf_write = 0x7fffa2972150
>        last_mrf_write = 0x7fffa29720c0
>        last_conditional_mod = {0x0, 0x0}
>        node = <optimized out>
>        last_accumulator_write = 0x0
>        last_fixed_grf_write = 0x0
>        prev = <optimized out>
>#3  0x00007fffe79016ba in instruction_scheduler::run (this=this@entry=0x7fffa29e53e0, cfg=0x7ffed30cd538)
>    at ../../../../../../../src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp:1653
>        block = 0x7ffed3dc28c8
>#4  0x00007fffe79018ea in fs_visitor::schedule_instructions (this=this@entry=0x7fffa29e55a0, mode=<optimized out>)
>    at ../../../../../../../src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp:1685
>        grf_count = 3683
>        sched = {<instruction_scheduler> = {_vptr.instruction_scheduler = 0x7fffe7d03310 <vtable for fs_instruction_scheduler+16>, mem_ctx = 0x7ffef293a348, 
>            post_reg_alloc = false, instructions_to_schedule = 15, grf_count = 3683, hw_reg_count = 5, time = 0, reg_pressure = 0, block_idx = -1566681696, 
>            instructions = {head = 0x7ffed3dd9278, tail = 0x0, tail_pred = 0x7ffed3e207b8}, bs = 0x7fffa29e55a0, mode = SCHEDULE_PRE, 
>            reg_pressure_in = 0x7ffed3df6a48, livein = 0x7ffed3dd9188, liveout = 0x7ffed3e188f8, hw_liveout = 0x7ffed3e1b7e8, written = 0x7ffed3e1b8d8, 
>            reads_remaining = 0x7ffed3e1c778, hw_reads_remaining = 0x7ffed26dc008}, v = 0x7fffa29e55a0}
>#5  0x00007fffe78bd9e0 in fs_visitor::allocate_registers (this=this@entry=0x7fffa29e55a0) at ../../../../../../../src/mesa/drivers/dri/i965/brw_fs.cpp:5214
>        i = <optimized out>
>        allocated_without_spills = false
>        pre_modes = {SCHEDULE_PRE, SCHEDULE_PRE_NON_LIFO, SCHEDULE_PRE_LIFO}
>#6  0x00007fffe78c0542 in fs_visitor::run_cs (this=0x7fffa29e55a0) at ../../../../../../../src/mesa/drivers/dri/i965/brw_fs.cpp:5490
>        this = 0x7fffa29e55a0
>#7  0x00007fffe78c0666 in brw_compile_cs (compiler=0x4d090e8, log_data=log_data@entry=0x8491338, mem_ctx=mem_ctx@entry=0x7ffee2171278, 
>    key=key@entry=0x7fffa29e71b0, prog_data=prog_data@entry=0x7fffa29e70e0, src_shader=<optimized out>, shader_time_index=-1, 
>    final_assembly_size=0x7fffa29e70d4, error_str=0x7fffa29e70d8) at ../../../../../../../src/mesa/drivers/dri/i965/brw_fs.cpp:5743
>        local_workgroup_size = 1024
>        fail_msg = 0x0
>        v8 = {<backend_shader> = {_vptr.backend_shader = 0x7fffe7d17010 <vtable for fs_visitor+16>, compiler = 0x4d090e8, log_data = 0x8491338, 
>            devinfo = 0x7fffe7a26800 <brw_device_info_hsw_gt3>, nir = 0x7ffed31b35d8, stage_prog_data = 0x7fffa29e70e0, mem_ctx = 0x7ffee2171278, 
>            instructions = {head = 0x7fffa29e55e0, tail = 0x0, tail_pred = 0x7fffa29e55d8}, cfg = 0x7ffed30cd538, stage = MESA_SHADER_COMPUTE, 
>            debug_enabled = false, stage_name = 0x7fffe7a119c5 "compute", stage_abbrev = 0x7fffe7a1f99c "CS", alloc = {sizes = 0x7ffed3d88fa0, 
>              offsets = 0x7ffed3d90fb0, count = 3683, total_size = 5371, capacity = 8192}}, key = 0x7fffa29e71b0, key_tex = 0x7fffa29e71b4, 
>          gs_compile = 0x0, prog_data = 0x7fffa29e70e0, prog = 0x0, input_vue_map = 0x0, param_size = 0x7ffed3be8a28, virtual_grf_start = 0x7ffed3dd2018, 
>          virtual_grf_end = 0x7ffed3de3488, live_intervals = 0x7ffed3dd1e18, regs_live_at_ip = 0x0, uniforms = 24, last_scratch = 0, 
>          pull_constant_loc = 0x7ffed3dc3988, push_constant_loc = 0x7ffed3dc3a18, frag_depth = {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                file = BAD_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, 
>                    vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, 
>            stride = 1 '\001'}, frag_stencil = {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BAD_FILE, negate = 0, abs = 0, 
>                address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, 
>                    pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}, 
>          sample_mask = {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BAD_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, 
>                subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, 
>                  ud = 0}}, reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}, outputs = {{<backend_reg> = {<brw_reg> = {
>                  type = BRW_REGISTER_TYPE_UD, file = BAD_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, 
>                      writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 0}, 
>              subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'} <repeats 58 times>}, output_components = {0 <repeats 58 times>}, 
>          dual_src_output = {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BAD_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, 
>                subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, 
>                  ud = 0}}, reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}, do_dual_src = false, first_non_payload_grf = 5, 
>          max_grf = 112, nir_locals = 0x7ffed3d20998, nir_ssa_values = 0x7ffed3d51ad8, nir_inputs = {<backend_reg> = {<brw_reg> = {
>                type = BRW_REGISTER_TYPE_UD, file = BAD_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, 
>                    writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 0}, 
>            subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}, nir_outputs = {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_F, 
>                file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 228, writemask = 15, 
>                    indirect_offset = 0, vstride = 4, width = 3, hstride = 1, pad1 = 0}, f = 7.27948604e-12, d = 754978788, ud = 754978788}}, 
>              reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}, nir_system_values = 0x7ffed3c572e8, failed = false, 
>          fail_msg = 0x150 <error: Cannot access memory at address 0x150>, simd16_unsupported = false, no16_msg = 0x0, 
>          result = {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_F, file = VGRF, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, 
>                nr = 155, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, 
>              reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}, payload = {source_depth_reg = 0 '\000', source_w_reg = 0 '\000', 
>            aa_dest_stencil_reg = 0 '\000', dest_depth_reg = 0 '\000', sample_pos_reg = 0 '\000', sample_mask_in_reg = 0 '\000', 
>            barycentric_coord_reg = "\000\000\000\000\000", local_invocation_id_reg = 1 '\001', num_regs = 4 '\004'}, source_depth_to_render_target = false, 
>          runtime_check_aads_emit = false, pixel_x = {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BAD_FILE, negate = 0, abs = 0, 
>                address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, 
>                    pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}, 
>          pixel_y = {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BAD_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, 
>                nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, 
>              reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}, wpos_w = {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                file = BAD_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, 
>                    vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, 
>            stride = 1 '\001'}, pixel_w = {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BAD_FILE, negate = 0, abs = 0, 
>                address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, 
>                    pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}, delta_xy = {
>            {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BAD_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, 
>                  {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, 
>                reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                  file = BAD_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, 
>                      vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, 
>              stride = 1 '\001'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BAD_FILE, negate = 0, abs = 0, address_mode = 0, 
>                  pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, 
>                    d = 0, ud = 0}}, reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}, {<backend_reg> = {<brw_reg> = {
>                  type = BRW_REGISTER_TYPE_UD, file = BAD_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, 
>                      writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 0}, 
>              subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BAD_FILE, negate = 0, 
>                  abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, 
>                      hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}, 
>            {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BAD_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, 
>                  {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, 
>                reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}}, shader_start_time = {<backend_reg> = {<brw_reg> = {
>                type = BRW_REGISTER_TYPE_UD, file = BAD_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, 
>                    writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 0}, 
>            subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}, userplane = {{<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BAD_FILE, 
>                  negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, 
>                      width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}, 
>            {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BAD_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, 
>                  {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, 
>                reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                  file = BAD_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, 
>                      vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, 
>              stride = 1 '\001'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BAD_FILE, negate = 0, abs = 0, address_mode = 0, 
>                  pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, 
>                    d = 0, ud = 0}}, reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}, {<backend_reg> = {<brw_reg> = {
>                  type = BRW_REGISTER_TYPE_UD, file = BAD_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, 
>                      writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 0}, 
>              subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BAD_FILE, negate = 0, 
>                  abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, 
>                      hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}, 
>            {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BAD_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, 
>                  {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, 
>                reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                  file = BAD_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, 
>                      vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, 
>              stride = 1 '\001'}}, final_gs_vertex_count = {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BAD_FILE, negate = 0, abs = 0, 
>                address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, 
>                    pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}, 
>          control_data_bits = {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BAD_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, 
>                subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, 
>                  ud = 0}}, reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}, grf_used = 3548886616, spilled_any_registers = false, 
>          dispatch_width = 8, min_dispatch_width = 16, shader_time_index = -1, promoted_constants = 43, bld = {shader = 0x7fffa29e55a0, block = 0x0, 
>            cursor = 0x0, _dispatch_width = 64, _group = 0, force_writemask_all = false, annotation = {str = 0x0, ir = 0x0}}}
>        v16 = {<backend_shader> = {_vptr.backend_shader = 0x7fffe7d17130 <vtable for backend_shader+16>, compiler = 0x4d090e8, log_data = 0x0, 
>            devinfo = 0x0, nir = 0x0, stage_prog_data = 0x7ffed387ba58, mem_ctx = 0x0, instructions = {head = 0x0, tail = 0x1, tail_pred = 0x7fffa29e6328}, 
>            cfg = 0x0, stage = MESA_SHADER_VERTEX, debug_enabled = false, stage_name = 0x0, stage_abbrev = 0x7ffed387aa58 "", alloc = {sizes = 0x0, 
>              offsets = 0x0, count = 1, total_size = 0, capacity = 2048}}, key = 0x0, key_tex = 0x0, gs_compile = 0x0, prog_data = 0x7ffed387ab48, 
>          prog = 0x0, input_vue_map = 0x0, param_size = 0x1, virtual_grf_start = 0x7ffed2844838, virtual_grf_end = 0x0, live_intervals = 0x0, 
>          regs_live_at_ip = 0x0, uniforms = 3548884024, last_scratch = 32766, pull_constant_loc = 0x0, push_constant_loc = 0x0, 
>          frag_depth = {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_D, file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, 
>                address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, 
>                    pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, stride = 0 '\000'}, 
>          frag_stencil = {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, 
>                address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, 
>                    pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 44328}, subreg_offset = 32766, reladdr = 0x0, stride = 0 '\000'}, 
>          sample_mask = {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_D, file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, 
>                address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, 
>                    pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}, outputs = {
>            {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BAD_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, 
>                  {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, 
>                reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, stride = 192 '\300'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                  file = BRW_IMMEDIATE_VALUE, negate = 1, abs = 1, address_mode = 1, pad0 = 0, subnr = 13, nr = 41630, {{swizzle = 255, writemask = 15, 
>                      indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59163468e-41, d = 32767, ud = 32767}}, reg_offset = 54120}, 
>              subreg_offset = 32767, reladdr = 0x0, stride = 238 '\356'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_D, 
>                  file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, 
>                      indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 27328}, 
>              subreg_offset = 32767, reladdr = 0x7, stride = 121 'y'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = VGRF, negate = 1, 
>                  abs = 0, address_mode = 1, pad0 = 0, subnr = 13, nr = 41630, {{swizzle = 255, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, 
>                      hstride = 0, pad1 = 0}, f = 4.59163468e-41, d = 32767, ud = 32767}}, reg_offset = 27312}, subreg_offset = 32767, 
>              reladdr = 0x7fffe7a07fa7, stride = 170 '\252'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                  file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, 
>                      indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 20329}, 
>              subreg_offset = 32767, reladdr = 0x0, stride = 1 '\001'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                  file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 1, address_mode = 1, pad0 = 0, subnr = 13, nr = 41630, {{swizzle = 255, 
>                      writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59163468e-41, d = 32767, ud = 32767}}, 
>                reg_offset = 27376}, subreg_offset = 32767, reladdr = 0x0, stride = 0 '\000'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                  file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, 
>                      indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 46680}, 
>              subreg_offset = 32766, reladdr = 0x0, stride = 0 '\000'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_D, 
>                  file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, 
>                      indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 32}, subreg_offset = 32767, 
>              reladdr = 0x1b0, stride = 1 '\001'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = UNIFORM, negate = 0, abs = 1, 
>                  address_mode = 1, pad0 = 1, subnr = 31, nr = 54157, {{swizzle = 254, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, 
>                      hstride = 0, pad1 = 0}, f = 4.59149455e-41, d = 32766, ud = 32766}}, reg_offset = 424}, subreg_offset = 0, reladdr = 0x7fff44000078, 
>              stride = 232 '\350'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_HF, file = BRW_GENERAL_REGISTER_FILE, negate = 0, abs = 0, 
>                  address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, 
>                      pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 464}, subreg_offset = 0, reladdr = 0x6, stride = 54 '6'}, 
>            {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, 
>                  pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, 
>                    d = 0, ud = 0}}, reg_offset = 91}, subreg_offset = 0, reladdr = 0x0, stride = 0 '\000'}, {<backend_reg> = {<brw_reg> = {type = 14, 
>                  file = UNIFORM, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 119, writemask = 0, indirect_offset = 0, 
>                      vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 1.66754517e-43, d = 119, ud = 119}}, reg_offset = 11778}, subreg_offset = 32767, 
>              reladdr = 0x7ffed3bb6168, stride = 128 '\200'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_V, file = UNIFORM, negate = 0, 
>                  abs = 1, address_mode = 0, pad0 = 0, subnr = 12, nr = 54203, {{swizzle = 254, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, 
>                      hstride = 0, pad1 = 0}, f = 4.59149455e-41, d = 32766, ud = 32766}}, reg_offset = 17419}, subreg_offset = 32767, 
>              reladdr = 0x7ffed3bb6168, stride = 128 '\200'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BRW_IMMEDIATE_VALUE, 
>                  negate = 0, abs = 1, address_mode = 0, pad0 = 0, subnr = 12, nr = 54203, {{swizzle = 254, writemask = 15, indirect_offset = 7, 
>                      vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59149455e-41, d = 32766, ud = 32766}}, reg_offset = 15616}, 
>              subreg_offset = 629676489, reladdr = 0x7ffed3bb6168, stride = 120 'x'}, {<backend_reg> = {<brw_reg> = {type = 15, 
>                  file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, 
>                      indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 17128}, 
>              subreg_offset = 32767, reladdr = 0x7fffe77c2ac0 <add_ssa_def_cb>, stride = 104 'h'}, {<backend_reg> = {<brw_reg> = {type = 15, 
>                  file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, 
>                      indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 15616}, 
>              subreg_offset = 629676489, reladdr = 0x7ffed3bb6168, stride = 181 '\265'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                  file = VGRF, negate = 1, abs = 0, address_mode = 1, pad0 = 0, subnr = 5, nr = 59260, {{swizzle = 255, writemask = 15, indirect_offset = 7, 
>                      vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59163468e-41, d = 32767, ud = 32767}}, reg_offset = 29088}, 
>              subreg_offset = 32767, reladdr = 0x7ffed3bb6168, stride = 83 'S'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                  file = BRW_IMMEDIATE_VALUE, negate = 1, abs = 1, address_mode = 1, pad0 = 1, subnr = 12, nr = 41630, {{swizzle = 255, writemask = 15, 
>                      indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59163468e-41, d = 32767, ud = 32767}}, reg_offset = 27816}, 
>              subreg_offset = 32767, reladdr = 0x7fffe7cfd6b8 <replace39_0+24>, stride = 49 '1'}, {<backend_reg> = {<brw_reg> = {
>                  type = BRW_REGISTER_TYPE_UD, file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{
>                      swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, 
>                reg_offset = 4536}, subreg_offset = 32766, reladdr = 0x7fffa29e6890, stride = 123 '{'}, {<backend_reg> = {<brw_reg> = {
>                  type = BRW_REGISTER_TYPE_D, file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{
>                      swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, 
>                reg_offset = 23896}, subreg_offset = 32766, reladdr = 0x7fffa29e6c60, stride = 0 '\000'}, {<backend_reg> = {<brw_reg> = {
>                  type = BRW_REGISTER_TYPE_UD, file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{
>                      swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, 
>                reg_offset = 24264}, subreg_offset = 32766, reladdr = 0x0, stride = 0 '\000'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_D, 
>                  file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, 
>                      indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 23784}, 
>              subreg_offset = 32767, reladdr = 0x0, stride = 1 '\001'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                  file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, 
>                      indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 24504}, 
>              subreg_offset = 32766, reladdr = 0x1, stride = 0 '\000'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_D, 
>                  file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, 
>                      indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 4}, subreg_offset = 0, 
>              reladdr = 0x0, stride = 188 '\274'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_D, file = BRW_ARCHITECTURE_REGISTER_FILE, 
>                  negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, 
>                      width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 336}, subreg_offset = 0, reladdr = 0x4, stride = 2 '\002'}, 
>            {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, 
>                  pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, 
>                    d = 0, ud = 0}}, reg_offset = 91}, subreg_offset = 0, reladdr = 0x1, stride = 0 '\000'}, {<backend_reg> = {<brw_reg> = {type = 14, 
>                  file = UNIFORM, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 119, writemask = 0, indirect_offset = 0, 
>                      vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 1.66754517e-43, d = 119, ud = 119}}, reg_offset = 11778}, subreg_offset = 32767, 
>              reladdr = 0x7ffed3be10f8, stride = 128 '\200'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                  file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 1, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, 
>                      indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 1}, subreg_offset = 0, 
>              reladdr = 0x7fffe7a0f380 <search38_1_1_1_0>, stride = 38 '&'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_V, file = VGRF, 
>                  negate = 0, abs = 1, address_mode = 0, pad0 = 1, subnr = 27, nr = 53880, {{swizzle = 254, writemask = 15, indirect_offset = 7, 
>                      vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59149455e-41, d = 32766, ud = 32766}}, reg_offset = 39280}, 
>              subreg_offset = 32766, reladdr = 0x7ffed2c09970, stride = 88 'X'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                  file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, 
>                      indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 0}, subreg_offset = 0, 
>              reladdr = 0x80, stride = 1 '\001'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BRW_ARCHITECTURE_REGISTER_FILE, 
>                  negate = 1, abs = 1, address_mode = 1, pad0 = 0, subnr = 30, nr = 59296, {{swizzle = 255, writemask = 15, indirect_offset = 7, 
>                      vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59163468e-41, d = 32767, ud = 32767}}, reg_offset = 40742}, 
>              subreg_offset = 32767, reladdr = 0x7ffed278dd48, stride = 144 '\220'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                  file = BRW_GENERAL_REGISTER_FILE, negate = 1, abs = 0, address_mode = 0, pad0 = 1, subnr = 19, nr = 53952, {{swizzle = 254, 
>                      writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59149455e-41, d = 32766, ud = 32766}}, 
>                reg_offset = 40056}, subreg_offset = 32766, reladdr = 0x0, stride = 0 '\000'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                  file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 1, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, 
>                      indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 1}, subreg_offset = 0, 
>              reladdr = 0x7fffe7a0f380 <search38_1_1_1_0>, stride = 38 '&'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_V, file = VGRF, 
>                  negate = 0, abs = 1, address_mode = 0, pad0 = 1, subnr = 27, nr = 53880, {{swizzle = 254, writemask = 15, indirect_offset = 7, 
>                      vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59149455e-41, d = 32766, ud = 32766}}, reg_offset = 40080}, 
>              subreg_offset = 32766, reladdr = 0x7ffed2c09c90, stride = 120 'x'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                  file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, 
>                      indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 0}, subreg_offset = 0, 
>              reladdr = 0x1, stride = 8 '\b'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BRW_ARCHITECTURE_REGISTER_FILE, 
>                  negate = 1, abs = 0, address_mode = 1, pad0 = 0, subnr = 29, nr = 53945, {{swizzle = 254, writemask = 15, indirect_offset = 7, 
>                      vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59149455e-41, d = 32766, ud = 32766}}, reg_offset = 4144}, 
>              subreg_offset = 32766, reladdr = 0x7ffed31d1018, stride = 0 '\000'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                  file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, 
>                      indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 1}, subreg_offset = 0, 
>              reladdr = 0x7fffa29e6b90, stride = 1 '\001'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = VGRF, negate = 1, abs = 0, 
>                  address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, 
>                      pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 1}, subreg_offset = 0, reladdr = 0x7fffe7a0f530 <search10_1_0>, stride = 38 '&'}, 
>            {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_V, file = ATTR, negate = 1, abs = 0, address_mode = 0, pad0 = 0, subnr = 17, nr = 53944, 
>                  {{swizzle = 254, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59149455e-41, d = 32766, 
>                    ud = 32766}}, reg_offset = 28576}, subreg_offset = 32766, reladdr = 0xc0, stride = 1 '\001'}, {<backend_reg> = {<brw_reg> = {
>                  type = BRW_REGISTER_TYPE_UD, file = VGRF, negate = 0, abs = 0, address_mode = 1, pad0 = 1, subnr = 31, nr = 59296, {{swizzle = 255, 
>                      writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59163468e-41, d = 32767, ud = 32767}}, 
>                reg_offset = 40742}, subreg_offset = 32767, reladdr = 0x7ffed2415428, stride = 32 ' '}, {<backend_reg> = {<brw_reg> = {
>                  type = BRW_REGISTER_TYPE_UD, file = UNIFORM, negate = 1, abs = 1, address_mode = 1, pad0 = 1, subnr = 12, nr = 53852, {{swizzle = 254, 
>                      writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59149455e-41, d = 32766, ud = 32766}}, 
>                reg_offset = 37896}, subreg_offset = 32766, reladdr = 0x0, stride = 0 '\000'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                  file = VGRF, negate = 1, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, 
>                      vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 1}, subreg_offset = 0, 
>              reladdr = 0x7fffe7a0fe40 <search11_1_0>, stride = 38 '&'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_V, 
>                  file = BRW_GENERAL_REGISTER_FILE, negate = 0, abs = 1, address_mode = 1, pad0 = 1, subnr = 12, nr = 53852, {{swizzle = 254, 
>                      writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59149455e-41, d = 32766, ud = 32766}}, 
>                reg_offset = 64472}, subreg_offset = 32766, reladdr = 0x7ffed319fbd8, stride = 192 '\300'}, {<backend_reg> = {<brw_reg> = {
>                  type = BRW_REGISTER_TYPE_UD, file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{
>                      swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, 
>                reg_offset = 0}, subreg_offset = 0, reladdr = 0x1, stride = 40 '('}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                  file = UNIFORM, negate = 0, abs = 1, address_mode = 1, pad0 = 0, subnr = 4, nr = 53932, {{swizzle = 254, writemask = 15, 
>                      indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59149455e-41, d = 32766, ud = 32766}}, reg_offset = 55496}, 
>              subreg_offset = 32766, reladdr = 0x7ffed28ad8b0, stride = 0 '\000'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                  file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, 
>                      indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 1}, subreg_offset = 0, 
>              reladdr = 0x7fffa29e6bc0, stride = 1 '\001'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                  file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, 
>                      indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 15616}, 
>              subreg_offset = 629676489, reladdr = 0x7ffed2415428, stride = 0 '\000'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                  file = BRW_IMMEDIATE_VALUE, negate = 1, abs = 0, address_mode = 1, pad0 = 0, subnr = 13, nr = 41630, {{swizzle = 255, writemask = 15, 
>                      indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59163468e-41, d = 32767, ud = 32767}}, reg_offset = 52000}, 
>              subreg_offset = 32767, reladdr = 0x7fffa29e6bc0, stride = 42 '*'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = VGRF, 
>                  negate = 1, abs = 1, address_mode = 1, pad0 = 0, subnr = 13, nr = 41630, {{swizzle = 255, writemask = 15, indirect_offset = 7, 
>                      vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59163468e-41, d = 32767, ud = 32767}}, reg_offset = 1}, subreg_offset = 3, 
>              reladdr = 0x0, stride = 0 '\000'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_V, file = BRW_MESSAGE_REGISTER_FILE, negate = 0, 
>                  abs = 0, address_mode = 0, pad0 = 1, subnr = 10, nr = 53825, {{swizzle = 254, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, 
>                      hstride = 0, pad1 = 0}, f = 4.59149455e-41, d = 32766, ud = 32766}}, reg_offset = 0}, subreg_offset = 0, reladdr = 0x7fffa29e6fd0, 
>              stride = 32 ' '}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = VGRF, negate = 1, abs = 1, address_mode = 1, pad0 = 0, 
>                  subnr = 13, nr = 41630, {{swizzle = 255, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, 
>                    f = 4.59163468e-41, d = 32767, ud = 32767}}, reg_offset = 39978}, subreg_offset = 32767, reladdr = 0x7fffa29e6bc0, stride = 1 '\001'}, 
>            {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_D, file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 1, address_mode = 1, 
>                  pad0 = 0, subnr = 13, nr = 41630, {{swizzle = 255, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, 
>                    f = 4.59163468e-41, d = 32767, ud = 32767}}, reg_offset = 21544}, subreg_offset = 32766, reladdr = 0x7ffed2415428, stride = 232 '\350'}, 
>            {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BRW_MESSAGE_REGISTER_FILE, negate = 1, abs = 0, address_mode = 1, pad0 = 0, 
>                  subnr = 28, nr = 59343, {{swizzle = 255, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, 
>                    f = 4.59163468e-41, d = 32767, ud = 32767}}, reg_offset = 27584}, subreg_offset = 32767, reladdr = 0x7fffe7cf2b48, stride = 163 '\243'}, 
>            {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_V, file = BRW_MESSAGE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 1, 
>                  subnr = 10, nr = 53825, {{swizzle = 254, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, 
>                    f = 4.59149455e-41, d = 32766, ud = 32766}}, reg_offset = 0}, subreg_offset = 0, reladdr = 0x7fffa29e6b80, stride = 32 ' '}, 
>            {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BRW_GENERAL_REGISTER_FILE, negate = 1, abs = 0, address_mode = 0, pad0 = 1, 
>                  subnr = 13, nr = 41630, {{swizzle = 255, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, 
>                    f = 4.59163468e-41, d = 32767, ud = 32767}}, reg_offset = 41002}, subreg_offset = 32767, reladdr = 0x7fffa29e6c90, stride = 1 '\001'}, 
>            {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, 
>                  pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, 
>                    d = 0, ud = 0}}, reg_offset = 15616}, subreg_offset = 629676489, reladdr = 0x7ffed2415428, stride = 0 '\000'}, 
>            {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BRW_MESSAGE_REGISTER_FILE, negate = 1, abs = 0, address_mode = 0, pad0 = 0, 
>                  subnr = 14, nr = 41630, {{swizzle = 255, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, 
>                    f = 4.59163468e-41, d = 32767, ud = 32767}}, reg_offset = 58144}, subreg_offset = 32767, reladdr = 0x7fff00000000, stride = 120 'x'}, 
>            {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BAD_FILE, negate = 1, abs = 0, address_mode = 0, pad0 = 0, subnr = 4, 
>                  nr = 53927, {{swizzle = 254, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59149455e-41, 
>                    d = 32766, ud = 32766}}, reg_offset = 8432}, subreg_offset = 32766, reladdr = 0x7ffed2a720d8, stride = 0 '\000'}}, output_components = {
>            1, 0, 3536052440, 32766, 3536079344, 32766, 3536079408, 32766, 3526009336, 32766, 0, 0, 0, 0, 3527496744, 32766, 3534496608, 32766, 3532314824, 
>            32766, 3532314800, 32766, 0, 0, 0, 0, 1, 0, 0, 0, 3529271064, 32766, 3527496880, 32766, 3535964016, 32766, 3539244040, 32766, 0, 0, 0, 0, 1, 0, 
>            131072, 0, 1, 0, 0, 0, 0, 0, 1, 0, 3536052440, 32766, 3536079344, 32766}, dual_src_output = {<backend_reg> = {<brw_reg> = {
>                type = BRW_REGISTER_TYPE_UD, file = BRW_IMMEDIATE_VALUE, negate = 0, abs = 0, address_mode = 1, pad0 = 0, subnr = 9, nr = 53956, {{
>                    swizzle = 254, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59149455e-41, d = 32766, 
>                  ud = 32766}}, reg_offset = 41464}, subreg_offset = 32766, reladdr = 0x0, stride = 0 '\000'}, do_dual_src = 40, 
>          first_non_payload_grf = 32766, max_grf = 3534496608, nir_locals = 0x7ffed28ad8c8, nir_ssa_values = 0x7ffed28ad8b0, 
>          nir_inputs = {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, 
>                address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, 
>                    pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 0}, subreg_offset = 0, reladdr = 0x1, stride = 0 '\000'}, 
>          nir_outputs = {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_V, file = BRW_GENERAL_REGISTER_FILE, negate = 0, abs = 1, address_mode = 1, 
>                pad0 = 1, subnr = 12, nr = 53852, {{swizzle = 254, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, 
>                  f = 4.59149455e-41, d = 32766, ud = 32766}}, reg_offset = 55696}, subreg_offset = 32766, reladdr = 0x7fffe77e66f5 <dead_cf_list+1221>, 
>            stride = 96 '`'}, nir_system_values = 0x0, failed = 16, fail_msg = 0x7ffed26c4be0 "", simd16_unsupported = false, 
>          no16_msg = 0x7ffed26c4bd8 "\330\062r\322\376\177", result = {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, 
>                    indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 8}, subreg_offset = 0, 
>            reladdr = 0x811e0, stride = 224 '\340'}, payload = {source_depth_reg = 80 'P', source_w_reg = 110 'n', aa_dest_stencil_reg = 158 '\236', 
>            dest_depth_reg = 162 '\242', sample_pos_reg = 255 '\377', sample_mask_in_reg = 127 '\177', barycentric_coord_reg = "\000\000\002\000\000", 
>            local_invocation_id_reg = 0 '\000', num_regs = 0 '\000'}, source_depth_to_render_target = false, runtime_check_aads_emit = false, 
>          pixel_x = {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, 
>                address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, 
>                    pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 8}, subreg_offset = 0, reladdr = 0x7fffa29e6e40, stride = 80 'P'}, 
>          pixel_y = {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BRW_MESSAGE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, 
>                pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, 
>                  d = 0, ud = 0}}, reg_offset = 28240}, subreg_offset = 32767, reladdr = 0x7fffe77cd020 <cmp_phi_src>, stride = 104 'h'}, 
>          wpos_w = {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_V, file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 1, abs = 1, address_mode = 0, 
>                pad0 = 1, subnr = 27, nr = 54039, {{swizzle = 254, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, 
>                  f = 4.59149455e-41, d = 32766, ud = 32766}}, reg_offset = 7601}, subreg_offset = 32767, reladdr = 0x0, stride = 8 '\b'}, 
>          pixel_w = {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BRW_MESSAGE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, 
>                pad0 = 0, subnr = 26, nr = 59260, {{swizzle = 255, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, 
>                  f = 4.59163468e-41, d = 32767, ud = 32767}}, reg_offset = 28256}, subreg_offset = 32767, reladdr = 0x7fffa29e6ed0, stride = 177 '\261'}, 
>          delta_xy = {{<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, 
>                  address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, 
>                      pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 8}, subreg_offset = 0, reladdr = 0x7fffa29e6ec0, stride = 144 '\220'}, 
>            {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 1, address_mode = 1, 
>                  pad0 = 1, subnr = 13, nr = 41630, {{swizzle = 255, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, 
>                    f = 4.59163468e-41, d = 32767, ud = 32767}}, reg_offset = 15616}, subreg_offset = 629676489, reladdr = 0x7ffed26c4b68, 
>              stride = 0 '\000'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, 
>                  address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, 
>                      pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 1}, subreg_offset = 0, reladdr = 0x7ffed26b74e8, stride = 16 '\020'}, 
>            {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_V, file = UNIFORM, negate = 0, abs = 1, address_mode = 1, pad0 = 0, subnr = 9, 
>                  nr = 53868, {{swizzle = 254, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59149455e-41, 
>                    d = 32766, ud = 32766}}, reg_offset = 26357}, subreg_offset = 32767, reladdr = 0x7fffa29e6eb0, stride = 160 '\240'}, 
>            {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = UNIFORM, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 14, 
>                  nr = 41630, {{swizzle = 255, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59163468e-41, 
>                    d = 32767, ud = 32767}}, reg_offset = 54064}, subreg_offset = 32766, reladdr = 0x1000, stride = 40 '('}, {<backend_reg> = {<brw_reg> = {
>                  type = BRW_REGISTER_TYPE_W, file = BRW_MESSAGE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{
>                      swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, 
>                reg_offset = 4}, subreg_offset = 0, reladdr = 0x7b00000091, stride = 0 '\000'}}, shader_start_time = {<backend_reg> = {<brw_reg> = {
>                type = BRW_REGISTER_TYPE_UQ, file = BAD_FILE, negate = 0, abs = 0, address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, 
>                    writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 8}, 
>            subreg_offset = 0, reladdr = 0x7fffa29e6f80, stride = 32 ' '}, userplane = {{<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, 
>                  file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 1, address_mode = 0, pad0 = 1, subnr = 7, nr = 2, {{swizzle = 0, writemask = 0, 
>                      indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 13176}, subreg_offset = 0, 
>              reladdr = 0x7ffed3c18220, stride = 208 '\320'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UB, file = BRW_IMMEDIATE_VALUE, 
>                  negate = 0, abs = 1, address_mode = 1, pad0 = 0, subnr = 4, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, 
>                      width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 31196}, subreg_offset = 32767, reladdr = 0x20, 
>              stride = 24 '\030'}, {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = ATTR, negate = 0, abs = 1, address_mode = 1, pad0 = 0, 
>                  subnr = 6, nr = 2, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 0, d = 0, 
>                    ud = 0}}, reg_offset = 40008}, subreg_offset = 32766, reladdr = 0x7ffed322ac18, stride = 200 '\310'}, {<backend_reg> = {<brw_reg> = {
>                  type = BRW_REGISTER_TYPE_UD, file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 1, address_mode = 1, pad0 = 1, subnr = 13, 
>                  nr = 41630, {{swizzle = 255, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59163468e-41, 
>                    d = 32767, ud = 32767}}, reg_offset = 0}, subreg_offset = 0, reladdr = 0x7ffed2886c68, stride = 224 '\340'}, 
>            {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UD, file = BRW_IMMEDIATE_VALUE, negate = 1, abs = 0, address_mode = 0, pad0 = 0, 
>                  subnr = 12, nr = 53771, {{swizzle = 254, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, 
>                    f = 4.59149455e-41, d = 32766, ud = 32766}}, reg_offset = 21065}, subreg_offset = 32767, reladdr = 0x7fffa29e6fa0, stride = 0 '\000'}, 
>            {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_V, file = BRW_IMMEDIATE_VALUE, negate = 1, abs = 0, address_mode = 1, pad0 = 0, 
>                  subnr = 26, nr = 53849, {{swizzle = 254, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, 
>                    f = 4.59149455e-41, d = 32766, ud = 32766}}, reg_offset = 0}, subreg_offset = 0, reladdr = 0x0, stride = 1 '\001'}, 
>            {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_V, file = UNIFORM, negate = 1, abs = 1, address_mode = 1, pad0 = 1, subnr = 12, 
>                  nr = 53934, {{swizzle = 254, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59149455e-41, 
>                    d = 32766, ud = 32766}}, reg_offset = 32}, subreg_offset = 32767, reladdr = 0x530, stride = 40 '('}, {<backend_reg> = {<brw_reg> = {
>                  type = BRW_REGISTER_TYPE_UD, file = BRW_MESSAGE_REGISTER_FILE, negate = 0, abs = 0, address_mode = 1, pad0 = 0, subnr = 16, nr = 54209, {{
>                      swizzle = 254, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59149455e-41, d = 32766, 
>                    ud = 32766}}, reg_offset = 1320}, subreg_offset = 0, reladdr = 0x7ffed25c2828, stride = 152 '\230'}}, 
>          final_gs_vertex_count = {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_W, file = ATTR, negate = 0, abs = 0, address_mode = 0, pad0 = 0, 
>                subnr = 0, nr = 0, {{swizzle = 255, writemask = 15, indirect_offset = 7, vstride = 0, width = 0, hstride = 0, pad1 = 0}, f = 4.59163468e-41, 
>                  d = 32767, ud = 32767}}, reg_offset = 1360}, subreg_offset = 0, reladdr = 0x14, stride = 68 'D'}, 
>          control_data_bits = {<backend_reg> = {<brw_reg> = {type = BRW_REGISTER_TYPE_UW, file = BRW_ARCHITECTURE_REGISTER_FILE, negate = 0, abs = 0, 
>                address_mode = 0, pad0 = 0, subnr = 0, nr = 0, {{swizzle = 0, writemask = 0, indirect_offset = 0, vstride = 0, width = 0, hstride = 0, 
>                    pad1 = 0}, f = 0, d = 0, ud = 0}}, reg_offset = 93}, subreg_offset = 629676489, reladdr = 0x0, stride = 0 '\000'}, grf_used = 110, 
>          spilled_any_registers = 119, dispatch_width = 0, min_dispatch_width = 0, shader_time_index = 124, promoted_constants = 32767, bld = {
>            shader = 0x7fffe77e5000 <constant_fold_block>, block = 0x7fffa29e70d0, cursor = 0x7fff44000020, _dispatch_width = 146912, _group = 0, 
>            force_writemask_all = 119, annotation = {str = 0x7ffed3c18220 "", ir = 0x7ffed2718ae8}}}
>        g = {compiler = 0x0, log_data = 0x0, devinfo = 0x0, p = 0x7ffed2f9f6d8, key = 0x0, prog_data = 0x0, dispatch_width = 1, discard_halt_patches = {
>            head = 0x7fffa29e5570, tail = 0x0, tail_pred = 0x7fffa29e5568}, promoted_constants = 18, runtime_check_aads_emit = false, debug_flag = false, 
>          shader_name = 0x1 <error: Cannot access memory at address 0x1>, stage = MESA_SHADER_COMPUTE, mem_ctx = 0x7ffed5e18c08}
>        shader = 0x7ffed31b35d8
>        max_cs_threads = 70
>        cfg = 0x0
>#8  0x00007fffe784ac54 in brw_codegen_cs_prog (brw=brw@entry=0x8491338, prog=prog@entry=0x7fff44135448, cp=cp@entry=0x7ffed27887b0, 
>    key=key@entry=0x7fffa29e71b0) at ../../../../../../../src/mesa/drivers/dri/i965/brw_cs.c:124
>        ctx = 0x8491338
>        program = <optimized out>
>        mem_ctx = 0x7ffee2171278
>        program_size = 0
>        prog_data = {base = {binding_table = {size_bytes = 24, pull_constants_start = 6, texture_start = 1, gather_texture_start = 3503345872, 
>              ubo_start = 2, ssbo_start = 5, abo_start = 3503345872, image_start = 5, shader_time_start = 3503345872}, nr_params = 1, nr_pull_params = 0, 
>            nr_image_params = 1, curb_read_length = 1, total_scratch = 0, total_shared = 25088, dispatch_grf_start_reg = 4, use_alt_mode = false, 
>            param = 0x7ffed3be1848, pull_param = 0x7ffed3be1d78, image_param = 0x7ffed323d898}, dispatch_grf_start_reg_16 = 0, local_size = {32, 32, 1}, 
>          simd_size = 0, uses_barrier = true, uses_num_work_groups = false, local_invocation_id_regs = 3, binding_table = {work_groups_start = 0}}
>        start_busy = false
>        start_time = 0
>        cs = 0x7ffed25c2828
>        param_count = <optimized out>
>        st_index = <optimized out>
>        error_str = 0x1 <error: Cannot access memory at address 0x1>
>#9  0x00007fffe784b0c3 in brw_cs_precompile (ctx=0x8491338, shader_prog=0x7fff44135448, prog=0x7ffed27887b0)
>    at ../../../../../../../src/mesa/drivers/dri/i965/brw_cs.c:239
>        key = {program_string_id = 548, tex = {swizzles = {1672, 0 <repeats 31 times>}, gl_clamp_mask = {0, 0, 0}, gather_channel_quirk_mask = 0, 
>            compressed_multisample_layout_mask = 0, msaa_16 = 0, gen6_gather_wa = {(unknown: 0) <repeats 32 times>}}}
>        cp = 0x7ffed27887b0
>        old_prog_offset = 0
>        old_prog_data = 0x0
>        success = <optimized out>
>#10 0x00007fffe7852678 in brw_shader_precompile (sh_prog=<optimized out>, ctx=<optimized out>)
>    at ../../../../../../../src/mesa/drivers/dri/i965/brw_link.cpp:66
>        gs = 0x0
>        cs = 0x7ffed25c2828
>        vs = 0x0
>        tcs = 0x0
>        tes = 0x0
>        fs = 0x7fffa2972150
>#11 brw_link_shader (ctx=0x8491338, shProg=0x0) at ../../../../../../../src/mesa/drivers/dri/i965/brw_link.cpp:260
>No locals.
>#12 0x00007fffe76f0d86 in _mesa_glsl_link_shader (ctx=0x8491338, prog=0x7fff44135448) at ../../../../src/mesa/program/ir_to_mesa.cpp:3040
>        i = <optimized out>
>#13 0x00007fffe7605d4a in link_program (ctx=0x8491338, program=<optimized out>) at ../../../../src/mesa/main/shaderapi.c:1048
>        shProg = 0x7fff44135448
>#14 0x00000000009fe30b in ?? ()
>No symbol table info available.
>#15 0x00000000009fbcfc in ?? ()
>No symbol table info available.
>#16 0x0000000001108b29 in ?? ()
>No symbol table info available.
>#17 0x00000000010fd25a in ?? ()
>No symbol table info available.
>#18 0x000000000181254d in ?? ()
>No symbol table info available.
>#19 0x00000000012395ec in ?? ()
>No symbol table info available.
>#20 0x0000000000ce8ef3 in ?? ()
>No symbol table info available.
>#21 0x0000000000ce9135 in ?? ()
>No symbol table info available.
>#22 0x000000000137c58d in ?? ()
>No symbol table info available.
>#23 0x000000000137c5b7 in ?? ()
>No symbol table info available.
>#24 0x0000000000923d69 in ?? ()
>No symbol table info available.
>#25 0x0000000000b1dbd7 in ?? ()
>No symbol table info available.
>#26 0x00007ffff6ed80a4 in start_thread (arg=0x7fffa29e8700) at pthread_create.c:309
>        __res = <optimized out>
>        pd = 0x7fffa29e8700
>        now = <optimized out>
>        unwind_buf = {cancel_jmp_buf = {{jmp_buf = {140735921686272, -7254062393839813134, 1, 140737354125408, 0, 140735921686272, 7253928541436804594, 
>                7254042759281147378}, mask_was_saved = 0}}, priv = {pad = {0x0, 0x0, 0x0, 0x0}, data = {prev = 0x0, cleanup = 0x0, canceltype = 0}}}
>        not_first_call = <optimized out>
>        pagesize_m1 = <optimized out>
>        sp = <optimized out>
>        freesize = <optimized out>
>        __PRETTY_FUNCTION__ = "start_thread"
>#27 0x00007ffff53b387d in clone () at ../sysdeps/unix/sysv/linux/x86_64/clone.S:111
>No locals.
>(gdb) c
>Continuing.
>[Thread 0x7fffa2875700 (LWP 26666) exited]
>[Thread 0x7fffa28c6700 (LWP 26664) exited]
>[Thread 0x7fffa2023700 (LWP 26668) exited]
>[Thread 0x7fffa293f700 (LWP 26661) exited]
>[Thread 0x7fffa29a0700 (LWP 26660) exited]
>[Thread 0x7fffa29e8700 (LWP 26659) exited]
>[Thread 0x7fffe00b8700 (LWP 26658) exited]
>[Thread 0x7fffe0109700 (LWP 26645) exited]
>[Thread 0x7fffe015a700 (LWP 26644) exited]
>[Thread 0x7fffa3b3a700 (LWP 26642) exited]
>[Thread 0x7fffe01fc700 (LWP 26641) exited]
>[Thread 0x7fffe024d700 (LWP 26640) exited]
>[Thread 0x7fffe2ac8700 (LWP 26639) exited]
>[Thread 0x7fffa3f7b700 (LWP 26638) exited]
>[Thread 0x7fffa477c700 (LWP 26637) exited]
>[Thread 0x7fffe46cc700 (LWP 26636) exited]
>[Thread 0x7fffe51c6700 (LWP 26635) exited]
>[Thread 0x7fffe2a4f700 (LWP 26634) exited]
>[Thread 0x7ffff7fab700 (LWP 26633) exited]
>[Thread 0x7fffe9c15700 (LWP 26631) exited]
>[Thread 0x7ffff7faef00 (LWP 26627) exited]
>
>Program terminated with signal SIGSEGV, Segmentation fault.
>The program no longer exists.
>(gdb) q

Actions: View

Attachments on bug 93840: 121746 | 121900 | 121953 | 126122 | 126150

Use of freedesktop.org services, including Bugzilla, is subject to our Code of Conduct. How we collect and use information is described in our Privacy Policy.