Attachment 121979 Details for Bug 94242 – check_vm dump from ddebug-shader-dump branch

check_vm dump from ddebug-shader-dump branch

glretrace_1787_00000000 (text/plain), 226.17 KB, created by Michel Dänzer on 2016-02-26 09:08:13 UTC

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Creator: Michel Dänzer

Created: 2016-02-26 09:08:13 UTC

Size: 226.17 KB

patch

obsolete

>VM fault report.
>
>Driver vendor: X.Org
>Device vendor: AMD
>Device name: AMD KAVERI (DRM 2.43.0, LLVM 3.9.0)
>
>Failing VM page: 0x00000000
>
>[1;33mColor buffer 0:[0m
>  Info: npix_x=317, npix_y=88, npix_z=1, blk_w=1, blk_h=1, blk_d=1, array_size=1, last_level=0, bpe=4, nsamples=1, flags=0x100301, r8g8b8a8_unorm
>  Layout: size=163840, alignment=16384, bankw=1, bankh=1, nbanks=0, mtilea=2, tilesplit=512, pipeconfig=0, scanout=0
>  Level[0]: offset=0, slice_size=163840, npix_x=317, npix_y=88, npix_z=1, nblk_x=320, nblk_y=128, nblk_z=1, pitch_bytes=1280, mode=3
>
>SHADER KEY
>  instance_divisors = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
>  as_es = 0
>  as_ls = 0
>  export_prim_id = 0
>
>Vertex Shader as VS:
>Shader prolog disassembly:
>	v_add_i32_e32 v4, vcc, s10, v0 ; 4A08000A
>	v_mov_b32_e32 v5, v4           ; 7E0A0304
>Shader main disassembly:
>	s_load_dwordx4 s[0:3], s[8:9], 0x0                    ; C0800900
>	s_load_dwordx4 s[4:7], s[8:9], 0x4                    ; C0820904
>	s_waitcnt lgkmcnt(0)                                  ; BF8C007F
>	buffer_load_format_xyzw v[6:9], v4, s[0:3], 0 idxen   ; E00C2000 80000604
>	buffer_load_format_xyzw v[10:13], v5, s[4:7], 0 idxen ; E00C2000 80010A05
>	s_waitcnt vmcnt(0)                                    ; BF8C0F70
>	exp 15, 32, 0, 0, 0, v10, v11, v0, v0                 ; F800020F 00000B0A
>	exp 15, 12, 0, 1, 0, v6, v7, v8, v9                   ; F80008CF 09080706
>	s_waitcnt expcnt(0)                                   ; BF8C0F0F
>Shader epilog disassembly:
>	s_endpgm ; BF810000
>
>*** SHADER STATS ***
>SGPRS: 16
>VGPRS: 16
>Code Size: 64 bytes
>LDS: 0 blocks
>Scratch: 0 bytes per wave
>Max Waves: 10
>********************
>SHADER KEY
>  prolog.color_two_side = 0
>  prolog.poly_stipple = 0
>  prolog.force_persample_interp = 0
>  epilog.spi_shader_col_format = 0x4
>  epilog.color_is_int8 = 0x0
>  epilog.last_cbuf = 0
>  epilog.alpha_func = 7
>  epilog.alpha_to_one = 0
>  epilog.poly_line_smoothing = 0
>  epilog.clamp_color = 0
>
>Pixel Shader:
>Shader main disassembly:
>	s_wqm_b64 exec, exec                                                     ; BEFE0A7E
>	s_load_dwordx4 s[12:15], s[2:3], 0x0                                     ; C0860300
>	s_waitcnt lgkmcnt(0)                                                     ; BF8C007F
>	s_buffer_load_dword s0, s[12:15], 0x0                                    ; C2000D00
>	s_mov_b32 m0, s9                                                         ; BEFC0309
>	v_interp_p1_f32 v5, v2, 0, 0, [m0]                                       ; C8140002
>	v_mov_b32_e32 v7, -1                                                     ; 7E0E02C1
>	v_interp_p2_f32 v5, [v5], v3, 0, 0, [m0]                                 ; C8150003
>	v_interp_p1_f32 v6, v2, 1, 0, [m0]                                       ; C8180102
>	v_interp_p2_f32 v6, [v6], v3, 1, 0, [m0]                                 ; C8190103
>	s_waitcnt lgkmcnt(0)                                                     ; BF8C007F
>	v_cmp_lt_i32_e64 s[2:3], 9, s0                                           ; D1020002 00000089
>	v_cndmask_b32_e64 v4, 0, -1, s[2:3]                                      ; D2000004 00098280
>	s_cmp_lt_i32 s0, 10                                                      ; BF048A00
>	s_cbranch_scc1 BB0_3                                                     ; BF850000
>	v_mov_b32_e32 v2, s0                                                     ; 7E040200
>	s_buffer_load_dword s1, s[12:15], 0x8                                    ; C2008D08
>	s_buffer_load_dword s9, s[12:15], 0x9                                    ; C2048D09
>	v_cmp_eq_i32_e32 vcc, 10, v2                                             ; 7D04048A
>	s_and_b64 vcc, exec, vcc                                                 ; 87EA6A7E
>	s_waitcnt lgkmcnt(0)                                                     ; BF8C007F
>	v_mov_b32_e32 v0, s1                                                     ; 7E000201
>	v_mul_f32_e32 v5, s1, v5                                                 ; 100A0A01
>	v_mul_f32_e32 v1, s9, v6                                                 ; 10020C09
>	s_mov_b64 vcc, vcc                                                       ; BEEA046A
>	s_cbranch_vccnz BB0_6                                                    ; BF870000
>	v_cmp_eq_i32_e32 vcc, 11, v2                                             ; 7D04048B
>	s_and_b64 vcc, exec, vcc                                                 ; 87EA6A7E
>	s_cbranch_vccnz BB0_7                                                    ; BF870000
>	s_branch BB0_8                                                           ; BF820000
>	v_fract_f32_e32 v2, v5                                                   ; 7E044105
>	v_floor_f32_e32 v3, v5                                                   ; 7E064905
>	v_rcp_f32_e32 v4, v0                                                     ; 7E085500
>	v_rcp_f32_e32 v5, s9                                                     ; 7E0A5409
>	v_fract_f32_e32 v6, v1                                                   ; 7E0C4101
>	v_floor_f32_e32 v1, v1                                                   ; 7E024901
>	v_mac_f32_e32 v3, v4, v2                                                 ; 3E060504
>	v_mac_f32_e32 v1, v5, v6                                                 ; 3E020D05
>	v_mov_b32_e32 v5, v3                                                     ; 7E0A0303
>	s_branch BB0_6                                                           ; BF820000
>	v_cmp_ne_i32_e32 vcc, 12, v2                                             ; 7D0A048C
>	s_and_b64 vcc, exec, vcc                                                 ; 87EA6A7E
>	s_cbranch_vccnz BB0_10                                                   ; BF870000
>	v_cmp_le_f32_e32 vcc, 1.0, v5                                            ; 7C060AF2
>	s_and_saveexec_b64 s[2:3], vcc                                           ; BE82246A
>	s_xor_b64 s[2:3], exec, s[2:3]                                           ; 8982027E
>	s_buffer_load_dword s1, s[12:15], 0xa                                    ; C2008D0A
>	s_waitcnt lgkmcnt(0)                                                     ; BF8C007F
>	v_mul_f32_e32 v2, s1, v0                                                 ; 10040001
>	v_mad_f32 v2, -0.5, v2, 1.0                                              ; D2820002 03CA04F1
>	s_or_saveexec_b64 s[2:3], s[2:3]                                         ; BE822502
>	s_xor_b64 exec, exec, s[2:3]                                             ; 89FE027E
>	v_max_legacy_f32_e32 v2, 0, v5                                           ; 1C040A80
>	s_or_b64 exec, exec, s[2:3]                                              ; 88FE027E
>	v_cmp_le_f32_e32 vcc, 1.0, v1                                            ; 7C0602F2
>	s_and_saveexec_b64 s[2:3], vcc                                           ; BE82246A
>	s_xor_b64 s[2:3], exec, s[2:3]                                           ; 8982027E
>	s_buffer_load_dword s1, s[12:15], 0xb                                    ; C2008D0B
>	s_waitcnt lgkmcnt(0)                                                     ; BF8C007F
>	v_mov_b32_e32 v3, s1                                                     ; 7E060201
>	v_mul_f32_e32 v3, s9, v3                                                 ; 10060609
>	v_mad_f32 v3, -0.5, v3, 1.0                                              ; D2820003 03CA06F1
>	s_or_saveexec_b64 s[2:3], s[2:3]                                         ; BE822502
>	s_xor_b64 exec, exec, s[2:3]                                             ; 89FE027E
>	v_max_legacy_f32_e32 v3, 0, v1                                           ; 1C060280
>	s_or_b64 exec, exec, s[2:3]                                              ; 88FE027E
>	v_rcp_f32_e32 v1, v0                                                     ; 7E025500
>	v_rcp_f32_e32 v4, s9                                                     ; 7E085409
>	v_mul_f32_e32 v5, v1, v2                                                 ; 100A0501
>	v_mul_f32_e32 v1, v4, v3                                                 ; 10020704
>	s_branch BB0_6                                                           ; BF820000
>	v_cmp_eq_i32_e32 vcc, 13, v2                                             ; 7D04048D
>	s_and_b64 vcc, exec, vcc                                                 ; 87EA6A7E
>	s_cbranch_vccnz BB0_19                                                   ; BF870000
>	s_branch BB0_6                                                           ; BF820000
>	v_floor_f32_e32 v2, v5                                                   ; 7E044905
>	v_mul_f32_e64 v3, 0.5, |v2|                                              ; D2100203 000204F0
>	v_floor_f32_e32 v3, v3                                                   ; 7E064903
>	v_mad_f32 v2, -2.0, v3, |v2|                                             ; D2820402 040A06F5
>	v_sub_f32_e32 v3, 1.0, v2                                                ; 080604F2
>	v_fract_f32_e32 v2, v5                                                   ; 7E044105
>	v_mov_b32_e32 v4, 0x3a83126f                                             ; 7E0802FF 3A83126F
>	v_cmp_ngt_f32_e32 vcc, v4, v3                                            ; 7C160704
>	s_and_saveexec_b64 s[2:3], vcc                                           ; BE82246A
>	s_xor_b64 s[2:3], exec, s[2:3]                                           ; 8982027E
>	v_rcp_f32_e32 v3, s1                                                     ; 7E065401
>	v_mul_f32_e32 v5, v3, v2                                                 ; 100A0503
>	s_or_saveexec_b64 s[2:3], s[2:3]                                         ; BE822502
>	s_xor_b64 exec, exec, s[2:3]                                             ; 89FE027E
>	v_rcp_f32_e32 v3, s1                                                     ; 7E065401
>	v_sub_f32_e32 v2, 1.0, v2                                                ; 080404F2
>	v_mad_f32 v5, -v2, v3, 2.0                                               ; D2820005 23D20702
>	s_or_b64 exec, exec, s[2:3]                                              ; 88FE027E
>	v_floor_f32_e32 v2, v1                                                   ; 7E044901
>	v_mul_f32_e64 v3, 0.5, |v2|                                              ; D2100203 000204F0
>	v_floor_f32_e32 v3, v3                                                   ; 7E064903
>	v_mad_f32 v2, -2.0, v3, |v2|                                             ; D2820402 040A06F5
>	v_sub_f32_e32 v3, 1.0, v2                                                ; 080604F2
>	v_fract_f32_e32 v2, v1                                                   ; 7E044101
>	v_mov_b32_e32 v1, 0x3a83126f                                             ; 7E0202FF 3A83126F
>	v_cmp_ngt_f32_e32 vcc, v1, v3                                            ; 7C160701
>	s_and_saveexec_b64 s[2:3], vcc                                           ; BE82246A
>	s_xor_b64 s[2:3], exec, s[2:3]                                           ; 8982027E
>	v_rcp_f32_e32 v1, s9                                                     ; 7E025409
>	v_mul_f32_e32 v1, v1, v2                                                 ; 10020501
>	s_or_saveexec_b64 s[2:3], s[2:3]                                         ; BE822502
>	s_xor_b64 exec, exec, s[2:3]                                             ; 89FE027E
>	v_rcp_f32_e32 v1, s9                                                     ; 7E025409
>	v_sub_f32_e32 v2, 1.0, v2                                                ; 080404F2
>	v_mad_f32 v1, -v2, v1, 2.0                                               ; D2820001 23D20302
>	s_or_b64 exec, exec, s[2:3]                                              ; 88FE027E
>	v_cmp_eq_i32_e64 s[0:1], 10, s0                                          ; D1040000 0000008A
>	v_cndmask_b32_e64 v4, 0, -1, s[0:1]                                      ; D2000004 00018280
>	s_and_b64 vcc, exec, s[0:1]                                              ; 87EA007E
>	v_mov_b32_e32 v7, -1                                                     ; 7E0E02C1
>	v_mov_b32_e32 v6, v1                                                     ; 7E0C0301
>	s_cbranch_vccnz BB0_27                                                   ; BF870000
>	s_branch BB0_3                                                           ; BF820000
>	v_mov_b32_e32 v2, 0                                                      ; 7E040280
>	v_cmp_ngt_f32_e32 vcc, 0, v5                                             ; 7C160A80
>	v_cmp_gt_f32_e64 s[0:1], 0, v5                                           ; D0080000 00020A80
>	v_cmp_nle_f32_e64 s[2:3], 1.0, v5                                        ; D0180002 00020AF2
>	v_cmp_le_f32_e64 s[6:7], 1.0, v5                                         ; D0060006 00020AF2
>	s_or_b64 s[6:7], s[0:1], s[6:7]                                          ; 88860600
>	s_and_b64 s[2:3], vcc, s[2:3]                                            ; 8782026A
>	v_cmp_gt_f32_e32 vcc, 0, v1                                              ; 7C080280
>	v_cmp_ngt_f32_e64 s[0:1], 0, v1                                          ; D0160000 00020280
>	s_and_b64 s[2:3], s[2:3], s[0:1]                                         ; 87820002
>	s_or_b64 s[6:7], s[6:7], vcc                                             ; 88866A06
>	v_cmp_nle_f32_e32 vcc, 1.0, v1                                           ; 7C1802F2
>	v_cmp_le_f32_e64 s[0:1], 1.0, v1                                         ; D0060000 000202F2
>	s_or_b64 s[0:1], s[6:7], s[0:1]                                          ; 88800006
>	v_cndmask_b32_e64 v3, 0, -1, s[0:1]                                      ; D2000003 00018280
>	s_and_b64 s[0:1], s[2:3], vcc                                            ; 87806A02
>	v_mov_b32_e32 v7, 0                                                      ; 7E0E0280
>	v_mov_b32_e32 v6, v1                                                     ; 7E0C0301
>	v_mov_b32_e32 v4, 0                                                      ; 7E080280
>	s_and_saveexec_b64 s[0:1], s[0:1]                                        ; BE802400
>	s_xor_b64 s[0:1], exec, s[0:1]                                           ; 8980007E
>	v_cmp_ne_i32_e32 vcc, 0, v3                                              ; 7D0A0680
>	v_cndmask_b32_e64 v4, 0, -1, vcc                                         ; D2000004 01A98280
>	v_rcp_f32_e32 v0, v0                                                     ; 7E005500
>	v_rcp_f32_e32 v2, s9                                                     ; 7E045409
>	v_fract_f32_e32 v3, v5                                                   ; 7E064105
>	v_fract_f32_e32 v6, v1                                                   ; 7E0C4101
>	v_mul_f32_e32 v5, v0, v3                                                 ; 100A0700
>	v_mul_f32_e32 v6, v2, v6                                                 ; 100C0D02
>	v_mov_b32_e32 v7, -1                                                     ; 7E0E02C1
>	v_mov_b32_e32 v2, v1                                                     ; 7E040301
>	s_or_b64 exec, exec, s[0:1]                                              ; 88FE007E
>	v_mov_b32_e32 v1, v2                                                     ; 7E020302
>	v_mov_b32_e32 v2, 0                                                      ; 7E040280
>	v_cmp_ne_i32_e32 vcc, 0, v7                                              ; 7D0A0E80
>	v_mov_b32_e32 v3, 0                                                      ; 7E060280
>	s_and_saveexec_b64 s[0:1], vcc                                           ; BE80246A
>	s_xor_b64 s[0:1], exec, s[0:1]                                           ; 8980007E
>	s_load_dwordx8 s[12:19], s[4:5], 0x0                                     ; C0C60500
>	s_load_dwordx4 s[20:23], s[4:5], 0xc                                     ; C08A050C
>	s_waitcnt lgkmcnt(0)                                                     ; BF8C007F
>	image_sample v[4:7], 15, 0, 0, 0, 0, 0, 0, 0, v[5:6], s[12:19], s[20:23] ; F0800F00 00A30405
>	s_waitcnt vmcnt(0)                                                       ; BF8C0F70
>	v_mov_b32_e32 v1, v5                                                     ; 7E020305
>	v_mov_b32_e32 v2, v6                                                     ; 7E040306
>	v_mov_b32_e32 v3, v7                                                     ; 7E060307
>	s_or_b64 exec, exec, s[0:1]                                              ; 88FE007E
>	v_mov_b32_e32 v0, v4                                                     ; 7E000304
>Shader epilog disassembly:
>	v_cvt_pkrtz_f16_f32_e32 v0, v0, v1 ; 5E000300
>	v_cvt_pkrtz_f16_f32_e32 v1, v2, v3 ; 5E020702
>	exp 15, 0, 1, 1, 1, v0, v1, v0, v0 ; F8001C0F 00000100
>	s_endpgm                           ; BF810000
>
>*** SHADER CONFIG ***
>SPI_PS_INPUT_ADDR = 0xd077
>SPI_PS_INPUT_ENA  = 0x0002
>*** SHADER STATS ***
>SGPRS: 32
>VGPRS: 15
>Code Size: 772 bytes
>LDS: 0 blocks
>Scratch: 0 bytes per wave
>Max Waves: 10
>********************
>Buffer list (in units of pages = 4kB):
>[1;33m        Size    VM start page         VM end page           Usage[0m
>           1    0x0000000000811       0x0000000000812       TRACE
>           1    -- hole --
>          16    0x0000000000813       0x0000000000823       BORDER_COLORS
>           1    0x0000000000823       0x0000000000824       IB2
>           1    -- hole --
>           1    0x0000000000825       0x0000000000826       CONST_BUFFER
>          29    -- hole --
>           1    0x0000000000843       0x0000000000844       USER_SHADER
>         780    -- hole --
>         256    0x0000000000b50       0x0000000000c50       CONST_BUFFER, DESCRIPTORS
>          16    0x0000000000c50       0x0000000000c60       VERTEX_BUFFER
>           4    -- hole --
>           1    0x0000000000c64       0x0000000000c65       USER_SHADER
>          19    -- hole --
>         128    0x0000000000c78       0x0000000000cf8       VERTEX_BUFFER
>        1888    -- hole --
>           5    0x0000000001458       0x000000000145d       SAMPLER_TEXTURE, COLOR_BUFFER
>          19    -- hole --
>           5    0x0000000001470       0x0000000001475       SAMPLER_TEXTURE, COLOR_BUFFER
>          87    -- hole --
>          40    0x00000000014cc       0x00000000014f4       COLOR_BUFFER
>          11    0x00000000014f4       0x00000000014ff       SAMPLER_TEXTURE
>          11    -- hole --
>           1    0x000000000150a       0x000000000150b       USER_SHADER
>         261    -- hole --
>           2    0x0000000001610       0x0000000001612       SAMPLER_TEXTURE
>          10    -- hole --
>           2    0x000000000161c       0x000000000161e       SAMPLER_TEXTURE
>          66    -- hole --
>           1    0x0000000001660       0x0000000001661       USER_SHADER
>           5    -- hole --
>           1    0x0000000001666       0x0000000001667       USER_SHADER
>           1    0x0000000001667       0x0000000001668       USER_SHADER
>           2    -- hole --
>           1    0x000000000166a       0x000000000166b       USER_SHADER
>           1    0x000000000166b       0x000000000166c       USER_SHADER
>          96    -- hole --
>           2    0x00000000016cc       0x00000000016ce       SAMPLER_TEXTURE, COLOR_BUFFER
>           8    -- hole --
>           1    0x00000000016d6       0x00000000016d7       USER_SHADER
>           1    0x00000000016d7       0x00000000016d8       USER_SHADER
>         776    -- hole --
>         256    0x00000000019e0       0x0000000001ae0       CONST_BUFFER, DESCRIPTORS
>
>Note: The holes represent memory not used by the IB.
>      Other buffers can still be allocated there.
>
>------------------ IB2: Init config begin ------------------
>[1;32mCONTEXT_CONTROL[0m:
>        0x80000000
>        0x80000000
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_HOS_MAX_TESS_LEVEL[0m <- 64.0f (0x42800000)
>        [1;33mVGT_HOS_MIN_TESS_LEVEL[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_PER_ES[0m <- GS_PER_ES = 128 (0x80)
>        [1;33mVGT_ES_PER_GS[0m <- ES_PER_GS = 64 (0x40)
>        [1;33mVGT_GS_PER_VS[0m <- GS_PER_VS = 2
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_RESET[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_STRMOUT_DRAW_OPAQUE_OFFSET[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_STRMOUT_BUFFER_CONFIG[0m <- STREAM_0_BUFFER_EN = 0
>                                     STREAM_1_BUFFER_EN = 0
>                                     STREAM_2_BUFFER_EN = 0
>                                     STREAM_3_BUFFER_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_VTX_CNT_EN[0m <- VTX_CNT_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_CENTROID_PRIORITY_0[0m <- DISTANCE_0 = 0
>                                     DISTANCE_1 = 1
>                                     DISTANCE_2 = 2
>                                     DISTANCE_3 = 3
>                                     DISTANCE_4 = 4
>                                     DISTANCE_5 = 5
>                                     DISTANCE_6 = 6
>                                     DISTANCE_7 = 7
>        [1;33mPA_SC_CENTROID_PRIORITY_1[0m <- DISTANCE_8 = 8
>                                     DISTANCE_9 = 9
>                                     DISTANCE_10 = 10 (0xa)
>                                     DISTANCE_11 = 11 (0xb)
>                                     DISTANCE_12 = 12 (0xc)
>                                     DISTANCE_13 = 13 (0xd)
>                                     DISTANCE_14 = 14 (0xe)
>                                     DISTANCE_15 = 15 (0xf)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_PRIM_FILTER_CNTL[0m <- TRIANGLE_FILTER_DISABLE = 0
>                                  LINE_FILTER_DISABLE = 0
>                                  POINT_FILTER_DISABLE = 0
>                                  RECTANGLE_FILTER_DISABLE = 0
>                                  TRIANGLE_EXPAND_ENA = 0
>                                  LINE_EXPAND_ENA = 0
>                                  POINT_EXPAND_ENA = 0
>                                  RECTANGLE_EXPAND_ENA = 0
>                                  PRIM_EXPAND_CONSTANT = 0
>                                  XMAX_RIGHT_EXCLUSION = 0
>                                  YMAX_BOTTOM_EXCLUSION = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_VPORT_ZMIN_0[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_0[0m <- 1.0f (0x3f800000)
>        [1;33mPA_SC_VPORT_ZMIN_1[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_1[0m <- 1.0f (0x3f800000)
>        [1;33mPA_SC_VPORT_ZMIN_2[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_2[0m <- 1.0f (0x3f800000)
>        [1;33mPA_SC_VPORT_ZMIN_3[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_3[0m <- 1.0f (0x3f800000)
>        [1;33mPA_SC_VPORT_ZMIN_4[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_4[0m <- 1.0f (0x3f800000)
>        [1;33mPA_SC_VPORT_ZMIN_5[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_5[0m <- 1.0f (0x3f800000)
>        [1;33mPA_SC_VPORT_ZMIN_6[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_6[0m <- 1.0f (0x3f800000)
>        [1;33mPA_SC_VPORT_ZMIN_7[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_7[0m <- 1.0f (0x3f800000)
>        [1;33mPA_SC_VPORT_ZMIN_8[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_8[0m <- 1.0f (0x3f800000)
>        [1;33mPA_SC_VPORT_ZMIN_9[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_9[0m <- 1.0f (0x3f800000)
>        [1;33mPA_SC_VPORT_ZMIN_10[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_10[0m <- 1.0f (0x3f800000)
>        [1;33mPA_SC_VPORT_ZMIN_11[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_11[0m <- 1.0f (0x3f800000)
>        [1;33mPA_SC_VPORT_ZMIN_12[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_12[0m <- 1.0f (0x3f800000)
>        [1;33mPA_SC_VPORT_ZMIN_13[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_13[0m <- 1.0f (0x3f800000)
>        [1;33mPA_SC_VPORT_ZMIN_14[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_14[0m <- 1.0f (0x3f800000)
>        [1;33mPA_SC_VPORT_ZMIN_15[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_15[0m <- 1.0f (0x3f800000)
>        [1;33mPA_SC_RASTER_CONFIG[0m <- RB_MAP_PKR0 = RASTER_CONFIG_RB_MAP_0
>                               RB_MAP_PKR1 = RASTER_CONFIG_RB_MAP_0
>                               RB_XSEL2 = RASTER_CONFIG_RB_XSEL2_0
>                               RB_XSEL = 0
>                               RB_YSEL = 0
>                               PKR_MAP = RASTER_CONFIG_PKR_MAP_0
>                               PKR_XSEL = RASTER_CONFIG_PKR_XSEL_0
>                               PKR_YSEL = RASTER_CONFIG_PKR_YSEL_0
>                               PKR_XSEL2 = RASTER_CONFIG_PKR_XSEL2_0
>                               SC_MAP = RASTER_CONFIG_SC_MAP_0
>                               SC_XSEL = RASTER_CONFIG_SC_XSEL_8_WIDE_TILE
>                               SC_YSEL = RASTER_CONFIG_SC_YSEL_8_WIDE_TILE
>                               SE_MAP = RASTER_CONFIG_SE_MAP_0
>                               SE_XSEL = RASTER_CONFIG_SE_XSEL_8_WIDE_TILE
>                               SE_YSEL = RASTER_CONFIG_SE_YSEL_8_WIDE_TILE
>        [1;33mPA_SC_RASTER_CONFIG_1[0m <- SE_PAIR_MAP = RASTER_CONFIG_SE_PAIR_MAP_0
>                                 SE_PAIR_XSEL = RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE
>                                 SE_PAIR_YSEL = RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_TL[0m <- TL_X = 0
>                                   TL_Y = 0
>                                   WINDOW_OFFSET_DISABLE = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_GENERIC_SCISSOR_TL[0m <- TL_X = 0
>                                    TL_Y = 0
>                                    WINDOW_OFFSET_DISABLE = 1
>        [1;33mPA_SC_GENERIC_SCISSOR_BR[0m <- BR_X = 16384 (0x4000)
>                                    BR_Y = 16384 (0x4000)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_SCREEN_SCISSOR_TL[0m <- TL_X = 0
>                                   TL_Y = 0
>        [1;33mPA_SC_SCREEN_SCISSOR_BR[0m <- BR_X = 16384 (0x4000)
>                                   BR_Y = 16384 (0x4000)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_CLIPRECT_RULE[0m <- CLIP_RULE = 0xffff
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_EDGERULE[0m <- ER_TRI = 10 (0xa)
>                          ER_POINT = 10 (0xa)
>                          ER_RECT = 10 (0xa)
>                          ER_LINE_LR = 42 (0x2a)
>                          ER_LINE_RL = 42 (0x2a)
>                          ER_LINE_TB = 10 (0xa)
>                          ER_LINE_BT = 10 (0xa)
>        [1;33mPA_SU_HARDWARE_SCREEN_OFFSET[0m <- HW_SCREEN_OFFSET_X = 0
>                                        HW_SCREEN_OFFSET_Y = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_NANINF_CNTL[0m <- VTE_XY_INF_DISCARD = 0
>                             VTE_Z_INF_DISCARD = 0
>                             VTE_W_INF_DISCARD = 0
>                             VTE_0XNANINF_IS_0 = 0
>                             VTE_XY_NAN_RETAIN = 0
>                             VTE_Z_NAN_RETAIN = 0
>                             VTE_W_NAN_RETAIN = 0
>                             VTE_W_RECIP_NAN_IS_0 = 0
>                             VS_XY_NAN_TO_INF = 0
>                             VS_XY_INF_RETAIN = 0
>                             VS_Z_NAN_TO_INF = 0
>                             VS_Z_INF_RETAIN = 0
>                             VS_W_NAN_TO_INF = 0
>                             VS_W_INF_RETAIN = 0
>                             VS_CLIP_DIST_INF_DISCARD = 0
>                             VTE_NO_OUTPUT_NEG_0 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_GB_VERT_CLIP_ADJ[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_GB_VERT_DISC_ADJ[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_GB_HORZ_CLIP_ADJ[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_GB_HORZ_DISC_ADJ[0m <- 1.0f (0x3f800000)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SRESULTS_COMPARE_STATE0[0m <- COMPAREFUNC0 = REF_NEVER
>                                      COMPAREVALUE0 = 0
>                                      COMPAREMASK0 = 0
>                                      ENABLE0 = 0
>        [1;33mDB_SRESULTS_COMPARE_STATE1[0m <- COMPAREFUNC1 = REF_NEVER
>                                      COMPAREVALUE1 = 0
>                                      COMPAREMASK1 = 0
>                                      ENABLE1 = 0
>        [1;33mDB_PRELOAD_CONTROL[0m <- START_X = 0
>                              START_Y = 0
>                              MAX_X = 0
>                              MAX_Y = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE[0m <- FORCE_HIZ_ENABLE = FORCE_OFF
>                              FORCE_HIS_ENABLE0 = FORCE_DISABLE
>                              FORCE_HIS_ENABLE1 = FORCE_DISABLE
>                              FORCE_SHADER_Z_ORDER = 0
>                              FAST_Z_DISABLE = 0
>                              FAST_STENCIL_DISABLE = 0
>                              NOOP_CULL_DISABLE = 0
>                              FORCE_COLOR_KILL = 0
>                              FORCE_Z_READ = 0
>                              FORCE_STENCIL_READ = 0
>                              FORCE_FULL_Z_RANGE = FORCE_OFF
>                              FORCE_QC_SMASK_CONFLICT = 0
>                              DISABLE_VIEWPORT_CLAMP = 0
>                              IGNORE_SC_ZRANGE = 0
>                              DISABLE_FULLY_COVERED = 0
>                              FORCE_Z_LIMIT_SUMM = FORCE_SUMM_OFF
>                              MAX_TILES_IN_DTT = 0
>                              DISABLE_TILE_RATE_TILES = 0
>                              FORCE_Z_DIRTY = 0
>                              FORCE_STENCIL_DIRTY = 0
>                              FORCE_Z_VALID = 0
>                              FORCE_STENCIL_VALID = 0
>                              PRESERVE_COMPRESSION = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_MAX_VTX_INDX[0m <- 0xffffffff
>        [1;33mVGT_MIN_VTX_INDX[0m <- 0
>        [1;33mVGT_INDX_OFFSET[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_RSRC3_HS[0m <- WAVE_LIMIT = 0
>                                   LOCK_LOW_THRESHOLD = 0
>                                   GROUP_FIFO_DEPTH = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_RSRC3_ES[0m <- CU_EN = 0xffff
>                                   WAVE_LIMIT = 0
>                                   LOCK_LOW_THRESHOLD = 0
>                                   GROUP_FIFO_DEPTH = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_RSRC3_GS[0m <- CU_EN = 0xffff
>                                   WAVE_LIMIT = 0
>                                   LOCK_LOW_THRESHOLD = 0
>                                   GROUP_FIFO_DEPTH = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_RSRC3_LS[0m <- CU_EN = 0xfffe
>                                   WAVE_LIMIT = 0
>                                   LOCK_LOW_THRESHOLD = 0
>                                   GROUP_FIFO_DEPTH = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_RSRC3_VS[0m <- CU_EN = 0xfffe
>                                   WAVE_LIMIT = 0
>                                   LOCK_LOW_THRESHOLD = 0
>        [1;33mSPI_SHADER_LATE_ALLOC_VS[0m <- LIMIT = 31 (0x1f)
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_RSRC3_PS[0m <- CU_EN = 0xffff
>                                   WAVE_LIMIT = 0
>                                   LOCK_LOW_THRESHOLD = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mTA_BC_BASE_ADDR[0m <- 0x00008130
>        [1;33mTA_BC_BASE_ADDR_HI[0m <- ADDRESS = 0
>------------------- IB2: Init config end -------------------
>
>------------------ IB begin ------------------
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00811000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x00000001
>[1;32mNOP[0m:
>        [31mTrace point ID: 1
>        [31mThis trace point was reached by the CP.[0m
>[1;32mINDIRECT_BUFFER_CIK[0m:
>        0x00823000
>        0x00000000
>        0x00000088
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 1
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 1
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_STRMOUT_BUFFER_CONFIG[0m <- STREAM_0_BUFFER_EN = 0
>                                     STREAM_1_BUFFER_EN = 0
>                                     STREAM_2_BUFFER_EN = 0
>                                     STREAM_3_BUFFER_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_STRMOUT_CONFIG[0m <- STREAMOUT_0_EN = 0
>                              STREAMOUT_1_EN = 0
>                              STREAMOUT_2_EN = 0
>                              STREAMOUT_3_EN = 0
>                              RAST_STREAM = 0
>                              RAST_STREAM_MASK = 0
>                              USE_RAST_STREAM_MASK = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_BASE[0m <- 0x00014700
>        [1;33mCB_COLOR0_PITCH[0m <- TILE_MAX = 23 (0x17)
>                           FMASK_TILE_MAX = 23 (0x17)
>        [1;33mCB_COLOR0_SLICE[0m <- TILE_MAX = 71 (0x00047)
>        [1;33mCB_COLOR0_VIEW[0m <- SLICE_START = 0
>                          SLICE_MAX = 0
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_8_8_8_8
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 1
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>        [1;33mCB_COLOR0_ATTRIB[0m <- TILE_MODE_INDEX = 13 (0xd)
>                            FMASK_TILE_MODE_INDEX = 13 (0xd)
>                            FMASK_BANK_HEIGHT = 0
>                            NUM_SAMPLES = 0
>                            NUM_FRAGMENTS = 0
>                            FORCE_DST_ALPHA_1 = 0
>        [1;33mCB_COLOR0_DCC_CONTROL[0m <- OVERWRITE_COMBINER_DISABLE = 0
>                                 KEY_CLEAR_ENABLE = 0
>                                 MAX_UNCOMPRESSED_BLOCK_SIZE = 0
>                                 MIN_COMPRESSED_BLOCK_SIZE = 0
>                                 MAX_COMPRESSED_BLOCK_SIZE = 0
>                                 COLOR_TRANSFORM = 0
>                                 INDEPENDENT_64B_BLOCKS = 0
>                                 LOSSY_RGB_PRECISION = 0
>                                 LOSSY_ALPHA_PRECISION = 0
>        [1;33mCB_COLOR0_CMASK[0m <- 0x00014700
>        [1;33mCB_COLOR0_CMASK_SLICE[0m <- TILE_MAX = 0
>        [1;33mCB_COLOR0_FMASK[0m <- 0x00014700
>        [1;33mCB_COLOR0_FMASK_SLICE[0m <- TILE_MAX = 71 (0x00047)
>        [1;33mCB_COLOR0_CLEAR_WORD0[0m <- 0
>        [1;33mCB_COLOR0_CLEAR_WORD1[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR1_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_8_8_8_8
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 1
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR2_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_INVALID
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR3_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_INVALID
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR4_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_INVALID
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR5_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_INVALID
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR6_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_INVALID
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR7_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_INVALID
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_Z_INFO[0m <- FORMAT = Z_INVALID
>                     NUM_SAMPLES = 0
>                     TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                     TILE_MODE_INDEX = 0
>                     DECOMPRESS_ON_N_ZPLANES = 0
>                     ALLOW_EXPCLEAR = 0
>                     READ_SIZE = 0
>                     TILE_SURFACE_ENABLE = 0
>                     CLEAR_DISALLOWED = 0
>                     ZRANGE_PRECISION = 0
>        [1;33mDB_STENCIL_INFO[0m <- FORMAT = STENCIL_INVALID
>                           TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                           TILE_MODE_INDEX = 0
>                           ALLOW_EXPCLEAR = 0
>                           TILE_STENCIL_DISABLE = 0
>                           CLEAR_DISALLOWED = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 163 (0x0a3)
>                                   BR_Y = 22 (0x016)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0[0m <- S0_X = 14 (0xe)
>                                             S0_Y = 11 (0xb)
>                                             S1_X = 3
>                                             S1_Y = 12 (0xc)
>                                             S2_X = 15 (0xf)
>                                             S2_Y = 5
>                                             S3_X = 10 (0xa)
>                                             S3_Y = 14 (0xe)
>        [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1[0m <- S4_X = 6
>                                             S4_Y = 0
>                                             S5_X = 0
>                                             S5_Y = 0
>                                             S6_X = 11 (0xb)
>                                             S6_Y = 3
>                                             S7_X = 4
>                                             S7_Y = 4
>        [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2[0m <- S8_X = 0
>                                             S8_Y = 0
>                                             S9_X = 0
>                                             S9_Y = 0
>                                             S10_X = 0
>                                             S10_Y = 0
>                                             S11_X = 0
>                                             S11_Y = 0
>        [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3[0m <- S12_X = 0
>                                             S12_Y = 0
>                                             S13_X = 0
>                                             S13_Y = 0
>                                             S14_X = 0
>                                             S14_Y = 0
>                                             S15_X = 0
>                                             S15_Y = 0
>        [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0[0m <- S0_X = 14 (0xe)
>                                             S0_Y = 11 (0xb)
>                                             S1_X = 3
>                                             S1_Y = 12 (0xc)
>                                             S2_X = 15 (0xf)
>                                             S2_Y = 5
>                                             S3_X = 10 (0xa)
>                                             S3_Y = 14 (0xe)
>        [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1[0m <- S4_X = 6
>                                             S4_Y = 0
>                                             S5_X = 0
>                                             S5_Y = 0
>                                             S6_X = 11 (0xb)
>                                             S6_Y = 3
>                                             S7_X = 4
>                                             S7_Y = 4
>        [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2[0m <- S8_X = 0
>                                             S8_Y = 0
>                                             S9_X = 0
>                                             S9_Y = 0
>                                             S10_X = 0
>                                             S10_Y = 0
>                                             S11_X = 0
>                                             S11_Y = 0
>        [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3[0m <- S12_X = 0
>                                             S12_Y = 0
>                                             S13_X = 0
>                                             S13_Y = 0
>                                             S14_X = 0
>                                             S14_Y = 0
>                                             S15_X = 0
>                                             S15_Y = 0
>        [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0[0m <- S0_X = 14 (0xe)
>                                             S0_Y = 11 (0xb)
>                                             S1_X = 3
>                                             S1_Y = 12 (0xc)
>                                             S2_X = 15 (0xf)
>                                             S2_Y = 5
>                                             S3_X = 10 (0xa)
>                                             S3_Y = 14 (0xe)
>        [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1[0m <- S4_X = 6
>                                             S4_Y = 0
>                                             S5_X = 0
>                                             S5_Y = 0
>                                             S6_X = 11 (0xb)
>                                             S6_Y = 3
>                                             S7_X = 4
>                                             S7_Y = 4
>        [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2[0m <- S8_X = 0
>                                             S8_Y = 0
>                                             S9_X = 0
>                                             S9_Y = 0
>                                             S10_X = 0
>                                             S10_Y = 0
>                                             S11_X = 0
>                                             S11_Y = 0
>        [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3[0m <- S12_X = 0
>                                             S12_Y = 0
>                                             S13_X = 0
>                                             S13_Y = 0
>                                             S14_X = 0
>                                             S14_Y = 0
>                                             S15_X = 0
>                                             S15_Y = 0
>        [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0[0m <- S0_X = 14 (0xe)
>                                             S0_Y = 11 (0xb)
>                                             S1_X = 3
>                                             S1_Y = 12 (0xc)
>                                             S2_X = 15 (0xf)
>                                             S2_Y = 5
>                                             S3_X = 10 (0xa)
>                                             S3_Y = 14 (0xe)
>        [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1[0m <- S4_X = 6
>                                             S4_Y = 0
>                                             S5_X = 0
>                                             S5_Y = 0
>                                             S6_X = 11 (0xb)
>                                             S6_Y = 3
>                                             S7_X = 4
>                                             S7_Y = 4
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 0
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_LATE_Z
>                             KILL_ENABLE = 0
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>                             DUAL_QUAD_DISABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_LINE_CNTL[0m <- EXPAND_LINE_WIDTH = 0
>                           LAST_PIXEL = 1
>                           PERPENDICULAR_ENDCAP_ENA = 0
>                           DX10_DIAMOND_TEST_ENA = 0
>        [1;33mPA_SC_AA_CONFIG[0m <- MSAA_NUM_SAMPLES = 0
>                           AA_MASK_CENTROID_DTMN = 0
>                           MAX_SAMPLE_DIST = 0
>                           MSAA_EXPOSED_SAMPLES = 0
>                           DETAIL_TO_EXPOSED_MODE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_EQAA[0m <- MAX_ANCHOR_SAMPLES = 0
>                   PS_ITER_SAMPLES = 0
>                   MASK_EXPORT_NUM_SAMPLES = 0
>                   ALPHA_TO_MASK_NUM_SAMPLES = 0
>                   HIGH_QUALITY_INTERSECTIONS = 1
>                   INCOHERENT_EQAA_READS = 0
>                   INTERPOLATE_COMP_Z = 0
>                   INTERPOLATE_SRC_Z = 0
>                   STATIC_ANCHOR_ASSOCIATIONS = 1
>                   ALPHA_TO_MASK_EQAA_DISABLE = 0
>                   OVERRASTERIZATION_AMOUNT = 0
>                   ENABLE_POSTZ_OVERRASTERIZATION = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_1[0m <- WALK_SIZE = 0
>                             WALK_ALIGNMENT = 0
>                             WALK_ALIGN8_PRIM_FITS_ST = 0
>                             WALK_FENCE_ENABLE = 0
>                             WALK_FENCE_SIZE = 0
>                             SUPERTILE_WALK_ORDER_ENABLE = 0
>                             TILE_WALK_ORDER_ENABLE = 0
>                             TILE_COVER_DISABLE = 0
>                             TILE_COVER_NO_SCISSOR = 0
>                             ZMM_LINE_EXTENT = 0
>                             ZMM_LINE_OFFSET = 0
>                             ZMM_RECT_EXTENT = 0
>                             KILL_PIX_POST_HI_Z = 0
>                             KILL_PIX_POST_DETAIL_MASK = 0
>                             PS_ITER_SAMPLE = 0
>                             MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE = 0
>                             MULTI_GPU_SUPERTILE_ENABLE = 0
>                             GPU_ID_OVERRIDE_ENABLE = 0
>                             GPU_ID_OVERRIDE = 0
>                             MULTI_GPU_PRIM_DISCARD_ENABLE = 0
>                             FORCE_EOV_CNTDWN_ENABLE = 1
>                             FORCE_EOV_REZ_ENABLE = 1
>                             OUT_OF_ORDER_PRIMITIVE_ENABLE = 0
>                             OUT_OF_ORDER_WATER_MARK = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_AA_MASK_X0Y0_X1Y0[0m <- AA_MASK_X0Y0 = 0xffff
>                                   AA_MASK_X1Y0 = 0xffff
>        [1;33mPA_SC_AA_MASK_X0Y1_X1Y1[0m <- AA_MASK_X0Y1 = 0xffff
>                                   AA_MASK_X1Y1 = 0xffff
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15 (0xf)
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND_RED[0m <- 0
>        [1;33mCB_BLEND_GREEN[0m <- 0
>        [1;33mCB_BLEND_BLUE[0m <- 0
>        [1;33mCB_BLEND_ALPHA[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_REUSE_OFF[0m <- REUSE_OFF = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_UCP_0_X[0m <- 0
>        [1;33mPA_CL_UCP_0_Y[0m <- 0
>        [1;33mPA_CL_UCP_0_Z[0m <- 0
>        [1;33mPA_CL_UCP_0_W[0m <- 0
>        [1;33mPA_CL_UCP_1_X[0m <- 0
>        [1;33mPA_CL_UCP_1_Y[0m <- 0
>        [1;33mPA_CL_UCP_1_Z[0m <- 0
>        [1;33mPA_CL_UCP_1_W[0m <- 0
>        [1;33mPA_CL_UCP_2_X[0m <- 0
>        [1;33mPA_CL_UCP_2_Y[0m <- 0
>        [1;33mPA_CL_UCP_2_Z[0m <- 0
>        [1;33mPA_CL_UCP_2_W[0m <- 0
>        [1;33mPA_CL_UCP_3_X[0m <- 0
>        [1;33mPA_CL_UCP_3_Y[0m <- 0
>        [1;33mPA_CL_UCP_3_Z[0m <- 0
>        [1;33mPA_CL_UCP_3_W[0m <- 0
>        [1;33mPA_CL_UCP_4_X[0m <- 0
>        [1;33mPA_CL_UCP_4_Y[0m <- 0
>        [1;33mPA_CL_UCP_4_Z[0m <- 0
>        [1;33mPA_CL_UCP_4_W[0m <- 0
>        [1;33mPA_CL_UCP_5_X[0m <- 0
>        [1;33mPA_CL_UCP_5_Y[0m <- 0
>        [1;33mPA_CL_UCP_5_Z[0m <- 0
>        [1;33mPA_CL_UCP_5_W[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_0[0m <- 0x01a75e00
>        [1;33mSPI_SHADER_USER_DATA_VS_1[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x01a74c00
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_4[0m <- 0x00b50400
>        [1;33mSPI_SHADER_USER_DATA_VS_5[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_0[0m <- 0x00b50b00
>        [1;33mSPI_SHADER_USER_DATA_PS_1[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x01a76900
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x01a76b00
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_GS_0[0m <- 0x00b51300
>        [1;33mSPI_SHADER_USER_DATA_GS_1[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_GS_2[0m <- 0x00b51100
>        [1;33mSPI_SHADER_USER_DATA_GS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_GS_4[0m <- 0x00b51400
>        [1;33mSPI_SHADER_USER_DATA_GS_5[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_HS_0[0m <- 0x00b51b00
>        [1;33mSPI_SHADER_USER_DATA_HS_1[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_HS_2[0m <- 0x00b53400
>        [1;33mSPI_SHADER_USER_DATA_HS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_HS_4[0m <- 0x00b51c00
>        [1;33mSPI_SHADER_USER_DATA_HS_5[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x01a77000
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_VPORT_SCISSOR_0_TL[0m <- TL_X = 0
>                                    TL_Y = 0
>                                    WINDOW_OFFSET_DISABLE = 1
>        [1;33mPA_SC_VPORT_SCISSOR_0_BR[0m <- BR_X = 163 (0x0a3)
>                                    BR_Y = 22 (0x016)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 81.5f (0x42a30000)
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 81.5f (0x42a30000)
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 11.0f (0x41300000)
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 11.0f (0x41300000)
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0.5f (0x3f000000)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCILREFMASK[0m <- STENCILTESTVAL = 0
>                             STENCILMASK = 0
>                             STENCILWRITEMASK = 0
>                             STENCILOPVAL = 1
>        [1;33mDB_STENCILREFMASK_BF[0m <- STENCILTESTVAL_BF = 0
>                                STENCILMASK_BF = 0
>                                STENCILWRITEMASK_BF = 0
>                                STENCILOPVAL_BF = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                            DEGAMMA_ENABLE = 0
>                            MODE = CB_NORMAL
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 8
>                            WIDTH = 8
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 8
>                              MAX_SIZE = 8
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 8
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 0
>                              CULL_BACK = 0
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 0
>                              POLY_OFFSET_BACK_ENABLE = 0
>                              POLY_OFFSET_PARA_ENABLE = 0
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_12[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 0
>                            Z_ENABLE = 0
>                            Z_WRITE_ENABLE = 0
>                            DEPTH_BOUNDS_ENABLE = 0
>                            ZFUNC = FRAG_NEVER
>                            BACKFACE_ENABLE = 0
>                            STENCILFUNC = REF_NEVER
>                            STENCILFUNC_BF = REF_NEVER
>                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CONTROL[0m <- STENCILFAIL = STENCIL_KEEP
>                              STENCILZPASS = STENCIL_KEEP
>                              STENCILZFAIL = STENCIL_KEEP
>                              STENCILFAIL_BF = STENCIL_KEEP
>                              STENCILZPASS_BF = STENCIL_KEEP
>                              STENCILZFAIL_BF = STENCIL_KEEP
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_SHADER_STAGES_EN[0m <- LS_EN = LS_STAGE_OFF
>                                HS_EN = 0
>                                ES_EN = ES_STAGE_OFF
>                                GS_EN = 0
>                                VS_EN = VS_STAGE_REAL
>                                DYNAMIC_HS = 0
>                                DISPATCH_DRAW_EN = 0
>                                DIS_DEALLOC_ACCUM_0 = 0
>                                DIS_DEALLOC_ACCUM_1 = 0
>                                VS_WAVE_ID_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_1024
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 0
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x00016600
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 3
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 192 (0xc0)
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 0
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 13 (0xd)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 1
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 1
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 1
>                             LINEAR_CENTER_ENA = 1
>                             LINEAR_CENTROID_ENA = 1
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 1
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 1
>                             POS_FIXED_PT_ENA = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = 2
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 1
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15 (0xf)
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x000166a0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 5
>                                   SGPRS = 3
>                                   PRIORITY = 0
>                                   FLOAT_MODE = FP_64_DENORMS
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 9
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_TMPRING_SIZE[0m <- WAVES = 256 (0x100)
>                            WAVESIZE = 0
>[1;32mDRAW_PREAMBLE[0m:
>        [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_TRISTRIP
>        [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 127 (0x007f)
>                              PARTIAL_VS_WAVE_ON = 0
>                              SWITCH_ON_EOP = 0
>                              PARTIAL_ES_WAVE_ON = 0
>                              SWITCH_ON_EOI = 0
>                              WD_SWITCH_ON_EOP = 1
>                              MAX_PRIMGRP_IN_WAVE = 0
>        [1;33mVGT_LS_HS_CONFIG[0m <- NUM_PATCHES = 0
>                            HS_NUM_INPUT_CP = 0
>                            HS_NUM_OUTPUT_CP = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_OUT_PRIM_TYPE[0m <- OUTPRIM_TYPE = OUTPRIM_TYPE_TRISTRIP
>                                OUTPRIM_TYPE_1 = 0
>                                OUTPRIM_TYPE_2 = 0
>                                OUTPRIM_TYPE_3 = 0
>                                UNIQUE_TYPE_PER_STREAM = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_MULTI_PRIM_IB_RESET_EN[0m <- RESET_EN = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_10[0m <- 0
>        [1;33mSPI_SHADER_USER_DATA_VS_11[0m <- 0
>[1;32mDRAW_INDEX_AUTO[0m:
>        [1;33mVGT_NUM_INDICES[0m <- 4
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00811000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x00000002
>[1;32mNOP[0m:
>        [31mTrace point ID: 2
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_BASE[0m <- 0x00014cc0
>        [1;33mCB_COLOR0_PITCH[0m <- TILE_MAX = 39 (0x27)
>                           FMASK_TILE_MAX = 39 (0x27)
>        [1;33mCB_COLOR0_SLICE[0m <- TILE_MAX = 639 (0x0027f)
>        [1;33mCB_COLOR0_VIEW[0m <- SLICE_START = 0
>                          SLICE_MAX = 0
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_8_8_8_8
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 1
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>        [1;33mCB_COLOR0_ATTRIB[0m <- TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_BANK_HEIGHT = 0
>                            NUM_SAMPLES = 0
>                            NUM_FRAGMENTS = 0
>                            FORCE_DST_ALPHA_1 = 0
>        [1;33mCB_COLOR0_DCC_CONTROL[0m <- OVERWRITE_COMBINER_DISABLE = 0
>                                 KEY_CLEAR_ENABLE = 0
>                                 MAX_UNCOMPRESSED_BLOCK_SIZE = 0
>                                 MIN_COMPRESSED_BLOCK_SIZE = 0
>                                 MAX_COMPRESSED_BLOCK_SIZE = 0
>                                 COLOR_TRANSFORM = 0
>                                 INDEPENDENT_64B_BLOCKS = 0
>                                 LOSSY_RGB_PRECISION = 0
>                                 LOSSY_ALPHA_PRECISION = 0
>        [1;33mCB_COLOR0_CMASK[0m <- 0x00014cc0
>        [1;33mCB_COLOR0_CMASK_SLICE[0m <- TILE_MAX = 0
>        [1;33mCB_COLOR0_FMASK[0m <- 0x00014cc0
>        [1;33mCB_COLOR0_FMASK_SLICE[0m <- TILE_MAX = 639 (0x0027f)
>        [1;33mCB_COLOR0_CLEAR_WORD0[0m <- 0
>        [1;33mCB_COLOR0_CLEAR_WORD1[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR1_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_8_8_8_8
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 1
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 317 (0x13d)
>                                   BR_Y = 88 (0x058)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15 (0xf)
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_REUSE_OFF[0m <- REUSE_OFF = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x01a77200
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x01a77400
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x01a77900
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_VPORT_SCISSOR_0_TL[0m <- TL_X = 0
>                                    TL_Y = 0
>                                    WINDOW_OFFSET_DISABLE = 1
>        [1;33mPA_SC_VPORT_SCISSOR_0_BR[0m <- BR_X = 317 (0x13d)
>                                    BR_Y = 88 (0x058)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 158.5f (0x431e8000)
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 158.5f (0x431e8000)
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 44.0f (0x42300000)
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 44.0f (0x42300000)
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0.5f (0x3f000000)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ONE
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 1
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ONE
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 1
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ONE
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 1
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ONE
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 1
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ONE
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 1
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ONE
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 1
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ONE
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 1
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ONE
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 1
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                            DEGAMMA_ENABLE = 0
>                            MODE = CB_NORMAL
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_1024
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 0
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x00016d60
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 3
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 192 (0xc0)
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 0
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 13 (0xd)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 1
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 1
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 1
>                             LINEAR_CENTER_ENA = 1
>                             LINEAR_CENTROID_ENA = 1
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 1
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 1
>                             POS_FIXED_PT_ENA = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = 2
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 1
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15 (0xf)
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x00016d70
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 3
>                                   SGPRS = 3
>                                   PRIORITY = 0
>                                   FLOAT_MODE = FP_64_DENORMS
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 9
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mDRAW_PREAMBLE[0m:
>        [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_TRIFAN
>        [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 127 (0x007f)
>                              PARTIAL_VS_WAVE_ON = 0
>                              SWITCH_ON_EOP = 0
>                              PARTIAL_ES_WAVE_ON = 0
>                              SWITCH_ON_EOI = 0
>                              WD_SWITCH_ON_EOP = 1
>                              MAX_PRIMGRP_IN_WAVE = 0
>        [1;33mVGT_LS_HS_CONFIG[0m <- NUM_PATCHES = 0
>                            HS_NUM_INPUT_CP = 0
>                            HS_NUM_OUTPUT_CP = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_AUTO[0m:
>        [1;33mVGT_NUM_INDICES[0m <- 4
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00811000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x00000003
>[1;32mNOP[0m:
>        [31mTrace point ID: 3
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_BASE[0m <- 0x00014700
>        [1;33mCB_COLOR0_PITCH[0m <- TILE_MAX = 23 (0x17)
>                           FMASK_TILE_MAX = 23 (0x17)
>        [1;33mCB_COLOR0_SLICE[0m <- TILE_MAX = 71 (0x00047)
>        [1;33mCB_COLOR0_VIEW[0m <- SLICE_START = 0
>                          SLICE_MAX = 0
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_8_8_8_8
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 1
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>        [1;33mCB_COLOR0_ATTRIB[0m <- TILE_MODE_INDEX = 13 (0xd)
>                            FMASK_TILE_MODE_INDEX = 13 (0xd)
>                            FMASK_BANK_HEIGHT = 0
>                            NUM_SAMPLES = 0
>                            NUM_FRAGMENTS = 0
>                            FORCE_DST_ALPHA_1 = 0
>        [1;33mCB_COLOR0_DCC_CONTROL[0m <- OVERWRITE_COMBINER_DISABLE = 0
>                                 KEY_CLEAR_ENABLE = 0
>                                 MAX_UNCOMPRESSED_BLOCK_SIZE = 0
>                                 MIN_COMPRESSED_BLOCK_SIZE = 0
>                                 MAX_COMPRESSED_BLOCK_SIZE = 0
>                                 COLOR_TRANSFORM = 0
>                                 INDEPENDENT_64B_BLOCKS = 0
>                                 LOSSY_RGB_PRECISION = 0
>                                 LOSSY_ALPHA_PRECISION = 0
>        [1;33mCB_COLOR0_CMASK[0m <- 0x00014700
>        [1;33mCB_COLOR0_CMASK_SLICE[0m <- TILE_MAX = 0
>        [1;33mCB_COLOR0_FMASK[0m <- 0x00014700
>        [1;33mCB_COLOR0_FMASK_SLICE[0m <- TILE_MAX = 71 (0x00047)
>        [1;33mCB_COLOR0_CLEAR_WORD0[0m <- 0
>        [1;33mCB_COLOR0_CLEAR_WORD1[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR1_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_8_8_8_8
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 1
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 163 (0x0a3)
>                                   BR_Y = 22 (0x016)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15 (0xf)
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_REUSE_OFF[0m <- REUSE_OFF = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x01a77c00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x01a77e00
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x01a78300
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_VPORT_SCISSOR_0_TL[0m <- TL_X = 0
>                                    TL_Y = 0
>                                    WINDOW_OFFSET_DISABLE = 1
>        [1;33mPA_SC_VPORT_SCISSOR_0_BR[0m <- BR_X = 163 (0x0a3)
>                                    BR_Y = 22 (0x016)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 81.5f (0x42a30000)
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 81.5f (0x42a30000)
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 11.0f (0x41300000)
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 11.0f (0x41300000)
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0.5f (0x3f000000)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                            DEGAMMA_ENABLE = 0
>                            MODE = CB_NORMAL
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_1024
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 0
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x00016600
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 3
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 192 (0xc0)
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 0
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 13 (0xd)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 1
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 1
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 1
>                             LINEAR_CENTER_ENA = 1
>                             LINEAR_CENTROID_ENA = 1
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 1
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 1
>                             POS_FIXED_PT_ENA = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = 2
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 1
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15 (0xf)
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x000166a0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 5
>                                   SGPRS = 3
>                                   PRIORITY = 0
>                                   FLOAT_MODE = FP_64_DENORMS
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 9
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mDRAW_PREAMBLE[0m:
>        [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_TRISTRIP
>        [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 127 (0x007f)
>                              PARTIAL_VS_WAVE_ON = 0
>                              SWITCH_ON_EOP = 0
>                              PARTIAL_ES_WAVE_ON = 0
>                              SWITCH_ON_EOI = 0
>                              WD_SWITCH_ON_EOP = 1
>                              MAX_PRIMGRP_IN_WAVE = 0
>        [1;33mVGT_LS_HS_CONFIG[0m <- NUM_PATCHES = 0
>                            HS_NUM_INPUT_CP = 0
>                            HS_NUM_OUTPUT_CP = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_AUTO[0m:
>        [1;33mVGT_NUM_INDICES[0m <- 4
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00811000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x00000004
>[1;32mNOP[0m:
>        [31mTrace point ID: 4
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_BASE[0m <- 0x00016cc0
>        [1;33mCB_COLOR0_PITCH[0m <- TILE_MAX = 31 (0x1f)
>                           FMASK_TILE_MAX = 31 (0x1f)
>        [1;33mCB_COLOR0_SLICE[0m <- TILE_MAX = 95 (0x0005f)
>        [1;33mCB_COLOR0_VIEW[0m <- SLICE_START = 0
>                          SLICE_MAX = 0
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_8
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 1
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>        [1;33mCB_COLOR0_ATTRIB[0m <- TILE_MODE_INDEX = 13 (0xd)
>                            FMASK_TILE_MODE_INDEX = 13 (0xd)
>                            FMASK_BANK_HEIGHT = 0
>                            NUM_SAMPLES = 0
>                            NUM_FRAGMENTS = 0
>                            FORCE_DST_ALPHA_1 = 1
>        [1;33mCB_COLOR0_DCC_CONTROL[0m <- OVERWRITE_COMBINER_DISABLE = 0
>                                 KEY_CLEAR_ENABLE = 0
>                                 MAX_UNCOMPRESSED_BLOCK_SIZE = 0
>                                 MIN_COMPRESSED_BLOCK_SIZE = 0
>                                 MAX_COMPRESSED_BLOCK_SIZE = 0
>                                 COLOR_TRANSFORM = 0
>                                 INDEPENDENT_64B_BLOCKS = 0
>                                 LOSSY_RGB_PRECISION = 0
>                                 LOSSY_ALPHA_PRECISION = 0
>        [1;33mCB_COLOR0_CMASK[0m <- 0x00016cc0
>        [1;33mCB_COLOR0_CMASK_SLICE[0m <- TILE_MAX = 0
>        [1;33mCB_COLOR0_FMASK[0m <- 0x00016cc0
>        [1;33mCB_COLOR0_FMASK_SLICE[0m <- TILE_MAX = 95 (0x0005f)
>        [1;33mCB_COLOR0_CLEAR_WORD0[0m <- 0
>        [1;33mCB_COLOR0_CLEAR_WORD1[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR1_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_8
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 1
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 163 (0x0a3)
>                                   BR_Y = 22 (0x016)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15 (0xf)
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_REUSE_OFF[0m <- REUSE_OFF = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_0[0m <- 0x01a78400
>        [1;33mSPI_SHADER_USER_DATA_VS_1[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x01a78500
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x01a78a00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 81.5f (0x42a30000)
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 81.5f (0x42a30000)
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 11.0f (0x41300000)
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 11.0f (0x41300000)
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                            DEGAMMA_ENABLE = 0
>                            MODE = CB_NORMAL
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 0
>                            WIDTH = 0
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 0
>                              MAX_SIZE = 0
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 0
>                              CULL_BACK = 0
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 0
>                              POLY_OFFSET_BACK_ENABLE = 0
>                              POLY_OFFSET_PARA_ENABLE = 0
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_12[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 0
>                            Z_ENABLE = 0
>                            Z_WRITE_ENABLE = 0
>                            DEPTH_BOUNDS_ENABLE = 0
>                            ZFUNC = FRAG_NEVER
>                            BACKFACE_ENABLE = 0
>                            STENCILFUNC = REF_NEVER
>                            STENCILFUNC_BF = REF_NEVER
>                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CONTROL[0m <- STENCILFAIL = STENCIL_KEEP
>                              STENCILZPASS = STENCIL_KEEP
>                              STENCILZFAIL = STENCIL_KEEP
>                              STENCILFAIL_BF = STENCIL_KEEP
>                              STENCILZPASS_BF = STENCIL_KEEP
>                              STENCILZFAIL_BF = STENCIL_KEEP
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_1024
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 0
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x00008430
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 3
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 192 (0xc0)
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 0
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 13 (0xd)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 0
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 1
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 1
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 1
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 1
>                             LINEAR_CENTER_ENA = 1
>                             LINEAR_CENTROID_ENA = 1
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 1
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 1
>                             POS_FIXED_PT_ENA = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = 2
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 1
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15 (0xf)
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x0000c640
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 3
>                                   SGPRS = 2
>                                   PRIORITY = 0
>                                   FLOAT_MODE = FP_64_DENORMS
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 9
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mDRAW_PREAMBLE[0m:
>        [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_TRIFAN
>        [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 127 (0x007f)
>                              PARTIAL_VS_WAVE_ON = 0
>                              SWITCH_ON_EOP = 0
>                              PARTIAL_ES_WAVE_ON = 0
>                              SWITCH_ON_EOI = 0
>                              WD_SWITCH_ON_EOP = 1
>                              MAX_PRIMGRP_IN_WAVE = 0
>        [1;33mVGT_LS_HS_CONFIG[0m <- NUM_PATCHES = 0
>                            HS_NUM_INPUT_CP = 0
>                            HS_NUM_OUTPUT_CP = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_AUTO[0m:
>        [1;33mVGT_NUM_INDICES[0m <- 4
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00811000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x00000005
>[1;32mNOP[0m:
>        [31mTrace point ID: 5
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_BASE[0m <- 0x00014cc0
>        [1;33mCB_COLOR0_PITCH[0m <- TILE_MAX = 39 (0x27)
>                           FMASK_TILE_MAX = 39 (0x27)
>        [1;33mCB_COLOR0_SLICE[0m <- TILE_MAX = 639 (0x0027f)
>        [1;33mCB_COLOR0_VIEW[0m <- SLICE_START = 0
>                          SLICE_MAX = 0
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_8_8_8_8
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 1
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>        [1;33mCB_COLOR0_ATTRIB[0m <- TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_BANK_HEIGHT = 0
>                            NUM_SAMPLES = 0
>                            NUM_FRAGMENTS = 0
>                            FORCE_DST_ALPHA_1 = 0
>        [1;33mCB_COLOR0_DCC_CONTROL[0m <- OVERWRITE_COMBINER_DISABLE = 0
>                                 KEY_CLEAR_ENABLE = 0
>                                 MAX_UNCOMPRESSED_BLOCK_SIZE = 0
>                                 MIN_COMPRESSED_BLOCK_SIZE = 0
>                                 MAX_COMPRESSED_BLOCK_SIZE = 0
>                                 COLOR_TRANSFORM = 0
>                                 INDEPENDENT_64B_BLOCKS = 0
>                                 LOSSY_RGB_PRECISION = 0
>                                 LOSSY_ALPHA_PRECISION = 0
>        [1;33mCB_COLOR0_CMASK[0m <- 0x00014cc0
>        [1;33mCB_COLOR0_CMASK_SLICE[0m <- TILE_MAX = 0
>        [1;33mCB_COLOR0_FMASK[0m <- 0x00014cc0
>        [1;33mCB_COLOR0_FMASK_SLICE[0m <- TILE_MAX = 639 (0x0027f)
>        [1;33mCB_COLOR0_CLEAR_WORD0[0m <- 0
>        [1;33mCB_COLOR0_CLEAR_WORD1[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR1_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_8_8_8_8
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 1
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 317 (0x13d)
>                                   BR_Y = 88 (0x058)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15 (0xf)
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_REUSE_OFF[0m <- REUSE_OFF = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_0[0m <- 0x01a78c00
>        [1;33mSPI_SHADER_USER_DATA_VS_1[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x01a78d00
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x01a78f00
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x01a79400
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_VPORT_SCISSOR_0_TL[0m <- TL_X = 0
>                                    TL_Y = 0
>                                    WINDOW_OFFSET_DISABLE = 1
>        [1;33mPA_SC_VPORT_SCISSOR_0_BR[0m <- BR_X = 317 (0x13d)
>                                    BR_Y = 88 (0x058)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 158.5f (0x431e8000)
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 158.5f (0x431e8000)
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 44.0f (0x42300000)
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 44.0f (0x42300000)
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0.5f (0x3f000000)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ONE
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 1
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ONE
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 1
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ONE
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 1
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ONE
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 1
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ONE
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 1
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ONE
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 1
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ONE
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 1
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ONE
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 1
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                            DEGAMMA_ENABLE = 0
>                            MODE = CB_NORMAL
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 8
>                            WIDTH = 8
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 8
>                              MAX_SIZE = 8
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 8
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                             VPORT_SCISSOR_ENABLE = 0
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 0
>                              CULL_BACK = 0
>                              FACE = 1
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 0
>                              POLY_OFFSET_BACK_ENABLE = 0
>                              POLY_OFFSET_PARA_ENABLE = 0
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_12[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 0
>                            Z_ENABLE = 0
>                            Z_WRITE_ENABLE = 0
>                            DEPTH_BOUNDS_ENABLE = 0
>                            ZFUNC = FRAG_NEVER
>                            BACKFACE_ENABLE = 0
>                            STENCILFUNC = REF_NEVER
>                            STENCILFUNC_BF = REF_NEVER
>                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CONTROL[0m <- STENCILFAIL = STENCIL_KEEP
>                              STENCILZPASS = STENCIL_KEEP
>                              STENCILZFAIL = STENCIL_KEEP
>                              STENCILFAIL_BF = STENCIL_KEEP
>                              STENCILZPASS_BF = STENCIL_KEEP
>                              STENCILZFAIL_BF = STENCIL_KEEP
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_1024
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 0
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x000166b0
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 3
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 192 (0xc0)
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 0
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 13 (0xd)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 1
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 1
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 1
>                             LINEAR_CENTER_ENA = 1
>                             LINEAR_CENTROID_ENA = 1
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 1
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 1
>                             POS_FIXED_PT_ENA = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = 2
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 1
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15 (0xf)
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x00016660
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 3
>                                   SGPRS = 3
>                                   PRIORITY = 0
>                                   FLOAT_MODE = FP_64_DENORMS
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 9
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_AUTO[0m:
>        [1;33mVGT_NUM_INDICES[0m <- 4
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00811000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x00000006
>[1;32mNOP[0m:
>        [31mTrace point ID: 6
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_BASE[0m <- 0x00014580
>        [1;33mCB_COLOR0_PITCH[0m <- TILE_MAX = 23 (0x17)
>                           FMASK_TILE_MAX = 23 (0x17)
>        [1;33mCB_COLOR0_SLICE[0m <- TILE_MAX = 71 (0x00047)
>        [1;33mCB_COLOR0_VIEW[0m <- SLICE_START = 0
>                          SLICE_MAX = 0
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_8_8_8_8
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 1
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>        [1;33mCB_COLOR0_ATTRIB[0m <- TILE_MODE_INDEX = 13 (0xd)
>                            FMASK_TILE_MODE_INDEX = 13 (0xd)
>                            FMASK_BANK_HEIGHT = 0
>                            NUM_SAMPLES = 0
>                            NUM_FRAGMENTS = 0
>                            FORCE_DST_ALPHA_1 = 0
>        [1;33mCB_COLOR0_DCC_CONTROL[0m <- OVERWRITE_COMBINER_DISABLE = 0
>                                 KEY_CLEAR_ENABLE = 0
>                                 MAX_UNCOMPRESSED_BLOCK_SIZE = 0
>                                 MIN_COMPRESSED_BLOCK_SIZE = 0
>                                 MAX_COMPRESSED_BLOCK_SIZE = 0
>                                 COLOR_TRANSFORM = 0
>                                 INDEPENDENT_64B_BLOCKS = 0
>                                 LOSSY_RGB_PRECISION = 0
>                                 LOSSY_ALPHA_PRECISION = 0
>        [1;33mCB_COLOR0_CMASK[0m <- 0x00014580
>        [1;33mCB_COLOR0_CMASK_SLICE[0m <- TILE_MAX = 0
>        [1;33mCB_COLOR0_FMASK[0m <- 0x00014580
>        [1;33mCB_COLOR0_FMASK_SLICE[0m <- TILE_MAX = 71 (0x00047)
>        [1;33mCB_COLOR0_CLEAR_WORD0[0m <- 0
>        [1;33mCB_COLOR0_CLEAR_WORD1[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR1_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_8_8_8_8
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 1
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 163 (0x0a3)
>                                   BR_Y = 22 (0x016)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15 (0xf)
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_REUSE_OFF[0m <- REUSE_OFF = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x01a79700
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x01a79900
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x01a79e00
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_VPORT_SCISSOR_0_TL[0m <- TL_X = 0
>                                    TL_Y = 0
>                                    WINDOW_OFFSET_DISABLE = 1
>        [1;33mPA_SC_VPORT_SCISSOR_0_BR[0m <- BR_X = 163 (0x0a3)
>                                    BR_Y = 22 (0x016)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 81.5f (0x42a30000)
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 81.5f (0x42a30000)
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 11.0f (0x41300000)
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 11.0f (0x41300000)
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0.5f (0x3f000000)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                            DEGAMMA_ENABLE = 0
>                            MODE = CB_NORMAL
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_1024
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 0
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x00016670
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 3
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 192 (0xc0)
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 0
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 13 (0xd)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 1
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 1
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 1
>                             LINEAR_CENTER_ENA = 1
>                             LINEAR_CENTROID_ENA = 1
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 1
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 1
>                             POS_FIXED_PT_ENA = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = 2
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 1
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15 (0xf)
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x000150a0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 11 (0xb)
>                                   SGPRS = 6
>                                   PRIORITY = 0
>                                   FLOAT_MODE = FP_64_DENORMS
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 9
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mDRAW_PREAMBLE[0m:
>        [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_TRISTRIP
>        [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 127 (0x007f)
>                              PARTIAL_VS_WAVE_ON = 0
>                              SWITCH_ON_EOP = 0
>                              PARTIAL_ES_WAVE_ON = 0
>                              SWITCH_ON_EOI = 0
>                              WD_SWITCH_ON_EOP = 1
>                              MAX_PRIMGRP_IN_WAVE = 0
>        [1;33mVGT_LS_HS_CONFIG[0m <- NUM_PATCHES = 0
>                            HS_NUM_INPUT_CP = 0
>                            HS_NUM_OUTPUT_CP = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_AUTO[0m:
>        [1;33mVGT_NUM_INDICES[0m <- 4
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00811000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x00000007
>[1;32mNOP[0m:
>        [31mTrace point ID: 7
>        [31m!!!!! This is the last trace point that was reached by the CP !!!!![0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_BASE[0m <- 0x00014cc0
>        [1;33mCB_COLOR0_PITCH[0m <- TILE_MAX = 39 (0x27)
>                           FMASK_TILE_MAX = 39 (0x27)
>        [1;33mCB_COLOR0_SLICE[0m <- TILE_MAX = 639 (0x0027f)
>        [1;33mCB_COLOR0_VIEW[0m <- SLICE_START = 0
>                          SLICE_MAX = 0
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_8_8_8_8
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 1
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>        [1;33mCB_COLOR0_ATTRIB[0m <- TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_TILE_MODE_INDEX = 14 (0xe)
>                            FMASK_BANK_HEIGHT = 0
>                            NUM_SAMPLES = 0
>                            NUM_FRAGMENTS = 0
>                            FORCE_DST_ALPHA_1 = 0
>        [1;33mCB_COLOR0_DCC_CONTROL[0m <- OVERWRITE_COMBINER_DISABLE = 0
>                                 KEY_CLEAR_ENABLE = 0
>                                 MAX_UNCOMPRESSED_BLOCK_SIZE = 0
>                                 MIN_COMPRESSED_BLOCK_SIZE = 0
>                                 MAX_COMPRESSED_BLOCK_SIZE = 0
>                                 COLOR_TRANSFORM = 0
>                                 INDEPENDENT_64B_BLOCKS = 0
>                                 LOSSY_RGB_PRECISION = 0
>                                 LOSSY_ALPHA_PRECISION = 0
>        [1;33mCB_COLOR0_CMASK[0m <- 0x00014cc0
>        [1;33mCB_COLOR0_CMASK_SLICE[0m <- TILE_MAX = 0
>        [1;33mCB_COLOR0_FMASK[0m <- 0x00014cc0
>        [1;33mCB_COLOR0_FMASK_SLICE[0m <- TILE_MAX = 639 (0x0027f)
>        [1;33mCB_COLOR0_CLEAR_WORD0[0m <- 0
>        [1;33mCB_COLOR0_CLEAR_WORD1[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR1_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_8_8_8_8
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 1
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 317 (0x13d)
>                                   BR_Y = 88 (0x058)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15 (0xf)
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_REUSE_OFF[0m <- REUSE_OFF = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x01a7a000
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x01a7a200
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x01a7a700
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_VPORT_SCISSOR_0_TL[0m <- TL_X = 0
>                                    TL_Y = 0
>                                    WINDOW_OFFSET_DISABLE = 1
>        [1;33mPA_SC_VPORT_SCISSOR_0_BR[0m <- BR_X = 317 (0x13d)
>                                    BR_Y = 88 (0x058)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 158.5f (0x431e8000)
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 158.5f (0x431e8000)
>        [1;33mPA_CL_VPORT_YSCALE[0m <- 44.0f (0x42300000)
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 44.0f (0x42300000)
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0.5f (0x3f000000)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ONE
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 1
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ONE
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 1
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ONE
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 1
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ONE
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 1
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ONE
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 1
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ONE
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 1
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ONE
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 1
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ONE
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 1
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                            DEGAMMA_ENABLE = 0
>                            MODE = CB_NORMAL
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_1024
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 0
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x00016d60
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 3
>                                   SGPRS = 1
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 192 (0xc0)
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 0
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 13 (0xd)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 1
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 1
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 1
>                             LINEAR_CENTER_ENA = 1
>                             LINEAR_CENTROID_ENA = 1
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 1
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 1
>                             POS_FIXED_PT_ENA = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = 2
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 1
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15 (0xf)
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x00016d70
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 3
>                                   SGPRS = 3
>                                   PRIORITY = 0
>                                   FLOAT_MODE = FP_64_DENORMS
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 9
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;32mDRAW_PREAMBLE[0m:
>        [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_TRIFAN
>        [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 127 (0x007f)
>                              PARTIAL_VS_WAVE_ON = 0
>                              SWITCH_ON_EOP = 0
>                              PARTIAL_ES_WAVE_ON = 0
>                              SWITCH_ON_EOI = 0
>                              WD_SWITCH_ON_EOP = 1
>                              MAX_PRIMGRP_IN_WAVE = 0
>        [1;33mVGT_LS_HS_CONFIG[0m <- NUM_PATCHES = 0
>                            HS_NUM_INPUT_CP = 0
>                            HS_NUM_OUTPUT_CP = 0
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;32mDRAW_INDEX_AUTO[0m:
>        [1;33mVGT_NUM_INDICES[0m <- 4
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00811000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x00000008
>[1;32mNOP[0m:
>        [31mTrace point ID: 8
>        [31m!!!!! This trace point was NOT reached by the CP !!!!![0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_DB_META
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = PS_PARTIAL_FLUSH
>        [1;33mEVENT_INDEX[0m <- 4
>        [1;33mINV_L2[0m <- 0
>[1;32mACQUIRE_MEM[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         TC_SD_ACTION_ENA = 0
>                         TC_NC_ACTION_ENA = 0
>                         CB0_DEST_BASE_ENA = 1
>                         CB1_DEST_BASE_ENA = 1
>                         CB2_DEST_BASE_ENA = 1
>                         CB3_DEST_BASE_ENA = 1
>                         CB4_DEST_BASE_ENA = 1
>                         CB5_DEST_BASE_ENA = 1
>                         CB6_DEST_BASE_ENA = 1
>                         CB7_DEST_BASE_ENA = 1
>                         DB_DEST_BASE_ENA = 1
>                         TCL1_VOL_ACTION_ENA = 0
>                         TC_VOL_ACTION_ENA = 0
>                         TC_WB_ACTION_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 1
>                         DB_ACTION_ENA = 1
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_KCACHE_VOL_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>                         SH_KCACHE_WB_ACTION_ENA = 0
>                         SH_SD_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_SIZE_HI[0m <- COHER_SIZE_HI_256B = 255 (0xff)
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mCP_COHER_BASE_HI[0m <- COHER_BASE_HI_256B = 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0x00811000
>        [1;33mDST_ADDR_HI[0m <- 0
>        0x00000009
>[1;32mNOP[0m:
>        [31mTrace point ID: 9
>        [31m!!!!! This trace point was NOT reached by the CP !!!!![0m
>------------------- IB end -------------------
>
>Done.

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Attachments on bug 94242: 121873 | 121931 | 121979 | 121988

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