Attachment 122963 Details for Bug 91410 – [PATCH] drm/i915: Update CDCLK_FREQ register on BDW after changing cdclk frequency

[patch] [PATCH] drm/i915: Update CDCLK_FREQ register on BDW after changing cdclk frequency

0001-drm-i915-Update-CDCLK_FREQ-register-on-BDW-after-cha.patch (text/plain), 2.45 KB, created by Ville Syrjala on 2016-04-15 09:08:48 UTC

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Creator: Ville Syrjala

Created: 2016-04-15 09:08:48 UTC

Size: 2.45 KB

patch

obsolete

>From d7baedcdebe4d02fb08342aa8d1fbf9e535872be Mon Sep 17 00:00:00 2001
>From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
>Date: Fri, 15 Apr 2016 11:41:06 +0300
>Subject: [PATCH] drm/i915: Update CDCLK_FREQ register on BDW after changing
> cdclk frequency
>MIME-Version: 1.0
>Content-Type: text/plain; charset=UTF-8
>Content-Transfer-Encoding: 8bit
>
>Update CDCLK_FREQ on BDW after changing the cdclk frequency. Not sure
>if this is a late addition to the spec, or if I simply overlooked this
>step when writing the original code.
>
>This is what Bspec has to say about CDCLK_FREQ:
>"Program this field to the CD clock frequency minus one. This is used to
> generate a divided down clock for miscellaneous timers in display."
>
>And the "Broadwell Sequences for Changing CD Clock Frequency" section
>clarifies this further:
>"For CD clock 337.5 MHz, program 337 decimal.
> For CD clock 450 MHz, program 449 decimal.
> For CD clock 540 MHz, program 539 decimal.
> For CD clock 675 MHz, program 674 decimal."
>
>Cc: stable@vger.kernel.org
>Cc: Lu, Han <han.lu@intel.com>
>Cc: Vasily Khoruzhick <anarsoul@gmail.com>
>Cc: Mika Kahola <mika.kahola@intel.com>
>Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91410
>Fixes: b432e5cfd5e9 ("drm/i915: BDW clock change support")
>Signed-off-by: Ville SyrjÃ¤lÃ¤ <ville.syrjala@linux.intel.com>
>---
> drivers/gpu/drm/i915/i915_reg.h      | 2 ++
> drivers/gpu/drm/i915/intel_display.c | 2 ++
> 2 files changed, 4 insertions(+)
>
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index 03264fd30fdd..41c9ae03652b 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -7484,6 +7484,8 @@ enum skl_disp_power_wells {
> #define  TRANS_CLK_SEL_DISABLED		(0x0<<29)
> #define  TRANS_CLK_SEL_PORT(x)		(((x)+1)<<29)
> 
>+#define CDCLK_FREQ			_MMIO(0x46200)
>+
> #define _TRANSA_MSA_MISC		0x60410
> #define _TRANSB_MSA_MISC		0x61410
> #define _TRANSC_MSA_MISC		0x62410
>diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>index 929fd93b3e5d..ea55dd331fac 100644
>--- a/drivers/gpu/drm/i915/intel_display.c
>+++ b/drivers/gpu/drm/i915/intel_display.c
>@@ -9647,6 +9647,8 @@ static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
> 	sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
> 	mutex_unlock(&dev_priv->rps.hw_lock);
> 
>+	I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
>+
> 	intel_update_cdclk(dev);
> 
> 	WARN(cdclk != dev_priv->cdclk_freq,
>-- 
>2.7.4
>

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