Attachment 123083 Details for Bug 94528 – Re-attach again per Kevin's suggestion.

Re-attach again per Kevin's suggestion.

0001-Fix-VX900-HDMI-port-no-display-issue.patch (text/plain), 1.41 KB, created by HuangRan on 2016-04-20 03:42:12 UTC

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Creator: HuangRan

Created: 2016-04-20 03:42:12 UTC

Size: 1.41 KB

patch

obsolete

>From 3d111a36fdef4ee77ae7210f35405133795f6796 Mon Sep 17 00:00:00 2001
>From: HuangRan <huangranbj@126.com>
>Date: Tue, 19 Apr 2016 09:34:41 +0800
>Subject: [PATCH] Fix VX900 HDMI port no display issue
>
>Remove the write of bit6 for VGA/SVGA CRT Controller Register 0xFD
>(IGA1 Scaling Up and Timing Control). Bit6 of CRTC 0xFD is RO bit
>which can't be written. Verfied on VX900 board for HDMI port.
>
>Signed-off-by: Hu, Yi <huyi@iscas.ac.cn>
>Signed-off-by: Huang, Ran <huangranbj@126.com>
>---
> drivers/gpu/drm/via/via_crtc.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
>diff --git a/drivers/gpu/drm/via/via_crtc.c b/drivers/gpu/drm/via/via_crtc.c
>index fa29270..a50e654 100644
>--- a/drivers/gpu/drm/via/via_crtc.c
>+++ b/drivers/gpu/drm/via/via_crtc.c
>@@ -468,7 +468,7 @@ void via_load_crtc_pixel_timing(struct drm_crtc *crtc, struct drm_display_mode *
> 		svga_wcrt_mask(VGABASE, 0x32, 0x00, BIT(2));
> 
> 	}
>-	svga_wcrt_mask(VGABASE, 0xFD, BIT(5) | BIT(6), BIT(5) | BIT(6));
>+	svga_wcrt_mask(VGABASE, 0xFD, BIT(5), BIT(5));
> }
> 
> /* Load CRTC timing registers */
>@@ -484,7 +484,7 @@ void via_load_crtc_timing(struct via_crtc *iga, struct drm_display_mode *mode)
> 			svga_wcrt_mask(VGABASE, 0x45, 0x00, BIT(0));
> 
> 			/* Disable IGA1 pixel timing */
>-			svga_wcrt_mask(VGABASE, 0xFD, 0x00, BIT(6) | BIT(5));
>+			svga_wcrt_mask(VGABASE, 0xFD, 0x00, BIT(5));
> 		}
> 
> 		reg_value = IGA1_HOR_TOTAL_FORMULA(mode->crtc_htotal);
>-- 
>1.9.1
>

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