Attachment 123122 Details for Bug 91410 – [PATCH] ALSA: hda - Move i915 HSW/BDW BCLK setup to a common function

[patch] [PATCH] ALSA: hda - Move i915 HSW/BDW BCLK setup to a common function

0001-ALSA-hda-Move-i915-HSW-BDW-BCLK-setup-to-a-common-fu.patch (text/plain), 7.08 KB, created by Takashi Iwai on 2016-04-21 15:25:18 UTC

(hide)

Description:

Filename:

MIME Type:

Creator: Takashi Iwai

Created: 2016-04-21 15:25:18 UTC

Size: 7.08 KB

patch

obsolete

>From e8de8fa72b640de1e30dcf62bab1a7b012d48cc2 Mon Sep 17 00:00:00 2001
>From: Takashi Iwai <tiwai@suse.de>
>Date: Thu, 21 Apr 2016 16:39:17 +0200
>Subject: [PATCH] ALSA: hda - Move i915 HSW/BDW BCLK setup to a common function
>
>Since the setup of BCLK for i915 HSW/BDW is required not only at
>initialization and resume but also at the hotplug, move the code into
>HDA core i915 helper so that it can be called from both the controller
>and the codec drivers.
>
>Now with this patch, the former haswell_set_bclk() in hda_intel.c is
>exported as snd_hdac_i915_set_bclk().  This is called from the HDA
>controller driver and intel_pin_eld_notify() in HDMI codec driver.
>
>Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91410
>Signed-off-by: Takashi Iwai <tiwai@suse.de>
>---
> include/sound/hda_i915.h   |  5 ++--
> sound/hda/hdac_i915.c      | 62 +++++++++++++++++++++++++++++++++++++++++++++-
> sound/pci/hda/hda_intel.c  | 56 +++--------------------------------------
> sound/pci/hda/patch_hdmi.c |  1 +
> 4 files changed, 68 insertions(+), 56 deletions(-)
>
>diff --git a/include/sound/hda_i915.h b/include/sound/hda_i915.h
>index eed87a7559b7..075bf2419f85 100644
>--- a/include/sound/hda_i915.h
>+++ b/include/sound/hda_i915.h
>@@ -9,7 +9,7 @@
> #ifdef CONFIG_SND_HDA_I915
> int snd_hdac_set_codec_wakeup(struct hdac_bus *bus, bool enable);
> int snd_hdac_display_power(struct hdac_bus *bus, bool enable);
>-int snd_hdac_get_display_clk(struct hdac_bus *bus);
>+void snd_hdac_i915_set_bclk(struct hdac_bus *bus);
> int snd_hdac_sync_audio_rate(struct hdac_device *codec, hda_nid_t nid, int rate);
> int snd_hdac_acomp_get_eld(struct hdac_device *codec, hda_nid_t nid,
> 			   bool *audio_enabled, char *buffer, int max_bytes);
>@@ -25,9 +25,8 @@ static inline int snd_hdac_display_power(struct hdac_bus *bus, bool enable)
> {
> 	return 0;
> }
>-static inline int snd_hdac_get_display_clk(struct hdac_bus *bus)
>+static inline void snd_hdac_i915_set_bclk(struct hdac_bus *bus);
> {
>-	return 0;
> }
> static inline int snd_hdac_sync_audio_rate(struct hdac_device *codec,
> 					   hda_nid_t nid, int rate)
>diff --git a/sound/hda/hdac_i915.c b/sound/hda/hdac_i915.c
>index 6800e0c5a38f..206f00c48d7c 100644
>--- a/sound/hda/hdac_i915.c
>+++ b/sound/hda/hdac_i915.c
>@@ -20,6 +20,7 @@
> #include <sound/core.h>
> #include <sound/hdaudio.h>
> #include <sound/hda_i915.h>
>+#include <sound/hda_register.h>
> 
> static struct i915_audio_component *hdac_acomp;
> 
>@@ -116,7 +117,66 @@ int snd_hdac_get_display_clk(struct hdac_bus *bus)
> 
> 	return acomp->ops->get_cdclk_freq(acomp->dev);
> }
>-EXPORT_SYMBOL_GPL(snd_hdac_get_display_clk);
>+
>+#define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
>+				((pci)->device == 0x0c0c) || \
>+				((pci)->device == 0x0d0c) || \
>+				((pci)->device == 0x160c))
>+
>+/**
>+ * snd_hdac_i915_set_bclk - Reprogram BCLK for HSW/BDW
>+ * @bus: HDA core bus
>+ *
>+ * Intel HSW/BDW display HDA controller is in GPU. Both its power and link BCLK
>+ * depends on GPU. Two Extended Mode registers EM4 (M value) and EM5 (N Value)
>+ * are used to convert CDClk (Core Display Clock) to 24MHz BCLK:
>+ * BCLK = CDCLK * M / N
>+ * The values will be lost when the display power well is disabled and need to
>+ * be restored to avoid abnormal playback speed.
>+ *
>+ * Call this function at initializing and changing power well, as well as
>+ * at ELD notifier for the hotplug.
>+ */
>+void snd_hdac_i915_set_bclk(struct hdac_bus *bus)
>+{
>+	struct i915_audio_component *acomp = bus->audio_component;
>+	struct pci_dev *pci = to_pci_dev(bus->dev);
>+	int cdclk_freq;
>+	unsigned int bclk_m, bclk_n;
>+
>+	if (!acomp || !acomp->ops || !acomp->ops->get_cdclk_freq)
>+		return; /* only for i915 binding */
>+	if (!CONTROLLER_IN_GPU(pci))
>+		return; /* only HSW/BDW */
>+
>+	cdclk_freq = acomp->ops->get_cdclk_freq(acomp->dev);
>+	switch (cdclk_freq) {
>+	case 337500:
>+		bclk_m = 16;
>+		bclk_n = 225;
>+		break;
>+
>+	case 450000:
>+	default: /* default CDCLK 450MHz */
>+		bclk_m = 4;
>+		bclk_n = 75;
>+		break;
>+
>+	case 540000:
>+		bclk_m = 4;
>+		bclk_n = 90;
>+		break;
>+
>+	case 675000:
>+		bclk_m = 8;
>+		bclk_n = 225;
>+		break;
>+	}
>+
>+	snd_hdac_chip_writew(bus, HSW_EM4, bclk_m);
>+	snd_hdac_chip_writew(bus, HSW_EM5, bclk_n);
>+}
>+EXPORT_SYMBOL_GPL(snd_hdac_i915_set_bclk);
> 
> /* There is a fixed mapping between audio pin node and display port.
>  * on SNB, IVY, HSW, BSW, SKL, BXT, KBL:
>diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c
>index b680be0e937d..d2d36bc68193 100644
>--- a/sound/pci/hda/hda_intel.c
>+++ b/sound/pci/hda/hda_intel.c
>@@ -857,50 +857,6 @@ static int param_set_xint(const char *val, const struct kernel_param *kp)
> #define azx_del_card_list(chip) /* NOP */
> #endif /* CONFIG_PM */
> 
>-/* Intel HSW/BDW display HDA controller is in GPU. Both its power and link BCLK
>- * depends on GPU. Two Extended Mode registers EM4 (M value) and EM5 (N Value)
>- * are used to convert CDClk (Core Display Clock) to 24MHz BCLK:
>- * BCLK = CDCLK * M / N
>- * The values will be lost when the display power well is disabled and need to
>- * be restored to avoid abnormal playback speed.
>- */
>-static void haswell_set_bclk(struct hda_intel *hda)
>-{
>-	struct azx *chip = &hda->chip;
>-	int cdclk_freq;
>-	unsigned int bclk_m, bclk_n;
>-
>-	if (!hda->need_i915_power)
>-		return;
>-
>-	cdclk_freq = snd_hdac_get_display_clk(azx_bus(chip));
>-	switch (cdclk_freq) {
>-	case 337500:
>-		bclk_m = 16;
>-		bclk_n = 225;
>-		break;
>-
>-	case 450000:
>-	default: /* default CDCLK 450MHz */
>-		bclk_m = 4;
>-		bclk_n = 75;
>-		break;
>-
>-	case 540000:
>-		bclk_m = 4;
>-		bclk_n = 90;
>-		break;
>-
>-	case 675000:
>-		bclk_m = 8;
>-		bclk_n = 225;
>-		break;
>-	}
>-
>-	azx_writew(chip, HSW_EM4, bclk_m);
>-	azx_writew(chip, HSW_EM5, bclk_n);
>-}
>-
> #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
> /*
>  * power management
>@@ -958,7 +914,7 @@ static int azx_resume(struct device *dev)
> 	if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
> 		&& hda->need_i915_power) {
> 		snd_hdac_display_power(azx_bus(chip), true);
>-		haswell_set_bclk(hda);
>+		snd_hdac_i915_set_bclk(azx_bus(chip));
> 	}
> 	if (chip->msi)
> 		if (pci_enable_msi(pci) < 0)
>@@ -1058,7 +1014,7 @@ static int azx_runtime_resume(struct device *dev)
> 		bus = azx_bus(chip);
> 		if (hda->need_i915_power) {
> 			snd_hdac_display_power(bus, true);
>-			haswell_set_bclk(hda);
>+			snd_hdac_i915_set_bclk(bus);
> 		} else {
> 			/* toggle codec wakeup bit for STATESTS read */
> 			snd_hdac_set_codec_wakeup(bus, true);
>@@ -1796,12 +1752,8 @@ static int azx_first_init(struct azx *chip)
> 	/* initialize chip */
> 	azx_init_pci(chip);
> 
>-	if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
>-		struct hda_intel *hda;
>-
>-		hda = container_of(chip, struct hda_intel, chip);
>-		haswell_set_bclk(hda);
>-	}
>+	if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
>+		snd_hdac_i915_set_bclk(bus);
> 
> 	hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
> 
>diff --git a/sound/pci/hda/patch_hdmi.c b/sound/pci/hda/patch_hdmi.c
>index 9452384d2000..27164e3030c9 100644
>--- a/sound/pci/hda/patch_hdmi.c
>+++ b/sound/pci/hda/patch_hdmi.c
>@@ -2313,6 +2313,7 @@ static void intel_pin_eld_notify(void *audio_ptr, int port)
> 	if (atomic_read(&(codec)->core.in_pm))
> 		return;
> 
>+	snd_hdac_i915_set_bclk(&codec->bus->core);
> 	check_presence_and_report(codec, pin_nid);
> }
> 
>-- 
>2.8.1
>

Actions: View | Splinter Review

Attachments on bug 91410: 117270 | 122889 | 122916 | 122963 | 122964 | 123122 | 123130

Use of freedesktop.org services, including Bugzilla, is subject to our Code of Conduct. How we collect and use information is described in our Privacy Policy.