Attachment 123968 Details for Bug 95176 – Patch by danvet to fix the issue

[patch] Patch by danvet to fix the issue

0001-drm-i915-psr-Try-to-program-link-training-times-corr.patch (text/plain), 3.20 KB, created by Peter Frühberger on 2016-05-22 18:58:40 UTC

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Creator: Peter Frühberger

Created: 2016-05-22 18:58:40 UTC

Size: 3.20 KB

patch

obsolete

>From 963c5a02bbddc1b6c3c9ce06f85f2ff8ffd40d20 Mon Sep 17 00:00:00 2001
>From: Daniel Vetter <daniel.vetter@ffwll.ch>
>Date: Wed, 18 May 2016 09:43:36 +0200
>Subject: [PATCH] drm/i915/psr: Try to program link training times correctly
>
>Oops. Hw default for programming these fields to 0 is "skip link
>training". Display won't take that too well usually.
>
>v2: Unbotch the math a bit.
>
>v3: Drop debug hunk.
>
>Tested-by: Lyude <cpaul@redhat.com>
>Cc: Lyude <cpaul@redhat.com>
>Cc: stable@vger.kernel.org
>Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95176
>Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
>---
> drivers/gpu/drm/i915/intel_psr.c | 55 ++++++++++++++++++++++++++++++++++------
> 1 file changed, 47 insertions(+), 8 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
>index 0b42ada..bd322d8 100644
>--- a/drivers/gpu/drm/i915/intel_psr.c
>+++ b/drivers/gpu/drm/i915/intel_psr.c
>@@ -280,7 +280,10 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp)
> 	 * with the 5 or 6 idle patterns.
> 	 */
> 	uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
>-	uint32_t val = 0x0;
>+	uint32_t val = EDP_PSR_ENABLE;
>+
>+	val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT;
>+	val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
> 
> 	if (IS_HASWELL(dev))
> 		val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
>@@ -288,14 +291,50 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp)
> 	if (dev_priv->psr.link_standby)
> 		val |= EDP_PSR_LINK_STANDBY;
> 
>-	I915_WRITE(EDP_PSR_CTL, val |
>-		   max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
>-		   idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
>-		   EDP_PSR_ENABLE);
>+	if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
>+		val |= EDP_PSR_TP1_TIME_2500us;
>+	else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
>+		val |= EDP_PSR_TP1_TIME_500us;
>+	else if (dev_priv->vbt.psr.tp1_wakeup_time > 0)
>+		val |= EDP_PSR_TP1_TIME_100us;
>+	else
>+		val |= EDP_PSR_TP1_TIME_0us;
>+
>+	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
>+		val |= EDP_PSR_TP2_TP3_TIME_2500us;
>+	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
>+		val |= EDP_PSR_TP2_TP3_TIME_500us;
>+	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
>+		val |= EDP_PSR_TP2_TP3_TIME_100us;
>+	else
>+		val |= EDP_PSR_TP2_TP3_TIME_0us;
>+
>+	if (intel_dp_source_supports_hbr2(intel_dp) &&
>+	    drm_dp_tps3_supported(intel_dp->dpcd))
>+		val |= EDP_PSR_TP1_TP3_SEL;
>+	else
>+		val |= EDP_PSR_TP1_TP2_SEL;
>+
>+	I915_WRITE(EDP_PSR_CTL, val);
>+
>+	if (!dev_priv->psr.psr2_support)
>+		return;
>+
>+	/* FIXME: selective update is probably totally broken because it doesn't
>+	 * mesh at all with our frontbuffer tracking. And the hw alone isn't
>+	 * good enough. */
>+	val = EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE;
>+
>+	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
>+		val |= EDP_PSR2_TP2_TIME_2500;
>+	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
>+		val |= EDP_PSR2_TP2_TIME_500;
>+	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
>+		val |= EDP_PSR2_TP2_TIME_100;
>+	else
>+		val |= EDP_PSR2_TP2_TIME_50;
> 
>-	if (dev_priv->psr.psr2_support)
>-		I915_WRITE(EDP_PSR2_CTL, EDP_PSR2_ENABLE |
>-				EDP_SU_TRACK_ENABLE | EDP_PSR2_TP2_TIME_100);
>+	I915_WRITE(EDP_PSR2_CTL, val);
> }
> 
> static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
>-- 
>2.7.4
>

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