Attachment 123994 Details for Bug 95545 – vm fault report

vm fault report

vmfault.txt (text/plain), 88.66 KB, created by csaba.halasz on 2016-05-23 15:37:35 UTC

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Creator: csaba.halasz

Created: 2016-05-23 15:37:35 UTC

Size: 88.66 KB

patch

obsolete

>VM fault report.
>
>Driver vendor: X.Org
>Device vendor: AMD
>Device name: AMD TONGA (DRM 3.2.0, LLVM 3.9.0)
>
>Failing VM page: 0x001057ea
>
>[1;33mColor buffer 0:[0m
>  Info: npix_x=640, npix_y=341, npix_z=1, blk_w=1, blk_h=1, blk_d=1, array_size=1, last_level=0, bpe=4, nsamples=1, flags=0x110301, b8g8r8x8_unorm
>  Layout: size=1179648, alignment=131072, bankw=1, bankh=4, nbanks=16, mtilea=4, tilesplit=512, pipeconfig=12, scanout=1
>  CMask: offset=0, size=4096, alignment=2048, pitch=1024, height=512, xalign=512, yalign=256, slice_tile_max=31
>  Level[0]: offset=0, slice_size=1179648, npix_x=640, npix_y=341, npix_z=1, nblk_x=768, nblk_y=384, nblk_z=1, pitch_bytes=3072, mode=3
>
>SHADER KEY
>  instance_divisors = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
>  as_es = 0
>  as_ls = 0
>  export_prim_id = 0
>
>Vertex Shader as VS:
>Shader prolog disassembly:
>	v_add_i32_e32 v4, vcc, s12, v0 ; 3208000C
>	v_mov_b32_e32 v5, v4           ; 7E0A0304
>	v_mov_b32_e32 v6, v4           ; 7E0C0304
>	v_mov_b32_e32 v7, v4           ; 7E0E0304
>Shader main disassembly:
>	s_load_dwordx4 s[4:7], s[10:11], 0x0                    ; C00A0105 00000000
>	s_load_dwordx4 s[12:15], s[10:11], 0x10                 ; C00A0305 00000010
>	s_load_dwordx4 s[0:3], s[2:3], 0x0                      ; C00A0001 00000000
>	s_waitcnt lgkmcnt(0)                                    ; BF8C007F
>	buffer_load_format_xyzw v[8:11], v4, s[4:7], 0 idxen    ; E00C2000 80010804
>	s_load_dwordx4 s[4:7], s[10:11], 0x20                   ; C00A0105 00000020
>	s_load_dwordx4 s[8:11], s[10:11], 0x30                  ; C00A0205 00000030
>	buffer_load_format_xyzw v[12:15], v5, s[12:15], 0 idxen ; E00C2000 80030C05
>	s_buffer_load_dword s12, s[0:3], 0x20                   ; C0220300 00000020
>	s_buffer_load_dword s13, s[0:3], 0x24                   ; C0220340 00000024
>	s_waitcnt lgkmcnt(0)                                    ; BF8C007F
>	buffer_load_format_xyzw v[3:6], v6, s[4:7], 0 idxen     ; E00C2000 80010306
>	s_nop 0                                                 ; BF800000
>	buffer_load_format_xyzw v[16:19], v7, s[8:11], 0 idxen  ; E00C2000 80021007
>	s_buffer_load_dword s4, s[0:3], 0x0                     ; C0220100 00000000
>	s_buffer_load_dword s5, s[0:3], 0x4                     ; C0220140 00000004
>	s_buffer_load_dword s6, s[0:3], 0x8                     ; C0220180 00000008
>	s_buffer_load_dword s7, s[0:3], 0xc                     ; C02201C0 0000000C
>	s_buffer_load_dword s8, s[0:3], 0x10                    ; C0220200 00000010
>	s_buffer_load_dword s9, s[0:3], 0x14                    ; C0220240 00000014
>	s_buffer_load_dword s10, s[0:3], 0x18                   ; C0220280 00000018
>	s_buffer_load_dword s11, s[0:3], 0x1c                   ; C02202C0 0000001C
>	s_buffer_load_dword s14, s[0:3], 0x28                   ; C0220380 00000028
>	s_buffer_load_dword s15, s[0:3], 0x2c                   ; C02203C0 0000002C
>	s_buffer_load_dword s16, s[0:3], 0x30                   ; C0220400 00000030
>	s_buffer_load_dword s17, s[0:3], 0x34                   ; C0220440 00000034
>	s_buffer_load_dword s18, s[0:3], 0x38                   ; C0220480 00000038
>	s_buffer_load_dword s0, s[0:3], 0x3c                    ; C0220000 0000003C
>	s_waitcnt vmcnt(3) lgkmcnt(0)                           ; BF8C0073
>	v_mul_f32_e32 v0, s4, v8                                ; 0A001004
>	v_mul_f32_e32 v1, s5, v8                                ; 0A021005
>	v_mul_f32_e32 v7, s6, v8                                ; 0A0E1006
>	v_mul_f32_e32 v8, s7, v8                                ; 0A101007
>	v_mac_f32_e32 v0, s8, v9                                ; 2C001208
>	v_mac_f32_e32 v1, s9, v9                                ; 2C021209
>	v_mac_f32_e32 v7, s10, v9                               ; 2C0E120A
>	v_mac_f32_e32 v8, s11, v9                               ; 2C10120B
>	s_waitcnt vmcnt(2)                                      ; BF8C0F72
>	exp 15, 32, 0, 0, 0, v12, v13, v14, v15                 ; C400020F 0F0E0D0C
>	v_mac_f32_e32 v0, s12, v10                              ; 2C00140C
>	v_mac_f32_e32 v1, s13, v10                              ; 2C02140D
>	v_mac_f32_e32 v7, s14, v10                              ; 2C0E140E
>	v_mac_f32_e32 v8, s15, v10                              ; 2C10140F
>	s_waitcnt vmcnt(1)                                      ; BF8C0F71
>	exp 15, 33, 0, 0, 0, v3, v4, v5, v6                     ; C400021F 06050403
>	v_mac_f32_e32 v0, s16, v11                              ; 2C001610
>	v_mac_f32_e32 v1, s17, v11                              ; 2C021611
>	v_mac_f32_e32 v7, s18, v11                              ; 2C0E1612
>	v_mac_f32_e32 v8, s0, v11                               ; 2C101600
>	s_waitcnt vmcnt(0)                                      ; BF8C0F70
>	exp 15, 34, 0, 0, 0, v16, v17, v18, v19                 ; C400022F 13121110
>	exp 15, 12, 0, 1, 0, v0, v1, v7, v8                     ; C40008CF 08070100
>	s_waitcnt expcnt(0)                                     ; BF8C0F0F
>Shader epilog disassembly:
>	s_endpgm ; BF810000
>
>*** SHADER STATS ***
>SGPRS: 80
>VGPRS: 20
>Code Size: 348 bytes
>LDS: 0 blocks
>Scratch: 0 bytes per wave
>Max Waves: 10
>********************
>SHADER KEY
>  prolog.color_two_side = 0
>  prolog.poly_stipple = 0
>  prolog.force_persample_interp = 0
>  epilog.spi_shader_col_format = 0x4
>  epilog.color_is_int8 = 0x0
>  epilog.last_cbuf = 0
>  epilog.alpha_func = 7
>  epilog.alpha_to_one = 0
>  epilog.poly_line_smoothing = 0
>  epilog.clamp_color = 0
>
>Pixel Shader:
>Shader main disassembly:
>	s_wqm_b64 exec, exec                                    ; BEFE077E
>	s_mov_b32 m0, s11                                       ; BEFC000B
>	v_interp_p1_f32 v8, v2, 0, 0, [m0]                      ; D4200002
>	v_interp_p2_f32 v8, [v8], v3, 0, 0, [m0]                ; D4210003
>	v_mov_b32_e32 v0, 0x44800000                            ; 7E0002FF 44800000
>	v_mad_f32 v0, v0, v8, 0.5                               ; D1C10000 03C21100
>	v_fract_f32_e32 v0, v0                                  ; 7E003700
>	v_mov_b32_e32 v5, 0x3eaaa64c                            ; 7E0A02FF 3EAAA64C
>	v_mov_b32_e32 v6, 0xbeaaa64c                            ; 7E0C02FF BEAAA64C
>	v_interp_p1_f32 v10, v2, 1, 0, [m0]                     ; D4280102
>	v_mad_f32 v16, v0, v5, -0.5                             ; D1C10010 03C60B00
>	v_mad_f32 v17, v0, v6, 0.5                              ; D1C10011 03C20D00
>	v_mov_b32_e32 v4, 0x3e2a9931                            ; 7E0802FF 3E2A9931
>	v_interp_p2_f32 v10, [v10], v3, 1, 0, [m0]              ; D4290103
>	v_interp_p1_f32 v11, v2, 0, 1, [m0]                     ; D42C0402
>	v_mad_f32 v16, v16, v0, -0.5                            ; D1C10010 03C60110
>	v_mov_b32_e32 v18, 0x3f555326                           ; 7E2402FF 3F555326
>	v_mad_f32 v17, v17, v0, 0.5                             ; D1C10011 03C20111
>	v_interp_p2_f32 v11, [v11], v3, 0, 1, [m0]              ; D42D0403
>	v_interp_p1_f32 v14, v2, 1, 1, [m0]                     ; D4380502
>	v_mad_f32 v19, v0, v16, v18                             ; D1C10013 044A2100
>	v_mad_f32 v16, v0, v17, v4                              ; D1C10010 04122300
>	v_interp_p2_f32 v14, [v14], v3, 1, 1, [m0]              ; D4390503
>	v_interp_p1_f32 v15, v2, 0, 2, [m0]                     ; D43C0802
>	v_rcp_f32_e32 v16, v16                                  ; 7E204510
>	v_mad_f32 v12, v0, v4, 0                                ; D1C1000C 02020900
>	v_interp_p2_f32 v15, [v15], v3, 0, 2, [m0]              ; D43D0803
>	v_interp_p1_f32 v2, v2, 1, 2, [m0]                      ; D4080902
>	v_bfrev_b32_e32 v1, 34                                  ; 7E0258A2
>	v_mad_f32 v12, v12, v0, 0                               ; D1C1000C 0202010C
>	v_interp_p2_f32 v2, [v2], v3, 1, 2, [m0]                ; D4090903
>	v_mad_f32 v3, v10, v1, 0.5                              ; D1C10003 03C2030A
>	v_mad_f32 v12, v12, v0, 0                               ; D1C1000C 0202010C
>	v_fract_f32_e32 v3, v3                                  ; 7E063703
>	v_rcp_f32_e32 v17, v19                                  ; 7E224513
>	v_mad_f32 v9, v0, -0.5, 1.0                             ; D1C10009 03C9E300
>	v_mad_f32 v12, v12, v16, 1.0                            ; D1C1000C 03CA210C
>	v_mad_f32 v16, v3, v5, -0.5                             ; D1C10010 03C60B03
>	v_mad_f32 v16, v16, v3, -0.5                            ; D1C10010 03C60710
>	v_mov_b32_e32 v7, 0xbf2aa64c                            ; 7E0E02FF BF2AA64C
>	v_mad_f32 v9, v9, v0, 0                                 ; D1C10009 02020109
>	v_mad_f32 v9, v0, v9, v7                                ; D1C10009 041E1300
>	v_mad_f32 v20, v3, v16, v18                             ; D1C10014 044A2103
>	v_mad_f32 v9, v9, v17, 1.0                              ; D1C10009 03CA2309
>	v_mad_f32 v17, v3, v6, 0.5                              ; D1C10011 03C20D03
>	v_rcp_f32_e32 v16, v20                                  ; 7E204514
>	v_mad_f32 v17, v17, v3, 0.5                             ; D1C10011 03C20711
>	v_add_f32_e32 v9, v0, v9                                ; 02121300
>	v_subrev_f32_e32 v0, v0, v12                            ; 06001900
>	v_mad_f32 v12, v3, -0.5, 1.0                            ; D1C1000C 03C9E303
>	v_mad_f32 v12, v12, v3, 0                               ; D1C1000C 0202070C
>	v_mad_f32 v17, v3, v17, v4                              ; D1C10011 04122303
>	v_mad_f32 v12, v3, v12, v7                              ; D1C1000C 041E1903
>	v_rcp_f32_e32 v17, v17                                  ; 7E224511
>	v_mad_f32 v12, v12, v16, 1.0                            ; D1C1000C 03CA210C
>	v_mad_f32 v16, v3, v4, 0                                ; D1C10010 02020903
>	v_mad_f32 v16, v16, v3, 0                               ; D1C10010 02020710
>	v_mad_f32 v16, v16, v3, 0                               ; D1C10010 02020710
>	v_mad_f32 v16, v16, v17, 1.0                            ; D1C10010 03CA2310
>	s_load_dwordx8 s[20:27], s[4:5], 0x0                    ; C00E0502 00000000
>	s_load_dwordx4 s[28:31], s[4:5], 0x30                   ; C00A0702 00000030
>	v_add_f32_e32 v12, v3, v12                              ; 02181903
>	v_subrev_f32_e32 v3, v3, v16                            ; 06062103
>	v_mov_b32_e32 v16, 0xbb000000                           ; 7E2002FF BB000000
>	v_mov_b32_e32 v17, 0x3b000000                           ; 7E2202FF 3B000000
>	v_mad_f32 v22, v16, v12, v10                            ; D1C10016 042A1910
>	v_mac_f32_e32 v10, v17, v3                              ; 2C140711
>	v_mov_b32_e32 v3, 0xba800000                            ; 7E0602FF BA800000
>	v_mad_f32 v21, v9, v3, v8                               ; D1C10015 04220709
>	v_mov_b32_e32 v24, v22                                  ; 7E300316
>	v_mac_f32_e32 v8, 0x3a800000, v0                        ; 2C1000FF 3A800000
>	v_mov_b32_e32 v23, v21                                  ; 7E2E0315
>	v_mov_b32_e32 v24, v10                                  ; 7E30030A
>	v_mov_b32_e32 v9, v22                                   ; 7E120316
>	s_waitcnt lgkmcnt(0)                                    ; BF8C007F
>	image_sample v0, v[21:22], s[20:27], s[28:31] dmask:0x1 ; F0800100 00E50015
>	s_nop 0                                                 ; BF800000
>	image_sample v3, v[23:24], s[20:27], s[28:31] dmask:0x2 ; F0800200 00E50317
>	s_nop 0                                                 ; BF800000
>	image_sample v21, v[8:9], s[20:27], s[28:31] dmask:0x1  ; F0800100 00E51508
>	v_mov_b32_e32 v9, v10                                   ; 7E12030A
>	image_sample v8, v[8:9], s[20:27], s[28:31] dmask:0x2   ; F0800200 00E50808
>	v_mov_b32_e32 v9, 0x43800000                            ; 7E1202FF 43800000
>	v_mad_f32 v10, v14, v9, 0.5                             ; D1C1000A 03C2130E
>	v_fract_f32_e32 v10, v10                                ; 7E14370A
>	v_mad_f32 v12, v10, v5, -0.5                            ; D1C1000C 03C60B0A
>	v_mad_f32 v12, v12, v10, -0.5                           ; D1C1000C 03C6150C
>	v_mad_f32 v22, v10, v12, v18                            ; D1C10016 044A190A
>	v_rcp_f32_e32 v12, v22                                  ; 7E184516
>	v_mad_f32 v23, v10, -0.5, 1.0                           ; D1C10017 03C9E30A
>	v_mad_f32 v23, v23, v10, 0                              ; D1C10017 02021517
>	v_mad_f32 v23, v10, v23, v7                             ; D1C10017 041E2F0A
>	v_mad_f32 v12, v23, v12, 1.0                            ; D1C1000C 03CA1917
>	v_mad_f32 v23, v10, v6, 0.5                             ; D1C10017 03C20D0A
>	v_mad_f32 v23, v23, v10, 0.5                            ; D1C10017 03C21517
>	v_mad_f32 v23, v10, v23, v4                             ; D1C10017 04122F0A
>	v_rcp_f32_e32 v23, v23                                  ; 7E2E4517
>	v_mad_f32 v24, v10, v4, 0                               ; D1C10018 0202090A
>	v_mad_f32 v24, v24, v10, 0                              ; D1C10018 02021518
>	v_mad_f32 v24, v24, v10, 0                              ; D1C10018 02021518
>	v_mad_f32 v23, v24, v23, 1.0                            ; D1C10017 03CA2F18
>	v_add_f32_e32 v12, v10, v12                             ; 0218190A
>	v_subrev_f32_e32 v10, v10, v23                          ; 06142F0A
>	v_mov_b32_e32 v23, 0xbb800000                           ; 7E2E02FF BB800000
>	v_mov_b32_e32 v24, 0x3b800000                           ; 7E3002FF 3B800000
>	v_mad_f32 v26, v23, v12, v14                            ; D1C1001A 043A1917
>	v_mac_f32_e32 v14, v24, v10                             ; 2C1C1518
>	v_mad_f32 v10, v11, v1, 0.5                             ; D1C1000A 03C2030B
>	v_mad_f32 v1, v15, v1, 0.5                              ; D1C10001 03C2030F
>	v_fract_f32_e32 v1, v1                                  ; 7E023701
>	v_mad_f32 v9, v2, v9, 0.5                               ; D1C10009 03C21302
>	v_mad_f32 v25, v1, -0.5, 1.0                            ; D1C10019 03C9E301
>	v_fract_f32_e32 v10, v10                                ; 7E14370A
>	v_fract_f32_e32 v9, v9                                  ; 7E123709
>	v_mad_f32 v25, v25, v1, 0                               ; D1C10019 02020319
>	v_mad_f32 v12, v10, -0.5, 1.0                           ; D1C1000C 03C9E30A
>	v_mad_f32 v27, v1, v25, v7                              ; D1C1001B 041E3301
>	v_mad_f32 v25, v9, -0.5, 1.0                            ; D1C10019 03C9E309
>	v_mad_f32 v12, v12, v10, 0                              ; D1C1000C 0202150C
>	v_mad_f32 v25, v25, v9, 0                               ; D1C10019 02021319
>	v_mad_f32 v12, v10, v12, v7                             ; D1C1000C 041E190A
>	v_mac_f32_e32 v7, v9, v25                               ; 2C0E3309
>	v_mad_f32 v25, v10, v5, -0.5                            ; D1C10019 03C60B0A
>	v_mad_f32 v25, v25, v10, -0.5                           ; D1C10019 03C61519
>	v_mad_f32 v28, v10, v25, v18                            ; D1C1001C 044A330A
>	v_mad_f32 v25, v1, v5, -0.5                             ; D1C10019 03C60B01
>	v_mad_f32 v5, v9, v5, -0.5                              ; D1C10005 03C60B09
>	v_mad_f32 v25, v25, v1, -0.5                            ; D1C10019 03C60319
>	v_mad_f32 v5, v5, v9, -0.5                              ; D1C10005 03C61305
>	v_mad_f32 v29, v1, v25, v18                             ; D1C1001D 044A3301
>	v_mac_f32_e32 v18, v9, v5                               ; 2C240B09
>	v_mad_f32 v5, v10, v6, 0.5                              ; D1C10005 03C20D0A
>	v_mad_f32 v25, v1, v6, 0.5                              ; D1C10019 03C20D01
>	v_mad_f32 v6, v9, v6, 0.5                               ; D1C10006 03C20D09
>	v_mad_f32 v5, v5, v10, 0.5                              ; D1C10005 03C21505
>	v_mad_f32 v25, v25, v1, 0.5                             ; D1C10019 03C20319
>	v_mad_f32 v6, v6, v9, 0.5                               ; D1C10006 03C21306
>	v_rcp_f32_e32 v32, v18                                  ; 7E404512
>	v_mad_f32 v30, v1, v25, v4                              ; D1C1001E 04123301
>	v_mad_f32 v5, v10, v5, v4                               ; D1C10005 04120B0A
>	v_mad_f32 v25, v10, v4, 0                               ; D1C10019 0202090A
>	v_mad_f32 v31, v1, v4, 0                                ; D1C1001F 02020901
>	v_mad_f32 v33, v9, v4, 0                                ; D1C10021 02020909
>	v_mac_f32_e32 v4, v9, v6                                ; 2C080D09
>	v_rcp_f32_e32 v4, v4                                    ; 7E084504
>	v_mad_f32 v6, v7, v32, 1.0                              ; D1C10006 03CA4107
>	v_mad_f32 v7, v33, v9, 0                                ; D1C10007 02021321
>	v_mad_f32 v7, v7, v9, 0                                 ; D1C10007 02021307
>	v_mad_f32 v4, v7, v4, 1.0                               ; D1C10004 03CA0907
>	v_add_f32_e32 v6, v9, v6                                ; 020C0D09
>	v_subrev_f32_e32 v4, v9, v4                             ; 06080909
>	v_rcp_f32_e32 v7, v28                                   ; 7E0E451C
>	v_mad_f32 v33, v23, v6, v2                              ; D1C10021 040A0D17
>	v_mac_f32_e32 v2, v24, v4                               ; 2C040918
>	v_rcp_f32_e32 v4, v5                                    ; 7E084505
>	v_mad_f32 v6, v25, v10, 0                               ; D1C10006 02021519
>	v_mad_f32 v5, v12, v7, 1.0                              ; D1C10005 03CA0F0C
>	v_mad_f32 v6, v6, v10, 0                                ; D1C10006 02021506
>	v_mad_f32 v4, v6, v4, 1.0                               ; D1C10004 03CA0906
>	v_add_f32_e32 v5, v10, v5                               ; 020A0B0A
>	s_load_dwordx4 s[0:3], s[4:5], 0x70                     ; C00A0002 00000070
>	s_load_dwordx8 s[12:19], s[4:5], 0x40                   ; C00E0302 00000040
>	v_subrev_f32_e32 v4, v10, v4                            ; 0608090A
>	v_mad_f32 v25, v16, v5, v11                             ; D1C10019 042E0B10
>	v_mac_f32_e32 v11, v17, v4                              ; 2C160911
>	v_mov_b32_e32 v4, v25                                   ; 7E080319
>	v_mov_b32_e32 v5, v26                                   ; 7E0A031A
>	v_mov_b32_e32 v5, v14                                   ; 7E0A030E
>	s_waitcnt lgkmcnt(0)                                    ; BF8C007F
>	image_sample v6, v[25:26], s[12:19], s[0:3] dmask:0x1   ; F0800100 00030619
>	s_nop 0                                                 ; BF800000
>	image_sample v4, v[4:5], s[12:19], s[0:3] dmask:0x2     ; F0800200 00030404
>	v_rcp_f32_e32 v5, v29                                   ; 7E0A451D
>	v_mov_b32_e32 v12, v26                                  ; 7E18031A
>	v_rcp_f32_e32 v10, v30                                  ; 7E14451E
>	image_sample v7, v[11:12], s[12:19], s[0:3] dmask:0x1   ; F0800100 0003070B
>	v_mov_b32_e32 v12, v14                                  ; 7E18030E
>	image_sample v9, v[11:12], s[12:19], s[0:3] dmask:0x2   ; F0800200 0003090B
>	v_mad_f32 v5, v27, v5, 1.0                              ; D1C10005 03CA0B1B
>	v_mad_f32 v11, v31, v1, 0                               ; D1C1000B 0202031F
>	s_waitcnt vmcnt(6)                                      ; BF8C0F76
>	v_mad_f32 v3, -v20, v3, v3                              ; D1C10003 240E0714
>	v_mad_f32 v11, v11, v1, 0                               ; D1C1000B 0202030B
>	v_add_f32_e32 v5, v1, v5                                ; 020A0B01
>	v_mac_f32_e32 v3, v20, v0                               ; 2C060114
>	s_waitcnt vmcnt(4)                                      ; BF8C0F74
>	v_mad_f32 v0, -v20, v8, v8                              ; D1C10000 24221114
>	s_load_dwordx8 s[20:27], s[4:5], 0x80                   ; C00E0502 00000080
>	s_load_dwordx4 s[0:3], s[4:5], 0xb0                     ; C00A0002 000000B0
>	v_mad_f32 v10, v11, v10, 1.0                            ; D1C1000A 03CA150B
>	v_mad_f32 v32, v16, v5, v15                             ; D1C10020 043E0B10
>	v_mac_f32_e32 v0, v20, v21                              ; 2C002B14
>	v_subrev_f32_e32 v1, v1, v10                            ; 06021501
>	v_mad_f32 v8, -v19, v0, v0                              ; D1C10008 24020113
>	v_mov_b32_e32 v10, v32                                  ; 7E140320
>	v_mov_b32_e32 v11, v33                                  ; 7E160321
>	v_mac_f32_e32 v8, v19, v3                               ; 2C100713
>	s_waitcnt vmcnt(0)                                      ; BF8C0F70
>	v_mad_f32 v3, -v22, v9, v9                              ; D1C10003 24261316
>	v_mad_f32 v0, -v22, v4, v4                              ; D1C10000 24120916
>	v_mac_f32_e32 v3, v22, v7                               ; 2C060F16
>	v_mac_f32_e32 v15, v17, v1                              ; 2C1E0311
>	v_mov_b32_e32 v11, v2                                   ; 7E160302
>	v_mov_b32_e32 v16, v33                                  ; 7E200321
>	s_waitcnt lgkmcnt(0)                                    ; BF8C007F
>	image_sample v1, v[32:33], s[20:27], s[0:3] dmask:0x1   ; F0800100 00050120
>	s_nop 0                                                 ; BF800000
>	image_sample v5, v[10:11], s[20:27], s[0:3] dmask:0x2   ; F0800200 0005050A
>	s_nop 0                                                 ; BF800000
>	image_sample v10, v[15:16], s[20:27], s[0:3] dmask:0x1  ; F0800100 00050A0F
>	v_mov_b32_e32 v16, v2                                   ; 7E200302
>	v_mac_f32_e32 v0, v22, v6                               ; 2C000D16
>	v_mad_f32 v3, -v28, v3, v3                              ; D1C10003 240E071C
>	v_mac_f32_e32 v3, v28, v0                               ; 2C06011C
>	s_waitcnt vmcnt(1)                                      ; BF8C0F71
>	v_mad_f32 v0, -v18, v5, v5                              ; D1C10000 24160B12
>	image_sample v2, v[15:16], s[20:27], s[0:3] dmask:0x2   ; F0800200 0005020F
>	v_mac_f32_e32 v0, v18, v1                               ; 2C000312
>	s_waitcnt vmcnt(0)                                      ; BF8C0F70
>	v_mad_f32 v1, -v18, v2, v2                              ; D1C10001 240A0512
>	v_mac_f32_e32 v1, v18, v10                              ; 2C021512
>	v_mad_f32 v4, -v29, v1, v1                              ; D1C10004 2406031D
>	v_mov_b32_e32 v2, 0x3f94fdf4                            ; 7E0402FF 3F94FDF4
>	v_mac_f32_e32 v4, v29, v0                               ; 2C08011D
>	v_madak_f32_e32 v0, v8, v2, 0xbf5fc944                  ; 30000508 BF5FC944
>	v_madak_f32_e32 v1, v8, v2, 0x3f0804f3                  ; 30020508 3F0804F3
>	v_madak_f32_e32 v2, v8, v2, 0xbf8b01c9                  ; 30040508 BF8B01C9
>	v_mov_b32_e32 v5, 0xbec83127                            ; 7E0A02FF BEC83127
>	v_mac_f32_e32 v0, 0, v3                                 ; 2C000680
>	v_mac_f32_e32 v2, 0x400126e9, v3                        ; 2C0406FF 400126E9
>	v_mac_f32_e32 v1, v3, v5                                ; 2C020B03
>	v_mov_b32_e32 v3, 0xbf5020c5                            ; 7E0602FF BF5020C5
>	v_mac_f32_e32 v0, 0x3fcc49ba, v4                        ; 2C0008FF 3FCC49BA
>	v_mac_f32_e32 v1, v4, v3                                ; 2C020704
>	v_mac_f32_e32 v2, 0, v4                                 ; 2C040880
>Shader epilog disassembly:
>	v_cvt_pkrtz_f16_f32_e64 v0, v0, v1 ; D2960000 00020300
>	v_cvt_pkrtz_f16_f32_e64 v1, v2, v3 ; D2960001 00020702
>	exp 15, 0, 1, 1, 1, v0, v1, v0, v0 ; C4001C0F 00000100
>	s_endpgm                           ; BF810000
>
>*** SHADER CONFIG ***
>SPI_PS_INPUT_ADDR = 0xd077
>SPI_PS_INPUT_ENA  = 0x0002
>*** SHADER STATS ***
>SGPRS: 80
>VGPRS: 36
>Code Size: 1532 bytes
>LDS: 0 blocks
>Scratch: 0 bytes per wave
>Max Waves: 7
>********************
>Buffer list (in units of pages = 4kB):
>[1;33m        Size    VM start page         VM end page           Usage[0m
>          16    0x000000010061c       0x000000010062c       BORDER_COLORS
>           1    0x000000010062c       0x000000010062d       IB2
>           1    0x000000010062d       0x000000010062e       TRACE
>           2    -- hole --
>          16    0x0000000100630       0x0000000100640       VERTEX_BUFFER
>         171    0x0000000100640       0x00000001006eb       SAMPLER_TEXTURE
>          21    -- hole --
>         288    0x0000000100700       0x0000000100820       COLOR_BUFFER
>         128    -- hole --
>          43    0x00000001008a0       0x00000001008cb       SAMPLER_TEXTURE
>          32    -- hole --
>           1    0x00000001008eb       0x00000001008ec       CMASK
>           1    0x00000001008ec       0x00000001008ed       USER_SHADER
>           1    0x00000001008ed       0x00000001008ee       USER_SHADER
>           2    -- hole --
>          43    0x00000001008f0       0x000000010091b       SAMPLER_TEXTURE
>          32    -- hole --
>         256    0x000000010093b       0x0000000100a3b       CONST_BUFFER, DESCRIPTORS, RINGS_STREAMOUT
>         256    0x0000000100a3b       0x0000000100b3b       DESCRIPTORS
>
>Note: The holes represent memory not used by the IB.
>      Other buffers can still be allocated there.
>
>------------------ IB2: Init config begin ------------------
>[1;32mCONTEXT_CONTROL[0m:
>        0x80000000
>        0x80000000
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_HOS_MAX_TESS_LEVEL[0m <- 64.0f (0x42800000)
>        [1;33mVGT_HOS_MIN_TESS_LEVEL[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_PER_ES[0m <- GS_PER_ES = 128 (0x80)
>        [1;33mVGT_ES_PER_GS[0m <- ES_PER_GS = 64 (0x40)
>        [1;33mVGT_GS_PER_VS[0m <- GS_PER_VS = 2
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_RESET[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_STRMOUT_DRAW_OPAQUE_OFFSET[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_STRMOUT_BUFFER_CONFIG[0m <- STREAM_0_BUFFER_EN = 0
>                                     STREAM_1_BUFFER_EN = 0
>                                     STREAM_2_BUFFER_EN = 0
>                                     STREAM_3_BUFFER_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_VTX_CNT_EN[0m <- VTX_CNT_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_CENTROID_PRIORITY_0[0m <- DISTANCE_0 = 0
>                                     DISTANCE_1 = 1
>                                     DISTANCE_2 = 2
>                                     DISTANCE_3 = 3
>                                     DISTANCE_4 = 4
>                                     DISTANCE_5 = 5
>                                     DISTANCE_6 = 6
>                                     DISTANCE_7 = 7
>        [1;33mPA_SC_CENTROID_PRIORITY_1[0m <- DISTANCE_8 = 8
>                                     DISTANCE_9 = 9
>                                     DISTANCE_10 = 10 (0xa)
>                                     DISTANCE_11 = 11 (0xb)
>                                     DISTANCE_12 = 12 (0xc)
>                                     DISTANCE_13 = 13 (0xd)
>                                     DISTANCE_14 = 14 (0xe)
>                                     DISTANCE_15 = 15 (0xf)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_PRIM_FILTER_CNTL[0m <- TRIANGLE_FILTER_DISABLE = 0
>                                  LINE_FILTER_DISABLE = 0
>                                  POINT_FILTER_DISABLE = 0
>                                  RECTANGLE_FILTER_DISABLE = 0
>                                  TRIANGLE_EXPAND_ENA = 0
>                                  LINE_EXPAND_ENA = 0
>                                  POINT_EXPAND_ENA = 0
>                                  RECTANGLE_EXPAND_ENA = 0
>                                  PRIM_EXPAND_CONSTANT = 0
>                                  XMAX_RIGHT_EXCLUSION = 0
>                                  YMAX_BOTTOM_EXCLUSION = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_VPORT_ZMIN_0[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_0[0m <- 1.0f (0x3f800000)
>        [1;33mPA_SC_VPORT_ZMIN_1[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_1[0m <- 1.0f (0x3f800000)
>        [1;33mPA_SC_VPORT_ZMIN_2[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_2[0m <- 1.0f (0x3f800000)
>        [1;33mPA_SC_VPORT_ZMIN_3[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_3[0m <- 1.0f (0x3f800000)
>        [1;33mPA_SC_VPORT_ZMIN_4[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_4[0m <- 1.0f (0x3f800000)
>        [1;33mPA_SC_VPORT_ZMIN_5[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_5[0m <- 1.0f (0x3f800000)
>        [1;33mPA_SC_VPORT_ZMIN_6[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_6[0m <- 1.0f (0x3f800000)
>        [1;33mPA_SC_VPORT_ZMIN_7[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_7[0m <- 1.0f (0x3f800000)
>        [1;33mPA_SC_VPORT_ZMIN_8[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_8[0m <- 1.0f (0x3f800000)
>        [1;33mPA_SC_VPORT_ZMIN_9[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_9[0m <- 1.0f (0x3f800000)
>        [1;33mPA_SC_VPORT_ZMIN_10[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_10[0m <- 1.0f (0x3f800000)
>        [1;33mPA_SC_VPORT_ZMIN_11[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_11[0m <- 1.0f (0x3f800000)
>        [1;33mPA_SC_VPORT_ZMIN_12[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_12[0m <- 1.0f (0x3f800000)
>        [1;33mPA_SC_VPORT_ZMIN_13[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_13[0m <- 1.0f (0x3f800000)
>        [1;33mPA_SC_VPORT_ZMIN_14[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_14[0m <- 1.0f (0x3f800000)
>        [1;33mPA_SC_VPORT_ZMIN_15[0m <- 0
>        [1;33mPA_SC_VPORT_ZMAX_15[0m <- 1.0f (0x3f800000)
>        [1;33mPA_SC_RASTER_CONFIG[0m <- RB_MAP_PKR0 = RASTER_CONFIG_RB_MAP_2
>                               RB_MAP_PKR1 = RASTER_CONFIG_RB_MAP_0
>                               RB_XSEL2 = RASTER_CONFIG_RB_XSEL2_1
>                               RB_XSEL = 0
>                               RB_YSEL = 0
>                               PKR_MAP = RASTER_CONFIG_PKR_MAP_0
>                               PKR_XSEL = RASTER_CONFIG_PKR_XSEL_0
>                               PKR_YSEL = RASTER_CONFIG_PKR_YSEL_0
>                               PKR_XSEL2 = RASTER_CONFIG_PKR_XSEL2_0
>                               SC_MAP = RASTER_CONFIG_SC_MAP_0
>                               SC_XSEL = RASTER_CONFIG_SC_XSEL_8_WIDE_TILE
>                               SC_YSEL = RASTER_CONFIG_SC_YSEL_8_WIDE_TILE
>                               SE_MAP = RASTER_CONFIG_SE_MAP_2
>                               SE_XSEL = RASTER_CONFIG_SE_XSEL_16_WIDE_TILE
>                               SE_YSEL = RASTER_CONFIG_SE_YSEL_16_WIDE_TILE
>        [1;33mPA_SC_RASTER_CONFIG_1[0m <- SE_PAIR_MAP = RASTER_CONFIG_SE_PAIR_MAP_2
>                                 SE_PAIR_XSEL = RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE
>                                 SE_PAIR_YSEL = RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_TL[0m <- TL_X = 0
>                                   TL_Y = 0
>                                   WINDOW_OFFSET_DISABLE = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_GENERIC_SCISSOR_TL[0m <- TL_X = 0
>                                    TL_Y = 0
>                                    WINDOW_OFFSET_DISABLE = 1
>        [1;33mPA_SC_GENERIC_SCISSOR_BR[0m <- BR_X = 16384 (0x4000)
>                                    BR_Y = 16384 (0x4000)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_SCREEN_SCISSOR_TL[0m <- TL_X = 0
>                                   TL_Y = 0
>        [1;33mPA_SC_SCREEN_SCISSOR_BR[0m <- BR_X = 16384 (0x4000)
>                                   BR_Y = 16384 (0x4000)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_CLIPRECT_RULE[0m <- CLIP_RULE = 0.0f (0xffff)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_EDGERULE[0m <- ER_TRI = 10 (0xa)
>                          ER_POINT = 10 (0xa)
>                          ER_RECT = 10 (0xa)
>                          ER_LINE_LR = 42 (0x2a)
>                          ER_LINE_RL = 42 (0x2a)
>                          ER_LINE_TB = 10 (0xa)
>                          ER_LINE_BT = 10 (0xa)
>        [1;33mPA_SU_HARDWARE_SCREEN_OFFSET[0m <- HW_SCREEN_OFFSET_X = 0
>                                        HW_SCREEN_OFFSET_Y = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_NANINF_CNTL[0m <- VTE_XY_INF_DISCARD = 0
>                             VTE_Z_INF_DISCARD = 0
>                             VTE_W_INF_DISCARD = 0
>                             VTE_0XNANINF_IS_0 = 0
>                             VTE_XY_NAN_RETAIN = 0
>                             VTE_Z_NAN_RETAIN = 0
>                             VTE_W_NAN_RETAIN = 0
>                             VTE_W_RECIP_NAN_IS_0 = 0
>                             VS_XY_NAN_TO_INF = 0
>                             VS_XY_INF_RETAIN = 0
>                             VS_Z_NAN_TO_INF = 0
>                             VS_Z_INF_RETAIN = 0
>                             VS_W_NAN_TO_INF = 0
>                             VS_W_INF_RETAIN = 0
>                             VS_CLIP_DIST_INF_DISCARD = 0
>                             VTE_NO_OUTPUT_NEG_0 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SRESULTS_COMPARE_STATE0[0m <- COMPAREFUNC0 = REF_NEVER
>                                      COMPAREVALUE0 = 0
>                                      COMPAREMASK0 = 0
>                                      ENABLE0 = 0
>        [1;33mDB_SRESULTS_COMPARE_STATE1[0m <- COMPAREFUNC1 = REF_NEVER
>                                      COMPAREVALUE1 = 0
>                                      COMPAREMASK1 = 0
>                                      ENABLE1 = 0
>        [1;33mDB_PRELOAD_CONTROL[0m <- START_X = 0
>                              START_Y = 0
>                              MAX_X = 0
>                              MAX_Y = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE[0m <- FORCE_HIZ_ENABLE = FORCE_OFF
>                              FORCE_HIS_ENABLE0 = FORCE_DISABLE
>                              FORCE_HIS_ENABLE1 = FORCE_DISABLE
>                              FORCE_SHADER_Z_ORDER = 0
>                              FAST_Z_DISABLE = 0
>                              FAST_STENCIL_DISABLE = 0
>                              NOOP_CULL_DISABLE = 0
>                              FORCE_COLOR_KILL = 0
>                              FORCE_Z_READ = 0
>                              FORCE_STENCIL_READ = 0
>                              FORCE_FULL_Z_RANGE = FORCE_OFF
>                              FORCE_QC_SMASK_CONFLICT = 0
>                              DISABLE_VIEWPORT_CLAMP = 0
>                              IGNORE_SC_ZRANGE = 0
>                              DISABLE_FULLY_COVERED = 0
>                              FORCE_Z_LIMIT_SUMM = FORCE_SUMM_OFF
>                              MAX_TILES_IN_DTT = 0
>                              DISABLE_TILE_RATE_TILES = 0
>                              FORCE_Z_DIRTY = 0
>                              FORCE_STENCIL_DIRTY = 0
>                              FORCE_Z_VALID = 0
>                              FORCE_STENCIL_VALID = 0
>                              PRESERVE_COMPRESSION = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_MAX_VTX_INDX[0m <- 0xffffffff
>        [1;33mVGT_MIN_VTX_INDX[0m <- 0
>        [1;33mVGT_INDX_OFFSET[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_RSRC3_HS[0m <- WAVE_LIMIT = 0
>                                   LOCK_LOW_THRESHOLD = 0
>                                   GROUP_FIFO_DEPTH = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_RSRC3_ES[0m <- CU_EN = 0.0f (0xffff)
>                                   WAVE_LIMIT = 0
>                                   LOCK_LOW_THRESHOLD = 0
>                                   GROUP_FIFO_DEPTH = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_RSRC3_GS[0m <- CU_EN = 0.0f (0xffff)
>                                   WAVE_LIMIT = 0
>                                   LOCK_LOW_THRESHOLD = 0
>                                   GROUP_FIFO_DEPTH = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_RSRC3_LS[0m <- CU_EN = 0.0f (0xfffe)
>                                   WAVE_LIMIT = 0
>                                   LOCK_LOW_THRESHOLD = 0
>                                   GROUP_FIFO_DEPTH = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_RSRC3_VS[0m <- CU_EN = 0.0f (0xfffe)
>                                   WAVE_LIMIT = 0
>                                   LOCK_LOW_THRESHOLD = 0
>        [1;33mSPI_SHADER_LATE_ALLOC_VS[0m <- LIMIT = 31 (0x1f)
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_RSRC3_PS[0m <- CU_EN = 0.0f (0xffff)
>                                   WAVE_LIMIT = 0
>                                   LOCK_LOW_THRESHOLD = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_DCC_CONTROL[0m <- OVERWRITE_COMBINER_DISABLE = 0
>                          OVERWRITE_COMBINER_MRT_SHARING_DISABLE = 1
>                          OVERWRITE_COMBINER_WATERMARK = 4
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_VERTEX_REUSE_BLOCK_CNTL[0m <- VTX_REUSE_DEPTH = 30 (0x1e)
>        [1;33mVGT_OUT_DEALLOC_CNTL[0m <- DEALLOC_DIST = 32 (0x20)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mTA_BC_BASE_ADDR[0m <- 0x010061c0
>        [1;33mTA_BC_BASE_ADDR_HI[0m <- ADDRESS = 0
>------------------- IB2: Init config end -------------------
>
>------------------ IB begin ------------------
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0.0f (0x0062d000)
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000001
>[1;32mNOP[0m:
>        [31mTrace point ID: 1
>        [31mThis trace point was reached by the CP.[0m
>[1;32mINDIRECT_BUFFER_CIK[0m:
>        0x0062c000
>        0x00000001
>        0x00000088
>[1;32mPFP_SYNC_ME[0m:
>        0x00000000
>[1;32mSURFACE_SYNC[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         CB0_DEST_BASE_ENA = 0
>                         CB1_DEST_BASE_ENA = 0
>                         CB2_DEST_BASE_ENA = 0
>                         CB3_DEST_BASE_ENA = 0
>                         CB4_DEST_BASE_ENA = 0
>                         CB5_DEST_BASE_ENA = 0
>                         CB6_DEST_BASE_ENA = 0
>                         CB7_DEST_BASE_ENA = 0
>                         DB_DEST_BASE_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 0
>                         TC_ACTION_ENA = 0
>                         CB_ACTION_ENA = 0
>                         DB_ACTION_ENA = 0
>                         SH_KCACHE_ACTION_ENA = 1
>                         SH_ICACHE_ACTION_ENA = 1
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = PIPELINESTAT_START
>        [1;33mEVENT_INDEX[0m <- 0
>        [1;33mINV_L2[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_STRMOUT_BUFFER_CONFIG[0m <- STREAM_0_BUFFER_EN = 0
>                                     STREAM_1_BUFFER_EN = 0
>                                     STREAM_2_BUFFER_EN = 0
>                                     STREAM_3_BUFFER_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_STRMOUT_CONFIG[0m <- STREAMOUT_0_EN = 0
>                              STREAMOUT_1_EN = 0
>                              STREAMOUT_2_EN = 0
>                              STREAMOUT_3_EN = 0
>                              RAST_STREAM = 0
>                              RAST_STREAM_MASK = 0
>                              USE_RAST_STREAM_MASK = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR0_BASE[0m <- 0x01007000
>        [1;33mCB_COLOR0_PITCH[0m <- TILE_MAX = 95 (0x5f)
>                           FMASK_TILE_MAX = 95 (0x5f)
>        [1;33mCB_COLOR0_SLICE[0m <- TILE_MAX = 4607 (0x011ff)
>        [1;33mCB_COLOR0_VIEW[0m <- SLICE_START = 0
>                          SLICE_MAX = 0
>        [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_8_8_8_8
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_ALT
>                          FAST_CLEAR = 1
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 1
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>        [1;33mCB_COLOR0_ATTRIB[0m <- TILE_MODE_INDEX = 10 (0xa)
>                            FMASK_TILE_MODE_INDEX = 10 (0xa)
>                            FMASK_BANK_HEIGHT = 0
>                            NUM_SAMPLES = 0
>                            NUM_FRAGMENTS = 0
>                            FORCE_DST_ALPHA_1 = 1
>        [1;33mCB_COLOR0_DCC_CONTROL[0m <- OVERWRITE_COMBINER_DISABLE = 0
>                                 KEY_CLEAR_ENABLE = 0
>                                 MAX_UNCOMPRESSED_BLOCK_SIZE = 0
>                                 MIN_COMPRESSED_BLOCK_SIZE = 0
>                                 MAX_COMPRESSED_BLOCK_SIZE = 0
>                                 COLOR_TRANSFORM = 0
>                                 INDEPENDENT_64B_BLOCKS = 0
>                                 LOSSY_RGB_PRECISION = 0
>                                 LOSSY_ALPHA_PRECISION = 0
>        [1;33mCB_COLOR0_CMASK[0m <- 0x01008eb0
>        [1;33mCB_COLOR0_CMASK_SLICE[0m <- TILE_MAX = 31 (0x01f)
>        [1;33mCB_COLOR0_FMASK[0m <- 0x01007000
>        [1;33mCB_COLOR0_FMASK_SLICE[0m <- TILE_MAX = 4607 (0x011ff)
>        [1;33mCB_COLOR0_CLEAR_WORD0[0m <- 0xff000000
>        [1;33mCB_COLOR0_CLEAR_WORD1[0m <- 0
>        [1;33mCB_COLOR0_DCC_BASE[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR1_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_8_8_8_8
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_ALT
>                          FAST_CLEAR = 1
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 1
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR2_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_INVALID
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR3_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_INVALID
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR4_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_INVALID
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR5_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_INVALID
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR6_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_INVALID
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR7_INFO[0m <- ENDIAN = ENDIAN_NONE
>                          FORMAT = COLOR_INVALID
>                          LINEAR_GENERAL = 0
>                          NUMBER_TYPE = NUMBER_UNORM
>                          COMP_SWAP = SWAP_STD
>                          FAST_CLEAR = 0
>                          COMPRESSION = 0
>                          BLEND_CLAMP = 0
>                          BLEND_BYPASS = 0
>                          SIMPLE_FLOAT = 0
>                          ROUND_MODE = 0
>                          CMASK_IS_LINEAR = 0
>                          BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                          BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                          FMASK_COMPRESSION_DISABLE = 0
>                          FMASK_COMPRESS_1FRAG_ONLY = 0
>                          DCC_ENABLE = 0
>                          CMASK_ADDR_TYPE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_Z_INFO[0m <- FORMAT = Z_INVALID
>                     NUM_SAMPLES = 0
>                     TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                     TILE_MODE_INDEX = 0
>                     DECOMPRESS_ON_N_ZPLANES = 0
>                     ALLOW_EXPCLEAR = 0
>                     READ_SIZE = 0
>                     TILE_SURFACE_ENABLE = 0
>                     CLEAR_DISALLOWED = 0
>                     ZRANGE_PRECISION = 0
>        [1;33mDB_STENCIL_INFO[0m <- FORMAT = STENCIL_INVALID
>                           TILE_SPLIT = ADDR_SURF_TILE_SPLIT_64B
>                           TILE_MODE_INDEX = 0
>                           ALLOW_EXPCLEAR = 0
>                           TILE_STENCIL_DISABLE = 0
>                           CLEAR_DISALLOWED = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 640 (0x280)
>                                   BR_Y = 341 (0x155)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0[0m <- S0_X = 1
>                                             S0_Y = 13 (0xd)
>                                             S1_X = 15 (0xf)
>                                             S1_Y = 3
>                                             S2_X = 5
>                                             S2_Y = 1
>                                             S3_X = 13 (0xd)
>                                             S3_Y = 11 (0xb)
>        [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1[0m <- S4_X = 11 (0xb)
>                                             S4_Y = 5
>                                             S5_X = 9
>                                             S5_Y = 15 (0xf)
>                                             S6_X = 3
>                                             S6_Y = 7
>                                             S7_X = 7
>                                             S7_Y = 9
>        [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2[0m <- S8_X = 0
>                                             S8_Y = 0
>                                             S9_X = 0
>                                             S9_Y = 0
>                                             S10_X = 0
>                                             S10_Y = 0
>                                             S11_X = 0
>                                             S11_Y = 0
>        [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3[0m <- S12_X = 0
>                                             S12_Y = 0
>                                             S13_X = 0
>                                             S13_Y = 0
>                                             S14_X = 0
>                                             S14_Y = 0
>                                             S15_X = 0
>                                             S15_Y = 0
>        [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0[0m <- S0_X = 1
>                                             S0_Y = 13 (0xd)
>                                             S1_X = 15 (0xf)
>                                             S1_Y = 3
>                                             S2_X = 5
>                                             S2_Y = 1
>                                             S3_X = 13 (0xd)
>                                             S3_Y = 11 (0xb)
>        [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1[0m <- S4_X = 11 (0xb)
>                                             S4_Y = 5
>                                             S5_X = 9
>                                             S5_Y = 15 (0xf)
>                                             S6_X = 3
>                                             S6_Y = 7
>                                             S7_X = 7
>                                             S7_Y = 9
>        [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2[0m <- S8_X = 0
>                                             S8_Y = 0
>                                             S9_X = 0
>                                             S9_Y = 0
>                                             S10_X = 0
>                                             S10_Y = 0
>                                             S11_X = 0
>                                             S11_Y = 0
>        [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3[0m <- S12_X = 0
>                                             S12_Y = 0
>                                             S13_X = 0
>                                             S13_Y = 0
>                                             S14_X = 0
>                                             S14_Y = 0
>                                             S15_X = 0
>                                             S15_Y = 0
>        [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0[0m <- S0_X = 1
>                                             S0_Y = 13 (0xd)
>                                             S1_X = 15 (0xf)
>                                             S1_Y = 3
>                                             S2_X = 5
>                                             S2_Y = 1
>                                             S3_X = 13 (0xd)
>                                             S3_Y = 11 (0xb)
>        [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1[0m <- S4_X = 11 (0xb)
>                                             S4_Y = 5
>                                             S5_X = 9
>                                             S5_Y = 15 (0xf)
>                                             S6_X = 3
>                                             S6_Y = 7
>                                             S7_X = 7
>                                             S7_Y = 9
>        [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2[0m <- S8_X = 0
>                                             S8_Y = 0
>                                             S9_X = 0
>                                             S9_Y = 0
>                                             S10_X = 0
>                                             S10_Y = 0
>                                             S11_X = 0
>                                             S11_Y = 0
>        [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3[0m <- S12_X = 0
>                                             S12_Y = 0
>                                             S13_X = 0
>                                             S13_Y = 0
>                                             S14_X = 0
>                                             S14_Y = 0
>                                             S15_X = 0
>                                             S15_Y = 0
>        [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0[0m <- S0_X = 1
>                                             S0_Y = 13 (0xd)
>                                             S1_X = 15 (0xf)
>                                             S1_Y = 3
>                                             S2_X = 5
>                                             S2_Y = 1
>                                             S3_X = 13 (0xd)
>                                             S3_Y = 11 (0xb)
>        [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1[0m <- S4_X = 11 (0xb)
>                                             S4_Y = 5
>                                             S5_X = 9
>                                             S5_Y = 15 (0xf)
>                                             S6_X = 3
>                                             S6_Y = 7
>                                             S7_X = 7
>                                             S7_Y = 9
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_CONTROL[0m <- DEPTH_CLEAR_ENABLE = 0
>                             STENCIL_CLEAR_ENABLE = 0
>                             DEPTH_COPY = 0
>                             STENCIL_COPY = 0
>                             RESUMMARIZE_ENABLE = 0
>                             STENCIL_COMPRESS_DISABLE = 0
>                             DEPTH_COMPRESS_DISABLE = 0
>                             COPY_CENTROID = 0
>                             COPY_SAMPLE = 0
>                             DECOMPRESS_ENABLE = 0
>        [1;33mDB_COUNT_CONTROL[0m <- ZPASS_INCREMENT_DISABLE = 0
>                            PERFECT_ZPASS_COUNTS = 0
>                            SAMPLE_RATE = 0
>                            ZPASS_ENABLE = 0
>                            ZFAIL_ENABLE = 0
>                            SFAIL_ENABLE = 0
>                            DBFAIL_ENABLE = 0
>                            SLICE_EVEN_ENABLE = 0
>                            SLICE_ODD_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_RENDER_OVERRIDE2[0m <- PARTIAL_SQUAD_LAUNCH_CONTROL = PSLC_AUTO
>                               PARTIAL_SQUAD_LAUNCH_COUNTDOWN = 0
>                               DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_SMEM_EXPCLEAR_OPTIMIZATION = 0
>                               DISABLE_COLOR_ON_VALIDATION = 0
>                               DECOMPRESS_Z_ON_FLUSH = 0
>                               DISABLE_REG_SNOOP = 0
>                               DEPTH_BOUNDS_HIER_DEPTH_DISABLE = 0
>                               SEPARATE_HIZS_FUNC_ENABLE = 0
>                               HIZ_ZFUNC = 0
>                               HIS_SFUNC_FF = 0
>                               HIS_SFUNC_BF = 0
>                               PRESERVE_ZRANGE = 0
>                               PRESERVE_SRESULTS = 0
>                               DISABLE_FAST_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                             STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                             STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                             Z_ORDER = EARLY_Z_THEN_RE_Z
>                             KILL_ENABLE = 0
>                             COVERAGE_TO_MASK_ENABLE = 0
>                             MASK_EXPORT_ENABLE = 0
>                             EXEC_ON_HIER_FAIL = 0
>                             EXEC_ON_NOOP = 0
>                             ALPHA_TO_MASK_DISABLE = 0
>                             DEPTH_BEFORE_SHADER = 0
>                             CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>                             DUAL_QUAD_DISABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_LINE_CNTL[0m <- EXPAND_LINE_WIDTH = 0
>                           LAST_PIXEL = 1
>                           PERPENDICULAR_ENDCAP_ENA = 0
>                           DX10_DIAMOND_TEST_ENA = 0
>        [1;33mPA_SC_AA_CONFIG[0m <- MSAA_NUM_SAMPLES = 0
>                           AA_MASK_CENTROID_DTMN = 0
>                           MAX_SAMPLE_DIST = 0
>                           MSAA_EXPOSED_SAMPLES = 0
>                           DETAIL_TO_EXPOSED_MODE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_EQAA[0m <- MAX_ANCHOR_SAMPLES = 0
>                   PS_ITER_SAMPLES = 0
>                   MASK_EXPORT_NUM_SAMPLES = 0
>                   ALPHA_TO_MASK_NUM_SAMPLES = 0
>                   HIGH_QUALITY_INTERSECTIONS = 1
>                   INCOHERENT_EQAA_READS = 0
>                   INTERPOLATE_COMP_Z = 0
>                   INTERPOLATE_SRC_Z = 0
>                   STATIC_ANCHOR_ASSOCIATIONS = 1
>                   ALPHA_TO_MASK_EQAA_DISABLE = 0
>                   OVERRASTERIZATION_AMOUNT = 0
>                   ENABLE_POSTZ_OVERRASTERIZATION = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_1[0m <- WALK_SIZE = 0
>                             WALK_ALIGNMENT = 0
>                             WALK_ALIGN8_PRIM_FITS_ST = 0
>                             WALK_FENCE_ENABLE = 0
>                             WALK_FENCE_SIZE = 0
>                             SUPERTILE_WALK_ORDER_ENABLE = 0
>                             TILE_WALK_ORDER_ENABLE = 0
>                             TILE_COVER_DISABLE = 0
>                             TILE_COVER_NO_SCISSOR = 0
>                             ZMM_LINE_EXTENT = 0
>                             ZMM_LINE_OFFSET = 0
>                             ZMM_RECT_EXTENT = 0
>                             KILL_PIX_POST_HI_Z = 0
>                             KILL_PIX_POST_DETAIL_MASK = 0
>                             PS_ITER_SAMPLE = 0
>                             MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE = 0
>                             MULTI_GPU_SUPERTILE_ENABLE = 0
>                             GPU_ID_OVERRIDE_ENABLE = 0
>                             GPU_ID_OVERRIDE = 0
>                             MULTI_GPU_PRIM_DISCARD_ENABLE = 0
>                             FORCE_EOV_CNTDWN_ENABLE = 1
>                             FORCE_EOV_REZ_ENABLE = 1
>                             OUT_OF_ORDER_PRIMITIVE_ENABLE = 0
>                             OUT_OF_ORDER_WATER_MARK = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_AA_MASK_X0Y0_X1Y0[0m <- AA_MASK_X0Y0 = 0.0f (0xffff)
>                                   AA_MASK_X1Y0 = 0.0f (0xffff)
>        [1;33mPA_SC_AA_MASK_X0Y1_X1Y1[0m <- AA_MASK_X0Y1 = 0.0f (0xffff)
>                                   AA_MASK_X1Y1 = 0.0f (0xffff)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15 (0xf)
>                          TARGET1_ENABLE = 0
>                          TARGET2_ENABLE = 0
>                          TARGET3_ENABLE = 0
>                          TARGET4_ENABLE = 0
>                          TARGET5_ENABLE = 0
>                          TARGET6_ENABLE = 0
>                          TARGET7_ENABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND_RED[0m <- 0
>        [1;33mCB_BLEND_GREEN[0m <- 0
>        [1;33mCB_BLEND_BLUE[0m <- 0
>        [1;33mCB_BLEND_ALPHA[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VS_OUT_CNTL[0m <- CLIP_DIST_ENA_0 = 0
>                             CLIP_DIST_ENA_1 = 0
>                             CLIP_DIST_ENA_2 = 0
>                             CLIP_DIST_ENA_3 = 0
>                             CLIP_DIST_ENA_4 = 0
>                             CLIP_DIST_ENA_5 = 0
>                             CLIP_DIST_ENA_6 = 0
>                             CLIP_DIST_ENA_7 = 0
>                             CULL_DIST_ENA_0 = 0
>                             CULL_DIST_ENA_1 = 0
>                             CULL_DIST_ENA_2 = 0
>                             CULL_DIST_ENA_3 = 0
>                             CULL_DIST_ENA_4 = 0
>                             CULL_DIST_ENA_5 = 0
>                             CULL_DIST_ENA_6 = 0
>                             CULL_DIST_ENA_7 = 0
>                             USE_VTX_POINT_SIZE = 0
>                             USE_VTX_EDGE_FLAG = 0
>                             USE_VTX_RENDER_TARGET_INDX = 0
>                             USE_VTX_VIEWPORT_INDX = 0
>                             USE_VTX_KILL_FLAG = 0
>                             VS_OUT_MISC_VEC_ENA = 0
>                             VS_OUT_CCDIST0_VEC_ENA = 0
>                             VS_OUT_CCDIST1_VEC_ENA = 0
>                             VS_OUT_MISC_SIDE_BUS_ENA = 1
>                             USE_VTX_GS_CUT_FLAG = 0
>                             USE_VTX_LINE_WIDTH = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                           UCP_ENA_1 = 0
>                           UCP_ENA_2 = 0
>                           UCP_ENA_3 = 0
>                           UCP_ENA_4 = 0
>                           UCP_ENA_5 = 0
>                           PS_UCP_Y_SCALE_NEG = 0
>                           PS_UCP_MODE = 3
>                           CLIP_DISABLE = 0
>                           UCP_CULL_ONLY_ENA = 0
>                           BOUNDARY_EDGE_FLAG_ENA = 0
>                           DX_CLIP_SPACE_DEF = 0
>                           DIS_CLIP_ERR_DETECT = 0
>                           VTX_KILL_OR = 0
>                           DX_RASTERIZATION_KILL = 0
>                           DX_LINEAR_ATTR_CLIP_ENA = 1
>                           VTE_VPORT_PROVOKE_DISABLE = 0
>                           ZCLIP_NEAR_DISABLE = 0
>                           ZCLIP_FAR_DISABLE = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_REUSE_OFF[0m <- REUSE_OFF = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_UCP_0_X[0m <- 0
>        [1;33mPA_CL_UCP_0_Y[0m <- 0
>        [1;33mPA_CL_UCP_0_Z[0m <- 0
>        [1;33mPA_CL_UCP_0_W[0m <- 0
>        [1;33mPA_CL_UCP_1_X[0m <- 0
>        [1;33mPA_CL_UCP_1_Y[0m <- 0
>        [1;33mPA_CL_UCP_1_Z[0m <- 0
>        [1;33mPA_CL_UCP_1_W[0m <- 0
>        [1;33mPA_CL_UCP_2_X[0m <- 0
>        [1;33mPA_CL_UCP_2_Y[0m <- 0
>        [1;33mPA_CL_UCP_2_Z[0m <- 0
>        [1;33mPA_CL_UCP_2_W[0m <- 0
>        [1;33mPA_CL_UCP_3_X[0m <- 0
>        [1;33mPA_CL_UCP_3_Y[0m <- 0
>        [1;33mPA_CL_UCP_3_Z[0m <- 0
>        [1;33mPA_CL_UCP_3_W[0m <- 0
>        [1;33mPA_CL_UCP_4_X[0m <- 0
>        [1;33mPA_CL_UCP_4_Y[0m <- 0
>        [1;33mPA_CL_UCP_4_Z[0m <- 0
>        [1;33mPA_CL_UCP_4_W[0m <- 0
>        [1;33mPA_CL_UCP_5_X[0m <- 0
>        [1;33mPA_CL_UCP_5_Y[0m <- 0
>        [1;33mPA_CL_UCP_5_Z[0m <- 0
>        [1;33mPA_CL_UCP_5_W[0m <- 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_0[0m <- 0x00a3f800
>        [1;33mSPI_SHADER_USER_DATA_PS_1[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_0[0m <- 0x00a3f800
>        [1;33mSPI_SHADER_USER_DATA_VS_1[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_GS_0[0m <- 0x00a3f800
>        [1;33mSPI_SHADER_USER_DATA_GS_1[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_ES_0[0m <- 0x00a3f800
>        [1;33mSPI_SHADER_USER_DATA_ES_1[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_HS_0[0m <- 0x00a3f800
>        [1;33mSPI_SHADER_USER_DATA_HS_1[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x00a40300
>        [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x00a3b100
>        [1;33mSPI_SHADER_USER_DATA_VS_9[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_4[0m <- 0x00a3b200
>        [1;33mSPI_SHADER_USER_DATA_VS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_6[0m <- 0x00a3ba00
>        [1;33mSPI_SHADER_USER_DATA_VS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x00a40400
>        [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_8[0m <- 0x00a3bd00
>        [1;33mSPI_SHADER_USER_DATA_PS_9[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_4[0m <- 0x00a40500
>        [1;33mSPI_SHADER_USER_DATA_PS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_PS_6[0m <- 0x00a3c600
>        [1;33mSPI_SHADER_USER_DATA_PS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_GS_2[0m <- 0x00a3c800
>        [1;33mSPI_SHADER_USER_DATA_GS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_GS_8[0m <- 0x00a3c900
>        [1;33mSPI_SHADER_USER_DATA_GS_9[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_GS_4[0m <- 0x00a3ca00
>        [1;33mSPI_SHADER_USER_DATA_GS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_GS_6[0m <- 0x00a3d200
>        [1;33mSPI_SHADER_USER_DATA_GS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_HS_2[0m <- 0x00a3d400
>        [1;33mSPI_SHADER_USER_DATA_HS_3[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_HS_8[0m <- 0x00a3d500
>        [1;33mSPI_SHADER_USER_DATA_HS_9[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_HS_4[0m <- 0x00a3d600
>        [1;33mSPI_SHADER_USER_DATA_HS_5[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_HS_6[0m <- 0x00a3de00
>        [1;33mSPI_SHADER_USER_DATA_HS_7[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_10[0m <- 0x0093c700
>        [1;33mSPI_SHADER_USER_DATA_VS_11[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_VPORT_SCISSOR_0_TL[0m <- TL_X = 0
>                                    TL_Y = 0
>                                    WINDOW_OFFSET_DISABLE = 1
>        [1;33mPA_SC_VPORT_SCISSOR_0_BR[0m <- BR_X = 640 (0x280)
>                                    BR_Y = 341 (0x155)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_GB_VERT_CLIP_ADJ[0m <- 0x433f2e8c
>        [1;33mPA_CL_GB_VERT_DISC_ADJ[0m <- 1.0f (0x3f800000)
>        [1;33mPA_CL_GB_HORZ_CLIP_ADJ[0m <- 0x42cacb33
>        [1;33mPA_CL_GB_HORZ_DISC_ADJ[0m <- 1.0f (0x3f800000)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VPORT_XSCALE[0m <- 320.0f (0x43a00000)
>        [1;33mPA_CL_VPORT_XOFFSET[0m <- 320.0f (0x43a00000)
>        [1;33mPA_CL_VPORT_YSCALE[0m <- -170.5f (0xc32a8000)
>        [1;33mPA_CL_VPORT_YOFFSET[0m <- 170.5f (0x432a8000)
>        [1;33mPA_CL_VPORT_ZSCALE[0m <- 0.5f (0x3f000000)
>        [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0.5f (0x3f000000)
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCILREFMASK[0m <- STENCILTESTVAL = 0
>                             STENCILMASK = 0
>                             STENCILWRITEMASK = 0
>                             STENCILOPVAL = 1
>        [1;33mDB_STENCILREFMASK_BF[0m <- STENCILTESTVAL_BF = 0
>                                STENCILMASK_BF = 0
>                                STENCILWRITEMASK_BF = 0
>                                STENCILOPVAL_BF = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>        [1;33mSPI_PS_INPUT_CNTL_2[0m <- OFFSET = 2
>                               DEFAULT_VAL = X_0_0F
>                               FLAT_SHADE = 0
>                               CYL_WRAP = 0
>                               PT_SPRITE_TEX = 0
>                               DUP = 0
>                               FP16_INTERP_MODE = 0
>                               USE_DEFAULT_ATTR1 = 0
>                               DEFAULT_VAL_ATTR1 = 0
>                               PT_SPRITE_TEX_ATTR1 = 0
>                               ATTR0_VALID = 0
>                               ATTR1_VALID = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                            ALPHA_TO_MASK_OFFSET0 = 2
>                            ALPHA_TO_MASK_OFFSET1 = 2
>                            ALPHA_TO_MASK_OFFSET2 = 2
>                            ALPHA_TO_MASK_OFFSET3 = 2
>                            OFFSET_ROUND = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>        [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                             COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                             COLOR_DESTBLEND = BLEND_ZERO
>                             ALPHA_SRCBLEND = BLEND_ZERO
>                             ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                             ALPHA_DESTBLEND = BLEND_ZERO
>                             SEPARATE_ALPHA_BLEND = 0
>                             ENABLE = 0
>                             DISABLE_ROP3 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                            DEGAMMA_ENABLE = 0
>                            MODE = CB_NORMAL
>                            ROP3 = X_0XCC
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                PNT_SPRITE_ENA = 1
>                                PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                PNT_SPRITE_TOP_1 = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 8
>                            WIDTH = 8
>        [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 8
>                              MAX_SIZE = 8
>        [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 8
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                             VPORT_SCISSOR_ENABLE = 1
>                             LINE_STIPPLE_ENABLE = 0
>                             SEND_UNLIT_STILES_TO_PKR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                          ROUND_MODE = X_TRUNCATE
>                          QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 0
>                              CULL_BACK = 0
>                              FACE = 0
>                              POLY_MODE = X_DISABLE_POLY_MODE
>                              POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                              POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                              POLY_OFFSET_FRONT_ENABLE = 0
>                              POLY_OFFSET_BACK_ENABLE = 0
>                              POLY_OFFSET_PARA_ENABLE = 0
>                              VTX_WINDOW_OFFSET_ENABLE = 0
>                              PROVOKING_VTX_LAST = 1
>                              PERSP_CORR_DIS = 0
>                              MULTI_PRIM_IB_ENA = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_14[0m <- 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 0
>                            Z_ENABLE = 0
>                            Z_WRITE_ENABLE = 0
>                            DEPTH_BOUNDS_ENABLE = 0
>                            ZFUNC = FRAG_NEVER
>                            BACKFACE_ENABLE = 0
>                            STENCILFUNC = REF_NEVER
>                            STENCILFUNC_BF = REF_NEVER
>                            ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                            DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mDB_STENCIL_CONTROL[0m <- STENCILFAIL = STENCIL_KEEP
>                              STENCILZPASS = STENCIL_KEEP
>                              STENCILZFAIL = STENCIL_KEEP
>                              STENCILFAIL_BF = STENCIL_KEEP
>                              STENCILZPASS_BF = STENCIL_KEEP
>                              STENCILZFAIL_BF = STENCIL_KEEP
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_SHADER_STAGES_EN[0m <- LS_EN = LS_STAGE_OFF
>                                HS_EN = 0
>                                ES_EN = ES_STAGE_OFF
>                                GS_EN = 0
>                                VS_EN = VS_STAGE_REAL
>                                DYNAMIC_HS = 0
>                                DISPATCH_DRAW_EN = 0
>                                DIS_DEALLOC_ACCUM_0 = 0
>                                DIS_DEALLOC_ACCUM_1 = 0
>                                VS_WAVE_ID_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                       RESERVED_0 = 0
>                       CUT_MODE = GS_CUT_1024
>                       RESERVED_1 = 0
>                       GS_C_PACK_EN = 0
>                       RESERVED_2 = 0
>                       ES_PASSTHRU = 0
>                       COMPUTE_MODE = 0
>                       FAST_COMPUTE_MODE = 0
>                       ELEMENT_INFO_EN = 0
>                       PARTIAL_THD_AT_EOI = 0
>                       SUPPRESS_CUTS = 0
>                       ES_WRITE_OPTIMIZE = 0
>                       GS_WRITE_OPTIMIZE = 0
>                       ONCHIP = X_0_OFFCHIP_GS
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                              DISABLE_RESET_ON_EOI = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 2
>                             VS_HALF_PACK = 0
>                             VS_EXPORTS_FOG = 0
>                             VS_OUT_FOG_VEC_ADDR = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                 POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                 POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x01008ec0
>        [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 4
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = 192 (0xc0)
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   VGPR_COMP_CNT = 0
>                                   CU_GROUP_ENABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 15 (0xf)
>                                   TRAP_PRESENT = 0
>                                   OC_LDS_EN = 0
>                                   SO_BASE0_EN = 0
>                                   SO_BASE1_EN = 0
>                                   SO_BASE2_EN = 0
>                                   SO_BASE3_EN = 0
>                                   SO_EN = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>                                   DISPATCH_DRAW_EN = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                          VPORT_X_OFFSET_ENA = 1
>                          VPORT_Y_SCALE_ENA = 1
>                          VPORT_Y_OFFSET_ENA = 1
>                          VPORT_Z_SCALE_ENA = 1
>                          VPORT_Z_OFFSET_ENA = 1
>                          VTX_XY_FMT = 0
>                          VTX_Z_FMT = 0
>                          VTX_W0_FMT = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                            PERSP_CENTER_ENA = 1
>                            PERSP_CENTROID_ENA = 0
>                            PERSP_PULL_MODEL_ENA = 0
>                            LINEAR_SAMPLE_ENA = 0
>                            LINEAR_CENTER_ENA = 0
>                            LINEAR_CENTROID_ENA = 0
>                            LINE_STIPPLE_TEX_ENA = 0
>                            POS_X_FLOAT_ENA = 0
>                            POS_Y_FLOAT_ENA = 0
>                            POS_Z_FLOAT_ENA = 0
>                            POS_W_FLOAT_ENA = 0
>                            FRONT_FACE_ENA = 0
>                            ANCILLARY_ENA = 0
>                            SAMPLE_COVERAGE_ENA = 0
>                            POS_FIXED_PT_ENA = 0
>        [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 1
>                             PERSP_CENTER_ENA = 1
>                             PERSP_CENTROID_ENA = 1
>                             PERSP_PULL_MODEL_ENA = 0
>                             LINEAR_SAMPLE_ENA = 1
>                             LINEAR_CENTER_ENA = 1
>                             LINEAR_CENTROID_ENA = 1
>                             LINE_STIPPLE_TEX_ENA = 0
>                             POS_X_FLOAT_ENA = 0
>                             POS_Y_FLOAT_ENA = 0
>                             POS_Z_FLOAT_ENA = 0
>                             POS_W_FLOAT_ENA = 0
>                             FRONT_FACE_ENA = 1
>                             ANCILLARY_ENA = 0
>                             SAMPLE_COVERAGE_ENA = 1
>                             POS_FIXED_PT_ENA = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                          PERSP_CENTROID_CNTL = 0
>                          LINEAR_CENTER_CNTL = 0
>                          LINEAR_CENTROID_CNTL = 0
>                          POS_FLOAT_LOCATION = 2
>                          POS_FLOAT_ULC = 0
>                          FRONT_FACE_ALL_BITS = 1
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 3
>                             PARAM_GEN = 0
>                             FOG_ADDR = 0
>                             BC_OPTIMIZE_DISABLE = 0
>                             PASS_FOG_THROUGH_PS = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>        [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                 COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                 COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15 (0xf)
>                          OUTPUT1_ENABLE = 0
>                          OUTPUT2_ENABLE = 0
>                          OUTPUT3_ENABLE = 0
>                          OUTPUT4_ENABLE = 0
>                          OUTPUT5_ENABLE = 0
>                          OUTPUT6_ENABLE = 0
>                          OUTPUT7_ENABLE = 0
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x01008ed0
>        [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>        [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 8
>                                   SGPRS = 9
>                                   PRIORITY = 0
>                                   FLOAT_MODE = FP_64_DENORMS
>                                   PRIV = 0
>                                   DX10_CLAMP = 1
>                                   DEBUG_MODE = 0
>                                   IEEE_MODE = 0
>                                   CU_GROUP_DISABLE = 0
>                                   CACHE_CTL = 0
>                                   CDBG_USER = 0
>        [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                   USER_SGPR = 11 (0xb)
>                                   TRAP_PRESENT = 0
>                                   WAVE_CNT_EN = 0
>                                   EXTRA_LDS_SIZE = 0
>                                   EXCP_EN = 0
>                                   EXCP_EN_CIK = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mSPI_TMPRING_SIZE[0m <- WAVES = 896 (0x380)
>                            WAVESIZE = 0
>[1;32mDRAW_PREAMBLE[0m:
>        [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_TRISTRIP
>        [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 127 (0x007f)
>                              PARTIAL_VS_WAVE_ON = 0
>                              SWITCH_ON_EOP = 0
>                              PARTIAL_ES_WAVE_ON = 1
>                              SWITCH_ON_EOI = 1
>                              WD_SWITCH_ON_EOP = 0
>                              MAX_PRIMGRP_IN_WAVE = 2
>        [1;33mVGT_LS_HS_CONFIG[0m <- NUM_PATCHES = 0
>                            HS_NUM_INPUT_CP = 0
>                            HS_NUM_OUTPUT_CP = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_GS_OUT_PRIM_TYPE[0m <- OUTPRIM_TYPE = OUTPRIM_TYPE_TRISTRIP
>                                OUTPRIM_TYPE_1 = 0
>                                OUTPRIM_TYPE_2 = 0
>                                OUTPRIM_TYPE_3 = 0
>                                UNIQUE_TYPE_PER_STREAM = 0
>[1;36mSET_CONTEXT_REG[1;36m:
>        [1;33mVGT_MULTI_PRIM_IB_RESET_EN[0m <- RESET_EN = 0
>[1;32mWAIT_ON_CE_COUNTER[0m:
>        0x00000001
>[1;32mNUM_INSTANCES[0m:
>        [1;33mVGT_NUM_INSTANCES[0m <- 1
>[1;36mSET_SH_REG[1;36m:
>        [1;33mSPI_SHADER_USER_DATA_VS_12[0m <- 0
>        [1;33mSPI_SHADER_USER_DATA_VS_13[0m <- 0
>[1;32mDRAW_INDEX_AUTO[0m:
>        [1;33mVGT_NUM_INDICES[0m <- 4
>        [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX
>                              MAJOR_MODE = DI_MAJOR_MODE_0
>                              NOT_EOP = 0
>                              USE_OPAQUE = 0
>[1;32mINCREMENT_DE_COUNTER[0m:
>        0x00000000
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0.0f (0x0062d000)
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000002
>[1;32mNOP[0m:
>        [31mTrace point ID: 2
>        [31mThis trace point was reached by the CP.[0m
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = PS_PARTIAL_FLUSH
>        [1;33mEVENT_INDEX[0m <- 4
>        [1;33mINV_L2[0m <- 0
>[1;32mEVENT_WRITE[0m:
>        [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = CS_PARTIAL_FLUSH
>        [1;33mEVENT_INDEX[0m <- 4
>        [1;33mINV_L2[0m <- 0
>[1;32mPFP_SYNC_ME[0m:
>        0x00000000
>[1;32mSURFACE_SYNC[0m:
>        [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                         DEST_BASE_1_ENA = 0
>                         CB0_DEST_BASE_ENA = 0
>                         CB1_DEST_BASE_ENA = 0
>                         CB2_DEST_BASE_ENA = 0
>                         CB3_DEST_BASE_ENA = 0
>                         CB4_DEST_BASE_ENA = 0
>                         CB5_DEST_BASE_ENA = 0
>                         CB6_DEST_BASE_ENA = 0
>                         CB7_DEST_BASE_ENA = 0
>                         DB_DEST_BASE_ENA = 0
>                         DEST_BASE_2_ENA = 0
>                         DEST_BASE_3_ENA = 0
>                         TCL1_ACTION_ENA = 1
>                         TC_ACTION_ENA = 1
>                         CB_ACTION_ENA = 0
>                         DB_ACTION_ENA = 0
>                         SH_KCACHE_ACTION_ENA = 0
>                         SH_ICACHE_ACTION_ENA = 0
>        [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>        [1;33mCP_COHER_BASE[0m <- 0
>        [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>[1;32mWRITE_DATA[0m:
>        [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                   WR_CONFIRM = 1
>                   WR_ONE_ADDR = 0
>                   DST_SEL = MEMORY_SYNC
>        [1;33mDST_ADDR_LO[0m <- 0.0f (0x0062d000)
>        [1;33mDST_ADDR_HI[0m <- 1
>        0x00000003
>[1;32mNOP[0m:
>        [31mTrace point ID: 3
>        [31m!!!!! This is the last trace point that was reached by the CP !!!!![0m
>------------------- IB end -------------------
>
>Done.

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Attachments on bug 95545: 123994 | 123995 | 123996 | 123997

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