Attachment 123996 Details for Bug 95545 – stderr

stderr

stderr.txt (text/plain), 118.32 KB, created by csaba.halasz on 2016-05-23 15:39:05 UTC

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Creator: csaba.halasz

Created: 2016-05-23 15:39:05 UTC

Size: 118.32 KB

patch

obsolete

>apitrace: loaded into /usr/local/bin/mplayer
>apitrace: tracing to mplayer.trace
>apitrace: redirecting dlopen("libGL.so.1", 0x102)
>apitrace: loaded into /bin/dash
>apitrace: loaded into /home/user/bin/dmesg
>apitrace: unloaded from /home/user/bin/dmesg
>VM start=0x100304000  end=0x100314000 | Buffer 65536 bytes
>VM start=0x100314000  end=0x100315000 | Buffer 4096 bytes
>VM start=0x100315000  end=0x100316000 | Buffer 4096 bytes
>VM start=0x100316000  end=0x100317000 | Buffer 4096 bytes
>apitrace: loaded into /bin/dash
>apitrace: loaded into /home/user/bin/dmesg
>apitrace: unloaded from /home/user/bin/dmesg
>VM start=0x100317000  end=0x100318000 | Buffer 4096 bytes
>Gallium debugger active. Logging all calls.
>apitrace: loaded into /bin/dash
>apitrace: loaded into /home/user/bin/dmesg
>apitrace: unloaded from /home/user/bin/dmesg
>VM start=0x10061C000  end=0x10062C000 | Buffer 65536 bytes
>VM start=0x10062C000  end=0x10062D000 | Buffer 4096 bytes
>VM start=0x10062D000  end=0x10062E000 | Buffer 4096 bytes
>VM start=0x10062E000  end=0x10062F000 | Buffer 4096 bytes
>apitrace: loaded into /bin/dash
>apitrace: loaded into /home/user/bin/dmesg
>apitrace: unloaded from /home/user/bin/dmesg
>VM start=0x10062F000  end=0x100630000 | Buffer 4096 bytes
>VM start=0x100630000  end=0x100640000 | Buffer 65536 bytes
>VM start=0x100700000  end=0x100820000 | Texture 640x341x1, 1 levels, 1 samples, b8g8r8x8_unorm
>apitrace: attempting to read configuration file: /home/user/.config/apitrace/gltrace.conf
>SHADER KEY
>  prolog.color_two_side = 0
>  prolog.poly_stipple = 0
>  prolog.force_persample_interp = 0
>  epilog.spi_shader_col_format = 0x0
>  epilog.color_is_int8 = 0x0
>  epilog.last_cbuf = 0
>  epilog.alpha_func = 0
>  epilog.alpha_to_one = 0
>  epilog.poly_line_smoothing = 0
>  epilog.clamp_color = 0
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>radeonsi: Compiling shader 1
>TGSI shader LLVM IR:
>
>; ModuleID = 'tgsi'
>source_filename = "tgsi"
>target triple = "amdgcn--"
>
>define amdgpu_ps <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> @main([16 x <16 x i8>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [16 x <8 x i32>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, i32, i32, float, i32, float, float, float, float) #0 {
>main_body:
>  %27 = bitcast float %5 to i32
>  %28 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> undef, i32 %27, 10
>  %29 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %28, float %23, 11
>  %30 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %29, float %24, 12
>  %31 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %30, float %25, 13
>  %32 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %31, float %26, 14
>  %33 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %32, float %21, 24
>  ret <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %33
>}
>
>attributes #0 = { "InitialPSInputAddr"="36983" }
>
>SHADER KEY
>  instance_divisors = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
>  as_es = 0
>  as_ls = 0
>  export_prim_id = 0
>VERT
>PROPERTY NEXT_SHADER 1
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL CONST[0..3]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV OUT[1], IN[1]
>  5: END
>radeonsi: Compiling shader 2
>TGSI shader LLVM IR:
>
>; ModuleID = 'tgsi'
>source_filename = "tgsi"
>target triple = "amdgcn--"
>
>define amdgpu_vs <{ float, float, float }> @main([16 x <16 x i8>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [16 x <8 x i32>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32, i32, i32) {
>main_body:
>  %15 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0, !amdgpu.uniform !0
>  %16 = load <16 x i8>, <16 x i8> addrspace(2)* %15, align 16, !tbaa !1
>  %17 = call float @llvm.SI.load.const(<16 x i8> %16, i32 0)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %16, i32 4)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %16, i32 8)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %16, i32 12)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %16, i32 16)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %16, i32 20)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %16, i32 24)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %16, i32 28)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %16, i32 32)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %16, i32 36)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %16, i32 40)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %16, i32 44)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %16, i32 48)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %16, i32 52)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %16, i32 56)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %16, i32 60)
>  %33 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %5, i64 0, i64 0, !amdgpu.uniform !0
>  %34 = load <16 x i8>, <16 x i8> addrspace(2)* %33, align 16, !tbaa !1
>  %35 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %34, i32 0, i32 %13)
>  %36 = extractelement <4 x float> %35, i32 0
>  %37 = extractelement <4 x float> %35, i32 1
>  %38 = extractelement <4 x float> %35, i32 2
>  %39 = extractelement <4 x float> %35, i32 3
>  %40 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %5, i64 0, i64 1, !amdgpu.uniform !0
>  %41 = load <16 x i8>, <16 x i8> addrspace(2)* %40, align 16, !tbaa !1
>  %42 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %41, i32 0, i32 %14)
>  %43 = extractelement <4 x float> %42, i32 0
>  %44 = extractelement <4 x float> %42, i32 1
>  %45 = extractelement <4 x float> %42, i32 2
>  %46 = extractelement <4 x float> %42, i32 3
>  %47 = fmul float %36, %17
>  %48 = fmul float %36, %18
>  %49 = fmul float %36, %19
>  %50 = fmul float %36, %20
>  %51 = fmul float %37, %21
>  %52 = fadd float %51, %47
>  %53 = fmul float %37, %22
>  %54 = fadd float %53, %48
>  %55 = fmul float %37, %23
>  %56 = fadd float %55, %49
>  %57 = fmul float %37, %24
>  %58 = fadd float %57, %50
>  %59 = fmul float %38, %25
>  %60 = fadd float %59, %52
>  %61 = fmul float %38, %26
>  %62 = fadd float %61, %54
>  %63 = fmul float %38, %27
>  %64 = fadd float %63, %56
>  %65 = fmul float %38, %28
>  %66 = fadd float %65, %58
>  %67 = fmul float %39, %29
>  %68 = fadd float %67, %60
>  %69 = fmul float %39, %30
>  %70 = fadd float %69, %62
>  %71 = fmul float %39, %31
>  %72 = fadd float %71, %64
>  %73 = fmul float %39, %32
>  %74 = fadd float %73, %66
>  %75 = and i32 %8, 1
>  %76 = icmp eq i32 %75, 0
>  br i1 %76, label %endif-block, label %if-true-block
>
>if-true-block:                                    ; preds = %main_body
>  %77 = call float @llvm.AMDGPU.clamp.(float %43, float 0.000000e+00, float 1.000000e+00)
>  %78 = call float @llvm.AMDGPU.clamp.(float %44, float 0.000000e+00, float 1.000000e+00)
>  %79 = call float @llvm.AMDGPU.clamp.(float %45, float 0.000000e+00, float 1.000000e+00)
>  %80 = call float @llvm.AMDGPU.clamp.(float %46, float 0.000000e+00, float 1.000000e+00)
>  br label %endif-block
>
>endif-block:                                      ; preds = %main_body, %if-true-block
>  %.06 = phi float [ %77, %if-true-block ], [ %43, %main_body ]
>  %.05 = phi float [ %78, %if-true-block ], [ %44, %main_body ]
>  %.04 = phi float [ %79, %if-true-block ], [ %45, %main_body ]
>  %.0 = phi float [ %80, %if-true-block ], [ %46, %main_body ]
>  %81 = bitcast i32 %11 to float
>  %82 = insertvalue <{ float, float, float }> undef, float %81, 2
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %.06, float %.05, float %.04, float %.0)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %68, float %70, float %72, float %74)
>  ret <{ float, float, float }> %82
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #0
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #0
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.clamp.(float, float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { nounwind readnone }
>attributes #1 = { readnone }
>
>!0 = !{}
>!1 = !{!"const", null, i32 1}
>
>VM start=0x100640000  end=0x1006EB000 | Texture 1024x512x1, 11 levels, 1 samples, l8_unorm
>VM start=0x100820000  end=0x1008A0000 | Texture 1024x512x1, 1 levels, 1 samples, l8_unorm
>VM start=0x1008A0000  end=0x1008CB000 | Texture 512x256x1, 10 levels, 1 samples, l8_unorm
>VM start=0x1008CB000  end=0x1008EB000 | Texture 512x256x1, 1 levels, 1 samples, l8_unorm
>VM start=0x1008F0000  end=0x10091B000 | Texture 512x256x1, 10 levels, 1 samples, l8_unorm
>VM start=0x10091B000  end=0x10093B000 | Texture 512x256x1, 1 levels, 1 samples, l8_unorm
>SHADER KEY
>  prolog.color_two_side = 0
>  prolog.poly_stipple = 0
>  prolog.force_persample_interp = 0
>  epilog.spi_shader_col_format = 0x0
>  epilog.color_is_int8 = 0x0
>  epilog.last_cbuf = 0
>  epilog.alpha_func = 0
>  epilog.alpha_to_one = 0
>  epilog.poly_line_smoothing = 0
>  epilog.clamp_color = 0
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], TEXCOORD[0], PERSPECTIVE
>DCL IN[1], TEXCOORD[1], PERSPECTIVE
>DCL IN[2], TEXCOORD[2], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SAMP[1]
>DCL SAMP[2]
>DCL SVIEW[0], 2D, FLOAT
>DCL SVIEW[1], 2D, FLOAT
>DCL SVIEW[2], 2D, FLOAT
>DCL TEMP[0..8]
>IMM[0] FLT32 { 1024.0000,   512.0000,     0.0000,     1.0000}
>IMM[1] FLT32 {    0.5000,     0.0000,     1.0000,    -0.5000}
>IMM[2] FLT32 {   -0.5000,     0.1666,     0.3333,    -0.3333}
>IMM[3] FLT32 {   -0.6666,     0.0000,     0.8333,     0.1666}
>IMM[4] FLT32 {   -0.0010,     0.0000,     0.0010,     1.5960}
>IMM[5] FLT32 {    0.0000,    -0.0020,     0.0020,     1.5960}
>IMM[6] FLT32 {  512.0000,   256.0000,     0.0000,     1.0000}
>IMM[7] FLT32 {    0.0000,    -0.0039,     0.0039,     1.5960}
>IMM[8] FLT32 {    1.1640,     1.0000,     1.5960,    -0.8130}
>IMM[9] FLT32 {   -0.8742,     0.5313,    -1.0860,     1.0000}
>IMM[10] FLT32 {    0.0000,    -0.3910,     2.0180,     1.0000}
>IMM[11] FLT32 {    1.5960,    -0.8130,     0.0000,     1.0000}
>  0: MAD TEMP[0].xy, IN[0], IMM[0], IMM[1].xxyz
>  1: FRC TEMP[0].xy, TEMP[0].xyxy
>  2: MAD TEMP[1], IMM[2], TEMP[0].xxxx, IMM[1].zywx
>  3: MAD TEMP[1], TEMP[1], TEMP[0].xxxx, IMM[1].yywx
>  4: MAD TEMP[1], TEMP[1], TEMP[0].xxxx, IMM[3]
>  5: RCP TEMP[2].x, TEMP[1].zzzz
>  6: RCP TEMP[2].y, TEMP[1].wwww
>  7: MAD TEMP[1].xy, TEMP[1].xyxy, TEMP[2].xyxy, IMM[0].wwzz
>  8: ADD TEMP[1].x, TEMP[1].xxxx, TEMP[0].xxxx
>  9: SUB TEMP[1].y, TEMP[1].yyyy, TEMP[0].xxxx
> 10: MUL TEMP[3].xz, TEMP[1].xxyy, IMM[4].xyzy
> 11: MAD TEMP[4], IMM[2], TEMP[0].yyyy, IMM[1].zywx
> 12: MAD TEMP[4], TEMP[4], TEMP[0].yyyy, IMM[1].yywx
> 13: MAD TEMP[4], TEMP[4], TEMP[0].yyyy, IMM[3]
> 14: RCP TEMP[2].x, TEMP[4].zzzz
> 15: RCP TEMP[2].y, TEMP[4].wwww
> 16: MAD TEMP[4].xy, TEMP[4].xyxy, TEMP[2].xyxy, IMM[0].wwzz
> 17: ADD TEMP[4].x, TEMP[4].xxxx, TEMP[0].yyyy
> 18: SUB TEMP[4].y, TEMP[4].yyyy, TEMP[0].yyyy
> 19: MUL TEMP[3].yw, TEMP[4].xxyy, IMM[5].xyxz
> 20: ADD TEMP[0], IN[0].xyxy, TEMP[3].xyxw
> 21: ADD TEMP[5], IN[0].xyxy, TEMP[3].zyzw
> 22: TEX TEMP[2].x, TEMP[0].xyxy, SAMP[0], 2D
> 23: TEX TEMP[2].y, TEMP[0].zwzw, SAMP[0], 2D
> 24: TEX TEMP[6].x, TEMP[5].xyxy, SAMP[0], 2D
> 25: TEX TEMP[6].y, TEMP[5].zwzw, SAMP[0], 2D
> 26: LRP TEMP[2].z, TEMP[4].zzzz, TEMP[2].xxxx, TEMP[2].yyyy
> 27: LRP TEMP[2].w, TEMP[4].zzzz, TEMP[6].xxxx, TEMP[6].yyyy
> 28: LRP TEMP[7].x, TEMP[1].zzzz, TEMP[2].zzzz, TEMP[2].wwww
> 29: MAD TEMP[0].xy, IN[1], IMM[6], IMM[1].xxyz
> 30: FRC TEMP[0].xy, TEMP[0].xyxy
> 31: MAD TEMP[1], IMM[2], TEMP[0].xxxx, IMM[1].zywx
> 32: MAD TEMP[1], TEMP[1], TEMP[0].xxxx, IMM[1].yywx
> 33: MAD TEMP[1], TEMP[1], TEMP[0].xxxx, IMM[3]
> 34: RCP TEMP[2].x, TEMP[1].zzzz
> 35: RCP TEMP[2].y, TEMP[1].wwww
> 36: MAD TEMP[1].xy, TEMP[1].xyxy, TEMP[2].xyxy, IMM[0].wwzz
> 37: ADD TEMP[1].x, TEMP[1].xxxx, TEMP[0].xxxx
> 38: SUB TEMP[1].y, TEMP[1].yyyy, TEMP[0].xxxx
> 39: MUL TEMP[3].xz, TEMP[1].xxyy, IMM[5].yxzx
> 40: MAD TEMP[4], IMM[2], TEMP[0].yyyy, IMM[1].zywx
> 41: MAD TEMP[4], TEMP[4], TEMP[0].yyyy, IMM[1].yywx
> 42: MAD TEMP[4], TEMP[4], TEMP[0].yyyy, IMM[3]
> 43: RCP TEMP[2].x, TEMP[4].zzzz
> 44: RCP TEMP[2].y, TEMP[4].wwww
> 45: MAD TEMP[4].xy, TEMP[4].xyxy, TEMP[2].xyxy, IMM[0].wwzz
> 46: ADD TEMP[4].x, TEMP[4].xxxx, TEMP[0].yyyy
> 47: SUB TEMP[4].y, TEMP[4].yyyy, TEMP[0].yyyy
> 48: MUL TEMP[3].yw, TEMP[4].xxyy, IMM[7].xyxz
> 49: ADD TEMP[0], IN[1].xyxy, TEMP[3].xyxw
> 50: ADD TEMP[5], IN[1].xyxy, TEMP[3].zyzw
> 51: TEX TEMP[2].x, TEMP[0].xyxy, SAMP[1], 2D
> 52: TEX TEMP[2].y, TEMP[0].zwzw, SAMP[1], 2D
> 53: TEX TEMP[6].x, TEMP[5].xyxy, SAMP[1], 2D
> 54: TEX TEMP[6].y, TEMP[5].zwzw, SAMP[1], 2D
> 55: LRP TEMP[2].z, TEMP[4].zzzz, TEMP[2].xxxx, TEMP[2].yyyy
> 56: LRP TEMP[2].w, TEMP[4].zzzz, TEMP[6].xxxx, TEMP[6].yyyy
> 57: LRP TEMP[7].y, TEMP[1].zzzz, TEMP[2].zzzz, TEMP[2].wwww
> 58: MAD TEMP[0].xy, IN[2], IMM[6], IMM[1].xxyz
> 59: FRC TEMP[0].xy, TEMP[0].xyxy
> 60: MAD TEMP[1], IMM[2], TEMP[0].xxxx, IMM[1].zywx
> 61: MAD TEMP[1], TEMP[1], TEMP[0].xxxx, IMM[1].yywx
> 62: MAD TEMP[1], TEMP[1], TEMP[0].xxxx, IMM[3]
> 63: RCP TEMP[2].x, TEMP[1].zzzz
> 64: RCP TEMP[2].y, TEMP[1].wwww
> 65: MAD TEMP[1].xy, TEMP[1].xyxy, TEMP[2].xyxy, IMM[0].wwzz
> 66: ADD TEMP[1].x, TEMP[1].xxxx, TEMP[0].xxxx
> 67: SUB TEMP[1].y, TEMP[1].yyyy, TEMP[0].xxxx
> 68: MUL TEMP[3].xz, TEMP[1].xxyy, IMM[5].yxzx
> 69: MAD TEMP[4], IMM[2], TEMP[0].yyyy, IMM[1].zywx
> 70: MAD TEMP[4], TEMP[4], TEMP[0].yyyy, IMM[1].yywx
> 71: MAD TEMP[4], TEMP[4], TEMP[0].yyyy, IMM[3]
> 72: RCP TEMP[2].x, TEMP[4].zzzz
> 73: RCP TEMP[2].y, TEMP[4].wwww
> 74: MAD TEMP[4].xy, TEMP[4].xyxy, TEMP[2].xyxy, IMM[0].wwzz
> 75: ADD TEMP[4].x, TEMP[4].xxxx, TEMP[0].yyyy
> 76: SUB TEMP[4].y, TEMP[4].yyyy, TEMP[0].yyyy
> 77: MUL TEMP[3].yw, TEMP[4].xxyy, IMM[7].xyxz
> 78: ADD TEMP[0], IN[2].xyxy, TEMP[3].xyxw
> 79: ADD TEMP[5], IN[2].xyxy, TEMP[3].zyzw
> 80: TEX TEMP[2].x, TEMP[0].xyxy, SAMP[2], 2D
> 81: TEX TEMP[2].y, TEMP[0].zwzw, SAMP[2], 2D
> 82: TEX TEMP[6].x, TEMP[5].xyxy, SAMP[2], 2D
> 83: TEX TEMP[6].y, TEMP[5].zwzw, SAMP[2], 2D
> 84: LRP TEMP[2].z, TEMP[4].zzzz, TEMP[2].xxxx, TEMP[2].yyyy
> 85: LRP TEMP[2].w, TEMP[4].zzzz, TEMP[6].xxxx, TEMP[6].yyyy
> 86: LRP TEMP[7].z, TEMP[1].zzzz, TEMP[2].zzzz, TEMP[2].wwww
> 87: MAD TEMP[8].xyz, TEMP[7].xxxx, IMM[8].xxxy, IMM[9]
> 88: MAD TEMP[8].xyz, TEMP[7].yyyy, IMM[10], TEMP[8]
> 89: MAD TEMP[8].xyz, TEMP[7].zzzz, IMM[11], TEMP[8]
> 90: MOV OUT[0].xyz, TEMP[8]
> 91: END
>radeonsi: Compiling shader 3
>TGSI shader LLVM IR:
>
>; ModuleID = 'tgsi'
>source_filename = "tgsi"
>target triple = "amdgcn--"
>
>define amdgpu_ps <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> @main([16 x <16 x i8>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [16 x <8 x i32>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, i32, i32, float, i32) #0 {
>main_body:
>  %23 = getelementptr [32 x <8 x i32>], [32 x <8 x i32>] addrspace(2)* %2, i64 0, i64 0, !amdgpu.uniform !0
>  %24 = load <8 x i32>, <8 x i32> addrspace(2)* %23, align 32, !tbaa !1
>  %25 = bitcast [32 x <8 x i32>] addrspace(2)* %2 to [0 x <4 x i32>] addrspace(2)*
>  %26 = getelementptr [0 x <4 x i32>], [0 x <4 x i32>] addrspace(2)* %25, i64 0, i64 3, !amdgpu.uniform !0
>  %27 = load <4 x i32>, <4 x i32> addrspace(2)* %26, align 16, !tbaa !1
>  %28 = getelementptr [32 x <8 x i32>], [32 x <8 x i32>] addrspace(2)* %2, i64 0, i64 2, !amdgpu.uniform !0
>  %29 = load <8 x i32>, <8 x i32> addrspace(2)* %28, align 32, !tbaa !1
>  %30 = bitcast [32 x <8 x i32>] addrspace(2)* %2 to [0 x <4 x i32>] addrspace(2)*
>  %31 = getelementptr [0 x <4 x i32>], [0 x <4 x i32>] addrspace(2)* %30, i64 0, i64 7, !amdgpu.uniform !0
>  %32 = load <4 x i32>, <4 x i32> addrspace(2)* %31, align 16, !tbaa !1
>  %33 = getelementptr [32 x <8 x i32>], [32 x <8 x i32>] addrspace(2)* %2, i64 0, i64 4, !amdgpu.uniform !0
>  %34 = load <8 x i32>, <8 x i32> addrspace(2)* %33, align 32, !tbaa !1
>  %35 = bitcast [32 x <8 x i32>] addrspace(2)* %2 to [0 x <4 x i32>] addrspace(2)*
>  %36 = getelementptr [0 x <4 x i32>], [0 x <4 x i32>] addrspace(2)* %35, i64 0, i64 11, !amdgpu.uniform !0
>  %37 = load <4 x i32>, <4 x i32> addrspace(2)* %36, align 16, !tbaa !1
>  %38 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %6, <2 x i32> %8)
>  %39 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %6, <2 x i32> %8)
>  %40 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %6, <2 x i32> %8)
>  %41 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %6, <2 x i32> %8)
>  %42 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %6, <2 x i32> %8)
>  %43 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %6, <2 x i32> %8)
>  %44 = fmul float %38, 1.024000e+03
>  %45 = fadd float %44, 5.000000e-01
>  %46 = fmul float %39, 5.120000e+02
>  %47 = fadd float %46, 5.000000e-01
>  %48 = call float @llvm.floor.f32(float %45)
>  %49 = fsub float %45, %48
>  %50 = call float @llvm.floor.f32(float %47)
>  %51 = fsub float %47, %50
>  %52 = fmul float %49, -5.000000e-01
>  %53 = fadd float %52, 1.000000e+00
>  %54 = fmul float %49, 0x3FC5532620000000
>  %55 = fadd float %54, 0.000000e+00
>  %56 = fmul float %49, 0x3FD554C980000000
>  %57 = fadd float %56, -5.000000e-01
>  %58 = fmul float %49, 0xBFD554C980000000
>  %59 = fadd float %58, 5.000000e-01
>  %60 = fmul float %53, %49
>  %61 = fadd float %60, 0.000000e+00
>  %62 = fmul float %55, %49
>  %63 = fadd float %62, 0.000000e+00
>  %64 = fmul float %57, %49
>  %65 = fadd float %64, -5.000000e-01
>  %66 = fmul float %59, %49
>  %67 = fadd float %66, 5.000000e-01
>  %68 = fmul float %61, %49
>  %69 = fadd float %68, 0xBFE554C980000000
>  %70 = fmul float %63, %49
>  %71 = fadd float %70, 0.000000e+00
>  %72 = fmul float %65, %49
>  %73 = fadd float %72, 0x3FEAAA64C0000000
>  %74 = fmul float %67, %49
>  %75 = fadd float %74, 0x3FC5532620000000
>  %76 = fdiv float 1.000000e+00, %73
>  %77 = fdiv float 1.000000e+00, %75
>  %78 = fmul float %69, %76
>  %79 = fadd float %78, 1.000000e+00
>  %80 = fmul float %71, %77
>  %81 = fadd float %80, 1.000000e+00
>  %82 = fadd float %79, %49
>  %83 = fsub float %81, %49
>  %84 = fmul float %82, -9.765625e-04
>  %85 = fmul float %83, 9.765625e-04
>  %86 = fmul float %51, -5.000000e-01
>  %87 = fadd float %86, 1.000000e+00
>  %88 = fmul float %51, 0x3FC5532620000000
>  %89 = fadd float %88, 0.000000e+00
>  %90 = fmul float %51, 0x3FD554C980000000
>  %91 = fadd float %90, -5.000000e-01
>  %92 = fmul float %51, 0xBFD554C980000000
>  %93 = fadd float %92, 5.000000e-01
>  %94 = fmul float %87, %51
>  %95 = fadd float %94, 0.000000e+00
>  %96 = fmul float %89, %51
>  %97 = fadd float %96, 0.000000e+00
>  %98 = fmul float %91, %51
>  %99 = fadd float %98, -5.000000e-01
>  %100 = fmul float %93, %51
>  %101 = fadd float %100, 5.000000e-01
>  %102 = fmul float %95, %51
>  %103 = fadd float %102, 0xBFE554C980000000
>  %104 = fmul float %97, %51
>  %105 = fadd float %104, 0.000000e+00
>  %106 = fmul float %99, %51
>  %107 = fadd float %106, 0x3FEAAA64C0000000
>  %108 = fmul float %101, %51
>  %109 = fadd float %108, 0x3FC5532620000000
>  %110 = fdiv float 1.000000e+00, %107
>  %111 = fdiv float 1.000000e+00, %109
>  %112 = fmul float %103, %110
>  %113 = fadd float %112, 1.000000e+00
>  %114 = fmul float %105, %111
>  %115 = fadd float %114, 1.000000e+00
>  %116 = fadd float %113, %51
>  %117 = fsub float %115, %51
>  %118 = fmul float %116, -1.953125e-03
>  %119 = fmul float %117, 1.953125e-03
>  %120 = fadd float %38, %84
>  %121 = fadd float %39, %118
>  %122 = fadd float %38, %84
>  %123 = fadd float %39, %119
>  %124 = fadd float %38, %85
>  %125 = fadd float %39, %118
>  %126 = fadd float %38, %85
>  %127 = fadd float %39, %119
>  %128 = bitcast float %120 to i32
>  %129 = bitcast float %121 to i32
>  %130 = insertelement <2 x i32> undef, i32 %128, i32 0
>  %131 = insertelement <2 x i32> %130, i32 %129, i32 1
>  %132 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %131, <8 x i32> %24, <4 x i32> %27, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>  %133 = extractelement <4 x float> %132, i32 0
>  %134 = bitcast float %122 to i32
>  %135 = bitcast float %123 to i32
>  %136 = insertelement <2 x i32> undef, i32 %134, i32 0
>  %137 = insertelement <2 x i32> %136, i32 %135, i32 1
>  %138 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %137, <8 x i32> %24, <4 x i32> %27, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>  %139 = extractelement <4 x float> %138, i32 1
>  %140 = bitcast float %124 to i32
>  %141 = bitcast float %125 to i32
>  %142 = insertelement <2 x i32> undef, i32 %140, i32 0
>  %143 = insertelement <2 x i32> %142, i32 %141, i32 1
>  %144 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %143, <8 x i32> %24, <4 x i32> %27, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>  %145 = extractelement <4 x float> %144, i32 0
>  %146 = bitcast float %126 to i32
>  %147 = bitcast float %127 to i32
>  %148 = insertelement <2 x i32> undef, i32 %146, i32 0
>  %149 = insertelement <2 x i32> %148, i32 %147, i32 1
>  %150 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %149, <8 x i32> %24, <4 x i32> %27, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>  %151 = extractelement <4 x float> %150, i32 1
>  %152 = fsub float 1.000000e+00, %107
>  %153 = fmul float %133, %107
>  %154 = fmul float %139, %152
>  %155 = fadd float %153, %154
>  %156 = fsub float 1.000000e+00, %107
>  %157 = fmul float %145, %107
>  %158 = fmul float %151, %156
>  %159 = fadd float %157, %158
>  %160 = fsub float 1.000000e+00, %73
>  %161 = fmul float %155, %73
>  %162 = fmul float %159, %160
>  %163 = fadd float %161, %162
>  %164 = fmul float %40, 5.120000e+02
>  %165 = fadd float %164, 5.000000e-01
>  %166 = fmul float %41, 2.560000e+02
>  %167 = fadd float %166, 5.000000e-01
>  %168 = call float @llvm.floor.f32(float %165)
>  %169 = fsub float %165, %168
>  %170 = call float @llvm.floor.f32(float %167)
>  %171 = fsub float %167, %170
>  %172 = fmul float %169, -5.000000e-01
>  %173 = fadd float %172, 1.000000e+00
>  %174 = fmul float %169, 0x3FC5532620000000
>  %175 = fadd float %174, 0.000000e+00
>  %176 = fmul float %169, 0x3FD554C980000000
>  %177 = fadd float %176, -5.000000e-01
>  %178 = fmul float %169, 0xBFD554C980000000
>  %179 = fadd float %178, 5.000000e-01
>  %180 = fmul float %173, %169
>  %181 = fadd float %180, 0.000000e+00
>  %182 = fmul float %175, %169
>  %183 = fadd float %182, 0.000000e+00
>  %184 = fmul float %177, %169
>  %185 = fadd float %184, -5.000000e-01
>  %186 = fmul float %179, %169
>  %187 = fadd float %186, 5.000000e-01
>  %188 = fmul float %181, %169
>  %189 = fadd float %188, 0xBFE554C980000000
>  %190 = fmul float %183, %169
>  %191 = fadd float %190, 0.000000e+00
>  %192 = fmul float %185, %169
>  %193 = fadd float %192, 0x3FEAAA64C0000000
>  %194 = fmul float %187, %169
>  %195 = fadd float %194, 0x3FC5532620000000
>  %196 = fdiv float 1.000000e+00, %193
>  %197 = fdiv float 1.000000e+00, %195
>  %198 = fmul float %189, %196
>  %199 = fadd float %198, 1.000000e+00
>  %200 = fmul float %191, %197
>  %201 = fadd float %200, 1.000000e+00
>  %202 = fadd float %199, %169
>  %203 = fsub float %201, %169
>  %204 = fmul float %202, -1.953125e-03
>  %205 = fmul float %203, 1.953125e-03
>  %206 = fmul float %171, -5.000000e-01
>  %207 = fadd float %206, 1.000000e+00
>  %208 = fmul float %171, 0x3FC5532620000000
>  %209 = fadd float %208, 0.000000e+00
>  %210 = fmul float %171, 0x3FD554C980000000
>  %211 = fadd float %210, -5.000000e-01
>  %212 = fmul float %171, 0xBFD554C980000000
>  %213 = fadd float %212, 5.000000e-01
>  %214 = fmul float %207, %171
>  %215 = fadd float %214, 0.000000e+00
>  %216 = fmul float %209, %171
>  %217 = fadd float %216, 0.000000e+00
>  %218 = fmul float %211, %171
>  %219 = fadd float %218, -5.000000e-01
>  %220 = fmul float %213, %171
>  %221 = fadd float %220, 5.000000e-01
>  %222 = fmul float %215, %171
>  %223 = fadd float %222, 0xBFE554C980000000
>  %224 = fmul float %217, %171
>  %225 = fadd float %224, 0.000000e+00
>  %226 = fmul float %219, %171
>  %227 = fadd float %226, 0x3FEAAA64C0000000
>  %228 = fmul float %221, %171
>  %229 = fadd float %228, 0x3FC5532620000000
>  %230 = fdiv float 1.000000e+00, %227
>  %231 = fdiv float 1.000000e+00, %229
>  %232 = fmul float %223, %230
>  %233 = fadd float %232, 1.000000e+00
>  %234 = fmul float %225, %231
>  %235 = fadd float %234, 1.000000e+00
>  %236 = fadd float %233, %171
>  %237 = fsub float %235, %171
>  %238 = fmul float %236, -3.906250e-03
>  %239 = fmul float %237, 3.906250e-03
>  %240 = fadd float %40, %204
>  %241 = fadd float %41, %238
>  %242 = fadd float %40, %204
>  %243 = fadd float %41, %239
>  %244 = fadd float %40, %205
>  %245 = fadd float %41, %238
>  %246 = fadd float %40, %205
>  %247 = fadd float %41, %239
>  %248 = bitcast float %240 to i32
>  %249 = bitcast float %241 to i32
>  %250 = insertelement <2 x i32> undef, i32 %248, i32 0
>  %251 = insertelement <2 x i32> %250, i32 %249, i32 1
>  %252 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %251, <8 x i32> %29, <4 x i32> %32, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>  %253 = extractelement <4 x float> %252, i32 0
>  %254 = bitcast float %242 to i32
>  %255 = bitcast float %243 to i32
>  %256 = insertelement <2 x i32> undef, i32 %254, i32 0
>  %257 = insertelement <2 x i32> %256, i32 %255, i32 1
>  %258 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %257, <8 x i32> %29, <4 x i32> %32, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>  %259 = extractelement <4 x float> %258, i32 1
>  %260 = bitcast float %244 to i32
>  %261 = bitcast float %245 to i32
>  %262 = insertelement <2 x i32> undef, i32 %260, i32 0
>  %263 = insertelement <2 x i32> %262, i32 %261, i32 1
>  %264 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %263, <8 x i32> %29, <4 x i32> %32, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>  %265 = extractelement <4 x float> %264, i32 0
>  %266 = bitcast float %246 to i32
>  %267 = bitcast float %247 to i32
>  %268 = insertelement <2 x i32> undef, i32 %266, i32 0
>  %269 = insertelement <2 x i32> %268, i32 %267, i32 1
>  %270 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %269, <8 x i32> %29, <4 x i32> %32, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>  %271 = extractelement <4 x float> %270, i32 1
>  %272 = fsub float 1.000000e+00, %227
>  %273 = fmul float %253, %227
>  %274 = fmul float %259, %272
>  %275 = fadd float %273, %274
>  %276 = fsub float 1.000000e+00, %227
>  %277 = fmul float %265, %227
>  %278 = fmul float %271, %276
>  %279 = fadd float %277, %278
>  %280 = fsub float 1.000000e+00, %193
>  %281 = fmul float %275, %193
>  %282 = fmul float %279, %280
>  %283 = fadd float %281, %282
>  %284 = fmul float %42, 5.120000e+02
>  %285 = fadd float %284, 5.000000e-01
>  %286 = fmul float %43, 2.560000e+02
>  %287 = fadd float %286, 5.000000e-01
>  %288 = call float @llvm.floor.f32(float %285)
>  %289 = fsub float %285, %288
>  %290 = call float @llvm.floor.f32(float %287)
>  %291 = fsub float %287, %290
>  %292 = fmul float %289, -5.000000e-01
>  %293 = fadd float %292, 1.000000e+00
>  %294 = fmul float %289, 0x3FC5532620000000
>  %295 = fadd float %294, 0.000000e+00
>  %296 = fmul float %289, 0x3FD554C980000000
>  %297 = fadd float %296, -5.000000e-01
>  %298 = fmul float %289, 0xBFD554C980000000
>  %299 = fadd float %298, 5.000000e-01
>  %300 = fmul float %293, %289
>  %301 = fadd float %300, 0.000000e+00
>  %302 = fmul float %295, %289
>  %303 = fadd float %302, 0.000000e+00
>  %304 = fmul float %297, %289
>  %305 = fadd float %304, -5.000000e-01
>  %306 = fmul float %299, %289
>  %307 = fadd float %306, 5.000000e-01
>  %308 = fmul float %301, %289
>  %309 = fadd float %308, 0xBFE554C980000000
>  %310 = fmul float %303, %289
>  %311 = fadd float %310, 0.000000e+00
>  %312 = fmul float %305, %289
>  %313 = fadd float %312, 0x3FEAAA64C0000000
>  %314 = fmul float %307, %289
>  %315 = fadd float %314, 0x3FC5532620000000
>  %316 = fdiv float 1.000000e+00, %313
>  %317 = fdiv float 1.000000e+00, %315
>  %318 = fmul float %309, %316
>  %319 = fadd float %318, 1.000000e+00
>  %320 = fmul float %311, %317
>  %321 = fadd float %320, 1.000000e+00
>  %322 = fadd float %319, %289
>  %323 = fsub float %321, %289
>  %324 = fmul float %322, -1.953125e-03
>  %325 = fmul float %323, 1.953125e-03
>  %326 = fmul float %291, -5.000000e-01
>  %327 = fadd float %326, 1.000000e+00
>  %328 = fmul float %291, 0x3FC5532620000000
>  %329 = fadd float %328, 0.000000e+00
>  %330 = fmul float %291, 0x3FD554C980000000
>  %331 = fadd float %330, -5.000000e-01
>  %332 = fmul float %291, 0xBFD554C980000000
>  %333 = fadd float %332, 5.000000e-01
>  %334 = fmul float %327, %291
>  %335 = fadd float %334, 0.000000e+00
>  %336 = fmul float %329, %291
>  %337 = fadd float %336, 0.000000e+00
>  %338 = fmul float %331, %291
>  %339 = fadd float %338, -5.000000e-01
>  %340 = fmul float %333, %291
>  %341 = fadd float %340, 5.000000e-01
>  %342 = fmul float %335, %291
>  %343 = fadd float %342, 0xBFE554C980000000
>  %344 = fmul float %337, %291
>  %345 = fadd float %344, 0.000000e+00
>  %346 = fmul float %339, %291
>  %347 = fadd float %346, 0x3FEAAA64C0000000
>  %348 = fmul float %341, %291
>  %349 = fadd float %348, 0x3FC5532620000000
>  %350 = fdiv float 1.000000e+00, %347
>  %351 = fdiv float 1.000000e+00, %349
>  %352 = fmul float %343, %350
>  %353 = fadd float %352, 1.000000e+00
>  %354 = fmul float %345, %351
>  %355 = fadd float %354, 1.000000e+00
>  %356 = fadd float %353, %291
>  %357 = fsub float %355, %291
>  %358 = fmul float %356, -3.906250e-03
>  %359 = fmul float %357, 3.906250e-03
>  %360 = fadd float %42, %324
>  %361 = fadd float %43, %358
>  %362 = fadd float %42, %324
>  %363 = fadd float %43, %359
>  %364 = fadd float %42, %325
>  %365 = fadd float %43, %358
>  %366 = fadd float %42, %325
>  %367 = fadd float %43, %359
>  %368 = bitcast float %360 to i32
>  %369 = bitcast float %361 to i32
>  %370 = insertelement <2 x i32> undef, i32 %368, i32 0
>  %371 = insertelement <2 x i32> %370, i32 %369, i32 1
>  %372 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %371, <8 x i32> %34, <4 x i32> %37, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>  %373 = extractelement <4 x float> %372, i32 0
>  %374 = bitcast float %362 to i32
>  %375 = bitcast float %363 to i32
>  %376 = insertelement <2 x i32> undef, i32 %374, i32 0
>  %377 = insertelement <2 x i32> %376, i32 %375, i32 1
>  %378 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %377, <8 x i32> %34, <4 x i32> %37, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>  %379 = extractelement <4 x float> %378, i32 1
>  %380 = bitcast float %364 to i32
>  %381 = bitcast float %365 to i32
>  %382 = insertelement <2 x i32> undef, i32 %380, i32 0
>  %383 = insertelement <2 x i32> %382, i32 %381, i32 1
>  %384 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %383, <8 x i32> %34, <4 x i32> %37, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>  %385 = extractelement <4 x float> %384, i32 0
>  %386 = bitcast float %366 to i32
>  %387 = bitcast float %367 to i32
>  %388 = insertelement <2 x i32> undef, i32 %386, i32 0
>  %389 = insertelement <2 x i32> %388, i32 %387, i32 1
>  %390 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %389, <8 x i32> %34, <4 x i32> %37, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>  %391 = extractelement <4 x float> %390, i32 1
>  %392 = fsub float 1.000000e+00, %347
>  %393 = fmul float %373, %347
>  %394 = fmul float %379, %392
>  %395 = fadd float %393, %394
>  %396 = fsub float 1.000000e+00, %347
>  %397 = fmul float %385, %347
>  %398 = fmul float %391, %396
>  %399 = fadd float %397, %398
>  %400 = fsub float 1.000000e+00, %313
>  %401 = fmul float %395, %313
>  %402 = fmul float %399, %400
>  %403 = fadd float %401, %402
>  %404 = fmul float %163, 0x3FF29FBE80000000
>  %405 = fadd float %404, 0xBFEBF92880000000
>  %406 = fmul float %163, 0x3FF29FBE80000000
>  %407 = fadd float %406, 0x3FE1009E60000000
>  %408 = fmul float %163, 0x3FF29FBE80000000
>  %409 = fadd float %408, 0xBFF1603920000000
>  %410 = fmul float %283, 0.000000e+00
>  %411 = fadd float %410, %405
>  %412 = fmul float %283, 0xBFD90624E0000000
>  %413 = fadd float %412, %407
>  %414 = fmul float %283, 0x400024DD20000000
>  %415 = fadd float %414, %409
>  %416 = fmul float %403, 0x3FF9893740000000
>  %417 = fadd float %416, %411
>  %418 = fmul float %403, 0xBFEA0418A0000000
>  %419 = fadd float %418, %413
>  %420 = fmul float %403, 0.000000e+00
>  %421 = fadd float %420, %415
>  %422 = bitcast float %5 to i32
>  %423 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> undef, i32 %422, 10
>  %424 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %423, float %417, 11
>  %425 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %424, float %419, 12
>  %426 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %425, float %421, 13
>  %427 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %426, float undef, 14
>  %428 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %427, float %21, 24
>  ret <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %428
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.floor.f32(float) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1
>
>attributes #0 = { "InitialPSInputAddr"="36983" }
>attributes #1 = { nounwind readnone }
>
>!0 = !{}
>!1 = !{!"const", null, i32 1}
>
>SHADER KEY
>  prolog.color_two_side = 0
>  prolog.poly_stipple = 0
>  prolog.force_persample_interp = 0
>  epilog.spi_shader_col_format = 0x0
>  epilog.color_is_int8 = 0x0
>  epilog.last_cbuf = 0
>  epilog.alpha_func = 0
>  epilog.alpha_to_one = 0
>  epilog.poly_line_smoothing = 0
>  epilog.clamp_color = 0
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL IN[1], TEXCOORD[0], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SVIEW[0], 2D, FLOAT
>DCL TEMP[0], LOCAL
>  0: MOV TEMP[0].xy, IN[1].xyyy
>  1: MOV TEMP[0].w, IN[1].wwww
>  2: TXP TEMP[0].xyz, TEMP[0], SAMP[0], 2D
>  3: MOV TEMP[0].xyz, TEMP[0].xyzx
>  4: MOV TEMP[0].w, IN[0].wwww
>  5: MOV OUT[0], TEMP[0]
>  6: END
>radeonsi: Compiling shader 4
>TGSI shader LLVM IR:
>
>; ModuleID = 'tgsi'
>source_filename = "tgsi"
>target triple = "amdgcn--"
>
>define amdgpu_ps <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> @main([16 x <16 x i8>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [16 x <8 x i32>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, i32, i32, float, i32, float) #0 {
>main_body:
>  %24 = getelementptr [32 x <8 x i32>], [32 x <8 x i32>] addrspace(2)* %2, i64 0, i64 0, !amdgpu.uniform !0
>  %25 = load <8 x i32>, <8 x i32> addrspace(2)* %24, align 32, !tbaa !1
>  %26 = bitcast [32 x <8 x i32>] addrspace(2)* %2 to [0 x <4 x i32>] addrspace(2)*
>  %27 = getelementptr [0 x <4 x i32>], [0 x <4 x i32>] addrspace(2)* %26, i64 0, i64 3, !amdgpu.uniform !0
>  %28 = load <4 x i32>, <4 x i32> addrspace(2)* %27, align 16, !tbaa !1
>  %29 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %6, <2 x i32> %8)
>  %30 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %6, <2 x i32> %8)
>  %31 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %6, <2 x i32> %8)
>  %32 = fdiv float %29, %31
>  %33 = fdiv float %30, %31
>  %34 = bitcast float %32 to i32
>  %35 = bitcast float %33 to i32
>  %36 = insertelement <2 x i32> undef, i32 %34, i32 0
>  %37 = insertelement <2 x i32> %36, i32 %35, i32 1
>  %38 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %37, <8 x i32> %25, <4 x i32> %28, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>  %39 = extractelement <4 x float> %38, i32 0
>  %40 = extractelement <4 x float> %38, i32 1
>  %41 = extractelement <4 x float> %38, i32 2
>  %42 = bitcast float %5 to i32
>  %43 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> undef, i32 %42, 10
>  %44 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %43, float %39, 11
>  %45 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %44, float %40, 12
>  %46 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %45, float %41, 13
>  %47 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %46, float %23, 14
>  %48 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %47, float %21, 24
>  ret <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %48
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1
>
>attributes #0 = { "InitialPSInputAddr"="36983" }
>attributes #1 = { nounwind readnone }
>
>!0 = !{}
>!1 = !{!"const", null, i32 1}
>
>SHADER KEY
>  instance_divisors = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
>  as_es = 0
>  as_ls = 0
>  export_prim_id = 0
>VERT
>PROPERTY NEXT_SHADER 1
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL OUT[2], TEXCOORD[0]
>DCL CONST[0..3]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV OUT[1], IN[1]
>  5: MOV OUT[2], IN[2]
>  6: END
>radeonsi: Compiling shader 5
>TGSI shader LLVM IR:
>
>; ModuleID = 'tgsi'
>source_filename = "tgsi"
>target triple = "amdgcn--"
>
>define amdgpu_vs <{ float, float, float }> @main([16 x <16 x i8>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [16 x <8 x i32>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32, i32, i32, i32) {
>main_body:
>  %16 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0, !amdgpu.uniform !0
>  %17 = load <16 x i8>, <16 x i8> addrspace(2)* %16, align 16, !tbaa !1
>  %18 = call float @llvm.SI.load.const(<16 x i8> %17, i32 0)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %17, i32 4)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %17, i32 8)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %17, i32 12)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %17, i32 16)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %17, i32 20)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %17, i32 24)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %17, i32 28)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %17, i32 32)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %17, i32 36)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %17, i32 40)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %17, i32 44)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %17, i32 48)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %17, i32 52)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %17, i32 56)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %17, i32 60)
>  %34 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %5, i64 0, i64 0, !amdgpu.uniform !0
>  %35 = load <16 x i8>, <16 x i8> addrspace(2)* %34, align 16, !tbaa !1
>  %36 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %35, i32 0, i32 %13)
>  %37 = extractelement <4 x float> %36, i32 0
>  %38 = extractelement <4 x float> %36, i32 1
>  %39 = extractelement <4 x float> %36, i32 2
>  %40 = extractelement <4 x float> %36, i32 3
>  %41 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %5, i64 0, i64 1, !amdgpu.uniform !0
>  %42 = load <16 x i8>, <16 x i8> addrspace(2)* %41, align 16, !tbaa !1
>  %43 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %42, i32 0, i32 %14)
>  %44 = extractelement <4 x float> %43, i32 0
>  %45 = extractelement <4 x float> %43, i32 1
>  %46 = extractelement <4 x float> %43, i32 2
>  %47 = extractelement <4 x float> %43, i32 3
>  %48 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %5, i64 0, i64 2, !amdgpu.uniform !0
>  %49 = load <16 x i8>, <16 x i8> addrspace(2)* %48, align 16, !tbaa !1
>  %50 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %49, i32 0, i32 %15)
>  %51 = extractelement <4 x float> %50, i32 0
>  %52 = extractelement <4 x float> %50, i32 1
>  %53 = extractelement <4 x float> %50, i32 2
>  %54 = extractelement <4 x float> %50, i32 3
>  %55 = fmul float %37, %18
>  %56 = fmul float %37, %19
>  %57 = fmul float %37, %20
>  %58 = fmul float %37, %21
>  %59 = fmul float %38, %22
>  %60 = fadd float %59, %55
>  %61 = fmul float %38, %23
>  %62 = fadd float %61, %56
>  %63 = fmul float %38, %24
>  %64 = fadd float %63, %57
>  %65 = fmul float %38, %25
>  %66 = fadd float %65, %58
>  %67 = fmul float %39, %26
>  %68 = fadd float %67, %60
>  %69 = fmul float %39, %27
>  %70 = fadd float %69, %62
>  %71 = fmul float %39, %28
>  %72 = fadd float %71, %64
>  %73 = fmul float %39, %29
>  %74 = fadd float %73, %66
>  %75 = fmul float %40, %30
>  %76 = fadd float %75, %68
>  %77 = fmul float %40, %31
>  %78 = fadd float %77, %70
>  %79 = fmul float %40, %32
>  %80 = fadd float %79, %72
>  %81 = fmul float %40, %33
>  %82 = fadd float %81, %74
>  %83 = and i32 %8, 1
>  %84 = icmp eq i32 %83, 0
>  br i1 %84, label %endif-block, label %if-true-block
>
>if-true-block:                                    ; preds = %main_body
>  %85 = call float @llvm.AMDGPU.clamp.(float %44, float 0.000000e+00, float 1.000000e+00)
>  %86 = call float @llvm.AMDGPU.clamp.(float %45, float 0.000000e+00, float 1.000000e+00)
>  %87 = call float @llvm.AMDGPU.clamp.(float %46, float 0.000000e+00, float 1.000000e+00)
>  %88 = call float @llvm.AMDGPU.clamp.(float %47, float 0.000000e+00, float 1.000000e+00)
>  br label %endif-block
>
>endif-block:                                      ; preds = %main_body, %if-true-block
>  %.06 = phi float [ %85, %if-true-block ], [ %44, %main_body ]
>  %.05 = phi float [ %86, %if-true-block ], [ %45, %main_body ]
>  %.04 = phi float [ %87, %if-true-block ], [ %46, %main_body ]
>  %.0 = phi float [ %88, %if-true-block ], [ %47, %main_body ]
>  %89 = bitcast i32 %11 to float
>  %90 = insertvalue <{ float, float, float }> undef, float %89, 2
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %.06, float %.05, float %.04, float %.0)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %51, float %52, float %53, float %54)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %76, float %78, float %80, float %82)
>  ret <{ float, float, float }> %90
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #0
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #0
>
>; Function Attrs: readnone
>declare float @llvm.AMDGPU.clamp.(float, float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { nounwind readnone }
>attributes #1 = { readnone }
>
>!0 = !{}
>!1 = !{!"const", null, i32 1}
>
>VM start=0x10093B000  end=0x100A3B000 | Buffer 1048576 bytes
>VM start=0x1008EB000  end=0x1008EC000 | Buffer 4096 bytes
>apitrace: loaded into /bin/dash
>apitrace: loaded into /home/user/bin/dmesg
>apitrace: unloaded from /home/user/bin/dmesg
>VM start=0x10062D000  end=0x10062E000 | Buffer 4096 bytes
>SHADER KEY
>  instance_divisors = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
>  as_es = 0
>  as_ls = 0
>  export_prim_id = 0
>VERT
>PROPERTY NEXT_SHADER 1
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL OUT[0], POSITION
>DCL OUT[1], TEXCOORD[0]
>DCL OUT[2], TEXCOORD[1]
>DCL OUT[3], TEXCOORD[2]
>DCL CONST[0..3]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV OUT[1], IN[1]
>  5: MOV OUT[2], IN[2]
>  6: MOV OUT[3], IN[3]
>  7: END
>radeonsi: Compiling shader 6
>TGSI shader LLVM IR:
>
>; ModuleID = 'tgsi'
>source_filename = "tgsi"
>target triple = "amdgcn--"
>
>define amdgpu_vs <{ float, float, float }> @main([16 x <16 x i8>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [16 x <8 x i32>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32, i32, i32, i32, i32) {
>main_body:
>  %17 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0, !amdgpu.uniform !0
>  %18 = load <16 x i8>, <16 x i8> addrspace(2)* %17, align 16, !tbaa !1
>  %19 = call float @llvm.SI.load.const(<16 x i8> %18, i32 0)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %18, i32 4)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %18, i32 8)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %18, i32 12)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %18, i32 16)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %18, i32 20)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %18, i32 24)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %18, i32 28)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %18, i32 32)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %18, i32 36)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %18, i32 40)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %18, i32 44)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %18, i32 48)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %18, i32 52)
>  %33 = call float @llvm.SI.load.const(<16 x i8> %18, i32 56)
>  %34 = call float @llvm.SI.load.const(<16 x i8> %18, i32 60)
>  %35 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %5, i64 0, i64 0, !amdgpu.uniform !0
>  %36 = load <16 x i8>, <16 x i8> addrspace(2)* %35, align 16, !tbaa !1
>  %37 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %36, i32 0, i32 %13)
>  %38 = extractelement <4 x float> %37, i32 0
>  %39 = extractelement <4 x float> %37, i32 1
>  %40 = extractelement <4 x float> %37, i32 2
>  %41 = extractelement <4 x float> %37, i32 3
>  %42 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %5, i64 0, i64 1, !amdgpu.uniform !0
>  %43 = load <16 x i8>, <16 x i8> addrspace(2)* %42, align 16, !tbaa !1
>  %44 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %43, i32 0, i32 %14)
>  %45 = extractelement <4 x float> %44, i32 0
>  %46 = extractelement <4 x float> %44, i32 1
>  %47 = extractelement <4 x float> %44, i32 2
>  %48 = extractelement <4 x float> %44, i32 3
>  %49 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %5, i64 0, i64 2, !amdgpu.uniform !0
>  %50 = load <16 x i8>, <16 x i8> addrspace(2)* %49, align 16, !tbaa !1
>  %51 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %50, i32 0, i32 %15)
>  %52 = extractelement <4 x float> %51, i32 0
>  %53 = extractelement <4 x float> %51, i32 1
>  %54 = extractelement <4 x float> %51, i32 2
>  %55 = extractelement <4 x float> %51, i32 3
>  %56 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %5, i64 0, i64 3, !amdgpu.uniform !0
>  %57 = load <16 x i8>, <16 x i8> addrspace(2)* %56, align 16, !tbaa !1
>  %58 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %57, i32 0, i32 %16)
>  %59 = extractelement <4 x float> %58, i32 0
>  %60 = extractelement <4 x float> %58, i32 1
>  %61 = extractelement <4 x float> %58, i32 2
>  %62 = extractelement <4 x float> %58, i32 3
>  %63 = fmul float %38, %19
>  %64 = fmul float %38, %20
>  %65 = fmul float %38, %21
>  %66 = fmul float %38, %22
>  %67 = fmul float %39, %23
>  %68 = fadd float %67, %63
>  %69 = fmul float %39, %24
>  %70 = fadd float %69, %64
>  %71 = fmul float %39, %25
>  %72 = fadd float %71, %65
>  %73 = fmul float %39, %26
>  %74 = fadd float %73, %66
>  %75 = fmul float %40, %27
>  %76 = fadd float %75, %68
>  %77 = fmul float %40, %28
>  %78 = fadd float %77, %70
>  %79 = fmul float %40, %29
>  %80 = fadd float %79, %72
>  %81 = fmul float %40, %30
>  %82 = fadd float %81, %74
>  %83 = fmul float %41, %31
>  %84 = fadd float %83, %76
>  %85 = fmul float %41, %32
>  %86 = fadd float %85, %78
>  %87 = fmul float %41, %33
>  %88 = fadd float %87, %80
>  %89 = fmul float %41, %34
>  %90 = fadd float %89, %82
>  %91 = bitcast i32 %11 to float
>  %92 = insertvalue <{ float, float, float }> undef, float %91, 2
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %45, float %46, float %47, float %48)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 33, i32 0, float %52, float %53, float %54, float %55)
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 34, i32 0, float %59, float %60, float %61, float %62)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %84, float %86, float %88, float %90)
>  ret <{ float, float, float }> %92
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #0
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #0
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { nounwind readnone }
>
>!0 = !{}
>!1 = !{!"const", null, i32 1}
>
>radeonsi: Compiling shader 7
>Vertex Shader Prolog LLVM IR:
>
>; ModuleID = 'tgsi'
>source_filename = "tgsi"
>target triple = "amdgcn--"
>
>define amdgpu_vs <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float }> @main(i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) {
>main_body:
>  %19 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float }> undef, i32 %0, 0
>  %20 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float }> %19, i32 %1, 1
>  %21 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float }> %20, i32 %2, 2
>  %22 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float }> %21, i32 %3, 3
>  %23 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float }> %22, i32 %4, 4
>  %24 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float }> %23, i32 %5, 5
>  %25 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float }> %24, i32 %6, 6
>  %26 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float }> %25, i32 %7, 7
>  %27 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float }> %26, i32 %8, 8
>  %28 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float }> %27, i32 %9, 9
>  %29 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float }> %28, i32 %10, 10
>  %30 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float }> %29, i32 %11, 11
>  %31 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float }> %30, i32 %12, 12
>  %32 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float }> %31, i32 %13, 13
>  %33 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float }> %32, i32 %14, 14
>  %34 = bitcast i32 %15 to float
>  %35 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float }> %33, float %34, 15
>  %36 = bitcast i32 %16 to float
>  %37 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float }> %35, float %36, 16
>  %38 = bitcast i32 %17 to float
>  %39 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float }> %37, float %38, 17
>  %40 = bitcast i32 %18 to float
>  %41 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float }> %39, float %40, 18
>  %42 = add i32 %15, %12
>  %43 = bitcast i32 %42 to float
>  %44 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float }> %41, float %43, 19
>  %45 = add i32 %15, %12
>  %46 = bitcast i32 %45 to float
>  %47 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float }> %44, float %46, 20
>  %48 = add i32 %15, %12
>  %49 = bitcast i32 %48 to float
>  %50 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float }> %47, float %49, 21
>  %51 = add i32 %15, %12
>  %52 = bitcast i32 %51 to float
>  %53 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float }> %50, float %52, 22
>  ret <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float }> %53
>}
>
>radeonsi: Compiling shader 8
>Vertex Shader Epilog LLVM IR:
>
>; ModuleID = 'tgsi'
>source_filename = "tgsi"
>target triple = "amdgcn--"
>
>define amdgpu_vs void @main() {
>main_body:
>  ret void undef
>}
>
>
>Vertex Shader as VS:
>Shader prolog disassembly:
>	v_add_i32_e32 v4, vcc, s12, v0 ; 3208000C
>	v_mov_b32_e32 v5, v4           ; 7E0A0304
>	v_mov_b32_e32 v6, v4           ; 7E0C0304
>	v_mov_b32_e32 v7, v4           ; 7E0E0304
>Shader main disassembly:
>	s_load_dwordx4 s[4:7], s[10:11], 0x0                    ; C00A0105 00000000
>	s_load_dwordx4 s[12:15], s[10:11], 0x10                 ; C00A0305 00000010
>	s_load_dwordx4 s[0:3], s[2:3], 0x0                      ; C00A0001 00000000
>	s_waitcnt lgkmcnt(0)                                    ; BF8C007F
>	buffer_load_format_xyzw v[8:11], v4, s[4:7], 0 idxen    ; E00C2000 80010804
>	s_load_dwordx4 s[4:7], s[10:11], 0x20                   ; C00A0105 00000020
>	s_load_dwordx4 s[8:11], s[10:11], 0x30                  ; C00A0205 00000030
>	buffer_load_format_xyzw v[12:15], v5, s[12:15], 0 idxen ; E00C2000 80030C05
>	s_buffer_load_dword s12, s[0:3], 0x20                   ; C0220300 00000020
>	s_buffer_load_dword s13, s[0:3], 0x24                   ; C0220340 00000024
>	s_waitcnt lgkmcnt(0)                                    ; BF8C007F
>	buffer_load_format_xyzw v[3:6], v6, s[4:7], 0 idxen     ; E00C2000 80010306
>	s_nop 0                                                 ; BF800000
>	buffer_load_format_xyzw v[16:19], v7, s[8:11], 0 idxen  ; E00C2000 80021007
>	s_buffer_load_dword s4, s[0:3], 0x0                     ; C0220100 00000000
>	s_buffer_load_dword s5, s[0:3], 0x4                     ; C0220140 00000004
>	s_buffer_load_dword s6, s[0:3], 0x8                     ; C0220180 00000008
>	s_buffer_load_dword s7, s[0:3], 0xc                     ; C02201C0 0000000C
>	s_buffer_load_dword s8, s[0:3], 0x10                    ; C0220200 00000010
>	s_buffer_load_dword s9, s[0:3], 0x14                    ; C0220240 00000014
>	s_buffer_load_dword s10, s[0:3], 0x18                   ; C0220280 00000018
>	s_buffer_load_dword s11, s[0:3], 0x1c                   ; C02202C0 0000001C
>	s_buffer_load_dword s14, s[0:3], 0x28                   ; C0220380 00000028
>	s_buffer_load_dword s15, s[0:3], 0x2c                   ; C02203C0 0000002C
>	s_buffer_load_dword s16, s[0:3], 0x30                   ; C0220400 00000030
>	s_buffer_load_dword s17, s[0:3], 0x34                   ; C0220440 00000034
>	s_buffer_load_dword s18, s[0:3], 0x38                   ; C0220480 00000038
>	s_buffer_load_dword s0, s[0:3], 0x3c                    ; C0220000 0000003C
>	s_waitcnt vmcnt(3) lgkmcnt(0)                           ; BF8C0073
>	v_mul_f32_e32 v0, s4, v8                                ; 0A001004
>	v_mul_f32_e32 v1, s5, v8                                ; 0A021005
>	v_mul_f32_e32 v7, s6, v8                                ; 0A0E1006
>	v_mul_f32_e32 v8, s7, v8                                ; 0A101007
>	v_mac_f32_e32 v0, s8, v9                                ; 2C001208
>	v_mac_f32_e32 v1, s9, v9                                ; 2C021209
>	v_mac_f32_e32 v7, s10, v9                               ; 2C0E120A
>	v_mac_f32_e32 v8, s11, v9                               ; 2C10120B
>	s_waitcnt vmcnt(2)                                      ; BF8C0F72
>	exp 15, 32, 0, 0, 0, v12, v13, v14, v15                 ; C400020F 0F0E0D0C
>	v_mac_f32_e32 v0, s12, v10                              ; 2C00140C
>	v_mac_f32_e32 v1, s13, v10                              ; 2C02140D
>	v_mac_f32_e32 v7, s14, v10                              ; 2C0E140E
>	v_mac_f32_e32 v8, s15, v10                              ; 2C10140F
>	s_waitcnt vmcnt(1)                                      ; BF8C0F71
>	exp 15, 33, 0, 0, 0, v3, v4, v5, v6                     ; C400021F 06050403
>	v_mac_f32_e32 v0, s16, v11                              ; 2C001610
>	v_mac_f32_e32 v1, s17, v11                              ; 2C021611
>	v_mac_f32_e32 v7, s18, v11                              ; 2C0E1612
>	v_mac_f32_e32 v8, s0, v11                               ; 2C101600
>	s_waitcnt vmcnt(0)                                      ; BF8C0F70
>	exp 15, 34, 0, 0, 0, v16, v17, v18, v19                 ; C400022F 13121110
>	exp 15, 12, 0, 1, 0, v0, v1, v7, v8                     ; C40008CF 08070100
>	s_waitcnt expcnt(0)                                     ; BF8C0F0F
>Shader epilog disassembly:
>	s_endpgm ; BF810000
>
>*** SHADER STATS ***
>SGPRS: 80
>VGPRS: 20
>Code Size: 348 bytes
>LDS: 0 blocks
>Scratch: 0 bytes per wave
>Max Waves: 10
>********************
>VM start=0x1008EC000  end=0x1008ED000 | Buffer 4096 bytes
>radeonsi: Compiling shader 9
>Fragment Shader Epilog LLVM IR:
>
>; ModuleID = 'tgsi'
>source_filename = "tgsi"
>target triple = "amdgcn--"
>
>define amdgpu_ps void @main(i64 inreg, i64 inreg, i64 inreg, i64 inreg, i64 inreg, float inreg, float, float, float, float, float, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %20 = call i32 @llvm.SI.packf16(float %6, float %7)
>  %21 = bitcast i32 %20 to float
>  %22 = call i32 @llvm.SI.packf16(float %8, float %9)
>  %23 = bitcast i32 %22 to float
>  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %21, float %23, float undef, float undef)
>  ret void
>}
>
>; Function Attrs: nounwind readnone
>declare i32 @llvm.SI.packf16(float, float) #1
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { "InitialPSInputAddr"="16777215" }
>attributes #1 = { nounwind readnone }
>
>
>Pixel Shader:
>Shader main disassembly:
>	s_wqm_b64 exec, exec                                    ; BEFE077E
>	s_mov_b32 m0, s11                                       ; BEFC000B
>	v_interp_p1_f32 v8, v2, 0, 0, [m0]                      ; D4200002
>	v_interp_p2_f32 v8, [v8], v3, 0, 0, [m0]                ; D4210003
>	v_mov_b32_e32 v0, 0x44800000                            ; 7E0002FF 44800000
>	v_mad_f32 v0, v0, v8, 0.5                               ; D1C10000 03C21100
>	v_fract_f32_e32 v0, v0                                  ; 7E003700
>	v_mov_b32_e32 v5, 0x3eaaa64c                            ; 7E0A02FF 3EAAA64C
>	v_mov_b32_e32 v6, 0xbeaaa64c                            ; 7E0C02FF BEAAA64C
>	v_interp_p1_f32 v10, v2, 1, 0, [m0]                     ; D4280102
>	v_mad_f32 v16, v0, v5, -0.5                             ; D1C10010 03C60B00
>	v_mad_f32 v17, v0, v6, 0.5                              ; D1C10011 03C20D00
>	v_mov_b32_e32 v4, 0x3e2a9931                            ; 7E0802FF 3E2A9931
>	v_interp_p2_f32 v10, [v10], v3, 1, 0, [m0]              ; D4290103
>	v_interp_p1_f32 v11, v2, 0, 1, [m0]                     ; D42C0402
>	v_mad_f32 v16, v16, v0, -0.5                            ; D1C10010 03C60110
>	v_mov_b32_e32 v18, 0x3f555326                           ; 7E2402FF 3F555326
>	v_mad_f32 v17, v17, v0, 0.5                             ; D1C10011 03C20111
>	v_interp_p2_f32 v11, [v11], v3, 0, 1, [m0]              ; D42D0403
>	v_interp_p1_f32 v14, v2, 1, 1, [m0]                     ; D4380502
>	v_mad_f32 v19, v0, v16, v18                             ; D1C10013 044A2100
>	v_mad_f32 v16, v0, v17, v4                              ; D1C10010 04122300
>	v_interp_p2_f32 v14, [v14], v3, 1, 1, [m0]              ; D4390503
>	v_interp_p1_f32 v15, v2, 0, 2, [m0]                     ; D43C0802
>	v_rcp_f32_e32 v16, v16                                  ; 7E204510
>	v_mad_f32 v12, v0, v4, 0                                ; D1C1000C 02020900
>	v_interp_p2_f32 v15, [v15], v3, 0, 2, [m0]              ; D43D0803
>	v_interp_p1_f32 v2, v2, 1, 2, [m0]                      ; D4080902
>	v_bfrev_b32_e32 v1, 34                                  ; 7E0258A2
>	v_mad_f32 v12, v12, v0, 0                               ; D1C1000C 0202010C
>	v_interp_p2_f32 v2, [v2], v3, 1, 2, [m0]                ; D4090903
>	v_mad_f32 v3, v10, v1, 0.5                              ; D1C10003 03C2030A
>	v_mad_f32 v12, v12, v0, 0                               ; D1C1000C 0202010C
>	v_fract_f32_e32 v3, v3                                  ; 7E063703
>	v_rcp_f32_e32 v17, v19                                  ; 7E224513
>	v_mad_f32 v9, v0, -0.5, 1.0                             ; D1C10009 03C9E300
>	v_mad_f32 v12, v12, v16, 1.0                            ; D1C1000C 03CA210C
>	v_mad_f32 v16, v3, v5, -0.5                             ; D1C10010 03C60B03
>	v_mad_f32 v16, v16, v3, -0.5                            ; D1C10010 03C60710
>	v_mov_b32_e32 v7, 0xbf2aa64c                            ; 7E0E02FF BF2AA64C
>	v_mad_f32 v9, v9, v0, 0                                 ; D1C10009 02020109
>	v_mad_f32 v9, v0, v9, v7                                ; D1C10009 041E1300
>	v_mad_f32 v20, v3, v16, v18                             ; D1C10014 044A2103
>	v_mad_f32 v9, v9, v17, 1.0                              ; D1C10009 03CA2309
>	v_mad_f32 v17, v3, v6, 0.5                              ; D1C10011 03C20D03
>	v_rcp_f32_e32 v16, v20                                  ; 7E204514
>	v_mad_f32 v17, v17, v3, 0.5                             ; D1C10011 03C20711
>	v_add_f32_e32 v9, v0, v9                                ; 02121300
>	v_subrev_f32_e32 v0, v0, v12                            ; 06001900
>	v_mad_f32 v12, v3, -0.5, 1.0                            ; D1C1000C 03C9E303
>	v_mad_f32 v12, v12, v3, 0                               ; D1C1000C 0202070C
>	v_mad_f32 v17, v3, v17, v4                              ; D1C10011 04122303
>	v_mad_f32 v12, v3, v12, v7                              ; D1C1000C 041E1903
>	v_rcp_f32_e32 v17, v17                                  ; 7E224511
>	v_mad_f32 v12, v12, v16, 1.0                            ; D1C1000C 03CA210C
>	v_mad_f32 v16, v3, v4, 0                                ; D1C10010 02020903
>	v_mad_f32 v16, v16, v3, 0                               ; D1C10010 02020710
>	v_mad_f32 v16, v16, v3, 0                               ; D1C10010 02020710
>	v_mad_f32 v16, v16, v17, 1.0                            ; D1C10010 03CA2310
>	s_load_dwordx8 s[20:27], s[4:5], 0x0                    ; C00E0502 00000000
>	s_load_dwordx4 s[28:31], s[4:5], 0x30                   ; C00A0702 00000030
>	v_add_f32_e32 v12, v3, v12                              ; 02181903
>	v_subrev_f32_e32 v3, v3, v16                            ; 06062103
>	v_mov_b32_e32 v16, 0xbb000000                           ; 7E2002FF BB000000
>	v_mov_b32_e32 v17, 0x3b000000                           ; 7E2202FF 3B000000
>	v_mad_f32 v22, v16, v12, v10                            ; D1C10016 042A1910
>	v_mac_f32_e32 v10, v17, v3                              ; 2C140711
>	v_mov_b32_e32 v3, 0xba800000                            ; 7E0602FF BA800000
>	v_mad_f32 v21, v9, v3, v8                               ; D1C10015 04220709
>	v_mov_b32_e32 v24, v22                                  ; 7E300316
>	v_mac_f32_e32 v8, 0x3a800000, v0                        ; 2C1000FF 3A800000
>	v_mov_b32_e32 v23, v21                                  ; 7E2E0315
>	v_mov_b32_e32 v24, v10                                  ; 7E30030A
>	v_mov_b32_e32 v9, v22                                   ; 7E120316
>	s_waitcnt lgkmcnt(0)                                    ; BF8C007F
>	image_sample v0, v[21:22], s[20:27], s[28:31] dmask:0x1 ; F0800100 00E50015
>	s_nop 0                                                 ; BF800000
>	image_sample v3, v[23:24], s[20:27], s[28:31] dmask:0x2 ; F0800200 00E50317
>	s_nop 0                                                 ; BF800000
>	image_sample v21, v[8:9], s[20:27], s[28:31] dmask:0x1  ; F0800100 00E51508
>	v_mov_b32_e32 v9, v10                                   ; 7E12030A
>	image_sample v8, v[8:9], s[20:27], s[28:31] dmask:0x2   ; F0800200 00E50808
>	v_mov_b32_e32 v9, 0x43800000                            ; 7E1202FF 43800000
>	v_mad_f32 v10, v14, v9, 0.5                             ; D1C1000A 03C2130E
>	v_fract_f32_e32 v10, v10                                ; 7E14370A
>	v_mad_f32 v12, v10, v5, -0.5                            ; D1C1000C 03C60B0A
>	v_mad_f32 v12, v12, v10, -0.5                           ; D1C1000C 03C6150C
>	v_mad_f32 v22, v10, v12, v18                            ; D1C10016 044A190A
>	v_rcp_f32_e32 v12, v22                                  ; 7E184516
>	v_mad_f32 v23, v10, -0.5, 1.0                           ; D1C10017 03C9E30A
>	v_mad_f32 v23, v23, v10, 0                              ; D1C10017 02021517
>	v_mad_f32 v23, v10, v23, v7                             ; D1C10017 041E2F0A
>	v_mad_f32 v12, v23, v12, 1.0                            ; D1C1000C 03CA1917
>	v_mad_f32 v23, v10, v6, 0.5                             ; D1C10017 03C20D0A
>	v_mad_f32 v23, v23, v10, 0.5                            ; D1C10017 03C21517
>	v_mad_f32 v23, v10, v23, v4                             ; D1C10017 04122F0A
>	v_rcp_f32_e32 v23, v23                                  ; 7E2E4517
>	v_mad_f32 v24, v10, v4, 0                               ; D1C10018 0202090A
>	v_mad_f32 v24, v24, v10, 0                              ; D1C10018 02021518
>	v_mad_f32 v24, v24, v10, 0                              ; D1C10018 02021518
>	v_mad_f32 v23, v24, v23, 1.0                            ; D1C10017 03CA2F18
>	v_add_f32_e32 v12, v10, v12                             ; 0218190A
>	v_subrev_f32_e32 v10, v10, v23                          ; 06142F0A
>	v_mov_b32_e32 v23, 0xbb800000                           ; 7E2E02FF BB800000
>	v_mov_b32_e32 v24, 0x3b800000                           ; 7E3002FF 3B800000
>	v_mad_f32 v26, v23, v12, v14                            ; D1C1001A 043A1917
>	v_mac_f32_e32 v14, v24, v10                             ; 2C1C1518
>	v_mad_f32 v10, v11, v1, 0.5                             ; D1C1000A 03C2030B
>	v_mad_f32 v1, v15, v1, 0.5                              ; D1C10001 03C2030F
>	v_fract_f32_e32 v1, v1                                  ; 7E023701
>	v_mad_f32 v9, v2, v9, 0.5                               ; D1C10009 03C21302
>	v_mad_f32 v25, v1, -0.5, 1.0                            ; D1C10019 03C9E301
>	v_fract_f32_e32 v10, v10                                ; 7E14370A
>	v_fract_f32_e32 v9, v9                                  ; 7E123709
>	v_mad_f32 v25, v25, v1, 0                               ; D1C10019 02020319
>	v_mad_f32 v12, v10, -0.5, 1.0                           ; D1C1000C 03C9E30A
>	v_mad_f32 v27, v1, v25, v7                              ; D1C1001B 041E3301
>	v_mad_f32 v25, v9, -0.5, 1.0                            ; D1C10019 03C9E309
>	v_mad_f32 v12, v12, v10, 0                              ; D1C1000C 0202150C
>	v_mad_f32 v25, v25, v9, 0                               ; D1C10019 02021319
>	v_mad_f32 v12, v10, v12, v7                             ; D1C1000C 041E190A
>	v_mac_f32_e32 v7, v9, v25                               ; 2C0E3309
>	v_mad_f32 v25, v10, v5, -0.5                            ; D1C10019 03C60B0A
>	v_mad_f32 v25, v25, v10, -0.5                           ; D1C10019 03C61519
>	v_mad_f32 v28, v10, v25, v18                            ; D1C1001C 044A330A
>	v_mad_f32 v25, v1, v5, -0.5                             ; D1C10019 03C60B01
>	v_mad_f32 v5, v9, v5, -0.5                              ; D1C10005 03C60B09
>	v_mad_f32 v25, v25, v1, -0.5                            ; D1C10019 03C60319
>	v_mad_f32 v5, v5, v9, -0.5                              ; D1C10005 03C61305
>	v_mad_f32 v29, v1, v25, v18                             ; D1C1001D 044A3301
>	v_mac_f32_e32 v18, v9, v5                               ; 2C240B09
>	v_mad_f32 v5, v10, v6, 0.5                              ; D1C10005 03C20D0A
>	v_mad_f32 v25, v1, v6, 0.5                              ; D1C10019 03C20D01
>	v_mad_f32 v6, v9, v6, 0.5                               ; D1C10006 03C20D09
>	v_mad_f32 v5, v5, v10, 0.5                              ; D1C10005 03C21505
>	v_mad_f32 v25, v25, v1, 0.5                             ; D1C10019 03C20319
>	v_mad_f32 v6, v6, v9, 0.5                               ; D1C10006 03C21306
>	v_rcp_f32_e32 v32, v18                                  ; 7E404512
>	v_mad_f32 v30, v1, v25, v4                              ; D1C1001E 04123301
>	v_mad_f32 v5, v10, v5, v4                               ; D1C10005 04120B0A
>	v_mad_f32 v25, v10, v4, 0                               ; D1C10019 0202090A
>	v_mad_f32 v31, v1, v4, 0                                ; D1C1001F 02020901
>	v_mad_f32 v33, v9, v4, 0                                ; D1C10021 02020909
>	v_mac_f32_e32 v4, v9, v6                                ; 2C080D09
>	v_rcp_f32_e32 v4, v4                                    ; 7E084504
>	v_mad_f32 v6, v7, v32, 1.0                              ; D1C10006 03CA4107
>	v_mad_f32 v7, v33, v9, 0                                ; D1C10007 02021321
>	v_mad_f32 v7, v7, v9, 0                                 ; D1C10007 02021307
>	v_mad_f32 v4, v7, v4, 1.0                               ; D1C10004 03CA0907
>	v_add_f32_e32 v6, v9, v6                                ; 020C0D09
>	v_subrev_f32_e32 v4, v9, v4                             ; 06080909
>	v_rcp_f32_e32 v7, v28                                   ; 7E0E451C
>	v_mad_f32 v33, v23, v6, v2                              ; D1C10021 040A0D17
>	v_mac_f32_e32 v2, v24, v4                               ; 2C040918
>	v_rcp_f32_e32 v4, v5                                    ; 7E084505
>	v_mad_f32 v6, v25, v10, 0                               ; D1C10006 02021519
>	v_mad_f32 v5, v12, v7, 1.0                              ; D1C10005 03CA0F0C
>	v_mad_f32 v6, v6, v10, 0                                ; D1C10006 02021506
>	v_mad_f32 v4, v6, v4, 1.0                               ; D1C10004 03CA0906
>	v_add_f32_e32 v5, v10, v5                               ; 020A0B0A
>	s_load_dwordx4 s[0:3], s[4:5], 0x70                     ; C00A0002 00000070
>	s_load_dwordx8 s[12:19], s[4:5], 0x40                   ; C00E0302 00000040
>	v_subrev_f32_e32 v4, v10, v4                            ; 0608090A
>	v_mad_f32 v25, v16, v5, v11                             ; D1C10019 042E0B10
>	v_mac_f32_e32 v11, v17, v4                              ; 2C160911
>	v_mov_b32_e32 v4, v25                                   ; 7E080319
>	v_mov_b32_e32 v5, v26                                   ; 7E0A031A
>	v_mov_b32_e32 v5, v14                                   ; 7E0A030E
>	s_waitcnt lgkmcnt(0)                                    ; BF8C007F
>	image_sample v6, v[25:26], s[12:19], s[0:3] dmask:0x1   ; F0800100 00030619
>	s_nop 0                                                 ; BF800000
>	image_sample v4, v[4:5], s[12:19], s[0:3] dmask:0x2     ; F0800200 00030404
>	v_rcp_f32_e32 v5, v29                                   ; 7E0A451D
>	v_mov_b32_e32 v12, v26                                  ; 7E18031A
>	v_rcp_f32_e32 v10, v30                                  ; 7E14451E
>	image_sample v7, v[11:12], s[12:19], s[0:3] dmask:0x1   ; F0800100 0003070B
>	v_mov_b32_e32 v12, v14                                  ; 7E18030E
>	image_sample v9, v[11:12], s[12:19], s[0:3] dmask:0x2   ; F0800200 0003090B
>	v_mad_f32 v5, v27, v5, 1.0                              ; D1C10005 03CA0B1B
>	v_mad_f32 v11, v31, v1, 0                               ; D1C1000B 0202031F
>	s_waitcnt vmcnt(6)                                      ; BF8C0F76
>	v_mad_f32 v3, -v20, v3, v3                              ; D1C10003 240E0714
>	v_mad_f32 v11, v11, v1, 0                               ; D1C1000B 0202030B
>	v_add_f32_e32 v5, v1, v5                                ; 020A0B01
>	v_mac_f32_e32 v3, v20, v0                               ; 2C060114
>	s_waitcnt vmcnt(4)                                      ; BF8C0F74
>	v_mad_f32 v0, -v20, v8, v8                              ; D1C10000 24221114
>	s_load_dwordx8 s[20:27], s[4:5], 0x80                   ; C00E0502 00000080
>	s_load_dwordx4 s[0:3], s[4:5], 0xb0                     ; C00A0002 000000B0
>	v_mad_f32 v10, v11, v10, 1.0                            ; D1C1000A 03CA150B
>	v_mad_f32 v32, v16, v5, v15                             ; D1C10020 043E0B10
>	v_mac_f32_e32 v0, v20, v21                              ; 2C002B14
>	v_subrev_f32_e32 v1, v1, v10                            ; 06021501
>	v_mad_f32 v8, -v19, v0, v0                              ; D1C10008 24020113
>	v_mov_b32_e32 v10, v32                                  ; 7E140320
>	v_mov_b32_e32 v11, v33                                  ; 7E160321
>	v_mac_f32_e32 v8, v19, v3                               ; 2C100713
>	s_waitcnt vmcnt(0)                                      ; BF8C0F70
>	v_mad_f32 v3, -v22, v9, v9                              ; D1C10003 24261316
>	v_mad_f32 v0, -v22, v4, v4                              ; D1C10000 24120916
>	v_mac_f32_e32 v3, v22, v7                               ; 2C060F16
>	v_mac_f32_e32 v15, v17, v1                              ; 2C1E0311
>	v_mov_b32_e32 v11, v2                                   ; 7E160302
>	v_mov_b32_e32 v16, v33                                  ; 7E200321
>	s_waitcnt lgkmcnt(0)                                    ; BF8C007F
>	image_sample v1, v[32:33], s[20:27], s[0:3] dmask:0x1   ; F0800100 00050120
>	s_nop 0                                                 ; BF800000
>	image_sample v5, v[10:11], s[20:27], s[0:3] dmask:0x2   ; F0800200 0005050A
>	s_nop 0                                                 ; BF800000
>	image_sample v10, v[15:16], s[20:27], s[0:3] dmask:0x1  ; F0800100 00050A0F
>	v_mov_b32_e32 v16, v2                                   ; 7E200302
>	v_mac_f32_e32 v0, v22, v6                               ; 2C000D16
>	v_mad_f32 v3, -v28, v3, v3                              ; D1C10003 240E071C
>	v_mac_f32_e32 v3, v28, v0                               ; 2C06011C
>	s_waitcnt vmcnt(1)                                      ; BF8C0F71
>	v_mad_f32 v0, -v18, v5, v5                              ; D1C10000 24160B12
>	image_sample v2, v[15:16], s[20:27], s[0:3] dmask:0x2   ; F0800200 0005020F
>	v_mac_f32_e32 v0, v18, v1                               ; 2C000312
>	s_waitcnt vmcnt(0)                                      ; BF8C0F70
>	v_mad_f32 v1, -v18, v2, v2                              ; D1C10001 240A0512
>	v_mac_f32_e32 v1, v18, v10                              ; 2C021512
>	v_mad_f32 v4, -v29, v1, v1                              ; D1C10004 2406031D
>	v_mov_b32_e32 v2, 0x3f94fdf4                            ; 7E0402FF 3F94FDF4
>	v_mac_f32_e32 v4, v29, v0                               ; 2C08011D
>	v_madak_f32_e32 v0, v8, v2, 0xbf5fc944                  ; 30000508 BF5FC944
>	v_madak_f32_e32 v1, v8, v2, 0x3f0804f3                  ; 30020508 3F0804F3
>	v_madak_f32_e32 v2, v8, v2, 0xbf8b01c9                  ; 30040508 BF8B01C9
>	v_mov_b32_e32 v5, 0xbec83127                            ; 7E0A02FF BEC83127
>	v_mac_f32_e32 v0, 0, v3                                 ; 2C000680
>	v_mac_f32_e32 v2, 0x400126e9, v3                        ; 2C0406FF 400126E9
>	v_mac_f32_e32 v1, v3, v5                                ; 2C020B03
>	v_mov_b32_e32 v3, 0xbf5020c5                            ; 7E0602FF BF5020C5
>	v_mac_f32_e32 v0, 0x3fcc49ba, v4                        ; 2C0008FF 3FCC49BA
>	v_mac_f32_e32 v1, v4, v3                                ; 2C020704
>	v_mac_f32_e32 v2, 0, v4                                 ; 2C040880
>Shader epilog disassembly:
>	v_cvt_pkrtz_f16_f32_e64 v0, v0, v1 ; D2960000 00020300
>	v_cvt_pkrtz_f16_f32_e64 v1, v2, v3 ; D2960001 00020702
>	exp 15, 0, 1, 1, 1, v0, v1, v0, v0 ; C4001C0F 00000100
>	s_endpgm                           ; BF810000
>
>*** SHADER CONFIG ***
>SPI_PS_INPUT_ADDR = 0xd077
>SPI_PS_INPUT_ENA  = 0x0002
>*** SHADER STATS ***
>SGPRS: 80
>VGPRS: 36
>Code Size: 1532 bytes
>LDS: 0 blocks
>Scratch: 0 bytes per wave
>Max Waves: 7
>********************
>VM start=0x1008ED000  end=0x1008EE000 | Buffer 4096 bytes
>VM start=0x100A3B000  end=0x100B3B000 | Buffer 1048576 bytes
>apitrace: loaded into /bin/dash
>apitrace: loaded into /home/user/bin/dmesg
>apitrace: unloaded from /home/user/bin/dmesg
>VM start=0x10062E000  end=0x10062F000 | Buffer 4096 bytes
>SHADER KEY
>  prolog.color_two_side = 0
>  prolog.poly_stipple = 0
>  prolog.force_persample_interp = 0
>  epilog.spi_shader_col_format = 0x0
>  epilog.color_is_int8 = 0x0
>  epilog.last_cbuf = 0
>  epilog.alpha_func = 0
>  epilog.alpha_to_one = 0
>  epilog.poly_line_smoothing = 0
>  epilog.clamp_color = 0
>FRAG
>DCL IN[0], GENERIC[0], CONSTANT
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>radeonsi: Compiling shader 10
>TGSI shader LLVM IR:
>
>; ModuleID = 'tgsi'
>source_filename = "tgsi"
>target triple = "amdgcn--"
>
>define amdgpu_ps <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> @main([16 x <16 x i8>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [16 x <8 x i32>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, i32, i32, float, i32) #0 {
>main_body:
>  %23 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %6)
>  %24 = call float @llvm.SI.fs.constant(i32 1, i32 0, i32 %6)
>  %25 = call float @llvm.SI.fs.constant(i32 2, i32 0, i32 %6)
>  %26 = call float @llvm.SI.fs.constant(i32 3, i32 0, i32 %6)
>  %27 = bitcast float %5 to i32
>  %28 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> undef, i32 %27, 10
>  %29 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %28, float %23, 11
>  %30 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %29, float %24, 12
>  %31 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %30, float %25, 13
>  %32 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %31, float %26, 14
>  %33 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %32, float %21, 24
>  ret <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %33
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.constant(i32, i32, i32) #1
>
>attributes #0 = { "InitialPSInputAddr"="36983" }
>attributes #1 = { nounwind readnone }
>
>SHADER KEY
>  instance_divisors = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
>  as_es = 0
>  as_ls = 0
>  export_prim_id = 0
>VERT
>PROPERTY NEXT_SHADER 1
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[0]
>  0: MOV OUT[0], IN[0]
>  1: MOV OUT[1], IN[1]
>  2: END
>radeonsi: Compiling shader 11
>TGSI shader LLVM IR:
>
>; ModuleID = 'tgsi'
>source_filename = "tgsi"
>target triple = "amdgcn--"
>
>define amdgpu_vs <{ float, float, float }> @main([16 x <16 x i8>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [16 x <8 x i32>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32, i32, i32) {
>main_body:
>  %15 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %5, i64 0, i64 0, !amdgpu.uniform !0
>  %16 = load <16 x i8>, <16 x i8> addrspace(2)* %15, align 16, !tbaa !1
>  %17 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %16, i32 0, i32 %13)
>  %18 = extractelement <4 x float> %17, i32 0
>  %19 = extractelement <4 x float> %17, i32 1
>  %20 = extractelement <4 x float> %17, i32 2
>  %21 = extractelement <4 x float> %17, i32 3
>  %22 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %5, i64 0, i64 1, !amdgpu.uniform !0
>  %23 = load <16 x i8>, <16 x i8> addrspace(2)* %22, align 16, !tbaa !1
>  %24 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %23, i32 0, i32 %14)
>  %25 = extractelement <4 x float> %24, i32 0
>  %26 = extractelement <4 x float> %24, i32 1
>  %27 = extractelement <4 x float> %24, i32 2
>  %28 = extractelement <4 x float> %24, i32 3
>  %29 = bitcast i32 %11 to float
>  %30 = insertvalue <{ float, float, float }> undef, float %29, 2
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %25, float %26, float %27, float %28)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %18, float %19, float %20, float %21)
>  ret <{ float, float, float }> %30
>}
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #0
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { nounwind readnone }
>
>!0 = !{}
>!1 = !{!"const", null, i32 1}
>
>radeonsi: Compiling shader 12
>Vertex Shader Prolog LLVM IR:
>
>; ModuleID = 'tgsi'
>source_filename = "tgsi"
>target triple = "amdgcn--"
>
>define amdgpu_vs <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float }> @main(i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) {
>main_body:
>  %19 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float }> undef, i32 %0, 0
>  %20 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float }> %19, i32 %1, 1
>  %21 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float }> %20, i32 %2, 2
>  %22 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float }> %21, i32 %3, 3
>  %23 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float }> %22, i32 %4, 4
>  %24 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float }> %23, i32 %5, 5
>  %25 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float }> %24, i32 %6, 6
>  %26 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float }> %25, i32 %7, 7
>  %27 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float }> %26, i32 %8, 8
>  %28 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float }> %27, i32 %9, 9
>  %29 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float }> %28, i32 %10, 10
>  %30 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float }> %29, i32 %11, 11
>  %31 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float }> %30, i32 %12, 12
>  %32 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float }> %31, i32 %13, 13
>  %33 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float }> %32, i32 %14, 14
>  %34 = bitcast i32 %15 to float
>  %35 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float }> %33, float %34, 15
>  %36 = bitcast i32 %16 to float
>  %37 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float }> %35, float %36, 16
>  %38 = bitcast i32 %17 to float
>  %39 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float }> %37, float %38, 17
>  %40 = bitcast i32 %18 to float
>  %41 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float }> %39, float %40, 18
>  %42 = add i32 %15, %12
>  %43 = bitcast i32 %42 to float
>  %44 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float }> %41, float %43, 19
>  %45 = add i32 %15, %12
>  %46 = bitcast i32 %45 to float
>  %47 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float }> %44, float %46, 20
>  ret <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float }> %47
>}
>
>
>Vertex Shader as VS:
>Shader prolog disassembly:
>	v_add_i32_e32 v4, vcc, s12, v0 ; 3208000C
>	v_mov_b32_e32 v5, v4           ; 7E0A0304
>Shader main disassembly:
>	s_load_dwordx4 s[0:3], s[10:11], 0x0                  ; C00A0005 00000000
>	s_load_dwordx4 s[4:7], s[10:11], 0x10                 ; C00A0105 00000010
>	s_waitcnt lgkmcnt(0)                                  ; BF8C007F
>	buffer_load_format_xyzw v[6:9], v4, s[0:3], 0 idxen   ; E00C2000 80000604
>	s_nop 0                                               ; BF800000
>	buffer_load_format_xyzw v[10:13], v5, s[4:7], 0 idxen ; E00C2000 80010A05
>	s_waitcnt vmcnt(0)                                    ; BF8C0F70
>	exp 15, 32, 0, 0, 0, v10, v11, v12, v13               ; C400020F 0D0C0B0A
>	exp 15, 12, 0, 1, 0, v6, v7, v8, v9                   ; C40008CF 09080706
>	s_waitcnt expcnt(0)                                   ; BF8C0F0F
>Shader epilog disassembly:
>	s_endpgm ; BF810000
>
>*** SHADER STATS ***
>SGPRS: 80
>VGPRS: 16
>Code Size: 76 bytes
>LDS: 0 blocks
>Scratch: 0 bytes per wave
>Max Waves: 10
>********************
>VM start=0x1008EE000  end=0x1008EF000 | Buffer 4096 bytes
>
>Pixel Shader:
>Shader main disassembly:
>	s_mov_b32 m0, s11                   ; BEFC000B
>	v_interp_mov_f32 v0, P0, 0, 0, [m0] ; D4020002
>	v_interp_mov_f32 v1, P0, 1, 0, [m0] ; D4060102
>	v_interp_mov_f32 v2, P0, 2, 0, [m0] ; D40A0202
>	v_interp_mov_f32 v3, P0, 3, 0, [m0] ; D40E0302
>Shader epilog disassembly:
>	v_cvt_pkrtz_f16_f32_e64 v0, v0, v1 ; D2960000 00020300
>	v_cvt_pkrtz_f16_f32_e64 v1, v2, v3 ; D2960001 00020702
>	exp 15, 0, 1, 1, 1, v0, v1, v0, v0 ; C4001C0F 00000100
>	s_endpgm                           ; BF810000
>
>*** SHADER CONFIG ***
>SPI_PS_INPUT_ADDR = 0xd077
>SPI_PS_INPUT_ENA  = 0x0020
>*** SHADER STATS ***
>SGPRS: 80
>VGPRS: 15
>Code Size: 48 bytes
>LDS: 0 blocks
>Scratch: 0 bytes per wave
>Max Waves: 10
>********************
>VM start=0x1008EF000  end=0x1008F0000 | Buffer 4096 bytes
>apitrace: loaded into /bin/dash
>apitrace: loaded into /home/user/bin/dmesg
>apitrace: unloaded from /home/user/bin/dmesg
>VM start=0x10062F000  end=0x100630000 | Buffer 4096 bytes
>SHADER KEY
>  prolog.color_two_side = 0
>  prolog.poly_stipple = 0
>  prolog.force_persample_interp = 0
>  epilog.spi_shader_col_format = 0x0
>  epilog.color_is_int8 = 0x0
>  epilog.last_cbuf = 0
>  epilog.alpha_func = 0
>  epilog.alpha_to_one = 0
>  epilog.poly_line_smoothing = 0
>  epilog.clamp_color = 0
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], TEXCOORD[0], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SVIEW[0], 2D, FLOAT
>DCL CONST[1..4]
>DCL TEMP[0], LOCAL
>  0: MOV TEMP[0].xy, IN[0].xyyy
>  1: MOV TEMP[0].w, IN[0].wwww
>  2: TXP TEMP[0].xyz, TEMP[0], SAMP[0], 2D
>  3: MOV TEMP[0].xyz, TEMP[0].xyzx
>  4: MOV TEMP[0].w, CONST[4].wwww
>  5: MOV OUT[0], TEMP[0]
>  6: END
>radeonsi: Compiling shader 13
>TGSI shader LLVM IR:
>
>; ModuleID = 'tgsi'
>source_filename = "tgsi"
>target triple = "amdgcn--"
>
>define amdgpu_ps <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> @main([16 x <16 x i8>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [16 x <8 x i32>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, i32, i32, float, i32) #0 {
>main_body:
>  %23 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0, !amdgpu.uniform !0
>  %24 = load <16 x i8>, <16 x i8> addrspace(2)* %23, align 16, !tbaa !1
>  %25 = call float @llvm.SI.load.const(<16 x i8> %24, i32 76)
>  %26 = getelementptr [32 x <8 x i32>], [32 x <8 x i32>] addrspace(2)* %2, i64 0, i64 0, !amdgpu.uniform !0
>  %27 = load <8 x i32>, <8 x i32> addrspace(2)* %26, align 32, !tbaa !1
>  %28 = bitcast [32 x <8 x i32>] addrspace(2)* %2 to [0 x <4 x i32>] addrspace(2)*
>  %29 = getelementptr [0 x <4 x i32>], [0 x <4 x i32>] addrspace(2)* %28, i64 0, i64 3, !amdgpu.uniform !0
>  %30 = load <4 x i32>, <4 x i32> addrspace(2)* %29, align 16, !tbaa !1
>  %31 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %6, <2 x i32> %8)
>  %32 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %6, <2 x i32> %8)
>  %33 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %6, <2 x i32> %8)
>  %34 = fdiv float %31, %33
>  %35 = fdiv float %32, %33
>  %36 = bitcast float %34 to i32
>  %37 = bitcast float %35 to i32
>  %38 = insertelement <2 x i32> undef, i32 %36, i32 0
>  %39 = insertelement <2 x i32> %38, i32 %37, i32 1
>  %40 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %39, <8 x i32> %27, <4 x i32> %30, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
>  %41 = extractelement <4 x float> %40, i32 0
>  %42 = extractelement <4 x float> %40, i32 1
>  %43 = extractelement <4 x float> %40, i32 2
>  %44 = bitcast float %5 to i32
>  %45 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> undef, i32 %44, 10
>  %46 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %45, float %41, 11
>  %47 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %46, float %42, 12
>  %48 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %47, float %43, 13
>  %49 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %48, float %25, 14
>  %50 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %49, float %21, 24
>  ret <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %50
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1
>
>attributes #0 = { "InitialPSInputAddr"="36983" }
>attributes #1 = { nounwind readnone }
>
>!0 = !{}
>!1 = !{!"const", null, i32 1}
>
>SHADER KEY
>  instance_divisors = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
>  as_es = 0
>  as_ls = 0
>  export_prim_id = 0
>VERT
>PROPERTY NEXT_SHADER 1
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], TEXCOORD[0]
>DCL CONST[0..3]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV OUT[1], IN[1]
>  5: END
>radeonsi: Compiling shader 14
>TGSI shader LLVM IR:
>
>; ModuleID = 'tgsi'
>source_filename = "tgsi"
>target triple = "amdgcn--"
>
>define amdgpu_vs <{ float, float, float }> @main([16 x <16 x i8>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, [16 x <8 x i32>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32, i32, i32) {
>main_body:
>  %15 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0, !amdgpu.uniform !0
>  %16 = load <16 x i8>, <16 x i8> addrspace(2)* %15, align 16, !tbaa !1
>  %17 = call float @llvm.SI.load.const(<16 x i8> %16, i32 0)
>  %18 = call float @llvm.SI.load.const(<16 x i8> %16, i32 4)
>  %19 = call float @llvm.SI.load.const(<16 x i8> %16, i32 8)
>  %20 = call float @llvm.SI.load.const(<16 x i8> %16, i32 12)
>  %21 = call float @llvm.SI.load.const(<16 x i8> %16, i32 16)
>  %22 = call float @llvm.SI.load.const(<16 x i8> %16, i32 20)
>  %23 = call float @llvm.SI.load.const(<16 x i8> %16, i32 24)
>  %24 = call float @llvm.SI.load.const(<16 x i8> %16, i32 28)
>  %25 = call float @llvm.SI.load.const(<16 x i8> %16, i32 32)
>  %26 = call float @llvm.SI.load.const(<16 x i8> %16, i32 36)
>  %27 = call float @llvm.SI.load.const(<16 x i8> %16, i32 40)
>  %28 = call float @llvm.SI.load.const(<16 x i8> %16, i32 44)
>  %29 = call float @llvm.SI.load.const(<16 x i8> %16, i32 48)
>  %30 = call float @llvm.SI.load.const(<16 x i8> %16, i32 52)
>  %31 = call float @llvm.SI.load.const(<16 x i8> %16, i32 56)
>  %32 = call float @llvm.SI.load.const(<16 x i8> %16, i32 60)
>  %33 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %5, i64 0, i64 0, !amdgpu.uniform !0
>  %34 = load <16 x i8>, <16 x i8> addrspace(2)* %33, align 16, !tbaa !1
>  %35 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %34, i32 0, i32 %13)
>  %36 = extractelement <4 x float> %35, i32 0
>  %37 = extractelement <4 x float> %35, i32 1
>  %38 = extractelement <4 x float> %35, i32 2
>  %39 = extractelement <4 x float> %35, i32 3
>  %40 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %5, i64 0, i64 1, !amdgpu.uniform !0
>  %41 = load <16 x i8>, <16 x i8> addrspace(2)* %40, align 16, !tbaa !1
>  %42 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %41, i32 0, i32 %14)
>  %43 = extractelement <4 x float> %42, i32 0
>  %44 = extractelement <4 x float> %42, i32 1
>  %45 = extractelement <4 x float> %42, i32 2
>  %46 = extractelement <4 x float> %42, i32 3
>  %47 = fmul float %36, %17
>  %48 = fmul float %36, %18
>  %49 = fmul float %36, %19
>  %50 = fmul float %36, %20
>  %51 = fmul float %37, %21
>  %52 = fadd float %51, %47
>  %53 = fmul float %37, %22
>  %54 = fadd float %53, %48
>  %55 = fmul float %37, %23
>  %56 = fadd float %55, %49
>  %57 = fmul float %37, %24
>  %58 = fadd float %57, %50
>  %59 = fmul float %38, %25
>  %60 = fadd float %59, %52
>  %61 = fmul float %38, %26
>  %62 = fadd float %61, %54
>  %63 = fmul float %38, %27
>  %64 = fadd float %63, %56
>  %65 = fmul float %38, %28
>  %66 = fadd float %65, %58
>  %67 = fmul float %39, %29
>  %68 = fadd float %67, %60
>  %69 = fmul float %39, %30
>  %70 = fadd float %69, %62
>  %71 = fmul float %39, %31
>  %72 = fadd float %71, %64
>  %73 = fmul float %39, %32
>  %74 = fadd float %73, %66
>  %75 = bitcast i32 %11 to float
>  %76 = insertvalue <{ float, float, float }> undef, float %75, 2
>  call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %43, float %44, float %45, float %46)
>  call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %68, float %70, float %72, float %74)
>  ret <{ float, float, float }> %76
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const(<16 x i8>, i32) #0
>
>; Function Attrs: nounwind readnone
>declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #0
>
>declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
>
>attributes #0 = { nounwind readnone }
>
>!0 = !{}
>!1 = !{!"const", null, i32 1}
>
>apitrace: loaded into /bin/dash
>apitrace: loaded into /home/user/bin/dmesg
>apitrace: unloaded from /home/user/bin/dmesg
>VM start=0x10062D000  end=0x10062E000 | Buffer 4096 bytes
>apitrace: loaded into /bin/dash
>apitrace: loaded into /home/user/bin/dmesg
>apitrace: unloaded from /home/user/bin/dmesg
>VM start=0x10062E000  end=0x10062F000 | Buffer 4096 bytes
>[VD_FFMPEG] DRI failure.
>VM start=0x100820000  end=0x1008A0000 | Texture 1024x512x1, 1 levels, 1 samples, l8_unorm
>VM start=0x1008A0000  end=0x1008CB000 | Texture 512x256x1, 10 levels, 1 samples, l8_unorm
>VM start=0x1008CB000  end=0x1008EB000 | Texture 512x256x1, 1 levels, 1 samples, l8_unorm
>VM start=0x1008F0000  end=0x10091B000 | Texture 512x256x1, 10 levels, 1 samples, l8_unorm
>VM start=0x10091B000  end=0x10093B000 | Texture 512x256x1, 1 levels, 1 samples, l8_unorm
>apitrace: loaded into /bin/dash
>apitrace: loaded into /home/user/bin/dmesg
>apitrace: unloaded from /home/user/bin/dmesg
>VM start=0x10062F000  end=0x100630000 | Buffer 4096 bytes
>
>Pixel Shader:
>Shader main disassembly:
>	s_wqm_b64 exec, exec                                    ; BEFE077E
>	s_mov_b32 m0, s11                                       ; BEFC000B
>	v_interp_p1_f32 v8, v2, 0, 0, [m0]                      ; D4200002
>	v_interp_p2_f32 v8, [v8], v3, 0, 0, [m0]                ; D4210003
>	v_mov_b32_e32 v0, 0x44800000                            ; 7E0002FF 44800000
>	v_mad_f32 v0, v0, v8, 0.5                               ; D1C10000 03C21100
>	v_fract_f32_e32 v0, v0                                  ; 7E003700
>	v_mov_b32_e32 v5, 0x3eaaa64c                            ; 7E0A02FF 3EAAA64C
>	v_mov_b32_e32 v6, 0xbeaaa64c                            ; 7E0C02FF BEAAA64C
>	v_interp_p1_f32 v10, v2, 1, 0, [m0]                     ; D4280102
>	v_mad_f32 v16, v0, v5, -0.5                             ; D1C10010 03C60B00
>	v_mad_f32 v17, v0, v6, 0.5                              ; D1C10011 03C20D00
>	v_mov_b32_e32 v4, 0x3e2a9931                            ; 7E0802FF 3E2A9931
>	v_interp_p2_f32 v10, [v10], v3, 1, 0, [m0]              ; D4290103
>	v_interp_p1_f32 v11, v2, 0, 1, [m0]                     ; D42C0402
>	v_mad_f32 v16, v16, v0, -0.5                            ; D1C10010 03C60110
>	v_mov_b32_e32 v18, 0x3f555326                           ; 7E2402FF 3F555326
>	v_mad_f32 v17, v17, v0, 0.5                             ; D1C10011 03C20111
>	v_interp_p2_f32 v11, [v11], v3, 0, 1, [m0]              ; D42D0403
>	v_interp_p1_f32 v14, v2, 1, 1, [m0]                     ; D4380502
>	v_mad_f32 v19, v0, v16, v18                             ; D1C10013 044A2100
>	v_mad_f32 v16, v0, v17, v4                              ; D1C10010 04122300
>	v_interp_p2_f32 v14, [v14], v3, 1, 1, [m0]              ; D4390503
>	v_interp_p1_f32 v15, v2, 0, 2, [m0]                     ; D43C0802
>	v_rcp_f32_e32 v16, v16                                  ; 7E204510
>	v_mad_f32 v12, v0, v4, 0                                ; D1C1000C 02020900
>	v_interp_p2_f32 v15, [v15], v3, 0, 2, [m0]              ; D43D0803
>	v_interp_p1_f32 v2, v2, 1, 2, [m0]                      ; D4080902
>	v_bfrev_b32_e32 v1, 34                                  ; 7E0258A2
>	v_mad_f32 v12, v12, v0, 0                               ; D1C1000C 0202010C
>	v_interp_p2_f32 v2, [v2], v3, 1, 2, [m0]                ; D4090903
>	v_mad_f32 v3, v10, v1, 0.5                              ; D1C10003 03C2030A
>	v_mad_f32 v12, v12, v0, 0                               ; D1C1000C 0202010C
>	v_fract_f32_e32 v3, v3                                  ; 7E063703
>	v_rcp_f32_e32 v17, v19                                  ; 7E224513
>	v_mad_f32 v9, v0, -0.5, 1.0                             ; D1C10009 03C9E300
>	v_mad_f32 v12, v12, v16, 1.0                            ; D1C1000C 03CA210C
>	v_mad_f32 v16, v3, v5, -0.5                             ; D1C10010 03C60B03
>	v_mad_f32 v16, v16, v3, -0.5                            ; D1C10010 03C60710
>	v_mov_b32_e32 v7, 0xbf2aa64c                            ; 7E0E02FF BF2AA64C
>	v_mad_f32 v9, v9, v0, 0                                 ; D1C10009 02020109
>	v_mad_f32 v9, v0, v9, v7                                ; D1C10009 041E1300
>	v_mad_f32 v20, v3, v16, v18                             ; D1C10014 044A2103
>	v_mad_f32 v9, v9, v17, 1.0                              ; D1C10009 03CA2309
>	v_mad_f32 v17, v3, v6, 0.5                              ; D1C10011 03C20D03
>	v_rcp_f32_e32 v16, v20                                  ; 7E204514
>	v_mad_f32 v17, v17, v3, 0.5                             ; D1C10011 03C20711
>	v_add_f32_e32 v9, v0, v9                                ; 02121300
>	v_subrev_f32_e32 v0, v0, v12                            ; 06001900
>	v_mad_f32 v12, v3, -0.5, 1.0                            ; D1C1000C 03C9E303
>	v_mad_f32 v12, v12, v3, 0                               ; D1C1000C 0202070C
>	v_mad_f32 v17, v3, v17, v4                              ; D1C10011 04122303
>	v_mad_f32 v12, v3, v12, v7                              ; D1C1000C 041E1903
>	v_rcp_f32_e32 v17, v17                                  ; 7E224511
>	v_mad_f32 v12, v12, v16, 1.0                            ; D1C1000C 03CA210C
>	v_mad_f32 v16, v3, v4, 0                                ; D1C10010 02020903
>	v_mad_f32 v16, v16, v3, 0                               ; D1C10010 02020710
>	v_mad_f32 v16, v16, v3, 0                               ; D1C10010 02020710
>	v_mad_f32 v16, v16, v17, 1.0                            ; D1C10010 03CA2310
>	s_load_dwordx8 s[20:27], s[4:5], 0x0                    ; C00E0502 00000000
>	s_load_dwordx4 s[28:31], s[4:5], 0x30                   ; C00A0702 00000030
>	v_add_f32_e32 v12, v3, v12                              ; 02181903
>	v_subrev_f32_e32 v3, v3, v16                            ; 06062103
>	v_mov_b32_e32 v16, 0xbb000000                           ; 7E2002FF BB000000
>	v_mov_b32_e32 v17, 0x3b000000                           ; 7E2202FF 3B000000
>	v_mad_f32 v22, v16, v12, v10                            ; D1C10016 042A1910
>	v_mac_f32_e32 v10, v17, v3                              ; 2C140711
>	v_mov_b32_e32 v3, 0xba800000                            ; 7E0602FF BA800000
>	v_mad_f32 v21, v9, v3, v8                               ; D1C10015 04220709
>	v_mov_b32_e32 v24, v22                                  ; 7E300316
>	v_mac_f32_e32 v8, 0x3a800000, v0                        ; 2C1000FF 3A800000
>	v_mov_b32_e32 v23, v21                                  ; 7E2E0315
>	v_mov_b32_e32 v24, v10                                  ; 7E30030A
>	v_mov_b32_e32 v9, v22                                   ; 7E120316
>	s_waitcnt lgkmcnt(0)                                    ; BF8C007F
>	image_sample v0, v[21:22], s[20:27], s[28:31] dmask:0x1 ; F0800100 00E50015
>	s_nop 0                                                 ; BF800000
>	image_sample v3, v[23:24], s[20:27], s[28:31] dmask:0x2 ; F0800200 00E50317
>	s_nop 0                                                 ; BF800000
>	image_sample v21, v[8:9], s[20:27], s[28:31] dmask:0x1  ; F0800100 00E51508
>	v_mov_b32_e32 v9, v10                                   ; 7E12030A
>	image_sample v8, v[8:9], s[20:27], s[28:31] dmask:0x2   ; F0800200 00E50808
>	v_mov_b32_e32 v9, 0x43800000                            ; 7E1202FF 43800000
>	v_mad_f32 v10, v14, v9, 0.5                             ; D1C1000A 03C2130E
>	v_fract_f32_e32 v10, v10                                ; 7E14370A
>	v_mad_f32 v12, v10, v5, -0.5                            ; D1C1000C 03C60B0A
>	v_mad_f32 v12, v12, v10, -0.5                           ; D1C1000C 03C6150C
>	v_mad_f32 v22, v10, v12, v18                            ; D1C10016 044A190A
>	v_rcp_f32_e32 v12, v22                                  ; 7E184516
>	v_mad_f32 v23, v10, -0.5, 1.0                           ; D1C10017 03C9E30A
>	v_mad_f32 v23, v23, v10, 0                              ; D1C10017 02021517
>	v_mad_f32 v23, v10, v23, v7                             ; D1C10017 041E2F0A
>	v_mad_f32 v12, v23, v12, 1.0                            ; D1C1000C 03CA1917
>	v_mad_f32 v23, v10, v6, 0.5                             ; D1C10017 03C20D0A
>	v_mad_f32 v23, v23, v10, 0.5                            ; D1C10017 03C21517
>	v_mad_f32 v23, v10, v23, v4                             ; D1C10017 04122F0A
>	v_rcp_f32_e32 v23, v23                                  ; 7E2E4517
>	v_mad_f32 v24, v10, v4, 0                               ; D1C10018 0202090A
>	v_mad_f32 v24, v24, v10, 0                              ; D1C10018 02021518
>	v_mad_f32 v24, v24, v10, 0                              ; D1C10018 02021518
>	v_mad_f32 v23, v24, v23, 1.0                            ; D1C10017 03CA2F18
>	v_add_f32_e32 v12, v10, v12                             ; 0218190A
>	v_subrev_f32_e32 v10, v10, v23                          ; 06142F0A
>	v_mov_b32_e32 v23, 0xbb800000                           ; 7E2E02FF BB800000
>	v_mov_b32_e32 v24, 0x3b800000                           ; 7E3002FF 3B800000
>	v_mad_f32 v26, v23, v12, v14                            ; D1C1001A 043A1917
>	v_mac_f32_e32 v14, v24, v10                             ; 2C1C1518
>	v_mad_f32 v10, v11, v1, 0.5                             ; D1C1000A 03C2030B
>	v_mad_f32 v1, v15, v1, 0.5                              ; D1C10001 03C2030F
>	v_fract_f32_e32 v1, v1                                  ; 7E023701
>	v_mad_f32 v9, v2, v9, 0.5                               ; D1C10009 03C21302
>	v_mad_f32 v25, v1, -0.5, 1.0                            ; D1C10019 03C9E301
>	v_fract_f32_e32 v10, v10                                ; 7E14370A
>	v_fract_f32_e32 v9, v9                                  ; 7E123709
>	v_mad_f32 v25, v25, v1, 0                               ; D1C10019 02020319
>	v_mad_f32 v12, v10, -0.5, 1.0                           ; D1C1000C 03C9E30A
>	v_mad_f32 v27, v1, v25, v7                              ; D1C1001B 041E3301
>	v_mad_f32 v25, v9, -0.5, 1.0                            ; D1C10019 03C9E309
>	v_mad_f32 v12, v12, v10, 0                              ; D1C1000C 0202150C
>	v_mad_f32 v25, v25, v9, 0                               ; D1C10019 02021319
>	v_mad_f32 v12, v10, v12, v7                             ; D1C1000C 041E190A
>	v_mac_f32_e32 v7, v9, v25                               ; 2C0E3309
>	v_mad_f32 v25, v10, v5, -0.5                            ; D1C10019 03C60B0A
>	v_mad_f32 v25, v25, v10, -0.5                           ; D1C10019 03C61519
>	v_mad_f32 v28, v10, v25, v18                            ; D1C1001C 044A330A
>	v_mad_f32 v25, v1, v5, -0.5                             ; D1C10019 03C60B01
>	v_mad_f32 v5, v9, v5, -0.5                              ; D1C10005 03C60B09
>	v_mad_f32 v25, v25, v1, -0.5                            ; D1C10019 03C60319
>	v_mad_f32 v5, v5, v9, -0.5                              ; D1C10005 03C61305
>	v_mad_f32 v29, v1, v25, v18                             ; D1C1001D 044A3301
>	v_mac_f32_e32 v18, v9, v5                               ; 2C240B09
>	v_mad_f32 v5, v10, v6, 0.5                              ; D1C10005 03C20D0A
>	v_mad_f32 v25, v1, v6, 0.5                              ; D1C10019 03C20D01
>	v_mad_f32 v6, v9, v6, 0.5                               ; D1C10006 03C20D09
>	v_mad_f32 v5, v5, v10, 0.5                              ; D1C10005 03C21505
>	v_mad_f32 v25, v25, v1, 0.5                             ; D1C10019 03C20319
>	v_mad_f32 v6, v6, v9, 0.5                               ; D1C10006 03C21306
>	v_rcp_f32_e32 v32, v18                                  ; 7E404512
>	v_mad_f32 v30, v1, v25, v4                              ; D1C1001E 04123301
>	v_mad_f32 v5, v10, v5, v4                               ; D1C10005 04120B0A
>	v_mad_f32 v25, v10, v4, 0                               ; D1C10019 0202090A
>	v_mad_f32 v31, v1, v4, 0                                ; D1C1001F 02020901
>	v_mad_f32 v33, v9, v4, 0                                ; D1C10021 02020909
>	v_mac_f32_e32 v4, v9, v6                                ; 2C080D09
>	v_rcp_f32_e32 v4, v4                                    ; 7E084504
>	v_mad_f32 v6, v7, v32, 1.0                              ; D1C10006 03CA4107
>	v_mad_f32 v7, v33, v9, 0                                ; D1C10007 02021321
>	v_mad_f32 v7, v7, v9, 0                                 ; D1C10007 02021307
>	v_mad_f32 v4, v7, v4, 1.0                               ; D1C10004 03CA0907
>	v_add_f32_e32 v6, v9, v6                                ; 020C0D09
>	v_subrev_f32_e32 v4, v9, v4                             ; 06080909
>	v_rcp_f32_e32 v7, v28                                   ; 7E0E451C
>	v_mad_f32 v33, v23, v6, v2                              ; D1C10021 040A0D17
>	v_mac_f32_e32 v2, v24, v4                               ; 2C040918
>	v_rcp_f32_e32 v4, v5                                    ; 7E084505
>	v_mad_f32 v6, v25, v10, 0                               ; D1C10006 02021519
>	v_mad_f32 v5, v12, v7, 1.0                              ; D1C10005 03CA0F0C
>	v_mad_f32 v6, v6, v10, 0                                ; D1C10006 02021506
>	v_mad_f32 v4, v6, v4, 1.0                               ; D1C10004 03CA0906
>	v_add_f32_e32 v5, v10, v5                               ; 020A0B0A
>	s_load_dwordx4 s[0:3], s[4:5], 0x70                     ; C00A0002 00000070
>	s_load_dwordx8 s[12:19], s[4:5], 0x40                   ; C00E0302 00000040
>	v_subrev_f32_e32 v4, v10, v4                            ; 0608090A
>	v_mad_f32 v25, v16, v5, v11                             ; D1C10019 042E0B10
>	v_mac_f32_e32 v11, v17, v4                              ; 2C160911
>	v_mov_b32_e32 v4, v25                                   ; 7E080319
>	v_mov_b32_e32 v5, v26                                   ; 7E0A031A
>	v_mov_b32_e32 v5, v14                                   ; 7E0A030E
>	s_waitcnt lgkmcnt(0)                                    ; BF8C007F
>	image_sample v6, v[25:26], s[12:19], s[0:3] dmask:0x1   ; F0800100 00030619
>	s_nop 0                                                 ; BF800000
>	image_sample v4, v[4:5], s[12:19], s[0:3] dmask:0x2     ; F0800200 00030404
>	v_rcp_f32_e32 v5, v29                                   ; 7E0A451D
>	v_mov_b32_e32 v12, v26                                  ; 7E18031A
>	v_rcp_f32_e32 v10, v30                                  ; 7E14451E
>	image_sample v7, v[11:12], s[12:19], s[0:3] dmask:0x1   ; F0800100 0003070B
>	v_mov_b32_e32 v12, v14                                  ; 7E18030E
>	image_sample v9, v[11:12], s[12:19], s[0:3] dmask:0x2   ; F0800200 0003090B
>	v_mad_f32 v5, v27, v5, 1.0                              ; D1C10005 03CA0B1B
>	v_mad_f32 v11, v31, v1, 0                               ; D1C1000B 0202031F
>	s_waitcnt vmcnt(6)                                      ; BF8C0F76
>	v_mad_f32 v3, -v20, v3, v3                              ; D1C10003 240E0714
>	v_mad_f32 v11, v11, v1, 0                               ; D1C1000B 0202030B
>	v_add_f32_e32 v5, v1, v5                                ; 020A0B01
>	v_mac_f32_e32 v3, v20, v0                               ; 2C060114
>	s_waitcnt vmcnt(4)                                      ; BF8C0F74
>	v_mad_f32 v0, -v20, v8, v8                              ; D1C10000 24221114
>	s_load_dwordx8 s[20:27], s[4:5], 0x80                   ; C00E0502 00000080
>	s_load_dwordx4 s[0:3], s[4:5], 0xb0                     ; C00A0002 000000B0
>	v_mad_f32 v10, v11, v10, 1.0                            ; D1C1000A 03CA150B
>	v_mad_f32 v32, v16, v5, v15                             ; D1C10020 043E0B10
>	v_mac_f32_e32 v0, v20, v21                              ; 2C002B14
>	v_subrev_f32_e32 v1, v1, v10                            ; 06021501
>	v_mad_f32 v8, -v19, v0, v0                              ; D1C10008 24020113
>	v_mov_b32_e32 v10, v32                                  ; 7E140320
>	v_mov_b32_e32 v11, v33                                  ; 7E160321
>	v_mac_f32_e32 v8, v19, v3                               ; 2C100713
>	s_waitcnt vmcnt(0)                                      ; BF8C0F70
>	v_mad_f32 v3, -v22, v9, v9                              ; D1C10003 24261316
>	v_mad_f32 v0, -v22, v4, v4                              ; D1C10000 24120916
>	v_mac_f32_e32 v3, v22, v7                               ; 2C060F16
>	v_mac_f32_e32 v15, v17, v1                              ; 2C1E0311
>	v_mov_b32_e32 v11, v2                                   ; 7E160302
>	v_mov_b32_e32 v16, v33                                  ; 7E200321
>	s_waitcnt lgkmcnt(0)                                    ; BF8C007F
>	image_sample v1, v[32:33], s[20:27], s[0:3] dmask:0x1   ; F0800100 00050120
>	s_nop 0                                                 ; BF800000
>	image_sample v5, v[10:11], s[20:27], s[0:3] dmask:0x2   ; F0800200 0005050A
>	s_nop 0                                                 ; BF800000
>	image_sample v10, v[15:16], s[20:27], s[0:3] dmask:0x1  ; F0800100 00050A0F
>	v_mov_b32_e32 v16, v2                                   ; 7E200302
>	v_mac_f32_e32 v0, v22, v6                               ; 2C000D16
>	v_mad_f32 v3, -v28, v3, v3                              ; D1C10003 240E071C
>	v_mac_f32_e32 v3, v28, v0                               ; 2C06011C
>	s_waitcnt vmcnt(1)                                      ; BF8C0F71
>	v_mad_f32 v0, -v18, v5, v5                              ; D1C10000 24160B12
>	image_sample v2, v[15:16], s[20:27], s[0:3] dmask:0x2   ; F0800200 0005020F
>	v_mac_f32_e32 v0, v18, v1                               ; 2C000312
>	s_waitcnt vmcnt(0)                                      ; BF8C0F70
>	v_mad_f32 v1, -v18, v2, v2                              ; D1C10001 240A0512
>	v_mac_f32_e32 v1, v18, v10                              ; 2C021512
>	v_mad_f32 v4, -v29, v1, v1                              ; D1C10004 2406031D
>	v_mov_b32_e32 v2, 0x3f94fdf4                            ; 7E0402FF 3F94FDF4
>	v_mac_f32_e32 v4, v29, v0                               ; 2C08011D
>	v_madak_f32_e32 v0, v8, v2, 0xbf5fc944                  ; 30000508 BF5FC944
>	v_madak_f32_e32 v1, v8, v2, 0x3f0804f3                  ; 30020508 3F0804F3
>	v_madak_f32_e32 v2, v8, v2, 0xbf8b01c9                  ; 30040508 BF8B01C9
>	v_mov_b32_e32 v5, 0xbec83127                            ; 7E0A02FF BEC83127
>	v_mac_f32_e32 v0, 0, v3                                 ; 2C000680
>	v_mac_f32_e32 v2, 0x400126e9, v3                        ; 2C0406FF 400126E9
>	v_mac_f32_e32 v1, v3, v5                                ; 2C020B03
>	v_mov_b32_e32 v3, 0xbf5020c5                            ; 7E0602FF BF5020C5
>	v_mac_f32_e32 v0, 0x3fcc49ba, v4                        ; 2C0008FF 3FCC49BA
>	v_mac_f32_e32 v1, v4, v3                                ; 2C020704
>	v_mac_f32_e32 v2, 0, v4                                 ; 2C040880
>Shader epilog disassembly:
>	v_cvt_pkrtz_f16_f32_e64 v0, v0, v1 ; D2960000 00020300
>	v_cvt_pkrtz_f16_f32_e64 v1, v2, v3 ; D2960001 00020702
>	exp 15, 0, 1, 1, 1, v0, v1, v0, v0 ; C4001C0F 00000100
>	s_endpgm                           ; BF810000
>
>*** SHADER CONFIG ***
>SPI_PS_INPUT_ADDR = 0xd077
>SPI_PS_INPUT_ENA  = 0x0002
>*** SHADER STATS ***
>SGPRS: 80
>VGPRS: 36
>Code Size: 1532 bytes
>LDS: 0 blocks
>Scratch: 0 bytes per wave
>Max Waves: 7
>********************
>VM start=0x1008ED000  end=0x1008EE000 | Buffer 4096 bytes
>apitrace: loaded into /bin/dash
>apitrace: loaded into /home/user/bin/dmesg
>apitrace: unloaded from /home/user/bin/dmesg
>VM start=0x10062D000  end=0x10062E000 | Buffer 4096 bytes
>apitrace: loaded into /bin/dash
>apitrace: loaded into /home/user/bin/dmesg
>apitrace: unloaded from /home/user/bin/dmesg
>VM start=0x10062E000  end=0x10062F000 | Buffer 4096 bytes
>apitrace: loaded into /bin/dash
>apitrace: loaded into /home/user/bin/dmesg
>apitrace: unloaded from /home/user/bin/dmesg
>VM start=0x10062F000  end=0x100630000 | Buffer 4096 bytes
>apitrace: loaded into /bin/dash
>apitrace: loaded into /home/user/bin/dmesg
>apitrace: unloaded from /home/user/bin/dmesg
>VM start=0x10062D000  end=0x10062E000 | Buffer 4096 bytes
>VM start=0x100B3B000  end=0x100B74000 | Texture 640x360x1, 1 levels, 1 samples, l8_unorm
>VM start=0x1006EB000  end=0x1006FA000 | Texture 320x180x1, 1 levels, 1 samples, l8_unorm
>VM start=0x100B74000  end=0x100B83000 | Texture 320x180x1, 1 levels, 1 samples, l8_unorm
>apitrace: loaded into /bin/dash
>apitrace: loaded into /home/user/bin/dmesg
>apitrace: unloaded from /home/user/bin/dmesg
>Detected a VM fault, exiting...
>apitrace: unloaded from /usr/local/bin/mplayer

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Attachments on bug 95545: 123994 | 123995 | 123996 | 123997

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